2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
45 #include <asm/virtext.h>
47 #include <asm/fpu/internal.h>
48 #include <asm/perf_event.h>
49 #include <asm/debugreg.h>
50 #include <asm/kexec.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/mmu_context.h>
54 #include <asm/microcode.h>
55 #include <asm/spec-ctrl.h>
60 #define __ex(x) __kvm_handle_fault_on_reboot(x)
61 #define __ex_clear(x, reg) \
62 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id
[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
71 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
73 static bool __read_mostly enable_vpid
= 1;
74 module_param_named(vpid
, enable_vpid
, bool, 0444);
76 static bool __read_mostly enable_vnmi
= 1;
77 module_param_named(vnmi
, enable_vnmi
, bool, S_IRUGO
);
79 static bool __read_mostly flexpriority_enabled
= 1;
80 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
82 static bool __read_mostly enable_ept
= 1;
83 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
85 static bool __read_mostly enable_unrestricted_guest
= 1;
86 module_param_named(unrestricted_guest
,
87 enable_unrestricted_guest
, bool, S_IRUGO
);
89 static bool __read_mostly enable_ept_ad_bits
= 1;
90 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
92 static bool __read_mostly emulate_invalid_guest_state
= true;
93 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
95 static bool __read_mostly fasteoi
= 1;
96 module_param(fasteoi
, bool, S_IRUGO
);
98 static bool __read_mostly enable_apicv
= 1;
99 module_param(enable_apicv
, bool, S_IRUGO
);
101 static bool __read_mostly enable_shadow_vmcs
= 1;
102 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
104 * If nested=1, nested virtualization is supported, i.e., guests may use
105 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
106 * use VMX instructions.
108 static bool __read_mostly nested
= 0;
109 module_param(nested
, bool, S_IRUGO
);
111 static u64 __read_mostly host_xss
;
113 static bool __read_mostly enable_pml
= 1;
114 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
118 #define MSR_TYPE_RW 3
120 #define MSR_BITMAP_MODE_X2APIC 1
121 #define MSR_BITMAP_MODE_X2APIC_APICV 2
122 #define MSR_BITMAP_MODE_LM 4
124 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
126 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
127 static int __read_mostly cpu_preemption_timer_multi
;
128 static bool __read_mostly enable_preemption_timer
= 1;
130 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
133 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
134 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
135 #define KVM_VM_CR0_ALWAYS_ON \
136 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
137 #define KVM_CR4_GUEST_OWNED_BITS \
138 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
139 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
146 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
149 * Hyper-V requires all of these, so mark them as supported even though
150 * they are just treated the same as all-context.
152 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
153 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
154 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
155 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
156 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
159 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
160 * ple_gap: upper bound on the amount of time between two successive
161 * executions of PAUSE in a loop. Also indicate if ple enabled.
162 * According to test, this time is usually smaller than 128 cycles.
163 * ple_window: upper bound on the amount of time a guest is allowed to execute
164 * in a PAUSE loop. Tests indicate that most spinlocks are held for
165 * less than 2^12 cycles
166 * Time is measured based on a counter that runs at the same rate as the TSC,
167 * refer SDM volume 3b section 21.6.13 & 22.1.3.
169 #define KVM_VMX_DEFAULT_PLE_GAP 128
170 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
171 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
172 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
173 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
174 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
176 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
177 module_param(ple_gap
, int, S_IRUGO
);
179 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
180 module_param(ple_window
, int, S_IRUGO
);
182 /* Default doubles per-vcpu window every exit. */
183 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
184 module_param(ple_window_grow
, int, S_IRUGO
);
186 /* Default resets per-vcpu window every exit to ple_window. */
187 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
188 module_param(ple_window_shrink
, int, S_IRUGO
);
190 /* Default is to compute the maximum so we can never overflow. */
191 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
192 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
193 module_param(ple_window_max
, int, S_IRUGO
);
195 extern const ulong vmx_return
;
197 #define NR_AUTOLOAD_MSRS 8
206 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
207 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
208 * loaded on this CPU (so we can clear them if the CPU goes down).
212 struct vmcs
*shadow_vmcs
;
215 bool nmi_known_unmasked
;
216 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
217 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
218 /* Support for vnmi-less CPUs */
219 int soft_vnmi_blocked
;
221 s64 vnmi_blocked_time
;
222 unsigned long *msr_bitmap
;
223 struct list_head loaded_vmcss_on_cpu_link
;
226 struct shared_msr_entry
{
233 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
234 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
235 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
236 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
237 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
238 * More than one of these structures may exist, if L1 runs multiple L2 guests.
239 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
240 * underlying hardware which will be used to run L2.
241 * This structure is packed to ensure that its layout is identical across
242 * machines (necessary for live migration).
243 * If there are changes in this struct, VMCS12_REVISION must be changed.
245 typedef u64 natural_width
;
246 struct __packed vmcs12
{
247 /* According to the Intel spec, a VMCS region must start with the
248 * following two fields. Then follow implementation-specific data.
253 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
254 u32 padding
[7]; /* room for future expansion */
259 u64 vm_exit_msr_store_addr
;
260 u64 vm_exit_msr_load_addr
;
261 u64 vm_entry_msr_load_addr
;
263 u64 virtual_apic_page_addr
;
264 u64 apic_access_addr
;
265 u64 posted_intr_desc_addr
;
266 u64 vm_function_control
;
268 u64 eoi_exit_bitmap0
;
269 u64 eoi_exit_bitmap1
;
270 u64 eoi_exit_bitmap2
;
271 u64 eoi_exit_bitmap3
;
272 u64 eptp_list_address
;
274 u64 guest_physical_address
;
275 u64 vmcs_link_pointer
;
277 u64 guest_ia32_debugctl
;
280 u64 guest_ia32_perf_global_ctrl
;
288 u64 host_ia32_perf_global_ctrl
;
289 u64 padding64
[8]; /* room for future expansion */
291 * To allow migration of L1 (complete with its L2 guests) between
292 * machines of different natural widths (32 or 64 bit), we cannot have
293 * unsigned long fields with no explict size. We use u64 (aliased
294 * natural_width) instead. Luckily, x86 is little-endian.
296 natural_width cr0_guest_host_mask
;
297 natural_width cr4_guest_host_mask
;
298 natural_width cr0_read_shadow
;
299 natural_width cr4_read_shadow
;
300 natural_width cr3_target_value0
;
301 natural_width cr3_target_value1
;
302 natural_width cr3_target_value2
;
303 natural_width cr3_target_value3
;
304 natural_width exit_qualification
;
305 natural_width guest_linear_address
;
306 natural_width guest_cr0
;
307 natural_width guest_cr3
;
308 natural_width guest_cr4
;
309 natural_width guest_es_base
;
310 natural_width guest_cs_base
;
311 natural_width guest_ss_base
;
312 natural_width guest_ds_base
;
313 natural_width guest_fs_base
;
314 natural_width guest_gs_base
;
315 natural_width guest_ldtr_base
;
316 natural_width guest_tr_base
;
317 natural_width guest_gdtr_base
;
318 natural_width guest_idtr_base
;
319 natural_width guest_dr7
;
320 natural_width guest_rsp
;
321 natural_width guest_rip
;
322 natural_width guest_rflags
;
323 natural_width guest_pending_dbg_exceptions
;
324 natural_width guest_sysenter_esp
;
325 natural_width guest_sysenter_eip
;
326 natural_width host_cr0
;
327 natural_width host_cr3
;
328 natural_width host_cr4
;
329 natural_width host_fs_base
;
330 natural_width host_gs_base
;
331 natural_width host_tr_base
;
332 natural_width host_gdtr_base
;
333 natural_width host_idtr_base
;
334 natural_width host_ia32_sysenter_esp
;
335 natural_width host_ia32_sysenter_eip
;
336 natural_width host_rsp
;
337 natural_width host_rip
;
338 natural_width paddingl
[8]; /* room for future expansion */
339 u32 pin_based_vm_exec_control
;
340 u32 cpu_based_vm_exec_control
;
341 u32 exception_bitmap
;
342 u32 page_fault_error_code_mask
;
343 u32 page_fault_error_code_match
;
344 u32 cr3_target_count
;
345 u32 vm_exit_controls
;
346 u32 vm_exit_msr_store_count
;
347 u32 vm_exit_msr_load_count
;
348 u32 vm_entry_controls
;
349 u32 vm_entry_msr_load_count
;
350 u32 vm_entry_intr_info_field
;
351 u32 vm_entry_exception_error_code
;
352 u32 vm_entry_instruction_len
;
354 u32 secondary_vm_exec_control
;
355 u32 vm_instruction_error
;
357 u32 vm_exit_intr_info
;
358 u32 vm_exit_intr_error_code
;
359 u32 idt_vectoring_info_field
;
360 u32 idt_vectoring_error_code
;
361 u32 vm_exit_instruction_len
;
362 u32 vmx_instruction_info
;
369 u32 guest_ldtr_limit
;
371 u32 guest_gdtr_limit
;
372 u32 guest_idtr_limit
;
373 u32 guest_es_ar_bytes
;
374 u32 guest_cs_ar_bytes
;
375 u32 guest_ss_ar_bytes
;
376 u32 guest_ds_ar_bytes
;
377 u32 guest_fs_ar_bytes
;
378 u32 guest_gs_ar_bytes
;
379 u32 guest_ldtr_ar_bytes
;
380 u32 guest_tr_ar_bytes
;
381 u32 guest_interruptibility_info
;
382 u32 guest_activity_state
;
383 u32 guest_sysenter_cs
;
384 u32 host_ia32_sysenter_cs
;
385 u32 vmx_preemption_timer_value
;
386 u32 padding32
[7]; /* room for future expansion */
387 u16 virtual_processor_id
;
389 u16 guest_es_selector
;
390 u16 guest_cs_selector
;
391 u16 guest_ss_selector
;
392 u16 guest_ds_selector
;
393 u16 guest_fs_selector
;
394 u16 guest_gs_selector
;
395 u16 guest_ldtr_selector
;
396 u16 guest_tr_selector
;
397 u16 guest_intr_status
;
399 u16 host_es_selector
;
400 u16 host_cs_selector
;
401 u16 host_ss_selector
;
402 u16 host_ds_selector
;
403 u16 host_fs_selector
;
404 u16 host_gs_selector
;
405 u16 host_tr_selector
;
409 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
410 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
411 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
413 #define VMCS12_REVISION 0x11e57ed0
416 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
417 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
418 * current implementation, 4K are reserved to avoid future complications.
420 #define VMCS12_SIZE 0x1000
423 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
424 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
427 /* Has the level1 guest done vmxon? */
432 /* The guest-physical address of the current VMCS L1 keeps for L2 */
435 * Cache of the guest's VMCS, existing outside of guest memory.
436 * Loaded from guest memory during VMPTRLD. Flushed to guest
437 * memory during VMCLEAR and VMPTRLD.
439 struct vmcs12
*cached_vmcs12
;
441 * Indicates if the shadow vmcs must be updated with the
442 * data hold by vmcs12
444 bool sync_shadow_vmcs
;
446 bool change_vmcs01_virtual_x2apic_mode
;
447 /* L2 must run next, and mustn't decide to exit to L1. */
448 bool nested_run_pending
;
450 struct loaded_vmcs vmcs02
;
453 * Guest pages referred to in the vmcs02 with host-physical
454 * pointers, so we must keep them pinned while L2 runs.
456 struct page
*apic_access_page
;
457 struct page
*virtual_apic_page
;
458 struct page
*pi_desc_page
;
459 struct pi_desc
*pi_desc
;
463 struct hrtimer preemption_timer
;
464 bool preemption_timer_expired
;
466 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
473 * We only store the "true" versions of the VMX capability MSRs. We
474 * generate the "non-true" versions by setting the must-be-1 bits
475 * according to the SDM.
477 u32 nested_vmx_procbased_ctls_low
;
478 u32 nested_vmx_procbased_ctls_high
;
479 u32 nested_vmx_secondary_ctls_low
;
480 u32 nested_vmx_secondary_ctls_high
;
481 u32 nested_vmx_pinbased_ctls_low
;
482 u32 nested_vmx_pinbased_ctls_high
;
483 u32 nested_vmx_exit_ctls_low
;
484 u32 nested_vmx_exit_ctls_high
;
485 u32 nested_vmx_entry_ctls_low
;
486 u32 nested_vmx_entry_ctls_high
;
487 u32 nested_vmx_misc_low
;
488 u32 nested_vmx_misc_high
;
489 u32 nested_vmx_ept_caps
;
490 u32 nested_vmx_vpid_caps
;
491 u64 nested_vmx_basic
;
492 u64 nested_vmx_cr0_fixed0
;
493 u64 nested_vmx_cr0_fixed1
;
494 u64 nested_vmx_cr4_fixed0
;
495 u64 nested_vmx_cr4_fixed1
;
496 u64 nested_vmx_vmcs_enum
;
497 u64 nested_vmx_vmfunc_controls
;
499 /* SMM related state */
501 /* in VMX operation on SMM entry? */
503 /* in guest mode on SMM entry? */
508 #define POSTED_INTR_ON 0
509 #define POSTED_INTR_SN 1
511 /* Posted-Interrupt Descriptor */
513 u32 pir
[8]; /* Posted interrupt requested */
516 /* bit 256 - Outstanding Notification */
518 /* bit 257 - Suppress Notification */
520 /* bit 271:258 - Reserved */
522 /* bit 279:272 - Notification Vector */
524 /* bit 287:280 - Reserved */
526 /* bit 319:288 - Notification Destination */
534 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
536 return test_and_set_bit(POSTED_INTR_ON
,
537 (unsigned long *)&pi_desc
->control
);
540 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
542 return test_and_clear_bit(POSTED_INTR_ON
,
543 (unsigned long *)&pi_desc
->control
);
546 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
548 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
551 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
553 return clear_bit(POSTED_INTR_SN
,
554 (unsigned long *)&pi_desc
->control
);
557 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
559 return set_bit(POSTED_INTR_SN
,
560 (unsigned long *)&pi_desc
->control
);
563 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
565 clear_bit(POSTED_INTR_ON
,
566 (unsigned long *)&pi_desc
->control
);
569 static inline int pi_test_on(struct pi_desc
*pi_desc
)
571 return test_bit(POSTED_INTR_ON
,
572 (unsigned long *)&pi_desc
->control
);
575 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
577 return test_bit(POSTED_INTR_SN
,
578 (unsigned long *)&pi_desc
->control
);
582 struct kvm_vcpu vcpu
;
583 unsigned long host_rsp
;
587 u32 idt_vectoring_info
;
589 struct shared_msr_entry
*guest_msrs
;
592 unsigned long host_idt_base
;
594 u64 msr_host_kernel_gs_base
;
595 u64 msr_guest_kernel_gs_base
;
598 u64 arch_capabilities
;
601 u32 vm_entry_controls_shadow
;
602 u32 vm_exit_controls_shadow
;
603 u32 secondary_exec_control
;
606 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
607 * non-nested (L1) guest, it always points to vmcs01. For a nested
608 * guest (L2), it points to a different VMCS.
610 struct loaded_vmcs vmcs01
;
611 struct loaded_vmcs
*loaded_vmcs
;
612 bool __launched
; /* temporary, used in vmx_vcpu_run */
613 struct msr_autoload
{
615 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
616 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
620 u16 fs_sel
, gs_sel
, ldt_sel
;
624 int gs_ldt_reload_needed
;
625 int fs_reload_needed
;
626 u64 msr_host_bndcfgs
;
631 struct kvm_segment segs
[8];
634 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
635 struct kvm_save_segment
{
643 bool emulation_required
;
647 /* Posted interrupt descriptor */
648 struct pi_desc pi_desc
;
650 /* Support for a guest hypervisor (nested VMX) */
651 struct nested_vmx nested
;
653 /* Dynamic PLE window. */
655 bool ple_window_dirty
;
657 /* Support for PML */
658 #define PML_ENTITY_NUM 512
661 /* apic deadline value in host tsc */
664 u64 current_tsc_ratio
;
669 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
670 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
671 * in msr_ia32_feature_control_valid_bits.
673 u64 msr_ia32_feature_control
;
674 u64 msr_ia32_feature_control_valid_bits
;
677 enum segment_cache_field
{
686 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
688 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
691 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
693 return &(to_vmx(vcpu
)->pi_desc
);
696 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
697 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
698 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
699 [number##_HIGH] = VMCS12_OFFSET(name)+4
702 static unsigned long shadow_read_only_fields
[] = {
704 * We do NOT shadow fields that are modified when L0
705 * traps and emulates any vmx instruction (e.g. VMPTRLD,
706 * VMXON...) executed by L1.
707 * For example, VM_INSTRUCTION_ERROR is read
708 * by L1 if a vmx instruction fails (part of the error path).
709 * Note the code assumes this logic. If for some reason
710 * we start shadowing these fields then we need to
711 * force a shadow sync when L0 emulates vmx instructions
712 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
713 * by nested_vmx_failValid)
717 VM_EXIT_INSTRUCTION_LEN
,
718 IDT_VECTORING_INFO_FIELD
,
719 IDT_VECTORING_ERROR_CODE
,
720 VM_EXIT_INTR_ERROR_CODE
,
722 GUEST_LINEAR_ADDRESS
,
723 GUEST_PHYSICAL_ADDRESS
725 static int max_shadow_read_only_fields
=
726 ARRAY_SIZE(shadow_read_only_fields
);
728 static unsigned long shadow_read_write_fields
[] = {
735 GUEST_INTERRUPTIBILITY_INFO
,
748 CPU_BASED_VM_EXEC_CONTROL
,
749 VM_ENTRY_EXCEPTION_ERROR_CODE
,
750 VM_ENTRY_INTR_INFO_FIELD
,
751 VM_ENTRY_INSTRUCTION_LEN
,
752 VM_ENTRY_EXCEPTION_ERROR_CODE
,
758 static int max_shadow_read_write_fields
=
759 ARRAY_SIZE(shadow_read_write_fields
);
761 static const unsigned short vmcs_field_to_offset_table
[] = {
762 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
763 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
764 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
765 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
766 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
767 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
768 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
769 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
770 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
771 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
772 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
773 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
774 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
775 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
776 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
777 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
778 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
779 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
780 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
781 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
782 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
783 FIELD64(MSR_BITMAP
, msr_bitmap
),
784 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
785 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
786 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
787 FIELD64(TSC_OFFSET
, tsc_offset
),
788 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
789 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
790 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
791 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
792 FIELD64(EPT_POINTER
, ept_pointer
),
793 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
794 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
795 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
796 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
797 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
798 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
799 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
800 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
801 FIELD64(PML_ADDRESS
, pml_address
),
802 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
803 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
804 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
805 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
806 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
807 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
808 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
809 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
810 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
811 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
812 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
813 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
814 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
815 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
816 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
817 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
818 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
819 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
820 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
821 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
822 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
823 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
824 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
825 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
826 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
827 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
828 FIELD(TPR_THRESHOLD
, tpr_threshold
),
829 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
830 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
831 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
832 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
833 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
834 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
835 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
836 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
837 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
838 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
839 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
840 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
841 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
842 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
843 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
844 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
845 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
846 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
847 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
848 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
849 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
850 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
851 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
852 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
853 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
854 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
855 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
856 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
857 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
858 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
859 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
860 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
861 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
862 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
863 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
864 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
865 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
866 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
867 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
868 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
869 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
870 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
871 FIELD(GUEST_CR0
, guest_cr0
),
872 FIELD(GUEST_CR3
, guest_cr3
),
873 FIELD(GUEST_CR4
, guest_cr4
),
874 FIELD(GUEST_ES_BASE
, guest_es_base
),
875 FIELD(GUEST_CS_BASE
, guest_cs_base
),
876 FIELD(GUEST_SS_BASE
, guest_ss_base
),
877 FIELD(GUEST_DS_BASE
, guest_ds_base
),
878 FIELD(GUEST_FS_BASE
, guest_fs_base
),
879 FIELD(GUEST_GS_BASE
, guest_gs_base
),
880 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
881 FIELD(GUEST_TR_BASE
, guest_tr_base
),
882 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
883 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
884 FIELD(GUEST_DR7
, guest_dr7
),
885 FIELD(GUEST_RSP
, guest_rsp
),
886 FIELD(GUEST_RIP
, guest_rip
),
887 FIELD(GUEST_RFLAGS
, guest_rflags
),
888 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
889 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
890 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
891 FIELD(HOST_CR0
, host_cr0
),
892 FIELD(HOST_CR3
, host_cr3
),
893 FIELD(HOST_CR4
, host_cr4
),
894 FIELD(HOST_FS_BASE
, host_fs_base
),
895 FIELD(HOST_GS_BASE
, host_gs_base
),
896 FIELD(HOST_TR_BASE
, host_tr_base
),
897 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
898 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
899 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
900 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
901 FIELD(HOST_RSP
, host_rsp
),
902 FIELD(HOST_RIP
, host_rip
),
905 static inline short vmcs_field_to_offset(unsigned long field
)
907 const size_t size
= ARRAY_SIZE(vmcs_field_to_offset_table
);
908 unsigned short offset
;
910 BUILD_BUG_ON(size
> SHRT_MAX
);
914 field
= array_index_nospec(field
, size
);
915 offset
= vmcs_field_to_offset_table
[field
];
921 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
923 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
926 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
927 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
928 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
929 static bool vmx_xsaves_supported(void);
930 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
931 struct kvm_segment
*var
, int seg
);
932 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
933 struct kvm_segment
*var
, int seg
);
934 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
935 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
936 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
937 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
938 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
939 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
941 static void vmx_update_msr_bitmap(struct kvm_vcpu
*vcpu
);
942 static void __always_inline
vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
945 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
946 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
948 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
949 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
951 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
954 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
955 * can find which vCPU should be waken up.
957 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
958 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
968 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
970 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
971 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
972 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
973 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
975 static bool cpu_has_load_ia32_efer
;
976 static bool cpu_has_load_perf_global_ctrl
;
978 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
979 static DEFINE_SPINLOCK(vmx_vpid_lock
);
981 static struct vmcs_config
{
986 u32 pin_based_exec_ctrl
;
987 u32 cpu_based_exec_ctrl
;
988 u32 cpu_based_2nd_exec_ctrl
;
993 static struct vmx_capability
{
998 #define VMX_SEGMENT_FIELD(seg) \
999 [VCPU_SREG_##seg] = { \
1000 .selector = GUEST_##seg##_SELECTOR, \
1001 .base = GUEST_##seg##_BASE, \
1002 .limit = GUEST_##seg##_LIMIT, \
1003 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1006 static const struct kvm_vmx_segment_field
{
1011 } kvm_vmx_segment_fields
[] = {
1012 VMX_SEGMENT_FIELD(CS
),
1013 VMX_SEGMENT_FIELD(DS
),
1014 VMX_SEGMENT_FIELD(ES
),
1015 VMX_SEGMENT_FIELD(FS
),
1016 VMX_SEGMENT_FIELD(GS
),
1017 VMX_SEGMENT_FIELD(SS
),
1018 VMX_SEGMENT_FIELD(TR
),
1019 VMX_SEGMENT_FIELD(LDTR
),
1022 static u64 host_efer
;
1024 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1027 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1028 * away by decrementing the array size.
1030 static const u32 vmx_msr_index
[] = {
1031 #ifdef CONFIG_X86_64
1032 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1034 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1037 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1039 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1040 INTR_INFO_VALID_MASK
)) ==
1041 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1044 static inline bool is_debug(u32 intr_info
)
1046 return is_exception_n(intr_info
, DB_VECTOR
);
1049 static inline bool is_breakpoint(u32 intr_info
)
1051 return is_exception_n(intr_info
, BP_VECTOR
);
1054 static inline bool is_page_fault(u32 intr_info
)
1056 return is_exception_n(intr_info
, PF_VECTOR
);
1059 static inline bool is_no_device(u32 intr_info
)
1061 return is_exception_n(intr_info
, NM_VECTOR
);
1064 static inline bool is_invalid_opcode(u32 intr_info
)
1066 return is_exception_n(intr_info
, UD_VECTOR
);
1069 static inline bool is_external_interrupt(u32 intr_info
)
1071 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1072 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1075 static inline bool is_machine_check(u32 intr_info
)
1077 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1078 INTR_INFO_VALID_MASK
)) ==
1079 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1082 /* Undocumented: icebp/int1 */
1083 static inline bool is_icebp(u32 intr_info
)
1085 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1086 == (INTR_TYPE_PRIV_SW_EXCEPTION
| INTR_INFO_VALID_MASK
);
1089 static inline bool cpu_has_vmx_msr_bitmap(void)
1091 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1094 static inline bool cpu_has_vmx_tpr_shadow(void)
1096 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1099 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1101 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1104 static inline bool cpu_has_secondary_exec_ctrls(void)
1106 return vmcs_config
.cpu_based_exec_ctrl
&
1107 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1110 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1112 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1113 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1116 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1118 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1119 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1122 static inline bool cpu_has_vmx_apic_register_virt(void)
1124 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1125 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1128 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1130 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1131 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1135 * Comment's format: document - errata name - stepping - processor name.
1137 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1139 static u32 vmx_preemption_cpu_tfms
[] = {
1140 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1142 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1143 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1144 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1146 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1148 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1149 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1151 * 320767.pdf - AAP86 - B1 -
1152 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1155 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1157 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1159 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1161 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1162 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1163 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1167 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1169 u32 eax
= cpuid_eax(0x00000001), i
;
1171 /* Clear the reserved bits */
1172 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1173 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1174 if (eax
== vmx_preemption_cpu_tfms
[i
])
1180 static inline bool cpu_has_vmx_preemption_timer(void)
1182 return vmcs_config
.pin_based_exec_ctrl
&
1183 PIN_BASED_VMX_PREEMPTION_TIMER
;
1186 static inline bool cpu_has_vmx_posted_intr(void)
1188 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1189 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1192 static inline bool cpu_has_vmx_apicv(void)
1194 return cpu_has_vmx_apic_register_virt() &&
1195 cpu_has_vmx_virtual_intr_delivery() &&
1196 cpu_has_vmx_posted_intr();
1199 static inline bool cpu_has_vmx_flexpriority(void)
1201 return cpu_has_vmx_tpr_shadow() &&
1202 cpu_has_vmx_virtualize_apic_accesses();
1205 static inline bool cpu_has_vmx_ept_execute_only(void)
1207 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1210 static inline bool cpu_has_vmx_ept_2m_page(void)
1212 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1215 static inline bool cpu_has_vmx_ept_1g_page(void)
1217 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1220 static inline bool cpu_has_vmx_ept_4levels(void)
1222 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1225 static inline bool cpu_has_vmx_ept_mt_wb(void)
1227 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1230 static inline bool cpu_has_vmx_ept_5levels(void)
1232 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1235 static inline bool cpu_has_vmx_ept_ad_bits(void)
1237 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1240 static inline bool cpu_has_vmx_invept_context(void)
1242 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1245 static inline bool cpu_has_vmx_invept_global(void)
1247 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1250 static inline bool cpu_has_vmx_invvpid_single(void)
1252 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1255 static inline bool cpu_has_vmx_invvpid_global(void)
1257 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1260 static inline bool cpu_has_vmx_invvpid(void)
1262 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1265 static inline bool cpu_has_vmx_ept(void)
1267 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1268 SECONDARY_EXEC_ENABLE_EPT
;
1271 static inline bool cpu_has_vmx_unrestricted_guest(void)
1273 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1274 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1277 static inline bool cpu_has_vmx_ple(void)
1279 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1280 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1283 static inline bool cpu_has_vmx_basic_inout(void)
1285 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1288 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1290 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1293 static inline bool cpu_has_vmx_vpid(void)
1295 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1296 SECONDARY_EXEC_ENABLE_VPID
;
1299 static inline bool cpu_has_vmx_rdtscp(void)
1301 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1302 SECONDARY_EXEC_RDTSCP
;
1305 static inline bool cpu_has_vmx_invpcid(void)
1307 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1308 SECONDARY_EXEC_ENABLE_INVPCID
;
1311 static inline bool cpu_has_virtual_nmis(void)
1313 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1316 static inline bool cpu_has_vmx_wbinvd_exit(void)
1318 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1319 SECONDARY_EXEC_WBINVD_EXITING
;
1322 static inline bool cpu_has_vmx_shadow_vmcs(void)
1325 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1326 /* check if the cpu supports writing r/o exit information fields */
1327 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1330 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1331 SECONDARY_EXEC_SHADOW_VMCS
;
1334 static inline bool cpu_has_vmx_pml(void)
1336 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1339 static inline bool cpu_has_vmx_tsc_scaling(void)
1341 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1342 SECONDARY_EXEC_TSC_SCALING
;
1345 static inline bool cpu_has_vmx_vmfunc(void)
1347 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1348 SECONDARY_EXEC_ENABLE_VMFUNC
;
1351 static inline bool report_flexpriority(void)
1353 return flexpriority_enabled
;
1356 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1358 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1361 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1363 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1366 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1368 return (vmcs12
->cpu_based_vm_exec_control
&
1369 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1370 (vmcs12
->secondary_vm_exec_control
& bit
);
1373 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1375 return vmcs12
->pin_based_vm_exec_control
&
1376 PIN_BASED_VMX_PREEMPTION_TIMER
;
1379 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1381 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1384 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1386 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
1389 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1391 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1394 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1396 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1399 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1401 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1404 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1406 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1409 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1411 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1414 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1416 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1419 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1421 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1424 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1426 return nested_cpu_has_vmfunc(vmcs12
) &&
1427 (vmcs12
->vm_function_control
&
1428 VMX_VMFUNC_EPTP_SWITCHING
);
1431 static inline bool is_nmi(u32 intr_info
)
1433 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1434 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1437 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1439 unsigned long exit_qualification
);
1440 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1441 struct vmcs12
*vmcs12
,
1442 u32 reason
, unsigned long qualification
);
1444 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1448 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1449 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1454 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1460 } operand
= { vpid
, 0, gva
};
1462 asm volatile (__ex(ASM_VMX_INVVPID
)
1463 /* CF==1 or ZF==1 --> rc = -1 */
1464 "; ja 1f ; ud2 ; 1:"
1465 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1468 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1472 } operand
= {eptp
, gpa
};
1474 asm volatile (__ex(ASM_VMX_INVEPT
)
1475 /* CF==1 or ZF==1 --> rc = -1 */
1476 "; ja 1f ; ud2 ; 1:\n"
1477 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1480 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1484 i
= __find_msr_index(vmx
, msr
);
1486 return &vmx
->guest_msrs
[i
];
1490 static void vmcs_clear(struct vmcs
*vmcs
)
1492 u64 phys_addr
= __pa(vmcs
);
1495 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1496 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1499 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1503 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1505 vmcs_clear(loaded_vmcs
->vmcs
);
1506 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1507 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1508 loaded_vmcs
->cpu
= -1;
1509 loaded_vmcs
->launched
= 0;
1512 static void vmcs_load(struct vmcs
*vmcs
)
1514 u64 phys_addr
= __pa(vmcs
);
1517 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1518 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1521 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1525 #ifdef CONFIG_KEXEC_CORE
1527 * This bitmap is used to indicate whether the vmclear
1528 * operation is enabled on all cpus. All disabled by
1531 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1533 static inline void crash_enable_local_vmclear(int cpu
)
1535 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1538 static inline void crash_disable_local_vmclear(int cpu
)
1540 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1543 static inline int crash_local_vmclear_enabled(int cpu
)
1545 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1548 static void crash_vmclear_local_loaded_vmcss(void)
1550 int cpu
= raw_smp_processor_id();
1551 struct loaded_vmcs
*v
;
1553 if (!crash_local_vmclear_enabled(cpu
))
1556 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1557 loaded_vmcss_on_cpu_link
)
1558 vmcs_clear(v
->vmcs
);
1561 static inline void crash_enable_local_vmclear(int cpu
) { }
1562 static inline void crash_disable_local_vmclear(int cpu
) { }
1563 #endif /* CONFIG_KEXEC_CORE */
1565 static void __loaded_vmcs_clear(void *arg
)
1567 struct loaded_vmcs
*loaded_vmcs
= arg
;
1568 int cpu
= raw_smp_processor_id();
1570 if (loaded_vmcs
->cpu
!= cpu
)
1571 return; /* vcpu migration can race with cpu offline */
1572 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1573 per_cpu(current_vmcs
, cpu
) = NULL
;
1574 crash_disable_local_vmclear(cpu
);
1575 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1578 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1579 * is before setting loaded_vmcs->vcpu to -1 which is done in
1580 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1581 * then adds the vmcs into percpu list before it is deleted.
1585 loaded_vmcs_init(loaded_vmcs
);
1586 crash_enable_local_vmclear(cpu
);
1589 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1591 int cpu
= loaded_vmcs
->cpu
;
1594 smp_call_function_single(cpu
,
1595 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1598 static inline void vpid_sync_vcpu_single(int vpid
)
1603 if (cpu_has_vmx_invvpid_single())
1604 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1607 static inline void vpid_sync_vcpu_global(void)
1609 if (cpu_has_vmx_invvpid_global())
1610 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1613 static inline void vpid_sync_context(int vpid
)
1615 if (cpu_has_vmx_invvpid_single())
1616 vpid_sync_vcpu_single(vpid
);
1618 vpid_sync_vcpu_global();
1621 static inline void ept_sync_global(void)
1623 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1626 static inline void ept_sync_context(u64 eptp
)
1628 if (cpu_has_vmx_invept_context())
1629 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1634 static __always_inline
void vmcs_check16(unsigned long field
)
1636 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1637 "16-bit accessor invalid for 64-bit field");
1638 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1639 "16-bit accessor invalid for 64-bit high field");
1640 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1641 "16-bit accessor invalid for 32-bit high field");
1642 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1643 "16-bit accessor invalid for natural width field");
1646 static __always_inline
void vmcs_check32(unsigned long field
)
1648 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1649 "32-bit accessor invalid for 16-bit field");
1650 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1651 "32-bit accessor invalid for natural width field");
1654 static __always_inline
void vmcs_check64(unsigned long field
)
1656 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1657 "64-bit accessor invalid for 16-bit field");
1658 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1659 "64-bit accessor invalid for 64-bit high field");
1660 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1661 "64-bit accessor invalid for 32-bit field");
1662 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1663 "64-bit accessor invalid for natural width field");
1666 static __always_inline
void vmcs_checkl(unsigned long field
)
1668 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1669 "Natural width accessor invalid for 16-bit field");
1670 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1671 "Natural width accessor invalid for 64-bit field");
1672 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1673 "Natural width accessor invalid for 64-bit high field");
1674 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1675 "Natural width accessor invalid for 32-bit field");
1678 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1680 unsigned long value
;
1682 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1683 : "=a"(value
) : "d"(field
) : "cc");
1687 static __always_inline u16
vmcs_read16(unsigned long field
)
1689 vmcs_check16(field
);
1690 return __vmcs_readl(field
);
1693 static __always_inline u32
vmcs_read32(unsigned long field
)
1695 vmcs_check32(field
);
1696 return __vmcs_readl(field
);
1699 static __always_inline u64
vmcs_read64(unsigned long field
)
1701 vmcs_check64(field
);
1702 #ifdef CONFIG_X86_64
1703 return __vmcs_readl(field
);
1705 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1709 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1712 return __vmcs_readl(field
);
1715 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1717 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1718 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1722 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1726 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1727 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1728 if (unlikely(error
))
1729 vmwrite_error(field
, value
);
1732 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1734 vmcs_check16(field
);
1735 __vmcs_writel(field
, value
);
1738 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1740 vmcs_check32(field
);
1741 __vmcs_writel(field
, value
);
1744 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1746 vmcs_check64(field
);
1747 __vmcs_writel(field
, value
);
1748 #ifndef CONFIG_X86_64
1750 __vmcs_writel(field
+1, value
>> 32);
1754 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1757 __vmcs_writel(field
, value
);
1760 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1762 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1763 "vmcs_clear_bits does not support 64-bit fields");
1764 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1767 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1769 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1770 "vmcs_set_bits does not support 64-bit fields");
1771 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1774 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1776 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1779 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1781 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1782 vmx
->vm_entry_controls_shadow
= val
;
1785 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1787 if (vmx
->vm_entry_controls_shadow
!= val
)
1788 vm_entry_controls_init(vmx
, val
);
1791 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1793 return vmx
->vm_entry_controls_shadow
;
1797 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1799 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1802 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1804 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1807 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1809 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1812 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1814 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1815 vmx
->vm_exit_controls_shadow
= val
;
1818 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1820 if (vmx
->vm_exit_controls_shadow
!= val
)
1821 vm_exit_controls_init(vmx
, val
);
1824 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1826 return vmx
->vm_exit_controls_shadow
;
1830 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1832 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1835 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1837 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1840 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1842 vmx
->segment_cache
.bitmask
= 0;
1845 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1849 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1851 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1852 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1853 vmx
->segment_cache
.bitmask
= 0;
1855 ret
= vmx
->segment_cache
.bitmask
& mask
;
1856 vmx
->segment_cache
.bitmask
|= mask
;
1860 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1862 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1864 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1865 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1869 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1871 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1873 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1874 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1878 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1880 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1882 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1883 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1887 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1889 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1891 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1892 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1896 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1900 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1901 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1902 if ((vcpu
->guest_debug
&
1903 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1904 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1905 eb
|= 1u << BP_VECTOR
;
1906 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1909 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1911 /* When we are running a nested L2 guest and L1 specified for it a
1912 * certain exception bitmap, we must trap the same exceptions and pass
1913 * them to L1. When running L2, we will only handle the exceptions
1914 * specified above if L1 did not want them.
1916 if (is_guest_mode(vcpu
))
1917 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1919 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1923 * Check if MSR is intercepted for currently loaded MSR bitmap.
1925 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, u32 msr
)
1927 unsigned long *msr_bitmap
;
1928 int f
= sizeof(unsigned long);
1930 if (!cpu_has_vmx_msr_bitmap())
1933 msr_bitmap
= to_vmx(vcpu
)->loaded_vmcs
->msr_bitmap
;
1935 if (msr
<= 0x1fff) {
1936 return !!test_bit(msr
, msr_bitmap
+ 0x800 / f
);
1937 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
1939 return !!test_bit(msr
, msr_bitmap
+ 0xc00 / f
);
1946 * Check if MSR is intercepted for L01 MSR bitmap.
1948 static bool msr_write_intercepted_l01(struct kvm_vcpu
*vcpu
, u32 msr
)
1950 unsigned long *msr_bitmap
;
1951 int f
= sizeof(unsigned long);
1953 if (!cpu_has_vmx_msr_bitmap())
1956 msr_bitmap
= to_vmx(vcpu
)->vmcs01
.msr_bitmap
;
1958 if (msr
<= 0x1fff) {
1959 return !!test_bit(msr
, msr_bitmap
+ 0x800 / f
);
1960 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
1962 return !!test_bit(msr
, msr_bitmap
+ 0xc00 / f
);
1968 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1969 unsigned long entry
, unsigned long exit
)
1971 vm_entry_controls_clearbit(vmx
, entry
);
1972 vm_exit_controls_clearbit(vmx
, exit
);
1975 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1978 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1982 if (cpu_has_load_ia32_efer
) {
1983 clear_atomic_switch_msr_special(vmx
,
1984 VM_ENTRY_LOAD_IA32_EFER
,
1985 VM_EXIT_LOAD_IA32_EFER
);
1989 case MSR_CORE_PERF_GLOBAL_CTRL
:
1990 if (cpu_has_load_perf_global_ctrl
) {
1991 clear_atomic_switch_msr_special(vmx
,
1992 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1993 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1999 for (i
= 0; i
< m
->nr
; ++i
)
2000 if (m
->guest
[i
].index
== msr
)
2006 m
->guest
[i
] = m
->guest
[m
->nr
];
2007 m
->host
[i
] = m
->host
[m
->nr
];
2008 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2009 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2012 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
2013 unsigned long entry
, unsigned long exit
,
2014 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
2015 u64 guest_val
, u64 host_val
)
2017 vmcs_write64(guest_val_vmcs
, guest_val
);
2018 vmcs_write64(host_val_vmcs
, host_val
);
2019 vm_entry_controls_setbit(vmx
, entry
);
2020 vm_exit_controls_setbit(vmx
, exit
);
2023 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
2024 u64 guest_val
, u64 host_val
)
2027 struct msr_autoload
*m
= &vmx
->msr_autoload
;
2031 if (cpu_has_load_ia32_efer
) {
2032 add_atomic_switch_msr_special(vmx
,
2033 VM_ENTRY_LOAD_IA32_EFER
,
2034 VM_EXIT_LOAD_IA32_EFER
,
2037 guest_val
, host_val
);
2041 case MSR_CORE_PERF_GLOBAL_CTRL
:
2042 if (cpu_has_load_perf_global_ctrl
) {
2043 add_atomic_switch_msr_special(vmx
,
2044 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
2045 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
2046 GUEST_IA32_PERF_GLOBAL_CTRL
,
2047 HOST_IA32_PERF_GLOBAL_CTRL
,
2048 guest_val
, host_val
);
2052 case MSR_IA32_PEBS_ENABLE
:
2053 /* PEBS needs a quiescent period after being disabled (to write
2054 * a record). Disabling PEBS through VMX MSR swapping doesn't
2055 * provide that period, so a CPU could write host's record into
2058 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
2061 for (i
= 0; i
< m
->nr
; ++i
)
2062 if (m
->guest
[i
].index
== msr
)
2065 if (i
== NR_AUTOLOAD_MSRS
) {
2066 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2067 "Can't add msr %x\n", msr
);
2069 } else if (i
== m
->nr
) {
2071 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2072 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2075 m
->guest
[i
].index
= msr
;
2076 m
->guest
[i
].value
= guest_val
;
2077 m
->host
[i
].index
= msr
;
2078 m
->host
[i
].value
= host_val
;
2081 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2083 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2084 u64 ignore_bits
= 0;
2088 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2089 * host CPUID is more efficient than testing guest CPUID
2090 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2092 if (boot_cpu_has(X86_FEATURE_SMEP
))
2093 guest_efer
|= EFER_NX
;
2094 else if (!(guest_efer
& EFER_NX
))
2095 ignore_bits
|= EFER_NX
;
2099 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2101 ignore_bits
|= EFER_SCE
;
2102 #ifdef CONFIG_X86_64
2103 ignore_bits
|= EFER_LMA
| EFER_LME
;
2104 /* SCE is meaningful only in long mode on Intel */
2105 if (guest_efer
& EFER_LMA
)
2106 ignore_bits
&= ~(u64
)EFER_SCE
;
2109 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2112 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2113 * On CPUs that support "load IA32_EFER", always switch EFER
2114 * atomically, since it's faster than switching it manually.
2116 if (cpu_has_load_ia32_efer
||
2117 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2118 if (!(guest_efer
& EFER_LMA
))
2119 guest_efer
&= ~EFER_LME
;
2120 if (guest_efer
!= host_efer
)
2121 add_atomic_switch_msr(vmx
, MSR_EFER
,
2122 guest_efer
, host_efer
);
2125 guest_efer
&= ~ignore_bits
;
2126 guest_efer
|= host_efer
& ignore_bits
;
2128 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2129 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2135 #ifdef CONFIG_X86_32
2137 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2138 * VMCS rather than the segment table. KVM uses this helper to figure
2139 * out the current bases to poke them into the VMCS before entry.
2141 static unsigned long segment_base(u16 selector
)
2143 struct desc_struct
*table
;
2146 if (!(selector
& ~SEGMENT_RPL_MASK
))
2149 table
= get_current_gdt_ro();
2151 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2152 u16 ldt_selector
= kvm_read_ldt();
2154 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2157 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2159 v
= get_desc_base(&table
[selector
>> 3]);
2164 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2166 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2169 if (vmx
->host_state
.loaded
)
2172 vmx
->host_state
.loaded
= 1;
2174 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2175 * allow segment selectors with cpl > 0 or ti == 1.
2177 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2178 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2179 savesegment(fs
, vmx
->host_state
.fs_sel
);
2180 if (!(vmx
->host_state
.fs_sel
& 7)) {
2181 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2182 vmx
->host_state
.fs_reload_needed
= 0;
2184 vmcs_write16(HOST_FS_SELECTOR
, 0);
2185 vmx
->host_state
.fs_reload_needed
= 1;
2187 savesegment(gs
, vmx
->host_state
.gs_sel
);
2188 if (!(vmx
->host_state
.gs_sel
& 7))
2189 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2191 vmcs_write16(HOST_GS_SELECTOR
, 0);
2192 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2195 #ifdef CONFIG_X86_64
2196 savesegment(ds
, vmx
->host_state
.ds_sel
);
2197 savesegment(es
, vmx
->host_state
.es_sel
);
2200 #ifdef CONFIG_X86_64
2201 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2202 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2204 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2205 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2208 #ifdef CONFIG_X86_64
2209 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2210 if (is_long_mode(&vmx
->vcpu
))
2211 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2213 if (boot_cpu_has(X86_FEATURE_MPX
))
2214 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2215 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2216 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2217 vmx
->guest_msrs
[i
].data
,
2218 vmx
->guest_msrs
[i
].mask
);
2221 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2223 if (!vmx
->host_state
.loaded
)
2226 ++vmx
->vcpu
.stat
.host_state_reload
;
2227 vmx
->host_state
.loaded
= 0;
2228 #ifdef CONFIG_X86_64
2229 if (is_long_mode(&vmx
->vcpu
))
2230 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2232 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2233 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2234 #ifdef CONFIG_X86_64
2235 load_gs_index(vmx
->host_state
.gs_sel
);
2237 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2240 if (vmx
->host_state
.fs_reload_needed
)
2241 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2242 #ifdef CONFIG_X86_64
2243 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2244 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2245 loadsegment(es
, vmx
->host_state
.es_sel
);
2248 invalidate_tss_limit();
2249 #ifdef CONFIG_X86_64
2250 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2252 if (vmx
->host_state
.msr_host_bndcfgs
)
2253 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2254 load_fixmap_gdt(raw_smp_processor_id());
2257 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2260 __vmx_load_host_state(vmx
);
2264 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2266 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2267 struct pi_desc old
, new;
2271 * In case of hot-plug or hot-unplug, we may have to undo
2272 * vmx_vcpu_pi_put even if there is no assigned device. And we
2273 * always keep PI.NDST up to date for simplicity: it makes the
2274 * code easier, and CPU migration is not a fast path.
2276 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2280 * First handle the simple case where no cmpxchg is necessary; just
2281 * allow posting non-urgent interrupts.
2283 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2284 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2285 * expects the VCPU to be on the blocked_vcpu_list that matches
2288 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2290 pi_clear_sn(pi_desc
);
2294 /* The full case. */
2296 old
.control
= new.control
= pi_desc
->control
;
2298 dest
= cpu_physical_id(cpu
);
2300 if (x2apic_enabled())
2303 new.ndst
= (dest
<< 8) & 0xFF00;
2306 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2307 new.control
) != old
.control
);
2310 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2312 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2313 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2317 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2318 * vcpu mutex is already taken.
2320 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2322 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2323 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2325 if (!already_loaded
) {
2326 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2327 local_irq_disable();
2328 crash_disable_local_vmclear(cpu
);
2331 * Read loaded_vmcs->cpu should be before fetching
2332 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2333 * See the comments in __loaded_vmcs_clear().
2337 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2338 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2339 crash_enable_local_vmclear(cpu
);
2343 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2344 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2345 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2346 indirect_branch_prediction_barrier();
2349 if (!already_loaded
) {
2350 void *gdt
= get_current_gdt_ro();
2351 unsigned long sysenter_esp
;
2353 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2356 * Linux uses per-cpu TSS and GDT, so set these when switching
2357 * processors. See 22.2.4.
2359 vmcs_writel(HOST_TR_BASE
,
2360 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
2361 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2364 * VM exits change the host TR limit to 0x67 after a VM
2365 * exit. This is okay, since 0x67 covers everything except
2366 * the IO bitmap and have have code to handle the IO bitmap
2367 * being lost after a VM exit.
2369 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2371 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2372 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2374 vmx
->loaded_vmcs
->cpu
= cpu
;
2377 /* Setup TSC multiplier */
2378 if (kvm_has_tsc_control
&&
2379 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2380 decache_tsc_multiplier(vmx
);
2382 vmx_vcpu_pi_load(vcpu
, cpu
);
2383 vmx
->host_pkru
= read_pkru();
2386 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2388 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2390 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2391 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2392 !kvm_vcpu_apicv_active(vcpu
))
2395 /* Set SN when the vCPU is preempted */
2396 if (vcpu
->preempted
)
2400 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2402 vmx_vcpu_pi_put(vcpu
);
2404 __vmx_load_host_state(to_vmx(vcpu
));
2407 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2409 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2412 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2415 * Return the cr0 value that a nested guest would read. This is a combination
2416 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2417 * its hypervisor (cr0_read_shadow).
2419 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2421 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2422 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2424 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2426 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2427 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2430 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2432 unsigned long rflags
, save_rflags
;
2434 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2435 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2436 rflags
= vmcs_readl(GUEST_RFLAGS
);
2437 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2438 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2439 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2440 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2442 to_vmx(vcpu
)->rflags
= rflags
;
2444 return to_vmx(vcpu
)->rflags
;
2447 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2449 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2451 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2452 to_vmx(vcpu
)->rflags
= rflags
;
2453 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2454 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2455 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2457 vmcs_writel(GUEST_RFLAGS
, rflags
);
2459 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2460 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2463 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2465 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2468 if (interruptibility
& GUEST_INTR_STATE_STI
)
2469 ret
|= KVM_X86_SHADOW_INT_STI
;
2470 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2471 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2476 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2478 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2479 u32 interruptibility
= interruptibility_old
;
2481 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2483 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2484 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2485 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2486 interruptibility
|= GUEST_INTR_STATE_STI
;
2488 if ((interruptibility
!= interruptibility_old
))
2489 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2492 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2496 rip
= kvm_rip_read(vcpu
);
2497 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2498 kvm_rip_write(vcpu
, rip
);
2500 /* skipping an emulated instruction also counts */
2501 vmx_set_interrupt_shadow(vcpu
, 0);
2504 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2505 unsigned long exit_qual
)
2507 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2508 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2509 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2511 if (vcpu
->arch
.exception
.has_error_code
) {
2512 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2513 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2516 if (kvm_exception_is_soft(nr
))
2517 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2519 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2521 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2522 vmx_get_nmi_mask(vcpu
))
2523 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2525 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2529 * KVM wants to inject page-faults which it got to the guest. This function
2530 * checks whether in a nested guest, we need to inject them to L1 or L2.
2532 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
2534 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2535 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2537 if (nr
== PF_VECTOR
) {
2538 if (vcpu
->arch
.exception
.nested_apf
) {
2539 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
2543 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2544 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2545 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2546 * can be written only when inject_pending_event runs. This should be
2547 * conditional on a new capability---if the capability is disabled,
2548 * kvm_multiple_exception would write the ancillary information to
2549 * CR2 or DR6, for backwards ABI-compatibility.
2551 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2552 vcpu
->arch
.exception
.error_code
)) {
2553 *exit_qual
= vcpu
->arch
.cr2
;
2557 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2558 if (nr
== DB_VECTOR
)
2559 *exit_qual
= vcpu
->arch
.dr6
;
2569 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2571 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2572 unsigned nr
= vcpu
->arch
.exception
.nr
;
2573 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2574 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2575 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2577 if (has_error_code
) {
2578 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2579 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2582 if (vmx
->rmode
.vm86_active
) {
2584 if (kvm_exception_is_soft(nr
))
2585 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2586 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2587 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2591 if (kvm_exception_is_soft(nr
)) {
2592 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2593 vmx
->vcpu
.arch
.event_exit_inst_len
);
2594 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2596 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2598 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2601 static bool vmx_rdtscp_supported(void)
2603 return cpu_has_vmx_rdtscp();
2606 static bool vmx_invpcid_supported(void)
2608 return cpu_has_vmx_invpcid() && enable_ept
;
2612 * Swap MSR entry in host/guest MSR entry array.
2614 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2616 struct shared_msr_entry tmp
;
2618 tmp
= vmx
->guest_msrs
[to
];
2619 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2620 vmx
->guest_msrs
[from
] = tmp
;
2624 * Set up the vmcs to automatically save and restore system
2625 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2626 * mode, as fiddling with msrs is very expensive.
2628 static void setup_msrs(struct vcpu_vmx
*vmx
)
2630 int save_nmsrs
, index
;
2633 #ifdef CONFIG_X86_64
2634 if (is_long_mode(&vmx
->vcpu
)) {
2635 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2637 move_msr_up(vmx
, index
, save_nmsrs
++);
2638 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2640 move_msr_up(vmx
, index
, save_nmsrs
++);
2641 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2643 move_msr_up(vmx
, index
, save_nmsrs
++);
2644 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2645 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2646 move_msr_up(vmx
, index
, save_nmsrs
++);
2648 * MSR_STAR is only needed on long mode guests, and only
2649 * if efer.sce is enabled.
2651 index
= __find_msr_index(vmx
, MSR_STAR
);
2652 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2653 move_msr_up(vmx
, index
, save_nmsrs
++);
2656 index
= __find_msr_index(vmx
, MSR_EFER
);
2657 if (index
>= 0 && update_transition_efer(vmx
, index
))
2658 move_msr_up(vmx
, index
, save_nmsrs
++);
2660 vmx
->save_nmsrs
= save_nmsrs
;
2662 if (cpu_has_vmx_msr_bitmap())
2663 vmx_update_msr_bitmap(&vmx
->vcpu
);
2667 * reads and returns guest's timestamp counter "register"
2668 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2669 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2671 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2673 u64 host_tsc
, tsc_offset
;
2676 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2677 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2681 * writes 'offset' into guest's timestamp counter offset register
2683 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2685 if (is_guest_mode(vcpu
)) {
2687 * We're here if L1 chose not to trap WRMSR to TSC. According
2688 * to the spec, this should set L1's TSC; The offset that L1
2689 * set for L2 remains unchanged, and still needs to be added
2690 * to the newly set TSC to get L2's TSC.
2692 struct vmcs12
*vmcs12
;
2693 /* recalculate vmcs02.TSC_OFFSET: */
2694 vmcs12
= get_vmcs12(vcpu
);
2695 vmcs_write64(TSC_OFFSET
, offset
+
2696 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2697 vmcs12
->tsc_offset
: 0));
2699 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2700 vmcs_read64(TSC_OFFSET
), offset
);
2701 vmcs_write64(TSC_OFFSET
, offset
);
2706 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2707 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2708 * all guests if the "nested" module option is off, and can also be disabled
2709 * for a single guest by disabling its VMX cpuid bit.
2711 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2713 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2717 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2718 * returned for the various VMX controls MSRs when nested VMX is enabled.
2719 * The same values should also be used to verify that vmcs12 control fields are
2720 * valid during nested entry from L1 to L2.
2721 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2722 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2723 * bit in the high half is on if the corresponding bit in the control field
2724 * may be on. See also vmx_control_verify().
2726 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2729 * Note that as a general rule, the high half of the MSRs (bits in
2730 * the control fields which may be 1) should be initialized by the
2731 * intersection of the underlying hardware's MSR (i.e., features which
2732 * can be supported) and the list of features we want to expose -
2733 * because they are known to be properly supported in our code.
2734 * Also, usually, the low half of the MSRs (bits which must be 1) can
2735 * be set to 0, meaning that L1 may turn off any of these bits. The
2736 * reason is that if one of these bits is necessary, it will appear
2737 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2738 * fields of vmcs01 and vmcs02, will turn these bits off - and
2739 * nested_vmx_exit_reflected() will not pass related exits to L1.
2740 * These rules have exceptions below.
2743 /* pin-based controls */
2744 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2745 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2746 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2747 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2748 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2749 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2750 PIN_BASED_EXT_INTR_MASK
|
2751 PIN_BASED_NMI_EXITING
|
2752 PIN_BASED_VIRTUAL_NMIS
;
2753 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2754 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2755 PIN_BASED_VMX_PREEMPTION_TIMER
;
2756 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2757 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2758 PIN_BASED_POSTED_INTR
;
2761 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2762 vmx
->nested
.nested_vmx_exit_ctls_low
,
2763 vmx
->nested
.nested_vmx_exit_ctls_high
);
2764 vmx
->nested
.nested_vmx_exit_ctls_low
=
2765 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2767 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2768 #ifdef CONFIG_X86_64
2769 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2771 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2772 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2773 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2774 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2775 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2777 if (kvm_mpx_supported())
2778 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2780 /* We support free control of debug control saving. */
2781 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2783 /* entry controls */
2784 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2785 vmx
->nested
.nested_vmx_entry_ctls_low
,
2786 vmx
->nested
.nested_vmx_entry_ctls_high
);
2787 vmx
->nested
.nested_vmx_entry_ctls_low
=
2788 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2789 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2790 #ifdef CONFIG_X86_64
2791 VM_ENTRY_IA32E_MODE
|
2793 VM_ENTRY_LOAD_IA32_PAT
;
2794 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2795 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2796 if (kvm_mpx_supported())
2797 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2799 /* We support free control of debug control loading. */
2800 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2802 /* cpu-based controls */
2803 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2804 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2805 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2806 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2807 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2808 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2809 CPU_BASED_VIRTUAL_INTR_PENDING
|
2810 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2811 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2812 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2813 CPU_BASED_CR3_STORE_EXITING
|
2814 #ifdef CONFIG_X86_64
2815 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2817 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2818 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2819 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2820 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2821 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2823 * We can allow some features even when not supported by the
2824 * hardware. For example, L1 can specify an MSR bitmap - and we
2825 * can use it to avoid exits to L1 - even when L0 runs L2
2826 * without MSR bitmaps.
2828 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2829 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2830 CPU_BASED_USE_MSR_BITMAPS
;
2832 /* We support free control of CR3 access interception. */
2833 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2834 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2837 * secondary cpu-based controls. Do not include those that
2838 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2840 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2841 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2842 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2843 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2844 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2845 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2846 SECONDARY_EXEC_DESC
|
2847 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2848 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2849 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2850 SECONDARY_EXEC_WBINVD_EXITING
;
2853 /* nested EPT: emulate EPT also to L1 */
2854 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2855 SECONDARY_EXEC_ENABLE_EPT
;
2856 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2857 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2858 if (cpu_has_vmx_ept_execute_only())
2859 vmx
->nested
.nested_vmx_ept_caps
|=
2860 VMX_EPT_EXECUTE_ONLY_BIT
;
2861 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2862 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2863 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2864 VMX_EPT_1GB_PAGE_BIT
;
2865 if (enable_ept_ad_bits
) {
2866 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2867 SECONDARY_EXEC_ENABLE_PML
;
2868 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2872 if (cpu_has_vmx_vmfunc()) {
2873 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2874 SECONDARY_EXEC_ENABLE_VMFUNC
;
2876 * Advertise EPTP switching unconditionally
2877 * since we emulate it
2880 vmx
->nested
.nested_vmx_vmfunc_controls
=
2881 VMX_VMFUNC_EPTP_SWITCHING
;
2885 * Old versions of KVM use the single-context version without
2886 * checking for support, so declare that it is supported even
2887 * though it is treated as global context. The alternative is
2888 * not failing the single-context invvpid, and it is worse.
2891 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2892 SECONDARY_EXEC_ENABLE_VPID
;
2893 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2894 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2897 if (enable_unrestricted_guest
)
2898 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2899 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2901 /* miscellaneous data */
2902 rdmsr(MSR_IA32_VMX_MISC
,
2903 vmx
->nested
.nested_vmx_misc_low
,
2904 vmx
->nested
.nested_vmx_misc_high
);
2905 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2906 vmx
->nested
.nested_vmx_misc_low
|=
2907 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2908 VMX_MISC_ACTIVITY_HLT
;
2909 vmx
->nested
.nested_vmx_misc_high
= 0;
2912 * This MSR reports some information about VMX support. We
2913 * should return information about the VMX we emulate for the
2914 * guest, and the VMCS structure we give it - not about the
2915 * VMX support of the underlying hardware.
2917 vmx
->nested
.nested_vmx_basic
=
2919 VMX_BASIC_TRUE_CTLS
|
2920 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2921 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2923 if (cpu_has_vmx_basic_inout())
2924 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2927 * These MSRs specify bits which the guest must keep fixed on
2928 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2929 * We picked the standard core2 setting.
2931 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2932 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2933 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2934 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2936 /* These MSRs specify bits which the guest must keep fixed off. */
2937 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2938 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2940 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2941 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2945 * if fixed0[i] == 1: val[i] must be 1
2946 * if fixed1[i] == 0: val[i] must be 0
2948 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2950 return ((val
& fixed1
) | fixed0
) == val
;
2953 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2955 return fixed_bits_valid(control
, low
, high
);
2958 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2960 return low
| ((u64
)high
<< 32);
2963 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2968 return (superset
| subset
) == superset
;
2971 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2973 const u64 feature_and_reserved
=
2974 /* feature (except bit 48; see below) */
2975 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2977 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2978 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2980 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2984 * KVM does not emulate a version of VMX that constrains physical
2985 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2987 if (data
& BIT_ULL(48))
2990 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2991 vmx_basic_vmcs_revision_id(data
))
2994 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2997 vmx
->nested
.nested_vmx_basic
= data
;
3002 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3007 switch (msr_index
) {
3008 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3009 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
3010 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
3012 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3013 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
3014 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
3016 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3017 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
3018 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
3020 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3021 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
3022 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
3024 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3025 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
3026 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
3032 supported
= vmx_control_msr(*lowp
, *highp
);
3034 /* Check must-be-1 bits are still 1. */
3035 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3038 /* Check must-be-0 bits are still 0. */
3039 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3043 *highp
= data
>> 32;
3047 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3049 const u64 feature_and_reserved_bits
=
3051 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3052 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3054 GENMASK_ULL(13, 9) | BIT_ULL(31);
3057 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3058 vmx
->nested
.nested_vmx_misc_high
);
3060 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3063 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3064 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3065 vmx_misc_preemption_timer_rate(data
) !=
3066 vmx_misc_preemption_timer_rate(vmx_misc
))
3069 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3072 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3075 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3078 vmx
->nested
.nested_vmx_misc_low
= data
;
3079 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3083 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3085 u64 vmx_ept_vpid_cap
;
3087 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3088 vmx
->nested
.nested_vmx_vpid_caps
);
3090 /* Every bit is either reserved or a feature bit. */
3091 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3094 vmx
->nested
.nested_vmx_ept_caps
= data
;
3095 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3099 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3103 switch (msr_index
) {
3104 case MSR_IA32_VMX_CR0_FIXED0
:
3105 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3107 case MSR_IA32_VMX_CR4_FIXED0
:
3108 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3115 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3116 * must be 1 in the restored value.
3118 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3126 * Called when userspace is restoring VMX MSRs.
3128 * Returns 0 on success, non-0 otherwise.
3130 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3132 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3134 switch (msr_index
) {
3135 case MSR_IA32_VMX_BASIC
:
3136 return vmx_restore_vmx_basic(vmx
, data
);
3137 case MSR_IA32_VMX_PINBASED_CTLS
:
3138 case MSR_IA32_VMX_PROCBASED_CTLS
:
3139 case MSR_IA32_VMX_EXIT_CTLS
:
3140 case MSR_IA32_VMX_ENTRY_CTLS
:
3142 * The "non-true" VMX capability MSRs are generated from the
3143 * "true" MSRs, so we do not support restoring them directly.
3145 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3146 * should restore the "true" MSRs with the must-be-1 bits
3147 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3148 * DEFAULT SETTINGS".
3151 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3152 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3153 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3154 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3155 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3156 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3157 case MSR_IA32_VMX_MISC
:
3158 return vmx_restore_vmx_misc(vmx
, data
);
3159 case MSR_IA32_VMX_CR0_FIXED0
:
3160 case MSR_IA32_VMX_CR4_FIXED0
:
3161 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3162 case MSR_IA32_VMX_CR0_FIXED1
:
3163 case MSR_IA32_VMX_CR4_FIXED1
:
3165 * These MSRs are generated based on the vCPU's CPUID, so we
3166 * do not support restoring them directly.
3169 case MSR_IA32_VMX_EPT_VPID_CAP
:
3170 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3171 case MSR_IA32_VMX_VMCS_ENUM
:
3172 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3176 * The rest of the VMX capability MSRs do not support restore.
3182 /* Returns 0 on success, non-0 otherwise. */
3183 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3185 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3187 switch (msr_index
) {
3188 case MSR_IA32_VMX_BASIC
:
3189 *pdata
= vmx
->nested
.nested_vmx_basic
;
3191 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3192 case MSR_IA32_VMX_PINBASED_CTLS
:
3193 *pdata
= vmx_control_msr(
3194 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3195 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3196 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3197 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3199 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3200 case MSR_IA32_VMX_PROCBASED_CTLS
:
3201 *pdata
= vmx_control_msr(
3202 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3203 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3204 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3205 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3207 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3208 case MSR_IA32_VMX_EXIT_CTLS
:
3209 *pdata
= vmx_control_msr(
3210 vmx
->nested
.nested_vmx_exit_ctls_low
,
3211 vmx
->nested
.nested_vmx_exit_ctls_high
);
3212 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3213 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3215 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3216 case MSR_IA32_VMX_ENTRY_CTLS
:
3217 *pdata
= vmx_control_msr(
3218 vmx
->nested
.nested_vmx_entry_ctls_low
,
3219 vmx
->nested
.nested_vmx_entry_ctls_high
);
3220 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3221 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3223 case MSR_IA32_VMX_MISC
:
3224 *pdata
= vmx_control_msr(
3225 vmx
->nested
.nested_vmx_misc_low
,
3226 vmx
->nested
.nested_vmx_misc_high
);
3228 case MSR_IA32_VMX_CR0_FIXED0
:
3229 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3231 case MSR_IA32_VMX_CR0_FIXED1
:
3232 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3234 case MSR_IA32_VMX_CR4_FIXED0
:
3235 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3237 case MSR_IA32_VMX_CR4_FIXED1
:
3238 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3240 case MSR_IA32_VMX_VMCS_ENUM
:
3241 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3243 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3244 *pdata
= vmx_control_msr(
3245 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3246 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3248 case MSR_IA32_VMX_EPT_VPID_CAP
:
3249 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3250 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3252 case MSR_IA32_VMX_VMFUNC
:
3253 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3262 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3265 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3267 return !(val
& ~valid_bits
);
3271 * Reads an msr value (of 'msr_index') into 'pdata'.
3272 * Returns 0 on success, non-0 otherwise.
3273 * Assumes vcpu_load() was already called.
3275 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3277 struct shared_msr_entry
*msr
;
3279 switch (msr_info
->index
) {
3280 #ifdef CONFIG_X86_64
3282 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3285 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3287 case MSR_KERNEL_GS_BASE
:
3288 vmx_load_host_state(to_vmx(vcpu
));
3289 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3293 return kvm_get_msr_common(vcpu
, msr_info
);
3295 msr_info
->data
= guest_read_tsc(vcpu
);
3297 case MSR_IA32_SPEC_CTRL
:
3298 if (!msr_info
->host_initiated
&&
3299 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
3302 msr_info
->data
= to_vmx(vcpu
)->spec_ctrl
;
3304 case MSR_IA32_ARCH_CAPABILITIES
:
3305 if (!msr_info
->host_initiated
&&
3306 !guest_cpuid_has(vcpu
, X86_FEATURE_ARCH_CAPABILITIES
))
3308 msr_info
->data
= to_vmx(vcpu
)->arch_capabilities
;
3310 case MSR_IA32_SYSENTER_CS
:
3311 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3313 case MSR_IA32_SYSENTER_EIP
:
3314 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3316 case MSR_IA32_SYSENTER_ESP
:
3317 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3319 case MSR_IA32_BNDCFGS
:
3320 if (!kvm_mpx_supported() ||
3321 (!msr_info
->host_initiated
&&
3322 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3324 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3326 case MSR_IA32_MCG_EXT_CTL
:
3327 if (!msr_info
->host_initiated
&&
3328 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3329 FEATURE_CONTROL_LMCE
))
3331 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3333 case MSR_IA32_FEATURE_CONTROL
:
3334 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3336 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3337 if (!nested_vmx_allowed(vcpu
))
3339 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3341 if (!vmx_xsaves_supported())
3343 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3346 if (!msr_info
->host_initiated
&&
3347 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3349 /* Otherwise falls through */
3351 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3353 msr_info
->data
= msr
->data
;
3356 return kvm_get_msr_common(vcpu
, msr_info
);
3362 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3365 * Writes msr value into into the appropriate "register".
3366 * Returns 0 on success, non-0 otherwise.
3367 * Assumes vcpu_load() was already called.
3369 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3371 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3372 struct shared_msr_entry
*msr
;
3374 u32 msr_index
= msr_info
->index
;
3375 u64 data
= msr_info
->data
;
3377 switch (msr_index
) {
3379 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3381 #ifdef CONFIG_X86_64
3383 vmx_segment_cache_clear(vmx
);
3384 vmcs_writel(GUEST_FS_BASE
, data
);
3387 vmx_segment_cache_clear(vmx
);
3388 vmcs_writel(GUEST_GS_BASE
, data
);
3390 case MSR_KERNEL_GS_BASE
:
3391 vmx_load_host_state(vmx
);
3392 vmx
->msr_guest_kernel_gs_base
= data
;
3395 case MSR_IA32_SYSENTER_CS
:
3396 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3398 case MSR_IA32_SYSENTER_EIP
:
3399 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3401 case MSR_IA32_SYSENTER_ESP
:
3402 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3404 case MSR_IA32_BNDCFGS
:
3405 if (!kvm_mpx_supported() ||
3406 (!msr_info
->host_initiated
&&
3407 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3409 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
3410 (data
& MSR_IA32_BNDCFGS_RSVD
))
3412 vmcs_write64(GUEST_BNDCFGS
, data
);
3415 kvm_write_tsc(vcpu
, msr_info
);
3417 case MSR_IA32_SPEC_CTRL
:
3418 if (!msr_info
->host_initiated
&&
3419 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
3422 /* The STIBP bit doesn't fault even if it's not advertised */
3423 if (data
& ~(SPEC_CTRL_IBRS
| SPEC_CTRL_STIBP
| SPEC_CTRL_SSBD
))
3426 vmx
->spec_ctrl
= data
;
3433 * When it's written (to non-zero) for the first time, pass
3437 * The handling of the MSR bitmap for L2 guests is done in
3438 * nested_vmx_merge_msr_bitmap. We should not touch the
3439 * vmcs02.msr_bitmap here since it gets completely overwritten
3440 * in the merging. We update the vmcs01 here for L1 as well
3441 * since it will end up touching the MSR anyway now.
3443 vmx_disable_intercept_for_msr(vmx
->vmcs01
.msr_bitmap
,
3447 case MSR_IA32_PRED_CMD
:
3448 if (!msr_info
->host_initiated
&&
3449 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
3452 if (data
& ~PRED_CMD_IBPB
)
3458 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
3462 * When it's written (to non-zero) for the first time, pass
3466 * The handling of the MSR bitmap for L2 guests is done in
3467 * nested_vmx_merge_msr_bitmap. We should not touch the
3468 * vmcs02.msr_bitmap here since it gets completely overwritten
3471 vmx_disable_intercept_for_msr(vmx
->vmcs01
.msr_bitmap
, MSR_IA32_PRED_CMD
,
3474 case MSR_IA32_ARCH_CAPABILITIES
:
3475 if (!msr_info
->host_initiated
)
3477 vmx
->arch_capabilities
= data
;
3479 case MSR_IA32_CR_PAT
:
3480 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3481 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3483 vmcs_write64(GUEST_IA32_PAT
, data
);
3484 vcpu
->arch
.pat
= data
;
3487 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3489 case MSR_IA32_TSC_ADJUST
:
3490 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3492 case MSR_IA32_MCG_EXT_CTL
:
3493 if ((!msr_info
->host_initiated
&&
3494 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3495 FEATURE_CONTROL_LMCE
)) ||
3496 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3498 vcpu
->arch
.mcg_ext_ctl
= data
;
3500 case MSR_IA32_FEATURE_CONTROL
:
3501 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3502 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3503 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3505 vmx
->msr_ia32_feature_control
= data
;
3506 if (msr_info
->host_initiated
&& data
== 0)
3507 vmx_leave_nested(vcpu
);
3509 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3510 if (!msr_info
->host_initiated
)
3511 return 1; /* they are read-only */
3512 if (!nested_vmx_allowed(vcpu
))
3514 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3516 if (!vmx_xsaves_supported())
3519 * The only supported bit as of Skylake is bit 8, but
3520 * it is not supported on KVM.
3524 vcpu
->arch
.ia32_xss
= data
;
3525 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3526 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3527 vcpu
->arch
.ia32_xss
, host_xss
);
3529 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3532 if (!msr_info
->host_initiated
&&
3533 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3535 /* Check reserved bit, higher 32 bits should be zero */
3536 if ((data
>> 32) != 0)
3538 /* Otherwise falls through */
3540 msr
= find_msr_entry(vmx
, msr_index
);
3542 u64 old_msr_data
= msr
->data
;
3544 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3546 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3550 msr
->data
= old_msr_data
;
3554 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3560 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3562 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3565 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3568 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3570 case VCPU_EXREG_PDPTR
:
3572 ept_save_pdptrs(vcpu
);
3579 static __init
int cpu_has_kvm_support(void)
3581 return cpu_has_vmx();
3584 static __init
int vmx_disabled_by_bios(void)
3588 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3589 if (msr
& FEATURE_CONTROL_LOCKED
) {
3590 /* launched w/ TXT and VMX disabled */
3591 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3594 /* launched w/o TXT and VMX only enabled w/ TXT */
3595 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3596 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3597 && !tboot_enabled()) {
3598 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3599 "activate TXT before enabling KVM\n");
3602 /* launched w/o TXT and VMX disabled */
3603 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3604 && !tboot_enabled())
3611 static void kvm_cpu_vmxon(u64 addr
)
3613 cr4_set_bits(X86_CR4_VMXE
);
3614 intel_pt_handle_vmx(1);
3616 asm volatile (ASM_VMX_VMXON_RAX
3617 : : "a"(&addr
), "m"(addr
)
3621 static int hardware_enable(void)
3623 int cpu
= raw_smp_processor_id();
3624 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3627 if (cr4_read_shadow() & X86_CR4_VMXE
)
3630 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3631 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3632 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3635 * Now we can enable the vmclear operation in kdump
3636 * since the loaded_vmcss_on_cpu list on this cpu
3637 * has been initialized.
3639 * Though the cpu is not in VMX operation now, there
3640 * is no problem to enable the vmclear operation
3641 * for the loaded_vmcss_on_cpu list is empty!
3643 crash_enable_local_vmclear(cpu
);
3645 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3647 test_bits
= FEATURE_CONTROL_LOCKED
;
3648 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3649 if (tboot_enabled())
3650 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3652 if ((old
& test_bits
) != test_bits
) {
3653 /* enable and lock */
3654 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3656 kvm_cpu_vmxon(phys_addr
);
3663 static void vmclear_local_loaded_vmcss(void)
3665 int cpu
= raw_smp_processor_id();
3666 struct loaded_vmcs
*v
, *n
;
3668 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3669 loaded_vmcss_on_cpu_link
)
3670 __loaded_vmcs_clear(v
);
3674 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3677 static void kvm_cpu_vmxoff(void)
3679 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3681 intel_pt_handle_vmx(0);
3682 cr4_clear_bits(X86_CR4_VMXE
);
3685 static void hardware_disable(void)
3687 vmclear_local_loaded_vmcss();
3691 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3692 u32 msr
, u32
*result
)
3694 u32 vmx_msr_low
, vmx_msr_high
;
3695 u32 ctl
= ctl_min
| ctl_opt
;
3697 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3699 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3700 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3702 /* Ensure minimum (required) set of control bits are supported. */
3710 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3712 u32 vmx_msr_low
, vmx_msr_high
;
3714 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3715 return vmx_msr_high
& ctl
;
3718 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3720 u32 vmx_msr_low
, vmx_msr_high
;
3721 u32 min
, opt
, min2
, opt2
;
3722 u32 _pin_based_exec_control
= 0;
3723 u32 _cpu_based_exec_control
= 0;
3724 u32 _cpu_based_2nd_exec_control
= 0;
3725 u32 _vmexit_control
= 0;
3726 u32 _vmentry_control
= 0;
3728 min
= CPU_BASED_HLT_EXITING
|
3729 #ifdef CONFIG_X86_64
3730 CPU_BASED_CR8_LOAD_EXITING
|
3731 CPU_BASED_CR8_STORE_EXITING
|
3733 CPU_BASED_CR3_LOAD_EXITING
|
3734 CPU_BASED_CR3_STORE_EXITING
|
3735 CPU_BASED_USE_IO_BITMAPS
|
3736 CPU_BASED_MOV_DR_EXITING
|
3737 CPU_BASED_USE_TSC_OFFSETING
|
3738 CPU_BASED_INVLPG_EXITING
|
3739 CPU_BASED_RDPMC_EXITING
;
3741 if (!kvm_mwait_in_guest())
3742 min
|= CPU_BASED_MWAIT_EXITING
|
3743 CPU_BASED_MONITOR_EXITING
;
3745 opt
= CPU_BASED_TPR_SHADOW
|
3746 CPU_BASED_USE_MSR_BITMAPS
|
3747 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3748 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3749 &_cpu_based_exec_control
) < 0)
3751 #ifdef CONFIG_X86_64
3752 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3753 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3754 ~CPU_BASED_CR8_STORE_EXITING
;
3756 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3758 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3759 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3760 SECONDARY_EXEC_WBINVD_EXITING
|
3761 SECONDARY_EXEC_ENABLE_VPID
|
3762 SECONDARY_EXEC_ENABLE_EPT
|
3763 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3764 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3765 SECONDARY_EXEC_RDTSCP
|
3766 SECONDARY_EXEC_ENABLE_INVPCID
|
3767 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3768 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3769 SECONDARY_EXEC_SHADOW_VMCS
|
3770 SECONDARY_EXEC_XSAVES
|
3771 SECONDARY_EXEC_RDSEED_EXITING
|
3772 SECONDARY_EXEC_RDRAND_EXITING
|
3773 SECONDARY_EXEC_ENABLE_PML
|
3774 SECONDARY_EXEC_TSC_SCALING
|
3775 SECONDARY_EXEC_ENABLE_VMFUNC
;
3776 if (adjust_vmx_controls(min2
, opt2
,
3777 MSR_IA32_VMX_PROCBASED_CTLS2
,
3778 &_cpu_based_2nd_exec_control
) < 0)
3781 #ifndef CONFIG_X86_64
3782 if (!(_cpu_based_2nd_exec_control
&
3783 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3784 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3787 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3788 _cpu_based_2nd_exec_control
&= ~(
3789 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3790 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3791 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3793 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP
,
3794 &vmx_capability
.ept
, &vmx_capability
.vpid
);
3796 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3797 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3799 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3800 CPU_BASED_CR3_STORE_EXITING
|
3801 CPU_BASED_INVLPG_EXITING
);
3802 } else if (vmx_capability
.ept
) {
3803 vmx_capability
.ept
= 0;
3804 pr_warn_once("EPT CAP should not exist if not support "
3805 "1-setting enable EPT VM-execution control\n");
3807 if (!(_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_VPID
) &&
3808 vmx_capability
.vpid
) {
3809 vmx_capability
.vpid
= 0;
3810 pr_warn_once("VPID CAP should not exist if not support "
3811 "1-setting enable VPID VM-execution control\n");
3814 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3815 #ifdef CONFIG_X86_64
3816 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3818 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3819 VM_EXIT_CLEAR_BNDCFGS
;
3820 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3821 &_vmexit_control
) < 0)
3824 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3825 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3826 PIN_BASED_VMX_PREEMPTION_TIMER
;
3827 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3828 &_pin_based_exec_control
) < 0)
3831 if (cpu_has_broken_vmx_preemption_timer())
3832 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3833 if (!(_cpu_based_2nd_exec_control
&
3834 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3835 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3837 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3838 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3839 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3840 &_vmentry_control
) < 0)
3843 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3845 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3846 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3849 #ifdef CONFIG_X86_64
3850 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3851 if (vmx_msr_high
& (1u<<16))
3855 /* Require Write-Back (WB) memory type for VMCS accesses. */
3856 if (((vmx_msr_high
>> 18) & 15) != 6)
3859 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3860 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3861 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3862 vmcs_conf
->revision_id
= vmx_msr_low
;
3864 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3865 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3866 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3867 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3868 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3870 cpu_has_load_ia32_efer
=
3871 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3872 VM_ENTRY_LOAD_IA32_EFER
)
3873 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3874 VM_EXIT_LOAD_IA32_EFER
);
3876 cpu_has_load_perf_global_ctrl
=
3877 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3878 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3879 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3880 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3883 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3884 * but due to errata below it can't be used. Workaround is to use
3885 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3887 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3892 * BC86,AAY89,BD102 (model 44)
3896 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3897 switch (boot_cpu_data
.x86_model
) {
3903 cpu_has_load_perf_global_ctrl
= false;
3904 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3905 "does not work properly. Using workaround\n");
3912 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3913 rdmsrl(MSR_IA32_XSS
, host_xss
);
3918 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3920 int node
= cpu_to_node(cpu
);
3924 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3927 vmcs
= page_address(pages
);
3928 memset(vmcs
, 0, vmcs_config
.size
);
3929 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3933 static void free_vmcs(struct vmcs
*vmcs
)
3935 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3939 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3941 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3943 if (!loaded_vmcs
->vmcs
)
3945 loaded_vmcs_clear(loaded_vmcs
);
3946 free_vmcs(loaded_vmcs
->vmcs
);
3947 loaded_vmcs
->vmcs
= NULL
;
3948 if (loaded_vmcs
->msr_bitmap
)
3949 free_page((unsigned long)loaded_vmcs
->msr_bitmap
);
3950 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3953 static struct vmcs
*alloc_vmcs(void)
3955 return alloc_vmcs_cpu(raw_smp_processor_id());
3958 static int alloc_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3960 loaded_vmcs
->vmcs
= alloc_vmcs();
3961 if (!loaded_vmcs
->vmcs
)
3964 loaded_vmcs
->shadow_vmcs
= NULL
;
3965 loaded_vmcs_init(loaded_vmcs
);
3967 if (cpu_has_vmx_msr_bitmap()) {
3968 loaded_vmcs
->msr_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3969 if (!loaded_vmcs
->msr_bitmap
)
3971 memset(loaded_vmcs
->msr_bitmap
, 0xff, PAGE_SIZE
);
3976 free_loaded_vmcs(loaded_vmcs
);
3980 static void free_kvm_area(void)
3984 for_each_possible_cpu(cpu
) {
3985 free_vmcs(per_cpu(vmxarea
, cpu
));
3986 per_cpu(vmxarea
, cpu
) = NULL
;
3990 enum vmcs_field_type
{
3991 VMCS_FIELD_TYPE_U16
= 0,
3992 VMCS_FIELD_TYPE_U64
= 1,
3993 VMCS_FIELD_TYPE_U32
= 2,
3994 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3997 static inline int vmcs_field_type(unsigned long field
)
3999 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
4000 return VMCS_FIELD_TYPE_U32
;
4001 return (field
>> 13) & 0x3 ;
4004 static inline int vmcs_field_readonly(unsigned long field
)
4006 return (((field
>> 10) & 0x3) == 1);
4009 static void init_vmcs_shadow_fields(void)
4013 /* No checks for read only fields yet */
4015 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
4016 switch (shadow_read_write_fields
[i
]) {
4018 if (!kvm_mpx_supported())
4026 shadow_read_write_fields
[j
] =
4027 shadow_read_write_fields
[i
];
4030 max_shadow_read_write_fields
= j
;
4032 /* shadowed fields guest access without vmexit */
4033 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
4034 unsigned long field
= shadow_read_write_fields
[i
];
4036 clear_bit(field
, vmx_vmwrite_bitmap
);
4037 clear_bit(field
, vmx_vmread_bitmap
);
4038 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
4039 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
4040 clear_bit(field
+ 1, vmx_vmread_bitmap
);
4043 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
4044 unsigned long field
= shadow_read_only_fields
[i
];
4046 clear_bit(field
, vmx_vmread_bitmap
);
4047 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
4048 clear_bit(field
+ 1, vmx_vmread_bitmap
);
4052 static __init
int alloc_kvm_area(void)
4056 for_each_possible_cpu(cpu
) {
4059 vmcs
= alloc_vmcs_cpu(cpu
);
4065 per_cpu(vmxarea
, cpu
) = vmcs
;
4070 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
4071 struct kvm_segment
*save
)
4073 if (!emulate_invalid_guest_state
) {
4075 * CS and SS RPL should be equal during guest entry according
4076 * to VMX spec, but in reality it is not always so. Since vcpu
4077 * is in the middle of the transition from real mode to
4078 * protected mode it is safe to assume that RPL 0 is a good
4081 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
4082 save
->selector
&= ~SEGMENT_RPL_MASK
;
4083 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
4086 vmx_set_segment(vcpu
, save
, seg
);
4089 static void enter_pmode(struct kvm_vcpu
*vcpu
)
4091 unsigned long flags
;
4092 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4095 * Update real mode segment cache. It may be not up-to-date if sement
4096 * register was written while vcpu was in a guest mode.
4098 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4099 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4100 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4101 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4102 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4103 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4105 vmx
->rmode
.vm86_active
= 0;
4107 vmx_segment_cache_clear(vmx
);
4109 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4111 flags
= vmcs_readl(GUEST_RFLAGS
);
4112 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
4113 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
4114 vmcs_writel(GUEST_RFLAGS
, flags
);
4116 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
4117 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
4119 update_exception_bitmap(vcpu
);
4121 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4122 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4123 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4124 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4125 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4126 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4129 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
4131 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4132 struct kvm_segment var
= *save
;
4135 if (seg
== VCPU_SREG_CS
)
4138 if (!emulate_invalid_guest_state
) {
4139 var
.selector
= var
.base
>> 4;
4140 var
.base
= var
.base
& 0xffff0;
4150 if (save
->base
& 0xf)
4151 printk_once(KERN_WARNING
"kvm: segment base is not "
4152 "paragraph aligned when entering "
4153 "protected mode (seg=%d)", seg
);
4156 vmcs_write16(sf
->selector
, var
.selector
);
4157 vmcs_writel(sf
->base
, var
.base
);
4158 vmcs_write32(sf
->limit
, var
.limit
);
4159 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4162 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4164 unsigned long flags
;
4165 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4167 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4168 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4169 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4170 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4171 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4172 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4173 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4175 vmx
->rmode
.vm86_active
= 1;
4178 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4179 * vcpu. Warn the user that an update is overdue.
4181 if (!vcpu
->kvm
->arch
.tss_addr
)
4182 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4183 "called before entering vcpu\n");
4185 vmx_segment_cache_clear(vmx
);
4187 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4188 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4189 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4191 flags
= vmcs_readl(GUEST_RFLAGS
);
4192 vmx
->rmode
.save_rflags
= flags
;
4194 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4196 vmcs_writel(GUEST_RFLAGS
, flags
);
4197 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4198 update_exception_bitmap(vcpu
);
4200 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4201 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4202 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4203 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4204 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4205 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4207 kvm_mmu_reset_context(vcpu
);
4210 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4212 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4213 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4219 * Force kernel_gs_base reloading before EFER changes, as control
4220 * of this msr depends on is_long_mode().
4222 vmx_load_host_state(to_vmx(vcpu
));
4223 vcpu
->arch
.efer
= efer
;
4224 if (efer
& EFER_LMA
) {
4225 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4228 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4230 msr
->data
= efer
& ~EFER_LME
;
4235 #ifdef CONFIG_X86_64
4237 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4241 vmx_segment_cache_clear(to_vmx(vcpu
));
4243 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4244 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4245 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4247 vmcs_write32(GUEST_TR_AR_BYTES
,
4248 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4249 | VMX_AR_TYPE_BUSY_64_TSS
);
4251 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4254 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4256 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4257 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4262 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4265 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4267 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4269 vpid_sync_context(vpid
);
4273 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4275 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4278 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4281 vmx_flush_tlb(vcpu
);
4284 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4286 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4288 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4289 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4292 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4294 if (enable_ept
&& is_paging(vcpu
))
4295 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4296 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4299 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4301 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4303 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4304 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4307 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4309 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4311 if (!test_bit(VCPU_EXREG_PDPTR
,
4312 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4315 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4316 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4317 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4318 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4319 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4323 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4325 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4327 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4328 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4329 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4330 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4331 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4334 __set_bit(VCPU_EXREG_PDPTR
,
4335 (unsigned long *)&vcpu
->arch
.regs_avail
);
4336 __set_bit(VCPU_EXREG_PDPTR
,
4337 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4340 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4342 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4343 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4344 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4346 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4347 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4348 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4349 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4351 return fixed_bits_valid(val
, fixed0
, fixed1
);
4354 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4356 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4357 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4359 return fixed_bits_valid(val
, fixed0
, fixed1
);
4362 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4364 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4365 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4367 return fixed_bits_valid(val
, fixed0
, fixed1
);
4370 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4371 #define nested_guest_cr4_valid nested_cr4_valid
4372 #define nested_host_cr4_valid nested_cr4_valid
4374 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4376 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4378 struct kvm_vcpu
*vcpu
)
4380 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4381 vmx_decache_cr3(vcpu
);
4382 if (!(cr0
& X86_CR0_PG
)) {
4383 /* From paging/starting to nonpaging */
4384 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4385 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4386 (CPU_BASED_CR3_LOAD_EXITING
|
4387 CPU_BASED_CR3_STORE_EXITING
));
4388 vcpu
->arch
.cr0
= cr0
;
4389 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4390 } else if (!is_paging(vcpu
)) {
4391 /* From nonpaging to paging */
4392 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4393 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4394 ~(CPU_BASED_CR3_LOAD_EXITING
|
4395 CPU_BASED_CR3_STORE_EXITING
));
4396 vcpu
->arch
.cr0
= cr0
;
4397 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4400 if (!(cr0
& X86_CR0_WP
))
4401 *hw_cr0
&= ~X86_CR0_WP
;
4404 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4406 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4407 unsigned long hw_cr0
;
4409 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4410 if (enable_unrestricted_guest
)
4411 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4413 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4415 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4418 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4422 #ifdef CONFIG_X86_64
4423 if (vcpu
->arch
.efer
& EFER_LME
) {
4424 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4426 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4432 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4434 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4435 vmcs_writel(GUEST_CR0
, hw_cr0
);
4436 vcpu
->arch
.cr0
= cr0
;
4438 /* depends on vcpu->arch.cr0 to be set to a new value */
4439 vmx
->emulation_required
= emulation_required(vcpu
);
4442 static int get_ept_level(struct kvm_vcpu
*vcpu
)
4444 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
4449 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4451 u64 eptp
= VMX_EPTP_MT_WB
;
4453 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
4455 if (enable_ept_ad_bits
&&
4456 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4457 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
4458 eptp
|= (root_hpa
& PAGE_MASK
);
4463 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4465 unsigned long guest_cr3
;
4470 eptp
= construct_eptp(vcpu
, cr3
);
4471 vmcs_write64(EPT_POINTER
, eptp
);
4472 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4473 guest_cr3
= kvm_read_cr3(vcpu
);
4475 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4476 ept_load_pdptrs(vcpu
);
4479 vmx_flush_tlb(vcpu
);
4480 vmcs_writel(GUEST_CR3
, guest_cr3
);
4483 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4486 * Pass through host's Machine Check Enable value to hw_cr4, which
4487 * is in force while we are in guest mode. Do not let guests control
4488 * this bit, even if host CR4.MCE == 0.
4490 unsigned long hw_cr4
=
4491 (cr4_read_shadow() & X86_CR4_MCE
) |
4492 (cr4
& ~X86_CR4_MCE
) |
4493 (to_vmx(vcpu
)->rmode
.vm86_active
?
4494 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4496 if (cr4
& X86_CR4_VMXE
) {
4498 * To use VMXON (and later other VMX instructions), a guest
4499 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4500 * So basically the check on whether to allow nested VMX
4503 if (!nested_vmx_allowed(vcpu
))
4507 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4510 vcpu
->arch
.cr4
= cr4
;
4512 if (!is_paging(vcpu
)) {
4513 hw_cr4
&= ~X86_CR4_PAE
;
4514 hw_cr4
|= X86_CR4_PSE
;
4515 } else if (!(cr4
& X86_CR4_PAE
)) {
4516 hw_cr4
&= ~X86_CR4_PAE
;
4520 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4522 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4523 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4524 * to be manually disabled when guest switches to non-paging
4527 * If !enable_unrestricted_guest, the CPU is always running
4528 * with CR0.PG=1 and CR4 needs to be modified.
4529 * If enable_unrestricted_guest, the CPU automatically
4530 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4532 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4534 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4535 vmcs_writel(GUEST_CR4
, hw_cr4
);
4539 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4540 struct kvm_segment
*var
, int seg
)
4542 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4545 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4546 *var
= vmx
->rmode
.segs
[seg
];
4547 if (seg
== VCPU_SREG_TR
4548 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4550 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4551 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4554 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4555 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4556 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4557 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4558 var
->unusable
= (ar
>> 16) & 1;
4559 var
->type
= ar
& 15;
4560 var
->s
= (ar
>> 4) & 1;
4561 var
->dpl
= (ar
>> 5) & 3;
4563 * Some userspaces do not preserve unusable property. Since usable
4564 * segment has to be present according to VMX spec we can use present
4565 * property to amend userspace bug by making unusable segment always
4566 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4567 * segment as unusable.
4569 var
->present
= !var
->unusable
;
4570 var
->avl
= (ar
>> 12) & 1;
4571 var
->l
= (ar
>> 13) & 1;
4572 var
->db
= (ar
>> 14) & 1;
4573 var
->g
= (ar
>> 15) & 1;
4576 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4578 struct kvm_segment s
;
4580 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4581 vmx_get_segment(vcpu
, &s
, seg
);
4584 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4587 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4589 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4591 if (unlikely(vmx
->rmode
.vm86_active
))
4594 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4595 return VMX_AR_DPL(ar
);
4599 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4603 if (var
->unusable
|| !var
->present
)
4606 ar
= var
->type
& 15;
4607 ar
|= (var
->s
& 1) << 4;
4608 ar
|= (var
->dpl
& 3) << 5;
4609 ar
|= (var
->present
& 1) << 7;
4610 ar
|= (var
->avl
& 1) << 12;
4611 ar
|= (var
->l
& 1) << 13;
4612 ar
|= (var
->db
& 1) << 14;
4613 ar
|= (var
->g
& 1) << 15;
4619 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4620 struct kvm_segment
*var
, int seg
)
4622 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4623 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4625 vmx_segment_cache_clear(vmx
);
4627 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4628 vmx
->rmode
.segs
[seg
] = *var
;
4629 if (seg
== VCPU_SREG_TR
)
4630 vmcs_write16(sf
->selector
, var
->selector
);
4632 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4636 vmcs_writel(sf
->base
, var
->base
);
4637 vmcs_write32(sf
->limit
, var
->limit
);
4638 vmcs_write16(sf
->selector
, var
->selector
);
4641 * Fix the "Accessed" bit in AR field of segment registers for older
4643 * IA32 arch specifies that at the time of processor reset the
4644 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4645 * is setting it to 0 in the userland code. This causes invalid guest
4646 * state vmexit when "unrestricted guest" mode is turned on.
4647 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4648 * tree. Newer qemu binaries with that qemu fix would not need this
4651 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4652 var
->type
|= 0x1; /* Accessed */
4654 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4657 vmx
->emulation_required
= emulation_required(vcpu
);
4660 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4662 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4664 *db
= (ar
>> 14) & 1;
4665 *l
= (ar
>> 13) & 1;
4668 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4670 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4671 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4674 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4676 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4677 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4680 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4682 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4683 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4686 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4688 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4689 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4692 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4694 struct kvm_segment var
;
4697 vmx_get_segment(vcpu
, &var
, seg
);
4699 if (seg
== VCPU_SREG_CS
)
4701 ar
= vmx_segment_access_rights(&var
);
4703 if (var
.base
!= (var
.selector
<< 4))
4705 if (var
.limit
!= 0xffff)
4713 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4715 struct kvm_segment cs
;
4716 unsigned int cs_rpl
;
4718 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4719 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4723 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4727 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4728 if (cs
.dpl
> cs_rpl
)
4731 if (cs
.dpl
!= cs_rpl
)
4737 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4741 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4743 struct kvm_segment ss
;
4744 unsigned int ss_rpl
;
4746 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4747 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4751 if (ss
.type
!= 3 && ss
.type
!= 7)
4755 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4763 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4765 struct kvm_segment var
;
4768 vmx_get_segment(vcpu
, &var
, seg
);
4769 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4777 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4778 if (var
.dpl
< rpl
) /* DPL < RPL */
4782 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4788 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4790 struct kvm_segment tr
;
4792 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4796 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4798 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4806 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4808 struct kvm_segment ldtr
;
4810 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4814 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4824 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4826 struct kvm_segment cs
, ss
;
4828 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4829 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4831 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4832 (ss
.selector
& SEGMENT_RPL_MASK
));
4836 * Check if guest state is valid. Returns true if valid, false if
4838 * We assume that registers are always usable
4840 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4842 if (enable_unrestricted_guest
)
4845 /* real mode guest state checks */
4846 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4847 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4849 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4851 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4853 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4855 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4857 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4860 /* protected mode guest state checks */
4861 if (!cs_ss_rpl_check(vcpu
))
4863 if (!code_segment_valid(vcpu
))
4865 if (!stack_segment_valid(vcpu
))
4867 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4869 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4871 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4873 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4875 if (!tr_valid(vcpu
))
4877 if (!ldtr_valid(vcpu
))
4881 * - Add checks on RIP
4882 * - Add checks on RFLAGS
4888 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4890 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4893 static int init_rmode_tss(struct kvm
*kvm
)
4899 idx
= srcu_read_lock(&kvm
->srcu
);
4900 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4901 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4904 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4905 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4906 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4909 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4912 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4916 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4917 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4920 srcu_read_unlock(&kvm
->srcu
, idx
);
4924 static int init_rmode_identity_map(struct kvm
*kvm
)
4927 kvm_pfn_t identity_map_pfn
;
4930 /* Protect kvm->arch.ept_identity_pagetable_done. */
4931 mutex_lock(&kvm
->slots_lock
);
4933 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4936 if (!kvm
->arch
.ept_identity_map_addr
)
4937 kvm
->arch
.ept_identity_map_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4938 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4940 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4941 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4945 idx
= srcu_read_lock(&kvm
->srcu
);
4946 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4949 /* Set up identity-mapping pagetable for EPT in real mode */
4950 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4951 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4952 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4953 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4954 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4958 kvm
->arch
.ept_identity_pagetable_done
= true;
4961 srcu_read_unlock(&kvm
->srcu
, idx
);
4964 mutex_unlock(&kvm
->slots_lock
);
4968 static void seg_setup(int seg
)
4970 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4973 vmcs_write16(sf
->selector
, 0);
4974 vmcs_writel(sf
->base
, 0);
4975 vmcs_write32(sf
->limit
, 0xffff);
4977 if (seg
== VCPU_SREG_CS
)
4978 ar
|= 0x08; /* code segment */
4980 vmcs_write32(sf
->ar_bytes
, ar
);
4983 static int alloc_apic_access_page(struct kvm
*kvm
)
4988 mutex_lock(&kvm
->slots_lock
);
4989 if (kvm
->arch
.apic_access_page_done
)
4991 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4992 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4996 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4997 if (is_error_page(page
)) {
5003 * Do not pin the page in memory, so that memory hot-unplug
5004 * is able to migrate it.
5007 kvm
->arch
.apic_access_page_done
= true;
5009 mutex_unlock(&kvm
->slots_lock
);
5013 static int allocate_vpid(void)
5019 spin_lock(&vmx_vpid_lock
);
5020 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
5021 if (vpid
< VMX_NR_VPIDS
)
5022 __set_bit(vpid
, vmx_vpid_bitmap
);
5025 spin_unlock(&vmx_vpid_lock
);
5029 static void free_vpid(int vpid
)
5031 if (!enable_vpid
|| vpid
== 0)
5033 spin_lock(&vmx_vpid_lock
);
5034 __clear_bit(vpid
, vmx_vpid_bitmap
);
5035 spin_unlock(&vmx_vpid_lock
);
5038 static void __always_inline
vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
5041 int f
= sizeof(unsigned long);
5043 if (!cpu_has_vmx_msr_bitmap())
5047 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5048 * have the write-low and read-high bitmap offsets the wrong way round.
5049 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5051 if (msr
<= 0x1fff) {
5052 if (type
& MSR_TYPE_R
)
5054 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
5056 if (type
& MSR_TYPE_W
)
5058 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
5060 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
5062 if (type
& MSR_TYPE_R
)
5064 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
5066 if (type
& MSR_TYPE_W
)
5068 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
5073 static void __always_inline
vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
5076 int f
= sizeof(unsigned long);
5078 if (!cpu_has_vmx_msr_bitmap())
5082 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5083 * have the write-low and read-high bitmap offsets the wrong way round.
5084 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5086 if (msr
<= 0x1fff) {
5087 if (type
& MSR_TYPE_R
)
5089 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
5091 if (type
& MSR_TYPE_W
)
5093 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
5095 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
5097 if (type
& MSR_TYPE_R
)
5099 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
5101 if (type
& MSR_TYPE_W
)
5103 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
5108 static void __always_inline
vmx_set_intercept_for_msr(unsigned long *msr_bitmap
,
5109 u32 msr
, int type
, bool value
)
5112 vmx_enable_intercept_for_msr(msr_bitmap
, msr
, type
);
5114 vmx_disable_intercept_for_msr(msr_bitmap
, msr
, type
);
5118 * If a msr is allowed by L0, we should check whether it is allowed by L1.
5119 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5121 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
5122 unsigned long *msr_bitmap_nested
,
5125 int f
= sizeof(unsigned long);
5127 if (!cpu_has_vmx_msr_bitmap()) {
5133 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5134 * have the write-low and read-high bitmap offsets the wrong way round.
5135 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5137 if (msr
<= 0x1fff) {
5138 if (type
& MSR_TYPE_R
&&
5139 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
5141 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
5143 if (type
& MSR_TYPE_W
&&
5144 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
5146 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
5148 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
5150 if (type
& MSR_TYPE_R
&&
5151 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
5153 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
5155 if (type
& MSR_TYPE_W
&&
5156 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
5158 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
5163 static u8
vmx_msr_bitmap_mode(struct kvm_vcpu
*vcpu
)
5167 if (cpu_has_secondary_exec_ctrls() &&
5168 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
5169 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
5170 mode
|= MSR_BITMAP_MODE_X2APIC
;
5171 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
))
5172 mode
|= MSR_BITMAP_MODE_X2APIC_APICV
;
5175 if (is_long_mode(vcpu
))
5176 mode
|= MSR_BITMAP_MODE_LM
;
5181 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5183 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap
,
5188 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
5189 unsigned word
= msr
/ BITS_PER_LONG
;
5190 msr_bitmap
[word
] = (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) ? 0 : ~0;
5191 msr_bitmap
[word
+ (0x800 / sizeof(long))] = ~0;
5194 if (mode
& MSR_BITMAP_MODE_X2APIC
) {
5196 * TPR reads and writes can be virtualized even if virtual interrupt
5197 * delivery is not in use.
5199 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_TASKPRI
), MSR_TYPE_RW
);
5200 if (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) {
5201 vmx_enable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_TMCCT
), MSR_TYPE_R
);
5202 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_EOI
), MSR_TYPE_W
);
5203 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_SELF_IPI
), MSR_TYPE_W
);
5208 static void vmx_update_msr_bitmap(struct kvm_vcpu
*vcpu
)
5210 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5211 unsigned long *msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
5212 u8 mode
= vmx_msr_bitmap_mode(vcpu
);
5213 u8 changed
= mode
^ vmx
->msr_bitmap_mode
;
5218 vmx_set_intercept_for_msr(msr_bitmap
, MSR_KERNEL_GS_BASE
, MSR_TYPE_RW
,
5219 !(mode
& MSR_BITMAP_MODE_LM
));
5221 if (changed
& (MSR_BITMAP_MODE_X2APIC
| MSR_BITMAP_MODE_X2APIC_APICV
))
5222 vmx_update_msr_bitmap_x2apic(msr_bitmap
, mode
);
5224 vmx
->msr_bitmap_mode
= mode
;
5227 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5229 return enable_apicv
;
5232 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5234 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5238 * Don't need to mark the APIC access page dirty; it is never
5239 * written to by the CPU during APIC virtualization.
5242 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5243 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5244 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5247 if (nested_cpu_has_posted_intr(vmcs12
)) {
5248 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5249 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5254 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5256 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5261 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5264 vmx
->nested
.pi_pending
= false;
5265 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5268 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5269 if (max_irr
!= 256) {
5270 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5271 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5272 kunmap(vmx
->nested
.virtual_apic_page
);
5274 status
= vmcs_read16(GUEST_INTR_STATUS
);
5275 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5277 status
|= (u8
)max_irr
;
5278 vmcs_write16(GUEST_INTR_STATUS
, status
);
5282 nested_mark_vmcs12_pages_dirty(vcpu
);
5285 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5289 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5291 if (vcpu
->mode
== IN_GUEST_MODE
) {
5293 * The vector of interrupt to be delivered to vcpu had
5294 * been set in PIR before this function.
5296 * Following cases will be reached in this block, and
5297 * we always send a notification event in all cases as
5300 * Case 1: vcpu keeps in non-root mode. Sending a
5301 * notification event posts the interrupt to vcpu.
5303 * Case 2: vcpu exits to root mode and is still
5304 * runnable. PIR will be synced to vIRR before the
5305 * next vcpu entry. Sending a notification event in
5306 * this case has no effect, as vcpu is not in root
5309 * Case 3: vcpu exits to root mode and is blocked.
5310 * vcpu_block() has already synced PIR to vIRR and
5311 * never blocks vcpu if vIRR is not cleared. Therefore,
5312 * a blocked vcpu here does not wait for any requested
5313 * interrupts in PIR, and sending a notification event
5314 * which has no effect is safe here.
5317 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5324 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5327 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5329 if (is_guest_mode(vcpu
) &&
5330 vector
== vmx
->nested
.posted_intr_nv
) {
5332 * If a posted intr is not recognized by hardware,
5333 * we will accomplish it in the next vmentry.
5335 vmx
->nested
.pi_pending
= true;
5336 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5337 /* the PIR and ON have been set by L1. */
5338 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, true))
5339 kvm_vcpu_kick(vcpu
);
5345 * Send interrupt to vcpu via posted interrupt way.
5346 * 1. If target vcpu is running(non-root mode), send posted interrupt
5347 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5348 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5349 * interrupt from PIR in next vmentry.
5351 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5353 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5356 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5360 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5363 /* If a previous notification has sent the IPI, nothing to do. */
5364 if (pi_test_and_set_on(&vmx
->pi_desc
))
5367 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5368 kvm_vcpu_kick(vcpu
);
5372 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5373 * will not change in the lifetime of the guest.
5374 * Note that host-state that does change is set elsewhere. E.g., host-state
5375 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5377 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5382 unsigned long cr0
, cr3
, cr4
;
5385 WARN_ON(cr0
& X86_CR0_TS
);
5386 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5389 * Save the most likely value for this task's CR3 in the VMCS.
5390 * We can't use __get_current_cr3_fast() because we're not atomic.
5393 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5394 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5396 /* Save the most likely value for this task's CR4 in the VMCS. */
5397 cr4
= cr4_read_shadow();
5398 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5399 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5401 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5402 #ifdef CONFIG_X86_64
5404 * Load null selectors, so we can avoid reloading them in
5405 * __vmx_load_host_state(), in case userspace uses the null selectors
5406 * too (the expected case).
5408 vmcs_write16(HOST_DS_SELECTOR
, 0);
5409 vmcs_write16(HOST_ES_SELECTOR
, 0);
5411 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5412 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5414 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5415 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5418 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5419 vmx
->host_idt_base
= dt
.address
;
5421 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5423 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5424 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5425 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5426 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5428 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5429 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5430 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5434 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5436 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5438 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5439 if (is_guest_mode(&vmx
->vcpu
))
5440 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5441 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5442 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5445 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5447 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5449 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5450 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5453 pin_based_exec_ctrl
&= ~PIN_BASED_VIRTUAL_NMIS
;
5455 /* Enable the preemption timer dynamically */
5456 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5457 return pin_based_exec_ctrl
;
5460 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5462 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5464 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5465 if (cpu_has_secondary_exec_ctrls()) {
5466 if (kvm_vcpu_apicv_active(vcpu
))
5467 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5468 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5469 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5471 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5472 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5473 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5476 if (cpu_has_vmx_msr_bitmap())
5477 vmx_update_msr_bitmap(vcpu
);
5480 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5482 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5484 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5485 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5487 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5488 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5489 #ifdef CONFIG_X86_64
5490 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5491 CPU_BASED_CR8_LOAD_EXITING
;
5495 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5496 CPU_BASED_CR3_LOAD_EXITING
|
5497 CPU_BASED_INVLPG_EXITING
;
5498 return exec_control
;
5501 static bool vmx_rdrand_supported(void)
5503 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5504 SECONDARY_EXEC_RDRAND_EXITING
;
5507 static bool vmx_rdseed_supported(void)
5509 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5510 SECONDARY_EXEC_RDSEED_EXITING
;
5513 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
5515 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
5517 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5518 if (!cpu_need_virtualize_apic_accesses(vcpu
))
5519 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5521 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5523 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5524 enable_unrestricted_guest
= 0;
5525 /* Enable INVPCID for non-ept guests may cause performance regression. */
5526 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5528 if (!enable_unrestricted_guest
)
5529 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5531 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5532 if (!kvm_vcpu_apicv_active(vcpu
))
5533 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5534 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5535 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5536 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5538 We can NOT enable shadow_vmcs here because we don't have yet
5541 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5544 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5546 if (vmx_xsaves_supported()) {
5547 /* Exposing XSAVES only when XSAVE is exposed */
5548 bool xsaves_enabled
=
5549 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
5550 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
5552 if (!xsaves_enabled
)
5553 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
5557 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5558 SECONDARY_EXEC_XSAVES
;
5560 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5561 ~SECONDARY_EXEC_XSAVES
;
5565 if (vmx_rdtscp_supported()) {
5566 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
5567 if (!rdtscp_enabled
)
5568 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5572 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5573 SECONDARY_EXEC_RDTSCP
;
5575 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5576 ~SECONDARY_EXEC_RDTSCP
;
5580 if (vmx_invpcid_supported()) {
5581 /* Exposing INVPCID only when PCID is exposed */
5582 bool invpcid_enabled
=
5583 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
5584 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
5586 if (!invpcid_enabled
) {
5587 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5588 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
5592 if (invpcid_enabled
)
5593 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5594 SECONDARY_EXEC_ENABLE_INVPCID
;
5596 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5597 ~SECONDARY_EXEC_ENABLE_INVPCID
;
5601 if (vmx_rdrand_supported()) {
5602 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
5604 exec_control
&= ~SECONDARY_EXEC_RDRAND_EXITING
;
5608 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5609 SECONDARY_EXEC_RDRAND_EXITING
;
5611 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5612 ~SECONDARY_EXEC_RDRAND_EXITING
;
5616 if (vmx_rdseed_supported()) {
5617 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
5619 exec_control
&= ~SECONDARY_EXEC_RDSEED_EXITING
;
5623 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5624 SECONDARY_EXEC_RDSEED_EXITING
;
5626 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5627 ~SECONDARY_EXEC_RDSEED_EXITING
;
5631 vmx
->secondary_exec_control
= exec_control
;
5634 static void ept_set_mmio_spte_mask(void)
5637 * EPT Misconfigurations can be generated if the value of bits 2:0
5638 * of an EPT paging-structure entry is 110b (write/execute).
5640 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5641 VMX_EPT_MISCONFIG_WX_VALUE
);
5644 #define VMX_XSS_EXIT_BITMAP 0
5646 * Sets up the vmcs for emulated real mode.
5648 static void vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5650 #ifdef CONFIG_X86_64
5656 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5657 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5659 if (enable_shadow_vmcs
) {
5660 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5661 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5663 if (cpu_has_vmx_msr_bitmap())
5664 vmcs_write64(MSR_BITMAP
, __pa(vmx
->vmcs01
.msr_bitmap
));
5666 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5669 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5670 vmx
->hv_deadline_tsc
= -1;
5672 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5674 if (cpu_has_secondary_exec_ctrls()) {
5675 vmx_compute_secondary_exec_control(vmx
);
5676 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5677 vmx
->secondary_exec_control
);
5680 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5681 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5682 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5683 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5684 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5686 vmcs_write16(GUEST_INTR_STATUS
, 0);
5688 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5689 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5693 vmcs_write32(PLE_GAP
, ple_gap
);
5694 vmx
->ple_window
= ple_window
;
5695 vmx
->ple_window_dirty
= true;
5698 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5699 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5700 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5702 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5703 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5704 vmx_set_constant_host_state(vmx
);
5705 #ifdef CONFIG_X86_64
5706 rdmsrl(MSR_FS_BASE
, a
);
5707 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5708 rdmsrl(MSR_GS_BASE
, a
);
5709 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5711 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5712 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5715 if (cpu_has_vmx_vmfunc())
5716 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5718 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5719 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5720 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5721 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5722 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5724 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5725 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5727 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5728 u32 index
= vmx_msr_index
[i
];
5729 u32 data_low
, data_high
;
5732 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5734 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5736 vmx
->guest_msrs
[j
].index
= i
;
5737 vmx
->guest_msrs
[j
].data
= 0;
5738 vmx
->guest_msrs
[j
].mask
= -1ull;
5742 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
))
5743 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, vmx
->arch_capabilities
);
5745 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5747 /* 22.2.1, 20.8.1 */
5748 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5750 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5751 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5753 set_cr4_guest_host_mask(vmx
);
5755 if (vmx_xsaves_supported())
5756 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5759 ASSERT(vmx
->pml_pg
);
5760 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5761 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5765 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5767 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5768 struct msr_data apic_base_msr
;
5771 vmx
->rmode
.vm86_active
= 0;
5774 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5775 kvm_set_cr8(vcpu
, 0);
5778 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5779 MSR_IA32_APICBASE_ENABLE
;
5780 if (kvm_vcpu_is_reset_bsp(vcpu
))
5781 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5782 apic_base_msr
.host_initiated
= true;
5783 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5786 vmx_segment_cache_clear(vmx
);
5788 seg_setup(VCPU_SREG_CS
);
5789 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5790 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5792 seg_setup(VCPU_SREG_DS
);
5793 seg_setup(VCPU_SREG_ES
);
5794 seg_setup(VCPU_SREG_FS
);
5795 seg_setup(VCPU_SREG_GS
);
5796 seg_setup(VCPU_SREG_SS
);
5798 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5799 vmcs_writel(GUEST_TR_BASE
, 0);
5800 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5801 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5803 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5804 vmcs_writel(GUEST_LDTR_BASE
, 0);
5805 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5806 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5809 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5810 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5811 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5812 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5815 kvm_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
5816 kvm_rip_write(vcpu
, 0xfff0);
5818 vmcs_writel(GUEST_GDTR_BASE
, 0);
5819 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5821 vmcs_writel(GUEST_IDTR_BASE
, 0);
5822 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5824 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5825 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5826 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5827 if (kvm_mpx_supported())
5828 vmcs_write64(GUEST_BNDCFGS
, 0);
5832 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5834 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5835 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5836 if (cpu_need_tpr_shadow(vcpu
))
5837 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5838 __pa(vcpu
->arch
.apic
->regs
));
5839 vmcs_write32(TPR_THRESHOLD
, 0);
5842 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5845 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5847 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5848 vmx
->vcpu
.arch
.cr0
= cr0
;
5849 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5850 vmx_set_cr4(vcpu
, 0);
5851 vmx_set_efer(vcpu
, 0);
5853 update_exception_bitmap(vcpu
);
5855 vpid_sync_context(vmx
->vpid
);
5859 * In nested virtualization, check if L1 asked to exit on external interrupts.
5860 * For most existing hypervisors, this will always return true.
5862 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5864 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5865 PIN_BASED_EXT_INTR_MASK
;
5869 * In nested virtualization, check if L1 has set
5870 * VM_EXIT_ACK_INTR_ON_EXIT
5872 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5874 return get_vmcs12(vcpu
)->vm_exit_controls
&
5875 VM_EXIT_ACK_INTR_ON_EXIT
;
5878 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5880 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5881 PIN_BASED_NMI_EXITING
;
5884 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5886 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5887 CPU_BASED_VIRTUAL_INTR_PENDING
);
5890 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5893 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5894 enable_irq_window(vcpu
);
5898 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5899 CPU_BASED_VIRTUAL_NMI_PENDING
);
5902 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5904 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5906 int irq
= vcpu
->arch
.interrupt
.nr
;
5908 trace_kvm_inj_virq(irq
);
5910 ++vcpu
->stat
.irq_injections
;
5911 if (vmx
->rmode
.vm86_active
) {
5913 if (vcpu
->arch
.interrupt
.soft
)
5914 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5915 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5916 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5919 intr
= irq
| INTR_INFO_VALID_MASK
;
5920 if (vcpu
->arch
.interrupt
.soft
) {
5921 intr
|= INTR_TYPE_SOFT_INTR
;
5922 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5923 vmx
->vcpu
.arch
.event_exit_inst_len
);
5925 intr
|= INTR_TYPE_EXT_INTR
;
5926 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5929 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5931 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5935 * Tracking the NMI-blocked state in software is built upon
5936 * finding the next open IRQ window. This, in turn, depends on
5937 * well-behaving guests: They have to keep IRQs disabled at
5938 * least as long as the NMI handler runs. Otherwise we may
5939 * cause NMI nesting, maybe breaking the guest. But as this is
5940 * highly unlikely, we can live with the residual risk.
5942 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 1;
5943 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5946 ++vcpu
->stat
.nmi_injections
;
5947 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5949 if (vmx
->rmode
.vm86_active
) {
5950 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5951 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5955 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5956 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5959 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5961 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5965 return vmx
->loaded_vmcs
->soft_vnmi_blocked
;
5966 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5968 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5969 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5973 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5975 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5978 if (vmx
->loaded_vmcs
->soft_vnmi_blocked
!= masked
) {
5979 vmx
->loaded_vmcs
->soft_vnmi_blocked
= masked
;
5980 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5983 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5985 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5986 GUEST_INTR_STATE_NMI
);
5988 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5989 GUEST_INTR_STATE_NMI
);
5993 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5995 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5999 to_vmx(vcpu
)->loaded_vmcs
->soft_vnmi_blocked
)
6002 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
6003 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
6004 | GUEST_INTR_STATE_NMI
));
6007 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
6009 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
6010 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
6011 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
6012 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
6015 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
6019 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
6023 kvm
->arch
.tss_addr
= addr
;
6024 return init_rmode_tss(kvm
);
6027 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
6032 * Update instruction length as we may reinject the exception
6033 * from user space while in guest debugging mode.
6035 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
6036 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6037 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
6041 if (vcpu
->guest_debug
&
6042 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
6059 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
6060 int vec
, u32 err_code
)
6063 * Instruction with address size override prefix opcode 0x67
6064 * Cause the #SS fault with 0 error code in VM86 mode.
6066 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
6067 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
6068 if (vcpu
->arch
.halt_request
) {
6069 vcpu
->arch
.halt_request
= 0;
6070 return kvm_vcpu_halt(vcpu
);
6078 * Forward all other exceptions that are valid in real mode.
6079 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6080 * the required debugging infrastructure rework.
6082 kvm_queue_exception(vcpu
, vec
);
6087 * Trigger machine check on the host. We assume all the MSRs are already set up
6088 * by the CPU and that we still run on the same CPU as the MCE occurred on.
6089 * We pass a fake environment to the machine check handler because we want
6090 * the guest to be always treated like user space, no matter what context
6091 * it used internally.
6093 static void kvm_machine_check(void)
6095 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6096 struct pt_regs regs
= {
6097 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
6098 .flags
= X86_EFLAGS_IF
,
6101 do_machine_check(®s
, 0);
6105 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
6107 /* already handled by vcpu_run */
6111 static int handle_exception(struct kvm_vcpu
*vcpu
)
6113 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6114 struct kvm_run
*kvm_run
= vcpu
->run
;
6115 u32 intr_info
, ex_no
, error_code
;
6116 unsigned long cr2
, rip
, dr6
;
6118 enum emulation_result er
;
6120 vect_info
= vmx
->idt_vectoring_info
;
6121 intr_info
= vmx
->exit_intr_info
;
6123 if (is_machine_check(intr_info
))
6124 return handle_machine_check(vcpu
);
6126 if (is_nmi(intr_info
))
6127 return 1; /* already handled by vmx_vcpu_run() */
6129 if (is_invalid_opcode(intr_info
)) {
6130 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
6131 if (er
== EMULATE_USER_EXIT
)
6133 if (er
!= EMULATE_DONE
)
6134 kvm_queue_exception(vcpu
, UD_VECTOR
);
6139 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
6140 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
6143 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6144 * MMIO, it is better to report an internal error.
6145 * See the comments in vmx_handle_exit.
6147 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
6148 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
6149 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6150 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
6151 vcpu
->run
->internal
.ndata
= 3;
6152 vcpu
->run
->internal
.data
[0] = vect_info
;
6153 vcpu
->run
->internal
.data
[1] = intr_info
;
6154 vcpu
->run
->internal
.data
[2] = error_code
;
6158 if (is_page_fault(intr_info
)) {
6159 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
6160 /* EPT won't cause page fault directly */
6161 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
6162 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0);
6165 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
6167 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
6168 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
6172 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
6175 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
6176 if (!(vcpu
->guest_debug
&
6177 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
6178 vcpu
->arch
.dr6
&= ~15;
6179 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
6180 if (is_icebp(intr_info
))
6181 skip_emulated_instruction(vcpu
);
6183 kvm_queue_exception(vcpu
, DB_VECTOR
);
6186 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
6187 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
6191 * Update instruction length as we may reinject #BP from
6192 * user space while in guest debugging mode. Reading it for
6193 * #DB as well causes no harm, it is not used in that case.
6195 vmx
->vcpu
.arch
.event_exit_inst_len
=
6196 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6197 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
6198 rip
= kvm_rip_read(vcpu
);
6199 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
6200 kvm_run
->debug
.arch
.exception
= ex_no
;
6203 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
6204 kvm_run
->ex
.exception
= ex_no
;
6205 kvm_run
->ex
.error_code
= error_code
;
6211 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
6213 ++vcpu
->stat
.irq_exits
;
6217 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
6219 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
6220 vcpu
->mmio_needed
= 0;
6224 static int handle_io(struct kvm_vcpu
*vcpu
)
6226 unsigned long exit_qualification
;
6227 int size
, in
, string
, ret
;
6230 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6231 string
= (exit_qualification
& 16) != 0;
6232 in
= (exit_qualification
& 8) != 0;
6234 ++vcpu
->stat
.io_exits
;
6237 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6239 port
= exit_qualification
>> 16;
6240 size
= (exit_qualification
& 7) + 1;
6242 ret
= kvm_skip_emulated_instruction(vcpu
);
6245 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6246 * KVM_EXIT_DEBUG here.
6248 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
6252 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
6255 * Patch in the VMCALL instruction:
6257 hypercall
[0] = 0x0f;
6258 hypercall
[1] = 0x01;
6259 hypercall
[2] = 0xc1;
6262 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6263 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
6265 if (is_guest_mode(vcpu
)) {
6266 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6267 unsigned long orig_val
= val
;
6270 * We get here when L2 changed cr0 in a way that did not change
6271 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6272 * but did change L0 shadowed bits. So we first calculate the
6273 * effective cr0 value that L1 would like to write into the
6274 * hardware. It consists of the L2-owned bits from the new
6275 * value combined with the L1-owned bits from L1's guest_cr0.
6277 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
6278 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
6280 if (!nested_guest_cr0_valid(vcpu
, val
))
6283 if (kvm_set_cr0(vcpu
, val
))
6285 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
6288 if (to_vmx(vcpu
)->nested
.vmxon
&&
6289 !nested_host_cr0_valid(vcpu
, val
))
6292 return kvm_set_cr0(vcpu
, val
);
6296 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
6298 if (is_guest_mode(vcpu
)) {
6299 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6300 unsigned long orig_val
= val
;
6302 /* analogously to handle_set_cr0 */
6303 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
6304 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
6305 if (kvm_set_cr4(vcpu
, val
))
6307 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
6310 return kvm_set_cr4(vcpu
, val
);
6313 static int handle_cr(struct kvm_vcpu
*vcpu
)
6315 unsigned long exit_qualification
, val
;
6321 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6322 cr
= exit_qualification
& 15;
6323 reg
= (exit_qualification
>> 8) & 15;
6324 switch ((exit_qualification
>> 4) & 3) {
6325 case 0: /* mov to cr */
6326 val
= kvm_register_readl(vcpu
, reg
);
6327 trace_kvm_cr_write(cr
, val
);
6330 err
= handle_set_cr0(vcpu
, val
);
6331 return kvm_complete_insn_gp(vcpu
, err
);
6333 err
= kvm_set_cr3(vcpu
, val
);
6334 return kvm_complete_insn_gp(vcpu
, err
);
6336 err
= handle_set_cr4(vcpu
, val
);
6337 return kvm_complete_insn_gp(vcpu
, err
);
6339 u8 cr8_prev
= kvm_get_cr8(vcpu
);
6341 err
= kvm_set_cr8(vcpu
, cr8
);
6342 ret
= kvm_complete_insn_gp(vcpu
, err
);
6343 if (lapic_in_kernel(vcpu
))
6345 if (cr8_prev
<= cr8
)
6348 * TODO: we might be squashing a
6349 * KVM_GUESTDBG_SINGLESTEP-triggered
6350 * KVM_EXIT_DEBUG here.
6352 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6358 WARN_ONCE(1, "Guest should always own CR0.TS");
6359 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6360 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6361 return kvm_skip_emulated_instruction(vcpu
);
6362 case 1: /*mov from cr*/
6365 val
= kvm_read_cr3(vcpu
);
6366 kvm_register_write(vcpu
, reg
, val
);
6367 trace_kvm_cr_read(cr
, val
);
6368 return kvm_skip_emulated_instruction(vcpu
);
6370 val
= kvm_get_cr8(vcpu
);
6371 kvm_register_write(vcpu
, reg
, val
);
6372 trace_kvm_cr_read(cr
, val
);
6373 return kvm_skip_emulated_instruction(vcpu
);
6377 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6378 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6379 kvm_lmsw(vcpu
, val
);
6381 return kvm_skip_emulated_instruction(vcpu
);
6385 vcpu
->run
->exit_reason
= 0;
6386 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6387 (int)(exit_qualification
>> 4) & 3, cr
);
6391 static int handle_dr(struct kvm_vcpu
*vcpu
)
6393 unsigned long exit_qualification
;
6396 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6397 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6399 /* First, if DR does not exist, trigger UD */
6400 if (!kvm_require_dr(vcpu
, dr
))
6403 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6404 if (!kvm_require_cpl(vcpu
, 0))
6406 dr7
= vmcs_readl(GUEST_DR7
);
6409 * As the vm-exit takes precedence over the debug trap, we
6410 * need to emulate the latter, either for the host or the
6411 * guest debugging itself.
6413 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6414 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6415 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6416 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6417 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6418 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6421 vcpu
->arch
.dr6
&= ~15;
6422 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6423 kvm_queue_exception(vcpu
, DB_VECTOR
);
6428 if (vcpu
->guest_debug
== 0) {
6429 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6430 CPU_BASED_MOV_DR_EXITING
);
6433 * No more DR vmexits; force a reload of the debug registers
6434 * and reenter on this instruction. The next vmexit will
6435 * retrieve the full state of the debug registers.
6437 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6441 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6442 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6445 if (kvm_get_dr(vcpu
, dr
, &val
))
6447 kvm_register_write(vcpu
, reg
, val
);
6449 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6452 return kvm_skip_emulated_instruction(vcpu
);
6455 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6457 return vcpu
->arch
.dr6
;
6460 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6464 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6466 get_debugreg(vcpu
->arch
.db
[0], 0);
6467 get_debugreg(vcpu
->arch
.db
[1], 1);
6468 get_debugreg(vcpu
->arch
.db
[2], 2);
6469 get_debugreg(vcpu
->arch
.db
[3], 3);
6470 get_debugreg(vcpu
->arch
.dr6
, 6);
6471 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6473 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6474 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6477 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6479 vmcs_writel(GUEST_DR7
, val
);
6482 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6484 return kvm_emulate_cpuid(vcpu
);
6487 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6489 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6490 struct msr_data msr_info
;
6492 msr_info
.index
= ecx
;
6493 msr_info
.host_initiated
= false;
6494 if (vmx_get_msr(vcpu
, &msr_info
)) {
6495 trace_kvm_msr_read_ex(ecx
);
6496 kvm_inject_gp(vcpu
, 0);
6500 trace_kvm_msr_read(ecx
, msr_info
.data
);
6502 /* FIXME: handling of bits 32:63 of rax, rdx */
6503 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6504 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6505 return kvm_skip_emulated_instruction(vcpu
);
6508 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6510 struct msr_data msr
;
6511 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6512 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6513 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6517 msr
.host_initiated
= false;
6518 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6519 trace_kvm_msr_write_ex(ecx
, data
);
6520 kvm_inject_gp(vcpu
, 0);
6524 trace_kvm_msr_write(ecx
, data
);
6525 return kvm_skip_emulated_instruction(vcpu
);
6528 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6530 kvm_apic_update_ppr(vcpu
);
6534 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6536 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6537 CPU_BASED_VIRTUAL_INTR_PENDING
);
6539 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6541 ++vcpu
->stat
.irq_window_exits
;
6545 static int handle_halt(struct kvm_vcpu
*vcpu
)
6547 return kvm_emulate_halt(vcpu
);
6550 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6552 return kvm_emulate_hypercall(vcpu
);
6555 static int handle_invd(struct kvm_vcpu
*vcpu
)
6557 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6560 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6562 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6564 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6565 return kvm_skip_emulated_instruction(vcpu
);
6568 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6572 err
= kvm_rdpmc(vcpu
);
6573 return kvm_complete_insn_gp(vcpu
, err
);
6576 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6578 return kvm_emulate_wbinvd(vcpu
);
6581 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6583 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6584 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6586 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6587 return kvm_skip_emulated_instruction(vcpu
);
6591 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6593 kvm_skip_emulated_instruction(vcpu
);
6594 WARN(1, "this should never happen\n");
6598 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6600 kvm_skip_emulated_instruction(vcpu
);
6601 WARN(1, "this should never happen\n");
6605 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6607 if (likely(fasteoi
)) {
6608 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6609 int access_type
, offset
;
6611 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6612 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6614 * Sane guest uses MOV to write EOI, with written value
6615 * not cared. So make a short-circuit here by avoiding
6616 * heavy instruction emulation.
6618 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6619 (offset
== APIC_EOI
)) {
6620 kvm_lapic_set_eoi(vcpu
);
6621 return kvm_skip_emulated_instruction(vcpu
);
6624 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6627 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6629 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6630 int vector
= exit_qualification
& 0xff;
6632 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6633 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6637 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6639 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6640 u32 offset
= exit_qualification
& 0xfff;
6642 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6643 kvm_apic_write_nodecode(vcpu
, offset
);
6647 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6649 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6650 unsigned long exit_qualification
;
6651 bool has_error_code
= false;
6654 int reason
, type
, idt_v
, idt_index
;
6656 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6657 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6658 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6660 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6662 reason
= (u32
)exit_qualification
>> 30;
6663 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6665 case INTR_TYPE_NMI_INTR
:
6666 vcpu
->arch
.nmi_injected
= false;
6667 vmx_set_nmi_mask(vcpu
, true);
6669 case INTR_TYPE_EXT_INTR
:
6670 case INTR_TYPE_SOFT_INTR
:
6671 kvm_clear_interrupt_queue(vcpu
);
6673 case INTR_TYPE_HARD_EXCEPTION
:
6674 if (vmx
->idt_vectoring_info
&
6675 VECTORING_INFO_DELIVER_CODE_MASK
) {
6676 has_error_code
= true;
6678 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6681 case INTR_TYPE_SOFT_EXCEPTION
:
6682 kvm_clear_exception_queue(vcpu
);
6688 tss_selector
= exit_qualification
;
6690 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6691 type
!= INTR_TYPE_EXT_INTR
&&
6692 type
!= INTR_TYPE_NMI_INTR
))
6693 skip_emulated_instruction(vcpu
);
6695 if (kvm_task_switch(vcpu
, tss_selector
,
6696 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6697 has_error_code
, error_code
) == EMULATE_FAIL
) {
6698 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6699 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6700 vcpu
->run
->internal
.ndata
= 0;
6705 * TODO: What about debug traps on tss switch?
6706 * Are we supposed to inject them and update dr6?
6712 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6714 unsigned long exit_qualification
;
6718 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6721 * EPT violation happened while executing iret from NMI,
6722 * "blocked by NMI" bit has to be set before next VM entry.
6723 * There are errata that may cause this bit to not be set:
6726 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6728 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6729 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6731 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6732 trace_kvm_page_fault(gpa
, exit_qualification
);
6734 /* Is it a read fault? */
6735 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6736 ? PFERR_USER_MASK
: 0;
6737 /* Is it a write fault? */
6738 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6739 ? PFERR_WRITE_MASK
: 0;
6740 /* Is it a fetch fault? */
6741 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6742 ? PFERR_FETCH_MASK
: 0;
6743 /* ept page table entry is present? */
6744 error_code
|= (exit_qualification
&
6745 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6746 EPT_VIOLATION_EXECUTABLE
))
6747 ? PFERR_PRESENT_MASK
: 0;
6749 error_code
|= (exit_qualification
& 0x100) != 0 ?
6750 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6752 vcpu
->arch
.exit_qualification
= exit_qualification
;
6753 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6756 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6762 * A nested guest cannot optimize MMIO vmexits, because we have an
6763 * nGPA here instead of the required GPA.
6765 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6766 if (!is_guest_mode(vcpu
) &&
6767 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6768 trace_kvm_fast_mmio(gpa
);
6770 * Doing kvm_skip_emulated_instruction() depends on undefined
6771 * behavior: Intel's manual doesn't mandate
6772 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
6773 * occurs and while on real hardware it was observed to be set,
6774 * other hypervisors (namely Hyper-V) don't set it, we end up
6775 * advancing IP with some random value. Disable fast mmio when
6776 * running nested and keep it for real hardware in hope that
6777 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
6779 if (!static_cpu_has(X86_FEATURE_HYPERVISOR
))
6780 return kvm_skip_emulated_instruction(vcpu
);
6782 return x86_emulate_instruction(vcpu
, gpa
, EMULTYPE_SKIP
,
6783 NULL
, 0) == EMULATE_DONE
;
6786 ret
= kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
6790 /* It is the real ept misconfig */
6793 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6794 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6799 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6801 WARN_ON_ONCE(!enable_vnmi
);
6802 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6803 CPU_BASED_VIRTUAL_NMI_PENDING
);
6804 ++vcpu
->stat
.nmi_window_exits
;
6805 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6810 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6812 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6813 enum emulation_result err
= EMULATE_DONE
;
6816 bool intr_window_requested
;
6817 unsigned count
= 130;
6819 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6820 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6822 while (vmx
->emulation_required
&& count
-- != 0) {
6823 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6824 return handle_interrupt_window(&vmx
->vcpu
);
6826 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6829 err
= emulate_instruction(vcpu
, 0);
6831 if (err
== EMULATE_USER_EXIT
) {
6832 ++vcpu
->stat
.mmio_exits
;
6837 if (err
!= EMULATE_DONE
) {
6838 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6839 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6840 vcpu
->run
->internal
.ndata
= 0;
6844 if (vcpu
->arch
.halt_request
) {
6845 vcpu
->arch
.halt_request
= 0;
6846 ret
= kvm_vcpu_halt(vcpu
);
6850 if (signal_pending(current
))
6860 static int __grow_ple_window(int val
)
6862 if (ple_window_grow
< 1)
6865 val
= min(val
, ple_window_actual_max
);
6867 if (ple_window_grow
< ple_window
)
6868 val
*= ple_window_grow
;
6870 val
+= ple_window_grow
;
6875 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6880 if (modifier
< ple_window
)
6885 return max(val
, minimum
);
6888 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6890 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6891 int old
= vmx
->ple_window
;
6893 vmx
->ple_window
= __grow_ple_window(old
);
6895 if (vmx
->ple_window
!= old
)
6896 vmx
->ple_window_dirty
= true;
6898 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6901 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6903 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6904 int old
= vmx
->ple_window
;
6906 vmx
->ple_window
= __shrink_ple_window(old
,
6907 ple_window_shrink
, ple_window
);
6909 if (vmx
->ple_window
!= old
)
6910 vmx
->ple_window_dirty
= true;
6912 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6916 * ple_window_actual_max is computed to be one grow_ple_window() below
6917 * ple_window_max. (See __grow_ple_window for the reason.)
6918 * This prevents overflows, because ple_window_max is int.
6919 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6921 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6923 static void update_ple_window_actual_max(void)
6925 ple_window_actual_max
=
6926 __shrink_ple_window(max(ple_window_max
, ple_window
),
6927 ple_window_grow
, INT_MIN
);
6931 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6933 static void wakeup_handler(void)
6935 struct kvm_vcpu
*vcpu
;
6936 int cpu
= smp_processor_id();
6938 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6939 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6940 blocked_vcpu_list
) {
6941 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6943 if (pi_test_on(pi_desc
) == 1)
6944 kvm_vcpu_kick(vcpu
);
6946 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6949 void vmx_enable_tdp(void)
6951 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6952 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6953 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6954 0ull, VMX_EPT_EXECUTABLE_MASK
,
6955 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6956 VMX_EPT_RWX_MASK
, 0ull);
6958 ept_set_mmio_spte_mask();
6962 static __init
int hardware_setup(void)
6966 rdmsrl_safe(MSR_EFER
, &host_efer
);
6968 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6969 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6971 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6972 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6977 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6978 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6980 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6982 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6984 if (setup_vmcs_config(&vmcs_config
) < 0) {
6989 if (boot_cpu_has(X86_FEATURE_NX
))
6990 kvm_enable_efer_bits(EFER_NX
);
6992 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6993 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6996 if (!cpu_has_vmx_shadow_vmcs())
6997 enable_shadow_vmcs
= 0;
6998 if (enable_shadow_vmcs
)
6999 init_vmcs_shadow_fields();
7001 if (!cpu_has_vmx_ept() ||
7002 !cpu_has_vmx_ept_4levels() ||
7003 !cpu_has_vmx_ept_mt_wb() ||
7004 !cpu_has_vmx_invept_global())
7007 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
7008 enable_ept_ad_bits
= 0;
7010 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept
)
7011 enable_unrestricted_guest
= 0;
7013 if (!cpu_has_vmx_flexpriority())
7014 flexpriority_enabled
= 0;
7016 if (!cpu_has_virtual_nmis())
7020 * set_apic_access_page_addr() is used to reload apic access
7021 * page upon invalidation. No need to do anything if not
7022 * using the APIC_ACCESS_ADDR VMCS field.
7024 if (!flexpriority_enabled
)
7025 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
7027 if (!cpu_has_vmx_tpr_shadow())
7028 kvm_x86_ops
->update_cr8_intercept
= NULL
;
7030 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
7031 kvm_disable_largepages();
7033 if (!cpu_has_vmx_ple()) {
7036 ple_window_grow
= 0;
7038 ple_window_shrink
= 0;
7041 if (!cpu_has_vmx_apicv()) {
7043 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
7046 if (cpu_has_vmx_tsc_scaling()) {
7047 kvm_has_tsc_control
= true;
7048 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
7049 kvm_tsc_scaling_ratio_frac_bits
= 48;
7052 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7059 update_ple_window_actual_max();
7062 * Only enable PML when hardware supports PML feature, and both EPT
7063 * and EPT A/D bit features are enabled -- PML depends on them to work.
7065 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
7069 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
7070 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
7071 kvm_x86_ops
->flush_log_dirty
= NULL
;
7072 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
7075 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
7078 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
7079 cpu_preemption_timer_multi
=
7080 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
7082 kvm_x86_ops
->set_hv_timer
= NULL
;
7083 kvm_x86_ops
->cancel_hv_timer
= NULL
;
7086 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
7088 kvm_mce_cap_supported
|= MCG_LMCE_P
;
7090 return alloc_kvm_area();
7093 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
7094 free_page((unsigned long)vmx_bitmap
[i
]);
7099 static __exit
void hardware_unsetup(void)
7103 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
7104 free_page((unsigned long)vmx_bitmap
[i
]);
7110 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7111 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7113 static int handle_pause(struct kvm_vcpu
*vcpu
)
7116 grow_ple_window(vcpu
);
7119 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7120 * VM-execution control is ignored if CPL > 0. OTOH, KVM
7121 * never set PAUSE_EXITING and just set PLE if supported,
7122 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7124 kvm_vcpu_on_spin(vcpu
, true);
7125 return kvm_skip_emulated_instruction(vcpu
);
7128 static int handle_nop(struct kvm_vcpu
*vcpu
)
7130 return kvm_skip_emulated_instruction(vcpu
);
7133 static int handle_mwait(struct kvm_vcpu
*vcpu
)
7135 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
7136 return handle_nop(vcpu
);
7139 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
7141 kvm_queue_exception(vcpu
, UD_VECTOR
);
7145 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
7150 static int handle_monitor(struct kvm_vcpu
*vcpu
)
7152 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
7153 return handle_nop(vcpu
);
7157 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7158 * set the success or error code of an emulated VMX instruction, as specified
7159 * by Vol 2B, VMX Instruction Reference, "Conventions".
7161 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
7163 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
7164 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7165 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
7168 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
7170 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7171 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
7172 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7176 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
7177 u32 vm_instruction_error
)
7179 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
7181 * failValid writes the error number to the current VMCS, which
7182 * can't be done there isn't a current VMCS.
7184 nested_vmx_failInvalid(vcpu
);
7187 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7188 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7189 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7191 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
7193 * We don't need to force a shadow sync because
7194 * VM_INSTRUCTION_ERROR is not shadowed
7198 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
7200 /* TODO: not to reset guest simply here. */
7201 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7202 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
7205 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
7207 struct vcpu_vmx
*vmx
=
7208 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
7210 vmx
->nested
.preemption_timer_expired
= true;
7211 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
7212 kvm_vcpu_kick(&vmx
->vcpu
);
7214 return HRTIMER_NORESTART
;
7218 * Decode the memory-address operand of a vmx instruction, as recorded on an
7219 * exit caused by such an instruction (run by a guest hypervisor).
7220 * On success, returns 0. When the operand is invalid, returns 1 and throws
7223 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
7224 unsigned long exit_qualification
,
7225 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
7229 struct kvm_segment s
;
7232 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7233 * Execution", on an exit, vmx_instruction_info holds most of the
7234 * addressing components of the operand. Only the displacement part
7235 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7236 * For how an actual address is calculated from all these components,
7237 * refer to Vol. 1, "Operand Addressing".
7239 int scaling
= vmx_instruction_info
& 3;
7240 int addr_size
= (vmx_instruction_info
>> 7) & 7;
7241 bool is_reg
= vmx_instruction_info
& (1u << 10);
7242 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
7243 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
7244 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
7245 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
7246 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7249 kvm_queue_exception(vcpu
, UD_VECTOR
);
7253 /* Addr = segment_base + offset */
7254 /* offset = base + [index * scale] + displacement */
7255 off
= exit_qualification
; /* holds the displacement */
7257 off
+= kvm_register_read(vcpu
, base_reg
);
7259 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7260 vmx_get_segment(vcpu
, &s
, seg_reg
);
7261 *ret
= s
.base
+ off
;
7263 if (addr_size
== 1) /* 32 bit */
7266 /* Checks for #GP/#SS exceptions. */
7268 if (is_long_mode(vcpu
)) {
7269 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7270 * non-canonical form. This is the only check on the memory
7271 * destination for long mode!
7273 exn
= is_noncanonical_address(*ret
, vcpu
);
7274 } else if (is_protmode(vcpu
)) {
7275 /* Protected mode: apply checks for segment validity in the
7277 * - segment type check (#GP(0) may be thrown)
7278 * - usability check (#GP(0)/#SS(0))
7279 * - limit check (#GP(0)/#SS(0))
7282 /* #GP(0) if the destination operand is located in a
7283 * read-only data segment or any code segment.
7285 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7287 /* #GP(0) if the source operand is located in an
7288 * execute-only code segment
7290 exn
= ((s
.type
& 0xa) == 8);
7292 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7295 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7297 exn
= (s
.unusable
!= 0);
7298 /* Protected mode: #GP(0)/#SS(0) if the memory
7299 * operand is outside the segment limit.
7301 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7304 kvm_queue_exception_e(vcpu
,
7305 seg_reg
== VCPU_SREG_SS
?
7306 SS_VECTOR
: GP_VECTOR
,
7314 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7317 struct x86_exception e
;
7319 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7320 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7323 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7324 sizeof(*vmpointer
), &e
)) {
7325 kvm_inject_page_fault(vcpu
, &e
);
7332 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7334 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7335 struct vmcs
*shadow_vmcs
;
7338 r
= alloc_loaded_vmcs(&vmx
->nested
.vmcs02
);
7342 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7343 if (!vmx
->nested
.cached_vmcs12
)
7344 goto out_cached_vmcs12
;
7346 if (enable_shadow_vmcs
) {
7347 shadow_vmcs
= alloc_vmcs();
7349 goto out_shadow_vmcs
;
7350 /* mark vmcs as shadow */
7351 shadow_vmcs
->revision_id
|= (1u << 31);
7352 /* init shadow vmcs */
7353 vmcs_clear(shadow_vmcs
);
7354 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7357 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7358 HRTIMER_MODE_REL_PINNED
);
7359 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7361 vmx
->nested
.vmxon
= true;
7365 kfree(vmx
->nested
.cached_vmcs12
);
7368 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
7375 * Emulate the VMXON instruction.
7376 * Currently, we just remember that VMX is active, and do not save or even
7377 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7378 * do not currently need to store anything in that guest-allocated memory
7379 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7380 * argument is different from the VMXON pointer (which the spec says they do).
7382 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7387 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7388 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7389 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7392 * The Intel VMX Instruction Reference lists a bunch of bits that are
7393 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7394 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7395 * Otherwise, we should fail with #UD. But most faulting conditions
7396 * have already been checked by hardware, prior to the VM-exit for
7397 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7398 * that bit set to 1 in non-root mode.
7400 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7401 kvm_queue_exception(vcpu
, UD_VECTOR
);
7405 if (vmx
->nested
.vmxon
) {
7406 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7407 return kvm_skip_emulated_instruction(vcpu
);
7410 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7411 != VMXON_NEEDED_FEATURES
) {
7412 kvm_inject_gp(vcpu
, 0);
7416 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7421 * The first 4 bytes of VMXON region contain the supported
7422 * VMCS revision identifier
7424 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7425 * which replaces physical address width with 32
7427 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7428 nested_vmx_failInvalid(vcpu
);
7429 return kvm_skip_emulated_instruction(vcpu
);
7432 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7433 if (is_error_page(page
)) {
7434 nested_vmx_failInvalid(vcpu
);
7435 return kvm_skip_emulated_instruction(vcpu
);
7437 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7439 kvm_release_page_clean(page
);
7440 nested_vmx_failInvalid(vcpu
);
7441 return kvm_skip_emulated_instruction(vcpu
);
7444 kvm_release_page_clean(page
);
7446 vmx
->nested
.vmxon_ptr
= vmptr
;
7447 ret
= enter_vmx_operation(vcpu
);
7451 nested_vmx_succeed(vcpu
);
7452 return kvm_skip_emulated_instruction(vcpu
);
7456 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7457 * for running VMX instructions (except VMXON, whose prerequisites are
7458 * slightly different). It also specifies what exception to inject otherwise.
7459 * Note that many of these exceptions have priority over VM exits, so they
7460 * don't have to be checked again here.
7462 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7464 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7465 kvm_queue_exception(vcpu
, UD_VECTOR
);
7471 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7473 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7474 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7477 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7479 if (vmx
->nested
.current_vmptr
== -1ull)
7482 if (enable_shadow_vmcs
) {
7483 /* copy to memory all shadowed fields in case
7484 they were modified */
7485 copy_shadow_to_vmcs12(vmx
);
7486 vmx
->nested
.sync_shadow_vmcs
= false;
7487 vmx_disable_shadow_vmcs(vmx
);
7489 vmx
->nested
.posted_intr_nv
= -1;
7491 /* Flush VMCS12 to guest memory */
7492 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7493 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7494 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7496 vmx
->nested
.current_vmptr
= -1ull;
7500 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7501 * just stops using VMX.
7503 static void free_nested(struct vcpu_vmx
*vmx
)
7505 if (!vmx
->nested
.vmxon
&& !vmx
->nested
.smm
.vmxon
)
7508 vmx
->nested
.vmxon
= false;
7509 vmx
->nested
.smm
.vmxon
= false;
7510 free_vpid(vmx
->nested
.vpid02
);
7511 vmx
->nested
.posted_intr_nv
= -1;
7512 vmx
->nested
.current_vmptr
= -1ull;
7513 if (enable_shadow_vmcs
) {
7514 vmx_disable_shadow_vmcs(vmx
);
7515 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7516 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7517 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7519 kfree(vmx
->nested
.cached_vmcs12
);
7520 /* Unpin physical memory we referred to in the vmcs02 */
7521 if (vmx
->nested
.apic_access_page
) {
7522 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7523 vmx
->nested
.apic_access_page
= NULL
;
7525 if (vmx
->nested
.virtual_apic_page
) {
7526 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7527 vmx
->nested
.virtual_apic_page
= NULL
;
7529 if (vmx
->nested
.pi_desc_page
) {
7530 kunmap(vmx
->nested
.pi_desc_page
);
7531 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7532 vmx
->nested
.pi_desc_page
= NULL
;
7533 vmx
->nested
.pi_desc
= NULL
;
7536 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
7539 /* Emulate the VMXOFF instruction */
7540 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7542 if (!nested_vmx_check_permission(vcpu
))
7544 free_nested(to_vmx(vcpu
));
7545 nested_vmx_succeed(vcpu
);
7546 return kvm_skip_emulated_instruction(vcpu
);
7549 /* Emulate the VMCLEAR instruction */
7550 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7552 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7556 if (!nested_vmx_check_permission(vcpu
))
7559 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7562 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7563 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7564 return kvm_skip_emulated_instruction(vcpu
);
7567 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7568 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7569 return kvm_skip_emulated_instruction(vcpu
);
7572 if (vmptr
== vmx
->nested
.current_vmptr
)
7573 nested_release_vmcs12(vmx
);
7575 kvm_vcpu_write_guest(vcpu
,
7576 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7577 &zero
, sizeof(zero
));
7579 nested_vmx_succeed(vcpu
);
7580 return kvm_skip_emulated_instruction(vcpu
);
7583 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7585 /* Emulate the VMLAUNCH instruction */
7586 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7588 return nested_vmx_run(vcpu
, true);
7591 /* Emulate the VMRESUME instruction */
7592 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7595 return nested_vmx_run(vcpu
, false);
7599 * Read a vmcs12 field. Since these can have varying lengths and we return
7600 * one type, we chose the biggest type (u64) and zero-extend the return value
7601 * to that size. Note that the caller, handle_vmread, might need to use only
7602 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7603 * 64-bit fields are to be returned).
7605 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7606 unsigned long field
, u64
*ret
)
7608 short offset
= vmcs_field_to_offset(field
);
7614 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7616 switch (vmcs_field_type(field
)) {
7617 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7618 *ret
= *((natural_width
*)p
);
7620 case VMCS_FIELD_TYPE_U16
:
7623 case VMCS_FIELD_TYPE_U32
:
7626 case VMCS_FIELD_TYPE_U64
:
7636 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7637 unsigned long field
, u64 field_value
){
7638 short offset
= vmcs_field_to_offset(field
);
7639 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7643 switch (vmcs_field_type(field
)) {
7644 case VMCS_FIELD_TYPE_U16
:
7645 *(u16
*)p
= field_value
;
7647 case VMCS_FIELD_TYPE_U32
:
7648 *(u32
*)p
= field_value
;
7650 case VMCS_FIELD_TYPE_U64
:
7651 *(u64
*)p
= field_value
;
7653 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7654 *(natural_width
*)p
= field_value
;
7663 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7666 unsigned long field
;
7668 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7669 const unsigned long *fields
= shadow_read_write_fields
;
7670 const int num_fields
= max_shadow_read_write_fields
;
7674 vmcs_load(shadow_vmcs
);
7676 for (i
= 0; i
< num_fields
; i
++) {
7678 switch (vmcs_field_type(field
)) {
7679 case VMCS_FIELD_TYPE_U16
:
7680 field_value
= vmcs_read16(field
);
7682 case VMCS_FIELD_TYPE_U32
:
7683 field_value
= vmcs_read32(field
);
7685 case VMCS_FIELD_TYPE_U64
:
7686 field_value
= vmcs_read64(field
);
7688 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7689 field_value
= vmcs_readl(field
);
7695 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7698 vmcs_clear(shadow_vmcs
);
7699 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7704 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7706 const unsigned long *fields
[] = {
7707 shadow_read_write_fields
,
7708 shadow_read_only_fields
7710 const int max_fields
[] = {
7711 max_shadow_read_write_fields
,
7712 max_shadow_read_only_fields
7715 unsigned long field
;
7716 u64 field_value
= 0;
7717 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7719 vmcs_load(shadow_vmcs
);
7721 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7722 for (i
= 0; i
< max_fields
[q
]; i
++) {
7723 field
= fields
[q
][i
];
7724 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7726 switch (vmcs_field_type(field
)) {
7727 case VMCS_FIELD_TYPE_U16
:
7728 vmcs_write16(field
, (u16
)field_value
);
7730 case VMCS_FIELD_TYPE_U32
:
7731 vmcs_write32(field
, (u32
)field_value
);
7733 case VMCS_FIELD_TYPE_U64
:
7734 vmcs_write64(field
, (u64
)field_value
);
7736 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7737 vmcs_writel(field
, (long)field_value
);
7746 vmcs_clear(shadow_vmcs
);
7747 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7751 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7752 * used before) all generate the same failure when it is missing.
7754 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7756 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7757 if (vmx
->nested
.current_vmptr
== -1ull) {
7758 nested_vmx_failInvalid(vcpu
);
7764 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7766 unsigned long field
;
7768 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7769 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7772 if (!nested_vmx_check_permission(vcpu
))
7775 if (!nested_vmx_check_vmcs12(vcpu
))
7776 return kvm_skip_emulated_instruction(vcpu
);
7778 /* Decode instruction info and find the field to read */
7779 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7780 /* Read the field, zero-extended to a u64 field_value */
7781 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7782 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7783 return kvm_skip_emulated_instruction(vcpu
);
7786 * Now copy part of this value to register or memory, as requested.
7787 * Note that the number of bits actually copied is 32 or 64 depending
7788 * on the guest's mode (32 or 64 bit), not on the given field's length.
7790 if (vmx_instruction_info
& (1u << 10)) {
7791 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7794 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7795 vmx_instruction_info
, true, &gva
))
7797 /* _system ok, as hardware has verified cpl=0 */
7798 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7799 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7802 nested_vmx_succeed(vcpu
);
7803 return kvm_skip_emulated_instruction(vcpu
);
7807 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7809 unsigned long field
;
7811 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7812 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7813 /* The value to write might be 32 or 64 bits, depending on L1's long
7814 * mode, and eventually we need to write that into a field of several
7815 * possible lengths. The code below first zero-extends the value to 64
7816 * bit (field_value), and then copies only the appropriate number of
7817 * bits into the vmcs12 field.
7819 u64 field_value
= 0;
7820 struct x86_exception e
;
7822 if (!nested_vmx_check_permission(vcpu
))
7825 if (!nested_vmx_check_vmcs12(vcpu
))
7826 return kvm_skip_emulated_instruction(vcpu
);
7828 if (vmx_instruction_info
& (1u << 10))
7829 field_value
= kvm_register_readl(vcpu
,
7830 (((vmx_instruction_info
) >> 3) & 0xf));
7832 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7833 vmx_instruction_info
, false, &gva
))
7835 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7836 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7837 kvm_inject_page_fault(vcpu
, &e
);
7843 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7844 if (vmcs_field_readonly(field
)) {
7845 nested_vmx_failValid(vcpu
,
7846 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7847 return kvm_skip_emulated_instruction(vcpu
);
7850 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7851 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7852 return kvm_skip_emulated_instruction(vcpu
);
7855 nested_vmx_succeed(vcpu
);
7856 return kvm_skip_emulated_instruction(vcpu
);
7859 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7861 vmx
->nested
.current_vmptr
= vmptr
;
7862 if (enable_shadow_vmcs
) {
7863 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7864 SECONDARY_EXEC_SHADOW_VMCS
);
7865 vmcs_write64(VMCS_LINK_POINTER
,
7866 __pa(vmx
->vmcs01
.shadow_vmcs
));
7867 vmx
->nested
.sync_shadow_vmcs
= true;
7871 /* Emulate the VMPTRLD instruction */
7872 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7874 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7877 if (!nested_vmx_check_permission(vcpu
))
7880 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7883 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7884 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7885 return kvm_skip_emulated_instruction(vcpu
);
7888 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7889 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7890 return kvm_skip_emulated_instruction(vcpu
);
7893 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7894 struct vmcs12
*new_vmcs12
;
7896 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7897 if (is_error_page(page
)) {
7898 nested_vmx_failInvalid(vcpu
);
7899 return kvm_skip_emulated_instruction(vcpu
);
7901 new_vmcs12
= kmap(page
);
7902 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7904 kvm_release_page_clean(page
);
7905 nested_vmx_failValid(vcpu
,
7906 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7907 return kvm_skip_emulated_instruction(vcpu
);
7910 nested_release_vmcs12(vmx
);
7912 * Load VMCS12 from guest memory since it is not already
7915 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7917 kvm_release_page_clean(page
);
7919 set_current_vmptr(vmx
, vmptr
);
7922 nested_vmx_succeed(vcpu
);
7923 return kvm_skip_emulated_instruction(vcpu
);
7926 /* Emulate the VMPTRST instruction */
7927 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7929 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7930 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7932 struct x86_exception e
;
7934 if (!nested_vmx_check_permission(vcpu
))
7937 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7938 vmx_instruction_info
, true, &vmcs_gva
))
7940 /* ok to use *_system, as hardware has verified cpl=0 */
7941 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7942 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7944 kvm_inject_page_fault(vcpu
, &e
);
7947 nested_vmx_succeed(vcpu
);
7948 return kvm_skip_emulated_instruction(vcpu
);
7951 /* Emulate the INVEPT instruction */
7952 static int handle_invept(struct kvm_vcpu
*vcpu
)
7954 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7955 u32 vmx_instruction_info
, types
;
7958 struct x86_exception e
;
7963 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7964 SECONDARY_EXEC_ENABLE_EPT
) ||
7965 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7966 kvm_queue_exception(vcpu
, UD_VECTOR
);
7970 if (!nested_vmx_check_permission(vcpu
))
7973 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7974 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7976 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7978 if (type
>= 32 || !(types
& (1 << type
))) {
7979 nested_vmx_failValid(vcpu
,
7980 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7981 return kvm_skip_emulated_instruction(vcpu
);
7984 /* According to the Intel VMX instruction reference, the memory
7985 * operand is read even if it isn't needed (e.g., for type==global)
7987 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7988 vmx_instruction_info
, false, &gva
))
7990 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7991 sizeof(operand
), &e
)) {
7992 kvm_inject_page_fault(vcpu
, &e
);
7997 case VMX_EPT_EXTENT_GLOBAL
:
7999 * TODO: track mappings and invalidate
8000 * single context requests appropriately
8002 case VMX_EPT_EXTENT_CONTEXT
:
8003 kvm_mmu_sync_roots(vcpu
);
8004 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
8005 nested_vmx_succeed(vcpu
);
8012 return kvm_skip_emulated_instruction(vcpu
);
8015 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
8017 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8018 u32 vmx_instruction_info
;
8019 unsigned long type
, types
;
8021 struct x86_exception e
;
8027 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
8028 SECONDARY_EXEC_ENABLE_VPID
) ||
8029 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
8030 kvm_queue_exception(vcpu
, UD_VECTOR
);
8034 if (!nested_vmx_check_permission(vcpu
))
8037 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8038 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
8040 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
8041 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
8043 if (type
>= 32 || !(types
& (1 << type
))) {
8044 nested_vmx_failValid(vcpu
,
8045 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8046 return kvm_skip_emulated_instruction(vcpu
);
8049 /* according to the intel vmx instruction reference, the memory
8050 * operand is read even if it isn't needed (e.g., for type==global)
8052 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
8053 vmx_instruction_info
, false, &gva
))
8055 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
8056 sizeof(operand
), &e
)) {
8057 kvm_inject_page_fault(vcpu
, &e
);
8060 if (operand
.vpid
>> 16) {
8061 nested_vmx_failValid(vcpu
,
8062 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8063 return kvm_skip_emulated_instruction(vcpu
);
8067 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
8068 if (is_noncanonical_address(operand
.gla
, vcpu
)) {
8069 nested_vmx_failValid(vcpu
,
8070 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8071 return kvm_skip_emulated_instruction(vcpu
);
8074 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
8075 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
8076 if (!operand
.vpid
) {
8077 nested_vmx_failValid(vcpu
,
8078 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8079 return kvm_skip_emulated_instruction(vcpu
);
8082 case VMX_VPID_EXTENT_ALL_CONTEXT
:
8086 return kvm_skip_emulated_instruction(vcpu
);
8089 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
8090 nested_vmx_succeed(vcpu
);
8092 return kvm_skip_emulated_instruction(vcpu
);
8095 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
8097 unsigned long exit_qualification
;
8099 trace_kvm_pml_full(vcpu
->vcpu_id
);
8101 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8104 * PML buffer FULL happened while executing iret from NMI,
8105 * "blocked by NMI" bit has to be set before next VM entry.
8107 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8109 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
8110 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8111 GUEST_INTR_STATE_NMI
);
8114 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8115 * here.., and there's no userspace involvement needed for PML.
8120 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
8122 kvm_lapic_expired_hv_timer(vcpu
);
8126 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
8128 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8129 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8131 /* Check for memory type validity */
8132 switch (address
& VMX_EPTP_MT_MASK
) {
8133 case VMX_EPTP_MT_UC
:
8134 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
8137 case VMX_EPTP_MT_WB
:
8138 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
8145 /* only 4 levels page-walk length are valid */
8146 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
8149 /* Reserved bits should not be set */
8150 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
8153 /* AD, if set, should be supported */
8154 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
8155 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
8162 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
8163 struct vmcs12
*vmcs12
)
8165 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8167 bool accessed_dirty
;
8168 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
8170 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
8171 !nested_cpu_has_ept(vmcs12
))
8174 if (index
>= VMFUNC_EPTP_ENTRIES
)
8178 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
8179 &address
, index
* 8, 8))
8182 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
8185 * If the (L2) guest does a vmfunc to the currently
8186 * active ept pointer, we don't have to do anything else
8188 if (vmcs12
->ept_pointer
!= address
) {
8189 if (!valid_ept_address(vcpu
, address
))
8192 kvm_mmu_unload(vcpu
);
8193 mmu
->ept_ad
= accessed_dirty
;
8194 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
8195 vmcs12
->ept_pointer
= address
;
8197 * TODO: Check what's the correct approach in case
8198 * mmu reload fails. Currently, we just let the next
8199 * reload potentially fail
8201 kvm_mmu_reload(vcpu
);
8207 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
8209 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8210 struct vmcs12
*vmcs12
;
8211 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
8214 * VMFUNC is only supported for nested guests, but we always enable the
8215 * secondary control for simplicity; for non-nested mode, fake that we
8216 * didn't by injecting #UD.
8218 if (!is_guest_mode(vcpu
)) {
8219 kvm_queue_exception(vcpu
, UD_VECTOR
);
8223 vmcs12
= get_vmcs12(vcpu
);
8224 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
8229 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
8235 return kvm_skip_emulated_instruction(vcpu
);
8238 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8239 vmcs_read32(VM_EXIT_INTR_INFO
),
8240 vmcs_readl(EXIT_QUALIFICATION
));
8245 * The exit handlers return 1 if the exit was handled fully and guest execution
8246 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8247 * to be done to userspace and return 0.
8249 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8250 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8251 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8252 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8253 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8254 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8255 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8256 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8257 [EXIT_REASON_CPUID
] = handle_cpuid
,
8258 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8259 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8260 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8261 [EXIT_REASON_HLT
] = handle_halt
,
8262 [EXIT_REASON_INVD
] = handle_invd
,
8263 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8264 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8265 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8266 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8267 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8268 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8269 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8270 [EXIT_REASON_VMREAD
] = handle_vmread
,
8271 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8272 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8273 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8274 [EXIT_REASON_VMON
] = handle_vmon
,
8275 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8276 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8277 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8278 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8279 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8280 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8281 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8282 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8283 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8284 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8285 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8286 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8287 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8288 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8289 [EXIT_REASON_INVEPT
] = handle_invept
,
8290 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8291 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
8292 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
8293 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8294 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8295 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8296 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8297 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8300 static const int kvm_vmx_max_exit_handlers
=
8301 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8303 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8304 struct vmcs12
*vmcs12
)
8306 unsigned long exit_qualification
;
8307 gpa_t bitmap
, last_bitmap
;
8312 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8313 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8315 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8317 port
= exit_qualification
>> 16;
8318 size
= (exit_qualification
& 7) + 1;
8320 last_bitmap
= (gpa_t
)-1;
8325 bitmap
= vmcs12
->io_bitmap_a
;
8326 else if (port
< 0x10000)
8327 bitmap
= vmcs12
->io_bitmap_b
;
8330 bitmap
+= (port
& 0x7fff) / 8;
8332 if (last_bitmap
!= bitmap
)
8333 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8335 if (b
& (1 << (port
& 7)))
8340 last_bitmap
= bitmap
;
8347 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8348 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8349 * disinterest in the current event (read or write a specific MSR) by using an
8350 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8352 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8353 struct vmcs12
*vmcs12
, u32 exit_reason
)
8355 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8358 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8362 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8363 * for the four combinations of read/write and low/high MSR numbers.
8364 * First we need to figure out which of the four to use:
8366 bitmap
= vmcs12
->msr_bitmap
;
8367 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8369 if (msr_index
>= 0xc0000000) {
8370 msr_index
-= 0xc0000000;
8374 /* Then read the msr_index'th bit from this bitmap: */
8375 if (msr_index
< 1024*8) {
8377 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8379 return 1 & (b
>> (msr_index
& 7));
8381 return true; /* let L1 handle the wrong parameter */
8385 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8386 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8387 * intercept (via guest_host_mask etc.) the current event.
8389 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8390 struct vmcs12
*vmcs12
)
8392 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8393 int cr
= exit_qualification
& 15;
8397 switch ((exit_qualification
>> 4) & 3) {
8398 case 0: /* mov to cr */
8399 reg
= (exit_qualification
>> 8) & 15;
8400 val
= kvm_register_readl(vcpu
, reg
);
8403 if (vmcs12
->cr0_guest_host_mask
&
8404 (val
^ vmcs12
->cr0_read_shadow
))
8408 if ((vmcs12
->cr3_target_count
>= 1 &&
8409 vmcs12
->cr3_target_value0
== val
) ||
8410 (vmcs12
->cr3_target_count
>= 2 &&
8411 vmcs12
->cr3_target_value1
== val
) ||
8412 (vmcs12
->cr3_target_count
>= 3 &&
8413 vmcs12
->cr3_target_value2
== val
) ||
8414 (vmcs12
->cr3_target_count
>= 4 &&
8415 vmcs12
->cr3_target_value3
== val
))
8417 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8421 if (vmcs12
->cr4_guest_host_mask
&
8422 (vmcs12
->cr4_read_shadow
^ val
))
8426 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8432 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8433 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8436 case 1: /* mov from cr */
8439 if (vmcs12
->cpu_based_vm_exec_control
&
8440 CPU_BASED_CR3_STORE_EXITING
)
8444 if (vmcs12
->cpu_based_vm_exec_control
&
8445 CPU_BASED_CR8_STORE_EXITING
)
8452 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8453 * cr0. Other attempted changes are ignored, with no exit.
8455 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8456 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8457 (val
^ vmcs12
->cr0_read_shadow
))
8459 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8460 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8469 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8470 * should handle it ourselves in L0 (and then continue L2). Only call this
8471 * when in is_guest_mode (L2).
8473 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8475 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8476 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8477 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8479 if (vmx
->nested
.nested_run_pending
)
8482 if (unlikely(vmx
->fail
)) {
8483 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8484 vmcs_read32(VM_INSTRUCTION_ERROR
));
8489 * The host physical addresses of some pages of guest memory
8490 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8491 * Page). The CPU may write to these pages via their host
8492 * physical address while L2 is running, bypassing any
8493 * address-translation-based dirty tracking (e.g. EPT write
8496 * Mark them dirty on every exit from L2 to prevent them from
8497 * getting out of sync with dirty tracking.
8499 nested_mark_vmcs12_pages_dirty(vcpu
);
8501 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8502 vmcs_readl(EXIT_QUALIFICATION
),
8503 vmx
->idt_vectoring_info
,
8505 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8508 switch (exit_reason
) {
8509 case EXIT_REASON_EXCEPTION_NMI
:
8510 if (is_nmi(intr_info
))
8512 else if (is_page_fault(intr_info
))
8513 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8514 else if (is_no_device(intr_info
) &&
8515 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8517 else if (is_debug(intr_info
) &&
8519 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8521 else if (is_breakpoint(intr_info
) &&
8522 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8524 return vmcs12
->exception_bitmap
&
8525 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8526 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8528 case EXIT_REASON_TRIPLE_FAULT
:
8530 case EXIT_REASON_PENDING_INTERRUPT
:
8531 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8532 case EXIT_REASON_NMI_WINDOW
:
8533 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8534 case EXIT_REASON_TASK_SWITCH
:
8536 case EXIT_REASON_CPUID
:
8538 case EXIT_REASON_HLT
:
8539 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8540 case EXIT_REASON_INVD
:
8542 case EXIT_REASON_INVLPG
:
8543 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8544 case EXIT_REASON_RDPMC
:
8545 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8546 case EXIT_REASON_RDRAND
:
8547 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND_EXITING
);
8548 case EXIT_REASON_RDSEED
:
8549 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED_EXITING
);
8550 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8551 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8552 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8553 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8554 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8555 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8556 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8557 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8559 * VMX instructions trap unconditionally. This allows L1 to
8560 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8563 case EXIT_REASON_CR_ACCESS
:
8564 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8565 case EXIT_REASON_DR_ACCESS
:
8566 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8567 case EXIT_REASON_IO_INSTRUCTION
:
8568 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8569 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8570 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8571 case EXIT_REASON_MSR_READ
:
8572 case EXIT_REASON_MSR_WRITE
:
8573 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8574 case EXIT_REASON_INVALID_STATE
:
8576 case EXIT_REASON_MWAIT_INSTRUCTION
:
8577 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8578 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8579 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8580 case EXIT_REASON_MONITOR_INSTRUCTION
:
8581 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8582 case EXIT_REASON_PAUSE_INSTRUCTION
:
8583 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8584 nested_cpu_has2(vmcs12
,
8585 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8586 case EXIT_REASON_MCE_DURING_VMENTRY
:
8588 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8589 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8590 case EXIT_REASON_APIC_ACCESS
:
8591 return nested_cpu_has2(vmcs12
,
8592 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8593 case EXIT_REASON_APIC_WRITE
:
8594 case EXIT_REASON_EOI_INDUCED
:
8595 /* apic_write and eoi_induced should exit unconditionally. */
8597 case EXIT_REASON_EPT_VIOLATION
:
8599 * L0 always deals with the EPT violation. If nested EPT is
8600 * used, and the nested mmu code discovers that the address is
8601 * missing in the guest EPT table (EPT12), the EPT violation
8602 * will be injected with nested_ept_inject_page_fault()
8605 case EXIT_REASON_EPT_MISCONFIG
:
8607 * L2 never uses directly L1's EPT, but rather L0's own EPT
8608 * table (shadow on EPT) or a merged EPT table that L0 built
8609 * (EPT on EPT). So any problems with the structure of the
8610 * table is L0's fault.
8613 case EXIT_REASON_INVPCID
:
8615 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8616 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8617 case EXIT_REASON_WBINVD
:
8618 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8619 case EXIT_REASON_XSETBV
:
8621 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8623 * This should never happen, since it is not possible to
8624 * set XSS to a non-zero value---neither in L1 nor in L2.
8625 * If if it were, XSS would have to be checked against
8626 * the XSS exit bitmap in vmcs12.
8628 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8629 case EXIT_REASON_PREEMPTION_TIMER
:
8631 case EXIT_REASON_PML_FULL
:
8632 /* We emulate PML support to L1. */
8634 case EXIT_REASON_VMFUNC
:
8635 /* VM functions are emulated through L2->L0 vmexits. */
8642 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8644 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8647 * At this point, the exit interruption info in exit_intr_info
8648 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8649 * we need to query the in-kernel LAPIC.
8651 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8652 if ((exit_intr_info
&
8653 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8654 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8655 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8656 vmcs12
->vm_exit_intr_error_code
=
8657 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8660 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8661 vmcs_readl(EXIT_QUALIFICATION
));
8665 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8667 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8668 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8671 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8674 __free_page(vmx
->pml_pg
);
8679 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8681 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8685 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8687 /* Do nothing if PML buffer is empty */
8688 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8691 /* PML index always points to next available PML buffer entity */
8692 if (pml_idx
>= PML_ENTITY_NUM
)
8697 pml_buf
= page_address(vmx
->pml_pg
);
8698 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8701 gpa
= pml_buf
[pml_idx
];
8702 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8703 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8706 /* reset PML index */
8707 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8711 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8712 * Called before reporting dirty_bitmap to userspace.
8714 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8717 struct kvm_vcpu
*vcpu
;
8719 * We only need to kick vcpu out of guest mode here, as PML buffer
8720 * is flushed at beginning of all VMEXITs, and it's obvious that only
8721 * vcpus running in guest are possible to have unflushed GPAs in PML
8724 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8725 kvm_vcpu_kick(vcpu
);
8728 static void vmx_dump_sel(char *name
, uint32_t sel
)
8730 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8731 name
, vmcs_read16(sel
),
8732 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8733 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8734 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8737 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8739 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8740 name
, vmcs_read32(limit
),
8741 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8744 static void dump_vmcs(void)
8746 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8747 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8748 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8749 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8750 u32 secondary_exec_control
= 0;
8751 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8752 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8755 if (cpu_has_secondary_exec_ctrls())
8756 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8758 pr_err("*** Guest State ***\n");
8759 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8760 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8761 vmcs_readl(CR0_GUEST_HOST_MASK
));
8762 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8763 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8764 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8765 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8766 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8768 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8769 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8770 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8771 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8773 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8774 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8775 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8776 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8777 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8778 vmcs_readl(GUEST_SYSENTER_ESP
),
8779 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8780 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8781 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8782 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8783 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8784 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8785 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8786 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8787 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8788 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8789 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8790 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8791 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8792 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8793 efer
, vmcs_read64(GUEST_IA32_PAT
));
8794 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8795 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8796 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8797 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8798 pr_err("PerfGlobCtl = 0x%016llx\n",
8799 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8800 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8801 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8802 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8803 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8804 vmcs_read32(GUEST_ACTIVITY_STATE
));
8805 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8806 pr_err("InterruptStatus = %04x\n",
8807 vmcs_read16(GUEST_INTR_STATUS
));
8809 pr_err("*** Host State ***\n");
8810 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8811 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8812 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8813 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8814 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8815 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8816 vmcs_read16(HOST_TR_SELECTOR
));
8817 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8818 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8819 vmcs_readl(HOST_TR_BASE
));
8820 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8821 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8822 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8823 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8824 vmcs_readl(HOST_CR4
));
8825 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8826 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8827 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8828 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8829 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8830 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8831 vmcs_read64(HOST_IA32_EFER
),
8832 vmcs_read64(HOST_IA32_PAT
));
8833 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8834 pr_err("PerfGlobCtl = 0x%016llx\n",
8835 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8837 pr_err("*** Control State ***\n");
8838 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8839 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8840 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8841 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8842 vmcs_read32(EXCEPTION_BITMAP
),
8843 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8844 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8845 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8846 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8847 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8848 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8849 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8850 vmcs_read32(VM_EXIT_INTR_INFO
),
8851 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8852 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8853 pr_err(" reason=%08x qualification=%016lx\n",
8854 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8855 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8856 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8857 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8858 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8859 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8860 pr_err("TSC Multiplier = 0x%016llx\n",
8861 vmcs_read64(TSC_MULTIPLIER
));
8862 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8863 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8864 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8865 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8866 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8867 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8868 n
= vmcs_read32(CR3_TARGET_COUNT
);
8869 for (i
= 0; i
+ 1 < n
; i
+= 4)
8870 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8871 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8872 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8874 pr_err("CR3 target%u=%016lx\n",
8875 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8876 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8877 pr_err("PLE Gap=%08x Window=%08x\n",
8878 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8879 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8880 pr_err("Virtual processor ID = 0x%04x\n",
8881 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8885 * The guest has exited. See if we can fix it or if we need userspace
8888 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8890 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8891 u32 exit_reason
= vmx
->exit_reason
;
8892 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8894 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8897 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8898 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8899 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8900 * mode as if vcpus is in root mode, the PML buffer must has been
8904 vmx_flush_pml_buffer(vcpu
);
8906 /* If guest state is invalid, start emulating */
8907 if (vmx
->emulation_required
)
8908 return handle_invalid_guest_state(vcpu
);
8910 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8911 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8913 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8915 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8916 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8921 if (unlikely(vmx
->fail
)) {
8922 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8923 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8924 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8930 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8931 * delivery event since it indicates guest is accessing MMIO.
8932 * The vm-exit can be triggered again after return to guest that
8933 * will cause infinite loop.
8935 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8936 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8937 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8938 exit_reason
!= EXIT_REASON_PML_FULL
&&
8939 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8940 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8941 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8942 vcpu
->run
->internal
.ndata
= 3;
8943 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8944 vcpu
->run
->internal
.data
[1] = exit_reason
;
8945 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8946 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8947 vcpu
->run
->internal
.ndata
++;
8948 vcpu
->run
->internal
.data
[3] =
8949 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8954 if (unlikely(!enable_vnmi
&&
8955 vmx
->loaded_vmcs
->soft_vnmi_blocked
)) {
8956 if (vmx_interrupt_allowed(vcpu
)) {
8957 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8958 } else if (vmx
->loaded_vmcs
->vnmi_blocked_time
> 1000000000LL &&
8959 vcpu
->arch
.nmi_pending
) {
8961 * This CPU don't support us in finding the end of an
8962 * NMI-blocked window if the guest runs with IRQs
8963 * disabled. So we pull the trigger after 1 s of
8964 * futile waiting, but inform the user about this.
8966 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8967 "state on VCPU %d after 1 s timeout\n",
8968 __func__
, vcpu
->vcpu_id
);
8969 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8973 if (exit_reason
< kvm_vmx_max_exit_handlers
8974 && kvm_vmx_exit_handlers
[exit_reason
])
8975 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8977 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8979 kvm_queue_exception(vcpu
, UD_VECTOR
);
8984 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8986 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8988 if (is_guest_mode(vcpu
) &&
8989 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8992 if (irr
== -1 || tpr
< irr
) {
8993 vmcs_write32(TPR_THRESHOLD
, 0);
8997 vmcs_write32(TPR_THRESHOLD
, irr
);
9000 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
9002 u32 sec_exec_control
;
9004 /* Postpone execution until vmcs01 is the current VMCS. */
9005 if (is_guest_mode(vcpu
)) {
9006 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
9010 if (!cpu_has_vmx_virtualize_x2apic_mode())
9013 if (!cpu_need_tpr_shadow(vcpu
))
9016 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9019 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9020 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
9022 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
9023 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9024 vmx_flush_tlb_ept_only(vcpu
);
9026 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
9028 vmx_update_msr_bitmap(vcpu
);
9031 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
9033 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9036 * Currently we do not handle the nested case where L2 has an
9037 * APIC access page of its own; that page is still pinned.
9038 * Hence, we skip the case where the VCPU is in guest mode _and_
9039 * L1 prepared an APIC access page for L2.
9041 * For the case where L1 and L2 share the same APIC access page
9042 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
9043 * in the vmcs12), this function will only update either the vmcs01
9044 * or the vmcs02. If the former, the vmcs02 will be updated by
9045 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
9046 * the next L2->L1 exit.
9048 if (!is_guest_mode(vcpu
) ||
9049 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
9050 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9051 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9052 vmx_flush_tlb_ept_only(vcpu
);
9056 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
9064 status
= vmcs_read16(GUEST_INTR_STATUS
);
9066 if (max_isr
!= old
) {
9068 status
|= max_isr
<< 8;
9069 vmcs_write16(GUEST_INTR_STATUS
, status
);
9073 static void vmx_set_rvi(int vector
)
9081 status
= vmcs_read16(GUEST_INTR_STATUS
);
9082 old
= (u8
)status
& 0xff;
9083 if ((u8
)vector
!= old
) {
9085 status
|= (u8
)vector
;
9086 vmcs_write16(GUEST_INTR_STATUS
, status
);
9090 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
9092 if (!is_guest_mode(vcpu
)) {
9093 vmx_set_rvi(max_irr
);
9101 * In guest mode. If a vmexit is needed, vmx_check_nested_events
9104 if (nested_exit_on_intr(vcpu
))
9108 * Else, fall back to pre-APICv interrupt injection since L2
9109 * is run without virtual interrupt delivery.
9111 if (!kvm_event_needs_reinjection(vcpu
) &&
9112 vmx_interrupt_allowed(vcpu
)) {
9113 kvm_queue_interrupt(vcpu
, max_irr
, false);
9114 vmx_inject_irq(vcpu
);
9118 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
9120 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9123 WARN_ON(!vcpu
->arch
.apicv_active
);
9124 if (pi_test_on(&vmx
->pi_desc
)) {
9125 pi_clear_on(&vmx
->pi_desc
);
9127 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9128 * But on x86 this is just a compiler barrier anyway.
9130 smp_mb__after_atomic();
9131 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
9133 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
9135 vmx_hwapic_irr_update(vcpu
, max_irr
);
9139 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
9141 if (!kvm_vcpu_apicv_active(vcpu
))
9144 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
9145 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
9146 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
9147 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
9150 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
9152 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9154 pi_clear_on(&vmx
->pi_desc
);
9155 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
9158 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
9160 u32 exit_intr_info
= 0;
9161 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
9163 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
9164 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
9167 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9168 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9169 vmx
->exit_intr_info
= exit_intr_info
;
9171 /* if exit due to PF check for async PF */
9172 if (is_page_fault(exit_intr_info
))
9173 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
9175 /* Handle machine checks before interrupts are enabled */
9176 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
9177 is_machine_check(exit_intr_info
))
9178 kvm_machine_check();
9180 /* We need to handle NMIs before interrupts are enabled */
9181 if (is_nmi(exit_intr_info
)) {
9182 kvm_before_handle_nmi(&vmx
->vcpu
);
9184 kvm_after_handle_nmi(&vmx
->vcpu
);
9188 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
9190 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9192 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
9193 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
9194 unsigned int vector
;
9195 unsigned long entry
;
9197 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9198 #ifdef CONFIG_X86_64
9202 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9203 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
9204 entry
= gate_offset(desc
);
9206 #ifdef CONFIG_X86_64
9207 "mov %%" _ASM_SP
", %[sp]\n\t"
9208 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
9213 __ASM_SIZE(push
) " $%c[cs]\n\t"
9216 #ifdef CONFIG_X86_64
9221 THUNK_TARGET(entry
),
9222 [ss
]"i"(__KERNEL_DS
),
9223 [cs
]"i"(__KERNEL_CS
)
9227 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
9229 static bool vmx_has_emulated_msr(int index
)
9232 case MSR_IA32_SMBASE
:
9234 * We cannot do SMM unless we can run the guest in big
9237 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
9238 case MSR_AMD64_VIRT_SPEC_CTRL
:
9239 /* This is AMD only. */
9246 static bool vmx_mpx_supported(void)
9248 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
9249 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
9252 static bool vmx_xsaves_supported(void)
9254 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9255 SECONDARY_EXEC_XSAVES
;
9258 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
9263 bool idtv_info_valid
;
9265 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9268 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9271 * Can't use vmx->exit_intr_info since we're not sure what
9272 * the exit reason is.
9274 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9275 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9276 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9278 * SDM 3: 27.7.1.2 (September 2008)
9279 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9280 * a guest IRET fault.
9281 * SDM 3: 23.2.2 (September 2008)
9282 * Bit 12 is undefined in any of the following cases:
9283 * If the VM exit sets the valid bit in the IDT-vectoring
9284 * information field.
9285 * If the VM exit is due to a double fault.
9287 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9288 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9289 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9290 GUEST_INTR_STATE_NMI
);
9292 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9293 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9294 & GUEST_INTR_STATE_NMI
);
9295 } else if (unlikely(vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9296 vmx
->loaded_vmcs
->vnmi_blocked_time
+=
9297 ktime_to_ns(ktime_sub(ktime_get(),
9298 vmx
->loaded_vmcs
->entry_time
));
9301 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9302 u32 idt_vectoring_info
,
9303 int instr_len_field
,
9304 int error_code_field
)
9308 bool idtv_info_valid
;
9310 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9312 vcpu
->arch
.nmi_injected
= false;
9313 kvm_clear_exception_queue(vcpu
);
9314 kvm_clear_interrupt_queue(vcpu
);
9316 if (!idtv_info_valid
)
9319 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9321 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9322 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9325 case INTR_TYPE_NMI_INTR
:
9326 vcpu
->arch
.nmi_injected
= true;
9328 * SDM 3: 27.7.1.2 (September 2008)
9329 * Clear bit "block by NMI" before VM entry if a NMI
9332 vmx_set_nmi_mask(vcpu
, false);
9334 case INTR_TYPE_SOFT_EXCEPTION
:
9335 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9337 case INTR_TYPE_HARD_EXCEPTION
:
9338 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9339 u32 err
= vmcs_read32(error_code_field
);
9340 kvm_requeue_exception_e(vcpu
, vector
, err
);
9342 kvm_requeue_exception(vcpu
, vector
);
9344 case INTR_TYPE_SOFT_INTR
:
9345 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9347 case INTR_TYPE_EXT_INTR
:
9348 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9355 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9357 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9358 VM_EXIT_INSTRUCTION_LEN
,
9359 IDT_VECTORING_ERROR_CODE
);
9362 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9364 __vmx_complete_interrupts(vcpu
,
9365 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9366 VM_ENTRY_INSTRUCTION_LEN
,
9367 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9369 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9372 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9375 struct perf_guest_switch_msr
*msrs
;
9377 msrs
= perf_guest_get_msrs(&nr_msrs
);
9382 for (i
= 0; i
< nr_msrs
; i
++)
9383 if (msrs
[i
].host
== msrs
[i
].guest
)
9384 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9386 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9390 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9392 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9396 if (vmx
->hv_deadline_tsc
== -1)
9400 if (vmx
->hv_deadline_tsc
> tscl
)
9401 /* sure to be 32 bit only because checked on set_hv_timer */
9402 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9403 cpu_preemption_timer_multi
);
9407 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9410 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9412 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9413 unsigned long debugctlmsr
, cr3
, cr4
;
9415 /* Record the guest's net vcpu time for enforced NMI injections. */
9416 if (unlikely(!enable_vnmi
&&
9417 vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9418 vmx
->loaded_vmcs
->entry_time
= ktime_get();
9420 /* Don't enter VMX if guest state is invalid, let the exit handler
9421 start emulation until we arrive back to a valid state */
9422 if (vmx
->emulation_required
)
9425 if (vmx
->ple_window_dirty
) {
9426 vmx
->ple_window_dirty
= false;
9427 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9430 if (vmx
->nested
.sync_shadow_vmcs
) {
9431 copy_vmcs12_to_shadow(vmx
);
9432 vmx
->nested
.sync_shadow_vmcs
= false;
9435 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9436 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9437 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9438 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9440 cr3
= __get_current_cr3_fast();
9441 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9442 vmcs_writel(HOST_CR3
, cr3
);
9443 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9446 cr4
= cr4_read_shadow();
9447 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9448 vmcs_writel(HOST_CR4
, cr4
);
9449 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9452 /* When single-stepping over STI and MOV SS, we must clear the
9453 * corresponding interruptibility bits in the guest state. Otherwise
9454 * vmentry fails as it then expects bit 14 (BS) in pending debug
9455 * exceptions being set, but that's not correct for the guest debugging
9457 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9458 vmx_set_interrupt_shadow(vcpu
, 0);
9460 if (static_cpu_has(X86_FEATURE_PKU
) &&
9461 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9462 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9463 __write_pkru(vcpu
->arch
.pkru
);
9465 atomic_switch_perf_msrs(vmx
);
9466 debugctlmsr
= get_debugctlmsr();
9468 vmx_arm_hv_timer(vcpu
);
9471 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9472 * it's non-zero. Since vmentry is serialising on affected CPUs, there
9473 * is no need to worry about the conditional branch over the wrmsr
9474 * being speculatively taken.
9476 x86_spec_ctrl_set_guest(vmx
->spec_ctrl
, 0);
9478 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9480 /* Store host registers */
9481 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9482 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9483 "push %%" _ASM_CX
" \n\t"
9484 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9486 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9487 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9489 /* Reload cr2 if changed */
9490 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9491 "mov %%cr2, %%" _ASM_DX
" \n\t"
9492 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9494 "mov %%" _ASM_AX
", %%cr2 \n\t"
9496 /* Check if vmlaunch of vmresume is needed */
9497 "cmpl $0, %c[launched](%0) \n\t"
9498 /* Load guest registers. Don't clobber flags. */
9499 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9500 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9501 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9502 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9503 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9504 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9505 #ifdef CONFIG_X86_64
9506 "mov %c[r8](%0), %%r8 \n\t"
9507 "mov %c[r9](%0), %%r9 \n\t"
9508 "mov %c[r10](%0), %%r10 \n\t"
9509 "mov %c[r11](%0), %%r11 \n\t"
9510 "mov %c[r12](%0), %%r12 \n\t"
9511 "mov %c[r13](%0), %%r13 \n\t"
9512 "mov %c[r14](%0), %%r14 \n\t"
9513 "mov %c[r15](%0), %%r15 \n\t"
9515 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9517 /* Enter guest mode */
9519 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9521 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9523 /* Save guest registers, load host registers, keep flags */
9524 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9526 "setbe %c[fail](%0)\n\t"
9527 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9528 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9529 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9530 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9531 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9532 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9533 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9534 #ifdef CONFIG_X86_64
9535 "mov %%r8, %c[r8](%0) \n\t"
9536 "mov %%r9, %c[r9](%0) \n\t"
9537 "mov %%r10, %c[r10](%0) \n\t"
9538 "mov %%r11, %c[r11](%0) \n\t"
9539 "mov %%r12, %c[r12](%0) \n\t"
9540 "mov %%r13, %c[r13](%0) \n\t"
9541 "mov %%r14, %c[r14](%0) \n\t"
9542 "mov %%r15, %c[r15](%0) \n\t"
9543 "xor %%r8d, %%r8d \n\t"
9544 "xor %%r9d, %%r9d \n\t"
9545 "xor %%r10d, %%r10d \n\t"
9546 "xor %%r11d, %%r11d \n\t"
9547 "xor %%r12d, %%r12d \n\t"
9548 "xor %%r13d, %%r13d \n\t"
9549 "xor %%r14d, %%r14d \n\t"
9550 "xor %%r15d, %%r15d \n\t"
9552 "mov %%cr2, %%" _ASM_AX
" \n\t"
9553 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9555 "xor %%eax, %%eax \n\t"
9556 "xor %%ebx, %%ebx \n\t"
9557 "xor %%esi, %%esi \n\t"
9558 "xor %%edi, %%edi \n\t"
9559 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9560 ".pushsection .rodata \n\t"
9561 ".global vmx_return \n\t"
9562 "vmx_return: " _ASM_PTR
" 2b \n\t"
9564 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9565 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9566 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9567 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9568 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9569 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9570 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9571 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9572 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9573 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9574 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9575 #ifdef CONFIG_X86_64
9576 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9577 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9578 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9579 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9580 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9581 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9582 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9583 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9585 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9586 [wordsize
]"i"(sizeof(ulong
))
9588 #ifdef CONFIG_X86_64
9589 , "rax", "rbx", "rdi", "rsi"
9590 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9592 , "eax", "ebx", "edi", "esi"
9597 * We do not use IBRS in the kernel. If this vCPU has used the
9598 * SPEC_CTRL MSR it may have left it on; save the value and
9599 * turn it off. This is much more efficient than blindly adding
9600 * it to the atomic save/restore list. Especially as the former
9601 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9603 * For non-nested case:
9604 * If the L01 MSR bitmap does not intercept the MSR, then we need to
9608 * If the L02 MSR bitmap does not intercept the MSR, then we need to
9611 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
9612 vmx
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
9614 x86_spec_ctrl_restore_host(vmx
->spec_ctrl
, 0);
9616 /* Eliminate branch target predictions from guest mode */
9619 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9621 update_debugctlmsr(debugctlmsr
);
9623 #ifndef CONFIG_X86_64
9625 * The sysexit path does not restore ds/es, so we must set them to
9626 * a reasonable value ourselves.
9628 * We can't defer this to vmx_load_host_state() since that function
9629 * may be executed in interrupt context, which saves and restore segments
9630 * around it, nullifying its effect.
9632 loadsegment(ds
, __USER_DS
);
9633 loadsegment(es
, __USER_DS
);
9636 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9637 | (1 << VCPU_EXREG_RFLAGS
)
9638 | (1 << VCPU_EXREG_PDPTR
)
9639 | (1 << VCPU_EXREG_SEGMENTS
)
9640 | (1 << VCPU_EXREG_CR3
));
9641 vcpu
->arch
.regs_dirty
= 0;
9644 * eager fpu is enabled if PKEY is supported and CR4 is switched
9645 * back on host, so it is safe to read guest PKRU from current
9648 if (static_cpu_has(X86_FEATURE_PKU
) &&
9649 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9650 vcpu
->arch
.pkru
= __read_pkru();
9651 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9652 __write_pkru(vmx
->host_pkru
);
9656 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9657 * we did not inject a still-pending event to L1 now because of
9658 * nested_run_pending, we need to re-enable this bit.
9660 if (vmx
->nested
.nested_run_pending
)
9661 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9663 vmx
->nested
.nested_run_pending
= 0;
9664 vmx
->idt_vectoring_info
= 0;
9666 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
9667 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9670 vmx
->loaded_vmcs
->launched
= 1;
9671 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9673 vmx_complete_atomic_exit(vmx
);
9674 vmx_recover_nmi_blocking(vmx
);
9675 vmx_complete_interrupts(vmx
);
9677 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9679 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9681 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9684 if (vmx
->loaded_vmcs
== vmcs
)
9688 vmx
->loaded_vmcs
= vmcs
;
9690 vmx_vcpu_load(vcpu
, cpu
);
9695 * Ensure that the current vmcs of the logical processor is the
9696 * vmcs01 of the vcpu before calling free_nested().
9698 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9700 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9703 r
= vcpu_load(vcpu
);
9705 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9710 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9712 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9715 vmx_destroy_pml_buffer(vmx
);
9716 free_vpid(vmx
->vpid
);
9717 leave_guest_mode(vcpu
);
9718 vmx_free_vcpu_nested(vcpu
);
9719 free_loaded_vmcs(vmx
->loaded_vmcs
);
9720 kfree(vmx
->guest_msrs
);
9721 kvm_vcpu_uninit(vcpu
);
9722 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9725 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9728 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9729 unsigned long *msr_bitmap
;
9733 return ERR_PTR(-ENOMEM
);
9735 vmx
->vpid
= allocate_vpid();
9737 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9744 * If PML is turned on, failure on enabling PML just results in failure
9745 * of creating the vcpu, therefore we can simplify PML logic (by
9746 * avoiding dealing with cases, such as enabling PML partially on vcpus
9747 * for the guest, etc.
9750 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9755 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9756 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9759 if (!vmx
->guest_msrs
)
9762 err
= alloc_loaded_vmcs(&vmx
->vmcs01
);
9766 msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
9767 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_FS_BASE
, MSR_TYPE_RW
);
9768 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_GS_BASE
, MSR_TYPE_RW
);
9769 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_KERNEL_GS_BASE
, MSR_TYPE_RW
);
9770 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_CS
, MSR_TYPE_RW
);
9771 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_ESP
, MSR_TYPE_RW
);
9772 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_EIP
, MSR_TYPE_RW
);
9773 vmx
->msr_bitmap_mode
= 0;
9775 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9777 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9778 vmx
->vcpu
.cpu
= cpu
;
9779 vmx_vcpu_setup(vmx
);
9780 vmx_vcpu_put(&vmx
->vcpu
);
9782 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9783 err
= alloc_apic_access_page(kvm
);
9789 err
= init_rmode_identity_map(kvm
);
9795 nested_vmx_setup_ctls_msrs(vmx
);
9796 vmx
->nested
.vpid02
= allocate_vpid();
9799 vmx
->nested
.posted_intr_nv
= -1;
9800 vmx
->nested
.current_vmptr
= -1ull;
9802 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9805 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9806 * or POSTED_INTR_WAKEUP_VECTOR.
9808 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9809 vmx
->pi_desc
.sn
= 1;
9814 free_vpid(vmx
->nested
.vpid02
);
9815 free_loaded_vmcs(vmx
->loaded_vmcs
);
9817 kfree(vmx
->guest_msrs
);
9819 vmx_destroy_pml_buffer(vmx
);
9821 kvm_vcpu_uninit(&vmx
->vcpu
);
9823 free_vpid(vmx
->vpid
);
9824 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9825 return ERR_PTR(err
);
9828 static void __init
vmx_check_processor_compat(void *rtn
)
9830 struct vmcs_config vmcs_conf
;
9833 if (setup_vmcs_config(&vmcs_conf
) < 0)
9835 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9836 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9837 smp_processor_id());
9842 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9847 /* For VT-d and EPT combination
9848 * 1. MMIO: always map as UC
9850 * a. VT-d without snooping control feature: can't guarantee the
9851 * result, try to trust guest.
9852 * b. VT-d with snooping control feature: snooping control feature of
9853 * VT-d engine can guarantee the cache correctness. Just set it
9854 * to WB to keep consistent with host. So the same as item 3.
9855 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9856 * consistent with host MTRR
9859 cache
= MTRR_TYPE_UNCACHABLE
;
9863 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9864 ipat
= VMX_EPT_IPAT_BIT
;
9865 cache
= MTRR_TYPE_WRBACK
;
9869 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9870 ipat
= VMX_EPT_IPAT_BIT
;
9871 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9872 cache
= MTRR_TYPE_WRBACK
;
9874 cache
= MTRR_TYPE_UNCACHABLE
;
9878 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9881 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9884 static int vmx_get_lpage_level(void)
9886 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9887 return PT_DIRECTORY_LEVEL
;
9889 /* For shadow and EPT supported 1GB page */
9890 return PT_PDPE_LEVEL
;
9893 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9896 * These bits in the secondary execution controls field
9897 * are dynamic, the others are mostly based on the hypervisor
9898 * architecture and the guest's CPUID. Do not touch the
9902 SECONDARY_EXEC_SHADOW_VMCS
|
9903 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9904 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9906 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9908 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9909 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9913 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9914 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9916 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9918 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9919 struct kvm_cpuid_entry2
*entry
;
9921 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9922 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9924 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9925 if (entry && (entry->_reg & (_cpuid_mask))) \
9926 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9929 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9930 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9931 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9932 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9933 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9934 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9935 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9936 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9937 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9938 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9939 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9940 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9941 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9942 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9943 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9945 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9946 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9947 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9948 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9949 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9950 cr4_fixed1_update(X86_CR4_UMIP
, ecx
, bit(X86_FEATURE_UMIP
));
9952 #undef cr4_fixed1_update
9955 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9957 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9959 if (cpu_has_secondary_exec_ctrls()) {
9960 vmx_compute_secondary_exec_control(vmx
);
9961 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9964 if (nested_vmx_allowed(vcpu
))
9965 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9966 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9968 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9969 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9971 if (nested_vmx_allowed(vcpu
))
9972 nested_vmx_cr_fixed1_bits_update(vcpu
);
9975 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9977 if (func
== 1 && nested
)
9978 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9981 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9982 struct x86_exception
*fault
)
9984 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9985 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9987 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9989 if (vmx
->nested
.pml_full
) {
9990 exit_reason
= EXIT_REASON_PML_FULL
;
9991 vmx
->nested
.pml_full
= false;
9992 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9993 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9994 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9996 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9998 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9999 vmcs12
->guest_physical_address
= fault
->address
;
10002 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
10004 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
10007 /* Callbacks for nested_ept_init_mmu_context: */
10009 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
10011 /* return the page table to be shadowed - in our case, EPT12 */
10012 return get_vmcs12(vcpu
)->ept_pointer
;
10015 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
10017 WARN_ON(mmu_is_nested(vcpu
));
10018 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
10021 kvm_mmu_unload(vcpu
);
10022 kvm_init_shadow_ept_mmu(vcpu
,
10023 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
10024 VMX_EPT_EXECUTE_ONLY_BIT
,
10025 nested_ept_ad_enabled(vcpu
));
10026 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
10027 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
10028 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
10030 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
10034 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
10036 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
10039 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
10042 bool inequality
, bit
;
10044 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
10046 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
10047 vmcs12
->page_fault_error_code_match
;
10048 return inequality
^ bit
;
10051 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
10052 struct x86_exception
*fault
)
10054 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10056 WARN_ON(!is_guest_mode(vcpu
));
10058 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
) &&
10059 !to_vmx(vcpu
)->nested
.nested_run_pending
) {
10060 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
10061 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10062 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
10063 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
10066 kvm_inject_page_fault(vcpu
, fault
);
10070 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10071 struct vmcs12
*vmcs12
);
10073 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
10074 struct vmcs12
*vmcs12
)
10076 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10080 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10082 * Translate L1 physical address to host physical
10083 * address for vmcs02. Keep the page pinned, so this
10084 * physical address remains valid. We keep a reference
10085 * to it so we can release it later.
10087 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
10088 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
10089 vmx
->nested
.apic_access_page
= NULL
;
10091 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
10093 * If translation failed, no matter: This feature asks
10094 * to exit when accessing the given address, and if it
10095 * can never be accessed, this feature won't do
10098 if (!is_error_page(page
)) {
10099 vmx
->nested
.apic_access_page
= page
;
10100 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
10101 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
10103 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
10104 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
10106 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
10107 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
10108 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
10109 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
10110 kvm_vcpu_reload_apic_access_page(vcpu
);
10113 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
10114 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
10115 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
10116 vmx
->nested
.virtual_apic_page
= NULL
;
10118 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
10121 * If translation failed, VM entry will fail because
10122 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10123 * Failing the vm entry is _not_ what the processor
10124 * does but it's basically the only possibility we
10125 * have. We could still enter the guest if CR8 load
10126 * exits are enabled, CR8 store exits are enabled, and
10127 * virtualize APIC access is disabled; in this case
10128 * the processor would never use the TPR shadow and we
10129 * could simply clear the bit from the execution
10130 * control. But such a configuration is useless, so
10131 * let's keep the code simple.
10133 if (!is_error_page(page
)) {
10134 vmx
->nested
.virtual_apic_page
= page
;
10135 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
10136 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
10140 if (nested_cpu_has_posted_intr(vmcs12
)) {
10141 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
10142 kunmap(vmx
->nested
.pi_desc_page
);
10143 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
10144 vmx
->nested
.pi_desc_page
= NULL
;
10146 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
10147 if (is_error_page(page
))
10149 vmx
->nested
.pi_desc_page
= page
;
10150 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
10151 vmx
->nested
.pi_desc
=
10152 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
10153 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
10155 vmcs_write64(POSTED_INTR_DESC_ADDR
,
10156 page_to_phys(vmx
->nested
.pi_desc_page
) +
10157 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
10160 if (cpu_has_vmx_msr_bitmap() &&
10161 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
10162 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
10163 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
10164 CPU_BASED_USE_MSR_BITMAPS
);
10166 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
10167 CPU_BASED_USE_MSR_BITMAPS
);
10170 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
10172 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
10173 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10175 if (vcpu
->arch
.virtual_tsc_khz
== 0)
10178 /* Make sure short timeouts reliably trigger an immediate vmexit.
10179 * hrtimer_start does not guarantee this. */
10180 if (preemption_timeout
<= 1) {
10181 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
10185 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10186 preemption_timeout
*= 1000000;
10187 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
10188 hrtimer_start(&vmx
->nested
.preemption_timer
,
10189 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
10192 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
10193 struct vmcs12
*vmcs12
)
10195 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
10198 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
10199 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
10205 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
10206 struct vmcs12
*vmcs12
)
10208 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
10211 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
10217 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
10218 struct vmcs12
*vmcs12
)
10220 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10223 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
10230 * Merge L0's and L1's MSR bitmap, return false to indicate that
10231 * we do not use the hardware.
10233 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10234 struct vmcs12
*vmcs12
)
10238 unsigned long *msr_bitmap_l1
;
10239 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.vmcs02
.msr_bitmap
;
10241 * pred_cmd & spec_ctrl are trying to verify two things:
10243 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10244 * ensures that we do not accidentally generate an L02 MSR bitmap
10245 * from the L12 MSR bitmap that is too permissive.
10246 * 2. That L1 or L2s have actually used the MSR. This avoids
10247 * unnecessarily merging of the bitmap if the MSR is unused. This
10248 * works properly because we only update the L01 MSR bitmap lazily.
10249 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10250 * updated to reflect this when L1 (or its L2s) actually write to
10253 bool pred_cmd
= !msr_write_intercepted_l01(vcpu
, MSR_IA32_PRED_CMD
);
10254 bool spec_ctrl
= !msr_write_intercepted_l01(vcpu
, MSR_IA32_SPEC_CTRL
);
10256 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10257 !pred_cmd
&& !spec_ctrl
)
10260 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10261 if (is_error_page(page
))
10263 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10265 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
10267 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
10268 if (nested_cpu_has_apic_reg_virt(vmcs12
))
10269 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
10270 nested_vmx_disable_intercept_for_msr(
10271 msr_bitmap_l1
, msr_bitmap_l0
,
10274 nested_vmx_disable_intercept_for_msr(
10275 msr_bitmap_l1
, msr_bitmap_l0
,
10276 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
10277 MSR_TYPE_R
| MSR_TYPE_W
);
10279 if (nested_cpu_has_vid(vmcs12
)) {
10280 nested_vmx_disable_intercept_for_msr(
10281 msr_bitmap_l1
, msr_bitmap_l0
,
10282 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
10284 nested_vmx_disable_intercept_for_msr(
10285 msr_bitmap_l1
, msr_bitmap_l0
,
10286 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
10292 nested_vmx_disable_intercept_for_msr(
10293 msr_bitmap_l1
, msr_bitmap_l0
,
10294 MSR_IA32_SPEC_CTRL
,
10295 MSR_TYPE_R
| MSR_TYPE_W
);
10298 nested_vmx_disable_intercept_for_msr(
10299 msr_bitmap_l1
, msr_bitmap_l0
,
10304 kvm_release_page_clean(page
);
10309 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10310 struct vmcs12
*vmcs12
)
10312 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10313 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10314 !nested_cpu_has_vid(vmcs12
) &&
10315 !nested_cpu_has_posted_intr(vmcs12
))
10319 * If virtualize x2apic mode is enabled,
10320 * virtualize apic access must be disabled.
10322 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10323 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10327 * If virtual interrupt delivery is enabled,
10328 * we must exit on external interrupts.
10330 if (nested_cpu_has_vid(vmcs12
) &&
10331 !nested_exit_on_intr(vcpu
))
10335 * bits 15:8 should be zero in posted_intr_nv,
10336 * the descriptor address has been already checked
10337 * in nested_get_vmcs12_pages.
10339 if (nested_cpu_has_posted_intr(vmcs12
) &&
10340 (!nested_cpu_has_vid(vmcs12
) ||
10341 !nested_exit_intr_ack_set(vcpu
) ||
10342 vmcs12
->posted_intr_nv
& 0xff00))
10345 /* tpr shadow is needed by all apicv features. */
10346 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10352 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10353 unsigned long count_field
,
10354 unsigned long addr_field
)
10359 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10360 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10366 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10367 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10368 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10369 pr_debug_ratelimited(
10370 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10371 addr_field
, maxphyaddr
, count
, addr
);
10377 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10378 struct vmcs12
*vmcs12
)
10380 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10381 vmcs12
->vm_exit_msr_store_count
== 0 &&
10382 vmcs12
->vm_entry_msr_load_count
== 0)
10383 return 0; /* Fast path */
10384 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10385 VM_EXIT_MSR_LOAD_ADDR
) ||
10386 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10387 VM_EXIT_MSR_STORE_ADDR
) ||
10388 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10389 VM_ENTRY_MSR_LOAD_ADDR
))
10394 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10395 struct vmcs12
*vmcs12
)
10397 u64 address
= vmcs12
->pml_address
;
10398 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10400 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10401 if (!nested_cpu_has_ept(vmcs12
) ||
10402 !IS_ALIGNED(address
, 4096) ||
10403 address
>> maxphyaddr
)
10410 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10411 struct vmx_msr_entry
*e
)
10413 /* x2APIC MSR accesses are not allowed */
10414 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10416 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10417 e
->index
== MSR_IA32_UCODE_REV
)
10419 if (e
->reserved
!= 0)
10424 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10425 struct vmx_msr_entry
*e
)
10427 if (e
->index
== MSR_FS_BASE
||
10428 e
->index
== MSR_GS_BASE
||
10429 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10430 nested_vmx_msr_check_common(vcpu
, e
))
10435 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10436 struct vmx_msr_entry
*e
)
10438 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10439 nested_vmx_msr_check_common(vcpu
, e
))
10445 * Load guest's/host's msr at nested entry/exit.
10446 * return 0 for success, entry index for failure.
10448 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10451 struct vmx_msr_entry e
;
10452 struct msr_data msr
;
10454 msr
.host_initiated
= false;
10455 for (i
= 0; i
< count
; i
++) {
10456 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10458 pr_debug_ratelimited(
10459 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10460 __func__
, i
, gpa
+ i
* sizeof(e
));
10463 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10464 pr_debug_ratelimited(
10465 "%s check failed (%u, 0x%x, 0x%x)\n",
10466 __func__
, i
, e
.index
, e
.reserved
);
10469 msr
.index
= e
.index
;
10470 msr
.data
= e
.value
;
10471 if (kvm_set_msr(vcpu
, &msr
)) {
10472 pr_debug_ratelimited(
10473 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10474 __func__
, i
, e
.index
, e
.value
);
10483 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10486 struct vmx_msr_entry e
;
10488 for (i
= 0; i
< count
; i
++) {
10489 struct msr_data msr_info
;
10490 if (kvm_vcpu_read_guest(vcpu
,
10491 gpa
+ i
* sizeof(e
),
10492 &e
, 2 * sizeof(u32
))) {
10493 pr_debug_ratelimited(
10494 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10495 __func__
, i
, gpa
+ i
* sizeof(e
));
10498 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10499 pr_debug_ratelimited(
10500 "%s check failed (%u, 0x%x, 0x%x)\n",
10501 __func__
, i
, e
.index
, e
.reserved
);
10504 msr_info
.host_initiated
= false;
10505 msr_info
.index
= e
.index
;
10506 if (kvm_get_msr(vcpu
, &msr_info
)) {
10507 pr_debug_ratelimited(
10508 "%s cannot read MSR (%u, 0x%x)\n",
10509 __func__
, i
, e
.index
);
10512 if (kvm_vcpu_write_guest(vcpu
,
10513 gpa
+ i
* sizeof(e
) +
10514 offsetof(struct vmx_msr_entry
, value
),
10515 &msr_info
.data
, sizeof(msr_info
.data
))) {
10516 pr_debug_ratelimited(
10517 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10518 __func__
, i
, e
.index
, msr_info
.data
);
10525 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10527 unsigned long invalid_mask
;
10529 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10530 return (val
& invalid_mask
) == 0;
10534 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10535 * emulating VM entry into a guest with EPT enabled.
10536 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10537 * is assigned to entry_failure_code on failure.
10539 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10540 u32
*entry_failure_code
)
10542 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10543 if (!nested_cr3_valid(vcpu
, cr3
)) {
10544 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10549 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10550 * must not be dereferenced.
10552 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10554 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10555 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10560 vcpu
->arch
.cr3
= cr3
;
10561 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10564 kvm_mmu_reset_context(vcpu
);
10569 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10570 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10571 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10572 * guest in a way that will both be appropriate to L1's requests, and our
10573 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10574 * function also has additional necessary side-effects, like setting various
10575 * vcpu->arch fields.
10576 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10577 * is assigned to entry_failure_code on failure.
10579 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10580 bool from_vmentry
, u32
*entry_failure_code
)
10582 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10583 u32 exec_control
, vmcs12_exec_ctrl
;
10585 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10586 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10587 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10588 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10589 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10590 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10591 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10592 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10593 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10594 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10595 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10596 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10597 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10598 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10599 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10600 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10601 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10602 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10603 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10604 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10605 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10606 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10607 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10608 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10609 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10610 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10611 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10612 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10613 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10614 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10615 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10616 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10617 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10618 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10619 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10620 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10622 if (from_vmentry
&&
10623 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10624 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10625 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10627 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10628 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10630 if (from_vmentry
) {
10631 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10632 vmcs12
->vm_entry_intr_info_field
);
10633 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10634 vmcs12
->vm_entry_exception_error_code
);
10635 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10636 vmcs12
->vm_entry_instruction_len
);
10637 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10638 vmcs12
->guest_interruptibility_info
);
10639 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10640 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10642 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10644 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10645 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10646 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10647 vmcs12
->guest_pending_dbg_exceptions
);
10648 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10649 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10651 if (nested_cpu_has_xsaves(vmcs12
))
10652 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10653 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10655 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10657 /* Preemption timer setting is only taken from vmcs01. */
10658 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10659 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10660 if (vmx
->hv_deadline_tsc
== -1)
10661 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10663 /* Posted interrupts setting is only taken from vmcs12. */
10664 if (nested_cpu_has_posted_intr(vmcs12
)) {
10665 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10666 vmx
->nested
.pi_pending
= false;
10667 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10669 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10672 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10674 vmx
->nested
.preemption_timer_expired
= false;
10675 if (nested_cpu_has_preemption_timer(vmcs12
))
10676 vmx_start_preemption_timer(vcpu
);
10679 * Whether page-faults are trapped is determined by a combination of
10680 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10681 * If enable_ept, L0 doesn't care about page faults and we should
10682 * set all of these to L1's desires. However, if !enable_ept, L0 does
10683 * care about (at least some) page faults, and because it is not easy
10684 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10685 * to exit on each and every L2 page fault. This is done by setting
10686 * MASK=MATCH=0 and (see below) EB.PF=1.
10687 * Note that below we don't need special code to set EB.PF beyond the
10688 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10689 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10690 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10692 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10693 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10694 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10695 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10697 if (cpu_has_secondary_exec_ctrls()) {
10698 exec_control
= vmx
->secondary_exec_control
;
10700 /* Take the following fields only from vmcs12 */
10701 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10702 SECONDARY_EXEC_ENABLE_INVPCID
|
10703 SECONDARY_EXEC_RDTSCP
|
10704 SECONDARY_EXEC_XSAVES
|
10705 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10706 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10707 SECONDARY_EXEC_ENABLE_VMFUNC
);
10708 if (nested_cpu_has(vmcs12
,
10709 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10710 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10711 ~SECONDARY_EXEC_ENABLE_PML
;
10712 exec_control
|= vmcs12_exec_ctrl
;
10715 /* All VMFUNCs are currently emulated through L0 vmexits. */
10716 if (exec_control
& SECONDARY_EXEC_ENABLE_VMFUNC
)
10717 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10719 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10720 vmcs_write64(EOI_EXIT_BITMAP0
,
10721 vmcs12
->eoi_exit_bitmap0
);
10722 vmcs_write64(EOI_EXIT_BITMAP1
,
10723 vmcs12
->eoi_exit_bitmap1
);
10724 vmcs_write64(EOI_EXIT_BITMAP2
,
10725 vmcs12
->eoi_exit_bitmap2
);
10726 vmcs_write64(EOI_EXIT_BITMAP3
,
10727 vmcs12
->eoi_exit_bitmap3
);
10728 vmcs_write16(GUEST_INTR_STATUS
,
10729 vmcs12
->guest_intr_status
);
10733 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10734 * nested_get_vmcs12_pages will either fix it up or
10735 * remove the VM execution control.
10737 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10738 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10740 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10745 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10746 * Some constant fields are set here by vmx_set_constant_host_state().
10747 * Other fields are different per CPU, and will be set later when
10748 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10750 vmx_set_constant_host_state(vmx
);
10753 * Set the MSR load/store lists to match L0's settings.
10755 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10756 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10757 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10758 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10759 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10762 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10763 * entry, but only if the current (host) sp changed from the value
10764 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10765 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10766 * here we just force the write to happen on entry.
10770 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10771 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10772 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10773 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10774 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10777 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10778 * nested_get_vmcs12_pages can't fix it up, the illegal value
10779 * will result in a VM entry failure.
10781 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10782 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10783 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10785 #ifdef CONFIG_X86_64
10786 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10787 CPU_BASED_CR8_STORE_EXITING
;
10792 * Merging of IO bitmap not currently supported.
10793 * Rather, exit every time.
10795 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10796 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10798 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10800 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10801 * bitwise-or of what L1 wants to trap for L2, and what we want to
10802 * trap. Note that CR0.TS also needs updating - we do this later.
10804 update_exception_bitmap(vcpu
);
10805 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10806 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10808 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10809 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10810 * bits are further modified by vmx_set_efer() below.
10812 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10814 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10815 * emulated by vmx_set_efer(), below.
10817 vm_entry_controls_init(vmx
,
10818 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10819 ~VM_ENTRY_IA32E_MODE
) |
10820 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10822 if (from_vmentry
&&
10823 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10824 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10825 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10826 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10827 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10830 set_cr4_guest_host_mask(vmx
);
10832 if (from_vmentry
&&
10833 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10834 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10836 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10837 vmcs_write64(TSC_OFFSET
,
10838 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10840 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10841 if (kvm_has_tsc_control
)
10842 decache_tsc_multiplier(vmx
);
10844 if (cpu_has_vmx_msr_bitmap())
10845 vmcs_write64(MSR_BITMAP
, __pa(vmx
->nested
.vmcs02
.msr_bitmap
));
10849 * There is no direct mapping between vpid02 and vpid12, the
10850 * vpid02 is per-vCPU for L0 and reused while the value of
10851 * vpid12 is changed w/ one invvpid during nested vmentry.
10852 * The vpid12 is allocated by L1 for L2, so it will not
10853 * influence global bitmap(for vpid01 and vpid02 allocation)
10854 * even if spawn a lot of nested vCPUs.
10856 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10857 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10858 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10859 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10860 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10863 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10864 vmx_flush_tlb(vcpu
);
10871 * Conceptually we want to copy the PML address and index from
10872 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10873 * since we always flush the log on each vmexit, this happens
10874 * to be equivalent to simply resetting the fields in vmcs02.
10876 ASSERT(vmx
->pml_pg
);
10877 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10878 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10881 if (nested_cpu_has_ept(vmcs12
)) {
10882 if (nested_ept_init_mmu_context(vcpu
)) {
10883 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10886 } else if (nested_cpu_has2(vmcs12
,
10887 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10888 vmx_flush_tlb_ept_only(vcpu
);
10892 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10893 * bits which we consider mandatory enabled.
10894 * The CR0_READ_SHADOW is what L2 should have expected to read given
10895 * the specifications by L1; It's not enough to take
10896 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10897 * have more bits than L1 expected.
10899 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10900 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10902 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10903 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10905 if (from_vmentry
&&
10906 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10907 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10908 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10909 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10911 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10912 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10913 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10915 /* Shadow page tables on either EPT or shadow page tables. */
10916 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10917 entry_failure_code
))
10921 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10924 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10927 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10928 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10929 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10930 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10933 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10934 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10938 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10940 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10942 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10943 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10944 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10946 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10947 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10949 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10950 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10952 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
10953 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10955 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10956 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10958 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10959 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10961 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10962 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10964 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10965 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10966 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10967 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10968 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10969 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10970 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10971 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10972 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10973 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10974 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10975 vmx
->nested
.nested_vmx_exit_ctls_low
,
10976 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10977 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10978 vmx
->nested
.nested_vmx_entry_ctls_low
,
10979 vmx
->nested
.nested_vmx_entry_ctls_high
))
10980 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10982 if (nested_cpu_has_vmfunc(vmcs12
)) {
10983 if (vmcs12
->vm_function_control
&
10984 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
10985 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10987 if (nested_cpu_has_eptp_switching(vmcs12
)) {
10988 if (!nested_cpu_has_ept(vmcs12
) ||
10989 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
10990 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10994 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10995 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10997 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10998 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10999 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
11000 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
11005 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11010 *exit_qual
= ENTRY_FAIL_DEFAULT
;
11012 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
11013 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
11016 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
11017 vmcs12
->vmcs_link_pointer
!= -1ull) {
11018 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
11023 * If the load IA32_EFER VM-entry control is 1, the following checks
11024 * are performed on the field for the IA32_EFER MSR:
11025 * - Bits reserved in the IA32_EFER MSR must be 0.
11026 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11027 * the IA-32e mode guest VM-exit control. It must also be identical
11028 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11031 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
11032 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
11033 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
11034 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
11035 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
11036 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
11037 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
11042 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11043 * IA32_EFER MSR must be 0 in the field for that register. In addition,
11044 * the values of the LMA and LME bits in the field must each be that of
11045 * the host address-space size VM-exit control.
11047 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
11048 ia32e
= (vmcs12
->vm_exit_controls
&
11049 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
11050 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
11051 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
11052 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
11056 if ((vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
) &&
11057 (is_noncanonical_address(vmcs12
->guest_bndcfgs
& PAGE_MASK
, vcpu
) ||
11058 (vmcs12
->guest_bndcfgs
& MSR_IA32_BNDCFGS_RSVD
)))
11064 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
11066 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11067 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11071 enter_guest_mode(vcpu
);
11073 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
11074 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11076 vmx_switch_vmcs(vcpu
, &vmx
->nested
.vmcs02
);
11077 vmx_segment_cache_clear(vmx
);
11079 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
11080 leave_guest_mode(vcpu
);
11081 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11082 nested_vmx_entry_failure(vcpu
, vmcs12
,
11083 EXIT_REASON_INVALID_STATE
, exit_qual
);
11087 nested_get_vmcs12_pages(vcpu
, vmcs12
);
11089 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
11090 vmcs12
->vm_entry_msr_load_addr
,
11091 vmcs12
->vm_entry_msr_load_count
);
11092 if (msr_entry_idx
) {
11093 leave_guest_mode(vcpu
);
11094 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11095 nested_vmx_entry_failure(vcpu
, vmcs12
,
11096 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
11101 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11102 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11103 * returned as far as L1 is concerned. It will only return (and set
11104 * the success flag) when L2 exits (see nested_vmx_vmexit()).
11110 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11111 * for running an L2 nested guest.
11113 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
11115 struct vmcs12
*vmcs12
;
11116 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11117 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
11121 if (!nested_vmx_check_permission(vcpu
))
11124 if (!nested_vmx_check_vmcs12(vcpu
))
11127 vmcs12
= get_vmcs12(vcpu
);
11129 if (enable_shadow_vmcs
)
11130 copy_shadow_to_vmcs12(vmx
);
11133 * The nested entry process starts with enforcing various prerequisites
11134 * on vmcs12 as required by the Intel SDM, and act appropriately when
11135 * they fail: As the SDM explains, some conditions should cause the
11136 * instruction to fail, while others will cause the instruction to seem
11137 * to succeed, but return an EXIT_REASON_INVALID_STATE.
11138 * To speed up the normal (success) code path, we should avoid checking
11139 * for misconfigurations which will anyway be caught by the processor
11140 * when using the merged vmcs02.
11142 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
11143 nested_vmx_failValid(vcpu
,
11144 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
11148 if (vmcs12
->launch_state
== launch
) {
11149 nested_vmx_failValid(vcpu
,
11150 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11151 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
11155 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
11157 nested_vmx_failValid(vcpu
, ret
);
11162 * After this point, the trap flag no longer triggers a singlestep trap
11163 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11164 * This is not 100% correct; for performance reasons, we delegate most
11165 * of the checks on host state to the processor. If those fail,
11166 * the singlestep trap is missed.
11168 skip_emulated_instruction(vcpu
);
11170 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
11172 nested_vmx_entry_failure(vcpu
, vmcs12
,
11173 EXIT_REASON_INVALID_STATE
, exit_qual
);
11178 * We're finally done with prerequisite checking, and can start with
11179 * the nested entry.
11182 ret
= enter_vmx_non_root_mode(vcpu
, true);
11186 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
11187 return kvm_vcpu_halt(vcpu
);
11189 vmx
->nested
.nested_run_pending
= 1;
11194 return kvm_skip_emulated_instruction(vcpu
);
11198 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11199 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11200 * This function returns the new value we should put in vmcs12.guest_cr0.
11201 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11202 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11203 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11204 * didn't trap the bit, because if L1 did, so would L0).
11205 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11206 * been modified by L2, and L1 knows it. So just leave the old value of
11207 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11208 * isn't relevant, because if L0 traps this bit it can set it to anything.
11209 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11210 * changed these bits, and therefore they need to be updated, but L0
11211 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11212 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11214 static inline unsigned long
11215 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11218 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
11219 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
11220 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
11221 vcpu
->arch
.cr0_guest_owned_bits
));
11224 static inline unsigned long
11225 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11228 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
11229 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
11230 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
11231 vcpu
->arch
.cr4_guest_owned_bits
));
11234 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
11235 struct vmcs12
*vmcs12
)
11240 if (vcpu
->arch
.exception
.injected
) {
11241 nr
= vcpu
->arch
.exception
.nr
;
11242 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11244 if (kvm_exception_is_soft(nr
)) {
11245 vmcs12
->vm_exit_instruction_len
=
11246 vcpu
->arch
.event_exit_inst_len
;
11247 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
11249 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
11251 if (vcpu
->arch
.exception
.has_error_code
) {
11252 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
11253 vmcs12
->idt_vectoring_error_code
=
11254 vcpu
->arch
.exception
.error_code
;
11257 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11258 } else if (vcpu
->arch
.nmi_injected
) {
11259 vmcs12
->idt_vectoring_info_field
=
11260 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
11261 } else if (vcpu
->arch
.interrupt
.pending
) {
11262 nr
= vcpu
->arch
.interrupt
.nr
;
11263 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11265 if (vcpu
->arch
.interrupt
.soft
) {
11266 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11267 vmcs12
->vm_entry_instruction_len
=
11268 vcpu
->arch
.event_exit_inst_len
;
11270 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11272 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11276 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11278 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11279 unsigned long exit_qual
;
11280 bool block_nested_events
=
11281 vmx
->nested
.nested_run_pending
|| kvm_event_needs_reinjection(vcpu
);
11283 if (vcpu
->arch
.exception
.pending
&&
11284 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
11285 if (block_nested_events
)
11287 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
11291 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11292 vmx
->nested
.preemption_timer_expired
) {
11293 if (block_nested_events
)
11295 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11299 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11300 if (block_nested_events
)
11302 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11303 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11304 INTR_INFO_VALID_MASK
, 0);
11306 * The NMI-triggered VM exit counts as injection:
11307 * clear this one and block further NMIs.
11309 vcpu
->arch
.nmi_pending
= 0;
11310 vmx_set_nmi_mask(vcpu
, true);
11314 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11315 nested_exit_on_intr(vcpu
)) {
11316 if (block_nested_events
)
11318 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11322 vmx_complete_nested_posted_interrupt(vcpu
);
11326 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11328 ktime_t remaining
=
11329 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11332 if (ktime_to_ns(remaining
) <= 0)
11335 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11336 do_div(value
, 1000000);
11337 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11341 * Update the guest state fields of vmcs12 to reflect changes that
11342 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11343 * VM-entry controls is also updated, since this is really a guest
11346 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11348 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11349 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11351 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11352 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11353 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11355 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11356 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11357 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11358 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11359 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11360 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11361 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11362 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11363 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11364 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11365 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11366 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11367 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11368 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11369 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11370 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11371 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11372 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11373 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11374 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11375 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11376 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11377 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11378 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11379 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11380 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11381 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11382 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11383 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11384 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11385 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11386 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11387 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11388 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11389 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11390 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11392 vmcs12
->guest_interruptibility_info
=
11393 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11394 vmcs12
->guest_pending_dbg_exceptions
=
11395 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11396 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11397 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11399 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11401 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11402 if (vmcs12
->vm_exit_controls
&
11403 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11404 vmcs12
->vmx_preemption_timer_value
=
11405 vmx_get_preemption_timer_value(vcpu
);
11406 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11410 * In some cases (usually, nested EPT), L2 is allowed to change its
11411 * own CR3 without exiting. If it has changed it, we must keep it.
11412 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11413 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11415 * Additionally, restore L2's PDPTR to vmcs12.
11418 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11419 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11420 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11421 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11422 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11425 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11427 if (nested_cpu_has_vid(vmcs12
))
11428 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11430 vmcs12
->vm_entry_controls
=
11431 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11432 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11434 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11435 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11436 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11439 /* TODO: These cannot have changed unless we have MSR bitmaps and
11440 * the relevant bit asks not to trap the change */
11441 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11442 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11443 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11444 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11445 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11446 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11447 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11448 if (kvm_mpx_supported())
11449 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11453 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11454 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11455 * and this function updates it to reflect the changes to the guest state while
11456 * L2 was running (and perhaps made some exits which were handled directly by L0
11457 * without going back to L1), and to reflect the exit reason.
11458 * Note that we do not have to copy here all VMCS fields, just those that
11459 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11460 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11461 * which already writes to vmcs12 directly.
11463 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11464 u32 exit_reason
, u32 exit_intr_info
,
11465 unsigned long exit_qualification
)
11467 /* update guest state fields: */
11468 sync_vmcs12(vcpu
, vmcs12
);
11470 /* update exit information fields: */
11472 vmcs12
->vm_exit_reason
= exit_reason
;
11473 vmcs12
->exit_qualification
= exit_qualification
;
11474 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11476 vmcs12
->idt_vectoring_info_field
= 0;
11477 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11478 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11480 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11481 vmcs12
->launch_state
= 1;
11483 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11484 * instead of reading the real value. */
11485 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11488 * Transfer the event that L0 or L1 may wanted to inject into
11489 * L2 to IDT_VECTORING_INFO_FIELD.
11491 vmcs12_save_pending_event(vcpu
, vmcs12
);
11495 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11496 * preserved above and would only end up incorrectly in L1.
11498 vcpu
->arch
.nmi_injected
= false;
11499 kvm_clear_exception_queue(vcpu
);
11500 kvm_clear_interrupt_queue(vcpu
);
11503 static void load_vmcs12_mmu_host_state(struct kvm_vcpu
*vcpu
,
11504 struct vmcs12
*vmcs12
)
11506 u32 entry_failure_code
;
11508 nested_ept_uninit_mmu_context(vcpu
);
11511 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11512 * couldn't have changed.
11514 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11515 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11518 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11522 * A part of what we need to when the nested L2 guest exits and we want to
11523 * run its L1 parent, is to reset L1's guest state to the host state specified
11525 * This function is to be called not only on normal nested exit, but also on
11526 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11527 * Failures During or After Loading Guest State").
11528 * This function should be called when the active VMCS is L1's (vmcs01).
11530 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11531 struct vmcs12
*vmcs12
)
11533 struct kvm_segment seg
;
11535 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11536 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11537 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11538 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11540 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11541 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11543 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11544 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11545 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11547 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11548 * actually changed, because vmx_set_cr0 refers to efer set above.
11550 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11551 * (KVM doesn't change it);
11553 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11554 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11556 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11557 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11558 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11560 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
11564 * Trivially support vpid by letting L2s share their parent
11565 * L1's vpid. TODO: move to a more elaborate solution, giving
11566 * each L2 its own vpid and exposing the vpid feature to L1.
11568 vmx_flush_tlb(vcpu
);
11570 /* Restore posted intr vector. */
11571 if (nested_cpu_has_posted_intr(vmcs12
))
11572 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11574 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11575 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11576 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11577 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11578 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11579 vmcs_write32(GUEST_IDTR_LIMIT
, 0xFFFF);
11580 vmcs_write32(GUEST_GDTR_LIMIT
, 0xFFFF);
11582 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11583 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11584 vmcs_write64(GUEST_BNDCFGS
, 0);
11586 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11587 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11588 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11590 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11591 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11592 vmcs12
->host_ia32_perf_global_ctrl
);
11594 /* Set L1 segment info according to Intel SDM
11595 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11596 seg
= (struct kvm_segment
) {
11598 .limit
= 0xFFFFFFFF,
11599 .selector
= vmcs12
->host_cs_selector
,
11605 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11609 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11610 seg
= (struct kvm_segment
) {
11612 .limit
= 0xFFFFFFFF,
11619 seg
.selector
= vmcs12
->host_ds_selector
;
11620 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11621 seg
.selector
= vmcs12
->host_es_selector
;
11622 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11623 seg
.selector
= vmcs12
->host_ss_selector
;
11624 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11625 seg
.selector
= vmcs12
->host_fs_selector
;
11626 seg
.base
= vmcs12
->host_fs_base
;
11627 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11628 seg
.selector
= vmcs12
->host_gs_selector
;
11629 seg
.base
= vmcs12
->host_gs_base
;
11630 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11631 seg
= (struct kvm_segment
) {
11632 .base
= vmcs12
->host_tr_base
,
11634 .selector
= vmcs12
->host_tr_selector
,
11638 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11640 kvm_set_dr(vcpu
, 7, 0x400);
11641 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11643 if (cpu_has_vmx_msr_bitmap())
11644 vmx_update_msr_bitmap(vcpu
);
11646 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11647 vmcs12
->vm_exit_msr_load_count
))
11648 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11652 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11653 * and modify vmcs12 to make it see what it would expect to see there if
11654 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11656 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11657 u32 exit_intr_info
,
11658 unsigned long exit_qualification
)
11660 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11661 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11663 /* trying to cancel vmlaunch/vmresume is a bug */
11664 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11667 * The only expected VM-instruction error is "VM entry with
11668 * invalid control field(s)." Anything else indicates a
11671 WARN_ON_ONCE(vmx
->fail
&& (vmcs_read32(VM_INSTRUCTION_ERROR
) !=
11672 VMXERR_ENTRY_INVALID_CONTROL_FIELD
));
11674 leave_guest_mode(vcpu
);
11676 if (likely(!vmx
->fail
)) {
11677 if (exit_reason
== -1)
11678 sync_vmcs12(vcpu
, vmcs12
);
11680 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11681 exit_qualification
);
11683 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11684 vmcs12
->vm_exit_msr_store_count
))
11685 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11688 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11689 vm_entry_controls_reset_shadow(vmx
);
11690 vm_exit_controls_reset_shadow(vmx
);
11691 vmx_segment_cache_clear(vmx
);
11693 /* Update any VMCS fields that might have changed while L2 ran */
11694 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11695 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11696 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11697 if (vmx
->hv_deadline_tsc
== -1)
11698 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11699 PIN_BASED_VMX_PREEMPTION_TIMER
);
11701 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11702 PIN_BASED_VMX_PREEMPTION_TIMER
);
11703 if (kvm_has_tsc_control
)
11704 decache_tsc_multiplier(vmx
);
11706 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11707 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11708 vmx_set_virtual_x2apic_mode(vcpu
,
11709 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11710 } else if (!nested_cpu_has_ept(vmcs12
) &&
11711 nested_cpu_has2(vmcs12
,
11712 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11713 vmx_flush_tlb_ept_only(vcpu
);
11716 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11719 /* Unpin physical memory we referred to in vmcs02 */
11720 if (vmx
->nested
.apic_access_page
) {
11721 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11722 vmx
->nested
.apic_access_page
= NULL
;
11724 if (vmx
->nested
.virtual_apic_page
) {
11725 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11726 vmx
->nested
.virtual_apic_page
= NULL
;
11728 if (vmx
->nested
.pi_desc_page
) {
11729 kunmap(vmx
->nested
.pi_desc_page
);
11730 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11731 vmx
->nested
.pi_desc_page
= NULL
;
11732 vmx
->nested
.pi_desc
= NULL
;
11736 * We are now running in L2, mmu_notifier will force to reload the
11737 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11739 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11741 if (enable_shadow_vmcs
&& exit_reason
!= -1)
11742 vmx
->nested
.sync_shadow_vmcs
= true;
11744 /* in case we halted in L2 */
11745 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11747 if (likely(!vmx
->fail
)) {
11749 * TODO: SDM says that with acknowledge interrupt on
11750 * exit, bit 31 of the VM-exit interrupt information
11751 * (valid interrupt) is always set to 1 on
11752 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11753 * need kvm_cpu_has_interrupt(). See the commit
11754 * message for details.
11756 if (nested_exit_intr_ack_set(vcpu
) &&
11757 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11758 kvm_cpu_has_interrupt(vcpu
)) {
11759 int irq
= kvm_cpu_get_interrupt(vcpu
);
11761 vmcs12
->vm_exit_intr_info
= irq
|
11762 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11765 if (exit_reason
!= -1)
11766 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11767 vmcs12
->exit_qualification
,
11768 vmcs12
->idt_vectoring_info_field
,
11769 vmcs12
->vm_exit_intr_info
,
11770 vmcs12
->vm_exit_intr_error_code
,
11773 load_vmcs12_host_state(vcpu
, vmcs12
);
11779 * After an early L2 VM-entry failure, we're now back
11780 * in L1 which thinks it just finished a VMLAUNCH or
11781 * VMRESUME instruction, so we need to set the failure
11782 * flag and the VM-instruction error field of the VMCS
11785 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11787 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
11790 * The emulated instruction was already skipped in
11791 * nested_vmx_run, but the updated RIP was never
11792 * written back to the vmcs01.
11794 skip_emulated_instruction(vcpu
);
11799 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11801 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11803 if (is_guest_mode(vcpu
)) {
11804 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11805 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11807 free_nested(to_vmx(vcpu
));
11811 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11812 * 23.7 "VM-entry failures during or after loading guest state" (this also
11813 * lists the acceptable exit-reason and exit-qualification parameters).
11814 * It should only be called before L2 actually succeeded to run, and when
11815 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11817 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11818 struct vmcs12
*vmcs12
,
11819 u32 reason
, unsigned long qualification
)
11821 load_vmcs12_host_state(vcpu
, vmcs12
);
11822 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11823 vmcs12
->exit_qualification
= qualification
;
11824 nested_vmx_succeed(vcpu
);
11825 if (enable_shadow_vmcs
)
11826 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11829 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11830 struct x86_instruction_info
*info
,
11831 enum x86_intercept_stage stage
)
11833 return X86EMUL_CONTINUE
;
11836 #ifdef CONFIG_X86_64
11837 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11838 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11839 u64 divisor
, u64
*result
)
11841 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11843 /* To avoid the overflow on divq */
11844 if (high
>= divisor
)
11847 /* Low hold the result, high hold rem which is discarded */
11848 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11849 "rm" (divisor
), "0" (low
), "1" (high
));
11855 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11857 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11858 u64 tscl
= rdtsc();
11859 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11860 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11862 /* Convert to host delta tsc if tsc scaling is enabled */
11863 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11864 u64_shl_div_u64(delta_tsc
,
11865 kvm_tsc_scaling_ratio_frac_bits
,
11866 vcpu
->arch
.tsc_scaling_ratio
,
11871 * If the delta tsc can't fit in the 32 bit after the multi shift,
11872 * we can't use the preemption timer.
11873 * It's possible that it fits on later vmentries, but checking
11874 * on every vmentry is costly so we just use an hrtimer.
11876 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11879 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11880 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11881 PIN_BASED_VMX_PREEMPTION_TIMER
);
11883 return delta_tsc
== 0;
11886 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11888 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11889 vmx
->hv_deadline_tsc
= -1;
11890 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11891 PIN_BASED_VMX_PREEMPTION_TIMER
);
11895 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11898 shrink_ple_window(vcpu
);
11901 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11902 struct kvm_memory_slot
*slot
)
11904 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11905 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11908 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11909 struct kvm_memory_slot
*slot
)
11911 kvm_mmu_slot_set_dirty(kvm
, slot
);
11914 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11916 kvm_flush_pml_buffers(kvm
);
11919 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11921 struct vmcs12
*vmcs12
;
11922 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11924 struct page
*page
= NULL
;
11927 if (is_guest_mode(vcpu
)) {
11928 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11931 * Check if PML is enabled for the nested guest.
11932 * Whether eptp bit 6 is set is already checked
11933 * as part of A/D emulation.
11935 vmcs12
= get_vmcs12(vcpu
);
11936 if (!nested_cpu_has_pml(vmcs12
))
11939 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11940 vmx
->nested
.pml_full
= true;
11944 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11946 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11947 if (is_error_page(page
))
11950 pml_address
= kmap(page
);
11951 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11953 kvm_release_page_clean(page
);
11959 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11960 struct kvm_memory_slot
*memslot
,
11961 gfn_t offset
, unsigned long mask
)
11963 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11966 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
11968 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11969 struct pi_desc old
, new;
11973 old
.control
= new.control
= pi_desc
->control
;
11974 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
11975 "Wakeup handler not enabled while the VCPU is blocked\n");
11977 dest
= cpu_physical_id(vcpu
->cpu
);
11979 if (x2apic_enabled())
11982 new.ndst
= (dest
<< 8) & 0xFF00;
11984 /* set 'NV' to 'notification vector' */
11985 new.nv
= POSTED_INTR_VECTOR
;
11986 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11987 new.control
) != old
.control
);
11989 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
11990 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11991 list_del(&vcpu
->blocked_vcpu_list
);
11992 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11993 vcpu
->pre_pcpu
= -1;
11998 * This routine does the following things for vCPU which is going
11999 * to be blocked if VT-d PI is enabled.
12000 * - Store the vCPU to the wakeup list, so when interrupts happen
12001 * we can find the right vCPU to wake up.
12002 * - Change the Posted-interrupt descriptor as below:
12003 * 'NDST' <-- vcpu->pre_pcpu
12004 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12005 * - If 'ON' is set during this process, which means at least one
12006 * interrupt is posted for this vCPU, we cannot block it, in
12007 * this case, return 1, otherwise, return 0.
12010 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
12013 struct pi_desc old
, new;
12014 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
12016 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
12017 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
12018 !kvm_vcpu_apicv_active(vcpu
))
12021 WARN_ON(irqs_disabled());
12022 local_irq_disable();
12023 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
12024 vcpu
->pre_pcpu
= vcpu
->cpu
;
12025 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12026 list_add_tail(&vcpu
->blocked_vcpu_list
,
12027 &per_cpu(blocked_vcpu_on_cpu
,
12029 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12033 old
.control
= new.control
= pi_desc
->control
;
12035 WARN((pi_desc
->sn
== 1),
12036 "Warning: SN field of posted-interrupts "
12037 "is set before blocking\n");
12040 * Since vCPU can be preempted during this process,
12041 * vcpu->cpu could be different with pre_pcpu, we
12042 * need to set pre_pcpu as the destination of wakeup
12043 * notification event, then we can find the right vCPU
12044 * to wakeup in wakeup handler if interrupts happen
12045 * when the vCPU is in blocked state.
12047 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
12049 if (x2apic_enabled())
12052 new.ndst
= (dest
<< 8) & 0xFF00;
12054 /* set 'NV' to 'wakeup vector' */
12055 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
12056 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
12057 new.control
) != old
.control
);
12059 /* We should not block the vCPU if an interrupt is posted for it. */
12060 if (pi_test_on(pi_desc
) == 1)
12061 __pi_post_block(vcpu
);
12063 local_irq_enable();
12064 return (vcpu
->pre_pcpu
== -1);
12067 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
12069 if (pi_pre_block(vcpu
))
12072 if (kvm_lapic_hv_timer_in_use(vcpu
))
12073 kvm_lapic_switch_to_sw_timer(vcpu
);
12078 static void pi_post_block(struct kvm_vcpu
*vcpu
)
12080 if (vcpu
->pre_pcpu
== -1)
12083 WARN_ON(irqs_disabled());
12084 local_irq_disable();
12085 __pi_post_block(vcpu
);
12086 local_irq_enable();
12089 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
12091 if (kvm_x86_ops
->set_hv_timer
)
12092 kvm_lapic_switch_to_hv_timer(vcpu
);
12094 pi_post_block(vcpu
);
12098 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12101 * @host_irq: host irq of the interrupt
12102 * @guest_irq: gsi of the interrupt
12103 * @set: set or unset PI
12104 * returns 0 on success, < 0 on failure
12106 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
12107 uint32_t guest_irq
, bool set
)
12109 struct kvm_kernel_irq_routing_entry
*e
;
12110 struct kvm_irq_routing_table
*irq_rt
;
12111 struct kvm_lapic_irq irq
;
12112 struct kvm_vcpu
*vcpu
;
12113 struct vcpu_data vcpu_info
;
12116 if (!kvm_arch_has_assigned_device(kvm
) ||
12117 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
12118 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
12121 idx
= srcu_read_lock(&kvm
->irq_srcu
);
12122 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
12123 if (guest_irq
>= irq_rt
->nr_rt_entries
||
12124 hlist_empty(&irq_rt
->map
[guest_irq
])) {
12125 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12126 guest_irq
, irq_rt
->nr_rt_entries
);
12130 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
12131 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
12134 * VT-d PI cannot support posting multicast/broadcast
12135 * interrupts to a vCPU, we still use interrupt remapping
12136 * for these kind of interrupts.
12138 * For lowest-priority interrupts, we only support
12139 * those with single CPU as the destination, e.g. user
12140 * configures the interrupts via /proc/irq or uses
12141 * irqbalance to make the interrupts single-CPU.
12143 * We will support full lowest-priority interrupt later.
12146 kvm_set_msi_irq(kvm
, e
, &irq
);
12147 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
12149 * Make sure the IRTE is in remapped mode if
12150 * we don't handle it in posted mode.
12152 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
12155 "failed to back to remapped mode, irq: %u\n",
12163 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
12164 vcpu_info
.vector
= irq
.vector
;
12166 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
12167 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
12170 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
12172 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
12175 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
12183 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
12187 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
12189 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
12190 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
12191 FEATURE_CONTROL_LMCE
;
12193 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
12194 ~FEATURE_CONTROL_LMCE
;
12197 static int vmx_smi_allowed(struct kvm_vcpu
*vcpu
)
12199 /* we need a nested vmexit to enter SMM, postpone if run is pending */
12200 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
12205 static int vmx_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
12207 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12209 vmx
->nested
.smm
.guest_mode
= is_guest_mode(vcpu
);
12210 if (vmx
->nested
.smm
.guest_mode
)
12211 nested_vmx_vmexit(vcpu
, -1, 0, 0);
12213 vmx
->nested
.smm
.vmxon
= vmx
->nested
.vmxon
;
12214 vmx
->nested
.vmxon
= false;
12218 static int vmx_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
12220 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12223 if (vmx
->nested
.smm
.vmxon
) {
12224 vmx
->nested
.vmxon
= true;
12225 vmx
->nested
.smm
.vmxon
= false;
12228 if (vmx
->nested
.smm
.guest_mode
) {
12229 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
12230 ret
= enter_vmx_non_root_mode(vcpu
, false);
12231 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
12235 vmx
->nested
.smm
.guest_mode
= false;
12240 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
12245 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
12246 .cpu_has_kvm_support
= cpu_has_kvm_support
,
12247 .disabled_by_bios
= vmx_disabled_by_bios
,
12248 .hardware_setup
= hardware_setup
,
12249 .hardware_unsetup
= hardware_unsetup
,
12250 .check_processor_compatibility
= vmx_check_processor_compat
,
12251 .hardware_enable
= hardware_enable
,
12252 .hardware_disable
= hardware_disable
,
12253 .cpu_has_accelerated_tpr
= report_flexpriority
,
12254 .has_emulated_msr
= vmx_has_emulated_msr
,
12256 .vcpu_create
= vmx_create_vcpu
,
12257 .vcpu_free
= vmx_free_vcpu
,
12258 .vcpu_reset
= vmx_vcpu_reset
,
12260 .prepare_guest_switch
= vmx_save_host_state
,
12261 .vcpu_load
= vmx_vcpu_load
,
12262 .vcpu_put
= vmx_vcpu_put
,
12264 .update_bp_intercept
= update_exception_bitmap
,
12265 .get_msr
= vmx_get_msr
,
12266 .set_msr
= vmx_set_msr
,
12267 .get_segment_base
= vmx_get_segment_base
,
12268 .get_segment
= vmx_get_segment
,
12269 .set_segment
= vmx_set_segment
,
12270 .get_cpl
= vmx_get_cpl
,
12271 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
12272 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
12273 .decache_cr3
= vmx_decache_cr3
,
12274 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
12275 .set_cr0
= vmx_set_cr0
,
12276 .set_cr3
= vmx_set_cr3
,
12277 .set_cr4
= vmx_set_cr4
,
12278 .set_efer
= vmx_set_efer
,
12279 .get_idt
= vmx_get_idt
,
12280 .set_idt
= vmx_set_idt
,
12281 .get_gdt
= vmx_get_gdt
,
12282 .set_gdt
= vmx_set_gdt
,
12283 .get_dr6
= vmx_get_dr6
,
12284 .set_dr6
= vmx_set_dr6
,
12285 .set_dr7
= vmx_set_dr7
,
12286 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
12287 .cache_reg
= vmx_cache_reg
,
12288 .get_rflags
= vmx_get_rflags
,
12289 .set_rflags
= vmx_set_rflags
,
12291 .tlb_flush
= vmx_flush_tlb
,
12293 .run
= vmx_vcpu_run
,
12294 .handle_exit
= vmx_handle_exit
,
12295 .skip_emulated_instruction
= skip_emulated_instruction
,
12296 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
12297 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
12298 .patch_hypercall
= vmx_patch_hypercall
,
12299 .set_irq
= vmx_inject_irq
,
12300 .set_nmi
= vmx_inject_nmi
,
12301 .queue_exception
= vmx_queue_exception
,
12302 .cancel_injection
= vmx_cancel_injection
,
12303 .interrupt_allowed
= vmx_interrupt_allowed
,
12304 .nmi_allowed
= vmx_nmi_allowed
,
12305 .get_nmi_mask
= vmx_get_nmi_mask
,
12306 .set_nmi_mask
= vmx_set_nmi_mask
,
12307 .enable_nmi_window
= enable_nmi_window
,
12308 .enable_irq_window
= enable_irq_window
,
12309 .update_cr8_intercept
= update_cr8_intercept
,
12310 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
12311 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
12312 .get_enable_apicv
= vmx_get_enable_apicv
,
12313 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
12314 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
12315 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
12316 .hwapic_irr_update
= vmx_hwapic_irr_update
,
12317 .hwapic_isr_update
= vmx_hwapic_isr_update
,
12318 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
12319 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
12321 .set_tss_addr
= vmx_set_tss_addr
,
12322 .get_tdp_level
= get_ept_level
,
12323 .get_mt_mask
= vmx_get_mt_mask
,
12325 .get_exit_info
= vmx_get_exit_info
,
12327 .get_lpage_level
= vmx_get_lpage_level
,
12329 .cpuid_update
= vmx_cpuid_update
,
12331 .rdtscp_supported
= vmx_rdtscp_supported
,
12332 .invpcid_supported
= vmx_invpcid_supported
,
12334 .set_supported_cpuid
= vmx_set_supported_cpuid
,
12336 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
12338 .write_tsc_offset
= vmx_write_tsc_offset
,
12340 .set_tdp_cr3
= vmx_set_cr3
,
12342 .check_intercept
= vmx_check_intercept
,
12343 .handle_external_intr
= vmx_handle_external_intr
,
12344 .mpx_supported
= vmx_mpx_supported
,
12345 .xsaves_supported
= vmx_xsaves_supported
,
12347 .check_nested_events
= vmx_check_nested_events
,
12349 .sched_in
= vmx_sched_in
,
12351 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
12352 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
12353 .flush_log_dirty
= vmx_flush_log_dirty
,
12354 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
12355 .write_log_dirty
= vmx_write_pml_buffer
,
12357 .pre_block
= vmx_pre_block
,
12358 .post_block
= vmx_post_block
,
12360 .pmu_ops
= &intel_pmu_ops
,
12362 .update_pi_irte
= vmx_update_pi_irte
,
12364 #ifdef CONFIG_X86_64
12365 .set_hv_timer
= vmx_set_hv_timer
,
12366 .cancel_hv_timer
= vmx_cancel_hv_timer
,
12369 .setup_mce
= vmx_setup_mce
,
12371 .smi_allowed
= vmx_smi_allowed
,
12372 .pre_enter_smm
= vmx_pre_enter_smm
,
12373 .pre_leave_smm
= vmx_pre_leave_smm
,
12374 .enable_smi_window
= enable_smi_window
,
12377 static int __init
vmx_init(void)
12379 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
12380 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
12384 #ifdef CONFIG_KEXEC_CORE
12385 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
12386 crash_vmclear_local_loaded_vmcss
);
12392 static void __exit
vmx_exit(void)
12394 #ifdef CONFIG_KEXEC_CORE
12395 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
12402 module_init(vmx_init
)
12403 module_exit(vmx_exit
)