2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
52 #define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
58 static const struct x86_cpu_id vmx_cpu_id
[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
62 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
64 static bool __read_mostly enable_vpid
= 1;
65 module_param_named(vpid
, enable_vpid
, bool, 0444);
67 static bool __read_mostly flexpriority_enabled
= 1;
68 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
70 static bool __read_mostly enable_ept
= 1;
71 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
73 static bool __read_mostly enable_unrestricted_guest
= 1;
74 module_param_named(unrestricted_guest
,
75 enable_unrestricted_guest
, bool, S_IRUGO
);
77 static bool __read_mostly enable_ept_ad_bits
= 1;
78 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
80 static bool __read_mostly emulate_invalid_guest_state
= true;
81 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
83 static bool __read_mostly vmm_exclusive
= 1;
84 module_param(vmm_exclusive
, bool, S_IRUGO
);
86 static bool __read_mostly fasteoi
= 1;
87 module_param(fasteoi
, bool, S_IRUGO
);
89 static bool __read_mostly enable_apicv
= 1;
90 module_param(enable_apicv
, bool, S_IRUGO
);
92 static bool __read_mostly enable_shadow_vmcs
= 1;
93 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
99 static bool __read_mostly nested
= 0;
100 module_param(nested
, bool, S_IRUGO
);
102 static u64 __read_mostly host_xss
;
104 static bool __read_mostly enable_pml
= 1;
105 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
107 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
108 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
109 #define KVM_VM_CR0_ALWAYS_ON \
110 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
111 #define KVM_CR4_GUEST_OWNED_BITS \
112 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
113 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
115 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
116 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
123 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
124 * ple_gap: upper bound on the amount of time between two successive
125 * executions of PAUSE in a loop. Also indicate if ple enabled.
126 * According to test, this time is usually smaller than 128 cycles.
127 * ple_window: upper bound on the amount of time a guest is allowed to execute
128 * in a PAUSE loop. Tests indicate that most spinlocks are held for
129 * less than 2^12 cycles
130 * Time is measured based on a counter that runs at the same rate as the TSC,
131 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 #define KVM_VMX_DEFAULT_PLE_GAP 128
134 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
135 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
136 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
137 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
138 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
141 module_param(ple_gap
, int, S_IRUGO
);
143 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
144 module_param(ple_window
, int, S_IRUGO
);
146 /* Default doubles per-vcpu window every exit. */
147 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
148 module_param(ple_window_grow
, int, S_IRUGO
);
150 /* Default resets per-vcpu window every exit to ple_window. */
151 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
152 module_param(ple_window_shrink
, int, S_IRUGO
);
154 /* Default is to compute the maximum so we can never overflow. */
155 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
156 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
157 module_param(ple_window_max
, int, S_IRUGO
);
159 extern const ulong vmx_return
;
161 #define NR_AUTOLOAD_MSRS 8
162 #define VMCS02_POOL_SIZE 1
171 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
172 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
173 * loaded on this CPU (so we can clear them if the CPU goes down).
179 struct list_head loaded_vmcss_on_cpu_link
;
182 struct shared_msr_entry
{
189 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
190 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
191 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
192 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
193 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
194 * More than one of these structures may exist, if L1 runs multiple L2 guests.
195 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
196 * underlying hardware which will be used to run L2.
197 * This structure is packed to ensure that its layout is identical across
198 * machines (necessary for live migration).
199 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 typedef u64 natural_width
;
202 struct __packed vmcs12
{
203 /* According to the Intel spec, a VMCS region must start with the
204 * following two fields. Then follow implementation-specific data.
209 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
210 u32 padding
[7]; /* room for future expansion */
215 u64 vm_exit_msr_store_addr
;
216 u64 vm_exit_msr_load_addr
;
217 u64 vm_entry_msr_load_addr
;
219 u64 virtual_apic_page_addr
;
220 u64 apic_access_addr
;
223 u64 guest_physical_address
;
224 u64 vmcs_link_pointer
;
225 u64 guest_ia32_debugctl
;
228 u64 guest_ia32_perf_global_ctrl
;
236 u64 host_ia32_perf_global_ctrl
;
237 u64 padding64
[8]; /* room for future expansion */
239 * To allow migration of L1 (complete with its L2 guests) between
240 * machines of different natural widths (32 or 64 bit), we cannot have
241 * unsigned long fields with no explict size. We use u64 (aliased
242 * natural_width) instead. Luckily, x86 is little-endian.
244 natural_width cr0_guest_host_mask
;
245 natural_width cr4_guest_host_mask
;
246 natural_width cr0_read_shadow
;
247 natural_width cr4_read_shadow
;
248 natural_width cr3_target_value0
;
249 natural_width cr3_target_value1
;
250 natural_width cr3_target_value2
;
251 natural_width cr3_target_value3
;
252 natural_width exit_qualification
;
253 natural_width guest_linear_address
;
254 natural_width guest_cr0
;
255 natural_width guest_cr3
;
256 natural_width guest_cr4
;
257 natural_width guest_es_base
;
258 natural_width guest_cs_base
;
259 natural_width guest_ss_base
;
260 natural_width guest_ds_base
;
261 natural_width guest_fs_base
;
262 natural_width guest_gs_base
;
263 natural_width guest_ldtr_base
;
264 natural_width guest_tr_base
;
265 natural_width guest_gdtr_base
;
266 natural_width guest_idtr_base
;
267 natural_width guest_dr7
;
268 natural_width guest_rsp
;
269 natural_width guest_rip
;
270 natural_width guest_rflags
;
271 natural_width guest_pending_dbg_exceptions
;
272 natural_width guest_sysenter_esp
;
273 natural_width guest_sysenter_eip
;
274 natural_width host_cr0
;
275 natural_width host_cr3
;
276 natural_width host_cr4
;
277 natural_width host_fs_base
;
278 natural_width host_gs_base
;
279 natural_width host_tr_base
;
280 natural_width host_gdtr_base
;
281 natural_width host_idtr_base
;
282 natural_width host_ia32_sysenter_esp
;
283 natural_width host_ia32_sysenter_eip
;
284 natural_width host_rsp
;
285 natural_width host_rip
;
286 natural_width paddingl
[8]; /* room for future expansion */
287 u32 pin_based_vm_exec_control
;
288 u32 cpu_based_vm_exec_control
;
289 u32 exception_bitmap
;
290 u32 page_fault_error_code_mask
;
291 u32 page_fault_error_code_match
;
292 u32 cr3_target_count
;
293 u32 vm_exit_controls
;
294 u32 vm_exit_msr_store_count
;
295 u32 vm_exit_msr_load_count
;
296 u32 vm_entry_controls
;
297 u32 vm_entry_msr_load_count
;
298 u32 vm_entry_intr_info_field
;
299 u32 vm_entry_exception_error_code
;
300 u32 vm_entry_instruction_len
;
302 u32 secondary_vm_exec_control
;
303 u32 vm_instruction_error
;
305 u32 vm_exit_intr_info
;
306 u32 vm_exit_intr_error_code
;
307 u32 idt_vectoring_info_field
;
308 u32 idt_vectoring_error_code
;
309 u32 vm_exit_instruction_len
;
310 u32 vmx_instruction_info
;
317 u32 guest_ldtr_limit
;
319 u32 guest_gdtr_limit
;
320 u32 guest_idtr_limit
;
321 u32 guest_es_ar_bytes
;
322 u32 guest_cs_ar_bytes
;
323 u32 guest_ss_ar_bytes
;
324 u32 guest_ds_ar_bytes
;
325 u32 guest_fs_ar_bytes
;
326 u32 guest_gs_ar_bytes
;
327 u32 guest_ldtr_ar_bytes
;
328 u32 guest_tr_ar_bytes
;
329 u32 guest_interruptibility_info
;
330 u32 guest_activity_state
;
331 u32 guest_sysenter_cs
;
332 u32 host_ia32_sysenter_cs
;
333 u32 vmx_preemption_timer_value
;
334 u32 padding32
[7]; /* room for future expansion */
335 u16 virtual_processor_id
;
336 u16 guest_es_selector
;
337 u16 guest_cs_selector
;
338 u16 guest_ss_selector
;
339 u16 guest_ds_selector
;
340 u16 guest_fs_selector
;
341 u16 guest_gs_selector
;
342 u16 guest_ldtr_selector
;
343 u16 guest_tr_selector
;
344 u16 host_es_selector
;
345 u16 host_cs_selector
;
346 u16 host_ss_selector
;
347 u16 host_ds_selector
;
348 u16 host_fs_selector
;
349 u16 host_gs_selector
;
350 u16 host_tr_selector
;
354 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
355 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
356 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
358 #define VMCS12_REVISION 0x11e57ed0
361 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
362 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
363 * current implementation, 4K are reserved to avoid future complications.
365 #define VMCS12_SIZE 0x1000
367 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
369 struct list_head list
;
371 struct loaded_vmcs vmcs02
;
375 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
376 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
379 /* Has the level1 guest done vmxon? */
383 /* The guest-physical address of the current VMCS L1 keeps for L2 */
385 /* The host-usable pointer to the above */
386 struct page
*current_vmcs12_page
;
387 struct vmcs12
*current_vmcs12
;
388 struct vmcs
*current_shadow_vmcs
;
390 * Indicates if the shadow vmcs must be updated with the
391 * data hold by vmcs12
393 bool sync_shadow_vmcs
;
395 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
396 struct list_head vmcs02_pool
;
398 u64 vmcs01_tsc_offset
;
399 /* L2 must run next, and mustn't decide to exit to L1. */
400 bool nested_run_pending
;
402 * Guest pages referred to in vmcs02 with host-physical pointers, so
403 * we must keep them pinned while L2 runs.
405 struct page
*apic_access_page
;
406 struct page
*virtual_apic_page
;
407 u64 msr_ia32_feature_control
;
409 struct hrtimer preemption_timer
;
410 bool preemption_timer_expired
;
412 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
415 u32 nested_vmx_procbased_ctls_low
;
416 u32 nested_vmx_procbased_ctls_high
;
417 u32 nested_vmx_true_procbased_ctls_low
;
418 u32 nested_vmx_secondary_ctls_low
;
419 u32 nested_vmx_secondary_ctls_high
;
420 u32 nested_vmx_pinbased_ctls_low
;
421 u32 nested_vmx_pinbased_ctls_high
;
422 u32 nested_vmx_exit_ctls_low
;
423 u32 nested_vmx_exit_ctls_high
;
424 u32 nested_vmx_true_exit_ctls_low
;
425 u32 nested_vmx_entry_ctls_low
;
426 u32 nested_vmx_entry_ctls_high
;
427 u32 nested_vmx_true_entry_ctls_low
;
428 u32 nested_vmx_misc_low
;
429 u32 nested_vmx_misc_high
;
430 u32 nested_vmx_ept_caps
;
433 #define POSTED_INTR_ON 0
434 /* Posted-Interrupt Descriptor */
436 u32 pir
[8]; /* Posted interrupt requested */
437 u32 control
; /* bit 0 of control is outstanding notification bit */
441 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
443 return test_and_set_bit(POSTED_INTR_ON
,
444 (unsigned long *)&pi_desc
->control
);
447 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
449 return test_and_clear_bit(POSTED_INTR_ON
,
450 (unsigned long *)&pi_desc
->control
);
453 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
455 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
459 struct kvm_vcpu vcpu
;
460 unsigned long host_rsp
;
462 bool nmi_known_unmasked
;
464 u32 idt_vectoring_info
;
466 struct shared_msr_entry
*guest_msrs
;
469 unsigned long host_idt_base
;
471 u64 msr_host_kernel_gs_base
;
472 u64 msr_guest_kernel_gs_base
;
474 u32 vm_entry_controls_shadow
;
475 u32 vm_exit_controls_shadow
;
477 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
478 * non-nested (L1) guest, it always points to vmcs01. For a nested
479 * guest (L2), it points to a different VMCS.
481 struct loaded_vmcs vmcs01
;
482 struct loaded_vmcs
*loaded_vmcs
;
483 bool __launched
; /* temporary, used in vmx_vcpu_run */
484 struct msr_autoload
{
486 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
487 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
491 u16 fs_sel
, gs_sel
, ldt_sel
;
495 int gs_ldt_reload_needed
;
496 int fs_reload_needed
;
497 u64 msr_host_bndcfgs
;
498 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
503 struct kvm_segment segs
[8];
506 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
507 struct kvm_save_segment
{
515 bool emulation_required
;
517 /* Support for vnmi-less CPUs */
518 int soft_vnmi_blocked
;
520 s64 vnmi_blocked_time
;
525 /* Posted interrupt descriptor */
526 struct pi_desc pi_desc
;
528 /* Support for a guest hypervisor (nested VMX) */
529 struct nested_vmx nested
;
531 /* Dynamic PLE window. */
533 bool ple_window_dirty
;
535 /* Support for PML */
536 #define PML_ENTITY_NUM 512
540 enum segment_cache_field
{
549 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
551 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
554 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
555 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
556 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
557 [number##_HIGH] = VMCS12_OFFSET(name)+4
560 static unsigned long shadow_read_only_fields
[] = {
562 * We do NOT shadow fields that are modified when L0
563 * traps and emulates any vmx instruction (e.g. VMPTRLD,
564 * VMXON...) executed by L1.
565 * For example, VM_INSTRUCTION_ERROR is read
566 * by L1 if a vmx instruction fails (part of the error path).
567 * Note the code assumes this logic. If for some reason
568 * we start shadowing these fields then we need to
569 * force a shadow sync when L0 emulates vmx instructions
570 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
571 * by nested_vmx_failValid)
575 VM_EXIT_INSTRUCTION_LEN
,
576 IDT_VECTORING_INFO_FIELD
,
577 IDT_VECTORING_ERROR_CODE
,
578 VM_EXIT_INTR_ERROR_CODE
,
580 GUEST_LINEAR_ADDRESS
,
581 GUEST_PHYSICAL_ADDRESS
583 static int max_shadow_read_only_fields
=
584 ARRAY_SIZE(shadow_read_only_fields
);
586 static unsigned long shadow_read_write_fields
[] = {
593 GUEST_INTERRUPTIBILITY_INFO
,
606 CPU_BASED_VM_EXEC_CONTROL
,
607 VM_ENTRY_EXCEPTION_ERROR_CODE
,
608 VM_ENTRY_INTR_INFO_FIELD
,
609 VM_ENTRY_INSTRUCTION_LEN
,
610 VM_ENTRY_EXCEPTION_ERROR_CODE
,
616 static int max_shadow_read_write_fields
=
617 ARRAY_SIZE(shadow_read_write_fields
);
619 static const unsigned short vmcs_field_to_offset_table
[] = {
620 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
621 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
622 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
623 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
624 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
625 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
626 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
627 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
628 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
629 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
630 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
631 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
632 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
633 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
634 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
635 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
636 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
637 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
638 FIELD64(MSR_BITMAP
, msr_bitmap
),
639 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
640 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
641 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
642 FIELD64(TSC_OFFSET
, tsc_offset
),
643 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
644 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
645 FIELD64(EPT_POINTER
, ept_pointer
),
646 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
647 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
648 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
649 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
650 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
651 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
652 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
653 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
654 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
655 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
656 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
657 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
658 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
659 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
660 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
661 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
662 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
663 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
664 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
665 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
666 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
667 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
668 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
669 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
670 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
671 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
672 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
673 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
674 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
675 FIELD(TPR_THRESHOLD
, tpr_threshold
),
676 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
677 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
678 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
679 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
680 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
681 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
682 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
683 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
684 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
685 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
686 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
687 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
688 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
689 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
690 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
691 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
692 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
693 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
694 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
695 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
696 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
697 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
698 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
699 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
700 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
701 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
702 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
703 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
704 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
705 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
706 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
707 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
708 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
709 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
710 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
711 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
712 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
713 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
714 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
715 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
716 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
717 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
718 FIELD(GUEST_CR0
, guest_cr0
),
719 FIELD(GUEST_CR3
, guest_cr3
),
720 FIELD(GUEST_CR4
, guest_cr4
),
721 FIELD(GUEST_ES_BASE
, guest_es_base
),
722 FIELD(GUEST_CS_BASE
, guest_cs_base
),
723 FIELD(GUEST_SS_BASE
, guest_ss_base
),
724 FIELD(GUEST_DS_BASE
, guest_ds_base
),
725 FIELD(GUEST_FS_BASE
, guest_fs_base
),
726 FIELD(GUEST_GS_BASE
, guest_gs_base
),
727 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
728 FIELD(GUEST_TR_BASE
, guest_tr_base
),
729 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
730 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
731 FIELD(GUEST_DR7
, guest_dr7
),
732 FIELD(GUEST_RSP
, guest_rsp
),
733 FIELD(GUEST_RIP
, guest_rip
),
734 FIELD(GUEST_RFLAGS
, guest_rflags
),
735 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
736 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
737 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
738 FIELD(HOST_CR0
, host_cr0
),
739 FIELD(HOST_CR3
, host_cr3
),
740 FIELD(HOST_CR4
, host_cr4
),
741 FIELD(HOST_FS_BASE
, host_fs_base
),
742 FIELD(HOST_GS_BASE
, host_gs_base
),
743 FIELD(HOST_TR_BASE
, host_tr_base
),
744 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
745 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
746 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
747 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
748 FIELD(HOST_RSP
, host_rsp
),
749 FIELD(HOST_RIP
, host_rip
),
752 static inline short vmcs_field_to_offset(unsigned long field
)
754 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
756 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
757 vmcs_field_to_offset_table
[field
] == 0)
760 return vmcs_field_to_offset_table
[field
];
763 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
765 return to_vmx(vcpu
)->nested
.current_vmcs12
;
768 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
770 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
771 if (is_error_page(page
))
777 static void nested_release_page(struct page
*page
)
779 kvm_release_page_dirty(page
);
782 static void nested_release_page_clean(struct page
*page
)
784 kvm_release_page_clean(page
);
787 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
788 static u64
construct_eptp(unsigned long root_hpa
);
789 static void kvm_cpu_vmxon(u64 addr
);
790 static void kvm_cpu_vmxoff(void);
791 static bool vmx_mpx_supported(void);
792 static bool vmx_xsaves_supported(void);
793 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
794 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
795 struct kvm_segment
*var
, int seg
);
796 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
797 struct kvm_segment
*var
, int seg
);
798 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
799 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
800 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
801 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
802 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
803 static int alloc_identity_pagetable(struct kvm
*kvm
);
805 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
806 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
808 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
809 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
811 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
812 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
814 static unsigned long *vmx_io_bitmap_a
;
815 static unsigned long *vmx_io_bitmap_b
;
816 static unsigned long *vmx_msr_bitmap_legacy
;
817 static unsigned long *vmx_msr_bitmap_longmode
;
818 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
819 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
820 static unsigned long *vmx_msr_bitmap_nested
;
821 static unsigned long *vmx_vmread_bitmap
;
822 static unsigned long *vmx_vmwrite_bitmap
;
824 static bool cpu_has_load_ia32_efer
;
825 static bool cpu_has_load_perf_global_ctrl
;
827 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
828 static DEFINE_SPINLOCK(vmx_vpid_lock
);
830 static struct vmcs_config
{
834 u32 pin_based_exec_ctrl
;
835 u32 cpu_based_exec_ctrl
;
836 u32 cpu_based_2nd_exec_ctrl
;
841 static struct vmx_capability
{
846 #define VMX_SEGMENT_FIELD(seg) \
847 [VCPU_SREG_##seg] = { \
848 .selector = GUEST_##seg##_SELECTOR, \
849 .base = GUEST_##seg##_BASE, \
850 .limit = GUEST_##seg##_LIMIT, \
851 .ar_bytes = GUEST_##seg##_AR_BYTES, \
854 static const struct kvm_vmx_segment_field
{
859 } kvm_vmx_segment_fields
[] = {
860 VMX_SEGMENT_FIELD(CS
),
861 VMX_SEGMENT_FIELD(DS
),
862 VMX_SEGMENT_FIELD(ES
),
863 VMX_SEGMENT_FIELD(FS
),
864 VMX_SEGMENT_FIELD(GS
),
865 VMX_SEGMENT_FIELD(SS
),
866 VMX_SEGMENT_FIELD(TR
),
867 VMX_SEGMENT_FIELD(LDTR
),
870 static u64 host_efer
;
872 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
875 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
876 * away by decrementing the array size.
878 static const u32 vmx_msr_index
[] = {
880 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
882 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
885 static inline bool is_page_fault(u32 intr_info
)
887 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
888 INTR_INFO_VALID_MASK
)) ==
889 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
892 static inline bool is_no_device(u32 intr_info
)
894 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
895 INTR_INFO_VALID_MASK
)) ==
896 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
899 static inline bool is_invalid_opcode(u32 intr_info
)
901 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
902 INTR_INFO_VALID_MASK
)) ==
903 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
906 static inline bool is_external_interrupt(u32 intr_info
)
908 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
909 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
912 static inline bool is_machine_check(u32 intr_info
)
914 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
915 INTR_INFO_VALID_MASK
)) ==
916 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
919 static inline bool cpu_has_vmx_msr_bitmap(void)
921 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
924 static inline bool cpu_has_vmx_tpr_shadow(void)
926 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
929 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
931 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
934 static inline bool cpu_has_secondary_exec_ctrls(void)
936 return vmcs_config
.cpu_based_exec_ctrl
&
937 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
940 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
942 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
943 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
946 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
948 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
949 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
952 static inline bool cpu_has_vmx_apic_register_virt(void)
954 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
955 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
958 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
960 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
961 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
964 static inline bool cpu_has_vmx_posted_intr(void)
966 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
969 static inline bool cpu_has_vmx_apicv(void)
971 return cpu_has_vmx_apic_register_virt() &&
972 cpu_has_vmx_virtual_intr_delivery() &&
973 cpu_has_vmx_posted_intr();
976 static inline bool cpu_has_vmx_flexpriority(void)
978 return cpu_has_vmx_tpr_shadow() &&
979 cpu_has_vmx_virtualize_apic_accesses();
982 static inline bool cpu_has_vmx_ept_execute_only(void)
984 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
987 static inline bool cpu_has_vmx_ept_2m_page(void)
989 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
992 static inline bool cpu_has_vmx_ept_1g_page(void)
994 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
997 static inline bool cpu_has_vmx_ept_4levels(void)
999 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1002 static inline bool cpu_has_vmx_ept_ad_bits(void)
1004 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1007 static inline bool cpu_has_vmx_invept_context(void)
1009 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1012 static inline bool cpu_has_vmx_invept_global(void)
1014 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1017 static inline bool cpu_has_vmx_invvpid_single(void)
1019 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1022 static inline bool cpu_has_vmx_invvpid_global(void)
1024 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1027 static inline bool cpu_has_vmx_ept(void)
1029 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1030 SECONDARY_EXEC_ENABLE_EPT
;
1033 static inline bool cpu_has_vmx_unrestricted_guest(void)
1035 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1036 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1039 static inline bool cpu_has_vmx_ple(void)
1041 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1042 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1045 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
1047 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
1050 static inline bool cpu_has_vmx_vpid(void)
1052 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1053 SECONDARY_EXEC_ENABLE_VPID
;
1056 static inline bool cpu_has_vmx_rdtscp(void)
1058 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1059 SECONDARY_EXEC_RDTSCP
;
1062 static inline bool cpu_has_vmx_invpcid(void)
1064 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1065 SECONDARY_EXEC_ENABLE_INVPCID
;
1068 static inline bool cpu_has_virtual_nmis(void)
1070 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1073 static inline bool cpu_has_vmx_wbinvd_exit(void)
1075 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1076 SECONDARY_EXEC_WBINVD_EXITING
;
1079 static inline bool cpu_has_vmx_shadow_vmcs(void)
1082 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1083 /* check if the cpu supports writing r/o exit information fields */
1084 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1087 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1088 SECONDARY_EXEC_SHADOW_VMCS
;
1091 static inline bool cpu_has_vmx_pml(void)
1093 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1096 static inline bool report_flexpriority(void)
1098 return flexpriority_enabled
;
1101 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1103 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1106 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1108 return (vmcs12
->cpu_based_vm_exec_control
&
1109 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1110 (vmcs12
->secondary_vm_exec_control
& bit
);
1113 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1115 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1118 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1120 return vmcs12
->pin_based_vm_exec_control
&
1121 PIN_BASED_VMX_PREEMPTION_TIMER
;
1124 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1126 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1129 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1131 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1132 vmx_xsaves_supported();
1135 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1137 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1140 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1142 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1145 static inline bool is_exception(u32 intr_info
)
1147 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1148 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1151 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1153 unsigned long exit_qualification
);
1154 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1155 struct vmcs12
*vmcs12
,
1156 u32 reason
, unsigned long qualification
);
1158 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1162 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1163 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1168 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1174 } operand
= { vpid
, 0, gva
};
1176 asm volatile (__ex(ASM_VMX_INVVPID
)
1177 /* CF==1 or ZF==1 --> rc = -1 */
1178 "; ja 1f ; ud2 ; 1:"
1179 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1182 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1186 } operand
= {eptp
, gpa
};
1188 asm volatile (__ex(ASM_VMX_INVEPT
)
1189 /* CF==1 or ZF==1 --> rc = -1 */
1190 "; ja 1f ; ud2 ; 1:\n"
1191 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1194 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1198 i
= __find_msr_index(vmx
, msr
);
1200 return &vmx
->guest_msrs
[i
];
1204 static void vmcs_clear(struct vmcs
*vmcs
)
1206 u64 phys_addr
= __pa(vmcs
);
1209 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1210 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1213 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1217 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1219 vmcs_clear(loaded_vmcs
->vmcs
);
1220 loaded_vmcs
->cpu
= -1;
1221 loaded_vmcs
->launched
= 0;
1224 static void vmcs_load(struct vmcs
*vmcs
)
1226 u64 phys_addr
= __pa(vmcs
);
1229 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1230 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1233 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1239 * This bitmap is used to indicate whether the vmclear
1240 * operation is enabled on all cpus. All disabled by
1243 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1245 static inline void crash_enable_local_vmclear(int cpu
)
1247 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1250 static inline void crash_disable_local_vmclear(int cpu
)
1252 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1255 static inline int crash_local_vmclear_enabled(int cpu
)
1257 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1260 static void crash_vmclear_local_loaded_vmcss(void)
1262 int cpu
= raw_smp_processor_id();
1263 struct loaded_vmcs
*v
;
1265 if (!crash_local_vmclear_enabled(cpu
))
1268 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1269 loaded_vmcss_on_cpu_link
)
1270 vmcs_clear(v
->vmcs
);
1273 static inline void crash_enable_local_vmclear(int cpu
) { }
1274 static inline void crash_disable_local_vmclear(int cpu
) { }
1275 #endif /* CONFIG_KEXEC */
1277 static void __loaded_vmcs_clear(void *arg
)
1279 struct loaded_vmcs
*loaded_vmcs
= arg
;
1280 int cpu
= raw_smp_processor_id();
1282 if (loaded_vmcs
->cpu
!= cpu
)
1283 return; /* vcpu migration can race with cpu offline */
1284 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1285 per_cpu(current_vmcs
, cpu
) = NULL
;
1286 crash_disable_local_vmclear(cpu
);
1287 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1290 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1291 * is before setting loaded_vmcs->vcpu to -1 which is done in
1292 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1293 * then adds the vmcs into percpu list before it is deleted.
1297 loaded_vmcs_init(loaded_vmcs
);
1298 crash_enable_local_vmclear(cpu
);
1301 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1303 int cpu
= loaded_vmcs
->cpu
;
1306 smp_call_function_single(cpu
,
1307 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1310 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1315 if (cpu_has_vmx_invvpid_single())
1316 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1319 static inline void vpid_sync_vcpu_global(void)
1321 if (cpu_has_vmx_invvpid_global())
1322 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1325 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1327 if (cpu_has_vmx_invvpid_single())
1328 vpid_sync_vcpu_single(vmx
);
1330 vpid_sync_vcpu_global();
1333 static inline void ept_sync_global(void)
1335 if (cpu_has_vmx_invept_global())
1336 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1339 static inline void ept_sync_context(u64 eptp
)
1342 if (cpu_has_vmx_invept_context())
1343 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1349 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1351 unsigned long value
;
1353 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1354 : "=a"(value
) : "d"(field
) : "cc");
1358 static __always_inline u16
vmcs_read16(unsigned long field
)
1360 return vmcs_readl(field
);
1363 static __always_inline u32
vmcs_read32(unsigned long field
)
1365 return vmcs_readl(field
);
1368 static __always_inline u64
vmcs_read64(unsigned long field
)
1370 #ifdef CONFIG_X86_64
1371 return vmcs_readl(field
);
1373 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1377 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1379 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1380 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1384 static void vmcs_writel(unsigned long field
, unsigned long value
)
1388 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1389 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1390 if (unlikely(error
))
1391 vmwrite_error(field
, value
);
1394 static void vmcs_write16(unsigned long field
, u16 value
)
1396 vmcs_writel(field
, value
);
1399 static void vmcs_write32(unsigned long field
, u32 value
)
1401 vmcs_writel(field
, value
);
1404 static void vmcs_write64(unsigned long field
, u64 value
)
1406 vmcs_writel(field
, value
);
1407 #ifndef CONFIG_X86_64
1409 vmcs_writel(field
+1, value
>> 32);
1413 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1415 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1418 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1420 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1423 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1425 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1426 vmx
->vm_entry_controls_shadow
= val
;
1429 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1431 if (vmx
->vm_entry_controls_shadow
!= val
)
1432 vm_entry_controls_init(vmx
, val
);
1435 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1437 return vmx
->vm_entry_controls_shadow
;
1441 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1443 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1446 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1448 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1451 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1453 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1454 vmx
->vm_exit_controls_shadow
= val
;
1457 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1459 if (vmx
->vm_exit_controls_shadow
!= val
)
1460 vm_exit_controls_init(vmx
, val
);
1463 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1465 return vmx
->vm_exit_controls_shadow
;
1469 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1471 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1474 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1476 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1479 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1481 vmx
->segment_cache
.bitmask
= 0;
1484 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1488 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1490 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1491 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1492 vmx
->segment_cache
.bitmask
= 0;
1494 ret
= vmx
->segment_cache
.bitmask
& mask
;
1495 vmx
->segment_cache
.bitmask
|= mask
;
1499 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1501 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1503 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1504 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1508 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1510 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1512 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1513 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1517 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1519 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1521 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1522 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1526 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1528 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1530 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1531 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1535 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1539 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1540 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1541 if ((vcpu
->guest_debug
&
1542 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1543 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1544 eb
|= 1u << BP_VECTOR
;
1545 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1548 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1549 if (vcpu
->fpu_active
)
1550 eb
&= ~(1u << NM_VECTOR
);
1552 /* When we are running a nested L2 guest and L1 specified for it a
1553 * certain exception bitmap, we must trap the same exceptions and pass
1554 * them to L1. When running L2, we will only handle the exceptions
1555 * specified above if L1 did not want them.
1557 if (is_guest_mode(vcpu
))
1558 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1560 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1563 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1564 unsigned long entry
, unsigned long exit
)
1566 vm_entry_controls_clearbit(vmx
, entry
);
1567 vm_exit_controls_clearbit(vmx
, exit
);
1570 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1573 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1577 if (cpu_has_load_ia32_efer
) {
1578 clear_atomic_switch_msr_special(vmx
,
1579 VM_ENTRY_LOAD_IA32_EFER
,
1580 VM_EXIT_LOAD_IA32_EFER
);
1584 case MSR_CORE_PERF_GLOBAL_CTRL
:
1585 if (cpu_has_load_perf_global_ctrl
) {
1586 clear_atomic_switch_msr_special(vmx
,
1587 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1588 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1594 for (i
= 0; i
< m
->nr
; ++i
)
1595 if (m
->guest
[i
].index
== msr
)
1601 m
->guest
[i
] = m
->guest
[m
->nr
];
1602 m
->host
[i
] = m
->host
[m
->nr
];
1603 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1604 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1607 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1608 unsigned long entry
, unsigned long exit
,
1609 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1610 u64 guest_val
, u64 host_val
)
1612 vmcs_write64(guest_val_vmcs
, guest_val
);
1613 vmcs_write64(host_val_vmcs
, host_val
);
1614 vm_entry_controls_setbit(vmx
, entry
);
1615 vm_exit_controls_setbit(vmx
, exit
);
1618 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1619 u64 guest_val
, u64 host_val
)
1622 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1626 if (cpu_has_load_ia32_efer
) {
1627 add_atomic_switch_msr_special(vmx
,
1628 VM_ENTRY_LOAD_IA32_EFER
,
1629 VM_EXIT_LOAD_IA32_EFER
,
1632 guest_val
, host_val
);
1636 case MSR_CORE_PERF_GLOBAL_CTRL
:
1637 if (cpu_has_load_perf_global_ctrl
) {
1638 add_atomic_switch_msr_special(vmx
,
1639 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1640 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1641 GUEST_IA32_PERF_GLOBAL_CTRL
,
1642 HOST_IA32_PERF_GLOBAL_CTRL
,
1643 guest_val
, host_val
);
1649 for (i
= 0; i
< m
->nr
; ++i
)
1650 if (m
->guest
[i
].index
== msr
)
1653 if (i
== NR_AUTOLOAD_MSRS
) {
1654 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1655 "Can't add msr %x\n", msr
);
1657 } else if (i
== m
->nr
) {
1659 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1660 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1663 m
->guest
[i
].index
= msr
;
1664 m
->guest
[i
].value
= guest_val
;
1665 m
->host
[i
].index
= msr
;
1666 m
->host
[i
].value
= host_val
;
1669 static void reload_tss(void)
1672 * VT restores TR but not its size. Useless.
1674 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1675 struct desc_struct
*descs
;
1677 descs
= (void *)gdt
->address
;
1678 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1682 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1687 guest_efer
= vmx
->vcpu
.arch
.efer
;
1690 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1693 ignore_bits
= EFER_NX
| EFER_SCE
;
1694 #ifdef CONFIG_X86_64
1695 ignore_bits
|= EFER_LMA
| EFER_LME
;
1696 /* SCE is meaningful only in long mode on Intel */
1697 if (guest_efer
& EFER_LMA
)
1698 ignore_bits
&= ~(u64
)EFER_SCE
;
1700 guest_efer
&= ~ignore_bits
;
1701 guest_efer
|= host_efer
& ignore_bits
;
1702 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1703 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1705 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1708 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1709 * On CPUs that support "load IA32_EFER", always switch EFER
1710 * atomically, since it's faster than switching it manually.
1712 if (cpu_has_load_ia32_efer
||
1713 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1714 guest_efer
= vmx
->vcpu
.arch
.efer
;
1715 if (!(guest_efer
& EFER_LMA
))
1716 guest_efer
&= ~EFER_LME
;
1717 if (guest_efer
!= host_efer
)
1718 add_atomic_switch_msr(vmx
, MSR_EFER
,
1719 guest_efer
, host_efer
);
1726 static unsigned long segment_base(u16 selector
)
1728 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1729 struct desc_struct
*d
;
1730 unsigned long table_base
;
1733 if (!(selector
& ~3))
1736 table_base
= gdt
->address
;
1738 if (selector
& 4) { /* from ldt */
1739 u16 ldt_selector
= kvm_read_ldt();
1741 if (!(ldt_selector
& ~3))
1744 table_base
= segment_base(ldt_selector
);
1746 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1747 v
= get_desc_base(d
);
1748 #ifdef CONFIG_X86_64
1749 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1750 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1755 static inline unsigned long kvm_read_tr_base(void)
1758 asm("str %0" : "=g"(tr
));
1759 return segment_base(tr
);
1762 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1764 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1767 if (vmx
->host_state
.loaded
)
1770 vmx
->host_state
.loaded
= 1;
1772 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1773 * allow segment selectors with cpl > 0 or ti == 1.
1775 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1776 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1777 savesegment(fs
, vmx
->host_state
.fs_sel
);
1778 if (!(vmx
->host_state
.fs_sel
& 7)) {
1779 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1780 vmx
->host_state
.fs_reload_needed
= 0;
1782 vmcs_write16(HOST_FS_SELECTOR
, 0);
1783 vmx
->host_state
.fs_reload_needed
= 1;
1785 savesegment(gs
, vmx
->host_state
.gs_sel
);
1786 if (!(vmx
->host_state
.gs_sel
& 7))
1787 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1789 vmcs_write16(HOST_GS_SELECTOR
, 0);
1790 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1793 #ifdef CONFIG_X86_64
1794 savesegment(ds
, vmx
->host_state
.ds_sel
);
1795 savesegment(es
, vmx
->host_state
.es_sel
);
1798 #ifdef CONFIG_X86_64
1799 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1800 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1802 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1803 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1806 #ifdef CONFIG_X86_64
1807 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1808 if (is_long_mode(&vmx
->vcpu
))
1809 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1811 if (boot_cpu_has(X86_FEATURE_MPX
))
1812 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1813 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1814 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1815 vmx
->guest_msrs
[i
].data
,
1816 vmx
->guest_msrs
[i
].mask
);
1819 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1821 if (!vmx
->host_state
.loaded
)
1824 ++vmx
->vcpu
.stat
.host_state_reload
;
1825 vmx
->host_state
.loaded
= 0;
1826 #ifdef CONFIG_X86_64
1827 if (is_long_mode(&vmx
->vcpu
))
1828 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1830 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1831 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1832 #ifdef CONFIG_X86_64
1833 load_gs_index(vmx
->host_state
.gs_sel
);
1835 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1838 if (vmx
->host_state
.fs_reload_needed
)
1839 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1840 #ifdef CONFIG_X86_64
1841 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1842 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1843 loadsegment(es
, vmx
->host_state
.es_sel
);
1847 #ifdef CONFIG_X86_64
1848 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1850 if (vmx
->host_state
.msr_host_bndcfgs
)
1851 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1853 * If the FPU is not active (through the host task or
1854 * the guest vcpu), then restore the cr0.TS bit.
1856 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1858 load_gdt(this_cpu_ptr(&host_gdt
));
1861 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1864 __vmx_load_host_state(vmx
);
1869 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1870 * vcpu mutex is already taken.
1872 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1874 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1875 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1878 kvm_cpu_vmxon(phys_addr
);
1879 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1880 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1882 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1883 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1884 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1887 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1888 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1889 unsigned long sysenter_esp
;
1891 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1892 local_irq_disable();
1893 crash_disable_local_vmclear(cpu
);
1896 * Read loaded_vmcs->cpu should be before fetching
1897 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1898 * See the comments in __loaded_vmcs_clear().
1902 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1903 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1904 crash_enable_local_vmclear(cpu
);
1908 * Linux uses per-cpu TSS and GDT, so set these when switching
1911 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1912 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1914 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1915 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1916 vmx
->loaded_vmcs
->cpu
= cpu
;
1920 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1922 __vmx_load_host_state(to_vmx(vcpu
));
1923 if (!vmm_exclusive
) {
1924 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1930 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1934 if (vcpu
->fpu_active
)
1936 vcpu
->fpu_active
= 1;
1937 cr0
= vmcs_readl(GUEST_CR0
);
1938 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1939 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1940 vmcs_writel(GUEST_CR0
, cr0
);
1941 update_exception_bitmap(vcpu
);
1942 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1943 if (is_guest_mode(vcpu
))
1944 vcpu
->arch
.cr0_guest_owned_bits
&=
1945 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1946 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1949 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1952 * Return the cr0 value that a nested guest would read. This is a combination
1953 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1954 * its hypervisor (cr0_read_shadow).
1956 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1958 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1959 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1961 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1963 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1964 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1967 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1969 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1970 * set this *before* calling this function.
1972 vmx_decache_cr0_guest_bits(vcpu
);
1973 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1974 update_exception_bitmap(vcpu
);
1975 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1976 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1977 if (is_guest_mode(vcpu
)) {
1979 * L1's specified read shadow might not contain the TS bit,
1980 * so now that we turned on shadowing of this bit, we need to
1981 * set this bit of the shadow. Like in nested_vmx_run we need
1982 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1983 * up-to-date here because we just decached cr0.TS (and we'll
1984 * only update vmcs12->guest_cr0 on nested exit).
1986 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1987 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1988 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1989 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1991 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1994 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1996 unsigned long rflags
, save_rflags
;
1998 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1999 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2000 rflags
= vmcs_readl(GUEST_RFLAGS
);
2001 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2002 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2003 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2004 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2006 to_vmx(vcpu
)->rflags
= rflags
;
2008 return to_vmx(vcpu
)->rflags
;
2011 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2013 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2014 to_vmx(vcpu
)->rflags
= rflags
;
2015 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2016 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2017 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2019 vmcs_writel(GUEST_RFLAGS
, rflags
);
2022 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2024 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2027 if (interruptibility
& GUEST_INTR_STATE_STI
)
2028 ret
|= KVM_X86_SHADOW_INT_STI
;
2029 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2030 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2035 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2037 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2038 u32 interruptibility
= interruptibility_old
;
2040 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2042 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2043 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2044 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2045 interruptibility
|= GUEST_INTR_STATE_STI
;
2047 if ((interruptibility
!= interruptibility_old
))
2048 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2051 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2055 rip
= kvm_rip_read(vcpu
);
2056 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2057 kvm_rip_write(vcpu
, rip
);
2059 /* skipping an emulated instruction also counts */
2060 vmx_set_interrupt_shadow(vcpu
, 0);
2064 * KVM wants to inject page-faults which it got to the guest. This function
2065 * checks whether in a nested guest, we need to inject them to L1 or L2.
2067 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2069 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2071 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2074 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2075 vmcs_read32(VM_EXIT_INTR_INFO
),
2076 vmcs_readl(EXIT_QUALIFICATION
));
2080 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2081 bool has_error_code
, u32 error_code
,
2084 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2085 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2087 if (!reinject
&& is_guest_mode(vcpu
) &&
2088 nested_vmx_check_exception(vcpu
, nr
))
2091 if (has_error_code
) {
2092 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2093 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2096 if (vmx
->rmode
.vm86_active
) {
2098 if (kvm_exception_is_soft(nr
))
2099 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2100 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2101 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2105 if (kvm_exception_is_soft(nr
)) {
2106 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2107 vmx
->vcpu
.arch
.event_exit_inst_len
);
2108 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2110 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2112 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2115 static bool vmx_rdtscp_supported(void)
2117 return cpu_has_vmx_rdtscp();
2120 static bool vmx_invpcid_supported(void)
2122 return cpu_has_vmx_invpcid() && enable_ept
;
2126 * Swap MSR entry in host/guest MSR entry array.
2128 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2130 struct shared_msr_entry tmp
;
2132 tmp
= vmx
->guest_msrs
[to
];
2133 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2134 vmx
->guest_msrs
[from
] = tmp
;
2137 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2139 unsigned long *msr_bitmap
;
2141 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
2142 if (is_long_mode(vcpu
))
2143 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2145 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2147 if (is_long_mode(vcpu
))
2148 msr_bitmap
= vmx_msr_bitmap_longmode
;
2150 msr_bitmap
= vmx_msr_bitmap_legacy
;
2153 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2157 * Set up the vmcs to automatically save and restore system
2158 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2159 * mode, as fiddling with msrs is very expensive.
2161 static void setup_msrs(struct vcpu_vmx
*vmx
)
2163 int save_nmsrs
, index
;
2166 #ifdef CONFIG_X86_64
2167 if (is_long_mode(&vmx
->vcpu
)) {
2168 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2170 move_msr_up(vmx
, index
, save_nmsrs
++);
2171 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2173 move_msr_up(vmx
, index
, save_nmsrs
++);
2174 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2176 move_msr_up(vmx
, index
, save_nmsrs
++);
2177 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2178 if (index
>= 0 && vmx
->rdtscp_enabled
)
2179 move_msr_up(vmx
, index
, save_nmsrs
++);
2181 * MSR_STAR is only needed on long mode guests, and only
2182 * if efer.sce is enabled.
2184 index
= __find_msr_index(vmx
, MSR_STAR
);
2185 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2186 move_msr_up(vmx
, index
, save_nmsrs
++);
2189 index
= __find_msr_index(vmx
, MSR_EFER
);
2190 if (index
>= 0 && update_transition_efer(vmx
, index
))
2191 move_msr_up(vmx
, index
, save_nmsrs
++);
2193 vmx
->save_nmsrs
= save_nmsrs
;
2195 if (cpu_has_vmx_msr_bitmap())
2196 vmx_set_msr_bitmap(&vmx
->vcpu
);
2200 * reads and returns guest's timestamp counter "register"
2201 * guest_tsc = host_tsc + tsc_offset -- 21.3
2203 static u64
guest_read_tsc(void)
2205 u64 host_tsc
, tsc_offset
;
2208 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2209 return host_tsc
+ tsc_offset
;
2213 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2214 * counter, even if a nested guest (L2) is currently running.
2216 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2220 tsc_offset
= is_guest_mode(vcpu
) ?
2221 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2222 vmcs_read64(TSC_OFFSET
);
2223 return host_tsc
+ tsc_offset
;
2227 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2228 * software catchup for faster rates on slower CPUs.
2230 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2235 if (user_tsc_khz
> tsc_khz
) {
2236 vcpu
->arch
.tsc_catchup
= 1;
2237 vcpu
->arch
.tsc_always_catchup
= 1;
2239 WARN(1, "user requested TSC rate below hardware speed\n");
2242 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2244 return vmcs_read64(TSC_OFFSET
);
2248 * writes 'offset' into guest's timestamp counter offset register
2250 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2252 if (is_guest_mode(vcpu
)) {
2254 * We're here if L1 chose not to trap WRMSR to TSC. According
2255 * to the spec, this should set L1's TSC; The offset that L1
2256 * set for L2 remains unchanged, and still needs to be added
2257 * to the newly set TSC to get L2's TSC.
2259 struct vmcs12
*vmcs12
;
2260 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2261 /* recalculate vmcs02.TSC_OFFSET: */
2262 vmcs12
= get_vmcs12(vcpu
);
2263 vmcs_write64(TSC_OFFSET
, offset
+
2264 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2265 vmcs12
->tsc_offset
: 0));
2267 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2268 vmcs_read64(TSC_OFFSET
), offset
);
2269 vmcs_write64(TSC_OFFSET
, offset
);
2273 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2275 u64 offset
= vmcs_read64(TSC_OFFSET
);
2277 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2278 if (is_guest_mode(vcpu
)) {
2279 /* Even when running L2, the adjustment needs to apply to L1 */
2280 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2282 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2283 offset
+ adjustment
);
2286 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2288 return target_tsc
- native_read_tsc();
2291 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2293 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2294 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2298 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2299 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2300 * all guests if the "nested" module option is off, and can also be disabled
2301 * for a single guest by disabling its VMX cpuid bit.
2303 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2305 return nested
&& guest_cpuid_has_vmx(vcpu
);
2309 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2310 * returned for the various VMX controls MSRs when nested VMX is enabled.
2311 * The same values should also be used to verify that vmcs12 control fields are
2312 * valid during nested entry from L1 to L2.
2313 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2314 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2315 * bit in the high half is on if the corresponding bit in the control field
2316 * may be on. See also vmx_control_verify().
2318 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2321 * Note that as a general rule, the high half of the MSRs (bits in
2322 * the control fields which may be 1) should be initialized by the
2323 * intersection of the underlying hardware's MSR (i.e., features which
2324 * can be supported) and the list of features we want to expose -
2325 * because they are known to be properly supported in our code.
2326 * Also, usually, the low half of the MSRs (bits which must be 1) can
2327 * be set to 0, meaning that L1 may turn off any of these bits. The
2328 * reason is that if one of these bits is necessary, it will appear
2329 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2330 * fields of vmcs01 and vmcs02, will turn these bits off - and
2331 * nested_vmx_exit_handled() will not pass related exits to L1.
2332 * These rules have exceptions below.
2335 /* pin-based controls */
2336 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2337 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2338 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2339 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2340 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2341 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2342 PIN_BASED_EXT_INTR_MASK
|
2343 PIN_BASED_NMI_EXITING
|
2344 PIN_BASED_VIRTUAL_NMIS
;
2345 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2346 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2347 PIN_BASED_VMX_PREEMPTION_TIMER
;
2350 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2351 vmx
->nested
.nested_vmx_exit_ctls_low
,
2352 vmx
->nested
.nested_vmx_exit_ctls_high
);
2353 vmx
->nested
.nested_vmx_exit_ctls_low
=
2354 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2356 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2357 #ifdef CONFIG_X86_64
2358 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2360 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2361 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2362 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2363 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2364 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2366 if (vmx_mpx_supported())
2367 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2369 /* We support free control of debug control saving. */
2370 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2371 vmx
->nested
.nested_vmx_exit_ctls_low
&
2372 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2374 /* entry controls */
2375 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2376 vmx
->nested
.nested_vmx_entry_ctls_low
,
2377 vmx
->nested
.nested_vmx_entry_ctls_high
);
2378 vmx
->nested
.nested_vmx_entry_ctls_low
=
2379 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2380 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2381 #ifdef CONFIG_X86_64
2382 VM_ENTRY_IA32E_MODE
|
2384 VM_ENTRY_LOAD_IA32_PAT
;
2385 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2386 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2387 if (vmx_mpx_supported())
2388 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2390 /* We support free control of debug control loading. */
2391 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2392 vmx
->nested
.nested_vmx_entry_ctls_low
&
2393 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2395 /* cpu-based controls */
2396 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2397 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2398 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2399 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2400 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2401 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2402 CPU_BASED_VIRTUAL_INTR_PENDING
|
2403 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2404 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2405 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2406 CPU_BASED_CR3_STORE_EXITING
|
2407 #ifdef CONFIG_X86_64
2408 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2410 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2411 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2412 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2413 CPU_BASED_PAUSE_EXITING
| CPU_BASED_TPR_SHADOW
|
2414 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2416 * We can allow some features even when not supported by the
2417 * hardware. For example, L1 can specify an MSR bitmap - and we
2418 * can use it to avoid exits to L1 - even when L0 runs L2
2419 * without MSR bitmaps.
2421 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2422 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2423 CPU_BASED_USE_MSR_BITMAPS
;
2425 /* We support free control of CR3 access interception. */
2426 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2427 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2428 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2430 /* secondary cpu-based controls */
2431 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2432 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2433 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2434 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2435 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2436 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2437 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2438 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2439 SECONDARY_EXEC_WBINVD_EXITING
|
2440 SECONDARY_EXEC_XSAVES
;
2443 /* nested EPT: emulate EPT also to L1 */
2444 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2445 SECONDARY_EXEC_ENABLE_EPT
|
2446 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2447 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2448 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2450 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2452 * For nested guests, we don't do anything specific
2453 * for single context invalidation. Hence, only advertise
2454 * support for global context invalidation.
2456 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2458 vmx
->nested
.nested_vmx_ept_caps
= 0;
2460 /* miscellaneous data */
2461 rdmsr(MSR_IA32_VMX_MISC
,
2462 vmx
->nested
.nested_vmx_misc_low
,
2463 vmx
->nested
.nested_vmx_misc_high
);
2464 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2465 vmx
->nested
.nested_vmx_misc_low
|=
2466 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2467 VMX_MISC_ACTIVITY_HLT
;
2468 vmx
->nested
.nested_vmx_misc_high
= 0;
2471 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2474 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2476 return ((control
& high
) | low
) == control
;
2479 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2481 return low
| ((u64
)high
<< 32);
2484 /* Returns 0 on success, non-0 otherwise. */
2485 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2487 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2489 switch (msr_index
) {
2490 case MSR_IA32_VMX_BASIC
:
2492 * This MSR reports some information about VMX support. We
2493 * should return information about the VMX we emulate for the
2494 * guest, and the VMCS structure we give it - not about the
2495 * VMX support of the underlying hardware.
2497 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2498 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2499 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2501 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2502 case MSR_IA32_VMX_PINBASED_CTLS
:
2503 *pdata
= vmx_control_msr(
2504 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2505 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2507 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2508 *pdata
= vmx_control_msr(
2509 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2510 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2512 case MSR_IA32_VMX_PROCBASED_CTLS
:
2513 *pdata
= vmx_control_msr(
2514 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2515 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2517 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2518 *pdata
= vmx_control_msr(
2519 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2520 vmx
->nested
.nested_vmx_exit_ctls_high
);
2522 case MSR_IA32_VMX_EXIT_CTLS
:
2523 *pdata
= vmx_control_msr(
2524 vmx
->nested
.nested_vmx_exit_ctls_low
,
2525 vmx
->nested
.nested_vmx_exit_ctls_high
);
2527 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2528 *pdata
= vmx_control_msr(
2529 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2530 vmx
->nested
.nested_vmx_entry_ctls_high
);
2532 case MSR_IA32_VMX_ENTRY_CTLS
:
2533 *pdata
= vmx_control_msr(
2534 vmx
->nested
.nested_vmx_entry_ctls_low
,
2535 vmx
->nested
.nested_vmx_entry_ctls_high
);
2537 case MSR_IA32_VMX_MISC
:
2538 *pdata
= vmx_control_msr(
2539 vmx
->nested
.nested_vmx_misc_low
,
2540 vmx
->nested
.nested_vmx_misc_high
);
2543 * These MSRs specify bits which the guest must keep fixed (on or off)
2544 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2545 * We picked the standard core2 setting.
2547 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2548 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2549 case MSR_IA32_VMX_CR0_FIXED0
:
2550 *pdata
= VMXON_CR0_ALWAYSON
;
2552 case MSR_IA32_VMX_CR0_FIXED1
:
2555 case MSR_IA32_VMX_CR4_FIXED0
:
2556 *pdata
= VMXON_CR4_ALWAYSON
;
2558 case MSR_IA32_VMX_CR4_FIXED1
:
2561 case MSR_IA32_VMX_VMCS_ENUM
:
2562 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2564 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2565 *pdata
= vmx_control_msr(
2566 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2567 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2569 case MSR_IA32_VMX_EPT_VPID_CAP
:
2570 /* Currently, no nested vpid support */
2571 *pdata
= vmx
->nested
.nested_vmx_ept_caps
;
2581 * Reads an msr value (of 'msr_index') into 'pdata'.
2582 * Returns 0 on success, non-0 otherwise.
2583 * Assumes vcpu_load() was already called.
2585 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2588 struct shared_msr_entry
*msr
;
2591 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2595 switch (msr_index
) {
2596 #ifdef CONFIG_X86_64
2598 data
= vmcs_readl(GUEST_FS_BASE
);
2601 data
= vmcs_readl(GUEST_GS_BASE
);
2603 case MSR_KERNEL_GS_BASE
:
2604 vmx_load_host_state(to_vmx(vcpu
));
2605 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2609 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2611 data
= guest_read_tsc();
2613 case MSR_IA32_SYSENTER_CS
:
2614 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2616 case MSR_IA32_SYSENTER_EIP
:
2617 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2619 case MSR_IA32_SYSENTER_ESP
:
2620 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2622 case MSR_IA32_BNDCFGS
:
2623 if (!vmx_mpx_supported())
2625 data
= vmcs_read64(GUEST_BNDCFGS
);
2627 case MSR_IA32_FEATURE_CONTROL
:
2628 if (!nested_vmx_allowed(vcpu
))
2630 data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2632 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2633 if (!nested_vmx_allowed(vcpu
))
2635 return vmx_get_vmx_msr(vcpu
, msr_index
, pdata
);
2637 if (!vmx_xsaves_supported())
2639 data
= vcpu
->arch
.ia32_xss
;
2642 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2644 /* Otherwise falls through */
2646 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2651 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2658 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2661 * Writes msr value into into the appropriate "register".
2662 * Returns 0 on success, non-0 otherwise.
2663 * Assumes vcpu_load() was already called.
2665 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2667 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2668 struct shared_msr_entry
*msr
;
2670 u32 msr_index
= msr_info
->index
;
2671 u64 data
= msr_info
->data
;
2673 switch (msr_index
) {
2675 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2677 #ifdef CONFIG_X86_64
2679 vmx_segment_cache_clear(vmx
);
2680 vmcs_writel(GUEST_FS_BASE
, data
);
2683 vmx_segment_cache_clear(vmx
);
2684 vmcs_writel(GUEST_GS_BASE
, data
);
2686 case MSR_KERNEL_GS_BASE
:
2687 vmx_load_host_state(vmx
);
2688 vmx
->msr_guest_kernel_gs_base
= data
;
2691 case MSR_IA32_SYSENTER_CS
:
2692 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2694 case MSR_IA32_SYSENTER_EIP
:
2695 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2697 case MSR_IA32_SYSENTER_ESP
:
2698 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2700 case MSR_IA32_BNDCFGS
:
2701 if (!vmx_mpx_supported())
2703 vmcs_write64(GUEST_BNDCFGS
, data
);
2706 kvm_write_tsc(vcpu
, msr_info
);
2708 case MSR_IA32_CR_PAT
:
2709 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2710 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2712 vmcs_write64(GUEST_IA32_PAT
, data
);
2713 vcpu
->arch
.pat
= data
;
2716 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2718 case MSR_IA32_TSC_ADJUST
:
2719 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2721 case MSR_IA32_FEATURE_CONTROL
:
2722 if (!nested_vmx_allowed(vcpu
) ||
2723 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2724 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2726 vmx
->nested
.msr_ia32_feature_control
= data
;
2727 if (msr_info
->host_initiated
&& data
== 0)
2728 vmx_leave_nested(vcpu
);
2730 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2731 return 1; /* they are read-only */
2733 if (!vmx_xsaves_supported())
2736 * The only supported bit as of Skylake is bit 8, but
2737 * it is not supported on KVM.
2741 vcpu
->arch
.ia32_xss
= data
;
2742 if (vcpu
->arch
.ia32_xss
!= host_xss
)
2743 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
2744 vcpu
->arch
.ia32_xss
, host_xss
);
2746 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
2749 if (!vmx
->rdtscp_enabled
)
2751 /* Check reserved bit, higher 32 bits should be zero */
2752 if ((data
>> 32) != 0)
2754 /* Otherwise falls through */
2756 msr
= find_msr_entry(vmx
, msr_index
);
2758 u64 old_msr_data
= msr
->data
;
2760 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2762 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2766 msr
->data
= old_msr_data
;
2770 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2776 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2778 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2781 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2784 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2786 case VCPU_EXREG_PDPTR
:
2788 ept_save_pdptrs(vcpu
);
2795 static __init
int cpu_has_kvm_support(void)
2797 return cpu_has_vmx();
2800 static __init
int vmx_disabled_by_bios(void)
2804 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2805 if (msr
& FEATURE_CONTROL_LOCKED
) {
2806 /* launched w/ TXT and VMX disabled */
2807 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2810 /* launched w/o TXT and VMX only enabled w/ TXT */
2811 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2812 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2813 && !tboot_enabled()) {
2814 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2815 "activate TXT before enabling KVM\n");
2818 /* launched w/o TXT and VMX disabled */
2819 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2820 && !tboot_enabled())
2827 static void kvm_cpu_vmxon(u64 addr
)
2829 asm volatile (ASM_VMX_VMXON_RAX
2830 : : "a"(&addr
), "m"(addr
)
2834 static int hardware_enable(void)
2836 int cpu
= raw_smp_processor_id();
2837 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2840 if (read_cr4() & X86_CR4_VMXE
)
2843 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2846 * Now we can enable the vmclear operation in kdump
2847 * since the loaded_vmcss_on_cpu list on this cpu
2848 * has been initialized.
2850 * Though the cpu is not in VMX operation now, there
2851 * is no problem to enable the vmclear operation
2852 * for the loaded_vmcss_on_cpu list is empty!
2854 crash_enable_local_vmclear(cpu
);
2856 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2858 test_bits
= FEATURE_CONTROL_LOCKED
;
2859 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2860 if (tboot_enabled())
2861 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2863 if ((old
& test_bits
) != test_bits
) {
2864 /* enable and lock */
2865 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2867 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2869 if (vmm_exclusive
) {
2870 kvm_cpu_vmxon(phys_addr
);
2874 native_store_gdt(this_cpu_ptr(&host_gdt
));
2879 static void vmclear_local_loaded_vmcss(void)
2881 int cpu
= raw_smp_processor_id();
2882 struct loaded_vmcs
*v
, *n
;
2884 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2885 loaded_vmcss_on_cpu_link
)
2886 __loaded_vmcs_clear(v
);
2890 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2893 static void kvm_cpu_vmxoff(void)
2895 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2898 static void hardware_disable(void)
2900 if (vmm_exclusive
) {
2901 vmclear_local_loaded_vmcss();
2904 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2907 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2908 u32 msr
, u32
*result
)
2910 u32 vmx_msr_low
, vmx_msr_high
;
2911 u32 ctl
= ctl_min
| ctl_opt
;
2913 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2915 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2916 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2918 /* Ensure minimum (required) set of control bits are supported. */
2926 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2928 u32 vmx_msr_low
, vmx_msr_high
;
2930 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2931 return vmx_msr_high
& ctl
;
2934 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2936 u32 vmx_msr_low
, vmx_msr_high
;
2937 u32 min
, opt
, min2
, opt2
;
2938 u32 _pin_based_exec_control
= 0;
2939 u32 _cpu_based_exec_control
= 0;
2940 u32 _cpu_based_2nd_exec_control
= 0;
2941 u32 _vmexit_control
= 0;
2942 u32 _vmentry_control
= 0;
2944 min
= CPU_BASED_HLT_EXITING
|
2945 #ifdef CONFIG_X86_64
2946 CPU_BASED_CR8_LOAD_EXITING
|
2947 CPU_BASED_CR8_STORE_EXITING
|
2949 CPU_BASED_CR3_LOAD_EXITING
|
2950 CPU_BASED_CR3_STORE_EXITING
|
2951 CPU_BASED_USE_IO_BITMAPS
|
2952 CPU_BASED_MOV_DR_EXITING
|
2953 CPU_BASED_USE_TSC_OFFSETING
|
2954 CPU_BASED_MWAIT_EXITING
|
2955 CPU_BASED_MONITOR_EXITING
|
2956 CPU_BASED_INVLPG_EXITING
|
2957 CPU_BASED_RDPMC_EXITING
;
2959 opt
= CPU_BASED_TPR_SHADOW
|
2960 CPU_BASED_USE_MSR_BITMAPS
|
2961 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2962 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2963 &_cpu_based_exec_control
) < 0)
2965 #ifdef CONFIG_X86_64
2966 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2967 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2968 ~CPU_BASED_CR8_STORE_EXITING
;
2970 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2972 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2973 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2974 SECONDARY_EXEC_WBINVD_EXITING
|
2975 SECONDARY_EXEC_ENABLE_VPID
|
2976 SECONDARY_EXEC_ENABLE_EPT
|
2977 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2978 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2979 SECONDARY_EXEC_RDTSCP
|
2980 SECONDARY_EXEC_ENABLE_INVPCID
|
2981 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2982 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2983 SECONDARY_EXEC_SHADOW_VMCS
|
2984 SECONDARY_EXEC_XSAVES
|
2985 SECONDARY_EXEC_ENABLE_PML
;
2986 if (adjust_vmx_controls(min2
, opt2
,
2987 MSR_IA32_VMX_PROCBASED_CTLS2
,
2988 &_cpu_based_2nd_exec_control
) < 0)
2991 #ifndef CONFIG_X86_64
2992 if (!(_cpu_based_2nd_exec_control
&
2993 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2994 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2997 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2998 _cpu_based_2nd_exec_control
&= ~(
2999 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3000 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3001 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3003 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3004 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3006 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3007 CPU_BASED_CR3_STORE_EXITING
|
3008 CPU_BASED_INVLPG_EXITING
);
3009 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3010 vmx_capability
.ept
, vmx_capability
.vpid
);
3013 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
3014 #ifdef CONFIG_X86_64
3015 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3017 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3018 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
3019 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3020 &_vmexit_control
) < 0)
3023 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3024 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
3025 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3026 &_pin_based_exec_control
) < 0)
3029 if (!(_cpu_based_2nd_exec_control
&
3030 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
3031 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
3032 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3034 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3035 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3036 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3037 &_vmentry_control
) < 0)
3040 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3042 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3043 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3046 #ifdef CONFIG_X86_64
3047 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3048 if (vmx_msr_high
& (1u<<16))
3052 /* Require Write-Back (WB) memory type for VMCS accesses. */
3053 if (((vmx_msr_high
>> 18) & 15) != 6)
3056 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3057 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3058 vmcs_conf
->revision_id
= vmx_msr_low
;
3060 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3061 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3062 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3063 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3064 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3066 cpu_has_load_ia32_efer
=
3067 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3068 VM_ENTRY_LOAD_IA32_EFER
)
3069 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3070 VM_EXIT_LOAD_IA32_EFER
);
3072 cpu_has_load_perf_global_ctrl
=
3073 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3074 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3075 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3076 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3079 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3080 * but due to arrata below it can't be used. Workaround is to use
3081 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3083 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3088 * BC86,AAY89,BD102 (model 44)
3092 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3093 switch (boot_cpu_data
.x86_model
) {
3099 cpu_has_load_perf_global_ctrl
= false;
3100 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3101 "does not work properly. Using workaround\n");
3109 rdmsrl(MSR_IA32_XSS
, host_xss
);
3114 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3116 int node
= cpu_to_node(cpu
);
3120 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3123 vmcs
= page_address(pages
);
3124 memset(vmcs
, 0, vmcs_config
.size
);
3125 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3129 static struct vmcs
*alloc_vmcs(void)
3131 return alloc_vmcs_cpu(raw_smp_processor_id());
3134 static void free_vmcs(struct vmcs
*vmcs
)
3136 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3140 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3142 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3144 if (!loaded_vmcs
->vmcs
)
3146 loaded_vmcs_clear(loaded_vmcs
);
3147 free_vmcs(loaded_vmcs
->vmcs
);
3148 loaded_vmcs
->vmcs
= NULL
;
3151 static void free_kvm_area(void)
3155 for_each_possible_cpu(cpu
) {
3156 free_vmcs(per_cpu(vmxarea
, cpu
));
3157 per_cpu(vmxarea
, cpu
) = NULL
;
3161 static void init_vmcs_shadow_fields(void)
3165 /* No checks for read only fields yet */
3167 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3168 switch (shadow_read_write_fields
[i
]) {
3170 if (!vmx_mpx_supported())
3178 shadow_read_write_fields
[j
] =
3179 shadow_read_write_fields
[i
];
3182 max_shadow_read_write_fields
= j
;
3184 /* shadowed fields guest access without vmexit */
3185 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3186 clear_bit(shadow_read_write_fields
[i
],
3187 vmx_vmwrite_bitmap
);
3188 clear_bit(shadow_read_write_fields
[i
],
3191 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3192 clear_bit(shadow_read_only_fields
[i
],
3196 static __init
int alloc_kvm_area(void)
3200 for_each_possible_cpu(cpu
) {
3203 vmcs
= alloc_vmcs_cpu(cpu
);
3209 per_cpu(vmxarea
, cpu
) = vmcs
;
3214 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3216 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3219 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3220 struct kvm_segment
*save
)
3222 if (!emulate_invalid_guest_state
) {
3224 * CS and SS RPL should be equal during guest entry according
3225 * to VMX spec, but in reality it is not always so. Since vcpu
3226 * is in the middle of the transition from real mode to
3227 * protected mode it is safe to assume that RPL 0 is a good
3230 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3231 save
->selector
&= ~SELECTOR_RPL_MASK
;
3232 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3235 vmx_set_segment(vcpu
, save
, seg
);
3238 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3240 unsigned long flags
;
3241 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3244 * Update real mode segment cache. It may be not up-to-date if sement
3245 * register was written while vcpu was in a guest mode.
3247 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3248 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3249 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3250 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3251 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3252 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3254 vmx
->rmode
.vm86_active
= 0;
3256 vmx_segment_cache_clear(vmx
);
3258 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3260 flags
= vmcs_readl(GUEST_RFLAGS
);
3261 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3262 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3263 vmcs_writel(GUEST_RFLAGS
, flags
);
3265 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3266 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3268 update_exception_bitmap(vcpu
);
3270 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3271 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3272 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3273 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3274 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3275 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3278 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3280 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3281 struct kvm_segment var
= *save
;
3284 if (seg
== VCPU_SREG_CS
)
3287 if (!emulate_invalid_guest_state
) {
3288 var
.selector
= var
.base
>> 4;
3289 var
.base
= var
.base
& 0xffff0;
3299 if (save
->base
& 0xf)
3300 printk_once(KERN_WARNING
"kvm: segment base is not "
3301 "paragraph aligned when entering "
3302 "protected mode (seg=%d)", seg
);
3305 vmcs_write16(sf
->selector
, var
.selector
);
3306 vmcs_write32(sf
->base
, var
.base
);
3307 vmcs_write32(sf
->limit
, var
.limit
);
3308 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3311 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3313 unsigned long flags
;
3314 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3316 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3317 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3318 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3319 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3320 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3321 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3322 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3324 vmx
->rmode
.vm86_active
= 1;
3327 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3328 * vcpu. Warn the user that an update is overdue.
3330 if (!vcpu
->kvm
->arch
.tss_addr
)
3331 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3332 "called before entering vcpu\n");
3334 vmx_segment_cache_clear(vmx
);
3336 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3337 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3338 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3340 flags
= vmcs_readl(GUEST_RFLAGS
);
3341 vmx
->rmode
.save_rflags
= flags
;
3343 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3345 vmcs_writel(GUEST_RFLAGS
, flags
);
3346 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3347 update_exception_bitmap(vcpu
);
3349 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3350 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3351 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3352 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3353 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3354 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3356 kvm_mmu_reset_context(vcpu
);
3359 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3361 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3362 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3368 * Force kernel_gs_base reloading before EFER changes, as control
3369 * of this msr depends on is_long_mode().
3371 vmx_load_host_state(to_vmx(vcpu
));
3372 vcpu
->arch
.efer
= efer
;
3373 if (efer
& EFER_LMA
) {
3374 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3377 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3379 msr
->data
= efer
& ~EFER_LME
;
3384 #ifdef CONFIG_X86_64
3386 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3390 vmx_segment_cache_clear(to_vmx(vcpu
));
3392 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3393 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3394 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3396 vmcs_write32(GUEST_TR_AR_BYTES
,
3397 (guest_tr_ar
& ~AR_TYPE_MASK
)
3398 | AR_TYPE_BUSY_64_TSS
);
3400 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3403 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3405 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3406 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3411 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3413 vpid_sync_context(to_vmx(vcpu
));
3415 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3417 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3421 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3423 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3425 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3426 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3429 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3431 if (enable_ept
&& is_paging(vcpu
))
3432 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3433 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3436 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3438 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3440 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3441 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3444 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3446 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3448 if (!test_bit(VCPU_EXREG_PDPTR
,
3449 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3452 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3453 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3454 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3455 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3456 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3460 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3462 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3464 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3465 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3466 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3467 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3468 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3471 __set_bit(VCPU_EXREG_PDPTR
,
3472 (unsigned long *)&vcpu
->arch
.regs_avail
);
3473 __set_bit(VCPU_EXREG_PDPTR
,
3474 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3477 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3479 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3481 struct kvm_vcpu
*vcpu
)
3483 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3484 vmx_decache_cr3(vcpu
);
3485 if (!(cr0
& X86_CR0_PG
)) {
3486 /* From paging/starting to nonpaging */
3487 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3488 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3489 (CPU_BASED_CR3_LOAD_EXITING
|
3490 CPU_BASED_CR3_STORE_EXITING
));
3491 vcpu
->arch
.cr0
= cr0
;
3492 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3493 } else if (!is_paging(vcpu
)) {
3494 /* From nonpaging to paging */
3495 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3496 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3497 ~(CPU_BASED_CR3_LOAD_EXITING
|
3498 CPU_BASED_CR3_STORE_EXITING
));
3499 vcpu
->arch
.cr0
= cr0
;
3500 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3503 if (!(cr0
& X86_CR0_WP
))
3504 *hw_cr0
&= ~X86_CR0_WP
;
3507 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3509 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3510 unsigned long hw_cr0
;
3512 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3513 if (enable_unrestricted_guest
)
3514 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3516 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3518 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3521 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3525 #ifdef CONFIG_X86_64
3526 if (vcpu
->arch
.efer
& EFER_LME
) {
3527 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3529 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3535 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3537 if (!vcpu
->fpu_active
)
3538 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3540 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3541 vmcs_writel(GUEST_CR0
, hw_cr0
);
3542 vcpu
->arch
.cr0
= cr0
;
3544 /* depends on vcpu->arch.cr0 to be set to a new value */
3545 vmx
->emulation_required
= emulation_required(vcpu
);
3548 static u64
construct_eptp(unsigned long root_hpa
)
3552 /* TODO write the value reading from MSR */
3553 eptp
= VMX_EPT_DEFAULT_MT
|
3554 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3555 if (enable_ept_ad_bits
)
3556 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3557 eptp
|= (root_hpa
& PAGE_MASK
);
3562 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3564 unsigned long guest_cr3
;
3569 eptp
= construct_eptp(cr3
);
3570 vmcs_write64(EPT_POINTER
, eptp
);
3571 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3572 guest_cr3
= kvm_read_cr3(vcpu
);
3574 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3575 ept_load_pdptrs(vcpu
);
3578 vmx_flush_tlb(vcpu
);
3579 vmcs_writel(GUEST_CR3
, guest_cr3
);
3582 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3584 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3585 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3587 if (cr4
& X86_CR4_VMXE
) {
3589 * To use VMXON (and later other VMX instructions), a guest
3590 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3591 * So basically the check on whether to allow nested VMX
3594 if (!nested_vmx_allowed(vcpu
))
3597 if (to_vmx(vcpu
)->nested
.vmxon
&&
3598 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3601 vcpu
->arch
.cr4
= cr4
;
3603 if (!is_paging(vcpu
)) {
3604 hw_cr4
&= ~X86_CR4_PAE
;
3605 hw_cr4
|= X86_CR4_PSE
;
3607 * SMEP/SMAP is disabled if CPU is in non-paging mode
3608 * in hardware. However KVM always uses paging mode to
3609 * emulate guest non-paging mode with TDP.
3610 * To emulate this behavior, SMEP/SMAP needs to be
3611 * manually disabled when guest switches to non-paging
3614 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3615 } else if (!(cr4
& X86_CR4_PAE
)) {
3616 hw_cr4
&= ~X86_CR4_PAE
;
3620 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3621 vmcs_writel(GUEST_CR4
, hw_cr4
);
3625 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3626 struct kvm_segment
*var
, int seg
)
3628 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3631 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3632 *var
= vmx
->rmode
.segs
[seg
];
3633 if (seg
== VCPU_SREG_TR
3634 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3636 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3637 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3640 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3641 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3642 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3643 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3644 var
->unusable
= (ar
>> 16) & 1;
3645 var
->type
= ar
& 15;
3646 var
->s
= (ar
>> 4) & 1;
3647 var
->dpl
= (ar
>> 5) & 3;
3649 * Some userspaces do not preserve unusable property. Since usable
3650 * segment has to be present according to VMX spec we can use present
3651 * property to amend userspace bug by making unusable segment always
3652 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3653 * segment as unusable.
3655 var
->present
= !var
->unusable
;
3656 var
->avl
= (ar
>> 12) & 1;
3657 var
->l
= (ar
>> 13) & 1;
3658 var
->db
= (ar
>> 14) & 1;
3659 var
->g
= (ar
>> 15) & 1;
3662 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3664 struct kvm_segment s
;
3666 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3667 vmx_get_segment(vcpu
, &s
, seg
);
3670 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3673 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3675 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3677 if (unlikely(vmx
->rmode
.vm86_active
))
3680 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3685 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3689 if (var
->unusable
|| !var
->present
)
3692 ar
= var
->type
& 15;
3693 ar
|= (var
->s
& 1) << 4;
3694 ar
|= (var
->dpl
& 3) << 5;
3695 ar
|= (var
->present
& 1) << 7;
3696 ar
|= (var
->avl
& 1) << 12;
3697 ar
|= (var
->l
& 1) << 13;
3698 ar
|= (var
->db
& 1) << 14;
3699 ar
|= (var
->g
& 1) << 15;
3705 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3706 struct kvm_segment
*var
, int seg
)
3708 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3709 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3711 vmx_segment_cache_clear(vmx
);
3713 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3714 vmx
->rmode
.segs
[seg
] = *var
;
3715 if (seg
== VCPU_SREG_TR
)
3716 vmcs_write16(sf
->selector
, var
->selector
);
3718 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3722 vmcs_writel(sf
->base
, var
->base
);
3723 vmcs_write32(sf
->limit
, var
->limit
);
3724 vmcs_write16(sf
->selector
, var
->selector
);
3727 * Fix the "Accessed" bit in AR field of segment registers for older
3729 * IA32 arch specifies that at the time of processor reset the
3730 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3731 * is setting it to 0 in the userland code. This causes invalid guest
3732 * state vmexit when "unrestricted guest" mode is turned on.
3733 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3734 * tree. Newer qemu binaries with that qemu fix would not need this
3737 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3738 var
->type
|= 0x1; /* Accessed */
3740 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3743 vmx
->emulation_required
= emulation_required(vcpu
);
3746 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3748 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3750 *db
= (ar
>> 14) & 1;
3751 *l
= (ar
>> 13) & 1;
3754 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3756 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3757 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3760 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3762 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3763 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3766 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3768 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3769 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3772 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3774 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3775 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3778 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3780 struct kvm_segment var
;
3783 vmx_get_segment(vcpu
, &var
, seg
);
3785 if (seg
== VCPU_SREG_CS
)
3787 ar
= vmx_segment_access_rights(&var
);
3789 if (var
.base
!= (var
.selector
<< 4))
3791 if (var
.limit
!= 0xffff)
3799 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3801 struct kvm_segment cs
;
3802 unsigned int cs_rpl
;
3804 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3805 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3809 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3813 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3814 if (cs
.dpl
> cs_rpl
)
3817 if (cs
.dpl
!= cs_rpl
)
3823 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3827 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3829 struct kvm_segment ss
;
3830 unsigned int ss_rpl
;
3832 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3833 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3837 if (ss
.type
!= 3 && ss
.type
!= 7)
3841 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3849 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3851 struct kvm_segment var
;
3854 vmx_get_segment(vcpu
, &var
, seg
);
3855 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3863 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3864 if (var
.dpl
< rpl
) /* DPL < RPL */
3868 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3874 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3876 struct kvm_segment tr
;
3878 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3882 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3884 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3892 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3894 struct kvm_segment ldtr
;
3896 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3900 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3910 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3912 struct kvm_segment cs
, ss
;
3914 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3915 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3917 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3918 (ss
.selector
& SELECTOR_RPL_MASK
));
3922 * Check if guest state is valid. Returns true if valid, false if
3924 * We assume that registers are always usable
3926 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3928 if (enable_unrestricted_guest
)
3931 /* real mode guest state checks */
3932 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3933 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3935 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3937 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3939 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3941 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3943 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3946 /* protected mode guest state checks */
3947 if (!cs_ss_rpl_check(vcpu
))
3949 if (!code_segment_valid(vcpu
))
3951 if (!stack_segment_valid(vcpu
))
3953 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3955 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3957 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3959 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3961 if (!tr_valid(vcpu
))
3963 if (!ldtr_valid(vcpu
))
3967 * - Add checks on RIP
3968 * - Add checks on RFLAGS
3974 static int init_rmode_tss(struct kvm
*kvm
)
3980 idx
= srcu_read_lock(&kvm
->srcu
);
3981 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3982 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3985 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3986 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3987 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3990 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3993 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3997 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3998 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4001 srcu_read_unlock(&kvm
->srcu
, idx
);
4005 static int init_rmode_identity_map(struct kvm
*kvm
)
4008 pfn_t identity_map_pfn
;
4014 /* Protect kvm->arch.ept_identity_pagetable_done. */
4015 mutex_lock(&kvm
->slots_lock
);
4017 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4020 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4022 r
= alloc_identity_pagetable(kvm
);
4026 idx
= srcu_read_lock(&kvm
->srcu
);
4027 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4030 /* Set up identity-mapping pagetable for EPT in real mode */
4031 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4032 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4033 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4034 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4035 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4039 kvm
->arch
.ept_identity_pagetable_done
= true;
4042 srcu_read_unlock(&kvm
->srcu
, idx
);
4045 mutex_unlock(&kvm
->slots_lock
);
4049 static void seg_setup(int seg
)
4051 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4054 vmcs_write16(sf
->selector
, 0);
4055 vmcs_writel(sf
->base
, 0);
4056 vmcs_write32(sf
->limit
, 0xffff);
4058 if (seg
== VCPU_SREG_CS
)
4059 ar
|= 0x08; /* code segment */
4061 vmcs_write32(sf
->ar_bytes
, ar
);
4064 static int alloc_apic_access_page(struct kvm
*kvm
)
4067 struct kvm_userspace_memory_region kvm_userspace_mem
;
4070 mutex_lock(&kvm
->slots_lock
);
4071 if (kvm
->arch
.apic_access_page_done
)
4073 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
4074 kvm_userspace_mem
.flags
= 0;
4075 kvm_userspace_mem
.guest_phys_addr
= APIC_DEFAULT_PHYS_BASE
;
4076 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4077 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4081 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4082 if (is_error_page(page
)) {
4088 * Do not pin the page in memory, so that memory hot-unplug
4089 * is able to migrate it.
4092 kvm
->arch
.apic_access_page_done
= true;
4094 mutex_unlock(&kvm
->slots_lock
);
4098 static int alloc_identity_pagetable(struct kvm
*kvm
)
4100 /* Called with kvm->slots_lock held. */
4102 struct kvm_userspace_memory_region kvm_userspace_mem
;
4105 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4107 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
4108 kvm_userspace_mem
.flags
= 0;
4109 kvm_userspace_mem
.guest_phys_addr
=
4110 kvm
->arch
.ept_identity_map_addr
;
4111 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4112 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4117 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4124 spin_lock(&vmx_vpid_lock
);
4125 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4126 if (vpid
< VMX_NR_VPIDS
) {
4128 __set_bit(vpid
, vmx_vpid_bitmap
);
4130 spin_unlock(&vmx_vpid_lock
);
4133 static void free_vpid(struct vcpu_vmx
*vmx
)
4137 spin_lock(&vmx_vpid_lock
);
4139 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4140 spin_unlock(&vmx_vpid_lock
);
4143 #define MSR_TYPE_R 1
4144 #define MSR_TYPE_W 2
4145 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4148 int f
= sizeof(unsigned long);
4150 if (!cpu_has_vmx_msr_bitmap())
4154 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4155 * have the write-low and read-high bitmap offsets the wrong way round.
4156 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4158 if (msr
<= 0x1fff) {
4159 if (type
& MSR_TYPE_R
)
4161 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4163 if (type
& MSR_TYPE_W
)
4165 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4167 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4169 if (type
& MSR_TYPE_R
)
4171 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4173 if (type
& MSR_TYPE_W
)
4175 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4180 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4183 int f
= sizeof(unsigned long);
4185 if (!cpu_has_vmx_msr_bitmap())
4189 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4190 * have the write-low and read-high bitmap offsets the wrong way round.
4191 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4193 if (msr
<= 0x1fff) {
4194 if (type
& MSR_TYPE_R
)
4196 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4198 if (type
& MSR_TYPE_W
)
4200 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4202 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4204 if (type
& MSR_TYPE_R
)
4206 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4208 if (type
& MSR_TYPE_W
)
4210 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4216 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4217 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4219 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4220 unsigned long *msr_bitmap_nested
,
4223 int f
= sizeof(unsigned long);
4225 if (!cpu_has_vmx_msr_bitmap()) {
4231 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4232 * have the write-low and read-high bitmap offsets the wrong way round.
4233 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4235 if (msr
<= 0x1fff) {
4236 if (type
& MSR_TYPE_R
&&
4237 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4239 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4241 if (type
& MSR_TYPE_W
&&
4242 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4244 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4246 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4248 if (type
& MSR_TYPE_R
&&
4249 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4251 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4253 if (type
& MSR_TYPE_W
&&
4254 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4256 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4261 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4264 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4265 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4266 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4267 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4270 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4272 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4274 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4278 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4280 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4282 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4286 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4288 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4290 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4294 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4296 return enable_apicv
&& irqchip_in_kernel(kvm
);
4300 * Send interrupt to vcpu via posted interrupt way.
4301 * 1. If target vcpu is running(non-root mode), send posted interrupt
4302 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4303 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4304 * interrupt from PIR in next vmentry.
4306 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4308 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4311 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4314 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4315 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4317 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4318 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4319 POSTED_INTR_VECTOR
);
4322 kvm_vcpu_kick(vcpu
);
4325 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4327 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4329 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4332 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4335 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4341 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4342 * will not change in the lifetime of the guest.
4343 * Note that host-state that does change is set elsewhere. E.g., host-state
4344 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4346 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4353 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4354 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4356 /* Save the most likely value for this task's CR4 in the VMCS. */
4358 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4359 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4361 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4362 #ifdef CONFIG_X86_64
4364 * Load null selectors, so we can avoid reloading them in
4365 * __vmx_load_host_state(), in case userspace uses the null selectors
4366 * too (the expected case).
4368 vmcs_write16(HOST_DS_SELECTOR
, 0);
4369 vmcs_write16(HOST_ES_SELECTOR
, 0);
4371 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4372 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4374 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4375 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4377 native_store_idt(&dt
);
4378 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4379 vmx
->host_idt_base
= dt
.address
;
4381 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4383 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4384 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4385 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4386 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4388 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4389 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4390 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4394 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4396 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4398 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4399 if (is_guest_mode(&vmx
->vcpu
))
4400 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4401 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4402 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4405 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4407 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4409 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4410 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4411 return pin_based_exec_ctrl
;
4414 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4416 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4418 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4419 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4421 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4422 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4423 #ifdef CONFIG_X86_64
4424 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4425 CPU_BASED_CR8_LOAD_EXITING
;
4429 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4430 CPU_BASED_CR3_LOAD_EXITING
|
4431 CPU_BASED_INVLPG_EXITING
;
4432 return exec_control
;
4435 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4437 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4438 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4439 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4441 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4443 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4444 enable_unrestricted_guest
= 0;
4445 /* Enable INVPCID for non-ept guests may cause performance regression. */
4446 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4448 if (!enable_unrestricted_guest
)
4449 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4451 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4452 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4453 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4454 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4455 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4456 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4458 We can NOT enable shadow_vmcs here because we don't have yet
4461 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4462 /* PML is enabled/disabled in creating/destorying vcpu */
4463 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4465 return exec_control
;
4468 static void ept_set_mmio_spte_mask(void)
4471 * EPT Misconfigurations can be generated if the value of bits 2:0
4472 * of an EPT paging-structure entry is 110b (write/execute).
4473 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4476 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4479 #define VMX_XSS_EXIT_BITMAP 0
4481 * Sets up the vmcs for emulated real mode.
4483 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4485 #ifdef CONFIG_X86_64
4491 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4492 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4494 if (enable_shadow_vmcs
) {
4495 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4496 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4498 if (cpu_has_vmx_msr_bitmap())
4499 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4501 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4504 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4506 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4508 if (cpu_has_secondary_exec_ctrls()) {
4509 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4510 vmx_secondary_exec_control(vmx
));
4513 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4514 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4515 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4516 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4517 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4519 vmcs_write16(GUEST_INTR_STATUS
, 0);
4521 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4522 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4526 vmcs_write32(PLE_GAP
, ple_gap
);
4527 vmx
->ple_window
= ple_window
;
4528 vmx
->ple_window_dirty
= true;
4531 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4532 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4533 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4535 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4536 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4537 vmx_set_constant_host_state(vmx
);
4538 #ifdef CONFIG_X86_64
4539 rdmsrl(MSR_FS_BASE
, a
);
4540 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4541 rdmsrl(MSR_GS_BASE
, a
);
4542 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4544 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4545 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4548 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4549 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4550 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4551 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4552 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4554 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4555 u32 msr_low
, msr_high
;
4557 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4558 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4559 /* Write the default value follow host pat */
4560 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4561 /* Keep arch.pat sync with GUEST_IA32_PAT */
4562 vmx
->vcpu
.arch
.pat
= host_pat
;
4565 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4566 u32 index
= vmx_msr_index
[i
];
4567 u32 data_low
, data_high
;
4570 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4572 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4574 vmx
->guest_msrs
[j
].index
= i
;
4575 vmx
->guest_msrs
[j
].data
= 0;
4576 vmx
->guest_msrs
[j
].mask
= -1ull;
4581 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4583 /* 22.2.1, 20.8.1 */
4584 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4586 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4587 set_cr4_guest_host_mask(vmx
);
4589 if (vmx_xsaves_supported())
4590 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4595 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4597 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4598 struct msr_data apic_base_msr
;
4600 vmx
->rmode
.vm86_active
= 0;
4602 vmx
->soft_vnmi_blocked
= 0;
4604 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4605 kvm_set_cr8(&vmx
->vcpu
, 0);
4606 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
;
4607 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4608 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4609 apic_base_msr
.host_initiated
= true;
4610 kvm_set_apic_base(&vmx
->vcpu
, &apic_base_msr
);
4612 vmx_segment_cache_clear(vmx
);
4614 seg_setup(VCPU_SREG_CS
);
4615 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4616 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4618 seg_setup(VCPU_SREG_DS
);
4619 seg_setup(VCPU_SREG_ES
);
4620 seg_setup(VCPU_SREG_FS
);
4621 seg_setup(VCPU_SREG_GS
);
4622 seg_setup(VCPU_SREG_SS
);
4624 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4625 vmcs_writel(GUEST_TR_BASE
, 0);
4626 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4627 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4629 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4630 vmcs_writel(GUEST_LDTR_BASE
, 0);
4631 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4632 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4634 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4635 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4636 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4638 vmcs_writel(GUEST_RFLAGS
, 0x02);
4639 kvm_rip_write(vcpu
, 0xfff0);
4641 vmcs_writel(GUEST_GDTR_BASE
, 0);
4642 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4644 vmcs_writel(GUEST_IDTR_BASE
, 0);
4645 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4647 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4648 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4649 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4651 /* Special registers */
4652 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4656 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4658 if (cpu_has_vmx_tpr_shadow()) {
4659 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4660 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4661 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4662 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4663 vmcs_write32(TPR_THRESHOLD
, 0);
4666 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
4668 if (vmx_vm_has_apicv(vcpu
->kvm
))
4669 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4672 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4674 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4675 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4676 vmx_set_cr4(&vmx
->vcpu
, 0);
4677 vmx_set_efer(&vmx
->vcpu
, 0);
4678 vmx_fpu_activate(&vmx
->vcpu
);
4679 update_exception_bitmap(&vmx
->vcpu
);
4681 vpid_sync_context(vmx
);
4685 * In nested virtualization, check if L1 asked to exit on external interrupts.
4686 * For most existing hypervisors, this will always return true.
4688 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4690 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4691 PIN_BASED_EXT_INTR_MASK
;
4695 * In nested virtualization, check if L1 has set
4696 * VM_EXIT_ACK_INTR_ON_EXIT
4698 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4700 return get_vmcs12(vcpu
)->vm_exit_controls
&
4701 VM_EXIT_ACK_INTR_ON_EXIT
;
4704 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4706 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4707 PIN_BASED_NMI_EXITING
;
4710 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4712 u32 cpu_based_vm_exec_control
;
4714 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4715 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4716 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4719 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4721 u32 cpu_based_vm_exec_control
;
4723 if (!cpu_has_virtual_nmis() ||
4724 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4725 enable_irq_window(vcpu
);
4729 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4730 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4731 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4734 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4736 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4738 int irq
= vcpu
->arch
.interrupt
.nr
;
4740 trace_kvm_inj_virq(irq
);
4742 ++vcpu
->stat
.irq_injections
;
4743 if (vmx
->rmode
.vm86_active
) {
4745 if (vcpu
->arch
.interrupt
.soft
)
4746 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4747 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4748 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4751 intr
= irq
| INTR_INFO_VALID_MASK
;
4752 if (vcpu
->arch
.interrupt
.soft
) {
4753 intr
|= INTR_TYPE_SOFT_INTR
;
4754 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4755 vmx
->vcpu
.arch
.event_exit_inst_len
);
4757 intr
|= INTR_TYPE_EXT_INTR
;
4758 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4761 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4763 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4765 if (is_guest_mode(vcpu
))
4768 if (!cpu_has_virtual_nmis()) {
4770 * Tracking the NMI-blocked state in software is built upon
4771 * finding the next open IRQ window. This, in turn, depends on
4772 * well-behaving guests: They have to keep IRQs disabled at
4773 * least as long as the NMI handler runs. Otherwise we may
4774 * cause NMI nesting, maybe breaking the guest. But as this is
4775 * highly unlikely, we can live with the residual risk.
4777 vmx
->soft_vnmi_blocked
= 1;
4778 vmx
->vnmi_blocked_time
= 0;
4781 ++vcpu
->stat
.nmi_injections
;
4782 vmx
->nmi_known_unmasked
= false;
4783 if (vmx
->rmode
.vm86_active
) {
4784 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4785 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4788 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4789 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4792 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4794 if (!cpu_has_virtual_nmis())
4795 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4796 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4798 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4801 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4803 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4805 if (!cpu_has_virtual_nmis()) {
4806 if (vmx
->soft_vnmi_blocked
!= masked
) {
4807 vmx
->soft_vnmi_blocked
= masked
;
4808 vmx
->vnmi_blocked_time
= 0;
4811 vmx
->nmi_known_unmasked
= !masked
;
4813 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4814 GUEST_INTR_STATE_NMI
);
4816 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4817 GUEST_INTR_STATE_NMI
);
4821 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4823 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4826 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4829 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4830 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4831 | GUEST_INTR_STATE_NMI
));
4834 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4836 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
4837 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4838 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4839 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4842 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4845 struct kvm_userspace_memory_region tss_mem
= {
4846 .slot
= TSS_PRIVATE_MEMSLOT
,
4847 .guest_phys_addr
= addr
,
4848 .memory_size
= PAGE_SIZE
* 3,
4852 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4855 kvm
->arch
.tss_addr
= addr
;
4856 return init_rmode_tss(kvm
);
4859 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4864 * Update instruction length as we may reinject the exception
4865 * from user space while in guest debugging mode.
4867 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4868 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4869 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4873 if (vcpu
->guest_debug
&
4874 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4891 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4892 int vec
, u32 err_code
)
4895 * Instruction with address size override prefix opcode 0x67
4896 * Cause the #SS fault with 0 error code in VM86 mode.
4898 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4899 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4900 if (vcpu
->arch
.halt_request
) {
4901 vcpu
->arch
.halt_request
= 0;
4902 return kvm_emulate_halt(vcpu
);
4910 * Forward all other exceptions that are valid in real mode.
4911 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4912 * the required debugging infrastructure rework.
4914 kvm_queue_exception(vcpu
, vec
);
4919 * Trigger machine check on the host. We assume all the MSRs are already set up
4920 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4921 * We pass a fake environment to the machine check handler because we want
4922 * the guest to be always treated like user space, no matter what context
4923 * it used internally.
4925 static void kvm_machine_check(void)
4927 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4928 struct pt_regs regs
= {
4929 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4930 .flags
= X86_EFLAGS_IF
,
4933 do_machine_check(®s
, 0);
4937 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4939 /* already handled by vcpu_run */
4943 static int handle_exception(struct kvm_vcpu
*vcpu
)
4945 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4946 struct kvm_run
*kvm_run
= vcpu
->run
;
4947 u32 intr_info
, ex_no
, error_code
;
4948 unsigned long cr2
, rip
, dr6
;
4950 enum emulation_result er
;
4952 vect_info
= vmx
->idt_vectoring_info
;
4953 intr_info
= vmx
->exit_intr_info
;
4955 if (is_machine_check(intr_info
))
4956 return handle_machine_check(vcpu
);
4958 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4959 return 1; /* already handled by vmx_vcpu_run() */
4961 if (is_no_device(intr_info
)) {
4962 vmx_fpu_activate(vcpu
);
4966 if (is_invalid_opcode(intr_info
)) {
4967 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4968 if (er
!= EMULATE_DONE
)
4969 kvm_queue_exception(vcpu
, UD_VECTOR
);
4974 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4975 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4978 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4979 * MMIO, it is better to report an internal error.
4980 * See the comments in vmx_handle_exit.
4982 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4983 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4984 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4985 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4986 vcpu
->run
->internal
.ndata
= 2;
4987 vcpu
->run
->internal
.data
[0] = vect_info
;
4988 vcpu
->run
->internal
.data
[1] = intr_info
;
4992 if (is_page_fault(intr_info
)) {
4993 /* EPT won't cause page fault directly */
4995 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4996 trace_kvm_page_fault(cr2
, error_code
);
4998 if (kvm_event_needs_reinjection(vcpu
))
4999 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5000 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5003 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5005 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5006 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5010 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5011 if (!(vcpu
->guest_debug
&
5012 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5013 vcpu
->arch
.dr6
&= ~15;
5014 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5015 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5016 skip_emulated_instruction(vcpu
);
5018 kvm_queue_exception(vcpu
, DB_VECTOR
);
5021 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5022 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5026 * Update instruction length as we may reinject #BP from
5027 * user space while in guest debugging mode. Reading it for
5028 * #DB as well causes no harm, it is not used in that case.
5030 vmx
->vcpu
.arch
.event_exit_inst_len
=
5031 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5032 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5033 rip
= kvm_rip_read(vcpu
);
5034 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5035 kvm_run
->debug
.arch
.exception
= ex_no
;
5038 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5039 kvm_run
->ex
.exception
= ex_no
;
5040 kvm_run
->ex
.error_code
= error_code
;
5046 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5048 ++vcpu
->stat
.irq_exits
;
5052 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5054 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5058 static int handle_io(struct kvm_vcpu
*vcpu
)
5060 unsigned long exit_qualification
;
5061 int size
, in
, string
;
5064 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5065 string
= (exit_qualification
& 16) != 0;
5066 in
= (exit_qualification
& 8) != 0;
5068 ++vcpu
->stat
.io_exits
;
5071 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5073 port
= exit_qualification
>> 16;
5074 size
= (exit_qualification
& 7) + 1;
5075 skip_emulated_instruction(vcpu
);
5077 return kvm_fast_pio_out(vcpu
, size
, port
);
5081 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5084 * Patch in the VMCALL instruction:
5086 hypercall
[0] = 0x0f;
5087 hypercall
[1] = 0x01;
5088 hypercall
[2] = 0xc1;
5091 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5093 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5094 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5096 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5097 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5098 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5099 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5100 return (val
& always_on
) == always_on
;
5103 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5104 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5106 if (is_guest_mode(vcpu
)) {
5107 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5108 unsigned long orig_val
= val
;
5111 * We get here when L2 changed cr0 in a way that did not change
5112 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5113 * but did change L0 shadowed bits. So we first calculate the
5114 * effective cr0 value that L1 would like to write into the
5115 * hardware. It consists of the L2-owned bits from the new
5116 * value combined with the L1-owned bits from L1's guest_cr0.
5118 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5119 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5121 if (!nested_cr0_valid(vcpu
, val
))
5124 if (kvm_set_cr0(vcpu
, val
))
5126 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5129 if (to_vmx(vcpu
)->nested
.vmxon
&&
5130 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5132 return kvm_set_cr0(vcpu
, val
);
5136 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5138 if (is_guest_mode(vcpu
)) {
5139 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5140 unsigned long orig_val
= val
;
5142 /* analogously to handle_set_cr0 */
5143 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5144 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5145 if (kvm_set_cr4(vcpu
, val
))
5147 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5150 return kvm_set_cr4(vcpu
, val
);
5153 /* called to set cr0 as approriate for clts instruction exit. */
5154 static void handle_clts(struct kvm_vcpu
*vcpu
)
5156 if (is_guest_mode(vcpu
)) {
5158 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5159 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5160 * just pretend it's off (also in arch.cr0 for fpu_activate).
5162 vmcs_writel(CR0_READ_SHADOW
,
5163 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5164 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5166 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5169 static int handle_cr(struct kvm_vcpu
*vcpu
)
5171 unsigned long exit_qualification
, val
;
5176 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5177 cr
= exit_qualification
& 15;
5178 reg
= (exit_qualification
>> 8) & 15;
5179 switch ((exit_qualification
>> 4) & 3) {
5180 case 0: /* mov to cr */
5181 val
= kvm_register_readl(vcpu
, reg
);
5182 trace_kvm_cr_write(cr
, val
);
5185 err
= handle_set_cr0(vcpu
, val
);
5186 kvm_complete_insn_gp(vcpu
, err
);
5189 err
= kvm_set_cr3(vcpu
, val
);
5190 kvm_complete_insn_gp(vcpu
, err
);
5193 err
= handle_set_cr4(vcpu
, val
);
5194 kvm_complete_insn_gp(vcpu
, err
);
5197 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5199 err
= kvm_set_cr8(vcpu
, cr8
);
5200 kvm_complete_insn_gp(vcpu
, err
);
5201 if (irqchip_in_kernel(vcpu
->kvm
))
5203 if (cr8_prev
<= cr8
)
5205 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5212 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5213 skip_emulated_instruction(vcpu
);
5214 vmx_fpu_activate(vcpu
);
5216 case 1: /*mov from cr*/
5219 val
= kvm_read_cr3(vcpu
);
5220 kvm_register_write(vcpu
, reg
, val
);
5221 trace_kvm_cr_read(cr
, val
);
5222 skip_emulated_instruction(vcpu
);
5225 val
= kvm_get_cr8(vcpu
);
5226 kvm_register_write(vcpu
, reg
, val
);
5227 trace_kvm_cr_read(cr
, val
);
5228 skip_emulated_instruction(vcpu
);
5233 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5234 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5235 kvm_lmsw(vcpu
, val
);
5237 skip_emulated_instruction(vcpu
);
5242 vcpu
->run
->exit_reason
= 0;
5243 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5244 (int)(exit_qualification
>> 4) & 3, cr
);
5248 static int handle_dr(struct kvm_vcpu
*vcpu
)
5250 unsigned long exit_qualification
;
5253 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5254 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5256 /* First, if DR does not exist, trigger UD */
5257 if (!kvm_require_dr(vcpu
, dr
))
5260 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5261 if (!kvm_require_cpl(vcpu
, 0))
5263 dr7
= vmcs_readl(GUEST_DR7
);
5266 * As the vm-exit takes precedence over the debug trap, we
5267 * need to emulate the latter, either for the host or the
5268 * guest debugging itself.
5270 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5271 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5272 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5273 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5274 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5275 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5278 vcpu
->arch
.dr6
&= ~15;
5279 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5280 kvm_queue_exception(vcpu
, DB_VECTOR
);
5285 if (vcpu
->guest_debug
== 0) {
5286 u32 cpu_based_vm_exec_control
;
5288 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5289 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5290 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5293 * No more DR vmexits; force a reload of the debug registers
5294 * and reenter on this instruction. The next vmexit will
5295 * retrieve the full state of the debug registers.
5297 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5301 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5302 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5305 if (kvm_get_dr(vcpu
, dr
, &val
))
5307 kvm_register_write(vcpu
, reg
, val
);
5309 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5312 skip_emulated_instruction(vcpu
);
5316 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5318 return vcpu
->arch
.dr6
;
5321 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5325 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5327 u32 cpu_based_vm_exec_control
;
5329 get_debugreg(vcpu
->arch
.db
[0], 0);
5330 get_debugreg(vcpu
->arch
.db
[1], 1);
5331 get_debugreg(vcpu
->arch
.db
[2], 2);
5332 get_debugreg(vcpu
->arch
.db
[3], 3);
5333 get_debugreg(vcpu
->arch
.dr6
, 6);
5334 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5336 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5338 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5339 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5340 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5343 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5345 vmcs_writel(GUEST_DR7
, val
);
5348 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5350 kvm_emulate_cpuid(vcpu
);
5354 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5356 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5359 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5360 trace_kvm_msr_read_ex(ecx
);
5361 kvm_inject_gp(vcpu
, 0);
5365 trace_kvm_msr_read(ecx
, data
);
5367 /* FIXME: handling of bits 32:63 of rax, rdx */
5368 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5369 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5370 skip_emulated_instruction(vcpu
);
5374 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5376 struct msr_data msr
;
5377 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5378 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5379 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5383 msr
.host_initiated
= false;
5384 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5385 trace_kvm_msr_write_ex(ecx
, data
);
5386 kvm_inject_gp(vcpu
, 0);
5390 trace_kvm_msr_write(ecx
, data
);
5391 skip_emulated_instruction(vcpu
);
5395 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5397 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5401 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5403 u32 cpu_based_vm_exec_control
;
5405 /* clear pending irq */
5406 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5407 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5408 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5410 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5412 ++vcpu
->stat
.irq_window_exits
;
5415 * If the user space waits to inject interrupts, exit as soon as
5418 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5419 vcpu
->run
->request_interrupt_window
&&
5420 !kvm_cpu_has_interrupt(vcpu
)) {
5421 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5427 static int handle_halt(struct kvm_vcpu
*vcpu
)
5429 skip_emulated_instruction(vcpu
);
5430 return kvm_emulate_halt(vcpu
);
5433 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5435 skip_emulated_instruction(vcpu
);
5436 kvm_emulate_hypercall(vcpu
);
5440 static int handle_invd(struct kvm_vcpu
*vcpu
)
5442 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5445 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5447 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5449 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5450 skip_emulated_instruction(vcpu
);
5454 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5458 err
= kvm_rdpmc(vcpu
);
5459 kvm_complete_insn_gp(vcpu
, err
);
5464 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5466 skip_emulated_instruction(vcpu
);
5467 kvm_emulate_wbinvd(vcpu
);
5471 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5473 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5474 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5476 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5477 skip_emulated_instruction(vcpu
);
5481 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5483 skip_emulated_instruction(vcpu
);
5484 WARN(1, "this should never happen\n");
5488 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5490 skip_emulated_instruction(vcpu
);
5491 WARN(1, "this should never happen\n");
5495 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5497 if (likely(fasteoi
)) {
5498 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5499 int access_type
, offset
;
5501 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5502 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5504 * Sane guest uses MOV to write EOI, with written value
5505 * not cared. So make a short-circuit here by avoiding
5506 * heavy instruction emulation.
5508 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5509 (offset
== APIC_EOI
)) {
5510 kvm_lapic_set_eoi(vcpu
);
5511 skip_emulated_instruction(vcpu
);
5515 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5518 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5520 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5521 int vector
= exit_qualification
& 0xff;
5523 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5524 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5528 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5530 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5531 u32 offset
= exit_qualification
& 0xfff;
5533 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5534 kvm_apic_write_nodecode(vcpu
, offset
);
5538 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5540 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5541 unsigned long exit_qualification
;
5542 bool has_error_code
= false;
5545 int reason
, type
, idt_v
, idt_index
;
5547 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5548 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5549 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5551 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5553 reason
= (u32
)exit_qualification
>> 30;
5554 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5556 case INTR_TYPE_NMI_INTR
:
5557 vcpu
->arch
.nmi_injected
= false;
5558 vmx_set_nmi_mask(vcpu
, true);
5560 case INTR_TYPE_EXT_INTR
:
5561 case INTR_TYPE_SOFT_INTR
:
5562 kvm_clear_interrupt_queue(vcpu
);
5564 case INTR_TYPE_HARD_EXCEPTION
:
5565 if (vmx
->idt_vectoring_info
&
5566 VECTORING_INFO_DELIVER_CODE_MASK
) {
5567 has_error_code
= true;
5569 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5572 case INTR_TYPE_SOFT_EXCEPTION
:
5573 kvm_clear_exception_queue(vcpu
);
5579 tss_selector
= exit_qualification
;
5581 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5582 type
!= INTR_TYPE_EXT_INTR
&&
5583 type
!= INTR_TYPE_NMI_INTR
))
5584 skip_emulated_instruction(vcpu
);
5586 if (kvm_task_switch(vcpu
, tss_selector
,
5587 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5588 has_error_code
, error_code
) == EMULATE_FAIL
) {
5589 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5590 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5591 vcpu
->run
->internal
.ndata
= 0;
5595 /* clear all local breakpoint enable flags */
5596 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~0x155);
5599 * TODO: What about debug traps on tss switch?
5600 * Are we supposed to inject them and update dr6?
5606 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5608 unsigned long exit_qualification
;
5613 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5615 gla_validity
= (exit_qualification
>> 7) & 0x3;
5616 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5617 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5618 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5619 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5620 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5621 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5622 (long unsigned int)exit_qualification
);
5623 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5624 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5629 * EPT violation happened while executing iret from NMI,
5630 * "blocked by NMI" bit has to be set before next VM entry.
5631 * There are errata that may cause this bit to not be set:
5634 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5635 cpu_has_virtual_nmis() &&
5636 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5637 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5639 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5640 trace_kvm_page_fault(gpa
, exit_qualification
);
5642 /* It is a write fault? */
5643 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
5644 /* It is a fetch fault? */
5645 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
5646 /* ept page table is present? */
5647 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
5649 vcpu
->arch
.exit_qualification
= exit_qualification
;
5651 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5654 static u64
ept_rsvd_mask(u64 spte
, int level
)
5659 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5660 mask
|= (1ULL << i
);
5663 /* bits 7:3 reserved */
5665 else if (spte
& (1ULL << 7))
5667 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5668 * level == 1 if the hypervisor is using the ignored bit 7.
5670 mask
|= (PAGE_SIZE
<< ((level
- 1) * 9)) - PAGE_SIZE
;
5672 /* bits 6:3 reserved */
5678 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5681 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5683 /* 010b (write-only) */
5684 WARN_ON((spte
& 0x7) == 0x2);
5686 /* 110b (write/execute) */
5687 WARN_ON((spte
& 0x7) == 0x6);
5689 /* 100b (execute-only) and value not supported by logical processor */
5690 if (!cpu_has_vmx_ept_execute_only())
5691 WARN_ON((spte
& 0x7) == 0x4);
5695 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5697 if (rsvd_bits
!= 0) {
5698 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5699 __func__
, rsvd_bits
);
5703 /* bits 5:3 are _not_ reserved for large page or leaf page */
5704 if ((rsvd_bits
& 0x38) == 0) {
5705 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5707 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5708 ept_mem_type
== 7) {
5709 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5710 __func__
, ept_mem_type
);
5717 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5720 int nr_sptes
, i
, ret
;
5723 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5724 if (!kvm_io_bus_write(vcpu
->kvm
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5725 skip_emulated_instruction(vcpu
);
5729 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5730 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5731 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5734 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5735 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5737 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5740 /* It is the real ept misconfig */
5741 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5742 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5744 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5746 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5747 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5749 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5750 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5755 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5757 u32 cpu_based_vm_exec_control
;
5759 /* clear pending NMI */
5760 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5761 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5762 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5763 ++vcpu
->stat
.nmi_window_exits
;
5764 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5769 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5771 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5772 enum emulation_result err
= EMULATE_DONE
;
5775 bool intr_window_requested
;
5776 unsigned count
= 130;
5778 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5779 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5781 while (vmx
->emulation_required
&& count
-- != 0) {
5782 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5783 return handle_interrupt_window(&vmx
->vcpu
);
5785 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5788 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5790 if (err
== EMULATE_USER_EXIT
) {
5791 ++vcpu
->stat
.mmio_exits
;
5796 if (err
!= EMULATE_DONE
) {
5797 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5798 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5799 vcpu
->run
->internal
.ndata
= 0;
5803 if (vcpu
->arch
.halt_request
) {
5804 vcpu
->arch
.halt_request
= 0;
5805 ret
= kvm_emulate_halt(vcpu
);
5809 if (signal_pending(current
))
5819 static int __grow_ple_window(int val
)
5821 if (ple_window_grow
< 1)
5824 val
= min(val
, ple_window_actual_max
);
5826 if (ple_window_grow
< ple_window
)
5827 val
*= ple_window_grow
;
5829 val
+= ple_window_grow
;
5834 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
5839 if (modifier
< ple_window
)
5844 return max(val
, minimum
);
5847 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
5849 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5850 int old
= vmx
->ple_window
;
5852 vmx
->ple_window
= __grow_ple_window(old
);
5854 if (vmx
->ple_window
!= old
)
5855 vmx
->ple_window_dirty
= true;
5857 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5860 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
5862 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5863 int old
= vmx
->ple_window
;
5865 vmx
->ple_window
= __shrink_ple_window(old
,
5866 ple_window_shrink
, ple_window
);
5868 if (vmx
->ple_window
!= old
)
5869 vmx
->ple_window_dirty
= true;
5871 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5875 * ple_window_actual_max is computed to be one grow_ple_window() below
5876 * ple_window_max. (See __grow_ple_window for the reason.)
5877 * This prevents overflows, because ple_window_max is int.
5878 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5880 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5882 static void update_ple_window_actual_max(void)
5884 ple_window_actual_max
=
5885 __shrink_ple_window(max(ple_window_max
, ple_window
),
5886 ple_window_grow
, INT_MIN
);
5889 static __init
int hardware_setup(void)
5891 int r
= -ENOMEM
, i
, msr
;
5893 rdmsrl_safe(MSR_EFER
, &host_efer
);
5895 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
5896 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
5898 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5899 if (!vmx_io_bitmap_a
)
5902 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5903 if (!vmx_io_bitmap_b
)
5906 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5907 if (!vmx_msr_bitmap_legacy
)
5910 vmx_msr_bitmap_legacy_x2apic
=
5911 (unsigned long *)__get_free_page(GFP_KERNEL
);
5912 if (!vmx_msr_bitmap_legacy_x2apic
)
5915 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5916 if (!vmx_msr_bitmap_longmode
)
5919 vmx_msr_bitmap_longmode_x2apic
=
5920 (unsigned long *)__get_free_page(GFP_KERNEL
);
5921 if (!vmx_msr_bitmap_longmode_x2apic
)
5925 vmx_msr_bitmap_nested
=
5926 (unsigned long *)__get_free_page(GFP_KERNEL
);
5927 if (!vmx_msr_bitmap_nested
)
5931 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5932 if (!vmx_vmread_bitmap
)
5935 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5936 if (!vmx_vmwrite_bitmap
)
5939 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
5940 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
5943 * Allow direct access to the PC debug port (it is often used for I/O
5944 * delays, but the vmexits simply slow things down).
5946 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
5947 clear_bit(0x80, vmx_io_bitmap_a
);
5949 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
5951 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
5952 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
5954 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
5956 if (setup_vmcs_config(&vmcs_config
) < 0) {
5961 if (boot_cpu_has(X86_FEATURE_NX
))
5962 kvm_enable_efer_bits(EFER_NX
);
5964 if (!cpu_has_vmx_vpid())
5966 if (!cpu_has_vmx_shadow_vmcs())
5967 enable_shadow_vmcs
= 0;
5968 if (enable_shadow_vmcs
)
5969 init_vmcs_shadow_fields();
5971 if (!cpu_has_vmx_ept() ||
5972 !cpu_has_vmx_ept_4levels()) {
5974 enable_unrestricted_guest
= 0;
5975 enable_ept_ad_bits
= 0;
5978 if (!cpu_has_vmx_ept_ad_bits())
5979 enable_ept_ad_bits
= 0;
5981 if (!cpu_has_vmx_unrestricted_guest())
5982 enable_unrestricted_guest
= 0;
5984 if (!cpu_has_vmx_flexpriority())
5985 flexpriority_enabled
= 0;
5988 * set_apic_access_page_addr() is used to reload apic access
5989 * page upon invalidation. No need to do anything if not
5990 * using the APIC_ACCESS_ADDR VMCS field.
5992 if (!flexpriority_enabled
)
5993 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
5995 if (!cpu_has_vmx_tpr_shadow())
5996 kvm_x86_ops
->update_cr8_intercept
= NULL
;
5998 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
5999 kvm_disable_largepages();
6001 if (!cpu_has_vmx_ple())
6004 if (!cpu_has_vmx_apicv())
6008 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6010 kvm_x86_ops
->hwapic_irr_update
= NULL
;
6011 kvm_x86_ops
->hwapic_isr_update
= NULL
;
6012 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
6013 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
6016 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6017 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6018 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6019 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6020 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6021 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6022 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6024 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6025 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6026 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6027 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6030 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6031 vmx_disable_intercept_msr_read_x2apic(msr
);
6033 /* According SDM, in x2apic mode, the whole id reg is used.
6034 * But in KVM, it only use the highest eight bits. Need to
6036 vmx_enable_intercept_msr_read_x2apic(0x802);
6038 vmx_enable_intercept_msr_read_x2apic(0x839);
6040 vmx_disable_intercept_msr_write_x2apic(0x808);
6042 vmx_disable_intercept_msr_write_x2apic(0x80b);
6044 vmx_disable_intercept_msr_write_x2apic(0x83f);
6048 kvm_mmu_set_mask_ptes(0ull,
6049 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6050 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6051 0ull, VMX_EPT_EXECUTABLE_MASK
);
6052 ept_set_mmio_spte_mask();
6057 update_ple_window_actual_max();
6060 * Only enable PML when hardware supports PML feature, and both EPT
6061 * and EPT A/D bit features are enabled -- PML depends on them to work.
6063 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6067 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6068 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6069 kvm_x86_ops
->flush_log_dirty
= NULL
;
6070 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6073 return alloc_kvm_area();
6076 free_page((unsigned long)vmx_vmwrite_bitmap
);
6078 free_page((unsigned long)vmx_vmread_bitmap
);
6081 free_page((unsigned long)vmx_msr_bitmap_nested
);
6083 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6085 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6087 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6089 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6091 free_page((unsigned long)vmx_io_bitmap_b
);
6093 free_page((unsigned long)vmx_io_bitmap_a
);
6098 static __exit
void hardware_unsetup(void)
6100 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6101 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6102 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6103 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6104 free_page((unsigned long)vmx_io_bitmap_b
);
6105 free_page((unsigned long)vmx_io_bitmap_a
);
6106 free_page((unsigned long)vmx_vmwrite_bitmap
);
6107 free_page((unsigned long)vmx_vmread_bitmap
);
6109 free_page((unsigned long)vmx_msr_bitmap_nested
);
6115 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6116 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6118 static int handle_pause(struct kvm_vcpu
*vcpu
)
6121 grow_ple_window(vcpu
);
6123 skip_emulated_instruction(vcpu
);
6124 kvm_vcpu_on_spin(vcpu
);
6129 static int handle_nop(struct kvm_vcpu
*vcpu
)
6131 skip_emulated_instruction(vcpu
);
6135 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6137 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6138 return handle_nop(vcpu
);
6141 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6143 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6144 return handle_nop(vcpu
);
6148 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6149 * We could reuse a single VMCS for all the L2 guests, but we also want the
6150 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6151 * allows keeping them loaded on the processor, and in the future will allow
6152 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6153 * every entry if they never change.
6154 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6155 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6157 * The following functions allocate and free a vmcs02 in this pool.
6160 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6161 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6163 struct vmcs02_list
*item
;
6164 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6165 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6166 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6167 return &item
->vmcs02
;
6170 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6171 /* Recycle the least recently used VMCS. */
6172 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
6173 struct vmcs02_list
, list
);
6174 item
->vmptr
= vmx
->nested
.current_vmptr
;
6175 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6176 return &item
->vmcs02
;
6179 /* Create a new VMCS */
6180 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6183 item
->vmcs02
.vmcs
= alloc_vmcs();
6184 if (!item
->vmcs02
.vmcs
) {
6188 loaded_vmcs_init(&item
->vmcs02
);
6189 item
->vmptr
= vmx
->nested
.current_vmptr
;
6190 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6191 vmx
->nested
.vmcs02_num
++;
6192 return &item
->vmcs02
;
6195 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6196 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6198 struct vmcs02_list
*item
;
6199 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6200 if (item
->vmptr
== vmptr
) {
6201 free_loaded_vmcs(&item
->vmcs02
);
6202 list_del(&item
->list
);
6204 vmx
->nested
.vmcs02_num
--;
6210 * Free all VMCSs saved for this vcpu, except the one pointed by
6211 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6212 * must be &vmx->vmcs01.
6214 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6216 struct vmcs02_list
*item
, *n
;
6218 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6219 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6221 * Something will leak if the above WARN triggers. Better than
6224 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6227 free_loaded_vmcs(&item
->vmcs02
);
6228 list_del(&item
->list
);
6230 vmx
->nested
.vmcs02_num
--;
6235 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6236 * set the success or error code of an emulated VMX instruction, as specified
6237 * by Vol 2B, VMX Instruction Reference, "Conventions".
6239 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6241 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6242 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6243 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6246 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6248 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6249 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6250 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6254 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6255 u32 vm_instruction_error
)
6257 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6259 * failValid writes the error number to the current VMCS, which
6260 * can't be done there isn't a current VMCS.
6262 nested_vmx_failInvalid(vcpu
);
6265 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6266 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6267 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6269 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6271 * We don't need to force a shadow sync because
6272 * VM_INSTRUCTION_ERROR is not shadowed
6276 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6278 /* TODO: not to reset guest simply here. */
6279 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6280 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6283 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6285 struct vcpu_vmx
*vmx
=
6286 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6288 vmx
->nested
.preemption_timer_expired
= true;
6289 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6290 kvm_vcpu_kick(&vmx
->vcpu
);
6292 return HRTIMER_NORESTART
;
6296 * Decode the memory-address operand of a vmx instruction, as recorded on an
6297 * exit caused by such an instruction (run by a guest hypervisor).
6298 * On success, returns 0. When the operand is invalid, returns 1 and throws
6301 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6302 unsigned long exit_qualification
,
6303 u32 vmx_instruction_info
, gva_t
*ret
)
6306 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6307 * Execution", on an exit, vmx_instruction_info holds most of the
6308 * addressing components of the operand. Only the displacement part
6309 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6310 * For how an actual address is calculated from all these components,
6311 * refer to Vol. 1, "Operand Addressing".
6313 int scaling
= vmx_instruction_info
& 3;
6314 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6315 bool is_reg
= vmx_instruction_info
& (1u << 10);
6316 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6317 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6318 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6319 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6320 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6323 kvm_queue_exception(vcpu
, UD_VECTOR
);
6327 /* Addr = segment_base + offset */
6328 /* offset = base + [index * scale] + displacement */
6329 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
6331 *ret
+= kvm_register_read(vcpu
, base_reg
);
6333 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6334 *ret
+= exit_qualification
; /* holds the displacement */
6336 if (addr_size
== 1) /* 32 bit */
6340 * TODO: throw #GP (and return 1) in various cases that the VM*
6341 * instructions require it - e.g., offset beyond segment limit,
6342 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6343 * address, and so on. Currently these are not checked.
6349 * This function performs the various checks including
6350 * - if it's 4KB aligned
6351 * - No bits beyond the physical address width are set
6352 * - Returns 0 on success or else 1
6353 * (Intel SDM Section 30.3)
6355 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6360 struct x86_exception e
;
6362 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6363 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6365 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6366 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6369 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6370 sizeof(vmptr
), &e
)) {
6371 kvm_inject_page_fault(vcpu
, &e
);
6375 switch (exit_reason
) {
6376 case EXIT_REASON_VMON
:
6379 * The first 4 bytes of VMXON region contain the supported
6380 * VMCS revision identifier
6382 * Note - IA32_VMX_BASIC[48] will never be 1
6383 * for the nested case;
6384 * which replaces physical address width with 32
6387 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6388 nested_vmx_failInvalid(vcpu
);
6389 skip_emulated_instruction(vcpu
);
6393 page
= nested_get_page(vcpu
, vmptr
);
6395 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6396 nested_vmx_failInvalid(vcpu
);
6398 skip_emulated_instruction(vcpu
);
6402 vmx
->nested
.vmxon_ptr
= vmptr
;
6404 case EXIT_REASON_VMCLEAR
:
6405 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6406 nested_vmx_failValid(vcpu
,
6407 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6408 skip_emulated_instruction(vcpu
);
6412 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6413 nested_vmx_failValid(vcpu
,
6414 VMXERR_VMCLEAR_VMXON_POINTER
);
6415 skip_emulated_instruction(vcpu
);
6419 case EXIT_REASON_VMPTRLD
:
6420 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6421 nested_vmx_failValid(vcpu
,
6422 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6423 skip_emulated_instruction(vcpu
);
6427 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6428 nested_vmx_failValid(vcpu
,
6429 VMXERR_VMCLEAR_VMXON_POINTER
);
6430 skip_emulated_instruction(vcpu
);
6435 return 1; /* shouldn't happen */
6444 * Emulate the VMXON instruction.
6445 * Currently, we just remember that VMX is active, and do not save or even
6446 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6447 * do not currently need to store anything in that guest-allocated memory
6448 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6449 * argument is different from the VMXON pointer (which the spec says they do).
6451 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6453 struct kvm_segment cs
;
6454 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6455 struct vmcs
*shadow_vmcs
;
6456 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6457 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6459 /* The Intel VMX Instruction Reference lists a bunch of bits that
6460 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6461 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6462 * Otherwise, we should fail with #UD. We test these now:
6464 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6465 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6466 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6467 kvm_queue_exception(vcpu
, UD_VECTOR
);
6471 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6472 if (is_long_mode(vcpu
) && !cs
.l
) {
6473 kvm_queue_exception(vcpu
, UD_VECTOR
);
6477 if (vmx_get_cpl(vcpu
)) {
6478 kvm_inject_gp(vcpu
, 0);
6482 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6485 if (vmx
->nested
.vmxon
) {
6486 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6487 skip_emulated_instruction(vcpu
);
6491 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6492 != VMXON_NEEDED_FEATURES
) {
6493 kvm_inject_gp(vcpu
, 0);
6497 if (enable_shadow_vmcs
) {
6498 shadow_vmcs
= alloc_vmcs();
6501 /* mark vmcs as shadow */
6502 shadow_vmcs
->revision_id
|= (1u << 31);
6503 /* init shadow vmcs */
6504 vmcs_clear(shadow_vmcs
);
6505 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6508 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6509 vmx
->nested
.vmcs02_num
= 0;
6511 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6513 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6515 vmx
->nested
.vmxon
= true;
6517 skip_emulated_instruction(vcpu
);
6518 nested_vmx_succeed(vcpu
);
6523 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6524 * for running VMX instructions (except VMXON, whose prerequisites are
6525 * slightly different). It also specifies what exception to inject otherwise.
6527 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6529 struct kvm_segment cs
;
6530 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6532 if (!vmx
->nested
.vmxon
) {
6533 kvm_queue_exception(vcpu
, UD_VECTOR
);
6537 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6538 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6539 (is_long_mode(vcpu
) && !cs
.l
)) {
6540 kvm_queue_exception(vcpu
, UD_VECTOR
);
6544 if (vmx_get_cpl(vcpu
)) {
6545 kvm_inject_gp(vcpu
, 0);
6552 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6555 if (vmx
->nested
.current_vmptr
== -1ull)
6558 /* current_vmptr and current_vmcs12 are always set/reset together */
6559 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6562 if (enable_shadow_vmcs
) {
6563 /* copy to memory all shadowed fields in case
6564 they were modified */
6565 copy_shadow_to_vmcs12(vmx
);
6566 vmx
->nested
.sync_shadow_vmcs
= false;
6567 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6568 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
6569 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6570 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6572 kunmap(vmx
->nested
.current_vmcs12_page
);
6573 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6574 vmx
->nested
.current_vmptr
= -1ull;
6575 vmx
->nested
.current_vmcs12
= NULL
;
6579 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6580 * just stops using VMX.
6582 static void free_nested(struct vcpu_vmx
*vmx
)
6584 if (!vmx
->nested
.vmxon
)
6587 vmx
->nested
.vmxon
= false;
6588 nested_release_vmcs12(vmx
);
6589 if (enable_shadow_vmcs
)
6590 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6591 /* Unpin physical memory we referred to in current vmcs02 */
6592 if (vmx
->nested
.apic_access_page
) {
6593 nested_release_page(vmx
->nested
.apic_access_page
);
6594 vmx
->nested
.apic_access_page
= NULL
;
6596 if (vmx
->nested
.virtual_apic_page
) {
6597 nested_release_page(vmx
->nested
.virtual_apic_page
);
6598 vmx
->nested
.virtual_apic_page
= NULL
;
6601 nested_free_all_saved_vmcss(vmx
);
6604 /* Emulate the VMXOFF instruction */
6605 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6607 if (!nested_vmx_check_permission(vcpu
))
6609 free_nested(to_vmx(vcpu
));
6610 skip_emulated_instruction(vcpu
);
6611 nested_vmx_succeed(vcpu
);
6615 /* Emulate the VMCLEAR instruction */
6616 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6618 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6620 struct vmcs12
*vmcs12
;
6623 if (!nested_vmx_check_permission(vcpu
))
6626 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6629 if (vmptr
== vmx
->nested
.current_vmptr
)
6630 nested_release_vmcs12(vmx
);
6632 page
= nested_get_page(vcpu
, vmptr
);
6635 * For accurate processor emulation, VMCLEAR beyond available
6636 * physical memory should do nothing at all. However, it is
6637 * possible that a nested vmx bug, not a guest hypervisor bug,
6638 * resulted in this case, so let's shut down before doing any
6641 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6644 vmcs12
= kmap(page
);
6645 vmcs12
->launch_state
= 0;
6647 nested_release_page(page
);
6649 nested_free_vmcs02(vmx
, vmptr
);
6651 skip_emulated_instruction(vcpu
);
6652 nested_vmx_succeed(vcpu
);
6656 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6658 /* Emulate the VMLAUNCH instruction */
6659 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6661 return nested_vmx_run(vcpu
, true);
6664 /* Emulate the VMRESUME instruction */
6665 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6668 return nested_vmx_run(vcpu
, false);
6671 enum vmcs_field_type
{
6672 VMCS_FIELD_TYPE_U16
= 0,
6673 VMCS_FIELD_TYPE_U64
= 1,
6674 VMCS_FIELD_TYPE_U32
= 2,
6675 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6678 static inline int vmcs_field_type(unsigned long field
)
6680 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6681 return VMCS_FIELD_TYPE_U32
;
6682 return (field
>> 13) & 0x3 ;
6685 static inline int vmcs_field_readonly(unsigned long field
)
6687 return (((field
>> 10) & 0x3) == 1);
6691 * Read a vmcs12 field. Since these can have varying lengths and we return
6692 * one type, we chose the biggest type (u64) and zero-extend the return value
6693 * to that size. Note that the caller, handle_vmread, might need to use only
6694 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6695 * 64-bit fields are to be returned).
6697 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6698 unsigned long field
, u64
*ret
)
6700 short offset
= vmcs_field_to_offset(field
);
6706 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6708 switch (vmcs_field_type(field
)) {
6709 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6710 *ret
= *((natural_width
*)p
);
6712 case VMCS_FIELD_TYPE_U16
:
6715 case VMCS_FIELD_TYPE_U32
:
6718 case VMCS_FIELD_TYPE_U64
:
6728 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6729 unsigned long field
, u64 field_value
){
6730 short offset
= vmcs_field_to_offset(field
);
6731 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6735 switch (vmcs_field_type(field
)) {
6736 case VMCS_FIELD_TYPE_U16
:
6737 *(u16
*)p
= field_value
;
6739 case VMCS_FIELD_TYPE_U32
:
6740 *(u32
*)p
= field_value
;
6742 case VMCS_FIELD_TYPE_U64
:
6743 *(u64
*)p
= field_value
;
6745 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6746 *(natural_width
*)p
= field_value
;
6755 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6758 unsigned long field
;
6760 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6761 const unsigned long *fields
= shadow_read_write_fields
;
6762 const int num_fields
= max_shadow_read_write_fields
;
6766 vmcs_load(shadow_vmcs
);
6768 for (i
= 0; i
< num_fields
; i
++) {
6770 switch (vmcs_field_type(field
)) {
6771 case VMCS_FIELD_TYPE_U16
:
6772 field_value
= vmcs_read16(field
);
6774 case VMCS_FIELD_TYPE_U32
:
6775 field_value
= vmcs_read32(field
);
6777 case VMCS_FIELD_TYPE_U64
:
6778 field_value
= vmcs_read64(field
);
6780 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6781 field_value
= vmcs_readl(field
);
6787 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6790 vmcs_clear(shadow_vmcs
);
6791 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6796 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6798 const unsigned long *fields
[] = {
6799 shadow_read_write_fields
,
6800 shadow_read_only_fields
6802 const int max_fields
[] = {
6803 max_shadow_read_write_fields
,
6804 max_shadow_read_only_fields
6807 unsigned long field
;
6808 u64 field_value
= 0;
6809 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6811 vmcs_load(shadow_vmcs
);
6813 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6814 for (i
= 0; i
< max_fields
[q
]; i
++) {
6815 field
= fields
[q
][i
];
6816 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6818 switch (vmcs_field_type(field
)) {
6819 case VMCS_FIELD_TYPE_U16
:
6820 vmcs_write16(field
, (u16
)field_value
);
6822 case VMCS_FIELD_TYPE_U32
:
6823 vmcs_write32(field
, (u32
)field_value
);
6825 case VMCS_FIELD_TYPE_U64
:
6826 vmcs_write64(field
, (u64
)field_value
);
6828 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6829 vmcs_writel(field
, (long)field_value
);
6838 vmcs_clear(shadow_vmcs
);
6839 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6843 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6844 * used before) all generate the same failure when it is missing.
6846 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6848 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6849 if (vmx
->nested
.current_vmptr
== -1ull) {
6850 nested_vmx_failInvalid(vcpu
);
6851 skip_emulated_instruction(vcpu
);
6857 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6859 unsigned long field
;
6861 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6862 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6865 if (!nested_vmx_check_permission(vcpu
) ||
6866 !nested_vmx_check_vmcs12(vcpu
))
6869 /* Decode instruction info and find the field to read */
6870 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6871 /* Read the field, zero-extended to a u64 field_value */
6872 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
6873 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6874 skip_emulated_instruction(vcpu
);
6878 * Now copy part of this value to register or memory, as requested.
6879 * Note that the number of bits actually copied is 32 or 64 depending
6880 * on the guest's mode (32 or 64 bit), not on the given field's length.
6882 if (vmx_instruction_info
& (1u << 10)) {
6883 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6886 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6887 vmx_instruction_info
, &gva
))
6889 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6890 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6891 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6894 nested_vmx_succeed(vcpu
);
6895 skip_emulated_instruction(vcpu
);
6900 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6902 unsigned long field
;
6904 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6905 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6906 /* The value to write might be 32 or 64 bits, depending on L1's long
6907 * mode, and eventually we need to write that into a field of several
6908 * possible lengths. The code below first zero-extends the value to 64
6909 * bit (field_value), and then copies only the approriate number of
6910 * bits into the vmcs12 field.
6912 u64 field_value
= 0;
6913 struct x86_exception e
;
6915 if (!nested_vmx_check_permission(vcpu
) ||
6916 !nested_vmx_check_vmcs12(vcpu
))
6919 if (vmx_instruction_info
& (1u << 10))
6920 field_value
= kvm_register_readl(vcpu
,
6921 (((vmx_instruction_info
) >> 3) & 0xf));
6923 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6924 vmx_instruction_info
, &gva
))
6926 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6927 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
6928 kvm_inject_page_fault(vcpu
, &e
);
6934 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6935 if (vmcs_field_readonly(field
)) {
6936 nested_vmx_failValid(vcpu
,
6937 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6938 skip_emulated_instruction(vcpu
);
6942 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
6943 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6944 skip_emulated_instruction(vcpu
);
6948 nested_vmx_succeed(vcpu
);
6949 skip_emulated_instruction(vcpu
);
6953 /* Emulate the VMPTRLD instruction */
6954 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6956 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6960 if (!nested_vmx_check_permission(vcpu
))
6963 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
6966 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6967 struct vmcs12
*new_vmcs12
;
6969 page
= nested_get_page(vcpu
, vmptr
);
6971 nested_vmx_failInvalid(vcpu
);
6972 skip_emulated_instruction(vcpu
);
6975 new_vmcs12
= kmap(page
);
6976 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6978 nested_release_page_clean(page
);
6979 nested_vmx_failValid(vcpu
,
6980 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6981 skip_emulated_instruction(vcpu
);
6985 nested_release_vmcs12(vmx
);
6986 vmx
->nested
.current_vmptr
= vmptr
;
6987 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6988 vmx
->nested
.current_vmcs12_page
= page
;
6989 if (enable_shadow_vmcs
) {
6990 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6991 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6992 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6993 vmcs_write64(VMCS_LINK_POINTER
,
6994 __pa(vmx
->nested
.current_shadow_vmcs
));
6995 vmx
->nested
.sync_shadow_vmcs
= true;
6999 nested_vmx_succeed(vcpu
);
7000 skip_emulated_instruction(vcpu
);
7004 /* Emulate the VMPTRST instruction */
7005 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7007 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7008 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7010 struct x86_exception e
;
7012 if (!nested_vmx_check_permission(vcpu
))
7015 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7016 vmx_instruction_info
, &vmcs_gva
))
7018 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7019 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7020 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7022 kvm_inject_page_fault(vcpu
, &e
);
7025 nested_vmx_succeed(vcpu
);
7026 skip_emulated_instruction(vcpu
);
7030 /* Emulate the INVEPT instruction */
7031 static int handle_invept(struct kvm_vcpu
*vcpu
)
7033 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7034 u32 vmx_instruction_info
, types
;
7037 struct x86_exception e
;
7042 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7043 SECONDARY_EXEC_ENABLE_EPT
) ||
7044 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7045 kvm_queue_exception(vcpu
, UD_VECTOR
);
7049 if (!nested_vmx_check_permission(vcpu
))
7052 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7053 kvm_queue_exception(vcpu
, UD_VECTOR
);
7057 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7058 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7060 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7062 if (!(types
& (1UL << type
))) {
7063 nested_vmx_failValid(vcpu
,
7064 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7068 /* According to the Intel VMX instruction reference, the memory
7069 * operand is read even if it isn't needed (e.g., for type==global)
7071 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7072 vmx_instruction_info
, &gva
))
7074 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7075 sizeof(operand
), &e
)) {
7076 kvm_inject_page_fault(vcpu
, &e
);
7081 case VMX_EPT_EXTENT_GLOBAL
:
7082 kvm_mmu_sync_roots(vcpu
);
7083 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7084 nested_vmx_succeed(vcpu
);
7087 /* Trap single context invalidation invept calls */
7092 skip_emulated_instruction(vcpu
);
7096 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7098 kvm_queue_exception(vcpu
, UD_VECTOR
);
7102 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7104 unsigned long exit_qualification
;
7106 trace_kvm_pml_full(vcpu
->vcpu_id
);
7108 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7111 * PML buffer FULL happened while executing iret from NMI,
7112 * "blocked by NMI" bit has to be set before next VM entry.
7114 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7115 cpu_has_virtual_nmis() &&
7116 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7117 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7118 GUEST_INTR_STATE_NMI
);
7121 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7122 * here.., and there's no userspace involvement needed for PML.
7128 * The exit handlers return 1 if the exit was handled fully and guest execution
7129 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7130 * to be done to userspace and return 0.
7132 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7133 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7134 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7135 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7136 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7137 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7138 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7139 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7140 [EXIT_REASON_CPUID
] = handle_cpuid
,
7141 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7142 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7143 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7144 [EXIT_REASON_HLT
] = handle_halt
,
7145 [EXIT_REASON_INVD
] = handle_invd
,
7146 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7147 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7148 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7149 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7150 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7151 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7152 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7153 [EXIT_REASON_VMREAD
] = handle_vmread
,
7154 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7155 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7156 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7157 [EXIT_REASON_VMON
] = handle_vmon
,
7158 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7159 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7160 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7161 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7162 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7163 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7164 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7165 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7166 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7167 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7168 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7169 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7170 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7171 [EXIT_REASON_INVEPT
] = handle_invept
,
7172 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7173 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7174 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7175 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7178 static const int kvm_vmx_max_exit_handlers
=
7179 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7181 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7182 struct vmcs12
*vmcs12
)
7184 unsigned long exit_qualification
;
7185 gpa_t bitmap
, last_bitmap
;
7190 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7191 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7193 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7195 port
= exit_qualification
>> 16;
7196 size
= (exit_qualification
& 7) + 1;
7198 last_bitmap
= (gpa_t
)-1;
7203 bitmap
= vmcs12
->io_bitmap_a
;
7204 else if (port
< 0x10000)
7205 bitmap
= vmcs12
->io_bitmap_b
;
7208 bitmap
+= (port
& 0x7fff) / 8;
7210 if (last_bitmap
!= bitmap
)
7211 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
7213 if (b
& (1 << (port
& 7)))
7218 last_bitmap
= bitmap
;
7225 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7226 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7227 * disinterest in the current event (read or write a specific MSR) by using an
7228 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7230 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7231 struct vmcs12
*vmcs12
, u32 exit_reason
)
7233 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7236 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7240 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7241 * for the four combinations of read/write and low/high MSR numbers.
7242 * First we need to figure out which of the four to use:
7244 bitmap
= vmcs12
->msr_bitmap
;
7245 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7247 if (msr_index
>= 0xc0000000) {
7248 msr_index
-= 0xc0000000;
7252 /* Then read the msr_index'th bit from this bitmap: */
7253 if (msr_index
< 1024*8) {
7255 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
7257 return 1 & (b
>> (msr_index
& 7));
7259 return 1; /* let L1 handle the wrong parameter */
7263 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7264 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7265 * intercept (via guest_host_mask etc.) the current event.
7267 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7268 struct vmcs12
*vmcs12
)
7270 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7271 int cr
= exit_qualification
& 15;
7272 int reg
= (exit_qualification
>> 8) & 15;
7273 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7275 switch ((exit_qualification
>> 4) & 3) {
7276 case 0: /* mov to cr */
7279 if (vmcs12
->cr0_guest_host_mask
&
7280 (val
^ vmcs12
->cr0_read_shadow
))
7284 if ((vmcs12
->cr3_target_count
>= 1 &&
7285 vmcs12
->cr3_target_value0
== val
) ||
7286 (vmcs12
->cr3_target_count
>= 2 &&
7287 vmcs12
->cr3_target_value1
== val
) ||
7288 (vmcs12
->cr3_target_count
>= 3 &&
7289 vmcs12
->cr3_target_value2
== val
) ||
7290 (vmcs12
->cr3_target_count
>= 4 &&
7291 vmcs12
->cr3_target_value3
== val
))
7293 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7297 if (vmcs12
->cr4_guest_host_mask
&
7298 (vmcs12
->cr4_read_shadow
^ val
))
7302 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7308 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7309 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7312 case 1: /* mov from cr */
7315 if (vmcs12
->cpu_based_vm_exec_control
&
7316 CPU_BASED_CR3_STORE_EXITING
)
7320 if (vmcs12
->cpu_based_vm_exec_control
&
7321 CPU_BASED_CR8_STORE_EXITING
)
7328 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7329 * cr0. Other attempted changes are ignored, with no exit.
7331 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7332 (val
^ vmcs12
->cr0_read_shadow
))
7334 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7335 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7344 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7345 * should handle it ourselves in L0 (and then continue L2). Only call this
7346 * when in is_guest_mode (L2).
7348 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7350 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7351 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7352 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7353 u32 exit_reason
= vmx
->exit_reason
;
7355 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7356 vmcs_readl(EXIT_QUALIFICATION
),
7357 vmx
->idt_vectoring_info
,
7359 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7362 if (vmx
->nested
.nested_run_pending
)
7365 if (unlikely(vmx
->fail
)) {
7366 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7367 vmcs_read32(VM_INSTRUCTION_ERROR
));
7371 switch (exit_reason
) {
7372 case EXIT_REASON_EXCEPTION_NMI
:
7373 if (!is_exception(intr_info
))
7375 else if (is_page_fault(intr_info
))
7377 else if (is_no_device(intr_info
) &&
7378 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7380 return vmcs12
->exception_bitmap
&
7381 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7382 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7384 case EXIT_REASON_TRIPLE_FAULT
:
7386 case EXIT_REASON_PENDING_INTERRUPT
:
7387 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7388 case EXIT_REASON_NMI_WINDOW
:
7389 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7390 case EXIT_REASON_TASK_SWITCH
:
7392 case EXIT_REASON_CPUID
:
7393 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7396 case EXIT_REASON_HLT
:
7397 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7398 case EXIT_REASON_INVD
:
7400 case EXIT_REASON_INVLPG
:
7401 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7402 case EXIT_REASON_RDPMC
:
7403 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7404 case EXIT_REASON_RDTSC
:
7405 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7406 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7407 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7408 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7409 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7410 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7411 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7413 * VMX instructions trap unconditionally. This allows L1 to
7414 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7417 case EXIT_REASON_CR_ACCESS
:
7418 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7419 case EXIT_REASON_DR_ACCESS
:
7420 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7421 case EXIT_REASON_IO_INSTRUCTION
:
7422 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7423 case EXIT_REASON_MSR_READ
:
7424 case EXIT_REASON_MSR_WRITE
:
7425 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7426 case EXIT_REASON_INVALID_STATE
:
7428 case EXIT_REASON_MWAIT_INSTRUCTION
:
7429 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7430 case EXIT_REASON_MONITOR_INSTRUCTION
:
7431 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7432 case EXIT_REASON_PAUSE_INSTRUCTION
:
7433 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7434 nested_cpu_has2(vmcs12
,
7435 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7436 case EXIT_REASON_MCE_DURING_VMENTRY
:
7438 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7439 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7440 case EXIT_REASON_APIC_ACCESS
:
7441 return nested_cpu_has2(vmcs12
,
7442 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7443 case EXIT_REASON_APIC_WRITE
:
7444 /* apic_write should exit unconditionally. */
7446 case EXIT_REASON_EPT_VIOLATION
:
7448 * L0 always deals with the EPT violation. If nested EPT is
7449 * used, and the nested mmu code discovers that the address is
7450 * missing in the guest EPT table (EPT12), the EPT violation
7451 * will be injected with nested_ept_inject_page_fault()
7454 case EXIT_REASON_EPT_MISCONFIG
:
7456 * L2 never uses directly L1's EPT, but rather L0's own EPT
7457 * table (shadow on EPT) or a merged EPT table that L0 built
7458 * (EPT on EPT). So any problems with the structure of the
7459 * table is L0's fault.
7462 case EXIT_REASON_WBINVD
:
7463 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7464 case EXIT_REASON_XSETBV
:
7466 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
7468 * This should never happen, since it is not possible to
7469 * set XSS to a non-zero value---neither in L1 nor in L2.
7470 * If if it were, XSS would have to be checked against
7471 * the XSS exit bitmap in vmcs12.
7473 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
7479 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7481 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7482 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7485 static int vmx_enable_pml(struct vcpu_vmx
*vmx
)
7487 struct page
*pml_pg
;
7490 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
7494 vmx
->pml_pg
= pml_pg
;
7496 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
7497 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7499 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7500 exec_control
|= SECONDARY_EXEC_ENABLE_PML
;
7501 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7506 static void vmx_disable_pml(struct vcpu_vmx
*vmx
)
7510 ASSERT(vmx
->pml_pg
);
7511 __free_page(vmx
->pml_pg
);
7514 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7515 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
7516 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7519 static void vmx_flush_pml_buffer(struct vcpu_vmx
*vmx
)
7521 struct kvm
*kvm
= vmx
->vcpu
.kvm
;
7525 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
7527 /* Do nothing if PML buffer is empty */
7528 if (pml_idx
== (PML_ENTITY_NUM
- 1))
7531 /* PML index always points to next available PML buffer entity */
7532 if (pml_idx
>= PML_ENTITY_NUM
)
7537 pml_buf
= page_address(vmx
->pml_pg
);
7538 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
7541 gpa
= pml_buf
[pml_idx
];
7542 WARN_ON(gpa
& (PAGE_SIZE
- 1));
7543 mark_page_dirty(kvm
, gpa
>> PAGE_SHIFT
);
7546 /* reset PML index */
7547 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7551 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7552 * Called before reporting dirty_bitmap to userspace.
7554 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
7557 struct kvm_vcpu
*vcpu
;
7559 * We only need to kick vcpu out of guest mode here, as PML buffer
7560 * is flushed at beginning of all VMEXITs, and it's obvious that only
7561 * vcpus running in guest are possible to have unflushed GPAs in PML
7564 kvm_for_each_vcpu(i
, vcpu
, kvm
)
7565 kvm_vcpu_kick(vcpu
);
7569 * The guest has exited. See if we can fix it or if we need userspace
7572 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
7574 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7575 u32 exit_reason
= vmx
->exit_reason
;
7576 u32 vectoring_info
= vmx
->idt_vectoring_info
;
7579 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7580 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7581 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7582 * mode as if vcpus is in root mode, the PML buffer must has been
7586 vmx_flush_pml_buffer(vmx
);
7588 /* If guest state is invalid, start emulating */
7589 if (vmx
->emulation_required
)
7590 return handle_invalid_guest_state(vcpu
);
7592 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
7593 nested_vmx_vmexit(vcpu
, exit_reason
,
7594 vmcs_read32(VM_EXIT_INTR_INFO
),
7595 vmcs_readl(EXIT_QUALIFICATION
));
7599 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
7600 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7601 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7606 if (unlikely(vmx
->fail
)) {
7607 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7608 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7609 = vmcs_read32(VM_INSTRUCTION_ERROR
);
7615 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7616 * delivery event since it indicates guest is accessing MMIO.
7617 * The vm-exit can be triggered again after return to guest that
7618 * will cause infinite loop.
7620 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7621 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
7622 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
7623 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
7624 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7625 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
7626 vcpu
->run
->internal
.ndata
= 2;
7627 vcpu
->run
->internal
.data
[0] = vectoring_info
;
7628 vcpu
->run
->internal
.data
[1] = exit_reason
;
7632 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
7633 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
7634 get_vmcs12(vcpu
))))) {
7635 if (vmx_interrupt_allowed(vcpu
)) {
7636 vmx
->soft_vnmi_blocked
= 0;
7637 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
7638 vcpu
->arch
.nmi_pending
) {
7640 * This CPU don't support us in finding the end of an
7641 * NMI-blocked window if the guest runs with IRQs
7642 * disabled. So we pull the trigger after 1 s of
7643 * futile waiting, but inform the user about this.
7645 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
7646 "state on VCPU %d after 1 s timeout\n",
7647 __func__
, vcpu
->vcpu_id
);
7648 vmx
->soft_vnmi_blocked
= 0;
7652 if (exit_reason
< kvm_vmx_max_exit_handlers
7653 && kvm_vmx_exit_handlers
[exit_reason
])
7654 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
7656 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
7657 kvm_queue_exception(vcpu
, UD_VECTOR
);
7662 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
7664 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7666 if (is_guest_mode(vcpu
) &&
7667 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
7670 if (irr
== -1 || tpr
< irr
) {
7671 vmcs_write32(TPR_THRESHOLD
, 0);
7675 vmcs_write32(TPR_THRESHOLD
, irr
);
7678 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
7680 u32 sec_exec_control
;
7683 * There is not point to enable virtualize x2apic without enable
7686 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7687 !vmx_vm_has_apicv(vcpu
->kvm
))
7690 if (!vm_need_tpr_shadow(vcpu
->kvm
))
7693 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7696 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7697 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7699 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7700 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7702 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
7704 vmx_set_msr_bitmap(vcpu
);
7707 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
7709 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7712 * Currently we do not handle the nested case where L2 has an
7713 * APIC access page of its own; that page is still pinned.
7714 * Hence, we skip the case where the VCPU is in guest mode _and_
7715 * L1 prepared an APIC access page for L2.
7717 * For the case where L1 and L2 share the same APIC access page
7718 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7719 * in the vmcs12), this function will only update either the vmcs01
7720 * or the vmcs02. If the former, the vmcs02 will be updated by
7721 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7722 * the next L2->L1 exit.
7724 if (!is_guest_mode(vcpu
) ||
7725 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
7726 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
7727 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
7730 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
7738 status
= vmcs_read16(GUEST_INTR_STATUS
);
7743 vmcs_write16(GUEST_INTR_STATUS
, status
);
7747 static void vmx_set_rvi(int vector
)
7755 status
= vmcs_read16(GUEST_INTR_STATUS
);
7756 old
= (u8
)status
& 0xff;
7757 if ((u8
)vector
!= old
) {
7759 status
|= (u8
)vector
;
7760 vmcs_write16(GUEST_INTR_STATUS
, status
);
7764 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
7766 if (!is_guest_mode(vcpu
)) {
7767 vmx_set_rvi(max_irr
);
7775 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7778 if (nested_exit_on_intr(vcpu
))
7782 * Else, fall back to pre-APICv interrupt injection since L2
7783 * is run without virtual interrupt delivery.
7785 if (!kvm_event_needs_reinjection(vcpu
) &&
7786 vmx_interrupt_allowed(vcpu
)) {
7787 kvm_queue_interrupt(vcpu
, max_irr
, false);
7788 vmx_inject_irq(vcpu
);
7792 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
7794 if (!vmx_vm_has_apicv(vcpu
->kvm
))
7797 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
7798 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
7799 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
7800 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
7803 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
7807 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
7808 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
7811 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7812 exit_intr_info
= vmx
->exit_intr_info
;
7814 /* Handle machine checks before interrupts are enabled */
7815 if (is_machine_check(exit_intr_info
))
7816 kvm_machine_check();
7818 /* We need to handle NMIs before interrupts are enabled */
7819 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7820 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7821 kvm_before_handle_nmi(&vmx
->vcpu
);
7823 kvm_after_handle_nmi(&vmx
->vcpu
);
7827 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7829 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7832 * If external interrupt exists, IF bit is set in rflags/eflags on the
7833 * interrupt stack frame, and interrupt will be enabled on a return
7834 * from interrupt handler.
7836 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7837 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7838 unsigned int vector
;
7839 unsigned long entry
;
7841 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7842 #ifdef CONFIG_X86_64
7846 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7847 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7848 entry
= gate_offset(*desc
);
7850 #ifdef CONFIG_X86_64
7851 "mov %%" _ASM_SP
", %[sp]\n\t"
7852 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7857 "orl $0x200, (%%" _ASM_SP
")\n\t"
7858 __ASM_SIZE(push
) " $%c[cs]\n\t"
7859 "call *%[entry]\n\t"
7861 #ifdef CONFIG_X86_64
7866 [ss
]"i"(__KERNEL_DS
),
7867 [cs
]"i"(__KERNEL_CS
)
7873 static bool vmx_mpx_supported(void)
7875 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
7876 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
7879 static bool vmx_xsaves_supported(void)
7881 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
7882 SECONDARY_EXEC_XSAVES
;
7885 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7890 bool idtv_info_valid
;
7892 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7894 if (cpu_has_virtual_nmis()) {
7895 if (vmx
->nmi_known_unmasked
)
7898 * Can't use vmx->exit_intr_info since we're not sure what
7899 * the exit reason is.
7901 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7902 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7903 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7905 * SDM 3: 27.7.1.2 (September 2008)
7906 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7907 * a guest IRET fault.
7908 * SDM 3: 23.2.2 (September 2008)
7909 * Bit 12 is undefined in any of the following cases:
7910 * If the VM exit sets the valid bit in the IDT-vectoring
7911 * information field.
7912 * If the VM exit is due to a double fault.
7914 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7915 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7916 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7917 GUEST_INTR_STATE_NMI
);
7919 vmx
->nmi_known_unmasked
=
7920 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7921 & GUEST_INTR_STATE_NMI
);
7922 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7923 vmx
->vnmi_blocked_time
+=
7924 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7927 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7928 u32 idt_vectoring_info
,
7929 int instr_len_field
,
7930 int error_code_field
)
7934 bool idtv_info_valid
;
7936 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7938 vcpu
->arch
.nmi_injected
= false;
7939 kvm_clear_exception_queue(vcpu
);
7940 kvm_clear_interrupt_queue(vcpu
);
7942 if (!idtv_info_valid
)
7945 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7947 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7948 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7951 case INTR_TYPE_NMI_INTR
:
7952 vcpu
->arch
.nmi_injected
= true;
7954 * SDM 3: 27.7.1.2 (September 2008)
7955 * Clear bit "block by NMI" before VM entry if a NMI
7958 vmx_set_nmi_mask(vcpu
, false);
7960 case INTR_TYPE_SOFT_EXCEPTION
:
7961 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7963 case INTR_TYPE_HARD_EXCEPTION
:
7964 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7965 u32 err
= vmcs_read32(error_code_field
);
7966 kvm_requeue_exception_e(vcpu
, vector
, err
);
7968 kvm_requeue_exception(vcpu
, vector
);
7970 case INTR_TYPE_SOFT_INTR
:
7971 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7973 case INTR_TYPE_EXT_INTR
:
7974 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7981 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7983 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7984 VM_EXIT_INSTRUCTION_LEN
,
7985 IDT_VECTORING_ERROR_CODE
);
7988 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7990 __vmx_complete_interrupts(vcpu
,
7991 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7992 VM_ENTRY_INSTRUCTION_LEN
,
7993 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7995 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7998 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8001 struct perf_guest_switch_msr
*msrs
;
8003 msrs
= perf_guest_get_msrs(&nr_msrs
);
8008 for (i
= 0; i
< nr_msrs
; i
++)
8009 if (msrs
[i
].host
== msrs
[i
].guest
)
8010 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8012 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8016 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8018 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8019 unsigned long debugctlmsr
, cr4
;
8021 /* Record the guest's net vcpu time for enforced NMI injections. */
8022 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8023 vmx
->entry_time
= ktime_get();
8025 /* Don't enter VMX if guest state is invalid, let the exit handler
8026 start emulation until we arrive back to a valid state */
8027 if (vmx
->emulation_required
)
8030 if (vmx
->ple_window_dirty
) {
8031 vmx
->ple_window_dirty
= false;
8032 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8035 if (vmx
->nested
.sync_shadow_vmcs
) {
8036 copy_vmcs12_to_shadow(vmx
);
8037 vmx
->nested
.sync_shadow_vmcs
= false;
8040 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8041 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8042 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8043 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8046 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8047 vmcs_writel(HOST_CR4
, cr4
);
8048 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8051 /* When single-stepping over STI and MOV SS, we must clear the
8052 * corresponding interruptibility bits in the guest state. Otherwise
8053 * vmentry fails as it then expects bit 14 (BS) in pending debug
8054 * exceptions being set, but that's not correct for the guest debugging
8056 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8057 vmx_set_interrupt_shadow(vcpu
, 0);
8059 atomic_switch_perf_msrs(vmx
);
8060 debugctlmsr
= get_debugctlmsr();
8062 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8064 /* Store host registers */
8065 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8066 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8067 "push %%" _ASM_CX
" \n\t"
8068 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8070 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8071 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8073 /* Reload cr2 if changed */
8074 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8075 "mov %%cr2, %%" _ASM_DX
" \n\t"
8076 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8078 "mov %%" _ASM_AX
", %%cr2 \n\t"
8080 /* Check if vmlaunch of vmresume is needed */
8081 "cmpl $0, %c[launched](%0) \n\t"
8082 /* Load guest registers. Don't clobber flags. */
8083 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8084 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8085 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8086 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8087 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8088 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8089 #ifdef CONFIG_X86_64
8090 "mov %c[r8](%0), %%r8 \n\t"
8091 "mov %c[r9](%0), %%r9 \n\t"
8092 "mov %c[r10](%0), %%r10 \n\t"
8093 "mov %c[r11](%0), %%r11 \n\t"
8094 "mov %c[r12](%0), %%r12 \n\t"
8095 "mov %c[r13](%0), %%r13 \n\t"
8096 "mov %c[r14](%0), %%r14 \n\t"
8097 "mov %c[r15](%0), %%r15 \n\t"
8099 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8101 /* Enter guest mode */
8103 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8105 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8107 /* Save guest registers, load host registers, keep flags */
8108 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8110 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8111 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8112 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8113 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8114 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8115 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8116 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8117 #ifdef CONFIG_X86_64
8118 "mov %%r8, %c[r8](%0) \n\t"
8119 "mov %%r9, %c[r9](%0) \n\t"
8120 "mov %%r10, %c[r10](%0) \n\t"
8121 "mov %%r11, %c[r11](%0) \n\t"
8122 "mov %%r12, %c[r12](%0) \n\t"
8123 "mov %%r13, %c[r13](%0) \n\t"
8124 "mov %%r14, %c[r14](%0) \n\t"
8125 "mov %%r15, %c[r15](%0) \n\t"
8127 "mov %%cr2, %%" _ASM_AX
" \n\t"
8128 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8130 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8131 "setbe %c[fail](%0) \n\t"
8132 ".pushsection .rodata \n\t"
8133 ".global vmx_return \n\t"
8134 "vmx_return: " _ASM_PTR
" 2b \n\t"
8136 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8137 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8138 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8139 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8140 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8141 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8142 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8143 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8144 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8145 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8146 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8147 #ifdef CONFIG_X86_64
8148 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8149 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8150 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8151 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8152 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8153 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8154 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8155 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8157 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8158 [wordsize
]"i"(sizeof(ulong
))
8160 #ifdef CONFIG_X86_64
8161 , "rax", "rbx", "rdi", "rsi"
8162 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8164 , "eax", "ebx", "edi", "esi"
8168 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8170 update_debugctlmsr(debugctlmsr
);
8172 #ifndef CONFIG_X86_64
8174 * The sysexit path does not restore ds/es, so we must set them to
8175 * a reasonable value ourselves.
8177 * We can't defer this to vmx_load_host_state() since that function
8178 * may be executed in interrupt context, which saves and restore segments
8179 * around it, nullifying its effect.
8181 loadsegment(ds
, __USER_DS
);
8182 loadsegment(es
, __USER_DS
);
8185 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8186 | (1 << VCPU_EXREG_RFLAGS
)
8187 | (1 << VCPU_EXREG_PDPTR
)
8188 | (1 << VCPU_EXREG_SEGMENTS
)
8189 | (1 << VCPU_EXREG_CR3
));
8190 vcpu
->arch
.regs_dirty
= 0;
8192 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8194 vmx
->loaded_vmcs
->launched
= 1;
8196 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8197 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
8200 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8201 * we did not inject a still-pending event to L1 now because of
8202 * nested_run_pending, we need to re-enable this bit.
8204 if (vmx
->nested
.nested_run_pending
)
8205 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8207 vmx
->nested
.nested_run_pending
= 0;
8209 vmx_complete_atomic_exit(vmx
);
8210 vmx_recover_nmi_blocking(vmx
);
8211 vmx_complete_interrupts(vmx
);
8214 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8216 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8219 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8223 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8225 vmx_vcpu_load(vcpu
, cpu
);
8230 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8232 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8235 vmx_disable_pml(vmx
);
8237 leave_guest_mode(vcpu
);
8238 vmx_load_vmcs01(vcpu
);
8240 free_loaded_vmcs(vmx
->loaded_vmcs
);
8241 kfree(vmx
->guest_msrs
);
8242 kvm_vcpu_uninit(vcpu
);
8243 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8246 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
8249 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
8253 return ERR_PTR(-ENOMEM
);
8257 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
8261 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
8262 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
8266 if (!vmx
->guest_msrs
) {
8270 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8271 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
8272 if (!vmx
->loaded_vmcs
->vmcs
)
8275 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
8276 loaded_vmcs_init(vmx
->loaded_vmcs
);
8281 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
8282 vmx
->vcpu
.cpu
= cpu
;
8283 err
= vmx_vcpu_setup(vmx
);
8284 vmx_vcpu_put(&vmx
->vcpu
);
8288 if (vm_need_virtualize_apic_accesses(kvm
)) {
8289 err
= alloc_apic_access_page(kvm
);
8295 if (!kvm
->arch
.ept_identity_map_addr
)
8296 kvm
->arch
.ept_identity_map_addr
=
8297 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
8298 err
= init_rmode_identity_map(kvm
);
8304 nested_vmx_setup_ctls_msrs(vmx
);
8306 vmx
->nested
.current_vmptr
= -1ull;
8307 vmx
->nested
.current_vmcs12
= NULL
;
8310 * If PML is turned on, failure on enabling PML just results in failure
8311 * of creating the vcpu, therefore we can simplify PML logic (by
8312 * avoiding dealing with cases, such as enabling PML partially on vcpus
8313 * for the guest, etc.
8316 err
= vmx_enable_pml(vmx
);
8324 free_loaded_vmcs(vmx
->loaded_vmcs
);
8326 kfree(vmx
->guest_msrs
);
8328 kvm_vcpu_uninit(&vmx
->vcpu
);
8331 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8332 return ERR_PTR(err
);
8335 static void __init
vmx_check_processor_compat(void *rtn
)
8337 struct vmcs_config vmcs_conf
;
8340 if (setup_vmcs_config(&vmcs_conf
) < 0)
8342 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
8343 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
8344 smp_processor_id());
8349 static int get_ept_level(void)
8351 return VMX_EPT_DEFAULT_GAW
+ 1;
8354 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8358 /* For VT-d and EPT combination
8359 * 1. MMIO: always map as UC
8361 * a. VT-d without snooping control feature: can't guarantee the
8362 * result, try to trust guest.
8363 * b. VT-d with snooping control feature: snooping control feature of
8364 * VT-d engine can guarantee the cache correctness. Just set it
8365 * to WB to keep consistent with host. So the same as item 3.
8366 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8367 * consistent with host MTRR
8370 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
8371 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
8372 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
8373 VMX_EPT_MT_EPTE_SHIFT
;
8375 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
8381 static int vmx_get_lpage_level(void)
8383 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
8384 return PT_DIRECTORY_LEVEL
;
8386 /* For shadow and EPT supported 1GB page */
8387 return PT_PDPE_LEVEL
;
8390 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
8392 struct kvm_cpuid_entry2
*best
;
8393 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8396 vmx
->rdtscp_enabled
= false;
8397 if (vmx_rdtscp_supported()) {
8398 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8399 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
8400 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
8401 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
8402 vmx
->rdtscp_enabled
= true;
8404 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
8405 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8411 /* Exposing INVPCID only when PCID is exposed */
8412 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
8413 if (vmx_invpcid_supported() &&
8414 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
8415 guest_cpuid_has_pcid(vcpu
)) {
8416 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8417 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
8418 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8421 if (cpu_has_secondary_exec_ctrls()) {
8422 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8423 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
8424 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8428 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
8432 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
8434 if (func
== 1 && nested
)
8435 entry
->ecx
|= bit(X86_FEATURE_VMX
);
8438 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
8439 struct x86_exception
*fault
)
8441 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8444 if (fault
->error_code
& PFERR_RSVD_MASK
)
8445 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
8447 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
8448 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
8449 vmcs12
->guest_physical_address
= fault
->address
;
8452 /* Callbacks for nested_ept_init_mmu_context: */
8454 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
8456 /* return the page table to be shadowed - in our case, EPT12 */
8457 return get_vmcs12(vcpu
)->ept_pointer
;
8460 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
8462 WARN_ON(mmu_is_nested(vcpu
));
8463 kvm_init_shadow_ept_mmu(vcpu
,
8464 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
8465 VMX_EPT_EXECUTE_ONLY_BIT
);
8466 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
8467 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
8468 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
8470 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
8473 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
8475 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
8478 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
8481 bool inequality
, bit
;
8483 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
8485 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
8486 vmcs12
->page_fault_error_code_match
;
8487 return inequality
^ bit
;
8490 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
8491 struct x86_exception
*fault
)
8493 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8495 WARN_ON(!is_guest_mode(vcpu
));
8497 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
8498 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
8499 vmcs_read32(VM_EXIT_INTR_INFO
),
8500 vmcs_readl(EXIT_QUALIFICATION
));
8502 kvm_inject_page_fault(vcpu
, fault
);
8505 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
8506 struct vmcs12
*vmcs12
)
8508 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8510 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8511 /* TODO: Also verify bits beyond physical address width are 0 */
8512 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
))
8516 * Translate L1 physical address to host physical
8517 * address for vmcs02. Keep the page pinned, so this
8518 * physical address remains valid. We keep a reference
8519 * to it so we can release it later.
8521 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
8522 nested_release_page(vmx
->nested
.apic_access_page
);
8523 vmx
->nested
.apic_access_page
=
8524 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
8527 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
8528 /* TODO: Also verify bits beyond physical address width are 0 */
8529 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
))
8532 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
8533 nested_release_page(vmx
->nested
.virtual_apic_page
);
8534 vmx
->nested
.virtual_apic_page
=
8535 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
8538 * Failing the vm entry is _not_ what the processor does
8539 * but it's basically the only possibility we have.
8540 * We could still enter the guest if CR8 load exits are
8541 * enabled, CR8 store exits are enabled, and virtualize APIC
8542 * access is disabled; in this case the processor would never
8543 * use the TPR shadow and we could simply clear the bit from
8544 * the execution control. But such a configuration is useless,
8545 * so let's keep the code simple.
8547 if (!vmx
->nested
.virtual_apic_page
)
8554 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
8556 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
8557 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8559 if (vcpu
->arch
.virtual_tsc_khz
== 0)
8562 /* Make sure short timeouts reliably trigger an immediate vmexit.
8563 * hrtimer_start does not guarantee this. */
8564 if (preemption_timeout
<= 1) {
8565 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
8569 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8570 preemption_timeout
*= 1000000;
8571 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
8572 hrtimer_start(&vmx
->nested
.preemption_timer
,
8573 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
8576 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
8577 struct vmcs12
*vmcs12
)
8582 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8585 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
8589 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8591 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
8592 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
8599 * Merge L0's and L1's MSR bitmap, return false to indicate that
8600 * we do not use the hardware.
8602 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
8603 struct vmcs12
*vmcs12
)
8607 unsigned long *msr_bitmap
;
8609 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
8612 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
8617 msr_bitmap
= (unsigned long *)kmap(page
);
8619 nested_release_page_clean(page
);
8624 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
8625 if (nested_cpu_has_apic_reg_virt(vmcs12
))
8626 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8627 nested_vmx_disable_intercept_for_msr(
8629 vmx_msr_bitmap_nested
,
8631 /* TPR is allowed */
8632 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
8633 vmx_msr_bitmap_nested
,
8634 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
8635 MSR_TYPE_R
| MSR_TYPE_W
);
8638 * Enable reading intercept of all the x2apic
8639 * MSRs. We should not rely on vmcs12 to do any
8640 * optimizations here, it may have been modified
8643 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8644 __vmx_enable_intercept_for_msr(
8645 vmx_msr_bitmap_nested
,
8649 __vmx_enable_intercept_for_msr(
8650 vmx_msr_bitmap_nested
,
8651 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
8655 nested_release_page_clean(page
);
8660 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
8661 struct vmcs12
*vmcs12
)
8663 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
8664 !nested_cpu_has_apic_reg_virt(vmcs12
))
8668 * If virtualize x2apic mode is enabled,
8669 * virtualize apic access must be disabled.
8671 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
8672 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8675 /* tpr shadow is needed by all apicv features. */
8676 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8682 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
8683 unsigned long count_field
,
8684 unsigned long addr_field
,
8689 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
8690 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
8696 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
8697 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
8698 pr_warn_ratelimited(
8699 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8700 addr_field
, maxphyaddr
, count
, addr
);
8706 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
8707 struct vmcs12
*vmcs12
)
8711 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
8712 vmcs12
->vm_exit_msr_store_count
== 0 &&
8713 vmcs12
->vm_entry_msr_load_count
== 0)
8714 return 0; /* Fast path */
8715 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8716 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
8717 VM_EXIT_MSR_LOAD_ADDR
, maxphyaddr
) ||
8718 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
8719 VM_EXIT_MSR_STORE_ADDR
, maxphyaddr
) ||
8720 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
8721 VM_ENTRY_MSR_LOAD_ADDR
, maxphyaddr
))
8726 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
8727 struct vmx_msr_entry
*e
)
8729 /* x2APIC MSR accesses are not allowed */
8730 if (apic_x2apic_mode(vcpu
->arch
.apic
) && e
->index
>> 8 == 0x8)
8732 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
8733 e
->index
== MSR_IA32_UCODE_REV
)
8735 if (e
->reserved
!= 0)
8740 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
8741 struct vmx_msr_entry
*e
)
8743 if (e
->index
== MSR_FS_BASE
||
8744 e
->index
== MSR_GS_BASE
||
8745 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
8746 nested_vmx_msr_check_common(vcpu
, e
))
8751 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
8752 struct vmx_msr_entry
*e
)
8754 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
8755 nested_vmx_msr_check_common(vcpu
, e
))
8761 * Load guest's/host's msr at nested entry/exit.
8762 * return 0 for success, entry index for failure.
8764 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
8767 struct vmx_msr_entry e
;
8768 struct msr_data msr
;
8770 msr
.host_initiated
= false;
8771 for (i
= 0; i
< count
; i
++) {
8772 if (kvm_read_guest(vcpu
->kvm
, gpa
+ i
* sizeof(e
),
8774 pr_warn_ratelimited(
8775 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8776 __func__
, i
, gpa
+ i
* sizeof(e
));
8779 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
8780 pr_warn_ratelimited(
8781 "%s check failed (%u, 0x%x, 0x%x)\n",
8782 __func__
, i
, e
.index
, e
.reserved
);
8785 msr
.index
= e
.index
;
8787 if (kvm_set_msr(vcpu
, &msr
)) {
8788 pr_warn_ratelimited(
8789 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8790 __func__
, i
, e
.index
, e
.value
);
8799 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
8802 struct vmx_msr_entry e
;
8804 for (i
= 0; i
< count
; i
++) {
8805 if (kvm_read_guest(vcpu
->kvm
,
8806 gpa
+ i
* sizeof(e
),
8807 &e
, 2 * sizeof(u32
))) {
8808 pr_warn_ratelimited(
8809 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8810 __func__
, i
, gpa
+ i
* sizeof(e
));
8813 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
8814 pr_warn_ratelimited(
8815 "%s check failed (%u, 0x%x, 0x%x)\n",
8816 __func__
, i
, e
.index
, e
.reserved
);
8819 if (kvm_get_msr(vcpu
, e
.index
, &e
.value
)) {
8820 pr_warn_ratelimited(
8821 "%s cannot read MSR (%u, 0x%x)\n",
8822 __func__
, i
, e
.index
);
8825 if (kvm_write_guest(vcpu
->kvm
,
8826 gpa
+ i
* sizeof(e
) +
8827 offsetof(struct vmx_msr_entry
, value
),
8828 &e
.value
, sizeof(e
.value
))) {
8829 pr_warn_ratelimited(
8830 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8831 __func__
, i
, e
.index
, e
.value
);
8839 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8840 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
8841 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
8842 * guest in a way that will both be appropriate to L1's requests, and our
8843 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8844 * function also has additional necessary side-effects, like setting various
8845 * vcpu->arch fields.
8847 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8849 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8852 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
8853 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
8854 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
8855 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
8856 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
8857 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
8858 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
8859 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
8860 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
8861 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
8862 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
8863 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
8864 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
8865 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
8866 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
8867 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
8868 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
8869 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
8870 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
8871 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
8872 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
8873 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
8874 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
8875 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
8876 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
8877 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
8878 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
8879 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
8880 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
8881 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
8882 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
8883 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
8884 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
8885 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
8886 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
8887 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
8889 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
8890 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
8891 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
8893 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
8894 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
8896 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
8897 vmcs12
->vm_entry_intr_info_field
);
8898 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
8899 vmcs12
->vm_entry_exception_error_code
);
8900 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
8901 vmcs12
->vm_entry_instruction_len
);
8902 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
8903 vmcs12
->guest_interruptibility_info
);
8904 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
8905 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
8906 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
8907 vmcs12
->guest_pending_dbg_exceptions
);
8908 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
8909 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
8911 if (nested_cpu_has_xsaves(vmcs12
))
8912 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
8913 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
8915 exec_control
= vmcs12
->pin_based_vm_exec_control
;
8916 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
8917 exec_control
&= ~(PIN_BASED_VMX_PREEMPTION_TIMER
|
8918 PIN_BASED_POSTED_INTR
);
8919 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
8921 vmx
->nested
.preemption_timer_expired
= false;
8922 if (nested_cpu_has_preemption_timer(vmcs12
))
8923 vmx_start_preemption_timer(vcpu
);
8926 * Whether page-faults are trapped is determined by a combination of
8927 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8928 * If enable_ept, L0 doesn't care about page faults and we should
8929 * set all of these to L1's desires. However, if !enable_ept, L0 does
8930 * care about (at least some) page faults, and because it is not easy
8931 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8932 * to exit on each and every L2 page fault. This is done by setting
8933 * MASK=MATCH=0 and (see below) EB.PF=1.
8934 * Note that below we don't need special code to set EB.PF beyond the
8935 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8936 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8937 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8939 * A problem with this approach (when !enable_ept) is that L1 may be
8940 * injected with more page faults than it asked for. This could have
8941 * caused problems, but in practice existing hypervisors don't care.
8942 * To fix this, we will need to emulate the PFEC checking (on the L1
8943 * page tables), using walk_addr(), when injecting PFs to L1.
8945 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
8946 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
8947 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
8948 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
8950 if (cpu_has_secondary_exec_ctrls()) {
8951 exec_control
= vmx_secondary_exec_control(vmx
);
8952 if (!vmx
->rdtscp_enabled
)
8953 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
8954 /* Take the following fields only from vmcs12 */
8955 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
8956 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
8957 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
8958 if (nested_cpu_has(vmcs12
,
8959 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
8960 exec_control
|= vmcs12
->secondary_vm_exec_control
;
8962 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
8964 * If translation failed, no matter: This feature asks
8965 * to exit when accessing the given address, and if it
8966 * can never be accessed, this feature won't do
8969 if (!vmx
->nested
.apic_access_page
)
8971 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8973 vmcs_write64(APIC_ACCESS_ADDR
,
8974 page_to_phys(vmx
->nested
.apic_access_page
));
8975 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
8976 (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))) {
8978 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8979 kvm_vcpu_reload_apic_access_page(vcpu
);
8982 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
8987 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8988 * Some constant fields are set here by vmx_set_constant_host_state().
8989 * Other fields are different per CPU, and will be set later when
8990 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8992 vmx_set_constant_host_state(vmx
);
8995 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8996 * entry, but only if the current (host) sp changed from the value
8997 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8998 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8999 * here we just force the write to happen on entry.
9003 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9004 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9005 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9006 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9007 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9009 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9010 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9011 page_to_phys(vmx
->nested
.virtual_apic_page
));
9012 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9015 if (cpu_has_vmx_msr_bitmap() &&
9016 exec_control
& CPU_BASED_USE_MSR_BITMAPS
&&
9017 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
)) {
9018 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_nested
));
9020 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9023 * Merging of IO bitmap not currently supported.
9024 * Rather, exit every time.
9026 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9027 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9029 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9031 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9032 * bitwise-or of what L1 wants to trap for L2, and what we want to
9033 * trap. Note that CR0.TS also needs updating - we do this later.
9035 update_exception_bitmap(vcpu
);
9036 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9037 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9039 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9040 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9041 * bits are further modified by vmx_set_efer() below.
9043 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9045 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9046 * emulated by vmx_set_efer(), below.
9048 vm_entry_controls_init(vmx
,
9049 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9050 ~VM_ENTRY_IA32E_MODE
) |
9051 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9053 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9054 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9055 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9056 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9057 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9060 set_cr4_guest_host_mask(vmx
);
9062 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9063 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9065 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9066 vmcs_write64(TSC_OFFSET
,
9067 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9069 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9073 * Trivially support vpid by letting L2s share their parent
9074 * L1's vpid. TODO: move to a more elaborate solution, giving
9075 * each L2 its own vpid and exposing the vpid feature to L1.
9077 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9078 vmx_flush_tlb(vcpu
);
9081 if (nested_cpu_has_ept(vmcs12
)) {
9082 kvm_mmu_unload(vcpu
);
9083 nested_ept_init_mmu_context(vcpu
);
9086 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9087 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9088 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9089 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9091 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9092 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9093 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9096 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9097 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9098 * The CR0_READ_SHADOW is what L2 should have expected to read given
9099 * the specifications by L1; It's not enough to take
9100 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9101 * have more bits than L1 expected.
9103 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
9104 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
9106 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
9107 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
9109 /* shadow page tables on either EPT or shadow page tables */
9110 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
9111 kvm_mmu_reset_context(vcpu
);
9114 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
9117 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9120 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
9121 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
9122 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
9123 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
9126 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
9127 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
9131 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9132 * for running an L2 nested guest.
9134 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
9136 struct vmcs12
*vmcs12
;
9137 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9139 struct loaded_vmcs
*vmcs02
;
9143 if (!nested_vmx_check_permission(vcpu
) ||
9144 !nested_vmx_check_vmcs12(vcpu
))
9147 skip_emulated_instruction(vcpu
);
9148 vmcs12
= get_vmcs12(vcpu
);
9150 if (enable_shadow_vmcs
)
9151 copy_shadow_to_vmcs12(vmx
);
9154 * The nested entry process starts with enforcing various prerequisites
9155 * on vmcs12 as required by the Intel SDM, and act appropriately when
9156 * they fail: As the SDM explains, some conditions should cause the
9157 * instruction to fail, while others will cause the instruction to seem
9158 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9159 * To speed up the normal (success) code path, we should avoid checking
9160 * for misconfigurations which will anyway be caught by the processor
9161 * when using the merged vmcs02.
9163 if (vmcs12
->launch_state
== launch
) {
9164 nested_vmx_failValid(vcpu
,
9165 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9166 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
9170 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
9171 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
9172 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9176 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
9177 /*TODO: Also verify bits beyond physical address width are 0*/
9178 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9182 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
9183 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9187 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
9188 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9192 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
9193 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9197 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
9198 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
9199 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
9200 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
9201 vmx
->nested
.nested_vmx_secondary_ctls_low
,
9202 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
9203 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
9204 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
9205 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
9206 !vmx_control_verify(vmcs12
->vm_exit_controls
,
9207 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
9208 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
9209 !vmx_control_verify(vmcs12
->vm_entry_controls
,
9210 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
9211 vmx
->nested
.nested_vmx_entry_ctls_high
))
9213 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9217 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
9218 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9219 nested_vmx_failValid(vcpu
,
9220 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
9224 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
9225 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9226 nested_vmx_entry_failure(vcpu
, vmcs12
,
9227 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9230 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
9231 nested_vmx_entry_failure(vcpu
, vmcs12
,
9232 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
9237 * If the load IA32_EFER VM-entry control is 1, the following checks
9238 * are performed on the field for the IA32_EFER MSR:
9239 * - Bits reserved in the IA32_EFER MSR must be 0.
9240 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9241 * the IA-32e mode guest VM-exit control. It must also be identical
9242 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9245 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
9246 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
9247 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
9248 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
9249 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
9250 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
9251 nested_vmx_entry_failure(vcpu
, vmcs12
,
9252 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9258 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9259 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9260 * the values of the LMA and LME bits in the field must each be that of
9261 * the host address-space size VM-exit control.
9263 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
9264 ia32e
= (vmcs12
->vm_exit_controls
&
9265 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
9266 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
9267 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
9268 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
9269 nested_vmx_entry_failure(vcpu
, vmcs12
,
9270 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9276 * We're finally done with prerequisite checking, and can start with
9280 vmcs02
= nested_get_current_vmcs02(vmx
);
9284 enter_guest_mode(vcpu
);
9286 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
9288 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
9289 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9292 vmx
->loaded_vmcs
= vmcs02
;
9294 vmx_vcpu_load(vcpu
, cpu
);
9298 vmx_segment_cache_clear(vmx
);
9300 prepare_vmcs02(vcpu
, vmcs12
);
9302 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
9303 vmcs12
->vm_entry_msr_load_addr
,
9304 vmcs12
->vm_entry_msr_load_count
);
9305 if (msr_entry_idx
) {
9306 leave_guest_mode(vcpu
);
9307 vmx_load_vmcs01(vcpu
);
9308 nested_vmx_entry_failure(vcpu
, vmcs12
,
9309 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
9313 vmcs12
->launch_state
= 1;
9315 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
9316 return kvm_emulate_halt(vcpu
);
9318 vmx
->nested
.nested_run_pending
= 1;
9321 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9322 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9323 * returned as far as L1 is concerned. It will only return (and set
9324 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9330 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9331 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9332 * This function returns the new value we should put in vmcs12.guest_cr0.
9333 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9334 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9335 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9336 * didn't trap the bit, because if L1 did, so would L0).
9337 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9338 * been modified by L2, and L1 knows it. So just leave the old value of
9339 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9340 * isn't relevant, because if L0 traps this bit it can set it to anything.
9341 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9342 * changed these bits, and therefore they need to be updated, but L0
9343 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9344 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9346 static inline unsigned long
9347 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9350 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
9351 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
9352 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
9353 vcpu
->arch
.cr0_guest_owned_bits
));
9356 static inline unsigned long
9357 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9360 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
9361 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
9362 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
9363 vcpu
->arch
.cr4_guest_owned_bits
));
9366 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
9367 struct vmcs12
*vmcs12
)
9372 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
9373 nr
= vcpu
->arch
.exception
.nr
;
9374 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
9376 if (kvm_exception_is_soft(nr
)) {
9377 vmcs12
->vm_exit_instruction_len
=
9378 vcpu
->arch
.event_exit_inst_len
;
9379 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
9381 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
9383 if (vcpu
->arch
.exception
.has_error_code
) {
9384 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
9385 vmcs12
->idt_vectoring_error_code
=
9386 vcpu
->arch
.exception
.error_code
;
9389 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
9390 } else if (vcpu
->arch
.nmi_injected
) {
9391 vmcs12
->idt_vectoring_info_field
=
9392 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
9393 } else if (vcpu
->arch
.interrupt
.pending
) {
9394 nr
= vcpu
->arch
.interrupt
.nr
;
9395 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
9397 if (vcpu
->arch
.interrupt
.soft
) {
9398 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
9399 vmcs12
->vm_entry_instruction_len
=
9400 vcpu
->arch
.event_exit_inst_len
;
9402 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
9404 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
9408 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
9410 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9412 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
9413 vmx
->nested
.preemption_timer_expired
) {
9414 if (vmx
->nested
.nested_run_pending
)
9416 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
9420 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
9421 if (vmx
->nested
.nested_run_pending
||
9422 vcpu
->arch
.interrupt
.pending
)
9424 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9425 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
9426 INTR_INFO_VALID_MASK
, 0);
9428 * The NMI-triggered VM exit counts as injection:
9429 * clear this one and block further NMIs.
9431 vcpu
->arch
.nmi_pending
= 0;
9432 vmx_set_nmi_mask(vcpu
, true);
9436 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
9437 nested_exit_on_intr(vcpu
)) {
9438 if (vmx
->nested
.nested_run_pending
)
9440 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
9446 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
9449 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
9452 if (ktime_to_ns(remaining
) <= 0)
9455 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
9456 do_div(value
, 1000000);
9457 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9461 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9462 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9463 * and this function updates it to reflect the changes to the guest state while
9464 * L2 was running (and perhaps made some exits which were handled directly by L0
9465 * without going back to L1), and to reflect the exit reason.
9466 * Note that we do not have to copy here all VMCS fields, just those that
9467 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9468 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9469 * which already writes to vmcs12 directly.
9471 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
9472 u32 exit_reason
, u32 exit_intr_info
,
9473 unsigned long exit_qualification
)
9475 /* update guest state fields: */
9476 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
9477 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
9479 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
9480 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
9481 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
9483 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
9484 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
9485 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
9486 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
9487 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
9488 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
9489 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
9490 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
9491 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
9492 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
9493 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
9494 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
9495 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
9496 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
9497 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
9498 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
9499 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
9500 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
9501 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
9502 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
9503 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
9504 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
9505 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
9506 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
9507 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
9508 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
9509 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
9510 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
9511 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
9512 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
9513 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
9514 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
9515 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
9516 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
9517 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
9518 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
9520 vmcs12
->guest_interruptibility_info
=
9521 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
9522 vmcs12
->guest_pending_dbg_exceptions
=
9523 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
9524 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
9525 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
9527 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
9529 if (nested_cpu_has_preemption_timer(vmcs12
)) {
9530 if (vmcs12
->vm_exit_controls
&
9531 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
9532 vmcs12
->vmx_preemption_timer_value
=
9533 vmx_get_preemption_timer_value(vcpu
);
9534 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
9538 * In some cases (usually, nested EPT), L2 is allowed to change its
9539 * own CR3 without exiting. If it has changed it, we must keep it.
9540 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9541 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9543 * Additionally, restore L2's PDPTR to vmcs12.
9546 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
9547 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
9548 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
9549 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
9550 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
9553 vmcs12
->vm_entry_controls
=
9554 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
9555 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
9557 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
9558 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
9559 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9562 /* TODO: These cannot have changed unless we have MSR bitmaps and
9563 * the relevant bit asks not to trap the change */
9564 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
9565 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
9566 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
9567 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
9568 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
9569 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
9570 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
9571 if (vmx_mpx_supported())
9572 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
9573 if (nested_cpu_has_xsaves(vmcs12
))
9574 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
9576 /* update exit information fields: */
9578 vmcs12
->vm_exit_reason
= exit_reason
;
9579 vmcs12
->exit_qualification
= exit_qualification
;
9581 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
9582 if ((vmcs12
->vm_exit_intr_info
&
9583 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
9584 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
9585 vmcs12
->vm_exit_intr_error_code
=
9586 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
9587 vmcs12
->idt_vectoring_info_field
= 0;
9588 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
9589 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
9591 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
9592 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9593 * instead of reading the real value. */
9594 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
9597 * Transfer the event that L0 or L1 may wanted to inject into
9598 * L2 to IDT_VECTORING_INFO_FIELD.
9600 vmcs12_save_pending_event(vcpu
, vmcs12
);
9604 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9605 * preserved above and would only end up incorrectly in L1.
9607 vcpu
->arch
.nmi_injected
= false;
9608 kvm_clear_exception_queue(vcpu
);
9609 kvm_clear_interrupt_queue(vcpu
);
9613 * A part of what we need to when the nested L2 guest exits and we want to
9614 * run its L1 parent, is to reset L1's guest state to the host state specified
9616 * This function is to be called not only on normal nested exit, but also on
9617 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9618 * Failures During or After Loading Guest State").
9619 * This function should be called when the active VMCS is L1's (vmcs01).
9621 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
9622 struct vmcs12
*vmcs12
)
9624 struct kvm_segment seg
;
9626 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
9627 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
9628 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
9629 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9631 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9632 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9634 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
9635 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
9636 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
9638 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9639 * actually changed, because it depends on the current state of
9640 * fpu_active (which may have changed).
9641 * Note that vmx_set_cr0 refers to efer set above.
9643 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
9645 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9646 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9647 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9649 update_exception_bitmap(vcpu
);
9650 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
9651 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9654 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9655 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9657 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
9658 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
9660 nested_ept_uninit_mmu_context(vcpu
);
9662 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
9663 kvm_mmu_reset_context(vcpu
);
9666 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
9670 * Trivially support vpid by letting L2s share their parent
9671 * L1's vpid. TODO: move to a more elaborate solution, giving
9672 * each L2 its own vpid and exposing the vpid feature to L1.
9674 vmx_flush_tlb(vcpu
);
9678 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
9679 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
9680 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
9681 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
9682 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
9684 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9685 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
9686 vmcs_write64(GUEST_BNDCFGS
, 0);
9688 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
9689 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
9690 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
9692 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
9693 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
9694 vmcs12
->host_ia32_perf_global_ctrl
);
9696 /* Set L1 segment info according to Intel SDM
9697 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9698 seg
= (struct kvm_segment
) {
9700 .limit
= 0xFFFFFFFF,
9701 .selector
= vmcs12
->host_cs_selector
,
9707 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
9711 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
9712 seg
= (struct kvm_segment
) {
9714 .limit
= 0xFFFFFFFF,
9721 seg
.selector
= vmcs12
->host_ds_selector
;
9722 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
9723 seg
.selector
= vmcs12
->host_es_selector
;
9724 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
9725 seg
.selector
= vmcs12
->host_ss_selector
;
9726 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
9727 seg
.selector
= vmcs12
->host_fs_selector
;
9728 seg
.base
= vmcs12
->host_fs_base
;
9729 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
9730 seg
.selector
= vmcs12
->host_gs_selector
;
9731 seg
.base
= vmcs12
->host_gs_base
;
9732 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
9733 seg
= (struct kvm_segment
) {
9734 .base
= vmcs12
->host_tr_base
,
9736 .selector
= vmcs12
->host_tr_selector
,
9740 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
9742 kvm_set_dr(vcpu
, 7, 0x400);
9743 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
9745 if (cpu_has_vmx_msr_bitmap())
9746 vmx_set_msr_bitmap(vcpu
);
9748 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
9749 vmcs12
->vm_exit_msr_load_count
))
9750 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
9754 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9755 * and modify vmcs12 to make it see what it would expect to see there if
9756 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9758 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
9760 unsigned long exit_qualification
)
9762 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9763 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9765 /* trying to cancel vmlaunch/vmresume is a bug */
9766 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
9768 leave_guest_mode(vcpu
);
9769 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
9770 exit_qualification
);
9772 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
9773 vmcs12
->vm_exit_msr_store_count
))
9774 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
9776 vmx_load_vmcs01(vcpu
);
9778 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
9779 && nested_exit_intr_ack_set(vcpu
)) {
9780 int irq
= kvm_cpu_get_interrupt(vcpu
);
9782 vmcs12
->vm_exit_intr_info
= irq
|
9783 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
9786 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
9787 vmcs12
->exit_qualification
,
9788 vmcs12
->idt_vectoring_info_field
,
9789 vmcs12
->vm_exit_intr_info
,
9790 vmcs12
->vm_exit_intr_error_code
,
9793 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
9794 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
9795 vmx_segment_cache_clear(vmx
);
9797 /* if no vmcs02 cache requested, remove the one we used */
9798 if (VMCS02_POOL_SIZE
== 0)
9799 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
9801 load_vmcs12_host_state(vcpu
, vmcs12
);
9803 /* Update TSC_OFFSET if TSC was changed while L2 ran */
9804 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9806 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9809 /* Unpin physical memory we referred to in vmcs02 */
9810 if (vmx
->nested
.apic_access_page
) {
9811 nested_release_page(vmx
->nested
.apic_access_page
);
9812 vmx
->nested
.apic_access_page
= NULL
;
9814 if (vmx
->nested
.virtual_apic_page
) {
9815 nested_release_page(vmx
->nested
.virtual_apic_page
);
9816 vmx
->nested
.virtual_apic_page
= NULL
;
9820 * We are now running in L2, mmu_notifier will force to reload the
9821 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9823 kvm_vcpu_reload_apic_access_page(vcpu
);
9826 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9827 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9828 * success or failure flag accordingly.
9830 if (unlikely(vmx
->fail
)) {
9832 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
9834 nested_vmx_succeed(vcpu
);
9835 if (enable_shadow_vmcs
)
9836 vmx
->nested
.sync_shadow_vmcs
= true;
9838 /* in case we halted in L2 */
9839 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
9843 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9845 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
9847 if (is_guest_mode(vcpu
))
9848 nested_vmx_vmexit(vcpu
, -1, 0, 0);
9849 free_nested(to_vmx(vcpu
));
9853 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9854 * 23.7 "VM-entry failures during or after loading guest state" (this also
9855 * lists the acceptable exit-reason and exit-qualification parameters).
9856 * It should only be called before L2 actually succeeded to run, and when
9857 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9859 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
9860 struct vmcs12
*vmcs12
,
9861 u32 reason
, unsigned long qualification
)
9863 load_vmcs12_host_state(vcpu
, vmcs12
);
9864 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
9865 vmcs12
->exit_qualification
= qualification
;
9866 nested_vmx_succeed(vcpu
);
9867 if (enable_shadow_vmcs
)
9868 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
9871 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
9872 struct x86_instruction_info
*info
,
9873 enum x86_intercept_stage stage
)
9875 return X86EMUL_CONTINUE
;
9878 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
9881 shrink_ple_window(vcpu
);
9884 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
9885 struct kvm_memory_slot
*slot
)
9887 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
9888 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
9891 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
9892 struct kvm_memory_slot
*slot
)
9894 kvm_mmu_slot_set_dirty(kvm
, slot
);
9897 static void vmx_flush_log_dirty(struct kvm
*kvm
)
9899 kvm_flush_pml_buffers(kvm
);
9902 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
9903 struct kvm_memory_slot
*memslot
,
9904 gfn_t offset
, unsigned long mask
)
9906 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
9909 static struct kvm_x86_ops vmx_x86_ops
= {
9910 .cpu_has_kvm_support
= cpu_has_kvm_support
,
9911 .disabled_by_bios
= vmx_disabled_by_bios
,
9912 .hardware_setup
= hardware_setup
,
9913 .hardware_unsetup
= hardware_unsetup
,
9914 .check_processor_compatibility
= vmx_check_processor_compat
,
9915 .hardware_enable
= hardware_enable
,
9916 .hardware_disable
= hardware_disable
,
9917 .cpu_has_accelerated_tpr
= report_flexpriority
,
9919 .vcpu_create
= vmx_create_vcpu
,
9920 .vcpu_free
= vmx_free_vcpu
,
9921 .vcpu_reset
= vmx_vcpu_reset
,
9923 .prepare_guest_switch
= vmx_save_host_state
,
9924 .vcpu_load
= vmx_vcpu_load
,
9925 .vcpu_put
= vmx_vcpu_put
,
9927 .update_db_bp_intercept
= update_exception_bitmap
,
9928 .get_msr
= vmx_get_msr
,
9929 .set_msr
= vmx_set_msr
,
9930 .get_segment_base
= vmx_get_segment_base
,
9931 .get_segment
= vmx_get_segment
,
9932 .set_segment
= vmx_set_segment
,
9933 .get_cpl
= vmx_get_cpl
,
9934 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
9935 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
9936 .decache_cr3
= vmx_decache_cr3
,
9937 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
9938 .set_cr0
= vmx_set_cr0
,
9939 .set_cr3
= vmx_set_cr3
,
9940 .set_cr4
= vmx_set_cr4
,
9941 .set_efer
= vmx_set_efer
,
9942 .get_idt
= vmx_get_idt
,
9943 .set_idt
= vmx_set_idt
,
9944 .get_gdt
= vmx_get_gdt
,
9945 .set_gdt
= vmx_set_gdt
,
9946 .get_dr6
= vmx_get_dr6
,
9947 .set_dr6
= vmx_set_dr6
,
9948 .set_dr7
= vmx_set_dr7
,
9949 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
9950 .cache_reg
= vmx_cache_reg
,
9951 .get_rflags
= vmx_get_rflags
,
9952 .set_rflags
= vmx_set_rflags
,
9953 .fpu_deactivate
= vmx_fpu_deactivate
,
9955 .tlb_flush
= vmx_flush_tlb
,
9957 .run
= vmx_vcpu_run
,
9958 .handle_exit
= vmx_handle_exit
,
9959 .skip_emulated_instruction
= skip_emulated_instruction
,
9960 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
9961 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
9962 .patch_hypercall
= vmx_patch_hypercall
,
9963 .set_irq
= vmx_inject_irq
,
9964 .set_nmi
= vmx_inject_nmi
,
9965 .queue_exception
= vmx_queue_exception
,
9966 .cancel_injection
= vmx_cancel_injection
,
9967 .interrupt_allowed
= vmx_interrupt_allowed
,
9968 .nmi_allowed
= vmx_nmi_allowed
,
9969 .get_nmi_mask
= vmx_get_nmi_mask
,
9970 .set_nmi_mask
= vmx_set_nmi_mask
,
9971 .enable_nmi_window
= enable_nmi_window
,
9972 .enable_irq_window
= enable_irq_window
,
9973 .update_cr8_intercept
= update_cr8_intercept
,
9974 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
9975 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
9976 .vm_has_apicv
= vmx_vm_has_apicv
,
9977 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
9978 .hwapic_irr_update
= vmx_hwapic_irr_update
,
9979 .hwapic_isr_update
= vmx_hwapic_isr_update
,
9980 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
9981 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
9983 .set_tss_addr
= vmx_set_tss_addr
,
9984 .get_tdp_level
= get_ept_level
,
9985 .get_mt_mask
= vmx_get_mt_mask
,
9987 .get_exit_info
= vmx_get_exit_info
,
9989 .get_lpage_level
= vmx_get_lpage_level
,
9991 .cpuid_update
= vmx_cpuid_update
,
9993 .rdtscp_supported
= vmx_rdtscp_supported
,
9994 .invpcid_supported
= vmx_invpcid_supported
,
9996 .set_supported_cpuid
= vmx_set_supported_cpuid
,
9998 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
10000 .set_tsc_khz
= vmx_set_tsc_khz
,
10001 .read_tsc_offset
= vmx_read_tsc_offset
,
10002 .write_tsc_offset
= vmx_write_tsc_offset
,
10003 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
10004 .compute_tsc_offset
= vmx_compute_tsc_offset
,
10005 .read_l1_tsc
= vmx_read_l1_tsc
,
10007 .set_tdp_cr3
= vmx_set_cr3
,
10009 .check_intercept
= vmx_check_intercept
,
10010 .handle_external_intr
= vmx_handle_external_intr
,
10011 .mpx_supported
= vmx_mpx_supported
,
10012 .xsaves_supported
= vmx_xsaves_supported
,
10014 .check_nested_events
= vmx_check_nested_events
,
10016 .sched_in
= vmx_sched_in
,
10018 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
10019 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
10020 .flush_log_dirty
= vmx_flush_log_dirty
,
10021 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
10024 static int __init
vmx_init(void)
10026 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
10027 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
10031 #ifdef CONFIG_KEXEC
10032 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
10033 crash_vmclear_local_loaded_vmcss
);
10039 static void __exit
vmx_exit(void)
10041 #ifdef CONFIG_KEXEC
10042 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
10049 module_init(vmx_init
)
10050 module_exit(vmx_exit
)