2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
53 #include <asm/nospec-branch.h>
58 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 #define __ex_clear(x, reg) \
60 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
62 MODULE_AUTHOR("Qumranet");
63 MODULE_LICENSE("GPL");
65 static const struct x86_cpu_id vmx_cpu_id
[] = {
66 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
69 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
71 static bool __read_mostly enable_vpid
= 1;
72 module_param_named(vpid
, enable_vpid
, bool, 0444);
74 static bool __read_mostly enable_vnmi
= 1;
75 module_param_named(vnmi
, enable_vnmi
, bool, S_IRUGO
);
77 static bool __read_mostly flexpriority_enabled
= 1;
78 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
80 static bool __read_mostly enable_ept
= 1;
81 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
83 static bool __read_mostly enable_unrestricted_guest
= 1;
84 module_param_named(unrestricted_guest
,
85 enable_unrestricted_guest
, bool, S_IRUGO
);
87 static bool __read_mostly enable_ept_ad_bits
= 1;
88 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
90 static bool __read_mostly emulate_invalid_guest_state
= true;
91 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
93 static bool __read_mostly fasteoi
= 1;
94 module_param(fasteoi
, bool, S_IRUGO
);
96 static bool __read_mostly enable_apicv
= 1;
97 module_param(enable_apicv
, bool, S_IRUGO
);
99 static bool __read_mostly enable_shadow_vmcs
= 1;
100 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested
= 0;
107 module_param(nested
, bool, S_IRUGO
);
109 static u64 __read_mostly host_xss
;
111 static bool __read_mostly enable_pml
= 1;
112 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
114 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
116 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
117 static int __read_mostly cpu_preemption_timer_multi
;
118 static bool __read_mostly enable_preemption_timer
= 1;
120 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
123 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
124 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
125 #define KVM_VM_CR0_ALWAYS_ON \
126 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
127 #define KVM_CR4_GUEST_OWNED_BITS \
128 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
129 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
131 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
132 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
134 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
136 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
139 * Hyper-V requires all of these, so mark them as supported even though
140 * they are just treated the same as all-context.
142 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
143 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
144 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
145 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
146 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
149 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
150 * ple_gap: upper bound on the amount of time between two successive
151 * executions of PAUSE in a loop. Also indicate if ple enabled.
152 * According to test, this time is usually smaller than 128 cycles.
153 * ple_window: upper bound on the amount of time a guest is allowed to execute
154 * in a PAUSE loop. Tests indicate that most spinlocks are held for
155 * less than 2^12 cycles
156 * Time is measured based on a counter that runs at the same rate as the TSC,
157 * refer SDM volume 3b section 21.6.13 & 22.1.3.
159 #define KVM_VMX_DEFAULT_PLE_GAP 128
160 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
161 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
162 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
163 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
164 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
166 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
167 module_param(ple_gap
, int, S_IRUGO
);
169 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
170 module_param(ple_window
, int, S_IRUGO
);
172 /* Default doubles per-vcpu window every exit. */
173 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
174 module_param(ple_window_grow
, int, S_IRUGO
);
176 /* Default resets per-vcpu window every exit to ple_window. */
177 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
178 module_param(ple_window_shrink
, int, S_IRUGO
);
180 /* Default is to compute the maximum so we can never overflow. */
181 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
182 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
183 module_param(ple_window_max
, int, S_IRUGO
);
185 extern const ulong vmx_return
;
187 #define NR_AUTOLOAD_MSRS 8
196 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
197 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
198 * loaded on this CPU (so we can clear them if the CPU goes down).
202 struct vmcs
*shadow_vmcs
;
205 bool nmi_known_unmasked
;
206 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
207 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
208 /* Support for vnmi-less CPUs */
209 int soft_vnmi_blocked
;
211 s64 vnmi_blocked_time
;
212 struct list_head loaded_vmcss_on_cpu_link
;
215 struct shared_msr_entry
{
222 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
223 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
224 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
225 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
226 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
227 * More than one of these structures may exist, if L1 runs multiple L2 guests.
228 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
229 * underlying hardware which will be used to run L2.
230 * This structure is packed to ensure that its layout is identical across
231 * machines (necessary for live migration).
232 * If there are changes in this struct, VMCS12_REVISION must be changed.
234 typedef u64 natural_width
;
235 struct __packed vmcs12
{
236 /* According to the Intel spec, a VMCS region must start with the
237 * following two fields. Then follow implementation-specific data.
242 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
243 u32 padding
[7]; /* room for future expansion */
248 u64 vm_exit_msr_store_addr
;
249 u64 vm_exit_msr_load_addr
;
250 u64 vm_entry_msr_load_addr
;
252 u64 virtual_apic_page_addr
;
253 u64 apic_access_addr
;
254 u64 posted_intr_desc_addr
;
255 u64 vm_function_control
;
257 u64 eoi_exit_bitmap0
;
258 u64 eoi_exit_bitmap1
;
259 u64 eoi_exit_bitmap2
;
260 u64 eoi_exit_bitmap3
;
261 u64 eptp_list_address
;
263 u64 guest_physical_address
;
264 u64 vmcs_link_pointer
;
266 u64 guest_ia32_debugctl
;
269 u64 guest_ia32_perf_global_ctrl
;
277 u64 host_ia32_perf_global_ctrl
;
278 u64 padding64
[8]; /* room for future expansion */
280 * To allow migration of L1 (complete with its L2 guests) between
281 * machines of different natural widths (32 or 64 bit), we cannot have
282 * unsigned long fields with no explict size. We use u64 (aliased
283 * natural_width) instead. Luckily, x86 is little-endian.
285 natural_width cr0_guest_host_mask
;
286 natural_width cr4_guest_host_mask
;
287 natural_width cr0_read_shadow
;
288 natural_width cr4_read_shadow
;
289 natural_width cr3_target_value0
;
290 natural_width cr3_target_value1
;
291 natural_width cr3_target_value2
;
292 natural_width cr3_target_value3
;
293 natural_width exit_qualification
;
294 natural_width guest_linear_address
;
295 natural_width guest_cr0
;
296 natural_width guest_cr3
;
297 natural_width guest_cr4
;
298 natural_width guest_es_base
;
299 natural_width guest_cs_base
;
300 natural_width guest_ss_base
;
301 natural_width guest_ds_base
;
302 natural_width guest_fs_base
;
303 natural_width guest_gs_base
;
304 natural_width guest_ldtr_base
;
305 natural_width guest_tr_base
;
306 natural_width guest_gdtr_base
;
307 natural_width guest_idtr_base
;
308 natural_width guest_dr7
;
309 natural_width guest_rsp
;
310 natural_width guest_rip
;
311 natural_width guest_rflags
;
312 natural_width guest_pending_dbg_exceptions
;
313 natural_width guest_sysenter_esp
;
314 natural_width guest_sysenter_eip
;
315 natural_width host_cr0
;
316 natural_width host_cr3
;
317 natural_width host_cr4
;
318 natural_width host_fs_base
;
319 natural_width host_gs_base
;
320 natural_width host_tr_base
;
321 natural_width host_gdtr_base
;
322 natural_width host_idtr_base
;
323 natural_width host_ia32_sysenter_esp
;
324 natural_width host_ia32_sysenter_eip
;
325 natural_width host_rsp
;
326 natural_width host_rip
;
327 natural_width paddingl
[8]; /* room for future expansion */
328 u32 pin_based_vm_exec_control
;
329 u32 cpu_based_vm_exec_control
;
330 u32 exception_bitmap
;
331 u32 page_fault_error_code_mask
;
332 u32 page_fault_error_code_match
;
333 u32 cr3_target_count
;
334 u32 vm_exit_controls
;
335 u32 vm_exit_msr_store_count
;
336 u32 vm_exit_msr_load_count
;
337 u32 vm_entry_controls
;
338 u32 vm_entry_msr_load_count
;
339 u32 vm_entry_intr_info_field
;
340 u32 vm_entry_exception_error_code
;
341 u32 vm_entry_instruction_len
;
343 u32 secondary_vm_exec_control
;
344 u32 vm_instruction_error
;
346 u32 vm_exit_intr_info
;
347 u32 vm_exit_intr_error_code
;
348 u32 idt_vectoring_info_field
;
349 u32 idt_vectoring_error_code
;
350 u32 vm_exit_instruction_len
;
351 u32 vmx_instruction_info
;
358 u32 guest_ldtr_limit
;
360 u32 guest_gdtr_limit
;
361 u32 guest_idtr_limit
;
362 u32 guest_es_ar_bytes
;
363 u32 guest_cs_ar_bytes
;
364 u32 guest_ss_ar_bytes
;
365 u32 guest_ds_ar_bytes
;
366 u32 guest_fs_ar_bytes
;
367 u32 guest_gs_ar_bytes
;
368 u32 guest_ldtr_ar_bytes
;
369 u32 guest_tr_ar_bytes
;
370 u32 guest_interruptibility_info
;
371 u32 guest_activity_state
;
372 u32 guest_sysenter_cs
;
373 u32 host_ia32_sysenter_cs
;
374 u32 vmx_preemption_timer_value
;
375 u32 padding32
[7]; /* room for future expansion */
376 u16 virtual_processor_id
;
378 u16 guest_es_selector
;
379 u16 guest_cs_selector
;
380 u16 guest_ss_selector
;
381 u16 guest_ds_selector
;
382 u16 guest_fs_selector
;
383 u16 guest_gs_selector
;
384 u16 guest_ldtr_selector
;
385 u16 guest_tr_selector
;
386 u16 guest_intr_status
;
388 u16 host_es_selector
;
389 u16 host_cs_selector
;
390 u16 host_ss_selector
;
391 u16 host_ds_selector
;
392 u16 host_fs_selector
;
393 u16 host_gs_selector
;
394 u16 host_tr_selector
;
398 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
399 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
400 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
402 #define VMCS12_REVISION 0x11e57ed0
405 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
406 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
407 * current implementation, 4K are reserved to avoid future complications.
409 #define VMCS12_SIZE 0x1000
412 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
413 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
416 /* Has the level1 guest done vmxon? */
421 /* The guest-physical address of the current VMCS L1 keeps for L2 */
424 * Cache of the guest's VMCS, existing outside of guest memory.
425 * Loaded from guest memory during VMPTRLD. Flushed to guest
426 * memory during VMCLEAR and VMPTRLD.
428 struct vmcs12
*cached_vmcs12
;
430 * Indicates if the shadow vmcs must be updated with the
431 * data hold by vmcs12
433 bool sync_shadow_vmcs
;
435 bool change_vmcs01_virtual_x2apic_mode
;
436 /* L2 must run next, and mustn't decide to exit to L1. */
437 bool nested_run_pending
;
439 struct loaded_vmcs vmcs02
;
442 * Guest pages referred to in the vmcs02 with host-physical
443 * pointers, so we must keep them pinned while L2 runs.
445 struct page
*apic_access_page
;
446 struct page
*virtual_apic_page
;
447 struct page
*pi_desc_page
;
448 struct pi_desc
*pi_desc
;
452 unsigned long *msr_bitmap
;
454 struct hrtimer preemption_timer
;
455 bool preemption_timer_expired
;
457 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
464 * We only store the "true" versions of the VMX capability MSRs. We
465 * generate the "non-true" versions by setting the must-be-1 bits
466 * according to the SDM.
468 u32 nested_vmx_procbased_ctls_low
;
469 u32 nested_vmx_procbased_ctls_high
;
470 u32 nested_vmx_secondary_ctls_low
;
471 u32 nested_vmx_secondary_ctls_high
;
472 u32 nested_vmx_pinbased_ctls_low
;
473 u32 nested_vmx_pinbased_ctls_high
;
474 u32 nested_vmx_exit_ctls_low
;
475 u32 nested_vmx_exit_ctls_high
;
476 u32 nested_vmx_entry_ctls_low
;
477 u32 nested_vmx_entry_ctls_high
;
478 u32 nested_vmx_misc_low
;
479 u32 nested_vmx_misc_high
;
480 u32 nested_vmx_ept_caps
;
481 u32 nested_vmx_vpid_caps
;
482 u64 nested_vmx_basic
;
483 u64 nested_vmx_cr0_fixed0
;
484 u64 nested_vmx_cr0_fixed1
;
485 u64 nested_vmx_cr4_fixed0
;
486 u64 nested_vmx_cr4_fixed1
;
487 u64 nested_vmx_vmcs_enum
;
488 u64 nested_vmx_vmfunc_controls
;
490 /* SMM related state */
492 /* in VMX operation on SMM entry? */
494 /* in guest mode on SMM entry? */
499 #define POSTED_INTR_ON 0
500 #define POSTED_INTR_SN 1
502 /* Posted-Interrupt Descriptor */
504 u32 pir
[8]; /* Posted interrupt requested */
507 /* bit 256 - Outstanding Notification */
509 /* bit 257 - Suppress Notification */
511 /* bit 271:258 - Reserved */
513 /* bit 279:272 - Notification Vector */
515 /* bit 287:280 - Reserved */
517 /* bit 319:288 - Notification Destination */
525 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
527 return test_and_set_bit(POSTED_INTR_ON
,
528 (unsigned long *)&pi_desc
->control
);
531 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
533 return test_and_clear_bit(POSTED_INTR_ON
,
534 (unsigned long *)&pi_desc
->control
);
537 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
539 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
542 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
544 return clear_bit(POSTED_INTR_SN
,
545 (unsigned long *)&pi_desc
->control
);
548 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
550 return set_bit(POSTED_INTR_SN
,
551 (unsigned long *)&pi_desc
->control
);
554 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
556 clear_bit(POSTED_INTR_ON
,
557 (unsigned long *)&pi_desc
->control
);
560 static inline int pi_test_on(struct pi_desc
*pi_desc
)
562 return test_bit(POSTED_INTR_ON
,
563 (unsigned long *)&pi_desc
->control
);
566 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
568 return test_bit(POSTED_INTR_SN
,
569 (unsigned long *)&pi_desc
->control
);
573 struct kvm_vcpu vcpu
;
574 unsigned long host_rsp
;
577 u32 idt_vectoring_info
;
579 struct shared_msr_entry
*guest_msrs
;
582 unsigned long host_idt_base
;
584 u64 msr_host_kernel_gs_base
;
585 u64 msr_guest_kernel_gs_base
;
587 u32 vm_entry_controls_shadow
;
588 u32 vm_exit_controls_shadow
;
589 u32 secondary_exec_control
;
592 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
593 * non-nested (L1) guest, it always points to vmcs01. For a nested
594 * guest (L2), it points to a different VMCS.
596 struct loaded_vmcs vmcs01
;
597 struct loaded_vmcs
*loaded_vmcs
;
598 bool __launched
; /* temporary, used in vmx_vcpu_run */
599 struct msr_autoload
{
601 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
602 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
606 u16 fs_sel
, gs_sel
, ldt_sel
;
610 int gs_ldt_reload_needed
;
611 int fs_reload_needed
;
612 u64 msr_host_bndcfgs
;
617 struct kvm_segment segs
[8];
620 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
621 struct kvm_save_segment
{
629 bool emulation_required
;
633 /* Posted interrupt descriptor */
634 struct pi_desc pi_desc
;
636 /* Support for a guest hypervisor (nested VMX) */
637 struct nested_vmx nested
;
639 /* Dynamic PLE window. */
641 bool ple_window_dirty
;
643 /* Support for PML */
644 #define PML_ENTITY_NUM 512
647 /* apic deadline value in host tsc */
650 u64 current_tsc_ratio
;
655 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
656 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
657 * in msr_ia32_feature_control_valid_bits.
659 u64 msr_ia32_feature_control
;
660 u64 msr_ia32_feature_control_valid_bits
;
663 enum segment_cache_field
{
672 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
674 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
677 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
679 return &(to_vmx(vcpu
)->pi_desc
);
682 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
683 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
684 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
685 [number##_HIGH] = VMCS12_OFFSET(name)+4
688 static unsigned long shadow_read_only_fields
[] = {
690 * We do NOT shadow fields that are modified when L0
691 * traps and emulates any vmx instruction (e.g. VMPTRLD,
692 * VMXON...) executed by L1.
693 * For example, VM_INSTRUCTION_ERROR is read
694 * by L1 if a vmx instruction fails (part of the error path).
695 * Note the code assumes this logic. If for some reason
696 * we start shadowing these fields then we need to
697 * force a shadow sync when L0 emulates vmx instructions
698 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
699 * by nested_vmx_failValid)
703 VM_EXIT_INSTRUCTION_LEN
,
704 IDT_VECTORING_INFO_FIELD
,
705 IDT_VECTORING_ERROR_CODE
,
706 VM_EXIT_INTR_ERROR_CODE
,
708 GUEST_LINEAR_ADDRESS
,
709 GUEST_PHYSICAL_ADDRESS
711 static int max_shadow_read_only_fields
=
712 ARRAY_SIZE(shadow_read_only_fields
);
714 static unsigned long shadow_read_write_fields
[] = {
721 GUEST_INTERRUPTIBILITY_INFO
,
734 CPU_BASED_VM_EXEC_CONTROL
,
735 VM_ENTRY_EXCEPTION_ERROR_CODE
,
736 VM_ENTRY_INTR_INFO_FIELD
,
737 VM_ENTRY_INSTRUCTION_LEN
,
738 VM_ENTRY_EXCEPTION_ERROR_CODE
,
744 static int max_shadow_read_write_fields
=
745 ARRAY_SIZE(shadow_read_write_fields
);
747 static const unsigned short vmcs_field_to_offset_table
[] = {
748 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
749 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
750 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
751 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
752 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
753 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
754 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
755 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
756 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
757 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
758 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
759 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
760 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
761 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
762 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
763 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
764 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
765 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
766 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
767 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
768 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
769 FIELD64(MSR_BITMAP
, msr_bitmap
),
770 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
771 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
772 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
773 FIELD64(TSC_OFFSET
, tsc_offset
),
774 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
775 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
776 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
777 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
778 FIELD64(EPT_POINTER
, ept_pointer
),
779 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
780 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
781 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
782 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
783 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
784 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
785 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
786 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
787 FIELD64(PML_ADDRESS
, pml_address
),
788 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
789 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
790 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
791 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
792 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
793 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
794 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
795 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
796 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
797 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
798 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
799 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
800 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
801 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
802 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
803 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
804 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
805 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
806 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
807 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
808 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
809 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
810 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
811 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
812 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
813 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
814 FIELD(TPR_THRESHOLD
, tpr_threshold
),
815 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
816 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
817 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
818 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
819 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
820 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
821 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
822 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
823 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
824 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
825 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
826 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
827 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
828 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
829 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
830 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
831 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
832 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
833 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
834 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
835 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
836 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
837 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
838 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
839 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
840 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
841 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
842 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
843 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
844 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
845 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
846 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
847 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
848 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
849 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
850 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
851 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
852 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
853 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
854 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
855 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
856 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
857 FIELD(GUEST_CR0
, guest_cr0
),
858 FIELD(GUEST_CR3
, guest_cr3
),
859 FIELD(GUEST_CR4
, guest_cr4
),
860 FIELD(GUEST_ES_BASE
, guest_es_base
),
861 FIELD(GUEST_CS_BASE
, guest_cs_base
),
862 FIELD(GUEST_SS_BASE
, guest_ss_base
),
863 FIELD(GUEST_DS_BASE
, guest_ds_base
),
864 FIELD(GUEST_FS_BASE
, guest_fs_base
),
865 FIELD(GUEST_GS_BASE
, guest_gs_base
),
866 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
867 FIELD(GUEST_TR_BASE
, guest_tr_base
),
868 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
869 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
870 FIELD(GUEST_DR7
, guest_dr7
),
871 FIELD(GUEST_RSP
, guest_rsp
),
872 FIELD(GUEST_RIP
, guest_rip
),
873 FIELD(GUEST_RFLAGS
, guest_rflags
),
874 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
875 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
876 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
877 FIELD(HOST_CR0
, host_cr0
),
878 FIELD(HOST_CR3
, host_cr3
),
879 FIELD(HOST_CR4
, host_cr4
),
880 FIELD(HOST_FS_BASE
, host_fs_base
),
881 FIELD(HOST_GS_BASE
, host_gs_base
),
882 FIELD(HOST_TR_BASE
, host_tr_base
),
883 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
884 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
885 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
886 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
887 FIELD(HOST_RSP
, host_rsp
),
888 FIELD(HOST_RIP
, host_rip
),
891 static inline short vmcs_field_to_offset(unsigned long field
)
893 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
895 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
))
899 * FIXME: Mitigation for CVE-2017-5753. To be replaced with a
904 if (vmcs_field_to_offset_table
[field
] == 0)
907 return vmcs_field_to_offset_table
[field
];
910 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
912 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
915 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
916 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
917 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
918 static bool vmx_xsaves_supported(void);
919 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
920 struct kvm_segment
*var
, int seg
);
921 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
922 struct kvm_segment
*var
, int seg
);
923 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
924 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
925 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
926 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
927 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
928 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
931 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
932 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
937 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
940 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
941 * can find which vCPU should be waken up.
943 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
944 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
949 VMX_MSR_BITMAP_LEGACY
,
950 VMX_MSR_BITMAP_LONGMODE
,
951 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
952 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
953 VMX_MSR_BITMAP_LEGACY_X2APIC
,
954 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
960 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
962 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
963 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
964 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
965 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
966 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
967 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
968 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
969 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
970 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
971 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
973 static bool cpu_has_load_ia32_efer
;
974 static bool cpu_has_load_perf_global_ctrl
;
976 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
977 static DEFINE_SPINLOCK(vmx_vpid_lock
);
979 static struct vmcs_config
{
984 u32 pin_based_exec_ctrl
;
985 u32 cpu_based_exec_ctrl
;
986 u32 cpu_based_2nd_exec_ctrl
;
991 static struct vmx_capability
{
996 #define VMX_SEGMENT_FIELD(seg) \
997 [VCPU_SREG_##seg] = { \
998 .selector = GUEST_##seg##_SELECTOR, \
999 .base = GUEST_##seg##_BASE, \
1000 .limit = GUEST_##seg##_LIMIT, \
1001 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1004 static const struct kvm_vmx_segment_field
{
1009 } kvm_vmx_segment_fields
[] = {
1010 VMX_SEGMENT_FIELD(CS
),
1011 VMX_SEGMENT_FIELD(DS
),
1012 VMX_SEGMENT_FIELD(ES
),
1013 VMX_SEGMENT_FIELD(FS
),
1014 VMX_SEGMENT_FIELD(GS
),
1015 VMX_SEGMENT_FIELD(SS
),
1016 VMX_SEGMENT_FIELD(TR
),
1017 VMX_SEGMENT_FIELD(LDTR
),
1020 static u64 host_efer
;
1022 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1025 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1026 * away by decrementing the array size.
1028 static const u32 vmx_msr_index
[] = {
1029 #ifdef CONFIG_X86_64
1030 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1032 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1035 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1037 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1038 INTR_INFO_VALID_MASK
)) ==
1039 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1042 static inline bool is_debug(u32 intr_info
)
1044 return is_exception_n(intr_info
, DB_VECTOR
);
1047 static inline bool is_breakpoint(u32 intr_info
)
1049 return is_exception_n(intr_info
, BP_VECTOR
);
1052 static inline bool is_page_fault(u32 intr_info
)
1054 return is_exception_n(intr_info
, PF_VECTOR
);
1057 static inline bool is_no_device(u32 intr_info
)
1059 return is_exception_n(intr_info
, NM_VECTOR
);
1062 static inline bool is_invalid_opcode(u32 intr_info
)
1064 return is_exception_n(intr_info
, UD_VECTOR
);
1067 static inline bool is_external_interrupt(u32 intr_info
)
1069 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1070 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1073 static inline bool is_machine_check(u32 intr_info
)
1075 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1076 INTR_INFO_VALID_MASK
)) ==
1077 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1080 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1085 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1090 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1092 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1095 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 return vmcs_config
.cpu_based_exec_ctrl
&
1098 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1101 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1104 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1107 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1110 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1113 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1116 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1119 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1122 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1126 * Comment's format: document - errata name - stepping - processor name.
1128 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130 static u32 vmx_preemption_cpu_tfms
[] = {
1131 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1133 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1134 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1140 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1142 * 320767.pdf - AAP86 - B1 -
1143 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1146 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1158 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 u32 eax
= cpuid_eax(0x00000001), i
;
1162 /* Clear the reserved bits */
1163 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1164 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1165 if (eax
== vmx_preemption_cpu_tfms
[i
])
1171 static inline bool cpu_has_vmx_preemption_timer(void)
1173 return vmcs_config
.pin_based_exec_ctrl
&
1174 PIN_BASED_VMX_PREEMPTION_TIMER
;
1177 static inline bool cpu_has_vmx_posted_intr(void)
1179 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1180 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1183 static inline bool cpu_has_vmx_apicv(void)
1185 return cpu_has_vmx_apic_register_virt() &&
1186 cpu_has_vmx_virtual_intr_delivery() &&
1187 cpu_has_vmx_posted_intr();
1190 static inline bool cpu_has_vmx_flexpriority(void)
1192 return cpu_has_vmx_tpr_shadow() &&
1193 cpu_has_vmx_virtualize_apic_accesses();
1196 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1201 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1206 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1211 static inline bool cpu_has_vmx_ept_4levels(void)
1213 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1216 static inline bool cpu_has_vmx_ept_mt_wb(void)
1218 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1221 static inline bool cpu_has_vmx_ept_5levels(void)
1223 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1226 static inline bool cpu_has_vmx_ept_ad_bits(void)
1228 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1231 static inline bool cpu_has_vmx_invept_context(void)
1233 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1236 static inline bool cpu_has_vmx_invept_global(void)
1238 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1241 static inline bool cpu_has_vmx_invvpid_single(void)
1243 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1246 static inline bool cpu_has_vmx_invvpid_global(void)
1248 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1251 static inline bool cpu_has_vmx_invvpid(void)
1253 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1256 static inline bool cpu_has_vmx_ept(void)
1258 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1259 SECONDARY_EXEC_ENABLE_EPT
;
1262 static inline bool cpu_has_vmx_unrestricted_guest(void)
1264 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1265 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1268 static inline bool cpu_has_vmx_ple(void)
1270 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1271 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1274 static inline bool cpu_has_vmx_basic_inout(void)
1276 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1279 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1281 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1284 static inline bool cpu_has_vmx_vpid(void)
1286 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1287 SECONDARY_EXEC_ENABLE_VPID
;
1290 static inline bool cpu_has_vmx_rdtscp(void)
1292 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1293 SECONDARY_EXEC_RDTSCP
;
1296 static inline bool cpu_has_vmx_invpcid(void)
1298 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1299 SECONDARY_EXEC_ENABLE_INVPCID
;
1302 static inline bool cpu_has_virtual_nmis(void)
1304 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1307 static inline bool cpu_has_vmx_wbinvd_exit(void)
1309 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1310 SECONDARY_EXEC_WBINVD_EXITING
;
1313 static inline bool cpu_has_vmx_shadow_vmcs(void)
1316 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1317 /* check if the cpu supports writing r/o exit information fields */
1318 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1321 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1322 SECONDARY_EXEC_SHADOW_VMCS
;
1325 static inline bool cpu_has_vmx_pml(void)
1327 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1330 static inline bool cpu_has_vmx_tsc_scaling(void)
1332 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1333 SECONDARY_EXEC_TSC_SCALING
;
1336 static inline bool cpu_has_vmx_vmfunc(void)
1338 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1339 SECONDARY_EXEC_ENABLE_VMFUNC
;
1342 static inline bool report_flexpriority(void)
1344 return flexpriority_enabled
;
1347 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1349 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1352 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1354 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1357 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1359 return (vmcs12
->cpu_based_vm_exec_control
&
1360 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1361 (vmcs12
->secondary_vm_exec_control
& bit
);
1364 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1366 return vmcs12
->pin_based_vm_exec_control
&
1367 PIN_BASED_VMX_PREEMPTION_TIMER
;
1370 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1372 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1375 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1377 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
1380 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1382 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1385 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1387 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1390 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1392 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1395 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1397 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1400 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1402 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1405 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1407 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1410 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1412 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1415 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1417 return nested_cpu_has_vmfunc(vmcs12
) &&
1418 (vmcs12
->vm_function_control
&
1419 VMX_VMFUNC_EPTP_SWITCHING
);
1422 static inline bool is_nmi(u32 intr_info
)
1424 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1425 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1428 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1430 unsigned long exit_qualification
);
1431 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1432 struct vmcs12
*vmcs12
,
1433 u32 reason
, unsigned long qualification
);
1435 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1439 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1440 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1445 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1451 } operand
= { vpid
, 0, gva
};
1453 asm volatile (__ex(ASM_VMX_INVVPID
)
1454 /* CF==1 or ZF==1 --> rc = -1 */
1455 "; ja 1f ; ud2 ; 1:"
1456 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1459 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1463 } operand
= {eptp
, gpa
};
1465 asm volatile (__ex(ASM_VMX_INVEPT
)
1466 /* CF==1 or ZF==1 --> rc = -1 */
1467 "; ja 1f ; ud2 ; 1:\n"
1468 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1471 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1475 i
= __find_msr_index(vmx
, msr
);
1477 return &vmx
->guest_msrs
[i
];
1481 static void vmcs_clear(struct vmcs
*vmcs
)
1483 u64 phys_addr
= __pa(vmcs
);
1486 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1487 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1490 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1494 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1496 vmcs_clear(loaded_vmcs
->vmcs
);
1497 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1498 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1499 loaded_vmcs
->cpu
= -1;
1500 loaded_vmcs
->launched
= 0;
1503 static void vmcs_load(struct vmcs
*vmcs
)
1505 u64 phys_addr
= __pa(vmcs
);
1508 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1509 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1512 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1516 #ifdef CONFIG_KEXEC_CORE
1518 * This bitmap is used to indicate whether the vmclear
1519 * operation is enabled on all cpus. All disabled by
1522 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1524 static inline void crash_enable_local_vmclear(int cpu
)
1526 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1529 static inline void crash_disable_local_vmclear(int cpu
)
1531 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1534 static inline int crash_local_vmclear_enabled(int cpu
)
1536 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1539 static void crash_vmclear_local_loaded_vmcss(void)
1541 int cpu
= raw_smp_processor_id();
1542 struct loaded_vmcs
*v
;
1544 if (!crash_local_vmclear_enabled(cpu
))
1547 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1548 loaded_vmcss_on_cpu_link
)
1549 vmcs_clear(v
->vmcs
);
1552 static inline void crash_enable_local_vmclear(int cpu
) { }
1553 static inline void crash_disable_local_vmclear(int cpu
) { }
1554 #endif /* CONFIG_KEXEC_CORE */
1556 static void __loaded_vmcs_clear(void *arg
)
1558 struct loaded_vmcs
*loaded_vmcs
= arg
;
1559 int cpu
= raw_smp_processor_id();
1561 if (loaded_vmcs
->cpu
!= cpu
)
1562 return; /* vcpu migration can race with cpu offline */
1563 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1564 per_cpu(current_vmcs
, cpu
) = NULL
;
1565 crash_disable_local_vmclear(cpu
);
1566 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1569 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1570 * is before setting loaded_vmcs->vcpu to -1 which is done in
1571 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1572 * then adds the vmcs into percpu list before it is deleted.
1576 loaded_vmcs_init(loaded_vmcs
);
1577 crash_enable_local_vmclear(cpu
);
1580 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1582 int cpu
= loaded_vmcs
->cpu
;
1585 smp_call_function_single(cpu
,
1586 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1589 static inline void vpid_sync_vcpu_single(int vpid
)
1594 if (cpu_has_vmx_invvpid_single())
1595 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1598 static inline void vpid_sync_vcpu_global(void)
1600 if (cpu_has_vmx_invvpid_global())
1601 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1604 static inline void vpid_sync_context(int vpid
)
1606 if (cpu_has_vmx_invvpid_single())
1607 vpid_sync_vcpu_single(vpid
);
1609 vpid_sync_vcpu_global();
1612 static inline void ept_sync_global(void)
1614 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1617 static inline void ept_sync_context(u64 eptp
)
1619 if (cpu_has_vmx_invept_context())
1620 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1625 static __always_inline
void vmcs_check16(unsigned long field
)
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1628 "16-bit accessor invalid for 64-bit field");
1629 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1630 "16-bit accessor invalid for 64-bit high field");
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1632 "16-bit accessor invalid for 32-bit high field");
1633 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1634 "16-bit accessor invalid for natural width field");
1637 static __always_inline
void vmcs_check32(unsigned long field
)
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1640 "32-bit accessor invalid for 16-bit field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1642 "32-bit accessor invalid for natural width field");
1645 static __always_inline
void vmcs_check64(unsigned long field
)
1647 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1648 "64-bit accessor invalid for 16-bit field");
1649 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1650 "64-bit accessor invalid for 64-bit high field");
1651 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1652 "64-bit accessor invalid for 32-bit field");
1653 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1654 "64-bit accessor invalid for natural width field");
1657 static __always_inline
void vmcs_checkl(unsigned long field
)
1659 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1660 "Natural width accessor invalid for 16-bit field");
1661 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1662 "Natural width accessor invalid for 64-bit field");
1663 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1664 "Natural width accessor invalid for 64-bit high field");
1665 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1666 "Natural width accessor invalid for 32-bit field");
1669 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1671 unsigned long value
;
1673 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1674 : "=a"(value
) : "d"(field
) : "cc");
1678 static __always_inline u16
vmcs_read16(unsigned long field
)
1680 vmcs_check16(field
);
1681 return __vmcs_readl(field
);
1684 static __always_inline u32
vmcs_read32(unsigned long field
)
1686 vmcs_check32(field
);
1687 return __vmcs_readl(field
);
1690 static __always_inline u64
vmcs_read64(unsigned long field
)
1692 vmcs_check64(field
);
1693 #ifdef CONFIG_X86_64
1694 return __vmcs_readl(field
);
1696 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1700 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1703 return __vmcs_readl(field
);
1706 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1708 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1709 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1713 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1717 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1718 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1719 if (unlikely(error
))
1720 vmwrite_error(field
, value
);
1723 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1725 vmcs_check16(field
);
1726 __vmcs_writel(field
, value
);
1729 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1731 vmcs_check32(field
);
1732 __vmcs_writel(field
, value
);
1735 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1737 vmcs_check64(field
);
1738 __vmcs_writel(field
, value
);
1739 #ifndef CONFIG_X86_64
1741 __vmcs_writel(field
+1, value
>> 32);
1745 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1748 __vmcs_writel(field
, value
);
1751 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1753 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1754 "vmcs_clear_bits does not support 64-bit fields");
1755 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1758 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1760 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1761 "vmcs_set_bits does not support 64-bit fields");
1762 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1765 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1767 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1770 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1772 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1773 vmx
->vm_entry_controls_shadow
= val
;
1776 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1778 if (vmx
->vm_entry_controls_shadow
!= val
)
1779 vm_entry_controls_init(vmx
, val
);
1782 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1784 return vmx
->vm_entry_controls_shadow
;
1788 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1790 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1793 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1795 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1798 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1800 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1803 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1805 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1806 vmx
->vm_exit_controls_shadow
= val
;
1809 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1811 if (vmx
->vm_exit_controls_shadow
!= val
)
1812 vm_exit_controls_init(vmx
, val
);
1815 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1817 return vmx
->vm_exit_controls_shadow
;
1821 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1823 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1826 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1828 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1831 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1833 vmx
->segment_cache
.bitmask
= 0;
1836 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1840 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1842 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1843 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1844 vmx
->segment_cache
.bitmask
= 0;
1846 ret
= vmx
->segment_cache
.bitmask
& mask
;
1847 vmx
->segment_cache
.bitmask
|= mask
;
1851 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1853 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1855 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1856 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1860 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1862 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1864 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1865 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1869 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1871 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1873 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1874 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1878 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1880 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1882 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1883 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1887 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1891 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1892 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1893 if ((vcpu
->guest_debug
&
1894 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1895 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1896 eb
|= 1u << BP_VECTOR
;
1897 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1900 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1902 /* When we are running a nested L2 guest and L1 specified for it a
1903 * certain exception bitmap, we must trap the same exceptions and pass
1904 * them to L1. When running L2, we will only handle the exceptions
1905 * specified above if L1 did not want them.
1907 if (is_guest_mode(vcpu
))
1908 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1910 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1913 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1914 unsigned long entry
, unsigned long exit
)
1916 vm_entry_controls_clearbit(vmx
, entry
);
1917 vm_exit_controls_clearbit(vmx
, exit
);
1920 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1923 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1927 if (cpu_has_load_ia32_efer
) {
1928 clear_atomic_switch_msr_special(vmx
,
1929 VM_ENTRY_LOAD_IA32_EFER
,
1930 VM_EXIT_LOAD_IA32_EFER
);
1934 case MSR_CORE_PERF_GLOBAL_CTRL
:
1935 if (cpu_has_load_perf_global_ctrl
) {
1936 clear_atomic_switch_msr_special(vmx
,
1937 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1938 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1944 for (i
= 0; i
< m
->nr
; ++i
)
1945 if (m
->guest
[i
].index
== msr
)
1951 m
->guest
[i
] = m
->guest
[m
->nr
];
1952 m
->host
[i
] = m
->host
[m
->nr
];
1953 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1954 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1957 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1958 unsigned long entry
, unsigned long exit
,
1959 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1960 u64 guest_val
, u64 host_val
)
1962 vmcs_write64(guest_val_vmcs
, guest_val
);
1963 vmcs_write64(host_val_vmcs
, host_val
);
1964 vm_entry_controls_setbit(vmx
, entry
);
1965 vm_exit_controls_setbit(vmx
, exit
);
1968 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1969 u64 guest_val
, u64 host_val
)
1972 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1976 if (cpu_has_load_ia32_efer
) {
1977 add_atomic_switch_msr_special(vmx
,
1978 VM_ENTRY_LOAD_IA32_EFER
,
1979 VM_EXIT_LOAD_IA32_EFER
,
1982 guest_val
, host_val
);
1986 case MSR_CORE_PERF_GLOBAL_CTRL
:
1987 if (cpu_has_load_perf_global_ctrl
) {
1988 add_atomic_switch_msr_special(vmx
,
1989 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1990 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1991 GUEST_IA32_PERF_GLOBAL_CTRL
,
1992 HOST_IA32_PERF_GLOBAL_CTRL
,
1993 guest_val
, host_val
);
1997 case MSR_IA32_PEBS_ENABLE
:
1998 /* PEBS needs a quiescent period after being disabled (to write
1999 * a record). Disabling PEBS through VMX MSR swapping doesn't
2000 * provide that period, so a CPU could write host's record into
2003 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
2006 for (i
= 0; i
< m
->nr
; ++i
)
2007 if (m
->guest
[i
].index
== msr
)
2010 if (i
== NR_AUTOLOAD_MSRS
) {
2011 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2012 "Can't add msr %x\n", msr
);
2014 } else if (i
== m
->nr
) {
2016 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2017 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2020 m
->guest
[i
].index
= msr
;
2021 m
->guest
[i
].value
= guest_val
;
2022 m
->host
[i
].index
= msr
;
2023 m
->host
[i
].value
= host_val
;
2026 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2028 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2029 u64 ignore_bits
= 0;
2033 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2034 * host CPUID is more efficient than testing guest CPUID
2035 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2037 if (boot_cpu_has(X86_FEATURE_SMEP
))
2038 guest_efer
|= EFER_NX
;
2039 else if (!(guest_efer
& EFER_NX
))
2040 ignore_bits
|= EFER_NX
;
2044 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2046 ignore_bits
|= EFER_SCE
;
2047 #ifdef CONFIG_X86_64
2048 ignore_bits
|= EFER_LMA
| EFER_LME
;
2049 /* SCE is meaningful only in long mode on Intel */
2050 if (guest_efer
& EFER_LMA
)
2051 ignore_bits
&= ~(u64
)EFER_SCE
;
2054 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2057 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2058 * On CPUs that support "load IA32_EFER", always switch EFER
2059 * atomically, since it's faster than switching it manually.
2061 if (cpu_has_load_ia32_efer
||
2062 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2063 if (!(guest_efer
& EFER_LMA
))
2064 guest_efer
&= ~EFER_LME
;
2065 if (guest_efer
!= host_efer
)
2066 add_atomic_switch_msr(vmx
, MSR_EFER
,
2067 guest_efer
, host_efer
);
2070 guest_efer
&= ~ignore_bits
;
2071 guest_efer
|= host_efer
& ignore_bits
;
2073 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2074 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2080 #ifdef CONFIG_X86_32
2082 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2083 * VMCS rather than the segment table. KVM uses this helper to figure
2084 * out the current bases to poke them into the VMCS before entry.
2086 static unsigned long segment_base(u16 selector
)
2088 struct desc_struct
*table
;
2091 if (!(selector
& ~SEGMENT_RPL_MASK
))
2094 table
= get_current_gdt_ro();
2096 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2097 u16 ldt_selector
= kvm_read_ldt();
2099 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2102 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2104 v
= get_desc_base(&table
[selector
>> 3]);
2109 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2111 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2114 if (vmx
->host_state
.loaded
)
2117 vmx
->host_state
.loaded
= 1;
2119 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2120 * allow segment selectors with cpl > 0 or ti == 1.
2122 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2123 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2124 savesegment(fs
, vmx
->host_state
.fs_sel
);
2125 if (!(vmx
->host_state
.fs_sel
& 7)) {
2126 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2127 vmx
->host_state
.fs_reload_needed
= 0;
2129 vmcs_write16(HOST_FS_SELECTOR
, 0);
2130 vmx
->host_state
.fs_reload_needed
= 1;
2132 savesegment(gs
, vmx
->host_state
.gs_sel
);
2133 if (!(vmx
->host_state
.gs_sel
& 7))
2134 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2136 vmcs_write16(HOST_GS_SELECTOR
, 0);
2137 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2140 #ifdef CONFIG_X86_64
2141 savesegment(ds
, vmx
->host_state
.ds_sel
);
2142 savesegment(es
, vmx
->host_state
.es_sel
);
2145 #ifdef CONFIG_X86_64
2146 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2147 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2149 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2150 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2153 #ifdef CONFIG_X86_64
2154 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2155 if (is_long_mode(&vmx
->vcpu
))
2156 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2158 if (boot_cpu_has(X86_FEATURE_MPX
))
2159 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2160 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2161 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2162 vmx
->guest_msrs
[i
].data
,
2163 vmx
->guest_msrs
[i
].mask
);
2166 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2168 if (!vmx
->host_state
.loaded
)
2171 ++vmx
->vcpu
.stat
.host_state_reload
;
2172 vmx
->host_state
.loaded
= 0;
2173 #ifdef CONFIG_X86_64
2174 if (is_long_mode(&vmx
->vcpu
))
2175 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2177 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2178 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2179 #ifdef CONFIG_X86_64
2180 load_gs_index(vmx
->host_state
.gs_sel
);
2182 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2185 if (vmx
->host_state
.fs_reload_needed
)
2186 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2187 #ifdef CONFIG_X86_64
2188 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2189 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2190 loadsegment(es
, vmx
->host_state
.es_sel
);
2193 invalidate_tss_limit();
2194 #ifdef CONFIG_X86_64
2195 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2197 if (vmx
->host_state
.msr_host_bndcfgs
)
2198 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2199 load_fixmap_gdt(raw_smp_processor_id());
2202 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2205 __vmx_load_host_state(vmx
);
2209 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2211 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2212 struct pi_desc old
, new;
2216 * In case of hot-plug or hot-unplug, we may have to undo
2217 * vmx_vcpu_pi_put even if there is no assigned device. And we
2218 * always keep PI.NDST up to date for simplicity: it makes the
2219 * code easier, and CPU migration is not a fast path.
2221 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2225 * First handle the simple case where no cmpxchg is necessary; just
2226 * allow posting non-urgent interrupts.
2228 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2229 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2230 * expects the VCPU to be on the blocked_vcpu_list that matches
2233 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2235 pi_clear_sn(pi_desc
);
2239 /* The full case. */
2241 old
.control
= new.control
= pi_desc
->control
;
2243 dest
= cpu_physical_id(cpu
);
2245 if (x2apic_enabled())
2248 new.ndst
= (dest
<< 8) & 0xFF00;
2251 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2252 new.control
) != old
.control
);
2255 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2257 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2258 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2262 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2263 * vcpu mutex is already taken.
2265 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2267 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2268 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2270 if (!already_loaded
) {
2271 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2272 local_irq_disable();
2273 crash_disable_local_vmclear(cpu
);
2276 * Read loaded_vmcs->cpu should be before fetching
2277 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2278 * See the comments in __loaded_vmcs_clear().
2282 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2283 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2284 crash_enable_local_vmclear(cpu
);
2288 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2289 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2290 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2293 if (!already_loaded
) {
2294 void *gdt
= get_current_gdt_ro();
2295 unsigned long sysenter_esp
;
2297 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2300 * Linux uses per-cpu TSS and GDT, so set these when switching
2301 * processors. See 22.2.4.
2303 vmcs_writel(HOST_TR_BASE
,
2304 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
2305 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2308 * VM exits change the host TR limit to 0x67 after a VM
2309 * exit. This is okay, since 0x67 covers everything except
2310 * the IO bitmap and have have code to handle the IO bitmap
2311 * being lost after a VM exit.
2313 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2315 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2316 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2318 vmx
->loaded_vmcs
->cpu
= cpu
;
2321 /* Setup TSC multiplier */
2322 if (kvm_has_tsc_control
&&
2323 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2324 decache_tsc_multiplier(vmx
);
2326 vmx_vcpu_pi_load(vcpu
, cpu
);
2327 vmx
->host_pkru
= read_pkru();
2330 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2332 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2334 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2335 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2336 !kvm_vcpu_apicv_active(vcpu
))
2339 /* Set SN when the vCPU is preempted */
2340 if (vcpu
->preempted
)
2344 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2346 vmx_vcpu_pi_put(vcpu
);
2348 __vmx_load_host_state(to_vmx(vcpu
));
2351 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2353 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2356 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2359 * Return the cr0 value that a nested guest would read. This is a combination
2360 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2361 * its hypervisor (cr0_read_shadow).
2363 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2365 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2366 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2368 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2370 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2371 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2374 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2376 unsigned long rflags
, save_rflags
;
2378 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2379 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2380 rflags
= vmcs_readl(GUEST_RFLAGS
);
2381 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2382 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2383 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2384 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2386 to_vmx(vcpu
)->rflags
= rflags
;
2388 return to_vmx(vcpu
)->rflags
;
2391 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2393 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2395 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2396 to_vmx(vcpu
)->rflags
= rflags
;
2397 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2398 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2399 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2401 vmcs_writel(GUEST_RFLAGS
, rflags
);
2403 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2404 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2407 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2409 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2412 if (interruptibility
& GUEST_INTR_STATE_STI
)
2413 ret
|= KVM_X86_SHADOW_INT_STI
;
2414 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2415 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2420 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2422 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2423 u32 interruptibility
= interruptibility_old
;
2425 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2427 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2428 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2429 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2430 interruptibility
|= GUEST_INTR_STATE_STI
;
2432 if ((interruptibility
!= interruptibility_old
))
2433 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2436 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2440 rip
= kvm_rip_read(vcpu
);
2441 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2442 kvm_rip_write(vcpu
, rip
);
2444 /* skipping an emulated instruction also counts */
2445 vmx_set_interrupt_shadow(vcpu
, 0);
2448 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2449 unsigned long exit_qual
)
2451 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2452 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2453 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2455 if (vcpu
->arch
.exception
.has_error_code
) {
2456 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2457 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2460 if (kvm_exception_is_soft(nr
))
2461 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2463 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2465 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2466 vmx_get_nmi_mask(vcpu
))
2467 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2469 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2473 * KVM wants to inject page-faults which it got to the guest. This function
2474 * checks whether in a nested guest, we need to inject them to L1 or L2.
2476 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
2478 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2479 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2481 if (nr
== PF_VECTOR
) {
2482 if (vcpu
->arch
.exception
.nested_apf
) {
2483 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
2487 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2488 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2489 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2490 * can be written only when inject_pending_event runs. This should be
2491 * conditional on a new capability---if the capability is disabled,
2492 * kvm_multiple_exception would write the ancillary information to
2493 * CR2 or DR6, for backwards ABI-compatibility.
2495 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2496 vcpu
->arch
.exception
.error_code
)) {
2497 *exit_qual
= vcpu
->arch
.cr2
;
2501 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2502 if (nr
== DB_VECTOR
)
2503 *exit_qual
= vcpu
->arch
.dr6
;
2513 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2515 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2516 unsigned nr
= vcpu
->arch
.exception
.nr
;
2517 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2518 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2519 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2521 if (has_error_code
) {
2522 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2523 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2526 if (vmx
->rmode
.vm86_active
) {
2528 if (kvm_exception_is_soft(nr
))
2529 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2530 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2531 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2535 if (kvm_exception_is_soft(nr
)) {
2536 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2537 vmx
->vcpu
.arch
.event_exit_inst_len
);
2538 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2540 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2542 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2545 static bool vmx_rdtscp_supported(void)
2547 return cpu_has_vmx_rdtscp();
2550 static bool vmx_invpcid_supported(void)
2552 return cpu_has_vmx_invpcid() && enable_ept
;
2556 * Swap MSR entry in host/guest MSR entry array.
2558 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2560 struct shared_msr_entry tmp
;
2562 tmp
= vmx
->guest_msrs
[to
];
2563 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2564 vmx
->guest_msrs
[from
] = tmp
;
2567 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2569 unsigned long *msr_bitmap
;
2571 if (is_guest_mode(vcpu
))
2572 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2573 else if (cpu_has_secondary_exec_ctrls() &&
2574 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2575 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2576 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2577 if (is_long_mode(vcpu
))
2578 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2580 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2582 if (is_long_mode(vcpu
))
2583 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2585 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2588 if (is_long_mode(vcpu
))
2589 msr_bitmap
= vmx_msr_bitmap_longmode
;
2591 msr_bitmap
= vmx_msr_bitmap_legacy
;
2594 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2598 * Set up the vmcs to automatically save and restore system
2599 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2600 * mode, as fiddling with msrs is very expensive.
2602 static void setup_msrs(struct vcpu_vmx
*vmx
)
2604 int save_nmsrs
, index
;
2607 #ifdef CONFIG_X86_64
2608 if (is_long_mode(&vmx
->vcpu
)) {
2609 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2611 move_msr_up(vmx
, index
, save_nmsrs
++);
2612 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2614 move_msr_up(vmx
, index
, save_nmsrs
++);
2615 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2617 move_msr_up(vmx
, index
, save_nmsrs
++);
2618 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2619 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2620 move_msr_up(vmx
, index
, save_nmsrs
++);
2622 * MSR_STAR is only needed on long mode guests, and only
2623 * if efer.sce is enabled.
2625 index
= __find_msr_index(vmx
, MSR_STAR
);
2626 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2627 move_msr_up(vmx
, index
, save_nmsrs
++);
2630 index
= __find_msr_index(vmx
, MSR_EFER
);
2631 if (index
>= 0 && update_transition_efer(vmx
, index
))
2632 move_msr_up(vmx
, index
, save_nmsrs
++);
2634 vmx
->save_nmsrs
= save_nmsrs
;
2636 if (cpu_has_vmx_msr_bitmap())
2637 vmx_set_msr_bitmap(&vmx
->vcpu
);
2641 * reads and returns guest's timestamp counter "register"
2642 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2643 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2645 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2647 u64 host_tsc
, tsc_offset
;
2650 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2651 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2655 * writes 'offset' into guest's timestamp counter offset register
2657 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2659 if (is_guest_mode(vcpu
)) {
2661 * We're here if L1 chose not to trap WRMSR to TSC. According
2662 * to the spec, this should set L1's TSC; The offset that L1
2663 * set for L2 remains unchanged, and still needs to be added
2664 * to the newly set TSC to get L2's TSC.
2666 struct vmcs12
*vmcs12
;
2667 /* recalculate vmcs02.TSC_OFFSET: */
2668 vmcs12
= get_vmcs12(vcpu
);
2669 vmcs_write64(TSC_OFFSET
, offset
+
2670 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2671 vmcs12
->tsc_offset
: 0));
2673 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2674 vmcs_read64(TSC_OFFSET
), offset
);
2675 vmcs_write64(TSC_OFFSET
, offset
);
2680 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2681 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2682 * all guests if the "nested" module option is off, and can also be disabled
2683 * for a single guest by disabling its VMX cpuid bit.
2685 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2687 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2691 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2692 * returned for the various VMX controls MSRs when nested VMX is enabled.
2693 * The same values should also be used to verify that vmcs12 control fields are
2694 * valid during nested entry from L1 to L2.
2695 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2696 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2697 * bit in the high half is on if the corresponding bit in the control field
2698 * may be on. See also vmx_control_verify().
2700 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2703 * Note that as a general rule, the high half of the MSRs (bits in
2704 * the control fields which may be 1) should be initialized by the
2705 * intersection of the underlying hardware's MSR (i.e., features which
2706 * can be supported) and the list of features we want to expose -
2707 * because they are known to be properly supported in our code.
2708 * Also, usually, the low half of the MSRs (bits which must be 1) can
2709 * be set to 0, meaning that L1 may turn off any of these bits. The
2710 * reason is that if one of these bits is necessary, it will appear
2711 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2712 * fields of vmcs01 and vmcs02, will turn these bits off - and
2713 * nested_vmx_exit_reflected() will not pass related exits to L1.
2714 * These rules have exceptions below.
2717 /* pin-based controls */
2718 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2719 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2720 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2721 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2722 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2723 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2724 PIN_BASED_EXT_INTR_MASK
|
2725 PIN_BASED_NMI_EXITING
|
2726 PIN_BASED_VIRTUAL_NMIS
;
2727 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2728 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2729 PIN_BASED_VMX_PREEMPTION_TIMER
;
2730 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2731 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2732 PIN_BASED_POSTED_INTR
;
2735 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2736 vmx
->nested
.nested_vmx_exit_ctls_low
,
2737 vmx
->nested
.nested_vmx_exit_ctls_high
);
2738 vmx
->nested
.nested_vmx_exit_ctls_low
=
2739 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2741 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2742 #ifdef CONFIG_X86_64
2743 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2745 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2746 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2747 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2748 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2749 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2751 if (kvm_mpx_supported())
2752 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2754 /* We support free control of debug control saving. */
2755 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2757 /* entry controls */
2758 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2759 vmx
->nested
.nested_vmx_entry_ctls_low
,
2760 vmx
->nested
.nested_vmx_entry_ctls_high
);
2761 vmx
->nested
.nested_vmx_entry_ctls_low
=
2762 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2763 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2764 #ifdef CONFIG_X86_64
2765 VM_ENTRY_IA32E_MODE
|
2767 VM_ENTRY_LOAD_IA32_PAT
;
2768 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2769 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2770 if (kvm_mpx_supported())
2771 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2773 /* We support free control of debug control loading. */
2774 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2776 /* cpu-based controls */
2777 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2778 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2779 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2780 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2781 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2782 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2783 CPU_BASED_VIRTUAL_INTR_PENDING
|
2784 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2785 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2786 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2787 CPU_BASED_CR3_STORE_EXITING
|
2788 #ifdef CONFIG_X86_64
2789 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2791 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2792 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2793 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2794 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2795 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2797 * We can allow some features even when not supported by the
2798 * hardware. For example, L1 can specify an MSR bitmap - and we
2799 * can use it to avoid exits to L1 - even when L0 runs L2
2800 * without MSR bitmaps.
2802 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2803 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2804 CPU_BASED_USE_MSR_BITMAPS
;
2806 /* We support free control of CR3 access interception. */
2807 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2808 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2811 * secondary cpu-based controls. Do not include those that
2812 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2814 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2815 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2816 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2817 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2818 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2819 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2820 SECONDARY_EXEC_DESC
|
2821 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2822 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2823 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2824 SECONDARY_EXEC_WBINVD_EXITING
;
2827 /* nested EPT: emulate EPT also to L1 */
2828 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2829 SECONDARY_EXEC_ENABLE_EPT
;
2830 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2831 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2832 if (cpu_has_vmx_ept_execute_only())
2833 vmx
->nested
.nested_vmx_ept_caps
|=
2834 VMX_EPT_EXECUTE_ONLY_BIT
;
2835 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2836 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2837 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2838 VMX_EPT_1GB_PAGE_BIT
;
2839 if (enable_ept_ad_bits
) {
2840 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2841 SECONDARY_EXEC_ENABLE_PML
;
2842 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2846 if (cpu_has_vmx_vmfunc()) {
2847 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2848 SECONDARY_EXEC_ENABLE_VMFUNC
;
2850 * Advertise EPTP switching unconditionally
2851 * since we emulate it
2854 vmx
->nested
.nested_vmx_vmfunc_controls
=
2855 VMX_VMFUNC_EPTP_SWITCHING
;
2859 * Old versions of KVM use the single-context version without
2860 * checking for support, so declare that it is supported even
2861 * though it is treated as global context. The alternative is
2862 * not failing the single-context invvpid, and it is worse.
2865 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2866 SECONDARY_EXEC_ENABLE_VPID
;
2867 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2868 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2871 if (enable_unrestricted_guest
)
2872 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2873 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2875 /* miscellaneous data */
2876 rdmsr(MSR_IA32_VMX_MISC
,
2877 vmx
->nested
.nested_vmx_misc_low
,
2878 vmx
->nested
.nested_vmx_misc_high
);
2879 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2880 vmx
->nested
.nested_vmx_misc_low
|=
2881 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2882 VMX_MISC_ACTIVITY_HLT
;
2883 vmx
->nested
.nested_vmx_misc_high
= 0;
2886 * This MSR reports some information about VMX support. We
2887 * should return information about the VMX we emulate for the
2888 * guest, and the VMCS structure we give it - not about the
2889 * VMX support of the underlying hardware.
2891 vmx
->nested
.nested_vmx_basic
=
2893 VMX_BASIC_TRUE_CTLS
|
2894 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2895 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2897 if (cpu_has_vmx_basic_inout())
2898 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2901 * These MSRs specify bits which the guest must keep fixed on
2902 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2903 * We picked the standard core2 setting.
2905 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2906 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2907 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2908 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2910 /* These MSRs specify bits which the guest must keep fixed off. */
2911 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2912 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2914 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2915 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2919 * if fixed0[i] == 1: val[i] must be 1
2920 * if fixed1[i] == 0: val[i] must be 0
2922 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2924 return ((val
& fixed1
) | fixed0
) == val
;
2927 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2929 return fixed_bits_valid(control
, low
, high
);
2932 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2934 return low
| ((u64
)high
<< 32);
2937 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2942 return (superset
| subset
) == superset
;
2945 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2947 const u64 feature_and_reserved
=
2948 /* feature (except bit 48; see below) */
2949 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2951 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2952 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2954 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2958 * KVM does not emulate a version of VMX that constrains physical
2959 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2961 if (data
& BIT_ULL(48))
2964 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2965 vmx_basic_vmcs_revision_id(data
))
2968 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2971 vmx
->nested
.nested_vmx_basic
= data
;
2976 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2981 switch (msr_index
) {
2982 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2983 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2984 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2986 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2987 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2988 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2990 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2991 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2992 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2994 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2995 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2996 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2998 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2999 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
3000 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
3006 supported
= vmx_control_msr(*lowp
, *highp
);
3008 /* Check must-be-1 bits are still 1. */
3009 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3012 /* Check must-be-0 bits are still 0. */
3013 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3017 *highp
= data
>> 32;
3021 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3023 const u64 feature_and_reserved_bits
=
3025 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3026 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3028 GENMASK_ULL(13, 9) | BIT_ULL(31);
3031 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3032 vmx
->nested
.nested_vmx_misc_high
);
3034 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3037 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3038 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3039 vmx_misc_preemption_timer_rate(data
) !=
3040 vmx_misc_preemption_timer_rate(vmx_misc
))
3043 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3046 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3049 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3052 vmx
->nested
.nested_vmx_misc_low
= data
;
3053 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3057 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3059 u64 vmx_ept_vpid_cap
;
3061 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3062 vmx
->nested
.nested_vmx_vpid_caps
);
3064 /* Every bit is either reserved or a feature bit. */
3065 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3068 vmx
->nested
.nested_vmx_ept_caps
= data
;
3069 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3073 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3077 switch (msr_index
) {
3078 case MSR_IA32_VMX_CR0_FIXED0
:
3079 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3081 case MSR_IA32_VMX_CR4_FIXED0
:
3082 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3089 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3090 * must be 1 in the restored value.
3092 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3100 * Called when userspace is restoring VMX MSRs.
3102 * Returns 0 on success, non-0 otherwise.
3104 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3106 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3108 switch (msr_index
) {
3109 case MSR_IA32_VMX_BASIC
:
3110 return vmx_restore_vmx_basic(vmx
, data
);
3111 case MSR_IA32_VMX_PINBASED_CTLS
:
3112 case MSR_IA32_VMX_PROCBASED_CTLS
:
3113 case MSR_IA32_VMX_EXIT_CTLS
:
3114 case MSR_IA32_VMX_ENTRY_CTLS
:
3116 * The "non-true" VMX capability MSRs are generated from the
3117 * "true" MSRs, so we do not support restoring them directly.
3119 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3120 * should restore the "true" MSRs with the must-be-1 bits
3121 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3122 * DEFAULT SETTINGS".
3125 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3126 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3127 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3128 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3129 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3130 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3131 case MSR_IA32_VMX_MISC
:
3132 return vmx_restore_vmx_misc(vmx
, data
);
3133 case MSR_IA32_VMX_CR0_FIXED0
:
3134 case MSR_IA32_VMX_CR4_FIXED0
:
3135 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3136 case MSR_IA32_VMX_CR0_FIXED1
:
3137 case MSR_IA32_VMX_CR4_FIXED1
:
3139 * These MSRs are generated based on the vCPU's CPUID, so we
3140 * do not support restoring them directly.
3143 case MSR_IA32_VMX_EPT_VPID_CAP
:
3144 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3145 case MSR_IA32_VMX_VMCS_ENUM
:
3146 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3150 * The rest of the VMX capability MSRs do not support restore.
3156 /* Returns 0 on success, non-0 otherwise. */
3157 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3159 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3161 switch (msr_index
) {
3162 case MSR_IA32_VMX_BASIC
:
3163 *pdata
= vmx
->nested
.nested_vmx_basic
;
3165 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3166 case MSR_IA32_VMX_PINBASED_CTLS
:
3167 *pdata
= vmx_control_msr(
3168 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3169 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3170 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3171 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3173 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3174 case MSR_IA32_VMX_PROCBASED_CTLS
:
3175 *pdata
= vmx_control_msr(
3176 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3177 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3178 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3179 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3181 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3182 case MSR_IA32_VMX_EXIT_CTLS
:
3183 *pdata
= vmx_control_msr(
3184 vmx
->nested
.nested_vmx_exit_ctls_low
,
3185 vmx
->nested
.nested_vmx_exit_ctls_high
);
3186 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3187 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3189 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3190 case MSR_IA32_VMX_ENTRY_CTLS
:
3191 *pdata
= vmx_control_msr(
3192 vmx
->nested
.nested_vmx_entry_ctls_low
,
3193 vmx
->nested
.nested_vmx_entry_ctls_high
);
3194 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3195 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3197 case MSR_IA32_VMX_MISC
:
3198 *pdata
= vmx_control_msr(
3199 vmx
->nested
.nested_vmx_misc_low
,
3200 vmx
->nested
.nested_vmx_misc_high
);
3202 case MSR_IA32_VMX_CR0_FIXED0
:
3203 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3205 case MSR_IA32_VMX_CR0_FIXED1
:
3206 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3208 case MSR_IA32_VMX_CR4_FIXED0
:
3209 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3211 case MSR_IA32_VMX_CR4_FIXED1
:
3212 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3214 case MSR_IA32_VMX_VMCS_ENUM
:
3215 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3217 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3218 *pdata
= vmx_control_msr(
3219 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3220 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3222 case MSR_IA32_VMX_EPT_VPID_CAP
:
3223 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3224 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3226 case MSR_IA32_VMX_VMFUNC
:
3227 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3236 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3239 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3241 return !(val
& ~valid_bits
);
3245 * Reads an msr value (of 'msr_index') into 'pdata'.
3246 * Returns 0 on success, non-0 otherwise.
3247 * Assumes vcpu_load() was already called.
3249 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3251 struct shared_msr_entry
*msr
;
3253 switch (msr_info
->index
) {
3254 #ifdef CONFIG_X86_64
3256 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3259 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3261 case MSR_KERNEL_GS_BASE
:
3262 vmx_load_host_state(to_vmx(vcpu
));
3263 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3267 return kvm_get_msr_common(vcpu
, msr_info
);
3269 msr_info
->data
= guest_read_tsc(vcpu
);
3271 case MSR_IA32_SYSENTER_CS
:
3272 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3274 case MSR_IA32_SYSENTER_EIP
:
3275 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3277 case MSR_IA32_SYSENTER_ESP
:
3278 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3280 case MSR_IA32_BNDCFGS
:
3281 if (!kvm_mpx_supported() ||
3282 (!msr_info
->host_initiated
&&
3283 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3285 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3287 case MSR_IA32_MCG_EXT_CTL
:
3288 if (!msr_info
->host_initiated
&&
3289 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3290 FEATURE_CONTROL_LMCE
))
3292 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3294 case MSR_IA32_FEATURE_CONTROL
:
3295 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3297 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3298 if (!nested_vmx_allowed(vcpu
))
3300 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3302 if (!vmx_xsaves_supported())
3304 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3307 if (!msr_info
->host_initiated
&&
3308 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3310 /* Otherwise falls through */
3312 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3314 msr_info
->data
= msr
->data
;
3317 return kvm_get_msr_common(vcpu
, msr_info
);
3323 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3326 * Writes msr value into into the appropriate "register".
3327 * Returns 0 on success, non-0 otherwise.
3328 * Assumes vcpu_load() was already called.
3330 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3332 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3333 struct shared_msr_entry
*msr
;
3335 u32 msr_index
= msr_info
->index
;
3336 u64 data
= msr_info
->data
;
3338 switch (msr_index
) {
3340 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3342 #ifdef CONFIG_X86_64
3344 vmx_segment_cache_clear(vmx
);
3345 vmcs_writel(GUEST_FS_BASE
, data
);
3348 vmx_segment_cache_clear(vmx
);
3349 vmcs_writel(GUEST_GS_BASE
, data
);
3351 case MSR_KERNEL_GS_BASE
:
3352 vmx_load_host_state(vmx
);
3353 vmx
->msr_guest_kernel_gs_base
= data
;
3356 case MSR_IA32_SYSENTER_CS
:
3357 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3359 case MSR_IA32_SYSENTER_EIP
:
3360 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3362 case MSR_IA32_SYSENTER_ESP
:
3363 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3365 case MSR_IA32_BNDCFGS
:
3366 if (!kvm_mpx_supported() ||
3367 (!msr_info
->host_initiated
&&
3368 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3370 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
3371 (data
& MSR_IA32_BNDCFGS_RSVD
))
3373 vmcs_write64(GUEST_BNDCFGS
, data
);
3376 kvm_write_tsc(vcpu
, msr_info
);
3378 case MSR_IA32_CR_PAT
:
3379 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3380 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3382 vmcs_write64(GUEST_IA32_PAT
, data
);
3383 vcpu
->arch
.pat
= data
;
3386 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3388 case MSR_IA32_TSC_ADJUST
:
3389 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3391 case MSR_IA32_MCG_EXT_CTL
:
3392 if ((!msr_info
->host_initiated
&&
3393 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3394 FEATURE_CONTROL_LMCE
)) ||
3395 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3397 vcpu
->arch
.mcg_ext_ctl
= data
;
3399 case MSR_IA32_FEATURE_CONTROL
:
3400 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3401 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3402 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3404 vmx
->msr_ia32_feature_control
= data
;
3405 if (msr_info
->host_initiated
&& data
== 0)
3406 vmx_leave_nested(vcpu
);
3408 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3409 if (!msr_info
->host_initiated
)
3410 return 1; /* they are read-only */
3411 if (!nested_vmx_allowed(vcpu
))
3413 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3415 if (!vmx_xsaves_supported())
3418 * The only supported bit as of Skylake is bit 8, but
3419 * it is not supported on KVM.
3423 vcpu
->arch
.ia32_xss
= data
;
3424 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3425 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3426 vcpu
->arch
.ia32_xss
, host_xss
);
3428 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3431 if (!msr_info
->host_initiated
&&
3432 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3434 /* Check reserved bit, higher 32 bits should be zero */
3435 if ((data
>> 32) != 0)
3437 /* Otherwise falls through */
3439 msr
= find_msr_entry(vmx
, msr_index
);
3441 u64 old_msr_data
= msr
->data
;
3443 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3445 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3449 msr
->data
= old_msr_data
;
3453 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3459 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3461 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3464 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3467 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3469 case VCPU_EXREG_PDPTR
:
3471 ept_save_pdptrs(vcpu
);
3478 static __init
int cpu_has_kvm_support(void)
3480 return cpu_has_vmx();
3483 static __init
int vmx_disabled_by_bios(void)
3487 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3488 if (msr
& FEATURE_CONTROL_LOCKED
) {
3489 /* launched w/ TXT and VMX disabled */
3490 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3493 /* launched w/o TXT and VMX only enabled w/ TXT */
3494 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3495 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3496 && !tboot_enabled()) {
3497 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3498 "activate TXT before enabling KVM\n");
3501 /* launched w/o TXT and VMX disabled */
3502 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3503 && !tboot_enabled())
3510 static void kvm_cpu_vmxon(u64 addr
)
3512 cr4_set_bits(X86_CR4_VMXE
);
3513 intel_pt_handle_vmx(1);
3515 asm volatile (ASM_VMX_VMXON_RAX
3516 : : "a"(&addr
), "m"(addr
)
3520 static int hardware_enable(void)
3522 int cpu
= raw_smp_processor_id();
3523 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3526 if (cr4_read_shadow() & X86_CR4_VMXE
)
3529 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3530 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3531 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3534 * Now we can enable the vmclear operation in kdump
3535 * since the loaded_vmcss_on_cpu list on this cpu
3536 * has been initialized.
3538 * Though the cpu is not in VMX operation now, there
3539 * is no problem to enable the vmclear operation
3540 * for the loaded_vmcss_on_cpu list is empty!
3542 crash_enable_local_vmclear(cpu
);
3544 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3546 test_bits
= FEATURE_CONTROL_LOCKED
;
3547 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3548 if (tboot_enabled())
3549 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3551 if ((old
& test_bits
) != test_bits
) {
3552 /* enable and lock */
3553 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3555 kvm_cpu_vmxon(phys_addr
);
3562 static void vmclear_local_loaded_vmcss(void)
3564 int cpu
= raw_smp_processor_id();
3565 struct loaded_vmcs
*v
, *n
;
3567 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3568 loaded_vmcss_on_cpu_link
)
3569 __loaded_vmcs_clear(v
);
3573 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3576 static void kvm_cpu_vmxoff(void)
3578 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3580 intel_pt_handle_vmx(0);
3581 cr4_clear_bits(X86_CR4_VMXE
);
3584 static void hardware_disable(void)
3586 vmclear_local_loaded_vmcss();
3590 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3591 u32 msr
, u32
*result
)
3593 u32 vmx_msr_low
, vmx_msr_high
;
3594 u32 ctl
= ctl_min
| ctl_opt
;
3596 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3598 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3599 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3601 /* Ensure minimum (required) set of control bits are supported. */
3609 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3611 u32 vmx_msr_low
, vmx_msr_high
;
3613 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3614 return vmx_msr_high
& ctl
;
3617 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3619 u32 vmx_msr_low
, vmx_msr_high
;
3620 u32 min
, opt
, min2
, opt2
;
3621 u32 _pin_based_exec_control
= 0;
3622 u32 _cpu_based_exec_control
= 0;
3623 u32 _cpu_based_2nd_exec_control
= 0;
3624 u32 _vmexit_control
= 0;
3625 u32 _vmentry_control
= 0;
3627 min
= CPU_BASED_HLT_EXITING
|
3628 #ifdef CONFIG_X86_64
3629 CPU_BASED_CR8_LOAD_EXITING
|
3630 CPU_BASED_CR8_STORE_EXITING
|
3632 CPU_BASED_CR3_LOAD_EXITING
|
3633 CPU_BASED_CR3_STORE_EXITING
|
3634 CPU_BASED_USE_IO_BITMAPS
|
3635 CPU_BASED_MOV_DR_EXITING
|
3636 CPU_BASED_USE_TSC_OFFSETING
|
3637 CPU_BASED_INVLPG_EXITING
|
3638 CPU_BASED_RDPMC_EXITING
;
3640 if (!kvm_mwait_in_guest())
3641 min
|= CPU_BASED_MWAIT_EXITING
|
3642 CPU_BASED_MONITOR_EXITING
;
3644 opt
= CPU_BASED_TPR_SHADOW
|
3645 CPU_BASED_USE_MSR_BITMAPS
|
3646 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3647 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3648 &_cpu_based_exec_control
) < 0)
3650 #ifdef CONFIG_X86_64
3651 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3652 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3653 ~CPU_BASED_CR8_STORE_EXITING
;
3655 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3657 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3658 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3659 SECONDARY_EXEC_WBINVD_EXITING
|
3660 SECONDARY_EXEC_ENABLE_VPID
|
3661 SECONDARY_EXEC_ENABLE_EPT
|
3662 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3663 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3664 SECONDARY_EXEC_RDTSCP
|
3665 SECONDARY_EXEC_ENABLE_INVPCID
|
3666 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3667 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3668 SECONDARY_EXEC_SHADOW_VMCS
|
3669 SECONDARY_EXEC_XSAVES
|
3670 SECONDARY_EXEC_RDSEED_EXITING
|
3671 SECONDARY_EXEC_RDRAND_EXITING
|
3672 SECONDARY_EXEC_ENABLE_PML
|
3673 SECONDARY_EXEC_TSC_SCALING
|
3674 SECONDARY_EXEC_ENABLE_VMFUNC
;
3675 if (adjust_vmx_controls(min2
, opt2
,
3676 MSR_IA32_VMX_PROCBASED_CTLS2
,
3677 &_cpu_based_2nd_exec_control
) < 0)
3680 #ifndef CONFIG_X86_64
3681 if (!(_cpu_based_2nd_exec_control
&
3682 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3683 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3686 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3687 _cpu_based_2nd_exec_control
&= ~(
3688 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3689 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3690 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3692 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP
,
3693 &vmx_capability
.ept
, &vmx_capability
.vpid
);
3695 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3696 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3698 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3699 CPU_BASED_CR3_STORE_EXITING
|
3700 CPU_BASED_INVLPG_EXITING
);
3701 } else if (vmx_capability
.ept
) {
3702 vmx_capability
.ept
= 0;
3703 pr_warn_once("EPT CAP should not exist if not support "
3704 "1-setting enable EPT VM-execution control\n");
3706 if (!(_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_VPID
) &&
3707 vmx_capability
.vpid
) {
3708 vmx_capability
.vpid
= 0;
3709 pr_warn_once("VPID CAP should not exist if not support "
3710 "1-setting enable VPID VM-execution control\n");
3713 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3714 #ifdef CONFIG_X86_64
3715 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3717 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3718 VM_EXIT_CLEAR_BNDCFGS
;
3719 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3720 &_vmexit_control
) < 0)
3723 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3724 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3725 PIN_BASED_VMX_PREEMPTION_TIMER
;
3726 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3727 &_pin_based_exec_control
) < 0)
3730 if (cpu_has_broken_vmx_preemption_timer())
3731 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3732 if (!(_cpu_based_2nd_exec_control
&
3733 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3734 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3736 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3737 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3738 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3739 &_vmentry_control
) < 0)
3742 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3744 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3745 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3748 #ifdef CONFIG_X86_64
3749 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3750 if (vmx_msr_high
& (1u<<16))
3754 /* Require Write-Back (WB) memory type for VMCS accesses. */
3755 if (((vmx_msr_high
>> 18) & 15) != 6)
3758 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3759 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3760 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3761 vmcs_conf
->revision_id
= vmx_msr_low
;
3763 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3764 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3765 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3766 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3767 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3769 cpu_has_load_ia32_efer
=
3770 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3771 VM_ENTRY_LOAD_IA32_EFER
)
3772 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3773 VM_EXIT_LOAD_IA32_EFER
);
3775 cpu_has_load_perf_global_ctrl
=
3776 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3777 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3778 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3779 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3782 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3783 * but due to errata below it can't be used. Workaround is to use
3784 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3786 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3791 * BC86,AAY89,BD102 (model 44)
3795 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3796 switch (boot_cpu_data
.x86_model
) {
3802 cpu_has_load_perf_global_ctrl
= false;
3803 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3804 "does not work properly. Using workaround\n");
3811 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3812 rdmsrl(MSR_IA32_XSS
, host_xss
);
3817 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3819 int node
= cpu_to_node(cpu
);
3823 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3826 vmcs
= page_address(pages
);
3827 memset(vmcs
, 0, vmcs_config
.size
);
3828 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3832 static struct vmcs
*alloc_vmcs(void)
3834 return alloc_vmcs_cpu(raw_smp_processor_id());
3837 static void free_vmcs(struct vmcs
*vmcs
)
3839 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3843 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3845 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3847 if (!loaded_vmcs
->vmcs
)
3849 loaded_vmcs_clear(loaded_vmcs
);
3850 free_vmcs(loaded_vmcs
->vmcs
);
3851 loaded_vmcs
->vmcs
= NULL
;
3852 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3855 static void free_kvm_area(void)
3859 for_each_possible_cpu(cpu
) {
3860 free_vmcs(per_cpu(vmxarea
, cpu
));
3861 per_cpu(vmxarea
, cpu
) = NULL
;
3865 enum vmcs_field_type
{
3866 VMCS_FIELD_TYPE_U16
= 0,
3867 VMCS_FIELD_TYPE_U64
= 1,
3868 VMCS_FIELD_TYPE_U32
= 2,
3869 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3872 static inline int vmcs_field_type(unsigned long field
)
3874 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3875 return VMCS_FIELD_TYPE_U32
;
3876 return (field
>> 13) & 0x3 ;
3879 static inline int vmcs_field_readonly(unsigned long field
)
3881 return (((field
>> 10) & 0x3) == 1);
3884 static void init_vmcs_shadow_fields(void)
3888 /* No checks for read only fields yet */
3890 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3891 switch (shadow_read_write_fields
[i
]) {
3893 if (!kvm_mpx_supported())
3901 shadow_read_write_fields
[j
] =
3902 shadow_read_write_fields
[i
];
3905 max_shadow_read_write_fields
= j
;
3907 /* shadowed fields guest access without vmexit */
3908 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3909 unsigned long field
= shadow_read_write_fields
[i
];
3911 clear_bit(field
, vmx_vmwrite_bitmap
);
3912 clear_bit(field
, vmx_vmread_bitmap
);
3913 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3914 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3915 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3918 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3919 unsigned long field
= shadow_read_only_fields
[i
];
3921 clear_bit(field
, vmx_vmread_bitmap
);
3922 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3923 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3927 static __init
int alloc_kvm_area(void)
3931 for_each_possible_cpu(cpu
) {
3934 vmcs
= alloc_vmcs_cpu(cpu
);
3940 per_cpu(vmxarea
, cpu
) = vmcs
;
3945 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3946 struct kvm_segment
*save
)
3948 if (!emulate_invalid_guest_state
) {
3950 * CS and SS RPL should be equal during guest entry according
3951 * to VMX spec, but in reality it is not always so. Since vcpu
3952 * is in the middle of the transition from real mode to
3953 * protected mode it is safe to assume that RPL 0 is a good
3956 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3957 save
->selector
&= ~SEGMENT_RPL_MASK
;
3958 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3961 vmx_set_segment(vcpu
, save
, seg
);
3964 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3966 unsigned long flags
;
3967 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3970 * Update real mode segment cache. It may be not up-to-date if sement
3971 * register was written while vcpu was in a guest mode.
3973 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3974 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3975 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3976 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3977 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3978 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3980 vmx
->rmode
.vm86_active
= 0;
3982 vmx_segment_cache_clear(vmx
);
3984 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3986 flags
= vmcs_readl(GUEST_RFLAGS
);
3987 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3988 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3989 vmcs_writel(GUEST_RFLAGS
, flags
);
3991 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3992 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3994 update_exception_bitmap(vcpu
);
3996 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3997 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3998 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3999 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4000 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4001 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4004 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
4006 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4007 struct kvm_segment var
= *save
;
4010 if (seg
== VCPU_SREG_CS
)
4013 if (!emulate_invalid_guest_state
) {
4014 var
.selector
= var
.base
>> 4;
4015 var
.base
= var
.base
& 0xffff0;
4025 if (save
->base
& 0xf)
4026 printk_once(KERN_WARNING
"kvm: segment base is not "
4027 "paragraph aligned when entering "
4028 "protected mode (seg=%d)", seg
);
4031 vmcs_write16(sf
->selector
, var
.selector
);
4032 vmcs_writel(sf
->base
, var
.base
);
4033 vmcs_write32(sf
->limit
, var
.limit
);
4034 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4037 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4039 unsigned long flags
;
4040 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4042 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4043 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4044 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4045 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4046 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4047 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4048 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4050 vmx
->rmode
.vm86_active
= 1;
4053 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4054 * vcpu. Warn the user that an update is overdue.
4056 if (!vcpu
->kvm
->arch
.tss_addr
)
4057 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4058 "called before entering vcpu\n");
4060 vmx_segment_cache_clear(vmx
);
4062 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4063 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4064 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4066 flags
= vmcs_readl(GUEST_RFLAGS
);
4067 vmx
->rmode
.save_rflags
= flags
;
4069 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4071 vmcs_writel(GUEST_RFLAGS
, flags
);
4072 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4073 update_exception_bitmap(vcpu
);
4075 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4076 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4077 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4078 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4079 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4080 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4082 kvm_mmu_reset_context(vcpu
);
4085 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4087 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4088 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4094 * Force kernel_gs_base reloading before EFER changes, as control
4095 * of this msr depends on is_long_mode().
4097 vmx_load_host_state(to_vmx(vcpu
));
4098 vcpu
->arch
.efer
= efer
;
4099 if (efer
& EFER_LMA
) {
4100 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4103 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4105 msr
->data
= efer
& ~EFER_LME
;
4110 #ifdef CONFIG_X86_64
4112 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4116 vmx_segment_cache_clear(to_vmx(vcpu
));
4118 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4119 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4120 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4122 vmcs_write32(GUEST_TR_AR_BYTES
,
4123 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4124 | VMX_AR_TYPE_BUSY_64_TSS
);
4126 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4129 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4131 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4132 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4137 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4140 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4142 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4144 vpid_sync_context(vpid
);
4148 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4150 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4153 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4156 vmx_flush_tlb(vcpu
);
4159 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4161 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4163 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4164 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4167 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4169 if (enable_ept
&& is_paging(vcpu
))
4170 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4171 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4174 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4176 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4178 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4179 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4182 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4184 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4186 if (!test_bit(VCPU_EXREG_PDPTR
,
4187 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4190 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4191 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4192 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4193 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4194 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4198 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4200 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4202 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4203 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4204 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4205 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4206 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4209 __set_bit(VCPU_EXREG_PDPTR
,
4210 (unsigned long *)&vcpu
->arch
.regs_avail
);
4211 __set_bit(VCPU_EXREG_PDPTR
,
4212 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4215 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4217 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4218 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4219 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4221 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4222 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4223 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4224 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4226 return fixed_bits_valid(val
, fixed0
, fixed1
);
4229 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4231 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4232 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4234 return fixed_bits_valid(val
, fixed0
, fixed1
);
4237 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4239 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4240 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4242 return fixed_bits_valid(val
, fixed0
, fixed1
);
4245 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4246 #define nested_guest_cr4_valid nested_cr4_valid
4247 #define nested_host_cr4_valid nested_cr4_valid
4249 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4251 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4253 struct kvm_vcpu
*vcpu
)
4255 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4256 vmx_decache_cr3(vcpu
);
4257 if (!(cr0
& X86_CR0_PG
)) {
4258 /* From paging/starting to nonpaging */
4259 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4260 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4261 (CPU_BASED_CR3_LOAD_EXITING
|
4262 CPU_BASED_CR3_STORE_EXITING
));
4263 vcpu
->arch
.cr0
= cr0
;
4264 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4265 } else if (!is_paging(vcpu
)) {
4266 /* From nonpaging to paging */
4267 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4268 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4269 ~(CPU_BASED_CR3_LOAD_EXITING
|
4270 CPU_BASED_CR3_STORE_EXITING
));
4271 vcpu
->arch
.cr0
= cr0
;
4272 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4275 if (!(cr0
& X86_CR0_WP
))
4276 *hw_cr0
&= ~X86_CR0_WP
;
4279 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4281 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4282 unsigned long hw_cr0
;
4284 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4285 if (enable_unrestricted_guest
)
4286 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4288 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4290 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4293 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4297 #ifdef CONFIG_X86_64
4298 if (vcpu
->arch
.efer
& EFER_LME
) {
4299 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4301 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4307 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4309 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4310 vmcs_writel(GUEST_CR0
, hw_cr0
);
4311 vcpu
->arch
.cr0
= cr0
;
4313 /* depends on vcpu->arch.cr0 to be set to a new value */
4314 vmx
->emulation_required
= emulation_required(vcpu
);
4317 static int get_ept_level(struct kvm_vcpu
*vcpu
)
4319 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
4324 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4326 u64 eptp
= VMX_EPTP_MT_WB
;
4328 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
4330 if (enable_ept_ad_bits
&&
4331 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4332 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
4333 eptp
|= (root_hpa
& PAGE_MASK
);
4338 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4340 unsigned long guest_cr3
;
4345 eptp
= construct_eptp(vcpu
, cr3
);
4346 vmcs_write64(EPT_POINTER
, eptp
);
4347 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4348 guest_cr3
= kvm_read_cr3(vcpu
);
4350 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4351 ept_load_pdptrs(vcpu
);
4354 vmx_flush_tlb(vcpu
);
4355 vmcs_writel(GUEST_CR3
, guest_cr3
);
4358 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4361 * Pass through host's Machine Check Enable value to hw_cr4, which
4362 * is in force while we are in guest mode. Do not let guests control
4363 * this bit, even if host CR4.MCE == 0.
4365 unsigned long hw_cr4
=
4366 (cr4_read_shadow() & X86_CR4_MCE
) |
4367 (cr4
& ~X86_CR4_MCE
) |
4368 (to_vmx(vcpu
)->rmode
.vm86_active
?
4369 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4371 if (cr4
& X86_CR4_VMXE
) {
4373 * To use VMXON (and later other VMX instructions), a guest
4374 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4375 * So basically the check on whether to allow nested VMX
4378 if (!nested_vmx_allowed(vcpu
))
4382 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4385 vcpu
->arch
.cr4
= cr4
;
4387 if (!is_paging(vcpu
)) {
4388 hw_cr4
&= ~X86_CR4_PAE
;
4389 hw_cr4
|= X86_CR4_PSE
;
4390 } else if (!(cr4
& X86_CR4_PAE
)) {
4391 hw_cr4
&= ~X86_CR4_PAE
;
4395 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4397 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4398 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4399 * to be manually disabled when guest switches to non-paging
4402 * If !enable_unrestricted_guest, the CPU is always running
4403 * with CR0.PG=1 and CR4 needs to be modified.
4404 * If enable_unrestricted_guest, the CPU automatically
4405 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4407 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4409 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4410 vmcs_writel(GUEST_CR4
, hw_cr4
);
4414 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4415 struct kvm_segment
*var
, int seg
)
4417 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4420 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4421 *var
= vmx
->rmode
.segs
[seg
];
4422 if (seg
== VCPU_SREG_TR
4423 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4425 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4426 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4429 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4430 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4431 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4432 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4433 var
->unusable
= (ar
>> 16) & 1;
4434 var
->type
= ar
& 15;
4435 var
->s
= (ar
>> 4) & 1;
4436 var
->dpl
= (ar
>> 5) & 3;
4438 * Some userspaces do not preserve unusable property. Since usable
4439 * segment has to be present according to VMX spec we can use present
4440 * property to amend userspace bug by making unusable segment always
4441 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4442 * segment as unusable.
4444 var
->present
= !var
->unusable
;
4445 var
->avl
= (ar
>> 12) & 1;
4446 var
->l
= (ar
>> 13) & 1;
4447 var
->db
= (ar
>> 14) & 1;
4448 var
->g
= (ar
>> 15) & 1;
4451 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4453 struct kvm_segment s
;
4455 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4456 vmx_get_segment(vcpu
, &s
, seg
);
4459 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4462 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4464 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4466 if (unlikely(vmx
->rmode
.vm86_active
))
4469 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4470 return VMX_AR_DPL(ar
);
4474 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4478 if (var
->unusable
|| !var
->present
)
4481 ar
= var
->type
& 15;
4482 ar
|= (var
->s
& 1) << 4;
4483 ar
|= (var
->dpl
& 3) << 5;
4484 ar
|= (var
->present
& 1) << 7;
4485 ar
|= (var
->avl
& 1) << 12;
4486 ar
|= (var
->l
& 1) << 13;
4487 ar
|= (var
->db
& 1) << 14;
4488 ar
|= (var
->g
& 1) << 15;
4494 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4495 struct kvm_segment
*var
, int seg
)
4497 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4498 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4500 vmx_segment_cache_clear(vmx
);
4502 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4503 vmx
->rmode
.segs
[seg
] = *var
;
4504 if (seg
== VCPU_SREG_TR
)
4505 vmcs_write16(sf
->selector
, var
->selector
);
4507 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4511 vmcs_writel(sf
->base
, var
->base
);
4512 vmcs_write32(sf
->limit
, var
->limit
);
4513 vmcs_write16(sf
->selector
, var
->selector
);
4516 * Fix the "Accessed" bit in AR field of segment registers for older
4518 * IA32 arch specifies that at the time of processor reset the
4519 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4520 * is setting it to 0 in the userland code. This causes invalid guest
4521 * state vmexit when "unrestricted guest" mode is turned on.
4522 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4523 * tree. Newer qemu binaries with that qemu fix would not need this
4526 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4527 var
->type
|= 0x1; /* Accessed */
4529 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4532 vmx
->emulation_required
= emulation_required(vcpu
);
4535 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4537 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4539 *db
= (ar
>> 14) & 1;
4540 *l
= (ar
>> 13) & 1;
4543 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4545 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4546 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4549 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4551 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4552 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4555 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4557 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4558 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4561 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4563 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4564 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4567 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4569 struct kvm_segment var
;
4572 vmx_get_segment(vcpu
, &var
, seg
);
4574 if (seg
== VCPU_SREG_CS
)
4576 ar
= vmx_segment_access_rights(&var
);
4578 if (var
.base
!= (var
.selector
<< 4))
4580 if (var
.limit
!= 0xffff)
4588 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4590 struct kvm_segment cs
;
4591 unsigned int cs_rpl
;
4593 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4594 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4598 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4602 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4603 if (cs
.dpl
> cs_rpl
)
4606 if (cs
.dpl
!= cs_rpl
)
4612 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4616 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4618 struct kvm_segment ss
;
4619 unsigned int ss_rpl
;
4621 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4622 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4626 if (ss
.type
!= 3 && ss
.type
!= 7)
4630 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4638 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4640 struct kvm_segment var
;
4643 vmx_get_segment(vcpu
, &var
, seg
);
4644 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4652 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4653 if (var
.dpl
< rpl
) /* DPL < RPL */
4657 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4663 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4665 struct kvm_segment tr
;
4667 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4671 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4673 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4681 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4683 struct kvm_segment ldtr
;
4685 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4689 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4699 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4701 struct kvm_segment cs
, ss
;
4703 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4704 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4706 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4707 (ss
.selector
& SEGMENT_RPL_MASK
));
4711 * Check if guest state is valid. Returns true if valid, false if
4713 * We assume that registers are always usable
4715 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4717 if (enable_unrestricted_guest
)
4720 /* real mode guest state checks */
4721 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4722 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4724 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4726 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4728 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4730 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4732 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4735 /* protected mode guest state checks */
4736 if (!cs_ss_rpl_check(vcpu
))
4738 if (!code_segment_valid(vcpu
))
4740 if (!stack_segment_valid(vcpu
))
4742 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4744 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4746 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4748 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4750 if (!tr_valid(vcpu
))
4752 if (!ldtr_valid(vcpu
))
4756 * - Add checks on RIP
4757 * - Add checks on RFLAGS
4763 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4765 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4768 static int init_rmode_tss(struct kvm
*kvm
)
4774 idx
= srcu_read_lock(&kvm
->srcu
);
4775 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4776 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4779 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4780 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4781 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4784 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4787 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4791 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4792 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4795 srcu_read_unlock(&kvm
->srcu
, idx
);
4799 static int init_rmode_identity_map(struct kvm
*kvm
)
4802 kvm_pfn_t identity_map_pfn
;
4805 /* Protect kvm->arch.ept_identity_pagetable_done. */
4806 mutex_lock(&kvm
->slots_lock
);
4808 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4811 if (!kvm
->arch
.ept_identity_map_addr
)
4812 kvm
->arch
.ept_identity_map_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4813 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4815 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4816 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4820 idx
= srcu_read_lock(&kvm
->srcu
);
4821 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4824 /* Set up identity-mapping pagetable for EPT in real mode */
4825 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4826 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4827 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4828 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4829 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4833 kvm
->arch
.ept_identity_pagetable_done
= true;
4836 srcu_read_unlock(&kvm
->srcu
, idx
);
4839 mutex_unlock(&kvm
->slots_lock
);
4843 static void seg_setup(int seg
)
4845 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4848 vmcs_write16(sf
->selector
, 0);
4849 vmcs_writel(sf
->base
, 0);
4850 vmcs_write32(sf
->limit
, 0xffff);
4852 if (seg
== VCPU_SREG_CS
)
4853 ar
|= 0x08; /* code segment */
4855 vmcs_write32(sf
->ar_bytes
, ar
);
4858 static int alloc_apic_access_page(struct kvm
*kvm
)
4863 mutex_lock(&kvm
->slots_lock
);
4864 if (kvm
->arch
.apic_access_page_done
)
4866 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4867 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4871 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4872 if (is_error_page(page
)) {
4878 * Do not pin the page in memory, so that memory hot-unplug
4879 * is able to migrate it.
4882 kvm
->arch
.apic_access_page_done
= true;
4884 mutex_unlock(&kvm
->slots_lock
);
4888 static int allocate_vpid(void)
4894 spin_lock(&vmx_vpid_lock
);
4895 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4896 if (vpid
< VMX_NR_VPIDS
)
4897 __set_bit(vpid
, vmx_vpid_bitmap
);
4900 spin_unlock(&vmx_vpid_lock
);
4904 static void free_vpid(int vpid
)
4906 if (!enable_vpid
|| vpid
== 0)
4908 spin_lock(&vmx_vpid_lock
);
4909 __clear_bit(vpid
, vmx_vpid_bitmap
);
4910 spin_unlock(&vmx_vpid_lock
);
4913 #define MSR_TYPE_R 1
4914 #define MSR_TYPE_W 2
4915 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4918 int f
= sizeof(unsigned long);
4920 if (!cpu_has_vmx_msr_bitmap())
4924 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4925 * have the write-low and read-high bitmap offsets the wrong way round.
4926 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4928 if (msr
<= 0x1fff) {
4929 if (type
& MSR_TYPE_R
)
4931 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4933 if (type
& MSR_TYPE_W
)
4935 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4937 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4939 if (type
& MSR_TYPE_R
)
4941 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4943 if (type
& MSR_TYPE_W
)
4945 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4951 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4952 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4954 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4955 unsigned long *msr_bitmap_nested
,
4958 int f
= sizeof(unsigned long);
4960 if (!cpu_has_vmx_msr_bitmap()) {
4966 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4967 * have the write-low and read-high bitmap offsets the wrong way round.
4968 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4970 if (msr
<= 0x1fff) {
4971 if (type
& MSR_TYPE_R
&&
4972 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4974 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4976 if (type
& MSR_TYPE_W
&&
4977 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4979 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4981 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4983 if (type
& MSR_TYPE_R
&&
4984 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4986 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4988 if (type
& MSR_TYPE_W
&&
4989 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4991 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4996 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4999 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
5000 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
5001 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
5002 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
5005 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
5008 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
5010 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
5013 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
5015 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
5020 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5022 return enable_apicv
;
5025 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5027 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5031 * Don't need to mark the APIC access page dirty; it is never
5032 * written to by the CPU during APIC virtualization.
5035 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5036 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5037 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5040 if (nested_cpu_has_posted_intr(vmcs12
)) {
5041 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5042 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5047 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5049 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5054 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5057 vmx
->nested
.pi_pending
= false;
5058 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5061 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5062 if (max_irr
!= 256) {
5063 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5064 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5065 kunmap(vmx
->nested
.virtual_apic_page
);
5067 status
= vmcs_read16(GUEST_INTR_STATUS
);
5068 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5070 status
|= (u8
)max_irr
;
5071 vmcs_write16(GUEST_INTR_STATUS
, status
);
5075 nested_mark_vmcs12_pages_dirty(vcpu
);
5078 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5082 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5084 if (vcpu
->mode
== IN_GUEST_MODE
) {
5086 * The vector of interrupt to be delivered to vcpu had
5087 * been set in PIR before this function.
5089 * Following cases will be reached in this block, and
5090 * we always send a notification event in all cases as
5093 * Case 1: vcpu keeps in non-root mode. Sending a
5094 * notification event posts the interrupt to vcpu.
5096 * Case 2: vcpu exits to root mode and is still
5097 * runnable. PIR will be synced to vIRR before the
5098 * next vcpu entry. Sending a notification event in
5099 * this case has no effect, as vcpu is not in root
5102 * Case 3: vcpu exits to root mode and is blocked.
5103 * vcpu_block() has already synced PIR to vIRR and
5104 * never blocks vcpu if vIRR is not cleared. Therefore,
5105 * a blocked vcpu here does not wait for any requested
5106 * interrupts in PIR, and sending a notification event
5107 * which has no effect is safe here.
5110 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5117 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5120 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5122 if (is_guest_mode(vcpu
) &&
5123 vector
== vmx
->nested
.posted_intr_nv
) {
5124 /* the PIR and ON have been set by L1. */
5125 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5127 * If a posted intr is not recognized by hardware,
5128 * we will accomplish it in the next vmentry.
5130 vmx
->nested
.pi_pending
= true;
5131 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5137 * Send interrupt to vcpu via posted interrupt way.
5138 * 1. If target vcpu is running(non-root mode), send posted interrupt
5139 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5140 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5141 * interrupt from PIR in next vmentry.
5143 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5145 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5148 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5152 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5155 /* If a previous notification has sent the IPI, nothing to do. */
5156 if (pi_test_and_set_on(&vmx
->pi_desc
))
5159 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5160 kvm_vcpu_kick(vcpu
);
5164 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5165 * will not change in the lifetime of the guest.
5166 * Note that host-state that does change is set elsewhere. E.g., host-state
5167 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5169 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5174 unsigned long cr0
, cr3
, cr4
;
5177 WARN_ON(cr0
& X86_CR0_TS
);
5178 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5181 * Save the most likely value for this task's CR3 in the VMCS.
5182 * We can't use __get_current_cr3_fast() because we're not atomic.
5185 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5186 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5188 /* Save the most likely value for this task's CR4 in the VMCS. */
5189 cr4
= cr4_read_shadow();
5190 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5191 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5193 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5194 #ifdef CONFIG_X86_64
5196 * Load null selectors, so we can avoid reloading them in
5197 * __vmx_load_host_state(), in case userspace uses the null selectors
5198 * too (the expected case).
5200 vmcs_write16(HOST_DS_SELECTOR
, 0);
5201 vmcs_write16(HOST_ES_SELECTOR
, 0);
5203 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5204 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5206 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5207 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5210 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5211 vmx
->host_idt_base
= dt
.address
;
5213 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5215 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5216 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5217 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5218 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5220 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5221 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5222 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5226 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5228 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5230 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5231 if (is_guest_mode(&vmx
->vcpu
))
5232 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5233 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5234 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5237 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5239 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5241 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5242 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5245 pin_based_exec_ctrl
&= ~PIN_BASED_VIRTUAL_NMIS
;
5247 /* Enable the preemption timer dynamically */
5248 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5249 return pin_based_exec_ctrl
;
5252 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5254 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5256 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5257 if (cpu_has_secondary_exec_ctrls()) {
5258 if (kvm_vcpu_apicv_active(vcpu
))
5259 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5260 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5261 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5263 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5264 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5265 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5268 if (cpu_has_vmx_msr_bitmap())
5269 vmx_set_msr_bitmap(vcpu
);
5272 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5274 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5276 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5277 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5279 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5280 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5281 #ifdef CONFIG_X86_64
5282 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5283 CPU_BASED_CR8_LOAD_EXITING
;
5287 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5288 CPU_BASED_CR3_LOAD_EXITING
|
5289 CPU_BASED_INVLPG_EXITING
;
5290 return exec_control
;
5293 static bool vmx_rdrand_supported(void)
5295 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5296 SECONDARY_EXEC_RDRAND_EXITING
;
5299 static bool vmx_rdseed_supported(void)
5301 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5302 SECONDARY_EXEC_RDSEED_EXITING
;
5305 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
5307 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
5309 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5310 if (!cpu_need_virtualize_apic_accesses(vcpu
))
5311 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5313 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5315 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5316 enable_unrestricted_guest
= 0;
5317 /* Enable INVPCID for non-ept guests may cause performance regression. */
5318 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5320 if (!enable_unrestricted_guest
)
5321 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5323 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5324 if (!kvm_vcpu_apicv_active(vcpu
))
5325 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5326 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5327 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5328 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5330 We can NOT enable shadow_vmcs here because we don't have yet
5333 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5336 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5338 if (vmx_xsaves_supported()) {
5339 /* Exposing XSAVES only when XSAVE is exposed */
5340 bool xsaves_enabled
=
5341 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
5342 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
5344 if (!xsaves_enabled
)
5345 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
5349 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5350 SECONDARY_EXEC_XSAVES
;
5352 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5353 ~SECONDARY_EXEC_XSAVES
;
5357 if (vmx_rdtscp_supported()) {
5358 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
5359 if (!rdtscp_enabled
)
5360 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5364 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5365 SECONDARY_EXEC_RDTSCP
;
5367 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5368 ~SECONDARY_EXEC_RDTSCP
;
5372 if (vmx_invpcid_supported()) {
5373 /* Exposing INVPCID only when PCID is exposed */
5374 bool invpcid_enabled
=
5375 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
5376 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
5378 if (!invpcid_enabled
) {
5379 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5380 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
5384 if (invpcid_enabled
)
5385 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5386 SECONDARY_EXEC_ENABLE_INVPCID
;
5388 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5389 ~SECONDARY_EXEC_ENABLE_INVPCID
;
5393 if (vmx_rdrand_supported()) {
5394 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
5396 exec_control
&= ~SECONDARY_EXEC_RDRAND_EXITING
;
5400 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5401 SECONDARY_EXEC_RDRAND_EXITING
;
5403 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5404 ~SECONDARY_EXEC_RDRAND_EXITING
;
5408 if (vmx_rdseed_supported()) {
5409 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
5411 exec_control
&= ~SECONDARY_EXEC_RDSEED_EXITING
;
5415 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5416 SECONDARY_EXEC_RDSEED_EXITING
;
5418 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5419 ~SECONDARY_EXEC_RDSEED_EXITING
;
5423 vmx
->secondary_exec_control
= exec_control
;
5426 static void ept_set_mmio_spte_mask(void)
5429 * EPT Misconfigurations can be generated if the value of bits 2:0
5430 * of an EPT paging-structure entry is 110b (write/execute).
5432 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5433 VMX_EPT_MISCONFIG_WX_VALUE
);
5436 #define VMX_XSS_EXIT_BITMAP 0
5438 * Sets up the vmcs for emulated real mode.
5440 static void vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5442 #ifdef CONFIG_X86_64
5448 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5449 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5451 if (enable_shadow_vmcs
) {
5452 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5453 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5455 if (cpu_has_vmx_msr_bitmap())
5456 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5458 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5461 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5462 vmx
->hv_deadline_tsc
= -1;
5464 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5466 if (cpu_has_secondary_exec_ctrls()) {
5467 vmx_compute_secondary_exec_control(vmx
);
5468 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5469 vmx
->secondary_exec_control
);
5472 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5473 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5474 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5475 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5476 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5478 vmcs_write16(GUEST_INTR_STATUS
, 0);
5480 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5481 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5485 vmcs_write32(PLE_GAP
, ple_gap
);
5486 vmx
->ple_window
= ple_window
;
5487 vmx
->ple_window_dirty
= true;
5490 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5491 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5492 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5494 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5495 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5496 vmx_set_constant_host_state(vmx
);
5497 #ifdef CONFIG_X86_64
5498 rdmsrl(MSR_FS_BASE
, a
);
5499 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5500 rdmsrl(MSR_GS_BASE
, a
);
5501 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5503 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5504 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5507 if (cpu_has_vmx_vmfunc())
5508 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5510 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5511 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5512 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5513 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5514 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5516 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5517 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5519 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5520 u32 index
= vmx_msr_index
[i
];
5521 u32 data_low
, data_high
;
5524 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5526 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5528 vmx
->guest_msrs
[j
].index
= i
;
5529 vmx
->guest_msrs
[j
].data
= 0;
5530 vmx
->guest_msrs
[j
].mask
= -1ull;
5535 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5537 /* 22.2.1, 20.8.1 */
5538 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5540 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5541 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5543 set_cr4_guest_host_mask(vmx
);
5545 if (vmx_xsaves_supported())
5546 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5549 ASSERT(vmx
->pml_pg
);
5550 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5551 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5555 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5557 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5558 struct msr_data apic_base_msr
;
5561 vmx
->rmode
.vm86_active
= 0;
5563 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5564 kvm_set_cr8(vcpu
, 0);
5567 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5568 MSR_IA32_APICBASE_ENABLE
;
5569 if (kvm_vcpu_is_reset_bsp(vcpu
))
5570 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5571 apic_base_msr
.host_initiated
= true;
5572 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5575 vmx_segment_cache_clear(vmx
);
5577 seg_setup(VCPU_SREG_CS
);
5578 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5579 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5581 seg_setup(VCPU_SREG_DS
);
5582 seg_setup(VCPU_SREG_ES
);
5583 seg_setup(VCPU_SREG_FS
);
5584 seg_setup(VCPU_SREG_GS
);
5585 seg_setup(VCPU_SREG_SS
);
5587 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5588 vmcs_writel(GUEST_TR_BASE
, 0);
5589 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5590 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5592 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5593 vmcs_writel(GUEST_LDTR_BASE
, 0);
5594 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5595 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5598 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5599 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5600 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5601 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5604 kvm_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
5605 kvm_rip_write(vcpu
, 0xfff0);
5607 vmcs_writel(GUEST_GDTR_BASE
, 0);
5608 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5610 vmcs_writel(GUEST_IDTR_BASE
, 0);
5611 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5613 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5614 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5615 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5616 if (kvm_mpx_supported())
5617 vmcs_write64(GUEST_BNDCFGS
, 0);
5621 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5623 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5624 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5625 if (cpu_need_tpr_shadow(vcpu
))
5626 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5627 __pa(vcpu
->arch
.apic
->regs
));
5628 vmcs_write32(TPR_THRESHOLD
, 0);
5631 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5634 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5636 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5637 vmx
->vcpu
.arch
.cr0
= cr0
;
5638 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5639 vmx_set_cr4(vcpu
, 0);
5640 vmx_set_efer(vcpu
, 0);
5642 update_exception_bitmap(vcpu
);
5644 vpid_sync_context(vmx
->vpid
);
5648 * In nested virtualization, check if L1 asked to exit on external interrupts.
5649 * For most existing hypervisors, this will always return true.
5651 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5653 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5654 PIN_BASED_EXT_INTR_MASK
;
5658 * In nested virtualization, check if L1 has set
5659 * VM_EXIT_ACK_INTR_ON_EXIT
5661 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5663 return get_vmcs12(vcpu
)->vm_exit_controls
&
5664 VM_EXIT_ACK_INTR_ON_EXIT
;
5667 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5669 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5670 PIN_BASED_NMI_EXITING
;
5673 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5675 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5676 CPU_BASED_VIRTUAL_INTR_PENDING
);
5679 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5682 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5683 enable_irq_window(vcpu
);
5687 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5688 CPU_BASED_VIRTUAL_NMI_PENDING
);
5691 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5693 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5695 int irq
= vcpu
->arch
.interrupt
.nr
;
5697 trace_kvm_inj_virq(irq
);
5699 ++vcpu
->stat
.irq_injections
;
5700 if (vmx
->rmode
.vm86_active
) {
5702 if (vcpu
->arch
.interrupt
.soft
)
5703 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5704 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5705 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5708 intr
= irq
| INTR_INFO_VALID_MASK
;
5709 if (vcpu
->arch
.interrupt
.soft
) {
5710 intr
|= INTR_TYPE_SOFT_INTR
;
5711 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5712 vmx
->vcpu
.arch
.event_exit_inst_len
);
5714 intr
|= INTR_TYPE_EXT_INTR
;
5715 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5718 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5720 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5724 * Tracking the NMI-blocked state in software is built upon
5725 * finding the next open IRQ window. This, in turn, depends on
5726 * well-behaving guests: They have to keep IRQs disabled at
5727 * least as long as the NMI handler runs. Otherwise we may
5728 * cause NMI nesting, maybe breaking the guest. But as this is
5729 * highly unlikely, we can live with the residual risk.
5731 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 1;
5732 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5735 ++vcpu
->stat
.nmi_injections
;
5736 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5738 if (vmx
->rmode
.vm86_active
) {
5739 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5740 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5744 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5745 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5748 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5750 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5754 return vmx
->loaded_vmcs
->soft_vnmi_blocked
;
5755 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5757 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5758 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5762 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5764 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5767 if (vmx
->loaded_vmcs
->soft_vnmi_blocked
!= masked
) {
5768 vmx
->loaded_vmcs
->soft_vnmi_blocked
= masked
;
5769 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5772 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5774 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5775 GUEST_INTR_STATE_NMI
);
5777 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5778 GUEST_INTR_STATE_NMI
);
5782 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5784 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5788 to_vmx(vcpu
)->loaded_vmcs
->soft_vnmi_blocked
)
5791 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5792 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5793 | GUEST_INTR_STATE_NMI
));
5796 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5798 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5799 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5800 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5801 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5804 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5808 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5812 kvm
->arch
.tss_addr
= addr
;
5813 return init_rmode_tss(kvm
);
5816 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5821 * Update instruction length as we may reinject the exception
5822 * from user space while in guest debugging mode.
5824 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5825 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5826 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5830 if (vcpu
->guest_debug
&
5831 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5848 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5849 int vec
, u32 err_code
)
5852 * Instruction with address size override prefix opcode 0x67
5853 * Cause the #SS fault with 0 error code in VM86 mode.
5855 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5856 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5857 if (vcpu
->arch
.halt_request
) {
5858 vcpu
->arch
.halt_request
= 0;
5859 return kvm_vcpu_halt(vcpu
);
5867 * Forward all other exceptions that are valid in real mode.
5868 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5869 * the required debugging infrastructure rework.
5871 kvm_queue_exception(vcpu
, vec
);
5876 * Trigger machine check on the host. We assume all the MSRs are already set up
5877 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5878 * We pass a fake environment to the machine check handler because we want
5879 * the guest to be always treated like user space, no matter what context
5880 * it used internally.
5882 static void kvm_machine_check(void)
5884 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5885 struct pt_regs regs
= {
5886 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5887 .flags
= X86_EFLAGS_IF
,
5890 do_machine_check(®s
, 0);
5894 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5896 /* already handled by vcpu_run */
5900 static int handle_exception(struct kvm_vcpu
*vcpu
)
5902 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5903 struct kvm_run
*kvm_run
= vcpu
->run
;
5904 u32 intr_info
, ex_no
, error_code
;
5905 unsigned long cr2
, rip
, dr6
;
5907 enum emulation_result er
;
5909 vect_info
= vmx
->idt_vectoring_info
;
5910 intr_info
= vmx
->exit_intr_info
;
5912 if (is_machine_check(intr_info
))
5913 return handle_machine_check(vcpu
);
5915 if (is_nmi(intr_info
))
5916 return 1; /* already handled by vmx_vcpu_run() */
5918 if (is_invalid_opcode(intr_info
)) {
5919 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5920 if (er
== EMULATE_USER_EXIT
)
5922 if (er
!= EMULATE_DONE
)
5923 kvm_queue_exception(vcpu
, UD_VECTOR
);
5928 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5929 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5932 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5933 * MMIO, it is better to report an internal error.
5934 * See the comments in vmx_handle_exit.
5936 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5937 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5938 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5939 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5940 vcpu
->run
->internal
.ndata
= 3;
5941 vcpu
->run
->internal
.data
[0] = vect_info
;
5942 vcpu
->run
->internal
.data
[1] = intr_info
;
5943 vcpu
->run
->internal
.data
[2] = error_code
;
5947 if (is_page_fault(intr_info
)) {
5948 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5949 /* EPT won't cause page fault directly */
5950 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5951 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0);
5954 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5956 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5957 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5961 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5964 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5965 if (!(vcpu
->guest_debug
&
5966 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5967 vcpu
->arch
.dr6
&= ~15;
5968 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5969 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5970 skip_emulated_instruction(vcpu
);
5972 kvm_queue_exception(vcpu
, DB_VECTOR
);
5975 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5976 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5980 * Update instruction length as we may reinject #BP from
5981 * user space while in guest debugging mode. Reading it for
5982 * #DB as well causes no harm, it is not used in that case.
5984 vmx
->vcpu
.arch
.event_exit_inst_len
=
5985 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5986 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5987 rip
= kvm_rip_read(vcpu
);
5988 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5989 kvm_run
->debug
.arch
.exception
= ex_no
;
5992 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5993 kvm_run
->ex
.exception
= ex_no
;
5994 kvm_run
->ex
.error_code
= error_code
;
6000 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
6002 ++vcpu
->stat
.irq_exits
;
6006 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
6008 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
6009 vcpu
->mmio_needed
= 0;
6013 static int handle_io(struct kvm_vcpu
*vcpu
)
6015 unsigned long exit_qualification
;
6016 int size
, in
, string
, ret
;
6019 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6020 string
= (exit_qualification
& 16) != 0;
6021 in
= (exit_qualification
& 8) != 0;
6023 ++vcpu
->stat
.io_exits
;
6026 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6028 port
= exit_qualification
>> 16;
6029 size
= (exit_qualification
& 7) + 1;
6031 ret
= kvm_skip_emulated_instruction(vcpu
);
6034 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6035 * KVM_EXIT_DEBUG here.
6037 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
6041 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
6044 * Patch in the VMCALL instruction:
6046 hypercall
[0] = 0x0f;
6047 hypercall
[1] = 0x01;
6048 hypercall
[2] = 0xc1;
6051 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6052 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
6054 if (is_guest_mode(vcpu
)) {
6055 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6056 unsigned long orig_val
= val
;
6059 * We get here when L2 changed cr0 in a way that did not change
6060 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6061 * but did change L0 shadowed bits. So we first calculate the
6062 * effective cr0 value that L1 would like to write into the
6063 * hardware. It consists of the L2-owned bits from the new
6064 * value combined with the L1-owned bits from L1's guest_cr0.
6066 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
6067 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
6069 if (!nested_guest_cr0_valid(vcpu
, val
))
6072 if (kvm_set_cr0(vcpu
, val
))
6074 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
6077 if (to_vmx(vcpu
)->nested
.vmxon
&&
6078 !nested_host_cr0_valid(vcpu
, val
))
6081 return kvm_set_cr0(vcpu
, val
);
6085 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
6087 if (is_guest_mode(vcpu
)) {
6088 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6089 unsigned long orig_val
= val
;
6091 /* analogously to handle_set_cr0 */
6092 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
6093 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
6094 if (kvm_set_cr4(vcpu
, val
))
6096 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
6099 return kvm_set_cr4(vcpu
, val
);
6102 static int handle_cr(struct kvm_vcpu
*vcpu
)
6104 unsigned long exit_qualification
, val
;
6110 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6111 cr
= exit_qualification
& 15;
6112 reg
= (exit_qualification
>> 8) & 15;
6113 switch ((exit_qualification
>> 4) & 3) {
6114 case 0: /* mov to cr */
6115 val
= kvm_register_readl(vcpu
, reg
);
6116 trace_kvm_cr_write(cr
, val
);
6119 err
= handle_set_cr0(vcpu
, val
);
6120 return kvm_complete_insn_gp(vcpu
, err
);
6122 err
= kvm_set_cr3(vcpu
, val
);
6123 return kvm_complete_insn_gp(vcpu
, err
);
6125 err
= handle_set_cr4(vcpu
, val
);
6126 return kvm_complete_insn_gp(vcpu
, err
);
6128 u8 cr8_prev
= kvm_get_cr8(vcpu
);
6130 err
= kvm_set_cr8(vcpu
, cr8
);
6131 ret
= kvm_complete_insn_gp(vcpu
, err
);
6132 if (lapic_in_kernel(vcpu
))
6134 if (cr8_prev
<= cr8
)
6137 * TODO: we might be squashing a
6138 * KVM_GUESTDBG_SINGLESTEP-triggered
6139 * KVM_EXIT_DEBUG here.
6141 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6147 WARN_ONCE(1, "Guest should always own CR0.TS");
6148 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6149 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6150 return kvm_skip_emulated_instruction(vcpu
);
6151 case 1: /*mov from cr*/
6154 val
= kvm_read_cr3(vcpu
);
6155 kvm_register_write(vcpu
, reg
, val
);
6156 trace_kvm_cr_read(cr
, val
);
6157 return kvm_skip_emulated_instruction(vcpu
);
6159 val
= kvm_get_cr8(vcpu
);
6160 kvm_register_write(vcpu
, reg
, val
);
6161 trace_kvm_cr_read(cr
, val
);
6162 return kvm_skip_emulated_instruction(vcpu
);
6166 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6167 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6168 kvm_lmsw(vcpu
, val
);
6170 return kvm_skip_emulated_instruction(vcpu
);
6174 vcpu
->run
->exit_reason
= 0;
6175 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6176 (int)(exit_qualification
>> 4) & 3, cr
);
6180 static int handle_dr(struct kvm_vcpu
*vcpu
)
6182 unsigned long exit_qualification
;
6185 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6186 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6188 /* First, if DR does not exist, trigger UD */
6189 if (!kvm_require_dr(vcpu
, dr
))
6192 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6193 if (!kvm_require_cpl(vcpu
, 0))
6195 dr7
= vmcs_readl(GUEST_DR7
);
6198 * As the vm-exit takes precedence over the debug trap, we
6199 * need to emulate the latter, either for the host or the
6200 * guest debugging itself.
6202 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6203 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6204 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6205 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6206 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6207 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6210 vcpu
->arch
.dr6
&= ~15;
6211 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6212 kvm_queue_exception(vcpu
, DB_VECTOR
);
6217 if (vcpu
->guest_debug
== 0) {
6218 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6219 CPU_BASED_MOV_DR_EXITING
);
6222 * No more DR vmexits; force a reload of the debug registers
6223 * and reenter on this instruction. The next vmexit will
6224 * retrieve the full state of the debug registers.
6226 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6230 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6231 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6234 if (kvm_get_dr(vcpu
, dr
, &val
))
6236 kvm_register_write(vcpu
, reg
, val
);
6238 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6241 return kvm_skip_emulated_instruction(vcpu
);
6244 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6246 return vcpu
->arch
.dr6
;
6249 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6253 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6255 get_debugreg(vcpu
->arch
.db
[0], 0);
6256 get_debugreg(vcpu
->arch
.db
[1], 1);
6257 get_debugreg(vcpu
->arch
.db
[2], 2);
6258 get_debugreg(vcpu
->arch
.db
[3], 3);
6259 get_debugreg(vcpu
->arch
.dr6
, 6);
6260 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6262 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6263 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6266 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6268 vmcs_writel(GUEST_DR7
, val
);
6271 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6273 return kvm_emulate_cpuid(vcpu
);
6276 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6278 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6279 struct msr_data msr_info
;
6281 msr_info
.index
= ecx
;
6282 msr_info
.host_initiated
= false;
6283 if (vmx_get_msr(vcpu
, &msr_info
)) {
6284 trace_kvm_msr_read_ex(ecx
);
6285 kvm_inject_gp(vcpu
, 0);
6289 trace_kvm_msr_read(ecx
, msr_info
.data
);
6291 /* FIXME: handling of bits 32:63 of rax, rdx */
6292 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6293 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6294 return kvm_skip_emulated_instruction(vcpu
);
6297 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6299 struct msr_data msr
;
6300 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6301 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6302 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6306 msr
.host_initiated
= false;
6307 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6308 trace_kvm_msr_write_ex(ecx
, data
);
6309 kvm_inject_gp(vcpu
, 0);
6313 trace_kvm_msr_write(ecx
, data
);
6314 return kvm_skip_emulated_instruction(vcpu
);
6317 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6319 kvm_apic_update_ppr(vcpu
);
6323 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6325 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6326 CPU_BASED_VIRTUAL_INTR_PENDING
);
6328 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6330 ++vcpu
->stat
.irq_window_exits
;
6334 static int handle_halt(struct kvm_vcpu
*vcpu
)
6336 return kvm_emulate_halt(vcpu
);
6339 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6341 return kvm_emulate_hypercall(vcpu
);
6344 static int handle_invd(struct kvm_vcpu
*vcpu
)
6346 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6349 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6351 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6353 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6354 return kvm_skip_emulated_instruction(vcpu
);
6357 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6361 err
= kvm_rdpmc(vcpu
);
6362 return kvm_complete_insn_gp(vcpu
, err
);
6365 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6367 return kvm_emulate_wbinvd(vcpu
);
6370 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6372 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6373 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6375 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6376 return kvm_skip_emulated_instruction(vcpu
);
6380 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6382 kvm_skip_emulated_instruction(vcpu
);
6383 WARN(1, "this should never happen\n");
6387 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6389 kvm_skip_emulated_instruction(vcpu
);
6390 WARN(1, "this should never happen\n");
6394 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6396 if (likely(fasteoi
)) {
6397 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6398 int access_type
, offset
;
6400 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6401 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6403 * Sane guest uses MOV to write EOI, with written value
6404 * not cared. So make a short-circuit here by avoiding
6405 * heavy instruction emulation.
6407 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6408 (offset
== APIC_EOI
)) {
6409 kvm_lapic_set_eoi(vcpu
);
6410 return kvm_skip_emulated_instruction(vcpu
);
6413 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6416 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6418 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6419 int vector
= exit_qualification
& 0xff;
6421 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6422 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6426 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6428 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6429 u32 offset
= exit_qualification
& 0xfff;
6431 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6432 kvm_apic_write_nodecode(vcpu
, offset
);
6436 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6438 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6439 unsigned long exit_qualification
;
6440 bool has_error_code
= false;
6443 int reason
, type
, idt_v
, idt_index
;
6445 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6446 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6447 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6449 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6451 reason
= (u32
)exit_qualification
>> 30;
6452 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6454 case INTR_TYPE_NMI_INTR
:
6455 vcpu
->arch
.nmi_injected
= false;
6456 vmx_set_nmi_mask(vcpu
, true);
6458 case INTR_TYPE_EXT_INTR
:
6459 case INTR_TYPE_SOFT_INTR
:
6460 kvm_clear_interrupt_queue(vcpu
);
6462 case INTR_TYPE_HARD_EXCEPTION
:
6463 if (vmx
->idt_vectoring_info
&
6464 VECTORING_INFO_DELIVER_CODE_MASK
) {
6465 has_error_code
= true;
6467 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6470 case INTR_TYPE_SOFT_EXCEPTION
:
6471 kvm_clear_exception_queue(vcpu
);
6477 tss_selector
= exit_qualification
;
6479 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6480 type
!= INTR_TYPE_EXT_INTR
&&
6481 type
!= INTR_TYPE_NMI_INTR
))
6482 skip_emulated_instruction(vcpu
);
6484 if (kvm_task_switch(vcpu
, tss_selector
,
6485 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6486 has_error_code
, error_code
) == EMULATE_FAIL
) {
6487 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6488 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6489 vcpu
->run
->internal
.ndata
= 0;
6494 * TODO: What about debug traps on tss switch?
6495 * Are we supposed to inject them and update dr6?
6501 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6503 unsigned long exit_qualification
;
6507 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6510 * EPT violation happened while executing iret from NMI,
6511 * "blocked by NMI" bit has to be set before next VM entry.
6512 * There are errata that may cause this bit to not be set:
6515 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6517 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6518 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6520 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6521 trace_kvm_page_fault(gpa
, exit_qualification
);
6523 /* Is it a read fault? */
6524 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6525 ? PFERR_USER_MASK
: 0;
6526 /* Is it a write fault? */
6527 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6528 ? PFERR_WRITE_MASK
: 0;
6529 /* Is it a fetch fault? */
6530 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6531 ? PFERR_FETCH_MASK
: 0;
6532 /* ept page table entry is present? */
6533 error_code
|= (exit_qualification
&
6534 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6535 EPT_VIOLATION_EXECUTABLE
))
6536 ? PFERR_PRESENT_MASK
: 0;
6538 error_code
|= (exit_qualification
& 0x100) != 0 ?
6539 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6541 vcpu
->arch
.exit_qualification
= exit_qualification
;
6542 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6545 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6551 * A nested guest cannot optimize MMIO vmexits, because we have an
6552 * nGPA here instead of the required GPA.
6554 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6555 if (!is_guest_mode(vcpu
) &&
6556 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6557 trace_kvm_fast_mmio(gpa
);
6558 return kvm_skip_emulated_instruction(vcpu
);
6561 ret
= kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
6565 /* It is the real ept misconfig */
6568 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6569 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6574 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6576 WARN_ON_ONCE(!enable_vnmi
);
6577 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6578 CPU_BASED_VIRTUAL_NMI_PENDING
);
6579 ++vcpu
->stat
.nmi_window_exits
;
6580 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6585 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6587 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6588 enum emulation_result err
= EMULATE_DONE
;
6591 bool intr_window_requested
;
6592 unsigned count
= 130;
6594 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6595 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6597 while (vmx
->emulation_required
&& count
-- != 0) {
6598 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6599 return handle_interrupt_window(&vmx
->vcpu
);
6601 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6604 err
= emulate_instruction(vcpu
, 0);
6606 if (err
== EMULATE_USER_EXIT
) {
6607 ++vcpu
->stat
.mmio_exits
;
6612 if (err
!= EMULATE_DONE
) {
6613 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6614 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6615 vcpu
->run
->internal
.ndata
= 0;
6619 if (vcpu
->arch
.halt_request
) {
6620 vcpu
->arch
.halt_request
= 0;
6621 ret
= kvm_vcpu_halt(vcpu
);
6625 if (signal_pending(current
))
6635 static int __grow_ple_window(int val
)
6637 if (ple_window_grow
< 1)
6640 val
= min(val
, ple_window_actual_max
);
6642 if (ple_window_grow
< ple_window
)
6643 val
*= ple_window_grow
;
6645 val
+= ple_window_grow
;
6650 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6655 if (modifier
< ple_window
)
6660 return max(val
, minimum
);
6663 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6665 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6666 int old
= vmx
->ple_window
;
6668 vmx
->ple_window
= __grow_ple_window(old
);
6670 if (vmx
->ple_window
!= old
)
6671 vmx
->ple_window_dirty
= true;
6673 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6676 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6678 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6679 int old
= vmx
->ple_window
;
6681 vmx
->ple_window
= __shrink_ple_window(old
,
6682 ple_window_shrink
, ple_window
);
6684 if (vmx
->ple_window
!= old
)
6685 vmx
->ple_window_dirty
= true;
6687 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6691 * ple_window_actual_max is computed to be one grow_ple_window() below
6692 * ple_window_max. (See __grow_ple_window for the reason.)
6693 * This prevents overflows, because ple_window_max is int.
6694 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6696 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6698 static void update_ple_window_actual_max(void)
6700 ple_window_actual_max
=
6701 __shrink_ple_window(max(ple_window_max
, ple_window
),
6702 ple_window_grow
, INT_MIN
);
6706 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6708 static void wakeup_handler(void)
6710 struct kvm_vcpu
*vcpu
;
6711 int cpu
= smp_processor_id();
6713 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6714 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6715 blocked_vcpu_list
) {
6716 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6718 if (pi_test_on(pi_desc
) == 1)
6719 kvm_vcpu_kick(vcpu
);
6721 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6724 void vmx_enable_tdp(void)
6726 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6727 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6728 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6729 0ull, VMX_EPT_EXECUTABLE_MASK
,
6730 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6731 VMX_EPT_RWX_MASK
, 0ull);
6733 ept_set_mmio_spte_mask();
6737 static __init
int hardware_setup(void)
6739 int r
= -ENOMEM
, i
, msr
;
6741 rdmsrl_safe(MSR_EFER
, &host_efer
);
6743 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6744 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6746 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6747 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6752 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6753 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6755 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6757 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6759 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6760 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6762 if (setup_vmcs_config(&vmcs_config
) < 0) {
6767 if (boot_cpu_has(X86_FEATURE_NX
))
6768 kvm_enable_efer_bits(EFER_NX
);
6770 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6771 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6774 if (!cpu_has_vmx_shadow_vmcs())
6775 enable_shadow_vmcs
= 0;
6776 if (enable_shadow_vmcs
)
6777 init_vmcs_shadow_fields();
6779 if (!cpu_has_vmx_ept() ||
6780 !cpu_has_vmx_ept_4levels() ||
6781 !cpu_has_vmx_ept_mt_wb() ||
6782 !cpu_has_vmx_invept_global())
6785 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6786 enable_ept_ad_bits
= 0;
6788 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept
)
6789 enable_unrestricted_guest
= 0;
6791 if (!cpu_has_vmx_flexpriority())
6792 flexpriority_enabled
= 0;
6794 if (!cpu_has_virtual_nmis())
6798 * set_apic_access_page_addr() is used to reload apic access
6799 * page upon invalidation. No need to do anything if not
6800 * using the APIC_ACCESS_ADDR VMCS field.
6802 if (!flexpriority_enabled
)
6803 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6805 if (!cpu_has_vmx_tpr_shadow())
6806 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6808 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6809 kvm_disable_largepages();
6811 if (!cpu_has_vmx_ple()) {
6814 ple_window_grow
= 0;
6816 ple_window_shrink
= 0;
6819 if (!cpu_has_vmx_apicv()) {
6821 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6824 if (cpu_has_vmx_tsc_scaling()) {
6825 kvm_has_tsc_control
= true;
6826 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6827 kvm_tsc_scaling_ratio_frac_bits
= 48;
6830 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6831 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6832 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6833 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6834 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6835 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6837 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6838 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6839 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6840 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6841 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6842 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6843 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6844 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6846 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6848 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6849 if (msr
== 0x839 /* TMCCT */)
6851 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6855 * TPR reads and writes can be virtualized even if virtual interrupt
6856 * delivery is not in use.
6858 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6859 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6862 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6864 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6871 update_ple_window_actual_max();
6874 * Only enable PML when hardware supports PML feature, and both EPT
6875 * and EPT A/D bit features are enabled -- PML depends on them to work.
6877 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6881 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6882 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6883 kvm_x86_ops
->flush_log_dirty
= NULL
;
6884 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6887 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6890 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6891 cpu_preemption_timer_multi
=
6892 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6894 kvm_x86_ops
->set_hv_timer
= NULL
;
6895 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6898 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6900 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6902 return alloc_kvm_area();
6905 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6906 free_page((unsigned long)vmx_bitmap
[i
]);
6911 static __exit
void hardware_unsetup(void)
6915 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6916 free_page((unsigned long)vmx_bitmap
[i
]);
6922 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6923 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6925 static int handle_pause(struct kvm_vcpu
*vcpu
)
6928 grow_ple_window(vcpu
);
6931 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6932 * VM-execution control is ignored if CPL > 0. OTOH, KVM
6933 * never set PAUSE_EXITING and just set PLE if supported,
6934 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6936 kvm_vcpu_on_spin(vcpu
, true);
6937 return kvm_skip_emulated_instruction(vcpu
);
6940 static int handle_nop(struct kvm_vcpu
*vcpu
)
6942 return kvm_skip_emulated_instruction(vcpu
);
6945 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6947 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6948 return handle_nop(vcpu
);
6951 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
6953 kvm_queue_exception(vcpu
, UD_VECTOR
);
6957 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6962 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6964 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6965 return handle_nop(vcpu
);
6969 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6970 * set the success or error code of an emulated VMX instruction, as specified
6971 * by Vol 2B, VMX Instruction Reference, "Conventions".
6973 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6975 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6976 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6977 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6980 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6982 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6983 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6984 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6988 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6989 u32 vm_instruction_error
)
6991 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6993 * failValid writes the error number to the current VMCS, which
6994 * can't be done there isn't a current VMCS.
6996 nested_vmx_failInvalid(vcpu
);
6999 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7000 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7001 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7003 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
7005 * We don't need to force a shadow sync because
7006 * VM_INSTRUCTION_ERROR is not shadowed
7010 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
7012 /* TODO: not to reset guest simply here. */
7013 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7014 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
7017 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
7019 struct vcpu_vmx
*vmx
=
7020 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
7022 vmx
->nested
.preemption_timer_expired
= true;
7023 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
7024 kvm_vcpu_kick(&vmx
->vcpu
);
7026 return HRTIMER_NORESTART
;
7030 * Decode the memory-address operand of a vmx instruction, as recorded on an
7031 * exit caused by such an instruction (run by a guest hypervisor).
7032 * On success, returns 0. When the operand is invalid, returns 1 and throws
7035 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
7036 unsigned long exit_qualification
,
7037 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
7041 struct kvm_segment s
;
7044 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7045 * Execution", on an exit, vmx_instruction_info holds most of the
7046 * addressing components of the operand. Only the displacement part
7047 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7048 * For how an actual address is calculated from all these components,
7049 * refer to Vol. 1, "Operand Addressing".
7051 int scaling
= vmx_instruction_info
& 3;
7052 int addr_size
= (vmx_instruction_info
>> 7) & 7;
7053 bool is_reg
= vmx_instruction_info
& (1u << 10);
7054 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
7055 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
7056 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
7057 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
7058 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7061 kvm_queue_exception(vcpu
, UD_VECTOR
);
7065 /* Addr = segment_base + offset */
7066 /* offset = base + [index * scale] + displacement */
7067 off
= exit_qualification
; /* holds the displacement */
7069 off
+= kvm_register_read(vcpu
, base_reg
);
7071 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7072 vmx_get_segment(vcpu
, &s
, seg_reg
);
7073 *ret
= s
.base
+ off
;
7075 if (addr_size
== 1) /* 32 bit */
7078 /* Checks for #GP/#SS exceptions. */
7080 if (is_long_mode(vcpu
)) {
7081 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7082 * non-canonical form. This is the only check on the memory
7083 * destination for long mode!
7085 exn
= is_noncanonical_address(*ret
, vcpu
);
7086 } else if (is_protmode(vcpu
)) {
7087 /* Protected mode: apply checks for segment validity in the
7089 * - segment type check (#GP(0) may be thrown)
7090 * - usability check (#GP(0)/#SS(0))
7091 * - limit check (#GP(0)/#SS(0))
7094 /* #GP(0) if the destination operand is located in a
7095 * read-only data segment or any code segment.
7097 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7099 /* #GP(0) if the source operand is located in an
7100 * execute-only code segment
7102 exn
= ((s
.type
& 0xa) == 8);
7104 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7107 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7109 exn
= (s
.unusable
!= 0);
7110 /* Protected mode: #GP(0)/#SS(0) if the memory
7111 * operand is outside the segment limit.
7113 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7116 kvm_queue_exception_e(vcpu
,
7117 seg_reg
== VCPU_SREG_SS
?
7118 SS_VECTOR
: GP_VECTOR
,
7126 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7129 struct x86_exception e
;
7131 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7132 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7135 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7136 sizeof(*vmpointer
), &e
)) {
7137 kvm_inject_page_fault(vcpu
, &e
);
7144 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7146 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7147 struct vmcs
*shadow_vmcs
;
7149 vmx
->nested
.vmcs02
.vmcs
= alloc_vmcs();
7150 vmx
->nested
.vmcs02
.shadow_vmcs
= NULL
;
7151 if (!vmx
->nested
.vmcs02
.vmcs
)
7153 loaded_vmcs_init(&vmx
->nested
.vmcs02
);
7155 if (cpu_has_vmx_msr_bitmap()) {
7156 vmx
->nested
.msr_bitmap
=
7157 (unsigned long *)__get_free_page(GFP_KERNEL
);
7158 if (!vmx
->nested
.msr_bitmap
)
7159 goto out_msr_bitmap
;
7162 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7163 if (!vmx
->nested
.cached_vmcs12
)
7164 goto out_cached_vmcs12
;
7166 if (enable_shadow_vmcs
) {
7167 shadow_vmcs
= alloc_vmcs();
7169 goto out_shadow_vmcs
;
7170 /* mark vmcs as shadow */
7171 shadow_vmcs
->revision_id
|= (1u << 31);
7172 /* init shadow vmcs */
7173 vmcs_clear(shadow_vmcs
);
7174 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7177 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7178 HRTIMER_MODE_REL_PINNED
);
7179 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7181 vmx
->nested
.vmxon
= true;
7185 kfree(vmx
->nested
.cached_vmcs12
);
7188 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7191 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
7198 * Emulate the VMXON instruction.
7199 * Currently, we just remember that VMX is active, and do not save or even
7200 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7201 * do not currently need to store anything in that guest-allocated memory
7202 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7203 * argument is different from the VMXON pointer (which the spec says they do).
7205 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7210 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7211 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7212 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7215 * The Intel VMX Instruction Reference lists a bunch of bits that are
7216 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7217 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7218 * Otherwise, we should fail with #UD. But most faulting conditions
7219 * have already been checked by hardware, prior to the VM-exit for
7220 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7221 * that bit set to 1 in non-root mode.
7223 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7224 kvm_queue_exception(vcpu
, UD_VECTOR
);
7228 if (vmx
->nested
.vmxon
) {
7229 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7230 return kvm_skip_emulated_instruction(vcpu
);
7233 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7234 != VMXON_NEEDED_FEATURES
) {
7235 kvm_inject_gp(vcpu
, 0);
7239 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7244 * The first 4 bytes of VMXON region contain the supported
7245 * VMCS revision identifier
7247 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7248 * which replaces physical address width with 32
7250 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7251 nested_vmx_failInvalid(vcpu
);
7252 return kvm_skip_emulated_instruction(vcpu
);
7255 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7256 if (is_error_page(page
)) {
7257 nested_vmx_failInvalid(vcpu
);
7258 return kvm_skip_emulated_instruction(vcpu
);
7260 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7262 kvm_release_page_clean(page
);
7263 nested_vmx_failInvalid(vcpu
);
7264 return kvm_skip_emulated_instruction(vcpu
);
7267 kvm_release_page_clean(page
);
7269 vmx
->nested
.vmxon_ptr
= vmptr
;
7270 ret
= enter_vmx_operation(vcpu
);
7274 nested_vmx_succeed(vcpu
);
7275 return kvm_skip_emulated_instruction(vcpu
);
7279 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7280 * for running VMX instructions (except VMXON, whose prerequisites are
7281 * slightly different). It also specifies what exception to inject otherwise.
7282 * Note that many of these exceptions have priority over VM exits, so they
7283 * don't have to be checked again here.
7285 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7287 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7288 kvm_queue_exception(vcpu
, UD_VECTOR
);
7294 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7296 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7297 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7300 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7302 if (vmx
->nested
.current_vmptr
== -1ull)
7305 if (enable_shadow_vmcs
) {
7306 /* copy to memory all shadowed fields in case
7307 they were modified */
7308 copy_shadow_to_vmcs12(vmx
);
7309 vmx
->nested
.sync_shadow_vmcs
= false;
7310 vmx_disable_shadow_vmcs(vmx
);
7312 vmx
->nested
.posted_intr_nv
= -1;
7314 /* Flush VMCS12 to guest memory */
7315 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7316 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7317 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7319 vmx
->nested
.current_vmptr
= -1ull;
7323 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7324 * just stops using VMX.
7326 static void free_nested(struct vcpu_vmx
*vmx
)
7328 if (!vmx
->nested
.vmxon
&& !vmx
->nested
.smm
.vmxon
)
7331 vmx
->nested
.vmxon
= false;
7332 vmx
->nested
.smm
.vmxon
= false;
7333 free_vpid(vmx
->nested
.vpid02
);
7334 vmx
->nested
.posted_intr_nv
= -1;
7335 vmx
->nested
.current_vmptr
= -1ull;
7336 if (vmx
->nested
.msr_bitmap
) {
7337 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7338 vmx
->nested
.msr_bitmap
= NULL
;
7340 if (enable_shadow_vmcs
) {
7341 vmx_disable_shadow_vmcs(vmx
);
7342 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7343 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7344 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7346 kfree(vmx
->nested
.cached_vmcs12
);
7347 /* Unpin physical memory we referred to in the vmcs02 */
7348 if (vmx
->nested
.apic_access_page
) {
7349 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7350 vmx
->nested
.apic_access_page
= NULL
;
7352 if (vmx
->nested
.virtual_apic_page
) {
7353 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7354 vmx
->nested
.virtual_apic_page
= NULL
;
7356 if (vmx
->nested
.pi_desc_page
) {
7357 kunmap(vmx
->nested
.pi_desc_page
);
7358 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7359 vmx
->nested
.pi_desc_page
= NULL
;
7360 vmx
->nested
.pi_desc
= NULL
;
7363 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
7366 /* Emulate the VMXOFF instruction */
7367 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7369 if (!nested_vmx_check_permission(vcpu
))
7371 free_nested(to_vmx(vcpu
));
7372 nested_vmx_succeed(vcpu
);
7373 return kvm_skip_emulated_instruction(vcpu
);
7376 /* Emulate the VMCLEAR instruction */
7377 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7379 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7383 if (!nested_vmx_check_permission(vcpu
))
7386 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7389 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7390 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7391 return kvm_skip_emulated_instruction(vcpu
);
7394 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7395 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7396 return kvm_skip_emulated_instruction(vcpu
);
7399 if (vmptr
== vmx
->nested
.current_vmptr
)
7400 nested_release_vmcs12(vmx
);
7402 kvm_vcpu_write_guest(vcpu
,
7403 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7404 &zero
, sizeof(zero
));
7406 nested_vmx_succeed(vcpu
);
7407 return kvm_skip_emulated_instruction(vcpu
);
7410 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7412 /* Emulate the VMLAUNCH instruction */
7413 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7415 return nested_vmx_run(vcpu
, true);
7418 /* Emulate the VMRESUME instruction */
7419 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7422 return nested_vmx_run(vcpu
, false);
7426 * Read a vmcs12 field. Since these can have varying lengths and we return
7427 * one type, we chose the biggest type (u64) and zero-extend the return value
7428 * to that size. Note that the caller, handle_vmread, might need to use only
7429 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7430 * 64-bit fields are to be returned).
7432 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7433 unsigned long field
, u64
*ret
)
7435 short offset
= vmcs_field_to_offset(field
);
7441 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7443 switch (vmcs_field_type(field
)) {
7444 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7445 *ret
= *((natural_width
*)p
);
7447 case VMCS_FIELD_TYPE_U16
:
7450 case VMCS_FIELD_TYPE_U32
:
7453 case VMCS_FIELD_TYPE_U64
:
7463 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7464 unsigned long field
, u64 field_value
){
7465 short offset
= vmcs_field_to_offset(field
);
7466 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7470 switch (vmcs_field_type(field
)) {
7471 case VMCS_FIELD_TYPE_U16
:
7472 *(u16
*)p
= field_value
;
7474 case VMCS_FIELD_TYPE_U32
:
7475 *(u32
*)p
= field_value
;
7477 case VMCS_FIELD_TYPE_U64
:
7478 *(u64
*)p
= field_value
;
7480 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7481 *(natural_width
*)p
= field_value
;
7490 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7493 unsigned long field
;
7495 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7496 const unsigned long *fields
= shadow_read_write_fields
;
7497 const int num_fields
= max_shadow_read_write_fields
;
7501 vmcs_load(shadow_vmcs
);
7503 for (i
= 0; i
< num_fields
; i
++) {
7505 switch (vmcs_field_type(field
)) {
7506 case VMCS_FIELD_TYPE_U16
:
7507 field_value
= vmcs_read16(field
);
7509 case VMCS_FIELD_TYPE_U32
:
7510 field_value
= vmcs_read32(field
);
7512 case VMCS_FIELD_TYPE_U64
:
7513 field_value
= vmcs_read64(field
);
7515 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7516 field_value
= vmcs_readl(field
);
7522 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7525 vmcs_clear(shadow_vmcs
);
7526 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7531 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7533 const unsigned long *fields
[] = {
7534 shadow_read_write_fields
,
7535 shadow_read_only_fields
7537 const int max_fields
[] = {
7538 max_shadow_read_write_fields
,
7539 max_shadow_read_only_fields
7542 unsigned long field
;
7543 u64 field_value
= 0;
7544 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7546 vmcs_load(shadow_vmcs
);
7548 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7549 for (i
= 0; i
< max_fields
[q
]; i
++) {
7550 field
= fields
[q
][i
];
7551 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7553 switch (vmcs_field_type(field
)) {
7554 case VMCS_FIELD_TYPE_U16
:
7555 vmcs_write16(field
, (u16
)field_value
);
7557 case VMCS_FIELD_TYPE_U32
:
7558 vmcs_write32(field
, (u32
)field_value
);
7560 case VMCS_FIELD_TYPE_U64
:
7561 vmcs_write64(field
, (u64
)field_value
);
7563 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7564 vmcs_writel(field
, (long)field_value
);
7573 vmcs_clear(shadow_vmcs
);
7574 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7578 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7579 * used before) all generate the same failure when it is missing.
7581 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7583 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7584 if (vmx
->nested
.current_vmptr
== -1ull) {
7585 nested_vmx_failInvalid(vcpu
);
7591 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7593 unsigned long field
;
7595 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7596 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7599 if (!nested_vmx_check_permission(vcpu
))
7602 if (!nested_vmx_check_vmcs12(vcpu
))
7603 return kvm_skip_emulated_instruction(vcpu
);
7605 /* Decode instruction info and find the field to read */
7606 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7607 /* Read the field, zero-extended to a u64 field_value */
7608 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7609 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7610 return kvm_skip_emulated_instruction(vcpu
);
7613 * Now copy part of this value to register or memory, as requested.
7614 * Note that the number of bits actually copied is 32 or 64 depending
7615 * on the guest's mode (32 or 64 bit), not on the given field's length.
7617 if (vmx_instruction_info
& (1u << 10)) {
7618 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7621 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7622 vmx_instruction_info
, true, &gva
))
7624 /* _system ok, as hardware has verified cpl=0 */
7625 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7626 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7629 nested_vmx_succeed(vcpu
);
7630 return kvm_skip_emulated_instruction(vcpu
);
7634 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7636 unsigned long field
;
7638 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7639 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7640 /* The value to write might be 32 or 64 bits, depending on L1's long
7641 * mode, and eventually we need to write that into a field of several
7642 * possible lengths. The code below first zero-extends the value to 64
7643 * bit (field_value), and then copies only the appropriate number of
7644 * bits into the vmcs12 field.
7646 u64 field_value
= 0;
7647 struct x86_exception e
;
7649 if (!nested_vmx_check_permission(vcpu
))
7652 if (!nested_vmx_check_vmcs12(vcpu
))
7653 return kvm_skip_emulated_instruction(vcpu
);
7655 if (vmx_instruction_info
& (1u << 10))
7656 field_value
= kvm_register_readl(vcpu
,
7657 (((vmx_instruction_info
) >> 3) & 0xf));
7659 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7660 vmx_instruction_info
, false, &gva
))
7662 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7663 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7664 kvm_inject_page_fault(vcpu
, &e
);
7670 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7671 if (vmcs_field_readonly(field
)) {
7672 nested_vmx_failValid(vcpu
,
7673 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7674 return kvm_skip_emulated_instruction(vcpu
);
7677 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7678 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7679 return kvm_skip_emulated_instruction(vcpu
);
7682 nested_vmx_succeed(vcpu
);
7683 return kvm_skip_emulated_instruction(vcpu
);
7686 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7688 vmx
->nested
.current_vmptr
= vmptr
;
7689 if (enable_shadow_vmcs
) {
7690 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7691 SECONDARY_EXEC_SHADOW_VMCS
);
7692 vmcs_write64(VMCS_LINK_POINTER
,
7693 __pa(vmx
->vmcs01
.shadow_vmcs
));
7694 vmx
->nested
.sync_shadow_vmcs
= true;
7698 /* Emulate the VMPTRLD instruction */
7699 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7701 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7704 if (!nested_vmx_check_permission(vcpu
))
7707 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7710 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7711 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7712 return kvm_skip_emulated_instruction(vcpu
);
7715 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7716 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7717 return kvm_skip_emulated_instruction(vcpu
);
7720 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7721 struct vmcs12
*new_vmcs12
;
7723 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7724 if (is_error_page(page
)) {
7725 nested_vmx_failInvalid(vcpu
);
7726 return kvm_skip_emulated_instruction(vcpu
);
7728 new_vmcs12
= kmap(page
);
7729 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7731 kvm_release_page_clean(page
);
7732 nested_vmx_failValid(vcpu
,
7733 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7734 return kvm_skip_emulated_instruction(vcpu
);
7737 nested_release_vmcs12(vmx
);
7739 * Load VMCS12 from guest memory since it is not already
7742 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7744 kvm_release_page_clean(page
);
7746 set_current_vmptr(vmx
, vmptr
);
7749 nested_vmx_succeed(vcpu
);
7750 return kvm_skip_emulated_instruction(vcpu
);
7753 /* Emulate the VMPTRST instruction */
7754 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7756 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7757 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7759 struct x86_exception e
;
7761 if (!nested_vmx_check_permission(vcpu
))
7764 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7765 vmx_instruction_info
, true, &vmcs_gva
))
7767 /* ok to use *_system, as hardware has verified cpl=0 */
7768 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7769 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7771 kvm_inject_page_fault(vcpu
, &e
);
7774 nested_vmx_succeed(vcpu
);
7775 return kvm_skip_emulated_instruction(vcpu
);
7778 /* Emulate the INVEPT instruction */
7779 static int handle_invept(struct kvm_vcpu
*vcpu
)
7781 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7782 u32 vmx_instruction_info
, types
;
7785 struct x86_exception e
;
7790 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7791 SECONDARY_EXEC_ENABLE_EPT
) ||
7792 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7793 kvm_queue_exception(vcpu
, UD_VECTOR
);
7797 if (!nested_vmx_check_permission(vcpu
))
7800 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7801 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7803 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7805 if (type
>= 32 || !(types
& (1 << type
))) {
7806 nested_vmx_failValid(vcpu
,
7807 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7808 return kvm_skip_emulated_instruction(vcpu
);
7811 /* According to the Intel VMX instruction reference, the memory
7812 * operand is read even if it isn't needed (e.g., for type==global)
7814 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7815 vmx_instruction_info
, false, &gva
))
7817 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7818 sizeof(operand
), &e
)) {
7819 kvm_inject_page_fault(vcpu
, &e
);
7824 case VMX_EPT_EXTENT_GLOBAL
:
7826 * TODO: track mappings and invalidate
7827 * single context requests appropriately
7829 case VMX_EPT_EXTENT_CONTEXT
:
7830 kvm_mmu_sync_roots(vcpu
);
7831 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7832 nested_vmx_succeed(vcpu
);
7839 return kvm_skip_emulated_instruction(vcpu
);
7842 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7844 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7845 u32 vmx_instruction_info
;
7846 unsigned long type
, types
;
7848 struct x86_exception e
;
7854 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7855 SECONDARY_EXEC_ENABLE_VPID
) ||
7856 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7857 kvm_queue_exception(vcpu
, UD_VECTOR
);
7861 if (!nested_vmx_check_permission(vcpu
))
7864 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7865 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7867 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7868 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7870 if (type
>= 32 || !(types
& (1 << type
))) {
7871 nested_vmx_failValid(vcpu
,
7872 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7873 return kvm_skip_emulated_instruction(vcpu
);
7876 /* according to the intel vmx instruction reference, the memory
7877 * operand is read even if it isn't needed (e.g., for type==global)
7879 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7880 vmx_instruction_info
, false, &gva
))
7882 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7883 sizeof(operand
), &e
)) {
7884 kvm_inject_page_fault(vcpu
, &e
);
7887 if (operand
.vpid
>> 16) {
7888 nested_vmx_failValid(vcpu
,
7889 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7890 return kvm_skip_emulated_instruction(vcpu
);
7894 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7895 if (is_noncanonical_address(operand
.gla
, vcpu
)) {
7896 nested_vmx_failValid(vcpu
,
7897 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7898 return kvm_skip_emulated_instruction(vcpu
);
7901 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7902 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7903 if (!operand
.vpid
) {
7904 nested_vmx_failValid(vcpu
,
7905 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7906 return kvm_skip_emulated_instruction(vcpu
);
7909 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7913 return kvm_skip_emulated_instruction(vcpu
);
7916 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7917 nested_vmx_succeed(vcpu
);
7919 return kvm_skip_emulated_instruction(vcpu
);
7922 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7924 unsigned long exit_qualification
;
7926 trace_kvm_pml_full(vcpu
->vcpu_id
);
7928 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7931 * PML buffer FULL happened while executing iret from NMI,
7932 * "blocked by NMI" bit has to be set before next VM entry.
7934 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7936 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7937 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7938 GUEST_INTR_STATE_NMI
);
7941 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7942 * here.., and there's no userspace involvement needed for PML.
7947 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7949 kvm_lapic_expired_hv_timer(vcpu
);
7953 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
7955 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7956 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
7958 /* Check for memory type validity */
7959 switch (address
& VMX_EPTP_MT_MASK
) {
7960 case VMX_EPTP_MT_UC
:
7961 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
7964 case VMX_EPTP_MT_WB
:
7965 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
7972 /* only 4 levels page-walk length are valid */
7973 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
7976 /* Reserved bits should not be set */
7977 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
7980 /* AD, if set, should be supported */
7981 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
7982 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
7989 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
7990 struct vmcs12
*vmcs12
)
7992 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7994 bool accessed_dirty
;
7995 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
7997 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
7998 !nested_cpu_has_ept(vmcs12
))
8001 if (index
>= VMFUNC_EPTP_ENTRIES
)
8005 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
8006 &address
, index
* 8, 8))
8009 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
8012 * If the (L2) guest does a vmfunc to the currently
8013 * active ept pointer, we don't have to do anything else
8015 if (vmcs12
->ept_pointer
!= address
) {
8016 if (!valid_ept_address(vcpu
, address
))
8019 kvm_mmu_unload(vcpu
);
8020 mmu
->ept_ad
= accessed_dirty
;
8021 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
8022 vmcs12
->ept_pointer
= address
;
8024 * TODO: Check what's the correct approach in case
8025 * mmu reload fails. Currently, we just let the next
8026 * reload potentially fail
8028 kvm_mmu_reload(vcpu
);
8034 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
8036 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8037 struct vmcs12
*vmcs12
;
8038 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
8041 * VMFUNC is only supported for nested guests, but we always enable the
8042 * secondary control for simplicity; for non-nested mode, fake that we
8043 * didn't by injecting #UD.
8045 if (!is_guest_mode(vcpu
)) {
8046 kvm_queue_exception(vcpu
, UD_VECTOR
);
8050 vmcs12
= get_vmcs12(vcpu
);
8051 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
8056 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
8062 return kvm_skip_emulated_instruction(vcpu
);
8065 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8066 vmcs_read32(VM_EXIT_INTR_INFO
),
8067 vmcs_readl(EXIT_QUALIFICATION
));
8072 * The exit handlers return 1 if the exit was handled fully and guest execution
8073 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8074 * to be done to userspace and return 0.
8076 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8077 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8078 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8079 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8080 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8081 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8082 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8083 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8084 [EXIT_REASON_CPUID
] = handle_cpuid
,
8085 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8086 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8087 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8088 [EXIT_REASON_HLT
] = handle_halt
,
8089 [EXIT_REASON_INVD
] = handle_invd
,
8090 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8091 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8092 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8093 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8094 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8095 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8096 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8097 [EXIT_REASON_VMREAD
] = handle_vmread
,
8098 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8099 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8100 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8101 [EXIT_REASON_VMON
] = handle_vmon
,
8102 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8103 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8104 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8105 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8106 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8107 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8108 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8109 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8110 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8111 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8112 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8113 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8114 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8115 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8116 [EXIT_REASON_INVEPT
] = handle_invept
,
8117 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8118 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
8119 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
8120 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8121 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8122 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8123 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8124 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8127 static const int kvm_vmx_max_exit_handlers
=
8128 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8130 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8131 struct vmcs12
*vmcs12
)
8133 unsigned long exit_qualification
;
8134 gpa_t bitmap
, last_bitmap
;
8139 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8140 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8142 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8144 port
= exit_qualification
>> 16;
8145 size
= (exit_qualification
& 7) + 1;
8147 last_bitmap
= (gpa_t
)-1;
8152 bitmap
= vmcs12
->io_bitmap_a
;
8153 else if (port
< 0x10000)
8154 bitmap
= vmcs12
->io_bitmap_b
;
8157 bitmap
+= (port
& 0x7fff) / 8;
8159 if (last_bitmap
!= bitmap
)
8160 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8162 if (b
& (1 << (port
& 7)))
8167 last_bitmap
= bitmap
;
8174 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8175 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8176 * disinterest in the current event (read or write a specific MSR) by using an
8177 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8179 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8180 struct vmcs12
*vmcs12
, u32 exit_reason
)
8182 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8185 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8189 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8190 * for the four combinations of read/write and low/high MSR numbers.
8191 * First we need to figure out which of the four to use:
8193 bitmap
= vmcs12
->msr_bitmap
;
8194 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8196 if (msr_index
>= 0xc0000000) {
8197 msr_index
-= 0xc0000000;
8201 /* Then read the msr_index'th bit from this bitmap: */
8202 if (msr_index
< 1024*8) {
8204 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8206 return 1 & (b
>> (msr_index
& 7));
8208 return true; /* let L1 handle the wrong parameter */
8212 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8213 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8214 * intercept (via guest_host_mask etc.) the current event.
8216 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8217 struct vmcs12
*vmcs12
)
8219 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8220 int cr
= exit_qualification
& 15;
8224 switch ((exit_qualification
>> 4) & 3) {
8225 case 0: /* mov to cr */
8226 reg
= (exit_qualification
>> 8) & 15;
8227 val
= kvm_register_readl(vcpu
, reg
);
8230 if (vmcs12
->cr0_guest_host_mask
&
8231 (val
^ vmcs12
->cr0_read_shadow
))
8235 if ((vmcs12
->cr3_target_count
>= 1 &&
8236 vmcs12
->cr3_target_value0
== val
) ||
8237 (vmcs12
->cr3_target_count
>= 2 &&
8238 vmcs12
->cr3_target_value1
== val
) ||
8239 (vmcs12
->cr3_target_count
>= 3 &&
8240 vmcs12
->cr3_target_value2
== val
) ||
8241 (vmcs12
->cr3_target_count
>= 4 &&
8242 vmcs12
->cr3_target_value3
== val
))
8244 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8248 if (vmcs12
->cr4_guest_host_mask
&
8249 (vmcs12
->cr4_read_shadow
^ val
))
8253 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8259 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8260 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8263 case 1: /* mov from cr */
8266 if (vmcs12
->cpu_based_vm_exec_control
&
8267 CPU_BASED_CR3_STORE_EXITING
)
8271 if (vmcs12
->cpu_based_vm_exec_control
&
8272 CPU_BASED_CR8_STORE_EXITING
)
8279 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8280 * cr0. Other attempted changes are ignored, with no exit.
8282 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8283 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8284 (val
^ vmcs12
->cr0_read_shadow
))
8286 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8287 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8296 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8297 * should handle it ourselves in L0 (and then continue L2). Only call this
8298 * when in is_guest_mode (L2).
8300 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8302 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8303 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8304 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8306 if (vmx
->nested
.nested_run_pending
)
8309 if (unlikely(vmx
->fail
)) {
8310 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8311 vmcs_read32(VM_INSTRUCTION_ERROR
));
8316 * The host physical addresses of some pages of guest memory
8317 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8318 * Page). The CPU may write to these pages via their host
8319 * physical address while L2 is running, bypassing any
8320 * address-translation-based dirty tracking (e.g. EPT write
8323 * Mark them dirty on every exit from L2 to prevent them from
8324 * getting out of sync with dirty tracking.
8326 nested_mark_vmcs12_pages_dirty(vcpu
);
8328 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8329 vmcs_readl(EXIT_QUALIFICATION
),
8330 vmx
->idt_vectoring_info
,
8332 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8335 switch (exit_reason
) {
8336 case EXIT_REASON_EXCEPTION_NMI
:
8337 if (is_nmi(intr_info
))
8339 else if (is_page_fault(intr_info
))
8340 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8341 else if (is_no_device(intr_info
) &&
8342 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8344 else if (is_debug(intr_info
) &&
8346 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8348 else if (is_breakpoint(intr_info
) &&
8349 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8351 return vmcs12
->exception_bitmap
&
8352 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8353 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8355 case EXIT_REASON_TRIPLE_FAULT
:
8357 case EXIT_REASON_PENDING_INTERRUPT
:
8358 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8359 case EXIT_REASON_NMI_WINDOW
:
8360 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8361 case EXIT_REASON_TASK_SWITCH
:
8363 case EXIT_REASON_CPUID
:
8365 case EXIT_REASON_HLT
:
8366 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8367 case EXIT_REASON_INVD
:
8369 case EXIT_REASON_INVLPG
:
8370 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8371 case EXIT_REASON_RDPMC
:
8372 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8373 case EXIT_REASON_RDRAND
:
8374 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND_EXITING
);
8375 case EXIT_REASON_RDSEED
:
8376 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED_EXITING
);
8377 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8378 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8379 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8380 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8381 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8382 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8383 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8384 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8386 * VMX instructions trap unconditionally. This allows L1 to
8387 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8390 case EXIT_REASON_CR_ACCESS
:
8391 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8392 case EXIT_REASON_DR_ACCESS
:
8393 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8394 case EXIT_REASON_IO_INSTRUCTION
:
8395 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8396 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8397 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8398 case EXIT_REASON_MSR_READ
:
8399 case EXIT_REASON_MSR_WRITE
:
8400 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8401 case EXIT_REASON_INVALID_STATE
:
8403 case EXIT_REASON_MWAIT_INSTRUCTION
:
8404 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8405 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8406 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8407 case EXIT_REASON_MONITOR_INSTRUCTION
:
8408 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8409 case EXIT_REASON_PAUSE_INSTRUCTION
:
8410 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8411 nested_cpu_has2(vmcs12
,
8412 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8413 case EXIT_REASON_MCE_DURING_VMENTRY
:
8415 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8416 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8417 case EXIT_REASON_APIC_ACCESS
:
8418 return nested_cpu_has2(vmcs12
,
8419 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8420 case EXIT_REASON_APIC_WRITE
:
8421 case EXIT_REASON_EOI_INDUCED
:
8422 /* apic_write and eoi_induced should exit unconditionally. */
8424 case EXIT_REASON_EPT_VIOLATION
:
8426 * L0 always deals with the EPT violation. If nested EPT is
8427 * used, and the nested mmu code discovers that the address is
8428 * missing in the guest EPT table (EPT12), the EPT violation
8429 * will be injected with nested_ept_inject_page_fault()
8432 case EXIT_REASON_EPT_MISCONFIG
:
8434 * L2 never uses directly L1's EPT, but rather L0's own EPT
8435 * table (shadow on EPT) or a merged EPT table that L0 built
8436 * (EPT on EPT). So any problems with the structure of the
8437 * table is L0's fault.
8440 case EXIT_REASON_INVPCID
:
8442 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8443 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8444 case EXIT_REASON_WBINVD
:
8445 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8446 case EXIT_REASON_XSETBV
:
8448 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8450 * This should never happen, since it is not possible to
8451 * set XSS to a non-zero value---neither in L1 nor in L2.
8452 * If if it were, XSS would have to be checked against
8453 * the XSS exit bitmap in vmcs12.
8455 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8456 case EXIT_REASON_PREEMPTION_TIMER
:
8458 case EXIT_REASON_PML_FULL
:
8459 /* We emulate PML support to L1. */
8461 case EXIT_REASON_VMFUNC
:
8462 /* VM functions are emulated through L2->L0 vmexits. */
8469 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8471 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8474 * At this point, the exit interruption info in exit_intr_info
8475 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8476 * we need to query the in-kernel LAPIC.
8478 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8479 if ((exit_intr_info
&
8480 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8481 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8482 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8483 vmcs12
->vm_exit_intr_error_code
=
8484 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8487 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8488 vmcs_readl(EXIT_QUALIFICATION
));
8492 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8494 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8495 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8498 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8501 __free_page(vmx
->pml_pg
);
8506 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8508 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8512 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8514 /* Do nothing if PML buffer is empty */
8515 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8518 /* PML index always points to next available PML buffer entity */
8519 if (pml_idx
>= PML_ENTITY_NUM
)
8524 pml_buf
= page_address(vmx
->pml_pg
);
8525 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8528 gpa
= pml_buf
[pml_idx
];
8529 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8530 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8533 /* reset PML index */
8534 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8538 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8539 * Called before reporting dirty_bitmap to userspace.
8541 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8544 struct kvm_vcpu
*vcpu
;
8546 * We only need to kick vcpu out of guest mode here, as PML buffer
8547 * is flushed at beginning of all VMEXITs, and it's obvious that only
8548 * vcpus running in guest are possible to have unflushed GPAs in PML
8551 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8552 kvm_vcpu_kick(vcpu
);
8555 static void vmx_dump_sel(char *name
, uint32_t sel
)
8557 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8558 name
, vmcs_read16(sel
),
8559 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8560 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8561 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8564 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8566 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8567 name
, vmcs_read32(limit
),
8568 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8571 static void dump_vmcs(void)
8573 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8574 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8575 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8576 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8577 u32 secondary_exec_control
= 0;
8578 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8579 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8582 if (cpu_has_secondary_exec_ctrls())
8583 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8585 pr_err("*** Guest State ***\n");
8586 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8587 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8588 vmcs_readl(CR0_GUEST_HOST_MASK
));
8589 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8590 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8591 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8592 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8593 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8595 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8596 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8597 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8598 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8600 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8601 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8602 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8603 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8604 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8605 vmcs_readl(GUEST_SYSENTER_ESP
),
8606 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8607 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8608 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8609 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8610 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8611 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8612 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8613 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8614 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8615 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8616 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8617 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8618 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8619 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8620 efer
, vmcs_read64(GUEST_IA32_PAT
));
8621 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8622 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8623 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8624 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8625 pr_err("PerfGlobCtl = 0x%016llx\n",
8626 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8627 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8628 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8629 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8630 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8631 vmcs_read32(GUEST_ACTIVITY_STATE
));
8632 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8633 pr_err("InterruptStatus = %04x\n",
8634 vmcs_read16(GUEST_INTR_STATUS
));
8636 pr_err("*** Host State ***\n");
8637 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8638 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8639 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8640 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8641 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8642 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8643 vmcs_read16(HOST_TR_SELECTOR
));
8644 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8645 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8646 vmcs_readl(HOST_TR_BASE
));
8647 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8648 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8649 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8650 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8651 vmcs_readl(HOST_CR4
));
8652 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8653 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8654 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8655 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8656 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8657 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8658 vmcs_read64(HOST_IA32_EFER
),
8659 vmcs_read64(HOST_IA32_PAT
));
8660 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8661 pr_err("PerfGlobCtl = 0x%016llx\n",
8662 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8664 pr_err("*** Control State ***\n");
8665 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8666 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8667 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8668 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8669 vmcs_read32(EXCEPTION_BITMAP
),
8670 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8671 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8672 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8673 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8674 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8675 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8676 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8677 vmcs_read32(VM_EXIT_INTR_INFO
),
8678 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8679 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8680 pr_err(" reason=%08x qualification=%016lx\n",
8681 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8682 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8683 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8684 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8685 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8686 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8687 pr_err("TSC Multiplier = 0x%016llx\n",
8688 vmcs_read64(TSC_MULTIPLIER
));
8689 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8690 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8691 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8692 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8693 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8694 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8695 n
= vmcs_read32(CR3_TARGET_COUNT
);
8696 for (i
= 0; i
+ 1 < n
; i
+= 4)
8697 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8698 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8699 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8701 pr_err("CR3 target%u=%016lx\n",
8702 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8703 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8704 pr_err("PLE Gap=%08x Window=%08x\n",
8705 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8706 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8707 pr_err("Virtual processor ID = 0x%04x\n",
8708 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8712 * The guest has exited. See if we can fix it or if we need userspace
8715 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8717 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8718 u32 exit_reason
= vmx
->exit_reason
;
8719 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8721 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8724 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8725 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8726 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8727 * mode as if vcpus is in root mode, the PML buffer must has been
8731 vmx_flush_pml_buffer(vcpu
);
8733 /* If guest state is invalid, start emulating */
8734 if (vmx
->emulation_required
)
8735 return handle_invalid_guest_state(vcpu
);
8737 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8738 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8740 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8742 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8743 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8748 if (unlikely(vmx
->fail
)) {
8749 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8750 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8751 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8757 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8758 * delivery event since it indicates guest is accessing MMIO.
8759 * The vm-exit can be triggered again after return to guest that
8760 * will cause infinite loop.
8762 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8763 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8764 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8765 exit_reason
!= EXIT_REASON_PML_FULL
&&
8766 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8767 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8768 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8769 vcpu
->run
->internal
.ndata
= 3;
8770 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8771 vcpu
->run
->internal
.data
[1] = exit_reason
;
8772 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8773 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8774 vcpu
->run
->internal
.ndata
++;
8775 vcpu
->run
->internal
.data
[3] =
8776 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8781 if (unlikely(!enable_vnmi
&&
8782 vmx
->loaded_vmcs
->soft_vnmi_blocked
)) {
8783 if (vmx_interrupt_allowed(vcpu
)) {
8784 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8785 } else if (vmx
->loaded_vmcs
->vnmi_blocked_time
> 1000000000LL &&
8786 vcpu
->arch
.nmi_pending
) {
8788 * This CPU don't support us in finding the end of an
8789 * NMI-blocked window if the guest runs with IRQs
8790 * disabled. So we pull the trigger after 1 s of
8791 * futile waiting, but inform the user about this.
8793 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8794 "state on VCPU %d after 1 s timeout\n",
8795 __func__
, vcpu
->vcpu_id
);
8796 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8800 if (exit_reason
< kvm_vmx_max_exit_handlers
8801 && kvm_vmx_exit_handlers
[exit_reason
])
8802 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8804 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8806 kvm_queue_exception(vcpu
, UD_VECTOR
);
8811 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8813 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8815 if (is_guest_mode(vcpu
) &&
8816 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8819 if (irr
== -1 || tpr
< irr
) {
8820 vmcs_write32(TPR_THRESHOLD
, 0);
8824 vmcs_write32(TPR_THRESHOLD
, irr
);
8827 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8829 u32 sec_exec_control
;
8831 /* Postpone execution until vmcs01 is the current VMCS. */
8832 if (is_guest_mode(vcpu
)) {
8833 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8837 if (!cpu_has_vmx_virtualize_x2apic_mode())
8840 if (!cpu_need_tpr_shadow(vcpu
))
8843 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8846 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8847 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8849 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8850 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8851 vmx_flush_tlb_ept_only(vcpu
);
8853 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8855 vmx_set_msr_bitmap(vcpu
);
8858 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8860 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8863 * Currently we do not handle the nested case where L2 has an
8864 * APIC access page of its own; that page is still pinned.
8865 * Hence, we skip the case where the VCPU is in guest mode _and_
8866 * L1 prepared an APIC access page for L2.
8868 * For the case where L1 and L2 share the same APIC access page
8869 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8870 * in the vmcs12), this function will only update either the vmcs01
8871 * or the vmcs02. If the former, the vmcs02 will be updated by
8872 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8873 * the next L2->L1 exit.
8875 if (!is_guest_mode(vcpu
) ||
8876 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8877 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8878 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8879 vmx_flush_tlb_ept_only(vcpu
);
8883 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8891 status
= vmcs_read16(GUEST_INTR_STATUS
);
8893 if (max_isr
!= old
) {
8895 status
|= max_isr
<< 8;
8896 vmcs_write16(GUEST_INTR_STATUS
, status
);
8900 static void vmx_set_rvi(int vector
)
8908 status
= vmcs_read16(GUEST_INTR_STATUS
);
8909 old
= (u8
)status
& 0xff;
8910 if ((u8
)vector
!= old
) {
8912 status
|= (u8
)vector
;
8913 vmcs_write16(GUEST_INTR_STATUS
, status
);
8917 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8919 if (!is_guest_mode(vcpu
)) {
8920 vmx_set_rvi(max_irr
);
8928 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8931 if (nested_exit_on_intr(vcpu
))
8935 * Else, fall back to pre-APICv interrupt injection since L2
8936 * is run without virtual interrupt delivery.
8938 if (!kvm_event_needs_reinjection(vcpu
) &&
8939 vmx_interrupt_allowed(vcpu
)) {
8940 kvm_queue_interrupt(vcpu
, max_irr
, false);
8941 vmx_inject_irq(vcpu
);
8945 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8947 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8950 WARN_ON(!vcpu
->arch
.apicv_active
);
8951 if (pi_test_on(&vmx
->pi_desc
)) {
8952 pi_clear_on(&vmx
->pi_desc
);
8954 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8955 * But on x86 this is just a compiler barrier anyway.
8957 smp_mb__after_atomic();
8958 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8960 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8962 vmx_hwapic_irr_update(vcpu
, max_irr
);
8966 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8968 if (!kvm_vcpu_apicv_active(vcpu
))
8971 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8972 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8973 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8974 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8977 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8979 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8981 pi_clear_on(&vmx
->pi_desc
);
8982 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8985 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8987 u32 exit_intr_info
= 0;
8988 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
8990 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8991 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8994 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
8995 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8996 vmx
->exit_intr_info
= exit_intr_info
;
8998 /* if exit due to PF check for async PF */
8999 if (is_page_fault(exit_intr_info
))
9000 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
9002 /* Handle machine checks before interrupts are enabled */
9003 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
9004 is_machine_check(exit_intr_info
))
9005 kvm_machine_check();
9007 /* We need to handle NMIs before interrupts are enabled */
9008 if (is_nmi(exit_intr_info
)) {
9009 kvm_before_handle_nmi(&vmx
->vcpu
);
9011 kvm_after_handle_nmi(&vmx
->vcpu
);
9015 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
9017 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9019 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
9020 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
9021 unsigned int vector
;
9022 unsigned long entry
;
9024 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9025 #ifdef CONFIG_X86_64
9029 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9030 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
9031 entry
= gate_offset(desc
);
9033 #ifdef CONFIG_X86_64
9034 "mov %%" _ASM_SP
", %[sp]\n\t"
9035 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
9040 __ASM_SIZE(push
) " $%c[cs]\n\t"
9043 #ifdef CONFIG_X86_64
9048 THUNK_TARGET(entry
),
9049 [ss
]"i"(__KERNEL_DS
),
9050 [cs
]"i"(__KERNEL_CS
)
9054 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
9056 static bool vmx_has_high_real_mode_segbase(void)
9058 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
9061 static bool vmx_mpx_supported(void)
9063 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
9064 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
9067 static bool vmx_xsaves_supported(void)
9069 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9070 SECONDARY_EXEC_XSAVES
;
9073 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
9078 bool idtv_info_valid
;
9080 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9083 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9086 * Can't use vmx->exit_intr_info since we're not sure what
9087 * the exit reason is.
9089 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9090 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9091 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9093 * SDM 3: 27.7.1.2 (September 2008)
9094 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9095 * a guest IRET fault.
9096 * SDM 3: 23.2.2 (September 2008)
9097 * Bit 12 is undefined in any of the following cases:
9098 * If the VM exit sets the valid bit in the IDT-vectoring
9099 * information field.
9100 * If the VM exit is due to a double fault.
9102 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9103 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9104 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9105 GUEST_INTR_STATE_NMI
);
9107 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9108 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9109 & GUEST_INTR_STATE_NMI
);
9110 } else if (unlikely(vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9111 vmx
->loaded_vmcs
->vnmi_blocked_time
+=
9112 ktime_to_ns(ktime_sub(ktime_get(),
9113 vmx
->loaded_vmcs
->entry_time
));
9116 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9117 u32 idt_vectoring_info
,
9118 int instr_len_field
,
9119 int error_code_field
)
9123 bool idtv_info_valid
;
9125 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9127 vcpu
->arch
.nmi_injected
= false;
9128 kvm_clear_exception_queue(vcpu
);
9129 kvm_clear_interrupt_queue(vcpu
);
9131 if (!idtv_info_valid
)
9134 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9136 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9137 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9140 case INTR_TYPE_NMI_INTR
:
9141 vcpu
->arch
.nmi_injected
= true;
9143 * SDM 3: 27.7.1.2 (September 2008)
9144 * Clear bit "block by NMI" before VM entry if a NMI
9147 vmx_set_nmi_mask(vcpu
, false);
9149 case INTR_TYPE_SOFT_EXCEPTION
:
9150 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9152 case INTR_TYPE_HARD_EXCEPTION
:
9153 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9154 u32 err
= vmcs_read32(error_code_field
);
9155 kvm_requeue_exception_e(vcpu
, vector
, err
);
9157 kvm_requeue_exception(vcpu
, vector
);
9159 case INTR_TYPE_SOFT_INTR
:
9160 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9162 case INTR_TYPE_EXT_INTR
:
9163 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9170 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9172 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9173 VM_EXIT_INSTRUCTION_LEN
,
9174 IDT_VECTORING_ERROR_CODE
);
9177 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9179 __vmx_complete_interrupts(vcpu
,
9180 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9181 VM_ENTRY_INSTRUCTION_LEN
,
9182 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9184 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9187 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9190 struct perf_guest_switch_msr
*msrs
;
9192 msrs
= perf_guest_get_msrs(&nr_msrs
);
9197 for (i
= 0; i
< nr_msrs
; i
++)
9198 if (msrs
[i
].host
== msrs
[i
].guest
)
9199 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9201 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9205 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9207 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9211 if (vmx
->hv_deadline_tsc
== -1)
9215 if (vmx
->hv_deadline_tsc
> tscl
)
9216 /* sure to be 32 bit only because checked on set_hv_timer */
9217 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9218 cpu_preemption_timer_multi
);
9222 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9225 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9227 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9228 unsigned long debugctlmsr
, cr3
, cr4
;
9230 /* Record the guest's net vcpu time for enforced NMI injections. */
9231 if (unlikely(!enable_vnmi
&&
9232 vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9233 vmx
->loaded_vmcs
->entry_time
= ktime_get();
9235 /* Don't enter VMX if guest state is invalid, let the exit handler
9236 start emulation until we arrive back to a valid state */
9237 if (vmx
->emulation_required
)
9240 if (vmx
->ple_window_dirty
) {
9241 vmx
->ple_window_dirty
= false;
9242 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9245 if (vmx
->nested
.sync_shadow_vmcs
) {
9246 copy_vmcs12_to_shadow(vmx
);
9247 vmx
->nested
.sync_shadow_vmcs
= false;
9250 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9251 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9252 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9253 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9255 cr3
= __get_current_cr3_fast();
9256 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9257 vmcs_writel(HOST_CR3
, cr3
);
9258 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9261 cr4
= cr4_read_shadow();
9262 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9263 vmcs_writel(HOST_CR4
, cr4
);
9264 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9267 /* When single-stepping over STI and MOV SS, we must clear the
9268 * corresponding interruptibility bits in the guest state. Otherwise
9269 * vmentry fails as it then expects bit 14 (BS) in pending debug
9270 * exceptions being set, but that's not correct for the guest debugging
9272 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9273 vmx_set_interrupt_shadow(vcpu
, 0);
9275 if (static_cpu_has(X86_FEATURE_PKU
) &&
9276 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9277 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9278 __write_pkru(vcpu
->arch
.pkru
);
9280 atomic_switch_perf_msrs(vmx
);
9281 debugctlmsr
= get_debugctlmsr();
9283 vmx_arm_hv_timer(vcpu
);
9285 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9287 /* Store host registers */
9288 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9289 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9290 "push %%" _ASM_CX
" \n\t"
9291 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9293 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9294 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9296 /* Reload cr2 if changed */
9297 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9298 "mov %%cr2, %%" _ASM_DX
" \n\t"
9299 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9301 "mov %%" _ASM_AX
", %%cr2 \n\t"
9303 /* Check if vmlaunch of vmresume is needed */
9304 "cmpl $0, %c[launched](%0) \n\t"
9305 /* Load guest registers. Don't clobber flags. */
9306 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9307 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9308 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9309 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9310 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9311 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9312 #ifdef CONFIG_X86_64
9313 "mov %c[r8](%0), %%r8 \n\t"
9314 "mov %c[r9](%0), %%r9 \n\t"
9315 "mov %c[r10](%0), %%r10 \n\t"
9316 "mov %c[r11](%0), %%r11 \n\t"
9317 "mov %c[r12](%0), %%r12 \n\t"
9318 "mov %c[r13](%0), %%r13 \n\t"
9319 "mov %c[r14](%0), %%r14 \n\t"
9320 "mov %c[r15](%0), %%r15 \n\t"
9322 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9324 /* Enter guest mode */
9326 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9328 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9330 /* Save guest registers, load host registers, keep flags */
9331 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9333 "setbe %c[fail](%0)\n\t"
9334 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9335 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9336 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9337 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9338 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9339 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9340 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9341 #ifdef CONFIG_X86_64
9342 "mov %%r8, %c[r8](%0) \n\t"
9343 "mov %%r9, %c[r9](%0) \n\t"
9344 "mov %%r10, %c[r10](%0) \n\t"
9345 "mov %%r11, %c[r11](%0) \n\t"
9346 "mov %%r12, %c[r12](%0) \n\t"
9347 "mov %%r13, %c[r13](%0) \n\t"
9348 "mov %%r14, %c[r14](%0) \n\t"
9349 "mov %%r15, %c[r15](%0) \n\t"
9350 "xor %%r8d, %%r8d \n\t"
9351 "xor %%r9d, %%r9d \n\t"
9352 "xor %%r10d, %%r10d \n\t"
9353 "xor %%r11d, %%r11d \n\t"
9354 "xor %%r12d, %%r12d \n\t"
9355 "xor %%r13d, %%r13d \n\t"
9356 "xor %%r14d, %%r14d \n\t"
9357 "xor %%r15d, %%r15d \n\t"
9359 "mov %%cr2, %%" _ASM_AX
" \n\t"
9360 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9362 "xor %%eax, %%eax \n\t"
9363 "xor %%ebx, %%ebx \n\t"
9364 "xor %%esi, %%esi \n\t"
9365 "xor %%edi, %%edi \n\t"
9366 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9367 ".pushsection .rodata \n\t"
9368 ".global vmx_return \n\t"
9369 "vmx_return: " _ASM_PTR
" 2b \n\t"
9371 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9372 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9373 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9374 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9375 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9376 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9377 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9378 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9379 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9380 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9381 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9382 #ifdef CONFIG_X86_64
9383 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9384 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9385 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9386 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9387 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9388 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9389 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9390 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9392 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9393 [wordsize
]"i"(sizeof(ulong
))
9395 #ifdef CONFIG_X86_64
9396 , "rax", "rbx", "rdi", "rsi"
9397 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9399 , "eax", "ebx", "edi", "esi"
9403 /* Eliminate branch target predictions from guest mode */
9406 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9408 update_debugctlmsr(debugctlmsr
);
9410 #ifndef CONFIG_X86_64
9412 * The sysexit path does not restore ds/es, so we must set them to
9413 * a reasonable value ourselves.
9415 * We can't defer this to vmx_load_host_state() since that function
9416 * may be executed in interrupt context, which saves and restore segments
9417 * around it, nullifying its effect.
9419 loadsegment(ds
, __USER_DS
);
9420 loadsegment(es
, __USER_DS
);
9423 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9424 | (1 << VCPU_EXREG_RFLAGS
)
9425 | (1 << VCPU_EXREG_PDPTR
)
9426 | (1 << VCPU_EXREG_SEGMENTS
)
9427 | (1 << VCPU_EXREG_CR3
));
9428 vcpu
->arch
.regs_dirty
= 0;
9431 * eager fpu is enabled if PKEY is supported and CR4 is switched
9432 * back on host, so it is safe to read guest PKRU from current
9435 if (static_cpu_has(X86_FEATURE_PKU
) &&
9436 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9437 vcpu
->arch
.pkru
= __read_pkru();
9438 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9439 __write_pkru(vmx
->host_pkru
);
9443 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9444 * we did not inject a still-pending event to L1 now because of
9445 * nested_run_pending, we need to re-enable this bit.
9447 if (vmx
->nested
.nested_run_pending
)
9448 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9450 vmx
->nested
.nested_run_pending
= 0;
9451 vmx
->idt_vectoring_info
= 0;
9453 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
9454 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9457 vmx
->loaded_vmcs
->launched
= 1;
9458 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9460 vmx_complete_atomic_exit(vmx
);
9461 vmx_recover_nmi_blocking(vmx
);
9462 vmx_complete_interrupts(vmx
);
9464 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9466 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9468 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9471 if (vmx
->loaded_vmcs
== vmcs
)
9475 vmx
->loaded_vmcs
= vmcs
;
9477 vmx_vcpu_load(vcpu
, cpu
);
9482 * Ensure that the current vmcs of the logical processor is the
9483 * vmcs01 of the vcpu before calling free_nested().
9485 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9487 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9490 r
= vcpu_load(vcpu
);
9492 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9497 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9499 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9502 vmx_destroy_pml_buffer(vmx
);
9503 free_vpid(vmx
->vpid
);
9504 leave_guest_mode(vcpu
);
9505 vmx_free_vcpu_nested(vcpu
);
9506 free_loaded_vmcs(vmx
->loaded_vmcs
);
9507 kfree(vmx
->guest_msrs
);
9508 kvm_vcpu_uninit(vcpu
);
9509 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9512 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9515 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9519 return ERR_PTR(-ENOMEM
);
9521 vmx
->vpid
= allocate_vpid();
9523 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9530 * If PML is turned on, failure on enabling PML just results in failure
9531 * of creating the vcpu, therefore we can simplify PML logic (by
9532 * avoiding dealing with cases, such as enabling PML partially on vcpus
9533 * for the guest, etc.
9536 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9541 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9542 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9545 if (!vmx
->guest_msrs
)
9548 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9549 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9550 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9551 if (!vmx
->loaded_vmcs
->vmcs
)
9553 loaded_vmcs_init(vmx
->loaded_vmcs
);
9556 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9557 vmx
->vcpu
.cpu
= cpu
;
9558 vmx_vcpu_setup(vmx
);
9559 vmx_vcpu_put(&vmx
->vcpu
);
9561 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9562 err
= alloc_apic_access_page(kvm
);
9568 err
= init_rmode_identity_map(kvm
);
9574 nested_vmx_setup_ctls_msrs(vmx
);
9575 vmx
->nested
.vpid02
= allocate_vpid();
9578 vmx
->nested
.posted_intr_nv
= -1;
9579 vmx
->nested
.current_vmptr
= -1ull;
9581 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9584 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9585 * or POSTED_INTR_WAKEUP_VECTOR.
9587 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9588 vmx
->pi_desc
.sn
= 1;
9593 free_vpid(vmx
->nested
.vpid02
);
9594 free_loaded_vmcs(vmx
->loaded_vmcs
);
9596 kfree(vmx
->guest_msrs
);
9598 vmx_destroy_pml_buffer(vmx
);
9600 kvm_vcpu_uninit(&vmx
->vcpu
);
9602 free_vpid(vmx
->vpid
);
9603 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9604 return ERR_PTR(err
);
9607 static void __init
vmx_check_processor_compat(void *rtn
)
9609 struct vmcs_config vmcs_conf
;
9612 if (setup_vmcs_config(&vmcs_conf
) < 0)
9614 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9615 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9616 smp_processor_id());
9621 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9626 /* For VT-d and EPT combination
9627 * 1. MMIO: always map as UC
9629 * a. VT-d without snooping control feature: can't guarantee the
9630 * result, try to trust guest.
9631 * b. VT-d with snooping control feature: snooping control feature of
9632 * VT-d engine can guarantee the cache correctness. Just set it
9633 * to WB to keep consistent with host. So the same as item 3.
9634 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9635 * consistent with host MTRR
9638 cache
= MTRR_TYPE_UNCACHABLE
;
9642 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9643 ipat
= VMX_EPT_IPAT_BIT
;
9644 cache
= MTRR_TYPE_WRBACK
;
9648 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9649 ipat
= VMX_EPT_IPAT_BIT
;
9650 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9651 cache
= MTRR_TYPE_WRBACK
;
9653 cache
= MTRR_TYPE_UNCACHABLE
;
9657 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9660 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9663 static int vmx_get_lpage_level(void)
9665 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9666 return PT_DIRECTORY_LEVEL
;
9668 /* For shadow and EPT supported 1GB page */
9669 return PT_PDPE_LEVEL
;
9672 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9675 * These bits in the secondary execution controls field
9676 * are dynamic, the others are mostly based on the hypervisor
9677 * architecture and the guest's CPUID. Do not touch the
9681 SECONDARY_EXEC_SHADOW_VMCS
|
9682 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9683 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9685 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9687 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9688 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9692 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9693 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9695 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9697 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9698 struct kvm_cpuid_entry2
*entry
;
9700 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9701 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9703 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9704 if (entry && (entry->_reg & (_cpuid_mask))) \
9705 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9708 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9709 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9710 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9711 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9712 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9713 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9714 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9715 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9716 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9717 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9718 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9719 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9720 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9721 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9722 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9724 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9725 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9726 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9727 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9728 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9729 cr4_fixed1_update(X86_CR4_UMIP
, ecx
, bit(X86_FEATURE_UMIP
));
9731 #undef cr4_fixed1_update
9734 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9736 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9738 if (cpu_has_secondary_exec_ctrls()) {
9739 vmx_compute_secondary_exec_control(vmx
);
9740 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9743 if (nested_vmx_allowed(vcpu
))
9744 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9745 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9747 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9748 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9750 if (nested_vmx_allowed(vcpu
))
9751 nested_vmx_cr_fixed1_bits_update(vcpu
);
9754 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9756 if (func
== 1 && nested
)
9757 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9760 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9761 struct x86_exception
*fault
)
9763 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9764 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9766 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9768 if (vmx
->nested
.pml_full
) {
9769 exit_reason
= EXIT_REASON_PML_FULL
;
9770 vmx
->nested
.pml_full
= false;
9771 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9772 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9773 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9775 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9777 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9778 vmcs12
->guest_physical_address
= fault
->address
;
9781 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9783 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
9786 /* Callbacks for nested_ept_init_mmu_context: */
9788 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9790 /* return the page table to be shadowed - in our case, EPT12 */
9791 return get_vmcs12(vcpu
)->ept_pointer
;
9794 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9796 WARN_ON(mmu_is_nested(vcpu
));
9797 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
9800 kvm_mmu_unload(vcpu
);
9801 kvm_init_shadow_ept_mmu(vcpu
,
9802 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9803 VMX_EPT_EXECUTE_ONLY_BIT
,
9804 nested_ept_ad_enabled(vcpu
));
9805 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9806 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9807 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9809 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9813 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9815 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9818 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9821 bool inequality
, bit
;
9823 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9825 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9826 vmcs12
->page_fault_error_code_match
;
9827 return inequality
^ bit
;
9830 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9831 struct x86_exception
*fault
)
9833 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9835 WARN_ON(!is_guest_mode(vcpu
));
9837 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
) &&
9838 !to_vmx(vcpu
)->nested
.nested_run_pending
) {
9839 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9840 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9841 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9842 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9845 kvm_inject_page_fault(vcpu
, fault
);
9849 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9850 struct vmcs12
*vmcs12
);
9852 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9853 struct vmcs12
*vmcs12
)
9855 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9859 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9861 * Translate L1 physical address to host physical
9862 * address for vmcs02. Keep the page pinned, so this
9863 * physical address remains valid. We keep a reference
9864 * to it so we can release it later.
9866 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
9867 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
9868 vmx
->nested
.apic_access_page
= NULL
;
9870 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
9872 * If translation failed, no matter: This feature asks
9873 * to exit when accessing the given address, and if it
9874 * can never be accessed, this feature won't do
9877 if (!is_error_page(page
)) {
9878 vmx
->nested
.apic_access_page
= page
;
9879 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9880 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9882 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9883 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9885 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9886 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9887 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9888 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9889 kvm_vcpu_reload_apic_access_page(vcpu
);
9892 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9893 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
9894 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
9895 vmx
->nested
.virtual_apic_page
= NULL
;
9897 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9900 * If translation failed, VM entry will fail because
9901 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9902 * Failing the vm entry is _not_ what the processor
9903 * does but it's basically the only possibility we
9904 * have. We could still enter the guest if CR8 load
9905 * exits are enabled, CR8 store exits are enabled, and
9906 * virtualize APIC access is disabled; in this case
9907 * the processor would never use the TPR shadow and we
9908 * could simply clear the bit from the execution
9909 * control. But such a configuration is useless, so
9910 * let's keep the code simple.
9912 if (!is_error_page(page
)) {
9913 vmx
->nested
.virtual_apic_page
= page
;
9914 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9915 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9919 if (nested_cpu_has_posted_intr(vmcs12
)) {
9920 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9921 kunmap(vmx
->nested
.pi_desc_page
);
9922 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
9923 vmx
->nested
.pi_desc_page
= NULL
;
9925 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9926 if (is_error_page(page
))
9928 vmx
->nested
.pi_desc_page
= page
;
9929 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
9930 vmx
->nested
.pi_desc
=
9931 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9932 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9934 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9935 page_to_phys(vmx
->nested
.pi_desc_page
) +
9936 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9939 if (cpu_has_vmx_msr_bitmap() &&
9940 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9941 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9944 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9945 CPU_BASED_USE_MSR_BITMAPS
);
9948 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9950 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9951 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9953 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9956 /* Make sure short timeouts reliably trigger an immediate vmexit.
9957 * hrtimer_start does not guarantee this. */
9958 if (preemption_timeout
<= 1) {
9959 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9963 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9964 preemption_timeout
*= 1000000;
9965 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9966 hrtimer_start(&vmx
->nested
.preemption_timer
,
9967 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9970 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9971 struct vmcs12
*vmcs12
)
9973 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9976 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9977 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9983 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9984 struct vmcs12
*vmcs12
)
9986 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9989 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
9995 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
9996 struct vmcs12
*vmcs12
)
9998 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10001 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
10008 * Merge L0's and L1's MSR bitmap, return false to indicate that
10009 * we do not use the hardware.
10011 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10012 struct vmcs12
*vmcs12
)
10016 unsigned long *msr_bitmap_l1
;
10017 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
10019 /* This shortcut is ok because we support only x2APIC MSRs so far. */
10020 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
10023 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10024 if (is_error_page(page
))
10026 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10028 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
10030 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
10031 if (nested_cpu_has_apic_reg_virt(vmcs12
))
10032 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
10033 nested_vmx_disable_intercept_for_msr(
10034 msr_bitmap_l1
, msr_bitmap_l0
,
10037 nested_vmx_disable_intercept_for_msr(
10038 msr_bitmap_l1
, msr_bitmap_l0
,
10039 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
10040 MSR_TYPE_R
| MSR_TYPE_W
);
10042 if (nested_cpu_has_vid(vmcs12
)) {
10043 nested_vmx_disable_intercept_for_msr(
10044 msr_bitmap_l1
, msr_bitmap_l0
,
10045 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
10047 nested_vmx_disable_intercept_for_msr(
10048 msr_bitmap_l1
, msr_bitmap_l0
,
10049 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
10054 kvm_release_page_clean(page
);
10059 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10060 struct vmcs12
*vmcs12
)
10062 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10063 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10064 !nested_cpu_has_vid(vmcs12
) &&
10065 !nested_cpu_has_posted_intr(vmcs12
))
10069 * If virtualize x2apic mode is enabled,
10070 * virtualize apic access must be disabled.
10072 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10073 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10077 * If virtual interrupt delivery is enabled,
10078 * we must exit on external interrupts.
10080 if (nested_cpu_has_vid(vmcs12
) &&
10081 !nested_exit_on_intr(vcpu
))
10085 * bits 15:8 should be zero in posted_intr_nv,
10086 * the descriptor address has been already checked
10087 * in nested_get_vmcs12_pages.
10089 if (nested_cpu_has_posted_intr(vmcs12
) &&
10090 (!nested_cpu_has_vid(vmcs12
) ||
10091 !nested_exit_intr_ack_set(vcpu
) ||
10092 vmcs12
->posted_intr_nv
& 0xff00))
10095 /* tpr shadow is needed by all apicv features. */
10096 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10102 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10103 unsigned long count_field
,
10104 unsigned long addr_field
)
10109 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10110 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10116 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10117 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10118 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10119 pr_debug_ratelimited(
10120 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10121 addr_field
, maxphyaddr
, count
, addr
);
10127 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10128 struct vmcs12
*vmcs12
)
10130 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10131 vmcs12
->vm_exit_msr_store_count
== 0 &&
10132 vmcs12
->vm_entry_msr_load_count
== 0)
10133 return 0; /* Fast path */
10134 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10135 VM_EXIT_MSR_LOAD_ADDR
) ||
10136 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10137 VM_EXIT_MSR_STORE_ADDR
) ||
10138 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10139 VM_ENTRY_MSR_LOAD_ADDR
))
10144 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10145 struct vmcs12
*vmcs12
)
10147 u64 address
= vmcs12
->pml_address
;
10148 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10150 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10151 if (!nested_cpu_has_ept(vmcs12
) ||
10152 !IS_ALIGNED(address
, 4096) ||
10153 address
>> maxphyaddr
)
10160 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10161 struct vmx_msr_entry
*e
)
10163 /* x2APIC MSR accesses are not allowed */
10164 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10166 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10167 e
->index
== MSR_IA32_UCODE_REV
)
10169 if (e
->reserved
!= 0)
10174 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10175 struct vmx_msr_entry
*e
)
10177 if (e
->index
== MSR_FS_BASE
||
10178 e
->index
== MSR_GS_BASE
||
10179 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10180 nested_vmx_msr_check_common(vcpu
, e
))
10185 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10186 struct vmx_msr_entry
*e
)
10188 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10189 nested_vmx_msr_check_common(vcpu
, e
))
10195 * Load guest's/host's msr at nested entry/exit.
10196 * return 0 for success, entry index for failure.
10198 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10201 struct vmx_msr_entry e
;
10202 struct msr_data msr
;
10204 msr
.host_initiated
= false;
10205 for (i
= 0; i
< count
; i
++) {
10206 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10208 pr_debug_ratelimited(
10209 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10210 __func__
, i
, gpa
+ i
* sizeof(e
));
10213 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10214 pr_debug_ratelimited(
10215 "%s check failed (%u, 0x%x, 0x%x)\n",
10216 __func__
, i
, e
.index
, e
.reserved
);
10219 msr
.index
= e
.index
;
10220 msr
.data
= e
.value
;
10221 if (kvm_set_msr(vcpu
, &msr
)) {
10222 pr_debug_ratelimited(
10223 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10224 __func__
, i
, e
.index
, e
.value
);
10233 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10236 struct vmx_msr_entry e
;
10238 for (i
= 0; i
< count
; i
++) {
10239 struct msr_data msr_info
;
10240 if (kvm_vcpu_read_guest(vcpu
,
10241 gpa
+ i
* sizeof(e
),
10242 &e
, 2 * sizeof(u32
))) {
10243 pr_debug_ratelimited(
10244 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10245 __func__
, i
, gpa
+ i
* sizeof(e
));
10248 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10249 pr_debug_ratelimited(
10250 "%s check failed (%u, 0x%x, 0x%x)\n",
10251 __func__
, i
, e
.index
, e
.reserved
);
10254 msr_info
.host_initiated
= false;
10255 msr_info
.index
= e
.index
;
10256 if (kvm_get_msr(vcpu
, &msr_info
)) {
10257 pr_debug_ratelimited(
10258 "%s cannot read MSR (%u, 0x%x)\n",
10259 __func__
, i
, e
.index
);
10262 if (kvm_vcpu_write_guest(vcpu
,
10263 gpa
+ i
* sizeof(e
) +
10264 offsetof(struct vmx_msr_entry
, value
),
10265 &msr_info
.data
, sizeof(msr_info
.data
))) {
10266 pr_debug_ratelimited(
10267 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10268 __func__
, i
, e
.index
, msr_info
.data
);
10275 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10277 unsigned long invalid_mask
;
10279 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10280 return (val
& invalid_mask
) == 0;
10284 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10285 * emulating VM entry into a guest with EPT enabled.
10286 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10287 * is assigned to entry_failure_code on failure.
10289 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10290 u32
*entry_failure_code
)
10292 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10293 if (!nested_cr3_valid(vcpu
, cr3
)) {
10294 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10299 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10300 * must not be dereferenced.
10302 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10304 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10305 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10310 vcpu
->arch
.cr3
= cr3
;
10311 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10314 kvm_mmu_reset_context(vcpu
);
10319 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10320 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10321 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10322 * guest in a way that will both be appropriate to L1's requests, and our
10323 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10324 * function also has additional necessary side-effects, like setting various
10325 * vcpu->arch fields.
10326 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10327 * is assigned to entry_failure_code on failure.
10329 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10330 bool from_vmentry
, u32
*entry_failure_code
)
10332 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10333 u32 exec_control
, vmcs12_exec_ctrl
;
10335 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10336 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10337 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10338 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10339 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10340 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10341 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10342 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10343 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10344 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10345 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10346 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10347 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10348 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10349 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10350 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10351 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10352 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10353 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10354 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10355 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10356 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10357 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10358 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10359 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10360 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10361 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10362 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10363 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10364 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10365 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10366 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10367 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10368 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10369 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10370 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10372 if (from_vmentry
&&
10373 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10374 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10375 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10377 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10378 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10380 if (from_vmentry
) {
10381 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10382 vmcs12
->vm_entry_intr_info_field
);
10383 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10384 vmcs12
->vm_entry_exception_error_code
);
10385 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10386 vmcs12
->vm_entry_instruction_len
);
10387 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10388 vmcs12
->guest_interruptibility_info
);
10389 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10390 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10392 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10394 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10395 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10396 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10397 vmcs12
->guest_pending_dbg_exceptions
);
10398 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10399 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10401 if (nested_cpu_has_xsaves(vmcs12
))
10402 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10403 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10405 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10407 /* Preemption timer setting is only taken from vmcs01. */
10408 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10409 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10410 if (vmx
->hv_deadline_tsc
== -1)
10411 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10413 /* Posted interrupts setting is only taken from vmcs12. */
10414 if (nested_cpu_has_posted_intr(vmcs12
)) {
10415 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10416 vmx
->nested
.pi_pending
= false;
10417 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10419 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10422 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10424 vmx
->nested
.preemption_timer_expired
= false;
10425 if (nested_cpu_has_preemption_timer(vmcs12
))
10426 vmx_start_preemption_timer(vcpu
);
10429 * Whether page-faults are trapped is determined by a combination of
10430 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10431 * If enable_ept, L0 doesn't care about page faults and we should
10432 * set all of these to L1's desires. However, if !enable_ept, L0 does
10433 * care about (at least some) page faults, and because it is not easy
10434 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10435 * to exit on each and every L2 page fault. This is done by setting
10436 * MASK=MATCH=0 and (see below) EB.PF=1.
10437 * Note that below we don't need special code to set EB.PF beyond the
10438 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10439 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10440 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10442 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10443 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10444 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10445 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10447 if (cpu_has_secondary_exec_ctrls()) {
10448 exec_control
= vmx
->secondary_exec_control
;
10450 /* Take the following fields only from vmcs12 */
10451 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10452 SECONDARY_EXEC_ENABLE_INVPCID
|
10453 SECONDARY_EXEC_RDTSCP
|
10454 SECONDARY_EXEC_XSAVES
|
10455 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10456 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10457 SECONDARY_EXEC_ENABLE_VMFUNC
);
10458 if (nested_cpu_has(vmcs12
,
10459 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10460 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10461 ~SECONDARY_EXEC_ENABLE_PML
;
10462 exec_control
|= vmcs12_exec_ctrl
;
10465 /* All VMFUNCs are currently emulated through L0 vmexits. */
10466 if (exec_control
& SECONDARY_EXEC_ENABLE_VMFUNC
)
10467 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10469 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10470 vmcs_write64(EOI_EXIT_BITMAP0
,
10471 vmcs12
->eoi_exit_bitmap0
);
10472 vmcs_write64(EOI_EXIT_BITMAP1
,
10473 vmcs12
->eoi_exit_bitmap1
);
10474 vmcs_write64(EOI_EXIT_BITMAP2
,
10475 vmcs12
->eoi_exit_bitmap2
);
10476 vmcs_write64(EOI_EXIT_BITMAP3
,
10477 vmcs12
->eoi_exit_bitmap3
);
10478 vmcs_write16(GUEST_INTR_STATUS
,
10479 vmcs12
->guest_intr_status
);
10483 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10484 * nested_get_vmcs12_pages will either fix it up or
10485 * remove the VM execution control.
10487 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10488 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10490 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10495 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10496 * Some constant fields are set here by vmx_set_constant_host_state().
10497 * Other fields are different per CPU, and will be set later when
10498 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10500 vmx_set_constant_host_state(vmx
);
10503 * Set the MSR load/store lists to match L0's settings.
10505 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10506 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10507 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10508 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10509 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10512 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10513 * entry, but only if the current (host) sp changed from the value
10514 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10515 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10516 * here we just force the write to happen on entry.
10520 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10521 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10522 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10523 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10524 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10527 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10528 * nested_get_vmcs12_pages can't fix it up, the illegal value
10529 * will result in a VM entry failure.
10531 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10532 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10533 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10535 #ifdef CONFIG_X86_64
10536 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10537 CPU_BASED_CR8_STORE_EXITING
;
10542 * Merging of IO bitmap not currently supported.
10543 * Rather, exit every time.
10545 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10546 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10548 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10550 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10551 * bitwise-or of what L1 wants to trap for L2, and what we want to
10552 * trap. Note that CR0.TS also needs updating - we do this later.
10554 update_exception_bitmap(vcpu
);
10555 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10556 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10558 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10559 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10560 * bits are further modified by vmx_set_efer() below.
10562 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10564 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10565 * emulated by vmx_set_efer(), below.
10567 vm_entry_controls_init(vmx
,
10568 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10569 ~VM_ENTRY_IA32E_MODE
) |
10570 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10572 if (from_vmentry
&&
10573 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10574 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10575 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10576 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10577 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10580 set_cr4_guest_host_mask(vmx
);
10582 if (from_vmentry
&&
10583 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10584 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10586 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10587 vmcs_write64(TSC_OFFSET
,
10588 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10590 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10591 if (kvm_has_tsc_control
)
10592 decache_tsc_multiplier(vmx
);
10596 * There is no direct mapping between vpid02 and vpid12, the
10597 * vpid02 is per-vCPU for L0 and reused while the value of
10598 * vpid12 is changed w/ one invvpid during nested vmentry.
10599 * The vpid12 is allocated by L1 for L2, so it will not
10600 * influence global bitmap(for vpid01 and vpid02 allocation)
10601 * even if spawn a lot of nested vCPUs.
10603 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10604 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10605 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10606 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10607 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10610 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10611 vmx_flush_tlb(vcpu
);
10618 * Conceptually we want to copy the PML address and index from
10619 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10620 * since we always flush the log on each vmexit, this happens
10621 * to be equivalent to simply resetting the fields in vmcs02.
10623 ASSERT(vmx
->pml_pg
);
10624 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10625 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10628 if (nested_cpu_has_ept(vmcs12
)) {
10629 if (nested_ept_init_mmu_context(vcpu
)) {
10630 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10633 } else if (nested_cpu_has2(vmcs12
,
10634 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10635 vmx_flush_tlb_ept_only(vcpu
);
10639 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10640 * bits which we consider mandatory enabled.
10641 * The CR0_READ_SHADOW is what L2 should have expected to read given
10642 * the specifications by L1; It's not enough to take
10643 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10644 * have more bits than L1 expected.
10646 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10647 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10649 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10650 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10652 if (from_vmentry
&&
10653 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10654 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10655 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10656 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10658 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10659 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10660 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10662 /* Shadow page tables on either EPT or shadow page tables. */
10663 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10664 entry_failure_code
))
10668 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10671 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10674 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10675 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10676 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10677 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10680 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10681 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10685 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10687 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10689 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10690 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10691 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10693 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10694 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10696 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10697 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10699 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
10700 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10702 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10703 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10705 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10706 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10708 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10709 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10711 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10712 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10713 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10714 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10715 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10716 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10717 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10718 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10719 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10720 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10721 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10722 vmx
->nested
.nested_vmx_exit_ctls_low
,
10723 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10724 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10725 vmx
->nested
.nested_vmx_entry_ctls_low
,
10726 vmx
->nested
.nested_vmx_entry_ctls_high
))
10727 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10729 if (nested_cpu_has_vmfunc(vmcs12
)) {
10730 if (vmcs12
->vm_function_control
&
10731 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
10732 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10734 if (nested_cpu_has_eptp_switching(vmcs12
)) {
10735 if (!nested_cpu_has_ept(vmcs12
) ||
10736 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
10737 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10741 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10742 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10744 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10745 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10746 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10747 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10752 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10757 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10759 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10760 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10763 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10764 vmcs12
->vmcs_link_pointer
!= -1ull) {
10765 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10770 * If the load IA32_EFER VM-entry control is 1, the following checks
10771 * are performed on the field for the IA32_EFER MSR:
10772 * - Bits reserved in the IA32_EFER MSR must be 0.
10773 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10774 * the IA-32e mode guest VM-exit control. It must also be identical
10775 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10778 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10779 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10780 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10781 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10782 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10783 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10784 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10789 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10790 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10791 * the values of the LMA and LME bits in the field must each be that of
10792 * the host address-space size VM-exit control.
10794 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10795 ia32e
= (vmcs12
->vm_exit_controls
&
10796 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10797 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10798 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10799 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10803 if ((vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
) &&
10804 (is_noncanonical_address(vmcs12
->guest_bndcfgs
& PAGE_MASK
, vcpu
) ||
10805 (vmcs12
->guest_bndcfgs
& MSR_IA32_BNDCFGS_RSVD
)))
10811 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10813 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10814 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10818 enter_guest_mode(vcpu
);
10820 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10821 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10823 vmx_switch_vmcs(vcpu
, &vmx
->nested
.vmcs02
);
10824 vmx_segment_cache_clear(vmx
);
10826 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10827 leave_guest_mode(vcpu
);
10828 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10829 nested_vmx_entry_failure(vcpu
, vmcs12
,
10830 EXIT_REASON_INVALID_STATE
, exit_qual
);
10834 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10836 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10837 vmcs12
->vm_entry_msr_load_addr
,
10838 vmcs12
->vm_entry_msr_load_count
);
10839 if (msr_entry_idx
) {
10840 leave_guest_mode(vcpu
);
10841 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10842 nested_vmx_entry_failure(vcpu
, vmcs12
,
10843 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10848 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10849 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10850 * returned as far as L1 is concerned. It will only return (and set
10851 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10857 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10858 * for running an L2 nested guest.
10860 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10862 struct vmcs12
*vmcs12
;
10863 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10864 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10868 if (!nested_vmx_check_permission(vcpu
))
10871 if (!nested_vmx_check_vmcs12(vcpu
))
10874 vmcs12
= get_vmcs12(vcpu
);
10876 if (enable_shadow_vmcs
)
10877 copy_shadow_to_vmcs12(vmx
);
10880 * The nested entry process starts with enforcing various prerequisites
10881 * on vmcs12 as required by the Intel SDM, and act appropriately when
10882 * they fail: As the SDM explains, some conditions should cause the
10883 * instruction to fail, while others will cause the instruction to seem
10884 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10885 * To speed up the normal (success) code path, we should avoid checking
10886 * for misconfigurations which will anyway be caught by the processor
10887 * when using the merged vmcs02.
10889 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10890 nested_vmx_failValid(vcpu
,
10891 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10895 if (vmcs12
->launch_state
== launch
) {
10896 nested_vmx_failValid(vcpu
,
10897 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10898 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10902 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10904 nested_vmx_failValid(vcpu
, ret
);
10909 * After this point, the trap flag no longer triggers a singlestep trap
10910 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10911 * This is not 100% correct; for performance reasons, we delegate most
10912 * of the checks on host state to the processor. If those fail,
10913 * the singlestep trap is missed.
10915 skip_emulated_instruction(vcpu
);
10917 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10919 nested_vmx_entry_failure(vcpu
, vmcs12
,
10920 EXIT_REASON_INVALID_STATE
, exit_qual
);
10925 * We're finally done with prerequisite checking, and can start with
10926 * the nested entry.
10929 ret
= enter_vmx_non_root_mode(vcpu
, true);
10933 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10934 return kvm_vcpu_halt(vcpu
);
10936 vmx
->nested
.nested_run_pending
= 1;
10941 return kvm_skip_emulated_instruction(vcpu
);
10945 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10946 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10947 * This function returns the new value we should put in vmcs12.guest_cr0.
10948 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10949 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10950 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10951 * didn't trap the bit, because if L1 did, so would L0).
10952 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10953 * been modified by L2, and L1 knows it. So just leave the old value of
10954 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10955 * isn't relevant, because if L0 traps this bit it can set it to anything.
10956 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10957 * changed these bits, and therefore they need to be updated, but L0
10958 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10959 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10961 static inline unsigned long
10962 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10965 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10966 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10967 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10968 vcpu
->arch
.cr0_guest_owned_bits
));
10971 static inline unsigned long
10972 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10975 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10976 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10977 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10978 vcpu
->arch
.cr4_guest_owned_bits
));
10981 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10982 struct vmcs12
*vmcs12
)
10987 if (vcpu
->arch
.exception
.injected
) {
10988 nr
= vcpu
->arch
.exception
.nr
;
10989 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10991 if (kvm_exception_is_soft(nr
)) {
10992 vmcs12
->vm_exit_instruction_len
=
10993 vcpu
->arch
.event_exit_inst_len
;
10994 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10996 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10998 if (vcpu
->arch
.exception
.has_error_code
) {
10999 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
11000 vmcs12
->idt_vectoring_error_code
=
11001 vcpu
->arch
.exception
.error_code
;
11004 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11005 } else if (vcpu
->arch
.nmi_injected
) {
11006 vmcs12
->idt_vectoring_info_field
=
11007 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
11008 } else if (vcpu
->arch
.interrupt
.pending
) {
11009 nr
= vcpu
->arch
.interrupt
.nr
;
11010 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11012 if (vcpu
->arch
.interrupt
.soft
) {
11013 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11014 vmcs12
->vm_entry_instruction_len
=
11015 vcpu
->arch
.event_exit_inst_len
;
11017 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11019 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11023 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11025 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11026 unsigned long exit_qual
;
11027 bool block_nested_events
=
11028 vmx
->nested
.nested_run_pending
|| kvm_event_needs_reinjection(vcpu
);
11030 if (vcpu
->arch
.exception
.pending
&&
11031 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
11032 if (block_nested_events
)
11034 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
11035 vcpu
->arch
.exception
.pending
= false;
11039 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11040 vmx
->nested
.preemption_timer_expired
) {
11041 if (block_nested_events
)
11043 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11047 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11048 if (block_nested_events
)
11050 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11051 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11052 INTR_INFO_VALID_MASK
, 0);
11054 * The NMI-triggered VM exit counts as injection:
11055 * clear this one and block further NMIs.
11057 vcpu
->arch
.nmi_pending
= 0;
11058 vmx_set_nmi_mask(vcpu
, true);
11062 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11063 nested_exit_on_intr(vcpu
)) {
11064 if (block_nested_events
)
11066 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11070 vmx_complete_nested_posted_interrupt(vcpu
);
11074 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11076 ktime_t remaining
=
11077 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11080 if (ktime_to_ns(remaining
) <= 0)
11083 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11084 do_div(value
, 1000000);
11085 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11089 * Update the guest state fields of vmcs12 to reflect changes that
11090 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11091 * VM-entry controls is also updated, since this is really a guest
11094 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11096 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11097 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11099 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11100 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11101 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11103 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11104 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11105 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11106 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11107 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11108 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11109 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11110 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11111 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11112 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11113 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11114 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11115 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11116 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11117 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11118 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11119 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11120 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11121 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11122 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11123 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11124 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11125 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11126 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11127 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11128 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11129 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11130 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11131 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11132 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11133 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11134 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11135 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11136 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11137 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11138 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11140 vmcs12
->guest_interruptibility_info
=
11141 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11142 vmcs12
->guest_pending_dbg_exceptions
=
11143 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11144 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11145 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11147 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11149 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11150 if (vmcs12
->vm_exit_controls
&
11151 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11152 vmcs12
->vmx_preemption_timer_value
=
11153 vmx_get_preemption_timer_value(vcpu
);
11154 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11158 * In some cases (usually, nested EPT), L2 is allowed to change its
11159 * own CR3 without exiting. If it has changed it, we must keep it.
11160 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11161 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11163 * Additionally, restore L2's PDPTR to vmcs12.
11166 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11167 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11168 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11169 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11170 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11173 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11175 if (nested_cpu_has_vid(vmcs12
))
11176 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11178 vmcs12
->vm_entry_controls
=
11179 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11180 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11182 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11183 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11184 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11187 /* TODO: These cannot have changed unless we have MSR bitmaps and
11188 * the relevant bit asks not to trap the change */
11189 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11190 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11191 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11192 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11193 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11194 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11195 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11196 if (kvm_mpx_supported())
11197 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11201 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11202 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11203 * and this function updates it to reflect the changes to the guest state while
11204 * L2 was running (and perhaps made some exits which were handled directly by L0
11205 * without going back to L1), and to reflect the exit reason.
11206 * Note that we do not have to copy here all VMCS fields, just those that
11207 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11208 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11209 * which already writes to vmcs12 directly.
11211 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11212 u32 exit_reason
, u32 exit_intr_info
,
11213 unsigned long exit_qualification
)
11215 /* update guest state fields: */
11216 sync_vmcs12(vcpu
, vmcs12
);
11218 /* update exit information fields: */
11220 vmcs12
->vm_exit_reason
= exit_reason
;
11221 vmcs12
->exit_qualification
= exit_qualification
;
11222 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11224 vmcs12
->idt_vectoring_info_field
= 0;
11225 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11226 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11228 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11229 vmcs12
->launch_state
= 1;
11231 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11232 * instead of reading the real value. */
11233 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11236 * Transfer the event that L0 or L1 may wanted to inject into
11237 * L2 to IDT_VECTORING_INFO_FIELD.
11239 vmcs12_save_pending_event(vcpu
, vmcs12
);
11243 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11244 * preserved above and would only end up incorrectly in L1.
11246 vcpu
->arch
.nmi_injected
= false;
11247 kvm_clear_exception_queue(vcpu
);
11248 kvm_clear_interrupt_queue(vcpu
);
11251 static void load_vmcs12_mmu_host_state(struct kvm_vcpu
*vcpu
,
11252 struct vmcs12
*vmcs12
)
11254 u32 entry_failure_code
;
11256 nested_ept_uninit_mmu_context(vcpu
);
11259 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11260 * couldn't have changed.
11262 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11263 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11266 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11270 * A part of what we need to when the nested L2 guest exits and we want to
11271 * run its L1 parent, is to reset L1's guest state to the host state specified
11273 * This function is to be called not only on normal nested exit, but also on
11274 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11275 * Failures During or After Loading Guest State").
11276 * This function should be called when the active VMCS is L1's (vmcs01).
11278 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11279 struct vmcs12
*vmcs12
)
11281 struct kvm_segment seg
;
11283 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11284 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11285 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11286 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11288 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11289 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11291 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11292 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11293 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11295 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11296 * actually changed, because vmx_set_cr0 refers to efer set above.
11298 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11299 * (KVM doesn't change it);
11301 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11302 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11304 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11305 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11306 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11308 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
11312 * Trivially support vpid by letting L2s share their parent
11313 * L1's vpid. TODO: move to a more elaborate solution, giving
11314 * each L2 its own vpid and exposing the vpid feature to L1.
11316 vmx_flush_tlb(vcpu
);
11318 /* Restore posted intr vector. */
11319 if (nested_cpu_has_posted_intr(vmcs12
))
11320 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11322 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11323 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11324 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11325 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11326 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11327 vmcs_write32(GUEST_IDTR_LIMIT
, 0xFFFF);
11328 vmcs_write32(GUEST_GDTR_LIMIT
, 0xFFFF);
11330 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11331 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11332 vmcs_write64(GUEST_BNDCFGS
, 0);
11334 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11335 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11336 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11338 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11339 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11340 vmcs12
->host_ia32_perf_global_ctrl
);
11342 /* Set L1 segment info according to Intel SDM
11343 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11344 seg
= (struct kvm_segment
) {
11346 .limit
= 0xFFFFFFFF,
11347 .selector
= vmcs12
->host_cs_selector
,
11353 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11357 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11358 seg
= (struct kvm_segment
) {
11360 .limit
= 0xFFFFFFFF,
11367 seg
.selector
= vmcs12
->host_ds_selector
;
11368 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11369 seg
.selector
= vmcs12
->host_es_selector
;
11370 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11371 seg
.selector
= vmcs12
->host_ss_selector
;
11372 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11373 seg
.selector
= vmcs12
->host_fs_selector
;
11374 seg
.base
= vmcs12
->host_fs_base
;
11375 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11376 seg
.selector
= vmcs12
->host_gs_selector
;
11377 seg
.base
= vmcs12
->host_gs_base
;
11378 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11379 seg
= (struct kvm_segment
) {
11380 .base
= vmcs12
->host_tr_base
,
11382 .selector
= vmcs12
->host_tr_selector
,
11386 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11388 kvm_set_dr(vcpu
, 7, 0x400);
11389 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11391 if (cpu_has_vmx_msr_bitmap())
11392 vmx_set_msr_bitmap(vcpu
);
11394 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11395 vmcs12
->vm_exit_msr_load_count
))
11396 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11400 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11401 * and modify vmcs12 to make it see what it would expect to see there if
11402 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11404 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11405 u32 exit_intr_info
,
11406 unsigned long exit_qualification
)
11408 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11409 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11411 /* trying to cancel vmlaunch/vmresume is a bug */
11412 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11415 * The only expected VM-instruction error is "VM entry with
11416 * invalid control field(s)." Anything else indicates a
11419 WARN_ON_ONCE(vmx
->fail
&& (vmcs_read32(VM_INSTRUCTION_ERROR
) !=
11420 VMXERR_ENTRY_INVALID_CONTROL_FIELD
));
11422 leave_guest_mode(vcpu
);
11424 if (likely(!vmx
->fail
)) {
11425 if (exit_reason
== -1)
11426 sync_vmcs12(vcpu
, vmcs12
);
11428 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11429 exit_qualification
);
11431 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11432 vmcs12
->vm_exit_msr_store_count
))
11433 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11436 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11437 vm_entry_controls_reset_shadow(vmx
);
11438 vm_exit_controls_reset_shadow(vmx
);
11439 vmx_segment_cache_clear(vmx
);
11441 /* Update any VMCS fields that might have changed while L2 ran */
11442 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11443 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11444 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11445 if (vmx
->hv_deadline_tsc
== -1)
11446 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11447 PIN_BASED_VMX_PREEMPTION_TIMER
);
11449 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11450 PIN_BASED_VMX_PREEMPTION_TIMER
);
11451 if (kvm_has_tsc_control
)
11452 decache_tsc_multiplier(vmx
);
11454 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11455 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11456 vmx_set_virtual_x2apic_mode(vcpu
,
11457 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11458 } else if (!nested_cpu_has_ept(vmcs12
) &&
11459 nested_cpu_has2(vmcs12
,
11460 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11461 vmx_flush_tlb_ept_only(vcpu
);
11464 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11467 /* Unpin physical memory we referred to in vmcs02 */
11468 if (vmx
->nested
.apic_access_page
) {
11469 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11470 vmx
->nested
.apic_access_page
= NULL
;
11472 if (vmx
->nested
.virtual_apic_page
) {
11473 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11474 vmx
->nested
.virtual_apic_page
= NULL
;
11476 if (vmx
->nested
.pi_desc_page
) {
11477 kunmap(vmx
->nested
.pi_desc_page
);
11478 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11479 vmx
->nested
.pi_desc_page
= NULL
;
11480 vmx
->nested
.pi_desc
= NULL
;
11484 * We are now running in L2, mmu_notifier will force to reload the
11485 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11487 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11489 if (enable_shadow_vmcs
&& exit_reason
!= -1)
11490 vmx
->nested
.sync_shadow_vmcs
= true;
11492 /* in case we halted in L2 */
11493 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11495 if (likely(!vmx
->fail
)) {
11497 * TODO: SDM says that with acknowledge interrupt on
11498 * exit, bit 31 of the VM-exit interrupt information
11499 * (valid interrupt) is always set to 1 on
11500 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11501 * need kvm_cpu_has_interrupt(). See the commit
11502 * message for details.
11504 if (nested_exit_intr_ack_set(vcpu
) &&
11505 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11506 kvm_cpu_has_interrupt(vcpu
)) {
11507 int irq
= kvm_cpu_get_interrupt(vcpu
);
11509 vmcs12
->vm_exit_intr_info
= irq
|
11510 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11513 if (exit_reason
!= -1)
11514 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11515 vmcs12
->exit_qualification
,
11516 vmcs12
->idt_vectoring_info_field
,
11517 vmcs12
->vm_exit_intr_info
,
11518 vmcs12
->vm_exit_intr_error_code
,
11521 load_vmcs12_host_state(vcpu
, vmcs12
);
11527 * After an early L2 VM-entry failure, we're now back
11528 * in L1 which thinks it just finished a VMLAUNCH or
11529 * VMRESUME instruction, so we need to set the failure
11530 * flag and the VM-instruction error field of the VMCS
11533 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11535 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
11538 * The emulated instruction was already skipped in
11539 * nested_vmx_run, but the updated RIP was never
11540 * written back to the vmcs01.
11542 skip_emulated_instruction(vcpu
);
11547 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11549 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11551 if (is_guest_mode(vcpu
)) {
11552 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11553 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11555 free_nested(to_vmx(vcpu
));
11559 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11560 * 23.7 "VM-entry failures during or after loading guest state" (this also
11561 * lists the acceptable exit-reason and exit-qualification parameters).
11562 * It should only be called before L2 actually succeeded to run, and when
11563 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11565 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11566 struct vmcs12
*vmcs12
,
11567 u32 reason
, unsigned long qualification
)
11569 load_vmcs12_host_state(vcpu
, vmcs12
);
11570 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11571 vmcs12
->exit_qualification
= qualification
;
11572 nested_vmx_succeed(vcpu
);
11573 if (enable_shadow_vmcs
)
11574 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11577 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11578 struct x86_instruction_info
*info
,
11579 enum x86_intercept_stage stage
)
11581 return X86EMUL_CONTINUE
;
11584 #ifdef CONFIG_X86_64
11585 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11586 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11587 u64 divisor
, u64
*result
)
11589 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11591 /* To avoid the overflow on divq */
11592 if (high
>= divisor
)
11595 /* Low hold the result, high hold rem which is discarded */
11596 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11597 "rm" (divisor
), "0" (low
), "1" (high
));
11603 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11605 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11606 u64 tscl
= rdtsc();
11607 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11608 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11610 /* Convert to host delta tsc if tsc scaling is enabled */
11611 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11612 u64_shl_div_u64(delta_tsc
,
11613 kvm_tsc_scaling_ratio_frac_bits
,
11614 vcpu
->arch
.tsc_scaling_ratio
,
11619 * If the delta tsc can't fit in the 32 bit after the multi shift,
11620 * we can't use the preemption timer.
11621 * It's possible that it fits on later vmentries, but checking
11622 * on every vmentry is costly so we just use an hrtimer.
11624 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11627 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11628 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11629 PIN_BASED_VMX_PREEMPTION_TIMER
);
11631 return delta_tsc
== 0;
11634 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11636 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11637 vmx
->hv_deadline_tsc
= -1;
11638 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11639 PIN_BASED_VMX_PREEMPTION_TIMER
);
11643 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11646 shrink_ple_window(vcpu
);
11649 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11650 struct kvm_memory_slot
*slot
)
11652 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11653 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11656 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11657 struct kvm_memory_slot
*slot
)
11659 kvm_mmu_slot_set_dirty(kvm
, slot
);
11662 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11664 kvm_flush_pml_buffers(kvm
);
11667 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11669 struct vmcs12
*vmcs12
;
11670 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11672 struct page
*page
= NULL
;
11675 if (is_guest_mode(vcpu
)) {
11676 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11679 * Check if PML is enabled for the nested guest.
11680 * Whether eptp bit 6 is set is already checked
11681 * as part of A/D emulation.
11683 vmcs12
= get_vmcs12(vcpu
);
11684 if (!nested_cpu_has_pml(vmcs12
))
11687 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11688 vmx
->nested
.pml_full
= true;
11692 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11694 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11695 if (is_error_page(page
))
11698 pml_address
= kmap(page
);
11699 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11701 kvm_release_page_clean(page
);
11707 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11708 struct kvm_memory_slot
*memslot
,
11709 gfn_t offset
, unsigned long mask
)
11711 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11714 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
11716 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11717 struct pi_desc old
, new;
11721 old
.control
= new.control
= pi_desc
->control
;
11722 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
11723 "Wakeup handler not enabled while the VCPU is blocked\n");
11725 dest
= cpu_physical_id(vcpu
->cpu
);
11727 if (x2apic_enabled())
11730 new.ndst
= (dest
<< 8) & 0xFF00;
11732 /* set 'NV' to 'notification vector' */
11733 new.nv
= POSTED_INTR_VECTOR
;
11734 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11735 new.control
) != old
.control
);
11737 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
11738 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11739 list_del(&vcpu
->blocked_vcpu_list
);
11740 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11741 vcpu
->pre_pcpu
= -1;
11746 * This routine does the following things for vCPU which is going
11747 * to be blocked if VT-d PI is enabled.
11748 * - Store the vCPU to the wakeup list, so when interrupts happen
11749 * we can find the right vCPU to wake up.
11750 * - Change the Posted-interrupt descriptor as below:
11751 * 'NDST' <-- vcpu->pre_pcpu
11752 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11753 * - If 'ON' is set during this process, which means at least one
11754 * interrupt is posted for this vCPU, we cannot block it, in
11755 * this case, return 1, otherwise, return 0.
11758 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11761 struct pi_desc old
, new;
11762 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11764 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11765 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11766 !kvm_vcpu_apicv_active(vcpu
))
11769 WARN_ON(irqs_disabled());
11770 local_irq_disable();
11771 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
11772 vcpu
->pre_pcpu
= vcpu
->cpu
;
11773 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11774 list_add_tail(&vcpu
->blocked_vcpu_list
,
11775 &per_cpu(blocked_vcpu_on_cpu
,
11777 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11781 old
.control
= new.control
= pi_desc
->control
;
11783 WARN((pi_desc
->sn
== 1),
11784 "Warning: SN field of posted-interrupts "
11785 "is set before blocking\n");
11788 * Since vCPU can be preempted during this process,
11789 * vcpu->cpu could be different with pre_pcpu, we
11790 * need to set pre_pcpu as the destination of wakeup
11791 * notification event, then we can find the right vCPU
11792 * to wakeup in wakeup handler if interrupts happen
11793 * when the vCPU is in blocked state.
11795 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11797 if (x2apic_enabled())
11800 new.ndst
= (dest
<< 8) & 0xFF00;
11802 /* set 'NV' to 'wakeup vector' */
11803 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11804 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11805 new.control
) != old
.control
);
11807 /* We should not block the vCPU if an interrupt is posted for it. */
11808 if (pi_test_on(pi_desc
) == 1)
11809 __pi_post_block(vcpu
);
11811 local_irq_enable();
11812 return (vcpu
->pre_pcpu
== -1);
11815 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11817 if (pi_pre_block(vcpu
))
11820 if (kvm_lapic_hv_timer_in_use(vcpu
))
11821 kvm_lapic_switch_to_sw_timer(vcpu
);
11826 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11828 if (vcpu
->pre_pcpu
== -1)
11831 WARN_ON(irqs_disabled());
11832 local_irq_disable();
11833 __pi_post_block(vcpu
);
11834 local_irq_enable();
11837 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11839 if (kvm_x86_ops
->set_hv_timer
)
11840 kvm_lapic_switch_to_hv_timer(vcpu
);
11842 pi_post_block(vcpu
);
11846 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11849 * @host_irq: host irq of the interrupt
11850 * @guest_irq: gsi of the interrupt
11851 * @set: set or unset PI
11852 * returns 0 on success, < 0 on failure
11854 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11855 uint32_t guest_irq
, bool set
)
11857 struct kvm_kernel_irq_routing_entry
*e
;
11858 struct kvm_irq_routing_table
*irq_rt
;
11859 struct kvm_lapic_irq irq
;
11860 struct kvm_vcpu
*vcpu
;
11861 struct vcpu_data vcpu_info
;
11864 if (!kvm_arch_has_assigned_device(kvm
) ||
11865 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11866 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11869 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11870 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11871 if (guest_irq
>= irq_rt
->nr_rt_entries
||
11872 hlist_empty(&irq_rt
->map
[guest_irq
])) {
11873 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11874 guest_irq
, irq_rt
->nr_rt_entries
);
11878 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11879 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11882 * VT-d PI cannot support posting multicast/broadcast
11883 * interrupts to a vCPU, we still use interrupt remapping
11884 * for these kind of interrupts.
11886 * For lowest-priority interrupts, we only support
11887 * those with single CPU as the destination, e.g. user
11888 * configures the interrupts via /proc/irq or uses
11889 * irqbalance to make the interrupts single-CPU.
11891 * We will support full lowest-priority interrupt later.
11894 kvm_set_msi_irq(kvm
, e
, &irq
);
11895 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11897 * Make sure the IRTE is in remapped mode if
11898 * we don't handle it in posted mode.
11900 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11903 "failed to back to remapped mode, irq: %u\n",
11911 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11912 vcpu_info
.vector
= irq
.vector
;
11914 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11915 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11918 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11920 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11923 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11931 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11935 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11937 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11938 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11939 FEATURE_CONTROL_LMCE
;
11941 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11942 ~FEATURE_CONTROL_LMCE
;
11945 static int vmx_smi_allowed(struct kvm_vcpu
*vcpu
)
11947 /* we need a nested vmexit to enter SMM, postpone if run is pending */
11948 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
11953 static int vmx_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
11955 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11957 vmx
->nested
.smm
.guest_mode
= is_guest_mode(vcpu
);
11958 if (vmx
->nested
.smm
.guest_mode
)
11959 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11961 vmx
->nested
.smm
.vmxon
= vmx
->nested
.vmxon
;
11962 vmx
->nested
.vmxon
= false;
11966 static int vmx_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
11968 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11971 if (vmx
->nested
.smm
.vmxon
) {
11972 vmx
->nested
.vmxon
= true;
11973 vmx
->nested
.smm
.vmxon
= false;
11976 if (vmx
->nested
.smm
.guest_mode
) {
11977 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
11978 ret
= enter_vmx_non_root_mode(vcpu
, false);
11979 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
11983 vmx
->nested
.smm
.guest_mode
= false;
11988 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
11993 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11994 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11995 .disabled_by_bios
= vmx_disabled_by_bios
,
11996 .hardware_setup
= hardware_setup
,
11997 .hardware_unsetup
= hardware_unsetup
,
11998 .check_processor_compatibility
= vmx_check_processor_compat
,
11999 .hardware_enable
= hardware_enable
,
12000 .hardware_disable
= hardware_disable
,
12001 .cpu_has_accelerated_tpr
= report_flexpriority
,
12002 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
12004 .vcpu_create
= vmx_create_vcpu
,
12005 .vcpu_free
= vmx_free_vcpu
,
12006 .vcpu_reset
= vmx_vcpu_reset
,
12008 .prepare_guest_switch
= vmx_save_host_state
,
12009 .vcpu_load
= vmx_vcpu_load
,
12010 .vcpu_put
= vmx_vcpu_put
,
12012 .update_bp_intercept
= update_exception_bitmap
,
12013 .get_msr
= vmx_get_msr
,
12014 .set_msr
= vmx_set_msr
,
12015 .get_segment_base
= vmx_get_segment_base
,
12016 .get_segment
= vmx_get_segment
,
12017 .set_segment
= vmx_set_segment
,
12018 .get_cpl
= vmx_get_cpl
,
12019 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
12020 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
12021 .decache_cr3
= vmx_decache_cr3
,
12022 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
12023 .set_cr0
= vmx_set_cr0
,
12024 .set_cr3
= vmx_set_cr3
,
12025 .set_cr4
= vmx_set_cr4
,
12026 .set_efer
= vmx_set_efer
,
12027 .get_idt
= vmx_get_idt
,
12028 .set_idt
= vmx_set_idt
,
12029 .get_gdt
= vmx_get_gdt
,
12030 .set_gdt
= vmx_set_gdt
,
12031 .get_dr6
= vmx_get_dr6
,
12032 .set_dr6
= vmx_set_dr6
,
12033 .set_dr7
= vmx_set_dr7
,
12034 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
12035 .cache_reg
= vmx_cache_reg
,
12036 .get_rflags
= vmx_get_rflags
,
12037 .set_rflags
= vmx_set_rflags
,
12039 .tlb_flush
= vmx_flush_tlb
,
12041 .run
= vmx_vcpu_run
,
12042 .handle_exit
= vmx_handle_exit
,
12043 .skip_emulated_instruction
= skip_emulated_instruction
,
12044 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
12045 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
12046 .patch_hypercall
= vmx_patch_hypercall
,
12047 .set_irq
= vmx_inject_irq
,
12048 .set_nmi
= vmx_inject_nmi
,
12049 .queue_exception
= vmx_queue_exception
,
12050 .cancel_injection
= vmx_cancel_injection
,
12051 .interrupt_allowed
= vmx_interrupt_allowed
,
12052 .nmi_allowed
= vmx_nmi_allowed
,
12053 .get_nmi_mask
= vmx_get_nmi_mask
,
12054 .set_nmi_mask
= vmx_set_nmi_mask
,
12055 .enable_nmi_window
= enable_nmi_window
,
12056 .enable_irq_window
= enable_irq_window
,
12057 .update_cr8_intercept
= update_cr8_intercept
,
12058 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
12059 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
12060 .get_enable_apicv
= vmx_get_enable_apicv
,
12061 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
12062 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
12063 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
12064 .hwapic_irr_update
= vmx_hwapic_irr_update
,
12065 .hwapic_isr_update
= vmx_hwapic_isr_update
,
12066 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
12067 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
12069 .set_tss_addr
= vmx_set_tss_addr
,
12070 .get_tdp_level
= get_ept_level
,
12071 .get_mt_mask
= vmx_get_mt_mask
,
12073 .get_exit_info
= vmx_get_exit_info
,
12075 .get_lpage_level
= vmx_get_lpage_level
,
12077 .cpuid_update
= vmx_cpuid_update
,
12079 .rdtscp_supported
= vmx_rdtscp_supported
,
12080 .invpcid_supported
= vmx_invpcid_supported
,
12082 .set_supported_cpuid
= vmx_set_supported_cpuid
,
12084 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
12086 .write_tsc_offset
= vmx_write_tsc_offset
,
12088 .set_tdp_cr3
= vmx_set_cr3
,
12090 .check_intercept
= vmx_check_intercept
,
12091 .handle_external_intr
= vmx_handle_external_intr
,
12092 .mpx_supported
= vmx_mpx_supported
,
12093 .xsaves_supported
= vmx_xsaves_supported
,
12095 .check_nested_events
= vmx_check_nested_events
,
12097 .sched_in
= vmx_sched_in
,
12099 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
12100 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
12101 .flush_log_dirty
= vmx_flush_log_dirty
,
12102 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
12103 .write_log_dirty
= vmx_write_pml_buffer
,
12105 .pre_block
= vmx_pre_block
,
12106 .post_block
= vmx_post_block
,
12108 .pmu_ops
= &intel_pmu_ops
,
12110 .update_pi_irte
= vmx_update_pi_irte
,
12112 #ifdef CONFIG_X86_64
12113 .set_hv_timer
= vmx_set_hv_timer
,
12114 .cancel_hv_timer
= vmx_cancel_hv_timer
,
12117 .setup_mce
= vmx_setup_mce
,
12119 .smi_allowed
= vmx_smi_allowed
,
12120 .pre_enter_smm
= vmx_pre_enter_smm
,
12121 .pre_leave_smm
= vmx_pre_leave_smm
,
12122 .enable_smi_window
= enable_smi_window
,
12125 static int __init
vmx_init(void)
12127 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
12128 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
12132 #ifdef CONFIG_KEXEC_CORE
12133 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
12134 crash_vmclear_local_loaded_vmcss
);
12140 static void __exit
vmx_exit(void)
12142 #ifdef CONFIG_KEXEC_CORE
12143 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
12150 module_init(vmx_init
)
12151 module_exit(vmx_exit
)