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Merge git://git.kvack.org/~bcrl/aio-next
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
35 #include "x86.h"
36
37 #include <asm/io.h>
38 #include <asm/desc.h>
39 #include <asm/vmx.h>
40 #include <asm/virtext.h>
41 #include <asm/mce.h>
42 #include <asm/i387.h>
43 #include <asm/xcr.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
46
47 #include "trace.h"
48
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
52
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
55
56 static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59 };
60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
62 static bool __read_mostly enable_vpid = 1;
63 module_param_named(vpid, enable_vpid, bool, 0444);
64
65 static bool __read_mostly flexpriority_enabled = 1;
66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
67
68 static bool __read_mostly enable_ept = 1;
69 module_param_named(ept, enable_ept, bool, S_IRUGO);
70
71 static bool __read_mostly enable_unrestricted_guest = 1;
72 module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
75 static bool __read_mostly enable_ept_ad_bits = 1;
76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
78 static bool __read_mostly emulate_invalid_guest_state = true;
79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
80
81 static bool __read_mostly vmm_exclusive = 1;
82 module_param(vmm_exclusive, bool, S_IRUGO);
83
84 static bool __read_mostly fasteoi = 1;
85 module_param(fasteoi, bool, S_IRUGO);
86
87 static bool __read_mostly enable_apicv = 1;
88 module_param(enable_apicv, bool, S_IRUGO);
89
90 static bool __read_mostly enable_shadow_vmcs = 1;
91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
92 /*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
97 static bool __read_mostly nested = 0;
98 module_param(nested, bool, S_IRUGO);
99
100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
102 #define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
104 #define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
113 /*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
117 * According to test, this time is usually smaller than 128 cycles.
118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
124 #define KVM_VMX_DEFAULT_PLE_GAP 128
125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127 module_param(ple_gap, int, S_IRUGO);
128
129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130 module_param(ple_window, int, S_IRUGO);
131
132 extern const ulong vmx_return;
133
134 #define NR_AUTOLOAD_MSRS 8
135 #define VMCS02_POOL_SIZE 1
136
137 struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141 };
142
143 /*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148 struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153 };
154
155 struct shared_msr_entry {
156 unsigned index;
157 u64 data;
158 u64 mask;
159 };
160
161 /*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
174 typedef u64 natural_width;
175 struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
181
182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
322 };
323
324 /*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329 #define VMCS12_REVISION 0x11e57ed0
330
331 /*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336 #define VMCS12_SIZE 0x1000
337
338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
339 struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343 };
344
345 /*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349 struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
358 struct vmcs *current_shadow_vmcs;
359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
368 u64 vmcs01_tsc_offset;
369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
376 u64 msr_ia32_feature_control;
377 };
378
379 #define POSTED_INTR_ON 0
380 /* Posted-Interrupt Descriptor */
381 struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385 } __aligned(64);
386
387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388 {
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391 }
392
393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394 {
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397 }
398
399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400 {
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402 }
403
404 struct vcpu_vmx {
405 struct kvm_vcpu vcpu;
406 unsigned long host_rsp;
407 u8 fail;
408 u8 cpl;
409 bool nmi_known_unmasked;
410 u32 exit_intr_info;
411 u32 idt_vectoring_info;
412 ulong rflags;
413 struct shared_msr_entry *guest_msrs;
414 int nmsrs;
415 int save_nmsrs;
416 unsigned long host_idt_base;
417 #ifdef CONFIG_X86_64
418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
420 #endif
421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
437 #ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439 #endif
440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
442 } host_state;
443 struct {
444 int vm86_active;
445 ulong save_rflags;
446 struct kvm_segment segs[8];
447 } rmode;
448 struct {
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
450 struct kvm_save_segment {
451 u16 selector;
452 unsigned long base;
453 u32 limit;
454 u32 ar;
455 } seg[8];
456 } segment_cache;
457 int vpid;
458 bool emulation_required;
459
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
462 ktime_t entry_time;
463 s64 vnmi_blocked_time;
464 u32 exit_reason;
465
466 bool rdtscp_enabled;
467
468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
470
471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
473 };
474
475 enum segment_cache_field {
476 SEG_FIELD_SEL = 0,
477 SEG_FIELD_BASE = 1,
478 SEG_FIELD_LIMIT = 2,
479 SEG_FIELD_AR = 3,
480
481 SEG_FIELD_NR = 4
482 };
483
484 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
485 {
486 return container_of(vcpu, struct vcpu_vmx, vcpu);
487 }
488
489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
493
494
495 static const unsigned long shadow_read_only_fields[] = {
496 /*
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
507 */
508 VM_EXIT_REASON,
509 VM_EXIT_INTR_INFO,
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
514 EXIT_QUALIFICATION,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
517 };
518 static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
520
521 static const unsigned long shadow_read_write_fields[] = {
522 GUEST_RIP,
523 GUEST_RSP,
524 GUEST_CR0,
525 GUEST_CR3,
526 GUEST_CR4,
527 GUEST_INTERRUPTIBILITY_INFO,
528 GUEST_RFLAGS,
529 GUEST_CS_SELECTOR,
530 GUEST_CS_AR_BYTES,
531 GUEST_CS_LIMIT,
532 GUEST_CS_BASE,
533 GUEST_ES_BASE,
534 CR0_GUEST_HOST_MASK,
535 CR0_READ_SHADOW,
536 CR4_READ_SHADOW,
537 TSC_OFFSET,
538 EXCEPTION_BITMAP,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 HOST_FS_BASE,
545 HOST_GS_BASE,
546 HOST_FS_SELECTOR,
547 HOST_GS_SELECTOR
548 };
549 static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
551
552 static const unsigned short vmcs_field_to_offset_table[] = {
553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
681 };
682 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
683
684 static inline short vmcs_field_to_offset(unsigned long field)
685 {
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
687 return -1;
688 return vmcs_field_to_offset_table[field];
689 }
690
691 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
692 {
693 return to_vmx(vcpu)->nested.current_vmcs12;
694 }
695
696 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
697 {
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
699 if (is_error_page(page))
700 return NULL;
701
702 return page;
703 }
704
705 static void nested_release_page(struct page *page)
706 {
707 kvm_release_page_dirty(page);
708 }
709
710 static void nested_release_page_clean(struct page *page)
711 {
712 kvm_release_page_clean(page);
713 }
714
715 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
716 static u64 construct_eptp(unsigned long root_hpa);
717 static void kvm_cpu_vmxon(u64 addr);
718 static void kvm_cpu_vmxoff(void);
719 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
720 static void vmx_set_segment(struct kvm_vcpu *vcpu,
721 struct kvm_segment *var, int seg);
722 static void vmx_get_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
724 static bool guest_state_valid(struct kvm_vcpu *vcpu);
725 static u32 vmx_segment_access_rights(struct kvm_segment *var);
726 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
727 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
728 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
729
730 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
731 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
732 /*
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
735 */
736 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
737 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
738
739 static unsigned long *vmx_io_bitmap_a;
740 static unsigned long *vmx_io_bitmap_b;
741 static unsigned long *vmx_msr_bitmap_legacy;
742 static unsigned long *vmx_msr_bitmap_longmode;
743 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
744 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
745 static unsigned long *vmx_vmread_bitmap;
746 static unsigned long *vmx_vmwrite_bitmap;
747
748 static bool cpu_has_load_ia32_efer;
749 static bool cpu_has_load_perf_global_ctrl;
750
751 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
752 static DEFINE_SPINLOCK(vmx_vpid_lock);
753
754 static struct vmcs_config {
755 int size;
756 int order;
757 u32 revision_id;
758 u32 pin_based_exec_ctrl;
759 u32 cpu_based_exec_ctrl;
760 u32 cpu_based_2nd_exec_ctrl;
761 u32 vmexit_ctrl;
762 u32 vmentry_ctrl;
763 } vmcs_config;
764
765 static struct vmx_capability {
766 u32 ept;
767 u32 vpid;
768 } vmx_capability;
769
770 #define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
776 }
777
778 static const struct kvm_vmx_segment_field {
779 unsigned selector;
780 unsigned base;
781 unsigned limit;
782 unsigned ar_bytes;
783 } kvm_vmx_segment_fields[] = {
784 VMX_SEGMENT_FIELD(CS),
785 VMX_SEGMENT_FIELD(DS),
786 VMX_SEGMENT_FIELD(ES),
787 VMX_SEGMENT_FIELD(FS),
788 VMX_SEGMENT_FIELD(GS),
789 VMX_SEGMENT_FIELD(SS),
790 VMX_SEGMENT_FIELD(TR),
791 VMX_SEGMENT_FIELD(LDTR),
792 };
793
794 static u64 host_efer;
795
796 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
797
798 /*
799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
800 * away by decrementing the array size.
801 */
802 static const u32 vmx_msr_index[] = {
803 #ifdef CONFIG_X86_64
804 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
805 #endif
806 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
807 };
808 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
809
810 static inline bool is_page_fault(u32 intr_info)
811 {
812 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
813 INTR_INFO_VALID_MASK)) ==
814 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
815 }
816
817 static inline bool is_no_device(u32 intr_info)
818 {
819 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
820 INTR_INFO_VALID_MASK)) ==
821 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
822 }
823
824 static inline bool is_invalid_opcode(u32 intr_info)
825 {
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
828 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
829 }
830
831 static inline bool is_external_interrupt(u32 intr_info)
832 {
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
834 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
835 }
836
837 static inline bool is_machine_check(u32 intr_info)
838 {
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
841 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
842 }
843
844 static inline bool cpu_has_vmx_msr_bitmap(void)
845 {
846 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
847 }
848
849 static inline bool cpu_has_vmx_tpr_shadow(void)
850 {
851 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
852 }
853
854 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
855 {
856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
857 }
858
859 static inline bool cpu_has_secondary_exec_ctrls(void)
860 {
861 return vmcs_config.cpu_based_exec_ctrl &
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
863 }
864
865 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
866 {
867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
869 }
870
871 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
872 {
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
875 }
876
877 static inline bool cpu_has_vmx_apic_register_virt(void)
878 {
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_APIC_REGISTER_VIRT;
881 }
882
883 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
884 {
885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
887 }
888
889 static inline bool cpu_has_vmx_posted_intr(void)
890 {
891 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
892 }
893
894 static inline bool cpu_has_vmx_apicv(void)
895 {
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
899 }
900
901 static inline bool cpu_has_vmx_flexpriority(void)
902 {
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
905 }
906
907 static inline bool cpu_has_vmx_ept_execute_only(void)
908 {
909 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
910 }
911
912 static inline bool cpu_has_vmx_eptp_uncacheable(void)
913 {
914 return vmx_capability.ept & VMX_EPTP_UC_BIT;
915 }
916
917 static inline bool cpu_has_vmx_eptp_writeback(void)
918 {
919 return vmx_capability.ept & VMX_EPTP_WB_BIT;
920 }
921
922 static inline bool cpu_has_vmx_ept_2m_page(void)
923 {
924 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
925 }
926
927 static inline bool cpu_has_vmx_ept_1g_page(void)
928 {
929 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
930 }
931
932 static inline bool cpu_has_vmx_ept_4levels(void)
933 {
934 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
935 }
936
937 static inline bool cpu_has_vmx_ept_ad_bits(void)
938 {
939 return vmx_capability.ept & VMX_EPT_AD_BIT;
940 }
941
942 static inline bool cpu_has_vmx_invept_context(void)
943 {
944 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
945 }
946
947 static inline bool cpu_has_vmx_invept_global(void)
948 {
949 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
950 }
951
952 static inline bool cpu_has_vmx_invvpid_single(void)
953 {
954 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
955 }
956
957 static inline bool cpu_has_vmx_invvpid_global(void)
958 {
959 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
960 }
961
962 static inline bool cpu_has_vmx_ept(void)
963 {
964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_ENABLE_EPT;
966 }
967
968 static inline bool cpu_has_vmx_unrestricted_guest(void)
969 {
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_UNRESTRICTED_GUEST;
972 }
973
974 static inline bool cpu_has_vmx_ple(void)
975 {
976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
978 }
979
980 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
981 {
982 return flexpriority_enabled && irqchip_in_kernel(kvm);
983 }
984
985 static inline bool cpu_has_vmx_vpid(void)
986 {
987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_ENABLE_VPID;
989 }
990
991 static inline bool cpu_has_vmx_rdtscp(void)
992 {
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_RDTSCP;
995 }
996
997 static inline bool cpu_has_vmx_invpcid(void)
998 {
999 return vmcs_config.cpu_based_2nd_exec_ctrl &
1000 SECONDARY_EXEC_ENABLE_INVPCID;
1001 }
1002
1003 static inline bool cpu_has_virtual_nmis(void)
1004 {
1005 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006 }
1007
1008 static inline bool cpu_has_vmx_wbinvd_exit(void)
1009 {
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_WBINVD_EXITING;
1012 }
1013
1014 static inline bool cpu_has_vmx_shadow_vmcs(void)
1015 {
1016 u64 vmx_msr;
1017 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020 return false;
1021
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_SHADOW_VMCS;
1024 }
1025
1026 static inline bool report_flexpriority(void)
1027 {
1028 return flexpriority_enabled;
1029 }
1030
1031 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032 {
1033 return vmcs12->cpu_based_vm_exec_control & bit;
1034 }
1035
1036 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037 {
1038 return (vmcs12->cpu_based_vm_exec_control &
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040 (vmcs12->secondary_vm_exec_control & bit);
1041 }
1042
1043 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1044 {
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046 }
1047
1048 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049 {
1050 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051 }
1052
1053 static inline bool is_exception(u32 intr_info)
1054 {
1055 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057 }
1058
1059 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1060 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061 struct vmcs12 *vmcs12,
1062 u32 reason, unsigned long qualification);
1063
1064 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1065 {
1066 int i;
1067
1068 for (i = 0; i < vmx->nmsrs; ++i)
1069 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1070 return i;
1071 return -1;
1072 }
1073
1074 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075 {
1076 struct {
1077 u64 vpid : 16;
1078 u64 rsvd : 48;
1079 u64 gva;
1080 } operand = { vpid, 0, gva };
1081
1082 asm volatile (__ex(ASM_VMX_INVVPID)
1083 /* CF==1 or ZF==1 --> rc = -1 */
1084 "; ja 1f ; ud2 ; 1:"
1085 : : "a"(&operand), "c"(ext) : "cc", "memory");
1086 }
1087
1088 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089 {
1090 struct {
1091 u64 eptp, gpa;
1092 } operand = {eptp, gpa};
1093
1094 asm volatile (__ex(ASM_VMX_INVEPT)
1095 /* CF==1 or ZF==1 --> rc = -1 */
1096 "; ja 1f ; ud2 ; 1:\n"
1097 : : "a" (&operand), "c" (ext) : "cc", "memory");
1098 }
1099
1100 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1101 {
1102 int i;
1103
1104 i = __find_msr_index(vmx, msr);
1105 if (i >= 0)
1106 return &vmx->guest_msrs[i];
1107 return NULL;
1108 }
1109
1110 static void vmcs_clear(struct vmcs *vmcs)
1111 {
1112 u64 phys_addr = __pa(vmcs);
1113 u8 error;
1114
1115 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1116 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1117 : "cc", "memory");
1118 if (error)
1119 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120 vmcs, phys_addr);
1121 }
1122
1123 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124 {
1125 vmcs_clear(loaded_vmcs->vmcs);
1126 loaded_vmcs->cpu = -1;
1127 loaded_vmcs->launched = 0;
1128 }
1129
1130 static void vmcs_load(struct vmcs *vmcs)
1131 {
1132 u64 phys_addr = __pa(vmcs);
1133 u8 error;
1134
1135 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1136 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1137 : "cc", "memory");
1138 if (error)
1139 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1140 vmcs, phys_addr);
1141 }
1142
1143 #ifdef CONFIG_KEXEC
1144 /*
1145 * This bitmap is used to indicate whether the vmclear
1146 * operation is enabled on all cpus. All disabled by
1147 * default.
1148 */
1149 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151 static inline void crash_enable_local_vmclear(int cpu)
1152 {
1153 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154 }
1155
1156 static inline void crash_disable_local_vmclear(int cpu)
1157 {
1158 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159 }
1160
1161 static inline int crash_local_vmclear_enabled(int cpu)
1162 {
1163 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164 }
1165
1166 static void crash_vmclear_local_loaded_vmcss(void)
1167 {
1168 int cpu = raw_smp_processor_id();
1169 struct loaded_vmcs *v;
1170
1171 if (!crash_local_vmclear_enabled(cpu))
1172 return;
1173
1174 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175 loaded_vmcss_on_cpu_link)
1176 vmcs_clear(v->vmcs);
1177 }
1178 #else
1179 static inline void crash_enable_local_vmclear(int cpu) { }
1180 static inline void crash_disable_local_vmclear(int cpu) { }
1181 #endif /* CONFIG_KEXEC */
1182
1183 static void __loaded_vmcs_clear(void *arg)
1184 {
1185 struct loaded_vmcs *loaded_vmcs = arg;
1186 int cpu = raw_smp_processor_id();
1187
1188 if (loaded_vmcs->cpu != cpu)
1189 return; /* vcpu migration can race with cpu offline */
1190 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1191 per_cpu(current_vmcs, cpu) = NULL;
1192 crash_disable_local_vmclear(cpu);
1193 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1194
1195 /*
1196 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197 * is before setting loaded_vmcs->vcpu to -1 which is done in
1198 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199 * then adds the vmcs into percpu list before it is deleted.
1200 */
1201 smp_wmb();
1202
1203 loaded_vmcs_init(loaded_vmcs);
1204 crash_enable_local_vmclear(cpu);
1205 }
1206
1207 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1208 {
1209 int cpu = loaded_vmcs->cpu;
1210
1211 if (cpu != -1)
1212 smp_call_function_single(cpu,
1213 __loaded_vmcs_clear, loaded_vmcs, 1);
1214 }
1215
1216 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1217 {
1218 if (vmx->vpid == 0)
1219 return;
1220
1221 if (cpu_has_vmx_invvpid_single())
1222 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1223 }
1224
1225 static inline void vpid_sync_vcpu_global(void)
1226 {
1227 if (cpu_has_vmx_invvpid_global())
1228 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229 }
1230
1231 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232 {
1233 if (cpu_has_vmx_invvpid_single())
1234 vpid_sync_vcpu_single(vmx);
1235 else
1236 vpid_sync_vcpu_global();
1237 }
1238
1239 static inline void ept_sync_global(void)
1240 {
1241 if (cpu_has_vmx_invept_global())
1242 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243 }
1244
1245 static inline void ept_sync_context(u64 eptp)
1246 {
1247 if (enable_ept) {
1248 if (cpu_has_vmx_invept_context())
1249 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250 else
1251 ept_sync_global();
1252 }
1253 }
1254
1255 static __always_inline unsigned long vmcs_readl(unsigned long field)
1256 {
1257 unsigned long value;
1258
1259 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260 : "=a"(value) : "d"(field) : "cc");
1261 return value;
1262 }
1263
1264 static __always_inline u16 vmcs_read16(unsigned long field)
1265 {
1266 return vmcs_readl(field);
1267 }
1268
1269 static __always_inline u32 vmcs_read32(unsigned long field)
1270 {
1271 return vmcs_readl(field);
1272 }
1273
1274 static __always_inline u64 vmcs_read64(unsigned long field)
1275 {
1276 #ifdef CONFIG_X86_64
1277 return vmcs_readl(field);
1278 #else
1279 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280 #endif
1281 }
1282
1283 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284 {
1285 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287 dump_stack();
1288 }
1289
1290 static void vmcs_writel(unsigned long field, unsigned long value)
1291 {
1292 u8 error;
1293
1294 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1295 : "=q"(error) : "a"(value), "d"(field) : "cc");
1296 if (unlikely(error))
1297 vmwrite_error(field, value);
1298 }
1299
1300 static void vmcs_write16(unsigned long field, u16 value)
1301 {
1302 vmcs_writel(field, value);
1303 }
1304
1305 static void vmcs_write32(unsigned long field, u32 value)
1306 {
1307 vmcs_writel(field, value);
1308 }
1309
1310 static void vmcs_write64(unsigned long field, u64 value)
1311 {
1312 vmcs_writel(field, value);
1313 #ifndef CONFIG_X86_64
1314 asm volatile ("");
1315 vmcs_writel(field+1, value >> 32);
1316 #endif
1317 }
1318
1319 static void vmcs_clear_bits(unsigned long field, u32 mask)
1320 {
1321 vmcs_writel(field, vmcs_readl(field) & ~mask);
1322 }
1323
1324 static void vmcs_set_bits(unsigned long field, u32 mask)
1325 {
1326 vmcs_writel(field, vmcs_readl(field) | mask);
1327 }
1328
1329 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330 {
1331 vmx->segment_cache.bitmask = 0;
1332 }
1333
1334 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335 unsigned field)
1336 {
1337 bool ret;
1338 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342 vmx->segment_cache.bitmask = 0;
1343 }
1344 ret = vmx->segment_cache.bitmask & mask;
1345 vmx->segment_cache.bitmask |= mask;
1346 return ret;
1347 }
1348
1349 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350 {
1351 u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355 return *p;
1356 }
1357
1358 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359 {
1360 ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364 return *p;
1365 }
1366
1367 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368 {
1369 u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373 return *p;
1374 }
1375
1376 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377 {
1378 u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382 return *p;
1383 }
1384
1385 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386 {
1387 u32 eb;
1388
1389 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391 if ((vcpu->guest_debug &
1392 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394 eb |= 1u << BP_VECTOR;
1395 if (to_vmx(vcpu)->rmode.vm86_active)
1396 eb = ~0;
1397 if (enable_ept)
1398 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1399 if (vcpu->fpu_active)
1400 eb &= ~(1u << NM_VECTOR);
1401
1402 /* When we are running a nested L2 guest and L1 specified for it a
1403 * certain exception bitmap, we must trap the same exceptions and pass
1404 * them to L1. When running L2, we will only handle the exceptions
1405 * specified above if L1 did not want them.
1406 */
1407 if (is_guest_mode(vcpu))
1408 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
1410 vmcs_write32(EXCEPTION_BITMAP, eb);
1411 }
1412
1413 static void clear_atomic_switch_msr_special(unsigned long entry,
1414 unsigned long exit)
1415 {
1416 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418 }
1419
1420 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421 {
1422 unsigned i;
1423 struct msr_autoload *m = &vmx->msr_autoload;
1424
1425 switch (msr) {
1426 case MSR_EFER:
1427 if (cpu_has_load_ia32_efer) {
1428 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429 VM_EXIT_LOAD_IA32_EFER);
1430 return;
1431 }
1432 break;
1433 case MSR_CORE_PERF_GLOBAL_CTRL:
1434 if (cpu_has_load_perf_global_ctrl) {
1435 clear_atomic_switch_msr_special(
1436 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438 return;
1439 }
1440 break;
1441 }
1442
1443 for (i = 0; i < m->nr; ++i)
1444 if (m->guest[i].index == msr)
1445 break;
1446
1447 if (i == m->nr)
1448 return;
1449 --m->nr;
1450 m->guest[i] = m->guest[m->nr];
1451 m->host[i] = m->host[m->nr];
1452 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454 }
1455
1456 static void add_atomic_switch_msr_special(unsigned long entry,
1457 unsigned long exit, unsigned long guest_val_vmcs,
1458 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459 {
1460 vmcs_write64(guest_val_vmcs, guest_val);
1461 vmcs_write64(host_val_vmcs, host_val);
1462 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464 }
1465
1466 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467 u64 guest_val, u64 host_val)
1468 {
1469 unsigned i;
1470 struct msr_autoload *m = &vmx->msr_autoload;
1471
1472 switch (msr) {
1473 case MSR_EFER:
1474 if (cpu_has_load_ia32_efer) {
1475 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476 VM_EXIT_LOAD_IA32_EFER,
1477 GUEST_IA32_EFER,
1478 HOST_IA32_EFER,
1479 guest_val, host_val);
1480 return;
1481 }
1482 break;
1483 case MSR_CORE_PERF_GLOBAL_CTRL:
1484 if (cpu_has_load_perf_global_ctrl) {
1485 add_atomic_switch_msr_special(
1486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488 GUEST_IA32_PERF_GLOBAL_CTRL,
1489 HOST_IA32_PERF_GLOBAL_CTRL,
1490 guest_val, host_val);
1491 return;
1492 }
1493 break;
1494 }
1495
1496 for (i = 0; i < m->nr; ++i)
1497 if (m->guest[i].index == msr)
1498 break;
1499
1500 if (i == NR_AUTOLOAD_MSRS) {
1501 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502 "Can't add msr %x\n", msr);
1503 return;
1504 } else if (i == m->nr) {
1505 ++m->nr;
1506 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508 }
1509
1510 m->guest[i].index = msr;
1511 m->guest[i].value = guest_val;
1512 m->host[i].index = msr;
1513 m->host[i].value = host_val;
1514 }
1515
1516 static void reload_tss(void)
1517 {
1518 /*
1519 * VT restores TR but not its size. Useless.
1520 */
1521 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1522 struct desc_struct *descs;
1523
1524 descs = (void *)gdt->address;
1525 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526 load_TR_desc();
1527 }
1528
1529 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1530 {
1531 u64 guest_efer;
1532 u64 ignore_bits;
1533
1534 guest_efer = vmx->vcpu.arch.efer;
1535
1536 /*
1537 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1538 * outside long mode
1539 */
1540 ignore_bits = EFER_NX | EFER_SCE;
1541 #ifdef CONFIG_X86_64
1542 ignore_bits |= EFER_LMA | EFER_LME;
1543 /* SCE is meaningful only in long mode on Intel */
1544 if (guest_efer & EFER_LMA)
1545 ignore_bits &= ~(u64)EFER_SCE;
1546 #endif
1547 guest_efer &= ~ignore_bits;
1548 guest_efer |= host_efer & ignore_bits;
1549 vmx->guest_msrs[efer_offset].data = guest_efer;
1550 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1551
1552 clear_atomic_switch_msr(vmx, MSR_EFER);
1553 /* On ept, can't emulate nx, and must switch nx atomically */
1554 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555 guest_efer = vmx->vcpu.arch.efer;
1556 if (!(guest_efer & EFER_LMA))
1557 guest_efer &= ~EFER_LME;
1558 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559 return false;
1560 }
1561
1562 return true;
1563 }
1564
1565 static unsigned long segment_base(u16 selector)
1566 {
1567 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1568 struct desc_struct *d;
1569 unsigned long table_base;
1570 unsigned long v;
1571
1572 if (!(selector & ~3))
1573 return 0;
1574
1575 table_base = gdt->address;
1576
1577 if (selector & 4) { /* from ldt */
1578 u16 ldt_selector = kvm_read_ldt();
1579
1580 if (!(ldt_selector & ~3))
1581 return 0;
1582
1583 table_base = segment_base(ldt_selector);
1584 }
1585 d = (struct desc_struct *)(table_base + (selector & ~7));
1586 v = get_desc_base(d);
1587 #ifdef CONFIG_X86_64
1588 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590 #endif
1591 return v;
1592 }
1593
1594 static inline unsigned long kvm_read_tr_base(void)
1595 {
1596 u16 tr;
1597 asm("str %0" : "=g"(tr));
1598 return segment_base(tr);
1599 }
1600
1601 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1602 {
1603 struct vcpu_vmx *vmx = to_vmx(vcpu);
1604 int i;
1605
1606 if (vmx->host_state.loaded)
1607 return;
1608
1609 vmx->host_state.loaded = 1;
1610 /*
1611 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1612 * allow segment selectors with cpl > 0 or ti == 1.
1613 */
1614 vmx->host_state.ldt_sel = kvm_read_ldt();
1615 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1616 savesegment(fs, vmx->host_state.fs_sel);
1617 if (!(vmx->host_state.fs_sel & 7)) {
1618 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1619 vmx->host_state.fs_reload_needed = 0;
1620 } else {
1621 vmcs_write16(HOST_FS_SELECTOR, 0);
1622 vmx->host_state.fs_reload_needed = 1;
1623 }
1624 savesegment(gs, vmx->host_state.gs_sel);
1625 if (!(vmx->host_state.gs_sel & 7))
1626 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1627 else {
1628 vmcs_write16(HOST_GS_SELECTOR, 0);
1629 vmx->host_state.gs_ldt_reload_needed = 1;
1630 }
1631
1632 #ifdef CONFIG_X86_64
1633 savesegment(ds, vmx->host_state.ds_sel);
1634 savesegment(es, vmx->host_state.es_sel);
1635 #endif
1636
1637 #ifdef CONFIG_X86_64
1638 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640 #else
1641 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1643 #endif
1644
1645 #ifdef CONFIG_X86_64
1646 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647 if (is_long_mode(&vmx->vcpu))
1648 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1649 #endif
1650 for (i = 0; i < vmx->save_nmsrs; ++i)
1651 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1652 vmx->guest_msrs[i].data,
1653 vmx->guest_msrs[i].mask);
1654 }
1655
1656 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1657 {
1658 if (!vmx->host_state.loaded)
1659 return;
1660
1661 ++vmx->vcpu.stat.host_state_reload;
1662 vmx->host_state.loaded = 0;
1663 #ifdef CONFIG_X86_64
1664 if (is_long_mode(&vmx->vcpu))
1665 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666 #endif
1667 if (vmx->host_state.gs_ldt_reload_needed) {
1668 kvm_load_ldt(vmx->host_state.ldt_sel);
1669 #ifdef CONFIG_X86_64
1670 load_gs_index(vmx->host_state.gs_sel);
1671 #else
1672 loadsegment(gs, vmx->host_state.gs_sel);
1673 #endif
1674 }
1675 if (vmx->host_state.fs_reload_needed)
1676 loadsegment(fs, vmx->host_state.fs_sel);
1677 #ifdef CONFIG_X86_64
1678 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679 loadsegment(ds, vmx->host_state.ds_sel);
1680 loadsegment(es, vmx->host_state.es_sel);
1681 }
1682 #endif
1683 reload_tss();
1684 #ifdef CONFIG_X86_64
1685 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1686 #endif
1687 /*
1688 * If the FPU is not active (through the host task or
1689 * the guest vcpu), then restore the cr0.TS bit.
1690 */
1691 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692 stts();
1693 load_gdt(&__get_cpu_var(host_gdt));
1694 }
1695
1696 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697 {
1698 preempt_disable();
1699 __vmx_load_host_state(vmx);
1700 preempt_enable();
1701 }
1702
1703 /*
1704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705 * vcpu mutex is already taken.
1706 */
1707 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1708 {
1709 struct vcpu_vmx *vmx = to_vmx(vcpu);
1710 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1711
1712 if (!vmm_exclusive)
1713 kvm_cpu_vmxon(phys_addr);
1714 else if (vmx->loaded_vmcs->cpu != cpu)
1715 loaded_vmcs_clear(vmx->loaded_vmcs);
1716
1717 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719 vmcs_load(vmx->loaded_vmcs->vmcs);
1720 }
1721
1722 if (vmx->loaded_vmcs->cpu != cpu) {
1723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1724 unsigned long sysenter_esp;
1725
1726 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1727 local_irq_disable();
1728 crash_disable_local_vmclear(cpu);
1729
1730 /*
1731 * Read loaded_vmcs->cpu should be before fetching
1732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733 * See the comments in __loaded_vmcs_clear().
1734 */
1735 smp_rmb();
1736
1737 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738 &per_cpu(loaded_vmcss_on_cpu, cpu));
1739 crash_enable_local_vmclear(cpu);
1740 local_irq_enable();
1741
1742 /*
1743 * Linux uses per-cpu TSS and GDT, so set these when switching
1744 * processors.
1745 */
1746 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1747 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1748
1749 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1751 vmx->loaded_vmcs->cpu = cpu;
1752 }
1753 }
1754
1755 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756 {
1757 __vmx_load_host_state(to_vmx(vcpu));
1758 if (!vmm_exclusive) {
1759 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760 vcpu->cpu = -1;
1761 kvm_cpu_vmxoff();
1762 }
1763 }
1764
1765 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766 {
1767 ulong cr0;
1768
1769 if (vcpu->fpu_active)
1770 return;
1771 vcpu->fpu_active = 1;
1772 cr0 = vmcs_readl(GUEST_CR0);
1773 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775 vmcs_writel(GUEST_CR0, cr0);
1776 update_exception_bitmap(vcpu);
1777 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1778 if (is_guest_mode(vcpu))
1779 vcpu->arch.cr0_guest_owned_bits &=
1780 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1781 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1782 }
1783
1784 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
1786 /*
1787 * Return the cr0 value that a nested guest would read. This is a combination
1788 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789 * its hypervisor (cr0_read_shadow).
1790 */
1791 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792 {
1793 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795 }
1796 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797 {
1798 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800 }
1801
1802 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803 {
1804 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805 * set this *before* calling this function.
1806 */
1807 vmx_decache_cr0_guest_bits(vcpu);
1808 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1809 update_exception_bitmap(vcpu);
1810 vcpu->arch.cr0_guest_owned_bits = 0;
1811 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1812 if (is_guest_mode(vcpu)) {
1813 /*
1814 * L1's specified read shadow might not contain the TS bit,
1815 * so now that we turned on shadowing of this bit, we need to
1816 * set this bit of the shadow. Like in nested_vmx_run we need
1817 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818 * up-to-date here because we just decached cr0.TS (and we'll
1819 * only update vmcs12->guest_cr0 on nested exit).
1820 */
1821 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823 (vcpu->arch.cr0 & X86_CR0_TS);
1824 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825 } else
1826 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1827 }
1828
1829 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830 {
1831 unsigned long rflags, save_rflags;
1832
1833 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835 rflags = vmcs_readl(GUEST_RFLAGS);
1836 if (to_vmx(vcpu)->rmode.vm86_active) {
1837 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840 }
1841 to_vmx(vcpu)->rflags = rflags;
1842 }
1843 return to_vmx(vcpu)->rflags;
1844 }
1845
1846 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847 {
1848 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849 to_vmx(vcpu)->rflags = rflags;
1850 if (to_vmx(vcpu)->rmode.vm86_active) {
1851 to_vmx(vcpu)->rmode.save_rflags = rflags;
1852 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1853 }
1854 vmcs_writel(GUEST_RFLAGS, rflags);
1855 }
1856
1857 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858 {
1859 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860 int ret = 0;
1861
1862 if (interruptibility & GUEST_INTR_STATE_STI)
1863 ret |= KVM_X86_SHADOW_INT_STI;
1864 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1865 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1866
1867 return ret & mask;
1868 }
1869
1870 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871 {
1872 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873 u32 interruptibility = interruptibility_old;
1874
1875 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
1877 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1878 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1879 else if (mask & KVM_X86_SHADOW_INT_STI)
1880 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882 if ((interruptibility != interruptibility_old))
1883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884 }
1885
1886 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887 {
1888 unsigned long rip;
1889
1890 rip = kvm_rip_read(vcpu);
1891 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1892 kvm_rip_write(vcpu, rip);
1893
1894 /* skipping an emulated instruction also counts */
1895 vmx_set_interrupt_shadow(vcpu, 0);
1896 }
1897
1898 /*
1899 * KVM wants to inject page-faults which it got to the guest. This function
1900 * checks whether in a nested guest, we need to inject them to L1 or L2.
1901 * This function assumes it is called with the exit reason in vmcs02 being
1902 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1903 * is running).
1904 */
1905 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1906 {
1907 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908
1909 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1910 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1911 return 0;
1912
1913 nested_vmx_vmexit(vcpu);
1914 return 1;
1915 }
1916
1917 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1918 bool has_error_code, u32 error_code,
1919 bool reinject)
1920 {
1921 struct vcpu_vmx *vmx = to_vmx(vcpu);
1922 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1923
1924 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1925 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
1926 return;
1927
1928 if (has_error_code) {
1929 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1930 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1931 }
1932
1933 if (vmx->rmode.vm86_active) {
1934 int inc_eip = 0;
1935 if (kvm_exception_is_soft(nr))
1936 inc_eip = vcpu->arch.event_exit_inst_len;
1937 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1938 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1939 return;
1940 }
1941
1942 if (kvm_exception_is_soft(nr)) {
1943 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1944 vmx->vcpu.arch.event_exit_inst_len);
1945 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1946 } else
1947 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1948
1949 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1950 }
1951
1952 static bool vmx_rdtscp_supported(void)
1953 {
1954 return cpu_has_vmx_rdtscp();
1955 }
1956
1957 static bool vmx_invpcid_supported(void)
1958 {
1959 return cpu_has_vmx_invpcid() && enable_ept;
1960 }
1961
1962 /*
1963 * Swap MSR entry in host/guest MSR entry array.
1964 */
1965 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1966 {
1967 struct shared_msr_entry tmp;
1968
1969 tmp = vmx->guest_msrs[to];
1970 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1971 vmx->guest_msrs[from] = tmp;
1972 }
1973
1974 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1975 {
1976 unsigned long *msr_bitmap;
1977
1978 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1979 if (is_long_mode(vcpu))
1980 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1981 else
1982 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1983 } else {
1984 if (is_long_mode(vcpu))
1985 msr_bitmap = vmx_msr_bitmap_longmode;
1986 else
1987 msr_bitmap = vmx_msr_bitmap_legacy;
1988 }
1989
1990 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1991 }
1992
1993 /*
1994 * Set up the vmcs to automatically save and restore system
1995 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1996 * mode, as fiddling with msrs is very expensive.
1997 */
1998 static void setup_msrs(struct vcpu_vmx *vmx)
1999 {
2000 int save_nmsrs, index;
2001
2002 save_nmsrs = 0;
2003 #ifdef CONFIG_X86_64
2004 if (is_long_mode(&vmx->vcpu)) {
2005 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2006 if (index >= 0)
2007 move_msr_up(vmx, index, save_nmsrs++);
2008 index = __find_msr_index(vmx, MSR_LSTAR);
2009 if (index >= 0)
2010 move_msr_up(vmx, index, save_nmsrs++);
2011 index = __find_msr_index(vmx, MSR_CSTAR);
2012 if (index >= 0)
2013 move_msr_up(vmx, index, save_nmsrs++);
2014 index = __find_msr_index(vmx, MSR_TSC_AUX);
2015 if (index >= 0 && vmx->rdtscp_enabled)
2016 move_msr_up(vmx, index, save_nmsrs++);
2017 /*
2018 * MSR_STAR is only needed on long mode guests, and only
2019 * if efer.sce is enabled.
2020 */
2021 index = __find_msr_index(vmx, MSR_STAR);
2022 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2023 move_msr_up(vmx, index, save_nmsrs++);
2024 }
2025 #endif
2026 index = __find_msr_index(vmx, MSR_EFER);
2027 if (index >= 0 && update_transition_efer(vmx, index))
2028 move_msr_up(vmx, index, save_nmsrs++);
2029
2030 vmx->save_nmsrs = save_nmsrs;
2031
2032 if (cpu_has_vmx_msr_bitmap())
2033 vmx_set_msr_bitmap(&vmx->vcpu);
2034 }
2035
2036 /*
2037 * reads and returns guest's timestamp counter "register"
2038 * guest_tsc = host_tsc + tsc_offset -- 21.3
2039 */
2040 static u64 guest_read_tsc(void)
2041 {
2042 u64 host_tsc, tsc_offset;
2043
2044 rdtscll(host_tsc);
2045 tsc_offset = vmcs_read64(TSC_OFFSET);
2046 return host_tsc + tsc_offset;
2047 }
2048
2049 /*
2050 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2051 * counter, even if a nested guest (L2) is currently running.
2052 */
2053 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2054 {
2055 u64 tsc_offset;
2056
2057 tsc_offset = is_guest_mode(vcpu) ?
2058 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2059 vmcs_read64(TSC_OFFSET);
2060 return host_tsc + tsc_offset;
2061 }
2062
2063 /*
2064 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2065 * software catchup for faster rates on slower CPUs.
2066 */
2067 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2068 {
2069 if (!scale)
2070 return;
2071
2072 if (user_tsc_khz > tsc_khz) {
2073 vcpu->arch.tsc_catchup = 1;
2074 vcpu->arch.tsc_always_catchup = 1;
2075 } else
2076 WARN(1, "user requested TSC rate below hardware speed\n");
2077 }
2078
2079 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2080 {
2081 return vmcs_read64(TSC_OFFSET);
2082 }
2083
2084 /*
2085 * writes 'offset' into guest's timestamp counter offset register
2086 */
2087 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2088 {
2089 if (is_guest_mode(vcpu)) {
2090 /*
2091 * We're here if L1 chose not to trap WRMSR to TSC. According
2092 * to the spec, this should set L1's TSC; The offset that L1
2093 * set for L2 remains unchanged, and still needs to be added
2094 * to the newly set TSC to get L2's TSC.
2095 */
2096 struct vmcs12 *vmcs12;
2097 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2098 /* recalculate vmcs02.TSC_OFFSET: */
2099 vmcs12 = get_vmcs12(vcpu);
2100 vmcs_write64(TSC_OFFSET, offset +
2101 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2102 vmcs12->tsc_offset : 0));
2103 } else {
2104 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2105 vmcs_read64(TSC_OFFSET), offset);
2106 vmcs_write64(TSC_OFFSET, offset);
2107 }
2108 }
2109
2110 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2111 {
2112 u64 offset = vmcs_read64(TSC_OFFSET);
2113
2114 vmcs_write64(TSC_OFFSET, offset + adjustment);
2115 if (is_guest_mode(vcpu)) {
2116 /* Even when running L2, the adjustment needs to apply to L1 */
2117 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2118 } else
2119 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2120 offset + adjustment);
2121 }
2122
2123 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2124 {
2125 return target_tsc - native_read_tsc();
2126 }
2127
2128 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2129 {
2130 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2131 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2132 }
2133
2134 /*
2135 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2136 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2137 * all guests if the "nested" module option is off, and can also be disabled
2138 * for a single guest by disabling its VMX cpuid bit.
2139 */
2140 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2141 {
2142 return nested && guest_cpuid_has_vmx(vcpu);
2143 }
2144
2145 /*
2146 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2147 * returned for the various VMX controls MSRs when nested VMX is enabled.
2148 * The same values should also be used to verify that vmcs12 control fields are
2149 * valid during nested entry from L1 to L2.
2150 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2151 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2152 * bit in the high half is on if the corresponding bit in the control field
2153 * may be on. See also vmx_control_verify().
2154 * TODO: allow these variables to be modified (downgraded) by module options
2155 * or other means.
2156 */
2157 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2158 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2159 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2160 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2161 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2162 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2163 static u32 nested_vmx_ept_caps;
2164 static __init void nested_vmx_setup_ctls_msrs(void)
2165 {
2166 /*
2167 * Note that as a general rule, the high half of the MSRs (bits in
2168 * the control fields which may be 1) should be initialized by the
2169 * intersection of the underlying hardware's MSR (i.e., features which
2170 * can be supported) and the list of features we want to expose -
2171 * because they are known to be properly supported in our code.
2172 * Also, usually, the low half of the MSRs (bits which must be 1) can
2173 * be set to 0, meaning that L1 may turn off any of these bits. The
2174 * reason is that if one of these bits is necessary, it will appear
2175 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2176 * fields of vmcs01 and vmcs02, will turn these bits off - and
2177 * nested_vmx_exit_handled() will not pass related exits to L1.
2178 * These rules have exceptions below.
2179 */
2180
2181 /* pin-based controls */
2182 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2183 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2184 /*
2185 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2186 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2187 */
2188 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2189 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2190 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2191 PIN_BASED_VMX_PREEMPTION_TIMER;
2192 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2193
2194 /*
2195 * Exit controls
2196 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2197 * 17 must be 1.
2198 */
2199 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2200 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2201 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2202 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2203 nested_vmx_exit_ctls_high &=
2204 #ifdef CONFIG_X86_64
2205 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2206 #endif
2207 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2208 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2209 VM_EXIT_LOAD_IA32_EFER);
2210
2211 /* entry controls */
2212 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2213 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2214 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2215 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2216 nested_vmx_entry_ctls_high &=
2217 #ifdef CONFIG_X86_64
2218 VM_ENTRY_IA32E_MODE |
2219 #endif
2220 VM_ENTRY_LOAD_IA32_PAT;
2221 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2222 VM_ENTRY_LOAD_IA32_EFER);
2223
2224 /* cpu-based controls */
2225 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2226 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2227 nested_vmx_procbased_ctls_low = 0;
2228 nested_vmx_procbased_ctls_high &=
2229 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2230 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2231 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2232 CPU_BASED_CR3_STORE_EXITING |
2233 #ifdef CONFIG_X86_64
2234 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2235 #endif
2236 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2237 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2238 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2239 CPU_BASED_PAUSE_EXITING |
2240 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2241 /*
2242 * We can allow some features even when not supported by the
2243 * hardware. For example, L1 can specify an MSR bitmap - and we
2244 * can use it to avoid exits to L1 - even when L0 runs L2
2245 * without MSR bitmaps.
2246 */
2247 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2248
2249 /* secondary cpu-based controls */
2250 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2251 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2252 nested_vmx_secondary_ctls_low = 0;
2253 nested_vmx_secondary_ctls_high &=
2254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2255 SECONDARY_EXEC_WBINVD_EXITING;
2256
2257 if (enable_ept) {
2258 /* nested EPT: emulate EPT also to L1 */
2259 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2260 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2261 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2262 nested_vmx_ept_caps &= vmx_capability.ept;
2263 /*
2264 * Since invept is completely emulated we support both global
2265 * and context invalidation independent of what host cpu
2266 * supports
2267 */
2268 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2269 VMX_EPT_EXTENT_CONTEXT_BIT;
2270 } else
2271 nested_vmx_ept_caps = 0;
2272
2273 /* miscellaneous data */
2274 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2275 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2276 VMX_MISC_SAVE_EFER_LMA;
2277 nested_vmx_misc_high = 0;
2278 }
2279
2280 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2281 {
2282 /*
2283 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2284 */
2285 return ((control & high) | low) == control;
2286 }
2287
2288 static inline u64 vmx_control_msr(u32 low, u32 high)
2289 {
2290 return low | ((u64)high << 32);
2291 }
2292
2293 /*
2294 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2295 * also let it use VMX-specific MSRs.
2296 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2297 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2298 * like all other MSRs).
2299 */
2300 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2301 {
2302 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2303 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2304 /*
2305 * According to the spec, processors which do not support VMX
2306 * should throw a #GP(0) when VMX capability MSRs are read.
2307 */
2308 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2309 return 1;
2310 }
2311
2312 switch (msr_index) {
2313 case MSR_IA32_FEATURE_CONTROL:
2314 if (nested_vmx_allowed(vcpu)) {
2315 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2316 break;
2317 }
2318 return 0;
2319 case MSR_IA32_VMX_BASIC:
2320 /*
2321 * This MSR reports some information about VMX support. We
2322 * should return information about the VMX we emulate for the
2323 * guest, and the VMCS structure we give it - not about the
2324 * VMX support of the underlying hardware.
2325 */
2326 *pdata = VMCS12_REVISION |
2327 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2328 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2329 break;
2330 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2331 case MSR_IA32_VMX_PINBASED_CTLS:
2332 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2333 nested_vmx_pinbased_ctls_high);
2334 break;
2335 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2336 case MSR_IA32_VMX_PROCBASED_CTLS:
2337 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2338 nested_vmx_procbased_ctls_high);
2339 break;
2340 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2341 case MSR_IA32_VMX_EXIT_CTLS:
2342 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2343 nested_vmx_exit_ctls_high);
2344 break;
2345 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2346 case MSR_IA32_VMX_ENTRY_CTLS:
2347 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2348 nested_vmx_entry_ctls_high);
2349 break;
2350 case MSR_IA32_VMX_MISC:
2351 *pdata = vmx_control_msr(nested_vmx_misc_low,
2352 nested_vmx_misc_high);
2353 break;
2354 /*
2355 * These MSRs specify bits which the guest must keep fixed (on or off)
2356 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2357 * We picked the standard core2 setting.
2358 */
2359 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2360 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2361 case MSR_IA32_VMX_CR0_FIXED0:
2362 *pdata = VMXON_CR0_ALWAYSON;
2363 break;
2364 case MSR_IA32_VMX_CR0_FIXED1:
2365 *pdata = -1ULL;
2366 break;
2367 case MSR_IA32_VMX_CR4_FIXED0:
2368 *pdata = VMXON_CR4_ALWAYSON;
2369 break;
2370 case MSR_IA32_VMX_CR4_FIXED1:
2371 *pdata = -1ULL;
2372 break;
2373 case MSR_IA32_VMX_VMCS_ENUM:
2374 *pdata = 0x1f;
2375 break;
2376 case MSR_IA32_VMX_PROCBASED_CTLS2:
2377 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2378 nested_vmx_secondary_ctls_high);
2379 break;
2380 case MSR_IA32_VMX_EPT_VPID_CAP:
2381 /* Currently, no nested vpid support */
2382 *pdata = nested_vmx_ept_caps;
2383 break;
2384 default:
2385 return 0;
2386 }
2387
2388 return 1;
2389 }
2390
2391 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2392 {
2393 u32 msr_index = msr_info->index;
2394 u64 data = msr_info->data;
2395 bool host_initialized = msr_info->host_initiated;
2396
2397 if (!nested_vmx_allowed(vcpu))
2398 return 0;
2399
2400 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2401 if (!host_initialized &&
2402 to_vmx(vcpu)->nested.msr_ia32_feature_control
2403 & FEATURE_CONTROL_LOCKED)
2404 return 0;
2405 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
2406 return 1;
2407 }
2408
2409 /*
2410 * No need to treat VMX capability MSRs specially: If we don't handle
2411 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2412 */
2413 return 0;
2414 }
2415
2416 /*
2417 * Reads an msr value (of 'msr_index') into 'pdata'.
2418 * Returns 0 on success, non-0 otherwise.
2419 * Assumes vcpu_load() was already called.
2420 */
2421 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2422 {
2423 u64 data;
2424 struct shared_msr_entry *msr;
2425
2426 if (!pdata) {
2427 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2428 return -EINVAL;
2429 }
2430
2431 switch (msr_index) {
2432 #ifdef CONFIG_X86_64
2433 case MSR_FS_BASE:
2434 data = vmcs_readl(GUEST_FS_BASE);
2435 break;
2436 case MSR_GS_BASE:
2437 data = vmcs_readl(GUEST_GS_BASE);
2438 break;
2439 case MSR_KERNEL_GS_BASE:
2440 vmx_load_host_state(to_vmx(vcpu));
2441 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2442 break;
2443 #endif
2444 case MSR_EFER:
2445 return kvm_get_msr_common(vcpu, msr_index, pdata);
2446 case MSR_IA32_TSC:
2447 data = guest_read_tsc();
2448 break;
2449 case MSR_IA32_SYSENTER_CS:
2450 data = vmcs_read32(GUEST_SYSENTER_CS);
2451 break;
2452 case MSR_IA32_SYSENTER_EIP:
2453 data = vmcs_readl(GUEST_SYSENTER_EIP);
2454 break;
2455 case MSR_IA32_SYSENTER_ESP:
2456 data = vmcs_readl(GUEST_SYSENTER_ESP);
2457 break;
2458 case MSR_TSC_AUX:
2459 if (!to_vmx(vcpu)->rdtscp_enabled)
2460 return 1;
2461 /* Otherwise falls through */
2462 default:
2463 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2464 return 0;
2465 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2466 if (msr) {
2467 data = msr->data;
2468 break;
2469 }
2470 return kvm_get_msr_common(vcpu, msr_index, pdata);
2471 }
2472
2473 *pdata = data;
2474 return 0;
2475 }
2476
2477 /*
2478 * Writes msr value into into the appropriate "register".
2479 * Returns 0 on success, non-0 otherwise.
2480 * Assumes vcpu_load() was already called.
2481 */
2482 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2483 {
2484 struct vcpu_vmx *vmx = to_vmx(vcpu);
2485 struct shared_msr_entry *msr;
2486 int ret = 0;
2487 u32 msr_index = msr_info->index;
2488 u64 data = msr_info->data;
2489
2490 switch (msr_index) {
2491 case MSR_EFER:
2492 ret = kvm_set_msr_common(vcpu, msr_info);
2493 break;
2494 #ifdef CONFIG_X86_64
2495 case MSR_FS_BASE:
2496 vmx_segment_cache_clear(vmx);
2497 vmcs_writel(GUEST_FS_BASE, data);
2498 break;
2499 case MSR_GS_BASE:
2500 vmx_segment_cache_clear(vmx);
2501 vmcs_writel(GUEST_GS_BASE, data);
2502 break;
2503 case MSR_KERNEL_GS_BASE:
2504 vmx_load_host_state(vmx);
2505 vmx->msr_guest_kernel_gs_base = data;
2506 break;
2507 #endif
2508 case MSR_IA32_SYSENTER_CS:
2509 vmcs_write32(GUEST_SYSENTER_CS, data);
2510 break;
2511 case MSR_IA32_SYSENTER_EIP:
2512 vmcs_writel(GUEST_SYSENTER_EIP, data);
2513 break;
2514 case MSR_IA32_SYSENTER_ESP:
2515 vmcs_writel(GUEST_SYSENTER_ESP, data);
2516 break;
2517 case MSR_IA32_TSC:
2518 kvm_write_tsc(vcpu, msr_info);
2519 break;
2520 case MSR_IA32_CR_PAT:
2521 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2522 vmcs_write64(GUEST_IA32_PAT, data);
2523 vcpu->arch.pat = data;
2524 break;
2525 }
2526 ret = kvm_set_msr_common(vcpu, msr_info);
2527 break;
2528 case MSR_IA32_TSC_ADJUST:
2529 ret = kvm_set_msr_common(vcpu, msr_info);
2530 break;
2531 case MSR_TSC_AUX:
2532 if (!vmx->rdtscp_enabled)
2533 return 1;
2534 /* Check reserved bit, higher 32 bits should be zero */
2535 if ((data >> 32) != 0)
2536 return 1;
2537 /* Otherwise falls through */
2538 default:
2539 if (vmx_set_vmx_msr(vcpu, msr_info))
2540 break;
2541 msr = find_msr_entry(vmx, msr_index);
2542 if (msr) {
2543 msr->data = data;
2544 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2545 preempt_disable();
2546 kvm_set_shared_msr(msr->index, msr->data,
2547 msr->mask);
2548 preempt_enable();
2549 }
2550 break;
2551 }
2552 ret = kvm_set_msr_common(vcpu, msr_info);
2553 }
2554
2555 return ret;
2556 }
2557
2558 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2559 {
2560 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2561 switch (reg) {
2562 case VCPU_REGS_RSP:
2563 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2564 break;
2565 case VCPU_REGS_RIP:
2566 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2567 break;
2568 case VCPU_EXREG_PDPTR:
2569 if (enable_ept)
2570 ept_save_pdptrs(vcpu);
2571 break;
2572 default:
2573 break;
2574 }
2575 }
2576
2577 static __init int cpu_has_kvm_support(void)
2578 {
2579 return cpu_has_vmx();
2580 }
2581
2582 static __init int vmx_disabled_by_bios(void)
2583 {
2584 u64 msr;
2585
2586 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2587 if (msr & FEATURE_CONTROL_LOCKED) {
2588 /* launched w/ TXT and VMX disabled */
2589 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2590 && tboot_enabled())
2591 return 1;
2592 /* launched w/o TXT and VMX only enabled w/ TXT */
2593 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2594 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2595 && !tboot_enabled()) {
2596 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2597 "activate TXT before enabling KVM\n");
2598 return 1;
2599 }
2600 /* launched w/o TXT and VMX disabled */
2601 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2602 && !tboot_enabled())
2603 return 1;
2604 }
2605
2606 return 0;
2607 }
2608
2609 static void kvm_cpu_vmxon(u64 addr)
2610 {
2611 asm volatile (ASM_VMX_VMXON_RAX
2612 : : "a"(&addr), "m"(addr)
2613 : "memory", "cc");
2614 }
2615
2616 static int hardware_enable(void *garbage)
2617 {
2618 int cpu = raw_smp_processor_id();
2619 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2620 u64 old, test_bits;
2621
2622 if (read_cr4() & X86_CR4_VMXE)
2623 return -EBUSY;
2624
2625 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2626
2627 /*
2628 * Now we can enable the vmclear operation in kdump
2629 * since the loaded_vmcss_on_cpu list on this cpu
2630 * has been initialized.
2631 *
2632 * Though the cpu is not in VMX operation now, there
2633 * is no problem to enable the vmclear operation
2634 * for the loaded_vmcss_on_cpu list is empty!
2635 */
2636 crash_enable_local_vmclear(cpu);
2637
2638 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2639
2640 test_bits = FEATURE_CONTROL_LOCKED;
2641 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2642 if (tboot_enabled())
2643 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2644
2645 if ((old & test_bits) != test_bits) {
2646 /* enable and lock */
2647 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2648 }
2649 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2650
2651 if (vmm_exclusive) {
2652 kvm_cpu_vmxon(phys_addr);
2653 ept_sync_global();
2654 }
2655
2656 native_store_gdt(&__get_cpu_var(host_gdt));
2657
2658 return 0;
2659 }
2660
2661 static void vmclear_local_loaded_vmcss(void)
2662 {
2663 int cpu = raw_smp_processor_id();
2664 struct loaded_vmcs *v, *n;
2665
2666 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2667 loaded_vmcss_on_cpu_link)
2668 __loaded_vmcs_clear(v);
2669 }
2670
2671
2672 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2673 * tricks.
2674 */
2675 static void kvm_cpu_vmxoff(void)
2676 {
2677 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2678 }
2679
2680 static void hardware_disable(void *garbage)
2681 {
2682 if (vmm_exclusive) {
2683 vmclear_local_loaded_vmcss();
2684 kvm_cpu_vmxoff();
2685 }
2686 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2687 }
2688
2689 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2690 u32 msr, u32 *result)
2691 {
2692 u32 vmx_msr_low, vmx_msr_high;
2693 u32 ctl = ctl_min | ctl_opt;
2694
2695 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2696
2697 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2698 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2699
2700 /* Ensure minimum (required) set of control bits are supported. */
2701 if (ctl_min & ~ctl)
2702 return -EIO;
2703
2704 *result = ctl;
2705 return 0;
2706 }
2707
2708 static __init bool allow_1_setting(u32 msr, u32 ctl)
2709 {
2710 u32 vmx_msr_low, vmx_msr_high;
2711
2712 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2713 return vmx_msr_high & ctl;
2714 }
2715
2716 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2717 {
2718 u32 vmx_msr_low, vmx_msr_high;
2719 u32 min, opt, min2, opt2;
2720 u32 _pin_based_exec_control = 0;
2721 u32 _cpu_based_exec_control = 0;
2722 u32 _cpu_based_2nd_exec_control = 0;
2723 u32 _vmexit_control = 0;
2724 u32 _vmentry_control = 0;
2725
2726 min = CPU_BASED_HLT_EXITING |
2727 #ifdef CONFIG_X86_64
2728 CPU_BASED_CR8_LOAD_EXITING |
2729 CPU_BASED_CR8_STORE_EXITING |
2730 #endif
2731 CPU_BASED_CR3_LOAD_EXITING |
2732 CPU_BASED_CR3_STORE_EXITING |
2733 CPU_BASED_USE_IO_BITMAPS |
2734 CPU_BASED_MOV_DR_EXITING |
2735 CPU_BASED_USE_TSC_OFFSETING |
2736 CPU_BASED_MWAIT_EXITING |
2737 CPU_BASED_MONITOR_EXITING |
2738 CPU_BASED_INVLPG_EXITING |
2739 CPU_BASED_RDPMC_EXITING;
2740
2741 opt = CPU_BASED_TPR_SHADOW |
2742 CPU_BASED_USE_MSR_BITMAPS |
2743 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2744 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2745 &_cpu_based_exec_control) < 0)
2746 return -EIO;
2747 #ifdef CONFIG_X86_64
2748 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2749 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2750 ~CPU_BASED_CR8_STORE_EXITING;
2751 #endif
2752 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2753 min2 = 0;
2754 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2755 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2756 SECONDARY_EXEC_WBINVD_EXITING |
2757 SECONDARY_EXEC_ENABLE_VPID |
2758 SECONDARY_EXEC_ENABLE_EPT |
2759 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2760 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2761 SECONDARY_EXEC_RDTSCP |
2762 SECONDARY_EXEC_ENABLE_INVPCID |
2763 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2764 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2765 SECONDARY_EXEC_SHADOW_VMCS;
2766 if (adjust_vmx_controls(min2, opt2,
2767 MSR_IA32_VMX_PROCBASED_CTLS2,
2768 &_cpu_based_2nd_exec_control) < 0)
2769 return -EIO;
2770 }
2771 #ifndef CONFIG_X86_64
2772 if (!(_cpu_based_2nd_exec_control &
2773 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2774 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2775 #endif
2776
2777 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2778 _cpu_based_2nd_exec_control &= ~(
2779 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2780 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2781 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2782
2783 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2784 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2785 enabled */
2786 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2787 CPU_BASED_CR3_STORE_EXITING |
2788 CPU_BASED_INVLPG_EXITING);
2789 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2790 vmx_capability.ept, vmx_capability.vpid);
2791 }
2792
2793 min = 0;
2794 #ifdef CONFIG_X86_64
2795 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2796 #endif
2797 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2798 VM_EXIT_ACK_INTR_ON_EXIT;
2799 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2800 &_vmexit_control) < 0)
2801 return -EIO;
2802
2803 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2804 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2805 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2806 &_pin_based_exec_control) < 0)
2807 return -EIO;
2808
2809 if (!(_cpu_based_2nd_exec_control &
2810 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2811 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2812 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2813
2814 min = 0;
2815 opt = VM_ENTRY_LOAD_IA32_PAT;
2816 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2817 &_vmentry_control) < 0)
2818 return -EIO;
2819
2820 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2821
2822 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2823 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2824 return -EIO;
2825
2826 #ifdef CONFIG_X86_64
2827 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2828 if (vmx_msr_high & (1u<<16))
2829 return -EIO;
2830 #endif
2831
2832 /* Require Write-Back (WB) memory type for VMCS accesses. */
2833 if (((vmx_msr_high >> 18) & 15) != 6)
2834 return -EIO;
2835
2836 vmcs_conf->size = vmx_msr_high & 0x1fff;
2837 vmcs_conf->order = get_order(vmcs_config.size);
2838 vmcs_conf->revision_id = vmx_msr_low;
2839
2840 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2841 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2842 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2843 vmcs_conf->vmexit_ctrl = _vmexit_control;
2844 vmcs_conf->vmentry_ctrl = _vmentry_control;
2845
2846 cpu_has_load_ia32_efer =
2847 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2848 VM_ENTRY_LOAD_IA32_EFER)
2849 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2850 VM_EXIT_LOAD_IA32_EFER);
2851
2852 cpu_has_load_perf_global_ctrl =
2853 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2854 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2855 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2856 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2857
2858 /*
2859 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2860 * but due to arrata below it can't be used. Workaround is to use
2861 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2862 *
2863 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2864 *
2865 * AAK155 (model 26)
2866 * AAP115 (model 30)
2867 * AAT100 (model 37)
2868 * BC86,AAY89,BD102 (model 44)
2869 * BA97 (model 46)
2870 *
2871 */
2872 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2873 switch (boot_cpu_data.x86_model) {
2874 case 26:
2875 case 30:
2876 case 37:
2877 case 44:
2878 case 46:
2879 cpu_has_load_perf_global_ctrl = false;
2880 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2881 "does not work properly. Using workaround\n");
2882 break;
2883 default:
2884 break;
2885 }
2886 }
2887
2888 return 0;
2889 }
2890
2891 static struct vmcs *alloc_vmcs_cpu(int cpu)
2892 {
2893 int node = cpu_to_node(cpu);
2894 struct page *pages;
2895 struct vmcs *vmcs;
2896
2897 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2898 if (!pages)
2899 return NULL;
2900 vmcs = page_address(pages);
2901 memset(vmcs, 0, vmcs_config.size);
2902 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2903 return vmcs;
2904 }
2905
2906 static struct vmcs *alloc_vmcs(void)
2907 {
2908 return alloc_vmcs_cpu(raw_smp_processor_id());
2909 }
2910
2911 static void free_vmcs(struct vmcs *vmcs)
2912 {
2913 free_pages((unsigned long)vmcs, vmcs_config.order);
2914 }
2915
2916 /*
2917 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2918 */
2919 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2920 {
2921 if (!loaded_vmcs->vmcs)
2922 return;
2923 loaded_vmcs_clear(loaded_vmcs);
2924 free_vmcs(loaded_vmcs->vmcs);
2925 loaded_vmcs->vmcs = NULL;
2926 }
2927
2928 static void free_kvm_area(void)
2929 {
2930 int cpu;
2931
2932 for_each_possible_cpu(cpu) {
2933 free_vmcs(per_cpu(vmxarea, cpu));
2934 per_cpu(vmxarea, cpu) = NULL;
2935 }
2936 }
2937
2938 static __init int alloc_kvm_area(void)
2939 {
2940 int cpu;
2941
2942 for_each_possible_cpu(cpu) {
2943 struct vmcs *vmcs;
2944
2945 vmcs = alloc_vmcs_cpu(cpu);
2946 if (!vmcs) {
2947 free_kvm_area();
2948 return -ENOMEM;
2949 }
2950
2951 per_cpu(vmxarea, cpu) = vmcs;
2952 }
2953 return 0;
2954 }
2955
2956 static __init int hardware_setup(void)
2957 {
2958 if (setup_vmcs_config(&vmcs_config) < 0)
2959 return -EIO;
2960
2961 if (boot_cpu_has(X86_FEATURE_NX))
2962 kvm_enable_efer_bits(EFER_NX);
2963
2964 if (!cpu_has_vmx_vpid())
2965 enable_vpid = 0;
2966 if (!cpu_has_vmx_shadow_vmcs())
2967 enable_shadow_vmcs = 0;
2968
2969 if (!cpu_has_vmx_ept() ||
2970 !cpu_has_vmx_ept_4levels()) {
2971 enable_ept = 0;
2972 enable_unrestricted_guest = 0;
2973 enable_ept_ad_bits = 0;
2974 }
2975
2976 if (!cpu_has_vmx_ept_ad_bits())
2977 enable_ept_ad_bits = 0;
2978
2979 if (!cpu_has_vmx_unrestricted_guest())
2980 enable_unrestricted_guest = 0;
2981
2982 if (!cpu_has_vmx_flexpriority())
2983 flexpriority_enabled = 0;
2984
2985 if (!cpu_has_vmx_tpr_shadow())
2986 kvm_x86_ops->update_cr8_intercept = NULL;
2987
2988 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2989 kvm_disable_largepages();
2990
2991 if (!cpu_has_vmx_ple())
2992 ple_gap = 0;
2993
2994 if (!cpu_has_vmx_apicv())
2995 enable_apicv = 0;
2996
2997 if (enable_apicv)
2998 kvm_x86_ops->update_cr8_intercept = NULL;
2999 else {
3000 kvm_x86_ops->hwapic_irr_update = NULL;
3001 kvm_x86_ops->deliver_posted_interrupt = NULL;
3002 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3003 }
3004
3005 if (nested)
3006 nested_vmx_setup_ctls_msrs();
3007
3008 return alloc_kvm_area();
3009 }
3010
3011 static __exit void hardware_unsetup(void)
3012 {
3013 free_kvm_area();
3014 }
3015
3016 static bool emulation_required(struct kvm_vcpu *vcpu)
3017 {
3018 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3019 }
3020
3021 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3022 struct kvm_segment *save)
3023 {
3024 if (!emulate_invalid_guest_state) {
3025 /*
3026 * CS and SS RPL should be equal during guest entry according
3027 * to VMX spec, but in reality it is not always so. Since vcpu
3028 * is in the middle of the transition from real mode to
3029 * protected mode it is safe to assume that RPL 0 is a good
3030 * default value.
3031 */
3032 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3033 save->selector &= ~SELECTOR_RPL_MASK;
3034 save->dpl = save->selector & SELECTOR_RPL_MASK;
3035 save->s = 1;
3036 }
3037 vmx_set_segment(vcpu, save, seg);
3038 }
3039
3040 static void enter_pmode(struct kvm_vcpu *vcpu)
3041 {
3042 unsigned long flags;
3043 struct vcpu_vmx *vmx = to_vmx(vcpu);
3044
3045 /*
3046 * Update real mode segment cache. It may be not up-to-date if sement
3047 * register was written while vcpu was in a guest mode.
3048 */
3049 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3050 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3051 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3052 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3053 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3054 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3055
3056 vmx->rmode.vm86_active = 0;
3057
3058 vmx_segment_cache_clear(vmx);
3059
3060 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3061
3062 flags = vmcs_readl(GUEST_RFLAGS);
3063 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3064 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3065 vmcs_writel(GUEST_RFLAGS, flags);
3066
3067 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3068 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3069
3070 update_exception_bitmap(vcpu);
3071
3072 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3073 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3074 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3075 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3076 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3077 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3078
3079 /* CPL is always 0 when CPU enters protected mode */
3080 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3081 vmx->cpl = 0;
3082 }
3083
3084 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3085 {
3086 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3087 struct kvm_segment var = *save;
3088
3089 var.dpl = 0x3;
3090 if (seg == VCPU_SREG_CS)
3091 var.type = 0x3;
3092
3093 if (!emulate_invalid_guest_state) {
3094 var.selector = var.base >> 4;
3095 var.base = var.base & 0xffff0;
3096 var.limit = 0xffff;
3097 var.g = 0;
3098 var.db = 0;
3099 var.present = 1;
3100 var.s = 1;
3101 var.l = 0;
3102 var.unusable = 0;
3103 var.type = 0x3;
3104 var.avl = 0;
3105 if (save->base & 0xf)
3106 printk_once(KERN_WARNING "kvm: segment base is not "
3107 "paragraph aligned when entering "
3108 "protected mode (seg=%d)", seg);
3109 }
3110
3111 vmcs_write16(sf->selector, var.selector);
3112 vmcs_write32(sf->base, var.base);
3113 vmcs_write32(sf->limit, var.limit);
3114 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3115 }
3116
3117 static void enter_rmode(struct kvm_vcpu *vcpu)
3118 {
3119 unsigned long flags;
3120 struct vcpu_vmx *vmx = to_vmx(vcpu);
3121
3122 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3123 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3124 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3125 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3126 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3127 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3128 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3129
3130 vmx->rmode.vm86_active = 1;
3131
3132 /*
3133 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3134 * vcpu. Warn the user that an update is overdue.
3135 */
3136 if (!vcpu->kvm->arch.tss_addr)
3137 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3138 "called before entering vcpu\n");
3139
3140 vmx_segment_cache_clear(vmx);
3141
3142 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3143 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3144 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3145
3146 flags = vmcs_readl(GUEST_RFLAGS);
3147 vmx->rmode.save_rflags = flags;
3148
3149 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3150
3151 vmcs_writel(GUEST_RFLAGS, flags);
3152 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3153 update_exception_bitmap(vcpu);
3154
3155 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3156 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3157 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3158 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3159 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3160 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3161
3162 kvm_mmu_reset_context(vcpu);
3163 }
3164
3165 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3166 {
3167 struct vcpu_vmx *vmx = to_vmx(vcpu);
3168 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3169
3170 if (!msr)
3171 return;
3172
3173 /*
3174 * Force kernel_gs_base reloading before EFER changes, as control
3175 * of this msr depends on is_long_mode().
3176 */
3177 vmx_load_host_state(to_vmx(vcpu));
3178 vcpu->arch.efer = efer;
3179 if (efer & EFER_LMA) {
3180 vmcs_write32(VM_ENTRY_CONTROLS,
3181 vmcs_read32(VM_ENTRY_CONTROLS) |
3182 VM_ENTRY_IA32E_MODE);
3183 msr->data = efer;
3184 } else {
3185 vmcs_write32(VM_ENTRY_CONTROLS,
3186 vmcs_read32(VM_ENTRY_CONTROLS) &
3187 ~VM_ENTRY_IA32E_MODE);
3188
3189 msr->data = efer & ~EFER_LME;
3190 }
3191 setup_msrs(vmx);
3192 }
3193
3194 #ifdef CONFIG_X86_64
3195
3196 static void enter_lmode(struct kvm_vcpu *vcpu)
3197 {
3198 u32 guest_tr_ar;
3199
3200 vmx_segment_cache_clear(to_vmx(vcpu));
3201
3202 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3203 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3204 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3205 __func__);
3206 vmcs_write32(GUEST_TR_AR_BYTES,
3207 (guest_tr_ar & ~AR_TYPE_MASK)
3208 | AR_TYPE_BUSY_64_TSS);
3209 }
3210 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3211 }
3212
3213 static void exit_lmode(struct kvm_vcpu *vcpu)
3214 {
3215 vmcs_write32(VM_ENTRY_CONTROLS,
3216 vmcs_read32(VM_ENTRY_CONTROLS)
3217 & ~VM_ENTRY_IA32E_MODE);
3218 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3219 }
3220
3221 #endif
3222
3223 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3224 {
3225 vpid_sync_context(to_vmx(vcpu));
3226 if (enable_ept) {
3227 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3228 return;
3229 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3230 }
3231 }
3232
3233 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3234 {
3235 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3236
3237 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3238 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3239 }
3240
3241 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3242 {
3243 if (enable_ept && is_paging(vcpu))
3244 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3245 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3246 }
3247
3248 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3249 {
3250 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3251
3252 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3253 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3254 }
3255
3256 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3257 {
3258 if (!test_bit(VCPU_EXREG_PDPTR,
3259 (unsigned long *)&vcpu->arch.regs_dirty))
3260 return;
3261
3262 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3263 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3264 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3265 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3266 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3267 }
3268 }
3269
3270 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3271 {
3272 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3273 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3274 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3275 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3276 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3277 }
3278
3279 __set_bit(VCPU_EXREG_PDPTR,
3280 (unsigned long *)&vcpu->arch.regs_avail);
3281 __set_bit(VCPU_EXREG_PDPTR,
3282 (unsigned long *)&vcpu->arch.regs_dirty);
3283 }
3284
3285 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3286
3287 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3288 unsigned long cr0,
3289 struct kvm_vcpu *vcpu)
3290 {
3291 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3292 vmx_decache_cr3(vcpu);
3293 if (!(cr0 & X86_CR0_PG)) {
3294 /* From paging/starting to nonpaging */
3295 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3296 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3297 (CPU_BASED_CR3_LOAD_EXITING |
3298 CPU_BASED_CR3_STORE_EXITING));
3299 vcpu->arch.cr0 = cr0;
3300 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3301 } else if (!is_paging(vcpu)) {
3302 /* From nonpaging to paging */
3303 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3304 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3305 ~(CPU_BASED_CR3_LOAD_EXITING |
3306 CPU_BASED_CR3_STORE_EXITING));
3307 vcpu->arch.cr0 = cr0;
3308 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3309 }
3310
3311 if (!(cr0 & X86_CR0_WP))
3312 *hw_cr0 &= ~X86_CR0_WP;
3313 }
3314
3315 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3316 {
3317 struct vcpu_vmx *vmx = to_vmx(vcpu);
3318 unsigned long hw_cr0;
3319
3320 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3321 if (enable_unrestricted_guest)
3322 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3323 else {
3324 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3325
3326 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3327 enter_pmode(vcpu);
3328
3329 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3330 enter_rmode(vcpu);
3331 }
3332
3333 #ifdef CONFIG_X86_64
3334 if (vcpu->arch.efer & EFER_LME) {
3335 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3336 enter_lmode(vcpu);
3337 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3338 exit_lmode(vcpu);
3339 }
3340 #endif
3341
3342 if (enable_ept)
3343 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3344
3345 if (!vcpu->fpu_active)
3346 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3347
3348 vmcs_writel(CR0_READ_SHADOW, cr0);
3349 vmcs_writel(GUEST_CR0, hw_cr0);
3350 vcpu->arch.cr0 = cr0;
3351
3352 /* depends on vcpu->arch.cr0 to be set to a new value */
3353 vmx->emulation_required = emulation_required(vcpu);
3354 }
3355
3356 static u64 construct_eptp(unsigned long root_hpa)
3357 {
3358 u64 eptp;
3359
3360 /* TODO write the value reading from MSR */
3361 eptp = VMX_EPT_DEFAULT_MT |
3362 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3363 if (enable_ept_ad_bits)
3364 eptp |= VMX_EPT_AD_ENABLE_BIT;
3365 eptp |= (root_hpa & PAGE_MASK);
3366
3367 return eptp;
3368 }
3369
3370 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3371 {
3372 unsigned long guest_cr3;
3373 u64 eptp;
3374
3375 guest_cr3 = cr3;
3376 if (enable_ept) {
3377 eptp = construct_eptp(cr3);
3378 vmcs_write64(EPT_POINTER, eptp);
3379 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3380 vcpu->kvm->arch.ept_identity_map_addr;
3381 ept_load_pdptrs(vcpu);
3382 }
3383
3384 vmx_flush_tlb(vcpu);
3385 vmcs_writel(GUEST_CR3, guest_cr3);
3386 }
3387
3388 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3389 {
3390 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3391 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3392
3393 if (cr4 & X86_CR4_VMXE) {
3394 /*
3395 * To use VMXON (and later other VMX instructions), a guest
3396 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3397 * So basically the check on whether to allow nested VMX
3398 * is here.
3399 */
3400 if (!nested_vmx_allowed(vcpu))
3401 return 1;
3402 }
3403 if (to_vmx(vcpu)->nested.vmxon &&
3404 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3405 return 1;
3406
3407 vcpu->arch.cr4 = cr4;
3408 if (enable_ept) {
3409 if (!is_paging(vcpu)) {
3410 hw_cr4 &= ~X86_CR4_PAE;
3411 hw_cr4 |= X86_CR4_PSE;
3412 /*
3413 * SMEP is disabled if CPU is in non-paging mode in
3414 * hardware. However KVM always uses paging mode to
3415 * emulate guest non-paging mode with TDP.
3416 * To emulate this behavior, SMEP needs to be manually
3417 * disabled when guest switches to non-paging mode.
3418 */
3419 hw_cr4 &= ~X86_CR4_SMEP;
3420 } else if (!(cr4 & X86_CR4_PAE)) {
3421 hw_cr4 &= ~X86_CR4_PAE;
3422 }
3423 }
3424
3425 vmcs_writel(CR4_READ_SHADOW, cr4);
3426 vmcs_writel(GUEST_CR4, hw_cr4);
3427 return 0;
3428 }
3429
3430 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3431 struct kvm_segment *var, int seg)
3432 {
3433 struct vcpu_vmx *vmx = to_vmx(vcpu);
3434 u32 ar;
3435
3436 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3437 *var = vmx->rmode.segs[seg];
3438 if (seg == VCPU_SREG_TR
3439 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3440 return;
3441 var->base = vmx_read_guest_seg_base(vmx, seg);
3442 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3443 return;
3444 }
3445 var->base = vmx_read_guest_seg_base(vmx, seg);
3446 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3447 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3448 ar = vmx_read_guest_seg_ar(vmx, seg);
3449 var->unusable = (ar >> 16) & 1;
3450 var->type = ar & 15;
3451 var->s = (ar >> 4) & 1;
3452 var->dpl = (ar >> 5) & 3;
3453 /*
3454 * Some userspaces do not preserve unusable property. Since usable
3455 * segment has to be present according to VMX spec we can use present
3456 * property to amend userspace bug by making unusable segment always
3457 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3458 * segment as unusable.
3459 */
3460 var->present = !var->unusable;
3461 var->avl = (ar >> 12) & 1;
3462 var->l = (ar >> 13) & 1;
3463 var->db = (ar >> 14) & 1;
3464 var->g = (ar >> 15) & 1;
3465 }
3466
3467 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3468 {
3469 struct kvm_segment s;
3470
3471 if (to_vmx(vcpu)->rmode.vm86_active) {
3472 vmx_get_segment(vcpu, &s, seg);
3473 return s.base;
3474 }
3475 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3476 }
3477
3478 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3479 {
3480 struct vcpu_vmx *vmx = to_vmx(vcpu);
3481
3482 if (!is_protmode(vcpu))
3483 return 0;
3484
3485 if (!is_long_mode(vcpu)
3486 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3487 return 3;
3488
3489 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3490 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3491 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3492 }
3493
3494 return vmx->cpl;
3495 }
3496
3497
3498 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3499 {
3500 u32 ar;
3501
3502 if (var->unusable || !var->present)
3503 ar = 1 << 16;
3504 else {
3505 ar = var->type & 15;
3506 ar |= (var->s & 1) << 4;
3507 ar |= (var->dpl & 3) << 5;
3508 ar |= (var->present & 1) << 7;
3509 ar |= (var->avl & 1) << 12;
3510 ar |= (var->l & 1) << 13;
3511 ar |= (var->db & 1) << 14;
3512 ar |= (var->g & 1) << 15;
3513 }
3514
3515 return ar;
3516 }
3517
3518 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3519 struct kvm_segment *var, int seg)
3520 {
3521 struct vcpu_vmx *vmx = to_vmx(vcpu);
3522 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3523
3524 vmx_segment_cache_clear(vmx);
3525 if (seg == VCPU_SREG_CS)
3526 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3527
3528 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3529 vmx->rmode.segs[seg] = *var;
3530 if (seg == VCPU_SREG_TR)
3531 vmcs_write16(sf->selector, var->selector);
3532 else if (var->s)
3533 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3534 goto out;
3535 }
3536
3537 vmcs_writel(sf->base, var->base);
3538 vmcs_write32(sf->limit, var->limit);
3539 vmcs_write16(sf->selector, var->selector);
3540
3541 /*
3542 * Fix the "Accessed" bit in AR field of segment registers for older
3543 * qemu binaries.
3544 * IA32 arch specifies that at the time of processor reset the
3545 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3546 * is setting it to 0 in the userland code. This causes invalid guest
3547 * state vmexit when "unrestricted guest" mode is turned on.
3548 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3549 * tree. Newer qemu binaries with that qemu fix would not need this
3550 * kvm hack.
3551 */
3552 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3553 var->type |= 0x1; /* Accessed */
3554
3555 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3556
3557 out:
3558 vmx->emulation_required |= emulation_required(vcpu);
3559 }
3560
3561 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3562 {
3563 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3564
3565 *db = (ar >> 14) & 1;
3566 *l = (ar >> 13) & 1;
3567 }
3568
3569 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3570 {
3571 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3572 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3573 }
3574
3575 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3576 {
3577 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3578 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3579 }
3580
3581 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3582 {
3583 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3584 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3585 }
3586
3587 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3588 {
3589 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3590 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3591 }
3592
3593 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3594 {
3595 struct kvm_segment var;
3596 u32 ar;
3597
3598 vmx_get_segment(vcpu, &var, seg);
3599 var.dpl = 0x3;
3600 if (seg == VCPU_SREG_CS)
3601 var.type = 0x3;
3602 ar = vmx_segment_access_rights(&var);
3603
3604 if (var.base != (var.selector << 4))
3605 return false;
3606 if (var.limit != 0xffff)
3607 return false;
3608 if (ar != 0xf3)
3609 return false;
3610
3611 return true;
3612 }
3613
3614 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3615 {
3616 struct kvm_segment cs;
3617 unsigned int cs_rpl;
3618
3619 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3620 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3621
3622 if (cs.unusable)
3623 return false;
3624 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3625 return false;
3626 if (!cs.s)
3627 return false;
3628 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3629 if (cs.dpl > cs_rpl)
3630 return false;
3631 } else {
3632 if (cs.dpl != cs_rpl)
3633 return false;
3634 }
3635 if (!cs.present)
3636 return false;
3637
3638 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3639 return true;
3640 }
3641
3642 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3643 {
3644 struct kvm_segment ss;
3645 unsigned int ss_rpl;
3646
3647 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3648 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3649
3650 if (ss.unusable)
3651 return true;
3652 if (ss.type != 3 && ss.type != 7)
3653 return false;
3654 if (!ss.s)
3655 return false;
3656 if (ss.dpl != ss_rpl) /* DPL != RPL */
3657 return false;
3658 if (!ss.present)
3659 return false;
3660
3661 return true;
3662 }
3663
3664 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3665 {
3666 struct kvm_segment var;
3667 unsigned int rpl;
3668
3669 vmx_get_segment(vcpu, &var, seg);
3670 rpl = var.selector & SELECTOR_RPL_MASK;
3671
3672 if (var.unusable)
3673 return true;
3674 if (!var.s)
3675 return false;
3676 if (!var.present)
3677 return false;
3678 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3679 if (var.dpl < rpl) /* DPL < RPL */
3680 return false;
3681 }
3682
3683 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3684 * rights flags
3685 */
3686 return true;
3687 }
3688
3689 static bool tr_valid(struct kvm_vcpu *vcpu)
3690 {
3691 struct kvm_segment tr;
3692
3693 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3694
3695 if (tr.unusable)
3696 return false;
3697 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3698 return false;
3699 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3700 return false;
3701 if (!tr.present)
3702 return false;
3703
3704 return true;
3705 }
3706
3707 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3708 {
3709 struct kvm_segment ldtr;
3710
3711 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3712
3713 if (ldtr.unusable)
3714 return true;
3715 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3716 return false;
3717 if (ldtr.type != 2)
3718 return false;
3719 if (!ldtr.present)
3720 return false;
3721
3722 return true;
3723 }
3724
3725 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3726 {
3727 struct kvm_segment cs, ss;
3728
3729 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3730 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3731
3732 return ((cs.selector & SELECTOR_RPL_MASK) ==
3733 (ss.selector & SELECTOR_RPL_MASK));
3734 }
3735
3736 /*
3737 * Check if guest state is valid. Returns true if valid, false if
3738 * not.
3739 * We assume that registers are always usable
3740 */
3741 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3742 {
3743 if (enable_unrestricted_guest)
3744 return true;
3745
3746 /* real mode guest state checks */
3747 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3748 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3749 return false;
3750 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3751 return false;
3752 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3753 return false;
3754 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3755 return false;
3756 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3757 return false;
3758 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3759 return false;
3760 } else {
3761 /* protected mode guest state checks */
3762 if (!cs_ss_rpl_check(vcpu))
3763 return false;
3764 if (!code_segment_valid(vcpu))
3765 return false;
3766 if (!stack_segment_valid(vcpu))
3767 return false;
3768 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3769 return false;
3770 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3771 return false;
3772 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3773 return false;
3774 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3775 return false;
3776 if (!tr_valid(vcpu))
3777 return false;
3778 if (!ldtr_valid(vcpu))
3779 return false;
3780 }
3781 /* TODO:
3782 * - Add checks on RIP
3783 * - Add checks on RFLAGS
3784 */
3785
3786 return true;
3787 }
3788
3789 static int init_rmode_tss(struct kvm *kvm)
3790 {
3791 gfn_t fn;
3792 u16 data = 0;
3793 int r, idx, ret = 0;
3794
3795 idx = srcu_read_lock(&kvm->srcu);
3796 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3797 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3798 if (r < 0)
3799 goto out;
3800 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3801 r = kvm_write_guest_page(kvm, fn++, &data,
3802 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3803 if (r < 0)
3804 goto out;
3805 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3806 if (r < 0)
3807 goto out;
3808 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3809 if (r < 0)
3810 goto out;
3811 data = ~0;
3812 r = kvm_write_guest_page(kvm, fn, &data,
3813 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3814 sizeof(u8));
3815 if (r < 0)
3816 goto out;
3817
3818 ret = 1;
3819 out:
3820 srcu_read_unlock(&kvm->srcu, idx);
3821 return ret;
3822 }
3823
3824 static int init_rmode_identity_map(struct kvm *kvm)
3825 {
3826 int i, idx, r, ret;
3827 pfn_t identity_map_pfn;
3828 u32 tmp;
3829
3830 if (!enable_ept)
3831 return 1;
3832 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3833 printk(KERN_ERR "EPT: identity-mapping pagetable "
3834 "haven't been allocated!\n");
3835 return 0;
3836 }
3837 if (likely(kvm->arch.ept_identity_pagetable_done))
3838 return 1;
3839 ret = 0;
3840 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3841 idx = srcu_read_lock(&kvm->srcu);
3842 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3843 if (r < 0)
3844 goto out;
3845 /* Set up identity-mapping pagetable for EPT in real mode */
3846 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3847 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3848 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3849 r = kvm_write_guest_page(kvm, identity_map_pfn,
3850 &tmp, i * sizeof(tmp), sizeof(tmp));
3851 if (r < 0)
3852 goto out;
3853 }
3854 kvm->arch.ept_identity_pagetable_done = true;
3855 ret = 1;
3856 out:
3857 srcu_read_unlock(&kvm->srcu, idx);
3858 return ret;
3859 }
3860
3861 static void seg_setup(int seg)
3862 {
3863 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3864 unsigned int ar;
3865
3866 vmcs_write16(sf->selector, 0);
3867 vmcs_writel(sf->base, 0);
3868 vmcs_write32(sf->limit, 0xffff);
3869 ar = 0x93;
3870 if (seg == VCPU_SREG_CS)
3871 ar |= 0x08; /* code segment */
3872
3873 vmcs_write32(sf->ar_bytes, ar);
3874 }
3875
3876 static int alloc_apic_access_page(struct kvm *kvm)
3877 {
3878 struct page *page;
3879 struct kvm_userspace_memory_region kvm_userspace_mem;
3880 int r = 0;
3881
3882 mutex_lock(&kvm->slots_lock);
3883 if (kvm->arch.apic_access_page)
3884 goto out;
3885 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3886 kvm_userspace_mem.flags = 0;
3887 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3888 kvm_userspace_mem.memory_size = PAGE_SIZE;
3889 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3890 if (r)
3891 goto out;
3892
3893 page = gfn_to_page(kvm, 0xfee00);
3894 if (is_error_page(page)) {
3895 r = -EFAULT;
3896 goto out;
3897 }
3898
3899 kvm->arch.apic_access_page = page;
3900 out:
3901 mutex_unlock(&kvm->slots_lock);
3902 return r;
3903 }
3904
3905 static int alloc_identity_pagetable(struct kvm *kvm)
3906 {
3907 struct page *page;
3908 struct kvm_userspace_memory_region kvm_userspace_mem;
3909 int r = 0;
3910
3911 mutex_lock(&kvm->slots_lock);
3912 if (kvm->arch.ept_identity_pagetable)
3913 goto out;
3914 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3915 kvm_userspace_mem.flags = 0;
3916 kvm_userspace_mem.guest_phys_addr =
3917 kvm->arch.ept_identity_map_addr;
3918 kvm_userspace_mem.memory_size = PAGE_SIZE;
3919 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3920 if (r)
3921 goto out;
3922
3923 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3924 if (is_error_page(page)) {
3925 r = -EFAULT;
3926 goto out;
3927 }
3928
3929 kvm->arch.ept_identity_pagetable = page;
3930 out:
3931 mutex_unlock(&kvm->slots_lock);
3932 return r;
3933 }
3934
3935 static void allocate_vpid(struct vcpu_vmx *vmx)
3936 {
3937 int vpid;
3938
3939 vmx->vpid = 0;
3940 if (!enable_vpid)
3941 return;
3942 spin_lock(&vmx_vpid_lock);
3943 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3944 if (vpid < VMX_NR_VPIDS) {
3945 vmx->vpid = vpid;
3946 __set_bit(vpid, vmx_vpid_bitmap);
3947 }
3948 spin_unlock(&vmx_vpid_lock);
3949 }
3950
3951 static void free_vpid(struct vcpu_vmx *vmx)
3952 {
3953 if (!enable_vpid)
3954 return;
3955 spin_lock(&vmx_vpid_lock);
3956 if (vmx->vpid != 0)
3957 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3958 spin_unlock(&vmx_vpid_lock);
3959 }
3960
3961 #define MSR_TYPE_R 1
3962 #define MSR_TYPE_W 2
3963 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3964 u32 msr, int type)
3965 {
3966 int f = sizeof(unsigned long);
3967
3968 if (!cpu_has_vmx_msr_bitmap())
3969 return;
3970
3971 /*
3972 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3973 * have the write-low and read-high bitmap offsets the wrong way round.
3974 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3975 */
3976 if (msr <= 0x1fff) {
3977 if (type & MSR_TYPE_R)
3978 /* read-low */
3979 __clear_bit(msr, msr_bitmap + 0x000 / f);
3980
3981 if (type & MSR_TYPE_W)
3982 /* write-low */
3983 __clear_bit(msr, msr_bitmap + 0x800 / f);
3984
3985 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3986 msr &= 0x1fff;
3987 if (type & MSR_TYPE_R)
3988 /* read-high */
3989 __clear_bit(msr, msr_bitmap + 0x400 / f);
3990
3991 if (type & MSR_TYPE_W)
3992 /* write-high */
3993 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3994
3995 }
3996 }
3997
3998 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3999 u32 msr, int type)
4000 {
4001 int f = sizeof(unsigned long);
4002
4003 if (!cpu_has_vmx_msr_bitmap())
4004 return;
4005
4006 /*
4007 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4008 * have the write-low and read-high bitmap offsets the wrong way round.
4009 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4010 */
4011 if (msr <= 0x1fff) {
4012 if (type & MSR_TYPE_R)
4013 /* read-low */
4014 __set_bit(msr, msr_bitmap + 0x000 / f);
4015
4016 if (type & MSR_TYPE_W)
4017 /* write-low */
4018 __set_bit(msr, msr_bitmap + 0x800 / f);
4019
4020 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4021 msr &= 0x1fff;
4022 if (type & MSR_TYPE_R)
4023 /* read-high */
4024 __set_bit(msr, msr_bitmap + 0x400 / f);
4025
4026 if (type & MSR_TYPE_W)
4027 /* write-high */
4028 __set_bit(msr, msr_bitmap + 0xc00 / f);
4029
4030 }
4031 }
4032
4033 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4034 {
4035 if (!longmode_only)
4036 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4037 msr, MSR_TYPE_R | MSR_TYPE_W);
4038 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4039 msr, MSR_TYPE_R | MSR_TYPE_W);
4040 }
4041
4042 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4043 {
4044 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4045 msr, MSR_TYPE_R);
4046 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4047 msr, MSR_TYPE_R);
4048 }
4049
4050 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4051 {
4052 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4053 msr, MSR_TYPE_R);
4054 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4055 msr, MSR_TYPE_R);
4056 }
4057
4058 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4059 {
4060 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4061 msr, MSR_TYPE_W);
4062 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4063 msr, MSR_TYPE_W);
4064 }
4065
4066 static int vmx_vm_has_apicv(struct kvm *kvm)
4067 {
4068 return enable_apicv && irqchip_in_kernel(kvm);
4069 }
4070
4071 /*
4072 * Send interrupt to vcpu via posted interrupt way.
4073 * 1. If target vcpu is running(non-root mode), send posted interrupt
4074 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4075 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4076 * interrupt from PIR in next vmentry.
4077 */
4078 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4079 {
4080 struct vcpu_vmx *vmx = to_vmx(vcpu);
4081 int r;
4082
4083 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4084 return;
4085
4086 r = pi_test_and_set_on(&vmx->pi_desc);
4087 kvm_make_request(KVM_REQ_EVENT, vcpu);
4088 #ifdef CONFIG_SMP
4089 if (!r && (vcpu->mode == IN_GUEST_MODE))
4090 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4091 POSTED_INTR_VECTOR);
4092 else
4093 #endif
4094 kvm_vcpu_kick(vcpu);
4095 }
4096
4097 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4098 {
4099 struct vcpu_vmx *vmx = to_vmx(vcpu);
4100
4101 if (!pi_test_and_clear_on(&vmx->pi_desc))
4102 return;
4103
4104 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4105 }
4106
4107 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4108 {
4109 return;
4110 }
4111
4112 /*
4113 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4114 * will not change in the lifetime of the guest.
4115 * Note that host-state that does change is set elsewhere. E.g., host-state
4116 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4117 */
4118 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4119 {
4120 u32 low32, high32;
4121 unsigned long tmpl;
4122 struct desc_ptr dt;
4123
4124 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4125 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4126 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4127
4128 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4129 #ifdef CONFIG_X86_64
4130 /*
4131 * Load null selectors, so we can avoid reloading them in
4132 * __vmx_load_host_state(), in case userspace uses the null selectors
4133 * too (the expected case).
4134 */
4135 vmcs_write16(HOST_DS_SELECTOR, 0);
4136 vmcs_write16(HOST_ES_SELECTOR, 0);
4137 #else
4138 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4139 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4140 #endif
4141 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4142 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4143
4144 native_store_idt(&dt);
4145 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4146 vmx->host_idt_base = dt.address;
4147
4148 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4149
4150 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4151 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4152 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4153 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4154
4155 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4156 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4157 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4158 }
4159 }
4160
4161 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4162 {
4163 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4164 if (enable_ept)
4165 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4166 if (is_guest_mode(&vmx->vcpu))
4167 vmx->vcpu.arch.cr4_guest_owned_bits &=
4168 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4169 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4170 }
4171
4172 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4173 {
4174 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4175
4176 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4177 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4178 return pin_based_exec_ctrl;
4179 }
4180
4181 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4182 {
4183 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4184 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4185 exec_control &= ~CPU_BASED_TPR_SHADOW;
4186 #ifdef CONFIG_X86_64
4187 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4188 CPU_BASED_CR8_LOAD_EXITING;
4189 #endif
4190 }
4191 if (!enable_ept)
4192 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4193 CPU_BASED_CR3_LOAD_EXITING |
4194 CPU_BASED_INVLPG_EXITING;
4195 return exec_control;
4196 }
4197
4198 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4199 {
4200 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4201 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4202 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4203 if (vmx->vpid == 0)
4204 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4205 if (!enable_ept) {
4206 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4207 enable_unrestricted_guest = 0;
4208 /* Enable INVPCID for non-ept guests may cause performance regression. */
4209 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4210 }
4211 if (!enable_unrestricted_guest)
4212 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4213 if (!ple_gap)
4214 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4215 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4216 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4217 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4218 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4219 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4220 (handle_vmptrld).
4221 We can NOT enable shadow_vmcs here because we don't have yet
4222 a current VMCS12
4223 */
4224 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4225 return exec_control;
4226 }
4227
4228 static void ept_set_mmio_spte_mask(void)
4229 {
4230 /*
4231 * EPT Misconfigurations can be generated if the value of bits 2:0
4232 * of an EPT paging-structure entry is 110b (write/execute).
4233 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4234 * spte.
4235 */
4236 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4237 }
4238
4239 /*
4240 * Sets up the vmcs for emulated real mode.
4241 */
4242 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4243 {
4244 #ifdef CONFIG_X86_64
4245 unsigned long a;
4246 #endif
4247 int i;
4248
4249 /* I/O */
4250 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4251 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4252
4253 if (enable_shadow_vmcs) {
4254 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4255 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4256 }
4257 if (cpu_has_vmx_msr_bitmap())
4258 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4259
4260 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4261
4262 /* Control */
4263 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4264
4265 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4266
4267 if (cpu_has_secondary_exec_ctrls()) {
4268 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4269 vmx_secondary_exec_control(vmx));
4270 }
4271
4272 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4273 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4274 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4275 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4276 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4277
4278 vmcs_write16(GUEST_INTR_STATUS, 0);
4279
4280 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4281 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4282 }
4283
4284 if (ple_gap) {
4285 vmcs_write32(PLE_GAP, ple_gap);
4286 vmcs_write32(PLE_WINDOW, ple_window);
4287 }
4288
4289 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4290 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4291 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4292
4293 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4294 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4295 vmx_set_constant_host_state(vmx);
4296 #ifdef CONFIG_X86_64
4297 rdmsrl(MSR_FS_BASE, a);
4298 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4299 rdmsrl(MSR_GS_BASE, a);
4300 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4301 #else
4302 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4303 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4304 #endif
4305
4306 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4307 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4308 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4309 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4310 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4311
4312 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4313 u32 msr_low, msr_high;
4314 u64 host_pat;
4315 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4316 host_pat = msr_low | ((u64) msr_high << 32);
4317 /* Write the default value follow host pat */
4318 vmcs_write64(GUEST_IA32_PAT, host_pat);
4319 /* Keep arch.pat sync with GUEST_IA32_PAT */
4320 vmx->vcpu.arch.pat = host_pat;
4321 }
4322
4323 for (i = 0; i < NR_VMX_MSR; ++i) {
4324 u32 index = vmx_msr_index[i];
4325 u32 data_low, data_high;
4326 int j = vmx->nmsrs;
4327
4328 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4329 continue;
4330 if (wrmsr_safe(index, data_low, data_high) < 0)
4331 continue;
4332 vmx->guest_msrs[j].index = i;
4333 vmx->guest_msrs[j].data = 0;
4334 vmx->guest_msrs[j].mask = -1ull;
4335 ++vmx->nmsrs;
4336 }
4337
4338 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4339
4340 /* 22.2.1, 20.8.1 */
4341 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4342
4343 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4344 set_cr4_guest_host_mask(vmx);
4345
4346 return 0;
4347 }
4348
4349 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4350 {
4351 struct vcpu_vmx *vmx = to_vmx(vcpu);
4352 u64 msr;
4353
4354 vmx->rmode.vm86_active = 0;
4355
4356 vmx->soft_vnmi_blocked = 0;
4357
4358 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4359 kvm_set_cr8(&vmx->vcpu, 0);
4360 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4361 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4362 msr |= MSR_IA32_APICBASE_BSP;
4363 kvm_set_apic_base(&vmx->vcpu, msr);
4364
4365 vmx_segment_cache_clear(vmx);
4366
4367 seg_setup(VCPU_SREG_CS);
4368 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4369 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4370
4371 seg_setup(VCPU_SREG_DS);
4372 seg_setup(VCPU_SREG_ES);
4373 seg_setup(VCPU_SREG_FS);
4374 seg_setup(VCPU_SREG_GS);
4375 seg_setup(VCPU_SREG_SS);
4376
4377 vmcs_write16(GUEST_TR_SELECTOR, 0);
4378 vmcs_writel(GUEST_TR_BASE, 0);
4379 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4380 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4381
4382 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4383 vmcs_writel(GUEST_LDTR_BASE, 0);
4384 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4385 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4386
4387 vmcs_write32(GUEST_SYSENTER_CS, 0);
4388 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4389 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4390
4391 vmcs_writel(GUEST_RFLAGS, 0x02);
4392 kvm_rip_write(vcpu, 0xfff0);
4393
4394 vmcs_writel(GUEST_GDTR_BASE, 0);
4395 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4396
4397 vmcs_writel(GUEST_IDTR_BASE, 0);
4398 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4399
4400 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4401 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4402 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4403
4404 /* Special registers */
4405 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4406
4407 setup_msrs(vmx);
4408
4409 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4410
4411 if (cpu_has_vmx_tpr_shadow()) {
4412 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4413 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4414 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4415 __pa(vmx->vcpu.arch.apic->regs));
4416 vmcs_write32(TPR_THRESHOLD, 0);
4417 }
4418
4419 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4420 vmcs_write64(APIC_ACCESS_ADDR,
4421 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4422
4423 if (vmx_vm_has_apicv(vcpu->kvm))
4424 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4425
4426 if (vmx->vpid != 0)
4427 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4428
4429 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4430 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4431 vmx_set_cr4(&vmx->vcpu, 0);
4432 vmx_set_efer(&vmx->vcpu, 0);
4433 vmx_fpu_activate(&vmx->vcpu);
4434 update_exception_bitmap(&vmx->vcpu);
4435
4436 vpid_sync_context(vmx);
4437 }
4438
4439 /*
4440 * In nested virtualization, check if L1 asked to exit on external interrupts.
4441 * For most existing hypervisors, this will always return true.
4442 */
4443 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4444 {
4445 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4446 PIN_BASED_EXT_INTR_MASK;
4447 }
4448
4449 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4450 {
4451 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4452 PIN_BASED_NMI_EXITING;
4453 }
4454
4455 static int enable_irq_window(struct kvm_vcpu *vcpu)
4456 {
4457 u32 cpu_based_vm_exec_control;
4458
4459 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4460 /*
4461 * We get here if vmx_interrupt_allowed() said we can't
4462 * inject to L1 now because L2 must run. The caller will have
4463 * to make L2 exit right after entry, so we can inject to L1
4464 * more promptly.
4465 */
4466 return -EBUSY;
4467
4468 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4469 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4470 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4471 return 0;
4472 }
4473
4474 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4475 {
4476 u32 cpu_based_vm_exec_control;
4477
4478 if (!cpu_has_virtual_nmis())
4479 return enable_irq_window(vcpu);
4480
4481 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4482 return enable_irq_window(vcpu);
4483
4484 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4485 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4486 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4487 return 0;
4488 }
4489
4490 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4491 {
4492 struct vcpu_vmx *vmx = to_vmx(vcpu);
4493 uint32_t intr;
4494 int irq = vcpu->arch.interrupt.nr;
4495
4496 trace_kvm_inj_virq(irq);
4497
4498 ++vcpu->stat.irq_injections;
4499 if (vmx->rmode.vm86_active) {
4500 int inc_eip = 0;
4501 if (vcpu->arch.interrupt.soft)
4502 inc_eip = vcpu->arch.event_exit_inst_len;
4503 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4504 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4505 return;
4506 }
4507 intr = irq | INTR_INFO_VALID_MASK;
4508 if (vcpu->arch.interrupt.soft) {
4509 intr |= INTR_TYPE_SOFT_INTR;
4510 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4511 vmx->vcpu.arch.event_exit_inst_len);
4512 } else
4513 intr |= INTR_TYPE_EXT_INTR;
4514 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4515 }
4516
4517 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4518 {
4519 struct vcpu_vmx *vmx = to_vmx(vcpu);
4520
4521 if (is_guest_mode(vcpu))
4522 return;
4523
4524 if (!cpu_has_virtual_nmis()) {
4525 /*
4526 * Tracking the NMI-blocked state in software is built upon
4527 * finding the next open IRQ window. This, in turn, depends on
4528 * well-behaving guests: They have to keep IRQs disabled at
4529 * least as long as the NMI handler runs. Otherwise we may
4530 * cause NMI nesting, maybe breaking the guest. But as this is
4531 * highly unlikely, we can live with the residual risk.
4532 */
4533 vmx->soft_vnmi_blocked = 1;
4534 vmx->vnmi_blocked_time = 0;
4535 }
4536
4537 ++vcpu->stat.nmi_injections;
4538 vmx->nmi_known_unmasked = false;
4539 if (vmx->rmode.vm86_active) {
4540 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4541 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4542 return;
4543 }
4544 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4545 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4546 }
4547
4548 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4549 {
4550 if (!cpu_has_virtual_nmis())
4551 return to_vmx(vcpu)->soft_vnmi_blocked;
4552 if (to_vmx(vcpu)->nmi_known_unmasked)
4553 return false;
4554 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4555 }
4556
4557 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4558 {
4559 struct vcpu_vmx *vmx = to_vmx(vcpu);
4560
4561 if (!cpu_has_virtual_nmis()) {
4562 if (vmx->soft_vnmi_blocked != masked) {
4563 vmx->soft_vnmi_blocked = masked;
4564 vmx->vnmi_blocked_time = 0;
4565 }
4566 } else {
4567 vmx->nmi_known_unmasked = !masked;
4568 if (masked)
4569 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4570 GUEST_INTR_STATE_NMI);
4571 else
4572 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4573 GUEST_INTR_STATE_NMI);
4574 }
4575 }
4576
4577 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4578 {
4579 if (is_guest_mode(vcpu)) {
4580 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4581
4582 if (to_vmx(vcpu)->nested.nested_run_pending)
4583 return 0;
4584 if (nested_exit_on_nmi(vcpu)) {
4585 nested_vmx_vmexit(vcpu);
4586 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4587 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4588 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4589 /*
4590 * The NMI-triggered VM exit counts as injection:
4591 * clear this one and block further NMIs.
4592 */
4593 vcpu->arch.nmi_pending = 0;
4594 vmx_set_nmi_mask(vcpu, true);
4595 return 0;
4596 }
4597 }
4598
4599 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4600 return 0;
4601
4602 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4603 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4604 | GUEST_INTR_STATE_NMI));
4605 }
4606
4607 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4608 {
4609 if (is_guest_mode(vcpu)) {
4610 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4611
4612 if (to_vmx(vcpu)->nested.nested_run_pending)
4613 return 0;
4614 if (nested_exit_on_intr(vcpu)) {
4615 nested_vmx_vmexit(vcpu);
4616 vmcs12->vm_exit_reason =
4617 EXIT_REASON_EXTERNAL_INTERRUPT;
4618 vmcs12->vm_exit_intr_info = 0;
4619 /*
4620 * fall through to normal code, but now in L1, not L2
4621 */
4622 }
4623 }
4624
4625 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4626 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4627 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4628 }
4629
4630 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4631 {
4632 int ret;
4633 struct kvm_userspace_memory_region tss_mem = {
4634 .slot = TSS_PRIVATE_MEMSLOT,
4635 .guest_phys_addr = addr,
4636 .memory_size = PAGE_SIZE * 3,
4637 .flags = 0,
4638 };
4639
4640 ret = kvm_set_memory_region(kvm, &tss_mem);
4641 if (ret)
4642 return ret;
4643 kvm->arch.tss_addr = addr;
4644 if (!init_rmode_tss(kvm))
4645 return -ENOMEM;
4646
4647 return 0;
4648 }
4649
4650 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4651 {
4652 switch (vec) {
4653 case BP_VECTOR:
4654 /*
4655 * Update instruction length as we may reinject the exception
4656 * from user space while in guest debugging mode.
4657 */
4658 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4659 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4660 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4661 return false;
4662 /* fall through */
4663 case DB_VECTOR:
4664 if (vcpu->guest_debug &
4665 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4666 return false;
4667 /* fall through */
4668 case DE_VECTOR:
4669 case OF_VECTOR:
4670 case BR_VECTOR:
4671 case UD_VECTOR:
4672 case DF_VECTOR:
4673 case SS_VECTOR:
4674 case GP_VECTOR:
4675 case MF_VECTOR:
4676 return true;
4677 break;
4678 }
4679 return false;
4680 }
4681
4682 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4683 int vec, u32 err_code)
4684 {
4685 /*
4686 * Instruction with address size override prefix opcode 0x67
4687 * Cause the #SS fault with 0 error code in VM86 mode.
4688 */
4689 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4690 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4691 if (vcpu->arch.halt_request) {
4692 vcpu->arch.halt_request = 0;
4693 return kvm_emulate_halt(vcpu);
4694 }
4695 return 1;
4696 }
4697 return 0;
4698 }
4699
4700 /*
4701 * Forward all other exceptions that are valid in real mode.
4702 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4703 * the required debugging infrastructure rework.
4704 */
4705 kvm_queue_exception(vcpu, vec);
4706 return 1;
4707 }
4708
4709 /*
4710 * Trigger machine check on the host. We assume all the MSRs are already set up
4711 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4712 * We pass a fake environment to the machine check handler because we want
4713 * the guest to be always treated like user space, no matter what context
4714 * it used internally.
4715 */
4716 static void kvm_machine_check(void)
4717 {
4718 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4719 struct pt_regs regs = {
4720 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4721 .flags = X86_EFLAGS_IF,
4722 };
4723
4724 do_machine_check(&regs, 0);
4725 #endif
4726 }
4727
4728 static int handle_machine_check(struct kvm_vcpu *vcpu)
4729 {
4730 /* already handled by vcpu_run */
4731 return 1;
4732 }
4733
4734 static int handle_exception(struct kvm_vcpu *vcpu)
4735 {
4736 struct vcpu_vmx *vmx = to_vmx(vcpu);
4737 struct kvm_run *kvm_run = vcpu->run;
4738 u32 intr_info, ex_no, error_code;
4739 unsigned long cr2, rip, dr6;
4740 u32 vect_info;
4741 enum emulation_result er;
4742
4743 vect_info = vmx->idt_vectoring_info;
4744 intr_info = vmx->exit_intr_info;
4745
4746 if (is_machine_check(intr_info))
4747 return handle_machine_check(vcpu);
4748
4749 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4750 return 1; /* already handled by vmx_vcpu_run() */
4751
4752 if (is_no_device(intr_info)) {
4753 vmx_fpu_activate(vcpu);
4754 return 1;
4755 }
4756
4757 if (is_invalid_opcode(intr_info)) {
4758 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4759 if (er != EMULATE_DONE)
4760 kvm_queue_exception(vcpu, UD_VECTOR);
4761 return 1;
4762 }
4763
4764 error_code = 0;
4765 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4766 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4767
4768 /*
4769 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4770 * MMIO, it is better to report an internal error.
4771 * See the comments in vmx_handle_exit.
4772 */
4773 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4774 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4775 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4776 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4777 vcpu->run->internal.ndata = 2;
4778 vcpu->run->internal.data[0] = vect_info;
4779 vcpu->run->internal.data[1] = intr_info;
4780 return 0;
4781 }
4782
4783 if (is_page_fault(intr_info)) {
4784 /* EPT won't cause page fault directly */
4785 BUG_ON(enable_ept);
4786 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4787 trace_kvm_page_fault(cr2, error_code);
4788
4789 if (kvm_event_needs_reinjection(vcpu))
4790 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4791 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4792 }
4793
4794 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4795
4796 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4797 return handle_rmode_exception(vcpu, ex_no, error_code);
4798
4799 switch (ex_no) {
4800 case DB_VECTOR:
4801 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4802 if (!(vcpu->guest_debug &
4803 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4804 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4805 kvm_queue_exception(vcpu, DB_VECTOR);
4806 return 1;
4807 }
4808 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4809 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4810 /* fall through */
4811 case BP_VECTOR:
4812 /*
4813 * Update instruction length as we may reinject #BP from
4814 * user space while in guest debugging mode. Reading it for
4815 * #DB as well causes no harm, it is not used in that case.
4816 */
4817 vmx->vcpu.arch.event_exit_inst_len =
4818 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4819 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4820 rip = kvm_rip_read(vcpu);
4821 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4822 kvm_run->debug.arch.exception = ex_no;
4823 break;
4824 default:
4825 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4826 kvm_run->ex.exception = ex_no;
4827 kvm_run->ex.error_code = error_code;
4828 break;
4829 }
4830 return 0;
4831 }
4832
4833 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4834 {
4835 ++vcpu->stat.irq_exits;
4836 return 1;
4837 }
4838
4839 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4840 {
4841 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4842 return 0;
4843 }
4844
4845 static int handle_io(struct kvm_vcpu *vcpu)
4846 {
4847 unsigned long exit_qualification;
4848 int size, in, string;
4849 unsigned port;
4850
4851 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4852 string = (exit_qualification & 16) != 0;
4853 in = (exit_qualification & 8) != 0;
4854
4855 ++vcpu->stat.io_exits;
4856
4857 if (string || in)
4858 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4859
4860 port = exit_qualification >> 16;
4861 size = (exit_qualification & 7) + 1;
4862 skip_emulated_instruction(vcpu);
4863
4864 return kvm_fast_pio_out(vcpu, size, port);
4865 }
4866
4867 static void
4868 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4869 {
4870 /*
4871 * Patch in the VMCALL instruction:
4872 */
4873 hypercall[0] = 0x0f;
4874 hypercall[1] = 0x01;
4875 hypercall[2] = 0xc1;
4876 }
4877
4878 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4879 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4880 {
4881 if (is_guest_mode(vcpu)) {
4882 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4883 unsigned long orig_val = val;
4884
4885 /*
4886 * We get here when L2 changed cr0 in a way that did not change
4887 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4888 * but did change L0 shadowed bits. So we first calculate the
4889 * effective cr0 value that L1 would like to write into the
4890 * hardware. It consists of the L2-owned bits from the new
4891 * value combined with the L1-owned bits from L1's guest_cr0.
4892 */
4893 val = (val & ~vmcs12->cr0_guest_host_mask) |
4894 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4895
4896 /* TODO: will have to take unrestricted guest mode into
4897 * account */
4898 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4899 return 1;
4900
4901 if (kvm_set_cr0(vcpu, val))
4902 return 1;
4903 vmcs_writel(CR0_READ_SHADOW, orig_val);
4904 return 0;
4905 } else {
4906 if (to_vmx(vcpu)->nested.vmxon &&
4907 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4908 return 1;
4909 return kvm_set_cr0(vcpu, val);
4910 }
4911 }
4912
4913 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4914 {
4915 if (is_guest_mode(vcpu)) {
4916 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4917 unsigned long orig_val = val;
4918
4919 /* analogously to handle_set_cr0 */
4920 val = (val & ~vmcs12->cr4_guest_host_mask) |
4921 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4922 if (kvm_set_cr4(vcpu, val))
4923 return 1;
4924 vmcs_writel(CR4_READ_SHADOW, orig_val);
4925 return 0;
4926 } else
4927 return kvm_set_cr4(vcpu, val);
4928 }
4929
4930 /* called to set cr0 as approriate for clts instruction exit. */
4931 static void handle_clts(struct kvm_vcpu *vcpu)
4932 {
4933 if (is_guest_mode(vcpu)) {
4934 /*
4935 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4936 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4937 * just pretend it's off (also in arch.cr0 for fpu_activate).
4938 */
4939 vmcs_writel(CR0_READ_SHADOW,
4940 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4941 vcpu->arch.cr0 &= ~X86_CR0_TS;
4942 } else
4943 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4944 }
4945
4946 static int handle_cr(struct kvm_vcpu *vcpu)
4947 {
4948 unsigned long exit_qualification, val;
4949 int cr;
4950 int reg;
4951 int err;
4952
4953 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4954 cr = exit_qualification & 15;
4955 reg = (exit_qualification >> 8) & 15;
4956 switch ((exit_qualification >> 4) & 3) {
4957 case 0: /* mov to cr */
4958 val = kvm_register_read(vcpu, reg);
4959 trace_kvm_cr_write(cr, val);
4960 switch (cr) {
4961 case 0:
4962 err = handle_set_cr0(vcpu, val);
4963 kvm_complete_insn_gp(vcpu, err);
4964 return 1;
4965 case 3:
4966 err = kvm_set_cr3(vcpu, val);
4967 kvm_complete_insn_gp(vcpu, err);
4968 return 1;
4969 case 4:
4970 err = handle_set_cr4(vcpu, val);
4971 kvm_complete_insn_gp(vcpu, err);
4972 return 1;
4973 case 8: {
4974 u8 cr8_prev = kvm_get_cr8(vcpu);
4975 u8 cr8 = kvm_register_read(vcpu, reg);
4976 err = kvm_set_cr8(vcpu, cr8);
4977 kvm_complete_insn_gp(vcpu, err);
4978 if (irqchip_in_kernel(vcpu->kvm))
4979 return 1;
4980 if (cr8_prev <= cr8)
4981 return 1;
4982 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4983 return 0;
4984 }
4985 }
4986 break;
4987 case 2: /* clts */
4988 handle_clts(vcpu);
4989 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4990 skip_emulated_instruction(vcpu);
4991 vmx_fpu_activate(vcpu);
4992 return 1;
4993 case 1: /*mov from cr*/
4994 switch (cr) {
4995 case 3:
4996 val = kvm_read_cr3(vcpu);
4997 kvm_register_write(vcpu, reg, val);
4998 trace_kvm_cr_read(cr, val);
4999 skip_emulated_instruction(vcpu);
5000 return 1;
5001 case 8:
5002 val = kvm_get_cr8(vcpu);
5003 kvm_register_write(vcpu, reg, val);
5004 trace_kvm_cr_read(cr, val);
5005 skip_emulated_instruction(vcpu);
5006 return 1;
5007 }
5008 break;
5009 case 3: /* lmsw */
5010 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5011 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5012 kvm_lmsw(vcpu, val);
5013
5014 skip_emulated_instruction(vcpu);
5015 return 1;
5016 default:
5017 break;
5018 }
5019 vcpu->run->exit_reason = 0;
5020 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5021 (int)(exit_qualification >> 4) & 3, cr);
5022 return 0;
5023 }
5024
5025 static int handle_dr(struct kvm_vcpu *vcpu)
5026 {
5027 unsigned long exit_qualification;
5028 int dr, reg;
5029
5030 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5031 if (!kvm_require_cpl(vcpu, 0))
5032 return 1;
5033 dr = vmcs_readl(GUEST_DR7);
5034 if (dr & DR7_GD) {
5035 /*
5036 * As the vm-exit takes precedence over the debug trap, we
5037 * need to emulate the latter, either for the host or the
5038 * guest debugging itself.
5039 */
5040 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5041 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5042 vcpu->run->debug.arch.dr7 = dr;
5043 vcpu->run->debug.arch.pc =
5044 vmcs_readl(GUEST_CS_BASE) +
5045 vmcs_readl(GUEST_RIP);
5046 vcpu->run->debug.arch.exception = DB_VECTOR;
5047 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5048 return 0;
5049 } else {
5050 vcpu->arch.dr7 &= ~DR7_GD;
5051 vcpu->arch.dr6 |= DR6_BD;
5052 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5053 kvm_queue_exception(vcpu, DB_VECTOR);
5054 return 1;
5055 }
5056 }
5057
5058 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5059 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5060 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5061 if (exit_qualification & TYPE_MOV_FROM_DR) {
5062 unsigned long val;
5063 if (!kvm_get_dr(vcpu, dr, &val))
5064 kvm_register_write(vcpu, reg, val);
5065 } else
5066 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5067 skip_emulated_instruction(vcpu);
5068 return 1;
5069 }
5070
5071 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5072 {
5073 vmcs_writel(GUEST_DR7, val);
5074 }
5075
5076 static int handle_cpuid(struct kvm_vcpu *vcpu)
5077 {
5078 kvm_emulate_cpuid(vcpu);
5079 return 1;
5080 }
5081
5082 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5083 {
5084 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5085 u64 data;
5086
5087 if (vmx_get_msr(vcpu, ecx, &data)) {
5088 trace_kvm_msr_read_ex(ecx);
5089 kvm_inject_gp(vcpu, 0);
5090 return 1;
5091 }
5092
5093 trace_kvm_msr_read(ecx, data);
5094
5095 /* FIXME: handling of bits 32:63 of rax, rdx */
5096 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5097 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5098 skip_emulated_instruction(vcpu);
5099 return 1;
5100 }
5101
5102 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5103 {
5104 struct msr_data msr;
5105 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5106 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5107 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5108
5109 msr.data = data;
5110 msr.index = ecx;
5111 msr.host_initiated = false;
5112 if (vmx_set_msr(vcpu, &msr) != 0) {
5113 trace_kvm_msr_write_ex(ecx, data);
5114 kvm_inject_gp(vcpu, 0);
5115 return 1;
5116 }
5117
5118 trace_kvm_msr_write(ecx, data);
5119 skip_emulated_instruction(vcpu);
5120 return 1;
5121 }
5122
5123 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5124 {
5125 kvm_make_request(KVM_REQ_EVENT, vcpu);
5126 return 1;
5127 }
5128
5129 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5130 {
5131 u32 cpu_based_vm_exec_control;
5132
5133 /* clear pending irq */
5134 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5135 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5136 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5137
5138 kvm_make_request(KVM_REQ_EVENT, vcpu);
5139
5140 ++vcpu->stat.irq_window_exits;
5141
5142 /*
5143 * If the user space waits to inject interrupts, exit as soon as
5144 * possible
5145 */
5146 if (!irqchip_in_kernel(vcpu->kvm) &&
5147 vcpu->run->request_interrupt_window &&
5148 !kvm_cpu_has_interrupt(vcpu)) {
5149 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5150 return 0;
5151 }
5152 return 1;
5153 }
5154
5155 static int handle_halt(struct kvm_vcpu *vcpu)
5156 {
5157 skip_emulated_instruction(vcpu);
5158 return kvm_emulate_halt(vcpu);
5159 }
5160
5161 static int handle_vmcall(struct kvm_vcpu *vcpu)
5162 {
5163 skip_emulated_instruction(vcpu);
5164 kvm_emulate_hypercall(vcpu);
5165 return 1;
5166 }
5167
5168 static int handle_invd(struct kvm_vcpu *vcpu)
5169 {
5170 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5171 }
5172
5173 static int handle_invlpg(struct kvm_vcpu *vcpu)
5174 {
5175 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5176
5177 kvm_mmu_invlpg(vcpu, exit_qualification);
5178 skip_emulated_instruction(vcpu);
5179 return 1;
5180 }
5181
5182 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5183 {
5184 int err;
5185
5186 err = kvm_rdpmc(vcpu);
5187 kvm_complete_insn_gp(vcpu, err);
5188
5189 return 1;
5190 }
5191
5192 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5193 {
5194 skip_emulated_instruction(vcpu);
5195 kvm_emulate_wbinvd(vcpu);
5196 return 1;
5197 }
5198
5199 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5200 {
5201 u64 new_bv = kvm_read_edx_eax(vcpu);
5202 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5203
5204 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5205 skip_emulated_instruction(vcpu);
5206 return 1;
5207 }
5208
5209 static int handle_apic_access(struct kvm_vcpu *vcpu)
5210 {
5211 if (likely(fasteoi)) {
5212 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5213 int access_type, offset;
5214
5215 access_type = exit_qualification & APIC_ACCESS_TYPE;
5216 offset = exit_qualification & APIC_ACCESS_OFFSET;
5217 /*
5218 * Sane guest uses MOV to write EOI, with written value
5219 * not cared. So make a short-circuit here by avoiding
5220 * heavy instruction emulation.
5221 */
5222 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5223 (offset == APIC_EOI)) {
5224 kvm_lapic_set_eoi(vcpu);
5225 skip_emulated_instruction(vcpu);
5226 return 1;
5227 }
5228 }
5229 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5230 }
5231
5232 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5233 {
5234 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5235 int vector = exit_qualification & 0xff;
5236
5237 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5238 kvm_apic_set_eoi_accelerated(vcpu, vector);
5239 return 1;
5240 }
5241
5242 static int handle_apic_write(struct kvm_vcpu *vcpu)
5243 {
5244 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5245 u32 offset = exit_qualification & 0xfff;
5246
5247 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5248 kvm_apic_write_nodecode(vcpu, offset);
5249 return 1;
5250 }
5251
5252 static int handle_task_switch(struct kvm_vcpu *vcpu)
5253 {
5254 struct vcpu_vmx *vmx = to_vmx(vcpu);
5255 unsigned long exit_qualification;
5256 bool has_error_code = false;
5257 u32 error_code = 0;
5258 u16 tss_selector;
5259 int reason, type, idt_v, idt_index;
5260
5261 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5262 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5263 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5264
5265 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5266
5267 reason = (u32)exit_qualification >> 30;
5268 if (reason == TASK_SWITCH_GATE && idt_v) {
5269 switch (type) {
5270 case INTR_TYPE_NMI_INTR:
5271 vcpu->arch.nmi_injected = false;
5272 vmx_set_nmi_mask(vcpu, true);
5273 break;
5274 case INTR_TYPE_EXT_INTR:
5275 case INTR_TYPE_SOFT_INTR:
5276 kvm_clear_interrupt_queue(vcpu);
5277 break;
5278 case INTR_TYPE_HARD_EXCEPTION:
5279 if (vmx->idt_vectoring_info &
5280 VECTORING_INFO_DELIVER_CODE_MASK) {
5281 has_error_code = true;
5282 error_code =
5283 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5284 }
5285 /* fall through */
5286 case INTR_TYPE_SOFT_EXCEPTION:
5287 kvm_clear_exception_queue(vcpu);
5288 break;
5289 default:
5290 break;
5291 }
5292 }
5293 tss_selector = exit_qualification;
5294
5295 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5296 type != INTR_TYPE_EXT_INTR &&
5297 type != INTR_TYPE_NMI_INTR))
5298 skip_emulated_instruction(vcpu);
5299
5300 if (kvm_task_switch(vcpu, tss_selector,
5301 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5302 has_error_code, error_code) == EMULATE_FAIL) {
5303 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5304 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5305 vcpu->run->internal.ndata = 0;
5306 return 0;
5307 }
5308
5309 /* clear all local breakpoint enable flags */
5310 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5311
5312 /*
5313 * TODO: What about debug traps on tss switch?
5314 * Are we supposed to inject them and update dr6?
5315 */
5316
5317 return 1;
5318 }
5319
5320 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5321 {
5322 unsigned long exit_qualification;
5323 gpa_t gpa;
5324 u32 error_code;
5325 int gla_validity;
5326
5327 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5328
5329 gla_validity = (exit_qualification >> 7) & 0x3;
5330 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5331 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5332 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5333 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5334 vmcs_readl(GUEST_LINEAR_ADDRESS));
5335 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5336 (long unsigned int)exit_qualification);
5337 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5338 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5339 return 0;
5340 }
5341
5342 /*
5343 * EPT violation happened while executing iret from NMI,
5344 * "blocked by NMI" bit has to be set before next VM entry.
5345 * There are errata that may cause this bit to not be set:
5346 * AAK134, BY25.
5347 */
5348 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5349 cpu_has_virtual_nmis() &&
5350 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5351 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5352
5353 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5354 trace_kvm_page_fault(gpa, exit_qualification);
5355
5356 /* It is a write fault? */
5357 error_code = exit_qualification & (1U << 1);
5358 /* It is a fetch fault? */
5359 error_code |= (exit_qualification & (1U << 2)) << 2;
5360 /* ept page table is present? */
5361 error_code |= (exit_qualification >> 3) & 0x1;
5362
5363 vcpu->arch.exit_qualification = exit_qualification;
5364
5365 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5366 }
5367
5368 static u64 ept_rsvd_mask(u64 spte, int level)
5369 {
5370 int i;
5371 u64 mask = 0;
5372
5373 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5374 mask |= (1ULL << i);
5375
5376 if (level > 2)
5377 /* bits 7:3 reserved */
5378 mask |= 0xf8;
5379 else if (level == 2) {
5380 if (spte & (1ULL << 7))
5381 /* 2MB ref, bits 20:12 reserved */
5382 mask |= 0x1ff000;
5383 else
5384 /* bits 6:3 reserved */
5385 mask |= 0x78;
5386 }
5387
5388 return mask;
5389 }
5390
5391 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5392 int level)
5393 {
5394 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5395
5396 /* 010b (write-only) */
5397 WARN_ON((spte & 0x7) == 0x2);
5398
5399 /* 110b (write/execute) */
5400 WARN_ON((spte & 0x7) == 0x6);
5401
5402 /* 100b (execute-only) and value not supported by logical processor */
5403 if (!cpu_has_vmx_ept_execute_only())
5404 WARN_ON((spte & 0x7) == 0x4);
5405
5406 /* not 000b */
5407 if ((spte & 0x7)) {
5408 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5409
5410 if (rsvd_bits != 0) {
5411 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5412 __func__, rsvd_bits);
5413 WARN_ON(1);
5414 }
5415
5416 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5417 u64 ept_mem_type = (spte & 0x38) >> 3;
5418
5419 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5420 ept_mem_type == 7) {
5421 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5422 __func__, ept_mem_type);
5423 WARN_ON(1);
5424 }
5425 }
5426 }
5427 }
5428
5429 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5430 {
5431 u64 sptes[4];
5432 int nr_sptes, i, ret;
5433 gpa_t gpa;
5434
5435 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5436
5437 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5438 if (likely(ret == RET_MMIO_PF_EMULATE))
5439 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5440 EMULATE_DONE;
5441
5442 if (unlikely(ret == RET_MMIO_PF_INVALID))
5443 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5444
5445 if (unlikely(ret == RET_MMIO_PF_RETRY))
5446 return 1;
5447
5448 /* It is the real ept misconfig */
5449 printk(KERN_ERR "EPT: Misconfiguration.\n");
5450 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5451
5452 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5453
5454 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5455 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5456
5457 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5458 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5459
5460 return 0;
5461 }
5462
5463 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5464 {
5465 u32 cpu_based_vm_exec_control;
5466
5467 /* clear pending NMI */
5468 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5469 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5470 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5471 ++vcpu->stat.nmi_window_exits;
5472 kvm_make_request(KVM_REQ_EVENT, vcpu);
5473
5474 return 1;
5475 }
5476
5477 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5478 {
5479 struct vcpu_vmx *vmx = to_vmx(vcpu);
5480 enum emulation_result err = EMULATE_DONE;
5481 int ret = 1;
5482 u32 cpu_exec_ctrl;
5483 bool intr_window_requested;
5484 unsigned count = 130;
5485
5486 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5487 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5488
5489 while (!guest_state_valid(vcpu) && count-- != 0) {
5490 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5491 return handle_interrupt_window(&vmx->vcpu);
5492
5493 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5494 return 1;
5495
5496 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5497
5498 if (err == EMULATE_USER_EXIT) {
5499 ++vcpu->stat.mmio_exits;
5500 ret = 0;
5501 goto out;
5502 }
5503
5504 if (err != EMULATE_DONE) {
5505 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5506 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5507 vcpu->run->internal.ndata = 0;
5508 return 0;
5509 }
5510
5511 if (vcpu->arch.halt_request) {
5512 vcpu->arch.halt_request = 0;
5513 ret = kvm_emulate_halt(vcpu);
5514 goto out;
5515 }
5516
5517 if (signal_pending(current))
5518 goto out;
5519 if (need_resched())
5520 schedule();
5521 }
5522
5523 vmx->emulation_required = emulation_required(vcpu);
5524 out:
5525 return ret;
5526 }
5527
5528 /*
5529 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5530 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5531 */
5532 static int handle_pause(struct kvm_vcpu *vcpu)
5533 {
5534 skip_emulated_instruction(vcpu);
5535 kvm_vcpu_on_spin(vcpu);
5536
5537 return 1;
5538 }
5539
5540 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5541 {
5542 kvm_queue_exception(vcpu, UD_VECTOR);
5543 return 1;
5544 }
5545
5546 /*
5547 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5548 * We could reuse a single VMCS for all the L2 guests, but we also want the
5549 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5550 * allows keeping them loaded on the processor, and in the future will allow
5551 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5552 * every entry if they never change.
5553 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5554 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5555 *
5556 * The following functions allocate and free a vmcs02 in this pool.
5557 */
5558
5559 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5560 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5561 {
5562 struct vmcs02_list *item;
5563 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5564 if (item->vmptr == vmx->nested.current_vmptr) {
5565 list_move(&item->list, &vmx->nested.vmcs02_pool);
5566 return &item->vmcs02;
5567 }
5568
5569 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5570 /* Recycle the least recently used VMCS. */
5571 item = list_entry(vmx->nested.vmcs02_pool.prev,
5572 struct vmcs02_list, list);
5573 item->vmptr = vmx->nested.current_vmptr;
5574 list_move(&item->list, &vmx->nested.vmcs02_pool);
5575 return &item->vmcs02;
5576 }
5577
5578 /* Create a new VMCS */
5579 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5580 if (!item)
5581 return NULL;
5582 item->vmcs02.vmcs = alloc_vmcs();
5583 if (!item->vmcs02.vmcs) {
5584 kfree(item);
5585 return NULL;
5586 }
5587 loaded_vmcs_init(&item->vmcs02);
5588 item->vmptr = vmx->nested.current_vmptr;
5589 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5590 vmx->nested.vmcs02_num++;
5591 return &item->vmcs02;
5592 }
5593
5594 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5595 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5596 {
5597 struct vmcs02_list *item;
5598 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5599 if (item->vmptr == vmptr) {
5600 free_loaded_vmcs(&item->vmcs02);
5601 list_del(&item->list);
5602 kfree(item);
5603 vmx->nested.vmcs02_num--;
5604 return;
5605 }
5606 }
5607
5608 /*
5609 * Free all VMCSs saved for this vcpu, except the one pointed by
5610 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5611 * currently used, if running L2), and vmcs01 when running L2.
5612 */
5613 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5614 {
5615 struct vmcs02_list *item, *n;
5616 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5617 if (vmx->loaded_vmcs != &item->vmcs02)
5618 free_loaded_vmcs(&item->vmcs02);
5619 list_del(&item->list);
5620 kfree(item);
5621 }
5622 vmx->nested.vmcs02_num = 0;
5623
5624 if (vmx->loaded_vmcs != &vmx->vmcs01)
5625 free_loaded_vmcs(&vmx->vmcs01);
5626 }
5627
5628 /*
5629 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5630 * set the success or error code of an emulated VMX instruction, as specified
5631 * by Vol 2B, VMX Instruction Reference, "Conventions".
5632 */
5633 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5634 {
5635 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5636 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5637 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5638 }
5639
5640 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5641 {
5642 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5643 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5644 X86_EFLAGS_SF | X86_EFLAGS_OF))
5645 | X86_EFLAGS_CF);
5646 }
5647
5648 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5649 u32 vm_instruction_error)
5650 {
5651 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5652 /*
5653 * failValid writes the error number to the current VMCS, which
5654 * can't be done there isn't a current VMCS.
5655 */
5656 nested_vmx_failInvalid(vcpu);
5657 return;
5658 }
5659 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5660 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5661 X86_EFLAGS_SF | X86_EFLAGS_OF))
5662 | X86_EFLAGS_ZF);
5663 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5664 /*
5665 * We don't need to force a shadow sync because
5666 * VM_INSTRUCTION_ERROR is not shadowed
5667 */
5668 }
5669
5670 /*
5671 * Emulate the VMXON instruction.
5672 * Currently, we just remember that VMX is active, and do not save or even
5673 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5674 * do not currently need to store anything in that guest-allocated memory
5675 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5676 * argument is different from the VMXON pointer (which the spec says they do).
5677 */
5678 static int handle_vmon(struct kvm_vcpu *vcpu)
5679 {
5680 struct kvm_segment cs;
5681 struct vcpu_vmx *vmx = to_vmx(vcpu);
5682 struct vmcs *shadow_vmcs;
5683 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5684 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5685
5686 /* The Intel VMX Instruction Reference lists a bunch of bits that
5687 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5688 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5689 * Otherwise, we should fail with #UD. We test these now:
5690 */
5691 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5692 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5693 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5694 kvm_queue_exception(vcpu, UD_VECTOR);
5695 return 1;
5696 }
5697
5698 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5699 if (is_long_mode(vcpu) && !cs.l) {
5700 kvm_queue_exception(vcpu, UD_VECTOR);
5701 return 1;
5702 }
5703
5704 if (vmx_get_cpl(vcpu)) {
5705 kvm_inject_gp(vcpu, 0);
5706 return 1;
5707 }
5708 if (vmx->nested.vmxon) {
5709 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5710 skip_emulated_instruction(vcpu);
5711 return 1;
5712 }
5713
5714 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5715 != VMXON_NEEDED_FEATURES) {
5716 kvm_inject_gp(vcpu, 0);
5717 return 1;
5718 }
5719
5720 if (enable_shadow_vmcs) {
5721 shadow_vmcs = alloc_vmcs();
5722 if (!shadow_vmcs)
5723 return -ENOMEM;
5724 /* mark vmcs as shadow */
5725 shadow_vmcs->revision_id |= (1u << 31);
5726 /* init shadow vmcs */
5727 vmcs_clear(shadow_vmcs);
5728 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5729 }
5730
5731 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5732 vmx->nested.vmcs02_num = 0;
5733
5734 vmx->nested.vmxon = true;
5735
5736 skip_emulated_instruction(vcpu);
5737 nested_vmx_succeed(vcpu);
5738 return 1;
5739 }
5740
5741 /*
5742 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5743 * for running VMX instructions (except VMXON, whose prerequisites are
5744 * slightly different). It also specifies what exception to inject otherwise.
5745 */
5746 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5747 {
5748 struct kvm_segment cs;
5749 struct vcpu_vmx *vmx = to_vmx(vcpu);
5750
5751 if (!vmx->nested.vmxon) {
5752 kvm_queue_exception(vcpu, UD_VECTOR);
5753 return 0;
5754 }
5755
5756 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5757 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5758 (is_long_mode(vcpu) && !cs.l)) {
5759 kvm_queue_exception(vcpu, UD_VECTOR);
5760 return 0;
5761 }
5762
5763 if (vmx_get_cpl(vcpu)) {
5764 kvm_inject_gp(vcpu, 0);
5765 return 0;
5766 }
5767
5768 return 1;
5769 }
5770
5771 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5772 {
5773 u32 exec_control;
5774 if (enable_shadow_vmcs) {
5775 if (vmx->nested.current_vmcs12 != NULL) {
5776 /* copy to memory all shadowed fields in case
5777 they were modified */
5778 copy_shadow_to_vmcs12(vmx);
5779 vmx->nested.sync_shadow_vmcs = false;
5780 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5781 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5782 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5783 vmcs_write64(VMCS_LINK_POINTER, -1ull);
5784 }
5785 }
5786 kunmap(vmx->nested.current_vmcs12_page);
5787 nested_release_page(vmx->nested.current_vmcs12_page);
5788 }
5789
5790 /*
5791 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5792 * just stops using VMX.
5793 */
5794 static void free_nested(struct vcpu_vmx *vmx)
5795 {
5796 if (!vmx->nested.vmxon)
5797 return;
5798 vmx->nested.vmxon = false;
5799 if (vmx->nested.current_vmptr != -1ull) {
5800 nested_release_vmcs12(vmx);
5801 vmx->nested.current_vmptr = -1ull;
5802 vmx->nested.current_vmcs12 = NULL;
5803 }
5804 if (enable_shadow_vmcs)
5805 free_vmcs(vmx->nested.current_shadow_vmcs);
5806 /* Unpin physical memory we referred to in current vmcs02 */
5807 if (vmx->nested.apic_access_page) {
5808 nested_release_page(vmx->nested.apic_access_page);
5809 vmx->nested.apic_access_page = 0;
5810 }
5811
5812 nested_free_all_saved_vmcss(vmx);
5813 }
5814
5815 /* Emulate the VMXOFF instruction */
5816 static int handle_vmoff(struct kvm_vcpu *vcpu)
5817 {
5818 if (!nested_vmx_check_permission(vcpu))
5819 return 1;
5820 free_nested(to_vmx(vcpu));
5821 skip_emulated_instruction(vcpu);
5822 nested_vmx_succeed(vcpu);
5823 return 1;
5824 }
5825
5826 /*
5827 * Decode the memory-address operand of a vmx instruction, as recorded on an
5828 * exit caused by such an instruction (run by a guest hypervisor).
5829 * On success, returns 0. When the operand is invalid, returns 1 and throws
5830 * #UD or #GP.
5831 */
5832 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5833 unsigned long exit_qualification,
5834 u32 vmx_instruction_info, gva_t *ret)
5835 {
5836 /*
5837 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5838 * Execution", on an exit, vmx_instruction_info holds most of the
5839 * addressing components of the operand. Only the displacement part
5840 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5841 * For how an actual address is calculated from all these components,
5842 * refer to Vol. 1, "Operand Addressing".
5843 */
5844 int scaling = vmx_instruction_info & 3;
5845 int addr_size = (vmx_instruction_info >> 7) & 7;
5846 bool is_reg = vmx_instruction_info & (1u << 10);
5847 int seg_reg = (vmx_instruction_info >> 15) & 7;
5848 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5849 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5850 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5851 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5852
5853 if (is_reg) {
5854 kvm_queue_exception(vcpu, UD_VECTOR);
5855 return 1;
5856 }
5857
5858 /* Addr = segment_base + offset */
5859 /* offset = base + [index * scale] + displacement */
5860 *ret = vmx_get_segment_base(vcpu, seg_reg);
5861 if (base_is_valid)
5862 *ret += kvm_register_read(vcpu, base_reg);
5863 if (index_is_valid)
5864 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5865 *ret += exit_qualification; /* holds the displacement */
5866
5867 if (addr_size == 1) /* 32 bit */
5868 *ret &= 0xffffffff;
5869
5870 /*
5871 * TODO: throw #GP (and return 1) in various cases that the VM*
5872 * instructions require it - e.g., offset beyond segment limit,
5873 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5874 * address, and so on. Currently these are not checked.
5875 */
5876 return 0;
5877 }
5878
5879 /* Emulate the VMCLEAR instruction */
5880 static int handle_vmclear(struct kvm_vcpu *vcpu)
5881 {
5882 struct vcpu_vmx *vmx = to_vmx(vcpu);
5883 gva_t gva;
5884 gpa_t vmptr;
5885 struct vmcs12 *vmcs12;
5886 struct page *page;
5887 struct x86_exception e;
5888
5889 if (!nested_vmx_check_permission(vcpu))
5890 return 1;
5891
5892 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5893 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5894 return 1;
5895
5896 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5897 sizeof(vmptr), &e)) {
5898 kvm_inject_page_fault(vcpu, &e);
5899 return 1;
5900 }
5901
5902 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5903 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5904 skip_emulated_instruction(vcpu);
5905 return 1;
5906 }
5907
5908 if (vmptr == vmx->nested.current_vmptr) {
5909 nested_release_vmcs12(vmx);
5910 vmx->nested.current_vmptr = -1ull;
5911 vmx->nested.current_vmcs12 = NULL;
5912 }
5913
5914 page = nested_get_page(vcpu, vmptr);
5915 if (page == NULL) {
5916 /*
5917 * For accurate processor emulation, VMCLEAR beyond available
5918 * physical memory should do nothing at all. However, it is
5919 * possible that a nested vmx bug, not a guest hypervisor bug,
5920 * resulted in this case, so let's shut down before doing any
5921 * more damage:
5922 */
5923 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5924 return 1;
5925 }
5926 vmcs12 = kmap(page);
5927 vmcs12->launch_state = 0;
5928 kunmap(page);
5929 nested_release_page(page);
5930
5931 nested_free_vmcs02(vmx, vmptr);
5932
5933 skip_emulated_instruction(vcpu);
5934 nested_vmx_succeed(vcpu);
5935 return 1;
5936 }
5937
5938 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5939
5940 /* Emulate the VMLAUNCH instruction */
5941 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5942 {
5943 return nested_vmx_run(vcpu, true);
5944 }
5945
5946 /* Emulate the VMRESUME instruction */
5947 static int handle_vmresume(struct kvm_vcpu *vcpu)
5948 {
5949
5950 return nested_vmx_run(vcpu, false);
5951 }
5952
5953 enum vmcs_field_type {
5954 VMCS_FIELD_TYPE_U16 = 0,
5955 VMCS_FIELD_TYPE_U64 = 1,
5956 VMCS_FIELD_TYPE_U32 = 2,
5957 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5958 };
5959
5960 static inline int vmcs_field_type(unsigned long field)
5961 {
5962 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5963 return VMCS_FIELD_TYPE_U32;
5964 return (field >> 13) & 0x3 ;
5965 }
5966
5967 static inline int vmcs_field_readonly(unsigned long field)
5968 {
5969 return (((field >> 10) & 0x3) == 1);
5970 }
5971
5972 /*
5973 * Read a vmcs12 field. Since these can have varying lengths and we return
5974 * one type, we chose the biggest type (u64) and zero-extend the return value
5975 * to that size. Note that the caller, handle_vmread, might need to use only
5976 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5977 * 64-bit fields are to be returned).
5978 */
5979 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5980 unsigned long field, u64 *ret)
5981 {
5982 short offset = vmcs_field_to_offset(field);
5983 char *p;
5984
5985 if (offset < 0)
5986 return 0;
5987
5988 p = ((char *)(get_vmcs12(vcpu))) + offset;
5989
5990 switch (vmcs_field_type(field)) {
5991 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5992 *ret = *((natural_width *)p);
5993 return 1;
5994 case VMCS_FIELD_TYPE_U16:
5995 *ret = *((u16 *)p);
5996 return 1;
5997 case VMCS_FIELD_TYPE_U32:
5998 *ret = *((u32 *)p);
5999 return 1;
6000 case VMCS_FIELD_TYPE_U64:
6001 *ret = *((u64 *)p);
6002 return 1;
6003 default:
6004 return 0; /* can never happen. */
6005 }
6006 }
6007
6008
6009 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6010 unsigned long field, u64 field_value){
6011 short offset = vmcs_field_to_offset(field);
6012 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6013 if (offset < 0)
6014 return false;
6015
6016 switch (vmcs_field_type(field)) {
6017 case VMCS_FIELD_TYPE_U16:
6018 *(u16 *)p = field_value;
6019 return true;
6020 case VMCS_FIELD_TYPE_U32:
6021 *(u32 *)p = field_value;
6022 return true;
6023 case VMCS_FIELD_TYPE_U64:
6024 *(u64 *)p = field_value;
6025 return true;
6026 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6027 *(natural_width *)p = field_value;
6028 return true;
6029 default:
6030 return false; /* can never happen. */
6031 }
6032
6033 }
6034
6035 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6036 {
6037 int i;
6038 unsigned long field;
6039 u64 field_value;
6040 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6041 const unsigned long *fields = shadow_read_write_fields;
6042 const int num_fields = max_shadow_read_write_fields;
6043
6044 vmcs_load(shadow_vmcs);
6045
6046 for (i = 0; i < num_fields; i++) {
6047 field = fields[i];
6048 switch (vmcs_field_type(field)) {
6049 case VMCS_FIELD_TYPE_U16:
6050 field_value = vmcs_read16(field);
6051 break;
6052 case VMCS_FIELD_TYPE_U32:
6053 field_value = vmcs_read32(field);
6054 break;
6055 case VMCS_FIELD_TYPE_U64:
6056 field_value = vmcs_read64(field);
6057 break;
6058 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6059 field_value = vmcs_readl(field);
6060 break;
6061 }
6062 vmcs12_write_any(&vmx->vcpu, field, field_value);
6063 }
6064
6065 vmcs_clear(shadow_vmcs);
6066 vmcs_load(vmx->loaded_vmcs->vmcs);
6067 }
6068
6069 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6070 {
6071 const unsigned long *fields[] = {
6072 shadow_read_write_fields,
6073 shadow_read_only_fields
6074 };
6075 const int max_fields[] = {
6076 max_shadow_read_write_fields,
6077 max_shadow_read_only_fields
6078 };
6079 int i, q;
6080 unsigned long field;
6081 u64 field_value = 0;
6082 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6083
6084 vmcs_load(shadow_vmcs);
6085
6086 for (q = 0; q < ARRAY_SIZE(fields); q++) {
6087 for (i = 0; i < max_fields[q]; i++) {
6088 field = fields[q][i];
6089 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6090
6091 switch (vmcs_field_type(field)) {
6092 case VMCS_FIELD_TYPE_U16:
6093 vmcs_write16(field, (u16)field_value);
6094 break;
6095 case VMCS_FIELD_TYPE_U32:
6096 vmcs_write32(field, (u32)field_value);
6097 break;
6098 case VMCS_FIELD_TYPE_U64:
6099 vmcs_write64(field, (u64)field_value);
6100 break;
6101 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6102 vmcs_writel(field, (long)field_value);
6103 break;
6104 }
6105 }
6106 }
6107
6108 vmcs_clear(shadow_vmcs);
6109 vmcs_load(vmx->loaded_vmcs->vmcs);
6110 }
6111
6112 /*
6113 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6114 * used before) all generate the same failure when it is missing.
6115 */
6116 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6117 {
6118 struct vcpu_vmx *vmx = to_vmx(vcpu);
6119 if (vmx->nested.current_vmptr == -1ull) {
6120 nested_vmx_failInvalid(vcpu);
6121 skip_emulated_instruction(vcpu);
6122 return 0;
6123 }
6124 return 1;
6125 }
6126
6127 static int handle_vmread(struct kvm_vcpu *vcpu)
6128 {
6129 unsigned long field;
6130 u64 field_value;
6131 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6132 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6133 gva_t gva = 0;
6134
6135 if (!nested_vmx_check_permission(vcpu) ||
6136 !nested_vmx_check_vmcs12(vcpu))
6137 return 1;
6138
6139 /* Decode instruction info and find the field to read */
6140 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6141 /* Read the field, zero-extended to a u64 field_value */
6142 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6143 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6144 skip_emulated_instruction(vcpu);
6145 return 1;
6146 }
6147 /*
6148 * Now copy part of this value to register or memory, as requested.
6149 * Note that the number of bits actually copied is 32 or 64 depending
6150 * on the guest's mode (32 or 64 bit), not on the given field's length.
6151 */
6152 if (vmx_instruction_info & (1u << 10)) {
6153 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6154 field_value);
6155 } else {
6156 if (get_vmx_mem_address(vcpu, exit_qualification,
6157 vmx_instruction_info, &gva))
6158 return 1;
6159 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6160 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6161 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6162 }
6163
6164 nested_vmx_succeed(vcpu);
6165 skip_emulated_instruction(vcpu);
6166 return 1;
6167 }
6168
6169
6170 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6171 {
6172 unsigned long field;
6173 gva_t gva;
6174 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6175 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6176 /* The value to write might be 32 or 64 bits, depending on L1's long
6177 * mode, and eventually we need to write that into a field of several
6178 * possible lengths. The code below first zero-extends the value to 64
6179 * bit (field_value), and then copies only the approriate number of
6180 * bits into the vmcs12 field.
6181 */
6182 u64 field_value = 0;
6183 struct x86_exception e;
6184
6185 if (!nested_vmx_check_permission(vcpu) ||
6186 !nested_vmx_check_vmcs12(vcpu))
6187 return 1;
6188
6189 if (vmx_instruction_info & (1u << 10))
6190 field_value = kvm_register_read(vcpu,
6191 (((vmx_instruction_info) >> 3) & 0xf));
6192 else {
6193 if (get_vmx_mem_address(vcpu, exit_qualification,
6194 vmx_instruction_info, &gva))
6195 return 1;
6196 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6197 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6198 kvm_inject_page_fault(vcpu, &e);
6199 return 1;
6200 }
6201 }
6202
6203
6204 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6205 if (vmcs_field_readonly(field)) {
6206 nested_vmx_failValid(vcpu,
6207 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6208 skip_emulated_instruction(vcpu);
6209 return 1;
6210 }
6211
6212 if (!vmcs12_write_any(vcpu, field, field_value)) {
6213 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6214 skip_emulated_instruction(vcpu);
6215 return 1;
6216 }
6217
6218 nested_vmx_succeed(vcpu);
6219 skip_emulated_instruction(vcpu);
6220 return 1;
6221 }
6222
6223 /* Emulate the VMPTRLD instruction */
6224 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6225 {
6226 struct vcpu_vmx *vmx = to_vmx(vcpu);
6227 gva_t gva;
6228 gpa_t vmptr;
6229 struct x86_exception e;
6230 u32 exec_control;
6231
6232 if (!nested_vmx_check_permission(vcpu))
6233 return 1;
6234
6235 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6236 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6237 return 1;
6238
6239 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6240 sizeof(vmptr), &e)) {
6241 kvm_inject_page_fault(vcpu, &e);
6242 return 1;
6243 }
6244
6245 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6246 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6247 skip_emulated_instruction(vcpu);
6248 return 1;
6249 }
6250
6251 if (vmx->nested.current_vmptr != vmptr) {
6252 struct vmcs12 *new_vmcs12;
6253 struct page *page;
6254 page = nested_get_page(vcpu, vmptr);
6255 if (page == NULL) {
6256 nested_vmx_failInvalid(vcpu);
6257 skip_emulated_instruction(vcpu);
6258 return 1;
6259 }
6260 new_vmcs12 = kmap(page);
6261 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6262 kunmap(page);
6263 nested_release_page_clean(page);
6264 nested_vmx_failValid(vcpu,
6265 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6266 skip_emulated_instruction(vcpu);
6267 return 1;
6268 }
6269 if (vmx->nested.current_vmptr != -1ull)
6270 nested_release_vmcs12(vmx);
6271
6272 vmx->nested.current_vmptr = vmptr;
6273 vmx->nested.current_vmcs12 = new_vmcs12;
6274 vmx->nested.current_vmcs12_page = page;
6275 if (enable_shadow_vmcs) {
6276 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6277 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6278 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6279 vmcs_write64(VMCS_LINK_POINTER,
6280 __pa(vmx->nested.current_shadow_vmcs));
6281 vmx->nested.sync_shadow_vmcs = true;
6282 }
6283 }
6284
6285 nested_vmx_succeed(vcpu);
6286 skip_emulated_instruction(vcpu);
6287 return 1;
6288 }
6289
6290 /* Emulate the VMPTRST instruction */
6291 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6292 {
6293 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6294 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6295 gva_t vmcs_gva;
6296 struct x86_exception e;
6297
6298 if (!nested_vmx_check_permission(vcpu))
6299 return 1;
6300
6301 if (get_vmx_mem_address(vcpu, exit_qualification,
6302 vmx_instruction_info, &vmcs_gva))
6303 return 1;
6304 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6305 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6306 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6307 sizeof(u64), &e)) {
6308 kvm_inject_page_fault(vcpu, &e);
6309 return 1;
6310 }
6311 nested_vmx_succeed(vcpu);
6312 skip_emulated_instruction(vcpu);
6313 return 1;
6314 }
6315
6316 /* Emulate the INVEPT instruction */
6317 static int handle_invept(struct kvm_vcpu *vcpu)
6318 {
6319 u32 vmx_instruction_info, types;
6320 unsigned long type;
6321 gva_t gva;
6322 struct x86_exception e;
6323 struct {
6324 u64 eptp, gpa;
6325 } operand;
6326 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6327
6328 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6329 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6330 kvm_queue_exception(vcpu, UD_VECTOR);
6331 return 1;
6332 }
6333
6334 if (!nested_vmx_check_permission(vcpu))
6335 return 1;
6336
6337 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6338 kvm_queue_exception(vcpu, UD_VECTOR);
6339 return 1;
6340 }
6341
6342 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6343 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6344
6345 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6346
6347 if (!(types & (1UL << type))) {
6348 nested_vmx_failValid(vcpu,
6349 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6350 return 1;
6351 }
6352
6353 /* According to the Intel VMX instruction reference, the memory
6354 * operand is read even if it isn't needed (e.g., for type==global)
6355 */
6356 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6357 vmx_instruction_info, &gva))
6358 return 1;
6359 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6360 sizeof(operand), &e)) {
6361 kvm_inject_page_fault(vcpu, &e);
6362 return 1;
6363 }
6364
6365 switch (type) {
6366 case VMX_EPT_EXTENT_CONTEXT:
6367 if ((operand.eptp & eptp_mask) !=
6368 (nested_ept_get_cr3(vcpu) & eptp_mask))
6369 break;
6370 case VMX_EPT_EXTENT_GLOBAL:
6371 kvm_mmu_sync_roots(vcpu);
6372 kvm_mmu_flush_tlb(vcpu);
6373 nested_vmx_succeed(vcpu);
6374 break;
6375 default:
6376 BUG_ON(1);
6377 break;
6378 }
6379
6380 skip_emulated_instruction(vcpu);
6381 return 1;
6382 }
6383
6384 /*
6385 * The exit handlers return 1 if the exit was handled fully and guest execution
6386 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6387 * to be done to userspace and return 0.
6388 */
6389 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6390 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6391 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
6392 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6393 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6394 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6395 [EXIT_REASON_CR_ACCESS] = handle_cr,
6396 [EXIT_REASON_DR_ACCESS] = handle_dr,
6397 [EXIT_REASON_CPUID] = handle_cpuid,
6398 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6399 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6400 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6401 [EXIT_REASON_HLT] = handle_halt,
6402 [EXIT_REASON_INVD] = handle_invd,
6403 [EXIT_REASON_INVLPG] = handle_invlpg,
6404 [EXIT_REASON_RDPMC] = handle_rdpmc,
6405 [EXIT_REASON_VMCALL] = handle_vmcall,
6406 [EXIT_REASON_VMCLEAR] = handle_vmclear,
6407 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
6408 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6409 [EXIT_REASON_VMPTRST] = handle_vmptrst,
6410 [EXIT_REASON_VMREAD] = handle_vmread,
6411 [EXIT_REASON_VMRESUME] = handle_vmresume,
6412 [EXIT_REASON_VMWRITE] = handle_vmwrite,
6413 [EXIT_REASON_VMOFF] = handle_vmoff,
6414 [EXIT_REASON_VMON] = handle_vmon,
6415 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6416 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
6417 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
6418 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
6419 [EXIT_REASON_WBINVD] = handle_wbinvd,
6420 [EXIT_REASON_XSETBV] = handle_xsetbv,
6421 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
6422 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
6423 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6424 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
6425 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
6426 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6427 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6428 [EXIT_REASON_INVEPT] = handle_invept,
6429 };
6430
6431 static const int kvm_vmx_max_exit_handlers =
6432 ARRAY_SIZE(kvm_vmx_exit_handlers);
6433
6434 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6435 struct vmcs12 *vmcs12)
6436 {
6437 unsigned long exit_qualification;
6438 gpa_t bitmap, last_bitmap;
6439 unsigned int port;
6440 int size;
6441 u8 b;
6442
6443 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6444 return 1;
6445
6446 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6447 return 0;
6448
6449 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6450
6451 port = exit_qualification >> 16;
6452 size = (exit_qualification & 7) + 1;
6453
6454 last_bitmap = (gpa_t)-1;
6455 b = -1;
6456
6457 while (size > 0) {
6458 if (port < 0x8000)
6459 bitmap = vmcs12->io_bitmap_a;
6460 else if (port < 0x10000)
6461 bitmap = vmcs12->io_bitmap_b;
6462 else
6463 return 1;
6464 bitmap += (port & 0x7fff) / 8;
6465
6466 if (last_bitmap != bitmap)
6467 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6468 return 1;
6469 if (b & (1 << (port & 7)))
6470 return 1;
6471
6472 port++;
6473 size--;
6474 last_bitmap = bitmap;
6475 }
6476
6477 return 0;
6478 }
6479
6480 /*
6481 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6482 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6483 * disinterest in the current event (read or write a specific MSR) by using an
6484 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6485 */
6486 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6487 struct vmcs12 *vmcs12, u32 exit_reason)
6488 {
6489 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6490 gpa_t bitmap;
6491
6492 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6493 return 1;
6494
6495 /*
6496 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6497 * for the four combinations of read/write and low/high MSR numbers.
6498 * First we need to figure out which of the four to use:
6499 */
6500 bitmap = vmcs12->msr_bitmap;
6501 if (exit_reason == EXIT_REASON_MSR_WRITE)
6502 bitmap += 2048;
6503 if (msr_index >= 0xc0000000) {
6504 msr_index -= 0xc0000000;
6505 bitmap += 1024;
6506 }
6507
6508 /* Then read the msr_index'th bit from this bitmap: */
6509 if (msr_index < 1024*8) {
6510 unsigned char b;
6511 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6512 return 1;
6513 return 1 & (b >> (msr_index & 7));
6514 } else
6515 return 1; /* let L1 handle the wrong parameter */
6516 }
6517
6518 /*
6519 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6520 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6521 * intercept (via guest_host_mask etc.) the current event.
6522 */
6523 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6524 struct vmcs12 *vmcs12)
6525 {
6526 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6527 int cr = exit_qualification & 15;
6528 int reg = (exit_qualification >> 8) & 15;
6529 unsigned long val = kvm_register_read(vcpu, reg);
6530
6531 switch ((exit_qualification >> 4) & 3) {
6532 case 0: /* mov to cr */
6533 switch (cr) {
6534 case 0:
6535 if (vmcs12->cr0_guest_host_mask &
6536 (val ^ vmcs12->cr0_read_shadow))
6537 return 1;
6538 break;
6539 case 3:
6540 if ((vmcs12->cr3_target_count >= 1 &&
6541 vmcs12->cr3_target_value0 == val) ||
6542 (vmcs12->cr3_target_count >= 2 &&
6543 vmcs12->cr3_target_value1 == val) ||
6544 (vmcs12->cr3_target_count >= 3 &&
6545 vmcs12->cr3_target_value2 == val) ||
6546 (vmcs12->cr3_target_count >= 4 &&
6547 vmcs12->cr3_target_value3 == val))
6548 return 0;
6549 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6550 return 1;
6551 break;
6552 case 4:
6553 if (vmcs12->cr4_guest_host_mask &
6554 (vmcs12->cr4_read_shadow ^ val))
6555 return 1;
6556 break;
6557 case 8:
6558 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6559 return 1;
6560 break;
6561 }
6562 break;
6563 case 2: /* clts */
6564 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6565 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6566 return 1;
6567 break;
6568 case 1: /* mov from cr */
6569 switch (cr) {
6570 case 3:
6571 if (vmcs12->cpu_based_vm_exec_control &
6572 CPU_BASED_CR3_STORE_EXITING)
6573 return 1;
6574 break;
6575 case 8:
6576 if (vmcs12->cpu_based_vm_exec_control &
6577 CPU_BASED_CR8_STORE_EXITING)
6578 return 1;
6579 break;
6580 }
6581 break;
6582 case 3: /* lmsw */
6583 /*
6584 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6585 * cr0. Other attempted changes are ignored, with no exit.
6586 */
6587 if (vmcs12->cr0_guest_host_mask & 0xe &
6588 (val ^ vmcs12->cr0_read_shadow))
6589 return 1;
6590 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6591 !(vmcs12->cr0_read_shadow & 0x1) &&
6592 (val & 0x1))
6593 return 1;
6594 break;
6595 }
6596 return 0;
6597 }
6598
6599 /*
6600 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6601 * should handle it ourselves in L0 (and then continue L2). Only call this
6602 * when in is_guest_mode (L2).
6603 */
6604 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6605 {
6606 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6607 struct vcpu_vmx *vmx = to_vmx(vcpu);
6608 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6609 u32 exit_reason = vmx->exit_reason;
6610
6611 if (vmx->nested.nested_run_pending)
6612 return 0;
6613
6614 if (unlikely(vmx->fail)) {
6615 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6616 vmcs_read32(VM_INSTRUCTION_ERROR));
6617 return 1;
6618 }
6619
6620 switch (exit_reason) {
6621 case EXIT_REASON_EXCEPTION_NMI:
6622 if (!is_exception(intr_info))
6623 return 0;
6624 else if (is_page_fault(intr_info))
6625 return enable_ept;
6626 return vmcs12->exception_bitmap &
6627 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6628 case EXIT_REASON_EXTERNAL_INTERRUPT:
6629 return 0;
6630 case EXIT_REASON_TRIPLE_FAULT:
6631 return 1;
6632 case EXIT_REASON_PENDING_INTERRUPT:
6633 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6634 case EXIT_REASON_NMI_WINDOW:
6635 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6636 case EXIT_REASON_TASK_SWITCH:
6637 return 1;
6638 case EXIT_REASON_CPUID:
6639 return 1;
6640 case EXIT_REASON_HLT:
6641 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6642 case EXIT_REASON_INVD:
6643 return 1;
6644 case EXIT_REASON_INVLPG:
6645 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6646 case EXIT_REASON_RDPMC:
6647 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6648 case EXIT_REASON_RDTSC:
6649 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6650 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6651 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6652 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6653 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6654 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6655 case EXIT_REASON_INVEPT:
6656 /*
6657 * VMX instructions trap unconditionally. This allows L1 to
6658 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6659 */
6660 return 1;
6661 case EXIT_REASON_CR_ACCESS:
6662 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6663 case EXIT_REASON_DR_ACCESS:
6664 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6665 case EXIT_REASON_IO_INSTRUCTION:
6666 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6667 case EXIT_REASON_MSR_READ:
6668 case EXIT_REASON_MSR_WRITE:
6669 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6670 case EXIT_REASON_INVALID_STATE:
6671 return 1;
6672 case EXIT_REASON_MWAIT_INSTRUCTION:
6673 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6674 case EXIT_REASON_MONITOR_INSTRUCTION:
6675 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6676 case EXIT_REASON_PAUSE_INSTRUCTION:
6677 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6678 nested_cpu_has2(vmcs12,
6679 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6680 case EXIT_REASON_MCE_DURING_VMENTRY:
6681 return 0;
6682 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6683 return 1;
6684 case EXIT_REASON_APIC_ACCESS:
6685 return nested_cpu_has2(vmcs12,
6686 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6687 case EXIT_REASON_EPT_VIOLATION:
6688 /*
6689 * L0 always deals with the EPT violation. If nested EPT is
6690 * used, and the nested mmu code discovers that the address is
6691 * missing in the guest EPT table (EPT12), the EPT violation
6692 * will be injected with nested_ept_inject_page_fault()
6693 */
6694 return 0;
6695 case EXIT_REASON_EPT_MISCONFIG:
6696 /*
6697 * L2 never uses directly L1's EPT, but rather L0's own EPT
6698 * table (shadow on EPT) or a merged EPT table that L0 built
6699 * (EPT on EPT). So any problems with the structure of the
6700 * table is L0's fault.
6701 */
6702 return 0;
6703 case EXIT_REASON_PREEMPTION_TIMER:
6704 return vmcs12->pin_based_vm_exec_control &
6705 PIN_BASED_VMX_PREEMPTION_TIMER;
6706 case EXIT_REASON_WBINVD:
6707 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6708 case EXIT_REASON_XSETBV:
6709 return 1;
6710 default:
6711 return 1;
6712 }
6713 }
6714
6715 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6716 {
6717 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6718 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6719 }
6720
6721 /*
6722 * The guest has exited. See if we can fix it or if we need userspace
6723 * assistance.
6724 */
6725 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6726 {
6727 struct vcpu_vmx *vmx = to_vmx(vcpu);
6728 u32 exit_reason = vmx->exit_reason;
6729 u32 vectoring_info = vmx->idt_vectoring_info;
6730
6731 /* If guest state is invalid, start emulating */
6732 if (vmx->emulation_required)
6733 return handle_invalid_guest_state(vcpu);
6734
6735 /*
6736 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6737 * we did not inject a still-pending event to L1 now because of
6738 * nested_run_pending, we need to re-enable this bit.
6739 */
6740 if (vmx->nested.nested_run_pending)
6741 kvm_make_request(KVM_REQ_EVENT, vcpu);
6742
6743 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6744 exit_reason == EXIT_REASON_VMRESUME))
6745 vmx->nested.nested_run_pending = 1;
6746 else
6747 vmx->nested.nested_run_pending = 0;
6748
6749 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6750 nested_vmx_vmexit(vcpu);
6751 return 1;
6752 }
6753
6754 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6755 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6756 vcpu->run->fail_entry.hardware_entry_failure_reason
6757 = exit_reason;
6758 return 0;
6759 }
6760
6761 if (unlikely(vmx->fail)) {
6762 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6763 vcpu->run->fail_entry.hardware_entry_failure_reason
6764 = vmcs_read32(VM_INSTRUCTION_ERROR);
6765 return 0;
6766 }
6767
6768 /*
6769 * Note:
6770 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6771 * delivery event since it indicates guest is accessing MMIO.
6772 * The vm-exit can be triggered again after return to guest that
6773 * will cause infinite loop.
6774 */
6775 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6776 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6777 exit_reason != EXIT_REASON_EPT_VIOLATION &&
6778 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6779 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6780 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6781 vcpu->run->internal.ndata = 2;
6782 vcpu->run->internal.data[0] = vectoring_info;
6783 vcpu->run->internal.data[1] = exit_reason;
6784 return 0;
6785 }
6786
6787 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6788 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6789 get_vmcs12(vcpu))))) {
6790 if (vmx_interrupt_allowed(vcpu)) {
6791 vmx->soft_vnmi_blocked = 0;
6792 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6793 vcpu->arch.nmi_pending) {
6794 /*
6795 * This CPU don't support us in finding the end of an
6796 * NMI-blocked window if the guest runs with IRQs
6797 * disabled. So we pull the trigger after 1 s of
6798 * futile waiting, but inform the user about this.
6799 */
6800 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6801 "state on VCPU %d after 1 s timeout\n",
6802 __func__, vcpu->vcpu_id);
6803 vmx->soft_vnmi_blocked = 0;
6804 }
6805 }
6806
6807 if (exit_reason < kvm_vmx_max_exit_handlers
6808 && kvm_vmx_exit_handlers[exit_reason])
6809 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6810 else {
6811 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6812 vcpu->run->hw.hardware_exit_reason = exit_reason;
6813 }
6814 return 0;
6815 }
6816
6817 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6818 {
6819 if (irr == -1 || tpr < irr) {
6820 vmcs_write32(TPR_THRESHOLD, 0);
6821 return;
6822 }
6823
6824 vmcs_write32(TPR_THRESHOLD, irr);
6825 }
6826
6827 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6828 {
6829 u32 sec_exec_control;
6830
6831 /*
6832 * There is not point to enable virtualize x2apic without enable
6833 * apicv
6834 */
6835 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6836 !vmx_vm_has_apicv(vcpu->kvm))
6837 return;
6838
6839 if (!vm_need_tpr_shadow(vcpu->kvm))
6840 return;
6841
6842 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6843
6844 if (set) {
6845 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6846 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6847 } else {
6848 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6849 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6850 }
6851 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6852
6853 vmx_set_msr_bitmap(vcpu);
6854 }
6855
6856 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6857 {
6858 u16 status;
6859 u8 old;
6860
6861 if (!vmx_vm_has_apicv(kvm))
6862 return;
6863
6864 if (isr == -1)
6865 isr = 0;
6866
6867 status = vmcs_read16(GUEST_INTR_STATUS);
6868 old = status >> 8;
6869 if (isr != old) {
6870 status &= 0xff;
6871 status |= isr << 8;
6872 vmcs_write16(GUEST_INTR_STATUS, status);
6873 }
6874 }
6875
6876 static void vmx_set_rvi(int vector)
6877 {
6878 u16 status;
6879 u8 old;
6880
6881 status = vmcs_read16(GUEST_INTR_STATUS);
6882 old = (u8)status & 0xff;
6883 if ((u8)vector != old) {
6884 status &= ~0xff;
6885 status |= (u8)vector;
6886 vmcs_write16(GUEST_INTR_STATUS, status);
6887 }
6888 }
6889
6890 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6891 {
6892 if (max_irr == -1)
6893 return;
6894
6895 vmx_set_rvi(max_irr);
6896 }
6897
6898 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6899 {
6900 if (!vmx_vm_has_apicv(vcpu->kvm))
6901 return;
6902
6903 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6904 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6905 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6906 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6907 }
6908
6909 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6910 {
6911 u32 exit_intr_info;
6912
6913 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6914 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6915 return;
6916
6917 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6918 exit_intr_info = vmx->exit_intr_info;
6919
6920 /* Handle machine checks before interrupts are enabled */
6921 if (is_machine_check(exit_intr_info))
6922 kvm_machine_check();
6923
6924 /* We need to handle NMIs before interrupts are enabled */
6925 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6926 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6927 kvm_before_handle_nmi(&vmx->vcpu);
6928 asm("int $2");
6929 kvm_after_handle_nmi(&vmx->vcpu);
6930 }
6931 }
6932
6933 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6934 {
6935 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6936
6937 /*
6938 * If external interrupt exists, IF bit is set in rflags/eflags on the
6939 * interrupt stack frame, and interrupt will be enabled on a return
6940 * from interrupt handler.
6941 */
6942 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6943 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6944 unsigned int vector;
6945 unsigned long entry;
6946 gate_desc *desc;
6947 struct vcpu_vmx *vmx = to_vmx(vcpu);
6948 #ifdef CONFIG_X86_64
6949 unsigned long tmp;
6950 #endif
6951
6952 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6953 desc = (gate_desc *)vmx->host_idt_base + vector;
6954 entry = gate_offset(*desc);
6955 asm volatile(
6956 #ifdef CONFIG_X86_64
6957 "mov %%" _ASM_SP ", %[sp]\n\t"
6958 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6959 "push $%c[ss]\n\t"
6960 "push %[sp]\n\t"
6961 #endif
6962 "pushf\n\t"
6963 "orl $0x200, (%%" _ASM_SP ")\n\t"
6964 __ASM_SIZE(push) " $%c[cs]\n\t"
6965 "call *%[entry]\n\t"
6966 :
6967 #ifdef CONFIG_X86_64
6968 [sp]"=&r"(tmp)
6969 #endif
6970 :
6971 [entry]"r"(entry),
6972 [ss]"i"(__KERNEL_DS),
6973 [cs]"i"(__KERNEL_CS)
6974 );
6975 } else
6976 local_irq_enable();
6977 }
6978
6979 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6980 {
6981 u32 exit_intr_info;
6982 bool unblock_nmi;
6983 u8 vector;
6984 bool idtv_info_valid;
6985
6986 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6987
6988 if (cpu_has_virtual_nmis()) {
6989 if (vmx->nmi_known_unmasked)
6990 return;
6991 /*
6992 * Can't use vmx->exit_intr_info since we're not sure what
6993 * the exit reason is.
6994 */
6995 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6996 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6997 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6998 /*
6999 * SDM 3: 27.7.1.2 (September 2008)
7000 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7001 * a guest IRET fault.
7002 * SDM 3: 23.2.2 (September 2008)
7003 * Bit 12 is undefined in any of the following cases:
7004 * If the VM exit sets the valid bit in the IDT-vectoring
7005 * information field.
7006 * If the VM exit is due to a double fault.
7007 */
7008 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7009 vector != DF_VECTOR && !idtv_info_valid)
7010 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7011 GUEST_INTR_STATE_NMI);
7012 else
7013 vmx->nmi_known_unmasked =
7014 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7015 & GUEST_INTR_STATE_NMI);
7016 } else if (unlikely(vmx->soft_vnmi_blocked))
7017 vmx->vnmi_blocked_time +=
7018 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7019 }
7020
7021 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7022 u32 idt_vectoring_info,
7023 int instr_len_field,
7024 int error_code_field)
7025 {
7026 u8 vector;
7027 int type;
7028 bool idtv_info_valid;
7029
7030 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7031
7032 vcpu->arch.nmi_injected = false;
7033 kvm_clear_exception_queue(vcpu);
7034 kvm_clear_interrupt_queue(vcpu);
7035
7036 if (!idtv_info_valid)
7037 return;
7038
7039 kvm_make_request(KVM_REQ_EVENT, vcpu);
7040
7041 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7042 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7043
7044 switch (type) {
7045 case INTR_TYPE_NMI_INTR:
7046 vcpu->arch.nmi_injected = true;
7047 /*
7048 * SDM 3: 27.7.1.2 (September 2008)
7049 * Clear bit "block by NMI" before VM entry if a NMI
7050 * delivery faulted.
7051 */
7052 vmx_set_nmi_mask(vcpu, false);
7053 break;
7054 case INTR_TYPE_SOFT_EXCEPTION:
7055 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7056 /* fall through */
7057 case INTR_TYPE_HARD_EXCEPTION:
7058 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7059 u32 err = vmcs_read32(error_code_field);
7060 kvm_queue_exception_e(vcpu, vector, err);
7061 } else
7062 kvm_queue_exception(vcpu, vector);
7063 break;
7064 case INTR_TYPE_SOFT_INTR:
7065 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7066 /* fall through */
7067 case INTR_TYPE_EXT_INTR:
7068 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7069 break;
7070 default:
7071 break;
7072 }
7073 }
7074
7075 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7076 {
7077 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7078 VM_EXIT_INSTRUCTION_LEN,
7079 IDT_VECTORING_ERROR_CODE);
7080 }
7081
7082 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7083 {
7084 __vmx_complete_interrupts(vcpu,
7085 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7086 VM_ENTRY_INSTRUCTION_LEN,
7087 VM_ENTRY_EXCEPTION_ERROR_CODE);
7088
7089 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7090 }
7091
7092 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7093 {
7094 int i, nr_msrs;
7095 struct perf_guest_switch_msr *msrs;
7096
7097 msrs = perf_guest_get_msrs(&nr_msrs);
7098
7099 if (!msrs)
7100 return;
7101
7102 for (i = 0; i < nr_msrs; i++)
7103 if (msrs[i].host == msrs[i].guest)
7104 clear_atomic_switch_msr(vmx, msrs[i].msr);
7105 else
7106 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7107 msrs[i].host);
7108 }
7109
7110 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7111 {
7112 struct vcpu_vmx *vmx = to_vmx(vcpu);
7113 unsigned long debugctlmsr;
7114
7115 /* Record the guest's net vcpu time for enforced NMI injections. */
7116 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7117 vmx->entry_time = ktime_get();
7118
7119 /* Don't enter VMX if guest state is invalid, let the exit handler
7120 start emulation until we arrive back to a valid state */
7121 if (vmx->emulation_required)
7122 return;
7123
7124 if (vmx->nested.sync_shadow_vmcs) {
7125 copy_vmcs12_to_shadow(vmx);
7126 vmx->nested.sync_shadow_vmcs = false;
7127 }
7128
7129 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7130 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7131 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7132 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7133
7134 /* When single-stepping over STI and MOV SS, we must clear the
7135 * corresponding interruptibility bits in the guest state. Otherwise
7136 * vmentry fails as it then expects bit 14 (BS) in pending debug
7137 * exceptions being set, but that's not correct for the guest debugging
7138 * case. */
7139 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7140 vmx_set_interrupt_shadow(vcpu, 0);
7141
7142 atomic_switch_perf_msrs(vmx);
7143 debugctlmsr = get_debugctlmsr();
7144
7145 vmx->__launched = vmx->loaded_vmcs->launched;
7146 asm(
7147 /* Store host registers */
7148 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7149 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7150 "push %%" _ASM_CX " \n\t"
7151 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7152 "je 1f \n\t"
7153 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7154 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7155 "1: \n\t"
7156 /* Reload cr2 if changed */
7157 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7158 "mov %%cr2, %%" _ASM_DX " \n\t"
7159 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7160 "je 2f \n\t"
7161 "mov %%" _ASM_AX", %%cr2 \n\t"
7162 "2: \n\t"
7163 /* Check if vmlaunch of vmresume is needed */
7164 "cmpl $0, %c[launched](%0) \n\t"
7165 /* Load guest registers. Don't clobber flags. */
7166 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7167 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7168 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7169 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7170 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7171 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7172 #ifdef CONFIG_X86_64
7173 "mov %c[r8](%0), %%r8 \n\t"
7174 "mov %c[r9](%0), %%r9 \n\t"
7175 "mov %c[r10](%0), %%r10 \n\t"
7176 "mov %c[r11](%0), %%r11 \n\t"
7177 "mov %c[r12](%0), %%r12 \n\t"
7178 "mov %c[r13](%0), %%r13 \n\t"
7179 "mov %c[r14](%0), %%r14 \n\t"
7180 "mov %c[r15](%0), %%r15 \n\t"
7181 #endif
7182 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7183
7184 /* Enter guest mode */
7185 "jne 1f \n\t"
7186 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7187 "jmp 2f \n\t"
7188 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7189 "2: "
7190 /* Save guest registers, load host registers, keep flags */
7191 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7192 "pop %0 \n\t"
7193 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7194 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7195 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7196 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7197 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7198 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7199 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7200 #ifdef CONFIG_X86_64
7201 "mov %%r8, %c[r8](%0) \n\t"
7202 "mov %%r9, %c[r9](%0) \n\t"
7203 "mov %%r10, %c[r10](%0) \n\t"
7204 "mov %%r11, %c[r11](%0) \n\t"
7205 "mov %%r12, %c[r12](%0) \n\t"
7206 "mov %%r13, %c[r13](%0) \n\t"
7207 "mov %%r14, %c[r14](%0) \n\t"
7208 "mov %%r15, %c[r15](%0) \n\t"
7209 #endif
7210 "mov %%cr2, %%" _ASM_AX " \n\t"
7211 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7212
7213 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
7214 "setbe %c[fail](%0) \n\t"
7215 ".pushsection .rodata \n\t"
7216 ".global vmx_return \n\t"
7217 "vmx_return: " _ASM_PTR " 2b \n\t"
7218 ".popsection"
7219 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7220 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7221 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7222 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7223 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7224 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7225 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7226 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7227 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7228 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7229 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7230 #ifdef CONFIG_X86_64
7231 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7232 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7233 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7234 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7235 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7236 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7237 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7238 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7239 #endif
7240 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7241 [wordsize]"i"(sizeof(ulong))
7242 : "cc", "memory"
7243 #ifdef CONFIG_X86_64
7244 , "rax", "rbx", "rdi", "rsi"
7245 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7246 #else
7247 , "eax", "ebx", "edi", "esi"
7248 #endif
7249 );
7250
7251 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7252 if (debugctlmsr)
7253 update_debugctlmsr(debugctlmsr);
7254
7255 #ifndef CONFIG_X86_64
7256 /*
7257 * The sysexit path does not restore ds/es, so we must set them to
7258 * a reasonable value ourselves.
7259 *
7260 * We can't defer this to vmx_load_host_state() since that function
7261 * may be executed in interrupt context, which saves and restore segments
7262 * around it, nullifying its effect.
7263 */
7264 loadsegment(ds, __USER_DS);
7265 loadsegment(es, __USER_DS);
7266 #endif
7267
7268 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7269 | (1 << VCPU_EXREG_RFLAGS)
7270 | (1 << VCPU_EXREG_CPL)
7271 | (1 << VCPU_EXREG_PDPTR)
7272 | (1 << VCPU_EXREG_SEGMENTS)
7273 | (1 << VCPU_EXREG_CR3));
7274 vcpu->arch.regs_dirty = 0;
7275
7276 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7277
7278 vmx->loaded_vmcs->launched = 1;
7279
7280 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7281 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7282
7283 vmx_complete_atomic_exit(vmx);
7284 vmx_recover_nmi_blocking(vmx);
7285 vmx_complete_interrupts(vmx);
7286 }
7287
7288 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7289 {
7290 struct vcpu_vmx *vmx = to_vmx(vcpu);
7291
7292 free_vpid(vmx);
7293 free_nested(vmx);
7294 free_loaded_vmcs(vmx->loaded_vmcs);
7295 kfree(vmx->guest_msrs);
7296 kvm_vcpu_uninit(vcpu);
7297 kmem_cache_free(kvm_vcpu_cache, vmx);
7298 }
7299
7300 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7301 {
7302 int err;
7303 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7304 int cpu;
7305
7306 if (!vmx)
7307 return ERR_PTR(-ENOMEM);
7308
7309 allocate_vpid(vmx);
7310
7311 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7312 if (err)
7313 goto free_vcpu;
7314
7315 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7316 err = -ENOMEM;
7317 if (!vmx->guest_msrs) {
7318 goto uninit_vcpu;
7319 }
7320
7321 vmx->loaded_vmcs = &vmx->vmcs01;
7322 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7323 if (!vmx->loaded_vmcs->vmcs)
7324 goto free_msrs;
7325 if (!vmm_exclusive)
7326 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7327 loaded_vmcs_init(vmx->loaded_vmcs);
7328 if (!vmm_exclusive)
7329 kvm_cpu_vmxoff();
7330
7331 cpu = get_cpu();
7332 vmx_vcpu_load(&vmx->vcpu, cpu);
7333 vmx->vcpu.cpu = cpu;
7334 err = vmx_vcpu_setup(vmx);
7335 vmx_vcpu_put(&vmx->vcpu);
7336 put_cpu();
7337 if (err)
7338 goto free_vmcs;
7339 if (vm_need_virtualize_apic_accesses(kvm)) {
7340 err = alloc_apic_access_page(kvm);
7341 if (err)
7342 goto free_vmcs;
7343 }
7344
7345 if (enable_ept) {
7346 if (!kvm->arch.ept_identity_map_addr)
7347 kvm->arch.ept_identity_map_addr =
7348 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7349 err = -ENOMEM;
7350 if (alloc_identity_pagetable(kvm) != 0)
7351 goto free_vmcs;
7352 if (!init_rmode_identity_map(kvm))
7353 goto free_vmcs;
7354 }
7355
7356 vmx->nested.current_vmptr = -1ull;
7357 vmx->nested.current_vmcs12 = NULL;
7358
7359 return &vmx->vcpu;
7360
7361 free_vmcs:
7362 free_loaded_vmcs(vmx->loaded_vmcs);
7363 free_msrs:
7364 kfree(vmx->guest_msrs);
7365 uninit_vcpu:
7366 kvm_vcpu_uninit(&vmx->vcpu);
7367 free_vcpu:
7368 free_vpid(vmx);
7369 kmem_cache_free(kvm_vcpu_cache, vmx);
7370 return ERR_PTR(err);
7371 }
7372
7373 static void __init vmx_check_processor_compat(void *rtn)
7374 {
7375 struct vmcs_config vmcs_conf;
7376
7377 *(int *)rtn = 0;
7378 if (setup_vmcs_config(&vmcs_conf) < 0)
7379 *(int *)rtn = -EIO;
7380 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7381 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7382 smp_processor_id());
7383 *(int *)rtn = -EIO;
7384 }
7385 }
7386
7387 static int get_ept_level(void)
7388 {
7389 return VMX_EPT_DEFAULT_GAW + 1;
7390 }
7391
7392 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7393 {
7394 u64 ret;
7395
7396 /* For VT-d and EPT combination
7397 * 1. MMIO: always map as UC
7398 * 2. EPT with VT-d:
7399 * a. VT-d without snooping control feature: can't guarantee the
7400 * result, try to trust guest.
7401 * b. VT-d with snooping control feature: snooping control feature of
7402 * VT-d engine can guarantee the cache correctness. Just set it
7403 * to WB to keep consistent with host. So the same as item 3.
7404 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7405 * consistent with host MTRR
7406 */
7407 if (is_mmio)
7408 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7409 else if (vcpu->kvm->arch.iommu_domain &&
7410 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7411 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7412 VMX_EPT_MT_EPTE_SHIFT;
7413 else
7414 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7415 | VMX_EPT_IPAT_BIT;
7416
7417 return ret;
7418 }
7419
7420 static int vmx_get_lpage_level(void)
7421 {
7422 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7423 return PT_DIRECTORY_LEVEL;
7424 else
7425 /* For shadow and EPT supported 1GB page */
7426 return PT_PDPE_LEVEL;
7427 }
7428
7429 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7430 {
7431 struct kvm_cpuid_entry2 *best;
7432 struct vcpu_vmx *vmx = to_vmx(vcpu);
7433 u32 exec_control;
7434
7435 vmx->rdtscp_enabled = false;
7436 if (vmx_rdtscp_supported()) {
7437 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7438 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7439 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7440 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7441 vmx->rdtscp_enabled = true;
7442 else {
7443 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7444 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7445 exec_control);
7446 }
7447 }
7448 }
7449
7450 /* Exposing INVPCID only when PCID is exposed */
7451 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7452 if (vmx_invpcid_supported() &&
7453 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7454 guest_cpuid_has_pcid(vcpu)) {
7455 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7456 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7457 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7458 exec_control);
7459 } else {
7460 if (cpu_has_secondary_exec_ctrls()) {
7461 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7462 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7463 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7464 exec_control);
7465 }
7466 if (best)
7467 best->ebx &= ~bit(X86_FEATURE_INVPCID);
7468 }
7469 }
7470
7471 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7472 {
7473 if (func == 1 && nested)
7474 entry->ecx |= bit(X86_FEATURE_VMX);
7475 }
7476
7477 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7478 struct x86_exception *fault)
7479 {
7480 struct vmcs12 *vmcs12;
7481 nested_vmx_vmexit(vcpu);
7482 vmcs12 = get_vmcs12(vcpu);
7483
7484 if (fault->error_code & PFERR_RSVD_MASK)
7485 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7486 else
7487 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7488 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7489 vmcs12->guest_physical_address = fault->address;
7490 }
7491
7492 /* Callbacks for nested_ept_init_mmu_context: */
7493
7494 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7495 {
7496 /* return the page table to be shadowed - in our case, EPT12 */
7497 return get_vmcs12(vcpu)->ept_pointer;
7498 }
7499
7500 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7501 {
7502 int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7503 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7504
7505 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7506 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7507 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7508
7509 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
7510
7511 return r;
7512 }
7513
7514 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7515 {
7516 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7517 }
7518
7519 /*
7520 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7521 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7522 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7523 * guest in a way that will both be appropriate to L1's requests, and our
7524 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7525 * function also has additional necessary side-effects, like setting various
7526 * vcpu->arch fields.
7527 */
7528 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7529 {
7530 struct vcpu_vmx *vmx = to_vmx(vcpu);
7531 u32 exec_control;
7532
7533 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7534 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7535 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7536 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7537 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7538 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7539 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7540 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7541 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7542 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7543 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7544 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7545 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7546 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7547 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7548 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7549 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7550 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7551 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7552 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7553 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7554 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7555 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7556 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7557 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7558 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7559 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7560 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7561 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7562 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7563 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7564 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7565 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7566 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7567 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7568 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7569
7570 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7571 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7572 vmcs12->vm_entry_intr_info_field);
7573 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7574 vmcs12->vm_entry_exception_error_code);
7575 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7576 vmcs12->vm_entry_instruction_len);
7577 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7578 vmcs12->guest_interruptibility_info);
7579 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7580 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7581 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7582 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7583 vmcs12->guest_pending_dbg_exceptions);
7584 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7585 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7586
7587 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7588
7589 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7590 (vmcs_config.pin_based_exec_ctrl |
7591 vmcs12->pin_based_vm_exec_control));
7592
7593 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7594 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7595 vmcs12->vmx_preemption_timer_value);
7596
7597 /*
7598 * Whether page-faults are trapped is determined by a combination of
7599 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7600 * If enable_ept, L0 doesn't care about page faults and we should
7601 * set all of these to L1's desires. However, if !enable_ept, L0 does
7602 * care about (at least some) page faults, and because it is not easy
7603 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7604 * to exit on each and every L2 page fault. This is done by setting
7605 * MASK=MATCH=0 and (see below) EB.PF=1.
7606 * Note that below we don't need special code to set EB.PF beyond the
7607 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7608 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7609 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7610 *
7611 * A problem with this approach (when !enable_ept) is that L1 may be
7612 * injected with more page faults than it asked for. This could have
7613 * caused problems, but in practice existing hypervisors don't care.
7614 * To fix this, we will need to emulate the PFEC checking (on the L1
7615 * page tables), using walk_addr(), when injecting PFs to L1.
7616 */
7617 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7618 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7619 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7620 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7621
7622 if (cpu_has_secondary_exec_ctrls()) {
7623 u32 exec_control = vmx_secondary_exec_control(vmx);
7624 if (!vmx->rdtscp_enabled)
7625 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7626 /* Take the following fields only from vmcs12 */
7627 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7628 if (nested_cpu_has(vmcs12,
7629 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7630 exec_control |= vmcs12->secondary_vm_exec_control;
7631
7632 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7633 /*
7634 * Translate L1 physical address to host physical
7635 * address for vmcs02. Keep the page pinned, so this
7636 * physical address remains valid. We keep a reference
7637 * to it so we can release it later.
7638 */
7639 if (vmx->nested.apic_access_page) /* shouldn't happen */
7640 nested_release_page(vmx->nested.apic_access_page);
7641 vmx->nested.apic_access_page =
7642 nested_get_page(vcpu, vmcs12->apic_access_addr);
7643 /*
7644 * If translation failed, no matter: This feature asks
7645 * to exit when accessing the given address, and if it
7646 * can never be accessed, this feature won't do
7647 * anything anyway.
7648 */
7649 if (!vmx->nested.apic_access_page)
7650 exec_control &=
7651 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7652 else
7653 vmcs_write64(APIC_ACCESS_ADDR,
7654 page_to_phys(vmx->nested.apic_access_page));
7655 }
7656
7657 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7658 }
7659
7660
7661 /*
7662 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7663 * Some constant fields are set here by vmx_set_constant_host_state().
7664 * Other fields are different per CPU, and will be set later when
7665 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7666 */
7667 vmx_set_constant_host_state(vmx);
7668
7669 /*
7670 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7671 * entry, but only if the current (host) sp changed from the value
7672 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7673 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7674 * here we just force the write to happen on entry.
7675 */
7676 vmx->host_rsp = 0;
7677
7678 exec_control = vmx_exec_control(vmx); /* L0's desires */
7679 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7680 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7681 exec_control &= ~CPU_BASED_TPR_SHADOW;
7682 exec_control |= vmcs12->cpu_based_vm_exec_control;
7683 /*
7684 * Merging of IO and MSR bitmaps not currently supported.
7685 * Rather, exit every time.
7686 */
7687 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7688 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7689 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7690
7691 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7692
7693 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7694 * bitwise-or of what L1 wants to trap for L2, and what we want to
7695 * trap. Note that CR0.TS also needs updating - we do this later.
7696 */
7697 update_exception_bitmap(vcpu);
7698 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7699 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7700
7701 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7702 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7703 * bits are further modified by vmx_set_efer() below.
7704 */
7705 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7706
7707 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7708 * emulated by vmx_set_efer(), below.
7709 */
7710 vmcs_write32(VM_ENTRY_CONTROLS,
7711 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7712 ~VM_ENTRY_IA32E_MODE) |
7713 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7714
7715 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7716 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7717 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7718 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7719 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7720
7721
7722 set_cr4_guest_host_mask(vmx);
7723
7724 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7725 vmcs_write64(TSC_OFFSET,
7726 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7727 else
7728 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7729
7730 if (enable_vpid) {
7731 /*
7732 * Trivially support vpid by letting L2s share their parent
7733 * L1's vpid. TODO: move to a more elaborate solution, giving
7734 * each L2 its own vpid and exposing the vpid feature to L1.
7735 */
7736 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7737 vmx_flush_tlb(vcpu);
7738 }
7739
7740 if (nested_cpu_has_ept(vmcs12)) {
7741 kvm_mmu_unload(vcpu);
7742 nested_ept_init_mmu_context(vcpu);
7743 }
7744
7745 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7746 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7747 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7748 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7749 else
7750 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7751 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7752 vmx_set_efer(vcpu, vcpu->arch.efer);
7753
7754 /*
7755 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7756 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7757 * The CR0_READ_SHADOW is what L2 should have expected to read given
7758 * the specifications by L1; It's not enough to take
7759 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7760 * have more bits than L1 expected.
7761 */
7762 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7763 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7764
7765 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7766 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7767
7768 /* shadow page tables on either EPT or shadow page tables */
7769 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7770 kvm_mmu_reset_context(vcpu);
7771
7772 /*
7773 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7774 */
7775 if (enable_ept) {
7776 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7777 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7778 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7779 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7780 __clear_bit(VCPU_EXREG_PDPTR,
7781 (unsigned long *)&vcpu->arch.regs_avail);
7782 __clear_bit(VCPU_EXREG_PDPTR,
7783 (unsigned long *)&vcpu->arch.regs_dirty);
7784 }
7785
7786 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7787 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7788 }
7789
7790 /*
7791 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7792 * for running an L2 nested guest.
7793 */
7794 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7795 {
7796 struct vmcs12 *vmcs12;
7797 struct vcpu_vmx *vmx = to_vmx(vcpu);
7798 int cpu;
7799 struct loaded_vmcs *vmcs02;
7800 bool ia32e;
7801
7802 if (!nested_vmx_check_permission(vcpu) ||
7803 !nested_vmx_check_vmcs12(vcpu))
7804 return 1;
7805
7806 skip_emulated_instruction(vcpu);
7807 vmcs12 = get_vmcs12(vcpu);
7808
7809 if (enable_shadow_vmcs)
7810 copy_shadow_to_vmcs12(vmx);
7811
7812 /*
7813 * The nested entry process starts with enforcing various prerequisites
7814 * on vmcs12 as required by the Intel SDM, and act appropriately when
7815 * they fail: As the SDM explains, some conditions should cause the
7816 * instruction to fail, while others will cause the instruction to seem
7817 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7818 * To speed up the normal (success) code path, we should avoid checking
7819 * for misconfigurations which will anyway be caught by the processor
7820 * when using the merged vmcs02.
7821 */
7822 if (vmcs12->launch_state == launch) {
7823 nested_vmx_failValid(vcpu,
7824 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7825 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7826 return 1;
7827 }
7828
7829 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7830 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7831 return 1;
7832 }
7833
7834 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7835 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7836 /*TODO: Also verify bits beyond physical address width are 0*/
7837 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7838 return 1;
7839 }
7840
7841 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7842 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7843 /*TODO: Also verify bits beyond physical address width are 0*/
7844 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7845 return 1;
7846 }
7847
7848 if (vmcs12->vm_entry_msr_load_count > 0 ||
7849 vmcs12->vm_exit_msr_load_count > 0 ||
7850 vmcs12->vm_exit_msr_store_count > 0) {
7851 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7852 __func__);
7853 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7854 return 1;
7855 }
7856
7857 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7858 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7859 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7860 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7861 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7862 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7863 !vmx_control_verify(vmcs12->vm_exit_controls,
7864 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7865 !vmx_control_verify(vmcs12->vm_entry_controls,
7866 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7867 {
7868 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7869 return 1;
7870 }
7871
7872 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7873 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7874 nested_vmx_failValid(vcpu,
7875 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7876 return 1;
7877 }
7878
7879 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7880 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7881 nested_vmx_entry_failure(vcpu, vmcs12,
7882 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7883 return 1;
7884 }
7885 if (vmcs12->vmcs_link_pointer != -1ull) {
7886 nested_vmx_entry_failure(vcpu, vmcs12,
7887 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7888 return 1;
7889 }
7890
7891 /*
7892 * If the load IA32_EFER VM-entry control is 1, the following checks
7893 * are performed on the field for the IA32_EFER MSR:
7894 * - Bits reserved in the IA32_EFER MSR must be 0.
7895 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7896 * the IA-32e mode guest VM-exit control. It must also be identical
7897 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7898 * CR0.PG) is 1.
7899 */
7900 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7901 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7902 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7903 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7904 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7905 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7906 nested_vmx_entry_failure(vcpu, vmcs12,
7907 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7908 return 1;
7909 }
7910 }
7911
7912 /*
7913 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7914 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7915 * the values of the LMA and LME bits in the field must each be that of
7916 * the host address-space size VM-exit control.
7917 */
7918 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7919 ia32e = (vmcs12->vm_exit_controls &
7920 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7921 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7922 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7923 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7924 nested_vmx_entry_failure(vcpu, vmcs12,
7925 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7926 return 1;
7927 }
7928 }
7929
7930 /*
7931 * We're finally done with prerequisite checking, and can start with
7932 * the nested entry.
7933 */
7934
7935 vmcs02 = nested_get_current_vmcs02(vmx);
7936 if (!vmcs02)
7937 return -ENOMEM;
7938
7939 enter_guest_mode(vcpu);
7940
7941 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7942
7943 cpu = get_cpu();
7944 vmx->loaded_vmcs = vmcs02;
7945 vmx_vcpu_put(vcpu);
7946 vmx_vcpu_load(vcpu, cpu);
7947 vcpu->cpu = cpu;
7948 put_cpu();
7949
7950 vmx_segment_cache_clear(vmx);
7951
7952 vmcs12->launch_state = 1;
7953
7954 prepare_vmcs02(vcpu, vmcs12);
7955
7956 /*
7957 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7958 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7959 * returned as far as L1 is concerned. It will only return (and set
7960 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7961 */
7962 return 1;
7963 }
7964
7965 /*
7966 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7967 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7968 * This function returns the new value we should put in vmcs12.guest_cr0.
7969 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7970 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7971 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7972 * didn't trap the bit, because if L1 did, so would L0).
7973 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7974 * been modified by L2, and L1 knows it. So just leave the old value of
7975 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7976 * isn't relevant, because if L0 traps this bit it can set it to anything.
7977 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7978 * changed these bits, and therefore they need to be updated, but L0
7979 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7980 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7981 */
7982 static inline unsigned long
7983 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7984 {
7985 return
7986 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7987 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7988 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7989 vcpu->arch.cr0_guest_owned_bits));
7990 }
7991
7992 static inline unsigned long
7993 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7994 {
7995 return
7996 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7997 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7998 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7999 vcpu->arch.cr4_guest_owned_bits));
8000 }
8001
8002 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8003 struct vmcs12 *vmcs12)
8004 {
8005 u32 idt_vectoring;
8006 unsigned int nr;
8007
8008 if (vcpu->arch.exception.pending) {
8009 nr = vcpu->arch.exception.nr;
8010 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8011
8012 if (kvm_exception_is_soft(nr)) {
8013 vmcs12->vm_exit_instruction_len =
8014 vcpu->arch.event_exit_inst_len;
8015 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8016 } else
8017 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8018
8019 if (vcpu->arch.exception.has_error_code) {
8020 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8021 vmcs12->idt_vectoring_error_code =
8022 vcpu->arch.exception.error_code;
8023 }
8024
8025 vmcs12->idt_vectoring_info_field = idt_vectoring;
8026 } else if (vcpu->arch.nmi_pending) {
8027 vmcs12->idt_vectoring_info_field =
8028 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8029 } else if (vcpu->arch.interrupt.pending) {
8030 nr = vcpu->arch.interrupt.nr;
8031 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8032
8033 if (vcpu->arch.interrupt.soft) {
8034 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8035 vmcs12->vm_entry_instruction_len =
8036 vcpu->arch.event_exit_inst_len;
8037 } else
8038 idt_vectoring |= INTR_TYPE_EXT_INTR;
8039
8040 vmcs12->idt_vectoring_info_field = idt_vectoring;
8041 }
8042 }
8043
8044 /*
8045 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8046 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8047 * and this function updates it to reflect the changes to the guest state while
8048 * L2 was running (and perhaps made some exits which were handled directly by L0
8049 * without going back to L1), and to reflect the exit reason.
8050 * Note that we do not have to copy here all VMCS fields, just those that
8051 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8052 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8053 * which already writes to vmcs12 directly.
8054 */
8055 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8056 {
8057 /* update guest state fields: */
8058 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8059 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8060
8061 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8062 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8063 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8064 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8065
8066 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8067 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8068 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8069 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8070 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8071 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8072 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8073 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8074 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8075 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8076 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8077 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8078 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8079 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8080 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8081 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8082 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8083 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8084 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8085 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8086 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8087 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8088 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8089 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8090 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8091 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8092 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8093 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8094 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8095 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8096 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8097 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8098 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8099 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8100 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8101 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8102
8103 vmcs12->guest_interruptibility_info =
8104 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8105 vmcs12->guest_pending_dbg_exceptions =
8106 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8107
8108 /*
8109 * In some cases (usually, nested EPT), L2 is allowed to change its
8110 * own CR3 without exiting. If it has changed it, we must keep it.
8111 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8112 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8113 *
8114 * Additionally, restore L2's PDPTR to vmcs12.
8115 */
8116 if (enable_ept) {
8117 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8118 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8119 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8120 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8121 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8122 }
8123
8124 vmcs12->vm_entry_controls =
8125 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8126 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8127
8128 /* TODO: These cannot have changed unless we have MSR bitmaps and
8129 * the relevant bit asks not to trap the change */
8130 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8131 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8132 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8133 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8134 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8135 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8136
8137 /* update exit information fields: */
8138
8139 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
8140 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8141
8142 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8143 if ((vmcs12->vm_exit_intr_info &
8144 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8145 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8146 vmcs12->vm_exit_intr_error_code =
8147 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8148 vmcs12->idt_vectoring_info_field = 0;
8149 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8150 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8151
8152 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8153 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8154 * instead of reading the real value. */
8155 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8156
8157 /*
8158 * Transfer the event that L0 or L1 may wanted to inject into
8159 * L2 to IDT_VECTORING_INFO_FIELD.
8160 */
8161 vmcs12_save_pending_event(vcpu, vmcs12);
8162 }
8163
8164 /*
8165 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8166 * preserved above and would only end up incorrectly in L1.
8167 */
8168 vcpu->arch.nmi_injected = false;
8169 kvm_clear_exception_queue(vcpu);
8170 kvm_clear_interrupt_queue(vcpu);
8171 }
8172
8173 /*
8174 * A part of what we need to when the nested L2 guest exits and we want to
8175 * run its L1 parent, is to reset L1's guest state to the host state specified
8176 * in vmcs12.
8177 * This function is to be called not only on normal nested exit, but also on
8178 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8179 * Failures During or After Loading Guest State").
8180 * This function should be called when the active VMCS is L1's (vmcs01).
8181 */
8182 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8183 struct vmcs12 *vmcs12)
8184 {
8185 struct kvm_segment seg;
8186
8187 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8188 vcpu->arch.efer = vmcs12->host_ia32_efer;
8189 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8190 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8191 else
8192 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8193 vmx_set_efer(vcpu, vcpu->arch.efer);
8194
8195 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8196 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8197 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8198 /*
8199 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8200 * actually changed, because it depends on the current state of
8201 * fpu_active (which may have changed).
8202 * Note that vmx_set_cr0 refers to efer set above.
8203 */
8204 kvm_set_cr0(vcpu, vmcs12->host_cr0);
8205 /*
8206 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8207 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8208 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8209 */
8210 update_exception_bitmap(vcpu);
8211 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8212 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8213
8214 /*
8215 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8216 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8217 */
8218 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8219 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8220
8221 if (nested_cpu_has_ept(vmcs12))
8222 nested_ept_uninit_mmu_context(vcpu);
8223
8224 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8225 kvm_mmu_reset_context(vcpu);
8226
8227 if (enable_vpid) {
8228 /*
8229 * Trivially support vpid by letting L2s share their parent
8230 * L1's vpid. TODO: move to a more elaborate solution, giving
8231 * each L2 its own vpid and exposing the vpid feature to L1.
8232 */
8233 vmx_flush_tlb(vcpu);
8234 }
8235
8236
8237 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8238 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8239 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8240 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8241 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8242
8243 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8244 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8245 vcpu->arch.pat = vmcs12->host_ia32_pat;
8246 }
8247 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8248 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8249 vmcs12->host_ia32_perf_global_ctrl);
8250
8251 /* Set L1 segment info according to Intel SDM
8252 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8253 seg = (struct kvm_segment) {
8254 .base = 0,
8255 .limit = 0xFFFFFFFF,
8256 .selector = vmcs12->host_cs_selector,
8257 .type = 11,
8258 .present = 1,
8259 .s = 1,
8260 .g = 1
8261 };
8262 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8263 seg.l = 1;
8264 else
8265 seg.db = 1;
8266 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8267 seg = (struct kvm_segment) {
8268 .base = 0,
8269 .limit = 0xFFFFFFFF,
8270 .type = 3,
8271 .present = 1,
8272 .s = 1,
8273 .db = 1,
8274 .g = 1
8275 };
8276 seg.selector = vmcs12->host_ds_selector;
8277 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8278 seg.selector = vmcs12->host_es_selector;
8279 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8280 seg.selector = vmcs12->host_ss_selector;
8281 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8282 seg.selector = vmcs12->host_fs_selector;
8283 seg.base = vmcs12->host_fs_base;
8284 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8285 seg.selector = vmcs12->host_gs_selector;
8286 seg.base = vmcs12->host_gs_base;
8287 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8288 seg = (struct kvm_segment) {
8289 .base = vmcs12->host_tr_base,
8290 .limit = 0x67,
8291 .selector = vmcs12->host_tr_selector,
8292 .type = 11,
8293 .present = 1
8294 };
8295 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8296
8297 kvm_set_dr(vcpu, 7, 0x400);
8298 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8299 }
8300
8301 /*
8302 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8303 * and modify vmcs12 to make it see what it would expect to see there if
8304 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8305 */
8306 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8307 {
8308 struct vcpu_vmx *vmx = to_vmx(vcpu);
8309 int cpu;
8310 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8311
8312 /* trying to cancel vmlaunch/vmresume is a bug */
8313 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8314
8315 leave_guest_mode(vcpu);
8316 prepare_vmcs12(vcpu, vmcs12);
8317
8318 cpu = get_cpu();
8319 vmx->loaded_vmcs = &vmx->vmcs01;
8320 vmx_vcpu_put(vcpu);
8321 vmx_vcpu_load(vcpu, cpu);
8322 vcpu->cpu = cpu;
8323 put_cpu();
8324
8325 vmx_segment_cache_clear(vmx);
8326
8327 /* if no vmcs02 cache requested, remove the one we used */
8328 if (VMCS02_POOL_SIZE == 0)
8329 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8330
8331 load_vmcs12_host_state(vcpu, vmcs12);
8332
8333 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8334 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8335
8336 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8337 vmx->host_rsp = 0;
8338
8339 /* Unpin physical memory we referred to in vmcs02 */
8340 if (vmx->nested.apic_access_page) {
8341 nested_release_page(vmx->nested.apic_access_page);
8342 vmx->nested.apic_access_page = 0;
8343 }
8344
8345 /*
8346 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8347 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8348 * success or failure flag accordingly.
8349 */
8350 if (unlikely(vmx->fail)) {
8351 vmx->fail = 0;
8352 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8353 } else
8354 nested_vmx_succeed(vcpu);
8355 if (enable_shadow_vmcs)
8356 vmx->nested.sync_shadow_vmcs = true;
8357 }
8358
8359 /*
8360 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8361 * 23.7 "VM-entry failures during or after loading guest state" (this also
8362 * lists the acceptable exit-reason and exit-qualification parameters).
8363 * It should only be called before L2 actually succeeded to run, and when
8364 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8365 */
8366 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8367 struct vmcs12 *vmcs12,
8368 u32 reason, unsigned long qualification)
8369 {
8370 load_vmcs12_host_state(vcpu, vmcs12);
8371 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8372 vmcs12->exit_qualification = qualification;
8373 nested_vmx_succeed(vcpu);
8374 if (enable_shadow_vmcs)
8375 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8376 }
8377
8378 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8379 struct x86_instruction_info *info,
8380 enum x86_intercept_stage stage)
8381 {
8382 return X86EMUL_CONTINUE;
8383 }
8384
8385 static struct kvm_x86_ops vmx_x86_ops = {
8386 .cpu_has_kvm_support = cpu_has_kvm_support,
8387 .disabled_by_bios = vmx_disabled_by_bios,
8388 .hardware_setup = hardware_setup,
8389 .hardware_unsetup = hardware_unsetup,
8390 .check_processor_compatibility = vmx_check_processor_compat,
8391 .hardware_enable = hardware_enable,
8392 .hardware_disable = hardware_disable,
8393 .cpu_has_accelerated_tpr = report_flexpriority,
8394
8395 .vcpu_create = vmx_create_vcpu,
8396 .vcpu_free = vmx_free_vcpu,
8397 .vcpu_reset = vmx_vcpu_reset,
8398
8399 .prepare_guest_switch = vmx_save_host_state,
8400 .vcpu_load = vmx_vcpu_load,
8401 .vcpu_put = vmx_vcpu_put,
8402
8403 .update_db_bp_intercept = update_exception_bitmap,
8404 .get_msr = vmx_get_msr,
8405 .set_msr = vmx_set_msr,
8406 .get_segment_base = vmx_get_segment_base,
8407 .get_segment = vmx_get_segment,
8408 .set_segment = vmx_set_segment,
8409 .get_cpl = vmx_get_cpl,
8410 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8411 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8412 .decache_cr3 = vmx_decache_cr3,
8413 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8414 .set_cr0 = vmx_set_cr0,
8415 .set_cr3 = vmx_set_cr3,
8416 .set_cr4 = vmx_set_cr4,
8417 .set_efer = vmx_set_efer,
8418 .get_idt = vmx_get_idt,
8419 .set_idt = vmx_set_idt,
8420 .get_gdt = vmx_get_gdt,
8421 .set_gdt = vmx_set_gdt,
8422 .set_dr7 = vmx_set_dr7,
8423 .cache_reg = vmx_cache_reg,
8424 .get_rflags = vmx_get_rflags,
8425 .set_rflags = vmx_set_rflags,
8426 .fpu_activate = vmx_fpu_activate,
8427 .fpu_deactivate = vmx_fpu_deactivate,
8428
8429 .tlb_flush = vmx_flush_tlb,
8430
8431 .run = vmx_vcpu_run,
8432 .handle_exit = vmx_handle_exit,
8433 .skip_emulated_instruction = skip_emulated_instruction,
8434 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8435 .get_interrupt_shadow = vmx_get_interrupt_shadow,
8436 .patch_hypercall = vmx_patch_hypercall,
8437 .set_irq = vmx_inject_irq,
8438 .set_nmi = vmx_inject_nmi,
8439 .queue_exception = vmx_queue_exception,
8440 .cancel_injection = vmx_cancel_injection,
8441 .interrupt_allowed = vmx_interrupt_allowed,
8442 .nmi_allowed = vmx_nmi_allowed,
8443 .get_nmi_mask = vmx_get_nmi_mask,
8444 .set_nmi_mask = vmx_set_nmi_mask,
8445 .enable_nmi_window = enable_nmi_window,
8446 .enable_irq_window = enable_irq_window,
8447 .update_cr8_intercept = update_cr8_intercept,
8448 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8449 .vm_has_apicv = vmx_vm_has_apicv,
8450 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8451 .hwapic_irr_update = vmx_hwapic_irr_update,
8452 .hwapic_isr_update = vmx_hwapic_isr_update,
8453 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8454 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8455
8456 .set_tss_addr = vmx_set_tss_addr,
8457 .get_tdp_level = get_ept_level,
8458 .get_mt_mask = vmx_get_mt_mask,
8459
8460 .get_exit_info = vmx_get_exit_info,
8461
8462 .get_lpage_level = vmx_get_lpage_level,
8463
8464 .cpuid_update = vmx_cpuid_update,
8465
8466 .rdtscp_supported = vmx_rdtscp_supported,
8467 .invpcid_supported = vmx_invpcid_supported,
8468
8469 .set_supported_cpuid = vmx_set_supported_cpuid,
8470
8471 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8472
8473 .set_tsc_khz = vmx_set_tsc_khz,
8474 .read_tsc_offset = vmx_read_tsc_offset,
8475 .write_tsc_offset = vmx_write_tsc_offset,
8476 .adjust_tsc_offset = vmx_adjust_tsc_offset,
8477 .compute_tsc_offset = vmx_compute_tsc_offset,
8478 .read_l1_tsc = vmx_read_l1_tsc,
8479
8480 .set_tdp_cr3 = vmx_set_cr3,
8481
8482 .check_intercept = vmx_check_intercept,
8483 .handle_external_intr = vmx_handle_external_intr,
8484 };
8485
8486 static int __init vmx_init(void)
8487 {
8488 int r, i, msr;
8489
8490 rdmsrl_safe(MSR_EFER, &host_efer);
8491
8492 for (i = 0; i < NR_VMX_MSR; ++i)
8493 kvm_define_shared_msr(i, vmx_msr_index[i]);
8494
8495 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8496 if (!vmx_io_bitmap_a)
8497 return -ENOMEM;
8498
8499 r = -ENOMEM;
8500
8501 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8502 if (!vmx_io_bitmap_b)
8503 goto out;
8504
8505 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8506 if (!vmx_msr_bitmap_legacy)
8507 goto out1;
8508
8509 vmx_msr_bitmap_legacy_x2apic =
8510 (unsigned long *)__get_free_page(GFP_KERNEL);
8511 if (!vmx_msr_bitmap_legacy_x2apic)
8512 goto out2;
8513
8514 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8515 if (!vmx_msr_bitmap_longmode)
8516 goto out3;
8517
8518 vmx_msr_bitmap_longmode_x2apic =
8519 (unsigned long *)__get_free_page(GFP_KERNEL);
8520 if (!vmx_msr_bitmap_longmode_x2apic)
8521 goto out4;
8522 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8523 if (!vmx_vmread_bitmap)
8524 goto out5;
8525
8526 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8527 if (!vmx_vmwrite_bitmap)
8528 goto out6;
8529
8530 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8531 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8532 /* shadowed read/write fields */
8533 for (i = 0; i < max_shadow_read_write_fields; i++) {
8534 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8535 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8536 }
8537 /* shadowed read only fields */
8538 for (i = 0; i < max_shadow_read_only_fields; i++)
8539 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8540
8541 /*
8542 * Allow direct access to the PC debug port (it is often used for I/O
8543 * delays, but the vmexits simply slow things down).
8544 */
8545 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8546 clear_bit(0x80, vmx_io_bitmap_a);
8547
8548 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8549
8550 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8551 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8552
8553 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8554
8555 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8556 __alignof__(struct vcpu_vmx), THIS_MODULE);
8557 if (r)
8558 goto out7;
8559
8560 #ifdef CONFIG_KEXEC
8561 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8562 crash_vmclear_local_loaded_vmcss);
8563 #endif
8564
8565 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8566 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8567 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8568 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8569 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8570 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8571 memcpy(vmx_msr_bitmap_legacy_x2apic,
8572 vmx_msr_bitmap_legacy, PAGE_SIZE);
8573 memcpy(vmx_msr_bitmap_longmode_x2apic,
8574 vmx_msr_bitmap_longmode, PAGE_SIZE);
8575
8576 if (enable_apicv) {
8577 for (msr = 0x800; msr <= 0x8ff; msr++)
8578 vmx_disable_intercept_msr_read_x2apic(msr);
8579
8580 /* According SDM, in x2apic mode, the whole id reg is used.
8581 * But in KVM, it only use the highest eight bits. Need to
8582 * intercept it */
8583 vmx_enable_intercept_msr_read_x2apic(0x802);
8584 /* TMCCT */
8585 vmx_enable_intercept_msr_read_x2apic(0x839);
8586 /* TPR */
8587 vmx_disable_intercept_msr_write_x2apic(0x808);
8588 /* EOI */
8589 vmx_disable_intercept_msr_write_x2apic(0x80b);
8590 /* SELF-IPI */
8591 vmx_disable_intercept_msr_write_x2apic(0x83f);
8592 }
8593
8594 if (enable_ept) {
8595 kvm_mmu_set_mask_ptes(0ull,
8596 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8597 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8598 0ull, VMX_EPT_EXECUTABLE_MASK);
8599 ept_set_mmio_spte_mask();
8600 kvm_enable_tdp();
8601 } else
8602 kvm_disable_tdp();
8603
8604 return 0;
8605
8606 out7:
8607 free_page((unsigned long)vmx_vmwrite_bitmap);
8608 out6:
8609 free_page((unsigned long)vmx_vmread_bitmap);
8610 out5:
8611 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8612 out4:
8613 free_page((unsigned long)vmx_msr_bitmap_longmode);
8614 out3:
8615 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8616 out2:
8617 free_page((unsigned long)vmx_msr_bitmap_legacy);
8618 out1:
8619 free_page((unsigned long)vmx_io_bitmap_b);
8620 out:
8621 free_page((unsigned long)vmx_io_bitmap_a);
8622 return r;
8623 }
8624
8625 static void __exit vmx_exit(void)
8626 {
8627 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8628 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8629 free_page((unsigned long)vmx_msr_bitmap_legacy);
8630 free_page((unsigned long)vmx_msr_bitmap_longmode);
8631 free_page((unsigned long)vmx_io_bitmap_b);
8632 free_page((unsigned long)vmx_io_bitmap_a);
8633 free_page((unsigned long)vmx_vmwrite_bitmap);
8634 free_page((unsigned long)vmx_vmread_bitmap);
8635
8636 #ifdef CONFIG_KEXEC
8637 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8638 synchronize_rcu();
8639 #endif
8640
8641 kvm_exit();
8642 }
8643
8644 module_init(vmx_init)
8645 module_exit(vmx_exit)
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