2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
45 #include <asm/virtext.h>
47 #include <asm/fpu/internal.h>
48 #include <asm/perf_event.h>
49 #include <asm/debugreg.h>
50 #include <asm/kexec.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/mmu_context.h>
54 #include <asm/nospec-branch.h>
59 #define __ex(x) __kvm_handle_fault_on_reboot(x)
60 #define __ex_clear(x, reg) \
61 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
63 MODULE_AUTHOR("Qumranet");
64 MODULE_LICENSE("GPL");
66 static const struct x86_cpu_id vmx_cpu_id
[] = {
67 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
70 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
72 static bool __read_mostly enable_vpid
= 1;
73 module_param_named(vpid
, enable_vpid
, bool, 0444);
75 static bool __read_mostly enable_vnmi
= 1;
76 module_param_named(vnmi
, enable_vnmi
, bool, S_IRUGO
);
78 static bool __read_mostly flexpriority_enabled
= 1;
79 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept
= 1;
82 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
84 static bool __read_mostly enable_unrestricted_guest
= 1;
85 module_param_named(unrestricted_guest
,
86 enable_unrestricted_guest
, bool, S_IRUGO
);
88 static bool __read_mostly enable_ept_ad_bits
= 1;
89 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
91 static bool __read_mostly emulate_invalid_guest_state
= true;
92 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
94 static bool __read_mostly fasteoi
= 1;
95 module_param(fasteoi
, bool, S_IRUGO
);
97 static bool __read_mostly enable_apicv
= 1;
98 module_param(enable_apicv
, bool, S_IRUGO
);
100 static bool __read_mostly enable_shadow_vmcs
= 1;
101 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
103 * If nested=1, nested virtualization is supported, i.e., guests may use
104 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
105 * use VMX instructions.
107 static bool __read_mostly nested
= 0;
108 module_param(nested
, bool, S_IRUGO
);
110 static u64 __read_mostly host_xss
;
112 static bool __read_mostly enable_pml
= 1;
113 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
117 #define MSR_TYPE_RW 3
119 #define MSR_BITMAP_MODE_X2APIC 1
120 #define MSR_BITMAP_MODE_X2APIC_APICV 2
121 #define MSR_BITMAP_MODE_LM 4
123 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
125 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
126 static int __read_mostly cpu_preemption_timer_multi
;
127 static bool __read_mostly enable_preemption_timer
= 1;
129 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
132 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
133 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
134 #define KVM_VM_CR0_ALWAYS_ON \
135 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
136 #define KVM_CR4_GUEST_OWNED_BITS \
137 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
138 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
140 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
141 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
143 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
145 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
148 * Hyper-V requires all of these, so mark them as supported even though
149 * they are just treated the same as all-context.
151 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
152 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
153 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
154 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
155 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
158 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
159 * ple_gap: upper bound on the amount of time between two successive
160 * executions of PAUSE in a loop. Also indicate if ple enabled.
161 * According to test, this time is usually smaller than 128 cycles.
162 * ple_window: upper bound on the amount of time a guest is allowed to execute
163 * in a PAUSE loop. Tests indicate that most spinlocks are held for
164 * less than 2^12 cycles
165 * Time is measured based on a counter that runs at the same rate as the TSC,
166 * refer SDM volume 3b section 21.6.13 & 22.1.3.
168 #define KVM_VMX_DEFAULT_PLE_GAP 128
169 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
170 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
171 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
172 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
173 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
175 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
176 module_param(ple_gap
, int, S_IRUGO
);
178 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
179 module_param(ple_window
, int, S_IRUGO
);
181 /* Default doubles per-vcpu window every exit. */
182 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
183 module_param(ple_window_grow
, int, S_IRUGO
);
185 /* Default resets per-vcpu window every exit to ple_window. */
186 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
187 module_param(ple_window_shrink
, int, S_IRUGO
);
189 /* Default is to compute the maximum so we can never overflow. */
190 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
191 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
192 module_param(ple_window_max
, int, S_IRUGO
);
194 extern const ulong vmx_return
;
196 #define NR_AUTOLOAD_MSRS 8
205 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
206 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
207 * loaded on this CPU (so we can clear them if the CPU goes down).
211 struct vmcs
*shadow_vmcs
;
214 bool nmi_known_unmasked
;
215 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
216 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
217 /* Support for vnmi-less CPUs */
218 int soft_vnmi_blocked
;
220 s64 vnmi_blocked_time
;
221 unsigned long *msr_bitmap
;
222 struct list_head loaded_vmcss_on_cpu_link
;
225 struct shared_msr_entry
{
232 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
233 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
234 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
235 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
236 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
237 * More than one of these structures may exist, if L1 runs multiple L2 guests.
238 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
239 * underlying hardware which will be used to run L2.
240 * This structure is packed to ensure that its layout is identical across
241 * machines (necessary for live migration).
242 * If there are changes in this struct, VMCS12_REVISION must be changed.
244 typedef u64 natural_width
;
245 struct __packed vmcs12
{
246 /* According to the Intel spec, a VMCS region must start with the
247 * following two fields. Then follow implementation-specific data.
252 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
253 u32 padding
[7]; /* room for future expansion */
258 u64 vm_exit_msr_store_addr
;
259 u64 vm_exit_msr_load_addr
;
260 u64 vm_entry_msr_load_addr
;
262 u64 virtual_apic_page_addr
;
263 u64 apic_access_addr
;
264 u64 posted_intr_desc_addr
;
265 u64 vm_function_control
;
267 u64 eoi_exit_bitmap0
;
268 u64 eoi_exit_bitmap1
;
269 u64 eoi_exit_bitmap2
;
270 u64 eoi_exit_bitmap3
;
271 u64 eptp_list_address
;
273 u64 guest_physical_address
;
274 u64 vmcs_link_pointer
;
276 u64 guest_ia32_debugctl
;
279 u64 guest_ia32_perf_global_ctrl
;
287 u64 host_ia32_perf_global_ctrl
;
288 u64 padding64
[8]; /* room for future expansion */
290 * To allow migration of L1 (complete with its L2 guests) between
291 * machines of different natural widths (32 or 64 bit), we cannot have
292 * unsigned long fields with no explict size. We use u64 (aliased
293 * natural_width) instead. Luckily, x86 is little-endian.
295 natural_width cr0_guest_host_mask
;
296 natural_width cr4_guest_host_mask
;
297 natural_width cr0_read_shadow
;
298 natural_width cr4_read_shadow
;
299 natural_width cr3_target_value0
;
300 natural_width cr3_target_value1
;
301 natural_width cr3_target_value2
;
302 natural_width cr3_target_value3
;
303 natural_width exit_qualification
;
304 natural_width guest_linear_address
;
305 natural_width guest_cr0
;
306 natural_width guest_cr3
;
307 natural_width guest_cr4
;
308 natural_width guest_es_base
;
309 natural_width guest_cs_base
;
310 natural_width guest_ss_base
;
311 natural_width guest_ds_base
;
312 natural_width guest_fs_base
;
313 natural_width guest_gs_base
;
314 natural_width guest_ldtr_base
;
315 natural_width guest_tr_base
;
316 natural_width guest_gdtr_base
;
317 natural_width guest_idtr_base
;
318 natural_width guest_dr7
;
319 natural_width guest_rsp
;
320 natural_width guest_rip
;
321 natural_width guest_rflags
;
322 natural_width guest_pending_dbg_exceptions
;
323 natural_width guest_sysenter_esp
;
324 natural_width guest_sysenter_eip
;
325 natural_width host_cr0
;
326 natural_width host_cr3
;
327 natural_width host_cr4
;
328 natural_width host_fs_base
;
329 natural_width host_gs_base
;
330 natural_width host_tr_base
;
331 natural_width host_gdtr_base
;
332 natural_width host_idtr_base
;
333 natural_width host_ia32_sysenter_esp
;
334 natural_width host_ia32_sysenter_eip
;
335 natural_width host_rsp
;
336 natural_width host_rip
;
337 natural_width paddingl
[8]; /* room for future expansion */
338 u32 pin_based_vm_exec_control
;
339 u32 cpu_based_vm_exec_control
;
340 u32 exception_bitmap
;
341 u32 page_fault_error_code_mask
;
342 u32 page_fault_error_code_match
;
343 u32 cr3_target_count
;
344 u32 vm_exit_controls
;
345 u32 vm_exit_msr_store_count
;
346 u32 vm_exit_msr_load_count
;
347 u32 vm_entry_controls
;
348 u32 vm_entry_msr_load_count
;
349 u32 vm_entry_intr_info_field
;
350 u32 vm_entry_exception_error_code
;
351 u32 vm_entry_instruction_len
;
353 u32 secondary_vm_exec_control
;
354 u32 vm_instruction_error
;
356 u32 vm_exit_intr_info
;
357 u32 vm_exit_intr_error_code
;
358 u32 idt_vectoring_info_field
;
359 u32 idt_vectoring_error_code
;
360 u32 vm_exit_instruction_len
;
361 u32 vmx_instruction_info
;
368 u32 guest_ldtr_limit
;
370 u32 guest_gdtr_limit
;
371 u32 guest_idtr_limit
;
372 u32 guest_es_ar_bytes
;
373 u32 guest_cs_ar_bytes
;
374 u32 guest_ss_ar_bytes
;
375 u32 guest_ds_ar_bytes
;
376 u32 guest_fs_ar_bytes
;
377 u32 guest_gs_ar_bytes
;
378 u32 guest_ldtr_ar_bytes
;
379 u32 guest_tr_ar_bytes
;
380 u32 guest_interruptibility_info
;
381 u32 guest_activity_state
;
382 u32 guest_sysenter_cs
;
383 u32 host_ia32_sysenter_cs
;
384 u32 vmx_preemption_timer_value
;
385 u32 padding32
[7]; /* room for future expansion */
386 u16 virtual_processor_id
;
388 u16 guest_es_selector
;
389 u16 guest_cs_selector
;
390 u16 guest_ss_selector
;
391 u16 guest_ds_selector
;
392 u16 guest_fs_selector
;
393 u16 guest_gs_selector
;
394 u16 guest_ldtr_selector
;
395 u16 guest_tr_selector
;
396 u16 guest_intr_status
;
398 u16 host_es_selector
;
399 u16 host_cs_selector
;
400 u16 host_ss_selector
;
401 u16 host_ds_selector
;
402 u16 host_fs_selector
;
403 u16 host_gs_selector
;
404 u16 host_tr_selector
;
408 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
409 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
410 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
412 #define VMCS12_REVISION 0x11e57ed0
415 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
416 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
417 * current implementation, 4K are reserved to avoid future complications.
419 #define VMCS12_SIZE 0x1000
422 * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
423 * supported VMCS12 field encoding.
425 #define VMCS12_MAX_FIELD_INDEX 0x17
428 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
429 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
432 /* Has the level1 guest done vmxon? */
437 /* The guest-physical address of the current VMCS L1 keeps for L2 */
440 * Cache of the guest's VMCS, existing outside of guest memory.
441 * Loaded from guest memory during VMPTRLD. Flushed to guest
442 * memory during VMCLEAR and VMPTRLD.
444 struct vmcs12
*cached_vmcs12
;
446 * Indicates if the shadow vmcs must be updated with the
447 * data hold by vmcs12
449 bool sync_shadow_vmcs
;
452 bool change_vmcs01_virtual_x2apic_mode
;
453 /* L2 must run next, and mustn't decide to exit to L1. */
454 bool nested_run_pending
;
456 struct loaded_vmcs vmcs02
;
459 * Guest pages referred to in the vmcs02 with host-physical
460 * pointers, so we must keep them pinned while L2 runs.
462 struct page
*apic_access_page
;
463 struct page
*virtual_apic_page
;
464 struct page
*pi_desc_page
;
465 struct pi_desc
*pi_desc
;
469 struct hrtimer preemption_timer
;
470 bool preemption_timer_expired
;
472 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
479 * We only store the "true" versions of the VMX capability MSRs. We
480 * generate the "non-true" versions by setting the must-be-1 bits
481 * according to the SDM.
483 u32 nested_vmx_procbased_ctls_low
;
484 u32 nested_vmx_procbased_ctls_high
;
485 u32 nested_vmx_secondary_ctls_low
;
486 u32 nested_vmx_secondary_ctls_high
;
487 u32 nested_vmx_pinbased_ctls_low
;
488 u32 nested_vmx_pinbased_ctls_high
;
489 u32 nested_vmx_exit_ctls_low
;
490 u32 nested_vmx_exit_ctls_high
;
491 u32 nested_vmx_entry_ctls_low
;
492 u32 nested_vmx_entry_ctls_high
;
493 u32 nested_vmx_misc_low
;
494 u32 nested_vmx_misc_high
;
495 u32 nested_vmx_ept_caps
;
496 u32 nested_vmx_vpid_caps
;
497 u64 nested_vmx_basic
;
498 u64 nested_vmx_cr0_fixed0
;
499 u64 nested_vmx_cr0_fixed1
;
500 u64 nested_vmx_cr4_fixed0
;
501 u64 nested_vmx_cr4_fixed1
;
502 u64 nested_vmx_vmcs_enum
;
503 u64 nested_vmx_vmfunc_controls
;
505 /* SMM related state */
507 /* in VMX operation on SMM entry? */
509 /* in guest mode on SMM entry? */
514 #define POSTED_INTR_ON 0
515 #define POSTED_INTR_SN 1
517 /* Posted-Interrupt Descriptor */
519 u32 pir
[8]; /* Posted interrupt requested */
522 /* bit 256 - Outstanding Notification */
524 /* bit 257 - Suppress Notification */
526 /* bit 271:258 - Reserved */
528 /* bit 279:272 - Notification Vector */
530 /* bit 287:280 - Reserved */
532 /* bit 319:288 - Notification Destination */
540 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
542 return test_and_set_bit(POSTED_INTR_ON
,
543 (unsigned long *)&pi_desc
->control
);
546 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
548 return test_and_clear_bit(POSTED_INTR_ON
,
549 (unsigned long *)&pi_desc
->control
);
552 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
554 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
557 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
559 return clear_bit(POSTED_INTR_SN
,
560 (unsigned long *)&pi_desc
->control
);
563 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
565 return set_bit(POSTED_INTR_SN
,
566 (unsigned long *)&pi_desc
->control
);
569 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
571 clear_bit(POSTED_INTR_ON
,
572 (unsigned long *)&pi_desc
->control
);
575 static inline int pi_test_on(struct pi_desc
*pi_desc
)
577 return test_bit(POSTED_INTR_ON
,
578 (unsigned long *)&pi_desc
->control
);
581 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
583 return test_bit(POSTED_INTR_SN
,
584 (unsigned long *)&pi_desc
->control
);
588 struct kvm_vcpu vcpu
;
589 unsigned long host_rsp
;
593 u32 idt_vectoring_info
;
595 struct shared_msr_entry
*guest_msrs
;
598 unsigned long host_idt_base
;
600 u64 msr_host_kernel_gs_base
;
601 u64 msr_guest_kernel_gs_base
;
604 u64 arch_capabilities
;
607 u32 vm_entry_controls_shadow
;
608 u32 vm_exit_controls_shadow
;
609 u32 secondary_exec_control
;
612 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
613 * non-nested (L1) guest, it always points to vmcs01. For a nested
614 * guest (L2), it points to a different VMCS.
616 struct loaded_vmcs vmcs01
;
617 struct loaded_vmcs
*loaded_vmcs
;
618 bool __launched
; /* temporary, used in vmx_vcpu_run */
619 struct msr_autoload
{
621 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
622 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
626 u16 fs_sel
, gs_sel
, ldt_sel
;
630 int gs_ldt_reload_needed
;
631 int fs_reload_needed
;
632 u64 msr_host_bndcfgs
;
637 struct kvm_segment segs
[8];
640 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
641 struct kvm_save_segment
{
649 bool emulation_required
;
653 /* Posted interrupt descriptor */
654 struct pi_desc pi_desc
;
656 /* Support for a guest hypervisor (nested VMX) */
657 struct nested_vmx nested
;
659 /* Dynamic PLE window. */
661 bool ple_window_dirty
;
663 /* Support for PML */
664 #define PML_ENTITY_NUM 512
667 /* apic deadline value in host tsc */
670 u64 current_tsc_ratio
;
674 unsigned long host_debugctlmsr
;
677 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
678 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
679 * in msr_ia32_feature_control_valid_bits.
681 u64 msr_ia32_feature_control
;
682 u64 msr_ia32_feature_control_valid_bits
;
685 enum segment_cache_field
{
694 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
696 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
699 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
701 return &(to_vmx(vcpu
)->pi_desc
);
704 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
705 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
706 #define FIELD(number, name) [ROL16(number, 6)] = VMCS12_OFFSET(name)
707 #define FIELD64(number, name) \
708 FIELD(number, name), \
709 [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
712 static u16 shadow_read_only_fields
[] = {
713 #define SHADOW_FIELD_RO(x) x,
714 #include "vmx_shadow_fields.h"
716 static int max_shadow_read_only_fields
=
717 ARRAY_SIZE(shadow_read_only_fields
);
719 static u16 shadow_read_write_fields
[] = {
720 #define SHADOW_FIELD_RW(x) x,
721 #include "vmx_shadow_fields.h"
723 static int max_shadow_read_write_fields
=
724 ARRAY_SIZE(shadow_read_write_fields
);
726 static const unsigned short vmcs_field_to_offset_table
[] = {
727 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
728 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
729 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
730 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
731 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
732 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
733 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
734 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
735 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
736 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
737 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
738 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
739 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
740 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
741 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
742 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
743 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
744 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
745 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
746 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
747 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
748 FIELD64(MSR_BITMAP
, msr_bitmap
),
749 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
750 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
751 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
752 FIELD64(TSC_OFFSET
, tsc_offset
),
753 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
754 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
755 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
756 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
757 FIELD64(EPT_POINTER
, ept_pointer
),
758 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
759 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
760 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
761 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
762 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
763 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
764 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
765 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
766 FIELD64(PML_ADDRESS
, pml_address
),
767 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
768 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
769 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
770 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
771 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
772 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
773 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
774 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
775 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
776 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
777 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
778 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
779 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
780 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
781 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
782 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
783 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
784 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
785 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
786 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
787 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
788 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
789 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
790 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
791 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
792 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
793 FIELD(TPR_THRESHOLD
, tpr_threshold
),
794 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
795 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
796 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
797 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
798 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
799 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
800 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
801 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
802 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
803 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
804 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
805 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
806 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
807 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
808 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
809 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
810 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
811 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
812 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
813 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
814 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
815 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
816 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
817 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
818 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
819 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
820 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
821 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
822 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
823 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
824 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
825 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
826 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
827 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
828 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
829 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
830 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
831 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
832 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
833 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
834 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
835 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
836 FIELD(GUEST_CR0
, guest_cr0
),
837 FIELD(GUEST_CR3
, guest_cr3
),
838 FIELD(GUEST_CR4
, guest_cr4
),
839 FIELD(GUEST_ES_BASE
, guest_es_base
),
840 FIELD(GUEST_CS_BASE
, guest_cs_base
),
841 FIELD(GUEST_SS_BASE
, guest_ss_base
),
842 FIELD(GUEST_DS_BASE
, guest_ds_base
),
843 FIELD(GUEST_FS_BASE
, guest_fs_base
),
844 FIELD(GUEST_GS_BASE
, guest_gs_base
),
845 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
846 FIELD(GUEST_TR_BASE
, guest_tr_base
),
847 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
848 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
849 FIELD(GUEST_DR7
, guest_dr7
),
850 FIELD(GUEST_RSP
, guest_rsp
),
851 FIELD(GUEST_RIP
, guest_rip
),
852 FIELD(GUEST_RFLAGS
, guest_rflags
),
853 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
854 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
855 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
856 FIELD(HOST_CR0
, host_cr0
),
857 FIELD(HOST_CR3
, host_cr3
),
858 FIELD(HOST_CR4
, host_cr4
),
859 FIELD(HOST_FS_BASE
, host_fs_base
),
860 FIELD(HOST_GS_BASE
, host_gs_base
),
861 FIELD(HOST_TR_BASE
, host_tr_base
),
862 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
863 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
864 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
865 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
866 FIELD(HOST_RSP
, host_rsp
),
867 FIELD(HOST_RIP
, host_rip
),
870 static inline short vmcs_field_to_offset(unsigned long field
)
872 const size_t size
= ARRAY_SIZE(vmcs_field_to_offset_table
);
873 unsigned short offset
;
879 index
= ROL16(field
, 6);
883 index
= array_index_nospec(index
, size
);
884 offset
= vmcs_field_to_offset_table
[index
];
890 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
892 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
895 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
896 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
897 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
898 static bool vmx_xsaves_supported(void);
899 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
900 struct kvm_segment
*var
, int seg
);
901 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
902 struct kvm_segment
*var
, int seg
);
903 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
904 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
905 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
906 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
907 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
908 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
910 static void vmx_update_msr_bitmap(struct kvm_vcpu
*vcpu
);
911 static void __always_inline
vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
914 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
915 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
917 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
918 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
920 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
923 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
924 * can find which vCPU should be waken up.
926 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
927 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
935 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
937 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
938 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
940 static bool cpu_has_load_ia32_efer
;
941 static bool cpu_has_load_perf_global_ctrl
;
943 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
944 static DEFINE_SPINLOCK(vmx_vpid_lock
);
946 static struct vmcs_config
{
951 u32 pin_based_exec_ctrl
;
952 u32 cpu_based_exec_ctrl
;
953 u32 cpu_based_2nd_exec_ctrl
;
958 static struct vmx_capability
{
963 #define VMX_SEGMENT_FIELD(seg) \
964 [VCPU_SREG_##seg] = { \
965 .selector = GUEST_##seg##_SELECTOR, \
966 .base = GUEST_##seg##_BASE, \
967 .limit = GUEST_##seg##_LIMIT, \
968 .ar_bytes = GUEST_##seg##_AR_BYTES, \
971 static const struct kvm_vmx_segment_field
{
976 } kvm_vmx_segment_fields
[] = {
977 VMX_SEGMENT_FIELD(CS
),
978 VMX_SEGMENT_FIELD(DS
),
979 VMX_SEGMENT_FIELD(ES
),
980 VMX_SEGMENT_FIELD(FS
),
981 VMX_SEGMENT_FIELD(GS
),
982 VMX_SEGMENT_FIELD(SS
),
983 VMX_SEGMENT_FIELD(TR
),
984 VMX_SEGMENT_FIELD(LDTR
),
987 static u64 host_efer
;
989 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
992 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
993 * away by decrementing the array size.
995 static const u32 vmx_msr_index
[] = {
997 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
999 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1002 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1004 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1005 INTR_INFO_VALID_MASK
)) ==
1006 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1009 static inline bool is_debug(u32 intr_info
)
1011 return is_exception_n(intr_info
, DB_VECTOR
);
1014 static inline bool is_breakpoint(u32 intr_info
)
1016 return is_exception_n(intr_info
, BP_VECTOR
);
1019 static inline bool is_page_fault(u32 intr_info
)
1021 return is_exception_n(intr_info
, PF_VECTOR
);
1024 static inline bool is_no_device(u32 intr_info
)
1026 return is_exception_n(intr_info
, NM_VECTOR
);
1029 static inline bool is_invalid_opcode(u32 intr_info
)
1031 return is_exception_n(intr_info
, UD_VECTOR
);
1034 static inline bool is_external_interrupt(u32 intr_info
)
1036 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1037 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1040 static inline bool is_machine_check(u32 intr_info
)
1042 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1043 INTR_INFO_VALID_MASK
)) ==
1044 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1047 /* Undocumented: icebp/int1 */
1048 static inline bool is_icebp(u32 intr_info
)
1050 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1051 == (INTR_TYPE_PRIV_SW_EXCEPTION
| INTR_INFO_VALID_MASK
);
1054 static inline bool cpu_has_vmx_msr_bitmap(void)
1056 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1059 static inline bool cpu_has_vmx_tpr_shadow(void)
1061 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1064 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1066 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1069 static inline bool cpu_has_secondary_exec_ctrls(void)
1071 return vmcs_config
.cpu_based_exec_ctrl
&
1072 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1075 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1077 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1078 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1081 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1083 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1084 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1087 static inline bool cpu_has_vmx_apic_register_virt(void)
1089 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1090 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1093 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1095 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1096 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1100 * Comment's format: document - errata name - stepping - processor name.
1102 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1104 static u32 vmx_preemption_cpu_tfms
[] = {
1105 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1107 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1108 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1109 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1111 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1113 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1114 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1116 * 320767.pdf - AAP86 - B1 -
1117 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1120 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1122 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1124 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1126 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1127 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1128 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1132 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1134 u32 eax
= cpuid_eax(0x00000001), i
;
1136 /* Clear the reserved bits */
1137 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1138 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1139 if (eax
== vmx_preemption_cpu_tfms
[i
])
1145 static inline bool cpu_has_vmx_preemption_timer(void)
1147 return vmcs_config
.pin_based_exec_ctrl
&
1148 PIN_BASED_VMX_PREEMPTION_TIMER
;
1151 static inline bool cpu_has_vmx_posted_intr(void)
1153 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1154 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1157 static inline bool cpu_has_vmx_apicv(void)
1159 return cpu_has_vmx_apic_register_virt() &&
1160 cpu_has_vmx_virtual_intr_delivery() &&
1161 cpu_has_vmx_posted_intr();
1164 static inline bool cpu_has_vmx_flexpriority(void)
1166 return cpu_has_vmx_tpr_shadow() &&
1167 cpu_has_vmx_virtualize_apic_accesses();
1170 static inline bool cpu_has_vmx_ept_execute_only(void)
1172 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1175 static inline bool cpu_has_vmx_ept_2m_page(void)
1177 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1180 static inline bool cpu_has_vmx_ept_1g_page(void)
1182 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1185 static inline bool cpu_has_vmx_ept_4levels(void)
1187 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1190 static inline bool cpu_has_vmx_ept_mt_wb(void)
1192 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1195 static inline bool cpu_has_vmx_ept_5levels(void)
1197 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1200 static inline bool cpu_has_vmx_ept_ad_bits(void)
1202 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1205 static inline bool cpu_has_vmx_invept_context(void)
1207 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1210 static inline bool cpu_has_vmx_invept_global(void)
1212 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1215 static inline bool cpu_has_vmx_invvpid_single(void)
1217 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1220 static inline bool cpu_has_vmx_invvpid_global(void)
1222 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1225 static inline bool cpu_has_vmx_invvpid(void)
1227 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1230 static inline bool cpu_has_vmx_ept(void)
1232 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1233 SECONDARY_EXEC_ENABLE_EPT
;
1236 static inline bool cpu_has_vmx_unrestricted_guest(void)
1238 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1239 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1242 static inline bool cpu_has_vmx_ple(void)
1244 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1245 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1248 static inline bool cpu_has_vmx_basic_inout(void)
1250 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1253 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1255 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1258 static inline bool cpu_has_vmx_vpid(void)
1260 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1261 SECONDARY_EXEC_ENABLE_VPID
;
1264 static inline bool cpu_has_vmx_rdtscp(void)
1266 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1267 SECONDARY_EXEC_RDTSCP
;
1270 static inline bool cpu_has_vmx_invpcid(void)
1272 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1273 SECONDARY_EXEC_ENABLE_INVPCID
;
1276 static inline bool cpu_has_virtual_nmis(void)
1278 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1281 static inline bool cpu_has_vmx_wbinvd_exit(void)
1283 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1284 SECONDARY_EXEC_WBINVD_EXITING
;
1287 static inline bool cpu_has_vmx_shadow_vmcs(void)
1290 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1291 /* check if the cpu supports writing r/o exit information fields */
1292 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1295 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1296 SECONDARY_EXEC_SHADOW_VMCS
;
1299 static inline bool cpu_has_vmx_pml(void)
1301 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1304 static inline bool cpu_has_vmx_tsc_scaling(void)
1306 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1307 SECONDARY_EXEC_TSC_SCALING
;
1310 static inline bool cpu_has_vmx_vmfunc(void)
1312 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1313 SECONDARY_EXEC_ENABLE_VMFUNC
;
1316 static inline bool report_flexpriority(void)
1318 return flexpriority_enabled
;
1321 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1323 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1326 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1328 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1331 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1333 return (vmcs12
->cpu_based_vm_exec_control
&
1334 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1335 (vmcs12
->secondary_vm_exec_control
& bit
);
1338 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1340 return vmcs12
->pin_based_vm_exec_control
&
1341 PIN_BASED_VMX_PREEMPTION_TIMER
;
1344 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1346 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1349 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1351 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
1354 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1356 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1359 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1361 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1364 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1366 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1369 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1371 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1374 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1376 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1379 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1381 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1384 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1386 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1389 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1391 return nested_cpu_has_vmfunc(vmcs12
) &&
1392 (vmcs12
->vm_function_control
&
1393 VMX_VMFUNC_EPTP_SWITCHING
);
1396 static inline bool is_nmi(u32 intr_info
)
1398 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1399 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1402 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1404 unsigned long exit_qualification
);
1405 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1406 struct vmcs12
*vmcs12
,
1407 u32 reason
, unsigned long qualification
);
1409 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1413 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1414 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1419 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1425 } operand
= { vpid
, 0, gva
};
1427 asm volatile (__ex(ASM_VMX_INVVPID
)
1428 /* CF==1 or ZF==1 --> rc = -1 */
1429 "; ja 1f ; ud2 ; 1:"
1430 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1433 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1437 } operand
= {eptp
, gpa
};
1439 asm volatile (__ex(ASM_VMX_INVEPT
)
1440 /* CF==1 or ZF==1 --> rc = -1 */
1441 "; ja 1f ; ud2 ; 1:\n"
1442 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1445 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1449 i
= __find_msr_index(vmx
, msr
);
1451 return &vmx
->guest_msrs
[i
];
1455 static void vmcs_clear(struct vmcs
*vmcs
)
1457 u64 phys_addr
= __pa(vmcs
);
1460 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1461 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1464 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1468 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1470 vmcs_clear(loaded_vmcs
->vmcs
);
1471 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1472 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1473 loaded_vmcs
->cpu
= -1;
1474 loaded_vmcs
->launched
= 0;
1477 static void vmcs_load(struct vmcs
*vmcs
)
1479 u64 phys_addr
= __pa(vmcs
);
1482 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1483 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1486 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1490 #ifdef CONFIG_KEXEC_CORE
1492 * This bitmap is used to indicate whether the vmclear
1493 * operation is enabled on all cpus. All disabled by
1496 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1498 static inline void crash_enable_local_vmclear(int cpu
)
1500 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1503 static inline void crash_disable_local_vmclear(int cpu
)
1505 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1508 static inline int crash_local_vmclear_enabled(int cpu
)
1510 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1513 static void crash_vmclear_local_loaded_vmcss(void)
1515 int cpu
= raw_smp_processor_id();
1516 struct loaded_vmcs
*v
;
1518 if (!crash_local_vmclear_enabled(cpu
))
1521 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1522 loaded_vmcss_on_cpu_link
)
1523 vmcs_clear(v
->vmcs
);
1526 static inline void crash_enable_local_vmclear(int cpu
) { }
1527 static inline void crash_disable_local_vmclear(int cpu
) { }
1528 #endif /* CONFIG_KEXEC_CORE */
1530 static void __loaded_vmcs_clear(void *arg
)
1532 struct loaded_vmcs
*loaded_vmcs
= arg
;
1533 int cpu
= raw_smp_processor_id();
1535 if (loaded_vmcs
->cpu
!= cpu
)
1536 return; /* vcpu migration can race with cpu offline */
1537 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1538 per_cpu(current_vmcs
, cpu
) = NULL
;
1539 crash_disable_local_vmclear(cpu
);
1540 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1543 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1544 * is before setting loaded_vmcs->vcpu to -1 which is done in
1545 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1546 * then adds the vmcs into percpu list before it is deleted.
1550 loaded_vmcs_init(loaded_vmcs
);
1551 crash_enable_local_vmclear(cpu
);
1554 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1556 int cpu
= loaded_vmcs
->cpu
;
1559 smp_call_function_single(cpu
,
1560 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1563 static inline void vpid_sync_vcpu_single(int vpid
)
1568 if (cpu_has_vmx_invvpid_single())
1569 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1572 static inline void vpid_sync_vcpu_global(void)
1574 if (cpu_has_vmx_invvpid_global())
1575 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1578 static inline void vpid_sync_context(int vpid
)
1580 if (cpu_has_vmx_invvpid_single())
1581 vpid_sync_vcpu_single(vpid
);
1583 vpid_sync_vcpu_global();
1586 static inline void ept_sync_global(void)
1588 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1591 static inline void ept_sync_context(u64 eptp
)
1593 if (cpu_has_vmx_invept_context())
1594 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1599 static __always_inline
void vmcs_check16(unsigned long field
)
1601 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1602 "16-bit accessor invalid for 64-bit field");
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1604 "16-bit accessor invalid for 64-bit high field");
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1606 "16-bit accessor invalid for 32-bit high field");
1607 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1608 "16-bit accessor invalid for natural width field");
1611 static __always_inline
void vmcs_check32(unsigned long field
)
1613 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1614 "32-bit accessor invalid for 16-bit field");
1615 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1616 "32-bit accessor invalid for natural width field");
1619 static __always_inline
void vmcs_check64(unsigned long field
)
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1622 "64-bit accessor invalid for 16-bit field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1624 "64-bit accessor invalid for 64-bit high field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1626 "64-bit accessor invalid for 32-bit field");
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1628 "64-bit accessor invalid for natural width field");
1631 static __always_inline
void vmcs_checkl(unsigned long field
)
1633 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1634 "Natural width accessor invalid for 16-bit field");
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1636 "Natural width accessor invalid for 64-bit field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1638 "Natural width accessor invalid for 64-bit high field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1640 "Natural width accessor invalid for 32-bit field");
1643 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1645 unsigned long value
;
1647 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1648 : "=a"(value
) : "d"(field
) : "cc");
1652 static __always_inline u16
vmcs_read16(unsigned long field
)
1654 vmcs_check16(field
);
1655 return __vmcs_readl(field
);
1658 static __always_inline u32
vmcs_read32(unsigned long field
)
1660 vmcs_check32(field
);
1661 return __vmcs_readl(field
);
1664 static __always_inline u64
vmcs_read64(unsigned long field
)
1666 vmcs_check64(field
);
1667 #ifdef CONFIG_X86_64
1668 return __vmcs_readl(field
);
1670 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1674 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1677 return __vmcs_readl(field
);
1680 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1682 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1683 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1687 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1691 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1692 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1693 if (unlikely(error
))
1694 vmwrite_error(field
, value
);
1697 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1699 vmcs_check16(field
);
1700 __vmcs_writel(field
, value
);
1703 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1705 vmcs_check32(field
);
1706 __vmcs_writel(field
, value
);
1709 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1711 vmcs_check64(field
);
1712 __vmcs_writel(field
, value
);
1713 #ifndef CONFIG_X86_64
1715 __vmcs_writel(field
+1, value
>> 32);
1719 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1722 __vmcs_writel(field
, value
);
1725 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1727 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1728 "vmcs_clear_bits does not support 64-bit fields");
1729 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1732 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1734 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1735 "vmcs_set_bits does not support 64-bit fields");
1736 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1739 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1741 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1744 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1746 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1747 vmx
->vm_entry_controls_shadow
= val
;
1750 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1752 if (vmx
->vm_entry_controls_shadow
!= val
)
1753 vm_entry_controls_init(vmx
, val
);
1756 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1758 return vmx
->vm_entry_controls_shadow
;
1762 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1764 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1767 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1769 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1772 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1774 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1777 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1779 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1780 vmx
->vm_exit_controls_shadow
= val
;
1783 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1785 if (vmx
->vm_exit_controls_shadow
!= val
)
1786 vm_exit_controls_init(vmx
, val
);
1789 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1791 return vmx
->vm_exit_controls_shadow
;
1795 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1797 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1800 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1802 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1805 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1807 vmx
->segment_cache
.bitmask
= 0;
1810 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1814 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1816 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1817 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1818 vmx
->segment_cache
.bitmask
= 0;
1820 ret
= vmx
->segment_cache
.bitmask
& mask
;
1821 vmx
->segment_cache
.bitmask
|= mask
;
1825 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1827 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1829 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1830 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1834 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1836 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1838 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1839 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1843 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1845 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1847 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1848 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1852 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1854 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1856 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1857 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1861 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1865 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1866 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1867 if ((vcpu
->guest_debug
&
1868 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1869 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1870 eb
|= 1u << BP_VECTOR
;
1871 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1874 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1876 /* When we are running a nested L2 guest and L1 specified for it a
1877 * certain exception bitmap, we must trap the same exceptions and pass
1878 * them to L1. When running L2, we will only handle the exceptions
1879 * specified above if L1 did not want them.
1881 if (is_guest_mode(vcpu
))
1882 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1884 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1888 * Check if MSR is intercepted for currently loaded MSR bitmap.
1890 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, u32 msr
)
1892 unsigned long *msr_bitmap
;
1893 int f
= sizeof(unsigned long);
1895 if (!cpu_has_vmx_msr_bitmap())
1898 msr_bitmap
= to_vmx(vcpu
)->loaded_vmcs
->msr_bitmap
;
1900 if (msr
<= 0x1fff) {
1901 return !!test_bit(msr
, msr_bitmap
+ 0x800 / f
);
1902 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
1904 return !!test_bit(msr
, msr_bitmap
+ 0xc00 / f
);
1911 * Check if MSR is intercepted for L01 MSR bitmap.
1913 static bool msr_write_intercepted_l01(struct kvm_vcpu
*vcpu
, u32 msr
)
1915 unsigned long *msr_bitmap
;
1916 int f
= sizeof(unsigned long);
1918 if (!cpu_has_vmx_msr_bitmap())
1921 msr_bitmap
= to_vmx(vcpu
)->vmcs01
.msr_bitmap
;
1923 if (msr
<= 0x1fff) {
1924 return !!test_bit(msr
, msr_bitmap
+ 0x800 / f
);
1925 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
1927 return !!test_bit(msr
, msr_bitmap
+ 0xc00 / f
);
1933 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1934 unsigned long entry
, unsigned long exit
)
1936 vm_entry_controls_clearbit(vmx
, entry
);
1937 vm_exit_controls_clearbit(vmx
, exit
);
1940 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1943 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1947 if (cpu_has_load_ia32_efer
) {
1948 clear_atomic_switch_msr_special(vmx
,
1949 VM_ENTRY_LOAD_IA32_EFER
,
1950 VM_EXIT_LOAD_IA32_EFER
);
1954 case MSR_CORE_PERF_GLOBAL_CTRL
:
1955 if (cpu_has_load_perf_global_ctrl
) {
1956 clear_atomic_switch_msr_special(vmx
,
1957 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1958 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1964 for (i
= 0; i
< m
->nr
; ++i
)
1965 if (m
->guest
[i
].index
== msr
)
1971 m
->guest
[i
] = m
->guest
[m
->nr
];
1972 m
->host
[i
] = m
->host
[m
->nr
];
1973 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1974 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1977 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1978 unsigned long entry
, unsigned long exit
,
1979 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1980 u64 guest_val
, u64 host_val
)
1982 vmcs_write64(guest_val_vmcs
, guest_val
);
1983 vmcs_write64(host_val_vmcs
, host_val
);
1984 vm_entry_controls_setbit(vmx
, entry
);
1985 vm_exit_controls_setbit(vmx
, exit
);
1988 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1989 u64 guest_val
, u64 host_val
)
1992 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1996 if (cpu_has_load_ia32_efer
) {
1997 add_atomic_switch_msr_special(vmx
,
1998 VM_ENTRY_LOAD_IA32_EFER
,
1999 VM_EXIT_LOAD_IA32_EFER
,
2002 guest_val
, host_val
);
2006 case MSR_CORE_PERF_GLOBAL_CTRL
:
2007 if (cpu_has_load_perf_global_ctrl
) {
2008 add_atomic_switch_msr_special(vmx
,
2009 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
2010 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
2011 GUEST_IA32_PERF_GLOBAL_CTRL
,
2012 HOST_IA32_PERF_GLOBAL_CTRL
,
2013 guest_val
, host_val
);
2017 case MSR_IA32_PEBS_ENABLE
:
2018 /* PEBS needs a quiescent period after being disabled (to write
2019 * a record). Disabling PEBS through VMX MSR swapping doesn't
2020 * provide that period, so a CPU could write host's record into
2023 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
2026 for (i
= 0; i
< m
->nr
; ++i
)
2027 if (m
->guest
[i
].index
== msr
)
2030 if (i
== NR_AUTOLOAD_MSRS
) {
2031 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2032 "Can't add msr %x\n", msr
);
2034 } else if (i
== m
->nr
) {
2036 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2037 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2040 m
->guest
[i
].index
= msr
;
2041 m
->guest
[i
].value
= guest_val
;
2042 m
->host
[i
].index
= msr
;
2043 m
->host
[i
].value
= host_val
;
2046 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2048 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2049 u64 ignore_bits
= 0;
2053 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2054 * host CPUID is more efficient than testing guest CPUID
2055 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2057 if (boot_cpu_has(X86_FEATURE_SMEP
))
2058 guest_efer
|= EFER_NX
;
2059 else if (!(guest_efer
& EFER_NX
))
2060 ignore_bits
|= EFER_NX
;
2064 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2066 ignore_bits
|= EFER_SCE
;
2067 #ifdef CONFIG_X86_64
2068 ignore_bits
|= EFER_LMA
| EFER_LME
;
2069 /* SCE is meaningful only in long mode on Intel */
2070 if (guest_efer
& EFER_LMA
)
2071 ignore_bits
&= ~(u64
)EFER_SCE
;
2074 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2077 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2078 * On CPUs that support "load IA32_EFER", always switch EFER
2079 * atomically, since it's faster than switching it manually.
2081 if (cpu_has_load_ia32_efer
||
2082 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2083 if (!(guest_efer
& EFER_LMA
))
2084 guest_efer
&= ~EFER_LME
;
2085 if (guest_efer
!= host_efer
)
2086 add_atomic_switch_msr(vmx
, MSR_EFER
,
2087 guest_efer
, host_efer
);
2090 guest_efer
&= ~ignore_bits
;
2091 guest_efer
|= host_efer
& ignore_bits
;
2093 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2094 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2100 #ifdef CONFIG_X86_32
2102 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2103 * VMCS rather than the segment table. KVM uses this helper to figure
2104 * out the current bases to poke them into the VMCS before entry.
2106 static unsigned long segment_base(u16 selector
)
2108 struct desc_struct
*table
;
2111 if (!(selector
& ~SEGMENT_RPL_MASK
))
2114 table
= get_current_gdt_ro();
2116 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2117 u16 ldt_selector
= kvm_read_ldt();
2119 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2122 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2124 v
= get_desc_base(&table
[selector
>> 3]);
2129 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2131 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2134 if (vmx
->host_state
.loaded
)
2137 vmx
->host_state
.loaded
= 1;
2139 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2140 * allow segment selectors with cpl > 0 or ti == 1.
2142 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2143 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2144 savesegment(fs
, vmx
->host_state
.fs_sel
);
2145 if (!(vmx
->host_state
.fs_sel
& 7)) {
2146 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2147 vmx
->host_state
.fs_reload_needed
= 0;
2149 vmcs_write16(HOST_FS_SELECTOR
, 0);
2150 vmx
->host_state
.fs_reload_needed
= 1;
2152 savesegment(gs
, vmx
->host_state
.gs_sel
);
2153 if (!(vmx
->host_state
.gs_sel
& 7))
2154 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2156 vmcs_write16(HOST_GS_SELECTOR
, 0);
2157 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2160 #ifdef CONFIG_X86_64
2161 savesegment(ds
, vmx
->host_state
.ds_sel
);
2162 savesegment(es
, vmx
->host_state
.es_sel
);
2165 #ifdef CONFIG_X86_64
2166 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2167 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2169 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2170 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2173 #ifdef CONFIG_X86_64
2174 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2175 if (is_long_mode(&vmx
->vcpu
))
2176 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2178 if (boot_cpu_has(X86_FEATURE_MPX
))
2179 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2180 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2181 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2182 vmx
->guest_msrs
[i
].data
,
2183 vmx
->guest_msrs
[i
].mask
);
2186 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2188 if (!vmx
->host_state
.loaded
)
2191 ++vmx
->vcpu
.stat
.host_state_reload
;
2192 vmx
->host_state
.loaded
= 0;
2193 #ifdef CONFIG_X86_64
2194 if (is_long_mode(&vmx
->vcpu
))
2195 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2197 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2198 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2199 #ifdef CONFIG_X86_64
2200 load_gs_index(vmx
->host_state
.gs_sel
);
2202 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2205 if (vmx
->host_state
.fs_reload_needed
)
2206 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2207 #ifdef CONFIG_X86_64
2208 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2209 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2210 loadsegment(es
, vmx
->host_state
.es_sel
);
2213 invalidate_tss_limit();
2214 #ifdef CONFIG_X86_64
2215 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2217 if (vmx
->host_state
.msr_host_bndcfgs
)
2218 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2219 load_fixmap_gdt(raw_smp_processor_id());
2222 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2225 __vmx_load_host_state(vmx
);
2229 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2231 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2232 struct pi_desc old
, new;
2236 * In case of hot-plug or hot-unplug, we may have to undo
2237 * vmx_vcpu_pi_put even if there is no assigned device. And we
2238 * always keep PI.NDST up to date for simplicity: it makes the
2239 * code easier, and CPU migration is not a fast path.
2241 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2245 * First handle the simple case where no cmpxchg is necessary; just
2246 * allow posting non-urgent interrupts.
2248 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2249 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2250 * expects the VCPU to be on the blocked_vcpu_list that matches
2253 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2255 pi_clear_sn(pi_desc
);
2259 /* The full case. */
2261 old
.control
= new.control
= pi_desc
->control
;
2263 dest
= cpu_physical_id(cpu
);
2265 if (x2apic_enabled())
2268 new.ndst
= (dest
<< 8) & 0xFF00;
2271 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2272 new.control
) != old
.control
);
2275 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2277 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2278 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2282 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2283 * vcpu mutex is already taken.
2285 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2287 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2288 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2290 if (!already_loaded
) {
2291 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2292 local_irq_disable();
2293 crash_disable_local_vmclear(cpu
);
2296 * Read loaded_vmcs->cpu should be before fetching
2297 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2298 * See the comments in __loaded_vmcs_clear().
2302 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2303 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2304 crash_enable_local_vmclear(cpu
);
2308 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2309 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2310 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2311 indirect_branch_prediction_barrier();
2314 if (!already_loaded
) {
2315 void *gdt
= get_current_gdt_ro();
2316 unsigned long sysenter_esp
;
2318 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2321 * Linux uses per-cpu TSS and GDT, so set these when switching
2322 * processors. See 22.2.4.
2324 vmcs_writel(HOST_TR_BASE
,
2325 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
2326 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2329 * VM exits change the host TR limit to 0x67 after a VM
2330 * exit. This is okay, since 0x67 covers everything except
2331 * the IO bitmap and have have code to handle the IO bitmap
2332 * being lost after a VM exit.
2334 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2336 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2337 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2339 vmx
->loaded_vmcs
->cpu
= cpu
;
2342 /* Setup TSC multiplier */
2343 if (kvm_has_tsc_control
&&
2344 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2345 decache_tsc_multiplier(vmx
);
2347 vmx_vcpu_pi_load(vcpu
, cpu
);
2348 vmx
->host_pkru
= read_pkru();
2349 vmx
->host_debugctlmsr
= get_debugctlmsr();
2352 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2354 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2356 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2357 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2358 !kvm_vcpu_apicv_active(vcpu
))
2361 /* Set SN when the vCPU is preempted */
2362 if (vcpu
->preempted
)
2366 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2368 vmx_vcpu_pi_put(vcpu
);
2370 __vmx_load_host_state(to_vmx(vcpu
));
2373 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2375 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2378 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2381 * Return the cr0 value that a nested guest would read. This is a combination
2382 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2383 * its hypervisor (cr0_read_shadow).
2385 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2387 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2388 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2390 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2392 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2393 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2396 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2398 unsigned long rflags
, save_rflags
;
2400 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2401 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2402 rflags
= vmcs_readl(GUEST_RFLAGS
);
2403 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2404 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2405 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2406 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2408 to_vmx(vcpu
)->rflags
= rflags
;
2410 return to_vmx(vcpu
)->rflags
;
2413 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2415 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2417 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2418 to_vmx(vcpu
)->rflags
= rflags
;
2419 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2420 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2421 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2423 vmcs_writel(GUEST_RFLAGS
, rflags
);
2425 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2426 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2429 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2431 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2434 if (interruptibility
& GUEST_INTR_STATE_STI
)
2435 ret
|= KVM_X86_SHADOW_INT_STI
;
2436 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2437 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2442 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2444 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2445 u32 interruptibility
= interruptibility_old
;
2447 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2449 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2450 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2451 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2452 interruptibility
|= GUEST_INTR_STATE_STI
;
2454 if ((interruptibility
!= interruptibility_old
))
2455 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2458 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2462 rip
= kvm_rip_read(vcpu
);
2463 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2464 kvm_rip_write(vcpu
, rip
);
2466 /* skipping an emulated instruction also counts */
2467 vmx_set_interrupt_shadow(vcpu
, 0);
2470 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2471 unsigned long exit_qual
)
2473 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2474 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2475 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2477 if (vcpu
->arch
.exception
.has_error_code
) {
2478 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2479 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2482 if (kvm_exception_is_soft(nr
))
2483 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2485 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2487 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2488 vmx_get_nmi_mask(vcpu
))
2489 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2491 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2495 * KVM wants to inject page-faults which it got to the guest. This function
2496 * checks whether in a nested guest, we need to inject them to L1 or L2.
2498 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
2500 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2501 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2503 if (nr
== PF_VECTOR
) {
2504 if (vcpu
->arch
.exception
.nested_apf
) {
2505 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
2509 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2510 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2511 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2512 * can be written only when inject_pending_event runs. This should be
2513 * conditional on a new capability---if the capability is disabled,
2514 * kvm_multiple_exception would write the ancillary information to
2515 * CR2 or DR6, for backwards ABI-compatibility.
2517 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2518 vcpu
->arch
.exception
.error_code
)) {
2519 *exit_qual
= vcpu
->arch
.cr2
;
2523 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2524 if (nr
== DB_VECTOR
)
2525 *exit_qual
= vcpu
->arch
.dr6
;
2535 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2537 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2538 unsigned nr
= vcpu
->arch
.exception
.nr
;
2539 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2540 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2541 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2543 if (has_error_code
) {
2544 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2545 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2548 if (vmx
->rmode
.vm86_active
) {
2550 if (kvm_exception_is_soft(nr
))
2551 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2552 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2553 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2557 if (kvm_exception_is_soft(nr
)) {
2558 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2559 vmx
->vcpu
.arch
.event_exit_inst_len
);
2560 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2562 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2564 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2567 static bool vmx_rdtscp_supported(void)
2569 return cpu_has_vmx_rdtscp();
2572 static bool vmx_invpcid_supported(void)
2574 return cpu_has_vmx_invpcid() && enable_ept
;
2578 * Swap MSR entry in host/guest MSR entry array.
2580 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2582 struct shared_msr_entry tmp
;
2584 tmp
= vmx
->guest_msrs
[to
];
2585 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2586 vmx
->guest_msrs
[from
] = tmp
;
2590 * Set up the vmcs to automatically save and restore system
2591 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2592 * mode, as fiddling with msrs is very expensive.
2594 static void setup_msrs(struct vcpu_vmx
*vmx
)
2596 int save_nmsrs
, index
;
2599 #ifdef CONFIG_X86_64
2600 if (is_long_mode(&vmx
->vcpu
)) {
2601 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2603 move_msr_up(vmx
, index
, save_nmsrs
++);
2604 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2606 move_msr_up(vmx
, index
, save_nmsrs
++);
2607 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2609 move_msr_up(vmx
, index
, save_nmsrs
++);
2610 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2611 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2612 move_msr_up(vmx
, index
, save_nmsrs
++);
2614 * MSR_STAR is only needed on long mode guests, and only
2615 * if efer.sce is enabled.
2617 index
= __find_msr_index(vmx
, MSR_STAR
);
2618 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2619 move_msr_up(vmx
, index
, save_nmsrs
++);
2622 index
= __find_msr_index(vmx
, MSR_EFER
);
2623 if (index
>= 0 && update_transition_efer(vmx
, index
))
2624 move_msr_up(vmx
, index
, save_nmsrs
++);
2626 vmx
->save_nmsrs
= save_nmsrs
;
2628 if (cpu_has_vmx_msr_bitmap())
2629 vmx_update_msr_bitmap(&vmx
->vcpu
);
2633 * reads and returns guest's timestamp counter "register"
2634 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2635 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2637 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2639 u64 host_tsc
, tsc_offset
;
2642 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2643 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2647 * writes 'offset' into guest's timestamp counter offset register
2649 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2651 if (is_guest_mode(vcpu
)) {
2653 * We're here if L1 chose not to trap WRMSR to TSC. According
2654 * to the spec, this should set L1's TSC; The offset that L1
2655 * set for L2 remains unchanged, and still needs to be added
2656 * to the newly set TSC to get L2's TSC.
2658 struct vmcs12
*vmcs12
;
2659 /* recalculate vmcs02.TSC_OFFSET: */
2660 vmcs12
= get_vmcs12(vcpu
);
2661 vmcs_write64(TSC_OFFSET
, offset
+
2662 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2663 vmcs12
->tsc_offset
: 0));
2665 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2666 vmcs_read64(TSC_OFFSET
), offset
);
2667 vmcs_write64(TSC_OFFSET
, offset
);
2672 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2673 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2674 * all guests if the "nested" module option is off, and can also be disabled
2675 * for a single guest by disabling its VMX cpuid bit.
2677 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2679 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2683 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2684 * returned for the various VMX controls MSRs when nested VMX is enabled.
2685 * The same values should also be used to verify that vmcs12 control fields are
2686 * valid during nested entry from L1 to L2.
2687 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2688 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2689 * bit in the high half is on if the corresponding bit in the control field
2690 * may be on. See also vmx_control_verify().
2692 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2695 * Note that as a general rule, the high half of the MSRs (bits in
2696 * the control fields which may be 1) should be initialized by the
2697 * intersection of the underlying hardware's MSR (i.e., features which
2698 * can be supported) and the list of features we want to expose -
2699 * because they are known to be properly supported in our code.
2700 * Also, usually, the low half of the MSRs (bits which must be 1) can
2701 * be set to 0, meaning that L1 may turn off any of these bits. The
2702 * reason is that if one of these bits is necessary, it will appear
2703 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2704 * fields of vmcs01 and vmcs02, will turn these bits off - and
2705 * nested_vmx_exit_reflected() will not pass related exits to L1.
2706 * These rules have exceptions below.
2709 /* pin-based controls */
2710 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2711 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2712 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2713 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2714 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2715 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2716 PIN_BASED_EXT_INTR_MASK
|
2717 PIN_BASED_NMI_EXITING
|
2718 PIN_BASED_VIRTUAL_NMIS
;
2719 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2720 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2721 PIN_BASED_VMX_PREEMPTION_TIMER
;
2722 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2723 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2724 PIN_BASED_POSTED_INTR
;
2727 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2728 vmx
->nested
.nested_vmx_exit_ctls_low
,
2729 vmx
->nested
.nested_vmx_exit_ctls_high
);
2730 vmx
->nested
.nested_vmx_exit_ctls_low
=
2731 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2733 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2734 #ifdef CONFIG_X86_64
2735 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2737 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2738 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2739 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2740 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2741 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2743 if (kvm_mpx_supported())
2744 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2746 /* We support free control of debug control saving. */
2747 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2749 /* entry controls */
2750 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2751 vmx
->nested
.nested_vmx_entry_ctls_low
,
2752 vmx
->nested
.nested_vmx_entry_ctls_high
);
2753 vmx
->nested
.nested_vmx_entry_ctls_low
=
2754 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2755 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2756 #ifdef CONFIG_X86_64
2757 VM_ENTRY_IA32E_MODE
|
2759 VM_ENTRY_LOAD_IA32_PAT
;
2760 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2761 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2762 if (kvm_mpx_supported())
2763 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2765 /* We support free control of debug control loading. */
2766 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2768 /* cpu-based controls */
2769 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2770 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2771 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2772 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2773 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2774 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2775 CPU_BASED_VIRTUAL_INTR_PENDING
|
2776 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2777 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2778 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2779 CPU_BASED_CR3_STORE_EXITING
|
2780 #ifdef CONFIG_X86_64
2781 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2783 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2784 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2785 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2786 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2787 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2789 * We can allow some features even when not supported by the
2790 * hardware. For example, L1 can specify an MSR bitmap - and we
2791 * can use it to avoid exits to L1 - even when L0 runs L2
2792 * without MSR bitmaps.
2794 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2795 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2796 CPU_BASED_USE_MSR_BITMAPS
;
2798 /* We support free control of CR3 access interception. */
2799 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2800 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2803 * secondary cpu-based controls. Do not include those that
2804 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2806 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2807 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2808 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2809 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2810 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2811 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2812 SECONDARY_EXEC_DESC
|
2813 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2814 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2815 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2816 SECONDARY_EXEC_WBINVD_EXITING
;
2819 /* nested EPT: emulate EPT also to L1 */
2820 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2821 SECONDARY_EXEC_ENABLE_EPT
;
2822 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2823 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2824 if (cpu_has_vmx_ept_execute_only())
2825 vmx
->nested
.nested_vmx_ept_caps
|=
2826 VMX_EPT_EXECUTE_ONLY_BIT
;
2827 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2828 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2829 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2830 VMX_EPT_1GB_PAGE_BIT
;
2831 if (enable_ept_ad_bits
) {
2832 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2833 SECONDARY_EXEC_ENABLE_PML
;
2834 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2838 if (cpu_has_vmx_vmfunc()) {
2839 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2840 SECONDARY_EXEC_ENABLE_VMFUNC
;
2842 * Advertise EPTP switching unconditionally
2843 * since we emulate it
2846 vmx
->nested
.nested_vmx_vmfunc_controls
=
2847 VMX_VMFUNC_EPTP_SWITCHING
;
2851 * Old versions of KVM use the single-context version without
2852 * checking for support, so declare that it is supported even
2853 * though it is treated as global context. The alternative is
2854 * not failing the single-context invvpid, and it is worse.
2857 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2858 SECONDARY_EXEC_ENABLE_VPID
;
2859 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2860 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2863 if (enable_unrestricted_guest
)
2864 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2865 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2867 /* miscellaneous data */
2868 rdmsr(MSR_IA32_VMX_MISC
,
2869 vmx
->nested
.nested_vmx_misc_low
,
2870 vmx
->nested
.nested_vmx_misc_high
);
2871 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2872 vmx
->nested
.nested_vmx_misc_low
|=
2873 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2874 VMX_MISC_ACTIVITY_HLT
;
2875 vmx
->nested
.nested_vmx_misc_high
= 0;
2878 * This MSR reports some information about VMX support. We
2879 * should return information about the VMX we emulate for the
2880 * guest, and the VMCS structure we give it - not about the
2881 * VMX support of the underlying hardware.
2883 vmx
->nested
.nested_vmx_basic
=
2885 VMX_BASIC_TRUE_CTLS
|
2886 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2887 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2889 if (cpu_has_vmx_basic_inout())
2890 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2893 * These MSRs specify bits which the guest must keep fixed on
2894 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2895 * We picked the standard core2 setting.
2897 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2898 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2899 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2900 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2902 /* These MSRs specify bits which the guest must keep fixed off. */
2903 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2904 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2906 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2907 vmx
->nested
.nested_vmx_vmcs_enum
= VMCS12_MAX_FIELD_INDEX
<< 1;
2911 * if fixed0[i] == 1: val[i] must be 1
2912 * if fixed1[i] == 0: val[i] must be 0
2914 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2916 return ((val
& fixed1
) | fixed0
) == val
;
2919 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2921 return fixed_bits_valid(control
, low
, high
);
2924 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2926 return low
| ((u64
)high
<< 32);
2929 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2934 return (superset
| subset
) == superset
;
2937 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2939 const u64 feature_and_reserved
=
2940 /* feature (except bit 48; see below) */
2941 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2943 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2944 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2946 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2950 * KVM does not emulate a version of VMX that constrains physical
2951 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2953 if (data
& BIT_ULL(48))
2956 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2957 vmx_basic_vmcs_revision_id(data
))
2960 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2963 vmx
->nested
.nested_vmx_basic
= data
;
2968 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2973 switch (msr_index
) {
2974 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2975 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2976 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2978 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2979 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2980 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2982 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2983 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2984 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2986 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2987 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2988 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2990 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2991 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2992 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2998 supported
= vmx_control_msr(*lowp
, *highp
);
3000 /* Check must-be-1 bits are still 1. */
3001 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3004 /* Check must-be-0 bits are still 0. */
3005 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3009 *highp
= data
>> 32;
3013 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3015 const u64 feature_and_reserved_bits
=
3017 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3018 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3020 GENMASK_ULL(13, 9) | BIT_ULL(31);
3023 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3024 vmx
->nested
.nested_vmx_misc_high
);
3026 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3029 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3030 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3031 vmx_misc_preemption_timer_rate(data
) !=
3032 vmx_misc_preemption_timer_rate(vmx_misc
))
3035 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3038 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3041 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3044 vmx
->nested
.nested_vmx_misc_low
= data
;
3045 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3049 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3051 u64 vmx_ept_vpid_cap
;
3053 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3054 vmx
->nested
.nested_vmx_vpid_caps
);
3056 /* Every bit is either reserved or a feature bit. */
3057 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3060 vmx
->nested
.nested_vmx_ept_caps
= data
;
3061 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3065 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3069 switch (msr_index
) {
3070 case MSR_IA32_VMX_CR0_FIXED0
:
3071 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3073 case MSR_IA32_VMX_CR4_FIXED0
:
3074 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3081 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3082 * must be 1 in the restored value.
3084 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3092 * Called when userspace is restoring VMX MSRs.
3094 * Returns 0 on success, non-0 otherwise.
3096 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3098 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3100 switch (msr_index
) {
3101 case MSR_IA32_VMX_BASIC
:
3102 return vmx_restore_vmx_basic(vmx
, data
);
3103 case MSR_IA32_VMX_PINBASED_CTLS
:
3104 case MSR_IA32_VMX_PROCBASED_CTLS
:
3105 case MSR_IA32_VMX_EXIT_CTLS
:
3106 case MSR_IA32_VMX_ENTRY_CTLS
:
3108 * The "non-true" VMX capability MSRs are generated from the
3109 * "true" MSRs, so we do not support restoring them directly.
3111 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3112 * should restore the "true" MSRs with the must-be-1 bits
3113 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3114 * DEFAULT SETTINGS".
3117 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3118 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3119 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3120 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3121 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3122 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3123 case MSR_IA32_VMX_MISC
:
3124 return vmx_restore_vmx_misc(vmx
, data
);
3125 case MSR_IA32_VMX_CR0_FIXED0
:
3126 case MSR_IA32_VMX_CR4_FIXED0
:
3127 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3128 case MSR_IA32_VMX_CR0_FIXED1
:
3129 case MSR_IA32_VMX_CR4_FIXED1
:
3131 * These MSRs are generated based on the vCPU's CPUID, so we
3132 * do not support restoring them directly.
3135 case MSR_IA32_VMX_EPT_VPID_CAP
:
3136 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3137 case MSR_IA32_VMX_VMCS_ENUM
:
3138 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3142 * The rest of the VMX capability MSRs do not support restore.
3148 /* Returns 0 on success, non-0 otherwise. */
3149 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3151 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3153 switch (msr_index
) {
3154 case MSR_IA32_VMX_BASIC
:
3155 *pdata
= vmx
->nested
.nested_vmx_basic
;
3157 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3158 case MSR_IA32_VMX_PINBASED_CTLS
:
3159 *pdata
= vmx_control_msr(
3160 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3161 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3162 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3163 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3165 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3166 case MSR_IA32_VMX_PROCBASED_CTLS
:
3167 *pdata
= vmx_control_msr(
3168 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3169 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3170 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3171 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3173 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3174 case MSR_IA32_VMX_EXIT_CTLS
:
3175 *pdata
= vmx_control_msr(
3176 vmx
->nested
.nested_vmx_exit_ctls_low
,
3177 vmx
->nested
.nested_vmx_exit_ctls_high
);
3178 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3179 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3181 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3182 case MSR_IA32_VMX_ENTRY_CTLS
:
3183 *pdata
= vmx_control_msr(
3184 vmx
->nested
.nested_vmx_entry_ctls_low
,
3185 vmx
->nested
.nested_vmx_entry_ctls_high
);
3186 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3187 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3189 case MSR_IA32_VMX_MISC
:
3190 *pdata
= vmx_control_msr(
3191 vmx
->nested
.nested_vmx_misc_low
,
3192 vmx
->nested
.nested_vmx_misc_high
);
3194 case MSR_IA32_VMX_CR0_FIXED0
:
3195 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3197 case MSR_IA32_VMX_CR0_FIXED1
:
3198 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3200 case MSR_IA32_VMX_CR4_FIXED0
:
3201 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3203 case MSR_IA32_VMX_CR4_FIXED1
:
3204 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3206 case MSR_IA32_VMX_VMCS_ENUM
:
3207 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3209 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3210 *pdata
= vmx_control_msr(
3211 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3212 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3214 case MSR_IA32_VMX_EPT_VPID_CAP
:
3215 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3216 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3218 case MSR_IA32_VMX_VMFUNC
:
3219 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3228 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3231 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3233 return !(val
& ~valid_bits
);
3236 static int vmx_get_msr_feature(struct kvm_msr_entry
*msr
)
3242 * Reads an msr value (of 'msr_index') into 'pdata'.
3243 * Returns 0 on success, non-0 otherwise.
3244 * Assumes vcpu_load() was already called.
3246 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3248 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3249 struct shared_msr_entry
*msr
;
3251 switch (msr_info
->index
) {
3252 #ifdef CONFIG_X86_64
3254 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3257 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3259 case MSR_KERNEL_GS_BASE
:
3260 vmx_load_host_state(vmx
);
3261 msr_info
->data
= vmx
->msr_guest_kernel_gs_base
;
3265 return kvm_get_msr_common(vcpu
, msr_info
);
3267 msr_info
->data
= guest_read_tsc(vcpu
);
3269 case MSR_IA32_SPEC_CTRL
:
3270 if (!msr_info
->host_initiated
&&
3271 !guest_cpuid_has(vcpu
, X86_FEATURE_IBRS
) &&
3272 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
3275 msr_info
->data
= to_vmx(vcpu
)->spec_ctrl
;
3277 case MSR_IA32_ARCH_CAPABILITIES
:
3278 if (!msr_info
->host_initiated
&&
3279 !guest_cpuid_has(vcpu
, X86_FEATURE_ARCH_CAPABILITIES
))
3281 msr_info
->data
= to_vmx(vcpu
)->arch_capabilities
;
3283 case MSR_IA32_SYSENTER_CS
:
3284 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3286 case MSR_IA32_SYSENTER_EIP
:
3287 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3289 case MSR_IA32_SYSENTER_ESP
:
3290 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3292 case MSR_IA32_BNDCFGS
:
3293 if (!kvm_mpx_supported() ||
3294 (!msr_info
->host_initiated
&&
3295 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3297 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3299 case MSR_IA32_MCG_EXT_CTL
:
3300 if (!msr_info
->host_initiated
&&
3301 !(vmx
->msr_ia32_feature_control
&
3302 FEATURE_CONTROL_LMCE
))
3304 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3306 case MSR_IA32_FEATURE_CONTROL
:
3307 msr_info
->data
= vmx
->msr_ia32_feature_control
;
3309 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3310 if (!nested_vmx_allowed(vcpu
))
3312 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3314 if (!vmx_xsaves_supported())
3316 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3319 if (!msr_info
->host_initiated
&&
3320 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3322 /* Otherwise falls through */
3324 msr
= find_msr_entry(vmx
, msr_info
->index
);
3326 msr_info
->data
= msr
->data
;
3329 return kvm_get_msr_common(vcpu
, msr_info
);
3335 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3338 * Writes msr value into into the appropriate "register".
3339 * Returns 0 on success, non-0 otherwise.
3340 * Assumes vcpu_load() was already called.
3342 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3344 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3345 struct shared_msr_entry
*msr
;
3347 u32 msr_index
= msr_info
->index
;
3348 u64 data
= msr_info
->data
;
3350 switch (msr_index
) {
3352 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3354 #ifdef CONFIG_X86_64
3356 vmx_segment_cache_clear(vmx
);
3357 vmcs_writel(GUEST_FS_BASE
, data
);
3360 vmx_segment_cache_clear(vmx
);
3361 vmcs_writel(GUEST_GS_BASE
, data
);
3363 case MSR_KERNEL_GS_BASE
:
3364 vmx_load_host_state(vmx
);
3365 vmx
->msr_guest_kernel_gs_base
= data
;
3368 case MSR_IA32_SYSENTER_CS
:
3369 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3371 case MSR_IA32_SYSENTER_EIP
:
3372 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3374 case MSR_IA32_SYSENTER_ESP
:
3375 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3377 case MSR_IA32_BNDCFGS
:
3378 if (!kvm_mpx_supported() ||
3379 (!msr_info
->host_initiated
&&
3380 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3382 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
3383 (data
& MSR_IA32_BNDCFGS_RSVD
))
3385 vmcs_write64(GUEST_BNDCFGS
, data
);
3388 kvm_write_tsc(vcpu
, msr_info
);
3390 case MSR_IA32_SPEC_CTRL
:
3391 if (!msr_info
->host_initiated
&&
3392 !guest_cpuid_has(vcpu
, X86_FEATURE_IBRS
) &&
3393 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
3396 /* The STIBP bit doesn't fault even if it's not advertised */
3397 if (data
& ~(SPEC_CTRL_IBRS
| SPEC_CTRL_STIBP
))
3400 vmx
->spec_ctrl
= data
;
3407 * When it's written (to non-zero) for the first time, pass
3411 * The handling of the MSR bitmap for L2 guests is done in
3412 * nested_vmx_merge_msr_bitmap. We should not touch the
3413 * vmcs02.msr_bitmap here since it gets completely overwritten
3414 * in the merging. We update the vmcs01 here for L1 as well
3415 * since it will end up touching the MSR anyway now.
3417 vmx_disable_intercept_for_msr(vmx
->vmcs01
.msr_bitmap
,
3421 case MSR_IA32_PRED_CMD
:
3422 if (!msr_info
->host_initiated
&&
3423 !guest_cpuid_has(vcpu
, X86_FEATURE_IBPB
) &&
3424 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
3427 if (data
& ~PRED_CMD_IBPB
)
3433 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
3437 * When it's written (to non-zero) for the first time, pass
3441 * The handling of the MSR bitmap for L2 guests is done in
3442 * nested_vmx_merge_msr_bitmap. We should not touch the
3443 * vmcs02.msr_bitmap here since it gets completely overwritten
3446 vmx_disable_intercept_for_msr(vmx
->vmcs01
.msr_bitmap
, MSR_IA32_PRED_CMD
,
3449 case MSR_IA32_ARCH_CAPABILITIES
:
3450 if (!msr_info
->host_initiated
)
3452 vmx
->arch_capabilities
= data
;
3454 case MSR_IA32_CR_PAT
:
3455 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3456 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3458 vmcs_write64(GUEST_IA32_PAT
, data
);
3459 vcpu
->arch
.pat
= data
;
3462 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3464 case MSR_IA32_TSC_ADJUST
:
3465 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3467 case MSR_IA32_MCG_EXT_CTL
:
3468 if ((!msr_info
->host_initiated
&&
3469 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3470 FEATURE_CONTROL_LMCE
)) ||
3471 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3473 vcpu
->arch
.mcg_ext_ctl
= data
;
3475 case MSR_IA32_FEATURE_CONTROL
:
3476 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3477 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3478 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3480 vmx
->msr_ia32_feature_control
= data
;
3481 if (msr_info
->host_initiated
&& data
== 0)
3482 vmx_leave_nested(vcpu
);
3484 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3485 if (!msr_info
->host_initiated
)
3486 return 1; /* they are read-only */
3487 if (!nested_vmx_allowed(vcpu
))
3489 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3491 if (!vmx_xsaves_supported())
3494 * The only supported bit as of Skylake is bit 8, but
3495 * it is not supported on KVM.
3499 vcpu
->arch
.ia32_xss
= data
;
3500 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3501 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3502 vcpu
->arch
.ia32_xss
, host_xss
);
3504 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3507 if (!msr_info
->host_initiated
&&
3508 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3510 /* Check reserved bit, higher 32 bits should be zero */
3511 if ((data
>> 32) != 0)
3513 /* Otherwise falls through */
3515 msr
= find_msr_entry(vmx
, msr_index
);
3517 u64 old_msr_data
= msr
->data
;
3519 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3521 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3525 msr
->data
= old_msr_data
;
3529 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3535 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3537 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3540 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3543 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3545 case VCPU_EXREG_PDPTR
:
3547 ept_save_pdptrs(vcpu
);
3554 static __init
int cpu_has_kvm_support(void)
3556 return cpu_has_vmx();
3559 static __init
int vmx_disabled_by_bios(void)
3563 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3564 if (msr
& FEATURE_CONTROL_LOCKED
) {
3565 /* launched w/ TXT and VMX disabled */
3566 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3569 /* launched w/o TXT and VMX only enabled w/ TXT */
3570 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3571 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3572 && !tboot_enabled()) {
3573 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3574 "activate TXT before enabling KVM\n");
3577 /* launched w/o TXT and VMX disabled */
3578 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3579 && !tboot_enabled())
3586 static void kvm_cpu_vmxon(u64 addr
)
3588 cr4_set_bits(X86_CR4_VMXE
);
3589 intel_pt_handle_vmx(1);
3591 asm volatile (ASM_VMX_VMXON_RAX
3592 : : "a"(&addr
), "m"(addr
)
3596 static int hardware_enable(void)
3598 int cpu
= raw_smp_processor_id();
3599 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3602 if (cr4_read_shadow() & X86_CR4_VMXE
)
3605 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3606 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3607 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3610 * Now we can enable the vmclear operation in kdump
3611 * since the loaded_vmcss_on_cpu list on this cpu
3612 * has been initialized.
3614 * Though the cpu is not in VMX operation now, there
3615 * is no problem to enable the vmclear operation
3616 * for the loaded_vmcss_on_cpu list is empty!
3618 crash_enable_local_vmclear(cpu
);
3620 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3622 test_bits
= FEATURE_CONTROL_LOCKED
;
3623 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3624 if (tboot_enabled())
3625 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3627 if ((old
& test_bits
) != test_bits
) {
3628 /* enable and lock */
3629 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3631 kvm_cpu_vmxon(phys_addr
);
3638 static void vmclear_local_loaded_vmcss(void)
3640 int cpu
= raw_smp_processor_id();
3641 struct loaded_vmcs
*v
, *n
;
3643 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3644 loaded_vmcss_on_cpu_link
)
3645 __loaded_vmcs_clear(v
);
3649 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3652 static void kvm_cpu_vmxoff(void)
3654 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3656 intel_pt_handle_vmx(0);
3657 cr4_clear_bits(X86_CR4_VMXE
);
3660 static void hardware_disable(void)
3662 vmclear_local_loaded_vmcss();
3666 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3667 u32 msr
, u32
*result
)
3669 u32 vmx_msr_low
, vmx_msr_high
;
3670 u32 ctl
= ctl_min
| ctl_opt
;
3672 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3674 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3675 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3677 /* Ensure minimum (required) set of control bits are supported. */
3685 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3687 u32 vmx_msr_low
, vmx_msr_high
;
3689 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3690 return vmx_msr_high
& ctl
;
3693 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3695 u32 vmx_msr_low
, vmx_msr_high
;
3696 u32 min
, opt
, min2
, opt2
;
3697 u32 _pin_based_exec_control
= 0;
3698 u32 _cpu_based_exec_control
= 0;
3699 u32 _cpu_based_2nd_exec_control
= 0;
3700 u32 _vmexit_control
= 0;
3701 u32 _vmentry_control
= 0;
3703 min
= CPU_BASED_HLT_EXITING
|
3704 #ifdef CONFIG_X86_64
3705 CPU_BASED_CR8_LOAD_EXITING
|
3706 CPU_BASED_CR8_STORE_EXITING
|
3708 CPU_BASED_CR3_LOAD_EXITING
|
3709 CPU_BASED_CR3_STORE_EXITING
|
3710 CPU_BASED_UNCOND_IO_EXITING
|
3711 CPU_BASED_MOV_DR_EXITING
|
3712 CPU_BASED_USE_TSC_OFFSETING
|
3713 CPU_BASED_INVLPG_EXITING
|
3714 CPU_BASED_RDPMC_EXITING
;
3716 if (!kvm_mwait_in_guest())
3717 min
|= CPU_BASED_MWAIT_EXITING
|
3718 CPU_BASED_MONITOR_EXITING
;
3720 opt
= CPU_BASED_TPR_SHADOW
|
3721 CPU_BASED_USE_MSR_BITMAPS
|
3722 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3723 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3724 &_cpu_based_exec_control
) < 0)
3726 #ifdef CONFIG_X86_64
3727 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3728 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3729 ~CPU_BASED_CR8_STORE_EXITING
;
3731 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3733 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3734 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3735 SECONDARY_EXEC_WBINVD_EXITING
|
3736 SECONDARY_EXEC_ENABLE_VPID
|
3737 SECONDARY_EXEC_ENABLE_EPT
|
3738 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3739 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3740 SECONDARY_EXEC_DESC
|
3741 SECONDARY_EXEC_RDTSCP
|
3742 SECONDARY_EXEC_ENABLE_INVPCID
|
3743 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3744 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3745 SECONDARY_EXEC_SHADOW_VMCS
|
3746 SECONDARY_EXEC_XSAVES
|
3747 SECONDARY_EXEC_RDSEED_EXITING
|
3748 SECONDARY_EXEC_RDRAND_EXITING
|
3749 SECONDARY_EXEC_ENABLE_PML
|
3750 SECONDARY_EXEC_TSC_SCALING
|
3751 SECONDARY_EXEC_ENABLE_VMFUNC
;
3752 if (adjust_vmx_controls(min2
, opt2
,
3753 MSR_IA32_VMX_PROCBASED_CTLS2
,
3754 &_cpu_based_2nd_exec_control
) < 0)
3757 #ifndef CONFIG_X86_64
3758 if (!(_cpu_based_2nd_exec_control
&
3759 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3760 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3763 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3764 _cpu_based_2nd_exec_control
&= ~(
3765 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3766 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3767 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3769 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP
,
3770 &vmx_capability
.ept
, &vmx_capability
.vpid
);
3772 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3773 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3775 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3776 CPU_BASED_CR3_STORE_EXITING
|
3777 CPU_BASED_INVLPG_EXITING
);
3778 } else if (vmx_capability
.ept
) {
3779 vmx_capability
.ept
= 0;
3780 pr_warn_once("EPT CAP should not exist if not support "
3781 "1-setting enable EPT VM-execution control\n");
3783 if (!(_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_VPID
) &&
3784 vmx_capability
.vpid
) {
3785 vmx_capability
.vpid
= 0;
3786 pr_warn_once("VPID CAP should not exist if not support "
3787 "1-setting enable VPID VM-execution control\n");
3790 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3791 #ifdef CONFIG_X86_64
3792 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3794 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3795 VM_EXIT_CLEAR_BNDCFGS
;
3796 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3797 &_vmexit_control
) < 0)
3800 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3801 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3802 PIN_BASED_VMX_PREEMPTION_TIMER
;
3803 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3804 &_pin_based_exec_control
) < 0)
3807 if (cpu_has_broken_vmx_preemption_timer())
3808 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3809 if (!(_cpu_based_2nd_exec_control
&
3810 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3811 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3813 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3814 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3815 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3816 &_vmentry_control
) < 0)
3819 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3821 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3822 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3825 #ifdef CONFIG_X86_64
3826 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3827 if (vmx_msr_high
& (1u<<16))
3831 /* Require Write-Back (WB) memory type for VMCS accesses. */
3832 if (((vmx_msr_high
>> 18) & 15) != 6)
3835 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3836 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3837 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3838 vmcs_conf
->revision_id
= vmx_msr_low
;
3840 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3841 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3842 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3843 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3844 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3846 cpu_has_load_ia32_efer
=
3847 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3848 VM_ENTRY_LOAD_IA32_EFER
)
3849 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3850 VM_EXIT_LOAD_IA32_EFER
);
3852 cpu_has_load_perf_global_ctrl
=
3853 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3854 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3855 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3856 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3859 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3860 * but due to errata below it can't be used. Workaround is to use
3861 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3863 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3868 * BC86,AAY89,BD102 (model 44)
3872 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3873 switch (boot_cpu_data
.x86_model
) {
3879 cpu_has_load_perf_global_ctrl
= false;
3880 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3881 "does not work properly. Using workaround\n");
3888 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3889 rdmsrl(MSR_IA32_XSS
, host_xss
);
3894 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3896 int node
= cpu_to_node(cpu
);
3900 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3903 vmcs
= page_address(pages
);
3904 memset(vmcs
, 0, vmcs_config
.size
);
3905 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3909 static void free_vmcs(struct vmcs
*vmcs
)
3911 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3915 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3917 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3919 if (!loaded_vmcs
->vmcs
)
3921 loaded_vmcs_clear(loaded_vmcs
);
3922 free_vmcs(loaded_vmcs
->vmcs
);
3923 loaded_vmcs
->vmcs
= NULL
;
3924 if (loaded_vmcs
->msr_bitmap
)
3925 free_page((unsigned long)loaded_vmcs
->msr_bitmap
);
3926 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3929 static struct vmcs
*alloc_vmcs(void)
3931 return alloc_vmcs_cpu(raw_smp_processor_id());
3934 static int alloc_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3936 loaded_vmcs
->vmcs
= alloc_vmcs();
3937 if (!loaded_vmcs
->vmcs
)
3940 loaded_vmcs
->shadow_vmcs
= NULL
;
3941 loaded_vmcs_init(loaded_vmcs
);
3943 if (cpu_has_vmx_msr_bitmap()) {
3944 loaded_vmcs
->msr_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3945 if (!loaded_vmcs
->msr_bitmap
)
3947 memset(loaded_vmcs
->msr_bitmap
, 0xff, PAGE_SIZE
);
3952 free_loaded_vmcs(loaded_vmcs
);
3956 static void free_kvm_area(void)
3960 for_each_possible_cpu(cpu
) {
3961 free_vmcs(per_cpu(vmxarea
, cpu
));
3962 per_cpu(vmxarea
, cpu
) = NULL
;
3966 enum vmcs_field_width
{
3967 VMCS_FIELD_WIDTH_U16
= 0,
3968 VMCS_FIELD_WIDTH_U64
= 1,
3969 VMCS_FIELD_WIDTH_U32
= 2,
3970 VMCS_FIELD_WIDTH_NATURAL_WIDTH
= 3
3973 static inline int vmcs_field_width(unsigned long field
)
3975 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3976 return VMCS_FIELD_WIDTH_U32
;
3977 return (field
>> 13) & 0x3 ;
3980 static inline int vmcs_field_readonly(unsigned long field
)
3982 return (((field
>> 10) & 0x3) == 1);
3985 static void init_vmcs_shadow_fields(void)
3989 for (i
= j
= 0; i
< max_shadow_read_only_fields
; i
++) {
3990 u16 field
= shadow_read_only_fields
[i
];
3991 if (vmcs_field_width(field
) == VMCS_FIELD_WIDTH_U64
&&
3992 (i
+ 1 == max_shadow_read_only_fields
||
3993 shadow_read_only_fields
[i
+ 1] != field
+ 1))
3994 pr_err("Missing field from shadow_read_only_field %x\n",
3997 clear_bit(field
, vmx_vmread_bitmap
);
3998 #ifdef CONFIG_X86_64
4003 shadow_read_only_fields
[j
] = field
;
4006 max_shadow_read_only_fields
= j
;
4008 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
4009 u16 field
= shadow_read_write_fields
[i
];
4010 if (vmcs_field_width(field
) == VMCS_FIELD_WIDTH_U64
&&
4011 (i
+ 1 == max_shadow_read_write_fields
||
4012 shadow_read_write_fields
[i
+ 1] != field
+ 1))
4013 pr_err("Missing field from shadow_read_write_field %x\n",
4017 * PML and the preemption timer can be emulated, but the
4018 * processor cannot vmwrite to fields that don't exist
4022 case GUEST_PML_INDEX
:
4023 if (!cpu_has_vmx_pml())
4026 case VMX_PREEMPTION_TIMER_VALUE
:
4027 if (!cpu_has_vmx_preemption_timer())
4030 case GUEST_INTR_STATUS
:
4031 if (!cpu_has_vmx_apicv())
4038 clear_bit(field
, vmx_vmwrite_bitmap
);
4039 clear_bit(field
, vmx_vmread_bitmap
);
4040 #ifdef CONFIG_X86_64
4045 shadow_read_write_fields
[j
] = field
;
4048 max_shadow_read_write_fields
= j
;
4051 static __init
int alloc_kvm_area(void)
4055 for_each_possible_cpu(cpu
) {
4058 vmcs
= alloc_vmcs_cpu(cpu
);
4064 per_cpu(vmxarea
, cpu
) = vmcs
;
4069 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
4070 struct kvm_segment
*save
)
4072 if (!emulate_invalid_guest_state
) {
4074 * CS and SS RPL should be equal during guest entry according
4075 * to VMX spec, but in reality it is not always so. Since vcpu
4076 * is in the middle of the transition from real mode to
4077 * protected mode it is safe to assume that RPL 0 is a good
4080 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
4081 save
->selector
&= ~SEGMENT_RPL_MASK
;
4082 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
4085 vmx_set_segment(vcpu
, save
, seg
);
4088 static void enter_pmode(struct kvm_vcpu
*vcpu
)
4090 unsigned long flags
;
4091 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4094 * Update real mode segment cache. It may be not up-to-date if sement
4095 * register was written while vcpu was in a guest mode.
4097 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4098 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4099 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4100 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4101 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4102 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4104 vmx
->rmode
.vm86_active
= 0;
4106 vmx_segment_cache_clear(vmx
);
4108 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4110 flags
= vmcs_readl(GUEST_RFLAGS
);
4111 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
4112 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
4113 vmcs_writel(GUEST_RFLAGS
, flags
);
4115 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
4116 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
4118 update_exception_bitmap(vcpu
);
4120 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4121 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4122 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4123 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4124 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4125 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4128 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
4130 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4131 struct kvm_segment var
= *save
;
4134 if (seg
== VCPU_SREG_CS
)
4137 if (!emulate_invalid_guest_state
) {
4138 var
.selector
= var
.base
>> 4;
4139 var
.base
= var
.base
& 0xffff0;
4149 if (save
->base
& 0xf)
4150 printk_once(KERN_WARNING
"kvm: segment base is not "
4151 "paragraph aligned when entering "
4152 "protected mode (seg=%d)", seg
);
4155 vmcs_write16(sf
->selector
, var
.selector
);
4156 vmcs_writel(sf
->base
, var
.base
);
4157 vmcs_write32(sf
->limit
, var
.limit
);
4158 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4161 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4163 unsigned long flags
;
4164 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4166 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4167 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4168 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4169 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4170 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4171 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4172 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4174 vmx
->rmode
.vm86_active
= 1;
4177 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4178 * vcpu. Warn the user that an update is overdue.
4180 if (!vcpu
->kvm
->arch
.tss_addr
)
4181 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4182 "called before entering vcpu\n");
4184 vmx_segment_cache_clear(vmx
);
4186 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4187 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4188 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4190 flags
= vmcs_readl(GUEST_RFLAGS
);
4191 vmx
->rmode
.save_rflags
= flags
;
4193 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4195 vmcs_writel(GUEST_RFLAGS
, flags
);
4196 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4197 update_exception_bitmap(vcpu
);
4199 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4200 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4201 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4202 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4203 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4204 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4206 kvm_mmu_reset_context(vcpu
);
4209 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4211 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4212 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4218 * Force kernel_gs_base reloading before EFER changes, as control
4219 * of this msr depends on is_long_mode().
4221 vmx_load_host_state(to_vmx(vcpu
));
4222 vcpu
->arch
.efer
= efer
;
4223 if (efer
& EFER_LMA
) {
4224 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4227 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4229 msr
->data
= efer
& ~EFER_LME
;
4234 #ifdef CONFIG_X86_64
4236 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4240 vmx_segment_cache_clear(to_vmx(vcpu
));
4242 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4243 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4244 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4246 vmcs_write32(GUEST_TR_AR_BYTES
,
4247 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4248 | VMX_AR_TYPE_BUSY_64_TSS
);
4250 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4253 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4255 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4256 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4261 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
,
4262 bool invalidate_gpa
)
4264 if (enable_ept
&& (invalidate_gpa
|| !enable_vpid
)) {
4265 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4267 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4269 vpid_sync_context(vpid
);
4273 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
, bool invalidate_gpa
)
4275 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
, invalidate_gpa
);
4278 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4281 vmx_flush_tlb(vcpu
, true);
4284 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4286 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4288 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4289 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4292 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4294 if (enable_ept
&& is_paging(vcpu
))
4295 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4296 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4299 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4301 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4303 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4304 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4307 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4309 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4311 if (!test_bit(VCPU_EXREG_PDPTR
,
4312 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4315 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4316 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4317 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4318 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4319 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4323 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4325 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4327 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4328 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4329 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4330 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4331 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4334 __set_bit(VCPU_EXREG_PDPTR
,
4335 (unsigned long *)&vcpu
->arch
.regs_avail
);
4336 __set_bit(VCPU_EXREG_PDPTR
,
4337 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4340 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4342 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4343 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4344 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4346 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4347 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4348 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4349 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4351 return fixed_bits_valid(val
, fixed0
, fixed1
);
4354 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4356 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4357 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4359 return fixed_bits_valid(val
, fixed0
, fixed1
);
4362 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4364 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4365 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4367 return fixed_bits_valid(val
, fixed0
, fixed1
);
4370 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4371 #define nested_guest_cr4_valid nested_cr4_valid
4372 #define nested_host_cr4_valid nested_cr4_valid
4374 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4376 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4378 struct kvm_vcpu
*vcpu
)
4380 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4381 vmx_decache_cr3(vcpu
);
4382 if (!(cr0
& X86_CR0_PG
)) {
4383 /* From paging/starting to nonpaging */
4384 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4385 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4386 (CPU_BASED_CR3_LOAD_EXITING
|
4387 CPU_BASED_CR3_STORE_EXITING
));
4388 vcpu
->arch
.cr0
= cr0
;
4389 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4390 } else if (!is_paging(vcpu
)) {
4391 /* From nonpaging to paging */
4392 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4393 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4394 ~(CPU_BASED_CR3_LOAD_EXITING
|
4395 CPU_BASED_CR3_STORE_EXITING
));
4396 vcpu
->arch
.cr0
= cr0
;
4397 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4400 if (!(cr0
& X86_CR0_WP
))
4401 *hw_cr0
&= ~X86_CR0_WP
;
4404 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4406 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4407 unsigned long hw_cr0
;
4409 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4410 if (enable_unrestricted_guest
)
4411 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4413 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4415 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4418 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4422 #ifdef CONFIG_X86_64
4423 if (vcpu
->arch
.efer
& EFER_LME
) {
4424 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4426 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4432 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4434 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4435 vmcs_writel(GUEST_CR0
, hw_cr0
);
4436 vcpu
->arch
.cr0
= cr0
;
4438 /* depends on vcpu->arch.cr0 to be set to a new value */
4439 vmx
->emulation_required
= emulation_required(vcpu
);
4442 static int get_ept_level(struct kvm_vcpu
*vcpu
)
4444 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
4449 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4451 u64 eptp
= VMX_EPTP_MT_WB
;
4453 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
4455 if (enable_ept_ad_bits
&&
4456 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4457 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
4458 eptp
|= (root_hpa
& PAGE_MASK
);
4463 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4465 unsigned long guest_cr3
;
4470 eptp
= construct_eptp(vcpu
, cr3
);
4471 vmcs_write64(EPT_POINTER
, eptp
);
4472 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4473 guest_cr3
= kvm_read_cr3(vcpu
);
4475 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4476 ept_load_pdptrs(vcpu
);
4479 vmx_flush_tlb(vcpu
, true);
4480 vmcs_writel(GUEST_CR3
, guest_cr3
);
4483 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4486 * Pass through host's Machine Check Enable value to hw_cr4, which
4487 * is in force while we are in guest mode. Do not let guests control
4488 * this bit, even if host CR4.MCE == 0.
4490 unsigned long hw_cr4
=
4491 (cr4_read_shadow() & X86_CR4_MCE
) |
4492 (cr4
& ~X86_CR4_MCE
) |
4493 (to_vmx(vcpu
)->rmode
.vm86_active
?
4494 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4496 if ((cr4
& X86_CR4_UMIP
) && !boot_cpu_has(X86_FEATURE_UMIP
)) {
4497 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
4498 SECONDARY_EXEC_DESC
);
4499 hw_cr4
&= ~X86_CR4_UMIP
;
4500 } else if (!is_guest_mode(vcpu
) ||
4501 !nested_cpu_has2(get_vmcs12(vcpu
), SECONDARY_EXEC_DESC
))
4502 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
4503 SECONDARY_EXEC_DESC
);
4505 if (cr4
& X86_CR4_VMXE
) {
4507 * To use VMXON (and later other VMX instructions), a guest
4508 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4509 * So basically the check on whether to allow nested VMX
4512 if (!nested_vmx_allowed(vcpu
))
4516 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4519 vcpu
->arch
.cr4
= cr4
;
4521 if (!is_paging(vcpu
)) {
4522 hw_cr4
&= ~X86_CR4_PAE
;
4523 hw_cr4
|= X86_CR4_PSE
;
4524 } else if (!(cr4
& X86_CR4_PAE
)) {
4525 hw_cr4
&= ~X86_CR4_PAE
;
4529 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4531 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4532 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4533 * to be manually disabled when guest switches to non-paging
4536 * If !enable_unrestricted_guest, the CPU is always running
4537 * with CR0.PG=1 and CR4 needs to be modified.
4538 * If enable_unrestricted_guest, the CPU automatically
4539 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4541 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4543 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4544 vmcs_writel(GUEST_CR4
, hw_cr4
);
4548 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4549 struct kvm_segment
*var
, int seg
)
4551 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4554 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4555 *var
= vmx
->rmode
.segs
[seg
];
4556 if (seg
== VCPU_SREG_TR
4557 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4559 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4560 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4563 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4564 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4565 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4566 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4567 var
->unusable
= (ar
>> 16) & 1;
4568 var
->type
= ar
& 15;
4569 var
->s
= (ar
>> 4) & 1;
4570 var
->dpl
= (ar
>> 5) & 3;
4572 * Some userspaces do not preserve unusable property. Since usable
4573 * segment has to be present according to VMX spec we can use present
4574 * property to amend userspace bug by making unusable segment always
4575 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4576 * segment as unusable.
4578 var
->present
= !var
->unusable
;
4579 var
->avl
= (ar
>> 12) & 1;
4580 var
->l
= (ar
>> 13) & 1;
4581 var
->db
= (ar
>> 14) & 1;
4582 var
->g
= (ar
>> 15) & 1;
4585 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4587 struct kvm_segment s
;
4589 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4590 vmx_get_segment(vcpu
, &s
, seg
);
4593 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4596 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4598 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4600 if (unlikely(vmx
->rmode
.vm86_active
))
4603 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4604 return VMX_AR_DPL(ar
);
4608 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4612 if (var
->unusable
|| !var
->present
)
4615 ar
= var
->type
& 15;
4616 ar
|= (var
->s
& 1) << 4;
4617 ar
|= (var
->dpl
& 3) << 5;
4618 ar
|= (var
->present
& 1) << 7;
4619 ar
|= (var
->avl
& 1) << 12;
4620 ar
|= (var
->l
& 1) << 13;
4621 ar
|= (var
->db
& 1) << 14;
4622 ar
|= (var
->g
& 1) << 15;
4628 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4629 struct kvm_segment
*var
, int seg
)
4631 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4632 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4634 vmx_segment_cache_clear(vmx
);
4636 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4637 vmx
->rmode
.segs
[seg
] = *var
;
4638 if (seg
== VCPU_SREG_TR
)
4639 vmcs_write16(sf
->selector
, var
->selector
);
4641 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4645 vmcs_writel(sf
->base
, var
->base
);
4646 vmcs_write32(sf
->limit
, var
->limit
);
4647 vmcs_write16(sf
->selector
, var
->selector
);
4650 * Fix the "Accessed" bit in AR field of segment registers for older
4652 * IA32 arch specifies that at the time of processor reset the
4653 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4654 * is setting it to 0 in the userland code. This causes invalid guest
4655 * state vmexit when "unrestricted guest" mode is turned on.
4656 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4657 * tree. Newer qemu binaries with that qemu fix would not need this
4660 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4661 var
->type
|= 0x1; /* Accessed */
4663 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4666 vmx
->emulation_required
= emulation_required(vcpu
);
4669 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4671 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4673 *db
= (ar
>> 14) & 1;
4674 *l
= (ar
>> 13) & 1;
4677 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4679 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4680 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4683 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4685 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4686 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4689 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4691 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4692 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4695 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4697 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4698 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4701 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4703 struct kvm_segment var
;
4706 vmx_get_segment(vcpu
, &var
, seg
);
4708 if (seg
== VCPU_SREG_CS
)
4710 ar
= vmx_segment_access_rights(&var
);
4712 if (var
.base
!= (var
.selector
<< 4))
4714 if (var
.limit
!= 0xffff)
4722 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4724 struct kvm_segment cs
;
4725 unsigned int cs_rpl
;
4727 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4728 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4732 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4736 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4737 if (cs
.dpl
> cs_rpl
)
4740 if (cs
.dpl
!= cs_rpl
)
4746 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4750 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4752 struct kvm_segment ss
;
4753 unsigned int ss_rpl
;
4755 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4756 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4760 if (ss
.type
!= 3 && ss
.type
!= 7)
4764 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4772 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4774 struct kvm_segment var
;
4777 vmx_get_segment(vcpu
, &var
, seg
);
4778 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4786 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4787 if (var
.dpl
< rpl
) /* DPL < RPL */
4791 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4797 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4799 struct kvm_segment tr
;
4801 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4805 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4807 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4815 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4817 struct kvm_segment ldtr
;
4819 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4823 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4833 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4835 struct kvm_segment cs
, ss
;
4837 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4838 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4840 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4841 (ss
.selector
& SEGMENT_RPL_MASK
));
4845 * Check if guest state is valid. Returns true if valid, false if
4847 * We assume that registers are always usable
4849 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4851 if (enable_unrestricted_guest
)
4854 /* real mode guest state checks */
4855 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4856 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4858 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4860 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4862 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4864 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4866 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4869 /* protected mode guest state checks */
4870 if (!cs_ss_rpl_check(vcpu
))
4872 if (!code_segment_valid(vcpu
))
4874 if (!stack_segment_valid(vcpu
))
4876 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4878 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4880 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4882 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4884 if (!tr_valid(vcpu
))
4886 if (!ldtr_valid(vcpu
))
4890 * - Add checks on RIP
4891 * - Add checks on RFLAGS
4897 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4899 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4902 static int init_rmode_tss(struct kvm
*kvm
)
4908 idx
= srcu_read_lock(&kvm
->srcu
);
4909 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4910 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4913 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4914 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4915 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4918 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4921 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4925 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4926 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4929 srcu_read_unlock(&kvm
->srcu
, idx
);
4933 static int init_rmode_identity_map(struct kvm
*kvm
)
4936 kvm_pfn_t identity_map_pfn
;
4939 /* Protect kvm->arch.ept_identity_pagetable_done. */
4940 mutex_lock(&kvm
->slots_lock
);
4942 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4945 if (!kvm
->arch
.ept_identity_map_addr
)
4946 kvm
->arch
.ept_identity_map_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4947 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4949 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4950 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4954 idx
= srcu_read_lock(&kvm
->srcu
);
4955 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4958 /* Set up identity-mapping pagetable for EPT in real mode */
4959 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4960 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4961 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4962 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4963 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4967 kvm
->arch
.ept_identity_pagetable_done
= true;
4970 srcu_read_unlock(&kvm
->srcu
, idx
);
4973 mutex_unlock(&kvm
->slots_lock
);
4977 static void seg_setup(int seg
)
4979 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4982 vmcs_write16(sf
->selector
, 0);
4983 vmcs_writel(sf
->base
, 0);
4984 vmcs_write32(sf
->limit
, 0xffff);
4986 if (seg
== VCPU_SREG_CS
)
4987 ar
|= 0x08; /* code segment */
4989 vmcs_write32(sf
->ar_bytes
, ar
);
4992 static int alloc_apic_access_page(struct kvm
*kvm
)
4997 mutex_lock(&kvm
->slots_lock
);
4998 if (kvm
->arch
.apic_access_page_done
)
5000 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
5001 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
5005 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
5006 if (is_error_page(page
)) {
5012 * Do not pin the page in memory, so that memory hot-unplug
5013 * is able to migrate it.
5016 kvm
->arch
.apic_access_page_done
= true;
5018 mutex_unlock(&kvm
->slots_lock
);
5022 static int allocate_vpid(void)
5028 spin_lock(&vmx_vpid_lock
);
5029 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
5030 if (vpid
< VMX_NR_VPIDS
)
5031 __set_bit(vpid
, vmx_vpid_bitmap
);
5034 spin_unlock(&vmx_vpid_lock
);
5038 static void free_vpid(int vpid
)
5040 if (!enable_vpid
|| vpid
== 0)
5042 spin_lock(&vmx_vpid_lock
);
5043 __clear_bit(vpid
, vmx_vpid_bitmap
);
5044 spin_unlock(&vmx_vpid_lock
);
5047 static void __always_inline
vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
5050 int f
= sizeof(unsigned long);
5052 if (!cpu_has_vmx_msr_bitmap())
5056 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5057 * have the write-low and read-high bitmap offsets the wrong way round.
5058 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5060 if (msr
<= 0x1fff) {
5061 if (type
& MSR_TYPE_R
)
5063 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
5065 if (type
& MSR_TYPE_W
)
5067 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
5069 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
5071 if (type
& MSR_TYPE_R
)
5073 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
5075 if (type
& MSR_TYPE_W
)
5077 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
5082 static void __always_inline
vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
5085 int f
= sizeof(unsigned long);
5087 if (!cpu_has_vmx_msr_bitmap())
5091 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5092 * have the write-low and read-high bitmap offsets the wrong way round.
5093 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5095 if (msr
<= 0x1fff) {
5096 if (type
& MSR_TYPE_R
)
5098 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
5100 if (type
& MSR_TYPE_W
)
5102 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
5104 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
5106 if (type
& MSR_TYPE_R
)
5108 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
5110 if (type
& MSR_TYPE_W
)
5112 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
5117 static void __always_inline
vmx_set_intercept_for_msr(unsigned long *msr_bitmap
,
5118 u32 msr
, int type
, bool value
)
5121 vmx_enable_intercept_for_msr(msr_bitmap
, msr
, type
);
5123 vmx_disable_intercept_for_msr(msr_bitmap
, msr
, type
);
5127 * If a msr is allowed by L0, we should check whether it is allowed by L1.
5128 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5130 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
5131 unsigned long *msr_bitmap_nested
,
5134 int f
= sizeof(unsigned long);
5137 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5138 * have the write-low and read-high bitmap offsets the wrong way round.
5139 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5141 if (msr
<= 0x1fff) {
5142 if (type
& MSR_TYPE_R
&&
5143 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
5145 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
5147 if (type
& MSR_TYPE_W
&&
5148 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
5150 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
5152 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
5154 if (type
& MSR_TYPE_R
&&
5155 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
5157 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
5159 if (type
& MSR_TYPE_W
&&
5160 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
5162 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
5167 static u8
vmx_msr_bitmap_mode(struct kvm_vcpu
*vcpu
)
5171 if (cpu_has_secondary_exec_ctrls() &&
5172 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
5173 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
5174 mode
|= MSR_BITMAP_MODE_X2APIC
;
5175 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
))
5176 mode
|= MSR_BITMAP_MODE_X2APIC_APICV
;
5179 if (is_long_mode(vcpu
))
5180 mode
|= MSR_BITMAP_MODE_LM
;
5185 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5187 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap
,
5192 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
5193 unsigned word
= msr
/ BITS_PER_LONG
;
5194 msr_bitmap
[word
] = (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) ? 0 : ~0;
5195 msr_bitmap
[word
+ (0x800 / sizeof(long))] = ~0;
5198 if (mode
& MSR_BITMAP_MODE_X2APIC
) {
5200 * TPR reads and writes can be virtualized even if virtual interrupt
5201 * delivery is not in use.
5203 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_TASKPRI
), MSR_TYPE_RW
);
5204 if (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) {
5205 vmx_enable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_TMCCT
), MSR_TYPE_R
);
5206 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_EOI
), MSR_TYPE_W
);
5207 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_SELF_IPI
), MSR_TYPE_W
);
5212 static void vmx_update_msr_bitmap(struct kvm_vcpu
*vcpu
)
5214 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5215 unsigned long *msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
5216 u8 mode
= vmx_msr_bitmap_mode(vcpu
);
5217 u8 changed
= mode
^ vmx
->msr_bitmap_mode
;
5222 vmx_set_intercept_for_msr(msr_bitmap
, MSR_KERNEL_GS_BASE
, MSR_TYPE_RW
,
5223 !(mode
& MSR_BITMAP_MODE_LM
));
5225 if (changed
& (MSR_BITMAP_MODE_X2APIC
| MSR_BITMAP_MODE_X2APIC_APICV
))
5226 vmx_update_msr_bitmap_x2apic(msr_bitmap
, mode
);
5228 vmx
->msr_bitmap_mode
= mode
;
5231 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5233 return enable_apicv
;
5236 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5238 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5242 * Don't need to mark the APIC access page dirty; it is never
5243 * written to by the CPU during APIC virtualization.
5246 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5247 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5248 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5251 if (nested_cpu_has_posted_intr(vmcs12
)) {
5252 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5253 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5258 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5260 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5265 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5268 vmx
->nested
.pi_pending
= false;
5269 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5272 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5273 if (max_irr
!= 256) {
5274 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5275 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
,
5276 vapic_page
, &max_irr
);
5277 kunmap(vmx
->nested
.virtual_apic_page
);
5279 status
= vmcs_read16(GUEST_INTR_STATUS
);
5280 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5282 status
|= (u8
)max_irr
;
5283 vmcs_write16(GUEST_INTR_STATUS
, status
);
5287 nested_mark_vmcs12_pages_dirty(vcpu
);
5290 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5294 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5296 if (vcpu
->mode
== IN_GUEST_MODE
) {
5298 * The vector of interrupt to be delivered to vcpu had
5299 * been set in PIR before this function.
5301 * Following cases will be reached in this block, and
5302 * we always send a notification event in all cases as
5305 * Case 1: vcpu keeps in non-root mode. Sending a
5306 * notification event posts the interrupt to vcpu.
5308 * Case 2: vcpu exits to root mode and is still
5309 * runnable. PIR will be synced to vIRR before the
5310 * next vcpu entry. Sending a notification event in
5311 * this case has no effect, as vcpu is not in root
5314 * Case 3: vcpu exits to root mode and is blocked.
5315 * vcpu_block() has already synced PIR to vIRR and
5316 * never blocks vcpu if vIRR is not cleared. Therefore,
5317 * a blocked vcpu here does not wait for any requested
5318 * interrupts in PIR, and sending a notification event
5319 * which has no effect is safe here.
5322 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5329 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5332 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5334 if (is_guest_mode(vcpu
) &&
5335 vector
== vmx
->nested
.posted_intr_nv
) {
5337 * If a posted intr is not recognized by hardware,
5338 * we will accomplish it in the next vmentry.
5340 vmx
->nested
.pi_pending
= true;
5341 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5342 /* the PIR and ON have been set by L1. */
5343 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, true))
5344 kvm_vcpu_kick(vcpu
);
5350 * Send interrupt to vcpu via posted interrupt way.
5351 * 1. If target vcpu is running(non-root mode), send posted interrupt
5352 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5353 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5354 * interrupt from PIR in next vmentry.
5356 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5358 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5361 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5365 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5368 /* If a previous notification has sent the IPI, nothing to do. */
5369 if (pi_test_and_set_on(&vmx
->pi_desc
))
5372 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5373 kvm_vcpu_kick(vcpu
);
5377 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5378 * will not change in the lifetime of the guest.
5379 * Note that host-state that does change is set elsewhere. E.g., host-state
5380 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5382 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5387 unsigned long cr0
, cr3
, cr4
;
5390 WARN_ON(cr0
& X86_CR0_TS
);
5391 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5394 * Save the most likely value for this task's CR3 in the VMCS.
5395 * We can't use __get_current_cr3_fast() because we're not atomic.
5398 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5399 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5401 /* Save the most likely value for this task's CR4 in the VMCS. */
5402 cr4
= cr4_read_shadow();
5403 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5404 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5406 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5407 #ifdef CONFIG_X86_64
5409 * Load null selectors, so we can avoid reloading them in
5410 * __vmx_load_host_state(), in case userspace uses the null selectors
5411 * too (the expected case).
5413 vmcs_write16(HOST_DS_SELECTOR
, 0);
5414 vmcs_write16(HOST_ES_SELECTOR
, 0);
5416 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5417 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5419 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5420 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5423 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5424 vmx
->host_idt_base
= dt
.address
;
5426 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5428 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5429 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5430 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5431 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5433 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5434 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5435 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5439 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5441 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5443 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5444 if (is_guest_mode(&vmx
->vcpu
))
5445 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5446 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5447 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5450 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5452 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5454 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5455 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5458 pin_based_exec_ctrl
&= ~PIN_BASED_VIRTUAL_NMIS
;
5460 /* Enable the preemption timer dynamically */
5461 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5462 return pin_based_exec_ctrl
;
5465 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5467 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5469 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5470 if (cpu_has_secondary_exec_ctrls()) {
5471 if (kvm_vcpu_apicv_active(vcpu
))
5472 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5473 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5474 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5476 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5477 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5478 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5481 if (cpu_has_vmx_msr_bitmap())
5482 vmx_update_msr_bitmap(vcpu
);
5485 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5487 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5489 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5490 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5492 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5493 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5494 #ifdef CONFIG_X86_64
5495 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5496 CPU_BASED_CR8_LOAD_EXITING
;
5500 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5501 CPU_BASED_CR3_LOAD_EXITING
|
5502 CPU_BASED_INVLPG_EXITING
;
5503 return exec_control
;
5506 static bool vmx_rdrand_supported(void)
5508 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5509 SECONDARY_EXEC_RDRAND_EXITING
;
5512 static bool vmx_rdseed_supported(void)
5514 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5515 SECONDARY_EXEC_RDSEED_EXITING
;
5518 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
5520 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
5522 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5524 if (!cpu_need_virtualize_apic_accesses(vcpu
))
5525 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5527 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5529 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5530 enable_unrestricted_guest
= 0;
5531 /* Enable INVPCID for non-ept guests may cause performance regression. */
5532 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5534 if (!enable_unrestricted_guest
)
5535 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5537 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5538 if (!kvm_vcpu_apicv_active(vcpu
))
5539 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5540 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5541 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5543 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
5544 * in vmx_set_cr4. */
5545 exec_control
&= ~SECONDARY_EXEC_DESC
;
5547 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5549 We can NOT enable shadow_vmcs here because we don't have yet
5552 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5555 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5557 if (vmx_xsaves_supported()) {
5558 /* Exposing XSAVES only when XSAVE is exposed */
5559 bool xsaves_enabled
=
5560 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
5561 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
5563 if (!xsaves_enabled
)
5564 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
5568 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5569 SECONDARY_EXEC_XSAVES
;
5571 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5572 ~SECONDARY_EXEC_XSAVES
;
5576 if (vmx_rdtscp_supported()) {
5577 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
5578 if (!rdtscp_enabled
)
5579 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5583 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5584 SECONDARY_EXEC_RDTSCP
;
5586 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5587 ~SECONDARY_EXEC_RDTSCP
;
5591 if (vmx_invpcid_supported()) {
5592 /* Exposing INVPCID only when PCID is exposed */
5593 bool invpcid_enabled
=
5594 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
5595 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
5597 if (!invpcid_enabled
) {
5598 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5599 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
5603 if (invpcid_enabled
)
5604 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5605 SECONDARY_EXEC_ENABLE_INVPCID
;
5607 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5608 ~SECONDARY_EXEC_ENABLE_INVPCID
;
5612 if (vmx_rdrand_supported()) {
5613 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
5615 exec_control
&= ~SECONDARY_EXEC_RDRAND_EXITING
;
5619 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5620 SECONDARY_EXEC_RDRAND_EXITING
;
5622 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5623 ~SECONDARY_EXEC_RDRAND_EXITING
;
5627 if (vmx_rdseed_supported()) {
5628 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
5630 exec_control
&= ~SECONDARY_EXEC_RDSEED_EXITING
;
5634 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5635 SECONDARY_EXEC_RDSEED_EXITING
;
5637 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5638 ~SECONDARY_EXEC_RDSEED_EXITING
;
5642 vmx
->secondary_exec_control
= exec_control
;
5645 static void ept_set_mmio_spte_mask(void)
5648 * EPT Misconfigurations can be generated if the value of bits 2:0
5649 * of an EPT paging-structure entry is 110b (write/execute).
5651 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5652 VMX_EPT_MISCONFIG_WX_VALUE
);
5655 #define VMX_XSS_EXIT_BITMAP 0
5657 * Sets up the vmcs for emulated real mode.
5659 static void vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5661 #ifdef CONFIG_X86_64
5666 if (enable_shadow_vmcs
) {
5667 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5668 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5670 if (cpu_has_vmx_msr_bitmap())
5671 vmcs_write64(MSR_BITMAP
, __pa(vmx
->vmcs01
.msr_bitmap
));
5673 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5676 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5677 vmx
->hv_deadline_tsc
= -1;
5679 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5681 if (cpu_has_secondary_exec_ctrls()) {
5682 vmx_compute_secondary_exec_control(vmx
);
5683 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5684 vmx
->secondary_exec_control
);
5687 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5688 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5689 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5690 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5691 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5693 vmcs_write16(GUEST_INTR_STATUS
, 0);
5695 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5696 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5700 vmcs_write32(PLE_GAP
, ple_gap
);
5701 vmx
->ple_window
= ple_window
;
5702 vmx
->ple_window_dirty
= true;
5705 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5706 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5707 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5709 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5710 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5711 vmx_set_constant_host_state(vmx
);
5712 #ifdef CONFIG_X86_64
5713 rdmsrl(MSR_FS_BASE
, a
);
5714 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5715 rdmsrl(MSR_GS_BASE
, a
);
5716 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5718 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5719 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5722 if (cpu_has_vmx_vmfunc())
5723 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5725 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5726 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5727 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5728 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5729 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5731 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5732 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5734 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5735 u32 index
= vmx_msr_index
[i
];
5736 u32 data_low
, data_high
;
5739 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5741 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5743 vmx
->guest_msrs
[j
].index
= i
;
5744 vmx
->guest_msrs
[j
].data
= 0;
5745 vmx
->guest_msrs
[j
].mask
= -1ull;
5749 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
))
5750 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, vmx
->arch_capabilities
);
5752 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5754 /* 22.2.1, 20.8.1 */
5755 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5757 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5758 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5760 set_cr4_guest_host_mask(vmx
);
5762 if (vmx_xsaves_supported())
5763 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5766 ASSERT(vmx
->pml_pg
);
5767 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5768 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5772 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5774 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5775 struct msr_data apic_base_msr
;
5778 vmx
->rmode
.vm86_active
= 0;
5781 vcpu
->arch
.microcode_version
= 0x100000000ULL
;
5782 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5783 kvm_set_cr8(vcpu
, 0);
5786 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5787 MSR_IA32_APICBASE_ENABLE
;
5788 if (kvm_vcpu_is_reset_bsp(vcpu
))
5789 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5790 apic_base_msr
.host_initiated
= true;
5791 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5794 vmx_segment_cache_clear(vmx
);
5796 seg_setup(VCPU_SREG_CS
);
5797 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5798 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5800 seg_setup(VCPU_SREG_DS
);
5801 seg_setup(VCPU_SREG_ES
);
5802 seg_setup(VCPU_SREG_FS
);
5803 seg_setup(VCPU_SREG_GS
);
5804 seg_setup(VCPU_SREG_SS
);
5806 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5807 vmcs_writel(GUEST_TR_BASE
, 0);
5808 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5809 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5811 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5812 vmcs_writel(GUEST_LDTR_BASE
, 0);
5813 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5814 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5817 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5818 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5819 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5820 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5823 kvm_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
5824 kvm_rip_write(vcpu
, 0xfff0);
5826 vmcs_writel(GUEST_GDTR_BASE
, 0);
5827 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5829 vmcs_writel(GUEST_IDTR_BASE
, 0);
5830 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5832 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5833 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5834 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5835 if (kvm_mpx_supported())
5836 vmcs_write64(GUEST_BNDCFGS
, 0);
5840 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5842 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5843 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5844 if (cpu_need_tpr_shadow(vcpu
))
5845 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5846 __pa(vcpu
->arch
.apic
->regs
));
5847 vmcs_write32(TPR_THRESHOLD
, 0);
5850 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5853 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5855 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5856 vmx
->vcpu
.arch
.cr0
= cr0
;
5857 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5858 vmx_set_cr4(vcpu
, 0);
5859 vmx_set_efer(vcpu
, 0);
5861 update_exception_bitmap(vcpu
);
5863 vpid_sync_context(vmx
->vpid
);
5867 * In nested virtualization, check if L1 asked to exit on external interrupts.
5868 * For most existing hypervisors, this will always return true.
5870 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5872 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5873 PIN_BASED_EXT_INTR_MASK
;
5877 * In nested virtualization, check if L1 has set
5878 * VM_EXIT_ACK_INTR_ON_EXIT
5880 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5882 return get_vmcs12(vcpu
)->vm_exit_controls
&
5883 VM_EXIT_ACK_INTR_ON_EXIT
;
5886 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5888 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5889 PIN_BASED_NMI_EXITING
;
5892 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5894 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5895 CPU_BASED_VIRTUAL_INTR_PENDING
);
5898 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5901 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5902 enable_irq_window(vcpu
);
5906 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5907 CPU_BASED_VIRTUAL_NMI_PENDING
);
5910 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5912 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5914 int irq
= vcpu
->arch
.interrupt
.nr
;
5916 trace_kvm_inj_virq(irq
);
5918 ++vcpu
->stat
.irq_injections
;
5919 if (vmx
->rmode
.vm86_active
) {
5921 if (vcpu
->arch
.interrupt
.soft
)
5922 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5923 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5924 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5927 intr
= irq
| INTR_INFO_VALID_MASK
;
5928 if (vcpu
->arch
.interrupt
.soft
) {
5929 intr
|= INTR_TYPE_SOFT_INTR
;
5930 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5931 vmx
->vcpu
.arch
.event_exit_inst_len
);
5933 intr
|= INTR_TYPE_EXT_INTR
;
5934 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5937 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5939 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5943 * Tracking the NMI-blocked state in software is built upon
5944 * finding the next open IRQ window. This, in turn, depends on
5945 * well-behaving guests: They have to keep IRQs disabled at
5946 * least as long as the NMI handler runs. Otherwise we may
5947 * cause NMI nesting, maybe breaking the guest. But as this is
5948 * highly unlikely, we can live with the residual risk.
5950 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 1;
5951 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5954 ++vcpu
->stat
.nmi_injections
;
5955 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5957 if (vmx
->rmode
.vm86_active
) {
5958 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5959 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5963 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5964 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5967 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5969 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5973 return vmx
->loaded_vmcs
->soft_vnmi_blocked
;
5974 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5976 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5977 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5981 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5983 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5986 if (vmx
->loaded_vmcs
->soft_vnmi_blocked
!= masked
) {
5987 vmx
->loaded_vmcs
->soft_vnmi_blocked
= masked
;
5988 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5991 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5993 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5994 GUEST_INTR_STATE_NMI
);
5996 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5997 GUEST_INTR_STATE_NMI
);
6001 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
6003 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
6007 to_vmx(vcpu
)->loaded_vmcs
->soft_vnmi_blocked
)
6010 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
6011 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
6012 | GUEST_INTR_STATE_NMI
));
6015 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
6017 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
6018 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
6019 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
6020 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
6023 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
6027 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
6031 kvm
->arch
.tss_addr
= addr
;
6032 return init_rmode_tss(kvm
);
6035 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
6040 * Update instruction length as we may reinject the exception
6041 * from user space while in guest debugging mode.
6043 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
6044 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6045 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
6049 if (vcpu
->guest_debug
&
6050 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
6067 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
6068 int vec
, u32 err_code
)
6071 * Instruction with address size override prefix opcode 0x67
6072 * Cause the #SS fault with 0 error code in VM86 mode.
6074 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
6075 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
6076 if (vcpu
->arch
.halt_request
) {
6077 vcpu
->arch
.halt_request
= 0;
6078 return kvm_vcpu_halt(vcpu
);
6086 * Forward all other exceptions that are valid in real mode.
6087 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6088 * the required debugging infrastructure rework.
6090 kvm_queue_exception(vcpu
, vec
);
6095 * Trigger machine check on the host. We assume all the MSRs are already set up
6096 * by the CPU and that we still run on the same CPU as the MCE occurred on.
6097 * We pass a fake environment to the machine check handler because we want
6098 * the guest to be always treated like user space, no matter what context
6099 * it used internally.
6101 static void kvm_machine_check(void)
6103 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6104 struct pt_regs regs
= {
6105 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
6106 .flags
= X86_EFLAGS_IF
,
6109 do_machine_check(®s
, 0);
6113 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
6115 /* already handled by vcpu_run */
6119 static int handle_exception(struct kvm_vcpu
*vcpu
)
6121 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6122 struct kvm_run
*kvm_run
= vcpu
->run
;
6123 u32 intr_info
, ex_no
, error_code
;
6124 unsigned long cr2
, rip
, dr6
;
6126 enum emulation_result er
;
6128 vect_info
= vmx
->idt_vectoring_info
;
6129 intr_info
= vmx
->exit_intr_info
;
6131 if (is_machine_check(intr_info
))
6132 return handle_machine_check(vcpu
);
6134 if (is_nmi(intr_info
))
6135 return 1; /* already handled by vmx_vcpu_run() */
6137 if (is_invalid_opcode(intr_info
)) {
6138 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
6139 if (er
== EMULATE_USER_EXIT
)
6141 if (er
!= EMULATE_DONE
)
6142 kvm_queue_exception(vcpu
, UD_VECTOR
);
6147 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
6148 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
6151 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6152 * MMIO, it is better to report an internal error.
6153 * See the comments in vmx_handle_exit.
6155 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
6156 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
6157 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6158 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
6159 vcpu
->run
->internal
.ndata
= 3;
6160 vcpu
->run
->internal
.data
[0] = vect_info
;
6161 vcpu
->run
->internal
.data
[1] = intr_info
;
6162 vcpu
->run
->internal
.data
[2] = error_code
;
6166 if (is_page_fault(intr_info
)) {
6167 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
6168 /* EPT won't cause page fault directly */
6169 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
6170 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0);
6173 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
6175 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
6176 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
6180 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
6183 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
6184 if (!(vcpu
->guest_debug
&
6185 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
6186 vcpu
->arch
.dr6
&= ~15;
6187 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
6188 if (is_icebp(intr_info
))
6189 skip_emulated_instruction(vcpu
);
6191 kvm_queue_exception(vcpu
, DB_VECTOR
);
6194 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
6195 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
6199 * Update instruction length as we may reinject #BP from
6200 * user space while in guest debugging mode. Reading it for
6201 * #DB as well causes no harm, it is not used in that case.
6203 vmx
->vcpu
.arch
.event_exit_inst_len
=
6204 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6205 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
6206 rip
= kvm_rip_read(vcpu
);
6207 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
6208 kvm_run
->debug
.arch
.exception
= ex_no
;
6211 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
6212 kvm_run
->ex
.exception
= ex_no
;
6213 kvm_run
->ex
.error_code
= error_code
;
6219 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
6221 ++vcpu
->stat
.irq_exits
;
6225 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
6227 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
6228 vcpu
->mmio_needed
= 0;
6232 static int handle_io(struct kvm_vcpu
*vcpu
)
6234 unsigned long exit_qualification
;
6235 int size
, in
, string
, ret
;
6238 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6239 string
= (exit_qualification
& 16) != 0;
6240 in
= (exit_qualification
& 8) != 0;
6242 ++vcpu
->stat
.io_exits
;
6245 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6247 port
= exit_qualification
>> 16;
6248 size
= (exit_qualification
& 7) + 1;
6250 ret
= kvm_skip_emulated_instruction(vcpu
);
6253 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6254 * KVM_EXIT_DEBUG here.
6256 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
6260 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
6263 * Patch in the VMCALL instruction:
6265 hypercall
[0] = 0x0f;
6266 hypercall
[1] = 0x01;
6267 hypercall
[2] = 0xc1;
6270 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6271 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
6273 if (is_guest_mode(vcpu
)) {
6274 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6275 unsigned long orig_val
= val
;
6278 * We get here when L2 changed cr0 in a way that did not change
6279 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6280 * but did change L0 shadowed bits. So we first calculate the
6281 * effective cr0 value that L1 would like to write into the
6282 * hardware. It consists of the L2-owned bits from the new
6283 * value combined with the L1-owned bits from L1's guest_cr0.
6285 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
6286 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
6288 if (!nested_guest_cr0_valid(vcpu
, val
))
6291 if (kvm_set_cr0(vcpu
, val
))
6293 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
6296 if (to_vmx(vcpu
)->nested
.vmxon
&&
6297 !nested_host_cr0_valid(vcpu
, val
))
6300 return kvm_set_cr0(vcpu
, val
);
6304 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
6306 if (is_guest_mode(vcpu
)) {
6307 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6308 unsigned long orig_val
= val
;
6310 /* analogously to handle_set_cr0 */
6311 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
6312 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
6313 if (kvm_set_cr4(vcpu
, val
))
6315 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
6318 return kvm_set_cr4(vcpu
, val
);
6321 static int handle_desc(struct kvm_vcpu
*vcpu
)
6323 WARN_ON(!(vcpu
->arch
.cr4
& X86_CR4_UMIP
));
6324 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6327 static int handle_cr(struct kvm_vcpu
*vcpu
)
6329 unsigned long exit_qualification
, val
;
6335 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6336 cr
= exit_qualification
& 15;
6337 reg
= (exit_qualification
>> 8) & 15;
6338 switch ((exit_qualification
>> 4) & 3) {
6339 case 0: /* mov to cr */
6340 val
= kvm_register_readl(vcpu
, reg
);
6341 trace_kvm_cr_write(cr
, val
);
6344 err
= handle_set_cr0(vcpu
, val
);
6345 return kvm_complete_insn_gp(vcpu
, err
);
6347 err
= kvm_set_cr3(vcpu
, val
);
6348 return kvm_complete_insn_gp(vcpu
, err
);
6350 err
= handle_set_cr4(vcpu
, val
);
6351 return kvm_complete_insn_gp(vcpu
, err
);
6353 u8 cr8_prev
= kvm_get_cr8(vcpu
);
6355 err
= kvm_set_cr8(vcpu
, cr8
);
6356 ret
= kvm_complete_insn_gp(vcpu
, err
);
6357 if (lapic_in_kernel(vcpu
))
6359 if (cr8_prev
<= cr8
)
6362 * TODO: we might be squashing a
6363 * KVM_GUESTDBG_SINGLESTEP-triggered
6364 * KVM_EXIT_DEBUG here.
6366 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6372 WARN_ONCE(1, "Guest should always own CR0.TS");
6373 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6374 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6375 return kvm_skip_emulated_instruction(vcpu
);
6376 case 1: /*mov from cr*/
6379 val
= kvm_read_cr3(vcpu
);
6380 kvm_register_write(vcpu
, reg
, val
);
6381 trace_kvm_cr_read(cr
, val
);
6382 return kvm_skip_emulated_instruction(vcpu
);
6384 val
= kvm_get_cr8(vcpu
);
6385 kvm_register_write(vcpu
, reg
, val
);
6386 trace_kvm_cr_read(cr
, val
);
6387 return kvm_skip_emulated_instruction(vcpu
);
6391 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6392 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6393 kvm_lmsw(vcpu
, val
);
6395 return kvm_skip_emulated_instruction(vcpu
);
6399 vcpu
->run
->exit_reason
= 0;
6400 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6401 (int)(exit_qualification
>> 4) & 3, cr
);
6405 static int handle_dr(struct kvm_vcpu
*vcpu
)
6407 unsigned long exit_qualification
;
6410 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6411 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6413 /* First, if DR does not exist, trigger UD */
6414 if (!kvm_require_dr(vcpu
, dr
))
6417 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6418 if (!kvm_require_cpl(vcpu
, 0))
6420 dr7
= vmcs_readl(GUEST_DR7
);
6423 * As the vm-exit takes precedence over the debug trap, we
6424 * need to emulate the latter, either for the host or the
6425 * guest debugging itself.
6427 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6428 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6429 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6430 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6431 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6432 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6435 vcpu
->arch
.dr6
&= ~15;
6436 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6437 kvm_queue_exception(vcpu
, DB_VECTOR
);
6442 if (vcpu
->guest_debug
== 0) {
6443 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6444 CPU_BASED_MOV_DR_EXITING
);
6447 * No more DR vmexits; force a reload of the debug registers
6448 * and reenter on this instruction. The next vmexit will
6449 * retrieve the full state of the debug registers.
6451 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6455 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6456 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6459 if (kvm_get_dr(vcpu
, dr
, &val
))
6461 kvm_register_write(vcpu
, reg
, val
);
6463 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6466 return kvm_skip_emulated_instruction(vcpu
);
6469 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6471 return vcpu
->arch
.dr6
;
6474 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6478 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6480 get_debugreg(vcpu
->arch
.db
[0], 0);
6481 get_debugreg(vcpu
->arch
.db
[1], 1);
6482 get_debugreg(vcpu
->arch
.db
[2], 2);
6483 get_debugreg(vcpu
->arch
.db
[3], 3);
6484 get_debugreg(vcpu
->arch
.dr6
, 6);
6485 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6487 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6488 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6491 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6493 vmcs_writel(GUEST_DR7
, val
);
6496 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6498 return kvm_emulate_cpuid(vcpu
);
6501 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6503 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6504 struct msr_data msr_info
;
6506 msr_info
.index
= ecx
;
6507 msr_info
.host_initiated
= false;
6508 if (vmx_get_msr(vcpu
, &msr_info
)) {
6509 trace_kvm_msr_read_ex(ecx
);
6510 kvm_inject_gp(vcpu
, 0);
6514 trace_kvm_msr_read(ecx
, msr_info
.data
);
6516 /* FIXME: handling of bits 32:63 of rax, rdx */
6517 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6518 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6519 return kvm_skip_emulated_instruction(vcpu
);
6522 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6524 struct msr_data msr
;
6525 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6526 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6527 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6531 msr
.host_initiated
= false;
6532 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6533 trace_kvm_msr_write_ex(ecx
, data
);
6534 kvm_inject_gp(vcpu
, 0);
6538 trace_kvm_msr_write(ecx
, data
);
6539 return kvm_skip_emulated_instruction(vcpu
);
6542 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6544 kvm_apic_update_ppr(vcpu
);
6548 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6550 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6551 CPU_BASED_VIRTUAL_INTR_PENDING
);
6553 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6555 ++vcpu
->stat
.irq_window_exits
;
6559 static int handle_halt(struct kvm_vcpu
*vcpu
)
6561 return kvm_emulate_halt(vcpu
);
6564 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6566 return kvm_emulate_hypercall(vcpu
);
6569 static int handle_invd(struct kvm_vcpu
*vcpu
)
6571 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6574 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6576 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6578 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6579 return kvm_skip_emulated_instruction(vcpu
);
6582 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6586 err
= kvm_rdpmc(vcpu
);
6587 return kvm_complete_insn_gp(vcpu
, err
);
6590 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6592 return kvm_emulate_wbinvd(vcpu
);
6595 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6597 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6598 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6600 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6601 return kvm_skip_emulated_instruction(vcpu
);
6605 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6607 kvm_skip_emulated_instruction(vcpu
);
6608 WARN(1, "this should never happen\n");
6612 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6614 kvm_skip_emulated_instruction(vcpu
);
6615 WARN(1, "this should never happen\n");
6619 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6621 if (likely(fasteoi
)) {
6622 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6623 int access_type
, offset
;
6625 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6626 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6628 * Sane guest uses MOV to write EOI, with written value
6629 * not cared. So make a short-circuit here by avoiding
6630 * heavy instruction emulation.
6632 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6633 (offset
== APIC_EOI
)) {
6634 kvm_lapic_set_eoi(vcpu
);
6635 return kvm_skip_emulated_instruction(vcpu
);
6638 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6641 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6643 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6644 int vector
= exit_qualification
& 0xff;
6646 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6647 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6651 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6653 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6654 u32 offset
= exit_qualification
& 0xfff;
6656 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6657 kvm_apic_write_nodecode(vcpu
, offset
);
6661 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6663 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6664 unsigned long exit_qualification
;
6665 bool has_error_code
= false;
6668 int reason
, type
, idt_v
, idt_index
;
6670 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6671 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6672 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6674 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6676 reason
= (u32
)exit_qualification
>> 30;
6677 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6679 case INTR_TYPE_NMI_INTR
:
6680 vcpu
->arch
.nmi_injected
= false;
6681 vmx_set_nmi_mask(vcpu
, true);
6683 case INTR_TYPE_EXT_INTR
:
6684 case INTR_TYPE_SOFT_INTR
:
6685 kvm_clear_interrupt_queue(vcpu
);
6687 case INTR_TYPE_HARD_EXCEPTION
:
6688 if (vmx
->idt_vectoring_info
&
6689 VECTORING_INFO_DELIVER_CODE_MASK
) {
6690 has_error_code
= true;
6692 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6695 case INTR_TYPE_SOFT_EXCEPTION
:
6696 kvm_clear_exception_queue(vcpu
);
6702 tss_selector
= exit_qualification
;
6704 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6705 type
!= INTR_TYPE_EXT_INTR
&&
6706 type
!= INTR_TYPE_NMI_INTR
))
6707 skip_emulated_instruction(vcpu
);
6709 if (kvm_task_switch(vcpu
, tss_selector
,
6710 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6711 has_error_code
, error_code
) == EMULATE_FAIL
) {
6712 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6713 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6714 vcpu
->run
->internal
.ndata
= 0;
6719 * TODO: What about debug traps on tss switch?
6720 * Are we supposed to inject them and update dr6?
6726 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6728 unsigned long exit_qualification
;
6732 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6735 * EPT violation happened while executing iret from NMI,
6736 * "blocked by NMI" bit has to be set before next VM entry.
6737 * There are errata that may cause this bit to not be set:
6740 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6742 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6743 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6745 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6746 trace_kvm_page_fault(gpa
, exit_qualification
);
6748 /* Is it a read fault? */
6749 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6750 ? PFERR_USER_MASK
: 0;
6751 /* Is it a write fault? */
6752 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6753 ? PFERR_WRITE_MASK
: 0;
6754 /* Is it a fetch fault? */
6755 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6756 ? PFERR_FETCH_MASK
: 0;
6757 /* ept page table entry is present? */
6758 error_code
|= (exit_qualification
&
6759 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6760 EPT_VIOLATION_EXECUTABLE
))
6761 ? PFERR_PRESENT_MASK
: 0;
6763 error_code
|= (exit_qualification
& 0x100) != 0 ?
6764 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6766 vcpu
->arch
.exit_qualification
= exit_qualification
;
6767 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6770 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6776 * A nested guest cannot optimize MMIO vmexits, because we have an
6777 * nGPA here instead of the required GPA.
6779 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6780 if (!is_guest_mode(vcpu
) &&
6781 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6782 trace_kvm_fast_mmio(gpa
);
6784 * Doing kvm_skip_emulated_instruction() depends on undefined
6785 * behavior: Intel's manual doesn't mandate
6786 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
6787 * occurs and while on real hardware it was observed to be set,
6788 * other hypervisors (namely Hyper-V) don't set it, we end up
6789 * advancing IP with some random value. Disable fast mmio when
6790 * running nested and keep it for real hardware in hope that
6791 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
6793 if (!static_cpu_has(X86_FEATURE_HYPERVISOR
))
6794 return kvm_skip_emulated_instruction(vcpu
);
6796 return x86_emulate_instruction(vcpu
, gpa
, EMULTYPE_SKIP
,
6797 NULL
, 0) == EMULATE_DONE
;
6800 ret
= kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
6804 /* It is the real ept misconfig */
6807 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6808 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6813 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6815 WARN_ON_ONCE(!enable_vnmi
);
6816 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6817 CPU_BASED_VIRTUAL_NMI_PENDING
);
6818 ++vcpu
->stat
.nmi_window_exits
;
6819 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6824 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6826 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6827 enum emulation_result err
= EMULATE_DONE
;
6830 bool intr_window_requested
;
6831 unsigned count
= 130;
6833 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6834 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6836 while (vmx
->emulation_required
&& count
-- != 0) {
6837 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6838 return handle_interrupt_window(&vmx
->vcpu
);
6840 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6843 err
= emulate_instruction(vcpu
, 0);
6845 if (err
== EMULATE_USER_EXIT
) {
6846 ++vcpu
->stat
.mmio_exits
;
6851 if (err
!= EMULATE_DONE
) {
6852 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6853 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6854 vcpu
->run
->internal
.ndata
= 0;
6858 if (vcpu
->arch
.halt_request
) {
6859 vcpu
->arch
.halt_request
= 0;
6860 ret
= kvm_vcpu_halt(vcpu
);
6864 if (signal_pending(current
))
6874 static int __grow_ple_window(int val
)
6876 if (ple_window_grow
< 1)
6879 val
= min(val
, ple_window_actual_max
);
6881 if (ple_window_grow
< ple_window
)
6882 val
*= ple_window_grow
;
6884 val
+= ple_window_grow
;
6889 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6894 if (modifier
< ple_window
)
6899 return max(val
, minimum
);
6902 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6904 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6905 int old
= vmx
->ple_window
;
6907 vmx
->ple_window
= __grow_ple_window(old
);
6909 if (vmx
->ple_window
!= old
)
6910 vmx
->ple_window_dirty
= true;
6912 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6915 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6917 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6918 int old
= vmx
->ple_window
;
6920 vmx
->ple_window
= __shrink_ple_window(old
,
6921 ple_window_shrink
, ple_window
);
6923 if (vmx
->ple_window
!= old
)
6924 vmx
->ple_window_dirty
= true;
6926 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6930 * ple_window_actual_max is computed to be one grow_ple_window() below
6931 * ple_window_max. (See __grow_ple_window for the reason.)
6932 * This prevents overflows, because ple_window_max is int.
6933 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6935 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6937 static void update_ple_window_actual_max(void)
6939 ple_window_actual_max
=
6940 __shrink_ple_window(max(ple_window_max
, ple_window
),
6941 ple_window_grow
, INT_MIN
);
6945 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6947 static void wakeup_handler(void)
6949 struct kvm_vcpu
*vcpu
;
6950 int cpu
= smp_processor_id();
6952 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6953 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6954 blocked_vcpu_list
) {
6955 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6957 if (pi_test_on(pi_desc
) == 1)
6958 kvm_vcpu_kick(vcpu
);
6960 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6963 void vmx_enable_tdp(void)
6965 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6966 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6967 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6968 0ull, VMX_EPT_EXECUTABLE_MASK
,
6969 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6970 VMX_EPT_RWX_MASK
, 0ull);
6972 ept_set_mmio_spte_mask();
6976 static __init
int hardware_setup(void)
6980 rdmsrl_safe(MSR_EFER
, &host_efer
);
6982 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6983 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6985 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6986 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6991 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6992 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6994 if (setup_vmcs_config(&vmcs_config
) < 0) {
6999 if (boot_cpu_has(X86_FEATURE_NX
))
7000 kvm_enable_efer_bits(EFER_NX
);
7002 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7003 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7006 if (!cpu_has_vmx_ept() ||
7007 !cpu_has_vmx_ept_4levels() ||
7008 !cpu_has_vmx_ept_mt_wb() ||
7009 !cpu_has_vmx_invept_global())
7012 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
7013 enable_ept_ad_bits
= 0;
7015 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept
)
7016 enable_unrestricted_guest
= 0;
7018 if (!cpu_has_vmx_flexpriority())
7019 flexpriority_enabled
= 0;
7021 if (!cpu_has_virtual_nmis())
7025 * set_apic_access_page_addr() is used to reload apic access
7026 * page upon invalidation. No need to do anything if not
7027 * using the APIC_ACCESS_ADDR VMCS field.
7029 if (!flexpriority_enabled
)
7030 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
7032 if (!cpu_has_vmx_tpr_shadow())
7033 kvm_x86_ops
->update_cr8_intercept
= NULL
;
7035 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
7036 kvm_disable_largepages();
7038 if (!cpu_has_vmx_ple()) {
7041 ple_window_grow
= 0;
7043 ple_window_shrink
= 0;
7046 if (!cpu_has_vmx_apicv()) {
7048 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
7051 if (cpu_has_vmx_tsc_scaling()) {
7052 kvm_has_tsc_control
= true;
7053 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
7054 kvm_tsc_scaling_ratio_frac_bits
= 48;
7057 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7064 update_ple_window_actual_max();
7067 * Only enable PML when hardware supports PML feature, and both EPT
7068 * and EPT A/D bit features are enabled -- PML depends on them to work.
7070 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
7074 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
7075 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
7076 kvm_x86_ops
->flush_log_dirty
= NULL
;
7077 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
7080 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
7083 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
7084 cpu_preemption_timer_multi
=
7085 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
7087 kvm_x86_ops
->set_hv_timer
= NULL
;
7088 kvm_x86_ops
->cancel_hv_timer
= NULL
;
7091 if (!cpu_has_vmx_shadow_vmcs())
7092 enable_shadow_vmcs
= 0;
7093 if (enable_shadow_vmcs
)
7094 init_vmcs_shadow_fields();
7096 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
7098 kvm_mce_cap_supported
|= MCG_LMCE_P
;
7100 return alloc_kvm_area();
7103 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
7104 free_page((unsigned long)vmx_bitmap
[i
]);
7109 static __exit
void hardware_unsetup(void)
7113 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
7114 free_page((unsigned long)vmx_bitmap
[i
]);
7120 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7121 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7123 static int handle_pause(struct kvm_vcpu
*vcpu
)
7126 grow_ple_window(vcpu
);
7129 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7130 * VM-execution control is ignored if CPL > 0. OTOH, KVM
7131 * never set PAUSE_EXITING and just set PLE if supported,
7132 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7134 kvm_vcpu_on_spin(vcpu
, true);
7135 return kvm_skip_emulated_instruction(vcpu
);
7138 static int handle_nop(struct kvm_vcpu
*vcpu
)
7140 return kvm_skip_emulated_instruction(vcpu
);
7143 static int handle_mwait(struct kvm_vcpu
*vcpu
)
7145 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
7146 return handle_nop(vcpu
);
7149 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
7151 kvm_queue_exception(vcpu
, UD_VECTOR
);
7155 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
7160 static int handle_monitor(struct kvm_vcpu
*vcpu
)
7162 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
7163 return handle_nop(vcpu
);
7167 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7168 * set the success or error code of an emulated VMX instruction, as specified
7169 * by Vol 2B, VMX Instruction Reference, "Conventions".
7171 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
7173 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
7174 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7175 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
7178 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
7180 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7181 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
7182 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7186 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
7187 u32 vm_instruction_error
)
7189 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
7191 * failValid writes the error number to the current VMCS, which
7192 * can't be done there isn't a current VMCS.
7194 nested_vmx_failInvalid(vcpu
);
7197 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7198 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7199 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7201 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
7203 * We don't need to force a shadow sync because
7204 * VM_INSTRUCTION_ERROR is not shadowed
7208 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
7210 /* TODO: not to reset guest simply here. */
7211 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7212 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
7215 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
7217 struct vcpu_vmx
*vmx
=
7218 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
7220 vmx
->nested
.preemption_timer_expired
= true;
7221 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
7222 kvm_vcpu_kick(&vmx
->vcpu
);
7224 return HRTIMER_NORESTART
;
7228 * Decode the memory-address operand of a vmx instruction, as recorded on an
7229 * exit caused by such an instruction (run by a guest hypervisor).
7230 * On success, returns 0. When the operand is invalid, returns 1 and throws
7233 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
7234 unsigned long exit_qualification
,
7235 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
7239 struct kvm_segment s
;
7242 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7243 * Execution", on an exit, vmx_instruction_info holds most of the
7244 * addressing components of the operand. Only the displacement part
7245 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7246 * For how an actual address is calculated from all these components,
7247 * refer to Vol. 1, "Operand Addressing".
7249 int scaling
= vmx_instruction_info
& 3;
7250 int addr_size
= (vmx_instruction_info
>> 7) & 7;
7251 bool is_reg
= vmx_instruction_info
& (1u << 10);
7252 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
7253 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
7254 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
7255 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
7256 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7259 kvm_queue_exception(vcpu
, UD_VECTOR
);
7263 /* Addr = segment_base + offset */
7264 /* offset = base + [index * scale] + displacement */
7265 off
= exit_qualification
; /* holds the displacement */
7267 off
+= kvm_register_read(vcpu
, base_reg
);
7269 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7270 vmx_get_segment(vcpu
, &s
, seg_reg
);
7271 *ret
= s
.base
+ off
;
7273 if (addr_size
== 1) /* 32 bit */
7276 /* Checks for #GP/#SS exceptions. */
7278 if (is_long_mode(vcpu
)) {
7279 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7280 * non-canonical form. This is the only check on the memory
7281 * destination for long mode!
7283 exn
= is_noncanonical_address(*ret
, vcpu
);
7284 } else if (is_protmode(vcpu
)) {
7285 /* Protected mode: apply checks for segment validity in the
7287 * - segment type check (#GP(0) may be thrown)
7288 * - usability check (#GP(0)/#SS(0))
7289 * - limit check (#GP(0)/#SS(0))
7292 /* #GP(0) if the destination operand is located in a
7293 * read-only data segment or any code segment.
7295 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7297 /* #GP(0) if the source operand is located in an
7298 * execute-only code segment
7300 exn
= ((s
.type
& 0xa) == 8);
7302 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7305 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7307 exn
= (s
.unusable
!= 0);
7308 /* Protected mode: #GP(0)/#SS(0) if the memory
7309 * operand is outside the segment limit.
7311 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7314 kvm_queue_exception_e(vcpu
,
7315 seg_reg
== VCPU_SREG_SS
?
7316 SS_VECTOR
: GP_VECTOR
,
7324 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7327 struct x86_exception e
;
7329 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7330 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7333 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7334 sizeof(*vmpointer
), &e
)) {
7335 kvm_inject_page_fault(vcpu
, &e
);
7342 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7344 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7345 struct vmcs
*shadow_vmcs
;
7348 r
= alloc_loaded_vmcs(&vmx
->nested
.vmcs02
);
7352 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7353 if (!vmx
->nested
.cached_vmcs12
)
7354 goto out_cached_vmcs12
;
7356 if (enable_shadow_vmcs
) {
7357 shadow_vmcs
= alloc_vmcs();
7359 goto out_shadow_vmcs
;
7360 /* mark vmcs as shadow */
7361 shadow_vmcs
->revision_id
|= (1u << 31);
7362 /* init shadow vmcs */
7363 vmcs_clear(shadow_vmcs
);
7364 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7367 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7368 HRTIMER_MODE_REL_PINNED
);
7369 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7371 vmx
->nested
.vmxon
= true;
7375 kfree(vmx
->nested
.cached_vmcs12
);
7378 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
7385 * Emulate the VMXON instruction.
7386 * Currently, we just remember that VMX is active, and do not save or even
7387 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7388 * do not currently need to store anything in that guest-allocated memory
7389 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7390 * argument is different from the VMXON pointer (which the spec says they do).
7392 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7397 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7398 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7399 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7402 * The Intel VMX Instruction Reference lists a bunch of bits that are
7403 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7404 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7405 * Otherwise, we should fail with #UD. But most faulting conditions
7406 * have already been checked by hardware, prior to the VM-exit for
7407 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7408 * that bit set to 1 in non-root mode.
7410 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7411 kvm_queue_exception(vcpu
, UD_VECTOR
);
7415 if (vmx
->nested
.vmxon
) {
7416 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7417 return kvm_skip_emulated_instruction(vcpu
);
7420 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7421 != VMXON_NEEDED_FEATURES
) {
7422 kvm_inject_gp(vcpu
, 0);
7426 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7431 * The first 4 bytes of VMXON region contain the supported
7432 * VMCS revision identifier
7434 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7435 * which replaces physical address width with 32
7437 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7438 nested_vmx_failInvalid(vcpu
);
7439 return kvm_skip_emulated_instruction(vcpu
);
7442 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7443 if (is_error_page(page
)) {
7444 nested_vmx_failInvalid(vcpu
);
7445 return kvm_skip_emulated_instruction(vcpu
);
7447 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7449 kvm_release_page_clean(page
);
7450 nested_vmx_failInvalid(vcpu
);
7451 return kvm_skip_emulated_instruction(vcpu
);
7454 kvm_release_page_clean(page
);
7456 vmx
->nested
.vmxon_ptr
= vmptr
;
7457 ret
= enter_vmx_operation(vcpu
);
7461 nested_vmx_succeed(vcpu
);
7462 return kvm_skip_emulated_instruction(vcpu
);
7466 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7467 * for running VMX instructions (except VMXON, whose prerequisites are
7468 * slightly different). It also specifies what exception to inject otherwise.
7469 * Note that many of these exceptions have priority over VM exits, so they
7470 * don't have to be checked again here.
7472 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7474 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7475 kvm_queue_exception(vcpu
, UD_VECTOR
);
7481 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7483 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7484 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7487 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7489 if (vmx
->nested
.current_vmptr
== -1ull)
7492 if (enable_shadow_vmcs
) {
7493 /* copy to memory all shadowed fields in case
7494 they were modified */
7495 copy_shadow_to_vmcs12(vmx
);
7496 vmx
->nested
.sync_shadow_vmcs
= false;
7497 vmx_disable_shadow_vmcs(vmx
);
7499 vmx
->nested
.posted_intr_nv
= -1;
7501 /* Flush VMCS12 to guest memory */
7502 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7503 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7504 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7506 vmx
->nested
.current_vmptr
= -1ull;
7510 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7511 * just stops using VMX.
7513 static void free_nested(struct vcpu_vmx
*vmx
)
7515 if (!vmx
->nested
.vmxon
&& !vmx
->nested
.smm
.vmxon
)
7518 vmx
->nested
.vmxon
= false;
7519 vmx
->nested
.smm
.vmxon
= false;
7520 free_vpid(vmx
->nested
.vpid02
);
7521 vmx
->nested
.posted_intr_nv
= -1;
7522 vmx
->nested
.current_vmptr
= -1ull;
7523 if (enable_shadow_vmcs
) {
7524 vmx_disable_shadow_vmcs(vmx
);
7525 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7526 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7527 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7529 kfree(vmx
->nested
.cached_vmcs12
);
7530 /* Unpin physical memory we referred to in the vmcs02 */
7531 if (vmx
->nested
.apic_access_page
) {
7532 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7533 vmx
->nested
.apic_access_page
= NULL
;
7535 if (vmx
->nested
.virtual_apic_page
) {
7536 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7537 vmx
->nested
.virtual_apic_page
= NULL
;
7539 if (vmx
->nested
.pi_desc_page
) {
7540 kunmap(vmx
->nested
.pi_desc_page
);
7541 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7542 vmx
->nested
.pi_desc_page
= NULL
;
7543 vmx
->nested
.pi_desc
= NULL
;
7546 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
7549 /* Emulate the VMXOFF instruction */
7550 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7552 if (!nested_vmx_check_permission(vcpu
))
7554 free_nested(to_vmx(vcpu
));
7555 nested_vmx_succeed(vcpu
);
7556 return kvm_skip_emulated_instruction(vcpu
);
7559 /* Emulate the VMCLEAR instruction */
7560 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7562 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7566 if (!nested_vmx_check_permission(vcpu
))
7569 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7572 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7573 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7574 return kvm_skip_emulated_instruction(vcpu
);
7577 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7578 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7579 return kvm_skip_emulated_instruction(vcpu
);
7582 if (vmptr
== vmx
->nested
.current_vmptr
)
7583 nested_release_vmcs12(vmx
);
7585 kvm_vcpu_write_guest(vcpu
,
7586 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7587 &zero
, sizeof(zero
));
7589 nested_vmx_succeed(vcpu
);
7590 return kvm_skip_emulated_instruction(vcpu
);
7593 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7595 /* Emulate the VMLAUNCH instruction */
7596 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7598 return nested_vmx_run(vcpu
, true);
7601 /* Emulate the VMRESUME instruction */
7602 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7605 return nested_vmx_run(vcpu
, false);
7609 * Read a vmcs12 field. Since these can have varying lengths and we return
7610 * one type, we chose the biggest type (u64) and zero-extend the return value
7611 * to that size. Note that the caller, handle_vmread, might need to use only
7612 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7613 * 64-bit fields are to be returned).
7615 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7616 unsigned long field
, u64
*ret
)
7618 short offset
= vmcs_field_to_offset(field
);
7624 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7626 switch (vmcs_field_width(field
)) {
7627 case VMCS_FIELD_WIDTH_NATURAL_WIDTH
:
7628 *ret
= *((natural_width
*)p
);
7630 case VMCS_FIELD_WIDTH_U16
:
7633 case VMCS_FIELD_WIDTH_U32
:
7636 case VMCS_FIELD_WIDTH_U64
:
7646 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7647 unsigned long field
, u64 field_value
){
7648 short offset
= vmcs_field_to_offset(field
);
7649 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7653 switch (vmcs_field_width(field
)) {
7654 case VMCS_FIELD_WIDTH_U16
:
7655 *(u16
*)p
= field_value
;
7657 case VMCS_FIELD_WIDTH_U32
:
7658 *(u32
*)p
= field_value
;
7660 case VMCS_FIELD_WIDTH_U64
:
7661 *(u64
*)p
= field_value
;
7663 case VMCS_FIELD_WIDTH_NATURAL_WIDTH
:
7664 *(natural_width
*)p
= field_value
;
7673 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7676 unsigned long field
;
7678 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7679 const u16
*fields
= shadow_read_write_fields
;
7680 const int num_fields
= max_shadow_read_write_fields
;
7684 vmcs_load(shadow_vmcs
);
7686 for (i
= 0; i
< num_fields
; i
++) {
7688 field_value
= __vmcs_readl(field
);
7689 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7692 vmcs_clear(shadow_vmcs
);
7693 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7698 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7700 const u16
*fields
[] = {
7701 shadow_read_write_fields
,
7702 shadow_read_only_fields
7704 const int max_fields
[] = {
7705 max_shadow_read_write_fields
,
7706 max_shadow_read_only_fields
7709 unsigned long field
;
7710 u64 field_value
= 0;
7711 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7713 vmcs_load(shadow_vmcs
);
7715 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7716 for (i
= 0; i
< max_fields
[q
]; i
++) {
7717 field
= fields
[q
][i
];
7718 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7719 __vmcs_writel(field
, field_value
);
7723 vmcs_clear(shadow_vmcs
);
7724 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7728 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7729 * used before) all generate the same failure when it is missing.
7731 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7733 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7734 if (vmx
->nested
.current_vmptr
== -1ull) {
7735 nested_vmx_failInvalid(vcpu
);
7741 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7743 unsigned long field
;
7745 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7746 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7749 if (!nested_vmx_check_permission(vcpu
))
7752 if (!nested_vmx_check_vmcs12(vcpu
))
7753 return kvm_skip_emulated_instruction(vcpu
);
7755 /* Decode instruction info and find the field to read */
7756 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7757 /* Read the field, zero-extended to a u64 field_value */
7758 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7759 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7760 return kvm_skip_emulated_instruction(vcpu
);
7763 * Now copy part of this value to register or memory, as requested.
7764 * Note that the number of bits actually copied is 32 or 64 depending
7765 * on the guest's mode (32 or 64 bit), not on the given field's length.
7767 if (vmx_instruction_info
& (1u << 10)) {
7768 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7771 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7772 vmx_instruction_info
, true, &gva
))
7774 /* _system ok, as hardware has verified cpl=0 */
7775 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7776 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7779 nested_vmx_succeed(vcpu
);
7780 return kvm_skip_emulated_instruction(vcpu
);
7784 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7786 unsigned long field
;
7788 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7789 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7790 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7792 /* The value to write might be 32 or 64 bits, depending on L1's long
7793 * mode, and eventually we need to write that into a field of several
7794 * possible lengths. The code below first zero-extends the value to 64
7795 * bit (field_value), and then copies only the appropriate number of
7796 * bits into the vmcs12 field.
7798 u64 field_value
= 0;
7799 struct x86_exception e
;
7801 if (!nested_vmx_check_permission(vcpu
))
7804 if (!nested_vmx_check_vmcs12(vcpu
))
7805 return kvm_skip_emulated_instruction(vcpu
);
7807 if (vmx_instruction_info
& (1u << 10))
7808 field_value
= kvm_register_readl(vcpu
,
7809 (((vmx_instruction_info
) >> 3) & 0xf));
7811 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7812 vmx_instruction_info
, false, &gva
))
7814 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7815 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7816 kvm_inject_page_fault(vcpu
, &e
);
7822 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7823 if (vmcs_field_readonly(field
)) {
7824 nested_vmx_failValid(vcpu
,
7825 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7826 return kvm_skip_emulated_instruction(vcpu
);
7829 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7830 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7831 return kvm_skip_emulated_instruction(vcpu
);
7835 #define SHADOW_FIELD_RW(x) case x:
7836 #include "vmx_shadow_fields.h"
7838 * The fields that can be updated by L1 without a vmexit are
7839 * always updated in the vmcs02, the others go down the slow
7840 * path of prepare_vmcs02.
7844 vmx
->nested
.dirty_vmcs12
= true;
7848 nested_vmx_succeed(vcpu
);
7849 return kvm_skip_emulated_instruction(vcpu
);
7852 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7854 vmx
->nested
.current_vmptr
= vmptr
;
7855 if (enable_shadow_vmcs
) {
7856 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7857 SECONDARY_EXEC_SHADOW_VMCS
);
7858 vmcs_write64(VMCS_LINK_POINTER
,
7859 __pa(vmx
->vmcs01
.shadow_vmcs
));
7860 vmx
->nested
.sync_shadow_vmcs
= true;
7862 vmx
->nested
.dirty_vmcs12
= true;
7865 /* Emulate the VMPTRLD instruction */
7866 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7868 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7871 if (!nested_vmx_check_permission(vcpu
))
7874 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7877 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7878 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7879 return kvm_skip_emulated_instruction(vcpu
);
7882 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7883 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7884 return kvm_skip_emulated_instruction(vcpu
);
7887 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7888 struct vmcs12
*new_vmcs12
;
7890 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7891 if (is_error_page(page
)) {
7892 nested_vmx_failInvalid(vcpu
);
7893 return kvm_skip_emulated_instruction(vcpu
);
7895 new_vmcs12
= kmap(page
);
7896 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7898 kvm_release_page_clean(page
);
7899 nested_vmx_failValid(vcpu
,
7900 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7901 return kvm_skip_emulated_instruction(vcpu
);
7904 nested_release_vmcs12(vmx
);
7906 * Load VMCS12 from guest memory since it is not already
7909 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7911 kvm_release_page_clean(page
);
7913 set_current_vmptr(vmx
, vmptr
);
7916 nested_vmx_succeed(vcpu
);
7917 return kvm_skip_emulated_instruction(vcpu
);
7920 /* Emulate the VMPTRST instruction */
7921 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7923 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7924 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7926 struct x86_exception e
;
7928 if (!nested_vmx_check_permission(vcpu
))
7931 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7932 vmx_instruction_info
, true, &vmcs_gva
))
7934 /* ok to use *_system, as hardware has verified cpl=0 */
7935 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7936 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7938 kvm_inject_page_fault(vcpu
, &e
);
7941 nested_vmx_succeed(vcpu
);
7942 return kvm_skip_emulated_instruction(vcpu
);
7945 /* Emulate the INVEPT instruction */
7946 static int handle_invept(struct kvm_vcpu
*vcpu
)
7948 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7949 u32 vmx_instruction_info
, types
;
7952 struct x86_exception e
;
7957 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7958 SECONDARY_EXEC_ENABLE_EPT
) ||
7959 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7960 kvm_queue_exception(vcpu
, UD_VECTOR
);
7964 if (!nested_vmx_check_permission(vcpu
))
7967 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7968 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7970 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7972 if (type
>= 32 || !(types
& (1 << type
))) {
7973 nested_vmx_failValid(vcpu
,
7974 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7975 return kvm_skip_emulated_instruction(vcpu
);
7978 /* According to the Intel VMX instruction reference, the memory
7979 * operand is read even if it isn't needed (e.g., for type==global)
7981 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7982 vmx_instruction_info
, false, &gva
))
7984 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7985 sizeof(operand
), &e
)) {
7986 kvm_inject_page_fault(vcpu
, &e
);
7991 case VMX_EPT_EXTENT_GLOBAL
:
7993 * TODO: track mappings and invalidate
7994 * single context requests appropriately
7996 case VMX_EPT_EXTENT_CONTEXT
:
7997 kvm_mmu_sync_roots(vcpu
);
7998 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7999 nested_vmx_succeed(vcpu
);
8006 return kvm_skip_emulated_instruction(vcpu
);
8009 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
8011 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8012 u32 vmx_instruction_info
;
8013 unsigned long type
, types
;
8015 struct x86_exception e
;
8021 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
8022 SECONDARY_EXEC_ENABLE_VPID
) ||
8023 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
8024 kvm_queue_exception(vcpu
, UD_VECTOR
);
8028 if (!nested_vmx_check_permission(vcpu
))
8031 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8032 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
8034 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
8035 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
8037 if (type
>= 32 || !(types
& (1 << type
))) {
8038 nested_vmx_failValid(vcpu
,
8039 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8040 return kvm_skip_emulated_instruction(vcpu
);
8043 /* according to the intel vmx instruction reference, the memory
8044 * operand is read even if it isn't needed (e.g., for type==global)
8046 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
8047 vmx_instruction_info
, false, &gva
))
8049 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
8050 sizeof(operand
), &e
)) {
8051 kvm_inject_page_fault(vcpu
, &e
);
8054 if (operand
.vpid
>> 16) {
8055 nested_vmx_failValid(vcpu
,
8056 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8057 return kvm_skip_emulated_instruction(vcpu
);
8061 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
8062 if (is_noncanonical_address(operand
.gla
, vcpu
)) {
8063 nested_vmx_failValid(vcpu
,
8064 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8065 return kvm_skip_emulated_instruction(vcpu
);
8068 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
8069 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
8070 if (!operand
.vpid
) {
8071 nested_vmx_failValid(vcpu
,
8072 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8073 return kvm_skip_emulated_instruction(vcpu
);
8076 case VMX_VPID_EXTENT_ALL_CONTEXT
:
8080 return kvm_skip_emulated_instruction(vcpu
);
8083 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
, true);
8084 nested_vmx_succeed(vcpu
);
8086 return kvm_skip_emulated_instruction(vcpu
);
8089 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
8091 unsigned long exit_qualification
;
8093 trace_kvm_pml_full(vcpu
->vcpu_id
);
8095 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8098 * PML buffer FULL happened while executing iret from NMI,
8099 * "blocked by NMI" bit has to be set before next VM entry.
8101 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8103 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
8104 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8105 GUEST_INTR_STATE_NMI
);
8108 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8109 * here.., and there's no userspace involvement needed for PML.
8114 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
8116 kvm_lapic_expired_hv_timer(vcpu
);
8120 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
8122 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8123 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8125 /* Check for memory type validity */
8126 switch (address
& VMX_EPTP_MT_MASK
) {
8127 case VMX_EPTP_MT_UC
:
8128 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
8131 case VMX_EPTP_MT_WB
:
8132 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
8139 /* only 4 levels page-walk length are valid */
8140 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
8143 /* Reserved bits should not be set */
8144 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
8147 /* AD, if set, should be supported */
8148 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
8149 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
8156 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
8157 struct vmcs12
*vmcs12
)
8159 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8161 bool accessed_dirty
;
8162 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
8164 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
8165 !nested_cpu_has_ept(vmcs12
))
8168 if (index
>= VMFUNC_EPTP_ENTRIES
)
8172 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
8173 &address
, index
* 8, 8))
8176 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
8179 * If the (L2) guest does a vmfunc to the currently
8180 * active ept pointer, we don't have to do anything else
8182 if (vmcs12
->ept_pointer
!= address
) {
8183 if (!valid_ept_address(vcpu
, address
))
8186 kvm_mmu_unload(vcpu
);
8187 mmu
->ept_ad
= accessed_dirty
;
8188 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
8189 vmcs12
->ept_pointer
= address
;
8191 * TODO: Check what's the correct approach in case
8192 * mmu reload fails. Currently, we just let the next
8193 * reload potentially fail
8195 kvm_mmu_reload(vcpu
);
8201 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
8203 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8204 struct vmcs12
*vmcs12
;
8205 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
8208 * VMFUNC is only supported for nested guests, but we always enable the
8209 * secondary control for simplicity; for non-nested mode, fake that we
8210 * didn't by injecting #UD.
8212 if (!is_guest_mode(vcpu
)) {
8213 kvm_queue_exception(vcpu
, UD_VECTOR
);
8217 vmcs12
= get_vmcs12(vcpu
);
8218 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
8223 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
8229 return kvm_skip_emulated_instruction(vcpu
);
8232 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8233 vmcs_read32(VM_EXIT_INTR_INFO
),
8234 vmcs_readl(EXIT_QUALIFICATION
));
8239 * The exit handlers return 1 if the exit was handled fully and guest execution
8240 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8241 * to be done to userspace and return 0.
8243 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8244 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8245 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8246 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8247 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8248 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8249 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8250 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8251 [EXIT_REASON_CPUID
] = handle_cpuid
,
8252 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8253 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8254 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8255 [EXIT_REASON_HLT
] = handle_halt
,
8256 [EXIT_REASON_INVD
] = handle_invd
,
8257 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8258 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8259 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8260 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8261 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8262 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8263 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8264 [EXIT_REASON_VMREAD
] = handle_vmread
,
8265 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8266 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8267 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8268 [EXIT_REASON_VMON
] = handle_vmon
,
8269 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8270 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8271 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8272 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8273 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8274 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8275 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8276 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8277 [EXIT_REASON_GDTR_IDTR
] = handle_desc
,
8278 [EXIT_REASON_LDTR_TR
] = handle_desc
,
8279 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8280 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8281 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8282 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8283 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8284 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8285 [EXIT_REASON_INVEPT
] = handle_invept
,
8286 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8287 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
8288 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
8289 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8290 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8291 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8292 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8293 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8296 static const int kvm_vmx_max_exit_handlers
=
8297 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8299 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8300 struct vmcs12
*vmcs12
)
8302 unsigned long exit_qualification
;
8303 gpa_t bitmap
, last_bitmap
;
8308 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8309 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8311 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8313 port
= exit_qualification
>> 16;
8314 size
= (exit_qualification
& 7) + 1;
8316 last_bitmap
= (gpa_t
)-1;
8321 bitmap
= vmcs12
->io_bitmap_a
;
8322 else if (port
< 0x10000)
8323 bitmap
= vmcs12
->io_bitmap_b
;
8326 bitmap
+= (port
& 0x7fff) / 8;
8328 if (last_bitmap
!= bitmap
)
8329 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8331 if (b
& (1 << (port
& 7)))
8336 last_bitmap
= bitmap
;
8343 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8344 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8345 * disinterest in the current event (read or write a specific MSR) by using an
8346 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8348 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8349 struct vmcs12
*vmcs12
, u32 exit_reason
)
8351 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8354 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8358 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8359 * for the four combinations of read/write and low/high MSR numbers.
8360 * First we need to figure out which of the four to use:
8362 bitmap
= vmcs12
->msr_bitmap
;
8363 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8365 if (msr_index
>= 0xc0000000) {
8366 msr_index
-= 0xc0000000;
8370 /* Then read the msr_index'th bit from this bitmap: */
8371 if (msr_index
< 1024*8) {
8373 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8375 return 1 & (b
>> (msr_index
& 7));
8377 return true; /* let L1 handle the wrong parameter */
8381 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8382 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8383 * intercept (via guest_host_mask etc.) the current event.
8385 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8386 struct vmcs12
*vmcs12
)
8388 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8389 int cr
= exit_qualification
& 15;
8393 switch ((exit_qualification
>> 4) & 3) {
8394 case 0: /* mov to cr */
8395 reg
= (exit_qualification
>> 8) & 15;
8396 val
= kvm_register_readl(vcpu
, reg
);
8399 if (vmcs12
->cr0_guest_host_mask
&
8400 (val
^ vmcs12
->cr0_read_shadow
))
8404 if ((vmcs12
->cr3_target_count
>= 1 &&
8405 vmcs12
->cr3_target_value0
== val
) ||
8406 (vmcs12
->cr3_target_count
>= 2 &&
8407 vmcs12
->cr3_target_value1
== val
) ||
8408 (vmcs12
->cr3_target_count
>= 3 &&
8409 vmcs12
->cr3_target_value2
== val
) ||
8410 (vmcs12
->cr3_target_count
>= 4 &&
8411 vmcs12
->cr3_target_value3
== val
))
8413 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8417 if (vmcs12
->cr4_guest_host_mask
&
8418 (vmcs12
->cr4_read_shadow
^ val
))
8422 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8428 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8429 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8432 case 1: /* mov from cr */
8435 if (vmcs12
->cpu_based_vm_exec_control
&
8436 CPU_BASED_CR3_STORE_EXITING
)
8440 if (vmcs12
->cpu_based_vm_exec_control
&
8441 CPU_BASED_CR8_STORE_EXITING
)
8448 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8449 * cr0. Other attempted changes are ignored, with no exit.
8451 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8452 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8453 (val
^ vmcs12
->cr0_read_shadow
))
8455 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8456 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8465 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8466 * should handle it ourselves in L0 (and then continue L2). Only call this
8467 * when in is_guest_mode (L2).
8469 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8471 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8472 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8473 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8475 if (vmx
->nested
.nested_run_pending
)
8478 if (unlikely(vmx
->fail
)) {
8479 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8480 vmcs_read32(VM_INSTRUCTION_ERROR
));
8485 * The host physical addresses of some pages of guest memory
8486 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8487 * Page). The CPU may write to these pages via their host
8488 * physical address while L2 is running, bypassing any
8489 * address-translation-based dirty tracking (e.g. EPT write
8492 * Mark them dirty on every exit from L2 to prevent them from
8493 * getting out of sync with dirty tracking.
8495 nested_mark_vmcs12_pages_dirty(vcpu
);
8497 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8498 vmcs_readl(EXIT_QUALIFICATION
),
8499 vmx
->idt_vectoring_info
,
8501 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8504 switch (exit_reason
) {
8505 case EXIT_REASON_EXCEPTION_NMI
:
8506 if (is_nmi(intr_info
))
8508 else if (is_page_fault(intr_info
))
8509 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8510 else if (is_no_device(intr_info
) &&
8511 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8513 else if (is_debug(intr_info
) &&
8515 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8517 else if (is_breakpoint(intr_info
) &&
8518 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8520 return vmcs12
->exception_bitmap
&
8521 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8522 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8524 case EXIT_REASON_TRIPLE_FAULT
:
8526 case EXIT_REASON_PENDING_INTERRUPT
:
8527 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8528 case EXIT_REASON_NMI_WINDOW
:
8529 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8530 case EXIT_REASON_TASK_SWITCH
:
8532 case EXIT_REASON_CPUID
:
8534 case EXIT_REASON_HLT
:
8535 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8536 case EXIT_REASON_INVD
:
8538 case EXIT_REASON_INVLPG
:
8539 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8540 case EXIT_REASON_RDPMC
:
8541 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8542 case EXIT_REASON_RDRAND
:
8543 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND_EXITING
);
8544 case EXIT_REASON_RDSEED
:
8545 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED_EXITING
);
8546 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8547 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8548 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8549 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8550 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8551 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8552 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8553 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8555 * VMX instructions trap unconditionally. This allows L1 to
8556 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8559 case EXIT_REASON_CR_ACCESS
:
8560 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8561 case EXIT_REASON_DR_ACCESS
:
8562 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8563 case EXIT_REASON_IO_INSTRUCTION
:
8564 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8565 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8566 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8567 case EXIT_REASON_MSR_READ
:
8568 case EXIT_REASON_MSR_WRITE
:
8569 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8570 case EXIT_REASON_INVALID_STATE
:
8572 case EXIT_REASON_MWAIT_INSTRUCTION
:
8573 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8574 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8575 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8576 case EXIT_REASON_MONITOR_INSTRUCTION
:
8577 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8578 case EXIT_REASON_PAUSE_INSTRUCTION
:
8579 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8580 nested_cpu_has2(vmcs12
,
8581 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8582 case EXIT_REASON_MCE_DURING_VMENTRY
:
8584 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8585 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8586 case EXIT_REASON_APIC_ACCESS
:
8587 return nested_cpu_has2(vmcs12
,
8588 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8589 case EXIT_REASON_APIC_WRITE
:
8590 case EXIT_REASON_EOI_INDUCED
:
8591 /* apic_write and eoi_induced should exit unconditionally. */
8593 case EXIT_REASON_EPT_VIOLATION
:
8595 * L0 always deals with the EPT violation. If nested EPT is
8596 * used, and the nested mmu code discovers that the address is
8597 * missing in the guest EPT table (EPT12), the EPT violation
8598 * will be injected with nested_ept_inject_page_fault()
8601 case EXIT_REASON_EPT_MISCONFIG
:
8603 * L2 never uses directly L1's EPT, but rather L0's own EPT
8604 * table (shadow on EPT) or a merged EPT table that L0 built
8605 * (EPT on EPT). So any problems with the structure of the
8606 * table is L0's fault.
8609 case EXIT_REASON_INVPCID
:
8611 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8612 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8613 case EXIT_REASON_WBINVD
:
8614 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8615 case EXIT_REASON_XSETBV
:
8617 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8619 * This should never happen, since it is not possible to
8620 * set XSS to a non-zero value---neither in L1 nor in L2.
8621 * If if it were, XSS would have to be checked against
8622 * the XSS exit bitmap in vmcs12.
8624 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8625 case EXIT_REASON_PREEMPTION_TIMER
:
8627 case EXIT_REASON_PML_FULL
:
8628 /* We emulate PML support to L1. */
8630 case EXIT_REASON_VMFUNC
:
8631 /* VM functions are emulated through L2->L0 vmexits. */
8638 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8640 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8643 * At this point, the exit interruption info in exit_intr_info
8644 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8645 * we need to query the in-kernel LAPIC.
8647 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8648 if ((exit_intr_info
&
8649 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8650 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8651 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8652 vmcs12
->vm_exit_intr_error_code
=
8653 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8656 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8657 vmcs_readl(EXIT_QUALIFICATION
));
8661 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8663 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8664 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8667 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8670 __free_page(vmx
->pml_pg
);
8675 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8681 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8683 /* Do nothing if PML buffer is empty */
8684 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8687 /* PML index always points to next available PML buffer entity */
8688 if (pml_idx
>= PML_ENTITY_NUM
)
8693 pml_buf
= page_address(vmx
->pml_pg
);
8694 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8697 gpa
= pml_buf
[pml_idx
];
8698 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8699 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8702 /* reset PML index */
8703 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8707 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8708 * Called before reporting dirty_bitmap to userspace.
8710 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8713 struct kvm_vcpu
*vcpu
;
8715 * We only need to kick vcpu out of guest mode here, as PML buffer
8716 * is flushed at beginning of all VMEXITs, and it's obvious that only
8717 * vcpus running in guest are possible to have unflushed GPAs in PML
8720 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8721 kvm_vcpu_kick(vcpu
);
8724 static void vmx_dump_sel(char *name
, uint32_t sel
)
8726 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8727 name
, vmcs_read16(sel
),
8728 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8729 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8730 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8733 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8735 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8736 name
, vmcs_read32(limit
),
8737 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8740 static void dump_vmcs(void)
8742 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8743 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8744 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8745 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8746 u32 secondary_exec_control
= 0;
8747 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8748 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8751 if (cpu_has_secondary_exec_ctrls())
8752 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8754 pr_err("*** Guest State ***\n");
8755 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8756 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8757 vmcs_readl(CR0_GUEST_HOST_MASK
));
8758 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8759 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8760 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8761 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8762 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8764 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8765 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8766 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8767 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8769 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8770 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8771 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8772 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8773 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8774 vmcs_readl(GUEST_SYSENTER_ESP
),
8775 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8776 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8777 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8778 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8779 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8780 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8781 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8782 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8783 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8784 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8785 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8786 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8787 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8788 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8789 efer
, vmcs_read64(GUEST_IA32_PAT
));
8790 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8791 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8792 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8793 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8794 pr_err("PerfGlobCtl = 0x%016llx\n",
8795 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8796 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8797 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8798 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8799 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8800 vmcs_read32(GUEST_ACTIVITY_STATE
));
8801 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8802 pr_err("InterruptStatus = %04x\n",
8803 vmcs_read16(GUEST_INTR_STATUS
));
8805 pr_err("*** Host State ***\n");
8806 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8807 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8808 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8809 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8810 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8811 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8812 vmcs_read16(HOST_TR_SELECTOR
));
8813 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8814 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8815 vmcs_readl(HOST_TR_BASE
));
8816 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8817 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8818 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8819 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8820 vmcs_readl(HOST_CR4
));
8821 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8822 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8823 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8824 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8825 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8826 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8827 vmcs_read64(HOST_IA32_EFER
),
8828 vmcs_read64(HOST_IA32_PAT
));
8829 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8830 pr_err("PerfGlobCtl = 0x%016llx\n",
8831 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8833 pr_err("*** Control State ***\n");
8834 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8835 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8836 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8837 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8838 vmcs_read32(EXCEPTION_BITMAP
),
8839 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8840 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8841 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8842 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8843 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8844 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8845 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8846 vmcs_read32(VM_EXIT_INTR_INFO
),
8847 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8848 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8849 pr_err(" reason=%08x qualification=%016lx\n",
8850 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8851 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8852 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8853 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8854 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8855 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8856 pr_err("TSC Multiplier = 0x%016llx\n",
8857 vmcs_read64(TSC_MULTIPLIER
));
8858 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8859 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8860 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8861 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8862 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8863 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8864 n
= vmcs_read32(CR3_TARGET_COUNT
);
8865 for (i
= 0; i
+ 1 < n
; i
+= 4)
8866 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8867 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8868 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8870 pr_err("CR3 target%u=%016lx\n",
8871 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8872 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8873 pr_err("PLE Gap=%08x Window=%08x\n",
8874 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8875 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8876 pr_err("Virtual processor ID = 0x%04x\n",
8877 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8881 * The guest has exited. See if we can fix it or if we need userspace
8884 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8886 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8887 u32 exit_reason
= vmx
->exit_reason
;
8888 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8890 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8893 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8894 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8895 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8896 * mode as if vcpus is in root mode, the PML buffer must has been
8900 vmx_flush_pml_buffer(vcpu
);
8902 /* If guest state is invalid, start emulating */
8903 if (vmx
->emulation_required
)
8904 return handle_invalid_guest_state(vcpu
);
8906 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8907 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8909 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8911 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8912 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8917 if (unlikely(vmx
->fail
)) {
8918 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8919 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8920 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8926 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8927 * delivery event since it indicates guest is accessing MMIO.
8928 * The vm-exit can be triggered again after return to guest that
8929 * will cause infinite loop.
8931 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8932 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8933 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8934 exit_reason
!= EXIT_REASON_PML_FULL
&&
8935 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8936 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8937 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8938 vcpu
->run
->internal
.ndata
= 3;
8939 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8940 vcpu
->run
->internal
.data
[1] = exit_reason
;
8941 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8942 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8943 vcpu
->run
->internal
.ndata
++;
8944 vcpu
->run
->internal
.data
[3] =
8945 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8950 if (unlikely(!enable_vnmi
&&
8951 vmx
->loaded_vmcs
->soft_vnmi_blocked
)) {
8952 if (vmx_interrupt_allowed(vcpu
)) {
8953 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8954 } else if (vmx
->loaded_vmcs
->vnmi_blocked_time
> 1000000000LL &&
8955 vcpu
->arch
.nmi_pending
) {
8957 * This CPU don't support us in finding the end of an
8958 * NMI-blocked window if the guest runs with IRQs
8959 * disabled. So we pull the trigger after 1 s of
8960 * futile waiting, but inform the user about this.
8962 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8963 "state on VCPU %d after 1 s timeout\n",
8964 __func__
, vcpu
->vcpu_id
);
8965 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8969 if (exit_reason
< kvm_vmx_max_exit_handlers
8970 && kvm_vmx_exit_handlers
[exit_reason
])
8971 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8973 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8975 kvm_queue_exception(vcpu
, UD_VECTOR
);
8980 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8982 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8984 if (is_guest_mode(vcpu
) &&
8985 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8988 if (irr
== -1 || tpr
< irr
) {
8989 vmcs_write32(TPR_THRESHOLD
, 0);
8993 vmcs_write32(TPR_THRESHOLD
, irr
);
8996 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8998 u32 sec_exec_control
;
9000 /* Postpone execution until vmcs01 is the current VMCS. */
9001 if (is_guest_mode(vcpu
)) {
9002 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
9006 if (!cpu_has_vmx_virtualize_x2apic_mode())
9009 if (!cpu_need_tpr_shadow(vcpu
))
9012 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9015 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9016 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
9018 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
9019 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9020 vmx_flush_tlb_ept_only(vcpu
);
9022 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
9024 vmx_update_msr_bitmap(vcpu
);
9027 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
9029 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9032 * Currently we do not handle the nested case where L2 has an
9033 * APIC access page of its own; that page is still pinned.
9034 * Hence, we skip the case where the VCPU is in guest mode _and_
9035 * L1 prepared an APIC access page for L2.
9037 * For the case where L1 and L2 share the same APIC access page
9038 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
9039 * in the vmcs12), this function will only update either the vmcs01
9040 * or the vmcs02. If the former, the vmcs02 will be updated by
9041 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
9042 * the next L2->L1 exit.
9044 if (!is_guest_mode(vcpu
) ||
9045 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
9046 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9047 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9048 vmx_flush_tlb_ept_only(vcpu
);
9052 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
9060 status
= vmcs_read16(GUEST_INTR_STATUS
);
9062 if (max_isr
!= old
) {
9064 status
|= max_isr
<< 8;
9065 vmcs_write16(GUEST_INTR_STATUS
, status
);
9069 static void vmx_set_rvi(int vector
)
9077 status
= vmcs_read16(GUEST_INTR_STATUS
);
9078 old
= (u8
)status
& 0xff;
9079 if ((u8
)vector
!= old
) {
9081 status
|= (u8
)vector
;
9082 vmcs_write16(GUEST_INTR_STATUS
, status
);
9086 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
9089 * When running L2, updating RVI is only relevant when
9090 * vmcs12 virtual-interrupt-delivery enabled.
9091 * However, it can be enabled only when L1 also
9092 * intercepts external-interrupts and in that case
9093 * we should not update vmcs02 RVI but instead intercept
9094 * interrupt. Therefore, do nothing when running L2.
9096 if (!is_guest_mode(vcpu
))
9097 vmx_set_rvi(max_irr
);
9100 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
9102 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9104 bool max_irr_updated
;
9106 WARN_ON(!vcpu
->arch
.apicv_active
);
9107 if (pi_test_on(&vmx
->pi_desc
)) {
9108 pi_clear_on(&vmx
->pi_desc
);
9110 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9111 * But on x86 this is just a compiler barrier anyway.
9113 smp_mb__after_atomic();
9115 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
, &max_irr
);
9118 * If we are running L2 and L1 has a new pending interrupt
9119 * which can be injected, we should re-evaluate
9120 * what should be done with this new L1 interrupt.
9121 * If L1 intercepts external-interrupts, we should
9122 * exit from L2 to L1. Otherwise, interrupt should be
9123 * delivered directly to L2.
9125 if (is_guest_mode(vcpu
) && max_irr_updated
) {
9126 if (nested_exit_on_intr(vcpu
))
9127 kvm_vcpu_exiting_guest_mode(vcpu
);
9129 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9132 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
9134 vmx_hwapic_irr_update(vcpu
, max_irr
);
9138 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
9140 if (!kvm_vcpu_apicv_active(vcpu
))
9143 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
9144 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
9145 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
9146 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
9149 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
9151 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9153 pi_clear_on(&vmx
->pi_desc
);
9154 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
9157 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
9159 u32 exit_intr_info
= 0;
9160 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
9162 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
9163 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
9166 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9167 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9168 vmx
->exit_intr_info
= exit_intr_info
;
9170 /* if exit due to PF check for async PF */
9171 if (is_page_fault(exit_intr_info
))
9172 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
9174 /* Handle machine checks before interrupts are enabled */
9175 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
9176 is_machine_check(exit_intr_info
))
9177 kvm_machine_check();
9179 /* We need to handle NMIs before interrupts are enabled */
9180 if (is_nmi(exit_intr_info
)) {
9181 kvm_before_handle_nmi(&vmx
->vcpu
);
9183 kvm_after_handle_nmi(&vmx
->vcpu
);
9187 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
9189 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9191 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
9192 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
9193 unsigned int vector
;
9194 unsigned long entry
;
9196 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9197 #ifdef CONFIG_X86_64
9201 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9202 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
9203 entry
= gate_offset(desc
);
9205 #ifdef CONFIG_X86_64
9206 "mov %%" _ASM_SP
", %[sp]\n\t"
9207 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
9212 __ASM_SIZE(push
) " $%c[cs]\n\t"
9215 #ifdef CONFIG_X86_64
9220 THUNK_TARGET(entry
),
9221 [ss
]"i"(__KERNEL_DS
),
9222 [cs
]"i"(__KERNEL_CS
)
9226 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
9228 static bool vmx_has_high_real_mode_segbase(void)
9230 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
9233 static bool vmx_mpx_supported(void)
9235 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
9236 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
9239 static bool vmx_xsaves_supported(void)
9241 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9242 SECONDARY_EXEC_XSAVES
;
9245 static bool vmx_umip_emulated(void)
9247 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9248 SECONDARY_EXEC_DESC
;
9251 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
9256 bool idtv_info_valid
;
9258 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9261 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9264 * Can't use vmx->exit_intr_info since we're not sure what
9265 * the exit reason is.
9267 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9268 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9269 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9271 * SDM 3: 27.7.1.2 (September 2008)
9272 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9273 * a guest IRET fault.
9274 * SDM 3: 23.2.2 (September 2008)
9275 * Bit 12 is undefined in any of the following cases:
9276 * If the VM exit sets the valid bit in the IDT-vectoring
9277 * information field.
9278 * If the VM exit is due to a double fault.
9280 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9281 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9282 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9283 GUEST_INTR_STATE_NMI
);
9285 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9286 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9287 & GUEST_INTR_STATE_NMI
);
9288 } else if (unlikely(vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9289 vmx
->loaded_vmcs
->vnmi_blocked_time
+=
9290 ktime_to_ns(ktime_sub(ktime_get(),
9291 vmx
->loaded_vmcs
->entry_time
));
9294 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9295 u32 idt_vectoring_info
,
9296 int instr_len_field
,
9297 int error_code_field
)
9301 bool idtv_info_valid
;
9303 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9305 vcpu
->arch
.nmi_injected
= false;
9306 kvm_clear_exception_queue(vcpu
);
9307 kvm_clear_interrupt_queue(vcpu
);
9309 if (!idtv_info_valid
)
9312 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9314 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9315 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9318 case INTR_TYPE_NMI_INTR
:
9319 vcpu
->arch
.nmi_injected
= true;
9321 * SDM 3: 27.7.1.2 (September 2008)
9322 * Clear bit "block by NMI" before VM entry if a NMI
9325 vmx_set_nmi_mask(vcpu
, false);
9327 case INTR_TYPE_SOFT_EXCEPTION
:
9328 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9330 case INTR_TYPE_HARD_EXCEPTION
:
9331 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9332 u32 err
= vmcs_read32(error_code_field
);
9333 kvm_requeue_exception_e(vcpu
, vector
, err
);
9335 kvm_requeue_exception(vcpu
, vector
);
9337 case INTR_TYPE_SOFT_INTR
:
9338 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9340 case INTR_TYPE_EXT_INTR
:
9341 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9348 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9350 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9351 VM_EXIT_INSTRUCTION_LEN
,
9352 IDT_VECTORING_ERROR_CODE
);
9355 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9357 __vmx_complete_interrupts(vcpu
,
9358 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9359 VM_ENTRY_INSTRUCTION_LEN
,
9360 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9362 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9365 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9368 struct perf_guest_switch_msr
*msrs
;
9370 msrs
= perf_guest_get_msrs(&nr_msrs
);
9375 for (i
= 0; i
< nr_msrs
; i
++)
9376 if (msrs
[i
].host
== msrs
[i
].guest
)
9377 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9379 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9383 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9385 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9389 if (vmx
->hv_deadline_tsc
== -1)
9393 if (vmx
->hv_deadline_tsc
> tscl
)
9394 /* sure to be 32 bit only because checked on set_hv_timer */
9395 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9396 cpu_preemption_timer_multi
);
9400 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9403 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9405 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9406 unsigned long cr3
, cr4
;
9408 /* Record the guest's net vcpu time for enforced NMI injections. */
9409 if (unlikely(!enable_vnmi
&&
9410 vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9411 vmx
->loaded_vmcs
->entry_time
= ktime_get();
9413 /* Don't enter VMX if guest state is invalid, let the exit handler
9414 start emulation until we arrive back to a valid state */
9415 if (vmx
->emulation_required
)
9418 if (vmx
->ple_window_dirty
) {
9419 vmx
->ple_window_dirty
= false;
9420 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9423 if (vmx
->nested
.sync_shadow_vmcs
) {
9424 copy_vmcs12_to_shadow(vmx
);
9425 vmx
->nested
.sync_shadow_vmcs
= false;
9428 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9429 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9430 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9431 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9433 cr3
= __get_current_cr3_fast();
9434 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9435 vmcs_writel(HOST_CR3
, cr3
);
9436 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9439 cr4
= cr4_read_shadow();
9440 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9441 vmcs_writel(HOST_CR4
, cr4
);
9442 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9445 /* When single-stepping over STI and MOV SS, we must clear the
9446 * corresponding interruptibility bits in the guest state. Otherwise
9447 * vmentry fails as it then expects bit 14 (BS) in pending debug
9448 * exceptions being set, but that's not correct for the guest debugging
9450 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9451 vmx_set_interrupt_shadow(vcpu
, 0);
9453 if (static_cpu_has(X86_FEATURE_PKU
) &&
9454 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9455 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9456 __write_pkru(vcpu
->arch
.pkru
);
9458 atomic_switch_perf_msrs(vmx
);
9460 vmx_arm_hv_timer(vcpu
);
9463 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9464 * it's non-zero. Since vmentry is serialising on affected CPUs, there
9465 * is no need to worry about the conditional branch over the wrmsr
9466 * being speculatively taken.
9469 native_wrmsrl(MSR_IA32_SPEC_CTRL
, vmx
->spec_ctrl
);
9471 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9473 /* Store host registers */
9474 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9475 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9476 "push %%" _ASM_CX
" \n\t"
9477 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9479 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9480 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9482 /* Reload cr2 if changed */
9483 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9484 "mov %%cr2, %%" _ASM_DX
" \n\t"
9485 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9487 "mov %%" _ASM_AX
", %%cr2 \n\t"
9489 /* Check if vmlaunch of vmresume is needed */
9490 "cmpl $0, %c[launched](%0) \n\t"
9491 /* Load guest registers. Don't clobber flags. */
9492 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9493 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9494 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9495 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9496 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9497 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9498 #ifdef CONFIG_X86_64
9499 "mov %c[r8](%0), %%r8 \n\t"
9500 "mov %c[r9](%0), %%r9 \n\t"
9501 "mov %c[r10](%0), %%r10 \n\t"
9502 "mov %c[r11](%0), %%r11 \n\t"
9503 "mov %c[r12](%0), %%r12 \n\t"
9504 "mov %c[r13](%0), %%r13 \n\t"
9505 "mov %c[r14](%0), %%r14 \n\t"
9506 "mov %c[r15](%0), %%r15 \n\t"
9508 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9510 /* Enter guest mode */
9512 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9514 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9516 /* Save guest registers, load host registers, keep flags */
9517 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9519 "setbe %c[fail](%0)\n\t"
9520 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9521 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9522 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9523 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9524 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9525 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9526 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9527 #ifdef CONFIG_X86_64
9528 "mov %%r8, %c[r8](%0) \n\t"
9529 "mov %%r9, %c[r9](%0) \n\t"
9530 "mov %%r10, %c[r10](%0) \n\t"
9531 "mov %%r11, %c[r11](%0) \n\t"
9532 "mov %%r12, %c[r12](%0) \n\t"
9533 "mov %%r13, %c[r13](%0) \n\t"
9534 "mov %%r14, %c[r14](%0) \n\t"
9535 "mov %%r15, %c[r15](%0) \n\t"
9536 "xor %%r8d, %%r8d \n\t"
9537 "xor %%r9d, %%r9d \n\t"
9538 "xor %%r10d, %%r10d \n\t"
9539 "xor %%r11d, %%r11d \n\t"
9540 "xor %%r12d, %%r12d \n\t"
9541 "xor %%r13d, %%r13d \n\t"
9542 "xor %%r14d, %%r14d \n\t"
9543 "xor %%r15d, %%r15d \n\t"
9545 "mov %%cr2, %%" _ASM_AX
" \n\t"
9546 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9548 "xor %%eax, %%eax \n\t"
9549 "xor %%ebx, %%ebx \n\t"
9550 "xor %%esi, %%esi \n\t"
9551 "xor %%edi, %%edi \n\t"
9552 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9553 ".pushsection .rodata \n\t"
9554 ".global vmx_return \n\t"
9555 "vmx_return: " _ASM_PTR
" 2b \n\t"
9557 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9558 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9559 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9560 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9561 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9562 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9563 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9564 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9565 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9566 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9567 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9568 #ifdef CONFIG_X86_64
9569 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9570 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9571 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9572 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9573 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9574 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9575 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9576 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9578 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9579 [wordsize
]"i"(sizeof(ulong
))
9581 #ifdef CONFIG_X86_64
9582 , "rax", "rbx", "rdi", "rsi"
9583 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9585 , "eax", "ebx", "edi", "esi"
9590 * We do not use IBRS in the kernel. If this vCPU has used the
9591 * SPEC_CTRL MSR it may have left it on; save the value and
9592 * turn it off. This is much more efficient than blindly adding
9593 * it to the atomic save/restore list. Especially as the former
9594 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9596 * For non-nested case:
9597 * If the L01 MSR bitmap does not intercept the MSR, then we need to
9601 * If the L02 MSR bitmap does not intercept the MSR, then we need to
9604 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
9605 vmx
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
9608 native_wrmsrl(MSR_IA32_SPEC_CTRL
, 0);
9610 /* Eliminate branch target predictions from guest mode */
9613 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9614 if (vmx
->host_debugctlmsr
)
9615 update_debugctlmsr(vmx
->host_debugctlmsr
);
9617 #ifndef CONFIG_X86_64
9619 * The sysexit path does not restore ds/es, so we must set them to
9620 * a reasonable value ourselves.
9622 * We can't defer this to vmx_load_host_state() since that function
9623 * may be executed in interrupt context, which saves and restore segments
9624 * around it, nullifying its effect.
9626 loadsegment(ds
, __USER_DS
);
9627 loadsegment(es
, __USER_DS
);
9630 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9631 | (1 << VCPU_EXREG_RFLAGS
)
9632 | (1 << VCPU_EXREG_PDPTR
)
9633 | (1 << VCPU_EXREG_SEGMENTS
)
9634 | (1 << VCPU_EXREG_CR3
));
9635 vcpu
->arch
.regs_dirty
= 0;
9638 * eager fpu is enabled if PKEY is supported and CR4 is switched
9639 * back on host, so it is safe to read guest PKRU from current
9642 if (static_cpu_has(X86_FEATURE_PKU
) &&
9643 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9644 vcpu
->arch
.pkru
= __read_pkru();
9645 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9646 __write_pkru(vmx
->host_pkru
);
9650 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9651 * we did not inject a still-pending event to L1 now because of
9652 * nested_run_pending, we need to re-enable this bit.
9654 if (vmx
->nested
.nested_run_pending
)
9655 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9657 vmx
->nested
.nested_run_pending
= 0;
9658 vmx
->idt_vectoring_info
= 0;
9660 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
9661 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9664 vmx
->loaded_vmcs
->launched
= 1;
9665 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9667 vmx_complete_atomic_exit(vmx
);
9668 vmx_recover_nmi_blocking(vmx
);
9669 vmx_complete_interrupts(vmx
);
9671 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9673 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9675 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9678 if (vmx
->loaded_vmcs
== vmcs
)
9682 vmx
->loaded_vmcs
= vmcs
;
9684 vmx_vcpu_load(vcpu
, cpu
);
9689 * Ensure that the current vmcs of the logical processor is the
9690 * vmcs01 of the vcpu before calling free_nested().
9692 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9694 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9697 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9702 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9704 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9707 vmx_destroy_pml_buffer(vmx
);
9708 free_vpid(vmx
->vpid
);
9709 leave_guest_mode(vcpu
);
9710 vmx_free_vcpu_nested(vcpu
);
9711 free_loaded_vmcs(vmx
->loaded_vmcs
);
9712 kfree(vmx
->guest_msrs
);
9713 kvm_vcpu_uninit(vcpu
);
9714 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9717 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9720 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9721 unsigned long *msr_bitmap
;
9725 return ERR_PTR(-ENOMEM
);
9727 vmx
->vpid
= allocate_vpid();
9729 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9736 * If PML is turned on, failure on enabling PML just results in failure
9737 * of creating the vcpu, therefore we can simplify PML logic (by
9738 * avoiding dealing with cases, such as enabling PML partially on vcpus
9739 * for the guest, etc.
9742 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9747 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9748 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9751 if (!vmx
->guest_msrs
)
9754 err
= alloc_loaded_vmcs(&vmx
->vmcs01
);
9758 msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
9759 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_FS_BASE
, MSR_TYPE_RW
);
9760 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_GS_BASE
, MSR_TYPE_RW
);
9761 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_KERNEL_GS_BASE
, MSR_TYPE_RW
);
9762 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_CS
, MSR_TYPE_RW
);
9763 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_ESP
, MSR_TYPE_RW
);
9764 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_EIP
, MSR_TYPE_RW
);
9765 vmx
->msr_bitmap_mode
= 0;
9767 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9769 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9770 vmx
->vcpu
.cpu
= cpu
;
9771 vmx_vcpu_setup(vmx
);
9772 vmx_vcpu_put(&vmx
->vcpu
);
9774 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9775 err
= alloc_apic_access_page(kvm
);
9781 err
= init_rmode_identity_map(kvm
);
9787 nested_vmx_setup_ctls_msrs(vmx
);
9788 vmx
->nested
.vpid02
= allocate_vpid();
9791 vmx
->nested
.posted_intr_nv
= -1;
9792 vmx
->nested
.current_vmptr
= -1ull;
9794 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9797 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9798 * or POSTED_INTR_WAKEUP_VECTOR.
9800 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9801 vmx
->pi_desc
.sn
= 1;
9806 free_vpid(vmx
->nested
.vpid02
);
9807 free_loaded_vmcs(vmx
->loaded_vmcs
);
9809 kfree(vmx
->guest_msrs
);
9811 vmx_destroy_pml_buffer(vmx
);
9813 kvm_vcpu_uninit(&vmx
->vcpu
);
9815 free_vpid(vmx
->vpid
);
9816 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9817 return ERR_PTR(err
);
9820 static void __init
vmx_check_processor_compat(void *rtn
)
9822 struct vmcs_config vmcs_conf
;
9825 if (setup_vmcs_config(&vmcs_conf
) < 0)
9827 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9828 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9829 smp_processor_id());
9834 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9839 /* For VT-d and EPT combination
9840 * 1. MMIO: always map as UC
9842 * a. VT-d without snooping control feature: can't guarantee the
9843 * result, try to trust guest.
9844 * b. VT-d with snooping control feature: snooping control feature of
9845 * VT-d engine can guarantee the cache correctness. Just set it
9846 * to WB to keep consistent with host. So the same as item 3.
9847 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9848 * consistent with host MTRR
9851 cache
= MTRR_TYPE_UNCACHABLE
;
9855 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9856 ipat
= VMX_EPT_IPAT_BIT
;
9857 cache
= MTRR_TYPE_WRBACK
;
9861 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9862 ipat
= VMX_EPT_IPAT_BIT
;
9863 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9864 cache
= MTRR_TYPE_WRBACK
;
9866 cache
= MTRR_TYPE_UNCACHABLE
;
9870 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9873 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9876 static int vmx_get_lpage_level(void)
9878 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9879 return PT_DIRECTORY_LEVEL
;
9881 /* For shadow and EPT supported 1GB page */
9882 return PT_PDPE_LEVEL
;
9885 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9888 * These bits in the secondary execution controls field
9889 * are dynamic, the others are mostly based on the hypervisor
9890 * architecture and the guest's CPUID. Do not touch the
9894 SECONDARY_EXEC_SHADOW_VMCS
|
9895 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9896 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9897 SECONDARY_EXEC_DESC
;
9899 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9901 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9902 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9906 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9907 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9909 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9911 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9912 struct kvm_cpuid_entry2
*entry
;
9914 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9915 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9917 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9918 if (entry && (entry->_reg & (_cpuid_mask))) \
9919 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9922 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9923 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9924 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9925 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9926 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9927 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9928 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9929 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9930 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9931 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9932 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9933 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9934 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9935 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9936 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9938 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9939 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9940 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9941 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9942 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9943 cr4_fixed1_update(X86_CR4_UMIP
, ecx
, bit(X86_FEATURE_UMIP
));
9945 #undef cr4_fixed1_update
9948 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9950 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9952 if (cpu_has_secondary_exec_ctrls()) {
9953 vmx_compute_secondary_exec_control(vmx
);
9954 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9957 if (nested_vmx_allowed(vcpu
))
9958 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9959 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9961 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9962 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9964 if (nested_vmx_allowed(vcpu
))
9965 nested_vmx_cr_fixed1_bits_update(vcpu
);
9968 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9970 if (func
== 1 && nested
)
9971 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9974 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9975 struct x86_exception
*fault
)
9977 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9978 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9980 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9982 if (vmx
->nested
.pml_full
) {
9983 exit_reason
= EXIT_REASON_PML_FULL
;
9984 vmx
->nested
.pml_full
= false;
9985 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9986 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9987 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9989 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9991 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9992 vmcs12
->guest_physical_address
= fault
->address
;
9995 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9997 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
10000 /* Callbacks for nested_ept_init_mmu_context: */
10002 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
10004 /* return the page table to be shadowed - in our case, EPT12 */
10005 return get_vmcs12(vcpu
)->ept_pointer
;
10008 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
10010 WARN_ON(mmu_is_nested(vcpu
));
10011 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
10014 kvm_mmu_unload(vcpu
);
10015 kvm_init_shadow_ept_mmu(vcpu
,
10016 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
10017 VMX_EPT_EXECUTE_ONLY_BIT
,
10018 nested_ept_ad_enabled(vcpu
));
10019 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
10020 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
10021 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
10023 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
10027 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
10029 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
10032 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
10035 bool inequality
, bit
;
10037 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
10039 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
10040 vmcs12
->page_fault_error_code_match
;
10041 return inequality
^ bit
;
10044 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
10045 struct x86_exception
*fault
)
10047 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10049 WARN_ON(!is_guest_mode(vcpu
));
10051 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
) &&
10052 !to_vmx(vcpu
)->nested
.nested_run_pending
) {
10053 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
10054 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10055 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
10056 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
10059 kvm_inject_page_fault(vcpu
, fault
);
10063 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu
*vcpu
,
10064 struct vmcs12
*vmcs12
);
10066 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
10067 struct vmcs12
*vmcs12
)
10069 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10073 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10075 * Translate L1 physical address to host physical
10076 * address for vmcs02. Keep the page pinned, so this
10077 * physical address remains valid. We keep a reference
10078 * to it so we can release it later.
10080 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
10081 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
10082 vmx
->nested
.apic_access_page
= NULL
;
10084 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
10086 * If translation failed, no matter: This feature asks
10087 * to exit when accessing the given address, and if it
10088 * can never be accessed, this feature won't do
10091 if (!is_error_page(page
)) {
10092 vmx
->nested
.apic_access_page
= page
;
10093 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
10094 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
10096 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
10097 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
10099 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
10100 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
10101 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
10102 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
10103 kvm_vcpu_reload_apic_access_page(vcpu
);
10106 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
10107 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
10108 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
10109 vmx
->nested
.virtual_apic_page
= NULL
;
10111 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
10114 * If translation failed, VM entry will fail because
10115 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10116 * Failing the vm entry is _not_ what the processor
10117 * does but it's basically the only possibility we
10118 * have. We could still enter the guest if CR8 load
10119 * exits are enabled, CR8 store exits are enabled, and
10120 * virtualize APIC access is disabled; in this case
10121 * the processor would never use the TPR shadow and we
10122 * could simply clear the bit from the execution
10123 * control. But such a configuration is useless, so
10124 * let's keep the code simple.
10126 if (!is_error_page(page
)) {
10127 vmx
->nested
.virtual_apic_page
= page
;
10128 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
10129 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
10133 if (nested_cpu_has_posted_intr(vmcs12
)) {
10134 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
10135 kunmap(vmx
->nested
.pi_desc_page
);
10136 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
10137 vmx
->nested
.pi_desc_page
= NULL
;
10139 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
10140 if (is_error_page(page
))
10142 vmx
->nested
.pi_desc_page
= page
;
10143 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
10144 vmx
->nested
.pi_desc
=
10145 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
10146 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
10148 vmcs_write64(POSTED_INTR_DESC_ADDR
,
10149 page_to_phys(vmx
->nested
.pi_desc_page
) +
10150 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
10153 if (nested_vmx_prepare_msr_bitmap(vcpu
, vmcs12
))
10154 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
10155 CPU_BASED_USE_MSR_BITMAPS
);
10157 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
10158 CPU_BASED_USE_MSR_BITMAPS
);
10161 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
10163 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
10164 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10166 if (vcpu
->arch
.virtual_tsc_khz
== 0)
10169 /* Make sure short timeouts reliably trigger an immediate vmexit.
10170 * hrtimer_start does not guarantee this. */
10171 if (preemption_timeout
<= 1) {
10172 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
10176 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10177 preemption_timeout
*= 1000000;
10178 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
10179 hrtimer_start(&vmx
->nested
.preemption_timer
,
10180 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
10183 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
10184 struct vmcs12
*vmcs12
)
10186 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
10189 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
10190 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
10196 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
10197 struct vmcs12
*vmcs12
)
10199 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
10202 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
10208 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
10209 struct vmcs12
*vmcs12
)
10211 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10214 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
10221 * Merge L0's and L1's MSR bitmap, return false to indicate that
10222 * we do not use the hardware.
10224 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu
*vcpu
,
10225 struct vmcs12
*vmcs12
)
10229 unsigned long *msr_bitmap_l1
;
10230 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.vmcs02
.msr_bitmap
;
10232 * pred_cmd & spec_ctrl are trying to verify two things:
10234 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10235 * ensures that we do not accidentally generate an L02 MSR bitmap
10236 * from the L12 MSR bitmap that is too permissive.
10237 * 2. That L1 or L2s have actually used the MSR. This avoids
10238 * unnecessarily merging of the bitmap if the MSR is unused. This
10239 * works properly because we only update the L01 MSR bitmap lazily.
10240 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10241 * updated to reflect this when L1 (or its L2s) actually write to
10244 bool pred_cmd
= !msr_write_intercepted_l01(vcpu
, MSR_IA32_PRED_CMD
);
10245 bool spec_ctrl
= !msr_write_intercepted_l01(vcpu
, MSR_IA32_SPEC_CTRL
);
10247 /* Nothing to do if the MSR bitmap is not in use. */
10248 if (!cpu_has_vmx_msr_bitmap() ||
10249 !nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
10252 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10253 !pred_cmd
&& !spec_ctrl
)
10256 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10257 if (is_error_page(page
))
10260 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10261 if (nested_cpu_has_apic_reg_virt(vmcs12
)) {
10263 * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
10264 * just lets the processor take the value from the virtual-APIC page;
10265 * take those 256 bits directly from the L1 bitmap.
10267 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
10268 unsigned word
= msr
/ BITS_PER_LONG
;
10269 msr_bitmap_l0
[word
] = msr_bitmap_l1
[word
];
10270 msr_bitmap_l0
[word
+ (0x800 / sizeof(long))] = ~0;
10273 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
10274 unsigned word
= msr
/ BITS_PER_LONG
;
10275 msr_bitmap_l0
[word
] = ~0;
10276 msr_bitmap_l0
[word
+ (0x800 / sizeof(long))] = ~0;
10280 nested_vmx_disable_intercept_for_msr(
10281 msr_bitmap_l1
, msr_bitmap_l0
,
10282 X2APIC_MSR(APIC_TASKPRI
),
10285 if (nested_cpu_has_vid(vmcs12
)) {
10286 nested_vmx_disable_intercept_for_msr(
10287 msr_bitmap_l1
, msr_bitmap_l0
,
10288 X2APIC_MSR(APIC_EOI
),
10290 nested_vmx_disable_intercept_for_msr(
10291 msr_bitmap_l1
, msr_bitmap_l0
,
10292 X2APIC_MSR(APIC_SELF_IPI
),
10297 nested_vmx_disable_intercept_for_msr(
10298 msr_bitmap_l1
, msr_bitmap_l0
,
10299 MSR_IA32_SPEC_CTRL
,
10300 MSR_TYPE_R
| MSR_TYPE_W
);
10303 nested_vmx_disable_intercept_for_msr(
10304 msr_bitmap_l1
, msr_bitmap_l0
,
10309 kvm_release_page_clean(page
);
10314 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10315 struct vmcs12
*vmcs12
)
10317 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10318 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10319 !nested_cpu_has_vid(vmcs12
) &&
10320 !nested_cpu_has_posted_intr(vmcs12
))
10324 * If virtualize x2apic mode is enabled,
10325 * virtualize apic access must be disabled.
10327 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10328 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10332 * If virtual interrupt delivery is enabled,
10333 * we must exit on external interrupts.
10335 if (nested_cpu_has_vid(vmcs12
) &&
10336 !nested_exit_on_intr(vcpu
))
10340 * bits 15:8 should be zero in posted_intr_nv,
10341 * the descriptor address has been already checked
10342 * in nested_get_vmcs12_pages.
10344 if (nested_cpu_has_posted_intr(vmcs12
) &&
10345 (!nested_cpu_has_vid(vmcs12
) ||
10346 !nested_exit_intr_ack_set(vcpu
) ||
10347 vmcs12
->posted_intr_nv
& 0xff00))
10350 /* tpr shadow is needed by all apicv features. */
10351 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10357 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10358 unsigned long count_field
,
10359 unsigned long addr_field
)
10364 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10365 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10371 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10372 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10373 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10374 pr_debug_ratelimited(
10375 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10376 addr_field
, maxphyaddr
, count
, addr
);
10382 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10383 struct vmcs12
*vmcs12
)
10385 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10386 vmcs12
->vm_exit_msr_store_count
== 0 &&
10387 vmcs12
->vm_entry_msr_load_count
== 0)
10388 return 0; /* Fast path */
10389 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10390 VM_EXIT_MSR_LOAD_ADDR
) ||
10391 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10392 VM_EXIT_MSR_STORE_ADDR
) ||
10393 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10394 VM_ENTRY_MSR_LOAD_ADDR
))
10399 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10400 struct vmcs12
*vmcs12
)
10402 u64 address
= vmcs12
->pml_address
;
10403 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10405 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10406 if (!nested_cpu_has_ept(vmcs12
) ||
10407 !IS_ALIGNED(address
, 4096) ||
10408 address
>> maxphyaddr
)
10415 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10416 struct vmx_msr_entry
*e
)
10418 /* x2APIC MSR accesses are not allowed */
10419 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10421 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10422 e
->index
== MSR_IA32_UCODE_REV
)
10424 if (e
->reserved
!= 0)
10429 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10430 struct vmx_msr_entry
*e
)
10432 if (e
->index
== MSR_FS_BASE
||
10433 e
->index
== MSR_GS_BASE
||
10434 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10435 nested_vmx_msr_check_common(vcpu
, e
))
10440 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10441 struct vmx_msr_entry
*e
)
10443 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10444 nested_vmx_msr_check_common(vcpu
, e
))
10450 * Load guest's/host's msr at nested entry/exit.
10451 * return 0 for success, entry index for failure.
10453 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10456 struct vmx_msr_entry e
;
10457 struct msr_data msr
;
10459 msr
.host_initiated
= false;
10460 for (i
= 0; i
< count
; i
++) {
10461 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10463 pr_debug_ratelimited(
10464 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10465 __func__
, i
, gpa
+ i
* sizeof(e
));
10468 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10469 pr_debug_ratelimited(
10470 "%s check failed (%u, 0x%x, 0x%x)\n",
10471 __func__
, i
, e
.index
, e
.reserved
);
10474 msr
.index
= e
.index
;
10475 msr
.data
= e
.value
;
10476 if (kvm_set_msr(vcpu
, &msr
)) {
10477 pr_debug_ratelimited(
10478 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10479 __func__
, i
, e
.index
, e
.value
);
10488 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10491 struct vmx_msr_entry e
;
10493 for (i
= 0; i
< count
; i
++) {
10494 struct msr_data msr_info
;
10495 if (kvm_vcpu_read_guest(vcpu
,
10496 gpa
+ i
* sizeof(e
),
10497 &e
, 2 * sizeof(u32
))) {
10498 pr_debug_ratelimited(
10499 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10500 __func__
, i
, gpa
+ i
* sizeof(e
));
10503 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10504 pr_debug_ratelimited(
10505 "%s check failed (%u, 0x%x, 0x%x)\n",
10506 __func__
, i
, e
.index
, e
.reserved
);
10509 msr_info
.host_initiated
= false;
10510 msr_info
.index
= e
.index
;
10511 if (kvm_get_msr(vcpu
, &msr_info
)) {
10512 pr_debug_ratelimited(
10513 "%s cannot read MSR (%u, 0x%x)\n",
10514 __func__
, i
, e
.index
);
10517 if (kvm_vcpu_write_guest(vcpu
,
10518 gpa
+ i
* sizeof(e
) +
10519 offsetof(struct vmx_msr_entry
, value
),
10520 &msr_info
.data
, sizeof(msr_info
.data
))) {
10521 pr_debug_ratelimited(
10522 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10523 __func__
, i
, e
.index
, msr_info
.data
);
10530 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10532 unsigned long invalid_mask
;
10534 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10535 return (val
& invalid_mask
) == 0;
10539 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10540 * emulating VM entry into a guest with EPT enabled.
10541 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10542 * is assigned to entry_failure_code on failure.
10544 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10545 u32
*entry_failure_code
)
10547 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10548 if (!nested_cr3_valid(vcpu
, cr3
)) {
10549 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10554 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10555 * must not be dereferenced.
10557 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10559 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10560 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10565 vcpu
->arch
.cr3
= cr3
;
10566 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10569 kvm_mmu_reset_context(vcpu
);
10573 static void prepare_vmcs02_full(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10576 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10578 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10579 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10580 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10581 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10582 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10583 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10584 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10585 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10586 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10587 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10588 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10589 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10590 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10591 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10592 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10593 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10594 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10595 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10596 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10597 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10598 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10599 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10600 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10601 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10602 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10603 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10604 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10605 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10606 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10607 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10608 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10610 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10611 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10612 vmcs12
->guest_pending_dbg_exceptions
);
10613 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10614 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10616 if (nested_cpu_has_xsaves(vmcs12
))
10617 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10618 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10620 if (cpu_has_vmx_posted_intr())
10621 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10624 * Whether page-faults are trapped is determined by a combination of
10625 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10626 * If enable_ept, L0 doesn't care about page faults and we should
10627 * set all of these to L1's desires. However, if !enable_ept, L0 does
10628 * care about (at least some) page faults, and because it is not easy
10629 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10630 * to exit on each and every L2 page fault. This is done by setting
10631 * MASK=MATCH=0 and (see below) EB.PF=1.
10632 * Note that below we don't need special code to set EB.PF beyond the
10633 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10634 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10635 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10637 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10638 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10639 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10640 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10642 /* All VMFUNCs are currently emulated through L0 vmexits. */
10643 if (cpu_has_vmx_vmfunc())
10644 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10646 if (cpu_has_vmx_apicv()) {
10647 vmcs_write64(EOI_EXIT_BITMAP0
, vmcs12
->eoi_exit_bitmap0
);
10648 vmcs_write64(EOI_EXIT_BITMAP1
, vmcs12
->eoi_exit_bitmap1
);
10649 vmcs_write64(EOI_EXIT_BITMAP2
, vmcs12
->eoi_exit_bitmap2
);
10650 vmcs_write64(EOI_EXIT_BITMAP3
, vmcs12
->eoi_exit_bitmap3
);
10654 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10655 * Some constant fields are set here by vmx_set_constant_host_state().
10656 * Other fields are different per CPU, and will be set later when
10657 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10659 vmx_set_constant_host_state(vmx
);
10662 * Set the MSR load/store lists to match L0's settings.
10664 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10665 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10666 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10667 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10668 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10670 set_cr4_guest_host_mask(vmx
);
10672 if (vmx_mpx_supported())
10673 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10676 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
)
10677 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10679 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10683 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10686 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10687 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10688 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10689 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10692 if (cpu_has_vmx_msr_bitmap())
10693 vmcs_write64(MSR_BITMAP
, __pa(vmx
->nested
.vmcs02
.msr_bitmap
));
10697 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10698 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10699 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10700 * guest in a way that will both be appropriate to L1's requests, and our
10701 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10702 * function also has additional necessary side-effects, like setting various
10703 * vcpu->arch fields.
10704 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10705 * is assigned to entry_failure_code on failure.
10707 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10708 bool from_vmentry
, u32
*entry_failure_code
)
10710 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10711 u32 exec_control
, vmcs12_exec_ctrl
;
10713 if (vmx
->nested
.dirty_vmcs12
) {
10714 prepare_vmcs02_full(vcpu
, vmcs12
, from_vmentry
);
10715 vmx
->nested
.dirty_vmcs12
= false;
10719 * First, the fields that are shadowed. This must be kept in sync
10720 * with vmx_shadow_fields.h.
10723 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10724 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10725 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10726 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10727 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10730 * Not in vmcs02: GUEST_PML_INDEX, HOST_FS_SELECTOR, HOST_GS_SELECTOR,
10731 * HOST_FS_BASE, HOST_GS_BASE.
10734 if (from_vmentry
&&
10735 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10736 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10737 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10739 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10740 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10742 if (from_vmentry
) {
10743 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10744 vmcs12
->vm_entry_intr_info_field
);
10745 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10746 vmcs12
->vm_entry_exception_error_code
);
10747 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10748 vmcs12
->vm_entry_instruction_len
);
10749 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10750 vmcs12
->guest_interruptibility_info
);
10751 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10752 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10754 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10756 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10758 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10760 /* Preemption timer setting is only taken from vmcs01. */
10761 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10762 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10763 if (vmx
->hv_deadline_tsc
== -1)
10764 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10766 /* Posted interrupts setting is only taken from vmcs12. */
10767 if (nested_cpu_has_posted_intr(vmcs12
)) {
10768 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10769 vmx
->nested
.pi_pending
= false;
10771 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10774 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10776 vmx
->nested
.preemption_timer_expired
= false;
10777 if (nested_cpu_has_preemption_timer(vmcs12
))
10778 vmx_start_preemption_timer(vcpu
);
10780 if (cpu_has_secondary_exec_ctrls()) {
10781 exec_control
= vmx
->secondary_exec_control
;
10783 /* Take the following fields only from vmcs12 */
10784 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10785 SECONDARY_EXEC_ENABLE_INVPCID
|
10786 SECONDARY_EXEC_RDTSCP
|
10787 SECONDARY_EXEC_XSAVES
|
10788 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10789 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10790 SECONDARY_EXEC_ENABLE_VMFUNC
);
10791 if (nested_cpu_has(vmcs12
,
10792 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10793 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10794 ~SECONDARY_EXEC_ENABLE_PML
;
10795 exec_control
|= vmcs12_exec_ctrl
;
10798 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
10799 vmcs_write16(GUEST_INTR_STATUS
,
10800 vmcs12
->guest_intr_status
);
10803 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10804 * nested_get_vmcs12_pages will either fix it up or
10805 * remove the VM execution control.
10807 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10808 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10810 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10814 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10815 * entry, but only if the current (host) sp changed from the value
10816 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10817 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10818 * here we just force the write to happen on entry.
10822 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10823 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10824 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10825 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10826 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10829 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10830 * nested_get_vmcs12_pages can't fix it up, the illegal value
10831 * will result in a VM entry failure.
10833 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10834 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10835 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10837 #ifdef CONFIG_X86_64
10838 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10839 CPU_BASED_CR8_STORE_EXITING
;
10844 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
10845 * for I/O port accesses.
10847 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10848 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10850 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10852 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10853 * bitwise-or of what L1 wants to trap for L2, and what we want to
10854 * trap. Note that CR0.TS also needs updating - we do this later.
10856 update_exception_bitmap(vcpu
);
10857 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10858 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10860 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10861 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10862 * bits are further modified by vmx_set_efer() below.
10864 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10866 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10867 * emulated by vmx_set_efer(), below.
10869 vm_entry_controls_init(vmx
,
10870 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10871 ~VM_ENTRY_IA32E_MODE
) |
10872 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10874 if (from_vmentry
&&
10875 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10876 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10877 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10878 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10879 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10882 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10883 vmcs_write64(TSC_OFFSET
,
10884 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10886 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10887 if (kvm_has_tsc_control
)
10888 decache_tsc_multiplier(vmx
);
10892 * There is no direct mapping between vpid02 and vpid12, the
10893 * vpid02 is per-vCPU for L0 and reused while the value of
10894 * vpid12 is changed w/ one invvpid during nested vmentry.
10895 * The vpid12 is allocated by L1 for L2, so it will not
10896 * influence global bitmap(for vpid01 and vpid02 allocation)
10897 * even if spawn a lot of nested vCPUs.
10899 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10900 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10901 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10902 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
, true);
10905 vmx_flush_tlb(vcpu
, true);
10911 * Conceptually we want to copy the PML address and index from
10912 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10913 * since we always flush the log on each vmexit, this happens
10914 * to be equivalent to simply resetting the fields in vmcs02.
10916 ASSERT(vmx
->pml_pg
);
10917 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10918 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10921 if (nested_cpu_has_ept(vmcs12
)) {
10922 if (nested_ept_init_mmu_context(vcpu
)) {
10923 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10926 } else if (nested_cpu_has2(vmcs12
,
10927 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10928 vmx_flush_tlb_ept_only(vcpu
);
10932 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10933 * bits which we consider mandatory enabled.
10934 * The CR0_READ_SHADOW is what L2 should have expected to read given
10935 * the specifications by L1; It's not enough to take
10936 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10937 * have more bits than L1 expected.
10939 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10940 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10942 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10943 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10945 if (from_vmentry
&&
10946 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10947 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10948 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10949 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10951 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10952 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10953 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10955 /* Shadow page tables on either EPT or shadow page tables. */
10956 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10957 entry_failure_code
))
10961 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10963 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10964 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10968 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10970 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10972 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10973 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10974 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10976 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10977 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10979 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10980 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10982 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
10983 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10985 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10986 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10988 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10989 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10991 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10992 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10994 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10995 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10996 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10997 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10998 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10999 vmx
->nested
.nested_vmx_secondary_ctls_low
,
11000 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
11001 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
11002 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
11003 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
11004 !vmx_control_verify(vmcs12
->vm_exit_controls
,
11005 vmx
->nested
.nested_vmx_exit_ctls_low
,
11006 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
11007 !vmx_control_verify(vmcs12
->vm_entry_controls
,
11008 vmx
->nested
.nested_vmx_entry_ctls_low
,
11009 vmx
->nested
.nested_vmx_entry_ctls_high
))
11010 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11012 if (nested_cpu_has_vmfunc(vmcs12
)) {
11013 if (vmcs12
->vm_function_control
&
11014 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
11015 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11017 if (nested_cpu_has_eptp_switching(vmcs12
)) {
11018 if (!nested_cpu_has_ept(vmcs12
) ||
11019 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
11020 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11024 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
11025 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
11027 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
11028 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
11029 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
11030 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
11035 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11040 *exit_qual
= ENTRY_FAIL_DEFAULT
;
11042 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
11043 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
11046 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
11047 vmcs12
->vmcs_link_pointer
!= -1ull) {
11048 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
11053 * If the load IA32_EFER VM-entry control is 1, the following checks
11054 * are performed on the field for the IA32_EFER MSR:
11055 * - Bits reserved in the IA32_EFER MSR must be 0.
11056 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11057 * the IA-32e mode guest VM-exit control. It must also be identical
11058 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11061 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
11062 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
11063 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
11064 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
11065 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
11066 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
11067 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
11072 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11073 * IA32_EFER MSR must be 0 in the field for that register. In addition,
11074 * the values of the LMA and LME bits in the field must each be that of
11075 * the host address-space size VM-exit control.
11077 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
11078 ia32e
= (vmcs12
->vm_exit_controls
&
11079 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
11080 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
11081 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
11082 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
11086 if ((vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
) &&
11087 (is_noncanonical_address(vmcs12
->guest_bndcfgs
& PAGE_MASK
, vcpu
) ||
11088 (vmcs12
->guest_bndcfgs
& MSR_IA32_BNDCFGS_RSVD
)))
11094 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
11096 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11097 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11101 enter_guest_mode(vcpu
);
11103 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
11104 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11106 vmx_switch_vmcs(vcpu
, &vmx
->nested
.vmcs02
);
11107 vmx_segment_cache_clear(vmx
);
11109 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
11110 leave_guest_mode(vcpu
);
11111 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11112 nested_vmx_entry_failure(vcpu
, vmcs12
,
11113 EXIT_REASON_INVALID_STATE
, exit_qual
);
11117 nested_get_vmcs12_pages(vcpu
, vmcs12
);
11119 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
11120 vmcs12
->vm_entry_msr_load_addr
,
11121 vmcs12
->vm_entry_msr_load_count
);
11122 if (msr_entry_idx
) {
11123 leave_guest_mode(vcpu
);
11124 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11125 nested_vmx_entry_failure(vcpu
, vmcs12
,
11126 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
11131 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11132 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11133 * returned as far as L1 is concerned. It will only return (and set
11134 * the success flag) when L2 exits (see nested_vmx_vmexit()).
11140 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11141 * for running an L2 nested guest.
11143 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
11145 struct vmcs12
*vmcs12
;
11146 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11147 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
11151 if (!nested_vmx_check_permission(vcpu
))
11154 if (!nested_vmx_check_vmcs12(vcpu
))
11157 vmcs12
= get_vmcs12(vcpu
);
11159 if (enable_shadow_vmcs
)
11160 copy_shadow_to_vmcs12(vmx
);
11163 * The nested entry process starts with enforcing various prerequisites
11164 * on vmcs12 as required by the Intel SDM, and act appropriately when
11165 * they fail: As the SDM explains, some conditions should cause the
11166 * instruction to fail, while others will cause the instruction to seem
11167 * to succeed, but return an EXIT_REASON_INVALID_STATE.
11168 * To speed up the normal (success) code path, we should avoid checking
11169 * for misconfigurations which will anyway be caught by the processor
11170 * when using the merged vmcs02.
11172 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
11173 nested_vmx_failValid(vcpu
,
11174 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
11178 if (vmcs12
->launch_state
== launch
) {
11179 nested_vmx_failValid(vcpu
,
11180 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11181 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
11185 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
11187 nested_vmx_failValid(vcpu
, ret
);
11192 * After this point, the trap flag no longer triggers a singlestep trap
11193 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11194 * This is not 100% correct; for performance reasons, we delegate most
11195 * of the checks on host state to the processor. If those fail,
11196 * the singlestep trap is missed.
11198 skip_emulated_instruction(vcpu
);
11200 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
11202 nested_vmx_entry_failure(vcpu
, vmcs12
,
11203 EXIT_REASON_INVALID_STATE
, exit_qual
);
11208 * We're finally done with prerequisite checking, and can start with
11209 * the nested entry.
11212 ret
= enter_vmx_non_root_mode(vcpu
, true);
11217 * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
11218 * by event injection, halt vcpu.
11220 if ((vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
) &&
11221 !(vmcs12
->vm_entry_intr_info_field
& INTR_INFO_VALID_MASK
))
11222 return kvm_vcpu_halt(vcpu
);
11224 vmx
->nested
.nested_run_pending
= 1;
11229 return kvm_skip_emulated_instruction(vcpu
);
11233 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11234 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11235 * This function returns the new value we should put in vmcs12.guest_cr0.
11236 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11237 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11238 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11239 * didn't trap the bit, because if L1 did, so would L0).
11240 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11241 * been modified by L2, and L1 knows it. So just leave the old value of
11242 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11243 * isn't relevant, because if L0 traps this bit it can set it to anything.
11244 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11245 * changed these bits, and therefore they need to be updated, but L0
11246 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11247 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11249 static inline unsigned long
11250 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11253 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
11254 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
11255 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
11256 vcpu
->arch
.cr0_guest_owned_bits
));
11259 static inline unsigned long
11260 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11263 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
11264 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
11265 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
11266 vcpu
->arch
.cr4_guest_owned_bits
));
11269 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
11270 struct vmcs12
*vmcs12
)
11275 if (vcpu
->arch
.exception
.injected
) {
11276 nr
= vcpu
->arch
.exception
.nr
;
11277 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11279 if (kvm_exception_is_soft(nr
)) {
11280 vmcs12
->vm_exit_instruction_len
=
11281 vcpu
->arch
.event_exit_inst_len
;
11282 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
11284 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
11286 if (vcpu
->arch
.exception
.has_error_code
) {
11287 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
11288 vmcs12
->idt_vectoring_error_code
=
11289 vcpu
->arch
.exception
.error_code
;
11292 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11293 } else if (vcpu
->arch
.nmi_injected
) {
11294 vmcs12
->idt_vectoring_info_field
=
11295 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
11296 } else if (vcpu
->arch
.interrupt
.pending
) {
11297 nr
= vcpu
->arch
.interrupt
.nr
;
11298 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11300 if (vcpu
->arch
.interrupt
.soft
) {
11301 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11302 vmcs12
->vm_entry_instruction_len
=
11303 vcpu
->arch
.event_exit_inst_len
;
11305 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11307 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11311 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11313 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11314 unsigned long exit_qual
;
11315 bool block_nested_events
=
11316 vmx
->nested
.nested_run_pending
|| kvm_event_needs_reinjection(vcpu
);
11318 if (vcpu
->arch
.exception
.pending
&&
11319 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
11320 if (block_nested_events
)
11322 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
11326 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11327 vmx
->nested
.preemption_timer_expired
) {
11328 if (block_nested_events
)
11330 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11334 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11335 if (block_nested_events
)
11337 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11338 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11339 INTR_INFO_VALID_MASK
, 0);
11341 * The NMI-triggered VM exit counts as injection:
11342 * clear this one and block further NMIs.
11344 vcpu
->arch
.nmi_pending
= 0;
11345 vmx_set_nmi_mask(vcpu
, true);
11349 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11350 nested_exit_on_intr(vcpu
)) {
11351 if (block_nested_events
)
11353 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11357 vmx_complete_nested_posted_interrupt(vcpu
);
11361 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11363 ktime_t remaining
=
11364 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11367 if (ktime_to_ns(remaining
) <= 0)
11370 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11371 do_div(value
, 1000000);
11372 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11376 * Update the guest state fields of vmcs12 to reflect changes that
11377 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11378 * VM-entry controls is also updated, since this is really a guest
11381 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11383 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11384 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11386 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11387 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11388 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11390 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11391 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11392 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11393 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11394 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11395 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11396 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11397 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11398 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11399 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11400 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11401 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11402 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11403 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11404 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11405 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11406 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11407 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11408 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11409 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11410 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11411 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11412 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11413 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11414 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11415 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11416 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11417 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11418 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11419 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11420 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11421 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11422 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11423 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11424 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11425 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11427 vmcs12
->guest_interruptibility_info
=
11428 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11429 vmcs12
->guest_pending_dbg_exceptions
=
11430 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11431 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11432 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11434 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11436 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11437 if (vmcs12
->vm_exit_controls
&
11438 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11439 vmcs12
->vmx_preemption_timer_value
=
11440 vmx_get_preemption_timer_value(vcpu
);
11441 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11445 * In some cases (usually, nested EPT), L2 is allowed to change its
11446 * own CR3 without exiting. If it has changed it, we must keep it.
11447 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11448 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11450 * Additionally, restore L2's PDPTR to vmcs12.
11453 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11454 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11455 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11456 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11457 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11460 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11462 if (nested_cpu_has_vid(vmcs12
))
11463 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11465 vmcs12
->vm_entry_controls
=
11466 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11467 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11469 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11470 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11471 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11474 /* TODO: These cannot have changed unless we have MSR bitmaps and
11475 * the relevant bit asks not to trap the change */
11476 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11477 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11478 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11479 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11480 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11481 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11482 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11483 if (kvm_mpx_supported())
11484 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11488 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11489 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11490 * and this function updates it to reflect the changes to the guest state while
11491 * L2 was running (and perhaps made some exits which were handled directly by L0
11492 * without going back to L1), and to reflect the exit reason.
11493 * Note that we do not have to copy here all VMCS fields, just those that
11494 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11495 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11496 * which already writes to vmcs12 directly.
11498 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11499 u32 exit_reason
, u32 exit_intr_info
,
11500 unsigned long exit_qualification
)
11502 /* update guest state fields: */
11503 sync_vmcs12(vcpu
, vmcs12
);
11505 /* update exit information fields: */
11507 vmcs12
->vm_exit_reason
= exit_reason
;
11508 vmcs12
->exit_qualification
= exit_qualification
;
11509 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11511 vmcs12
->idt_vectoring_info_field
= 0;
11512 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11513 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11515 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11516 vmcs12
->launch_state
= 1;
11518 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11519 * instead of reading the real value. */
11520 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11523 * Transfer the event that L0 or L1 may wanted to inject into
11524 * L2 to IDT_VECTORING_INFO_FIELD.
11526 vmcs12_save_pending_event(vcpu
, vmcs12
);
11530 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11531 * preserved above and would only end up incorrectly in L1.
11533 vcpu
->arch
.nmi_injected
= false;
11534 kvm_clear_exception_queue(vcpu
);
11535 kvm_clear_interrupt_queue(vcpu
);
11538 static void load_vmcs12_mmu_host_state(struct kvm_vcpu
*vcpu
,
11539 struct vmcs12
*vmcs12
)
11541 u32 entry_failure_code
;
11543 nested_ept_uninit_mmu_context(vcpu
);
11546 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11547 * couldn't have changed.
11549 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11550 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11553 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11557 * A part of what we need to when the nested L2 guest exits and we want to
11558 * run its L1 parent, is to reset L1's guest state to the host state specified
11560 * This function is to be called not only on normal nested exit, but also on
11561 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11562 * Failures During or After Loading Guest State").
11563 * This function should be called when the active VMCS is L1's (vmcs01).
11565 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11566 struct vmcs12
*vmcs12
)
11568 struct kvm_segment seg
;
11570 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11571 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11572 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11573 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11575 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11576 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11578 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11579 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11580 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11582 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11583 * actually changed, because vmx_set_cr0 refers to efer set above.
11585 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11586 * (KVM doesn't change it);
11588 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11589 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11591 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11592 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11593 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11595 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
11599 * Trivially support vpid by letting L2s share their parent
11600 * L1's vpid. TODO: move to a more elaborate solution, giving
11601 * each L2 its own vpid and exposing the vpid feature to L1.
11603 vmx_flush_tlb(vcpu
, true);
11606 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11607 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11608 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11609 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11610 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11611 vmcs_write32(GUEST_IDTR_LIMIT
, 0xFFFF);
11612 vmcs_write32(GUEST_GDTR_LIMIT
, 0xFFFF);
11614 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11615 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11616 vmcs_write64(GUEST_BNDCFGS
, 0);
11618 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11619 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11620 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11622 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11623 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11624 vmcs12
->host_ia32_perf_global_ctrl
);
11626 /* Set L1 segment info according to Intel SDM
11627 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11628 seg
= (struct kvm_segment
) {
11630 .limit
= 0xFFFFFFFF,
11631 .selector
= vmcs12
->host_cs_selector
,
11637 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11641 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11642 seg
= (struct kvm_segment
) {
11644 .limit
= 0xFFFFFFFF,
11651 seg
.selector
= vmcs12
->host_ds_selector
;
11652 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11653 seg
.selector
= vmcs12
->host_es_selector
;
11654 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11655 seg
.selector
= vmcs12
->host_ss_selector
;
11656 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11657 seg
.selector
= vmcs12
->host_fs_selector
;
11658 seg
.base
= vmcs12
->host_fs_base
;
11659 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11660 seg
.selector
= vmcs12
->host_gs_selector
;
11661 seg
.base
= vmcs12
->host_gs_base
;
11662 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11663 seg
= (struct kvm_segment
) {
11664 .base
= vmcs12
->host_tr_base
,
11666 .selector
= vmcs12
->host_tr_selector
,
11670 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11672 kvm_set_dr(vcpu
, 7, 0x400);
11673 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11675 if (cpu_has_vmx_msr_bitmap())
11676 vmx_update_msr_bitmap(vcpu
);
11678 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11679 vmcs12
->vm_exit_msr_load_count
))
11680 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11684 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11685 * and modify vmcs12 to make it see what it would expect to see there if
11686 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11688 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11689 u32 exit_intr_info
,
11690 unsigned long exit_qualification
)
11692 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11693 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11695 /* trying to cancel vmlaunch/vmresume is a bug */
11696 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11699 * The only expected VM-instruction error is "VM entry with
11700 * invalid control field(s)." Anything else indicates a
11703 WARN_ON_ONCE(vmx
->fail
&& (vmcs_read32(VM_INSTRUCTION_ERROR
) !=
11704 VMXERR_ENTRY_INVALID_CONTROL_FIELD
));
11706 leave_guest_mode(vcpu
);
11708 if (likely(!vmx
->fail
)) {
11709 if (exit_reason
== -1)
11710 sync_vmcs12(vcpu
, vmcs12
);
11712 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11713 exit_qualification
);
11715 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11716 vmcs12
->vm_exit_msr_store_count
))
11717 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11720 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11721 vm_entry_controls_reset_shadow(vmx
);
11722 vm_exit_controls_reset_shadow(vmx
);
11723 vmx_segment_cache_clear(vmx
);
11725 /* Update any VMCS fields that might have changed while L2 ran */
11726 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11727 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11728 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11729 if (vmx
->hv_deadline_tsc
== -1)
11730 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11731 PIN_BASED_VMX_PREEMPTION_TIMER
);
11733 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11734 PIN_BASED_VMX_PREEMPTION_TIMER
);
11735 if (kvm_has_tsc_control
)
11736 decache_tsc_multiplier(vmx
);
11738 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11739 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11740 vmx_set_virtual_x2apic_mode(vcpu
,
11741 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11742 } else if (!nested_cpu_has_ept(vmcs12
) &&
11743 nested_cpu_has2(vmcs12
,
11744 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11745 vmx_flush_tlb_ept_only(vcpu
);
11748 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11751 /* Unpin physical memory we referred to in vmcs02 */
11752 if (vmx
->nested
.apic_access_page
) {
11753 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11754 vmx
->nested
.apic_access_page
= NULL
;
11756 if (vmx
->nested
.virtual_apic_page
) {
11757 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11758 vmx
->nested
.virtual_apic_page
= NULL
;
11760 if (vmx
->nested
.pi_desc_page
) {
11761 kunmap(vmx
->nested
.pi_desc_page
);
11762 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11763 vmx
->nested
.pi_desc_page
= NULL
;
11764 vmx
->nested
.pi_desc
= NULL
;
11768 * We are now running in L2, mmu_notifier will force to reload the
11769 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11771 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11773 if (enable_shadow_vmcs
&& exit_reason
!= -1)
11774 vmx
->nested
.sync_shadow_vmcs
= true;
11776 /* in case we halted in L2 */
11777 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11779 if (likely(!vmx
->fail
)) {
11781 * TODO: SDM says that with acknowledge interrupt on
11782 * exit, bit 31 of the VM-exit interrupt information
11783 * (valid interrupt) is always set to 1 on
11784 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11785 * need kvm_cpu_has_interrupt(). See the commit
11786 * message for details.
11788 if (nested_exit_intr_ack_set(vcpu
) &&
11789 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11790 kvm_cpu_has_interrupt(vcpu
)) {
11791 int irq
= kvm_cpu_get_interrupt(vcpu
);
11793 vmcs12
->vm_exit_intr_info
= irq
|
11794 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11797 if (exit_reason
!= -1)
11798 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11799 vmcs12
->exit_qualification
,
11800 vmcs12
->idt_vectoring_info_field
,
11801 vmcs12
->vm_exit_intr_info
,
11802 vmcs12
->vm_exit_intr_error_code
,
11805 load_vmcs12_host_state(vcpu
, vmcs12
);
11811 * After an early L2 VM-entry failure, we're now back
11812 * in L1 which thinks it just finished a VMLAUNCH or
11813 * VMRESUME instruction, so we need to set the failure
11814 * flag and the VM-instruction error field of the VMCS
11817 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11819 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
11822 * The emulated instruction was already skipped in
11823 * nested_vmx_run, but the updated RIP was never
11824 * written back to the vmcs01.
11826 skip_emulated_instruction(vcpu
);
11831 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11833 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11835 if (is_guest_mode(vcpu
)) {
11836 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11837 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11839 free_nested(to_vmx(vcpu
));
11843 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11844 * 23.7 "VM-entry failures during or after loading guest state" (this also
11845 * lists the acceptable exit-reason and exit-qualification parameters).
11846 * It should only be called before L2 actually succeeded to run, and when
11847 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11849 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11850 struct vmcs12
*vmcs12
,
11851 u32 reason
, unsigned long qualification
)
11853 load_vmcs12_host_state(vcpu
, vmcs12
);
11854 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11855 vmcs12
->exit_qualification
= qualification
;
11856 nested_vmx_succeed(vcpu
);
11857 if (enable_shadow_vmcs
)
11858 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11861 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11862 struct x86_instruction_info
*info
,
11863 enum x86_intercept_stage stage
)
11865 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11866 struct x86_emulate_ctxt
*ctxt
= &vcpu
->arch
.emulate_ctxt
;
11869 * RDPID causes #UD if disabled through secondary execution controls.
11870 * Because it is marked as EmulateOnUD, we need to intercept it here.
11872 if (info
->intercept
== x86_intercept_rdtscp
&&
11873 !nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDTSCP
)) {
11874 ctxt
->exception
.vector
= UD_VECTOR
;
11875 ctxt
->exception
.error_code_valid
= false;
11876 return X86EMUL_PROPAGATE_FAULT
;
11879 /* TODO: check more intercepts... */
11880 return X86EMUL_CONTINUE
;
11883 #ifdef CONFIG_X86_64
11884 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11885 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11886 u64 divisor
, u64
*result
)
11888 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11890 /* To avoid the overflow on divq */
11891 if (high
>= divisor
)
11894 /* Low hold the result, high hold rem which is discarded */
11895 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11896 "rm" (divisor
), "0" (low
), "1" (high
));
11902 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11904 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11905 u64 tscl
= rdtsc();
11906 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11907 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11909 /* Convert to host delta tsc if tsc scaling is enabled */
11910 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11911 u64_shl_div_u64(delta_tsc
,
11912 kvm_tsc_scaling_ratio_frac_bits
,
11913 vcpu
->arch
.tsc_scaling_ratio
,
11918 * If the delta tsc can't fit in the 32 bit after the multi shift,
11919 * we can't use the preemption timer.
11920 * It's possible that it fits on later vmentries, but checking
11921 * on every vmentry is costly so we just use an hrtimer.
11923 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11926 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11927 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11928 PIN_BASED_VMX_PREEMPTION_TIMER
);
11930 return delta_tsc
== 0;
11933 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11935 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11936 vmx
->hv_deadline_tsc
= -1;
11937 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11938 PIN_BASED_VMX_PREEMPTION_TIMER
);
11942 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11945 shrink_ple_window(vcpu
);
11948 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11949 struct kvm_memory_slot
*slot
)
11951 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11952 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11955 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11956 struct kvm_memory_slot
*slot
)
11958 kvm_mmu_slot_set_dirty(kvm
, slot
);
11961 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11963 kvm_flush_pml_buffers(kvm
);
11966 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11968 struct vmcs12
*vmcs12
;
11969 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11971 struct page
*page
= NULL
;
11974 if (is_guest_mode(vcpu
)) {
11975 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11978 * Check if PML is enabled for the nested guest.
11979 * Whether eptp bit 6 is set is already checked
11980 * as part of A/D emulation.
11982 vmcs12
= get_vmcs12(vcpu
);
11983 if (!nested_cpu_has_pml(vmcs12
))
11986 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11987 vmx
->nested
.pml_full
= true;
11991 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11993 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11994 if (is_error_page(page
))
11997 pml_address
= kmap(page
);
11998 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
12000 kvm_release_page_clean(page
);
12006 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
12007 struct kvm_memory_slot
*memslot
,
12008 gfn_t offset
, unsigned long mask
)
12010 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
12013 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
12015 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
12016 struct pi_desc old
, new;
12020 old
.control
= new.control
= pi_desc
->control
;
12021 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
12022 "Wakeup handler not enabled while the VCPU is blocked\n");
12024 dest
= cpu_physical_id(vcpu
->cpu
);
12026 if (x2apic_enabled())
12029 new.ndst
= (dest
<< 8) & 0xFF00;
12031 /* set 'NV' to 'notification vector' */
12032 new.nv
= POSTED_INTR_VECTOR
;
12033 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
12034 new.control
) != old
.control
);
12036 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
12037 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12038 list_del(&vcpu
->blocked_vcpu_list
);
12039 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12040 vcpu
->pre_pcpu
= -1;
12045 * This routine does the following things for vCPU which is going
12046 * to be blocked if VT-d PI is enabled.
12047 * - Store the vCPU to the wakeup list, so when interrupts happen
12048 * we can find the right vCPU to wake up.
12049 * - Change the Posted-interrupt descriptor as below:
12050 * 'NDST' <-- vcpu->pre_pcpu
12051 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
12052 * - If 'ON' is set during this process, which means at least one
12053 * interrupt is posted for this vCPU, we cannot block it, in
12054 * this case, return 1, otherwise, return 0.
12057 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
12060 struct pi_desc old
, new;
12061 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
12063 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
12064 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
12065 !kvm_vcpu_apicv_active(vcpu
))
12068 WARN_ON(irqs_disabled());
12069 local_irq_disable();
12070 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
12071 vcpu
->pre_pcpu
= vcpu
->cpu
;
12072 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12073 list_add_tail(&vcpu
->blocked_vcpu_list
,
12074 &per_cpu(blocked_vcpu_on_cpu
,
12076 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
12080 old
.control
= new.control
= pi_desc
->control
;
12082 WARN((pi_desc
->sn
== 1),
12083 "Warning: SN field of posted-interrupts "
12084 "is set before blocking\n");
12087 * Since vCPU can be preempted during this process,
12088 * vcpu->cpu could be different with pre_pcpu, we
12089 * need to set pre_pcpu as the destination of wakeup
12090 * notification event, then we can find the right vCPU
12091 * to wakeup in wakeup handler if interrupts happen
12092 * when the vCPU is in blocked state.
12094 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
12096 if (x2apic_enabled())
12099 new.ndst
= (dest
<< 8) & 0xFF00;
12101 /* set 'NV' to 'wakeup vector' */
12102 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
12103 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
12104 new.control
) != old
.control
);
12106 /* We should not block the vCPU if an interrupt is posted for it. */
12107 if (pi_test_on(pi_desc
) == 1)
12108 __pi_post_block(vcpu
);
12110 local_irq_enable();
12111 return (vcpu
->pre_pcpu
== -1);
12114 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
12116 if (pi_pre_block(vcpu
))
12119 if (kvm_lapic_hv_timer_in_use(vcpu
))
12120 kvm_lapic_switch_to_sw_timer(vcpu
);
12125 static void pi_post_block(struct kvm_vcpu
*vcpu
)
12127 if (vcpu
->pre_pcpu
== -1)
12130 WARN_ON(irqs_disabled());
12131 local_irq_disable();
12132 __pi_post_block(vcpu
);
12133 local_irq_enable();
12136 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
12138 if (kvm_x86_ops
->set_hv_timer
)
12139 kvm_lapic_switch_to_hv_timer(vcpu
);
12141 pi_post_block(vcpu
);
12145 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12148 * @host_irq: host irq of the interrupt
12149 * @guest_irq: gsi of the interrupt
12150 * @set: set or unset PI
12151 * returns 0 on success, < 0 on failure
12153 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
12154 uint32_t guest_irq
, bool set
)
12156 struct kvm_kernel_irq_routing_entry
*e
;
12157 struct kvm_irq_routing_table
*irq_rt
;
12158 struct kvm_lapic_irq irq
;
12159 struct kvm_vcpu
*vcpu
;
12160 struct vcpu_data vcpu_info
;
12163 if (!kvm_arch_has_assigned_device(kvm
) ||
12164 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
12165 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
12168 idx
= srcu_read_lock(&kvm
->irq_srcu
);
12169 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
12170 if (guest_irq
>= irq_rt
->nr_rt_entries
||
12171 hlist_empty(&irq_rt
->map
[guest_irq
])) {
12172 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12173 guest_irq
, irq_rt
->nr_rt_entries
);
12177 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
12178 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
12181 * VT-d PI cannot support posting multicast/broadcast
12182 * interrupts to a vCPU, we still use interrupt remapping
12183 * for these kind of interrupts.
12185 * For lowest-priority interrupts, we only support
12186 * those with single CPU as the destination, e.g. user
12187 * configures the interrupts via /proc/irq or uses
12188 * irqbalance to make the interrupts single-CPU.
12190 * We will support full lowest-priority interrupt later.
12193 kvm_set_msi_irq(kvm
, e
, &irq
);
12194 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
12196 * Make sure the IRTE is in remapped mode if
12197 * we don't handle it in posted mode.
12199 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
12202 "failed to back to remapped mode, irq: %u\n",
12210 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
12211 vcpu_info
.vector
= irq
.vector
;
12213 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
12214 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
12217 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
12219 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
12222 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
12230 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
12234 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
12236 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
12237 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
12238 FEATURE_CONTROL_LMCE
;
12240 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
12241 ~FEATURE_CONTROL_LMCE
;
12244 static int vmx_smi_allowed(struct kvm_vcpu
*vcpu
)
12246 /* we need a nested vmexit to enter SMM, postpone if run is pending */
12247 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
12252 static int vmx_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
12254 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12256 vmx
->nested
.smm
.guest_mode
= is_guest_mode(vcpu
);
12257 if (vmx
->nested
.smm
.guest_mode
)
12258 nested_vmx_vmexit(vcpu
, -1, 0, 0);
12260 vmx
->nested
.smm
.vmxon
= vmx
->nested
.vmxon
;
12261 vmx
->nested
.vmxon
= false;
12265 static int vmx_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
12267 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12270 if (vmx
->nested
.smm
.vmxon
) {
12271 vmx
->nested
.vmxon
= true;
12272 vmx
->nested
.smm
.vmxon
= false;
12275 if (vmx
->nested
.smm
.guest_mode
) {
12276 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
12277 ret
= enter_vmx_non_root_mode(vcpu
, false);
12278 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
12282 vmx
->nested
.smm
.guest_mode
= false;
12287 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
12292 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
12293 .cpu_has_kvm_support
= cpu_has_kvm_support
,
12294 .disabled_by_bios
= vmx_disabled_by_bios
,
12295 .hardware_setup
= hardware_setup
,
12296 .hardware_unsetup
= hardware_unsetup
,
12297 .check_processor_compatibility
= vmx_check_processor_compat
,
12298 .hardware_enable
= hardware_enable
,
12299 .hardware_disable
= hardware_disable
,
12300 .cpu_has_accelerated_tpr
= report_flexpriority
,
12301 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
12303 .vcpu_create
= vmx_create_vcpu
,
12304 .vcpu_free
= vmx_free_vcpu
,
12305 .vcpu_reset
= vmx_vcpu_reset
,
12307 .prepare_guest_switch
= vmx_save_host_state
,
12308 .vcpu_load
= vmx_vcpu_load
,
12309 .vcpu_put
= vmx_vcpu_put
,
12311 .update_bp_intercept
= update_exception_bitmap
,
12312 .get_msr_feature
= vmx_get_msr_feature
,
12313 .get_msr
= vmx_get_msr
,
12314 .set_msr
= vmx_set_msr
,
12315 .get_segment_base
= vmx_get_segment_base
,
12316 .get_segment
= vmx_get_segment
,
12317 .set_segment
= vmx_set_segment
,
12318 .get_cpl
= vmx_get_cpl
,
12319 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
12320 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
12321 .decache_cr3
= vmx_decache_cr3
,
12322 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
12323 .set_cr0
= vmx_set_cr0
,
12324 .set_cr3
= vmx_set_cr3
,
12325 .set_cr4
= vmx_set_cr4
,
12326 .set_efer
= vmx_set_efer
,
12327 .get_idt
= vmx_get_idt
,
12328 .set_idt
= vmx_set_idt
,
12329 .get_gdt
= vmx_get_gdt
,
12330 .set_gdt
= vmx_set_gdt
,
12331 .get_dr6
= vmx_get_dr6
,
12332 .set_dr6
= vmx_set_dr6
,
12333 .set_dr7
= vmx_set_dr7
,
12334 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
12335 .cache_reg
= vmx_cache_reg
,
12336 .get_rflags
= vmx_get_rflags
,
12337 .set_rflags
= vmx_set_rflags
,
12339 .tlb_flush
= vmx_flush_tlb
,
12341 .run
= vmx_vcpu_run
,
12342 .handle_exit
= vmx_handle_exit
,
12343 .skip_emulated_instruction
= skip_emulated_instruction
,
12344 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
12345 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
12346 .patch_hypercall
= vmx_patch_hypercall
,
12347 .set_irq
= vmx_inject_irq
,
12348 .set_nmi
= vmx_inject_nmi
,
12349 .queue_exception
= vmx_queue_exception
,
12350 .cancel_injection
= vmx_cancel_injection
,
12351 .interrupt_allowed
= vmx_interrupt_allowed
,
12352 .nmi_allowed
= vmx_nmi_allowed
,
12353 .get_nmi_mask
= vmx_get_nmi_mask
,
12354 .set_nmi_mask
= vmx_set_nmi_mask
,
12355 .enable_nmi_window
= enable_nmi_window
,
12356 .enable_irq_window
= enable_irq_window
,
12357 .update_cr8_intercept
= update_cr8_intercept
,
12358 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
12359 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
12360 .get_enable_apicv
= vmx_get_enable_apicv
,
12361 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
12362 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
12363 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
12364 .hwapic_irr_update
= vmx_hwapic_irr_update
,
12365 .hwapic_isr_update
= vmx_hwapic_isr_update
,
12366 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
12367 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
12369 .set_tss_addr
= vmx_set_tss_addr
,
12370 .get_tdp_level
= get_ept_level
,
12371 .get_mt_mask
= vmx_get_mt_mask
,
12373 .get_exit_info
= vmx_get_exit_info
,
12375 .get_lpage_level
= vmx_get_lpage_level
,
12377 .cpuid_update
= vmx_cpuid_update
,
12379 .rdtscp_supported
= vmx_rdtscp_supported
,
12380 .invpcid_supported
= vmx_invpcid_supported
,
12382 .set_supported_cpuid
= vmx_set_supported_cpuid
,
12384 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
12386 .write_tsc_offset
= vmx_write_tsc_offset
,
12388 .set_tdp_cr3
= vmx_set_cr3
,
12390 .check_intercept
= vmx_check_intercept
,
12391 .handle_external_intr
= vmx_handle_external_intr
,
12392 .mpx_supported
= vmx_mpx_supported
,
12393 .xsaves_supported
= vmx_xsaves_supported
,
12394 .umip_emulated
= vmx_umip_emulated
,
12396 .check_nested_events
= vmx_check_nested_events
,
12398 .sched_in
= vmx_sched_in
,
12400 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
12401 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
12402 .flush_log_dirty
= vmx_flush_log_dirty
,
12403 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
12404 .write_log_dirty
= vmx_write_pml_buffer
,
12406 .pre_block
= vmx_pre_block
,
12407 .post_block
= vmx_post_block
,
12409 .pmu_ops
= &intel_pmu_ops
,
12411 .update_pi_irte
= vmx_update_pi_irte
,
12413 #ifdef CONFIG_X86_64
12414 .set_hv_timer
= vmx_set_hv_timer
,
12415 .cancel_hv_timer
= vmx_cancel_hv_timer
,
12418 .setup_mce
= vmx_setup_mce
,
12420 .smi_allowed
= vmx_smi_allowed
,
12421 .pre_enter_smm
= vmx_pre_enter_smm
,
12422 .pre_leave_smm
= vmx_pre_leave_smm
,
12423 .enable_smi_window
= enable_smi_window
,
12426 static int __init
vmx_init(void)
12428 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
12429 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
12433 #ifdef CONFIG_KEXEC_CORE
12434 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
12435 crash_vmclear_local_loaded_vmcss
);
12441 static void __exit
vmx_exit(void)
12443 #ifdef CONFIG_KEXEC_CORE
12444 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
12451 module_init(vmx_init
)
12452 module_exit(vmx_exit
)