2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id vmx_cpu_id
[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
60 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
62 static bool __read_mostly enable_vpid
= 1;
63 module_param_named(vpid
, enable_vpid
, bool, 0444);
65 static bool __read_mostly flexpriority_enabled
= 1;
66 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
68 static bool __read_mostly enable_ept
= 1;
69 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
71 static bool __read_mostly enable_unrestricted_guest
= 1;
72 module_param_named(unrestricted_guest
,
73 enable_unrestricted_guest
, bool, S_IRUGO
);
75 static bool __read_mostly enable_ept_ad_bits
= 1;
76 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
78 static bool __read_mostly emulate_invalid_guest_state
= true;
79 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
81 static bool __read_mostly vmm_exclusive
= 1;
82 module_param(vmm_exclusive
, bool, S_IRUGO
);
84 static bool __read_mostly fasteoi
= 1;
85 module_param(fasteoi
, bool, S_IRUGO
);
87 static bool __read_mostly enable_apicv
= 1;
88 module_param(enable_apicv
, bool, S_IRUGO
);
90 static bool __read_mostly enable_shadow_vmcs
= 1;
91 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
97 static bool __read_mostly nested
= 0;
98 module_param(nested
, bool, S_IRUGO
);
100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
102 #define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
104 #define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
117 * According to test, this time is usually smaller than 128 cycles.
118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
124 #define KVM_VMX_DEFAULT_PLE_GAP 128
125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
127 module_param(ple_gap
, int, S_IRUGO
);
129 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
130 module_param(ple_window
, int, S_IRUGO
);
132 extern const ulong vmx_return
;
134 #define NR_AUTOLOAD_MSRS 8
135 #define VMCS02_POOL_SIZE 1
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
152 struct list_head loaded_vmcss_on_cpu_link
;
155 struct shared_msr_entry
{
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
174 typedef u64 natural_width
;
175 struct __packed vmcs12
{
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
182 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding
[7]; /* room for future expansion */
188 u64 vm_exit_msr_store_addr
;
189 u64 vm_exit_msr_load_addr
;
190 u64 vm_entry_msr_load_addr
;
192 u64 virtual_apic_page_addr
;
193 u64 apic_access_addr
;
195 u64 guest_physical_address
;
196 u64 vmcs_link_pointer
;
197 u64 guest_ia32_debugctl
;
200 u64 guest_ia32_perf_global_ctrl
;
207 u64 host_ia32_perf_global_ctrl
;
208 u64 padding64
[8]; /* room for future expansion */
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
215 natural_width cr0_guest_host_mask
;
216 natural_width cr4_guest_host_mask
;
217 natural_width cr0_read_shadow
;
218 natural_width cr4_read_shadow
;
219 natural_width cr3_target_value0
;
220 natural_width cr3_target_value1
;
221 natural_width cr3_target_value2
;
222 natural_width cr3_target_value3
;
223 natural_width exit_qualification
;
224 natural_width guest_linear_address
;
225 natural_width guest_cr0
;
226 natural_width guest_cr3
;
227 natural_width guest_cr4
;
228 natural_width guest_es_base
;
229 natural_width guest_cs_base
;
230 natural_width guest_ss_base
;
231 natural_width guest_ds_base
;
232 natural_width guest_fs_base
;
233 natural_width guest_gs_base
;
234 natural_width guest_ldtr_base
;
235 natural_width guest_tr_base
;
236 natural_width guest_gdtr_base
;
237 natural_width guest_idtr_base
;
238 natural_width guest_dr7
;
239 natural_width guest_rsp
;
240 natural_width guest_rip
;
241 natural_width guest_rflags
;
242 natural_width guest_pending_dbg_exceptions
;
243 natural_width guest_sysenter_esp
;
244 natural_width guest_sysenter_eip
;
245 natural_width host_cr0
;
246 natural_width host_cr3
;
247 natural_width host_cr4
;
248 natural_width host_fs_base
;
249 natural_width host_gs_base
;
250 natural_width host_tr_base
;
251 natural_width host_gdtr_base
;
252 natural_width host_idtr_base
;
253 natural_width host_ia32_sysenter_esp
;
254 natural_width host_ia32_sysenter_eip
;
255 natural_width host_rsp
;
256 natural_width host_rip
;
257 natural_width paddingl
[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control
;
259 u32 cpu_based_vm_exec_control
;
260 u32 exception_bitmap
;
261 u32 page_fault_error_code_mask
;
262 u32 page_fault_error_code_match
;
263 u32 cr3_target_count
;
264 u32 vm_exit_controls
;
265 u32 vm_exit_msr_store_count
;
266 u32 vm_exit_msr_load_count
;
267 u32 vm_entry_controls
;
268 u32 vm_entry_msr_load_count
;
269 u32 vm_entry_intr_info_field
;
270 u32 vm_entry_exception_error_code
;
271 u32 vm_entry_instruction_len
;
273 u32 secondary_vm_exec_control
;
274 u32 vm_instruction_error
;
276 u32 vm_exit_intr_info
;
277 u32 vm_exit_intr_error_code
;
278 u32 idt_vectoring_info_field
;
279 u32 idt_vectoring_error_code
;
280 u32 vm_exit_instruction_len
;
281 u32 vmx_instruction_info
;
288 u32 guest_ldtr_limit
;
290 u32 guest_gdtr_limit
;
291 u32 guest_idtr_limit
;
292 u32 guest_es_ar_bytes
;
293 u32 guest_cs_ar_bytes
;
294 u32 guest_ss_ar_bytes
;
295 u32 guest_ds_ar_bytes
;
296 u32 guest_fs_ar_bytes
;
297 u32 guest_gs_ar_bytes
;
298 u32 guest_ldtr_ar_bytes
;
299 u32 guest_tr_ar_bytes
;
300 u32 guest_interruptibility_info
;
301 u32 guest_activity_state
;
302 u32 guest_sysenter_cs
;
303 u32 host_ia32_sysenter_cs
;
304 u32 vmx_preemption_timer_value
;
305 u32 padding32
[7]; /* room for future expansion */
306 u16 virtual_processor_id
;
307 u16 guest_es_selector
;
308 u16 guest_cs_selector
;
309 u16 guest_ss_selector
;
310 u16 guest_ds_selector
;
311 u16 guest_fs_selector
;
312 u16 guest_gs_selector
;
313 u16 guest_ldtr_selector
;
314 u16 guest_tr_selector
;
315 u16 host_es_selector
;
316 u16 host_cs_selector
;
317 u16 host_ss_selector
;
318 u16 host_ds_selector
;
319 u16 host_fs_selector
;
320 u16 host_gs_selector
;
321 u16 host_tr_selector
;
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
329 #define VMCS12_REVISION 0x11e57ed0
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
336 #define VMCS12_SIZE 0x1000
338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
340 struct list_head list
;
342 struct loaded_vmcs vmcs02
;
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
350 /* Has the level1 guest done vmxon? */
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
355 /* The host-usable pointer to the above */
356 struct page
*current_vmcs12_page
;
357 struct vmcs12
*current_vmcs12
;
358 struct vmcs
*current_shadow_vmcs
;
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
363 bool sync_shadow_vmcs
;
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool
;
368 u64 vmcs01_tsc_offset
;
369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending
;
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
375 struct page
*apic_access_page
;
376 u64 msr_ia32_feature_control
;
379 #define POSTED_INTR_ON 0
380 /* Posted-Interrupt Descriptor */
382 u32 pir
[8]; /* Posted interrupt requested */
383 u32 control
; /* bit 0 of control is outstanding notification bit */
387 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
389 return test_and_set_bit(POSTED_INTR_ON
,
390 (unsigned long *)&pi_desc
->control
);
393 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
395 return test_and_clear_bit(POSTED_INTR_ON
,
396 (unsigned long *)&pi_desc
->control
);
399 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
401 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
405 struct kvm_vcpu vcpu
;
406 unsigned long host_rsp
;
409 bool nmi_known_unmasked
;
411 u32 idt_vectoring_info
;
413 struct shared_msr_entry
*guest_msrs
;
416 unsigned long host_idt_base
;
418 u64 msr_host_kernel_gs_base
;
419 u64 msr_guest_kernel_gs_base
;
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
426 struct loaded_vmcs vmcs01
;
427 struct loaded_vmcs
*loaded_vmcs
;
428 bool __launched
; /* temporary, used in vmx_vcpu_run */
429 struct msr_autoload
{
431 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
432 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
436 u16 fs_sel
, gs_sel
, ldt_sel
;
440 int gs_ldt_reload_needed
;
441 int fs_reload_needed
;
446 struct kvm_segment segs
[8];
449 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
450 struct kvm_save_segment
{
458 bool emulation_required
;
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked
;
463 s64 vnmi_blocked_time
;
468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc
;
471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested
;
475 enum segment_cache_field
{
484 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
486 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
495 static const unsigned long shadow_read_only_fields
[] = {
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
510 VM_EXIT_INSTRUCTION_LEN
,
511 IDT_VECTORING_INFO_FIELD
,
512 IDT_VECTORING_ERROR_CODE
,
513 VM_EXIT_INTR_ERROR_CODE
,
515 GUEST_LINEAR_ADDRESS
,
516 GUEST_PHYSICAL_ADDRESS
518 static const int max_shadow_read_only_fields
=
519 ARRAY_SIZE(shadow_read_only_fields
);
521 static const unsigned long shadow_read_write_fields
[] = {
527 GUEST_INTERRUPTIBILITY_INFO
,
539 CPU_BASED_VM_EXEC_CONTROL
,
540 VM_ENTRY_EXCEPTION_ERROR_CODE
,
541 VM_ENTRY_INTR_INFO_FIELD
,
542 VM_ENTRY_INSTRUCTION_LEN
,
543 VM_ENTRY_EXCEPTION_ERROR_CODE
,
549 static const int max_shadow_read_write_fields
=
550 ARRAY_SIZE(shadow_read_write_fields
);
552 static const unsigned short vmcs_field_to_offset_table
[] = {
553 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
554 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
555 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
556 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
557 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
558 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
559 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
560 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
561 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
562 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
563 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
564 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
565 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
566 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
567 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
568 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
569 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
570 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
571 FIELD64(MSR_BITMAP
, msr_bitmap
),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
575 FIELD64(TSC_OFFSET
, tsc_offset
),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
577 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
578 FIELD64(EPT_POINTER
, ept_pointer
),
579 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
580 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
581 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
582 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
583 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
585 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
586 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
587 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
588 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
589 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
590 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
594 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
597 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
598 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
599 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
601 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
606 FIELD(TPR_THRESHOLD
, tpr_threshold
),
607 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
608 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
609 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
610 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
611 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
612 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
613 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
614 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
615 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
616 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
617 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
618 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
619 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
620 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
621 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
622 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
623 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
624 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
625 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
626 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
627 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
628 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
629 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
630 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
631 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
632 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
633 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
635 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
636 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
637 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
638 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
639 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
640 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
641 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
642 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
643 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
644 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
645 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
646 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
647 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
648 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
649 FIELD(GUEST_CR0
, guest_cr0
),
650 FIELD(GUEST_CR3
, guest_cr3
),
651 FIELD(GUEST_CR4
, guest_cr4
),
652 FIELD(GUEST_ES_BASE
, guest_es_base
),
653 FIELD(GUEST_CS_BASE
, guest_cs_base
),
654 FIELD(GUEST_SS_BASE
, guest_ss_base
),
655 FIELD(GUEST_DS_BASE
, guest_ds_base
),
656 FIELD(GUEST_FS_BASE
, guest_fs_base
),
657 FIELD(GUEST_GS_BASE
, guest_gs_base
),
658 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
659 FIELD(GUEST_TR_BASE
, guest_tr_base
),
660 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
661 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
662 FIELD(GUEST_DR7
, guest_dr7
),
663 FIELD(GUEST_RSP
, guest_rsp
),
664 FIELD(GUEST_RIP
, guest_rip
),
665 FIELD(GUEST_RFLAGS
, guest_rflags
),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
667 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
668 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
669 FIELD(HOST_CR0
, host_cr0
),
670 FIELD(HOST_CR3
, host_cr3
),
671 FIELD(HOST_CR4
, host_cr4
),
672 FIELD(HOST_FS_BASE
, host_fs_base
),
673 FIELD(HOST_GS_BASE
, host_gs_base
),
674 FIELD(HOST_TR_BASE
, host_tr_base
),
675 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
676 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
677 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
678 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
679 FIELD(HOST_RSP
, host_rsp
),
680 FIELD(HOST_RIP
, host_rip
),
682 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
684 static inline short vmcs_field_to_offset(unsigned long field
)
686 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
688 return vmcs_field_to_offset_table
[field
];
691 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
693 return to_vmx(vcpu
)->nested
.current_vmcs12
;
696 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
698 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
699 if (is_error_page(page
))
705 static void nested_release_page(struct page
*page
)
707 kvm_release_page_dirty(page
);
710 static void nested_release_page_clean(struct page
*page
)
712 kvm_release_page_clean(page
);
715 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
716 static u64
construct_eptp(unsigned long root_hpa
);
717 static void kvm_cpu_vmxon(u64 addr
);
718 static void kvm_cpu_vmxoff(void);
719 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
720 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
721 struct kvm_segment
*var
, int seg
);
722 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
723 struct kvm_segment
*var
, int seg
);
724 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
725 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
726 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
727 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
728 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
730 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
731 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
736 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
737 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
739 static unsigned long *vmx_io_bitmap_a
;
740 static unsigned long *vmx_io_bitmap_b
;
741 static unsigned long *vmx_msr_bitmap_legacy
;
742 static unsigned long *vmx_msr_bitmap_longmode
;
743 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
744 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
745 static unsigned long *vmx_vmread_bitmap
;
746 static unsigned long *vmx_vmwrite_bitmap
;
748 static bool cpu_has_load_ia32_efer
;
749 static bool cpu_has_load_perf_global_ctrl
;
751 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
752 static DEFINE_SPINLOCK(vmx_vpid_lock
);
754 static struct vmcs_config
{
758 u32 pin_based_exec_ctrl
;
759 u32 cpu_based_exec_ctrl
;
760 u32 cpu_based_2nd_exec_ctrl
;
765 static struct vmx_capability
{
770 #define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
778 static const struct kvm_vmx_segment_field
{
783 } kvm_vmx_segment_fields
[] = {
784 VMX_SEGMENT_FIELD(CS
),
785 VMX_SEGMENT_FIELD(DS
),
786 VMX_SEGMENT_FIELD(ES
),
787 VMX_SEGMENT_FIELD(FS
),
788 VMX_SEGMENT_FIELD(GS
),
789 VMX_SEGMENT_FIELD(SS
),
790 VMX_SEGMENT_FIELD(TR
),
791 VMX_SEGMENT_FIELD(LDTR
),
794 static u64 host_efer
;
796 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
800 * away by decrementing the array size.
802 static const u32 vmx_msr_index
[] = {
804 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
806 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
808 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
810 static inline bool is_page_fault(u32 intr_info
)
812 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
813 INTR_INFO_VALID_MASK
)) ==
814 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
817 static inline bool is_no_device(u32 intr_info
)
819 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
820 INTR_INFO_VALID_MASK
)) ==
821 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
824 static inline bool is_invalid_opcode(u32 intr_info
)
826 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
827 INTR_INFO_VALID_MASK
)) ==
828 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
831 static inline bool is_external_interrupt(u32 intr_info
)
833 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
834 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
837 static inline bool is_machine_check(u32 intr_info
)
839 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
840 INTR_INFO_VALID_MASK
)) ==
841 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
844 static inline bool cpu_has_vmx_msr_bitmap(void)
846 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
849 static inline bool cpu_has_vmx_tpr_shadow(void)
851 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
854 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
859 static inline bool cpu_has_secondary_exec_ctrls(void)
861 return vmcs_config
.cpu_based_exec_ctrl
&
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
865 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
867 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
871 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
873 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
877 static inline bool cpu_has_vmx_apic_register_virt(void)
879 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
880 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
883 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
885 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
889 static inline bool cpu_has_vmx_posted_intr(void)
891 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
894 static inline bool cpu_has_vmx_apicv(void)
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
901 static inline bool cpu_has_vmx_flexpriority(void)
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
907 static inline bool cpu_has_vmx_ept_execute_only(void)
909 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
912 static inline bool cpu_has_vmx_eptp_uncacheable(void)
914 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
917 static inline bool cpu_has_vmx_eptp_writeback(void)
919 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
922 static inline bool cpu_has_vmx_ept_2m_page(void)
924 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
927 static inline bool cpu_has_vmx_ept_1g_page(void)
929 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
932 static inline bool cpu_has_vmx_ept_4levels(void)
934 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
937 static inline bool cpu_has_vmx_ept_ad_bits(void)
939 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
942 static inline bool cpu_has_vmx_invept_context(void)
944 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
947 static inline bool cpu_has_vmx_invept_global(void)
949 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
952 static inline bool cpu_has_vmx_invvpid_single(void)
954 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
957 static inline bool cpu_has_vmx_invvpid_global(void)
959 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
962 static inline bool cpu_has_vmx_ept(void)
964 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
965 SECONDARY_EXEC_ENABLE_EPT
;
968 static inline bool cpu_has_vmx_unrestricted_guest(void)
970 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
971 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
974 static inline bool cpu_has_vmx_ple(void)
976 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
980 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
982 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
985 static inline bool cpu_has_vmx_vpid(void)
987 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
988 SECONDARY_EXEC_ENABLE_VPID
;
991 static inline bool cpu_has_vmx_rdtscp(void)
993 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
994 SECONDARY_EXEC_RDTSCP
;
997 static inline bool cpu_has_vmx_invpcid(void)
999 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1000 SECONDARY_EXEC_ENABLE_INVPCID
;
1003 static inline bool cpu_has_virtual_nmis(void)
1005 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1008 static inline bool cpu_has_vmx_wbinvd_exit(void)
1010 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1011 SECONDARY_EXEC_WBINVD_EXITING
;
1014 static inline bool cpu_has_vmx_shadow_vmcs(void)
1017 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1022 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1023 SECONDARY_EXEC_SHADOW_VMCS
;
1026 static inline bool report_flexpriority(void)
1028 return flexpriority_enabled
;
1031 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1033 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1036 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1038 return (vmcs12
->cpu_based_vm_exec_control
&
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1040 (vmcs12
->secondary_vm_exec_control
& bit
);
1043 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1045 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1048 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1050 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1053 static inline bool is_exception(u32 intr_info
)
1055 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1056 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1059 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
1060 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1061 struct vmcs12
*vmcs12
,
1062 u32 reason
, unsigned long qualification
);
1064 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1068 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1069 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1074 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1080 } operand
= { vpid
, 0, gva
};
1082 asm volatile (__ex(ASM_VMX_INVVPID
)
1083 /* CF==1 or ZF==1 --> rc = -1 */
1084 "; ja 1f ; ud2 ; 1:"
1085 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1088 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1092 } operand
= {eptp
, gpa
};
1094 asm volatile (__ex(ASM_VMX_INVEPT
)
1095 /* CF==1 or ZF==1 --> rc = -1 */
1096 "; ja 1f ; ud2 ; 1:\n"
1097 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1100 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1104 i
= __find_msr_index(vmx
, msr
);
1106 return &vmx
->guest_msrs
[i
];
1110 static void vmcs_clear(struct vmcs
*vmcs
)
1112 u64 phys_addr
= __pa(vmcs
);
1115 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1116 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1119 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1123 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1125 vmcs_clear(loaded_vmcs
->vmcs
);
1126 loaded_vmcs
->cpu
= -1;
1127 loaded_vmcs
->launched
= 0;
1130 static void vmcs_load(struct vmcs
*vmcs
)
1132 u64 phys_addr
= __pa(vmcs
);
1135 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1136 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1139 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1145 * This bitmap is used to indicate whether the vmclear
1146 * operation is enabled on all cpus. All disabled by
1149 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1151 static inline void crash_enable_local_vmclear(int cpu
)
1153 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1156 static inline void crash_disable_local_vmclear(int cpu
)
1158 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1161 static inline int crash_local_vmclear_enabled(int cpu
)
1163 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1166 static void crash_vmclear_local_loaded_vmcss(void)
1168 int cpu
= raw_smp_processor_id();
1169 struct loaded_vmcs
*v
;
1171 if (!crash_local_vmclear_enabled(cpu
))
1174 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1175 loaded_vmcss_on_cpu_link
)
1176 vmcs_clear(v
->vmcs
);
1179 static inline void crash_enable_local_vmclear(int cpu
) { }
1180 static inline void crash_disable_local_vmclear(int cpu
) { }
1181 #endif /* CONFIG_KEXEC */
1183 static void __loaded_vmcs_clear(void *arg
)
1185 struct loaded_vmcs
*loaded_vmcs
= arg
;
1186 int cpu
= raw_smp_processor_id();
1188 if (loaded_vmcs
->cpu
!= cpu
)
1189 return; /* vcpu migration can race with cpu offline */
1190 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1191 per_cpu(current_vmcs
, cpu
) = NULL
;
1192 crash_disable_local_vmclear(cpu
);
1193 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1196 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197 * is before setting loaded_vmcs->vcpu to -1 which is done in
1198 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199 * then adds the vmcs into percpu list before it is deleted.
1203 loaded_vmcs_init(loaded_vmcs
);
1204 crash_enable_local_vmclear(cpu
);
1207 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1209 int cpu
= loaded_vmcs
->cpu
;
1212 smp_call_function_single(cpu
,
1213 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1216 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1221 if (cpu_has_vmx_invvpid_single())
1222 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1225 static inline void vpid_sync_vcpu_global(void)
1227 if (cpu_has_vmx_invvpid_global())
1228 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1231 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1233 if (cpu_has_vmx_invvpid_single())
1234 vpid_sync_vcpu_single(vmx
);
1236 vpid_sync_vcpu_global();
1239 static inline void ept_sync_global(void)
1241 if (cpu_has_vmx_invept_global())
1242 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1245 static inline void ept_sync_context(u64 eptp
)
1248 if (cpu_has_vmx_invept_context())
1249 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1255 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1257 unsigned long value
;
1259 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1260 : "=a"(value
) : "d"(field
) : "cc");
1264 static __always_inline u16
vmcs_read16(unsigned long field
)
1266 return vmcs_readl(field
);
1269 static __always_inline u32
vmcs_read32(unsigned long field
)
1271 return vmcs_readl(field
);
1274 static __always_inline u64
vmcs_read64(unsigned long field
)
1276 #ifdef CONFIG_X86_64
1277 return vmcs_readl(field
);
1279 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1283 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1285 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1286 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1290 static void vmcs_writel(unsigned long field
, unsigned long value
)
1294 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1295 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1296 if (unlikely(error
))
1297 vmwrite_error(field
, value
);
1300 static void vmcs_write16(unsigned long field
, u16 value
)
1302 vmcs_writel(field
, value
);
1305 static void vmcs_write32(unsigned long field
, u32 value
)
1307 vmcs_writel(field
, value
);
1310 static void vmcs_write64(unsigned long field
, u64 value
)
1312 vmcs_writel(field
, value
);
1313 #ifndef CONFIG_X86_64
1315 vmcs_writel(field
+1, value
>> 32);
1319 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1321 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1324 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1326 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1329 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1331 vmx
->segment_cache
.bitmask
= 0;
1334 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1338 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1340 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1341 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1342 vmx
->segment_cache
.bitmask
= 0;
1344 ret
= vmx
->segment_cache
.bitmask
& mask
;
1345 vmx
->segment_cache
.bitmask
|= mask
;
1349 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1351 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1353 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1354 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1358 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1360 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1362 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1363 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1367 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1369 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1371 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1372 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1376 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1378 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1380 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1381 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1385 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1389 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1390 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1391 if ((vcpu
->guest_debug
&
1392 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1393 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1394 eb
|= 1u << BP_VECTOR
;
1395 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1398 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1399 if (vcpu
->fpu_active
)
1400 eb
&= ~(1u << NM_VECTOR
);
1402 /* When we are running a nested L2 guest and L1 specified for it a
1403 * certain exception bitmap, we must trap the same exceptions and pass
1404 * them to L1. When running L2, we will only handle the exceptions
1405 * specified above if L1 did not want them.
1407 if (is_guest_mode(vcpu
))
1408 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1410 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1413 static void clear_atomic_switch_msr_special(unsigned long entry
,
1416 vmcs_clear_bits(VM_ENTRY_CONTROLS
, entry
);
1417 vmcs_clear_bits(VM_EXIT_CONTROLS
, exit
);
1420 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1423 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1427 if (cpu_has_load_ia32_efer
) {
1428 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1429 VM_EXIT_LOAD_IA32_EFER
);
1433 case MSR_CORE_PERF_GLOBAL_CTRL
:
1434 if (cpu_has_load_perf_global_ctrl
) {
1435 clear_atomic_switch_msr_special(
1436 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1437 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1443 for (i
= 0; i
< m
->nr
; ++i
)
1444 if (m
->guest
[i
].index
== msr
)
1450 m
->guest
[i
] = m
->guest
[m
->nr
];
1451 m
->host
[i
] = m
->host
[m
->nr
];
1452 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1456 static void add_atomic_switch_msr_special(unsigned long entry
,
1457 unsigned long exit
, unsigned long guest_val_vmcs
,
1458 unsigned long host_val_vmcs
, u64 guest_val
, u64 host_val
)
1460 vmcs_write64(guest_val_vmcs
, guest_val
);
1461 vmcs_write64(host_val_vmcs
, host_val
);
1462 vmcs_set_bits(VM_ENTRY_CONTROLS
, entry
);
1463 vmcs_set_bits(VM_EXIT_CONTROLS
, exit
);
1466 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1467 u64 guest_val
, u64 host_val
)
1470 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1474 if (cpu_has_load_ia32_efer
) {
1475 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1476 VM_EXIT_LOAD_IA32_EFER
,
1479 guest_val
, host_val
);
1483 case MSR_CORE_PERF_GLOBAL_CTRL
:
1484 if (cpu_has_load_perf_global_ctrl
) {
1485 add_atomic_switch_msr_special(
1486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1487 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1488 GUEST_IA32_PERF_GLOBAL_CTRL
,
1489 HOST_IA32_PERF_GLOBAL_CTRL
,
1490 guest_val
, host_val
);
1496 for (i
= 0; i
< m
->nr
; ++i
)
1497 if (m
->guest
[i
].index
== msr
)
1500 if (i
== NR_AUTOLOAD_MSRS
) {
1501 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1502 "Can't add msr %x\n", msr
);
1504 } else if (i
== m
->nr
) {
1506 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1510 m
->guest
[i
].index
= msr
;
1511 m
->guest
[i
].value
= guest_val
;
1512 m
->host
[i
].index
= msr
;
1513 m
->host
[i
].value
= host_val
;
1516 static void reload_tss(void)
1519 * VT restores TR but not its size. Useless.
1521 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1522 struct desc_struct
*descs
;
1524 descs
= (void *)gdt
->address
;
1525 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1529 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1534 guest_efer
= vmx
->vcpu
.arch
.efer
;
1537 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1540 ignore_bits
= EFER_NX
| EFER_SCE
;
1541 #ifdef CONFIG_X86_64
1542 ignore_bits
|= EFER_LMA
| EFER_LME
;
1543 /* SCE is meaningful only in long mode on Intel */
1544 if (guest_efer
& EFER_LMA
)
1545 ignore_bits
&= ~(u64
)EFER_SCE
;
1547 guest_efer
&= ~ignore_bits
;
1548 guest_efer
|= host_efer
& ignore_bits
;
1549 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1550 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1552 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1553 /* On ept, can't emulate nx, and must switch nx atomically */
1554 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1555 guest_efer
= vmx
->vcpu
.arch
.efer
;
1556 if (!(guest_efer
& EFER_LMA
))
1557 guest_efer
&= ~EFER_LME
;
1558 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1565 static unsigned long segment_base(u16 selector
)
1567 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1568 struct desc_struct
*d
;
1569 unsigned long table_base
;
1572 if (!(selector
& ~3))
1575 table_base
= gdt
->address
;
1577 if (selector
& 4) { /* from ldt */
1578 u16 ldt_selector
= kvm_read_ldt();
1580 if (!(ldt_selector
& ~3))
1583 table_base
= segment_base(ldt_selector
);
1585 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1586 v
= get_desc_base(d
);
1587 #ifdef CONFIG_X86_64
1588 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1589 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1594 static inline unsigned long kvm_read_tr_base(void)
1597 asm("str %0" : "=g"(tr
));
1598 return segment_base(tr
);
1601 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1603 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1606 if (vmx
->host_state
.loaded
)
1609 vmx
->host_state
.loaded
= 1;
1611 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1612 * allow segment selectors with cpl > 0 or ti == 1.
1614 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1615 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1616 savesegment(fs
, vmx
->host_state
.fs_sel
);
1617 if (!(vmx
->host_state
.fs_sel
& 7)) {
1618 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1619 vmx
->host_state
.fs_reload_needed
= 0;
1621 vmcs_write16(HOST_FS_SELECTOR
, 0);
1622 vmx
->host_state
.fs_reload_needed
= 1;
1624 savesegment(gs
, vmx
->host_state
.gs_sel
);
1625 if (!(vmx
->host_state
.gs_sel
& 7))
1626 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1628 vmcs_write16(HOST_GS_SELECTOR
, 0);
1629 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1632 #ifdef CONFIG_X86_64
1633 savesegment(ds
, vmx
->host_state
.ds_sel
);
1634 savesegment(es
, vmx
->host_state
.es_sel
);
1637 #ifdef CONFIG_X86_64
1638 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1639 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1641 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1642 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1645 #ifdef CONFIG_X86_64
1646 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1647 if (is_long_mode(&vmx
->vcpu
))
1648 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1650 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1651 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1652 vmx
->guest_msrs
[i
].data
,
1653 vmx
->guest_msrs
[i
].mask
);
1656 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1658 if (!vmx
->host_state
.loaded
)
1661 ++vmx
->vcpu
.stat
.host_state_reload
;
1662 vmx
->host_state
.loaded
= 0;
1663 #ifdef CONFIG_X86_64
1664 if (is_long_mode(&vmx
->vcpu
))
1665 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1667 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1668 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1669 #ifdef CONFIG_X86_64
1670 load_gs_index(vmx
->host_state
.gs_sel
);
1672 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1675 if (vmx
->host_state
.fs_reload_needed
)
1676 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1677 #ifdef CONFIG_X86_64
1678 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1679 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1680 loadsegment(es
, vmx
->host_state
.es_sel
);
1684 #ifdef CONFIG_X86_64
1685 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1688 * If the FPU is not active (through the host task or
1689 * the guest vcpu), then restore the cr0.TS bit.
1691 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1693 load_gdt(&__get_cpu_var(host_gdt
));
1696 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1699 __vmx_load_host_state(vmx
);
1704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705 * vcpu mutex is already taken.
1707 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1709 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1710 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1713 kvm_cpu_vmxon(phys_addr
);
1714 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1715 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1717 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1718 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1719 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1722 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1723 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1724 unsigned long sysenter_esp
;
1726 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1727 local_irq_disable();
1728 crash_disable_local_vmclear(cpu
);
1731 * Read loaded_vmcs->cpu should be before fetching
1732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733 * See the comments in __loaded_vmcs_clear().
1737 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1738 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1739 crash_enable_local_vmclear(cpu
);
1743 * Linux uses per-cpu TSS and GDT, so set these when switching
1746 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1747 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1749 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1750 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1751 vmx
->loaded_vmcs
->cpu
= cpu
;
1755 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1757 __vmx_load_host_state(to_vmx(vcpu
));
1758 if (!vmm_exclusive
) {
1759 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1765 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1769 if (vcpu
->fpu_active
)
1771 vcpu
->fpu_active
= 1;
1772 cr0
= vmcs_readl(GUEST_CR0
);
1773 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1774 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1775 vmcs_writel(GUEST_CR0
, cr0
);
1776 update_exception_bitmap(vcpu
);
1777 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1778 if (is_guest_mode(vcpu
))
1779 vcpu
->arch
.cr0_guest_owned_bits
&=
1780 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1781 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1784 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1787 * Return the cr0 value that a nested guest would read. This is a combination
1788 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789 * its hypervisor (cr0_read_shadow).
1791 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1793 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1794 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1796 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1798 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1799 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1802 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1804 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805 * set this *before* calling this function.
1807 vmx_decache_cr0_guest_bits(vcpu
);
1808 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1809 update_exception_bitmap(vcpu
);
1810 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1811 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1812 if (is_guest_mode(vcpu
)) {
1814 * L1's specified read shadow might not contain the TS bit,
1815 * so now that we turned on shadowing of this bit, we need to
1816 * set this bit of the shadow. Like in nested_vmx_run we need
1817 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818 * up-to-date here because we just decached cr0.TS (and we'll
1819 * only update vmcs12->guest_cr0 on nested exit).
1821 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1822 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1823 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1824 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1826 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1829 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1831 unsigned long rflags
, save_rflags
;
1833 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1834 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1835 rflags
= vmcs_readl(GUEST_RFLAGS
);
1836 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1837 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1838 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1839 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1841 to_vmx(vcpu
)->rflags
= rflags
;
1843 return to_vmx(vcpu
)->rflags
;
1846 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1848 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1849 to_vmx(vcpu
)->rflags
= rflags
;
1850 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1851 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1852 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1854 vmcs_writel(GUEST_RFLAGS
, rflags
);
1857 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1859 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1862 if (interruptibility
& GUEST_INTR_STATE_STI
)
1863 ret
|= KVM_X86_SHADOW_INT_STI
;
1864 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1865 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1870 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1872 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1873 u32 interruptibility
= interruptibility_old
;
1875 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1877 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1878 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1879 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1880 interruptibility
|= GUEST_INTR_STATE_STI
;
1882 if ((interruptibility
!= interruptibility_old
))
1883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1886 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1890 rip
= kvm_rip_read(vcpu
);
1891 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1892 kvm_rip_write(vcpu
, rip
);
1894 /* skipping an emulated instruction also counts */
1895 vmx_set_interrupt_shadow(vcpu
, 0);
1899 * KVM wants to inject page-faults which it got to the guest. This function
1900 * checks whether in a nested guest, we need to inject them to L1 or L2.
1902 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
1904 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1906 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
1909 nested_vmx_vmexit(vcpu
);
1913 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1914 bool has_error_code
, u32 error_code
,
1917 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1918 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1920 if (!reinject
&& is_guest_mode(vcpu
) &&
1921 nested_vmx_check_exception(vcpu
, nr
))
1924 if (has_error_code
) {
1925 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1926 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1929 if (vmx
->rmode
.vm86_active
) {
1931 if (kvm_exception_is_soft(nr
))
1932 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1933 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1934 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1938 if (kvm_exception_is_soft(nr
)) {
1939 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1940 vmx
->vcpu
.arch
.event_exit_inst_len
);
1941 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1943 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1948 static bool vmx_rdtscp_supported(void)
1950 return cpu_has_vmx_rdtscp();
1953 static bool vmx_invpcid_supported(void)
1955 return cpu_has_vmx_invpcid() && enable_ept
;
1959 * Swap MSR entry in host/guest MSR entry array.
1961 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1963 struct shared_msr_entry tmp
;
1965 tmp
= vmx
->guest_msrs
[to
];
1966 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1967 vmx
->guest_msrs
[from
] = tmp
;
1970 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
1972 unsigned long *msr_bitmap
;
1974 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
1975 if (is_long_mode(vcpu
))
1976 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
1978 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
1980 if (is_long_mode(vcpu
))
1981 msr_bitmap
= vmx_msr_bitmap_longmode
;
1983 msr_bitmap
= vmx_msr_bitmap_legacy
;
1986 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1990 * Set up the vmcs to automatically save and restore system
1991 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1992 * mode, as fiddling with msrs is very expensive.
1994 static void setup_msrs(struct vcpu_vmx
*vmx
)
1996 int save_nmsrs
, index
;
1999 #ifdef CONFIG_X86_64
2000 if (is_long_mode(&vmx
->vcpu
)) {
2001 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2003 move_msr_up(vmx
, index
, save_nmsrs
++);
2004 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2006 move_msr_up(vmx
, index
, save_nmsrs
++);
2007 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2009 move_msr_up(vmx
, index
, save_nmsrs
++);
2010 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2011 if (index
>= 0 && vmx
->rdtscp_enabled
)
2012 move_msr_up(vmx
, index
, save_nmsrs
++);
2014 * MSR_STAR is only needed on long mode guests, and only
2015 * if efer.sce is enabled.
2017 index
= __find_msr_index(vmx
, MSR_STAR
);
2018 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2019 move_msr_up(vmx
, index
, save_nmsrs
++);
2022 index
= __find_msr_index(vmx
, MSR_EFER
);
2023 if (index
>= 0 && update_transition_efer(vmx
, index
))
2024 move_msr_up(vmx
, index
, save_nmsrs
++);
2026 vmx
->save_nmsrs
= save_nmsrs
;
2028 if (cpu_has_vmx_msr_bitmap())
2029 vmx_set_msr_bitmap(&vmx
->vcpu
);
2033 * reads and returns guest's timestamp counter "register"
2034 * guest_tsc = host_tsc + tsc_offset -- 21.3
2036 static u64
guest_read_tsc(void)
2038 u64 host_tsc
, tsc_offset
;
2041 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2042 return host_tsc
+ tsc_offset
;
2046 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047 * counter, even if a nested guest (L2) is currently running.
2049 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2053 tsc_offset
= is_guest_mode(vcpu
) ?
2054 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2055 vmcs_read64(TSC_OFFSET
);
2056 return host_tsc
+ tsc_offset
;
2060 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2061 * software catchup for faster rates on slower CPUs.
2063 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2068 if (user_tsc_khz
> tsc_khz
) {
2069 vcpu
->arch
.tsc_catchup
= 1;
2070 vcpu
->arch
.tsc_always_catchup
= 1;
2072 WARN(1, "user requested TSC rate below hardware speed\n");
2075 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2077 return vmcs_read64(TSC_OFFSET
);
2081 * writes 'offset' into guest's timestamp counter offset register
2083 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2085 if (is_guest_mode(vcpu
)) {
2087 * We're here if L1 chose not to trap WRMSR to TSC. According
2088 * to the spec, this should set L1's TSC; The offset that L1
2089 * set for L2 remains unchanged, and still needs to be added
2090 * to the newly set TSC to get L2's TSC.
2092 struct vmcs12
*vmcs12
;
2093 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2094 /* recalculate vmcs02.TSC_OFFSET: */
2095 vmcs12
= get_vmcs12(vcpu
);
2096 vmcs_write64(TSC_OFFSET
, offset
+
2097 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2098 vmcs12
->tsc_offset
: 0));
2100 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2101 vmcs_read64(TSC_OFFSET
), offset
);
2102 vmcs_write64(TSC_OFFSET
, offset
);
2106 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2108 u64 offset
= vmcs_read64(TSC_OFFSET
);
2110 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2111 if (is_guest_mode(vcpu
)) {
2112 /* Even when running L2, the adjustment needs to apply to L1 */
2113 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2115 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2116 offset
+ adjustment
);
2119 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2121 return target_tsc
- native_read_tsc();
2124 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2126 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2127 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2131 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133 * all guests if the "nested" module option is off, and can also be disabled
2134 * for a single guest by disabling its VMX cpuid bit.
2136 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2138 return nested
&& guest_cpuid_has_vmx(vcpu
);
2142 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143 * returned for the various VMX controls MSRs when nested VMX is enabled.
2144 * The same values should also be used to verify that vmcs12 control fields are
2145 * valid during nested entry from L1 to L2.
2146 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148 * bit in the high half is on if the corresponding bit in the control field
2149 * may be on. See also vmx_control_verify().
2150 * TODO: allow these variables to be modified (downgraded) by module options
2153 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2154 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2155 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2156 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2157 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2158 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2159 static u32 nested_vmx_ept_caps
;
2160 static __init
void nested_vmx_setup_ctls_msrs(void)
2163 * Note that as a general rule, the high half of the MSRs (bits in
2164 * the control fields which may be 1) should be initialized by the
2165 * intersection of the underlying hardware's MSR (i.e., features which
2166 * can be supported) and the list of features we want to expose -
2167 * because they are known to be properly supported in our code.
2168 * Also, usually, the low half of the MSRs (bits which must be 1) can
2169 * be set to 0, meaning that L1 may turn off any of these bits. The
2170 * reason is that if one of these bits is necessary, it will appear
2171 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2172 * fields of vmcs01 and vmcs02, will turn these bits off - and
2173 * nested_vmx_exit_handled() will not pass related exits to L1.
2174 * These rules have exceptions below.
2177 /* pin-based controls */
2178 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2179 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2181 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2182 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2184 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2185 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2186 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
|
2187 PIN_BASED_VMX_PREEMPTION_TIMER
;
2188 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2192 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2195 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2196 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2197 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2198 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2199 nested_vmx_exit_ctls_high
&=
2200 #ifdef CONFIG_X86_64
2201 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2203 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
|
2204 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
2205 if (!(nested_vmx_pinbased_ctls_high
& PIN_BASED_VMX_PREEMPTION_TIMER
) ||
2206 !(nested_vmx_exit_ctls_high
& VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)) {
2207 nested_vmx_exit_ctls_high
&= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
2208 nested_vmx_pinbased_ctls_high
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
2210 nested_vmx_exit_ctls_high
|= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2211 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
);
2213 /* entry controls */
2214 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2215 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2216 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2217 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2218 nested_vmx_entry_ctls_high
&=
2219 #ifdef CONFIG_X86_64
2220 VM_ENTRY_IA32E_MODE
|
2222 VM_ENTRY_LOAD_IA32_PAT
;
2223 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2224 VM_ENTRY_LOAD_IA32_EFER
);
2226 /* cpu-based controls */
2227 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2228 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2229 nested_vmx_procbased_ctls_low
= 0;
2230 nested_vmx_procbased_ctls_high
&=
2231 CPU_BASED_VIRTUAL_INTR_PENDING
|
2232 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2233 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2234 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2235 CPU_BASED_CR3_STORE_EXITING
|
2236 #ifdef CONFIG_X86_64
2237 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2239 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2240 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2241 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2242 CPU_BASED_PAUSE_EXITING
|
2243 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2245 * We can allow some features even when not supported by the
2246 * hardware. For example, L1 can specify an MSR bitmap - and we
2247 * can use it to avoid exits to L1 - even when L0 runs L2
2248 * without MSR bitmaps.
2250 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2252 /* secondary cpu-based controls */
2253 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2254 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2255 nested_vmx_secondary_ctls_low
= 0;
2256 nested_vmx_secondary_ctls_high
&=
2257 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2258 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2259 SECONDARY_EXEC_WBINVD_EXITING
;
2262 /* nested EPT: emulate EPT also to L1 */
2263 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2264 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2265 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2267 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2269 * Since invept is completely emulated we support both global
2270 * and context invalidation independent of what host cpu
2273 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2274 VMX_EPT_EXTENT_CONTEXT_BIT
;
2276 nested_vmx_ept_caps
= 0;
2278 /* miscellaneous data */
2279 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2280 nested_vmx_misc_low
&= VMX_MISC_PREEMPTION_TIMER_RATE_MASK
|
2281 VMX_MISC_SAVE_EFER_LMA
;
2282 nested_vmx_misc_high
= 0;
2285 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2288 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2290 return ((control
& high
) | low
) == control
;
2293 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2295 return low
| ((u64
)high
<< 32);
2299 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2300 * also let it use VMX-specific MSRs.
2301 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2302 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2303 * like all other MSRs).
2305 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2307 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
2308 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
2310 * According to the spec, processors which do not support VMX
2311 * should throw a #GP(0) when VMX capability MSRs are read.
2313 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
2317 switch (msr_index
) {
2318 case MSR_IA32_FEATURE_CONTROL
:
2319 if (nested_vmx_allowed(vcpu
)) {
2320 *pdata
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2324 case MSR_IA32_VMX_BASIC
:
2326 * This MSR reports some information about VMX support. We
2327 * should return information about the VMX we emulate for the
2328 * guest, and the VMCS structure we give it - not about the
2329 * VMX support of the underlying hardware.
2331 *pdata
= VMCS12_REVISION
|
2332 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2333 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2335 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2336 case MSR_IA32_VMX_PINBASED_CTLS
:
2337 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2338 nested_vmx_pinbased_ctls_high
);
2340 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2341 case MSR_IA32_VMX_PROCBASED_CTLS
:
2342 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2343 nested_vmx_procbased_ctls_high
);
2345 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2346 case MSR_IA32_VMX_EXIT_CTLS
:
2347 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2348 nested_vmx_exit_ctls_high
);
2350 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2351 case MSR_IA32_VMX_ENTRY_CTLS
:
2352 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2353 nested_vmx_entry_ctls_high
);
2355 case MSR_IA32_VMX_MISC
:
2356 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2357 nested_vmx_misc_high
);
2360 * These MSRs specify bits which the guest must keep fixed (on or off)
2361 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2362 * We picked the standard core2 setting.
2364 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2365 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2366 case MSR_IA32_VMX_CR0_FIXED0
:
2367 *pdata
= VMXON_CR0_ALWAYSON
;
2369 case MSR_IA32_VMX_CR0_FIXED1
:
2372 case MSR_IA32_VMX_CR4_FIXED0
:
2373 *pdata
= VMXON_CR4_ALWAYSON
;
2375 case MSR_IA32_VMX_CR4_FIXED1
:
2378 case MSR_IA32_VMX_VMCS_ENUM
:
2381 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2382 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2383 nested_vmx_secondary_ctls_high
);
2385 case MSR_IA32_VMX_EPT_VPID_CAP
:
2386 /* Currently, no nested vpid support */
2387 *pdata
= nested_vmx_ept_caps
;
2396 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2398 u32 msr_index
= msr_info
->index
;
2399 u64 data
= msr_info
->data
;
2400 bool host_initialized
= msr_info
->host_initiated
;
2402 if (!nested_vmx_allowed(vcpu
))
2405 if (msr_index
== MSR_IA32_FEATURE_CONTROL
) {
2406 if (!host_initialized
&&
2407 to_vmx(vcpu
)->nested
.msr_ia32_feature_control
2408 & FEATURE_CONTROL_LOCKED
)
2410 to_vmx(vcpu
)->nested
.msr_ia32_feature_control
= data
;
2415 * No need to treat VMX capability MSRs specially: If we don't handle
2416 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2422 * Reads an msr value (of 'msr_index') into 'pdata'.
2423 * Returns 0 on success, non-0 otherwise.
2424 * Assumes vcpu_load() was already called.
2426 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2429 struct shared_msr_entry
*msr
;
2432 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2436 switch (msr_index
) {
2437 #ifdef CONFIG_X86_64
2439 data
= vmcs_readl(GUEST_FS_BASE
);
2442 data
= vmcs_readl(GUEST_GS_BASE
);
2444 case MSR_KERNEL_GS_BASE
:
2445 vmx_load_host_state(to_vmx(vcpu
));
2446 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2450 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2452 data
= guest_read_tsc();
2454 case MSR_IA32_SYSENTER_CS
:
2455 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2457 case MSR_IA32_SYSENTER_EIP
:
2458 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2460 case MSR_IA32_SYSENTER_ESP
:
2461 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2464 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2466 /* Otherwise falls through */
2468 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2470 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2475 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2483 * Writes msr value into into the appropriate "register".
2484 * Returns 0 on success, non-0 otherwise.
2485 * Assumes vcpu_load() was already called.
2487 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2489 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2490 struct shared_msr_entry
*msr
;
2492 u32 msr_index
= msr_info
->index
;
2493 u64 data
= msr_info
->data
;
2495 switch (msr_index
) {
2497 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2499 #ifdef CONFIG_X86_64
2501 vmx_segment_cache_clear(vmx
);
2502 vmcs_writel(GUEST_FS_BASE
, data
);
2505 vmx_segment_cache_clear(vmx
);
2506 vmcs_writel(GUEST_GS_BASE
, data
);
2508 case MSR_KERNEL_GS_BASE
:
2509 vmx_load_host_state(vmx
);
2510 vmx
->msr_guest_kernel_gs_base
= data
;
2513 case MSR_IA32_SYSENTER_CS
:
2514 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2516 case MSR_IA32_SYSENTER_EIP
:
2517 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2519 case MSR_IA32_SYSENTER_ESP
:
2520 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2523 kvm_write_tsc(vcpu
, msr_info
);
2525 case MSR_IA32_CR_PAT
:
2526 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2527 vmcs_write64(GUEST_IA32_PAT
, data
);
2528 vcpu
->arch
.pat
= data
;
2531 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2533 case MSR_IA32_TSC_ADJUST
:
2534 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2537 if (!vmx
->rdtscp_enabled
)
2539 /* Check reserved bit, higher 32 bits should be zero */
2540 if ((data
>> 32) != 0)
2542 /* Otherwise falls through */
2544 if (vmx_set_vmx_msr(vcpu
, msr_info
))
2546 msr
= find_msr_entry(vmx
, msr_index
);
2549 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2551 kvm_set_shared_msr(msr
->index
, msr
->data
,
2557 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2563 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2565 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2568 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2571 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2573 case VCPU_EXREG_PDPTR
:
2575 ept_save_pdptrs(vcpu
);
2582 static __init
int cpu_has_kvm_support(void)
2584 return cpu_has_vmx();
2587 static __init
int vmx_disabled_by_bios(void)
2591 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2592 if (msr
& FEATURE_CONTROL_LOCKED
) {
2593 /* launched w/ TXT and VMX disabled */
2594 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2597 /* launched w/o TXT and VMX only enabled w/ TXT */
2598 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2599 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2600 && !tboot_enabled()) {
2601 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2602 "activate TXT before enabling KVM\n");
2605 /* launched w/o TXT and VMX disabled */
2606 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2607 && !tboot_enabled())
2614 static void kvm_cpu_vmxon(u64 addr
)
2616 asm volatile (ASM_VMX_VMXON_RAX
2617 : : "a"(&addr
), "m"(addr
)
2621 static int hardware_enable(void *garbage
)
2623 int cpu
= raw_smp_processor_id();
2624 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2627 if (read_cr4() & X86_CR4_VMXE
)
2630 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2633 * Now we can enable the vmclear operation in kdump
2634 * since the loaded_vmcss_on_cpu list on this cpu
2635 * has been initialized.
2637 * Though the cpu is not in VMX operation now, there
2638 * is no problem to enable the vmclear operation
2639 * for the loaded_vmcss_on_cpu list is empty!
2641 crash_enable_local_vmclear(cpu
);
2643 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2645 test_bits
= FEATURE_CONTROL_LOCKED
;
2646 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2647 if (tboot_enabled())
2648 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2650 if ((old
& test_bits
) != test_bits
) {
2651 /* enable and lock */
2652 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2654 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2656 if (vmm_exclusive
) {
2657 kvm_cpu_vmxon(phys_addr
);
2661 native_store_gdt(&__get_cpu_var(host_gdt
));
2666 static void vmclear_local_loaded_vmcss(void)
2668 int cpu
= raw_smp_processor_id();
2669 struct loaded_vmcs
*v
, *n
;
2671 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2672 loaded_vmcss_on_cpu_link
)
2673 __loaded_vmcs_clear(v
);
2677 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2680 static void kvm_cpu_vmxoff(void)
2682 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2685 static void hardware_disable(void *garbage
)
2687 if (vmm_exclusive
) {
2688 vmclear_local_loaded_vmcss();
2691 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2694 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2695 u32 msr
, u32
*result
)
2697 u32 vmx_msr_low
, vmx_msr_high
;
2698 u32 ctl
= ctl_min
| ctl_opt
;
2700 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2702 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2703 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2705 /* Ensure minimum (required) set of control bits are supported. */
2713 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2715 u32 vmx_msr_low
, vmx_msr_high
;
2717 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2718 return vmx_msr_high
& ctl
;
2721 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2723 u32 vmx_msr_low
, vmx_msr_high
;
2724 u32 min
, opt
, min2
, opt2
;
2725 u32 _pin_based_exec_control
= 0;
2726 u32 _cpu_based_exec_control
= 0;
2727 u32 _cpu_based_2nd_exec_control
= 0;
2728 u32 _vmexit_control
= 0;
2729 u32 _vmentry_control
= 0;
2731 min
= CPU_BASED_HLT_EXITING
|
2732 #ifdef CONFIG_X86_64
2733 CPU_BASED_CR8_LOAD_EXITING
|
2734 CPU_BASED_CR8_STORE_EXITING
|
2736 CPU_BASED_CR3_LOAD_EXITING
|
2737 CPU_BASED_CR3_STORE_EXITING
|
2738 CPU_BASED_USE_IO_BITMAPS
|
2739 CPU_BASED_MOV_DR_EXITING
|
2740 CPU_BASED_USE_TSC_OFFSETING
|
2741 CPU_BASED_MWAIT_EXITING
|
2742 CPU_BASED_MONITOR_EXITING
|
2743 CPU_BASED_INVLPG_EXITING
|
2744 CPU_BASED_RDPMC_EXITING
;
2746 opt
= CPU_BASED_TPR_SHADOW
|
2747 CPU_BASED_USE_MSR_BITMAPS
|
2748 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2749 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2750 &_cpu_based_exec_control
) < 0)
2752 #ifdef CONFIG_X86_64
2753 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2754 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2755 ~CPU_BASED_CR8_STORE_EXITING
;
2757 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2759 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2760 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2761 SECONDARY_EXEC_WBINVD_EXITING
|
2762 SECONDARY_EXEC_ENABLE_VPID
|
2763 SECONDARY_EXEC_ENABLE_EPT
|
2764 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2765 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2766 SECONDARY_EXEC_RDTSCP
|
2767 SECONDARY_EXEC_ENABLE_INVPCID
|
2768 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2769 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2770 SECONDARY_EXEC_SHADOW_VMCS
;
2771 if (adjust_vmx_controls(min2
, opt2
,
2772 MSR_IA32_VMX_PROCBASED_CTLS2
,
2773 &_cpu_based_2nd_exec_control
) < 0)
2776 #ifndef CONFIG_X86_64
2777 if (!(_cpu_based_2nd_exec_control
&
2778 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2779 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2782 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2783 _cpu_based_2nd_exec_control
&= ~(
2784 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2785 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2786 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2788 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2789 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2791 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2792 CPU_BASED_CR3_STORE_EXITING
|
2793 CPU_BASED_INVLPG_EXITING
);
2794 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2795 vmx_capability
.ept
, vmx_capability
.vpid
);
2799 #ifdef CONFIG_X86_64
2800 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2802 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2803 VM_EXIT_ACK_INTR_ON_EXIT
;
2804 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2805 &_vmexit_control
) < 0)
2808 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2809 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2810 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2811 &_pin_based_exec_control
) < 0)
2814 if (!(_cpu_based_2nd_exec_control
&
2815 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2816 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2817 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2820 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2821 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2822 &_vmentry_control
) < 0)
2825 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2827 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2828 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2831 #ifdef CONFIG_X86_64
2832 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2833 if (vmx_msr_high
& (1u<<16))
2837 /* Require Write-Back (WB) memory type for VMCS accesses. */
2838 if (((vmx_msr_high
>> 18) & 15) != 6)
2841 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2842 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2843 vmcs_conf
->revision_id
= vmx_msr_low
;
2845 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2846 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2847 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2848 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2849 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2851 cpu_has_load_ia32_efer
=
2852 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2853 VM_ENTRY_LOAD_IA32_EFER
)
2854 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2855 VM_EXIT_LOAD_IA32_EFER
);
2857 cpu_has_load_perf_global_ctrl
=
2858 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2859 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2860 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2861 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2864 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2865 * but due to arrata below it can't be used. Workaround is to use
2866 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2868 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2873 * BC86,AAY89,BD102 (model 44)
2877 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2878 switch (boot_cpu_data
.x86_model
) {
2884 cpu_has_load_perf_global_ctrl
= false;
2885 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2886 "does not work properly. Using workaround\n");
2896 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2898 int node
= cpu_to_node(cpu
);
2902 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2905 vmcs
= page_address(pages
);
2906 memset(vmcs
, 0, vmcs_config
.size
);
2907 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2911 static struct vmcs
*alloc_vmcs(void)
2913 return alloc_vmcs_cpu(raw_smp_processor_id());
2916 static void free_vmcs(struct vmcs
*vmcs
)
2918 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2922 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2924 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2926 if (!loaded_vmcs
->vmcs
)
2928 loaded_vmcs_clear(loaded_vmcs
);
2929 free_vmcs(loaded_vmcs
->vmcs
);
2930 loaded_vmcs
->vmcs
= NULL
;
2933 static void free_kvm_area(void)
2937 for_each_possible_cpu(cpu
) {
2938 free_vmcs(per_cpu(vmxarea
, cpu
));
2939 per_cpu(vmxarea
, cpu
) = NULL
;
2943 static __init
int alloc_kvm_area(void)
2947 for_each_possible_cpu(cpu
) {
2950 vmcs
= alloc_vmcs_cpu(cpu
);
2956 per_cpu(vmxarea
, cpu
) = vmcs
;
2961 static __init
int hardware_setup(void)
2963 if (setup_vmcs_config(&vmcs_config
) < 0)
2966 if (boot_cpu_has(X86_FEATURE_NX
))
2967 kvm_enable_efer_bits(EFER_NX
);
2969 if (!cpu_has_vmx_vpid())
2971 if (!cpu_has_vmx_shadow_vmcs())
2972 enable_shadow_vmcs
= 0;
2974 if (!cpu_has_vmx_ept() ||
2975 !cpu_has_vmx_ept_4levels()) {
2977 enable_unrestricted_guest
= 0;
2978 enable_ept_ad_bits
= 0;
2981 if (!cpu_has_vmx_ept_ad_bits())
2982 enable_ept_ad_bits
= 0;
2984 if (!cpu_has_vmx_unrestricted_guest())
2985 enable_unrestricted_guest
= 0;
2987 if (!cpu_has_vmx_flexpriority())
2988 flexpriority_enabled
= 0;
2990 if (!cpu_has_vmx_tpr_shadow())
2991 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2993 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2994 kvm_disable_largepages();
2996 if (!cpu_has_vmx_ple())
2999 if (!cpu_has_vmx_apicv())
3003 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3005 kvm_x86_ops
->hwapic_irr_update
= NULL
;
3006 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
3007 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
3011 nested_vmx_setup_ctls_msrs();
3013 return alloc_kvm_area();
3016 static __exit
void hardware_unsetup(void)
3021 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3023 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3026 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3027 struct kvm_segment
*save
)
3029 if (!emulate_invalid_guest_state
) {
3031 * CS and SS RPL should be equal during guest entry according
3032 * to VMX spec, but in reality it is not always so. Since vcpu
3033 * is in the middle of the transition from real mode to
3034 * protected mode it is safe to assume that RPL 0 is a good
3037 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3038 save
->selector
&= ~SELECTOR_RPL_MASK
;
3039 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3042 vmx_set_segment(vcpu
, save
, seg
);
3045 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3047 unsigned long flags
;
3048 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3051 * Update real mode segment cache. It may be not up-to-date if sement
3052 * register was written while vcpu was in a guest mode.
3054 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3055 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3056 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3057 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3058 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3059 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3061 vmx
->rmode
.vm86_active
= 0;
3063 vmx_segment_cache_clear(vmx
);
3065 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3067 flags
= vmcs_readl(GUEST_RFLAGS
);
3068 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3069 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3070 vmcs_writel(GUEST_RFLAGS
, flags
);
3072 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3073 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3075 update_exception_bitmap(vcpu
);
3077 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3078 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3079 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3080 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3081 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3082 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3084 /* CPL is always 0 when CPU enters protected mode */
3085 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3089 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3091 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3092 struct kvm_segment var
= *save
;
3095 if (seg
== VCPU_SREG_CS
)
3098 if (!emulate_invalid_guest_state
) {
3099 var
.selector
= var
.base
>> 4;
3100 var
.base
= var
.base
& 0xffff0;
3110 if (save
->base
& 0xf)
3111 printk_once(KERN_WARNING
"kvm: segment base is not "
3112 "paragraph aligned when entering "
3113 "protected mode (seg=%d)", seg
);
3116 vmcs_write16(sf
->selector
, var
.selector
);
3117 vmcs_write32(sf
->base
, var
.base
);
3118 vmcs_write32(sf
->limit
, var
.limit
);
3119 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3122 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3124 unsigned long flags
;
3125 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3127 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3128 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3129 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3130 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3131 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3132 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3133 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3135 vmx
->rmode
.vm86_active
= 1;
3138 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3139 * vcpu. Warn the user that an update is overdue.
3141 if (!vcpu
->kvm
->arch
.tss_addr
)
3142 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3143 "called before entering vcpu\n");
3145 vmx_segment_cache_clear(vmx
);
3147 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3148 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3149 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3151 flags
= vmcs_readl(GUEST_RFLAGS
);
3152 vmx
->rmode
.save_rflags
= flags
;
3154 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3156 vmcs_writel(GUEST_RFLAGS
, flags
);
3157 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3158 update_exception_bitmap(vcpu
);
3160 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3161 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3162 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3163 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3164 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3165 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3167 kvm_mmu_reset_context(vcpu
);
3170 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3172 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3173 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3179 * Force kernel_gs_base reloading before EFER changes, as control
3180 * of this msr depends on is_long_mode().
3182 vmx_load_host_state(to_vmx(vcpu
));
3183 vcpu
->arch
.efer
= efer
;
3184 if (efer
& EFER_LMA
) {
3185 vmcs_write32(VM_ENTRY_CONTROLS
,
3186 vmcs_read32(VM_ENTRY_CONTROLS
) |
3187 VM_ENTRY_IA32E_MODE
);
3190 vmcs_write32(VM_ENTRY_CONTROLS
,
3191 vmcs_read32(VM_ENTRY_CONTROLS
) &
3192 ~VM_ENTRY_IA32E_MODE
);
3194 msr
->data
= efer
& ~EFER_LME
;
3199 #ifdef CONFIG_X86_64
3201 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3205 vmx_segment_cache_clear(to_vmx(vcpu
));
3207 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3208 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3209 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3211 vmcs_write32(GUEST_TR_AR_BYTES
,
3212 (guest_tr_ar
& ~AR_TYPE_MASK
)
3213 | AR_TYPE_BUSY_64_TSS
);
3215 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3218 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3220 vmcs_write32(VM_ENTRY_CONTROLS
,
3221 vmcs_read32(VM_ENTRY_CONTROLS
)
3222 & ~VM_ENTRY_IA32E_MODE
);
3223 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3228 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3230 vpid_sync_context(to_vmx(vcpu
));
3232 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3234 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3238 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3240 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3242 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3243 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3246 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3248 if (enable_ept
&& is_paging(vcpu
))
3249 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3250 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3253 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3255 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3257 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3258 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3261 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3263 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3265 if (!test_bit(VCPU_EXREG_PDPTR
,
3266 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3269 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3270 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3271 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3272 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3273 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3277 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3279 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3281 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3282 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3283 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3284 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3285 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3288 __set_bit(VCPU_EXREG_PDPTR
,
3289 (unsigned long *)&vcpu
->arch
.regs_avail
);
3290 __set_bit(VCPU_EXREG_PDPTR
,
3291 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3294 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3296 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3298 struct kvm_vcpu
*vcpu
)
3300 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3301 vmx_decache_cr3(vcpu
);
3302 if (!(cr0
& X86_CR0_PG
)) {
3303 /* From paging/starting to nonpaging */
3304 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3305 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3306 (CPU_BASED_CR3_LOAD_EXITING
|
3307 CPU_BASED_CR3_STORE_EXITING
));
3308 vcpu
->arch
.cr0
= cr0
;
3309 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3310 } else if (!is_paging(vcpu
)) {
3311 /* From nonpaging to paging */
3312 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3313 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3314 ~(CPU_BASED_CR3_LOAD_EXITING
|
3315 CPU_BASED_CR3_STORE_EXITING
));
3316 vcpu
->arch
.cr0
= cr0
;
3317 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3320 if (!(cr0
& X86_CR0_WP
))
3321 *hw_cr0
&= ~X86_CR0_WP
;
3324 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3326 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3327 unsigned long hw_cr0
;
3329 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3330 if (enable_unrestricted_guest
)
3331 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3333 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3335 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3338 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3342 #ifdef CONFIG_X86_64
3343 if (vcpu
->arch
.efer
& EFER_LME
) {
3344 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3346 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3352 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3354 if (!vcpu
->fpu_active
)
3355 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3357 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3358 vmcs_writel(GUEST_CR0
, hw_cr0
);
3359 vcpu
->arch
.cr0
= cr0
;
3361 /* depends on vcpu->arch.cr0 to be set to a new value */
3362 vmx
->emulation_required
= emulation_required(vcpu
);
3365 static u64
construct_eptp(unsigned long root_hpa
)
3369 /* TODO write the value reading from MSR */
3370 eptp
= VMX_EPT_DEFAULT_MT
|
3371 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3372 if (enable_ept_ad_bits
)
3373 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3374 eptp
|= (root_hpa
& PAGE_MASK
);
3379 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3381 unsigned long guest_cr3
;
3386 eptp
= construct_eptp(cr3
);
3387 vmcs_write64(EPT_POINTER
, eptp
);
3388 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3389 guest_cr3
= kvm_read_cr3(vcpu
);
3391 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3392 ept_load_pdptrs(vcpu
);
3395 vmx_flush_tlb(vcpu
);
3396 vmcs_writel(GUEST_CR3
, guest_cr3
);
3399 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3401 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3402 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3404 if (cr4
& X86_CR4_VMXE
) {
3406 * To use VMXON (and later other VMX instructions), a guest
3407 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3408 * So basically the check on whether to allow nested VMX
3411 if (!nested_vmx_allowed(vcpu
))
3414 if (to_vmx(vcpu
)->nested
.vmxon
&&
3415 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3418 vcpu
->arch
.cr4
= cr4
;
3420 if (!is_paging(vcpu
)) {
3421 hw_cr4
&= ~X86_CR4_PAE
;
3422 hw_cr4
|= X86_CR4_PSE
;
3424 * SMEP is disabled if CPU is in non-paging mode in
3425 * hardware. However KVM always uses paging mode to
3426 * emulate guest non-paging mode with TDP.
3427 * To emulate this behavior, SMEP needs to be manually
3428 * disabled when guest switches to non-paging mode.
3430 hw_cr4
&= ~X86_CR4_SMEP
;
3431 } else if (!(cr4
& X86_CR4_PAE
)) {
3432 hw_cr4
&= ~X86_CR4_PAE
;
3436 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3437 vmcs_writel(GUEST_CR4
, hw_cr4
);
3441 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3442 struct kvm_segment
*var
, int seg
)
3444 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3447 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3448 *var
= vmx
->rmode
.segs
[seg
];
3449 if (seg
== VCPU_SREG_TR
3450 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3452 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3453 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3456 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3457 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3458 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3459 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3460 var
->unusable
= (ar
>> 16) & 1;
3461 var
->type
= ar
& 15;
3462 var
->s
= (ar
>> 4) & 1;
3463 var
->dpl
= (ar
>> 5) & 3;
3465 * Some userspaces do not preserve unusable property. Since usable
3466 * segment has to be present according to VMX spec we can use present
3467 * property to amend userspace bug by making unusable segment always
3468 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3469 * segment as unusable.
3471 var
->present
= !var
->unusable
;
3472 var
->avl
= (ar
>> 12) & 1;
3473 var
->l
= (ar
>> 13) & 1;
3474 var
->db
= (ar
>> 14) & 1;
3475 var
->g
= (ar
>> 15) & 1;
3478 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3480 struct kvm_segment s
;
3482 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3483 vmx_get_segment(vcpu
, &s
, seg
);
3486 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3489 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3491 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3493 if (!is_protmode(vcpu
))
3496 if (!is_long_mode(vcpu
)
3497 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3500 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3501 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3502 vmx
->cpl
= vmx_read_guest_seg_selector(vmx
, VCPU_SREG_CS
) & 3;
3509 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3513 if (var
->unusable
|| !var
->present
)
3516 ar
= var
->type
& 15;
3517 ar
|= (var
->s
& 1) << 4;
3518 ar
|= (var
->dpl
& 3) << 5;
3519 ar
|= (var
->present
& 1) << 7;
3520 ar
|= (var
->avl
& 1) << 12;
3521 ar
|= (var
->l
& 1) << 13;
3522 ar
|= (var
->db
& 1) << 14;
3523 ar
|= (var
->g
& 1) << 15;
3529 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3530 struct kvm_segment
*var
, int seg
)
3532 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3533 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3535 vmx_segment_cache_clear(vmx
);
3536 if (seg
== VCPU_SREG_CS
)
3537 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3539 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3540 vmx
->rmode
.segs
[seg
] = *var
;
3541 if (seg
== VCPU_SREG_TR
)
3542 vmcs_write16(sf
->selector
, var
->selector
);
3544 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3548 vmcs_writel(sf
->base
, var
->base
);
3549 vmcs_write32(sf
->limit
, var
->limit
);
3550 vmcs_write16(sf
->selector
, var
->selector
);
3553 * Fix the "Accessed" bit in AR field of segment registers for older
3555 * IA32 arch specifies that at the time of processor reset the
3556 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3557 * is setting it to 0 in the userland code. This causes invalid guest
3558 * state vmexit when "unrestricted guest" mode is turned on.
3559 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3560 * tree. Newer qemu binaries with that qemu fix would not need this
3563 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3564 var
->type
|= 0x1; /* Accessed */
3566 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3569 vmx
->emulation_required
|= emulation_required(vcpu
);
3572 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3574 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3576 *db
= (ar
>> 14) & 1;
3577 *l
= (ar
>> 13) & 1;
3580 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3582 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3583 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3586 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3588 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3589 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3592 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3594 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3595 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3598 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3600 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3601 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3604 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3606 struct kvm_segment var
;
3609 vmx_get_segment(vcpu
, &var
, seg
);
3611 if (seg
== VCPU_SREG_CS
)
3613 ar
= vmx_segment_access_rights(&var
);
3615 if (var
.base
!= (var
.selector
<< 4))
3617 if (var
.limit
!= 0xffff)
3625 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3627 struct kvm_segment cs
;
3628 unsigned int cs_rpl
;
3630 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3631 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3635 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3639 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3640 if (cs
.dpl
> cs_rpl
)
3643 if (cs
.dpl
!= cs_rpl
)
3649 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3653 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3655 struct kvm_segment ss
;
3656 unsigned int ss_rpl
;
3658 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3659 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3663 if (ss
.type
!= 3 && ss
.type
!= 7)
3667 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3675 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3677 struct kvm_segment var
;
3680 vmx_get_segment(vcpu
, &var
, seg
);
3681 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3689 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3690 if (var
.dpl
< rpl
) /* DPL < RPL */
3694 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3700 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3702 struct kvm_segment tr
;
3704 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3708 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3710 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3718 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3720 struct kvm_segment ldtr
;
3722 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3726 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3736 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3738 struct kvm_segment cs
, ss
;
3740 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3741 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3743 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3744 (ss
.selector
& SELECTOR_RPL_MASK
));
3748 * Check if guest state is valid. Returns true if valid, false if
3750 * We assume that registers are always usable
3752 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3754 if (enable_unrestricted_guest
)
3757 /* real mode guest state checks */
3758 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3759 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3761 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3763 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3765 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3767 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3769 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3772 /* protected mode guest state checks */
3773 if (!cs_ss_rpl_check(vcpu
))
3775 if (!code_segment_valid(vcpu
))
3777 if (!stack_segment_valid(vcpu
))
3779 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3781 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3783 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3785 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3787 if (!tr_valid(vcpu
))
3789 if (!ldtr_valid(vcpu
))
3793 * - Add checks on RIP
3794 * - Add checks on RFLAGS
3800 static int init_rmode_tss(struct kvm
*kvm
)
3804 int r
, idx
, ret
= 0;
3806 idx
= srcu_read_lock(&kvm
->srcu
);
3807 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3808 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3811 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3812 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3813 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3816 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3819 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3823 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3824 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3831 srcu_read_unlock(&kvm
->srcu
, idx
);
3835 static int init_rmode_identity_map(struct kvm
*kvm
)
3838 pfn_t identity_map_pfn
;
3843 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3844 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3845 "haven't been allocated!\n");
3848 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3851 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3852 idx
= srcu_read_lock(&kvm
->srcu
);
3853 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3856 /* Set up identity-mapping pagetable for EPT in real mode */
3857 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3858 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3859 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3860 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3861 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3865 kvm
->arch
.ept_identity_pagetable_done
= true;
3868 srcu_read_unlock(&kvm
->srcu
, idx
);
3872 static void seg_setup(int seg
)
3874 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3877 vmcs_write16(sf
->selector
, 0);
3878 vmcs_writel(sf
->base
, 0);
3879 vmcs_write32(sf
->limit
, 0xffff);
3881 if (seg
== VCPU_SREG_CS
)
3882 ar
|= 0x08; /* code segment */
3884 vmcs_write32(sf
->ar_bytes
, ar
);
3887 static int alloc_apic_access_page(struct kvm
*kvm
)
3890 struct kvm_userspace_memory_region kvm_userspace_mem
;
3893 mutex_lock(&kvm
->slots_lock
);
3894 if (kvm
->arch
.apic_access_page
)
3896 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3897 kvm_userspace_mem
.flags
= 0;
3898 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3899 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3900 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3904 page
= gfn_to_page(kvm
, 0xfee00);
3905 if (is_error_page(page
)) {
3910 kvm
->arch
.apic_access_page
= page
;
3912 mutex_unlock(&kvm
->slots_lock
);
3916 static int alloc_identity_pagetable(struct kvm
*kvm
)
3919 struct kvm_userspace_memory_region kvm_userspace_mem
;
3922 mutex_lock(&kvm
->slots_lock
);
3923 if (kvm
->arch
.ept_identity_pagetable
)
3925 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3926 kvm_userspace_mem
.flags
= 0;
3927 kvm_userspace_mem
.guest_phys_addr
=
3928 kvm
->arch
.ept_identity_map_addr
;
3929 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3930 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3934 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3935 if (is_error_page(page
)) {
3940 kvm
->arch
.ept_identity_pagetable
= page
;
3942 mutex_unlock(&kvm
->slots_lock
);
3946 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3953 spin_lock(&vmx_vpid_lock
);
3954 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3955 if (vpid
< VMX_NR_VPIDS
) {
3957 __set_bit(vpid
, vmx_vpid_bitmap
);
3959 spin_unlock(&vmx_vpid_lock
);
3962 static void free_vpid(struct vcpu_vmx
*vmx
)
3966 spin_lock(&vmx_vpid_lock
);
3968 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3969 spin_unlock(&vmx_vpid_lock
);
3972 #define MSR_TYPE_R 1
3973 #define MSR_TYPE_W 2
3974 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
3977 int f
= sizeof(unsigned long);
3979 if (!cpu_has_vmx_msr_bitmap())
3983 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3984 * have the write-low and read-high bitmap offsets the wrong way round.
3985 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3987 if (msr
<= 0x1fff) {
3988 if (type
& MSR_TYPE_R
)
3990 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
3992 if (type
& MSR_TYPE_W
)
3994 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
3996 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3998 if (type
& MSR_TYPE_R
)
4000 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4002 if (type
& MSR_TYPE_W
)
4004 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4009 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4012 int f
= sizeof(unsigned long);
4014 if (!cpu_has_vmx_msr_bitmap())
4018 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4019 * have the write-low and read-high bitmap offsets the wrong way round.
4020 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4022 if (msr
<= 0x1fff) {
4023 if (type
& MSR_TYPE_R
)
4025 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4027 if (type
& MSR_TYPE_W
)
4029 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4031 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4033 if (type
& MSR_TYPE_R
)
4035 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4037 if (type
& MSR_TYPE_W
)
4039 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4044 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4047 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4048 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4049 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4050 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4053 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4055 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4057 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4061 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4063 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4065 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4069 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4071 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4073 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4077 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4079 return enable_apicv
&& irqchip_in_kernel(kvm
);
4083 * Send interrupt to vcpu via posted interrupt way.
4084 * 1. If target vcpu is running(non-root mode), send posted interrupt
4085 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4086 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4087 * interrupt from PIR in next vmentry.
4089 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4091 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4094 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4097 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4098 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4100 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4101 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4102 POSTED_INTR_VECTOR
);
4105 kvm_vcpu_kick(vcpu
);
4108 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4110 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4112 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4115 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4118 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4124 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4125 * will not change in the lifetime of the guest.
4126 * Note that host-state that does change is set elsewhere. E.g., host-state
4127 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4129 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4135 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4136 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
4137 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4139 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4140 #ifdef CONFIG_X86_64
4142 * Load null selectors, so we can avoid reloading them in
4143 * __vmx_load_host_state(), in case userspace uses the null selectors
4144 * too (the expected case).
4146 vmcs_write16(HOST_DS_SELECTOR
, 0);
4147 vmcs_write16(HOST_ES_SELECTOR
, 0);
4149 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4150 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4152 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4153 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4155 native_store_idt(&dt
);
4156 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4157 vmx
->host_idt_base
= dt
.address
;
4159 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4161 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4162 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4163 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4164 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4166 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4167 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4168 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4172 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4174 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4176 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4177 if (is_guest_mode(&vmx
->vcpu
))
4178 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4179 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4180 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4183 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4185 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4187 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4188 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4189 return pin_based_exec_ctrl
;
4192 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4194 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4195 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4196 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4197 #ifdef CONFIG_X86_64
4198 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4199 CPU_BASED_CR8_LOAD_EXITING
;
4203 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4204 CPU_BASED_CR3_LOAD_EXITING
|
4205 CPU_BASED_INVLPG_EXITING
;
4206 return exec_control
;
4209 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4211 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4212 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4213 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4215 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4217 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4218 enable_unrestricted_guest
= 0;
4219 /* Enable INVPCID for non-ept guests may cause performance regression. */
4220 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4222 if (!enable_unrestricted_guest
)
4223 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4225 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4226 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4227 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4228 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4229 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4230 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4232 We can NOT enable shadow_vmcs here because we don't have yet
4235 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4236 return exec_control
;
4239 static void ept_set_mmio_spte_mask(void)
4242 * EPT Misconfigurations can be generated if the value of bits 2:0
4243 * of an EPT paging-structure entry is 110b (write/execute).
4244 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4247 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4251 * Sets up the vmcs for emulated real mode.
4253 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4255 #ifdef CONFIG_X86_64
4261 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4262 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4264 if (enable_shadow_vmcs
) {
4265 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4266 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4268 if (cpu_has_vmx_msr_bitmap())
4269 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4271 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4274 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4276 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4278 if (cpu_has_secondary_exec_ctrls()) {
4279 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4280 vmx_secondary_exec_control(vmx
));
4283 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4284 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4285 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4286 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4287 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4289 vmcs_write16(GUEST_INTR_STATUS
, 0);
4291 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4292 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4296 vmcs_write32(PLE_GAP
, ple_gap
);
4297 vmcs_write32(PLE_WINDOW
, ple_window
);
4300 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4301 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4302 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4304 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4305 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4306 vmx_set_constant_host_state(vmx
);
4307 #ifdef CONFIG_X86_64
4308 rdmsrl(MSR_FS_BASE
, a
);
4309 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4310 rdmsrl(MSR_GS_BASE
, a
);
4311 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4313 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4314 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4317 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4318 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4319 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4320 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4321 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4323 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4324 u32 msr_low
, msr_high
;
4326 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4327 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4328 /* Write the default value follow host pat */
4329 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4330 /* Keep arch.pat sync with GUEST_IA32_PAT */
4331 vmx
->vcpu
.arch
.pat
= host_pat
;
4334 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
4335 u32 index
= vmx_msr_index
[i
];
4336 u32 data_low
, data_high
;
4339 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4341 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4343 vmx
->guest_msrs
[j
].index
= i
;
4344 vmx
->guest_msrs
[j
].data
= 0;
4345 vmx
->guest_msrs
[j
].mask
= -1ull;
4349 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
4351 /* 22.2.1, 20.8.1 */
4352 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
4354 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4355 set_cr4_guest_host_mask(vmx
);
4360 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4362 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4365 vmx
->rmode
.vm86_active
= 0;
4367 vmx
->soft_vnmi_blocked
= 0;
4369 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4370 kvm_set_cr8(&vmx
->vcpu
, 0);
4371 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4372 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4373 msr
|= MSR_IA32_APICBASE_BSP
;
4374 kvm_set_apic_base(&vmx
->vcpu
, msr
);
4376 vmx_segment_cache_clear(vmx
);
4378 seg_setup(VCPU_SREG_CS
);
4379 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4380 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4382 seg_setup(VCPU_SREG_DS
);
4383 seg_setup(VCPU_SREG_ES
);
4384 seg_setup(VCPU_SREG_FS
);
4385 seg_setup(VCPU_SREG_GS
);
4386 seg_setup(VCPU_SREG_SS
);
4388 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4389 vmcs_writel(GUEST_TR_BASE
, 0);
4390 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4391 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4393 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4394 vmcs_writel(GUEST_LDTR_BASE
, 0);
4395 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4396 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4398 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4399 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4400 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4402 vmcs_writel(GUEST_RFLAGS
, 0x02);
4403 kvm_rip_write(vcpu
, 0xfff0);
4405 vmcs_writel(GUEST_GDTR_BASE
, 0);
4406 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4408 vmcs_writel(GUEST_IDTR_BASE
, 0);
4409 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4411 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4412 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4413 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4415 /* Special registers */
4416 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4420 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4422 if (cpu_has_vmx_tpr_shadow()) {
4423 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4424 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4425 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4426 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4427 vmcs_write32(TPR_THRESHOLD
, 0);
4430 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4431 vmcs_write64(APIC_ACCESS_ADDR
,
4432 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4434 if (vmx_vm_has_apicv(vcpu
->kvm
))
4435 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4438 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4440 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4441 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4442 vmx_set_cr4(&vmx
->vcpu
, 0);
4443 vmx_set_efer(&vmx
->vcpu
, 0);
4444 vmx_fpu_activate(&vmx
->vcpu
);
4445 update_exception_bitmap(&vmx
->vcpu
);
4447 vpid_sync_context(vmx
);
4451 * In nested virtualization, check if L1 asked to exit on external interrupts.
4452 * For most existing hypervisors, this will always return true.
4454 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4456 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4457 PIN_BASED_EXT_INTR_MASK
;
4460 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4462 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4463 PIN_BASED_NMI_EXITING
;
4466 static int enable_irq_window(struct kvm_vcpu
*vcpu
)
4468 u32 cpu_based_vm_exec_control
;
4470 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
4472 * We get here if vmx_interrupt_allowed() said we can't
4473 * inject to L1 now because L2 must run. The caller will have
4474 * to make L2 exit right after entry, so we can inject to L1
4479 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4480 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4481 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4485 static int enable_nmi_window(struct kvm_vcpu
*vcpu
)
4487 u32 cpu_based_vm_exec_control
;
4489 if (!cpu_has_virtual_nmis())
4490 return enable_irq_window(vcpu
);
4492 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
)
4493 return enable_irq_window(vcpu
);
4495 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4496 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4497 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4501 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4503 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4505 int irq
= vcpu
->arch
.interrupt
.nr
;
4507 trace_kvm_inj_virq(irq
);
4509 ++vcpu
->stat
.irq_injections
;
4510 if (vmx
->rmode
.vm86_active
) {
4512 if (vcpu
->arch
.interrupt
.soft
)
4513 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4514 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4515 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4518 intr
= irq
| INTR_INFO_VALID_MASK
;
4519 if (vcpu
->arch
.interrupt
.soft
) {
4520 intr
|= INTR_TYPE_SOFT_INTR
;
4521 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4522 vmx
->vcpu
.arch
.event_exit_inst_len
);
4524 intr
|= INTR_TYPE_EXT_INTR
;
4525 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4528 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4530 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4532 if (is_guest_mode(vcpu
))
4535 if (!cpu_has_virtual_nmis()) {
4537 * Tracking the NMI-blocked state in software is built upon
4538 * finding the next open IRQ window. This, in turn, depends on
4539 * well-behaving guests: They have to keep IRQs disabled at
4540 * least as long as the NMI handler runs. Otherwise we may
4541 * cause NMI nesting, maybe breaking the guest. But as this is
4542 * highly unlikely, we can live with the residual risk.
4544 vmx
->soft_vnmi_blocked
= 1;
4545 vmx
->vnmi_blocked_time
= 0;
4548 ++vcpu
->stat
.nmi_injections
;
4549 vmx
->nmi_known_unmasked
= false;
4550 if (vmx
->rmode
.vm86_active
) {
4551 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4552 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4555 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4556 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4559 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4561 if (!cpu_has_virtual_nmis())
4562 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4563 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4565 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4568 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4570 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4572 if (!cpu_has_virtual_nmis()) {
4573 if (vmx
->soft_vnmi_blocked
!= masked
) {
4574 vmx
->soft_vnmi_blocked
= masked
;
4575 vmx
->vnmi_blocked_time
= 0;
4578 vmx
->nmi_known_unmasked
= !masked
;
4580 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4581 GUEST_INTR_STATE_NMI
);
4583 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4584 GUEST_INTR_STATE_NMI
);
4588 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4590 if (is_guest_mode(vcpu
)) {
4591 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4593 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4595 if (nested_exit_on_nmi(vcpu
)) {
4596 nested_vmx_vmexit(vcpu
);
4597 vmcs12
->vm_exit_reason
= EXIT_REASON_EXCEPTION_NMI
;
4598 vmcs12
->vm_exit_intr_info
= NMI_VECTOR
|
4599 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
;
4601 * The NMI-triggered VM exit counts as injection:
4602 * clear this one and block further NMIs.
4604 vcpu
->arch
.nmi_pending
= 0;
4605 vmx_set_nmi_mask(vcpu
, true);
4610 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4613 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4614 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4615 | GUEST_INTR_STATE_NMI
));
4618 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4620 if (is_guest_mode(vcpu
)) {
4621 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4623 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4625 if (nested_exit_on_intr(vcpu
)) {
4626 nested_vmx_vmexit(vcpu
);
4627 vmcs12
->vm_exit_reason
=
4628 EXIT_REASON_EXTERNAL_INTERRUPT
;
4629 vmcs12
->vm_exit_intr_info
= 0;
4631 * fall through to normal code, but now in L1, not L2
4636 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4637 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4638 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4641 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4644 struct kvm_userspace_memory_region tss_mem
= {
4645 .slot
= TSS_PRIVATE_MEMSLOT
,
4646 .guest_phys_addr
= addr
,
4647 .memory_size
= PAGE_SIZE
* 3,
4651 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4654 kvm
->arch
.tss_addr
= addr
;
4655 if (!init_rmode_tss(kvm
))
4661 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4666 * Update instruction length as we may reinject the exception
4667 * from user space while in guest debugging mode.
4669 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4670 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4671 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4675 if (vcpu
->guest_debug
&
4676 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4693 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4694 int vec
, u32 err_code
)
4697 * Instruction with address size override prefix opcode 0x67
4698 * Cause the #SS fault with 0 error code in VM86 mode.
4700 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4701 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4702 if (vcpu
->arch
.halt_request
) {
4703 vcpu
->arch
.halt_request
= 0;
4704 return kvm_emulate_halt(vcpu
);
4712 * Forward all other exceptions that are valid in real mode.
4713 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4714 * the required debugging infrastructure rework.
4716 kvm_queue_exception(vcpu
, vec
);
4721 * Trigger machine check on the host. We assume all the MSRs are already set up
4722 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4723 * We pass a fake environment to the machine check handler because we want
4724 * the guest to be always treated like user space, no matter what context
4725 * it used internally.
4727 static void kvm_machine_check(void)
4729 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4730 struct pt_regs regs
= {
4731 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4732 .flags
= X86_EFLAGS_IF
,
4735 do_machine_check(®s
, 0);
4739 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4741 /* already handled by vcpu_run */
4745 static int handle_exception(struct kvm_vcpu
*vcpu
)
4747 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4748 struct kvm_run
*kvm_run
= vcpu
->run
;
4749 u32 intr_info
, ex_no
, error_code
;
4750 unsigned long cr2
, rip
, dr6
;
4752 enum emulation_result er
;
4754 vect_info
= vmx
->idt_vectoring_info
;
4755 intr_info
= vmx
->exit_intr_info
;
4757 if (is_machine_check(intr_info
))
4758 return handle_machine_check(vcpu
);
4760 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4761 return 1; /* already handled by vmx_vcpu_run() */
4763 if (is_no_device(intr_info
)) {
4764 vmx_fpu_activate(vcpu
);
4768 if (is_invalid_opcode(intr_info
)) {
4769 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4770 if (er
!= EMULATE_DONE
)
4771 kvm_queue_exception(vcpu
, UD_VECTOR
);
4776 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4777 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4780 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4781 * MMIO, it is better to report an internal error.
4782 * See the comments in vmx_handle_exit.
4784 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4785 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4786 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4787 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4788 vcpu
->run
->internal
.ndata
= 2;
4789 vcpu
->run
->internal
.data
[0] = vect_info
;
4790 vcpu
->run
->internal
.data
[1] = intr_info
;
4794 if (is_page_fault(intr_info
)) {
4795 /* EPT won't cause page fault directly */
4797 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4798 trace_kvm_page_fault(cr2
, error_code
);
4800 if (kvm_event_needs_reinjection(vcpu
))
4801 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4802 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4805 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4807 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4808 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4812 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4813 if (!(vcpu
->guest_debug
&
4814 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4815 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4816 kvm_queue_exception(vcpu
, DB_VECTOR
);
4819 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4820 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4824 * Update instruction length as we may reinject #BP from
4825 * user space while in guest debugging mode. Reading it for
4826 * #DB as well causes no harm, it is not used in that case.
4828 vmx
->vcpu
.arch
.event_exit_inst_len
=
4829 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4830 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4831 rip
= kvm_rip_read(vcpu
);
4832 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4833 kvm_run
->debug
.arch
.exception
= ex_no
;
4836 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4837 kvm_run
->ex
.exception
= ex_no
;
4838 kvm_run
->ex
.error_code
= error_code
;
4844 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4846 ++vcpu
->stat
.irq_exits
;
4850 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4852 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4856 static int handle_io(struct kvm_vcpu
*vcpu
)
4858 unsigned long exit_qualification
;
4859 int size
, in
, string
;
4862 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4863 string
= (exit_qualification
& 16) != 0;
4864 in
= (exit_qualification
& 8) != 0;
4866 ++vcpu
->stat
.io_exits
;
4869 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4871 port
= exit_qualification
>> 16;
4872 size
= (exit_qualification
& 7) + 1;
4873 skip_emulated_instruction(vcpu
);
4875 return kvm_fast_pio_out(vcpu
, size
, port
);
4879 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4882 * Patch in the VMCALL instruction:
4884 hypercall
[0] = 0x0f;
4885 hypercall
[1] = 0x01;
4886 hypercall
[2] = 0xc1;
4889 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
4891 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
4893 if (nested_vmx_secondary_ctls_high
&
4894 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4895 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4896 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4897 return (val
& always_on
) == always_on
;
4900 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4901 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4903 if (is_guest_mode(vcpu
)) {
4904 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4905 unsigned long orig_val
= val
;
4908 * We get here when L2 changed cr0 in a way that did not change
4909 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4910 * but did change L0 shadowed bits. So we first calculate the
4911 * effective cr0 value that L1 would like to write into the
4912 * hardware. It consists of the L2-owned bits from the new
4913 * value combined with the L1-owned bits from L1's guest_cr0.
4915 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4916 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4918 if (!nested_cr0_valid(vmcs12
, val
))
4921 if (kvm_set_cr0(vcpu
, val
))
4923 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4926 if (to_vmx(vcpu
)->nested
.vmxon
&&
4927 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4929 return kvm_set_cr0(vcpu
, val
);
4933 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4935 if (is_guest_mode(vcpu
)) {
4936 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4937 unsigned long orig_val
= val
;
4939 /* analogously to handle_set_cr0 */
4940 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
4941 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
4942 if (kvm_set_cr4(vcpu
, val
))
4944 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
4947 return kvm_set_cr4(vcpu
, val
);
4950 /* called to set cr0 as approriate for clts instruction exit. */
4951 static void handle_clts(struct kvm_vcpu
*vcpu
)
4953 if (is_guest_mode(vcpu
)) {
4955 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4956 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4957 * just pretend it's off (also in arch.cr0 for fpu_activate).
4959 vmcs_writel(CR0_READ_SHADOW
,
4960 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4961 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4963 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4966 static int handle_cr(struct kvm_vcpu
*vcpu
)
4968 unsigned long exit_qualification
, val
;
4973 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4974 cr
= exit_qualification
& 15;
4975 reg
= (exit_qualification
>> 8) & 15;
4976 switch ((exit_qualification
>> 4) & 3) {
4977 case 0: /* mov to cr */
4978 val
= kvm_register_read(vcpu
, reg
);
4979 trace_kvm_cr_write(cr
, val
);
4982 err
= handle_set_cr0(vcpu
, val
);
4983 kvm_complete_insn_gp(vcpu
, err
);
4986 err
= kvm_set_cr3(vcpu
, val
);
4987 kvm_complete_insn_gp(vcpu
, err
);
4990 err
= handle_set_cr4(vcpu
, val
);
4991 kvm_complete_insn_gp(vcpu
, err
);
4994 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4995 u8 cr8
= kvm_register_read(vcpu
, reg
);
4996 err
= kvm_set_cr8(vcpu
, cr8
);
4997 kvm_complete_insn_gp(vcpu
, err
);
4998 if (irqchip_in_kernel(vcpu
->kvm
))
5000 if (cr8_prev
<= cr8
)
5002 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5009 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5010 skip_emulated_instruction(vcpu
);
5011 vmx_fpu_activate(vcpu
);
5013 case 1: /*mov from cr*/
5016 val
= kvm_read_cr3(vcpu
);
5017 kvm_register_write(vcpu
, reg
, val
);
5018 trace_kvm_cr_read(cr
, val
);
5019 skip_emulated_instruction(vcpu
);
5022 val
= kvm_get_cr8(vcpu
);
5023 kvm_register_write(vcpu
, reg
, val
);
5024 trace_kvm_cr_read(cr
, val
);
5025 skip_emulated_instruction(vcpu
);
5030 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5031 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5032 kvm_lmsw(vcpu
, val
);
5034 skip_emulated_instruction(vcpu
);
5039 vcpu
->run
->exit_reason
= 0;
5040 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5041 (int)(exit_qualification
>> 4) & 3, cr
);
5045 static int handle_dr(struct kvm_vcpu
*vcpu
)
5047 unsigned long exit_qualification
;
5050 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5051 if (!kvm_require_cpl(vcpu
, 0))
5053 dr
= vmcs_readl(GUEST_DR7
);
5056 * As the vm-exit takes precedence over the debug trap, we
5057 * need to emulate the latter, either for the host or the
5058 * guest debugging itself.
5060 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5061 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5062 vcpu
->run
->debug
.arch
.dr7
= dr
;
5063 vcpu
->run
->debug
.arch
.pc
=
5064 vmcs_readl(GUEST_CS_BASE
) +
5065 vmcs_readl(GUEST_RIP
);
5066 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5067 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5070 vcpu
->arch
.dr7
&= ~DR7_GD
;
5071 vcpu
->arch
.dr6
|= DR6_BD
;
5072 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5073 kvm_queue_exception(vcpu
, DB_VECTOR
);
5078 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5079 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5080 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5081 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5083 if (!kvm_get_dr(vcpu
, dr
, &val
))
5084 kvm_register_write(vcpu
, reg
, val
);
5086 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
5087 skip_emulated_instruction(vcpu
);
5091 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5093 vmcs_writel(GUEST_DR7
, val
);
5096 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5098 kvm_emulate_cpuid(vcpu
);
5102 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5104 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5107 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5108 trace_kvm_msr_read_ex(ecx
);
5109 kvm_inject_gp(vcpu
, 0);
5113 trace_kvm_msr_read(ecx
, data
);
5115 /* FIXME: handling of bits 32:63 of rax, rdx */
5116 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5117 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5118 skip_emulated_instruction(vcpu
);
5122 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5124 struct msr_data msr
;
5125 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5126 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5127 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5131 msr
.host_initiated
= false;
5132 if (vmx_set_msr(vcpu
, &msr
) != 0) {
5133 trace_kvm_msr_write_ex(ecx
, data
);
5134 kvm_inject_gp(vcpu
, 0);
5138 trace_kvm_msr_write(ecx
, data
);
5139 skip_emulated_instruction(vcpu
);
5143 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5145 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5149 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5151 u32 cpu_based_vm_exec_control
;
5153 /* clear pending irq */
5154 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5155 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5156 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5158 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5160 ++vcpu
->stat
.irq_window_exits
;
5163 * If the user space waits to inject interrupts, exit as soon as
5166 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5167 vcpu
->run
->request_interrupt_window
&&
5168 !kvm_cpu_has_interrupt(vcpu
)) {
5169 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5175 static int handle_halt(struct kvm_vcpu
*vcpu
)
5177 skip_emulated_instruction(vcpu
);
5178 return kvm_emulate_halt(vcpu
);
5181 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5183 skip_emulated_instruction(vcpu
);
5184 kvm_emulate_hypercall(vcpu
);
5188 static int handle_invd(struct kvm_vcpu
*vcpu
)
5190 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5193 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5195 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5197 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5198 skip_emulated_instruction(vcpu
);
5202 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5206 err
= kvm_rdpmc(vcpu
);
5207 kvm_complete_insn_gp(vcpu
, err
);
5212 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5214 skip_emulated_instruction(vcpu
);
5215 kvm_emulate_wbinvd(vcpu
);
5219 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5221 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5222 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5224 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5225 skip_emulated_instruction(vcpu
);
5229 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5231 if (likely(fasteoi
)) {
5232 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5233 int access_type
, offset
;
5235 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5236 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5238 * Sane guest uses MOV to write EOI, with written value
5239 * not cared. So make a short-circuit here by avoiding
5240 * heavy instruction emulation.
5242 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5243 (offset
== APIC_EOI
)) {
5244 kvm_lapic_set_eoi(vcpu
);
5245 skip_emulated_instruction(vcpu
);
5249 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5252 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5254 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5255 int vector
= exit_qualification
& 0xff;
5257 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5258 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5262 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5264 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5265 u32 offset
= exit_qualification
& 0xfff;
5267 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5268 kvm_apic_write_nodecode(vcpu
, offset
);
5272 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5274 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5275 unsigned long exit_qualification
;
5276 bool has_error_code
= false;
5279 int reason
, type
, idt_v
, idt_index
;
5281 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5282 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5283 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5285 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5287 reason
= (u32
)exit_qualification
>> 30;
5288 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5290 case INTR_TYPE_NMI_INTR
:
5291 vcpu
->arch
.nmi_injected
= false;
5292 vmx_set_nmi_mask(vcpu
, true);
5294 case INTR_TYPE_EXT_INTR
:
5295 case INTR_TYPE_SOFT_INTR
:
5296 kvm_clear_interrupt_queue(vcpu
);
5298 case INTR_TYPE_HARD_EXCEPTION
:
5299 if (vmx
->idt_vectoring_info
&
5300 VECTORING_INFO_DELIVER_CODE_MASK
) {
5301 has_error_code
= true;
5303 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5306 case INTR_TYPE_SOFT_EXCEPTION
:
5307 kvm_clear_exception_queue(vcpu
);
5313 tss_selector
= exit_qualification
;
5315 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5316 type
!= INTR_TYPE_EXT_INTR
&&
5317 type
!= INTR_TYPE_NMI_INTR
))
5318 skip_emulated_instruction(vcpu
);
5320 if (kvm_task_switch(vcpu
, tss_selector
,
5321 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5322 has_error_code
, error_code
) == EMULATE_FAIL
) {
5323 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5324 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5325 vcpu
->run
->internal
.ndata
= 0;
5329 /* clear all local breakpoint enable flags */
5330 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
5333 * TODO: What about debug traps on tss switch?
5334 * Are we supposed to inject them and update dr6?
5340 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5342 unsigned long exit_qualification
;
5347 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5349 gla_validity
= (exit_qualification
>> 7) & 0x3;
5350 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5351 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5352 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5353 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5354 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5355 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5356 (long unsigned int)exit_qualification
);
5357 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5358 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5363 * EPT violation happened while executing iret from NMI,
5364 * "blocked by NMI" bit has to be set before next VM entry.
5365 * There are errata that may cause this bit to not be set:
5368 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5369 cpu_has_virtual_nmis() &&
5370 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5371 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5373 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5374 trace_kvm_page_fault(gpa
, exit_qualification
);
5376 /* It is a write fault? */
5377 error_code
= exit_qualification
& (1U << 1);
5378 /* It is a fetch fault? */
5379 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5380 /* ept page table is present? */
5381 error_code
|= (exit_qualification
>> 3) & 0x1;
5383 vcpu
->arch
.exit_qualification
= exit_qualification
;
5385 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5388 static u64
ept_rsvd_mask(u64 spte
, int level
)
5393 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5394 mask
|= (1ULL << i
);
5397 /* bits 7:3 reserved */
5399 else if (level
== 2) {
5400 if (spte
& (1ULL << 7))
5401 /* 2MB ref, bits 20:12 reserved */
5404 /* bits 6:3 reserved */
5411 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5414 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5416 /* 010b (write-only) */
5417 WARN_ON((spte
& 0x7) == 0x2);
5419 /* 110b (write/execute) */
5420 WARN_ON((spte
& 0x7) == 0x6);
5422 /* 100b (execute-only) and value not supported by logical processor */
5423 if (!cpu_has_vmx_ept_execute_only())
5424 WARN_ON((spte
& 0x7) == 0x4);
5428 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5430 if (rsvd_bits
!= 0) {
5431 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5432 __func__
, rsvd_bits
);
5436 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
5437 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5439 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5440 ept_mem_type
== 7) {
5441 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5442 __func__
, ept_mem_type
);
5449 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5452 int nr_sptes
, i
, ret
;
5455 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5457 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5458 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5459 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5462 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5463 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5465 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5468 /* It is the real ept misconfig */
5469 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5470 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5472 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5474 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5475 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5477 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5478 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5483 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5485 u32 cpu_based_vm_exec_control
;
5487 /* clear pending NMI */
5488 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5489 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5490 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5491 ++vcpu
->stat
.nmi_window_exits
;
5492 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5497 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5499 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5500 enum emulation_result err
= EMULATE_DONE
;
5503 bool intr_window_requested
;
5504 unsigned count
= 130;
5506 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5507 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5509 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5510 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5511 return handle_interrupt_window(&vmx
->vcpu
);
5513 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5516 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5518 if (err
== EMULATE_USER_EXIT
) {
5519 ++vcpu
->stat
.mmio_exits
;
5524 if (err
!= EMULATE_DONE
) {
5525 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5526 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5527 vcpu
->run
->internal
.ndata
= 0;
5531 if (vcpu
->arch
.halt_request
) {
5532 vcpu
->arch
.halt_request
= 0;
5533 ret
= kvm_emulate_halt(vcpu
);
5537 if (signal_pending(current
))
5543 vmx
->emulation_required
= emulation_required(vcpu
);
5549 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5550 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5552 static int handle_pause(struct kvm_vcpu
*vcpu
)
5554 skip_emulated_instruction(vcpu
);
5555 kvm_vcpu_on_spin(vcpu
);
5560 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5562 kvm_queue_exception(vcpu
, UD_VECTOR
);
5567 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5568 * We could reuse a single VMCS for all the L2 guests, but we also want the
5569 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5570 * allows keeping them loaded on the processor, and in the future will allow
5571 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5572 * every entry if they never change.
5573 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5574 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5576 * The following functions allocate and free a vmcs02 in this pool.
5579 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5580 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5582 struct vmcs02_list
*item
;
5583 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5584 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5585 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5586 return &item
->vmcs02
;
5589 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5590 /* Recycle the least recently used VMCS. */
5591 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5592 struct vmcs02_list
, list
);
5593 item
->vmptr
= vmx
->nested
.current_vmptr
;
5594 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5595 return &item
->vmcs02
;
5598 /* Create a new VMCS */
5599 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5602 item
->vmcs02
.vmcs
= alloc_vmcs();
5603 if (!item
->vmcs02
.vmcs
) {
5607 loaded_vmcs_init(&item
->vmcs02
);
5608 item
->vmptr
= vmx
->nested
.current_vmptr
;
5609 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5610 vmx
->nested
.vmcs02_num
++;
5611 return &item
->vmcs02
;
5614 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5615 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5617 struct vmcs02_list
*item
;
5618 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5619 if (item
->vmptr
== vmptr
) {
5620 free_loaded_vmcs(&item
->vmcs02
);
5621 list_del(&item
->list
);
5623 vmx
->nested
.vmcs02_num
--;
5629 * Free all VMCSs saved for this vcpu, except the one pointed by
5630 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5631 * currently used, if running L2), and vmcs01 when running L2.
5633 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5635 struct vmcs02_list
*item
, *n
;
5636 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5637 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5638 free_loaded_vmcs(&item
->vmcs02
);
5639 list_del(&item
->list
);
5642 vmx
->nested
.vmcs02_num
= 0;
5644 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5645 free_loaded_vmcs(&vmx
->vmcs01
);
5649 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5650 * set the success or error code of an emulated VMX instruction, as specified
5651 * by Vol 2B, VMX Instruction Reference, "Conventions".
5653 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5655 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5656 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5657 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5660 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5662 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5663 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5664 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5668 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5669 u32 vm_instruction_error
)
5671 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5673 * failValid writes the error number to the current VMCS, which
5674 * can't be done there isn't a current VMCS.
5676 nested_vmx_failInvalid(vcpu
);
5679 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5680 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5681 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5683 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5685 * We don't need to force a shadow sync because
5686 * VM_INSTRUCTION_ERROR is not shadowed
5691 * Emulate the VMXON instruction.
5692 * Currently, we just remember that VMX is active, and do not save or even
5693 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5694 * do not currently need to store anything in that guest-allocated memory
5695 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5696 * argument is different from the VMXON pointer (which the spec says they do).
5698 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5700 struct kvm_segment cs
;
5701 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5702 struct vmcs
*shadow_vmcs
;
5703 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
5704 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
5706 /* The Intel VMX Instruction Reference lists a bunch of bits that
5707 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5708 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5709 * Otherwise, we should fail with #UD. We test these now:
5711 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5712 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5713 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5714 kvm_queue_exception(vcpu
, UD_VECTOR
);
5718 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5719 if (is_long_mode(vcpu
) && !cs
.l
) {
5720 kvm_queue_exception(vcpu
, UD_VECTOR
);
5724 if (vmx_get_cpl(vcpu
)) {
5725 kvm_inject_gp(vcpu
, 0);
5728 if (vmx
->nested
.vmxon
) {
5729 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
5730 skip_emulated_instruction(vcpu
);
5734 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
5735 != VMXON_NEEDED_FEATURES
) {
5736 kvm_inject_gp(vcpu
, 0);
5740 if (enable_shadow_vmcs
) {
5741 shadow_vmcs
= alloc_vmcs();
5744 /* mark vmcs as shadow */
5745 shadow_vmcs
->revision_id
|= (1u << 31);
5746 /* init shadow vmcs */
5747 vmcs_clear(shadow_vmcs
);
5748 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
5751 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5752 vmx
->nested
.vmcs02_num
= 0;
5754 vmx
->nested
.vmxon
= true;
5756 skip_emulated_instruction(vcpu
);
5757 nested_vmx_succeed(vcpu
);
5762 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5763 * for running VMX instructions (except VMXON, whose prerequisites are
5764 * slightly different). It also specifies what exception to inject otherwise.
5766 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5768 struct kvm_segment cs
;
5769 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5771 if (!vmx
->nested
.vmxon
) {
5772 kvm_queue_exception(vcpu
, UD_VECTOR
);
5776 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5777 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5778 (is_long_mode(vcpu
) && !cs
.l
)) {
5779 kvm_queue_exception(vcpu
, UD_VECTOR
);
5783 if (vmx_get_cpl(vcpu
)) {
5784 kvm_inject_gp(vcpu
, 0);
5791 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
5794 if (enable_shadow_vmcs
) {
5795 if (vmx
->nested
.current_vmcs12
!= NULL
) {
5796 /* copy to memory all shadowed fields in case
5797 they were modified */
5798 copy_shadow_to_vmcs12(vmx
);
5799 vmx
->nested
.sync_shadow_vmcs
= false;
5800 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
5801 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5802 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
5803 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
5806 kunmap(vmx
->nested
.current_vmcs12_page
);
5807 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5811 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5812 * just stops using VMX.
5814 static void free_nested(struct vcpu_vmx
*vmx
)
5816 if (!vmx
->nested
.vmxon
)
5818 vmx
->nested
.vmxon
= false;
5819 if (vmx
->nested
.current_vmptr
!= -1ull) {
5820 nested_release_vmcs12(vmx
);
5821 vmx
->nested
.current_vmptr
= -1ull;
5822 vmx
->nested
.current_vmcs12
= NULL
;
5824 if (enable_shadow_vmcs
)
5825 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
5826 /* Unpin physical memory we referred to in current vmcs02 */
5827 if (vmx
->nested
.apic_access_page
) {
5828 nested_release_page(vmx
->nested
.apic_access_page
);
5829 vmx
->nested
.apic_access_page
= 0;
5832 nested_free_all_saved_vmcss(vmx
);
5835 /* Emulate the VMXOFF instruction */
5836 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5838 if (!nested_vmx_check_permission(vcpu
))
5840 free_nested(to_vmx(vcpu
));
5841 skip_emulated_instruction(vcpu
);
5842 nested_vmx_succeed(vcpu
);
5847 * Decode the memory-address operand of a vmx instruction, as recorded on an
5848 * exit caused by such an instruction (run by a guest hypervisor).
5849 * On success, returns 0. When the operand is invalid, returns 1 and throws
5852 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5853 unsigned long exit_qualification
,
5854 u32 vmx_instruction_info
, gva_t
*ret
)
5857 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5858 * Execution", on an exit, vmx_instruction_info holds most of the
5859 * addressing components of the operand. Only the displacement part
5860 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5861 * For how an actual address is calculated from all these components,
5862 * refer to Vol. 1, "Operand Addressing".
5864 int scaling
= vmx_instruction_info
& 3;
5865 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5866 bool is_reg
= vmx_instruction_info
& (1u << 10);
5867 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5868 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5869 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5870 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5871 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5874 kvm_queue_exception(vcpu
, UD_VECTOR
);
5878 /* Addr = segment_base + offset */
5879 /* offset = base + [index * scale] + displacement */
5880 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5882 *ret
+= kvm_register_read(vcpu
, base_reg
);
5884 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5885 *ret
+= exit_qualification
; /* holds the displacement */
5887 if (addr_size
== 1) /* 32 bit */
5891 * TODO: throw #GP (and return 1) in various cases that the VM*
5892 * instructions require it - e.g., offset beyond segment limit,
5893 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5894 * address, and so on. Currently these are not checked.
5899 /* Emulate the VMCLEAR instruction */
5900 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5902 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5905 struct vmcs12
*vmcs12
;
5907 struct x86_exception e
;
5909 if (!nested_vmx_check_permission(vcpu
))
5912 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5913 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5916 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5917 sizeof(vmptr
), &e
)) {
5918 kvm_inject_page_fault(vcpu
, &e
);
5922 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5923 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5924 skip_emulated_instruction(vcpu
);
5928 if (vmptr
== vmx
->nested
.current_vmptr
) {
5929 nested_release_vmcs12(vmx
);
5930 vmx
->nested
.current_vmptr
= -1ull;
5931 vmx
->nested
.current_vmcs12
= NULL
;
5934 page
= nested_get_page(vcpu
, vmptr
);
5937 * For accurate processor emulation, VMCLEAR beyond available
5938 * physical memory should do nothing at all. However, it is
5939 * possible that a nested vmx bug, not a guest hypervisor bug,
5940 * resulted in this case, so let's shut down before doing any
5943 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5946 vmcs12
= kmap(page
);
5947 vmcs12
->launch_state
= 0;
5949 nested_release_page(page
);
5951 nested_free_vmcs02(vmx
, vmptr
);
5953 skip_emulated_instruction(vcpu
);
5954 nested_vmx_succeed(vcpu
);
5958 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5960 /* Emulate the VMLAUNCH instruction */
5961 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
5963 return nested_vmx_run(vcpu
, true);
5966 /* Emulate the VMRESUME instruction */
5967 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
5970 return nested_vmx_run(vcpu
, false);
5973 enum vmcs_field_type
{
5974 VMCS_FIELD_TYPE_U16
= 0,
5975 VMCS_FIELD_TYPE_U64
= 1,
5976 VMCS_FIELD_TYPE_U32
= 2,
5977 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
5980 static inline int vmcs_field_type(unsigned long field
)
5982 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
5983 return VMCS_FIELD_TYPE_U32
;
5984 return (field
>> 13) & 0x3 ;
5987 static inline int vmcs_field_readonly(unsigned long field
)
5989 return (((field
>> 10) & 0x3) == 1);
5993 * Read a vmcs12 field. Since these can have varying lengths and we return
5994 * one type, we chose the biggest type (u64) and zero-extend the return value
5995 * to that size. Note that the caller, handle_vmread, might need to use only
5996 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5997 * 64-bit fields are to be returned).
5999 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6000 unsigned long field
, u64
*ret
)
6002 short offset
= vmcs_field_to_offset(field
);
6008 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6010 switch (vmcs_field_type(field
)) {
6011 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6012 *ret
= *((natural_width
*)p
);
6014 case VMCS_FIELD_TYPE_U16
:
6017 case VMCS_FIELD_TYPE_U32
:
6020 case VMCS_FIELD_TYPE_U64
:
6024 return 0; /* can never happen. */
6029 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6030 unsigned long field
, u64 field_value
){
6031 short offset
= vmcs_field_to_offset(field
);
6032 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6036 switch (vmcs_field_type(field
)) {
6037 case VMCS_FIELD_TYPE_U16
:
6038 *(u16
*)p
= field_value
;
6040 case VMCS_FIELD_TYPE_U32
:
6041 *(u32
*)p
= field_value
;
6043 case VMCS_FIELD_TYPE_U64
:
6044 *(u64
*)p
= field_value
;
6046 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6047 *(natural_width
*)p
= field_value
;
6050 return false; /* can never happen. */
6055 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6058 unsigned long field
;
6060 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6061 const unsigned long *fields
= shadow_read_write_fields
;
6062 const int num_fields
= max_shadow_read_write_fields
;
6064 vmcs_load(shadow_vmcs
);
6066 for (i
= 0; i
< num_fields
; i
++) {
6068 switch (vmcs_field_type(field
)) {
6069 case VMCS_FIELD_TYPE_U16
:
6070 field_value
= vmcs_read16(field
);
6072 case VMCS_FIELD_TYPE_U32
:
6073 field_value
= vmcs_read32(field
);
6075 case VMCS_FIELD_TYPE_U64
:
6076 field_value
= vmcs_read64(field
);
6078 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6079 field_value
= vmcs_readl(field
);
6082 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6085 vmcs_clear(shadow_vmcs
);
6086 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6089 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6091 const unsigned long *fields
[] = {
6092 shadow_read_write_fields
,
6093 shadow_read_only_fields
6095 const int max_fields
[] = {
6096 max_shadow_read_write_fields
,
6097 max_shadow_read_only_fields
6100 unsigned long field
;
6101 u64 field_value
= 0;
6102 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6104 vmcs_load(shadow_vmcs
);
6106 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6107 for (i
= 0; i
< max_fields
[q
]; i
++) {
6108 field
= fields
[q
][i
];
6109 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6111 switch (vmcs_field_type(field
)) {
6112 case VMCS_FIELD_TYPE_U16
:
6113 vmcs_write16(field
, (u16
)field_value
);
6115 case VMCS_FIELD_TYPE_U32
:
6116 vmcs_write32(field
, (u32
)field_value
);
6118 case VMCS_FIELD_TYPE_U64
:
6119 vmcs_write64(field
, (u64
)field_value
);
6121 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6122 vmcs_writel(field
, (long)field_value
);
6128 vmcs_clear(shadow_vmcs
);
6129 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6133 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6134 * used before) all generate the same failure when it is missing.
6136 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6138 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6139 if (vmx
->nested
.current_vmptr
== -1ull) {
6140 nested_vmx_failInvalid(vcpu
);
6141 skip_emulated_instruction(vcpu
);
6147 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6149 unsigned long field
;
6151 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6152 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6155 if (!nested_vmx_check_permission(vcpu
) ||
6156 !nested_vmx_check_vmcs12(vcpu
))
6159 /* Decode instruction info and find the field to read */
6160 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6161 /* Read the field, zero-extended to a u64 field_value */
6162 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6163 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6164 skip_emulated_instruction(vcpu
);
6168 * Now copy part of this value to register or memory, as requested.
6169 * Note that the number of bits actually copied is 32 or 64 depending
6170 * on the guest's mode (32 or 64 bit), not on the given field's length.
6172 if (vmx_instruction_info
& (1u << 10)) {
6173 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6176 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6177 vmx_instruction_info
, &gva
))
6179 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6180 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6181 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6184 nested_vmx_succeed(vcpu
);
6185 skip_emulated_instruction(vcpu
);
6190 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6192 unsigned long field
;
6194 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6195 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6196 /* The value to write might be 32 or 64 bits, depending on L1's long
6197 * mode, and eventually we need to write that into a field of several
6198 * possible lengths. The code below first zero-extends the value to 64
6199 * bit (field_value), and then copies only the approriate number of
6200 * bits into the vmcs12 field.
6202 u64 field_value
= 0;
6203 struct x86_exception e
;
6205 if (!nested_vmx_check_permission(vcpu
) ||
6206 !nested_vmx_check_vmcs12(vcpu
))
6209 if (vmx_instruction_info
& (1u << 10))
6210 field_value
= kvm_register_read(vcpu
,
6211 (((vmx_instruction_info
) >> 3) & 0xf));
6213 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6214 vmx_instruction_info
, &gva
))
6216 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6217 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
6218 kvm_inject_page_fault(vcpu
, &e
);
6224 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6225 if (vmcs_field_readonly(field
)) {
6226 nested_vmx_failValid(vcpu
,
6227 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6228 skip_emulated_instruction(vcpu
);
6232 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6233 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6234 skip_emulated_instruction(vcpu
);
6238 nested_vmx_succeed(vcpu
);
6239 skip_emulated_instruction(vcpu
);
6243 /* Emulate the VMPTRLD instruction */
6244 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6246 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6249 struct x86_exception e
;
6252 if (!nested_vmx_check_permission(vcpu
))
6255 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6256 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6259 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6260 sizeof(vmptr
), &e
)) {
6261 kvm_inject_page_fault(vcpu
, &e
);
6265 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
6266 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
6267 skip_emulated_instruction(vcpu
);
6271 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6272 struct vmcs12
*new_vmcs12
;
6274 page
= nested_get_page(vcpu
, vmptr
);
6276 nested_vmx_failInvalid(vcpu
);
6277 skip_emulated_instruction(vcpu
);
6280 new_vmcs12
= kmap(page
);
6281 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6283 nested_release_page_clean(page
);
6284 nested_vmx_failValid(vcpu
,
6285 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6286 skip_emulated_instruction(vcpu
);
6289 if (vmx
->nested
.current_vmptr
!= -1ull)
6290 nested_release_vmcs12(vmx
);
6292 vmx
->nested
.current_vmptr
= vmptr
;
6293 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6294 vmx
->nested
.current_vmcs12_page
= page
;
6295 if (enable_shadow_vmcs
) {
6296 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6297 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6298 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6299 vmcs_write64(VMCS_LINK_POINTER
,
6300 __pa(vmx
->nested
.current_shadow_vmcs
));
6301 vmx
->nested
.sync_shadow_vmcs
= true;
6305 nested_vmx_succeed(vcpu
);
6306 skip_emulated_instruction(vcpu
);
6310 /* Emulate the VMPTRST instruction */
6311 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6313 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6314 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6316 struct x86_exception e
;
6318 if (!nested_vmx_check_permission(vcpu
))
6321 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6322 vmx_instruction_info
, &vmcs_gva
))
6324 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6325 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6326 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6328 kvm_inject_page_fault(vcpu
, &e
);
6331 nested_vmx_succeed(vcpu
);
6332 skip_emulated_instruction(vcpu
);
6336 /* Emulate the INVEPT instruction */
6337 static int handle_invept(struct kvm_vcpu
*vcpu
)
6339 u32 vmx_instruction_info
, types
;
6342 struct x86_exception e
;
6346 u64 eptp_mask
= ((1ull << 51) - 1) & PAGE_MASK
;
6348 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6349 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6350 kvm_queue_exception(vcpu
, UD_VECTOR
);
6354 if (!nested_vmx_check_permission(vcpu
))
6357 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6358 kvm_queue_exception(vcpu
, UD_VECTOR
);
6362 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6363 type
= kvm_register_read(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6365 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6367 if (!(types
& (1UL << type
))) {
6368 nested_vmx_failValid(vcpu
,
6369 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6373 /* According to the Intel VMX instruction reference, the memory
6374 * operand is read even if it isn't needed (e.g., for type==global)
6376 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6377 vmx_instruction_info
, &gva
))
6379 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6380 sizeof(operand
), &e
)) {
6381 kvm_inject_page_fault(vcpu
, &e
);
6386 case VMX_EPT_EXTENT_CONTEXT
:
6387 if ((operand
.eptp
& eptp_mask
) !=
6388 (nested_ept_get_cr3(vcpu
) & eptp_mask
))
6390 case VMX_EPT_EXTENT_GLOBAL
:
6391 kvm_mmu_sync_roots(vcpu
);
6392 kvm_mmu_flush_tlb(vcpu
);
6393 nested_vmx_succeed(vcpu
);
6400 skip_emulated_instruction(vcpu
);
6405 * The exit handlers return 1 if the exit was handled fully and guest execution
6406 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6407 * to be done to userspace and return 0.
6409 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6410 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6411 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6412 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6413 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6414 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6415 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6416 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6417 [EXIT_REASON_CPUID
] = handle_cpuid
,
6418 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6419 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6420 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6421 [EXIT_REASON_HLT
] = handle_halt
,
6422 [EXIT_REASON_INVD
] = handle_invd
,
6423 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6424 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6425 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6426 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6427 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6428 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6429 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6430 [EXIT_REASON_VMREAD
] = handle_vmread
,
6431 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6432 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6433 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6434 [EXIT_REASON_VMON
] = handle_vmon
,
6435 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6436 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6437 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6438 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6439 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6440 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6441 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6442 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6443 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6444 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6445 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6446 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
6447 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
6448 [EXIT_REASON_INVEPT
] = handle_invept
,
6451 static const int kvm_vmx_max_exit_handlers
=
6452 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6454 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6455 struct vmcs12
*vmcs12
)
6457 unsigned long exit_qualification
;
6458 gpa_t bitmap
, last_bitmap
;
6463 if (nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
))
6466 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6469 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6471 port
= exit_qualification
>> 16;
6472 size
= (exit_qualification
& 7) + 1;
6474 last_bitmap
= (gpa_t
)-1;
6479 bitmap
= vmcs12
->io_bitmap_a
;
6480 else if (port
< 0x10000)
6481 bitmap
= vmcs12
->io_bitmap_b
;
6484 bitmap
+= (port
& 0x7fff) / 8;
6486 if (last_bitmap
!= bitmap
)
6487 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6489 if (b
& (1 << (port
& 7)))
6494 last_bitmap
= bitmap
;
6501 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6502 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6503 * disinterest in the current event (read or write a specific MSR) by using an
6504 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6506 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6507 struct vmcs12
*vmcs12
, u32 exit_reason
)
6509 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6512 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6516 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6517 * for the four combinations of read/write and low/high MSR numbers.
6518 * First we need to figure out which of the four to use:
6520 bitmap
= vmcs12
->msr_bitmap
;
6521 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6523 if (msr_index
>= 0xc0000000) {
6524 msr_index
-= 0xc0000000;
6528 /* Then read the msr_index'th bit from this bitmap: */
6529 if (msr_index
< 1024*8) {
6531 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6533 return 1 & (b
>> (msr_index
& 7));
6535 return 1; /* let L1 handle the wrong parameter */
6539 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6540 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6541 * intercept (via guest_host_mask etc.) the current event.
6543 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6544 struct vmcs12
*vmcs12
)
6546 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6547 int cr
= exit_qualification
& 15;
6548 int reg
= (exit_qualification
>> 8) & 15;
6549 unsigned long val
= kvm_register_read(vcpu
, reg
);
6551 switch ((exit_qualification
>> 4) & 3) {
6552 case 0: /* mov to cr */
6555 if (vmcs12
->cr0_guest_host_mask
&
6556 (val
^ vmcs12
->cr0_read_shadow
))
6560 if ((vmcs12
->cr3_target_count
>= 1 &&
6561 vmcs12
->cr3_target_value0
== val
) ||
6562 (vmcs12
->cr3_target_count
>= 2 &&
6563 vmcs12
->cr3_target_value1
== val
) ||
6564 (vmcs12
->cr3_target_count
>= 3 &&
6565 vmcs12
->cr3_target_value2
== val
) ||
6566 (vmcs12
->cr3_target_count
>= 4 &&
6567 vmcs12
->cr3_target_value3
== val
))
6569 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6573 if (vmcs12
->cr4_guest_host_mask
&
6574 (vmcs12
->cr4_read_shadow
^ val
))
6578 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6584 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6585 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6588 case 1: /* mov from cr */
6591 if (vmcs12
->cpu_based_vm_exec_control
&
6592 CPU_BASED_CR3_STORE_EXITING
)
6596 if (vmcs12
->cpu_based_vm_exec_control
&
6597 CPU_BASED_CR8_STORE_EXITING
)
6604 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6605 * cr0. Other attempted changes are ignored, with no exit.
6607 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6608 (val
^ vmcs12
->cr0_read_shadow
))
6610 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6611 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6620 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6621 * should handle it ourselves in L0 (and then continue L2). Only call this
6622 * when in is_guest_mode (L2).
6624 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6626 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6627 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6628 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6629 u32 exit_reason
= vmx
->exit_reason
;
6631 if (vmx
->nested
.nested_run_pending
)
6634 if (unlikely(vmx
->fail
)) {
6635 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6636 vmcs_read32(VM_INSTRUCTION_ERROR
));
6640 switch (exit_reason
) {
6641 case EXIT_REASON_EXCEPTION_NMI
:
6642 if (!is_exception(intr_info
))
6644 else if (is_page_fault(intr_info
))
6646 else if (is_no_device(intr_info
) &&
6647 !(nested_read_cr0(vmcs12
) & X86_CR0_TS
))
6649 return vmcs12
->exception_bitmap
&
6650 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6651 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6653 case EXIT_REASON_TRIPLE_FAULT
:
6655 case EXIT_REASON_PENDING_INTERRUPT
:
6656 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
6657 case EXIT_REASON_NMI_WINDOW
:
6658 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
6659 case EXIT_REASON_TASK_SWITCH
:
6661 case EXIT_REASON_CPUID
:
6663 case EXIT_REASON_HLT
:
6664 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6665 case EXIT_REASON_INVD
:
6667 case EXIT_REASON_INVLPG
:
6668 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6669 case EXIT_REASON_RDPMC
:
6670 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6671 case EXIT_REASON_RDTSC
:
6672 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6673 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6674 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6675 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6676 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6677 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6678 case EXIT_REASON_INVEPT
:
6680 * VMX instructions trap unconditionally. This allows L1 to
6681 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6684 case EXIT_REASON_CR_ACCESS
:
6685 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6686 case EXIT_REASON_DR_ACCESS
:
6687 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6688 case EXIT_REASON_IO_INSTRUCTION
:
6689 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
6690 case EXIT_REASON_MSR_READ
:
6691 case EXIT_REASON_MSR_WRITE
:
6692 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6693 case EXIT_REASON_INVALID_STATE
:
6695 case EXIT_REASON_MWAIT_INSTRUCTION
:
6696 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6697 case EXIT_REASON_MONITOR_INSTRUCTION
:
6698 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6699 case EXIT_REASON_PAUSE_INSTRUCTION
:
6700 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6701 nested_cpu_has2(vmcs12
,
6702 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6703 case EXIT_REASON_MCE_DURING_VMENTRY
:
6705 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6707 case EXIT_REASON_APIC_ACCESS
:
6708 return nested_cpu_has2(vmcs12
,
6709 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6710 case EXIT_REASON_EPT_VIOLATION
:
6712 * L0 always deals with the EPT violation. If nested EPT is
6713 * used, and the nested mmu code discovers that the address is
6714 * missing in the guest EPT table (EPT12), the EPT violation
6715 * will be injected with nested_ept_inject_page_fault()
6718 case EXIT_REASON_EPT_MISCONFIG
:
6720 * L2 never uses directly L1's EPT, but rather L0's own EPT
6721 * table (shadow on EPT) or a merged EPT table that L0 built
6722 * (EPT on EPT). So any problems with the structure of the
6723 * table is L0's fault.
6726 case EXIT_REASON_PREEMPTION_TIMER
:
6727 return vmcs12
->pin_based_vm_exec_control
&
6728 PIN_BASED_VMX_PREEMPTION_TIMER
;
6729 case EXIT_REASON_WBINVD
:
6730 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6731 case EXIT_REASON_XSETBV
:
6738 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6740 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6741 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6744 static void nested_adjust_preemption_timer(struct kvm_vcpu
*vcpu
)
6747 u32 preempt_val_l1
, preempt_val_l2
, preempt_scale
;
6749 if (!(get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
6750 PIN_BASED_VMX_PREEMPTION_TIMER
))
6752 preempt_scale
= native_read_msr(MSR_IA32_VMX_MISC
) &
6753 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE
;
6754 preempt_val_l2
= vmcs_read32(VMX_PREEMPTION_TIMER_VALUE
);
6755 delta_tsc_l1
= vmx_read_l1_tsc(vcpu
, native_read_tsc())
6756 - vcpu
->arch
.last_guest_tsc
;
6757 preempt_val_l1
= delta_tsc_l1
>> preempt_scale
;
6758 if (preempt_val_l2
<= preempt_val_l1
)
6761 preempt_val_l2
-= preempt_val_l1
;
6762 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, preempt_val_l2
);
6766 * The guest has exited. See if we can fix it or if we need userspace
6769 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6771 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6772 u32 exit_reason
= vmx
->exit_reason
;
6773 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6775 /* If guest state is invalid, start emulating */
6776 if (vmx
->emulation_required
)
6777 return handle_invalid_guest_state(vcpu
);
6779 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6780 nested_vmx_vmexit(vcpu
);
6784 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
6785 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6786 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6791 if (unlikely(vmx
->fail
)) {
6792 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6793 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6794 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6800 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6801 * delivery event since it indicates guest is accessing MMIO.
6802 * The vm-exit can be triggered again after return to guest that
6803 * will cause infinite loop.
6805 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6806 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6807 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6808 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6809 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6810 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
6811 vcpu
->run
->internal
.ndata
= 2;
6812 vcpu
->run
->internal
.data
[0] = vectoring_info
;
6813 vcpu
->run
->internal
.data
[1] = exit_reason
;
6817 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6818 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6819 get_vmcs12(vcpu
))))) {
6820 if (vmx_interrupt_allowed(vcpu
)) {
6821 vmx
->soft_vnmi_blocked
= 0;
6822 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6823 vcpu
->arch
.nmi_pending
) {
6825 * This CPU don't support us in finding the end of an
6826 * NMI-blocked window if the guest runs with IRQs
6827 * disabled. So we pull the trigger after 1 s of
6828 * futile waiting, but inform the user about this.
6830 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6831 "state on VCPU %d after 1 s timeout\n",
6832 __func__
, vcpu
->vcpu_id
);
6833 vmx
->soft_vnmi_blocked
= 0;
6837 if (exit_reason
< kvm_vmx_max_exit_handlers
6838 && kvm_vmx_exit_handlers
[exit_reason
])
6839 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6841 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6842 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
6847 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6849 if (irr
== -1 || tpr
< irr
) {
6850 vmcs_write32(TPR_THRESHOLD
, 0);
6854 vmcs_write32(TPR_THRESHOLD
, irr
);
6857 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
6859 u32 sec_exec_control
;
6862 * There is not point to enable virtualize x2apic without enable
6865 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6866 !vmx_vm_has_apicv(vcpu
->kvm
))
6869 if (!vm_need_tpr_shadow(vcpu
->kvm
))
6872 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6875 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6876 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6878 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6879 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6881 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
6883 vmx_set_msr_bitmap(vcpu
);
6886 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
6891 if (!vmx_vm_has_apicv(kvm
))
6897 status
= vmcs_read16(GUEST_INTR_STATUS
);
6902 vmcs_write16(GUEST_INTR_STATUS
, status
);
6906 static void vmx_set_rvi(int vector
)
6911 status
= vmcs_read16(GUEST_INTR_STATUS
);
6912 old
= (u8
)status
& 0xff;
6913 if ((u8
)vector
!= old
) {
6915 status
|= (u8
)vector
;
6916 vmcs_write16(GUEST_INTR_STATUS
, status
);
6920 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
6925 vmx_set_rvi(max_irr
);
6928 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
6930 if (!vmx_vm_has_apicv(vcpu
->kvm
))
6933 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
6934 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
6935 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
6936 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
6939 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
6943 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
6944 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
6947 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6948 exit_intr_info
= vmx
->exit_intr_info
;
6950 /* Handle machine checks before interrupts are enabled */
6951 if (is_machine_check(exit_intr_info
))
6952 kvm_machine_check();
6954 /* We need to handle NMIs before interrupts are enabled */
6955 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
6956 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
6957 kvm_before_handle_nmi(&vmx
->vcpu
);
6959 kvm_after_handle_nmi(&vmx
->vcpu
);
6963 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
6965 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6968 * If external interrupt exists, IF bit is set in rflags/eflags on the
6969 * interrupt stack frame, and interrupt will be enabled on a return
6970 * from interrupt handler.
6972 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
6973 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
6974 unsigned int vector
;
6975 unsigned long entry
;
6977 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6978 #ifdef CONFIG_X86_64
6982 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6983 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
6984 entry
= gate_offset(*desc
);
6986 #ifdef CONFIG_X86_64
6987 "mov %%" _ASM_SP
", %[sp]\n\t"
6988 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
6993 "orl $0x200, (%%" _ASM_SP
")\n\t"
6994 __ASM_SIZE(push
) " $%c[cs]\n\t"
6995 "call *%[entry]\n\t"
6997 #ifdef CONFIG_X86_64
7002 [ss
]"i"(__KERNEL_DS
),
7003 [cs
]"i"(__KERNEL_CS
)
7009 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7014 bool idtv_info_valid
;
7016 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7018 if (cpu_has_virtual_nmis()) {
7019 if (vmx
->nmi_known_unmasked
)
7022 * Can't use vmx->exit_intr_info since we're not sure what
7023 * the exit reason is.
7025 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7026 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7027 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7029 * SDM 3: 27.7.1.2 (September 2008)
7030 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7031 * a guest IRET fault.
7032 * SDM 3: 23.2.2 (September 2008)
7033 * Bit 12 is undefined in any of the following cases:
7034 * If the VM exit sets the valid bit in the IDT-vectoring
7035 * information field.
7036 * If the VM exit is due to a double fault.
7038 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7039 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7040 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7041 GUEST_INTR_STATE_NMI
);
7043 vmx
->nmi_known_unmasked
=
7044 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7045 & GUEST_INTR_STATE_NMI
);
7046 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7047 vmx
->vnmi_blocked_time
+=
7048 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7051 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7052 u32 idt_vectoring_info
,
7053 int instr_len_field
,
7054 int error_code_field
)
7058 bool idtv_info_valid
;
7060 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7062 vcpu
->arch
.nmi_injected
= false;
7063 kvm_clear_exception_queue(vcpu
);
7064 kvm_clear_interrupt_queue(vcpu
);
7066 if (!idtv_info_valid
)
7069 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7071 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7072 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7075 case INTR_TYPE_NMI_INTR
:
7076 vcpu
->arch
.nmi_injected
= true;
7078 * SDM 3: 27.7.1.2 (September 2008)
7079 * Clear bit "block by NMI" before VM entry if a NMI
7082 vmx_set_nmi_mask(vcpu
, false);
7084 case INTR_TYPE_SOFT_EXCEPTION
:
7085 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7087 case INTR_TYPE_HARD_EXCEPTION
:
7088 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7089 u32 err
= vmcs_read32(error_code_field
);
7090 kvm_requeue_exception_e(vcpu
, vector
, err
);
7092 kvm_requeue_exception(vcpu
, vector
);
7094 case INTR_TYPE_SOFT_INTR
:
7095 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7097 case INTR_TYPE_EXT_INTR
:
7098 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7105 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7107 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7108 VM_EXIT_INSTRUCTION_LEN
,
7109 IDT_VECTORING_ERROR_CODE
);
7112 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7114 __vmx_complete_interrupts(vcpu
,
7115 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7116 VM_ENTRY_INSTRUCTION_LEN
,
7117 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7119 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7122 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7125 struct perf_guest_switch_msr
*msrs
;
7127 msrs
= perf_guest_get_msrs(&nr_msrs
);
7132 for (i
= 0; i
< nr_msrs
; i
++)
7133 if (msrs
[i
].host
== msrs
[i
].guest
)
7134 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7136 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7140 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7142 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7143 unsigned long debugctlmsr
;
7145 /* Record the guest's net vcpu time for enforced NMI injections. */
7146 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7147 vmx
->entry_time
= ktime_get();
7149 /* Don't enter VMX if guest state is invalid, let the exit handler
7150 start emulation until we arrive back to a valid state */
7151 if (vmx
->emulation_required
)
7154 if (vmx
->nested
.sync_shadow_vmcs
) {
7155 copy_vmcs12_to_shadow(vmx
);
7156 vmx
->nested
.sync_shadow_vmcs
= false;
7159 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7160 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7161 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7162 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7164 /* When single-stepping over STI and MOV SS, we must clear the
7165 * corresponding interruptibility bits in the guest state. Otherwise
7166 * vmentry fails as it then expects bit 14 (BS) in pending debug
7167 * exceptions being set, but that's not correct for the guest debugging
7169 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7170 vmx_set_interrupt_shadow(vcpu
, 0);
7172 atomic_switch_perf_msrs(vmx
);
7173 debugctlmsr
= get_debugctlmsr();
7175 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
)
7176 nested_adjust_preemption_timer(vcpu
);
7177 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7179 /* Store host registers */
7180 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7181 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7182 "push %%" _ASM_CX
" \n\t"
7183 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7185 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7186 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7188 /* Reload cr2 if changed */
7189 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7190 "mov %%cr2, %%" _ASM_DX
" \n\t"
7191 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7193 "mov %%" _ASM_AX
", %%cr2 \n\t"
7195 /* Check if vmlaunch of vmresume is needed */
7196 "cmpl $0, %c[launched](%0) \n\t"
7197 /* Load guest registers. Don't clobber flags. */
7198 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7199 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7200 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7201 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7202 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7203 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7204 #ifdef CONFIG_X86_64
7205 "mov %c[r8](%0), %%r8 \n\t"
7206 "mov %c[r9](%0), %%r9 \n\t"
7207 "mov %c[r10](%0), %%r10 \n\t"
7208 "mov %c[r11](%0), %%r11 \n\t"
7209 "mov %c[r12](%0), %%r12 \n\t"
7210 "mov %c[r13](%0), %%r13 \n\t"
7211 "mov %c[r14](%0), %%r14 \n\t"
7212 "mov %c[r15](%0), %%r15 \n\t"
7214 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7216 /* Enter guest mode */
7218 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7220 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7222 /* Save guest registers, load host registers, keep flags */
7223 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7225 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7226 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7227 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7228 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7229 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7230 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7231 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7232 #ifdef CONFIG_X86_64
7233 "mov %%r8, %c[r8](%0) \n\t"
7234 "mov %%r9, %c[r9](%0) \n\t"
7235 "mov %%r10, %c[r10](%0) \n\t"
7236 "mov %%r11, %c[r11](%0) \n\t"
7237 "mov %%r12, %c[r12](%0) \n\t"
7238 "mov %%r13, %c[r13](%0) \n\t"
7239 "mov %%r14, %c[r14](%0) \n\t"
7240 "mov %%r15, %c[r15](%0) \n\t"
7242 "mov %%cr2, %%" _ASM_AX
" \n\t"
7243 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7245 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7246 "setbe %c[fail](%0) \n\t"
7247 ".pushsection .rodata \n\t"
7248 ".global vmx_return \n\t"
7249 "vmx_return: " _ASM_PTR
" 2b \n\t"
7251 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7252 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7253 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7254 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7255 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7256 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7257 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7258 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7259 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7260 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7261 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7262 #ifdef CONFIG_X86_64
7263 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7264 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7265 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7266 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7267 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7268 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7269 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7270 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7272 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7273 [wordsize
]"i"(sizeof(ulong
))
7275 #ifdef CONFIG_X86_64
7276 , "rax", "rbx", "rdi", "rsi"
7277 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7279 , "eax", "ebx", "edi", "esi"
7283 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7285 update_debugctlmsr(debugctlmsr
);
7287 #ifndef CONFIG_X86_64
7289 * The sysexit path does not restore ds/es, so we must set them to
7290 * a reasonable value ourselves.
7292 * We can't defer this to vmx_load_host_state() since that function
7293 * may be executed in interrupt context, which saves and restore segments
7294 * around it, nullifying its effect.
7296 loadsegment(ds
, __USER_DS
);
7297 loadsegment(es
, __USER_DS
);
7300 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7301 | (1 << VCPU_EXREG_RFLAGS
)
7302 | (1 << VCPU_EXREG_CPL
)
7303 | (1 << VCPU_EXREG_PDPTR
)
7304 | (1 << VCPU_EXREG_SEGMENTS
)
7305 | (1 << VCPU_EXREG_CR3
));
7306 vcpu
->arch
.regs_dirty
= 0;
7308 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7310 vmx
->loaded_vmcs
->launched
= 1;
7312 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7313 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7316 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7317 * we did not inject a still-pending event to L1 now because of
7318 * nested_run_pending, we need to re-enable this bit.
7320 if (vmx
->nested
.nested_run_pending
)
7321 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7323 vmx
->nested
.nested_run_pending
= 0;
7325 vmx_complete_atomic_exit(vmx
);
7326 vmx_recover_nmi_blocking(vmx
);
7327 vmx_complete_interrupts(vmx
);
7330 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7332 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7336 free_loaded_vmcs(vmx
->loaded_vmcs
);
7337 kfree(vmx
->guest_msrs
);
7338 kvm_vcpu_uninit(vcpu
);
7339 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7342 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7345 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7349 return ERR_PTR(-ENOMEM
);
7353 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7357 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7359 if (!vmx
->guest_msrs
) {
7363 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7364 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7365 if (!vmx
->loaded_vmcs
->vmcs
)
7368 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7369 loaded_vmcs_init(vmx
->loaded_vmcs
);
7374 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7375 vmx
->vcpu
.cpu
= cpu
;
7376 err
= vmx_vcpu_setup(vmx
);
7377 vmx_vcpu_put(&vmx
->vcpu
);
7381 if (vm_need_virtualize_apic_accesses(kvm
)) {
7382 err
= alloc_apic_access_page(kvm
);
7388 if (!kvm
->arch
.ept_identity_map_addr
)
7389 kvm
->arch
.ept_identity_map_addr
=
7390 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7392 if (alloc_identity_pagetable(kvm
) != 0)
7394 if (!init_rmode_identity_map(kvm
))
7398 vmx
->nested
.current_vmptr
= -1ull;
7399 vmx
->nested
.current_vmcs12
= NULL
;
7404 free_loaded_vmcs(vmx
->loaded_vmcs
);
7406 kfree(vmx
->guest_msrs
);
7408 kvm_vcpu_uninit(&vmx
->vcpu
);
7411 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7412 return ERR_PTR(err
);
7415 static void __init
vmx_check_processor_compat(void *rtn
)
7417 struct vmcs_config vmcs_conf
;
7420 if (setup_vmcs_config(&vmcs_conf
) < 0)
7422 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7423 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7424 smp_processor_id());
7429 static int get_ept_level(void)
7431 return VMX_EPT_DEFAULT_GAW
+ 1;
7434 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7438 /* For VT-d and EPT combination
7439 * 1. MMIO: always map as UC
7441 * a. VT-d without snooping control feature: can't guarantee the
7442 * result, try to trust guest.
7443 * b. VT-d with snooping control feature: snooping control feature of
7444 * VT-d engine can guarantee the cache correctness. Just set it
7445 * to WB to keep consistent with host. So the same as item 3.
7446 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7447 * consistent with host MTRR
7450 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7451 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
7452 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7453 VMX_EPT_MT_EPTE_SHIFT
;
7455 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7461 static int vmx_get_lpage_level(void)
7463 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7464 return PT_DIRECTORY_LEVEL
;
7466 /* For shadow and EPT supported 1GB page */
7467 return PT_PDPE_LEVEL
;
7470 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7472 struct kvm_cpuid_entry2
*best
;
7473 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7476 vmx
->rdtscp_enabled
= false;
7477 if (vmx_rdtscp_supported()) {
7478 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7479 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7480 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7481 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7482 vmx
->rdtscp_enabled
= true;
7484 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7485 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7491 /* Exposing INVPCID only when PCID is exposed */
7492 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7493 if (vmx_invpcid_supported() &&
7494 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7495 guest_cpuid_has_pcid(vcpu
)) {
7496 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7497 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7498 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7501 if (cpu_has_secondary_exec_ctrls()) {
7502 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7503 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7504 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7508 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7512 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7514 if (func
== 1 && nested
)
7515 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7518 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
7519 struct x86_exception
*fault
)
7521 struct vmcs12
*vmcs12
;
7522 nested_vmx_vmexit(vcpu
);
7523 vmcs12
= get_vmcs12(vcpu
);
7525 if (fault
->error_code
& PFERR_RSVD_MASK
)
7526 vmcs12
->vm_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
7528 vmcs12
->vm_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
7529 vmcs12
->exit_qualification
= vcpu
->arch
.exit_qualification
;
7530 vmcs12
->guest_physical_address
= fault
->address
;
7533 /* Callbacks for nested_ept_init_mmu_context: */
7535 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
7537 /* return the page table to be shadowed - in our case, EPT12 */
7538 return get_vmcs12(vcpu
)->ept_pointer
;
7541 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
7543 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
7544 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
7546 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
7547 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
7548 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
7550 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
7553 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
7555 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
7558 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
7559 struct x86_exception
*fault
)
7561 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7563 WARN_ON(!is_guest_mode(vcpu
));
7565 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7566 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
7567 nested_vmx_vmexit(vcpu
);
7569 kvm_inject_page_fault(vcpu
, fault
);
7573 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7574 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7575 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7576 * guest in a way that will both be appropriate to L1's requests, and our
7577 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7578 * function also has additional necessary side-effects, like setting various
7579 * vcpu->arch fields.
7581 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7583 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7587 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
7588 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
7589 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
7590 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
7591 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
7592 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
7593 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
7594 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
7595 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
7596 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
7597 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
7598 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
7599 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
7600 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
7601 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
7602 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
7603 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
7604 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
7605 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
7606 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
7607 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
7608 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
7609 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
7610 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
7611 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
7612 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
7613 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
7614 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
7615 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
7616 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
7617 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
7618 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
7619 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
7620 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
7621 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
7622 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
7624 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
7625 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
7626 vmcs12
->vm_entry_intr_info_field
);
7627 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
7628 vmcs12
->vm_entry_exception_error_code
);
7629 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
7630 vmcs12
->vm_entry_instruction_len
);
7631 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
7632 vmcs12
->guest_interruptibility_info
);
7633 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
7634 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
7635 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
7636 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
7637 vmcs12
->guest_pending_dbg_exceptions
);
7638 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
7639 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
7641 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7643 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
7644 (vmcs_config
.pin_based_exec_ctrl
|
7645 vmcs12
->pin_based_vm_exec_control
));
7647 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7648 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
,
7649 vmcs12
->vmx_preemption_timer_value
);
7652 * Whether page-faults are trapped is determined by a combination of
7653 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7654 * If enable_ept, L0 doesn't care about page faults and we should
7655 * set all of these to L1's desires. However, if !enable_ept, L0 does
7656 * care about (at least some) page faults, and because it is not easy
7657 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7658 * to exit on each and every L2 page fault. This is done by setting
7659 * MASK=MATCH=0 and (see below) EB.PF=1.
7660 * Note that below we don't need special code to set EB.PF beyond the
7661 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7662 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7663 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7665 * A problem with this approach (when !enable_ept) is that L1 may be
7666 * injected with more page faults than it asked for. This could have
7667 * caused problems, but in practice existing hypervisors don't care.
7668 * To fix this, we will need to emulate the PFEC checking (on the L1
7669 * page tables), using walk_addr(), when injecting PFs to L1.
7671 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
7672 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
7673 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
7674 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
7676 if (cpu_has_secondary_exec_ctrls()) {
7677 u32 exec_control
= vmx_secondary_exec_control(vmx
);
7678 if (!vmx
->rdtscp_enabled
)
7679 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7680 /* Take the following fields only from vmcs12 */
7681 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7682 if (nested_cpu_has(vmcs12
,
7683 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
7684 exec_control
|= vmcs12
->secondary_vm_exec_control
;
7686 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
7688 * Translate L1 physical address to host physical
7689 * address for vmcs02. Keep the page pinned, so this
7690 * physical address remains valid. We keep a reference
7691 * to it so we can release it later.
7693 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7694 nested_release_page(vmx
->nested
.apic_access_page
);
7695 vmx
->nested
.apic_access_page
=
7696 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7698 * If translation failed, no matter: This feature asks
7699 * to exit when accessing the given address, and if it
7700 * can never be accessed, this feature won't do
7703 if (!vmx
->nested
.apic_access_page
)
7705 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7707 vmcs_write64(APIC_ACCESS_ADDR
,
7708 page_to_phys(vmx
->nested
.apic_access_page
));
7711 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7716 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7717 * Some constant fields are set here by vmx_set_constant_host_state().
7718 * Other fields are different per CPU, and will be set later when
7719 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7721 vmx_set_constant_host_state(vmx
);
7724 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7725 * entry, but only if the current (host) sp changed from the value
7726 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7727 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7728 * here we just force the write to happen on entry.
7732 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
7733 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
7734 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
7735 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
7736 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
7738 * Merging of IO and MSR bitmaps not currently supported.
7739 * Rather, exit every time.
7741 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
7742 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
7743 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
7745 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
7747 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7748 * bitwise-or of what L1 wants to trap for L2, and what we want to
7749 * trap. Note that CR0.TS also needs updating - we do this later.
7751 update_exception_bitmap(vcpu
);
7752 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
7753 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7755 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7756 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7757 * bits are further modified by vmx_set_efer() below.
7759 exit_control
= vmcs_config
.vmexit_ctrl
;
7760 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7761 exit_control
|= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
7762 vmcs_write32(VM_EXIT_CONTROLS
, exit_control
);
7764 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7765 * emulated by vmx_set_efer(), below.
7767 vmcs_write32(VM_ENTRY_CONTROLS
,
7768 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
7769 ~VM_ENTRY_IA32E_MODE
) |
7770 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
7772 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
7773 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
7774 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
7775 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
7776 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
7779 set_cr4_guest_host_mask(vmx
);
7781 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
7782 vmcs_write64(TSC_OFFSET
,
7783 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
7785 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7789 * Trivially support vpid by letting L2s share their parent
7790 * L1's vpid. TODO: move to a more elaborate solution, giving
7791 * each L2 its own vpid and exposing the vpid feature to L1.
7793 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
7794 vmx_flush_tlb(vcpu
);
7797 if (nested_cpu_has_ept(vmcs12
)) {
7798 kvm_mmu_unload(vcpu
);
7799 nested_ept_init_mmu_context(vcpu
);
7802 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
7803 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
7804 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
7805 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7807 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7808 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7809 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7812 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7813 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7814 * The CR0_READ_SHADOW is what L2 should have expected to read given
7815 * the specifications by L1; It's not enough to take
7816 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7817 * have more bits than L1 expected.
7819 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
7820 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
7822 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
7823 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
7825 /* shadow page tables on either EPT or shadow page tables */
7826 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
7827 kvm_mmu_reset_context(vcpu
);
7830 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
7833 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7836 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
7837 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
7838 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
7839 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
7842 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
7843 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
7847 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7848 * for running an L2 nested guest.
7850 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
7852 struct vmcs12
*vmcs12
;
7853 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7855 struct loaded_vmcs
*vmcs02
;
7858 if (!nested_vmx_check_permission(vcpu
) ||
7859 !nested_vmx_check_vmcs12(vcpu
))
7862 skip_emulated_instruction(vcpu
);
7863 vmcs12
= get_vmcs12(vcpu
);
7865 if (enable_shadow_vmcs
)
7866 copy_shadow_to_vmcs12(vmx
);
7869 * The nested entry process starts with enforcing various prerequisites
7870 * on vmcs12 as required by the Intel SDM, and act appropriately when
7871 * they fail: As the SDM explains, some conditions should cause the
7872 * instruction to fail, while others will cause the instruction to seem
7873 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7874 * To speed up the normal (success) code path, we should avoid checking
7875 * for misconfigurations which will anyway be caught by the processor
7876 * when using the merged vmcs02.
7878 if (vmcs12
->launch_state
== launch
) {
7879 nested_vmx_failValid(vcpu
,
7880 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7881 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
7885 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
) {
7886 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7890 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
7891 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
7892 /*TODO: Also verify bits beyond physical address width are 0*/
7893 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7897 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
7898 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
7899 /*TODO: Also verify bits beyond physical address width are 0*/
7900 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7904 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
7905 vmcs12
->vm_exit_msr_load_count
> 0 ||
7906 vmcs12
->vm_exit_msr_store_count
> 0) {
7907 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7909 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7913 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
7914 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
7915 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
7916 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
7917 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
7918 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
7919 !vmx_control_verify(vmcs12
->vm_exit_controls
,
7920 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
7921 !vmx_control_verify(vmcs12
->vm_entry_controls
,
7922 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
7924 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7928 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
7929 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7930 nested_vmx_failValid(vcpu
,
7931 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
7935 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
7936 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7937 nested_vmx_entry_failure(vcpu
, vmcs12
,
7938 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7941 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
7942 nested_vmx_entry_failure(vcpu
, vmcs12
,
7943 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
7948 * If the load IA32_EFER VM-entry control is 1, the following checks
7949 * are performed on the field for the IA32_EFER MSR:
7950 * - Bits reserved in the IA32_EFER MSR must be 0.
7951 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7952 * the IA-32e mode guest VM-exit control. It must also be identical
7953 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7956 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
7957 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
7958 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
7959 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
7960 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
7961 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
7962 nested_vmx_entry_failure(vcpu
, vmcs12
,
7963 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7969 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7970 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7971 * the values of the LMA and LME bits in the field must each be that of
7972 * the host address-space size VM-exit control.
7974 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
7975 ia32e
= (vmcs12
->vm_exit_controls
&
7976 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
7977 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
7978 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
7979 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
7980 nested_vmx_entry_failure(vcpu
, vmcs12
,
7981 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7987 * We're finally done with prerequisite checking, and can start with
7991 vmcs02
= nested_get_current_vmcs02(vmx
);
7995 enter_guest_mode(vcpu
);
7997 vmx
->nested
.nested_run_pending
= 1;
7999 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
8002 vmx
->loaded_vmcs
= vmcs02
;
8004 vmx_vcpu_load(vcpu
, cpu
);
8008 vmx_segment_cache_clear(vmx
);
8010 vmcs12
->launch_state
= 1;
8012 prepare_vmcs02(vcpu
, vmcs12
);
8015 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8016 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8017 * returned as far as L1 is concerned. It will only return (and set
8018 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8024 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8025 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8026 * This function returns the new value we should put in vmcs12.guest_cr0.
8027 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8028 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8029 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8030 * didn't trap the bit, because if L1 did, so would L0).
8031 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8032 * been modified by L2, and L1 knows it. So just leave the old value of
8033 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8034 * isn't relevant, because if L0 traps this bit it can set it to anything.
8035 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8036 * changed these bits, and therefore they need to be updated, but L0
8037 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8038 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8040 static inline unsigned long
8041 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8044 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8045 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8046 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8047 vcpu
->arch
.cr0_guest_owned_bits
));
8050 static inline unsigned long
8051 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8054 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8055 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8056 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8057 vcpu
->arch
.cr4_guest_owned_bits
));
8060 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8061 struct vmcs12
*vmcs12
)
8066 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8067 nr
= vcpu
->arch
.exception
.nr
;
8068 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8070 if (kvm_exception_is_soft(nr
)) {
8071 vmcs12
->vm_exit_instruction_len
=
8072 vcpu
->arch
.event_exit_inst_len
;
8073 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8075 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8077 if (vcpu
->arch
.exception
.has_error_code
) {
8078 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8079 vmcs12
->idt_vectoring_error_code
=
8080 vcpu
->arch
.exception
.error_code
;
8083 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8084 } else if (vcpu
->arch
.nmi_injected
) {
8085 vmcs12
->idt_vectoring_info_field
=
8086 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8087 } else if (vcpu
->arch
.interrupt
.pending
) {
8088 nr
= vcpu
->arch
.interrupt
.nr
;
8089 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8091 if (vcpu
->arch
.interrupt
.soft
) {
8092 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8093 vmcs12
->vm_entry_instruction_len
=
8094 vcpu
->arch
.event_exit_inst_len
;
8096 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8098 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8103 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8104 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8105 * and this function updates it to reflect the changes to the guest state while
8106 * L2 was running (and perhaps made some exits which were handled directly by L0
8107 * without going back to L1), and to reflect the exit reason.
8108 * Note that we do not have to copy here all VMCS fields, just those that
8109 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8110 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8111 * which already writes to vmcs12 directly.
8113 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8115 /* update guest state fields: */
8116 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8117 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8119 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8120 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8121 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8122 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8124 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8125 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8126 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8127 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8128 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8129 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8130 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8131 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8132 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8133 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8134 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8135 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8136 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8137 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8138 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8139 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8140 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8141 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8142 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8143 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8144 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8145 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8146 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8147 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8148 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8149 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8150 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8151 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8152 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8153 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8154 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8155 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8156 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8157 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8158 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8159 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8161 vmcs12
->guest_interruptibility_info
=
8162 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8163 vmcs12
->guest_pending_dbg_exceptions
=
8164 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8166 if ((vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
) &&
8167 (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
))
8168 vmcs12
->vmx_preemption_timer_value
=
8169 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE
);
8172 * In some cases (usually, nested EPT), L2 is allowed to change its
8173 * own CR3 without exiting. If it has changed it, we must keep it.
8174 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8175 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8177 * Additionally, restore L2's PDPTR to vmcs12.
8180 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8181 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8182 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8183 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8184 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8187 vmcs12
->vm_entry_controls
=
8188 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8189 (vmcs_read32(VM_ENTRY_CONTROLS
) & VM_ENTRY_IA32E_MODE
);
8191 /* TODO: These cannot have changed unless we have MSR bitmaps and
8192 * the relevant bit asks not to trap the change */
8193 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8194 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8195 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8196 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8197 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8198 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8199 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8200 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8202 /* update exit information fields: */
8204 vmcs12
->vm_exit_reason
= to_vmx(vcpu
)->exit_reason
;
8205 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8207 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8208 if ((vmcs12
->vm_exit_intr_info
&
8209 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8210 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8211 vmcs12
->vm_exit_intr_error_code
=
8212 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8213 vmcs12
->idt_vectoring_info_field
= 0;
8214 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8215 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8217 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8218 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8219 * instead of reading the real value. */
8220 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8223 * Transfer the event that L0 or L1 may wanted to inject into
8224 * L2 to IDT_VECTORING_INFO_FIELD.
8226 vmcs12_save_pending_event(vcpu
, vmcs12
);
8230 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8231 * preserved above and would only end up incorrectly in L1.
8233 vcpu
->arch
.nmi_injected
= false;
8234 kvm_clear_exception_queue(vcpu
);
8235 kvm_clear_interrupt_queue(vcpu
);
8239 * A part of what we need to when the nested L2 guest exits and we want to
8240 * run its L1 parent, is to reset L1's guest state to the host state specified
8242 * This function is to be called not only on normal nested exit, but also on
8243 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8244 * Failures During or After Loading Guest State").
8245 * This function should be called when the active VMCS is L1's (vmcs01).
8247 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8248 struct vmcs12
*vmcs12
)
8250 struct kvm_segment seg
;
8252 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8253 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8254 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8255 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8257 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8258 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8260 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8261 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8262 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8264 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8265 * actually changed, because it depends on the current state of
8266 * fpu_active (which may have changed).
8267 * Note that vmx_set_cr0 refers to efer set above.
8269 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8271 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8272 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8273 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8275 update_exception_bitmap(vcpu
);
8276 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8277 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8280 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8281 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8283 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8284 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
8286 if (nested_cpu_has_ept(vmcs12
))
8287 nested_ept_uninit_mmu_context(vcpu
);
8289 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8290 kvm_mmu_reset_context(vcpu
);
8293 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
8297 * Trivially support vpid by letting L2s share their parent
8298 * L1's vpid. TODO: move to a more elaborate solution, giving
8299 * each L2 its own vpid and exposing the vpid feature to L1.
8301 vmx_flush_tlb(vcpu
);
8305 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8306 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8307 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8308 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8309 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8311 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
8312 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8313 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
8315 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8316 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8317 vmcs12
->host_ia32_perf_global_ctrl
);
8319 /* Set L1 segment info according to Intel SDM
8320 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8321 seg
= (struct kvm_segment
) {
8323 .limit
= 0xFFFFFFFF,
8324 .selector
= vmcs12
->host_cs_selector
,
8330 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8334 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
8335 seg
= (struct kvm_segment
) {
8337 .limit
= 0xFFFFFFFF,
8344 seg
.selector
= vmcs12
->host_ds_selector
;
8345 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
8346 seg
.selector
= vmcs12
->host_es_selector
;
8347 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
8348 seg
.selector
= vmcs12
->host_ss_selector
;
8349 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
8350 seg
.selector
= vmcs12
->host_fs_selector
;
8351 seg
.base
= vmcs12
->host_fs_base
;
8352 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
8353 seg
.selector
= vmcs12
->host_gs_selector
;
8354 seg
.base
= vmcs12
->host_gs_base
;
8355 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
8356 seg
= (struct kvm_segment
) {
8357 .base
= vmcs12
->host_tr_base
,
8359 .selector
= vmcs12
->host_tr_selector
,
8363 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
8365 kvm_set_dr(vcpu
, 7, 0x400);
8366 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8370 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8371 * and modify vmcs12 to make it see what it would expect to see there if
8372 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8374 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
8376 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8378 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8380 /* trying to cancel vmlaunch/vmresume is a bug */
8381 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8383 leave_guest_mode(vcpu
);
8384 prepare_vmcs12(vcpu
, vmcs12
);
8387 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8389 vmx_vcpu_load(vcpu
, cpu
);
8393 vmx_segment_cache_clear(vmx
);
8395 /* if no vmcs02 cache requested, remove the one we used */
8396 if (VMCS02_POOL_SIZE
== 0)
8397 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8399 load_vmcs12_host_state(vcpu
, vmcs12
);
8401 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8402 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8404 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8407 /* Unpin physical memory we referred to in vmcs02 */
8408 if (vmx
->nested
.apic_access_page
) {
8409 nested_release_page(vmx
->nested
.apic_access_page
);
8410 vmx
->nested
.apic_access_page
= 0;
8414 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8415 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8416 * success or failure flag accordingly.
8418 if (unlikely(vmx
->fail
)) {
8420 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
8422 nested_vmx_succeed(vcpu
);
8423 if (enable_shadow_vmcs
)
8424 vmx
->nested
.sync_shadow_vmcs
= true;
8428 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8429 * 23.7 "VM-entry failures during or after loading guest state" (this also
8430 * lists the acceptable exit-reason and exit-qualification parameters).
8431 * It should only be called before L2 actually succeeded to run, and when
8432 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8434 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
8435 struct vmcs12
*vmcs12
,
8436 u32 reason
, unsigned long qualification
)
8438 load_vmcs12_host_state(vcpu
, vmcs12
);
8439 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
8440 vmcs12
->exit_qualification
= qualification
;
8441 nested_vmx_succeed(vcpu
);
8442 if (enable_shadow_vmcs
)
8443 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
8446 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
8447 struct x86_instruction_info
*info
,
8448 enum x86_intercept_stage stage
)
8450 return X86EMUL_CONTINUE
;
8453 static struct kvm_x86_ops vmx_x86_ops
= {
8454 .cpu_has_kvm_support
= cpu_has_kvm_support
,
8455 .disabled_by_bios
= vmx_disabled_by_bios
,
8456 .hardware_setup
= hardware_setup
,
8457 .hardware_unsetup
= hardware_unsetup
,
8458 .check_processor_compatibility
= vmx_check_processor_compat
,
8459 .hardware_enable
= hardware_enable
,
8460 .hardware_disable
= hardware_disable
,
8461 .cpu_has_accelerated_tpr
= report_flexpriority
,
8463 .vcpu_create
= vmx_create_vcpu
,
8464 .vcpu_free
= vmx_free_vcpu
,
8465 .vcpu_reset
= vmx_vcpu_reset
,
8467 .prepare_guest_switch
= vmx_save_host_state
,
8468 .vcpu_load
= vmx_vcpu_load
,
8469 .vcpu_put
= vmx_vcpu_put
,
8471 .update_db_bp_intercept
= update_exception_bitmap
,
8472 .get_msr
= vmx_get_msr
,
8473 .set_msr
= vmx_set_msr
,
8474 .get_segment_base
= vmx_get_segment_base
,
8475 .get_segment
= vmx_get_segment
,
8476 .set_segment
= vmx_set_segment
,
8477 .get_cpl
= vmx_get_cpl
,
8478 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
8479 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
8480 .decache_cr3
= vmx_decache_cr3
,
8481 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
8482 .set_cr0
= vmx_set_cr0
,
8483 .set_cr3
= vmx_set_cr3
,
8484 .set_cr4
= vmx_set_cr4
,
8485 .set_efer
= vmx_set_efer
,
8486 .get_idt
= vmx_get_idt
,
8487 .set_idt
= vmx_set_idt
,
8488 .get_gdt
= vmx_get_gdt
,
8489 .set_gdt
= vmx_set_gdt
,
8490 .set_dr7
= vmx_set_dr7
,
8491 .cache_reg
= vmx_cache_reg
,
8492 .get_rflags
= vmx_get_rflags
,
8493 .set_rflags
= vmx_set_rflags
,
8494 .fpu_activate
= vmx_fpu_activate
,
8495 .fpu_deactivate
= vmx_fpu_deactivate
,
8497 .tlb_flush
= vmx_flush_tlb
,
8499 .run
= vmx_vcpu_run
,
8500 .handle_exit
= vmx_handle_exit
,
8501 .skip_emulated_instruction
= skip_emulated_instruction
,
8502 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
8503 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
8504 .patch_hypercall
= vmx_patch_hypercall
,
8505 .set_irq
= vmx_inject_irq
,
8506 .set_nmi
= vmx_inject_nmi
,
8507 .queue_exception
= vmx_queue_exception
,
8508 .cancel_injection
= vmx_cancel_injection
,
8509 .interrupt_allowed
= vmx_interrupt_allowed
,
8510 .nmi_allowed
= vmx_nmi_allowed
,
8511 .get_nmi_mask
= vmx_get_nmi_mask
,
8512 .set_nmi_mask
= vmx_set_nmi_mask
,
8513 .enable_nmi_window
= enable_nmi_window
,
8514 .enable_irq_window
= enable_irq_window
,
8515 .update_cr8_intercept
= update_cr8_intercept
,
8516 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
8517 .vm_has_apicv
= vmx_vm_has_apicv
,
8518 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
8519 .hwapic_irr_update
= vmx_hwapic_irr_update
,
8520 .hwapic_isr_update
= vmx_hwapic_isr_update
,
8521 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
8522 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
8524 .set_tss_addr
= vmx_set_tss_addr
,
8525 .get_tdp_level
= get_ept_level
,
8526 .get_mt_mask
= vmx_get_mt_mask
,
8528 .get_exit_info
= vmx_get_exit_info
,
8530 .get_lpage_level
= vmx_get_lpage_level
,
8532 .cpuid_update
= vmx_cpuid_update
,
8534 .rdtscp_supported
= vmx_rdtscp_supported
,
8535 .invpcid_supported
= vmx_invpcid_supported
,
8537 .set_supported_cpuid
= vmx_set_supported_cpuid
,
8539 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
8541 .set_tsc_khz
= vmx_set_tsc_khz
,
8542 .read_tsc_offset
= vmx_read_tsc_offset
,
8543 .write_tsc_offset
= vmx_write_tsc_offset
,
8544 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
8545 .compute_tsc_offset
= vmx_compute_tsc_offset
,
8546 .read_l1_tsc
= vmx_read_l1_tsc
,
8548 .set_tdp_cr3
= vmx_set_cr3
,
8550 .check_intercept
= vmx_check_intercept
,
8551 .handle_external_intr
= vmx_handle_external_intr
,
8554 static int __init
vmx_init(void)
8558 rdmsrl_safe(MSR_EFER
, &host_efer
);
8560 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
8561 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
8563 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8564 if (!vmx_io_bitmap_a
)
8569 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8570 if (!vmx_io_bitmap_b
)
8573 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8574 if (!vmx_msr_bitmap_legacy
)
8577 vmx_msr_bitmap_legacy_x2apic
=
8578 (unsigned long *)__get_free_page(GFP_KERNEL
);
8579 if (!vmx_msr_bitmap_legacy_x2apic
)
8582 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8583 if (!vmx_msr_bitmap_longmode
)
8586 vmx_msr_bitmap_longmode_x2apic
=
8587 (unsigned long *)__get_free_page(GFP_KERNEL
);
8588 if (!vmx_msr_bitmap_longmode_x2apic
)
8590 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8591 if (!vmx_vmread_bitmap
)
8594 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8595 if (!vmx_vmwrite_bitmap
)
8598 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
8599 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
8600 /* shadowed read/write fields */
8601 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
8602 clear_bit(shadow_read_write_fields
[i
], vmx_vmwrite_bitmap
);
8603 clear_bit(shadow_read_write_fields
[i
], vmx_vmread_bitmap
);
8605 /* shadowed read only fields */
8606 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
8607 clear_bit(shadow_read_only_fields
[i
], vmx_vmread_bitmap
);
8610 * Allow direct access to the PC debug port (it is often used for I/O
8611 * delays, but the vmexits simply slow things down).
8613 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
8614 clear_bit(0x80, vmx_io_bitmap_a
);
8616 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
8618 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
8619 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
8621 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
8623 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
8624 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
8629 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
8630 crash_vmclear_local_loaded_vmcss
);
8633 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
8634 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
8635 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
8636 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
8637 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
8638 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
8639 memcpy(vmx_msr_bitmap_legacy_x2apic
,
8640 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
8641 memcpy(vmx_msr_bitmap_longmode_x2apic
,
8642 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
8645 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8646 vmx_disable_intercept_msr_read_x2apic(msr
);
8648 /* According SDM, in x2apic mode, the whole id reg is used.
8649 * But in KVM, it only use the highest eight bits. Need to
8651 vmx_enable_intercept_msr_read_x2apic(0x802);
8653 vmx_enable_intercept_msr_read_x2apic(0x839);
8655 vmx_disable_intercept_msr_write_x2apic(0x808);
8657 vmx_disable_intercept_msr_write_x2apic(0x80b);
8659 vmx_disable_intercept_msr_write_x2apic(0x83f);
8663 kvm_mmu_set_mask_ptes(0ull,
8664 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
8665 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
8666 0ull, VMX_EPT_EXECUTABLE_MASK
);
8667 ept_set_mmio_spte_mask();
8675 free_page((unsigned long)vmx_vmwrite_bitmap
);
8677 free_page((unsigned long)vmx_vmread_bitmap
);
8679 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8681 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8683 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8685 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8687 free_page((unsigned long)vmx_io_bitmap_b
);
8689 free_page((unsigned long)vmx_io_bitmap_a
);
8693 static void __exit
vmx_exit(void)
8695 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8696 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8697 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8698 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8699 free_page((unsigned long)vmx_io_bitmap_b
);
8700 free_page((unsigned long)vmx_io_bitmap_a
);
8701 free_page((unsigned long)vmx_vmwrite_bitmap
);
8702 free_page((unsigned long)vmx_vmread_bitmap
);
8705 rcu_assign_pointer(crash_vmclear_loaded_vmcss
, NULL
);
8712 module_init(vmx_init
)
8713 module_exit(vmx_exit
)