2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
64 static const struct x86_cpu_id vmx_cpu_id
[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
68 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
70 static bool __read_mostly enable_vpid
= 1;
71 module_param_named(vpid
, enable_vpid
, bool, 0444);
73 static bool __read_mostly flexpriority_enabled
= 1;
74 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
76 static bool __read_mostly enable_ept
= 1;
77 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
79 static bool __read_mostly enable_unrestricted_guest
= 1;
80 module_param_named(unrestricted_guest
,
81 enable_unrestricted_guest
, bool, S_IRUGO
);
83 static bool __read_mostly enable_ept_ad_bits
= 1;
84 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
86 static bool __read_mostly emulate_invalid_guest_state
= true;
87 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
89 static bool __read_mostly fasteoi
= 1;
90 module_param(fasteoi
, bool, S_IRUGO
);
92 static bool __read_mostly enable_apicv
= 1;
93 module_param(enable_apicv
, bool, S_IRUGO
);
95 static bool __read_mostly enable_shadow_vmcs
= 1;
96 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested
= 0;
103 module_param(nested
, bool, S_IRUGO
);
105 static u64 __read_mostly host_xss
;
107 static bool __read_mostly enable_pml
= 1;
108 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113 static int __read_mostly cpu_preemption_timer_multi
;
114 static bool __read_mostly enable_preemption_timer
= 1;
116 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
121 #define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
123 #define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
125 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
138 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
148 * According to test, this time is usually smaller than 128 cycles.
149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
155 #define KVM_VMX_DEFAULT_PLE_GAP 128
156 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
162 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
163 module_param(ple_gap
, int, S_IRUGO
);
165 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
166 module_param(ple_window
, int, S_IRUGO
);
168 /* Default doubles per-vcpu window every exit. */
169 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
170 module_param(ple_window_grow
, int, S_IRUGO
);
172 /* Default resets per-vcpu window every exit to ple_window. */
173 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
174 module_param(ple_window_shrink
, int, S_IRUGO
);
176 /* Default is to compute the maximum so we can never overflow. */
177 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
178 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 module_param(ple_window_max
, int, S_IRUGO
);
181 extern const ulong vmx_return
;
183 #define NR_AUTOLOAD_MSRS 8
184 #define VMCS02_POOL_SIZE 1
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
199 struct vmcs
*shadow_vmcs
;
202 bool nmi_known_unmasked
;
203 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
204 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
205 struct list_head loaded_vmcss_on_cpu_link
;
208 struct shared_msr_entry
{
215 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
216 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
217 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
218 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
219 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
220 * More than one of these structures may exist, if L1 runs multiple L2 guests.
221 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
222 * underlying hardware which will be used to run L2.
223 * This structure is packed to ensure that its layout is identical across
224 * machines (necessary for live migration).
225 * If there are changes in this struct, VMCS12_REVISION must be changed.
227 typedef u64 natural_width
;
228 struct __packed vmcs12
{
229 /* According to the Intel spec, a VMCS region must start with the
230 * following two fields. Then follow implementation-specific data.
235 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
236 u32 padding
[7]; /* room for future expansion */
241 u64 vm_exit_msr_store_addr
;
242 u64 vm_exit_msr_load_addr
;
243 u64 vm_entry_msr_load_addr
;
245 u64 virtual_apic_page_addr
;
246 u64 apic_access_addr
;
247 u64 posted_intr_desc_addr
;
248 u64 vm_function_control
;
250 u64 eoi_exit_bitmap0
;
251 u64 eoi_exit_bitmap1
;
252 u64 eoi_exit_bitmap2
;
253 u64 eoi_exit_bitmap3
;
254 u64 eptp_list_address
;
256 u64 guest_physical_address
;
257 u64 vmcs_link_pointer
;
259 u64 guest_ia32_debugctl
;
262 u64 guest_ia32_perf_global_ctrl
;
270 u64 host_ia32_perf_global_ctrl
;
271 u64 padding64
[8]; /* room for future expansion */
273 * To allow migration of L1 (complete with its L2 guests) between
274 * machines of different natural widths (32 or 64 bit), we cannot have
275 * unsigned long fields with no explict size. We use u64 (aliased
276 * natural_width) instead. Luckily, x86 is little-endian.
278 natural_width cr0_guest_host_mask
;
279 natural_width cr4_guest_host_mask
;
280 natural_width cr0_read_shadow
;
281 natural_width cr4_read_shadow
;
282 natural_width cr3_target_value0
;
283 natural_width cr3_target_value1
;
284 natural_width cr3_target_value2
;
285 natural_width cr3_target_value3
;
286 natural_width exit_qualification
;
287 natural_width guest_linear_address
;
288 natural_width guest_cr0
;
289 natural_width guest_cr3
;
290 natural_width guest_cr4
;
291 natural_width guest_es_base
;
292 natural_width guest_cs_base
;
293 natural_width guest_ss_base
;
294 natural_width guest_ds_base
;
295 natural_width guest_fs_base
;
296 natural_width guest_gs_base
;
297 natural_width guest_ldtr_base
;
298 natural_width guest_tr_base
;
299 natural_width guest_gdtr_base
;
300 natural_width guest_idtr_base
;
301 natural_width guest_dr7
;
302 natural_width guest_rsp
;
303 natural_width guest_rip
;
304 natural_width guest_rflags
;
305 natural_width guest_pending_dbg_exceptions
;
306 natural_width guest_sysenter_esp
;
307 natural_width guest_sysenter_eip
;
308 natural_width host_cr0
;
309 natural_width host_cr3
;
310 natural_width host_cr4
;
311 natural_width host_fs_base
;
312 natural_width host_gs_base
;
313 natural_width host_tr_base
;
314 natural_width host_gdtr_base
;
315 natural_width host_idtr_base
;
316 natural_width host_ia32_sysenter_esp
;
317 natural_width host_ia32_sysenter_eip
;
318 natural_width host_rsp
;
319 natural_width host_rip
;
320 natural_width paddingl
[8]; /* room for future expansion */
321 u32 pin_based_vm_exec_control
;
322 u32 cpu_based_vm_exec_control
;
323 u32 exception_bitmap
;
324 u32 page_fault_error_code_mask
;
325 u32 page_fault_error_code_match
;
326 u32 cr3_target_count
;
327 u32 vm_exit_controls
;
328 u32 vm_exit_msr_store_count
;
329 u32 vm_exit_msr_load_count
;
330 u32 vm_entry_controls
;
331 u32 vm_entry_msr_load_count
;
332 u32 vm_entry_intr_info_field
;
333 u32 vm_entry_exception_error_code
;
334 u32 vm_entry_instruction_len
;
336 u32 secondary_vm_exec_control
;
337 u32 vm_instruction_error
;
339 u32 vm_exit_intr_info
;
340 u32 vm_exit_intr_error_code
;
341 u32 idt_vectoring_info_field
;
342 u32 idt_vectoring_error_code
;
343 u32 vm_exit_instruction_len
;
344 u32 vmx_instruction_info
;
351 u32 guest_ldtr_limit
;
353 u32 guest_gdtr_limit
;
354 u32 guest_idtr_limit
;
355 u32 guest_es_ar_bytes
;
356 u32 guest_cs_ar_bytes
;
357 u32 guest_ss_ar_bytes
;
358 u32 guest_ds_ar_bytes
;
359 u32 guest_fs_ar_bytes
;
360 u32 guest_gs_ar_bytes
;
361 u32 guest_ldtr_ar_bytes
;
362 u32 guest_tr_ar_bytes
;
363 u32 guest_interruptibility_info
;
364 u32 guest_activity_state
;
365 u32 guest_sysenter_cs
;
366 u32 host_ia32_sysenter_cs
;
367 u32 vmx_preemption_timer_value
;
368 u32 padding32
[7]; /* room for future expansion */
369 u16 virtual_processor_id
;
371 u16 guest_es_selector
;
372 u16 guest_cs_selector
;
373 u16 guest_ss_selector
;
374 u16 guest_ds_selector
;
375 u16 guest_fs_selector
;
376 u16 guest_gs_selector
;
377 u16 guest_ldtr_selector
;
378 u16 guest_tr_selector
;
379 u16 guest_intr_status
;
381 u16 host_es_selector
;
382 u16 host_cs_selector
;
383 u16 host_ss_selector
;
384 u16 host_ds_selector
;
385 u16 host_fs_selector
;
386 u16 host_gs_selector
;
387 u16 host_tr_selector
;
391 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
392 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
393 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
395 #define VMCS12_REVISION 0x11e57ed0
398 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
399 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
400 * current implementation, 4K are reserved to avoid future complications.
402 #define VMCS12_SIZE 0x1000
404 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
406 struct list_head list
;
408 struct loaded_vmcs vmcs02
;
412 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
413 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
416 /* Has the level1 guest done vmxon? */
421 /* The guest-physical address of the current VMCS L1 keeps for L2 */
424 * Cache of the guest's VMCS, existing outside of guest memory.
425 * Loaded from guest memory during VMPTRLD. Flushed to guest
426 * memory during VMCLEAR and VMPTRLD.
428 struct vmcs12
*cached_vmcs12
;
430 * Indicates if the shadow vmcs must be updated with the
431 * data hold by vmcs12
433 bool sync_shadow_vmcs
;
435 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
436 struct list_head vmcs02_pool
;
438 bool change_vmcs01_virtual_x2apic_mode
;
439 /* L2 must run next, and mustn't decide to exit to L1. */
440 bool nested_run_pending
;
442 * Guest pages referred to in vmcs02 with host-physical pointers, so
443 * we must keep them pinned while L2 runs.
445 struct page
*apic_access_page
;
446 struct page
*virtual_apic_page
;
447 struct page
*pi_desc_page
;
448 struct pi_desc
*pi_desc
;
452 unsigned long *msr_bitmap
;
454 struct hrtimer preemption_timer
;
455 bool preemption_timer_expired
;
457 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
464 * We only store the "true" versions of the VMX capability MSRs. We
465 * generate the "non-true" versions by setting the must-be-1 bits
466 * according to the SDM.
468 u32 nested_vmx_procbased_ctls_low
;
469 u32 nested_vmx_procbased_ctls_high
;
470 u32 nested_vmx_secondary_ctls_low
;
471 u32 nested_vmx_secondary_ctls_high
;
472 u32 nested_vmx_pinbased_ctls_low
;
473 u32 nested_vmx_pinbased_ctls_high
;
474 u32 nested_vmx_exit_ctls_low
;
475 u32 nested_vmx_exit_ctls_high
;
476 u32 nested_vmx_entry_ctls_low
;
477 u32 nested_vmx_entry_ctls_high
;
478 u32 nested_vmx_misc_low
;
479 u32 nested_vmx_misc_high
;
480 u32 nested_vmx_ept_caps
;
481 u32 nested_vmx_vpid_caps
;
482 u64 nested_vmx_basic
;
483 u64 nested_vmx_cr0_fixed0
;
484 u64 nested_vmx_cr0_fixed1
;
485 u64 nested_vmx_cr4_fixed0
;
486 u64 nested_vmx_cr4_fixed1
;
487 u64 nested_vmx_vmcs_enum
;
488 u64 nested_vmx_vmfunc_controls
;
491 #define POSTED_INTR_ON 0
492 #define POSTED_INTR_SN 1
494 /* Posted-Interrupt Descriptor */
496 u32 pir
[8]; /* Posted interrupt requested */
499 /* bit 256 - Outstanding Notification */
501 /* bit 257 - Suppress Notification */
503 /* bit 271:258 - Reserved */
505 /* bit 279:272 - Notification Vector */
507 /* bit 287:280 - Reserved */
509 /* bit 319:288 - Notification Destination */
517 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
519 return test_and_set_bit(POSTED_INTR_ON
,
520 (unsigned long *)&pi_desc
->control
);
523 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
525 return test_and_clear_bit(POSTED_INTR_ON
,
526 (unsigned long *)&pi_desc
->control
);
529 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
531 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
534 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
536 return clear_bit(POSTED_INTR_SN
,
537 (unsigned long *)&pi_desc
->control
);
540 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
542 return set_bit(POSTED_INTR_SN
,
543 (unsigned long *)&pi_desc
->control
);
546 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
548 clear_bit(POSTED_INTR_ON
,
549 (unsigned long *)&pi_desc
->control
);
552 static inline int pi_test_on(struct pi_desc
*pi_desc
)
554 return test_bit(POSTED_INTR_ON
,
555 (unsigned long *)&pi_desc
->control
);
558 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
560 return test_bit(POSTED_INTR_SN
,
561 (unsigned long *)&pi_desc
->control
);
565 struct kvm_vcpu vcpu
;
566 unsigned long host_rsp
;
569 u32 idt_vectoring_info
;
571 struct shared_msr_entry
*guest_msrs
;
574 unsigned long host_idt_base
;
576 u64 msr_host_kernel_gs_base
;
577 u64 msr_guest_kernel_gs_base
;
579 u32 vm_entry_controls_shadow
;
580 u32 vm_exit_controls_shadow
;
581 u32 secondary_exec_control
;
584 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
585 * non-nested (L1) guest, it always points to vmcs01. For a nested
586 * guest (L2), it points to a different VMCS.
588 struct loaded_vmcs vmcs01
;
589 struct loaded_vmcs
*loaded_vmcs
;
590 bool __launched
; /* temporary, used in vmx_vcpu_run */
591 struct msr_autoload
{
593 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
594 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
598 u16 fs_sel
, gs_sel
, ldt_sel
;
602 int gs_ldt_reload_needed
;
603 int fs_reload_needed
;
604 u64 msr_host_bndcfgs
;
609 struct kvm_segment segs
[8];
612 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
613 struct kvm_save_segment
{
621 bool emulation_required
;
625 /* Posted interrupt descriptor */
626 struct pi_desc pi_desc
;
628 /* Support for a guest hypervisor (nested VMX) */
629 struct nested_vmx nested
;
631 /* Dynamic PLE window. */
633 bool ple_window_dirty
;
635 /* Support for PML */
636 #define PML_ENTITY_NUM 512
639 /* apic deadline value in host tsc */
642 u64 current_tsc_ratio
;
647 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
648 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
649 * in msr_ia32_feature_control_valid_bits.
651 u64 msr_ia32_feature_control
;
652 u64 msr_ia32_feature_control_valid_bits
;
655 enum segment_cache_field
{
664 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
666 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
669 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
671 return &(to_vmx(vcpu
)->pi_desc
);
674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
675 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
676 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
677 [number##_HIGH] = VMCS12_OFFSET(name)+4
680 static unsigned long shadow_read_only_fields
[] = {
682 * We do NOT shadow fields that are modified when L0
683 * traps and emulates any vmx instruction (e.g. VMPTRLD,
684 * VMXON...) executed by L1.
685 * For example, VM_INSTRUCTION_ERROR is read
686 * by L1 if a vmx instruction fails (part of the error path).
687 * Note the code assumes this logic. If for some reason
688 * we start shadowing these fields then we need to
689 * force a shadow sync when L0 emulates vmx instructions
690 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
691 * by nested_vmx_failValid)
695 VM_EXIT_INSTRUCTION_LEN
,
696 IDT_VECTORING_INFO_FIELD
,
697 IDT_VECTORING_ERROR_CODE
,
698 VM_EXIT_INTR_ERROR_CODE
,
700 GUEST_LINEAR_ADDRESS
,
701 GUEST_PHYSICAL_ADDRESS
703 static int max_shadow_read_only_fields
=
704 ARRAY_SIZE(shadow_read_only_fields
);
706 static unsigned long shadow_read_write_fields
[] = {
713 GUEST_INTERRUPTIBILITY_INFO
,
726 CPU_BASED_VM_EXEC_CONTROL
,
727 VM_ENTRY_EXCEPTION_ERROR_CODE
,
728 VM_ENTRY_INTR_INFO_FIELD
,
729 VM_ENTRY_INSTRUCTION_LEN
,
730 VM_ENTRY_EXCEPTION_ERROR_CODE
,
736 static int max_shadow_read_write_fields
=
737 ARRAY_SIZE(shadow_read_write_fields
);
739 static const unsigned short vmcs_field_to_offset_table
[] = {
740 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
741 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
742 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
743 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
744 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
745 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
746 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
747 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
748 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
749 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
750 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
751 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
752 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
753 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
754 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
755 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
756 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
757 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
758 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
759 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
760 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
761 FIELD64(MSR_BITMAP
, msr_bitmap
),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
765 FIELD64(TSC_OFFSET
, tsc_offset
),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
767 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
768 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
769 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
770 FIELD64(EPT_POINTER
, ept_pointer
),
771 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
772 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
773 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
774 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
775 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
776 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
777 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
778 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
779 FIELD64(PML_ADDRESS
, pml_address
),
780 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
781 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
782 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
783 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
784 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
785 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
786 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
787 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
788 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
789 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
790 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
791 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
792 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
793 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
794 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
795 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
796 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
797 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
798 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
799 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
800 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
801 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
802 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
803 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
804 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
805 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
806 FIELD(TPR_THRESHOLD
, tpr_threshold
),
807 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
808 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
809 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
810 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
811 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
812 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
813 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
814 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
815 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
816 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
817 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
818 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
819 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
820 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
821 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
822 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
823 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
824 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
825 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
826 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
827 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
828 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
829 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
830 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
831 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
832 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
833 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
834 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
835 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
836 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
837 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
838 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
839 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
840 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
841 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
842 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
843 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
844 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
845 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
846 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
847 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
848 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
849 FIELD(GUEST_CR0
, guest_cr0
),
850 FIELD(GUEST_CR3
, guest_cr3
),
851 FIELD(GUEST_CR4
, guest_cr4
),
852 FIELD(GUEST_ES_BASE
, guest_es_base
),
853 FIELD(GUEST_CS_BASE
, guest_cs_base
),
854 FIELD(GUEST_SS_BASE
, guest_ss_base
),
855 FIELD(GUEST_DS_BASE
, guest_ds_base
),
856 FIELD(GUEST_FS_BASE
, guest_fs_base
),
857 FIELD(GUEST_GS_BASE
, guest_gs_base
),
858 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
859 FIELD(GUEST_TR_BASE
, guest_tr_base
),
860 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
861 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
862 FIELD(GUEST_DR7
, guest_dr7
),
863 FIELD(GUEST_RSP
, guest_rsp
),
864 FIELD(GUEST_RIP
, guest_rip
),
865 FIELD(GUEST_RFLAGS
, guest_rflags
),
866 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
867 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
868 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
869 FIELD(HOST_CR0
, host_cr0
),
870 FIELD(HOST_CR3
, host_cr3
),
871 FIELD(HOST_CR4
, host_cr4
),
872 FIELD(HOST_FS_BASE
, host_fs_base
),
873 FIELD(HOST_GS_BASE
, host_gs_base
),
874 FIELD(HOST_TR_BASE
, host_tr_base
),
875 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
876 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
877 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
878 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
879 FIELD(HOST_RSP
, host_rsp
),
880 FIELD(HOST_RIP
, host_rip
),
883 static inline short vmcs_field_to_offset(unsigned long field
)
885 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
887 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
888 vmcs_field_to_offset_table
[field
] == 0)
891 return vmcs_field_to_offset_table
[field
];
894 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
896 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
899 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
900 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
901 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
902 static bool vmx_xsaves_supported(void);
903 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
904 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
905 struct kvm_segment
*var
, int seg
);
906 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
907 struct kvm_segment
*var
, int seg
);
908 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
909 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
910 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
911 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
912 static int alloc_identity_pagetable(struct kvm
*kvm
);
913 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
914 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
915 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
918 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
919 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
921 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
922 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
924 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
927 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
928 * can find which vCPU should be waken up.
930 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
931 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
936 VMX_MSR_BITMAP_LEGACY
,
937 VMX_MSR_BITMAP_LONGMODE
,
938 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
939 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
940 VMX_MSR_BITMAP_LEGACY_X2APIC
,
941 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
947 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
949 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
950 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
951 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
952 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
953 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
954 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
955 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
956 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
957 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
958 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
960 static bool cpu_has_load_ia32_efer
;
961 static bool cpu_has_load_perf_global_ctrl
;
963 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
964 static DEFINE_SPINLOCK(vmx_vpid_lock
);
966 static struct vmcs_config
{
971 u32 pin_based_exec_ctrl
;
972 u32 cpu_based_exec_ctrl
;
973 u32 cpu_based_2nd_exec_ctrl
;
978 static struct vmx_capability
{
983 #define VMX_SEGMENT_FIELD(seg) \
984 [VCPU_SREG_##seg] = { \
985 .selector = GUEST_##seg##_SELECTOR, \
986 .base = GUEST_##seg##_BASE, \
987 .limit = GUEST_##seg##_LIMIT, \
988 .ar_bytes = GUEST_##seg##_AR_BYTES, \
991 static const struct kvm_vmx_segment_field
{
996 } kvm_vmx_segment_fields
[] = {
997 VMX_SEGMENT_FIELD(CS
),
998 VMX_SEGMENT_FIELD(DS
),
999 VMX_SEGMENT_FIELD(ES
),
1000 VMX_SEGMENT_FIELD(FS
),
1001 VMX_SEGMENT_FIELD(GS
),
1002 VMX_SEGMENT_FIELD(SS
),
1003 VMX_SEGMENT_FIELD(TR
),
1004 VMX_SEGMENT_FIELD(LDTR
),
1007 static u64 host_efer
;
1009 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1012 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1013 * away by decrementing the array size.
1015 static const u32 vmx_msr_index
[] = {
1016 #ifdef CONFIG_X86_64
1017 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1019 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1022 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1024 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1025 INTR_INFO_VALID_MASK
)) ==
1026 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1029 static inline bool is_debug(u32 intr_info
)
1031 return is_exception_n(intr_info
, DB_VECTOR
);
1034 static inline bool is_breakpoint(u32 intr_info
)
1036 return is_exception_n(intr_info
, BP_VECTOR
);
1039 static inline bool is_page_fault(u32 intr_info
)
1041 return is_exception_n(intr_info
, PF_VECTOR
);
1044 static inline bool is_no_device(u32 intr_info
)
1046 return is_exception_n(intr_info
, NM_VECTOR
);
1049 static inline bool is_invalid_opcode(u32 intr_info
)
1051 return is_exception_n(intr_info
, UD_VECTOR
);
1054 static inline bool is_external_interrupt(u32 intr_info
)
1056 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1057 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1060 static inline bool is_machine_check(u32 intr_info
)
1062 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1063 INTR_INFO_VALID_MASK
)) ==
1064 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1067 static inline bool cpu_has_vmx_msr_bitmap(void)
1069 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1072 static inline bool cpu_has_vmx_tpr_shadow(void)
1074 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1077 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1079 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1082 static inline bool cpu_has_secondary_exec_ctrls(void)
1084 return vmcs_config
.cpu_based_exec_ctrl
&
1085 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1088 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1090 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1091 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1094 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1096 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1097 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1100 static inline bool cpu_has_vmx_apic_register_virt(void)
1102 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1103 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1106 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1108 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1109 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1113 * Comment's format: document - errata name - stepping - processor name.
1115 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1117 static u32 vmx_preemption_cpu_tfms
[] = {
1118 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1120 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1121 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1122 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1124 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1126 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1127 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1129 * 320767.pdf - AAP86 - B1 -
1130 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1133 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1135 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1137 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1139 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1140 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1141 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1145 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1147 u32 eax
= cpuid_eax(0x00000001), i
;
1149 /* Clear the reserved bits */
1150 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1151 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1152 if (eax
== vmx_preemption_cpu_tfms
[i
])
1158 static inline bool cpu_has_vmx_preemption_timer(void)
1160 return vmcs_config
.pin_based_exec_ctrl
&
1161 PIN_BASED_VMX_PREEMPTION_TIMER
;
1164 static inline bool cpu_has_vmx_posted_intr(void)
1166 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1167 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1170 static inline bool cpu_has_vmx_apicv(void)
1172 return cpu_has_vmx_apic_register_virt() &&
1173 cpu_has_vmx_virtual_intr_delivery() &&
1174 cpu_has_vmx_posted_intr();
1177 static inline bool cpu_has_vmx_flexpriority(void)
1179 return cpu_has_vmx_tpr_shadow() &&
1180 cpu_has_vmx_virtualize_apic_accesses();
1183 static inline bool cpu_has_vmx_ept_execute_only(void)
1185 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1188 static inline bool cpu_has_vmx_ept_2m_page(void)
1190 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1193 static inline bool cpu_has_vmx_ept_1g_page(void)
1195 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1198 static inline bool cpu_has_vmx_ept_4levels(void)
1200 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1203 static inline bool cpu_has_vmx_ept_mt_wb(void)
1205 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1208 static inline bool cpu_has_vmx_ept_5levels(void)
1210 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1213 static inline bool cpu_has_vmx_ept_ad_bits(void)
1215 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1218 static inline bool cpu_has_vmx_invept_context(void)
1220 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1223 static inline bool cpu_has_vmx_invept_global(void)
1225 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1228 static inline bool cpu_has_vmx_invvpid_single(void)
1230 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1233 static inline bool cpu_has_vmx_invvpid_global(void)
1235 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1238 static inline bool cpu_has_vmx_invvpid(void)
1240 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1243 static inline bool cpu_has_vmx_ept(void)
1245 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1246 SECONDARY_EXEC_ENABLE_EPT
;
1249 static inline bool cpu_has_vmx_unrestricted_guest(void)
1251 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1252 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1255 static inline bool cpu_has_vmx_ple(void)
1257 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1258 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1261 static inline bool cpu_has_vmx_basic_inout(void)
1263 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1266 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1268 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1271 static inline bool cpu_has_vmx_vpid(void)
1273 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1274 SECONDARY_EXEC_ENABLE_VPID
;
1277 static inline bool cpu_has_vmx_rdtscp(void)
1279 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1280 SECONDARY_EXEC_RDTSCP
;
1283 static inline bool cpu_has_vmx_invpcid(void)
1285 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1286 SECONDARY_EXEC_ENABLE_INVPCID
;
1289 static inline bool cpu_has_vmx_wbinvd_exit(void)
1291 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1292 SECONDARY_EXEC_WBINVD_EXITING
;
1295 static inline bool cpu_has_vmx_shadow_vmcs(void)
1298 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1299 /* check if the cpu supports writing r/o exit information fields */
1300 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1303 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1304 SECONDARY_EXEC_SHADOW_VMCS
;
1307 static inline bool cpu_has_vmx_pml(void)
1309 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1312 static inline bool cpu_has_vmx_tsc_scaling(void)
1314 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1315 SECONDARY_EXEC_TSC_SCALING
;
1318 static inline bool cpu_has_vmx_vmfunc(void)
1320 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1321 SECONDARY_EXEC_ENABLE_VMFUNC
;
1324 static inline bool report_flexpriority(void)
1326 return flexpriority_enabled
;
1329 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1331 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1334 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1336 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1339 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1341 return (vmcs12
->cpu_based_vm_exec_control
&
1342 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1343 (vmcs12
->secondary_vm_exec_control
& bit
);
1346 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1348 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1351 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1353 return vmcs12
->pin_based_vm_exec_control
&
1354 PIN_BASED_VMX_PREEMPTION_TIMER
;
1357 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1359 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1362 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1364 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
1367 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1369 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1372 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1374 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1377 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1379 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1382 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1384 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1387 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1389 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1392 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1394 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1397 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1399 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1402 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1404 return nested_cpu_has_vmfunc(vmcs12
) &&
1405 (vmcs12
->vm_function_control
&
1406 VMX_VMFUNC_EPTP_SWITCHING
);
1409 static inline bool is_nmi(u32 intr_info
)
1411 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1412 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1415 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1417 unsigned long exit_qualification
);
1418 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1419 struct vmcs12
*vmcs12
,
1420 u32 reason
, unsigned long qualification
);
1422 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1426 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1427 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1432 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1438 } operand
= { vpid
, 0, gva
};
1440 asm volatile (__ex(ASM_VMX_INVVPID
)
1441 /* CF==1 or ZF==1 --> rc = -1 */
1442 "; ja 1f ; ud2 ; 1:"
1443 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1446 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1450 } operand
= {eptp
, gpa
};
1452 asm volatile (__ex(ASM_VMX_INVEPT
)
1453 /* CF==1 or ZF==1 --> rc = -1 */
1454 "; ja 1f ; ud2 ; 1:\n"
1455 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1458 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1462 i
= __find_msr_index(vmx
, msr
);
1464 return &vmx
->guest_msrs
[i
];
1468 static void vmcs_clear(struct vmcs
*vmcs
)
1470 u64 phys_addr
= __pa(vmcs
);
1473 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1474 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1477 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1481 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1483 vmcs_clear(loaded_vmcs
->vmcs
);
1484 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1485 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1486 loaded_vmcs
->cpu
= -1;
1487 loaded_vmcs
->launched
= 0;
1490 static void vmcs_load(struct vmcs
*vmcs
)
1492 u64 phys_addr
= __pa(vmcs
);
1495 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1496 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1499 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1503 #ifdef CONFIG_KEXEC_CORE
1505 * This bitmap is used to indicate whether the vmclear
1506 * operation is enabled on all cpus. All disabled by
1509 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1511 static inline void crash_enable_local_vmclear(int cpu
)
1513 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1516 static inline void crash_disable_local_vmclear(int cpu
)
1518 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1521 static inline int crash_local_vmclear_enabled(int cpu
)
1523 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1526 static void crash_vmclear_local_loaded_vmcss(void)
1528 int cpu
= raw_smp_processor_id();
1529 struct loaded_vmcs
*v
;
1531 if (!crash_local_vmclear_enabled(cpu
))
1534 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1535 loaded_vmcss_on_cpu_link
)
1536 vmcs_clear(v
->vmcs
);
1539 static inline void crash_enable_local_vmclear(int cpu
) { }
1540 static inline void crash_disable_local_vmclear(int cpu
) { }
1541 #endif /* CONFIG_KEXEC_CORE */
1543 static void __loaded_vmcs_clear(void *arg
)
1545 struct loaded_vmcs
*loaded_vmcs
= arg
;
1546 int cpu
= raw_smp_processor_id();
1548 if (loaded_vmcs
->cpu
!= cpu
)
1549 return; /* vcpu migration can race with cpu offline */
1550 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1551 per_cpu(current_vmcs
, cpu
) = NULL
;
1552 crash_disable_local_vmclear(cpu
);
1553 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1556 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1557 * is before setting loaded_vmcs->vcpu to -1 which is done in
1558 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1559 * then adds the vmcs into percpu list before it is deleted.
1563 loaded_vmcs_init(loaded_vmcs
);
1564 crash_enable_local_vmclear(cpu
);
1567 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1569 int cpu
= loaded_vmcs
->cpu
;
1572 smp_call_function_single(cpu
,
1573 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1576 static inline void vpid_sync_vcpu_single(int vpid
)
1581 if (cpu_has_vmx_invvpid_single())
1582 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1585 static inline void vpid_sync_vcpu_global(void)
1587 if (cpu_has_vmx_invvpid_global())
1588 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1591 static inline void vpid_sync_context(int vpid
)
1593 if (cpu_has_vmx_invvpid_single())
1594 vpid_sync_vcpu_single(vpid
);
1596 vpid_sync_vcpu_global();
1599 static inline void ept_sync_global(void)
1601 if (cpu_has_vmx_invept_global())
1602 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1605 static inline void ept_sync_context(u64 eptp
)
1608 if (cpu_has_vmx_invept_context())
1609 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1615 static __always_inline
void vmcs_check16(unsigned long field
)
1617 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1618 "16-bit accessor invalid for 64-bit field");
1619 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1620 "16-bit accessor invalid for 64-bit high field");
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1622 "16-bit accessor invalid for 32-bit high field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1624 "16-bit accessor invalid for natural width field");
1627 static __always_inline
void vmcs_check32(unsigned long field
)
1629 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1630 "32-bit accessor invalid for 16-bit field");
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1632 "32-bit accessor invalid for natural width field");
1635 static __always_inline
void vmcs_check64(unsigned long field
)
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1638 "64-bit accessor invalid for 16-bit field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1640 "64-bit accessor invalid for 64-bit high field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1642 "64-bit accessor invalid for 32-bit field");
1643 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1644 "64-bit accessor invalid for natural width field");
1647 static __always_inline
void vmcs_checkl(unsigned long field
)
1649 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1650 "Natural width accessor invalid for 16-bit field");
1651 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1652 "Natural width accessor invalid for 64-bit field");
1653 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1654 "Natural width accessor invalid for 64-bit high field");
1655 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1656 "Natural width accessor invalid for 32-bit field");
1659 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1661 unsigned long value
;
1663 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1664 : "=a"(value
) : "d"(field
) : "cc");
1668 static __always_inline u16
vmcs_read16(unsigned long field
)
1670 vmcs_check16(field
);
1671 return __vmcs_readl(field
);
1674 static __always_inline u32
vmcs_read32(unsigned long field
)
1676 vmcs_check32(field
);
1677 return __vmcs_readl(field
);
1680 static __always_inline u64
vmcs_read64(unsigned long field
)
1682 vmcs_check64(field
);
1683 #ifdef CONFIG_X86_64
1684 return __vmcs_readl(field
);
1686 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1690 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1693 return __vmcs_readl(field
);
1696 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1698 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1699 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1703 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1707 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1708 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1709 if (unlikely(error
))
1710 vmwrite_error(field
, value
);
1713 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1715 vmcs_check16(field
);
1716 __vmcs_writel(field
, value
);
1719 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1721 vmcs_check32(field
);
1722 __vmcs_writel(field
, value
);
1725 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1727 vmcs_check64(field
);
1728 __vmcs_writel(field
, value
);
1729 #ifndef CONFIG_X86_64
1731 __vmcs_writel(field
+1, value
>> 32);
1735 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1738 __vmcs_writel(field
, value
);
1741 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1743 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1744 "vmcs_clear_bits does not support 64-bit fields");
1745 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1748 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1750 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1751 "vmcs_set_bits does not support 64-bit fields");
1752 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1755 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1757 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1760 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1762 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1763 vmx
->vm_entry_controls_shadow
= val
;
1766 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1768 if (vmx
->vm_entry_controls_shadow
!= val
)
1769 vm_entry_controls_init(vmx
, val
);
1772 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1774 return vmx
->vm_entry_controls_shadow
;
1778 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1780 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1783 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1785 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1788 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1790 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1793 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1795 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1796 vmx
->vm_exit_controls_shadow
= val
;
1799 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1801 if (vmx
->vm_exit_controls_shadow
!= val
)
1802 vm_exit_controls_init(vmx
, val
);
1805 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1807 return vmx
->vm_exit_controls_shadow
;
1811 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1813 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1816 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1818 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1821 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1823 vmx
->segment_cache
.bitmask
= 0;
1826 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1830 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1832 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1833 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1834 vmx
->segment_cache
.bitmask
= 0;
1836 ret
= vmx
->segment_cache
.bitmask
& mask
;
1837 vmx
->segment_cache
.bitmask
|= mask
;
1841 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1843 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1845 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1846 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1850 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1852 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1854 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1855 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1859 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1861 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1863 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1864 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1868 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1870 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1872 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1873 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1877 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1881 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1882 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1883 if ((vcpu
->guest_debug
&
1884 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1885 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1886 eb
|= 1u << BP_VECTOR
;
1887 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1890 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1892 /* When we are running a nested L2 guest and L1 specified for it a
1893 * certain exception bitmap, we must trap the same exceptions and pass
1894 * them to L1. When running L2, we will only handle the exceptions
1895 * specified above if L1 did not want them.
1897 if (is_guest_mode(vcpu
))
1898 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1900 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1903 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1904 unsigned long entry
, unsigned long exit
)
1906 vm_entry_controls_clearbit(vmx
, entry
);
1907 vm_exit_controls_clearbit(vmx
, exit
);
1910 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1913 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1917 if (cpu_has_load_ia32_efer
) {
1918 clear_atomic_switch_msr_special(vmx
,
1919 VM_ENTRY_LOAD_IA32_EFER
,
1920 VM_EXIT_LOAD_IA32_EFER
);
1924 case MSR_CORE_PERF_GLOBAL_CTRL
:
1925 if (cpu_has_load_perf_global_ctrl
) {
1926 clear_atomic_switch_msr_special(vmx
,
1927 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1928 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1934 for (i
= 0; i
< m
->nr
; ++i
)
1935 if (m
->guest
[i
].index
== msr
)
1941 m
->guest
[i
] = m
->guest
[m
->nr
];
1942 m
->host
[i
] = m
->host
[m
->nr
];
1943 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1944 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1947 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1948 unsigned long entry
, unsigned long exit
,
1949 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1950 u64 guest_val
, u64 host_val
)
1952 vmcs_write64(guest_val_vmcs
, guest_val
);
1953 vmcs_write64(host_val_vmcs
, host_val
);
1954 vm_entry_controls_setbit(vmx
, entry
);
1955 vm_exit_controls_setbit(vmx
, exit
);
1958 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1959 u64 guest_val
, u64 host_val
)
1962 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1966 if (cpu_has_load_ia32_efer
) {
1967 add_atomic_switch_msr_special(vmx
,
1968 VM_ENTRY_LOAD_IA32_EFER
,
1969 VM_EXIT_LOAD_IA32_EFER
,
1972 guest_val
, host_val
);
1976 case MSR_CORE_PERF_GLOBAL_CTRL
:
1977 if (cpu_has_load_perf_global_ctrl
) {
1978 add_atomic_switch_msr_special(vmx
,
1979 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1980 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1981 GUEST_IA32_PERF_GLOBAL_CTRL
,
1982 HOST_IA32_PERF_GLOBAL_CTRL
,
1983 guest_val
, host_val
);
1987 case MSR_IA32_PEBS_ENABLE
:
1988 /* PEBS needs a quiescent period after being disabled (to write
1989 * a record). Disabling PEBS through VMX MSR swapping doesn't
1990 * provide that period, so a CPU could write host's record into
1993 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1996 for (i
= 0; i
< m
->nr
; ++i
)
1997 if (m
->guest
[i
].index
== msr
)
2000 if (i
== NR_AUTOLOAD_MSRS
) {
2001 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2002 "Can't add msr %x\n", msr
);
2004 } else if (i
== m
->nr
) {
2006 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2007 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2010 m
->guest
[i
].index
= msr
;
2011 m
->guest
[i
].value
= guest_val
;
2012 m
->host
[i
].index
= msr
;
2013 m
->host
[i
].value
= host_val
;
2016 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2018 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2019 u64 ignore_bits
= 0;
2023 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2024 * host CPUID is more efficient than testing guest CPUID
2025 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2027 if (boot_cpu_has(X86_FEATURE_SMEP
))
2028 guest_efer
|= EFER_NX
;
2029 else if (!(guest_efer
& EFER_NX
))
2030 ignore_bits
|= EFER_NX
;
2034 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2036 ignore_bits
|= EFER_SCE
;
2037 #ifdef CONFIG_X86_64
2038 ignore_bits
|= EFER_LMA
| EFER_LME
;
2039 /* SCE is meaningful only in long mode on Intel */
2040 if (guest_efer
& EFER_LMA
)
2041 ignore_bits
&= ~(u64
)EFER_SCE
;
2044 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2047 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2048 * On CPUs that support "load IA32_EFER", always switch EFER
2049 * atomically, since it's faster than switching it manually.
2051 if (cpu_has_load_ia32_efer
||
2052 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2053 if (!(guest_efer
& EFER_LMA
))
2054 guest_efer
&= ~EFER_LME
;
2055 if (guest_efer
!= host_efer
)
2056 add_atomic_switch_msr(vmx
, MSR_EFER
,
2057 guest_efer
, host_efer
);
2060 guest_efer
&= ~ignore_bits
;
2061 guest_efer
|= host_efer
& ignore_bits
;
2063 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2064 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2070 #ifdef CONFIG_X86_32
2072 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2073 * VMCS rather than the segment table. KVM uses this helper to figure
2074 * out the current bases to poke them into the VMCS before entry.
2076 static unsigned long segment_base(u16 selector
)
2078 struct desc_struct
*table
;
2081 if (!(selector
& ~SEGMENT_RPL_MASK
))
2084 table
= get_current_gdt_ro();
2086 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2087 u16 ldt_selector
= kvm_read_ldt();
2089 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2092 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2094 v
= get_desc_base(&table
[selector
>> 3]);
2099 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2101 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2104 if (vmx
->host_state
.loaded
)
2107 vmx
->host_state
.loaded
= 1;
2109 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2110 * allow segment selectors with cpl > 0 or ti == 1.
2112 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2113 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2114 savesegment(fs
, vmx
->host_state
.fs_sel
);
2115 if (!(vmx
->host_state
.fs_sel
& 7)) {
2116 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2117 vmx
->host_state
.fs_reload_needed
= 0;
2119 vmcs_write16(HOST_FS_SELECTOR
, 0);
2120 vmx
->host_state
.fs_reload_needed
= 1;
2122 savesegment(gs
, vmx
->host_state
.gs_sel
);
2123 if (!(vmx
->host_state
.gs_sel
& 7))
2124 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2126 vmcs_write16(HOST_GS_SELECTOR
, 0);
2127 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2130 #ifdef CONFIG_X86_64
2131 savesegment(ds
, vmx
->host_state
.ds_sel
);
2132 savesegment(es
, vmx
->host_state
.es_sel
);
2135 #ifdef CONFIG_X86_64
2136 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2137 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2139 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2140 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2143 #ifdef CONFIG_X86_64
2144 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2145 if (is_long_mode(&vmx
->vcpu
))
2146 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2148 if (boot_cpu_has(X86_FEATURE_MPX
))
2149 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2150 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2151 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2152 vmx
->guest_msrs
[i
].data
,
2153 vmx
->guest_msrs
[i
].mask
);
2156 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2158 if (!vmx
->host_state
.loaded
)
2161 ++vmx
->vcpu
.stat
.host_state_reload
;
2162 vmx
->host_state
.loaded
= 0;
2163 #ifdef CONFIG_X86_64
2164 if (is_long_mode(&vmx
->vcpu
))
2165 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2167 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2168 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2169 #ifdef CONFIG_X86_64
2170 load_gs_index(vmx
->host_state
.gs_sel
);
2172 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2175 if (vmx
->host_state
.fs_reload_needed
)
2176 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2177 #ifdef CONFIG_X86_64
2178 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2179 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2180 loadsegment(es
, vmx
->host_state
.es_sel
);
2183 invalidate_tss_limit();
2184 #ifdef CONFIG_X86_64
2185 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2187 if (vmx
->host_state
.msr_host_bndcfgs
)
2188 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2189 load_fixmap_gdt(raw_smp_processor_id());
2192 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2195 __vmx_load_host_state(vmx
);
2199 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2201 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2202 struct pi_desc old
, new;
2206 * In case of hot-plug or hot-unplug, we may have to undo
2207 * vmx_vcpu_pi_put even if there is no assigned device. And we
2208 * always keep PI.NDST up to date for simplicity: it makes the
2209 * code easier, and CPU migration is not a fast path.
2211 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2215 * First handle the simple case where no cmpxchg is necessary; just
2216 * allow posting non-urgent interrupts.
2218 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2219 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2220 * expects the VCPU to be on the blocked_vcpu_list that matches
2223 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2225 pi_clear_sn(pi_desc
);
2229 /* The full case. */
2231 old
.control
= new.control
= pi_desc
->control
;
2233 dest
= cpu_physical_id(cpu
);
2235 if (x2apic_enabled())
2238 new.ndst
= (dest
<< 8) & 0xFF00;
2241 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2242 new.control
) != old
.control
);
2245 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2247 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2248 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2252 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2253 * vcpu mutex is already taken.
2255 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2257 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2258 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2260 if (!already_loaded
) {
2261 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2262 local_irq_disable();
2263 crash_disable_local_vmclear(cpu
);
2266 * Read loaded_vmcs->cpu should be before fetching
2267 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2268 * See the comments in __loaded_vmcs_clear().
2272 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2273 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2274 crash_enable_local_vmclear(cpu
);
2278 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2279 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2280 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2283 if (!already_loaded
) {
2284 void *gdt
= get_current_gdt_ro();
2285 unsigned long sysenter_esp
;
2287 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2290 * Linux uses per-cpu TSS and GDT, so set these when switching
2291 * processors. See 22.2.4.
2293 vmcs_writel(HOST_TR_BASE
,
2294 (unsigned long)this_cpu_ptr(&cpu_tss
));
2295 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2298 * VM exits change the host TR limit to 0x67 after a VM
2299 * exit. This is okay, since 0x67 covers everything except
2300 * the IO bitmap and have have code to handle the IO bitmap
2301 * being lost after a VM exit.
2303 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2305 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2306 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2308 vmx
->loaded_vmcs
->cpu
= cpu
;
2311 /* Setup TSC multiplier */
2312 if (kvm_has_tsc_control
&&
2313 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2314 decache_tsc_multiplier(vmx
);
2316 vmx_vcpu_pi_load(vcpu
, cpu
);
2317 vmx
->host_pkru
= read_pkru();
2320 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2322 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2324 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2325 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2326 !kvm_vcpu_apicv_active(vcpu
))
2329 /* Set SN when the vCPU is preempted */
2330 if (vcpu
->preempted
)
2334 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2336 vmx_vcpu_pi_put(vcpu
);
2338 __vmx_load_host_state(to_vmx(vcpu
));
2341 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2343 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2346 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2349 * Return the cr0 value that a nested guest would read. This is a combination
2350 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2351 * its hypervisor (cr0_read_shadow).
2353 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2355 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2356 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2358 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2360 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2361 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2364 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2366 unsigned long rflags
, save_rflags
;
2368 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2369 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2370 rflags
= vmcs_readl(GUEST_RFLAGS
);
2371 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2372 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2373 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2374 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2376 to_vmx(vcpu
)->rflags
= rflags
;
2378 return to_vmx(vcpu
)->rflags
;
2381 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2383 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2385 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2386 to_vmx(vcpu
)->rflags
= rflags
;
2387 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2388 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2389 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2391 vmcs_writel(GUEST_RFLAGS
, rflags
);
2393 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2394 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2397 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2399 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2402 if (interruptibility
& GUEST_INTR_STATE_STI
)
2403 ret
|= KVM_X86_SHADOW_INT_STI
;
2404 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2405 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2410 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2412 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2413 u32 interruptibility
= interruptibility_old
;
2415 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2417 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2418 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2419 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2420 interruptibility
|= GUEST_INTR_STATE_STI
;
2422 if ((interruptibility
!= interruptibility_old
))
2423 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2426 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2430 rip
= kvm_rip_read(vcpu
);
2431 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2432 kvm_rip_write(vcpu
, rip
);
2434 /* skipping an emulated instruction also counts */
2435 vmx_set_interrupt_shadow(vcpu
, 0);
2438 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2439 unsigned long exit_qual
)
2441 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2442 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2443 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2445 if (vcpu
->arch
.exception
.has_error_code
) {
2446 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2447 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2450 if (kvm_exception_is_soft(nr
))
2451 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2453 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2455 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2456 vmx_get_nmi_mask(vcpu
))
2457 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2459 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2463 * KVM wants to inject page-faults which it got to the guest. This function
2464 * checks whether in a nested guest, we need to inject them to L1 or L2.
2466 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
2468 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2469 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2471 if (nr
== PF_VECTOR
) {
2472 if (vcpu
->arch
.exception
.nested_apf
) {
2473 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
2477 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2478 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2479 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2480 * can be written only when inject_pending_event runs. This should be
2481 * conditional on a new capability---if the capability is disabled,
2482 * kvm_multiple_exception would write the ancillary information to
2483 * CR2 or DR6, for backwards ABI-compatibility.
2485 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2486 vcpu
->arch
.exception
.error_code
)) {
2487 *exit_qual
= vcpu
->arch
.cr2
;
2491 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2492 if (nr
== DB_VECTOR
)
2493 *exit_qual
= vcpu
->arch
.dr6
;
2503 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2505 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2506 unsigned nr
= vcpu
->arch
.exception
.nr
;
2507 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2508 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2509 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2511 if (has_error_code
) {
2512 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2513 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2516 if (vmx
->rmode
.vm86_active
) {
2518 if (kvm_exception_is_soft(nr
))
2519 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2520 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2521 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2525 if (kvm_exception_is_soft(nr
)) {
2526 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2527 vmx
->vcpu
.arch
.event_exit_inst_len
);
2528 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2530 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2532 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2535 static bool vmx_rdtscp_supported(void)
2537 return cpu_has_vmx_rdtscp();
2540 static bool vmx_invpcid_supported(void)
2542 return cpu_has_vmx_invpcid() && enable_ept
;
2546 * Swap MSR entry in host/guest MSR entry array.
2548 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2550 struct shared_msr_entry tmp
;
2552 tmp
= vmx
->guest_msrs
[to
];
2553 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2554 vmx
->guest_msrs
[from
] = tmp
;
2557 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2559 unsigned long *msr_bitmap
;
2561 if (is_guest_mode(vcpu
))
2562 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2563 else if (cpu_has_secondary_exec_ctrls() &&
2564 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2565 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2566 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2567 if (is_long_mode(vcpu
))
2568 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2570 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2572 if (is_long_mode(vcpu
))
2573 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2575 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2578 if (is_long_mode(vcpu
))
2579 msr_bitmap
= vmx_msr_bitmap_longmode
;
2581 msr_bitmap
= vmx_msr_bitmap_legacy
;
2584 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2588 * Set up the vmcs to automatically save and restore system
2589 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2590 * mode, as fiddling with msrs is very expensive.
2592 static void setup_msrs(struct vcpu_vmx
*vmx
)
2594 int save_nmsrs
, index
;
2597 #ifdef CONFIG_X86_64
2598 if (is_long_mode(&vmx
->vcpu
)) {
2599 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2601 move_msr_up(vmx
, index
, save_nmsrs
++);
2602 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2604 move_msr_up(vmx
, index
, save_nmsrs
++);
2605 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2607 move_msr_up(vmx
, index
, save_nmsrs
++);
2608 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2609 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2610 move_msr_up(vmx
, index
, save_nmsrs
++);
2612 * MSR_STAR is only needed on long mode guests, and only
2613 * if efer.sce is enabled.
2615 index
= __find_msr_index(vmx
, MSR_STAR
);
2616 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2617 move_msr_up(vmx
, index
, save_nmsrs
++);
2620 index
= __find_msr_index(vmx
, MSR_EFER
);
2621 if (index
>= 0 && update_transition_efer(vmx
, index
))
2622 move_msr_up(vmx
, index
, save_nmsrs
++);
2624 vmx
->save_nmsrs
= save_nmsrs
;
2626 if (cpu_has_vmx_msr_bitmap())
2627 vmx_set_msr_bitmap(&vmx
->vcpu
);
2631 * reads and returns guest's timestamp counter "register"
2632 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2633 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2635 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2637 u64 host_tsc
, tsc_offset
;
2640 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2641 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2645 * writes 'offset' into guest's timestamp counter offset register
2647 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2649 if (is_guest_mode(vcpu
)) {
2651 * We're here if L1 chose not to trap WRMSR to TSC. According
2652 * to the spec, this should set L1's TSC; The offset that L1
2653 * set for L2 remains unchanged, and still needs to be added
2654 * to the newly set TSC to get L2's TSC.
2656 struct vmcs12
*vmcs12
;
2657 /* recalculate vmcs02.TSC_OFFSET: */
2658 vmcs12
= get_vmcs12(vcpu
);
2659 vmcs_write64(TSC_OFFSET
, offset
+
2660 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2661 vmcs12
->tsc_offset
: 0));
2663 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2664 vmcs_read64(TSC_OFFSET
), offset
);
2665 vmcs_write64(TSC_OFFSET
, offset
);
2670 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2671 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2672 * all guests if the "nested" module option is off, and can also be disabled
2673 * for a single guest by disabling its VMX cpuid bit.
2675 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2677 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2681 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2682 * returned for the various VMX controls MSRs when nested VMX is enabled.
2683 * The same values should also be used to verify that vmcs12 control fields are
2684 * valid during nested entry from L1 to L2.
2685 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2686 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2687 * bit in the high half is on if the corresponding bit in the control field
2688 * may be on. See also vmx_control_verify().
2690 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2693 * Note that as a general rule, the high half of the MSRs (bits in
2694 * the control fields which may be 1) should be initialized by the
2695 * intersection of the underlying hardware's MSR (i.e., features which
2696 * can be supported) and the list of features we want to expose -
2697 * because they are known to be properly supported in our code.
2698 * Also, usually, the low half of the MSRs (bits which must be 1) can
2699 * be set to 0, meaning that L1 may turn off any of these bits. The
2700 * reason is that if one of these bits is necessary, it will appear
2701 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2702 * fields of vmcs01 and vmcs02, will turn these bits off - and
2703 * nested_vmx_exit_reflected() will not pass related exits to L1.
2704 * These rules have exceptions below.
2707 /* pin-based controls */
2708 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2709 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2710 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2711 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2712 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2713 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2714 PIN_BASED_EXT_INTR_MASK
|
2715 PIN_BASED_NMI_EXITING
|
2716 PIN_BASED_VIRTUAL_NMIS
;
2717 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2718 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2719 PIN_BASED_VMX_PREEMPTION_TIMER
;
2720 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2721 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2722 PIN_BASED_POSTED_INTR
;
2725 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2726 vmx
->nested
.nested_vmx_exit_ctls_low
,
2727 vmx
->nested
.nested_vmx_exit_ctls_high
);
2728 vmx
->nested
.nested_vmx_exit_ctls_low
=
2729 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2731 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2732 #ifdef CONFIG_X86_64
2733 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2735 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2736 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2737 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2738 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2739 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2741 if (kvm_mpx_supported())
2742 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2744 /* We support free control of debug control saving. */
2745 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2747 /* entry controls */
2748 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2749 vmx
->nested
.nested_vmx_entry_ctls_low
,
2750 vmx
->nested
.nested_vmx_entry_ctls_high
);
2751 vmx
->nested
.nested_vmx_entry_ctls_low
=
2752 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2753 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2754 #ifdef CONFIG_X86_64
2755 VM_ENTRY_IA32E_MODE
|
2757 VM_ENTRY_LOAD_IA32_PAT
;
2758 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2759 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2760 if (kvm_mpx_supported())
2761 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2763 /* We support free control of debug control loading. */
2764 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2766 /* cpu-based controls */
2767 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2768 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2769 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2770 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2771 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2772 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2773 CPU_BASED_VIRTUAL_INTR_PENDING
|
2774 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2775 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2776 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2777 CPU_BASED_CR3_STORE_EXITING
|
2778 #ifdef CONFIG_X86_64
2779 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2781 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2782 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2783 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2784 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2785 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2787 * We can allow some features even when not supported by the
2788 * hardware. For example, L1 can specify an MSR bitmap - and we
2789 * can use it to avoid exits to L1 - even when L0 runs L2
2790 * without MSR bitmaps.
2792 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2793 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2794 CPU_BASED_USE_MSR_BITMAPS
;
2796 /* We support free control of CR3 access interception. */
2797 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2798 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2801 * secondary cpu-based controls. Do not include those that
2802 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2804 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2805 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2806 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2807 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2808 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2809 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2810 SECONDARY_EXEC_DESC
|
2811 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2812 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2813 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2814 SECONDARY_EXEC_WBINVD_EXITING
;
2817 /* nested EPT: emulate EPT also to L1 */
2818 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2819 SECONDARY_EXEC_ENABLE_EPT
;
2820 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2821 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2822 if (cpu_has_vmx_ept_execute_only())
2823 vmx
->nested
.nested_vmx_ept_caps
|=
2824 VMX_EPT_EXECUTE_ONLY_BIT
;
2825 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2826 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2827 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2828 VMX_EPT_1GB_PAGE_BIT
;
2829 if (enable_ept_ad_bits
) {
2830 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2831 SECONDARY_EXEC_ENABLE_PML
;
2832 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2835 vmx
->nested
.nested_vmx_ept_caps
= 0;
2837 if (cpu_has_vmx_vmfunc()) {
2838 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2839 SECONDARY_EXEC_ENABLE_VMFUNC
;
2841 * Advertise EPTP switching unconditionally
2842 * since we emulate it
2844 vmx
->nested
.nested_vmx_vmfunc_controls
=
2845 VMX_VMFUNC_EPTP_SWITCHING
;
2849 * Old versions of KVM use the single-context version without
2850 * checking for support, so declare that it is supported even
2851 * though it is treated as global context. The alternative is
2852 * not failing the single-context invvpid, and it is worse.
2855 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2856 SECONDARY_EXEC_ENABLE_VPID
;
2857 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2858 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2860 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2862 if (enable_unrestricted_guest
)
2863 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2864 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2866 /* miscellaneous data */
2867 rdmsr(MSR_IA32_VMX_MISC
,
2868 vmx
->nested
.nested_vmx_misc_low
,
2869 vmx
->nested
.nested_vmx_misc_high
);
2870 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2871 vmx
->nested
.nested_vmx_misc_low
|=
2872 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2873 VMX_MISC_ACTIVITY_HLT
;
2874 vmx
->nested
.nested_vmx_misc_high
= 0;
2877 * This MSR reports some information about VMX support. We
2878 * should return information about the VMX we emulate for the
2879 * guest, and the VMCS structure we give it - not about the
2880 * VMX support of the underlying hardware.
2882 vmx
->nested
.nested_vmx_basic
=
2884 VMX_BASIC_TRUE_CTLS
|
2885 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2886 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2888 if (cpu_has_vmx_basic_inout())
2889 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2892 * These MSRs specify bits which the guest must keep fixed on
2893 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2894 * We picked the standard core2 setting.
2896 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2897 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2898 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2899 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2901 /* These MSRs specify bits which the guest must keep fixed off. */
2902 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2903 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2905 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2906 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2910 * if fixed0[i] == 1: val[i] must be 1
2911 * if fixed1[i] == 0: val[i] must be 0
2913 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2915 return ((val
& fixed1
) | fixed0
) == val
;
2918 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2920 return fixed_bits_valid(control
, low
, high
);
2923 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2925 return low
| ((u64
)high
<< 32);
2928 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2933 return (superset
| subset
) == superset
;
2936 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2938 const u64 feature_and_reserved
=
2939 /* feature (except bit 48; see below) */
2940 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2942 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2943 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2945 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2949 * KVM does not emulate a version of VMX that constrains physical
2950 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2952 if (data
& BIT_ULL(48))
2955 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2956 vmx_basic_vmcs_revision_id(data
))
2959 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2962 vmx
->nested
.nested_vmx_basic
= data
;
2967 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2972 switch (msr_index
) {
2973 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2974 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2975 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2977 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2978 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2979 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2981 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2982 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2983 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2985 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2986 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2987 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2989 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2990 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2991 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2997 supported
= vmx_control_msr(*lowp
, *highp
);
2999 /* Check must-be-1 bits are still 1. */
3000 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3003 /* Check must-be-0 bits are still 0. */
3004 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3008 *highp
= data
>> 32;
3012 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3014 const u64 feature_and_reserved_bits
=
3016 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3017 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3019 GENMASK_ULL(13, 9) | BIT_ULL(31);
3022 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3023 vmx
->nested
.nested_vmx_misc_high
);
3025 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3028 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3029 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3030 vmx_misc_preemption_timer_rate(data
) !=
3031 vmx_misc_preemption_timer_rate(vmx_misc
))
3034 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3037 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3040 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3043 vmx
->nested
.nested_vmx_misc_low
= data
;
3044 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3048 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3050 u64 vmx_ept_vpid_cap
;
3052 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3053 vmx
->nested
.nested_vmx_vpid_caps
);
3055 /* Every bit is either reserved or a feature bit. */
3056 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3059 vmx
->nested
.nested_vmx_ept_caps
= data
;
3060 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3064 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3068 switch (msr_index
) {
3069 case MSR_IA32_VMX_CR0_FIXED0
:
3070 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3072 case MSR_IA32_VMX_CR4_FIXED0
:
3073 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3080 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3081 * must be 1 in the restored value.
3083 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3091 * Called when userspace is restoring VMX MSRs.
3093 * Returns 0 on success, non-0 otherwise.
3095 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3097 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3099 switch (msr_index
) {
3100 case MSR_IA32_VMX_BASIC
:
3101 return vmx_restore_vmx_basic(vmx
, data
);
3102 case MSR_IA32_VMX_PINBASED_CTLS
:
3103 case MSR_IA32_VMX_PROCBASED_CTLS
:
3104 case MSR_IA32_VMX_EXIT_CTLS
:
3105 case MSR_IA32_VMX_ENTRY_CTLS
:
3107 * The "non-true" VMX capability MSRs are generated from the
3108 * "true" MSRs, so we do not support restoring them directly.
3110 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3111 * should restore the "true" MSRs with the must-be-1 bits
3112 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3113 * DEFAULT SETTINGS".
3116 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3117 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3118 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3119 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3120 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3121 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3122 case MSR_IA32_VMX_MISC
:
3123 return vmx_restore_vmx_misc(vmx
, data
);
3124 case MSR_IA32_VMX_CR0_FIXED0
:
3125 case MSR_IA32_VMX_CR4_FIXED0
:
3126 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3127 case MSR_IA32_VMX_CR0_FIXED1
:
3128 case MSR_IA32_VMX_CR4_FIXED1
:
3130 * These MSRs are generated based on the vCPU's CPUID, so we
3131 * do not support restoring them directly.
3134 case MSR_IA32_VMX_EPT_VPID_CAP
:
3135 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3136 case MSR_IA32_VMX_VMCS_ENUM
:
3137 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3141 * The rest of the VMX capability MSRs do not support restore.
3147 /* Returns 0 on success, non-0 otherwise. */
3148 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3150 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3152 switch (msr_index
) {
3153 case MSR_IA32_VMX_BASIC
:
3154 *pdata
= vmx
->nested
.nested_vmx_basic
;
3156 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3157 case MSR_IA32_VMX_PINBASED_CTLS
:
3158 *pdata
= vmx_control_msr(
3159 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3160 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3161 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3162 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3164 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3165 case MSR_IA32_VMX_PROCBASED_CTLS
:
3166 *pdata
= vmx_control_msr(
3167 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3168 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3169 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3170 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3172 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3173 case MSR_IA32_VMX_EXIT_CTLS
:
3174 *pdata
= vmx_control_msr(
3175 vmx
->nested
.nested_vmx_exit_ctls_low
,
3176 vmx
->nested
.nested_vmx_exit_ctls_high
);
3177 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3178 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3180 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3181 case MSR_IA32_VMX_ENTRY_CTLS
:
3182 *pdata
= vmx_control_msr(
3183 vmx
->nested
.nested_vmx_entry_ctls_low
,
3184 vmx
->nested
.nested_vmx_entry_ctls_high
);
3185 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3186 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3188 case MSR_IA32_VMX_MISC
:
3189 *pdata
= vmx_control_msr(
3190 vmx
->nested
.nested_vmx_misc_low
,
3191 vmx
->nested
.nested_vmx_misc_high
);
3193 case MSR_IA32_VMX_CR0_FIXED0
:
3194 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3196 case MSR_IA32_VMX_CR0_FIXED1
:
3197 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3199 case MSR_IA32_VMX_CR4_FIXED0
:
3200 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3202 case MSR_IA32_VMX_CR4_FIXED1
:
3203 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3205 case MSR_IA32_VMX_VMCS_ENUM
:
3206 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3208 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3209 *pdata
= vmx_control_msr(
3210 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3211 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3213 case MSR_IA32_VMX_EPT_VPID_CAP
:
3214 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3215 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3217 case MSR_IA32_VMX_VMFUNC
:
3218 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3227 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3230 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3232 return !(val
& ~valid_bits
);
3236 * Reads an msr value (of 'msr_index') into 'pdata'.
3237 * Returns 0 on success, non-0 otherwise.
3238 * Assumes vcpu_load() was already called.
3240 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3242 struct shared_msr_entry
*msr
;
3244 switch (msr_info
->index
) {
3245 #ifdef CONFIG_X86_64
3247 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3250 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3252 case MSR_KERNEL_GS_BASE
:
3253 vmx_load_host_state(to_vmx(vcpu
));
3254 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3258 return kvm_get_msr_common(vcpu
, msr_info
);
3260 msr_info
->data
= guest_read_tsc(vcpu
);
3262 case MSR_IA32_SYSENTER_CS
:
3263 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3265 case MSR_IA32_SYSENTER_EIP
:
3266 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3268 case MSR_IA32_SYSENTER_ESP
:
3269 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3271 case MSR_IA32_BNDCFGS
:
3272 if (!kvm_mpx_supported() ||
3273 (!msr_info
->host_initiated
&&
3274 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3276 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3278 case MSR_IA32_MCG_EXT_CTL
:
3279 if (!msr_info
->host_initiated
&&
3280 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3281 FEATURE_CONTROL_LMCE
))
3283 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3285 case MSR_IA32_FEATURE_CONTROL
:
3286 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3288 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3289 if (!nested_vmx_allowed(vcpu
))
3291 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3293 if (!vmx_xsaves_supported())
3295 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3298 if (!msr_info
->host_initiated
&&
3299 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3301 /* Otherwise falls through */
3303 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3305 msr_info
->data
= msr
->data
;
3308 return kvm_get_msr_common(vcpu
, msr_info
);
3314 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3317 * Writes msr value into into the appropriate "register".
3318 * Returns 0 on success, non-0 otherwise.
3319 * Assumes vcpu_load() was already called.
3321 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3323 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3324 struct shared_msr_entry
*msr
;
3326 u32 msr_index
= msr_info
->index
;
3327 u64 data
= msr_info
->data
;
3329 switch (msr_index
) {
3331 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3333 #ifdef CONFIG_X86_64
3335 vmx_segment_cache_clear(vmx
);
3336 vmcs_writel(GUEST_FS_BASE
, data
);
3339 vmx_segment_cache_clear(vmx
);
3340 vmcs_writel(GUEST_GS_BASE
, data
);
3342 case MSR_KERNEL_GS_BASE
:
3343 vmx_load_host_state(vmx
);
3344 vmx
->msr_guest_kernel_gs_base
= data
;
3347 case MSR_IA32_SYSENTER_CS
:
3348 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3350 case MSR_IA32_SYSENTER_EIP
:
3351 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3353 case MSR_IA32_SYSENTER_ESP
:
3354 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3356 case MSR_IA32_BNDCFGS
:
3357 if (!kvm_mpx_supported() ||
3358 (!msr_info
->host_initiated
&&
3359 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3361 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
3362 (data
& MSR_IA32_BNDCFGS_RSVD
))
3364 vmcs_write64(GUEST_BNDCFGS
, data
);
3367 kvm_write_tsc(vcpu
, msr_info
);
3369 case MSR_IA32_CR_PAT
:
3370 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3371 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3373 vmcs_write64(GUEST_IA32_PAT
, data
);
3374 vcpu
->arch
.pat
= data
;
3377 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3379 case MSR_IA32_TSC_ADJUST
:
3380 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3382 case MSR_IA32_MCG_EXT_CTL
:
3383 if ((!msr_info
->host_initiated
&&
3384 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3385 FEATURE_CONTROL_LMCE
)) ||
3386 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3388 vcpu
->arch
.mcg_ext_ctl
= data
;
3390 case MSR_IA32_FEATURE_CONTROL
:
3391 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3392 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3393 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3395 vmx
->msr_ia32_feature_control
= data
;
3396 if (msr_info
->host_initiated
&& data
== 0)
3397 vmx_leave_nested(vcpu
);
3399 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3400 if (!msr_info
->host_initiated
)
3401 return 1; /* they are read-only */
3402 if (!nested_vmx_allowed(vcpu
))
3404 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3406 if (!vmx_xsaves_supported())
3409 * The only supported bit as of Skylake is bit 8, but
3410 * it is not supported on KVM.
3414 vcpu
->arch
.ia32_xss
= data
;
3415 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3416 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3417 vcpu
->arch
.ia32_xss
, host_xss
);
3419 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3422 if (!msr_info
->host_initiated
&&
3423 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3425 /* Check reserved bit, higher 32 bits should be zero */
3426 if ((data
>> 32) != 0)
3428 /* Otherwise falls through */
3430 msr
= find_msr_entry(vmx
, msr_index
);
3432 u64 old_msr_data
= msr
->data
;
3434 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3436 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3440 msr
->data
= old_msr_data
;
3444 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3450 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3452 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3455 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3458 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3460 case VCPU_EXREG_PDPTR
:
3462 ept_save_pdptrs(vcpu
);
3469 static __init
int cpu_has_kvm_support(void)
3471 return cpu_has_vmx();
3474 static __init
int vmx_disabled_by_bios(void)
3478 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3479 if (msr
& FEATURE_CONTROL_LOCKED
) {
3480 /* launched w/ TXT and VMX disabled */
3481 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3484 /* launched w/o TXT and VMX only enabled w/ TXT */
3485 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3486 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3487 && !tboot_enabled()) {
3488 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3489 "activate TXT before enabling KVM\n");
3492 /* launched w/o TXT and VMX disabled */
3493 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3494 && !tboot_enabled())
3501 static void kvm_cpu_vmxon(u64 addr
)
3503 cr4_set_bits(X86_CR4_VMXE
);
3504 intel_pt_handle_vmx(1);
3506 asm volatile (ASM_VMX_VMXON_RAX
3507 : : "a"(&addr
), "m"(addr
)
3511 static int hardware_enable(void)
3513 int cpu
= raw_smp_processor_id();
3514 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3517 if (cr4_read_shadow() & X86_CR4_VMXE
)
3520 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3521 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3522 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3525 * Now we can enable the vmclear operation in kdump
3526 * since the loaded_vmcss_on_cpu list on this cpu
3527 * has been initialized.
3529 * Though the cpu is not in VMX operation now, there
3530 * is no problem to enable the vmclear operation
3531 * for the loaded_vmcss_on_cpu list is empty!
3533 crash_enable_local_vmclear(cpu
);
3535 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3537 test_bits
= FEATURE_CONTROL_LOCKED
;
3538 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3539 if (tboot_enabled())
3540 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3542 if ((old
& test_bits
) != test_bits
) {
3543 /* enable and lock */
3544 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3546 kvm_cpu_vmxon(phys_addr
);
3552 static void vmclear_local_loaded_vmcss(void)
3554 int cpu
= raw_smp_processor_id();
3555 struct loaded_vmcs
*v
, *n
;
3557 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3558 loaded_vmcss_on_cpu_link
)
3559 __loaded_vmcs_clear(v
);
3563 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3566 static void kvm_cpu_vmxoff(void)
3568 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3570 intel_pt_handle_vmx(0);
3571 cr4_clear_bits(X86_CR4_VMXE
);
3574 static void hardware_disable(void)
3576 vmclear_local_loaded_vmcss();
3580 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3581 u32 msr
, u32
*result
)
3583 u32 vmx_msr_low
, vmx_msr_high
;
3584 u32 ctl
= ctl_min
| ctl_opt
;
3586 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3588 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3589 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3591 /* Ensure minimum (required) set of control bits are supported. */
3599 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3601 u32 vmx_msr_low
, vmx_msr_high
;
3603 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3604 return vmx_msr_high
& ctl
;
3607 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3609 u32 vmx_msr_low
, vmx_msr_high
;
3610 u32 min
, opt
, min2
, opt2
;
3611 u32 _pin_based_exec_control
= 0;
3612 u32 _cpu_based_exec_control
= 0;
3613 u32 _cpu_based_2nd_exec_control
= 0;
3614 u32 _vmexit_control
= 0;
3615 u32 _vmentry_control
= 0;
3617 min
= CPU_BASED_HLT_EXITING
|
3618 #ifdef CONFIG_X86_64
3619 CPU_BASED_CR8_LOAD_EXITING
|
3620 CPU_BASED_CR8_STORE_EXITING
|
3622 CPU_BASED_CR3_LOAD_EXITING
|
3623 CPU_BASED_CR3_STORE_EXITING
|
3624 CPU_BASED_USE_IO_BITMAPS
|
3625 CPU_BASED_MOV_DR_EXITING
|
3626 CPU_BASED_USE_TSC_OFFSETING
|
3627 CPU_BASED_INVLPG_EXITING
|
3628 CPU_BASED_RDPMC_EXITING
;
3630 if (!kvm_mwait_in_guest())
3631 min
|= CPU_BASED_MWAIT_EXITING
|
3632 CPU_BASED_MONITOR_EXITING
;
3634 opt
= CPU_BASED_TPR_SHADOW
|
3635 CPU_BASED_USE_MSR_BITMAPS
|
3636 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3637 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3638 &_cpu_based_exec_control
) < 0)
3640 #ifdef CONFIG_X86_64
3641 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3642 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3643 ~CPU_BASED_CR8_STORE_EXITING
;
3645 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3647 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3648 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3649 SECONDARY_EXEC_WBINVD_EXITING
|
3650 SECONDARY_EXEC_ENABLE_VPID
|
3651 SECONDARY_EXEC_ENABLE_EPT
|
3652 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3653 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3654 SECONDARY_EXEC_RDTSCP
|
3655 SECONDARY_EXEC_ENABLE_INVPCID
|
3656 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3657 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3658 SECONDARY_EXEC_SHADOW_VMCS
|
3659 SECONDARY_EXEC_XSAVES
|
3660 SECONDARY_EXEC_RDSEED
|
3661 SECONDARY_EXEC_RDRAND
|
3662 SECONDARY_EXEC_ENABLE_PML
|
3663 SECONDARY_EXEC_TSC_SCALING
|
3664 SECONDARY_EXEC_ENABLE_VMFUNC
;
3665 if (adjust_vmx_controls(min2
, opt2
,
3666 MSR_IA32_VMX_PROCBASED_CTLS2
,
3667 &_cpu_based_2nd_exec_control
) < 0)
3670 #ifndef CONFIG_X86_64
3671 if (!(_cpu_based_2nd_exec_control
&
3672 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3673 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3676 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3677 _cpu_based_2nd_exec_control
&= ~(
3678 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3679 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3680 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3682 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3683 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3685 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3686 CPU_BASED_CR3_STORE_EXITING
|
3687 CPU_BASED_INVLPG_EXITING
);
3688 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3689 vmx_capability
.ept
, vmx_capability
.vpid
);
3692 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3693 #ifdef CONFIG_X86_64
3694 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3696 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3697 VM_EXIT_CLEAR_BNDCFGS
;
3698 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3699 &_vmexit_control
) < 0)
3702 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3703 PIN_BASED_VIRTUAL_NMIS
;
3704 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3705 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3706 &_pin_based_exec_control
) < 0)
3709 if (cpu_has_broken_vmx_preemption_timer())
3710 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3711 if (!(_cpu_based_2nd_exec_control
&
3712 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3713 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3715 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3716 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3717 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3718 &_vmentry_control
) < 0)
3721 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3723 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3724 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3727 #ifdef CONFIG_X86_64
3728 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3729 if (vmx_msr_high
& (1u<<16))
3733 /* Require Write-Back (WB) memory type for VMCS accesses. */
3734 if (((vmx_msr_high
>> 18) & 15) != 6)
3737 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3738 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3739 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3740 vmcs_conf
->revision_id
= vmx_msr_low
;
3742 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3743 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3744 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3745 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3746 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3748 cpu_has_load_ia32_efer
=
3749 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3750 VM_ENTRY_LOAD_IA32_EFER
)
3751 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3752 VM_EXIT_LOAD_IA32_EFER
);
3754 cpu_has_load_perf_global_ctrl
=
3755 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3756 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3757 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3758 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3761 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3762 * but due to errata below it can't be used. Workaround is to use
3763 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3765 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3770 * BC86,AAY89,BD102 (model 44)
3774 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3775 switch (boot_cpu_data
.x86_model
) {
3781 cpu_has_load_perf_global_ctrl
= false;
3782 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3783 "does not work properly. Using workaround\n");
3790 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3791 rdmsrl(MSR_IA32_XSS
, host_xss
);
3796 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3798 int node
= cpu_to_node(cpu
);
3802 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3805 vmcs
= page_address(pages
);
3806 memset(vmcs
, 0, vmcs_config
.size
);
3807 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3811 static struct vmcs
*alloc_vmcs(void)
3813 return alloc_vmcs_cpu(raw_smp_processor_id());
3816 static void free_vmcs(struct vmcs
*vmcs
)
3818 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3822 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3824 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3826 if (!loaded_vmcs
->vmcs
)
3828 loaded_vmcs_clear(loaded_vmcs
);
3829 free_vmcs(loaded_vmcs
->vmcs
);
3830 loaded_vmcs
->vmcs
= NULL
;
3831 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3834 static void free_kvm_area(void)
3838 for_each_possible_cpu(cpu
) {
3839 free_vmcs(per_cpu(vmxarea
, cpu
));
3840 per_cpu(vmxarea
, cpu
) = NULL
;
3844 enum vmcs_field_type
{
3845 VMCS_FIELD_TYPE_U16
= 0,
3846 VMCS_FIELD_TYPE_U64
= 1,
3847 VMCS_FIELD_TYPE_U32
= 2,
3848 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3851 static inline int vmcs_field_type(unsigned long field
)
3853 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3854 return VMCS_FIELD_TYPE_U32
;
3855 return (field
>> 13) & 0x3 ;
3858 static inline int vmcs_field_readonly(unsigned long field
)
3860 return (((field
>> 10) & 0x3) == 1);
3863 static void init_vmcs_shadow_fields(void)
3867 /* No checks for read only fields yet */
3869 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3870 switch (shadow_read_write_fields
[i
]) {
3872 if (!kvm_mpx_supported())
3880 shadow_read_write_fields
[j
] =
3881 shadow_read_write_fields
[i
];
3884 max_shadow_read_write_fields
= j
;
3886 /* shadowed fields guest access without vmexit */
3887 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3888 unsigned long field
= shadow_read_write_fields
[i
];
3890 clear_bit(field
, vmx_vmwrite_bitmap
);
3891 clear_bit(field
, vmx_vmread_bitmap
);
3892 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3893 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3894 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3897 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3898 unsigned long field
= shadow_read_only_fields
[i
];
3900 clear_bit(field
, vmx_vmread_bitmap
);
3901 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3902 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3906 static __init
int alloc_kvm_area(void)
3910 for_each_possible_cpu(cpu
) {
3913 vmcs
= alloc_vmcs_cpu(cpu
);
3919 per_cpu(vmxarea
, cpu
) = vmcs
;
3924 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3925 struct kvm_segment
*save
)
3927 if (!emulate_invalid_guest_state
) {
3929 * CS and SS RPL should be equal during guest entry according
3930 * to VMX spec, but in reality it is not always so. Since vcpu
3931 * is in the middle of the transition from real mode to
3932 * protected mode it is safe to assume that RPL 0 is a good
3935 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3936 save
->selector
&= ~SEGMENT_RPL_MASK
;
3937 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3940 vmx_set_segment(vcpu
, save
, seg
);
3943 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3945 unsigned long flags
;
3946 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3949 * Update real mode segment cache. It may be not up-to-date if sement
3950 * register was written while vcpu was in a guest mode.
3952 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3953 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3954 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3955 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3956 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3957 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3959 vmx
->rmode
.vm86_active
= 0;
3961 vmx_segment_cache_clear(vmx
);
3963 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3965 flags
= vmcs_readl(GUEST_RFLAGS
);
3966 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3967 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3968 vmcs_writel(GUEST_RFLAGS
, flags
);
3970 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3971 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3973 update_exception_bitmap(vcpu
);
3975 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3976 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3977 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3978 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3979 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3980 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3983 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3985 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3986 struct kvm_segment var
= *save
;
3989 if (seg
== VCPU_SREG_CS
)
3992 if (!emulate_invalid_guest_state
) {
3993 var
.selector
= var
.base
>> 4;
3994 var
.base
= var
.base
& 0xffff0;
4004 if (save
->base
& 0xf)
4005 printk_once(KERN_WARNING
"kvm: segment base is not "
4006 "paragraph aligned when entering "
4007 "protected mode (seg=%d)", seg
);
4010 vmcs_write16(sf
->selector
, var
.selector
);
4011 vmcs_writel(sf
->base
, var
.base
);
4012 vmcs_write32(sf
->limit
, var
.limit
);
4013 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4016 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4018 unsigned long flags
;
4019 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4021 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4022 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4023 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4024 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4025 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4026 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4027 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4029 vmx
->rmode
.vm86_active
= 1;
4032 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4033 * vcpu. Warn the user that an update is overdue.
4035 if (!vcpu
->kvm
->arch
.tss_addr
)
4036 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4037 "called before entering vcpu\n");
4039 vmx_segment_cache_clear(vmx
);
4041 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4042 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4043 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4045 flags
= vmcs_readl(GUEST_RFLAGS
);
4046 vmx
->rmode
.save_rflags
= flags
;
4048 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4050 vmcs_writel(GUEST_RFLAGS
, flags
);
4051 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4052 update_exception_bitmap(vcpu
);
4054 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4055 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4056 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4057 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4058 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4059 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4061 kvm_mmu_reset_context(vcpu
);
4064 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4066 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4067 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4073 * Force kernel_gs_base reloading before EFER changes, as control
4074 * of this msr depends on is_long_mode().
4076 vmx_load_host_state(to_vmx(vcpu
));
4077 vcpu
->arch
.efer
= efer
;
4078 if (efer
& EFER_LMA
) {
4079 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4082 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4084 msr
->data
= efer
& ~EFER_LME
;
4089 #ifdef CONFIG_X86_64
4091 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4095 vmx_segment_cache_clear(to_vmx(vcpu
));
4097 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4098 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4099 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4101 vmcs_write32(GUEST_TR_AR_BYTES
,
4102 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4103 | VMX_AR_TYPE_BUSY_64_TSS
);
4105 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4108 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4110 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4111 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4116 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4119 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4121 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4123 vpid_sync_context(vpid
);
4127 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4129 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4132 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4135 vmx_flush_tlb(vcpu
);
4138 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4140 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4142 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4143 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4146 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4148 if (enable_ept
&& is_paging(vcpu
))
4149 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4150 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4153 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4155 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4157 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4158 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4161 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4163 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4165 if (!test_bit(VCPU_EXREG_PDPTR
,
4166 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4169 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4170 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4171 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4172 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4173 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4177 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4179 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4181 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4182 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4183 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4184 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4185 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4188 __set_bit(VCPU_EXREG_PDPTR
,
4189 (unsigned long *)&vcpu
->arch
.regs_avail
);
4190 __set_bit(VCPU_EXREG_PDPTR
,
4191 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4194 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4196 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4197 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4198 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4200 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4201 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4202 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4203 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4205 return fixed_bits_valid(val
, fixed0
, fixed1
);
4208 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4210 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4211 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4213 return fixed_bits_valid(val
, fixed0
, fixed1
);
4216 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4218 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4219 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4221 return fixed_bits_valid(val
, fixed0
, fixed1
);
4224 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4225 #define nested_guest_cr4_valid nested_cr4_valid
4226 #define nested_host_cr4_valid nested_cr4_valid
4228 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4230 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4232 struct kvm_vcpu
*vcpu
)
4234 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4235 vmx_decache_cr3(vcpu
);
4236 if (!(cr0
& X86_CR0_PG
)) {
4237 /* From paging/starting to nonpaging */
4238 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4239 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4240 (CPU_BASED_CR3_LOAD_EXITING
|
4241 CPU_BASED_CR3_STORE_EXITING
));
4242 vcpu
->arch
.cr0
= cr0
;
4243 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4244 } else if (!is_paging(vcpu
)) {
4245 /* From nonpaging to paging */
4246 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4247 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4248 ~(CPU_BASED_CR3_LOAD_EXITING
|
4249 CPU_BASED_CR3_STORE_EXITING
));
4250 vcpu
->arch
.cr0
= cr0
;
4251 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4254 if (!(cr0
& X86_CR0_WP
))
4255 *hw_cr0
&= ~X86_CR0_WP
;
4258 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4260 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4261 unsigned long hw_cr0
;
4263 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4264 if (enable_unrestricted_guest
)
4265 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4267 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4269 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4272 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4276 #ifdef CONFIG_X86_64
4277 if (vcpu
->arch
.efer
& EFER_LME
) {
4278 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4280 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4286 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4288 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4289 vmcs_writel(GUEST_CR0
, hw_cr0
);
4290 vcpu
->arch
.cr0
= cr0
;
4292 /* depends on vcpu->arch.cr0 to be set to a new value */
4293 vmx
->emulation_required
= emulation_required(vcpu
);
4296 static int get_ept_level(struct kvm_vcpu
*vcpu
)
4298 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
4303 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4305 u64 eptp
= VMX_EPTP_MT_WB
;
4307 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
4309 if (enable_ept_ad_bits
&&
4310 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4311 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
4312 eptp
|= (root_hpa
& PAGE_MASK
);
4317 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4319 unsigned long guest_cr3
;
4324 eptp
= construct_eptp(vcpu
, cr3
);
4325 vmcs_write64(EPT_POINTER
, eptp
);
4326 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4327 guest_cr3
= kvm_read_cr3(vcpu
);
4329 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4330 ept_load_pdptrs(vcpu
);
4333 vmx_flush_tlb(vcpu
);
4334 vmcs_writel(GUEST_CR3
, guest_cr3
);
4337 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4340 * Pass through host's Machine Check Enable value to hw_cr4, which
4341 * is in force while we are in guest mode. Do not let guests control
4342 * this bit, even if host CR4.MCE == 0.
4344 unsigned long hw_cr4
=
4345 (cr4_read_shadow() & X86_CR4_MCE
) |
4346 (cr4
& ~X86_CR4_MCE
) |
4347 (to_vmx(vcpu
)->rmode
.vm86_active
?
4348 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4350 if (cr4
& X86_CR4_VMXE
) {
4352 * To use VMXON (and later other VMX instructions), a guest
4353 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4354 * So basically the check on whether to allow nested VMX
4357 if (!nested_vmx_allowed(vcpu
))
4361 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4364 vcpu
->arch
.cr4
= cr4
;
4366 if (!is_paging(vcpu
)) {
4367 hw_cr4
&= ~X86_CR4_PAE
;
4368 hw_cr4
|= X86_CR4_PSE
;
4369 } else if (!(cr4
& X86_CR4_PAE
)) {
4370 hw_cr4
&= ~X86_CR4_PAE
;
4374 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4376 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4377 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4378 * to be manually disabled when guest switches to non-paging
4381 * If !enable_unrestricted_guest, the CPU is always running
4382 * with CR0.PG=1 and CR4 needs to be modified.
4383 * If enable_unrestricted_guest, the CPU automatically
4384 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4386 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4388 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4389 vmcs_writel(GUEST_CR4
, hw_cr4
);
4393 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4394 struct kvm_segment
*var
, int seg
)
4396 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4399 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4400 *var
= vmx
->rmode
.segs
[seg
];
4401 if (seg
== VCPU_SREG_TR
4402 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4404 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4405 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4408 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4409 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4410 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4411 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4412 var
->unusable
= (ar
>> 16) & 1;
4413 var
->type
= ar
& 15;
4414 var
->s
= (ar
>> 4) & 1;
4415 var
->dpl
= (ar
>> 5) & 3;
4417 * Some userspaces do not preserve unusable property. Since usable
4418 * segment has to be present according to VMX spec we can use present
4419 * property to amend userspace bug by making unusable segment always
4420 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4421 * segment as unusable.
4423 var
->present
= !var
->unusable
;
4424 var
->avl
= (ar
>> 12) & 1;
4425 var
->l
= (ar
>> 13) & 1;
4426 var
->db
= (ar
>> 14) & 1;
4427 var
->g
= (ar
>> 15) & 1;
4430 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4432 struct kvm_segment s
;
4434 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4435 vmx_get_segment(vcpu
, &s
, seg
);
4438 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4441 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4443 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4445 if (unlikely(vmx
->rmode
.vm86_active
))
4448 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4449 return VMX_AR_DPL(ar
);
4453 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4457 if (var
->unusable
|| !var
->present
)
4460 ar
= var
->type
& 15;
4461 ar
|= (var
->s
& 1) << 4;
4462 ar
|= (var
->dpl
& 3) << 5;
4463 ar
|= (var
->present
& 1) << 7;
4464 ar
|= (var
->avl
& 1) << 12;
4465 ar
|= (var
->l
& 1) << 13;
4466 ar
|= (var
->db
& 1) << 14;
4467 ar
|= (var
->g
& 1) << 15;
4473 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4474 struct kvm_segment
*var
, int seg
)
4476 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4477 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4479 vmx_segment_cache_clear(vmx
);
4481 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4482 vmx
->rmode
.segs
[seg
] = *var
;
4483 if (seg
== VCPU_SREG_TR
)
4484 vmcs_write16(sf
->selector
, var
->selector
);
4486 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4490 vmcs_writel(sf
->base
, var
->base
);
4491 vmcs_write32(sf
->limit
, var
->limit
);
4492 vmcs_write16(sf
->selector
, var
->selector
);
4495 * Fix the "Accessed" bit in AR field of segment registers for older
4497 * IA32 arch specifies that at the time of processor reset the
4498 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4499 * is setting it to 0 in the userland code. This causes invalid guest
4500 * state vmexit when "unrestricted guest" mode is turned on.
4501 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4502 * tree. Newer qemu binaries with that qemu fix would not need this
4505 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4506 var
->type
|= 0x1; /* Accessed */
4508 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4511 vmx
->emulation_required
= emulation_required(vcpu
);
4514 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4516 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4518 *db
= (ar
>> 14) & 1;
4519 *l
= (ar
>> 13) & 1;
4522 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4524 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4525 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4528 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4530 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4531 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4534 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4536 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4537 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4540 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4542 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4543 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4546 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4548 struct kvm_segment var
;
4551 vmx_get_segment(vcpu
, &var
, seg
);
4553 if (seg
== VCPU_SREG_CS
)
4555 ar
= vmx_segment_access_rights(&var
);
4557 if (var
.base
!= (var
.selector
<< 4))
4559 if (var
.limit
!= 0xffff)
4567 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4569 struct kvm_segment cs
;
4570 unsigned int cs_rpl
;
4572 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4573 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4577 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4581 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4582 if (cs
.dpl
> cs_rpl
)
4585 if (cs
.dpl
!= cs_rpl
)
4591 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4595 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4597 struct kvm_segment ss
;
4598 unsigned int ss_rpl
;
4600 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4601 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4605 if (ss
.type
!= 3 && ss
.type
!= 7)
4609 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4617 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4619 struct kvm_segment var
;
4622 vmx_get_segment(vcpu
, &var
, seg
);
4623 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4631 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4632 if (var
.dpl
< rpl
) /* DPL < RPL */
4636 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4642 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4644 struct kvm_segment tr
;
4646 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4650 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4652 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4660 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4662 struct kvm_segment ldtr
;
4664 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4668 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4678 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4680 struct kvm_segment cs
, ss
;
4682 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4683 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4685 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4686 (ss
.selector
& SEGMENT_RPL_MASK
));
4690 * Check if guest state is valid. Returns true if valid, false if
4692 * We assume that registers are always usable
4694 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4696 if (enable_unrestricted_guest
)
4699 /* real mode guest state checks */
4700 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4701 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4703 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4705 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4707 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4709 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4711 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4714 /* protected mode guest state checks */
4715 if (!cs_ss_rpl_check(vcpu
))
4717 if (!code_segment_valid(vcpu
))
4719 if (!stack_segment_valid(vcpu
))
4721 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4723 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4725 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4727 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4729 if (!tr_valid(vcpu
))
4731 if (!ldtr_valid(vcpu
))
4735 * - Add checks on RIP
4736 * - Add checks on RFLAGS
4742 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4744 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4747 static int init_rmode_tss(struct kvm
*kvm
)
4753 idx
= srcu_read_lock(&kvm
->srcu
);
4754 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4755 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4758 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4759 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4760 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4763 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4766 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4770 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4771 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4774 srcu_read_unlock(&kvm
->srcu
, idx
);
4778 static int init_rmode_identity_map(struct kvm
*kvm
)
4781 kvm_pfn_t identity_map_pfn
;
4787 /* Protect kvm->arch.ept_identity_pagetable_done. */
4788 mutex_lock(&kvm
->slots_lock
);
4790 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4793 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4795 r
= alloc_identity_pagetable(kvm
);
4799 idx
= srcu_read_lock(&kvm
->srcu
);
4800 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4803 /* Set up identity-mapping pagetable for EPT in real mode */
4804 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4805 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4806 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4807 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4808 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4812 kvm
->arch
.ept_identity_pagetable_done
= true;
4815 srcu_read_unlock(&kvm
->srcu
, idx
);
4818 mutex_unlock(&kvm
->slots_lock
);
4822 static void seg_setup(int seg
)
4824 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4827 vmcs_write16(sf
->selector
, 0);
4828 vmcs_writel(sf
->base
, 0);
4829 vmcs_write32(sf
->limit
, 0xffff);
4831 if (seg
== VCPU_SREG_CS
)
4832 ar
|= 0x08; /* code segment */
4834 vmcs_write32(sf
->ar_bytes
, ar
);
4837 static int alloc_apic_access_page(struct kvm
*kvm
)
4842 mutex_lock(&kvm
->slots_lock
);
4843 if (kvm
->arch
.apic_access_page_done
)
4845 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4846 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4850 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4851 if (is_error_page(page
)) {
4857 * Do not pin the page in memory, so that memory hot-unplug
4858 * is able to migrate it.
4861 kvm
->arch
.apic_access_page_done
= true;
4863 mutex_unlock(&kvm
->slots_lock
);
4867 static int alloc_identity_pagetable(struct kvm
*kvm
)
4869 /* Called with kvm->slots_lock held. */
4873 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4875 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4876 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4881 static int allocate_vpid(void)
4887 spin_lock(&vmx_vpid_lock
);
4888 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4889 if (vpid
< VMX_NR_VPIDS
)
4890 __set_bit(vpid
, vmx_vpid_bitmap
);
4893 spin_unlock(&vmx_vpid_lock
);
4897 static void free_vpid(int vpid
)
4899 if (!enable_vpid
|| vpid
== 0)
4901 spin_lock(&vmx_vpid_lock
);
4902 __clear_bit(vpid
, vmx_vpid_bitmap
);
4903 spin_unlock(&vmx_vpid_lock
);
4906 #define MSR_TYPE_R 1
4907 #define MSR_TYPE_W 2
4908 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4911 int f
= sizeof(unsigned long);
4913 if (!cpu_has_vmx_msr_bitmap())
4917 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4918 * have the write-low and read-high bitmap offsets the wrong way round.
4919 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4921 if (msr
<= 0x1fff) {
4922 if (type
& MSR_TYPE_R
)
4924 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4926 if (type
& MSR_TYPE_W
)
4928 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4930 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4932 if (type
& MSR_TYPE_R
)
4934 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4936 if (type
& MSR_TYPE_W
)
4938 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4944 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4945 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4947 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4948 unsigned long *msr_bitmap_nested
,
4951 int f
= sizeof(unsigned long);
4953 if (!cpu_has_vmx_msr_bitmap()) {
4959 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4960 * have the write-low and read-high bitmap offsets the wrong way round.
4961 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4963 if (msr
<= 0x1fff) {
4964 if (type
& MSR_TYPE_R
&&
4965 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4967 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4969 if (type
& MSR_TYPE_W
&&
4970 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4972 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4974 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4976 if (type
& MSR_TYPE_R
&&
4977 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4979 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4981 if (type
& MSR_TYPE_W
&&
4982 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4984 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4989 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4992 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4993 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4994 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4995 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4998 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
5001 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
5003 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
5006 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
5008 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
5013 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5015 return enable_apicv
;
5018 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5020 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5024 * Don't need to mark the APIC access page dirty; it is never
5025 * written to by the CPU during APIC virtualization.
5028 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5029 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5030 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5033 if (nested_cpu_has_posted_intr(vmcs12
)) {
5034 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5035 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5040 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5042 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5047 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5050 vmx
->nested
.pi_pending
= false;
5051 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5054 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5055 if (max_irr
!= 256) {
5056 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5057 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5058 kunmap(vmx
->nested
.virtual_apic_page
);
5060 status
= vmcs_read16(GUEST_INTR_STATUS
);
5061 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5063 status
|= (u8
)max_irr
;
5064 vmcs_write16(GUEST_INTR_STATUS
, status
);
5068 nested_mark_vmcs12_pages_dirty(vcpu
);
5071 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5075 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5077 if (vcpu
->mode
== IN_GUEST_MODE
) {
5079 * The vector of interrupt to be delivered to vcpu had
5080 * been set in PIR before this function.
5082 * Following cases will be reached in this block, and
5083 * we always send a notification event in all cases as
5086 * Case 1: vcpu keeps in non-root mode. Sending a
5087 * notification event posts the interrupt to vcpu.
5089 * Case 2: vcpu exits to root mode and is still
5090 * runnable. PIR will be synced to vIRR before the
5091 * next vcpu entry. Sending a notification event in
5092 * this case has no effect, as vcpu is not in root
5095 * Case 3: vcpu exits to root mode and is blocked.
5096 * vcpu_block() has already synced PIR to vIRR and
5097 * never blocks vcpu if vIRR is not cleared. Therefore,
5098 * a blocked vcpu here does not wait for any requested
5099 * interrupts in PIR, and sending a notification event
5100 * which has no effect is safe here.
5103 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5110 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5113 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5115 if (is_guest_mode(vcpu
) &&
5116 vector
== vmx
->nested
.posted_intr_nv
) {
5117 /* the PIR and ON have been set by L1. */
5118 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5120 * If a posted intr is not recognized by hardware,
5121 * we will accomplish it in the next vmentry.
5123 vmx
->nested
.pi_pending
= true;
5124 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5130 * Send interrupt to vcpu via posted interrupt way.
5131 * 1. If target vcpu is running(non-root mode), send posted interrupt
5132 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5133 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5134 * interrupt from PIR in next vmentry.
5136 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5138 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5141 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5145 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5148 /* If a previous notification has sent the IPI, nothing to do. */
5149 if (pi_test_and_set_on(&vmx
->pi_desc
))
5152 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5153 kvm_vcpu_kick(vcpu
);
5157 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5158 * will not change in the lifetime of the guest.
5159 * Note that host-state that does change is set elsewhere. E.g., host-state
5160 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5162 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5167 unsigned long cr0
, cr3
, cr4
;
5170 WARN_ON(cr0
& X86_CR0_TS
);
5171 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5174 * Save the most likely value for this task's CR3 in the VMCS.
5175 * We can't use __get_current_cr3_fast() because we're not atomic.
5178 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5179 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5181 /* Save the most likely value for this task's CR4 in the VMCS. */
5182 cr4
= cr4_read_shadow();
5183 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5184 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5186 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5187 #ifdef CONFIG_X86_64
5189 * Load null selectors, so we can avoid reloading them in
5190 * __vmx_load_host_state(), in case userspace uses the null selectors
5191 * too (the expected case).
5193 vmcs_write16(HOST_DS_SELECTOR
, 0);
5194 vmcs_write16(HOST_ES_SELECTOR
, 0);
5196 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5197 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5199 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5200 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5203 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5204 vmx
->host_idt_base
= dt
.address
;
5206 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5208 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5209 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5210 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5211 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5213 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5214 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5215 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5219 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5221 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5223 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5224 if (is_guest_mode(&vmx
->vcpu
))
5225 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5226 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5227 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5230 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5232 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5234 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5235 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5236 /* Enable the preemption timer dynamically */
5237 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5238 return pin_based_exec_ctrl
;
5241 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5243 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5245 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5246 if (cpu_has_secondary_exec_ctrls()) {
5247 if (kvm_vcpu_apicv_active(vcpu
))
5248 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5249 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5250 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5252 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5253 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5254 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5257 if (cpu_has_vmx_msr_bitmap())
5258 vmx_set_msr_bitmap(vcpu
);
5261 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5263 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5265 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5266 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5268 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5269 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5270 #ifdef CONFIG_X86_64
5271 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5272 CPU_BASED_CR8_LOAD_EXITING
;
5276 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5277 CPU_BASED_CR3_LOAD_EXITING
|
5278 CPU_BASED_INVLPG_EXITING
;
5279 return exec_control
;
5282 static bool vmx_rdrand_supported(void)
5284 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5285 SECONDARY_EXEC_RDRAND
;
5288 static bool vmx_rdseed_supported(void)
5290 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5291 SECONDARY_EXEC_RDSEED
;
5294 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
5296 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
5298 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5299 if (!cpu_need_virtualize_apic_accesses(vcpu
))
5300 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5302 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5304 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5305 enable_unrestricted_guest
= 0;
5306 /* Enable INVPCID for non-ept guests may cause performance regression. */
5307 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5309 if (!enable_unrestricted_guest
)
5310 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5312 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5313 if (!kvm_vcpu_apicv_active(vcpu
))
5314 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5315 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5316 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5317 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5319 We can NOT enable shadow_vmcs here because we don't have yet
5322 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5325 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5327 if (vmx_xsaves_supported()) {
5328 /* Exposing XSAVES only when XSAVE is exposed */
5329 bool xsaves_enabled
=
5330 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
5331 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
5333 if (!xsaves_enabled
)
5334 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
5338 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5339 SECONDARY_EXEC_XSAVES
;
5341 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5342 ~SECONDARY_EXEC_XSAVES
;
5346 if (vmx_rdtscp_supported()) {
5347 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
5348 if (!rdtscp_enabled
)
5349 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5353 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5354 SECONDARY_EXEC_RDTSCP
;
5356 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5357 ~SECONDARY_EXEC_RDTSCP
;
5361 if (vmx_invpcid_supported()) {
5362 /* Exposing INVPCID only when PCID is exposed */
5363 bool invpcid_enabled
=
5364 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
5365 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
5367 if (!invpcid_enabled
) {
5368 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5369 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
5373 if (invpcid_enabled
)
5374 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5375 SECONDARY_EXEC_ENABLE_INVPCID
;
5377 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5378 ~SECONDARY_EXEC_ENABLE_INVPCID
;
5382 if (vmx_rdrand_supported()) {
5383 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
5385 exec_control
&= ~SECONDARY_EXEC_RDRAND
;
5389 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5390 SECONDARY_EXEC_RDRAND
;
5392 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5393 ~SECONDARY_EXEC_RDRAND
;
5397 if (vmx_rdseed_supported()) {
5398 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
5400 exec_control
&= ~SECONDARY_EXEC_RDSEED
;
5404 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5405 SECONDARY_EXEC_RDSEED
;
5407 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5408 ~SECONDARY_EXEC_RDSEED
;
5412 vmx
->secondary_exec_control
= exec_control
;
5415 static void ept_set_mmio_spte_mask(void)
5418 * EPT Misconfigurations can be generated if the value of bits 2:0
5419 * of an EPT paging-structure entry is 110b (write/execute).
5421 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5422 VMX_EPT_MISCONFIG_WX_VALUE
);
5425 #define VMX_XSS_EXIT_BITMAP 0
5427 * Sets up the vmcs for emulated real mode.
5429 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5431 #ifdef CONFIG_X86_64
5437 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5438 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5440 if (enable_shadow_vmcs
) {
5441 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5442 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5444 if (cpu_has_vmx_msr_bitmap())
5445 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5447 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5450 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5451 vmx
->hv_deadline_tsc
= -1;
5453 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5455 if (cpu_has_secondary_exec_ctrls()) {
5456 vmx_compute_secondary_exec_control(vmx
);
5457 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5458 vmx
->secondary_exec_control
);
5461 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5462 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5463 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5464 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5465 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5467 vmcs_write16(GUEST_INTR_STATUS
, 0);
5469 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5470 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5474 vmcs_write32(PLE_GAP
, ple_gap
);
5475 vmx
->ple_window
= ple_window
;
5476 vmx
->ple_window_dirty
= true;
5479 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5480 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5481 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5483 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5484 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5485 vmx_set_constant_host_state(vmx
);
5486 #ifdef CONFIG_X86_64
5487 rdmsrl(MSR_FS_BASE
, a
);
5488 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5489 rdmsrl(MSR_GS_BASE
, a
);
5490 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5492 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5493 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5496 if (cpu_has_vmx_vmfunc())
5497 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5499 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5500 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5501 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5502 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5503 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5505 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5506 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5508 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5509 u32 index
= vmx_msr_index
[i
];
5510 u32 data_low
, data_high
;
5513 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5515 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5517 vmx
->guest_msrs
[j
].index
= i
;
5518 vmx
->guest_msrs
[j
].data
= 0;
5519 vmx
->guest_msrs
[j
].mask
= -1ull;
5524 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5526 /* 22.2.1, 20.8.1 */
5527 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5529 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5530 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5532 set_cr4_guest_host_mask(vmx
);
5534 if (vmx_xsaves_supported())
5535 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5538 ASSERT(vmx
->pml_pg
);
5539 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5540 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5546 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5548 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5549 struct msr_data apic_base_msr
;
5552 vmx
->rmode
.vm86_active
= 0;
5554 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5555 kvm_set_cr8(vcpu
, 0);
5558 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5559 MSR_IA32_APICBASE_ENABLE
;
5560 if (kvm_vcpu_is_reset_bsp(vcpu
))
5561 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5562 apic_base_msr
.host_initiated
= true;
5563 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5566 vmx_segment_cache_clear(vmx
);
5568 seg_setup(VCPU_SREG_CS
);
5569 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5570 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5572 seg_setup(VCPU_SREG_DS
);
5573 seg_setup(VCPU_SREG_ES
);
5574 seg_setup(VCPU_SREG_FS
);
5575 seg_setup(VCPU_SREG_GS
);
5576 seg_setup(VCPU_SREG_SS
);
5578 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5579 vmcs_writel(GUEST_TR_BASE
, 0);
5580 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5581 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5583 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5584 vmcs_writel(GUEST_LDTR_BASE
, 0);
5585 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5586 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5589 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5590 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5591 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5592 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5595 vmcs_writel(GUEST_RFLAGS
, 0x02);
5596 kvm_rip_write(vcpu
, 0xfff0);
5598 vmcs_writel(GUEST_GDTR_BASE
, 0);
5599 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5601 vmcs_writel(GUEST_IDTR_BASE
, 0);
5602 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5604 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5605 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5606 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5610 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5612 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5613 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5614 if (cpu_need_tpr_shadow(vcpu
))
5615 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5616 __pa(vcpu
->arch
.apic
->regs
));
5617 vmcs_write32(TPR_THRESHOLD
, 0);
5620 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5623 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5625 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5626 vmx
->vcpu
.arch
.cr0
= cr0
;
5627 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5628 vmx_set_cr4(vcpu
, 0);
5629 vmx_set_efer(vcpu
, 0);
5631 update_exception_bitmap(vcpu
);
5633 vpid_sync_context(vmx
->vpid
);
5637 * In nested virtualization, check if L1 asked to exit on external interrupts.
5638 * For most existing hypervisors, this will always return true.
5640 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5642 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5643 PIN_BASED_EXT_INTR_MASK
;
5647 * In nested virtualization, check if L1 has set
5648 * VM_EXIT_ACK_INTR_ON_EXIT
5650 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5652 return get_vmcs12(vcpu
)->vm_exit_controls
&
5653 VM_EXIT_ACK_INTR_ON_EXIT
;
5656 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5658 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5659 PIN_BASED_NMI_EXITING
;
5662 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5664 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5665 CPU_BASED_VIRTUAL_INTR_PENDING
);
5668 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5670 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5671 enable_irq_window(vcpu
);
5675 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5676 CPU_BASED_VIRTUAL_NMI_PENDING
);
5679 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5681 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5683 int irq
= vcpu
->arch
.interrupt
.nr
;
5685 trace_kvm_inj_virq(irq
);
5687 ++vcpu
->stat
.irq_injections
;
5688 if (vmx
->rmode
.vm86_active
) {
5690 if (vcpu
->arch
.interrupt
.soft
)
5691 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5692 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5693 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5696 intr
= irq
| INTR_INFO_VALID_MASK
;
5697 if (vcpu
->arch
.interrupt
.soft
) {
5698 intr
|= INTR_TYPE_SOFT_INTR
;
5699 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5700 vmx
->vcpu
.arch
.event_exit_inst_len
);
5702 intr
|= INTR_TYPE_EXT_INTR
;
5703 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5706 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5708 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5710 ++vcpu
->stat
.nmi_injections
;
5711 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5713 if (vmx
->rmode
.vm86_active
) {
5714 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5715 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5719 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5720 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5723 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5725 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5728 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5730 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5731 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5735 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5737 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5739 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5741 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5742 GUEST_INTR_STATE_NMI
);
5744 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5745 GUEST_INTR_STATE_NMI
);
5748 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5750 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5753 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5754 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5755 | GUEST_INTR_STATE_NMI
));
5758 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5760 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5761 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5762 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5763 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5766 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5770 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5774 kvm
->arch
.tss_addr
= addr
;
5775 return init_rmode_tss(kvm
);
5778 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5783 * Update instruction length as we may reinject the exception
5784 * from user space while in guest debugging mode.
5786 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5787 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5788 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5792 if (vcpu
->guest_debug
&
5793 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5810 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5811 int vec
, u32 err_code
)
5814 * Instruction with address size override prefix opcode 0x67
5815 * Cause the #SS fault with 0 error code in VM86 mode.
5817 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5818 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5819 if (vcpu
->arch
.halt_request
) {
5820 vcpu
->arch
.halt_request
= 0;
5821 return kvm_vcpu_halt(vcpu
);
5829 * Forward all other exceptions that are valid in real mode.
5830 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5831 * the required debugging infrastructure rework.
5833 kvm_queue_exception(vcpu
, vec
);
5838 * Trigger machine check on the host. We assume all the MSRs are already set up
5839 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5840 * We pass a fake environment to the machine check handler because we want
5841 * the guest to be always treated like user space, no matter what context
5842 * it used internally.
5844 static void kvm_machine_check(void)
5846 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5847 struct pt_regs regs
= {
5848 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5849 .flags
= X86_EFLAGS_IF
,
5852 do_machine_check(®s
, 0);
5856 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5858 /* already handled by vcpu_run */
5862 static int handle_exception(struct kvm_vcpu
*vcpu
)
5864 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5865 struct kvm_run
*kvm_run
= vcpu
->run
;
5866 u32 intr_info
, ex_no
, error_code
;
5867 unsigned long cr2
, rip
, dr6
;
5869 enum emulation_result er
;
5871 vect_info
= vmx
->idt_vectoring_info
;
5872 intr_info
= vmx
->exit_intr_info
;
5874 if (is_machine_check(intr_info
))
5875 return handle_machine_check(vcpu
);
5877 if (is_nmi(intr_info
))
5878 return 1; /* already handled by vmx_vcpu_run() */
5880 if (is_invalid_opcode(intr_info
)) {
5881 if (is_guest_mode(vcpu
)) {
5882 kvm_queue_exception(vcpu
, UD_VECTOR
);
5885 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5886 if (er
!= EMULATE_DONE
)
5887 kvm_queue_exception(vcpu
, UD_VECTOR
);
5892 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5893 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5896 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5897 * MMIO, it is better to report an internal error.
5898 * See the comments in vmx_handle_exit.
5900 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5901 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5902 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5903 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5904 vcpu
->run
->internal
.ndata
= 3;
5905 vcpu
->run
->internal
.data
[0] = vect_info
;
5906 vcpu
->run
->internal
.data
[1] = intr_info
;
5907 vcpu
->run
->internal
.data
[2] = error_code
;
5911 if (is_page_fault(intr_info
)) {
5912 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5913 /* EPT won't cause page fault directly */
5914 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5915 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0,
5919 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5921 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5922 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5926 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5929 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5930 if (!(vcpu
->guest_debug
&
5931 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5932 vcpu
->arch
.dr6
&= ~15;
5933 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5934 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5935 skip_emulated_instruction(vcpu
);
5937 kvm_queue_exception(vcpu
, DB_VECTOR
);
5940 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5941 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5945 * Update instruction length as we may reinject #BP from
5946 * user space while in guest debugging mode. Reading it for
5947 * #DB as well causes no harm, it is not used in that case.
5949 vmx
->vcpu
.arch
.event_exit_inst_len
=
5950 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5951 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5952 rip
= kvm_rip_read(vcpu
);
5953 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5954 kvm_run
->debug
.arch
.exception
= ex_no
;
5957 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5958 kvm_run
->ex
.exception
= ex_no
;
5959 kvm_run
->ex
.error_code
= error_code
;
5965 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5967 ++vcpu
->stat
.irq_exits
;
5971 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5973 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5974 vcpu
->mmio_needed
= 0;
5978 static int handle_io(struct kvm_vcpu
*vcpu
)
5980 unsigned long exit_qualification
;
5981 int size
, in
, string
, ret
;
5984 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5985 string
= (exit_qualification
& 16) != 0;
5986 in
= (exit_qualification
& 8) != 0;
5988 ++vcpu
->stat
.io_exits
;
5991 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5993 port
= exit_qualification
>> 16;
5994 size
= (exit_qualification
& 7) + 1;
5996 ret
= kvm_skip_emulated_instruction(vcpu
);
5999 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6000 * KVM_EXIT_DEBUG here.
6002 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
6006 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
6009 * Patch in the VMCALL instruction:
6011 hypercall
[0] = 0x0f;
6012 hypercall
[1] = 0x01;
6013 hypercall
[2] = 0xc1;
6016 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6017 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
6019 if (is_guest_mode(vcpu
)) {
6020 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6021 unsigned long orig_val
= val
;
6024 * We get here when L2 changed cr0 in a way that did not change
6025 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6026 * but did change L0 shadowed bits. So we first calculate the
6027 * effective cr0 value that L1 would like to write into the
6028 * hardware. It consists of the L2-owned bits from the new
6029 * value combined with the L1-owned bits from L1's guest_cr0.
6031 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
6032 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
6034 if (!nested_guest_cr0_valid(vcpu
, val
))
6037 if (kvm_set_cr0(vcpu
, val
))
6039 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
6042 if (to_vmx(vcpu
)->nested
.vmxon
&&
6043 !nested_host_cr0_valid(vcpu
, val
))
6046 return kvm_set_cr0(vcpu
, val
);
6050 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
6052 if (is_guest_mode(vcpu
)) {
6053 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6054 unsigned long orig_val
= val
;
6056 /* analogously to handle_set_cr0 */
6057 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
6058 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
6059 if (kvm_set_cr4(vcpu
, val
))
6061 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
6064 return kvm_set_cr4(vcpu
, val
);
6067 static int handle_cr(struct kvm_vcpu
*vcpu
)
6069 unsigned long exit_qualification
, val
;
6075 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6076 cr
= exit_qualification
& 15;
6077 reg
= (exit_qualification
>> 8) & 15;
6078 switch ((exit_qualification
>> 4) & 3) {
6079 case 0: /* mov to cr */
6080 val
= kvm_register_readl(vcpu
, reg
);
6081 trace_kvm_cr_write(cr
, val
);
6084 err
= handle_set_cr0(vcpu
, val
);
6085 return kvm_complete_insn_gp(vcpu
, err
);
6087 err
= kvm_set_cr3(vcpu
, val
);
6088 return kvm_complete_insn_gp(vcpu
, err
);
6090 err
= handle_set_cr4(vcpu
, val
);
6091 return kvm_complete_insn_gp(vcpu
, err
);
6093 u8 cr8_prev
= kvm_get_cr8(vcpu
);
6095 err
= kvm_set_cr8(vcpu
, cr8
);
6096 ret
= kvm_complete_insn_gp(vcpu
, err
);
6097 if (lapic_in_kernel(vcpu
))
6099 if (cr8_prev
<= cr8
)
6102 * TODO: we might be squashing a
6103 * KVM_GUESTDBG_SINGLESTEP-triggered
6104 * KVM_EXIT_DEBUG here.
6106 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6112 WARN_ONCE(1, "Guest should always own CR0.TS");
6113 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6114 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6115 return kvm_skip_emulated_instruction(vcpu
);
6116 case 1: /*mov from cr*/
6119 val
= kvm_read_cr3(vcpu
);
6120 kvm_register_write(vcpu
, reg
, val
);
6121 trace_kvm_cr_read(cr
, val
);
6122 return kvm_skip_emulated_instruction(vcpu
);
6124 val
= kvm_get_cr8(vcpu
);
6125 kvm_register_write(vcpu
, reg
, val
);
6126 trace_kvm_cr_read(cr
, val
);
6127 return kvm_skip_emulated_instruction(vcpu
);
6131 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6132 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6133 kvm_lmsw(vcpu
, val
);
6135 return kvm_skip_emulated_instruction(vcpu
);
6139 vcpu
->run
->exit_reason
= 0;
6140 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6141 (int)(exit_qualification
>> 4) & 3, cr
);
6145 static int handle_dr(struct kvm_vcpu
*vcpu
)
6147 unsigned long exit_qualification
;
6150 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6151 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6153 /* First, if DR does not exist, trigger UD */
6154 if (!kvm_require_dr(vcpu
, dr
))
6157 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6158 if (!kvm_require_cpl(vcpu
, 0))
6160 dr7
= vmcs_readl(GUEST_DR7
);
6163 * As the vm-exit takes precedence over the debug trap, we
6164 * need to emulate the latter, either for the host or the
6165 * guest debugging itself.
6167 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6168 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6169 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6170 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6171 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6172 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6175 vcpu
->arch
.dr6
&= ~15;
6176 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6177 kvm_queue_exception(vcpu
, DB_VECTOR
);
6182 if (vcpu
->guest_debug
== 0) {
6183 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6184 CPU_BASED_MOV_DR_EXITING
);
6187 * No more DR vmexits; force a reload of the debug registers
6188 * and reenter on this instruction. The next vmexit will
6189 * retrieve the full state of the debug registers.
6191 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6195 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6196 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6199 if (kvm_get_dr(vcpu
, dr
, &val
))
6201 kvm_register_write(vcpu
, reg
, val
);
6203 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6206 return kvm_skip_emulated_instruction(vcpu
);
6209 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6211 return vcpu
->arch
.dr6
;
6214 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6218 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6220 get_debugreg(vcpu
->arch
.db
[0], 0);
6221 get_debugreg(vcpu
->arch
.db
[1], 1);
6222 get_debugreg(vcpu
->arch
.db
[2], 2);
6223 get_debugreg(vcpu
->arch
.db
[3], 3);
6224 get_debugreg(vcpu
->arch
.dr6
, 6);
6225 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6227 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6228 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6231 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6233 vmcs_writel(GUEST_DR7
, val
);
6236 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6238 return kvm_emulate_cpuid(vcpu
);
6241 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6243 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6244 struct msr_data msr_info
;
6246 msr_info
.index
= ecx
;
6247 msr_info
.host_initiated
= false;
6248 if (vmx_get_msr(vcpu
, &msr_info
)) {
6249 trace_kvm_msr_read_ex(ecx
);
6250 kvm_inject_gp(vcpu
, 0);
6254 trace_kvm_msr_read(ecx
, msr_info
.data
);
6256 /* FIXME: handling of bits 32:63 of rax, rdx */
6257 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6258 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6259 return kvm_skip_emulated_instruction(vcpu
);
6262 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6264 struct msr_data msr
;
6265 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6266 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6267 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6271 msr
.host_initiated
= false;
6272 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6273 trace_kvm_msr_write_ex(ecx
, data
);
6274 kvm_inject_gp(vcpu
, 0);
6278 trace_kvm_msr_write(ecx
, data
);
6279 return kvm_skip_emulated_instruction(vcpu
);
6282 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6284 kvm_apic_update_ppr(vcpu
);
6288 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6290 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6291 CPU_BASED_VIRTUAL_INTR_PENDING
);
6293 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6295 ++vcpu
->stat
.irq_window_exits
;
6299 static int handle_halt(struct kvm_vcpu
*vcpu
)
6301 return kvm_emulate_halt(vcpu
);
6304 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6306 return kvm_emulate_hypercall(vcpu
);
6309 static int handle_invd(struct kvm_vcpu
*vcpu
)
6311 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6314 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6316 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6318 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6319 return kvm_skip_emulated_instruction(vcpu
);
6322 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6326 err
= kvm_rdpmc(vcpu
);
6327 return kvm_complete_insn_gp(vcpu
, err
);
6330 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6332 return kvm_emulate_wbinvd(vcpu
);
6335 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6337 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6338 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6340 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6341 return kvm_skip_emulated_instruction(vcpu
);
6345 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6347 kvm_skip_emulated_instruction(vcpu
);
6348 WARN(1, "this should never happen\n");
6352 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6354 kvm_skip_emulated_instruction(vcpu
);
6355 WARN(1, "this should never happen\n");
6359 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6361 if (likely(fasteoi
)) {
6362 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6363 int access_type
, offset
;
6365 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6366 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6368 * Sane guest uses MOV to write EOI, with written value
6369 * not cared. So make a short-circuit here by avoiding
6370 * heavy instruction emulation.
6372 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6373 (offset
== APIC_EOI
)) {
6374 kvm_lapic_set_eoi(vcpu
);
6375 return kvm_skip_emulated_instruction(vcpu
);
6378 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6381 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6383 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6384 int vector
= exit_qualification
& 0xff;
6386 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6387 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6391 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6393 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6394 u32 offset
= exit_qualification
& 0xfff;
6396 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6397 kvm_apic_write_nodecode(vcpu
, offset
);
6401 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6403 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6404 unsigned long exit_qualification
;
6405 bool has_error_code
= false;
6408 int reason
, type
, idt_v
, idt_index
;
6410 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6411 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6412 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6414 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6416 reason
= (u32
)exit_qualification
>> 30;
6417 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6419 case INTR_TYPE_NMI_INTR
:
6420 vcpu
->arch
.nmi_injected
= false;
6421 vmx_set_nmi_mask(vcpu
, true);
6423 case INTR_TYPE_EXT_INTR
:
6424 case INTR_TYPE_SOFT_INTR
:
6425 kvm_clear_interrupt_queue(vcpu
);
6427 case INTR_TYPE_HARD_EXCEPTION
:
6428 if (vmx
->idt_vectoring_info
&
6429 VECTORING_INFO_DELIVER_CODE_MASK
) {
6430 has_error_code
= true;
6432 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6435 case INTR_TYPE_SOFT_EXCEPTION
:
6436 kvm_clear_exception_queue(vcpu
);
6442 tss_selector
= exit_qualification
;
6444 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6445 type
!= INTR_TYPE_EXT_INTR
&&
6446 type
!= INTR_TYPE_NMI_INTR
))
6447 skip_emulated_instruction(vcpu
);
6449 if (kvm_task_switch(vcpu
, tss_selector
,
6450 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6451 has_error_code
, error_code
) == EMULATE_FAIL
) {
6452 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6453 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6454 vcpu
->run
->internal
.ndata
= 0;
6459 * TODO: What about debug traps on tss switch?
6460 * Are we supposed to inject them and update dr6?
6466 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6468 unsigned long exit_qualification
;
6472 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6475 * EPT violation happened while executing iret from NMI,
6476 * "blocked by NMI" bit has to be set before next VM entry.
6477 * There are errata that may cause this bit to not be set:
6480 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6481 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6482 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6484 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6485 trace_kvm_page_fault(gpa
, exit_qualification
);
6487 /* Is it a read fault? */
6488 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6489 ? PFERR_USER_MASK
: 0;
6490 /* Is it a write fault? */
6491 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6492 ? PFERR_WRITE_MASK
: 0;
6493 /* Is it a fetch fault? */
6494 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6495 ? PFERR_FETCH_MASK
: 0;
6496 /* ept page table entry is present? */
6497 error_code
|= (exit_qualification
&
6498 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6499 EPT_VIOLATION_EXECUTABLE
))
6500 ? PFERR_PRESENT_MASK
: 0;
6502 error_code
|= (exit_qualification
& 0x100) != 0 ?
6503 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6505 vcpu
->arch
.exit_qualification
= exit_qualification
;
6506 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6509 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6515 * A nested guest cannot optimize MMIO vmexits, because we have an
6516 * nGPA here instead of the required GPA.
6518 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6519 if (!is_guest_mode(vcpu
) &&
6520 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6521 trace_kvm_fast_mmio(gpa
);
6522 return kvm_skip_emulated_instruction(vcpu
);
6525 ret
= kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
6529 /* It is the real ept misconfig */
6532 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6533 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6538 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6540 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6541 CPU_BASED_VIRTUAL_NMI_PENDING
);
6542 ++vcpu
->stat
.nmi_window_exits
;
6543 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6548 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6550 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6551 enum emulation_result err
= EMULATE_DONE
;
6554 bool intr_window_requested
;
6555 unsigned count
= 130;
6557 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6558 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6560 while (vmx
->emulation_required
&& count
-- != 0) {
6561 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6562 return handle_interrupt_window(&vmx
->vcpu
);
6564 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6567 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6569 if (err
== EMULATE_USER_EXIT
) {
6570 ++vcpu
->stat
.mmio_exits
;
6575 if (err
!= EMULATE_DONE
) {
6576 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6577 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6578 vcpu
->run
->internal
.ndata
= 0;
6582 if (vcpu
->arch
.halt_request
) {
6583 vcpu
->arch
.halt_request
= 0;
6584 ret
= kvm_vcpu_halt(vcpu
);
6588 if (signal_pending(current
))
6598 static int __grow_ple_window(int val
)
6600 if (ple_window_grow
< 1)
6603 val
= min(val
, ple_window_actual_max
);
6605 if (ple_window_grow
< ple_window
)
6606 val
*= ple_window_grow
;
6608 val
+= ple_window_grow
;
6613 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6618 if (modifier
< ple_window
)
6623 return max(val
, minimum
);
6626 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6628 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6629 int old
= vmx
->ple_window
;
6631 vmx
->ple_window
= __grow_ple_window(old
);
6633 if (vmx
->ple_window
!= old
)
6634 vmx
->ple_window_dirty
= true;
6636 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6639 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6641 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6642 int old
= vmx
->ple_window
;
6644 vmx
->ple_window
= __shrink_ple_window(old
,
6645 ple_window_shrink
, ple_window
);
6647 if (vmx
->ple_window
!= old
)
6648 vmx
->ple_window_dirty
= true;
6650 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6654 * ple_window_actual_max is computed to be one grow_ple_window() below
6655 * ple_window_max. (See __grow_ple_window for the reason.)
6656 * This prevents overflows, because ple_window_max is int.
6657 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6659 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6661 static void update_ple_window_actual_max(void)
6663 ple_window_actual_max
=
6664 __shrink_ple_window(max(ple_window_max
, ple_window
),
6665 ple_window_grow
, INT_MIN
);
6669 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6671 static void wakeup_handler(void)
6673 struct kvm_vcpu
*vcpu
;
6674 int cpu
= smp_processor_id();
6676 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6677 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6678 blocked_vcpu_list
) {
6679 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6681 if (pi_test_on(pi_desc
) == 1)
6682 kvm_vcpu_kick(vcpu
);
6684 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6687 void vmx_enable_tdp(void)
6689 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6690 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6691 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6692 0ull, VMX_EPT_EXECUTABLE_MASK
,
6693 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6694 VMX_EPT_RWX_MASK
, 0ull);
6696 ept_set_mmio_spte_mask();
6700 static __init
int hardware_setup(void)
6702 int r
= -ENOMEM
, i
, msr
;
6704 rdmsrl_safe(MSR_EFER
, &host_efer
);
6706 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6707 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6709 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6710 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6715 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6716 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6717 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6720 * Allow direct access to the PC debug port (it is often used for I/O
6721 * delays, but the vmexits simply slow things down).
6723 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6724 clear_bit(0x80, vmx_io_bitmap_a
);
6726 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6728 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6729 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6731 if (setup_vmcs_config(&vmcs_config
) < 0) {
6736 if (boot_cpu_has(X86_FEATURE_NX
))
6737 kvm_enable_efer_bits(EFER_NX
);
6739 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6740 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6743 if (!cpu_has_vmx_shadow_vmcs())
6744 enable_shadow_vmcs
= 0;
6745 if (enable_shadow_vmcs
)
6746 init_vmcs_shadow_fields();
6748 if (!cpu_has_vmx_ept() ||
6749 !cpu_has_vmx_ept_4levels() ||
6750 !cpu_has_vmx_ept_mt_wb()) {
6752 enable_unrestricted_guest
= 0;
6753 enable_ept_ad_bits
= 0;
6756 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6757 enable_ept_ad_bits
= 0;
6759 if (!cpu_has_vmx_unrestricted_guest())
6760 enable_unrestricted_guest
= 0;
6762 if (!cpu_has_vmx_flexpriority())
6763 flexpriority_enabled
= 0;
6766 * set_apic_access_page_addr() is used to reload apic access
6767 * page upon invalidation. No need to do anything if not
6768 * using the APIC_ACCESS_ADDR VMCS field.
6770 if (!flexpriority_enabled
)
6771 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6773 if (!cpu_has_vmx_tpr_shadow())
6774 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6776 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6777 kvm_disable_largepages();
6779 if (!cpu_has_vmx_ple())
6782 if (!cpu_has_vmx_apicv()) {
6784 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6787 if (cpu_has_vmx_tsc_scaling()) {
6788 kvm_has_tsc_control
= true;
6789 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6790 kvm_tsc_scaling_ratio_frac_bits
= 48;
6793 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6794 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6795 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6796 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6797 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6798 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6800 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6801 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6802 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6803 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6804 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6805 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6806 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6807 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6809 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6811 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6812 if (msr
== 0x839 /* TMCCT */)
6814 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6818 * TPR reads and writes can be virtualized even if virtual interrupt
6819 * delivery is not in use.
6821 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6822 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6825 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6827 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6834 update_ple_window_actual_max();
6837 * Only enable PML when hardware supports PML feature, and both EPT
6838 * and EPT A/D bit features are enabled -- PML depends on them to work.
6840 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6844 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6845 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6846 kvm_x86_ops
->flush_log_dirty
= NULL
;
6847 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6850 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6853 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6854 cpu_preemption_timer_multi
=
6855 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6857 kvm_x86_ops
->set_hv_timer
= NULL
;
6858 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6861 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6863 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6865 return alloc_kvm_area();
6868 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6869 free_page((unsigned long)vmx_bitmap
[i
]);
6874 static __exit
void hardware_unsetup(void)
6878 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6879 free_page((unsigned long)vmx_bitmap
[i
]);
6885 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6886 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6888 static int handle_pause(struct kvm_vcpu
*vcpu
)
6891 grow_ple_window(vcpu
);
6894 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6895 * VM-execution control is ignored if CPL > 0. OTOH, KVM
6896 * never set PAUSE_EXITING and just set PLE if supported,
6897 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6899 kvm_vcpu_on_spin(vcpu
, true);
6900 return kvm_skip_emulated_instruction(vcpu
);
6903 static int handle_nop(struct kvm_vcpu
*vcpu
)
6905 return kvm_skip_emulated_instruction(vcpu
);
6908 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6910 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6911 return handle_nop(vcpu
);
6914 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
6916 kvm_queue_exception(vcpu
, UD_VECTOR
);
6920 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6925 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6927 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6928 return handle_nop(vcpu
);
6932 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6933 * We could reuse a single VMCS for all the L2 guests, but we also want the
6934 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6935 * allows keeping them loaded on the processor, and in the future will allow
6936 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6937 * every entry if they never change.
6938 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6939 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6941 * The following functions allocate and free a vmcs02 in this pool.
6944 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6945 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6947 struct vmcs02_list
*item
;
6948 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6949 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6950 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6951 return &item
->vmcs02
;
6954 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6955 /* Recycle the least recently used VMCS. */
6956 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6957 struct vmcs02_list
, list
);
6958 item
->vmptr
= vmx
->nested
.current_vmptr
;
6959 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6960 return &item
->vmcs02
;
6963 /* Create a new VMCS */
6964 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6967 item
->vmcs02
.vmcs
= alloc_vmcs();
6968 item
->vmcs02
.shadow_vmcs
= NULL
;
6969 if (!item
->vmcs02
.vmcs
) {
6973 loaded_vmcs_init(&item
->vmcs02
);
6974 item
->vmptr
= vmx
->nested
.current_vmptr
;
6975 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6976 vmx
->nested
.vmcs02_num
++;
6977 return &item
->vmcs02
;
6980 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6981 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6983 struct vmcs02_list
*item
;
6984 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6985 if (item
->vmptr
== vmptr
) {
6986 free_loaded_vmcs(&item
->vmcs02
);
6987 list_del(&item
->list
);
6989 vmx
->nested
.vmcs02_num
--;
6995 * Free all VMCSs saved for this vcpu, except the one pointed by
6996 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6997 * must be &vmx->vmcs01.
6999 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
7001 struct vmcs02_list
*item
, *n
;
7003 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
7004 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
7006 * Something will leak if the above WARN triggers. Better than
7009 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
7012 free_loaded_vmcs(&item
->vmcs02
);
7013 list_del(&item
->list
);
7015 vmx
->nested
.vmcs02_num
--;
7020 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7021 * set the success or error code of an emulated VMX instruction, as specified
7022 * by Vol 2B, VMX Instruction Reference, "Conventions".
7024 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
7026 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
7027 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7028 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
7031 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
7033 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7034 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
7035 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7039 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
7040 u32 vm_instruction_error
)
7042 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
7044 * failValid writes the error number to the current VMCS, which
7045 * can't be done there isn't a current VMCS.
7047 nested_vmx_failInvalid(vcpu
);
7050 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7051 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7052 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7054 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
7056 * We don't need to force a shadow sync because
7057 * VM_INSTRUCTION_ERROR is not shadowed
7061 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
7063 /* TODO: not to reset guest simply here. */
7064 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7065 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
7068 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
7070 struct vcpu_vmx
*vmx
=
7071 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
7073 vmx
->nested
.preemption_timer_expired
= true;
7074 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
7075 kvm_vcpu_kick(&vmx
->vcpu
);
7077 return HRTIMER_NORESTART
;
7081 * Decode the memory-address operand of a vmx instruction, as recorded on an
7082 * exit caused by such an instruction (run by a guest hypervisor).
7083 * On success, returns 0. When the operand is invalid, returns 1 and throws
7086 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
7087 unsigned long exit_qualification
,
7088 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
7092 struct kvm_segment s
;
7095 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7096 * Execution", on an exit, vmx_instruction_info holds most of the
7097 * addressing components of the operand. Only the displacement part
7098 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7099 * For how an actual address is calculated from all these components,
7100 * refer to Vol. 1, "Operand Addressing".
7102 int scaling
= vmx_instruction_info
& 3;
7103 int addr_size
= (vmx_instruction_info
>> 7) & 7;
7104 bool is_reg
= vmx_instruction_info
& (1u << 10);
7105 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
7106 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
7107 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
7108 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
7109 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7112 kvm_queue_exception(vcpu
, UD_VECTOR
);
7116 /* Addr = segment_base + offset */
7117 /* offset = base + [index * scale] + displacement */
7118 off
= exit_qualification
; /* holds the displacement */
7120 off
+= kvm_register_read(vcpu
, base_reg
);
7122 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7123 vmx_get_segment(vcpu
, &s
, seg_reg
);
7124 *ret
= s
.base
+ off
;
7126 if (addr_size
== 1) /* 32 bit */
7129 /* Checks for #GP/#SS exceptions. */
7131 if (is_long_mode(vcpu
)) {
7132 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7133 * non-canonical form. This is the only check on the memory
7134 * destination for long mode!
7136 exn
= is_noncanonical_address(*ret
, vcpu
);
7137 } else if (is_protmode(vcpu
)) {
7138 /* Protected mode: apply checks for segment validity in the
7140 * - segment type check (#GP(0) may be thrown)
7141 * - usability check (#GP(0)/#SS(0))
7142 * - limit check (#GP(0)/#SS(0))
7145 /* #GP(0) if the destination operand is located in a
7146 * read-only data segment or any code segment.
7148 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7150 /* #GP(0) if the source operand is located in an
7151 * execute-only code segment
7153 exn
= ((s
.type
& 0xa) == 8);
7155 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7158 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7160 exn
= (s
.unusable
!= 0);
7161 /* Protected mode: #GP(0)/#SS(0) if the memory
7162 * operand is outside the segment limit.
7164 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7167 kvm_queue_exception_e(vcpu
,
7168 seg_reg
== VCPU_SREG_SS
?
7169 SS_VECTOR
: GP_VECTOR
,
7177 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7180 struct x86_exception e
;
7182 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7183 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7186 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7187 sizeof(*vmpointer
), &e
)) {
7188 kvm_inject_page_fault(vcpu
, &e
);
7195 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7197 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7198 struct vmcs
*shadow_vmcs
;
7200 if (cpu_has_vmx_msr_bitmap()) {
7201 vmx
->nested
.msr_bitmap
=
7202 (unsigned long *)__get_free_page(GFP_KERNEL
);
7203 if (!vmx
->nested
.msr_bitmap
)
7204 goto out_msr_bitmap
;
7207 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7208 if (!vmx
->nested
.cached_vmcs12
)
7209 goto out_cached_vmcs12
;
7211 if (enable_shadow_vmcs
) {
7212 shadow_vmcs
= alloc_vmcs();
7214 goto out_shadow_vmcs
;
7215 /* mark vmcs as shadow */
7216 shadow_vmcs
->revision_id
|= (1u << 31);
7217 /* init shadow vmcs */
7218 vmcs_clear(shadow_vmcs
);
7219 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7222 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7223 vmx
->nested
.vmcs02_num
= 0;
7225 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7226 HRTIMER_MODE_REL_PINNED
);
7227 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7229 vmx
->nested
.vmxon
= true;
7233 kfree(vmx
->nested
.cached_vmcs12
);
7236 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7243 * Emulate the VMXON instruction.
7244 * Currently, we just remember that VMX is active, and do not save or even
7245 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7246 * do not currently need to store anything in that guest-allocated memory
7247 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7248 * argument is different from the VMXON pointer (which the spec says they do).
7250 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7255 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7256 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7257 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7260 * The Intel VMX Instruction Reference lists a bunch of bits that are
7261 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7262 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7263 * Otherwise, we should fail with #UD. But most faulting conditions
7264 * have already been checked by hardware, prior to the VM-exit for
7265 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7266 * that bit set to 1 in non-root mode.
7268 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7269 kvm_queue_exception(vcpu
, UD_VECTOR
);
7273 if (vmx
->nested
.vmxon
) {
7274 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7275 return kvm_skip_emulated_instruction(vcpu
);
7278 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7279 != VMXON_NEEDED_FEATURES
) {
7280 kvm_inject_gp(vcpu
, 0);
7284 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7289 * The first 4 bytes of VMXON region contain the supported
7290 * VMCS revision identifier
7292 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7293 * which replaces physical address width with 32
7295 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7296 nested_vmx_failInvalid(vcpu
);
7297 return kvm_skip_emulated_instruction(vcpu
);
7300 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7301 if (is_error_page(page
)) {
7302 nested_vmx_failInvalid(vcpu
);
7303 return kvm_skip_emulated_instruction(vcpu
);
7305 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7307 kvm_release_page_clean(page
);
7308 nested_vmx_failInvalid(vcpu
);
7309 return kvm_skip_emulated_instruction(vcpu
);
7312 kvm_release_page_clean(page
);
7314 vmx
->nested
.vmxon_ptr
= vmptr
;
7315 ret
= enter_vmx_operation(vcpu
);
7319 nested_vmx_succeed(vcpu
);
7320 return kvm_skip_emulated_instruction(vcpu
);
7324 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7325 * for running VMX instructions (except VMXON, whose prerequisites are
7326 * slightly different). It also specifies what exception to inject otherwise.
7327 * Note that many of these exceptions have priority over VM exits, so they
7328 * don't have to be checked again here.
7330 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7332 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7333 kvm_queue_exception(vcpu
, UD_VECTOR
);
7339 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7341 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7342 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7345 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7347 if (vmx
->nested
.current_vmptr
== -1ull)
7350 if (enable_shadow_vmcs
) {
7351 /* copy to memory all shadowed fields in case
7352 they were modified */
7353 copy_shadow_to_vmcs12(vmx
);
7354 vmx
->nested
.sync_shadow_vmcs
= false;
7355 vmx_disable_shadow_vmcs(vmx
);
7357 vmx
->nested
.posted_intr_nv
= -1;
7359 /* Flush VMCS12 to guest memory */
7360 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7361 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7362 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7364 vmx
->nested
.current_vmptr
= -1ull;
7368 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7369 * just stops using VMX.
7371 static void free_nested(struct vcpu_vmx
*vmx
)
7373 if (!vmx
->nested
.vmxon
)
7376 vmx
->nested
.vmxon
= false;
7377 free_vpid(vmx
->nested
.vpid02
);
7378 vmx
->nested
.posted_intr_nv
= -1;
7379 vmx
->nested
.current_vmptr
= -1ull;
7380 if (vmx
->nested
.msr_bitmap
) {
7381 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7382 vmx
->nested
.msr_bitmap
= NULL
;
7384 if (enable_shadow_vmcs
) {
7385 vmx_disable_shadow_vmcs(vmx
);
7386 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7387 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7388 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7390 kfree(vmx
->nested
.cached_vmcs12
);
7391 /* Unpin physical memory we referred to in current vmcs02 */
7392 if (vmx
->nested
.apic_access_page
) {
7393 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7394 vmx
->nested
.apic_access_page
= NULL
;
7396 if (vmx
->nested
.virtual_apic_page
) {
7397 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7398 vmx
->nested
.virtual_apic_page
= NULL
;
7400 if (vmx
->nested
.pi_desc_page
) {
7401 kunmap(vmx
->nested
.pi_desc_page
);
7402 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7403 vmx
->nested
.pi_desc_page
= NULL
;
7404 vmx
->nested
.pi_desc
= NULL
;
7407 nested_free_all_saved_vmcss(vmx
);
7410 /* Emulate the VMXOFF instruction */
7411 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7413 if (!nested_vmx_check_permission(vcpu
))
7415 free_nested(to_vmx(vcpu
));
7416 nested_vmx_succeed(vcpu
);
7417 return kvm_skip_emulated_instruction(vcpu
);
7420 /* Emulate the VMCLEAR instruction */
7421 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7423 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7427 if (!nested_vmx_check_permission(vcpu
))
7430 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7433 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7434 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7435 return kvm_skip_emulated_instruction(vcpu
);
7438 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7439 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7440 return kvm_skip_emulated_instruction(vcpu
);
7443 if (vmptr
== vmx
->nested
.current_vmptr
)
7444 nested_release_vmcs12(vmx
);
7446 kvm_vcpu_write_guest(vcpu
,
7447 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7448 &zero
, sizeof(zero
));
7450 nested_free_vmcs02(vmx
, vmptr
);
7452 nested_vmx_succeed(vcpu
);
7453 return kvm_skip_emulated_instruction(vcpu
);
7456 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7458 /* Emulate the VMLAUNCH instruction */
7459 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7461 return nested_vmx_run(vcpu
, true);
7464 /* Emulate the VMRESUME instruction */
7465 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7468 return nested_vmx_run(vcpu
, false);
7472 * Read a vmcs12 field. Since these can have varying lengths and we return
7473 * one type, we chose the biggest type (u64) and zero-extend the return value
7474 * to that size. Note that the caller, handle_vmread, might need to use only
7475 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7476 * 64-bit fields are to be returned).
7478 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7479 unsigned long field
, u64
*ret
)
7481 short offset
= vmcs_field_to_offset(field
);
7487 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7489 switch (vmcs_field_type(field
)) {
7490 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7491 *ret
= *((natural_width
*)p
);
7493 case VMCS_FIELD_TYPE_U16
:
7496 case VMCS_FIELD_TYPE_U32
:
7499 case VMCS_FIELD_TYPE_U64
:
7509 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7510 unsigned long field
, u64 field_value
){
7511 short offset
= vmcs_field_to_offset(field
);
7512 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7516 switch (vmcs_field_type(field
)) {
7517 case VMCS_FIELD_TYPE_U16
:
7518 *(u16
*)p
= field_value
;
7520 case VMCS_FIELD_TYPE_U32
:
7521 *(u32
*)p
= field_value
;
7523 case VMCS_FIELD_TYPE_U64
:
7524 *(u64
*)p
= field_value
;
7526 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7527 *(natural_width
*)p
= field_value
;
7536 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7539 unsigned long field
;
7541 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7542 const unsigned long *fields
= shadow_read_write_fields
;
7543 const int num_fields
= max_shadow_read_write_fields
;
7547 vmcs_load(shadow_vmcs
);
7549 for (i
= 0; i
< num_fields
; i
++) {
7551 switch (vmcs_field_type(field
)) {
7552 case VMCS_FIELD_TYPE_U16
:
7553 field_value
= vmcs_read16(field
);
7555 case VMCS_FIELD_TYPE_U32
:
7556 field_value
= vmcs_read32(field
);
7558 case VMCS_FIELD_TYPE_U64
:
7559 field_value
= vmcs_read64(field
);
7561 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7562 field_value
= vmcs_readl(field
);
7568 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7571 vmcs_clear(shadow_vmcs
);
7572 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7577 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7579 const unsigned long *fields
[] = {
7580 shadow_read_write_fields
,
7581 shadow_read_only_fields
7583 const int max_fields
[] = {
7584 max_shadow_read_write_fields
,
7585 max_shadow_read_only_fields
7588 unsigned long field
;
7589 u64 field_value
= 0;
7590 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7592 vmcs_load(shadow_vmcs
);
7594 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7595 for (i
= 0; i
< max_fields
[q
]; i
++) {
7596 field
= fields
[q
][i
];
7597 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7599 switch (vmcs_field_type(field
)) {
7600 case VMCS_FIELD_TYPE_U16
:
7601 vmcs_write16(field
, (u16
)field_value
);
7603 case VMCS_FIELD_TYPE_U32
:
7604 vmcs_write32(field
, (u32
)field_value
);
7606 case VMCS_FIELD_TYPE_U64
:
7607 vmcs_write64(field
, (u64
)field_value
);
7609 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7610 vmcs_writel(field
, (long)field_value
);
7619 vmcs_clear(shadow_vmcs
);
7620 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7624 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7625 * used before) all generate the same failure when it is missing.
7627 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7629 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7630 if (vmx
->nested
.current_vmptr
== -1ull) {
7631 nested_vmx_failInvalid(vcpu
);
7637 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7639 unsigned long field
;
7641 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7642 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7645 if (!nested_vmx_check_permission(vcpu
))
7648 if (!nested_vmx_check_vmcs12(vcpu
))
7649 return kvm_skip_emulated_instruction(vcpu
);
7651 /* Decode instruction info and find the field to read */
7652 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7653 /* Read the field, zero-extended to a u64 field_value */
7654 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7655 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7656 return kvm_skip_emulated_instruction(vcpu
);
7659 * Now copy part of this value to register or memory, as requested.
7660 * Note that the number of bits actually copied is 32 or 64 depending
7661 * on the guest's mode (32 or 64 bit), not on the given field's length.
7663 if (vmx_instruction_info
& (1u << 10)) {
7664 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7667 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7668 vmx_instruction_info
, true, &gva
))
7670 /* _system ok, as hardware has verified cpl=0 */
7671 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7672 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7675 nested_vmx_succeed(vcpu
);
7676 return kvm_skip_emulated_instruction(vcpu
);
7680 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7682 unsigned long field
;
7684 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7685 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7686 /* The value to write might be 32 or 64 bits, depending on L1's long
7687 * mode, and eventually we need to write that into a field of several
7688 * possible lengths. The code below first zero-extends the value to 64
7689 * bit (field_value), and then copies only the appropriate number of
7690 * bits into the vmcs12 field.
7692 u64 field_value
= 0;
7693 struct x86_exception e
;
7695 if (!nested_vmx_check_permission(vcpu
))
7698 if (!nested_vmx_check_vmcs12(vcpu
))
7699 return kvm_skip_emulated_instruction(vcpu
);
7701 if (vmx_instruction_info
& (1u << 10))
7702 field_value
= kvm_register_readl(vcpu
,
7703 (((vmx_instruction_info
) >> 3) & 0xf));
7705 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7706 vmx_instruction_info
, false, &gva
))
7708 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7709 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7710 kvm_inject_page_fault(vcpu
, &e
);
7716 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7717 if (vmcs_field_readonly(field
)) {
7718 nested_vmx_failValid(vcpu
,
7719 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7720 return kvm_skip_emulated_instruction(vcpu
);
7723 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7724 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7725 return kvm_skip_emulated_instruction(vcpu
);
7728 nested_vmx_succeed(vcpu
);
7729 return kvm_skip_emulated_instruction(vcpu
);
7732 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7734 vmx
->nested
.current_vmptr
= vmptr
;
7735 if (enable_shadow_vmcs
) {
7736 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7737 SECONDARY_EXEC_SHADOW_VMCS
);
7738 vmcs_write64(VMCS_LINK_POINTER
,
7739 __pa(vmx
->vmcs01
.shadow_vmcs
));
7740 vmx
->nested
.sync_shadow_vmcs
= true;
7744 /* Emulate the VMPTRLD instruction */
7745 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7747 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7750 if (!nested_vmx_check_permission(vcpu
))
7753 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7756 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7757 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7758 return kvm_skip_emulated_instruction(vcpu
);
7761 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7762 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7763 return kvm_skip_emulated_instruction(vcpu
);
7766 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7767 struct vmcs12
*new_vmcs12
;
7769 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7770 if (is_error_page(page
)) {
7771 nested_vmx_failInvalid(vcpu
);
7772 return kvm_skip_emulated_instruction(vcpu
);
7774 new_vmcs12
= kmap(page
);
7775 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7777 kvm_release_page_clean(page
);
7778 nested_vmx_failValid(vcpu
,
7779 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7780 return kvm_skip_emulated_instruction(vcpu
);
7783 nested_release_vmcs12(vmx
);
7785 * Load VMCS12 from guest memory since it is not already
7788 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7790 kvm_release_page_clean(page
);
7792 set_current_vmptr(vmx
, vmptr
);
7795 nested_vmx_succeed(vcpu
);
7796 return kvm_skip_emulated_instruction(vcpu
);
7799 /* Emulate the VMPTRST instruction */
7800 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7802 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7803 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7805 struct x86_exception e
;
7807 if (!nested_vmx_check_permission(vcpu
))
7810 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7811 vmx_instruction_info
, true, &vmcs_gva
))
7813 /* ok to use *_system, as hardware has verified cpl=0 */
7814 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7815 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7817 kvm_inject_page_fault(vcpu
, &e
);
7820 nested_vmx_succeed(vcpu
);
7821 return kvm_skip_emulated_instruction(vcpu
);
7824 /* Emulate the INVEPT instruction */
7825 static int handle_invept(struct kvm_vcpu
*vcpu
)
7827 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7828 u32 vmx_instruction_info
, types
;
7831 struct x86_exception e
;
7836 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7837 SECONDARY_EXEC_ENABLE_EPT
) ||
7838 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7839 kvm_queue_exception(vcpu
, UD_VECTOR
);
7843 if (!nested_vmx_check_permission(vcpu
))
7846 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7847 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7849 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7851 if (type
>= 32 || !(types
& (1 << type
))) {
7852 nested_vmx_failValid(vcpu
,
7853 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7854 return kvm_skip_emulated_instruction(vcpu
);
7857 /* According to the Intel VMX instruction reference, the memory
7858 * operand is read even if it isn't needed (e.g., for type==global)
7860 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7861 vmx_instruction_info
, false, &gva
))
7863 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7864 sizeof(operand
), &e
)) {
7865 kvm_inject_page_fault(vcpu
, &e
);
7870 case VMX_EPT_EXTENT_GLOBAL
:
7872 * TODO: track mappings and invalidate
7873 * single context requests appropriately
7875 case VMX_EPT_EXTENT_CONTEXT
:
7876 kvm_mmu_sync_roots(vcpu
);
7877 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7878 nested_vmx_succeed(vcpu
);
7885 return kvm_skip_emulated_instruction(vcpu
);
7888 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7890 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7891 u32 vmx_instruction_info
;
7892 unsigned long type
, types
;
7894 struct x86_exception e
;
7900 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7901 SECONDARY_EXEC_ENABLE_VPID
) ||
7902 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7903 kvm_queue_exception(vcpu
, UD_VECTOR
);
7907 if (!nested_vmx_check_permission(vcpu
))
7910 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7911 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7913 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7914 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7916 if (type
>= 32 || !(types
& (1 << type
))) {
7917 nested_vmx_failValid(vcpu
,
7918 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7919 return kvm_skip_emulated_instruction(vcpu
);
7922 /* according to the intel vmx instruction reference, the memory
7923 * operand is read even if it isn't needed (e.g., for type==global)
7925 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7926 vmx_instruction_info
, false, &gva
))
7928 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7929 sizeof(operand
), &e
)) {
7930 kvm_inject_page_fault(vcpu
, &e
);
7933 if (operand
.vpid
>> 16) {
7934 nested_vmx_failValid(vcpu
,
7935 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7936 return kvm_skip_emulated_instruction(vcpu
);
7940 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7941 if (is_noncanonical_address(operand
.gla
, vcpu
)) {
7942 nested_vmx_failValid(vcpu
,
7943 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7944 return kvm_skip_emulated_instruction(vcpu
);
7947 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7948 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7949 if (!operand
.vpid
) {
7950 nested_vmx_failValid(vcpu
,
7951 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7952 return kvm_skip_emulated_instruction(vcpu
);
7955 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7959 return kvm_skip_emulated_instruction(vcpu
);
7962 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7963 nested_vmx_succeed(vcpu
);
7965 return kvm_skip_emulated_instruction(vcpu
);
7968 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7970 unsigned long exit_qualification
;
7972 trace_kvm_pml_full(vcpu
->vcpu_id
);
7974 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7977 * PML buffer FULL happened while executing iret from NMI,
7978 * "blocked by NMI" bit has to be set before next VM entry.
7980 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7981 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7982 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7983 GUEST_INTR_STATE_NMI
);
7986 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7987 * here.., and there's no userspace involvement needed for PML.
7992 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7994 kvm_lapic_expired_hv_timer(vcpu
);
7998 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
8000 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8001 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8003 /* Check for memory type validity */
8004 switch (address
& VMX_EPTP_MT_MASK
) {
8005 case VMX_EPTP_MT_UC
:
8006 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
8009 case VMX_EPTP_MT_WB
:
8010 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
8017 /* only 4 levels page-walk length are valid */
8018 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
8021 /* Reserved bits should not be set */
8022 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
8025 /* AD, if set, should be supported */
8026 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
8027 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
8034 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
8035 struct vmcs12
*vmcs12
)
8037 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8039 bool accessed_dirty
;
8040 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
8042 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
8043 !nested_cpu_has_ept(vmcs12
))
8046 if (index
>= VMFUNC_EPTP_ENTRIES
)
8050 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
8051 &address
, index
* 8, 8))
8054 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
8057 * If the (L2) guest does a vmfunc to the currently
8058 * active ept pointer, we don't have to do anything else
8060 if (vmcs12
->ept_pointer
!= address
) {
8061 if (!valid_ept_address(vcpu
, address
))
8064 kvm_mmu_unload(vcpu
);
8065 mmu
->ept_ad
= accessed_dirty
;
8066 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
8067 vmcs12
->ept_pointer
= address
;
8069 * TODO: Check what's the correct approach in case
8070 * mmu reload fails. Currently, we just let the next
8071 * reload potentially fail
8073 kvm_mmu_reload(vcpu
);
8079 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
8081 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8082 struct vmcs12
*vmcs12
;
8083 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
8086 * VMFUNC is only supported for nested guests, but we always enable the
8087 * secondary control for simplicity; for non-nested mode, fake that we
8088 * didn't by injecting #UD.
8090 if (!is_guest_mode(vcpu
)) {
8091 kvm_queue_exception(vcpu
, UD_VECTOR
);
8095 vmcs12
= get_vmcs12(vcpu
);
8096 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
8101 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
8107 return kvm_skip_emulated_instruction(vcpu
);
8110 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8111 vmcs_read32(VM_EXIT_INTR_INFO
),
8112 vmcs_readl(EXIT_QUALIFICATION
));
8117 * The exit handlers return 1 if the exit was handled fully and guest execution
8118 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8119 * to be done to userspace and return 0.
8121 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8122 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8123 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8124 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8125 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8126 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8127 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8128 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8129 [EXIT_REASON_CPUID
] = handle_cpuid
,
8130 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8131 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8132 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8133 [EXIT_REASON_HLT
] = handle_halt
,
8134 [EXIT_REASON_INVD
] = handle_invd
,
8135 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8136 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8137 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8138 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8139 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8140 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8141 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8142 [EXIT_REASON_VMREAD
] = handle_vmread
,
8143 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8144 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8145 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8146 [EXIT_REASON_VMON
] = handle_vmon
,
8147 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8148 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8149 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8150 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8151 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8152 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8153 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8154 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8155 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8156 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8157 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8158 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8159 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8160 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8161 [EXIT_REASON_INVEPT
] = handle_invept
,
8162 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8163 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
8164 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
8165 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8166 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8167 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8168 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8169 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8172 static const int kvm_vmx_max_exit_handlers
=
8173 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8175 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8176 struct vmcs12
*vmcs12
)
8178 unsigned long exit_qualification
;
8179 gpa_t bitmap
, last_bitmap
;
8184 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8185 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8187 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8189 port
= exit_qualification
>> 16;
8190 size
= (exit_qualification
& 7) + 1;
8192 last_bitmap
= (gpa_t
)-1;
8197 bitmap
= vmcs12
->io_bitmap_a
;
8198 else if (port
< 0x10000)
8199 bitmap
= vmcs12
->io_bitmap_b
;
8202 bitmap
+= (port
& 0x7fff) / 8;
8204 if (last_bitmap
!= bitmap
)
8205 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8207 if (b
& (1 << (port
& 7)))
8212 last_bitmap
= bitmap
;
8219 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8220 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8221 * disinterest in the current event (read or write a specific MSR) by using an
8222 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8224 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8225 struct vmcs12
*vmcs12
, u32 exit_reason
)
8227 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8230 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8234 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8235 * for the four combinations of read/write and low/high MSR numbers.
8236 * First we need to figure out which of the four to use:
8238 bitmap
= vmcs12
->msr_bitmap
;
8239 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8241 if (msr_index
>= 0xc0000000) {
8242 msr_index
-= 0xc0000000;
8246 /* Then read the msr_index'th bit from this bitmap: */
8247 if (msr_index
< 1024*8) {
8249 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8251 return 1 & (b
>> (msr_index
& 7));
8253 return true; /* let L1 handle the wrong parameter */
8257 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8258 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8259 * intercept (via guest_host_mask etc.) the current event.
8261 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8262 struct vmcs12
*vmcs12
)
8264 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8265 int cr
= exit_qualification
& 15;
8269 switch ((exit_qualification
>> 4) & 3) {
8270 case 0: /* mov to cr */
8271 reg
= (exit_qualification
>> 8) & 15;
8272 val
= kvm_register_readl(vcpu
, reg
);
8275 if (vmcs12
->cr0_guest_host_mask
&
8276 (val
^ vmcs12
->cr0_read_shadow
))
8280 if ((vmcs12
->cr3_target_count
>= 1 &&
8281 vmcs12
->cr3_target_value0
== val
) ||
8282 (vmcs12
->cr3_target_count
>= 2 &&
8283 vmcs12
->cr3_target_value1
== val
) ||
8284 (vmcs12
->cr3_target_count
>= 3 &&
8285 vmcs12
->cr3_target_value2
== val
) ||
8286 (vmcs12
->cr3_target_count
>= 4 &&
8287 vmcs12
->cr3_target_value3
== val
))
8289 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8293 if (vmcs12
->cr4_guest_host_mask
&
8294 (vmcs12
->cr4_read_shadow
^ val
))
8298 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8304 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8305 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8308 case 1: /* mov from cr */
8311 if (vmcs12
->cpu_based_vm_exec_control
&
8312 CPU_BASED_CR3_STORE_EXITING
)
8316 if (vmcs12
->cpu_based_vm_exec_control
&
8317 CPU_BASED_CR8_STORE_EXITING
)
8324 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8325 * cr0. Other attempted changes are ignored, with no exit.
8327 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8328 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8329 (val
^ vmcs12
->cr0_read_shadow
))
8331 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8332 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8341 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8342 * should handle it ourselves in L0 (and then continue L2). Only call this
8343 * when in is_guest_mode (L2).
8345 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8347 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8348 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8349 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8351 if (vmx
->nested
.nested_run_pending
)
8354 if (unlikely(vmx
->fail
)) {
8355 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8356 vmcs_read32(VM_INSTRUCTION_ERROR
));
8361 * The host physical addresses of some pages of guest memory
8362 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8363 * may write to these pages via their host physical address while
8364 * L2 is running, bypassing any address-translation-based dirty
8365 * tracking (e.g. EPT write protection).
8367 * Mark them dirty on every exit from L2 to prevent them from
8368 * getting out of sync with dirty tracking.
8370 nested_mark_vmcs12_pages_dirty(vcpu
);
8372 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8373 vmcs_readl(EXIT_QUALIFICATION
),
8374 vmx
->idt_vectoring_info
,
8376 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8379 switch (exit_reason
) {
8380 case EXIT_REASON_EXCEPTION_NMI
:
8381 if (is_nmi(intr_info
))
8383 else if (is_page_fault(intr_info
))
8384 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8385 else if (is_no_device(intr_info
) &&
8386 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8388 else if (is_debug(intr_info
) &&
8390 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8392 else if (is_breakpoint(intr_info
) &&
8393 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8395 return vmcs12
->exception_bitmap
&
8396 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8397 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8399 case EXIT_REASON_TRIPLE_FAULT
:
8401 case EXIT_REASON_PENDING_INTERRUPT
:
8402 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8403 case EXIT_REASON_NMI_WINDOW
:
8404 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8405 case EXIT_REASON_TASK_SWITCH
:
8407 case EXIT_REASON_CPUID
:
8409 case EXIT_REASON_HLT
:
8410 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8411 case EXIT_REASON_INVD
:
8413 case EXIT_REASON_INVLPG
:
8414 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8415 case EXIT_REASON_RDPMC
:
8416 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8417 case EXIT_REASON_RDRAND
:
8418 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8419 case EXIT_REASON_RDSEED
:
8420 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8421 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8422 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8423 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8424 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8425 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8426 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8427 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8428 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8430 * VMX instructions trap unconditionally. This allows L1 to
8431 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8434 case EXIT_REASON_CR_ACCESS
:
8435 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8436 case EXIT_REASON_DR_ACCESS
:
8437 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8438 case EXIT_REASON_IO_INSTRUCTION
:
8439 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8440 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8441 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8442 case EXIT_REASON_MSR_READ
:
8443 case EXIT_REASON_MSR_WRITE
:
8444 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8445 case EXIT_REASON_INVALID_STATE
:
8447 case EXIT_REASON_MWAIT_INSTRUCTION
:
8448 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8449 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8450 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8451 case EXIT_REASON_MONITOR_INSTRUCTION
:
8452 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8453 case EXIT_REASON_PAUSE_INSTRUCTION
:
8454 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8455 nested_cpu_has2(vmcs12
,
8456 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8457 case EXIT_REASON_MCE_DURING_VMENTRY
:
8459 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8460 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8461 case EXIT_REASON_APIC_ACCESS
:
8462 return nested_cpu_has2(vmcs12
,
8463 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8464 case EXIT_REASON_APIC_WRITE
:
8465 case EXIT_REASON_EOI_INDUCED
:
8466 /* apic_write and eoi_induced should exit unconditionally. */
8468 case EXIT_REASON_EPT_VIOLATION
:
8470 * L0 always deals with the EPT violation. If nested EPT is
8471 * used, and the nested mmu code discovers that the address is
8472 * missing in the guest EPT table (EPT12), the EPT violation
8473 * will be injected with nested_ept_inject_page_fault()
8476 case EXIT_REASON_EPT_MISCONFIG
:
8478 * L2 never uses directly L1's EPT, but rather L0's own EPT
8479 * table (shadow on EPT) or a merged EPT table that L0 built
8480 * (EPT on EPT). So any problems with the structure of the
8481 * table is L0's fault.
8484 case EXIT_REASON_INVPCID
:
8486 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8487 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8488 case EXIT_REASON_WBINVD
:
8489 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8490 case EXIT_REASON_XSETBV
:
8492 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8494 * This should never happen, since it is not possible to
8495 * set XSS to a non-zero value---neither in L1 nor in L2.
8496 * If if it were, XSS would have to be checked against
8497 * the XSS exit bitmap in vmcs12.
8499 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8500 case EXIT_REASON_PREEMPTION_TIMER
:
8502 case EXIT_REASON_PML_FULL
:
8503 /* We emulate PML support to L1. */
8505 case EXIT_REASON_VMFUNC
:
8506 /* VM functions are emulated through L2->L0 vmexits. */
8513 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8515 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8518 * At this point, the exit interruption info in exit_intr_info
8519 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8520 * we need to query the in-kernel LAPIC.
8522 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8523 if ((exit_intr_info
&
8524 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8525 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8526 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8527 vmcs12
->vm_exit_intr_error_code
=
8528 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8531 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8532 vmcs_readl(EXIT_QUALIFICATION
));
8536 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8538 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8539 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8542 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8545 __free_page(vmx
->pml_pg
);
8550 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8552 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8556 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8558 /* Do nothing if PML buffer is empty */
8559 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8562 /* PML index always points to next available PML buffer entity */
8563 if (pml_idx
>= PML_ENTITY_NUM
)
8568 pml_buf
= page_address(vmx
->pml_pg
);
8569 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8572 gpa
= pml_buf
[pml_idx
];
8573 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8574 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8577 /* reset PML index */
8578 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8582 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8583 * Called before reporting dirty_bitmap to userspace.
8585 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8588 struct kvm_vcpu
*vcpu
;
8590 * We only need to kick vcpu out of guest mode here, as PML buffer
8591 * is flushed at beginning of all VMEXITs, and it's obvious that only
8592 * vcpus running in guest are possible to have unflushed GPAs in PML
8595 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8596 kvm_vcpu_kick(vcpu
);
8599 static void vmx_dump_sel(char *name
, uint32_t sel
)
8601 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8602 name
, vmcs_read16(sel
),
8603 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8604 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8605 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8608 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8610 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8611 name
, vmcs_read32(limit
),
8612 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8615 static void dump_vmcs(void)
8617 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8618 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8619 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8620 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8621 u32 secondary_exec_control
= 0;
8622 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8623 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8626 if (cpu_has_secondary_exec_ctrls())
8627 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8629 pr_err("*** Guest State ***\n");
8630 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8631 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8632 vmcs_readl(CR0_GUEST_HOST_MASK
));
8633 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8634 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8635 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8636 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8637 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8639 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8640 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8641 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8642 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8644 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8645 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8646 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8647 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8648 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8649 vmcs_readl(GUEST_SYSENTER_ESP
),
8650 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8651 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8652 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8653 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8654 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8655 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8656 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8657 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8658 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8659 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8660 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8661 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8662 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8663 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8664 efer
, vmcs_read64(GUEST_IA32_PAT
));
8665 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8666 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8667 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8668 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8669 pr_err("PerfGlobCtl = 0x%016llx\n",
8670 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8671 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8672 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8673 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8674 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8675 vmcs_read32(GUEST_ACTIVITY_STATE
));
8676 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8677 pr_err("InterruptStatus = %04x\n",
8678 vmcs_read16(GUEST_INTR_STATUS
));
8680 pr_err("*** Host State ***\n");
8681 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8682 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8683 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8684 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8685 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8686 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8687 vmcs_read16(HOST_TR_SELECTOR
));
8688 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8689 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8690 vmcs_readl(HOST_TR_BASE
));
8691 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8692 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8693 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8694 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8695 vmcs_readl(HOST_CR4
));
8696 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8697 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8698 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8699 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8700 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8701 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8702 vmcs_read64(HOST_IA32_EFER
),
8703 vmcs_read64(HOST_IA32_PAT
));
8704 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8705 pr_err("PerfGlobCtl = 0x%016llx\n",
8706 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8708 pr_err("*** Control State ***\n");
8709 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8710 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8711 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8712 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8713 vmcs_read32(EXCEPTION_BITMAP
),
8714 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8715 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8716 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8717 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8718 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8719 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8720 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8721 vmcs_read32(VM_EXIT_INTR_INFO
),
8722 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8723 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8724 pr_err(" reason=%08x qualification=%016lx\n",
8725 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8726 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8727 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8728 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8729 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8730 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8731 pr_err("TSC Multiplier = 0x%016llx\n",
8732 vmcs_read64(TSC_MULTIPLIER
));
8733 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8734 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8735 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8736 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8737 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8738 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8739 n
= vmcs_read32(CR3_TARGET_COUNT
);
8740 for (i
= 0; i
+ 1 < n
; i
+= 4)
8741 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8742 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8743 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8745 pr_err("CR3 target%u=%016lx\n",
8746 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8747 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8748 pr_err("PLE Gap=%08x Window=%08x\n",
8749 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8750 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8751 pr_err("Virtual processor ID = 0x%04x\n",
8752 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8756 * The guest has exited. See if we can fix it or if we need userspace
8759 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8761 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8762 u32 exit_reason
= vmx
->exit_reason
;
8763 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8765 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8768 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8769 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8770 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8771 * mode as if vcpus is in root mode, the PML buffer must has been
8775 vmx_flush_pml_buffer(vcpu
);
8777 /* If guest state is invalid, start emulating */
8778 if (vmx
->emulation_required
)
8779 return handle_invalid_guest_state(vcpu
);
8781 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8782 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8784 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8786 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8787 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8792 if (unlikely(vmx
->fail
)) {
8793 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8794 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8795 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8801 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8802 * delivery event since it indicates guest is accessing MMIO.
8803 * The vm-exit can be triggered again after return to guest that
8804 * will cause infinite loop.
8806 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8807 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8808 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8809 exit_reason
!= EXIT_REASON_PML_FULL
&&
8810 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8811 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8812 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8813 vcpu
->run
->internal
.ndata
= 3;
8814 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8815 vcpu
->run
->internal
.data
[1] = exit_reason
;
8816 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8817 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8818 vcpu
->run
->internal
.ndata
++;
8819 vcpu
->run
->internal
.data
[3] =
8820 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8825 if (exit_reason
< kvm_vmx_max_exit_handlers
8826 && kvm_vmx_exit_handlers
[exit_reason
])
8827 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8829 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8831 kvm_queue_exception(vcpu
, UD_VECTOR
);
8836 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8838 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8840 if (is_guest_mode(vcpu
) &&
8841 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8844 if (irr
== -1 || tpr
< irr
) {
8845 vmcs_write32(TPR_THRESHOLD
, 0);
8849 vmcs_write32(TPR_THRESHOLD
, irr
);
8852 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8854 u32 sec_exec_control
;
8856 /* Postpone execution until vmcs01 is the current VMCS. */
8857 if (is_guest_mode(vcpu
)) {
8858 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8862 if (!cpu_has_vmx_virtualize_x2apic_mode())
8865 if (!cpu_need_tpr_shadow(vcpu
))
8868 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8871 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8872 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8874 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8875 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8876 vmx_flush_tlb_ept_only(vcpu
);
8878 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8880 vmx_set_msr_bitmap(vcpu
);
8883 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8885 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8888 * Currently we do not handle the nested case where L2 has an
8889 * APIC access page of its own; that page is still pinned.
8890 * Hence, we skip the case where the VCPU is in guest mode _and_
8891 * L1 prepared an APIC access page for L2.
8893 * For the case where L1 and L2 share the same APIC access page
8894 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8895 * in the vmcs12), this function will only update either the vmcs01
8896 * or the vmcs02. If the former, the vmcs02 will be updated by
8897 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8898 * the next L2->L1 exit.
8900 if (!is_guest_mode(vcpu
) ||
8901 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8902 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8903 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8904 vmx_flush_tlb_ept_only(vcpu
);
8908 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8916 status
= vmcs_read16(GUEST_INTR_STATUS
);
8918 if (max_isr
!= old
) {
8920 status
|= max_isr
<< 8;
8921 vmcs_write16(GUEST_INTR_STATUS
, status
);
8925 static void vmx_set_rvi(int vector
)
8933 status
= vmcs_read16(GUEST_INTR_STATUS
);
8934 old
= (u8
)status
& 0xff;
8935 if ((u8
)vector
!= old
) {
8937 status
|= (u8
)vector
;
8938 vmcs_write16(GUEST_INTR_STATUS
, status
);
8942 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8944 if (!is_guest_mode(vcpu
)) {
8945 vmx_set_rvi(max_irr
);
8953 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8956 if (nested_exit_on_intr(vcpu
))
8960 * Else, fall back to pre-APICv interrupt injection since L2
8961 * is run without virtual interrupt delivery.
8963 if (!kvm_event_needs_reinjection(vcpu
) &&
8964 vmx_interrupt_allowed(vcpu
)) {
8965 kvm_queue_interrupt(vcpu
, max_irr
, false);
8966 vmx_inject_irq(vcpu
);
8970 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8972 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8975 WARN_ON(!vcpu
->arch
.apicv_active
);
8976 if (pi_test_on(&vmx
->pi_desc
)) {
8977 pi_clear_on(&vmx
->pi_desc
);
8979 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8980 * But on x86 this is just a compiler barrier anyway.
8982 smp_mb__after_atomic();
8983 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8985 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8987 vmx_hwapic_irr_update(vcpu
, max_irr
);
8991 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8993 if (!kvm_vcpu_apicv_active(vcpu
))
8996 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8997 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8998 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8999 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
9002 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
9004 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9006 pi_clear_on(&vmx
->pi_desc
);
9007 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
9010 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
9012 u32 exit_intr_info
= 0;
9013 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
9015 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
9016 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
9019 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9020 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9021 vmx
->exit_intr_info
= exit_intr_info
;
9023 /* if exit due to PF check for async PF */
9024 if (is_page_fault(exit_intr_info
))
9025 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
9027 /* Handle machine checks before interrupts are enabled */
9028 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
9029 is_machine_check(exit_intr_info
))
9030 kvm_machine_check();
9032 /* We need to handle NMIs before interrupts are enabled */
9033 if (is_nmi(exit_intr_info
)) {
9034 kvm_before_handle_nmi(&vmx
->vcpu
);
9036 kvm_after_handle_nmi(&vmx
->vcpu
);
9040 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
9042 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9044 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
9045 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
9046 unsigned int vector
;
9047 unsigned long entry
;
9049 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9050 #ifdef CONFIG_X86_64
9054 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9055 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
9056 entry
= gate_offset(desc
);
9058 #ifdef CONFIG_X86_64
9059 "mov %%" _ASM_SP
", %[sp]\n\t"
9060 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
9065 __ASM_SIZE(push
) " $%c[cs]\n\t"
9066 "call *%[entry]\n\t"
9068 #ifdef CONFIG_X86_64
9074 [ss
]"i"(__KERNEL_DS
),
9075 [cs
]"i"(__KERNEL_CS
)
9079 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
9081 static bool vmx_has_high_real_mode_segbase(void)
9083 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
9086 static bool vmx_mpx_supported(void)
9088 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
9089 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
9092 static bool vmx_xsaves_supported(void)
9094 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9095 SECONDARY_EXEC_XSAVES
;
9098 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
9103 bool idtv_info_valid
;
9105 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9107 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9110 * Can't use vmx->exit_intr_info since we're not sure what
9111 * the exit reason is.
9113 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9114 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9115 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9117 * SDM 3: 27.7.1.2 (September 2008)
9118 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9119 * a guest IRET fault.
9120 * SDM 3: 23.2.2 (September 2008)
9121 * Bit 12 is undefined in any of the following cases:
9122 * If the VM exit sets the valid bit in the IDT-vectoring
9123 * information field.
9124 * If the VM exit is due to a double fault.
9126 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9127 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9128 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9129 GUEST_INTR_STATE_NMI
);
9131 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9132 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9133 & GUEST_INTR_STATE_NMI
);
9136 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9137 u32 idt_vectoring_info
,
9138 int instr_len_field
,
9139 int error_code_field
)
9143 bool idtv_info_valid
;
9145 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9147 vcpu
->arch
.nmi_injected
= false;
9148 kvm_clear_exception_queue(vcpu
);
9149 kvm_clear_interrupt_queue(vcpu
);
9151 if (!idtv_info_valid
)
9154 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9156 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9157 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9160 case INTR_TYPE_NMI_INTR
:
9161 vcpu
->arch
.nmi_injected
= true;
9163 * SDM 3: 27.7.1.2 (September 2008)
9164 * Clear bit "block by NMI" before VM entry if a NMI
9167 vmx_set_nmi_mask(vcpu
, false);
9169 case INTR_TYPE_SOFT_EXCEPTION
:
9170 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9172 case INTR_TYPE_HARD_EXCEPTION
:
9173 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9174 u32 err
= vmcs_read32(error_code_field
);
9175 kvm_requeue_exception_e(vcpu
, vector
, err
);
9177 kvm_requeue_exception(vcpu
, vector
);
9179 case INTR_TYPE_SOFT_INTR
:
9180 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9182 case INTR_TYPE_EXT_INTR
:
9183 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9190 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9192 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9193 VM_EXIT_INSTRUCTION_LEN
,
9194 IDT_VECTORING_ERROR_CODE
);
9197 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9199 __vmx_complete_interrupts(vcpu
,
9200 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9201 VM_ENTRY_INSTRUCTION_LEN
,
9202 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9204 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9207 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9210 struct perf_guest_switch_msr
*msrs
;
9212 msrs
= perf_guest_get_msrs(&nr_msrs
);
9217 for (i
= 0; i
< nr_msrs
; i
++)
9218 if (msrs
[i
].host
== msrs
[i
].guest
)
9219 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9221 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9225 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9227 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9231 if (vmx
->hv_deadline_tsc
== -1)
9235 if (vmx
->hv_deadline_tsc
> tscl
)
9236 /* sure to be 32 bit only because checked on set_hv_timer */
9237 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9238 cpu_preemption_timer_multi
);
9242 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9245 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9247 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9248 unsigned long debugctlmsr
, cr3
, cr4
;
9250 /* Don't enter VMX if guest state is invalid, let the exit handler
9251 start emulation until we arrive back to a valid state */
9252 if (vmx
->emulation_required
)
9255 if (vmx
->ple_window_dirty
) {
9256 vmx
->ple_window_dirty
= false;
9257 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9260 if (vmx
->nested
.sync_shadow_vmcs
) {
9261 copy_vmcs12_to_shadow(vmx
);
9262 vmx
->nested
.sync_shadow_vmcs
= false;
9265 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9266 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9267 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9268 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9270 cr3
= __get_current_cr3_fast();
9271 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9272 vmcs_writel(HOST_CR3
, cr3
);
9273 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9276 cr4
= cr4_read_shadow();
9277 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9278 vmcs_writel(HOST_CR4
, cr4
);
9279 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9282 /* When single-stepping over STI and MOV SS, we must clear the
9283 * corresponding interruptibility bits in the guest state. Otherwise
9284 * vmentry fails as it then expects bit 14 (BS) in pending debug
9285 * exceptions being set, but that's not correct for the guest debugging
9287 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9288 vmx_set_interrupt_shadow(vcpu
, 0);
9290 if (static_cpu_has(X86_FEATURE_PKU
) &&
9291 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9292 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9293 __write_pkru(vcpu
->arch
.pkru
);
9295 atomic_switch_perf_msrs(vmx
);
9296 debugctlmsr
= get_debugctlmsr();
9298 vmx_arm_hv_timer(vcpu
);
9300 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9302 /* Store host registers */
9303 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9304 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9305 "push %%" _ASM_CX
" \n\t"
9306 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9308 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9309 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9311 /* Reload cr2 if changed */
9312 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9313 "mov %%cr2, %%" _ASM_DX
" \n\t"
9314 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9316 "mov %%" _ASM_AX
", %%cr2 \n\t"
9318 /* Check if vmlaunch of vmresume is needed */
9319 "cmpl $0, %c[launched](%0) \n\t"
9320 /* Load guest registers. Don't clobber flags. */
9321 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9322 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9323 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9324 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9325 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9326 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9327 #ifdef CONFIG_X86_64
9328 "mov %c[r8](%0), %%r8 \n\t"
9329 "mov %c[r9](%0), %%r9 \n\t"
9330 "mov %c[r10](%0), %%r10 \n\t"
9331 "mov %c[r11](%0), %%r11 \n\t"
9332 "mov %c[r12](%0), %%r12 \n\t"
9333 "mov %c[r13](%0), %%r13 \n\t"
9334 "mov %c[r14](%0), %%r14 \n\t"
9335 "mov %c[r15](%0), %%r15 \n\t"
9337 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9339 /* Enter guest mode */
9341 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9343 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9345 /* Save guest registers, load host registers, keep flags */
9346 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9348 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9349 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9350 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9351 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9352 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9353 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9354 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9355 #ifdef CONFIG_X86_64
9356 "mov %%r8, %c[r8](%0) \n\t"
9357 "mov %%r9, %c[r9](%0) \n\t"
9358 "mov %%r10, %c[r10](%0) \n\t"
9359 "mov %%r11, %c[r11](%0) \n\t"
9360 "mov %%r12, %c[r12](%0) \n\t"
9361 "mov %%r13, %c[r13](%0) \n\t"
9362 "mov %%r14, %c[r14](%0) \n\t"
9363 "mov %%r15, %c[r15](%0) \n\t"
9365 "mov %%cr2, %%" _ASM_AX
" \n\t"
9366 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9368 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9369 "setbe %c[fail](%0) \n\t"
9370 ".pushsection .rodata \n\t"
9371 ".global vmx_return \n\t"
9372 "vmx_return: " _ASM_PTR
" 2b \n\t"
9374 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9375 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9376 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9377 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9378 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9379 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9380 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9381 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9382 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9383 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9384 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9385 #ifdef CONFIG_X86_64
9386 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9387 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9388 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9389 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9390 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9391 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9392 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9393 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9395 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9396 [wordsize
]"i"(sizeof(ulong
))
9398 #ifdef CONFIG_X86_64
9399 , "rax", "rbx", "rdi", "rsi"
9400 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9402 , "eax", "ebx", "edi", "esi"
9406 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9408 update_debugctlmsr(debugctlmsr
);
9410 #ifndef CONFIG_X86_64
9412 * The sysexit path does not restore ds/es, so we must set them to
9413 * a reasonable value ourselves.
9415 * We can't defer this to vmx_load_host_state() since that function
9416 * may be executed in interrupt context, which saves and restore segments
9417 * around it, nullifying its effect.
9419 loadsegment(ds
, __USER_DS
);
9420 loadsegment(es
, __USER_DS
);
9423 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9424 | (1 << VCPU_EXREG_RFLAGS
)
9425 | (1 << VCPU_EXREG_PDPTR
)
9426 | (1 << VCPU_EXREG_SEGMENTS
)
9427 | (1 << VCPU_EXREG_CR3
));
9428 vcpu
->arch
.regs_dirty
= 0;
9431 * eager fpu is enabled if PKEY is supported and CR4 is switched
9432 * back on host, so it is safe to read guest PKRU from current
9435 if (static_cpu_has(X86_FEATURE_PKU
) &&
9436 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9437 vcpu
->arch
.pkru
= __read_pkru();
9438 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9439 __write_pkru(vmx
->host_pkru
);
9443 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9444 * we did not inject a still-pending event to L1 now because of
9445 * nested_run_pending, we need to re-enable this bit.
9447 if (vmx
->nested
.nested_run_pending
)
9448 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9450 vmx
->nested
.nested_run_pending
= 0;
9451 vmx
->idt_vectoring_info
= 0;
9453 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
9454 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9457 vmx
->loaded_vmcs
->launched
= 1;
9458 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9460 vmx_complete_atomic_exit(vmx
);
9461 vmx_recover_nmi_blocking(vmx
);
9462 vmx_complete_interrupts(vmx
);
9464 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9466 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9468 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9471 if (vmx
->loaded_vmcs
== vmcs
)
9475 vmx
->loaded_vmcs
= vmcs
;
9477 vmx_vcpu_load(vcpu
, cpu
);
9483 * Ensure that the current vmcs of the logical processor is the
9484 * vmcs01 of the vcpu before calling free_nested().
9486 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9488 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9491 r
= vcpu_load(vcpu
);
9493 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9498 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9500 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9503 vmx_destroy_pml_buffer(vmx
);
9504 free_vpid(vmx
->vpid
);
9505 leave_guest_mode(vcpu
);
9506 vmx_free_vcpu_nested(vcpu
);
9507 free_loaded_vmcs(vmx
->loaded_vmcs
);
9508 kfree(vmx
->guest_msrs
);
9509 kvm_vcpu_uninit(vcpu
);
9510 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9513 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9516 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9520 return ERR_PTR(-ENOMEM
);
9522 vmx
->vpid
= allocate_vpid();
9524 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9531 * If PML is turned on, failure on enabling PML just results in failure
9532 * of creating the vcpu, therefore we can simplify PML logic (by
9533 * avoiding dealing with cases, such as enabling PML partially on vcpus
9534 * for the guest, etc.
9537 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9542 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9543 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9546 if (!vmx
->guest_msrs
)
9549 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9550 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9551 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9552 if (!vmx
->loaded_vmcs
->vmcs
)
9554 loaded_vmcs_init(vmx
->loaded_vmcs
);
9557 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9558 vmx
->vcpu
.cpu
= cpu
;
9559 err
= vmx_vcpu_setup(vmx
);
9560 vmx_vcpu_put(&vmx
->vcpu
);
9564 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9565 err
= alloc_apic_access_page(kvm
);
9571 if (!kvm
->arch
.ept_identity_map_addr
)
9572 kvm
->arch
.ept_identity_map_addr
=
9573 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9574 err
= init_rmode_identity_map(kvm
);
9580 nested_vmx_setup_ctls_msrs(vmx
);
9581 vmx
->nested
.vpid02
= allocate_vpid();
9584 vmx
->nested
.posted_intr_nv
= -1;
9585 vmx
->nested
.current_vmptr
= -1ull;
9587 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9590 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9591 * or POSTED_INTR_WAKEUP_VECTOR.
9593 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9594 vmx
->pi_desc
.sn
= 1;
9599 free_vpid(vmx
->nested
.vpid02
);
9600 free_loaded_vmcs(vmx
->loaded_vmcs
);
9602 kfree(vmx
->guest_msrs
);
9604 vmx_destroy_pml_buffer(vmx
);
9606 kvm_vcpu_uninit(&vmx
->vcpu
);
9608 free_vpid(vmx
->vpid
);
9609 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9610 return ERR_PTR(err
);
9613 static void __init
vmx_check_processor_compat(void *rtn
)
9615 struct vmcs_config vmcs_conf
;
9618 if (setup_vmcs_config(&vmcs_conf
) < 0)
9620 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9621 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9622 smp_processor_id());
9627 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9632 /* For VT-d and EPT combination
9633 * 1. MMIO: always map as UC
9635 * a. VT-d without snooping control feature: can't guarantee the
9636 * result, try to trust guest.
9637 * b. VT-d with snooping control feature: snooping control feature of
9638 * VT-d engine can guarantee the cache correctness. Just set it
9639 * to WB to keep consistent with host. So the same as item 3.
9640 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9641 * consistent with host MTRR
9644 cache
= MTRR_TYPE_UNCACHABLE
;
9648 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9649 ipat
= VMX_EPT_IPAT_BIT
;
9650 cache
= MTRR_TYPE_WRBACK
;
9654 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9655 ipat
= VMX_EPT_IPAT_BIT
;
9656 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9657 cache
= MTRR_TYPE_WRBACK
;
9659 cache
= MTRR_TYPE_UNCACHABLE
;
9663 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9666 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9669 static int vmx_get_lpage_level(void)
9671 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9672 return PT_DIRECTORY_LEVEL
;
9674 /* For shadow and EPT supported 1GB page */
9675 return PT_PDPE_LEVEL
;
9678 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9681 * These bits in the secondary execution controls field
9682 * are dynamic, the others are mostly based on the hypervisor
9683 * architecture and the guest's CPUID. Do not touch the
9687 SECONDARY_EXEC_SHADOW_VMCS
|
9688 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9689 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9691 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9693 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9694 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9698 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9699 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9701 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9703 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9704 struct kvm_cpuid_entry2
*entry
;
9706 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9707 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9709 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9710 if (entry && (entry->_reg & (_cpuid_mask))) \
9711 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9714 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9715 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9716 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9717 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9718 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9719 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9720 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9721 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9722 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9723 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9724 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9725 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9726 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9727 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9728 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9730 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9731 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9732 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9733 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9734 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9735 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9736 cr4_fixed1_update(bit(11), ecx
, bit(2));
9738 #undef cr4_fixed1_update
9741 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9743 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9745 if (cpu_has_secondary_exec_ctrls()) {
9746 vmx_compute_secondary_exec_control(vmx
);
9747 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9750 if (nested_vmx_allowed(vcpu
))
9751 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9752 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9754 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9755 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9757 if (nested_vmx_allowed(vcpu
))
9758 nested_vmx_cr_fixed1_bits_update(vcpu
);
9761 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9763 if (func
== 1 && nested
)
9764 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9767 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9768 struct x86_exception
*fault
)
9770 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9771 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9773 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9775 if (vmx
->nested
.pml_full
) {
9776 exit_reason
= EXIT_REASON_PML_FULL
;
9777 vmx
->nested
.pml_full
= false;
9778 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9779 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9780 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9782 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9784 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9785 vmcs12
->guest_physical_address
= fault
->address
;
9788 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9790 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
9793 /* Callbacks for nested_ept_init_mmu_context: */
9795 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9797 /* return the page table to be shadowed - in our case, EPT12 */
9798 return get_vmcs12(vcpu
)->ept_pointer
;
9801 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9803 WARN_ON(mmu_is_nested(vcpu
));
9804 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
9807 kvm_mmu_unload(vcpu
);
9808 kvm_init_shadow_ept_mmu(vcpu
,
9809 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9810 VMX_EPT_EXECUTE_ONLY_BIT
,
9811 nested_ept_ad_enabled(vcpu
));
9812 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9813 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9814 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9816 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9820 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9822 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9825 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9828 bool inequality
, bit
;
9830 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9832 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9833 vmcs12
->page_fault_error_code_match
;
9834 return inequality
^ bit
;
9837 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9838 struct x86_exception
*fault
)
9840 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9842 WARN_ON(!is_guest_mode(vcpu
));
9844 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
) &&
9845 !to_vmx(vcpu
)->nested
.nested_run_pending
) {
9846 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9847 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9848 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9849 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9852 kvm_inject_page_fault(vcpu
, fault
);
9856 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9857 struct vmcs12
*vmcs12
);
9859 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9860 struct vmcs12
*vmcs12
)
9862 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9866 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9868 * Translate L1 physical address to host physical
9869 * address for vmcs02. Keep the page pinned, so this
9870 * physical address remains valid. We keep a reference
9871 * to it so we can release it later.
9873 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
9874 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
9875 vmx
->nested
.apic_access_page
= NULL
;
9877 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
9879 * If translation failed, no matter: This feature asks
9880 * to exit when accessing the given address, and if it
9881 * can never be accessed, this feature won't do
9884 if (!is_error_page(page
)) {
9885 vmx
->nested
.apic_access_page
= page
;
9886 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9887 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9889 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9890 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9892 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9893 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9894 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9895 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9896 kvm_vcpu_reload_apic_access_page(vcpu
);
9899 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9900 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
9901 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
9902 vmx
->nested
.virtual_apic_page
= NULL
;
9904 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9907 * If translation failed, VM entry will fail because
9908 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9909 * Failing the vm entry is _not_ what the processor
9910 * does but it's basically the only possibility we
9911 * have. We could still enter the guest if CR8 load
9912 * exits are enabled, CR8 store exits are enabled, and
9913 * virtualize APIC access is disabled; in this case
9914 * the processor would never use the TPR shadow and we
9915 * could simply clear the bit from the execution
9916 * control. But such a configuration is useless, so
9917 * let's keep the code simple.
9919 if (!is_error_page(page
)) {
9920 vmx
->nested
.virtual_apic_page
= page
;
9921 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9922 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9926 if (nested_cpu_has_posted_intr(vmcs12
)) {
9927 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9928 kunmap(vmx
->nested
.pi_desc_page
);
9929 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
9930 vmx
->nested
.pi_desc_page
= NULL
;
9932 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9933 if (is_error_page(page
))
9935 vmx
->nested
.pi_desc_page
= page
;
9936 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
9937 vmx
->nested
.pi_desc
=
9938 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9939 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9941 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9942 page_to_phys(vmx
->nested
.pi_desc_page
) +
9943 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9946 if (cpu_has_vmx_msr_bitmap() &&
9947 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9948 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9951 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9952 CPU_BASED_USE_MSR_BITMAPS
);
9955 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9957 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9958 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9960 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9963 /* Make sure short timeouts reliably trigger an immediate vmexit.
9964 * hrtimer_start does not guarantee this. */
9965 if (preemption_timeout
<= 1) {
9966 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9970 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9971 preemption_timeout
*= 1000000;
9972 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9973 hrtimer_start(&vmx
->nested
.preemption_timer
,
9974 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9977 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9978 struct vmcs12
*vmcs12
)
9980 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9983 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9984 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9990 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9991 struct vmcs12
*vmcs12
)
9993 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9996 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
10002 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
10003 struct vmcs12
*vmcs12
)
10005 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10008 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
10015 * Merge L0's and L1's MSR bitmap, return false to indicate that
10016 * we do not use the hardware.
10018 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10019 struct vmcs12
*vmcs12
)
10023 unsigned long *msr_bitmap_l1
;
10024 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
10026 /* This shortcut is ok because we support only x2APIC MSRs so far. */
10027 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
10030 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10031 if (is_error_page(page
))
10033 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10035 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
10037 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
10038 if (nested_cpu_has_apic_reg_virt(vmcs12
))
10039 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
10040 nested_vmx_disable_intercept_for_msr(
10041 msr_bitmap_l1
, msr_bitmap_l0
,
10044 nested_vmx_disable_intercept_for_msr(
10045 msr_bitmap_l1
, msr_bitmap_l0
,
10046 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
10047 MSR_TYPE_R
| MSR_TYPE_W
);
10049 if (nested_cpu_has_vid(vmcs12
)) {
10050 nested_vmx_disable_intercept_for_msr(
10051 msr_bitmap_l1
, msr_bitmap_l0
,
10052 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
10054 nested_vmx_disable_intercept_for_msr(
10055 msr_bitmap_l1
, msr_bitmap_l0
,
10056 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
10061 kvm_release_page_clean(page
);
10066 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10067 struct vmcs12
*vmcs12
)
10069 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10070 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10071 !nested_cpu_has_vid(vmcs12
) &&
10072 !nested_cpu_has_posted_intr(vmcs12
))
10076 * If virtualize x2apic mode is enabled,
10077 * virtualize apic access must be disabled.
10079 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10080 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10084 * If virtual interrupt delivery is enabled,
10085 * we must exit on external interrupts.
10087 if (nested_cpu_has_vid(vmcs12
) &&
10088 !nested_exit_on_intr(vcpu
))
10092 * bits 15:8 should be zero in posted_intr_nv,
10093 * the descriptor address has been already checked
10094 * in nested_get_vmcs12_pages.
10096 if (nested_cpu_has_posted_intr(vmcs12
) &&
10097 (!nested_cpu_has_vid(vmcs12
) ||
10098 !nested_exit_intr_ack_set(vcpu
) ||
10099 vmcs12
->posted_intr_nv
& 0xff00))
10102 /* tpr shadow is needed by all apicv features. */
10103 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10109 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10110 unsigned long count_field
,
10111 unsigned long addr_field
)
10116 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10117 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10123 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10124 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10125 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10126 pr_debug_ratelimited(
10127 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10128 addr_field
, maxphyaddr
, count
, addr
);
10134 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10135 struct vmcs12
*vmcs12
)
10137 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10138 vmcs12
->vm_exit_msr_store_count
== 0 &&
10139 vmcs12
->vm_entry_msr_load_count
== 0)
10140 return 0; /* Fast path */
10141 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10142 VM_EXIT_MSR_LOAD_ADDR
) ||
10143 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10144 VM_EXIT_MSR_STORE_ADDR
) ||
10145 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10146 VM_ENTRY_MSR_LOAD_ADDR
))
10151 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10152 struct vmcs12
*vmcs12
)
10154 u64 address
= vmcs12
->pml_address
;
10155 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10157 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10158 if (!nested_cpu_has_ept(vmcs12
) ||
10159 !IS_ALIGNED(address
, 4096) ||
10160 address
>> maxphyaddr
)
10167 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10168 struct vmx_msr_entry
*e
)
10170 /* x2APIC MSR accesses are not allowed */
10171 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10173 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10174 e
->index
== MSR_IA32_UCODE_REV
)
10176 if (e
->reserved
!= 0)
10181 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10182 struct vmx_msr_entry
*e
)
10184 if (e
->index
== MSR_FS_BASE
||
10185 e
->index
== MSR_GS_BASE
||
10186 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10187 nested_vmx_msr_check_common(vcpu
, e
))
10192 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10193 struct vmx_msr_entry
*e
)
10195 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10196 nested_vmx_msr_check_common(vcpu
, e
))
10202 * Load guest's/host's msr at nested entry/exit.
10203 * return 0 for success, entry index for failure.
10205 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10208 struct vmx_msr_entry e
;
10209 struct msr_data msr
;
10211 msr
.host_initiated
= false;
10212 for (i
= 0; i
< count
; i
++) {
10213 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10215 pr_debug_ratelimited(
10216 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10217 __func__
, i
, gpa
+ i
* sizeof(e
));
10220 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10221 pr_debug_ratelimited(
10222 "%s check failed (%u, 0x%x, 0x%x)\n",
10223 __func__
, i
, e
.index
, e
.reserved
);
10226 msr
.index
= e
.index
;
10227 msr
.data
= e
.value
;
10228 if (kvm_set_msr(vcpu
, &msr
)) {
10229 pr_debug_ratelimited(
10230 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10231 __func__
, i
, e
.index
, e
.value
);
10240 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10243 struct vmx_msr_entry e
;
10245 for (i
= 0; i
< count
; i
++) {
10246 struct msr_data msr_info
;
10247 if (kvm_vcpu_read_guest(vcpu
,
10248 gpa
+ i
* sizeof(e
),
10249 &e
, 2 * sizeof(u32
))) {
10250 pr_debug_ratelimited(
10251 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10252 __func__
, i
, gpa
+ i
* sizeof(e
));
10255 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10256 pr_debug_ratelimited(
10257 "%s check failed (%u, 0x%x, 0x%x)\n",
10258 __func__
, i
, e
.index
, e
.reserved
);
10261 msr_info
.host_initiated
= false;
10262 msr_info
.index
= e
.index
;
10263 if (kvm_get_msr(vcpu
, &msr_info
)) {
10264 pr_debug_ratelimited(
10265 "%s cannot read MSR (%u, 0x%x)\n",
10266 __func__
, i
, e
.index
);
10269 if (kvm_vcpu_write_guest(vcpu
,
10270 gpa
+ i
* sizeof(e
) +
10271 offsetof(struct vmx_msr_entry
, value
),
10272 &msr_info
.data
, sizeof(msr_info
.data
))) {
10273 pr_debug_ratelimited(
10274 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10275 __func__
, i
, e
.index
, msr_info
.data
);
10282 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10284 unsigned long invalid_mask
;
10286 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10287 return (val
& invalid_mask
) == 0;
10291 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10292 * emulating VM entry into a guest with EPT enabled.
10293 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10294 * is assigned to entry_failure_code on failure.
10296 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10297 u32
*entry_failure_code
)
10299 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10300 if (!nested_cr3_valid(vcpu
, cr3
)) {
10301 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10306 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10307 * must not be dereferenced.
10309 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10311 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10312 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10317 vcpu
->arch
.cr3
= cr3
;
10318 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10321 kvm_mmu_reset_context(vcpu
);
10326 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10327 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10328 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10329 * guest in a way that will both be appropriate to L1's requests, and our
10330 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10331 * function also has additional necessary side-effects, like setting various
10332 * vcpu->arch fields.
10333 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10334 * is assigned to entry_failure_code on failure.
10336 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10337 bool from_vmentry
, u32
*entry_failure_code
)
10339 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10340 u32 exec_control
, vmcs12_exec_ctrl
;
10342 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10343 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10344 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10345 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10346 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10347 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10348 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10349 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10350 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10351 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10352 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10353 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10354 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10355 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10356 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10357 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10358 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10359 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10360 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10361 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10362 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10363 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10364 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10365 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10366 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10367 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10368 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10369 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10370 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10371 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10372 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10373 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10374 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10375 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10376 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10377 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10379 if (from_vmentry
&&
10380 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10381 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10382 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10384 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10385 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10387 if (from_vmentry
) {
10388 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10389 vmcs12
->vm_entry_intr_info_field
);
10390 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10391 vmcs12
->vm_entry_exception_error_code
);
10392 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10393 vmcs12
->vm_entry_instruction_len
);
10394 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10395 vmcs12
->guest_interruptibility_info
);
10396 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10397 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10399 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10401 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10402 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10403 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10404 vmcs12
->guest_pending_dbg_exceptions
);
10405 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10406 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10408 if (nested_cpu_has_xsaves(vmcs12
))
10409 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10410 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10412 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10414 /* Preemption timer setting is only taken from vmcs01. */
10415 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10416 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10417 if (vmx
->hv_deadline_tsc
== -1)
10418 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10420 /* Posted interrupts setting is only taken from vmcs12. */
10421 if (nested_cpu_has_posted_intr(vmcs12
)) {
10422 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10423 vmx
->nested
.pi_pending
= false;
10424 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10426 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10429 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10431 vmx
->nested
.preemption_timer_expired
= false;
10432 if (nested_cpu_has_preemption_timer(vmcs12
))
10433 vmx_start_preemption_timer(vcpu
);
10436 * Whether page-faults are trapped is determined by a combination of
10437 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10438 * If enable_ept, L0 doesn't care about page faults and we should
10439 * set all of these to L1's desires. However, if !enable_ept, L0 does
10440 * care about (at least some) page faults, and because it is not easy
10441 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10442 * to exit on each and every L2 page fault. This is done by setting
10443 * MASK=MATCH=0 and (see below) EB.PF=1.
10444 * Note that below we don't need special code to set EB.PF beyond the
10445 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10446 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10447 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10449 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10450 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10451 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10452 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10454 if (cpu_has_secondary_exec_ctrls()) {
10455 exec_control
= vmx
->secondary_exec_control
;
10457 /* Take the following fields only from vmcs12 */
10458 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10459 SECONDARY_EXEC_ENABLE_INVPCID
|
10460 SECONDARY_EXEC_RDTSCP
|
10461 SECONDARY_EXEC_XSAVES
|
10462 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10463 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10464 SECONDARY_EXEC_ENABLE_VMFUNC
);
10465 if (nested_cpu_has(vmcs12
,
10466 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10467 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10468 ~SECONDARY_EXEC_ENABLE_PML
;
10469 exec_control
|= vmcs12_exec_ctrl
;
10472 /* All VMFUNCs are currently emulated through L0 vmexits. */
10473 if (exec_control
& SECONDARY_EXEC_ENABLE_VMFUNC
)
10474 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10476 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10477 vmcs_write64(EOI_EXIT_BITMAP0
,
10478 vmcs12
->eoi_exit_bitmap0
);
10479 vmcs_write64(EOI_EXIT_BITMAP1
,
10480 vmcs12
->eoi_exit_bitmap1
);
10481 vmcs_write64(EOI_EXIT_BITMAP2
,
10482 vmcs12
->eoi_exit_bitmap2
);
10483 vmcs_write64(EOI_EXIT_BITMAP3
,
10484 vmcs12
->eoi_exit_bitmap3
);
10485 vmcs_write16(GUEST_INTR_STATUS
,
10486 vmcs12
->guest_intr_status
);
10490 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10491 * nested_get_vmcs12_pages will either fix it up or
10492 * remove the VM execution control.
10494 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10495 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10497 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10502 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10503 * Some constant fields are set here by vmx_set_constant_host_state().
10504 * Other fields are different per CPU, and will be set later when
10505 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10507 vmx_set_constant_host_state(vmx
);
10510 * Set the MSR load/store lists to match L0's settings.
10512 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10513 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10514 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10515 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10516 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10519 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10520 * entry, but only if the current (host) sp changed from the value
10521 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10522 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10523 * here we just force the write to happen on entry.
10527 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10528 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10529 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10530 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10531 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10534 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10535 * nested_get_vmcs12_pages can't fix it up, the illegal value
10536 * will result in a VM entry failure.
10538 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10539 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10540 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10542 #ifdef CONFIG_X86_64
10543 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10544 CPU_BASED_CR8_STORE_EXITING
;
10549 * Merging of IO bitmap not currently supported.
10550 * Rather, exit every time.
10552 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10553 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10555 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10557 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10558 * bitwise-or of what L1 wants to trap for L2, and what we want to
10559 * trap. Note that CR0.TS also needs updating - we do this later.
10561 update_exception_bitmap(vcpu
);
10562 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10563 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10565 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10566 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10567 * bits are further modified by vmx_set_efer() below.
10569 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10571 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10572 * emulated by vmx_set_efer(), below.
10574 vm_entry_controls_init(vmx
,
10575 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10576 ~VM_ENTRY_IA32E_MODE
) |
10577 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10579 if (from_vmentry
&&
10580 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10581 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10582 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10583 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10584 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10587 set_cr4_guest_host_mask(vmx
);
10589 if (from_vmentry
&&
10590 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10591 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10593 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10594 vmcs_write64(TSC_OFFSET
,
10595 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10597 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10598 if (kvm_has_tsc_control
)
10599 decache_tsc_multiplier(vmx
);
10603 * There is no direct mapping between vpid02 and vpid12, the
10604 * vpid02 is per-vCPU for L0 and reused while the value of
10605 * vpid12 is changed w/ one invvpid during nested vmentry.
10606 * The vpid12 is allocated by L1 for L2, so it will not
10607 * influence global bitmap(for vpid01 and vpid02 allocation)
10608 * even if spawn a lot of nested vCPUs.
10610 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10611 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10612 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10613 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10614 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10617 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10618 vmx_flush_tlb(vcpu
);
10625 * Conceptually we want to copy the PML address and index from
10626 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10627 * since we always flush the log on each vmexit, this happens
10628 * to be equivalent to simply resetting the fields in vmcs02.
10630 ASSERT(vmx
->pml_pg
);
10631 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10632 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10635 if (nested_cpu_has_ept(vmcs12
)) {
10636 if (nested_ept_init_mmu_context(vcpu
)) {
10637 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10640 } else if (nested_cpu_has2(vmcs12
,
10641 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10642 vmx_flush_tlb_ept_only(vcpu
);
10646 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10647 * bits which we consider mandatory enabled.
10648 * The CR0_READ_SHADOW is what L2 should have expected to read given
10649 * the specifications by L1; It's not enough to take
10650 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10651 * have more bits than L1 expected.
10653 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10654 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10656 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10657 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10659 if (from_vmentry
&&
10660 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10661 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10662 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10663 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10665 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10666 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10667 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10669 /* Shadow page tables on either EPT or shadow page tables. */
10670 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10671 entry_failure_code
))
10675 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10678 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10681 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10682 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10683 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10684 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10687 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10688 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10692 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10694 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10696 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10697 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10698 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10700 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10701 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10703 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10704 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10706 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
10707 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10709 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10710 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10712 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10713 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10715 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10716 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10718 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10719 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10720 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10721 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10722 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10723 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10724 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10725 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10726 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10727 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10728 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10729 vmx
->nested
.nested_vmx_exit_ctls_low
,
10730 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10731 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10732 vmx
->nested
.nested_vmx_entry_ctls_low
,
10733 vmx
->nested
.nested_vmx_entry_ctls_high
))
10734 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10736 if (nested_cpu_has_vmfunc(vmcs12
)) {
10737 if (vmcs12
->vm_function_control
&
10738 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
10739 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10741 if (nested_cpu_has_eptp_switching(vmcs12
)) {
10742 if (!nested_cpu_has_ept(vmcs12
) ||
10743 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
10744 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10748 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10749 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10751 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10752 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10753 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10754 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10759 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10764 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10766 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10767 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10770 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10771 vmcs12
->vmcs_link_pointer
!= -1ull) {
10772 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10777 * If the load IA32_EFER VM-entry control is 1, the following checks
10778 * are performed on the field for the IA32_EFER MSR:
10779 * - Bits reserved in the IA32_EFER MSR must be 0.
10780 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10781 * the IA-32e mode guest VM-exit control. It must also be identical
10782 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10785 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10786 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10787 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10788 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10789 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10790 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10791 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10796 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10797 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10798 * the values of the LMA and LME bits in the field must each be that of
10799 * the host address-space size VM-exit control.
10801 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10802 ia32e
= (vmcs12
->vm_exit_controls
&
10803 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10804 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10805 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10806 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10813 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10815 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10816 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10817 struct loaded_vmcs
*vmcs02
;
10821 vmcs02
= nested_get_current_vmcs02(vmx
);
10825 enter_guest_mode(vcpu
);
10827 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10828 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10830 vmx_switch_vmcs(vcpu
, vmcs02
);
10831 vmx_segment_cache_clear(vmx
);
10833 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10834 leave_guest_mode(vcpu
);
10835 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10836 nested_vmx_entry_failure(vcpu
, vmcs12
,
10837 EXIT_REASON_INVALID_STATE
, exit_qual
);
10841 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10843 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10844 vmcs12
->vm_entry_msr_load_addr
,
10845 vmcs12
->vm_entry_msr_load_count
);
10846 if (msr_entry_idx
) {
10847 leave_guest_mode(vcpu
);
10848 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10849 nested_vmx_entry_failure(vcpu
, vmcs12
,
10850 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10855 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10856 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10857 * returned as far as L1 is concerned. It will only return (and set
10858 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10864 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10865 * for running an L2 nested guest.
10867 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10869 struct vmcs12
*vmcs12
;
10870 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10871 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10875 if (!nested_vmx_check_permission(vcpu
))
10878 if (!nested_vmx_check_vmcs12(vcpu
))
10881 vmcs12
= get_vmcs12(vcpu
);
10883 if (enable_shadow_vmcs
)
10884 copy_shadow_to_vmcs12(vmx
);
10887 * The nested entry process starts with enforcing various prerequisites
10888 * on vmcs12 as required by the Intel SDM, and act appropriately when
10889 * they fail: As the SDM explains, some conditions should cause the
10890 * instruction to fail, while others will cause the instruction to seem
10891 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10892 * To speed up the normal (success) code path, we should avoid checking
10893 * for misconfigurations which will anyway be caught by the processor
10894 * when using the merged vmcs02.
10896 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10897 nested_vmx_failValid(vcpu
,
10898 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10902 if (vmcs12
->launch_state
== launch
) {
10903 nested_vmx_failValid(vcpu
,
10904 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10905 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10909 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10911 nested_vmx_failValid(vcpu
, ret
);
10916 * After this point, the trap flag no longer triggers a singlestep trap
10917 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10918 * This is not 100% correct; for performance reasons, we delegate most
10919 * of the checks on host state to the processor. If those fail,
10920 * the singlestep trap is missed.
10922 skip_emulated_instruction(vcpu
);
10924 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10926 nested_vmx_entry_failure(vcpu
, vmcs12
,
10927 EXIT_REASON_INVALID_STATE
, exit_qual
);
10932 * We're finally done with prerequisite checking, and can start with
10933 * the nested entry.
10936 ret
= enter_vmx_non_root_mode(vcpu
, true);
10940 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10941 return kvm_vcpu_halt(vcpu
);
10943 vmx
->nested
.nested_run_pending
= 1;
10948 return kvm_skip_emulated_instruction(vcpu
);
10952 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10953 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10954 * This function returns the new value we should put in vmcs12.guest_cr0.
10955 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10956 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10957 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10958 * didn't trap the bit, because if L1 did, so would L0).
10959 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10960 * been modified by L2, and L1 knows it. So just leave the old value of
10961 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10962 * isn't relevant, because if L0 traps this bit it can set it to anything.
10963 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10964 * changed these bits, and therefore they need to be updated, but L0
10965 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10966 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10968 static inline unsigned long
10969 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10972 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10973 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10974 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10975 vcpu
->arch
.cr0_guest_owned_bits
));
10978 static inline unsigned long
10979 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10982 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10983 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10984 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10985 vcpu
->arch
.cr4_guest_owned_bits
));
10988 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10989 struct vmcs12
*vmcs12
)
10994 if (vcpu
->arch
.exception
.injected
) {
10995 nr
= vcpu
->arch
.exception
.nr
;
10996 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10998 if (kvm_exception_is_soft(nr
)) {
10999 vmcs12
->vm_exit_instruction_len
=
11000 vcpu
->arch
.event_exit_inst_len
;
11001 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
11003 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
11005 if (vcpu
->arch
.exception
.has_error_code
) {
11006 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
11007 vmcs12
->idt_vectoring_error_code
=
11008 vcpu
->arch
.exception
.error_code
;
11011 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11012 } else if (vcpu
->arch
.nmi_injected
) {
11013 vmcs12
->idt_vectoring_info_field
=
11014 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
11015 } else if (vcpu
->arch
.interrupt
.pending
) {
11016 nr
= vcpu
->arch
.interrupt
.nr
;
11017 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11019 if (vcpu
->arch
.interrupt
.soft
) {
11020 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11021 vmcs12
->vm_entry_instruction_len
=
11022 vcpu
->arch
.event_exit_inst_len
;
11024 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11026 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11030 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11032 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11033 unsigned long exit_qual
;
11035 if (kvm_event_needs_reinjection(vcpu
))
11038 if (vcpu
->arch
.exception
.pending
&&
11039 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
11040 if (vmx
->nested
.nested_run_pending
)
11042 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
11043 vcpu
->arch
.exception
.pending
= false;
11047 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11048 vmx
->nested
.preemption_timer_expired
) {
11049 if (vmx
->nested
.nested_run_pending
)
11051 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11055 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11056 if (vmx
->nested
.nested_run_pending
)
11058 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11059 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11060 INTR_INFO_VALID_MASK
, 0);
11062 * The NMI-triggered VM exit counts as injection:
11063 * clear this one and block further NMIs.
11065 vcpu
->arch
.nmi_pending
= 0;
11066 vmx_set_nmi_mask(vcpu
, true);
11070 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11071 nested_exit_on_intr(vcpu
)) {
11072 if (vmx
->nested
.nested_run_pending
)
11074 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11078 vmx_complete_nested_posted_interrupt(vcpu
);
11082 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11084 ktime_t remaining
=
11085 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11088 if (ktime_to_ns(remaining
) <= 0)
11091 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11092 do_div(value
, 1000000);
11093 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11097 * Update the guest state fields of vmcs12 to reflect changes that
11098 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11099 * VM-entry controls is also updated, since this is really a guest
11102 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11104 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11105 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11107 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11108 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11109 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11111 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11112 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11113 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11114 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11115 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11116 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11117 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11118 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11119 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11120 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11121 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11122 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11123 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11124 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11125 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11126 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11127 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11128 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11129 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11130 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11131 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11132 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11133 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11134 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11135 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11136 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11137 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11138 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11139 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11140 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11141 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11142 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11143 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11144 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11145 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11146 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11148 vmcs12
->guest_interruptibility_info
=
11149 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11150 vmcs12
->guest_pending_dbg_exceptions
=
11151 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11152 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11153 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11155 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11157 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11158 if (vmcs12
->vm_exit_controls
&
11159 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11160 vmcs12
->vmx_preemption_timer_value
=
11161 vmx_get_preemption_timer_value(vcpu
);
11162 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11166 * In some cases (usually, nested EPT), L2 is allowed to change its
11167 * own CR3 without exiting. If it has changed it, we must keep it.
11168 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11169 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11171 * Additionally, restore L2's PDPTR to vmcs12.
11174 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11175 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11176 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11177 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11178 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11181 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11183 if (nested_cpu_has_vid(vmcs12
))
11184 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11186 vmcs12
->vm_entry_controls
=
11187 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11188 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11190 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11191 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11192 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11195 /* TODO: These cannot have changed unless we have MSR bitmaps and
11196 * the relevant bit asks not to trap the change */
11197 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11198 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11199 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11200 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11201 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11202 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11203 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11204 if (kvm_mpx_supported())
11205 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11209 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11210 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11211 * and this function updates it to reflect the changes to the guest state while
11212 * L2 was running (and perhaps made some exits which were handled directly by L0
11213 * without going back to L1), and to reflect the exit reason.
11214 * Note that we do not have to copy here all VMCS fields, just those that
11215 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11216 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11217 * which already writes to vmcs12 directly.
11219 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11220 u32 exit_reason
, u32 exit_intr_info
,
11221 unsigned long exit_qualification
)
11223 /* update guest state fields: */
11224 sync_vmcs12(vcpu
, vmcs12
);
11226 /* update exit information fields: */
11228 vmcs12
->vm_exit_reason
= exit_reason
;
11229 vmcs12
->exit_qualification
= exit_qualification
;
11230 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11232 vmcs12
->idt_vectoring_info_field
= 0;
11233 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11234 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11236 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11237 vmcs12
->launch_state
= 1;
11239 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11240 * instead of reading the real value. */
11241 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11244 * Transfer the event that L0 or L1 may wanted to inject into
11245 * L2 to IDT_VECTORING_INFO_FIELD.
11247 vmcs12_save_pending_event(vcpu
, vmcs12
);
11251 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11252 * preserved above and would only end up incorrectly in L1.
11254 vcpu
->arch
.nmi_injected
= false;
11255 kvm_clear_exception_queue(vcpu
);
11256 kvm_clear_interrupt_queue(vcpu
);
11260 * A part of what we need to when the nested L2 guest exits and we want to
11261 * run its L1 parent, is to reset L1's guest state to the host state specified
11263 * This function is to be called not only on normal nested exit, but also on
11264 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11265 * Failures During or After Loading Guest State").
11266 * This function should be called when the active VMCS is L1's (vmcs01).
11268 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11269 struct vmcs12
*vmcs12
)
11271 struct kvm_segment seg
;
11272 u32 entry_failure_code
;
11274 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11275 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11276 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11277 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11279 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11280 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11282 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11283 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11284 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11286 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11287 * actually changed, because vmx_set_cr0 refers to efer set above.
11289 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11290 * (KVM doesn't change it);
11292 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11293 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11295 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11296 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11297 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11299 nested_ept_uninit_mmu_context(vcpu
);
11302 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11303 * couldn't have changed.
11305 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11306 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11309 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11313 * Trivially support vpid by letting L2s share their parent
11314 * L1's vpid. TODO: move to a more elaborate solution, giving
11315 * each L2 its own vpid and exposing the vpid feature to L1.
11317 vmx_flush_tlb(vcpu
);
11319 /* Restore posted intr vector. */
11320 if (nested_cpu_has_posted_intr(vmcs12
))
11321 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11323 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11324 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11325 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11326 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11327 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11329 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11330 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11331 vmcs_write64(GUEST_BNDCFGS
, 0);
11333 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11334 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11335 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11337 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11338 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11339 vmcs12
->host_ia32_perf_global_ctrl
);
11341 /* Set L1 segment info according to Intel SDM
11342 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11343 seg
= (struct kvm_segment
) {
11345 .limit
= 0xFFFFFFFF,
11346 .selector
= vmcs12
->host_cs_selector
,
11352 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11356 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11357 seg
= (struct kvm_segment
) {
11359 .limit
= 0xFFFFFFFF,
11366 seg
.selector
= vmcs12
->host_ds_selector
;
11367 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11368 seg
.selector
= vmcs12
->host_es_selector
;
11369 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11370 seg
.selector
= vmcs12
->host_ss_selector
;
11371 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11372 seg
.selector
= vmcs12
->host_fs_selector
;
11373 seg
.base
= vmcs12
->host_fs_base
;
11374 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11375 seg
.selector
= vmcs12
->host_gs_selector
;
11376 seg
.base
= vmcs12
->host_gs_base
;
11377 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11378 seg
= (struct kvm_segment
) {
11379 .base
= vmcs12
->host_tr_base
,
11381 .selector
= vmcs12
->host_tr_selector
,
11385 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11387 kvm_set_dr(vcpu
, 7, 0x400);
11388 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11390 if (cpu_has_vmx_msr_bitmap())
11391 vmx_set_msr_bitmap(vcpu
);
11393 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11394 vmcs12
->vm_exit_msr_load_count
))
11395 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11399 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11400 * and modify vmcs12 to make it see what it would expect to see there if
11401 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11403 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11404 u32 exit_intr_info
,
11405 unsigned long exit_qualification
)
11407 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11408 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11410 /* trying to cancel vmlaunch/vmresume is a bug */
11411 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11414 * The only expected VM-instruction error is "VM entry with
11415 * invalid control field(s)." Anything else indicates a
11418 WARN_ON_ONCE(vmx
->fail
&& (vmcs_read32(VM_INSTRUCTION_ERROR
) !=
11419 VMXERR_ENTRY_INVALID_CONTROL_FIELD
));
11421 leave_guest_mode(vcpu
);
11423 if (likely(!vmx
->fail
)) {
11424 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11425 exit_qualification
);
11427 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11428 vmcs12
->vm_exit_msr_store_count
))
11429 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11432 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11433 vm_entry_controls_reset_shadow(vmx
);
11434 vm_exit_controls_reset_shadow(vmx
);
11435 vmx_segment_cache_clear(vmx
);
11437 /* if no vmcs02 cache requested, remove the one we used */
11438 if (VMCS02_POOL_SIZE
== 0)
11439 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11441 /* Update any VMCS fields that might have changed while L2 ran */
11442 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11443 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11444 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11445 if (vmx
->hv_deadline_tsc
== -1)
11446 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11447 PIN_BASED_VMX_PREEMPTION_TIMER
);
11449 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11450 PIN_BASED_VMX_PREEMPTION_TIMER
);
11451 if (kvm_has_tsc_control
)
11452 decache_tsc_multiplier(vmx
);
11454 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11455 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11456 vmx_set_virtual_x2apic_mode(vcpu
,
11457 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11458 } else if (!nested_cpu_has_ept(vmcs12
) &&
11459 nested_cpu_has2(vmcs12
,
11460 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11461 vmx_flush_tlb_ept_only(vcpu
);
11464 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11467 /* Unpin physical memory we referred to in vmcs02 */
11468 if (vmx
->nested
.apic_access_page
) {
11469 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11470 vmx
->nested
.apic_access_page
= NULL
;
11472 if (vmx
->nested
.virtual_apic_page
) {
11473 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11474 vmx
->nested
.virtual_apic_page
= NULL
;
11476 if (vmx
->nested
.pi_desc_page
) {
11477 kunmap(vmx
->nested
.pi_desc_page
);
11478 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11479 vmx
->nested
.pi_desc_page
= NULL
;
11480 vmx
->nested
.pi_desc
= NULL
;
11484 * We are now running in L2, mmu_notifier will force to reload the
11485 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11487 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11489 if (enable_shadow_vmcs
)
11490 vmx
->nested
.sync_shadow_vmcs
= true;
11492 /* in case we halted in L2 */
11493 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11495 if (likely(!vmx
->fail
)) {
11497 * TODO: SDM says that with acknowledge interrupt on
11498 * exit, bit 31 of the VM-exit interrupt information
11499 * (valid interrupt) is always set to 1 on
11500 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11501 * need kvm_cpu_has_interrupt(). See the commit
11502 * message for details.
11504 if (nested_exit_intr_ack_set(vcpu
) &&
11505 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11506 kvm_cpu_has_interrupt(vcpu
)) {
11507 int irq
= kvm_cpu_get_interrupt(vcpu
);
11509 vmcs12
->vm_exit_intr_info
= irq
|
11510 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11513 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11514 vmcs12
->exit_qualification
,
11515 vmcs12
->idt_vectoring_info_field
,
11516 vmcs12
->vm_exit_intr_info
,
11517 vmcs12
->vm_exit_intr_error_code
,
11520 load_vmcs12_host_state(vcpu
, vmcs12
);
11526 * After an early L2 VM-entry failure, we're now back
11527 * in L1 which thinks it just finished a VMLAUNCH or
11528 * VMRESUME instruction, so we need to set the failure
11529 * flag and the VM-instruction error field of the VMCS
11532 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11534 * The emulated instruction was already skipped in
11535 * nested_vmx_run, but the updated RIP was never
11536 * written back to the vmcs01.
11538 skip_emulated_instruction(vcpu
);
11543 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11545 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11547 if (is_guest_mode(vcpu
)) {
11548 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11549 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11551 free_nested(to_vmx(vcpu
));
11555 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11556 * 23.7 "VM-entry failures during or after loading guest state" (this also
11557 * lists the acceptable exit-reason and exit-qualification parameters).
11558 * It should only be called before L2 actually succeeded to run, and when
11559 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11561 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11562 struct vmcs12
*vmcs12
,
11563 u32 reason
, unsigned long qualification
)
11565 load_vmcs12_host_state(vcpu
, vmcs12
);
11566 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11567 vmcs12
->exit_qualification
= qualification
;
11568 nested_vmx_succeed(vcpu
);
11569 if (enable_shadow_vmcs
)
11570 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11573 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11574 struct x86_instruction_info
*info
,
11575 enum x86_intercept_stage stage
)
11577 return X86EMUL_CONTINUE
;
11580 #ifdef CONFIG_X86_64
11581 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11582 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11583 u64 divisor
, u64
*result
)
11585 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11587 /* To avoid the overflow on divq */
11588 if (high
>= divisor
)
11591 /* Low hold the result, high hold rem which is discarded */
11592 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11593 "rm" (divisor
), "0" (low
), "1" (high
));
11599 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11601 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11602 u64 tscl
= rdtsc();
11603 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11604 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11606 /* Convert to host delta tsc if tsc scaling is enabled */
11607 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11608 u64_shl_div_u64(delta_tsc
,
11609 kvm_tsc_scaling_ratio_frac_bits
,
11610 vcpu
->arch
.tsc_scaling_ratio
,
11615 * If the delta tsc can't fit in the 32 bit after the multi shift,
11616 * we can't use the preemption timer.
11617 * It's possible that it fits on later vmentries, but checking
11618 * on every vmentry is costly so we just use an hrtimer.
11620 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11623 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11624 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11625 PIN_BASED_VMX_PREEMPTION_TIMER
);
11627 return delta_tsc
== 0;
11630 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11632 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11633 vmx
->hv_deadline_tsc
= -1;
11634 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11635 PIN_BASED_VMX_PREEMPTION_TIMER
);
11639 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11642 shrink_ple_window(vcpu
);
11645 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11646 struct kvm_memory_slot
*slot
)
11648 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11649 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11652 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11653 struct kvm_memory_slot
*slot
)
11655 kvm_mmu_slot_set_dirty(kvm
, slot
);
11658 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11660 kvm_flush_pml_buffers(kvm
);
11663 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11665 struct vmcs12
*vmcs12
;
11666 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11668 struct page
*page
= NULL
;
11671 if (is_guest_mode(vcpu
)) {
11672 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11675 * Check if PML is enabled for the nested guest.
11676 * Whether eptp bit 6 is set is already checked
11677 * as part of A/D emulation.
11679 vmcs12
= get_vmcs12(vcpu
);
11680 if (!nested_cpu_has_pml(vmcs12
))
11683 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11684 vmx
->nested
.pml_full
= true;
11688 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11690 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11691 if (is_error_page(page
))
11694 pml_address
= kmap(page
);
11695 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11697 kvm_release_page_clean(page
);
11703 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11704 struct kvm_memory_slot
*memslot
,
11705 gfn_t offset
, unsigned long mask
)
11707 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11710 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
11712 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11713 struct pi_desc old
, new;
11717 old
.control
= new.control
= pi_desc
->control
;
11718 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
11719 "Wakeup handler not enabled while the VCPU is blocked\n");
11721 dest
= cpu_physical_id(vcpu
->cpu
);
11723 if (x2apic_enabled())
11726 new.ndst
= (dest
<< 8) & 0xFF00;
11728 /* set 'NV' to 'notification vector' */
11729 new.nv
= POSTED_INTR_VECTOR
;
11730 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11731 new.control
) != old
.control
);
11733 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
11734 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11735 list_del(&vcpu
->blocked_vcpu_list
);
11736 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11737 vcpu
->pre_pcpu
= -1;
11742 * This routine does the following things for vCPU which is going
11743 * to be blocked if VT-d PI is enabled.
11744 * - Store the vCPU to the wakeup list, so when interrupts happen
11745 * we can find the right vCPU to wake up.
11746 * - Change the Posted-interrupt descriptor as below:
11747 * 'NDST' <-- vcpu->pre_pcpu
11748 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11749 * - If 'ON' is set during this process, which means at least one
11750 * interrupt is posted for this vCPU, we cannot block it, in
11751 * this case, return 1, otherwise, return 0.
11754 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11757 struct pi_desc old
, new;
11758 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11760 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11761 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11762 !kvm_vcpu_apicv_active(vcpu
))
11765 WARN_ON(irqs_disabled());
11766 local_irq_disable();
11767 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
11768 vcpu
->pre_pcpu
= vcpu
->cpu
;
11769 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11770 list_add_tail(&vcpu
->blocked_vcpu_list
,
11771 &per_cpu(blocked_vcpu_on_cpu
,
11773 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11777 old
.control
= new.control
= pi_desc
->control
;
11779 WARN((pi_desc
->sn
== 1),
11780 "Warning: SN field of posted-interrupts "
11781 "is set before blocking\n");
11784 * Since vCPU can be preempted during this process,
11785 * vcpu->cpu could be different with pre_pcpu, we
11786 * need to set pre_pcpu as the destination of wakeup
11787 * notification event, then we can find the right vCPU
11788 * to wakeup in wakeup handler if interrupts happen
11789 * when the vCPU is in blocked state.
11791 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11793 if (x2apic_enabled())
11796 new.ndst
= (dest
<< 8) & 0xFF00;
11798 /* set 'NV' to 'wakeup vector' */
11799 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11800 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11801 new.control
) != old
.control
);
11803 /* We should not block the vCPU if an interrupt is posted for it. */
11804 if (pi_test_on(pi_desc
) == 1)
11805 __pi_post_block(vcpu
);
11807 local_irq_enable();
11808 return (vcpu
->pre_pcpu
== -1);
11811 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11813 if (pi_pre_block(vcpu
))
11816 if (kvm_lapic_hv_timer_in_use(vcpu
))
11817 kvm_lapic_switch_to_sw_timer(vcpu
);
11822 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11824 if (vcpu
->pre_pcpu
== -1)
11827 WARN_ON(irqs_disabled());
11828 local_irq_disable();
11829 __pi_post_block(vcpu
);
11830 local_irq_enable();
11833 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11835 if (kvm_x86_ops
->set_hv_timer
)
11836 kvm_lapic_switch_to_hv_timer(vcpu
);
11838 pi_post_block(vcpu
);
11842 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11845 * @host_irq: host irq of the interrupt
11846 * @guest_irq: gsi of the interrupt
11847 * @set: set or unset PI
11848 * returns 0 on success, < 0 on failure
11850 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11851 uint32_t guest_irq
, bool set
)
11853 struct kvm_kernel_irq_routing_entry
*e
;
11854 struct kvm_irq_routing_table
*irq_rt
;
11855 struct kvm_lapic_irq irq
;
11856 struct kvm_vcpu
*vcpu
;
11857 struct vcpu_data vcpu_info
;
11860 if (!kvm_arch_has_assigned_device(kvm
) ||
11861 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11862 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11865 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11866 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11867 if (guest_irq
>= irq_rt
->nr_rt_entries
||
11868 hlist_empty(&irq_rt
->map
[guest_irq
])) {
11869 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11870 guest_irq
, irq_rt
->nr_rt_entries
);
11874 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11875 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11878 * VT-d PI cannot support posting multicast/broadcast
11879 * interrupts to a vCPU, we still use interrupt remapping
11880 * for these kind of interrupts.
11882 * For lowest-priority interrupts, we only support
11883 * those with single CPU as the destination, e.g. user
11884 * configures the interrupts via /proc/irq or uses
11885 * irqbalance to make the interrupts single-CPU.
11887 * We will support full lowest-priority interrupt later.
11890 kvm_set_msi_irq(kvm
, e
, &irq
);
11891 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11893 * Make sure the IRTE is in remapped mode if
11894 * we don't handle it in posted mode.
11896 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11899 "failed to back to remapped mode, irq: %u\n",
11907 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11908 vcpu_info
.vector
= irq
.vector
;
11910 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11911 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11914 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11916 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11919 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11927 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11931 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11933 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11934 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11935 FEATURE_CONTROL_LMCE
;
11937 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11938 ~FEATURE_CONTROL_LMCE
;
11941 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11942 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11943 .disabled_by_bios
= vmx_disabled_by_bios
,
11944 .hardware_setup
= hardware_setup
,
11945 .hardware_unsetup
= hardware_unsetup
,
11946 .check_processor_compatibility
= vmx_check_processor_compat
,
11947 .hardware_enable
= hardware_enable
,
11948 .hardware_disable
= hardware_disable
,
11949 .cpu_has_accelerated_tpr
= report_flexpriority
,
11950 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11952 .vcpu_create
= vmx_create_vcpu
,
11953 .vcpu_free
= vmx_free_vcpu
,
11954 .vcpu_reset
= vmx_vcpu_reset
,
11956 .prepare_guest_switch
= vmx_save_host_state
,
11957 .vcpu_load
= vmx_vcpu_load
,
11958 .vcpu_put
= vmx_vcpu_put
,
11960 .update_bp_intercept
= update_exception_bitmap
,
11961 .get_msr
= vmx_get_msr
,
11962 .set_msr
= vmx_set_msr
,
11963 .get_segment_base
= vmx_get_segment_base
,
11964 .get_segment
= vmx_get_segment
,
11965 .set_segment
= vmx_set_segment
,
11966 .get_cpl
= vmx_get_cpl
,
11967 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11968 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11969 .decache_cr3
= vmx_decache_cr3
,
11970 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11971 .set_cr0
= vmx_set_cr0
,
11972 .set_cr3
= vmx_set_cr3
,
11973 .set_cr4
= vmx_set_cr4
,
11974 .set_efer
= vmx_set_efer
,
11975 .get_idt
= vmx_get_idt
,
11976 .set_idt
= vmx_set_idt
,
11977 .get_gdt
= vmx_get_gdt
,
11978 .set_gdt
= vmx_set_gdt
,
11979 .get_dr6
= vmx_get_dr6
,
11980 .set_dr6
= vmx_set_dr6
,
11981 .set_dr7
= vmx_set_dr7
,
11982 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11983 .cache_reg
= vmx_cache_reg
,
11984 .get_rflags
= vmx_get_rflags
,
11985 .set_rflags
= vmx_set_rflags
,
11987 .tlb_flush
= vmx_flush_tlb
,
11989 .run
= vmx_vcpu_run
,
11990 .handle_exit
= vmx_handle_exit
,
11991 .skip_emulated_instruction
= skip_emulated_instruction
,
11992 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11993 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11994 .patch_hypercall
= vmx_patch_hypercall
,
11995 .set_irq
= vmx_inject_irq
,
11996 .set_nmi
= vmx_inject_nmi
,
11997 .queue_exception
= vmx_queue_exception
,
11998 .cancel_injection
= vmx_cancel_injection
,
11999 .interrupt_allowed
= vmx_interrupt_allowed
,
12000 .nmi_allowed
= vmx_nmi_allowed
,
12001 .get_nmi_mask
= vmx_get_nmi_mask
,
12002 .set_nmi_mask
= vmx_set_nmi_mask
,
12003 .enable_nmi_window
= enable_nmi_window
,
12004 .enable_irq_window
= enable_irq_window
,
12005 .update_cr8_intercept
= update_cr8_intercept
,
12006 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
12007 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
12008 .get_enable_apicv
= vmx_get_enable_apicv
,
12009 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
12010 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
12011 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
12012 .hwapic_irr_update
= vmx_hwapic_irr_update
,
12013 .hwapic_isr_update
= vmx_hwapic_isr_update
,
12014 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
12015 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
12017 .set_tss_addr
= vmx_set_tss_addr
,
12018 .get_tdp_level
= get_ept_level
,
12019 .get_mt_mask
= vmx_get_mt_mask
,
12021 .get_exit_info
= vmx_get_exit_info
,
12023 .get_lpage_level
= vmx_get_lpage_level
,
12025 .cpuid_update
= vmx_cpuid_update
,
12027 .rdtscp_supported
= vmx_rdtscp_supported
,
12028 .invpcid_supported
= vmx_invpcid_supported
,
12030 .set_supported_cpuid
= vmx_set_supported_cpuid
,
12032 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
12034 .write_tsc_offset
= vmx_write_tsc_offset
,
12036 .set_tdp_cr3
= vmx_set_cr3
,
12038 .check_intercept
= vmx_check_intercept
,
12039 .handle_external_intr
= vmx_handle_external_intr
,
12040 .mpx_supported
= vmx_mpx_supported
,
12041 .xsaves_supported
= vmx_xsaves_supported
,
12043 .check_nested_events
= vmx_check_nested_events
,
12045 .sched_in
= vmx_sched_in
,
12047 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
12048 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
12049 .flush_log_dirty
= vmx_flush_log_dirty
,
12050 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
12051 .write_log_dirty
= vmx_write_pml_buffer
,
12053 .pre_block
= vmx_pre_block
,
12054 .post_block
= vmx_post_block
,
12056 .pmu_ops
= &intel_pmu_ops
,
12058 .update_pi_irte
= vmx_update_pi_irte
,
12060 #ifdef CONFIG_X86_64
12061 .set_hv_timer
= vmx_set_hv_timer
,
12062 .cancel_hv_timer
= vmx_cancel_hv_timer
,
12065 .setup_mce
= vmx_setup_mce
,
12068 static int __init
vmx_init(void)
12070 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
12071 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
12075 #ifdef CONFIG_KEXEC_CORE
12076 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
12077 crash_vmclear_local_loaded_vmcss
);
12083 static void __exit
vmx_exit(void)
12085 #ifdef CONFIG_KEXEC_CORE
12086 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
12093 module_init(vmx_init
)
12094 module_exit(vmx_exit
)