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1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22 #include "lapic.h"
23
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/mm.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
38 #include "x86.h"
39
40 #include <asm/cpu.h>
41 #include <asm/io.h>
42 #include <asm/desc.h>
43 #include <asm/vmx.h>
44 #include <asm/virtext.h>
45 #include <asm/mce.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
50 #include <asm/apic.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
53
54 #include "trace.h"
55 #include "pmu.h"
56
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
60
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
63
64 static const struct x86_cpu_id vmx_cpu_id[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 {}
67 };
68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
69
70 static bool __read_mostly enable_vpid = 1;
71 module_param_named(vpid, enable_vpid, bool, 0444);
72
73 static bool __read_mostly flexpriority_enabled = 1;
74 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
75
76 static bool __read_mostly enable_ept = 1;
77 module_param_named(ept, enable_ept, bool, S_IRUGO);
78
79 static bool __read_mostly enable_unrestricted_guest = 1;
80 module_param_named(unrestricted_guest,
81 enable_unrestricted_guest, bool, S_IRUGO);
82
83 static bool __read_mostly enable_ept_ad_bits = 1;
84 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
85
86 static bool __read_mostly emulate_invalid_guest_state = true;
87 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
88
89 static bool __read_mostly fasteoi = 1;
90 module_param(fasteoi, bool, S_IRUGO);
91
92 static bool __read_mostly enable_apicv = 1;
93 module_param(enable_apicv, bool, S_IRUGO);
94
95 static bool __read_mostly enable_shadow_vmcs = 1;
96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
97 /*
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
101 */
102 static bool __read_mostly nested = 0;
103 module_param(nested, bool, S_IRUGO);
104
105 static u64 __read_mostly host_xss;
106
107 static bool __read_mostly enable_pml = 1;
108 module_param_named(pml, enable_pml, bool, S_IRUGO);
109
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
111
112 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113 static int __read_mostly cpu_preemption_timer_multi;
114 static bool __read_mostly enable_preemption_timer = 1;
115 #ifdef CONFIG_X86_64
116 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
117 #endif
118
119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
121 #define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
123 #define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
125 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
126
127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
129
130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
131
132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
133
134 /*
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
137 */
138 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
143
144 /*
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
148 * According to test, this time is usually smaller than 128 cycles.
149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
154 */
155 #define KVM_VMX_DEFAULT_PLE_GAP 128
156 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
161
162 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
163 module_param(ple_gap, int, S_IRUGO);
164
165 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
166 module_param(ple_window, int, S_IRUGO);
167
168 /* Default doubles per-vcpu window every exit. */
169 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
170 module_param(ple_window_grow, int, S_IRUGO);
171
172 /* Default resets per-vcpu window every exit to ple_window. */
173 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
174 module_param(ple_window_shrink, int, S_IRUGO);
175
176 /* Default is to compute the maximum so we can never overflow. */
177 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
178 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
179 module_param(ple_window_max, int, S_IRUGO);
180
181 extern const ulong vmx_return;
182
183 #define NR_AUTOLOAD_MSRS 8
184 #define VMCS02_POOL_SIZE 1
185
186 struct vmcs {
187 u32 revision_id;
188 u32 abort;
189 char data[0];
190 };
191
192 /*
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
196 */
197 struct loaded_vmcs {
198 struct vmcs *vmcs;
199 struct vmcs *shadow_vmcs;
200 int cpu;
201 bool launched;
202 bool nmi_known_unmasked;
203 struct list_head loaded_vmcss_on_cpu_link;
204 };
205
206 struct shared_msr_entry {
207 unsigned index;
208 u64 data;
209 u64 mask;
210 };
211
212 /*
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
224 */
225 typedef u64 natural_width;
226 struct __packed vmcs12 {
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
229 */
230 u32 revision_id;
231 u32 abort;
232
233 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding[7]; /* room for future expansion */
235
236 u64 io_bitmap_a;
237 u64 io_bitmap_b;
238 u64 msr_bitmap;
239 u64 vm_exit_msr_store_addr;
240 u64 vm_exit_msr_load_addr;
241 u64 vm_entry_msr_load_addr;
242 u64 tsc_offset;
243 u64 virtual_apic_page_addr;
244 u64 apic_access_addr;
245 u64 posted_intr_desc_addr;
246 u64 ept_pointer;
247 u64 eoi_exit_bitmap0;
248 u64 eoi_exit_bitmap1;
249 u64 eoi_exit_bitmap2;
250 u64 eoi_exit_bitmap3;
251 u64 xss_exit_bitmap;
252 u64 guest_physical_address;
253 u64 vmcs_link_pointer;
254 u64 pml_address;
255 u64 guest_ia32_debugctl;
256 u64 guest_ia32_pat;
257 u64 guest_ia32_efer;
258 u64 guest_ia32_perf_global_ctrl;
259 u64 guest_pdptr0;
260 u64 guest_pdptr1;
261 u64 guest_pdptr2;
262 u64 guest_pdptr3;
263 u64 guest_bndcfgs;
264 u64 host_ia32_pat;
265 u64 host_ia32_efer;
266 u64 host_ia32_perf_global_ctrl;
267 u64 padding64[8]; /* room for future expansion */
268 /*
269 * To allow migration of L1 (complete with its L2 guests) between
270 * machines of different natural widths (32 or 64 bit), we cannot have
271 * unsigned long fields with no explict size. We use u64 (aliased
272 * natural_width) instead. Luckily, x86 is little-endian.
273 */
274 natural_width cr0_guest_host_mask;
275 natural_width cr4_guest_host_mask;
276 natural_width cr0_read_shadow;
277 natural_width cr4_read_shadow;
278 natural_width cr3_target_value0;
279 natural_width cr3_target_value1;
280 natural_width cr3_target_value2;
281 natural_width cr3_target_value3;
282 natural_width exit_qualification;
283 natural_width guest_linear_address;
284 natural_width guest_cr0;
285 natural_width guest_cr3;
286 natural_width guest_cr4;
287 natural_width guest_es_base;
288 natural_width guest_cs_base;
289 natural_width guest_ss_base;
290 natural_width guest_ds_base;
291 natural_width guest_fs_base;
292 natural_width guest_gs_base;
293 natural_width guest_ldtr_base;
294 natural_width guest_tr_base;
295 natural_width guest_gdtr_base;
296 natural_width guest_idtr_base;
297 natural_width guest_dr7;
298 natural_width guest_rsp;
299 natural_width guest_rip;
300 natural_width guest_rflags;
301 natural_width guest_pending_dbg_exceptions;
302 natural_width guest_sysenter_esp;
303 natural_width guest_sysenter_eip;
304 natural_width host_cr0;
305 natural_width host_cr3;
306 natural_width host_cr4;
307 natural_width host_fs_base;
308 natural_width host_gs_base;
309 natural_width host_tr_base;
310 natural_width host_gdtr_base;
311 natural_width host_idtr_base;
312 natural_width host_ia32_sysenter_esp;
313 natural_width host_ia32_sysenter_eip;
314 natural_width host_rsp;
315 natural_width host_rip;
316 natural_width paddingl[8]; /* room for future expansion */
317 u32 pin_based_vm_exec_control;
318 u32 cpu_based_vm_exec_control;
319 u32 exception_bitmap;
320 u32 page_fault_error_code_mask;
321 u32 page_fault_error_code_match;
322 u32 cr3_target_count;
323 u32 vm_exit_controls;
324 u32 vm_exit_msr_store_count;
325 u32 vm_exit_msr_load_count;
326 u32 vm_entry_controls;
327 u32 vm_entry_msr_load_count;
328 u32 vm_entry_intr_info_field;
329 u32 vm_entry_exception_error_code;
330 u32 vm_entry_instruction_len;
331 u32 tpr_threshold;
332 u32 secondary_vm_exec_control;
333 u32 vm_instruction_error;
334 u32 vm_exit_reason;
335 u32 vm_exit_intr_info;
336 u32 vm_exit_intr_error_code;
337 u32 idt_vectoring_info_field;
338 u32 idt_vectoring_error_code;
339 u32 vm_exit_instruction_len;
340 u32 vmx_instruction_info;
341 u32 guest_es_limit;
342 u32 guest_cs_limit;
343 u32 guest_ss_limit;
344 u32 guest_ds_limit;
345 u32 guest_fs_limit;
346 u32 guest_gs_limit;
347 u32 guest_ldtr_limit;
348 u32 guest_tr_limit;
349 u32 guest_gdtr_limit;
350 u32 guest_idtr_limit;
351 u32 guest_es_ar_bytes;
352 u32 guest_cs_ar_bytes;
353 u32 guest_ss_ar_bytes;
354 u32 guest_ds_ar_bytes;
355 u32 guest_fs_ar_bytes;
356 u32 guest_gs_ar_bytes;
357 u32 guest_ldtr_ar_bytes;
358 u32 guest_tr_ar_bytes;
359 u32 guest_interruptibility_info;
360 u32 guest_activity_state;
361 u32 guest_sysenter_cs;
362 u32 host_ia32_sysenter_cs;
363 u32 vmx_preemption_timer_value;
364 u32 padding32[7]; /* room for future expansion */
365 u16 virtual_processor_id;
366 u16 posted_intr_nv;
367 u16 guest_es_selector;
368 u16 guest_cs_selector;
369 u16 guest_ss_selector;
370 u16 guest_ds_selector;
371 u16 guest_fs_selector;
372 u16 guest_gs_selector;
373 u16 guest_ldtr_selector;
374 u16 guest_tr_selector;
375 u16 guest_intr_status;
376 u16 guest_pml_index;
377 u16 host_es_selector;
378 u16 host_cs_selector;
379 u16 host_ss_selector;
380 u16 host_ds_selector;
381 u16 host_fs_selector;
382 u16 host_gs_selector;
383 u16 host_tr_selector;
384 };
385
386 /*
387 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
388 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
389 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
390 */
391 #define VMCS12_REVISION 0x11e57ed0
392
393 /*
394 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
395 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
396 * current implementation, 4K are reserved to avoid future complications.
397 */
398 #define VMCS12_SIZE 0x1000
399
400 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
401 struct vmcs02_list {
402 struct list_head list;
403 gpa_t vmptr;
404 struct loaded_vmcs vmcs02;
405 };
406
407 /*
408 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
409 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
410 */
411 struct nested_vmx {
412 /* Has the level1 guest done vmxon? */
413 bool vmxon;
414 gpa_t vmxon_ptr;
415 bool pml_full;
416
417 /* The guest-physical address of the current VMCS L1 keeps for L2 */
418 gpa_t current_vmptr;
419 /*
420 * Cache of the guest's VMCS, existing outside of guest memory.
421 * Loaded from guest memory during VMPTRLD. Flushed to guest
422 * memory during VMCLEAR and VMPTRLD.
423 */
424 struct vmcs12 *cached_vmcs12;
425 /*
426 * Indicates if the shadow vmcs must be updated with the
427 * data hold by vmcs12
428 */
429 bool sync_shadow_vmcs;
430
431 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
432 struct list_head vmcs02_pool;
433 int vmcs02_num;
434 bool change_vmcs01_virtual_x2apic_mode;
435 /* L2 must run next, and mustn't decide to exit to L1. */
436 bool nested_run_pending;
437 /*
438 * Guest pages referred to in vmcs02 with host-physical pointers, so
439 * we must keep them pinned while L2 runs.
440 */
441 struct page *apic_access_page;
442 struct page *virtual_apic_page;
443 struct page *pi_desc_page;
444 struct pi_desc *pi_desc;
445 bool pi_pending;
446 u16 posted_intr_nv;
447
448 unsigned long *msr_bitmap;
449
450 struct hrtimer preemption_timer;
451 bool preemption_timer_expired;
452
453 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
454 u64 vmcs01_debugctl;
455
456 u16 vpid02;
457 u16 last_vpid;
458
459 /*
460 * We only store the "true" versions of the VMX capability MSRs. We
461 * generate the "non-true" versions by setting the must-be-1 bits
462 * according to the SDM.
463 */
464 u32 nested_vmx_procbased_ctls_low;
465 u32 nested_vmx_procbased_ctls_high;
466 u32 nested_vmx_secondary_ctls_low;
467 u32 nested_vmx_secondary_ctls_high;
468 u32 nested_vmx_pinbased_ctls_low;
469 u32 nested_vmx_pinbased_ctls_high;
470 u32 nested_vmx_exit_ctls_low;
471 u32 nested_vmx_exit_ctls_high;
472 u32 nested_vmx_entry_ctls_low;
473 u32 nested_vmx_entry_ctls_high;
474 u32 nested_vmx_misc_low;
475 u32 nested_vmx_misc_high;
476 u32 nested_vmx_ept_caps;
477 u32 nested_vmx_vpid_caps;
478 u64 nested_vmx_basic;
479 u64 nested_vmx_cr0_fixed0;
480 u64 nested_vmx_cr0_fixed1;
481 u64 nested_vmx_cr4_fixed0;
482 u64 nested_vmx_cr4_fixed1;
483 u64 nested_vmx_vmcs_enum;
484 };
485
486 #define POSTED_INTR_ON 0
487 #define POSTED_INTR_SN 1
488
489 /* Posted-Interrupt Descriptor */
490 struct pi_desc {
491 u32 pir[8]; /* Posted interrupt requested */
492 union {
493 struct {
494 /* bit 256 - Outstanding Notification */
495 u16 on : 1,
496 /* bit 257 - Suppress Notification */
497 sn : 1,
498 /* bit 271:258 - Reserved */
499 rsvd_1 : 14;
500 /* bit 279:272 - Notification Vector */
501 u8 nv;
502 /* bit 287:280 - Reserved */
503 u8 rsvd_2;
504 /* bit 319:288 - Notification Destination */
505 u32 ndst;
506 };
507 u64 control;
508 };
509 u32 rsvd[6];
510 } __aligned(64);
511
512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
513 {
514 return test_and_set_bit(POSTED_INTR_ON,
515 (unsigned long *)&pi_desc->control);
516 }
517
518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
519 {
520 return test_and_clear_bit(POSTED_INTR_ON,
521 (unsigned long *)&pi_desc->control);
522 }
523
524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
525 {
526 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
527 }
528
529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
530 {
531 return clear_bit(POSTED_INTR_SN,
532 (unsigned long *)&pi_desc->control);
533 }
534
535 static inline void pi_set_sn(struct pi_desc *pi_desc)
536 {
537 return set_bit(POSTED_INTR_SN,
538 (unsigned long *)&pi_desc->control);
539 }
540
541 static inline void pi_clear_on(struct pi_desc *pi_desc)
542 {
543 clear_bit(POSTED_INTR_ON,
544 (unsigned long *)&pi_desc->control);
545 }
546
547 static inline int pi_test_on(struct pi_desc *pi_desc)
548 {
549 return test_bit(POSTED_INTR_ON,
550 (unsigned long *)&pi_desc->control);
551 }
552
553 static inline int pi_test_sn(struct pi_desc *pi_desc)
554 {
555 return test_bit(POSTED_INTR_SN,
556 (unsigned long *)&pi_desc->control);
557 }
558
559 struct vcpu_vmx {
560 struct kvm_vcpu vcpu;
561 unsigned long host_rsp;
562 u8 fail;
563 u32 exit_intr_info;
564 u32 idt_vectoring_info;
565 ulong rflags;
566 struct shared_msr_entry *guest_msrs;
567 int nmsrs;
568 int save_nmsrs;
569 unsigned long host_idt_base;
570 #ifdef CONFIG_X86_64
571 u64 msr_host_kernel_gs_base;
572 u64 msr_guest_kernel_gs_base;
573 #endif
574 u32 vm_entry_controls_shadow;
575 u32 vm_exit_controls_shadow;
576 /*
577 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
578 * non-nested (L1) guest, it always points to vmcs01. For a nested
579 * guest (L2), it points to a different VMCS.
580 */
581 struct loaded_vmcs vmcs01;
582 struct loaded_vmcs *loaded_vmcs;
583 bool __launched; /* temporary, used in vmx_vcpu_run */
584 struct msr_autoload {
585 unsigned nr;
586 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
587 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
588 } msr_autoload;
589 struct {
590 int loaded;
591 u16 fs_sel, gs_sel, ldt_sel;
592 #ifdef CONFIG_X86_64
593 u16 ds_sel, es_sel;
594 #endif
595 int gs_ldt_reload_needed;
596 int fs_reload_needed;
597 u64 msr_host_bndcfgs;
598 unsigned long vmcs_host_cr3; /* May not match real cr3 */
599 unsigned long vmcs_host_cr4; /* May not match real cr4 */
600 } host_state;
601 struct {
602 int vm86_active;
603 ulong save_rflags;
604 struct kvm_segment segs[8];
605 } rmode;
606 struct {
607 u32 bitmask; /* 4 bits per segment (1 bit per field) */
608 struct kvm_save_segment {
609 u16 selector;
610 unsigned long base;
611 u32 limit;
612 u32 ar;
613 } seg[8];
614 } segment_cache;
615 int vpid;
616 bool emulation_required;
617
618 u32 exit_reason;
619
620 /* Posted interrupt descriptor */
621 struct pi_desc pi_desc;
622
623 /* Support for a guest hypervisor (nested VMX) */
624 struct nested_vmx nested;
625
626 /* Dynamic PLE window. */
627 int ple_window;
628 bool ple_window_dirty;
629
630 /* Support for PML */
631 #define PML_ENTITY_NUM 512
632 struct page *pml_pg;
633
634 /* apic deadline value in host tsc */
635 u64 hv_deadline_tsc;
636
637 u64 current_tsc_ratio;
638
639 u32 host_pkru;
640
641 /*
642 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
643 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
644 * in msr_ia32_feature_control_valid_bits.
645 */
646 u64 msr_ia32_feature_control;
647 u64 msr_ia32_feature_control_valid_bits;
648 };
649
650 enum segment_cache_field {
651 SEG_FIELD_SEL = 0,
652 SEG_FIELD_BASE = 1,
653 SEG_FIELD_LIMIT = 2,
654 SEG_FIELD_AR = 3,
655
656 SEG_FIELD_NR = 4
657 };
658
659 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
660 {
661 return container_of(vcpu, struct vcpu_vmx, vcpu);
662 }
663
664 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
665 {
666 return &(to_vmx(vcpu)->pi_desc);
667 }
668
669 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
670 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
671 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
672 [number##_HIGH] = VMCS12_OFFSET(name)+4
673
674
675 static unsigned long shadow_read_only_fields[] = {
676 /*
677 * We do NOT shadow fields that are modified when L0
678 * traps and emulates any vmx instruction (e.g. VMPTRLD,
679 * VMXON...) executed by L1.
680 * For example, VM_INSTRUCTION_ERROR is read
681 * by L1 if a vmx instruction fails (part of the error path).
682 * Note the code assumes this logic. If for some reason
683 * we start shadowing these fields then we need to
684 * force a shadow sync when L0 emulates vmx instructions
685 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
686 * by nested_vmx_failValid)
687 */
688 VM_EXIT_REASON,
689 VM_EXIT_INTR_INFO,
690 VM_EXIT_INSTRUCTION_LEN,
691 IDT_VECTORING_INFO_FIELD,
692 IDT_VECTORING_ERROR_CODE,
693 VM_EXIT_INTR_ERROR_CODE,
694 EXIT_QUALIFICATION,
695 GUEST_LINEAR_ADDRESS,
696 GUEST_PHYSICAL_ADDRESS
697 };
698 static int max_shadow_read_only_fields =
699 ARRAY_SIZE(shadow_read_only_fields);
700
701 static unsigned long shadow_read_write_fields[] = {
702 TPR_THRESHOLD,
703 GUEST_RIP,
704 GUEST_RSP,
705 GUEST_CR0,
706 GUEST_CR3,
707 GUEST_CR4,
708 GUEST_INTERRUPTIBILITY_INFO,
709 GUEST_RFLAGS,
710 GUEST_CS_SELECTOR,
711 GUEST_CS_AR_BYTES,
712 GUEST_CS_LIMIT,
713 GUEST_CS_BASE,
714 GUEST_ES_BASE,
715 GUEST_BNDCFGS,
716 CR0_GUEST_HOST_MASK,
717 CR0_READ_SHADOW,
718 CR4_READ_SHADOW,
719 TSC_OFFSET,
720 EXCEPTION_BITMAP,
721 CPU_BASED_VM_EXEC_CONTROL,
722 VM_ENTRY_EXCEPTION_ERROR_CODE,
723 VM_ENTRY_INTR_INFO_FIELD,
724 VM_ENTRY_INSTRUCTION_LEN,
725 VM_ENTRY_EXCEPTION_ERROR_CODE,
726 HOST_FS_BASE,
727 HOST_GS_BASE,
728 HOST_FS_SELECTOR,
729 HOST_GS_SELECTOR
730 };
731 static int max_shadow_read_write_fields =
732 ARRAY_SIZE(shadow_read_write_fields);
733
734 static const unsigned short vmcs_field_to_offset_table[] = {
735 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
736 FIELD(POSTED_INTR_NV, posted_intr_nv),
737 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
738 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
739 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
740 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
741 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
742 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
743 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
744 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
745 FIELD(GUEST_INTR_STATUS, guest_intr_status),
746 FIELD(GUEST_PML_INDEX, guest_pml_index),
747 FIELD(HOST_ES_SELECTOR, host_es_selector),
748 FIELD(HOST_CS_SELECTOR, host_cs_selector),
749 FIELD(HOST_SS_SELECTOR, host_ss_selector),
750 FIELD(HOST_DS_SELECTOR, host_ds_selector),
751 FIELD(HOST_FS_SELECTOR, host_fs_selector),
752 FIELD(HOST_GS_SELECTOR, host_gs_selector),
753 FIELD(HOST_TR_SELECTOR, host_tr_selector),
754 FIELD64(IO_BITMAP_A, io_bitmap_a),
755 FIELD64(IO_BITMAP_B, io_bitmap_b),
756 FIELD64(MSR_BITMAP, msr_bitmap),
757 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
758 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
759 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
760 FIELD64(TSC_OFFSET, tsc_offset),
761 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
762 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
763 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
764 FIELD64(EPT_POINTER, ept_pointer),
765 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
766 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
767 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
768 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
769 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
770 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
771 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
772 FIELD64(PML_ADDRESS, pml_address),
773 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
774 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
775 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
776 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
777 FIELD64(GUEST_PDPTR0, guest_pdptr0),
778 FIELD64(GUEST_PDPTR1, guest_pdptr1),
779 FIELD64(GUEST_PDPTR2, guest_pdptr2),
780 FIELD64(GUEST_PDPTR3, guest_pdptr3),
781 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
782 FIELD64(HOST_IA32_PAT, host_ia32_pat),
783 FIELD64(HOST_IA32_EFER, host_ia32_efer),
784 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
785 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
786 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
787 FIELD(EXCEPTION_BITMAP, exception_bitmap),
788 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
789 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
790 FIELD(CR3_TARGET_COUNT, cr3_target_count),
791 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
792 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
793 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
794 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
795 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
796 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
797 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
798 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
799 FIELD(TPR_THRESHOLD, tpr_threshold),
800 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
801 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
802 FIELD(VM_EXIT_REASON, vm_exit_reason),
803 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
804 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
805 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
806 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
807 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
808 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
809 FIELD(GUEST_ES_LIMIT, guest_es_limit),
810 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
811 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
812 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
813 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
814 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
815 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
816 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
817 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
818 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
819 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
820 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
821 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
822 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
823 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
824 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
825 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
826 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
827 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
828 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
829 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
830 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
831 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
832 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
833 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
834 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
835 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
836 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
837 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
838 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
839 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
840 FIELD(EXIT_QUALIFICATION, exit_qualification),
841 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
842 FIELD(GUEST_CR0, guest_cr0),
843 FIELD(GUEST_CR3, guest_cr3),
844 FIELD(GUEST_CR4, guest_cr4),
845 FIELD(GUEST_ES_BASE, guest_es_base),
846 FIELD(GUEST_CS_BASE, guest_cs_base),
847 FIELD(GUEST_SS_BASE, guest_ss_base),
848 FIELD(GUEST_DS_BASE, guest_ds_base),
849 FIELD(GUEST_FS_BASE, guest_fs_base),
850 FIELD(GUEST_GS_BASE, guest_gs_base),
851 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
852 FIELD(GUEST_TR_BASE, guest_tr_base),
853 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
854 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
855 FIELD(GUEST_DR7, guest_dr7),
856 FIELD(GUEST_RSP, guest_rsp),
857 FIELD(GUEST_RIP, guest_rip),
858 FIELD(GUEST_RFLAGS, guest_rflags),
859 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
860 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
861 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
862 FIELD(HOST_CR0, host_cr0),
863 FIELD(HOST_CR3, host_cr3),
864 FIELD(HOST_CR4, host_cr4),
865 FIELD(HOST_FS_BASE, host_fs_base),
866 FIELD(HOST_GS_BASE, host_gs_base),
867 FIELD(HOST_TR_BASE, host_tr_base),
868 FIELD(HOST_GDTR_BASE, host_gdtr_base),
869 FIELD(HOST_IDTR_BASE, host_idtr_base),
870 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
871 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
872 FIELD(HOST_RSP, host_rsp),
873 FIELD(HOST_RIP, host_rip),
874 };
875
876 static inline short vmcs_field_to_offset(unsigned long field)
877 {
878 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
879
880 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
881 vmcs_field_to_offset_table[field] == 0)
882 return -ENOENT;
883
884 return vmcs_field_to_offset_table[field];
885 }
886
887 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
888 {
889 return to_vmx(vcpu)->nested.cached_vmcs12;
890 }
891
892 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
893 {
894 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
895 if (is_error_page(page))
896 return NULL;
897
898 return page;
899 }
900
901 static void nested_release_page(struct page *page)
902 {
903 kvm_release_page_dirty(page);
904 }
905
906 static void nested_release_page_clean(struct page *page)
907 {
908 kvm_release_page_clean(page);
909 }
910
911 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
912 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
913 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
914 static bool vmx_xsaves_supported(void);
915 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
916 static void vmx_set_segment(struct kvm_vcpu *vcpu,
917 struct kvm_segment *var, int seg);
918 static void vmx_get_segment(struct kvm_vcpu *vcpu,
919 struct kvm_segment *var, int seg);
920 static bool guest_state_valid(struct kvm_vcpu *vcpu);
921 static u32 vmx_segment_access_rights(struct kvm_segment *var);
922 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
923 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
924 static int alloc_identity_pagetable(struct kvm *kvm);
925 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
926 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
927 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
928 u16 error_code);
929
930 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
931 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
932 /*
933 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
934 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
935 */
936 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
937
938 /*
939 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
940 * can find which vCPU should be waken up.
941 */
942 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
943 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
944
945 enum {
946 VMX_IO_BITMAP_A,
947 VMX_IO_BITMAP_B,
948 VMX_MSR_BITMAP_LEGACY,
949 VMX_MSR_BITMAP_LONGMODE,
950 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
951 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
952 VMX_MSR_BITMAP_LEGACY_X2APIC,
953 VMX_MSR_BITMAP_LONGMODE_X2APIC,
954 VMX_VMREAD_BITMAP,
955 VMX_VMWRITE_BITMAP,
956 VMX_BITMAP_NR
957 };
958
959 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
960
961 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
962 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
963 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
964 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
965 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
966 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
967 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
968 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
969 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
970 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
971
972 static bool cpu_has_load_ia32_efer;
973 static bool cpu_has_load_perf_global_ctrl;
974
975 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
976 static DEFINE_SPINLOCK(vmx_vpid_lock);
977
978 static struct vmcs_config {
979 int size;
980 int order;
981 u32 basic_cap;
982 u32 revision_id;
983 u32 pin_based_exec_ctrl;
984 u32 cpu_based_exec_ctrl;
985 u32 cpu_based_2nd_exec_ctrl;
986 u32 vmexit_ctrl;
987 u32 vmentry_ctrl;
988 } vmcs_config;
989
990 static struct vmx_capability {
991 u32 ept;
992 u32 vpid;
993 } vmx_capability;
994
995 #define VMX_SEGMENT_FIELD(seg) \
996 [VCPU_SREG_##seg] = { \
997 .selector = GUEST_##seg##_SELECTOR, \
998 .base = GUEST_##seg##_BASE, \
999 .limit = GUEST_##seg##_LIMIT, \
1000 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1001 }
1002
1003 static const struct kvm_vmx_segment_field {
1004 unsigned selector;
1005 unsigned base;
1006 unsigned limit;
1007 unsigned ar_bytes;
1008 } kvm_vmx_segment_fields[] = {
1009 VMX_SEGMENT_FIELD(CS),
1010 VMX_SEGMENT_FIELD(DS),
1011 VMX_SEGMENT_FIELD(ES),
1012 VMX_SEGMENT_FIELD(FS),
1013 VMX_SEGMENT_FIELD(GS),
1014 VMX_SEGMENT_FIELD(SS),
1015 VMX_SEGMENT_FIELD(TR),
1016 VMX_SEGMENT_FIELD(LDTR),
1017 };
1018
1019 static u64 host_efer;
1020
1021 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1022
1023 /*
1024 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1025 * away by decrementing the array size.
1026 */
1027 static const u32 vmx_msr_index[] = {
1028 #ifdef CONFIG_X86_64
1029 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1030 #endif
1031 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1032 };
1033
1034 static inline bool is_exception_n(u32 intr_info, u8 vector)
1035 {
1036 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1037 INTR_INFO_VALID_MASK)) ==
1038 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1039 }
1040
1041 static inline bool is_debug(u32 intr_info)
1042 {
1043 return is_exception_n(intr_info, DB_VECTOR);
1044 }
1045
1046 static inline bool is_breakpoint(u32 intr_info)
1047 {
1048 return is_exception_n(intr_info, BP_VECTOR);
1049 }
1050
1051 static inline bool is_page_fault(u32 intr_info)
1052 {
1053 return is_exception_n(intr_info, PF_VECTOR);
1054 }
1055
1056 static inline bool is_no_device(u32 intr_info)
1057 {
1058 return is_exception_n(intr_info, NM_VECTOR);
1059 }
1060
1061 static inline bool is_invalid_opcode(u32 intr_info)
1062 {
1063 return is_exception_n(intr_info, UD_VECTOR);
1064 }
1065
1066 static inline bool is_external_interrupt(u32 intr_info)
1067 {
1068 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1069 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1070 }
1071
1072 static inline bool is_machine_check(u32 intr_info)
1073 {
1074 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1075 INTR_INFO_VALID_MASK)) ==
1076 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1077 }
1078
1079 static inline bool cpu_has_vmx_msr_bitmap(void)
1080 {
1081 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1082 }
1083
1084 static inline bool cpu_has_vmx_tpr_shadow(void)
1085 {
1086 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1087 }
1088
1089 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1090 {
1091 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1092 }
1093
1094 static inline bool cpu_has_secondary_exec_ctrls(void)
1095 {
1096 return vmcs_config.cpu_based_exec_ctrl &
1097 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1098 }
1099
1100 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1101 {
1102 return vmcs_config.cpu_based_2nd_exec_ctrl &
1103 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1104 }
1105
1106 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1107 {
1108 return vmcs_config.cpu_based_2nd_exec_ctrl &
1109 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1110 }
1111
1112 static inline bool cpu_has_vmx_apic_register_virt(void)
1113 {
1114 return vmcs_config.cpu_based_2nd_exec_ctrl &
1115 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1116 }
1117
1118 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1119 {
1120 return vmcs_config.cpu_based_2nd_exec_ctrl &
1121 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1122 }
1123
1124 /*
1125 * Comment's format: document - errata name - stepping - processor name.
1126 * Refer from
1127 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1128 */
1129 static u32 vmx_preemption_cpu_tfms[] = {
1130 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1131 0x000206E6,
1132 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1133 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1134 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1135 0x00020652,
1136 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 0x00020655,
1138 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1139 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1140 /*
1141 * 320767.pdf - AAP86 - B1 -
1142 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1143 */
1144 0x000106E5,
1145 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1146 0x000106A0,
1147 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1148 0x000106A1,
1149 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1150 0x000106A4,
1151 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1152 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1153 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1154 0x000106A5,
1155 };
1156
1157 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1158 {
1159 u32 eax = cpuid_eax(0x00000001), i;
1160
1161 /* Clear the reserved bits */
1162 eax &= ~(0x3U << 14 | 0xfU << 28);
1163 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1164 if (eax == vmx_preemption_cpu_tfms[i])
1165 return true;
1166
1167 return false;
1168 }
1169
1170 static inline bool cpu_has_vmx_preemption_timer(void)
1171 {
1172 return vmcs_config.pin_based_exec_ctrl &
1173 PIN_BASED_VMX_PREEMPTION_TIMER;
1174 }
1175
1176 static inline bool cpu_has_vmx_posted_intr(void)
1177 {
1178 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1179 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1180 }
1181
1182 static inline bool cpu_has_vmx_apicv(void)
1183 {
1184 return cpu_has_vmx_apic_register_virt() &&
1185 cpu_has_vmx_virtual_intr_delivery() &&
1186 cpu_has_vmx_posted_intr();
1187 }
1188
1189 static inline bool cpu_has_vmx_flexpriority(void)
1190 {
1191 return cpu_has_vmx_tpr_shadow() &&
1192 cpu_has_vmx_virtualize_apic_accesses();
1193 }
1194
1195 static inline bool cpu_has_vmx_ept_execute_only(void)
1196 {
1197 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1198 }
1199
1200 static inline bool cpu_has_vmx_ept_2m_page(void)
1201 {
1202 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1203 }
1204
1205 static inline bool cpu_has_vmx_ept_1g_page(void)
1206 {
1207 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1208 }
1209
1210 static inline bool cpu_has_vmx_ept_4levels(void)
1211 {
1212 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1213 }
1214
1215 static inline bool cpu_has_vmx_ept_ad_bits(void)
1216 {
1217 return vmx_capability.ept & VMX_EPT_AD_BIT;
1218 }
1219
1220 static inline bool cpu_has_vmx_invept_context(void)
1221 {
1222 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1223 }
1224
1225 static inline bool cpu_has_vmx_invept_global(void)
1226 {
1227 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1228 }
1229
1230 static inline bool cpu_has_vmx_invvpid_single(void)
1231 {
1232 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1233 }
1234
1235 static inline bool cpu_has_vmx_invvpid_global(void)
1236 {
1237 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1238 }
1239
1240 static inline bool cpu_has_vmx_invvpid(void)
1241 {
1242 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1243 }
1244
1245 static inline bool cpu_has_vmx_ept(void)
1246 {
1247 return vmcs_config.cpu_based_2nd_exec_ctrl &
1248 SECONDARY_EXEC_ENABLE_EPT;
1249 }
1250
1251 static inline bool cpu_has_vmx_unrestricted_guest(void)
1252 {
1253 return vmcs_config.cpu_based_2nd_exec_ctrl &
1254 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1255 }
1256
1257 static inline bool cpu_has_vmx_ple(void)
1258 {
1259 return vmcs_config.cpu_based_2nd_exec_ctrl &
1260 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1261 }
1262
1263 static inline bool cpu_has_vmx_basic_inout(void)
1264 {
1265 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1266 }
1267
1268 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1269 {
1270 return flexpriority_enabled && lapic_in_kernel(vcpu);
1271 }
1272
1273 static inline bool cpu_has_vmx_vpid(void)
1274 {
1275 return vmcs_config.cpu_based_2nd_exec_ctrl &
1276 SECONDARY_EXEC_ENABLE_VPID;
1277 }
1278
1279 static inline bool cpu_has_vmx_rdtscp(void)
1280 {
1281 return vmcs_config.cpu_based_2nd_exec_ctrl &
1282 SECONDARY_EXEC_RDTSCP;
1283 }
1284
1285 static inline bool cpu_has_vmx_invpcid(void)
1286 {
1287 return vmcs_config.cpu_based_2nd_exec_ctrl &
1288 SECONDARY_EXEC_ENABLE_INVPCID;
1289 }
1290
1291 static inline bool cpu_has_vmx_wbinvd_exit(void)
1292 {
1293 return vmcs_config.cpu_based_2nd_exec_ctrl &
1294 SECONDARY_EXEC_WBINVD_EXITING;
1295 }
1296
1297 static inline bool cpu_has_vmx_shadow_vmcs(void)
1298 {
1299 u64 vmx_msr;
1300 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1301 /* check if the cpu supports writing r/o exit information fields */
1302 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1303 return false;
1304
1305 return vmcs_config.cpu_based_2nd_exec_ctrl &
1306 SECONDARY_EXEC_SHADOW_VMCS;
1307 }
1308
1309 static inline bool cpu_has_vmx_pml(void)
1310 {
1311 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1312 }
1313
1314 static inline bool cpu_has_vmx_tsc_scaling(void)
1315 {
1316 return vmcs_config.cpu_based_2nd_exec_ctrl &
1317 SECONDARY_EXEC_TSC_SCALING;
1318 }
1319
1320 static inline bool report_flexpriority(void)
1321 {
1322 return flexpriority_enabled;
1323 }
1324
1325 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1326 {
1327 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1328 }
1329
1330 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1331 {
1332 return vmcs12->cpu_based_vm_exec_control & bit;
1333 }
1334
1335 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1336 {
1337 return (vmcs12->cpu_based_vm_exec_control &
1338 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1339 (vmcs12->secondary_vm_exec_control & bit);
1340 }
1341
1342 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1343 {
1344 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1345 }
1346
1347 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1348 {
1349 return vmcs12->pin_based_vm_exec_control &
1350 PIN_BASED_VMX_PREEMPTION_TIMER;
1351 }
1352
1353 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1354 {
1355 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1356 }
1357
1358 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1359 {
1360 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1361 vmx_xsaves_supported();
1362 }
1363
1364 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1365 {
1366 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1367 }
1368
1369 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1370 {
1371 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1372 }
1373
1374 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1375 {
1376 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1377 }
1378
1379 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1380 {
1381 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1382 }
1383
1384 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1385 {
1386 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1387 }
1388
1389 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1390 {
1391 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1392 }
1393
1394 static inline bool is_nmi(u32 intr_info)
1395 {
1396 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1397 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1398 }
1399
1400 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1401 u32 exit_intr_info,
1402 unsigned long exit_qualification);
1403 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1404 struct vmcs12 *vmcs12,
1405 u32 reason, unsigned long qualification);
1406
1407 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1408 {
1409 int i;
1410
1411 for (i = 0; i < vmx->nmsrs; ++i)
1412 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1413 return i;
1414 return -1;
1415 }
1416
1417 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1418 {
1419 struct {
1420 u64 vpid : 16;
1421 u64 rsvd : 48;
1422 u64 gva;
1423 } operand = { vpid, 0, gva };
1424
1425 asm volatile (__ex(ASM_VMX_INVVPID)
1426 /* CF==1 or ZF==1 --> rc = -1 */
1427 "; ja 1f ; ud2 ; 1:"
1428 : : "a"(&operand), "c"(ext) : "cc", "memory");
1429 }
1430
1431 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1432 {
1433 struct {
1434 u64 eptp, gpa;
1435 } operand = {eptp, gpa};
1436
1437 asm volatile (__ex(ASM_VMX_INVEPT)
1438 /* CF==1 or ZF==1 --> rc = -1 */
1439 "; ja 1f ; ud2 ; 1:\n"
1440 : : "a" (&operand), "c" (ext) : "cc", "memory");
1441 }
1442
1443 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1444 {
1445 int i;
1446
1447 i = __find_msr_index(vmx, msr);
1448 if (i >= 0)
1449 return &vmx->guest_msrs[i];
1450 return NULL;
1451 }
1452
1453 static void vmcs_clear(struct vmcs *vmcs)
1454 {
1455 u64 phys_addr = __pa(vmcs);
1456 u8 error;
1457
1458 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1459 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1460 : "cc", "memory");
1461 if (error)
1462 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1463 vmcs, phys_addr);
1464 }
1465
1466 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1467 {
1468 vmcs_clear(loaded_vmcs->vmcs);
1469 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1470 vmcs_clear(loaded_vmcs->shadow_vmcs);
1471 loaded_vmcs->cpu = -1;
1472 loaded_vmcs->launched = 0;
1473 }
1474
1475 static void vmcs_load(struct vmcs *vmcs)
1476 {
1477 u64 phys_addr = __pa(vmcs);
1478 u8 error;
1479
1480 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1481 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1482 : "cc", "memory");
1483 if (error)
1484 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1485 vmcs, phys_addr);
1486 }
1487
1488 #ifdef CONFIG_KEXEC_CORE
1489 /*
1490 * This bitmap is used to indicate whether the vmclear
1491 * operation is enabled on all cpus. All disabled by
1492 * default.
1493 */
1494 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1495
1496 static inline void crash_enable_local_vmclear(int cpu)
1497 {
1498 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1499 }
1500
1501 static inline void crash_disable_local_vmclear(int cpu)
1502 {
1503 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1504 }
1505
1506 static inline int crash_local_vmclear_enabled(int cpu)
1507 {
1508 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1509 }
1510
1511 static void crash_vmclear_local_loaded_vmcss(void)
1512 {
1513 int cpu = raw_smp_processor_id();
1514 struct loaded_vmcs *v;
1515
1516 if (!crash_local_vmclear_enabled(cpu))
1517 return;
1518
1519 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1520 loaded_vmcss_on_cpu_link)
1521 vmcs_clear(v->vmcs);
1522 }
1523 #else
1524 static inline void crash_enable_local_vmclear(int cpu) { }
1525 static inline void crash_disable_local_vmclear(int cpu) { }
1526 #endif /* CONFIG_KEXEC_CORE */
1527
1528 static void __loaded_vmcs_clear(void *arg)
1529 {
1530 struct loaded_vmcs *loaded_vmcs = arg;
1531 int cpu = raw_smp_processor_id();
1532
1533 if (loaded_vmcs->cpu != cpu)
1534 return; /* vcpu migration can race with cpu offline */
1535 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1536 per_cpu(current_vmcs, cpu) = NULL;
1537 crash_disable_local_vmclear(cpu);
1538 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1539
1540 /*
1541 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1542 * is before setting loaded_vmcs->vcpu to -1 which is done in
1543 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1544 * then adds the vmcs into percpu list before it is deleted.
1545 */
1546 smp_wmb();
1547
1548 loaded_vmcs_init(loaded_vmcs);
1549 crash_enable_local_vmclear(cpu);
1550 }
1551
1552 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1553 {
1554 int cpu = loaded_vmcs->cpu;
1555
1556 if (cpu != -1)
1557 smp_call_function_single(cpu,
1558 __loaded_vmcs_clear, loaded_vmcs, 1);
1559 }
1560
1561 static inline void vpid_sync_vcpu_single(int vpid)
1562 {
1563 if (vpid == 0)
1564 return;
1565
1566 if (cpu_has_vmx_invvpid_single())
1567 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1568 }
1569
1570 static inline void vpid_sync_vcpu_global(void)
1571 {
1572 if (cpu_has_vmx_invvpid_global())
1573 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1574 }
1575
1576 static inline void vpid_sync_context(int vpid)
1577 {
1578 if (cpu_has_vmx_invvpid_single())
1579 vpid_sync_vcpu_single(vpid);
1580 else
1581 vpid_sync_vcpu_global();
1582 }
1583
1584 static inline void ept_sync_global(void)
1585 {
1586 if (cpu_has_vmx_invept_global())
1587 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1588 }
1589
1590 static inline void ept_sync_context(u64 eptp)
1591 {
1592 if (enable_ept) {
1593 if (cpu_has_vmx_invept_context())
1594 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1595 else
1596 ept_sync_global();
1597 }
1598 }
1599
1600 static __always_inline void vmcs_check16(unsigned long field)
1601 {
1602 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1603 "16-bit accessor invalid for 64-bit field");
1604 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1605 "16-bit accessor invalid for 64-bit high field");
1606 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1607 "16-bit accessor invalid for 32-bit high field");
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1609 "16-bit accessor invalid for natural width field");
1610 }
1611
1612 static __always_inline void vmcs_check32(unsigned long field)
1613 {
1614 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1615 "32-bit accessor invalid for 16-bit field");
1616 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1617 "32-bit accessor invalid for natural width field");
1618 }
1619
1620 static __always_inline void vmcs_check64(unsigned long field)
1621 {
1622 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1623 "64-bit accessor invalid for 16-bit field");
1624 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1625 "64-bit accessor invalid for 64-bit high field");
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1627 "64-bit accessor invalid for 32-bit field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1629 "64-bit accessor invalid for natural width field");
1630 }
1631
1632 static __always_inline void vmcs_checkl(unsigned long field)
1633 {
1634 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1635 "Natural width accessor invalid for 16-bit field");
1636 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1637 "Natural width accessor invalid for 64-bit field");
1638 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1639 "Natural width accessor invalid for 64-bit high field");
1640 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1641 "Natural width accessor invalid for 32-bit field");
1642 }
1643
1644 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1645 {
1646 unsigned long value;
1647
1648 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1649 : "=a"(value) : "d"(field) : "cc");
1650 return value;
1651 }
1652
1653 static __always_inline u16 vmcs_read16(unsigned long field)
1654 {
1655 vmcs_check16(field);
1656 return __vmcs_readl(field);
1657 }
1658
1659 static __always_inline u32 vmcs_read32(unsigned long field)
1660 {
1661 vmcs_check32(field);
1662 return __vmcs_readl(field);
1663 }
1664
1665 static __always_inline u64 vmcs_read64(unsigned long field)
1666 {
1667 vmcs_check64(field);
1668 #ifdef CONFIG_X86_64
1669 return __vmcs_readl(field);
1670 #else
1671 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1672 #endif
1673 }
1674
1675 static __always_inline unsigned long vmcs_readl(unsigned long field)
1676 {
1677 vmcs_checkl(field);
1678 return __vmcs_readl(field);
1679 }
1680
1681 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1682 {
1683 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1684 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1685 dump_stack();
1686 }
1687
1688 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1689 {
1690 u8 error;
1691
1692 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1693 : "=q"(error) : "a"(value), "d"(field) : "cc");
1694 if (unlikely(error))
1695 vmwrite_error(field, value);
1696 }
1697
1698 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1699 {
1700 vmcs_check16(field);
1701 __vmcs_writel(field, value);
1702 }
1703
1704 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1705 {
1706 vmcs_check32(field);
1707 __vmcs_writel(field, value);
1708 }
1709
1710 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1711 {
1712 vmcs_check64(field);
1713 __vmcs_writel(field, value);
1714 #ifndef CONFIG_X86_64
1715 asm volatile ("");
1716 __vmcs_writel(field+1, value >> 32);
1717 #endif
1718 }
1719
1720 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1721 {
1722 vmcs_checkl(field);
1723 __vmcs_writel(field, value);
1724 }
1725
1726 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1727 {
1728 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1729 "vmcs_clear_bits does not support 64-bit fields");
1730 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1731 }
1732
1733 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1734 {
1735 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1736 "vmcs_set_bits does not support 64-bit fields");
1737 __vmcs_writel(field, __vmcs_readl(field) | mask);
1738 }
1739
1740 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1741 {
1742 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1743 }
1744
1745 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1746 {
1747 vmcs_write32(VM_ENTRY_CONTROLS, val);
1748 vmx->vm_entry_controls_shadow = val;
1749 }
1750
1751 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1752 {
1753 if (vmx->vm_entry_controls_shadow != val)
1754 vm_entry_controls_init(vmx, val);
1755 }
1756
1757 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1758 {
1759 return vmx->vm_entry_controls_shadow;
1760 }
1761
1762
1763 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1764 {
1765 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1766 }
1767
1768 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1769 {
1770 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1771 }
1772
1773 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1774 {
1775 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1776 }
1777
1778 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1779 {
1780 vmcs_write32(VM_EXIT_CONTROLS, val);
1781 vmx->vm_exit_controls_shadow = val;
1782 }
1783
1784 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1785 {
1786 if (vmx->vm_exit_controls_shadow != val)
1787 vm_exit_controls_init(vmx, val);
1788 }
1789
1790 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1791 {
1792 return vmx->vm_exit_controls_shadow;
1793 }
1794
1795
1796 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1797 {
1798 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1799 }
1800
1801 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1802 {
1803 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1804 }
1805
1806 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1807 {
1808 vmx->segment_cache.bitmask = 0;
1809 }
1810
1811 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1812 unsigned field)
1813 {
1814 bool ret;
1815 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1816
1817 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1818 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1819 vmx->segment_cache.bitmask = 0;
1820 }
1821 ret = vmx->segment_cache.bitmask & mask;
1822 vmx->segment_cache.bitmask |= mask;
1823 return ret;
1824 }
1825
1826 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1827 {
1828 u16 *p = &vmx->segment_cache.seg[seg].selector;
1829
1830 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1831 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1832 return *p;
1833 }
1834
1835 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1836 {
1837 ulong *p = &vmx->segment_cache.seg[seg].base;
1838
1839 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1840 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1841 return *p;
1842 }
1843
1844 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1845 {
1846 u32 *p = &vmx->segment_cache.seg[seg].limit;
1847
1848 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1849 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1850 return *p;
1851 }
1852
1853 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1854 {
1855 u32 *p = &vmx->segment_cache.seg[seg].ar;
1856
1857 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1858 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1859 return *p;
1860 }
1861
1862 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1863 {
1864 u32 eb;
1865
1866 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1867 (1u << DB_VECTOR) | (1u << AC_VECTOR);
1868 if ((vcpu->guest_debug &
1869 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1870 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1871 eb |= 1u << BP_VECTOR;
1872 if (to_vmx(vcpu)->rmode.vm86_active)
1873 eb = ~0;
1874 if (enable_ept)
1875 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1876
1877 /* When we are running a nested L2 guest and L1 specified for it a
1878 * certain exception bitmap, we must trap the same exceptions and pass
1879 * them to L1. When running L2, we will only handle the exceptions
1880 * specified above if L1 did not want them.
1881 */
1882 if (is_guest_mode(vcpu))
1883 eb |= get_vmcs12(vcpu)->exception_bitmap;
1884
1885 vmcs_write32(EXCEPTION_BITMAP, eb);
1886 }
1887
1888 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1889 unsigned long entry, unsigned long exit)
1890 {
1891 vm_entry_controls_clearbit(vmx, entry);
1892 vm_exit_controls_clearbit(vmx, exit);
1893 }
1894
1895 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1896 {
1897 unsigned i;
1898 struct msr_autoload *m = &vmx->msr_autoload;
1899
1900 switch (msr) {
1901 case MSR_EFER:
1902 if (cpu_has_load_ia32_efer) {
1903 clear_atomic_switch_msr_special(vmx,
1904 VM_ENTRY_LOAD_IA32_EFER,
1905 VM_EXIT_LOAD_IA32_EFER);
1906 return;
1907 }
1908 break;
1909 case MSR_CORE_PERF_GLOBAL_CTRL:
1910 if (cpu_has_load_perf_global_ctrl) {
1911 clear_atomic_switch_msr_special(vmx,
1912 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1913 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1914 return;
1915 }
1916 break;
1917 }
1918
1919 for (i = 0; i < m->nr; ++i)
1920 if (m->guest[i].index == msr)
1921 break;
1922
1923 if (i == m->nr)
1924 return;
1925 --m->nr;
1926 m->guest[i] = m->guest[m->nr];
1927 m->host[i] = m->host[m->nr];
1928 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1929 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1930 }
1931
1932 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1933 unsigned long entry, unsigned long exit,
1934 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1935 u64 guest_val, u64 host_val)
1936 {
1937 vmcs_write64(guest_val_vmcs, guest_val);
1938 vmcs_write64(host_val_vmcs, host_val);
1939 vm_entry_controls_setbit(vmx, entry);
1940 vm_exit_controls_setbit(vmx, exit);
1941 }
1942
1943 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1944 u64 guest_val, u64 host_val)
1945 {
1946 unsigned i;
1947 struct msr_autoload *m = &vmx->msr_autoload;
1948
1949 switch (msr) {
1950 case MSR_EFER:
1951 if (cpu_has_load_ia32_efer) {
1952 add_atomic_switch_msr_special(vmx,
1953 VM_ENTRY_LOAD_IA32_EFER,
1954 VM_EXIT_LOAD_IA32_EFER,
1955 GUEST_IA32_EFER,
1956 HOST_IA32_EFER,
1957 guest_val, host_val);
1958 return;
1959 }
1960 break;
1961 case MSR_CORE_PERF_GLOBAL_CTRL:
1962 if (cpu_has_load_perf_global_ctrl) {
1963 add_atomic_switch_msr_special(vmx,
1964 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1965 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1966 GUEST_IA32_PERF_GLOBAL_CTRL,
1967 HOST_IA32_PERF_GLOBAL_CTRL,
1968 guest_val, host_val);
1969 return;
1970 }
1971 break;
1972 case MSR_IA32_PEBS_ENABLE:
1973 /* PEBS needs a quiescent period after being disabled (to write
1974 * a record). Disabling PEBS through VMX MSR swapping doesn't
1975 * provide that period, so a CPU could write host's record into
1976 * guest's memory.
1977 */
1978 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1979 }
1980
1981 for (i = 0; i < m->nr; ++i)
1982 if (m->guest[i].index == msr)
1983 break;
1984
1985 if (i == NR_AUTOLOAD_MSRS) {
1986 printk_once(KERN_WARNING "Not enough msr switch entries. "
1987 "Can't add msr %x\n", msr);
1988 return;
1989 } else if (i == m->nr) {
1990 ++m->nr;
1991 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1992 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1993 }
1994
1995 m->guest[i].index = msr;
1996 m->guest[i].value = guest_val;
1997 m->host[i].index = msr;
1998 m->host[i].value = host_val;
1999 }
2000
2001 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2002 {
2003 u64 guest_efer = vmx->vcpu.arch.efer;
2004 u64 ignore_bits = 0;
2005
2006 if (!enable_ept) {
2007 /*
2008 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2009 * host CPUID is more efficient than testing guest CPUID
2010 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2011 */
2012 if (boot_cpu_has(X86_FEATURE_SMEP))
2013 guest_efer |= EFER_NX;
2014 else if (!(guest_efer & EFER_NX))
2015 ignore_bits |= EFER_NX;
2016 }
2017
2018 /*
2019 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2020 */
2021 ignore_bits |= EFER_SCE;
2022 #ifdef CONFIG_X86_64
2023 ignore_bits |= EFER_LMA | EFER_LME;
2024 /* SCE is meaningful only in long mode on Intel */
2025 if (guest_efer & EFER_LMA)
2026 ignore_bits &= ~(u64)EFER_SCE;
2027 #endif
2028
2029 clear_atomic_switch_msr(vmx, MSR_EFER);
2030
2031 /*
2032 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2033 * On CPUs that support "load IA32_EFER", always switch EFER
2034 * atomically, since it's faster than switching it manually.
2035 */
2036 if (cpu_has_load_ia32_efer ||
2037 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2038 if (!(guest_efer & EFER_LMA))
2039 guest_efer &= ~EFER_LME;
2040 if (guest_efer != host_efer)
2041 add_atomic_switch_msr(vmx, MSR_EFER,
2042 guest_efer, host_efer);
2043 return false;
2044 } else {
2045 guest_efer &= ~ignore_bits;
2046 guest_efer |= host_efer & ignore_bits;
2047
2048 vmx->guest_msrs[efer_offset].data = guest_efer;
2049 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2050
2051 return true;
2052 }
2053 }
2054
2055 #ifdef CONFIG_X86_32
2056 /*
2057 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2058 * VMCS rather than the segment table. KVM uses this helper to figure
2059 * out the current bases to poke them into the VMCS before entry.
2060 */
2061 static unsigned long segment_base(u16 selector)
2062 {
2063 struct desc_struct *table;
2064 unsigned long v;
2065
2066 if (!(selector & ~SEGMENT_RPL_MASK))
2067 return 0;
2068
2069 table = get_current_gdt_ro();
2070
2071 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2072 u16 ldt_selector = kvm_read_ldt();
2073
2074 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2075 return 0;
2076
2077 table = (struct desc_struct *)segment_base(ldt_selector);
2078 }
2079 v = get_desc_base(&table[selector >> 3]);
2080 return v;
2081 }
2082 #endif
2083
2084 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2085 {
2086 struct vcpu_vmx *vmx = to_vmx(vcpu);
2087 int i;
2088
2089 if (vmx->host_state.loaded)
2090 return;
2091
2092 vmx->host_state.loaded = 1;
2093 /*
2094 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2095 * allow segment selectors with cpl > 0 or ti == 1.
2096 */
2097 vmx->host_state.ldt_sel = kvm_read_ldt();
2098 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2099 savesegment(fs, vmx->host_state.fs_sel);
2100 if (!(vmx->host_state.fs_sel & 7)) {
2101 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2102 vmx->host_state.fs_reload_needed = 0;
2103 } else {
2104 vmcs_write16(HOST_FS_SELECTOR, 0);
2105 vmx->host_state.fs_reload_needed = 1;
2106 }
2107 savesegment(gs, vmx->host_state.gs_sel);
2108 if (!(vmx->host_state.gs_sel & 7))
2109 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2110 else {
2111 vmcs_write16(HOST_GS_SELECTOR, 0);
2112 vmx->host_state.gs_ldt_reload_needed = 1;
2113 }
2114
2115 #ifdef CONFIG_X86_64
2116 savesegment(ds, vmx->host_state.ds_sel);
2117 savesegment(es, vmx->host_state.es_sel);
2118 #endif
2119
2120 #ifdef CONFIG_X86_64
2121 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2122 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2123 #else
2124 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2125 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2126 #endif
2127
2128 #ifdef CONFIG_X86_64
2129 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2130 if (is_long_mode(&vmx->vcpu))
2131 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2132 #endif
2133 if (boot_cpu_has(X86_FEATURE_MPX))
2134 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2135 for (i = 0; i < vmx->save_nmsrs; ++i)
2136 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2137 vmx->guest_msrs[i].data,
2138 vmx->guest_msrs[i].mask);
2139 }
2140
2141 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2142 {
2143 if (!vmx->host_state.loaded)
2144 return;
2145
2146 ++vmx->vcpu.stat.host_state_reload;
2147 vmx->host_state.loaded = 0;
2148 #ifdef CONFIG_X86_64
2149 if (is_long_mode(&vmx->vcpu))
2150 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2151 #endif
2152 if (vmx->host_state.gs_ldt_reload_needed) {
2153 kvm_load_ldt(vmx->host_state.ldt_sel);
2154 #ifdef CONFIG_X86_64
2155 load_gs_index(vmx->host_state.gs_sel);
2156 #else
2157 loadsegment(gs, vmx->host_state.gs_sel);
2158 #endif
2159 }
2160 if (vmx->host_state.fs_reload_needed)
2161 loadsegment(fs, vmx->host_state.fs_sel);
2162 #ifdef CONFIG_X86_64
2163 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2164 loadsegment(ds, vmx->host_state.ds_sel);
2165 loadsegment(es, vmx->host_state.es_sel);
2166 }
2167 #endif
2168 invalidate_tss_limit();
2169 #ifdef CONFIG_X86_64
2170 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2171 #endif
2172 if (vmx->host_state.msr_host_bndcfgs)
2173 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2174 load_fixmap_gdt(raw_smp_processor_id());
2175 }
2176
2177 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2178 {
2179 preempt_disable();
2180 __vmx_load_host_state(vmx);
2181 preempt_enable();
2182 }
2183
2184 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2185 {
2186 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2187 struct pi_desc old, new;
2188 unsigned int dest;
2189
2190 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2191 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2192 !kvm_vcpu_apicv_active(vcpu))
2193 return;
2194
2195 do {
2196 old.control = new.control = pi_desc->control;
2197
2198 /*
2199 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2200 * are two possible cases:
2201 * 1. After running 'pre_block', context switch
2202 * happened. For this case, 'sn' was set in
2203 * vmx_vcpu_put(), so we need to clear it here.
2204 * 2. After running 'pre_block', we were blocked,
2205 * and woken up by some other guy. For this case,
2206 * we don't need to do anything, 'pi_post_block'
2207 * will do everything for us. However, we cannot
2208 * check whether it is case #1 or case #2 here
2209 * (maybe, not needed), so we also clear sn here,
2210 * I think it is not a big deal.
2211 */
2212 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2213 if (vcpu->cpu != cpu) {
2214 dest = cpu_physical_id(cpu);
2215
2216 if (x2apic_enabled())
2217 new.ndst = dest;
2218 else
2219 new.ndst = (dest << 8) & 0xFF00;
2220 }
2221
2222 /* set 'NV' to 'notification vector' */
2223 new.nv = POSTED_INTR_VECTOR;
2224 }
2225
2226 /* Allow posting non-urgent interrupts */
2227 new.sn = 0;
2228 } while (cmpxchg(&pi_desc->control, old.control,
2229 new.control) != old.control);
2230 }
2231
2232 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2233 {
2234 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2235 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2236 }
2237
2238 /*
2239 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2240 * vcpu mutex is already taken.
2241 */
2242 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2243 {
2244 struct vcpu_vmx *vmx = to_vmx(vcpu);
2245 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2246
2247 if (!already_loaded) {
2248 loaded_vmcs_clear(vmx->loaded_vmcs);
2249 local_irq_disable();
2250 crash_disable_local_vmclear(cpu);
2251
2252 /*
2253 * Read loaded_vmcs->cpu should be before fetching
2254 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2255 * See the comments in __loaded_vmcs_clear().
2256 */
2257 smp_rmb();
2258
2259 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2260 &per_cpu(loaded_vmcss_on_cpu, cpu));
2261 crash_enable_local_vmclear(cpu);
2262 local_irq_enable();
2263 }
2264
2265 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2266 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2267 vmcs_load(vmx->loaded_vmcs->vmcs);
2268 }
2269
2270 if (!already_loaded) {
2271 void *gdt = get_current_gdt_ro();
2272 unsigned long sysenter_esp;
2273
2274 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2275
2276 /*
2277 * Linux uses per-cpu TSS and GDT, so set these when switching
2278 * processors. See 22.2.4.
2279 */
2280 vmcs_writel(HOST_TR_BASE,
2281 (unsigned long)this_cpu_ptr(&cpu_tss));
2282 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
2283
2284 /*
2285 * VM exits change the host TR limit to 0x67 after a VM
2286 * exit. This is okay, since 0x67 covers everything except
2287 * the IO bitmap and have have code to handle the IO bitmap
2288 * being lost after a VM exit.
2289 */
2290 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2291
2292 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2293 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2294
2295 vmx->loaded_vmcs->cpu = cpu;
2296 }
2297
2298 /* Setup TSC multiplier */
2299 if (kvm_has_tsc_control &&
2300 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2301 decache_tsc_multiplier(vmx);
2302
2303 vmx_vcpu_pi_load(vcpu, cpu);
2304 vmx->host_pkru = read_pkru();
2305 }
2306
2307 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2308 {
2309 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2310
2311 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2312 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2313 !kvm_vcpu_apicv_active(vcpu))
2314 return;
2315
2316 /* Set SN when the vCPU is preempted */
2317 if (vcpu->preempted)
2318 pi_set_sn(pi_desc);
2319 }
2320
2321 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2322 {
2323 vmx_vcpu_pi_put(vcpu);
2324
2325 __vmx_load_host_state(to_vmx(vcpu));
2326 }
2327
2328 static bool emulation_required(struct kvm_vcpu *vcpu)
2329 {
2330 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2331 }
2332
2333 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2334
2335 /*
2336 * Return the cr0 value that a nested guest would read. This is a combination
2337 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2338 * its hypervisor (cr0_read_shadow).
2339 */
2340 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2341 {
2342 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2343 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2344 }
2345 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2346 {
2347 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2348 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2349 }
2350
2351 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2352 {
2353 unsigned long rflags, save_rflags;
2354
2355 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2356 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2357 rflags = vmcs_readl(GUEST_RFLAGS);
2358 if (to_vmx(vcpu)->rmode.vm86_active) {
2359 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2360 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2361 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2362 }
2363 to_vmx(vcpu)->rflags = rflags;
2364 }
2365 return to_vmx(vcpu)->rflags;
2366 }
2367
2368 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2369 {
2370 unsigned long old_rflags = vmx_get_rflags(vcpu);
2371
2372 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2373 to_vmx(vcpu)->rflags = rflags;
2374 if (to_vmx(vcpu)->rmode.vm86_active) {
2375 to_vmx(vcpu)->rmode.save_rflags = rflags;
2376 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2377 }
2378 vmcs_writel(GUEST_RFLAGS, rflags);
2379
2380 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2381 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2382 }
2383
2384 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2385 {
2386 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2387 int ret = 0;
2388
2389 if (interruptibility & GUEST_INTR_STATE_STI)
2390 ret |= KVM_X86_SHADOW_INT_STI;
2391 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2392 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2393
2394 return ret;
2395 }
2396
2397 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2398 {
2399 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2400 u32 interruptibility = interruptibility_old;
2401
2402 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2403
2404 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2405 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2406 else if (mask & KVM_X86_SHADOW_INT_STI)
2407 interruptibility |= GUEST_INTR_STATE_STI;
2408
2409 if ((interruptibility != interruptibility_old))
2410 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2411 }
2412
2413 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2414 {
2415 unsigned long rip;
2416
2417 rip = kvm_rip_read(vcpu);
2418 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2419 kvm_rip_write(vcpu, rip);
2420
2421 /* skipping an emulated instruction also counts */
2422 vmx_set_interrupt_shadow(vcpu, 0);
2423 }
2424
2425 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2426 unsigned long exit_qual)
2427 {
2428 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2429 unsigned int nr = vcpu->arch.exception.nr;
2430 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2431
2432 if (vcpu->arch.exception.has_error_code) {
2433 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2434 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2435 }
2436
2437 if (kvm_exception_is_soft(nr))
2438 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2439 else
2440 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2441
2442 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2443 vmx_get_nmi_mask(vcpu))
2444 intr_info |= INTR_INFO_UNBLOCK_NMI;
2445
2446 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2447 }
2448
2449 /*
2450 * KVM wants to inject page-faults which it got to the guest. This function
2451 * checks whether in a nested guest, we need to inject them to L1 or L2.
2452 */
2453 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu)
2454 {
2455 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2456 unsigned int nr = vcpu->arch.exception.nr;
2457
2458 if (nr == PF_VECTOR) {
2459 if (vcpu->arch.exception.nested_apf) {
2460 nested_vmx_inject_exception_vmexit(vcpu,
2461 vcpu->arch.apf.nested_apf_token);
2462 return 1;
2463 }
2464 /*
2465 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2466 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2467 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2468 * can be written only when inject_pending_event runs. This should be
2469 * conditional on a new capability---if the capability is disabled,
2470 * kvm_multiple_exception would write the ancillary information to
2471 * CR2 or DR6, for backwards ABI-compatibility.
2472 */
2473 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2474 vcpu->arch.exception.error_code)) {
2475 nested_vmx_inject_exception_vmexit(vcpu, vcpu->arch.cr2);
2476 return 1;
2477 }
2478 } else {
2479 unsigned long exit_qual = 0;
2480 if (nr == DB_VECTOR)
2481 exit_qual = vcpu->arch.dr6;
2482
2483 if (vmcs12->exception_bitmap & (1u << nr)) {
2484 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
2485 return 1;
2486 }
2487 }
2488
2489 return 0;
2490 }
2491
2492 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2493 {
2494 struct vcpu_vmx *vmx = to_vmx(vcpu);
2495 unsigned nr = vcpu->arch.exception.nr;
2496 bool has_error_code = vcpu->arch.exception.has_error_code;
2497 bool reinject = vcpu->arch.exception.reinject;
2498 u32 error_code = vcpu->arch.exception.error_code;
2499 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2500
2501 if (!reinject && is_guest_mode(vcpu) &&
2502 nested_vmx_check_exception(vcpu))
2503 return;
2504
2505 if (has_error_code) {
2506 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2507 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2508 }
2509
2510 if (vmx->rmode.vm86_active) {
2511 int inc_eip = 0;
2512 if (kvm_exception_is_soft(nr))
2513 inc_eip = vcpu->arch.event_exit_inst_len;
2514 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2515 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2516 return;
2517 }
2518
2519 if (kvm_exception_is_soft(nr)) {
2520 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2521 vmx->vcpu.arch.event_exit_inst_len);
2522 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2523 } else
2524 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2525
2526 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2527 }
2528
2529 static bool vmx_rdtscp_supported(void)
2530 {
2531 return cpu_has_vmx_rdtscp();
2532 }
2533
2534 static bool vmx_invpcid_supported(void)
2535 {
2536 return cpu_has_vmx_invpcid() && enable_ept;
2537 }
2538
2539 /*
2540 * Swap MSR entry in host/guest MSR entry array.
2541 */
2542 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2543 {
2544 struct shared_msr_entry tmp;
2545
2546 tmp = vmx->guest_msrs[to];
2547 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2548 vmx->guest_msrs[from] = tmp;
2549 }
2550
2551 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2552 {
2553 unsigned long *msr_bitmap;
2554
2555 if (is_guest_mode(vcpu))
2556 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2557 else if (cpu_has_secondary_exec_ctrls() &&
2558 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2559 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2560 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2561 if (is_long_mode(vcpu))
2562 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2563 else
2564 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2565 } else {
2566 if (is_long_mode(vcpu))
2567 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2568 else
2569 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2570 }
2571 } else {
2572 if (is_long_mode(vcpu))
2573 msr_bitmap = vmx_msr_bitmap_longmode;
2574 else
2575 msr_bitmap = vmx_msr_bitmap_legacy;
2576 }
2577
2578 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2579 }
2580
2581 /*
2582 * Set up the vmcs to automatically save and restore system
2583 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2584 * mode, as fiddling with msrs is very expensive.
2585 */
2586 static void setup_msrs(struct vcpu_vmx *vmx)
2587 {
2588 int save_nmsrs, index;
2589
2590 save_nmsrs = 0;
2591 #ifdef CONFIG_X86_64
2592 if (is_long_mode(&vmx->vcpu)) {
2593 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2594 if (index >= 0)
2595 move_msr_up(vmx, index, save_nmsrs++);
2596 index = __find_msr_index(vmx, MSR_LSTAR);
2597 if (index >= 0)
2598 move_msr_up(vmx, index, save_nmsrs++);
2599 index = __find_msr_index(vmx, MSR_CSTAR);
2600 if (index >= 0)
2601 move_msr_up(vmx, index, save_nmsrs++);
2602 index = __find_msr_index(vmx, MSR_TSC_AUX);
2603 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2604 move_msr_up(vmx, index, save_nmsrs++);
2605 /*
2606 * MSR_STAR is only needed on long mode guests, and only
2607 * if efer.sce is enabled.
2608 */
2609 index = __find_msr_index(vmx, MSR_STAR);
2610 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2611 move_msr_up(vmx, index, save_nmsrs++);
2612 }
2613 #endif
2614 index = __find_msr_index(vmx, MSR_EFER);
2615 if (index >= 0 && update_transition_efer(vmx, index))
2616 move_msr_up(vmx, index, save_nmsrs++);
2617
2618 vmx->save_nmsrs = save_nmsrs;
2619
2620 if (cpu_has_vmx_msr_bitmap())
2621 vmx_set_msr_bitmap(&vmx->vcpu);
2622 }
2623
2624 /*
2625 * reads and returns guest's timestamp counter "register"
2626 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2627 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2628 */
2629 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2630 {
2631 u64 host_tsc, tsc_offset;
2632
2633 host_tsc = rdtsc();
2634 tsc_offset = vmcs_read64(TSC_OFFSET);
2635 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2636 }
2637
2638 /*
2639 * writes 'offset' into guest's timestamp counter offset register
2640 */
2641 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2642 {
2643 if (is_guest_mode(vcpu)) {
2644 /*
2645 * We're here if L1 chose not to trap WRMSR to TSC. According
2646 * to the spec, this should set L1's TSC; The offset that L1
2647 * set for L2 remains unchanged, and still needs to be added
2648 * to the newly set TSC to get L2's TSC.
2649 */
2650 struct vmcs12 *vmcs12;
2651 /* recalculate vmcs02.TSC_OFFSET: */
2652 vmcs12 = get_vmcs12(vcpu);
2653 vmcs_write64(TSC_OFFSET, offset +
2654 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2655 vmcs12->tsc_offset : 0));
2656 } else {
2657 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2658 vmcs_read64(TSC_OFFSET), offset);
2659 vmcs_write64(TSC_OFFSET, offset);
2660 }
2661 }
2662
2663 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2664 {
2665 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2666 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2667 }
2668
2669 /*
2670 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2671 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2672 * all guests if the "nested" module option is off, and can also be disabled
2673 * for a single guest by disabling its VMX cpuid bit.
2674 */
2675 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2676 {
2677 return nested && guest_cpuid_has_vmx(vcpu);
2678 }
2679
2680 /*
2681 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2682 * returned for the various VMX controls MSRs when nested VMX is enabled.
2683 * The same values should also be used to verify that vmcs12 control fields are
2684 * valid during nested entry from L1 to L2.
2685 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2686 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2687 * bit in the high half is on if the corresponding bit in the control field
2688 * may be on. See also vmx_control_verify().
2689 */
2690 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2691 {
2692 /*
2693 * Note that as a general rule, the high half of the MSRs (bits in
2694 * the control fields which may be 1) should be initialized by the
2695 * intersection of the underlying hardware's MSR (i.e., features which
2696 * can be supported) and the list of features we want to expose -
2697 * because they are known to be properly supported in our code.
2698 * Also, usually, the low half of the MSRs (bits which must be 1) can
2699 * be set to 0, meaning that L1 may turn off any of these bits. The
2700 * reason is that if one of these bits is necessary, it will appear
2701 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2702 * fields of vmcs01 and vmcs02, will turn these bits off - and
2703 * nested_vmx_exit_reflected() will not pass related exits to L1.
2704 * These rules have exceptions below.
2705 */
2706
2707 /* pin-based controls */
2708 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2709 vmx->nested.nested_vmx_pinbased_ctls_low,
2710 vmx->nested.nested_vmx_pinbased_ctls_high);
2711 vmx->nested.nested_vmx_pinbased_ctls_low |=
2712 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2713 vmx->nested.nested_vmx_pinbased_ctls_high &=
2714 PIN_BASED_EXT_INTR_MASK |
2715 PIN_BASED_NMI_EXITING |
2716 PIN_BASED_VIRTUAL_NMIS;
2717 vmx->nested.nested_vmx_pinbased_ctls_high |=
2718 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2719 PIN_BASED_VMX_PREEMPTION_TIMER;
2720 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2721 vmx->nested.nested_vmx_pinbased_ctls_high |=
2722 PIN_BASED_POSTED_INTR;
2723
2724 /* exit controls */
2725 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2726 vmx->nested.nested_vmx_exit_ctls_low,
2727 vmx->nested.nested_vmx_exit_ctls_high);
2728 vmx->nested.nested_vmx_exit_ctls_low =
2729 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2730
2731 vmx->nested.nested_vmx_exit_ctls_high &=
2732 #ifdef CONFIG_X86_64
2733 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2734 #endif
2735 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2736 vmx->nested.nested_vmx_exit_ctls_high |=
2737 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2738 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2739 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2740
2741 if (kvm_mpx_supported())
2742 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2743
2744 /* We support free control of debug control saving. */
2745 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2746
2747 /* entry controls */
2748 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2749 vmx->nested.nested_vmx_entry_ctls_low,
2750 vmx->nested.nested_vmx_entry_ctls_high);
2751 vmx->nested.nested_vmx_entry_ctls_low =
2752 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2753 vmx->nested.nested_vmx_entry_ctls_high &=
2754 #ifdef CONFIG_X86_64
2755 VM_ENTRY_IA32E_MODE |
2756 #endif
2757 VM_ENTRY_LOAD_IA32_PAT;
2758 vmx->nested.nested_vmx_entry_ctls_high |=
2759 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2760 if (kvm_mpx_supported())
2761 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2762
2763 /* We support free control of debug control loading. */
2764 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2765
2766 /* cpu-based controls */
2767 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2768 vmx->nested.nested_vmx_procbased_ctls_low,
2769 vmx->nested.nested_vmx_procbased_ctls_high);
2770 vmx->nested.nested_vmx_procbased_ctls_low =
2771 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2772 vmx->nested.nested_vmx_procbased_ctls_high &=
2773 CPU_BASED_VIRTUAL_INTR_PENDING |
2774 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2775 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2776 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2777 CPU_BASED_CR3_STORE_EXITING |
2778 #ifdef CONFIG_X86_64
2779 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2780 #endif
2781 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2782 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2783 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2784 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2785 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2786 /*
2787 * We can allow some features even when not supported by the
2788 * hardware. For example, L1 can specify an MSR bitmap - and we
2789 * can use it to avoid exits to L1 - even when L0 runs L2
2790 * without MSR bitmaps.
2791 */
2792 vmx->nested.nested_vmx_procbased_ctls_high |=
2793 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2794 CPU_BASED_USE_MSR_BITMAPS;
2795
2796 /* We support free control of CR3 access interception. */
2797 vmx->nested.nested_vmx_procbased_ctls_low &=
2798 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2799
2800 /* secondary cpu-based controls */
2801 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2802 vmx->nested.nested_vmx_secondary_ctls_low,
2803 vmx->nested.nested_vmx_secondary_ctls_high);
2804 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2805 vmx->nested.nested_vmx_secondary_ctls_high &=
2806 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2807 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2808 SECONDARY_EXEC_RDTSCP |
2809 SECONDARY_EXEC_DESC |
2810 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2811 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2812 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2813 SECONDARY_EXEC_WBINVD_EXITING |
2814 SECONDARY_EXEC_XSAVES;
2815
2816 if (enable_ept) {
2817 /* nested EPT: emulate EPT also to L1 */
2818 vmx->nested.nested_vmx_secondary_ctls_high |=
2819 SECONDARY_EXEC_ENABLE_EPT;
2820 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2821 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2822 if (cpu_has_vmx_ept_execute_only())
2823 vmx->nested.nested_vmx_ept_caps |=
2824 VMX_EPT_EXECUTE_ONLY_BIT;
2825 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2826 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2827 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2828 VMX_EPT_1GB_PAGE_BIT;
2829 if (enable_ept_ad_bits) {
2830 vmx->nested.nested_vmx_secondary_ctls_high |=
2831 SECONDARY_EXEC_ENABLE_PML;
2832 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2833 }
2834 } else
2835 vmx->nested.nested_vmx_ept_caps = 0;
2836
2837 /*
2838 * Old versions of KVM use the single-context version without
2839 * checking for support, so declare that it is supported even
2840 * though it is treated as global context. The alternative is
2841 * not failing the single-context invvpid, and it is worse.
2842 */
2843 if (enable_vpid) {
2844 vmx->nested.nested_vmx_secondary_ctls_high |=
2845 SECONDARY_EXEC_ENABLE_VPID;
2846 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2847 VMX_VPID_EXTENT_SUPPORTED_MASK;
2848 } else
2849 vmx->nested.nested_vmx_vpid_caps = 0;
2850
2851 if (enable_unrestricted_guest)
2852 vmx->nested.nested_vmx_secondary_ctls_high |=
2853 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2854
2855 /* miscellaneous data */
2856 rdmsr(MSR_IA32_VMX_MISC,
2857 vmx->nested.nested_vmx_misc_low,
2858 vmx->nested.nested_vmx_misc_high);
2859 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2860 vmx->nested.nested_vmx_misc_low |=
2861 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2862 VMX_MISC_ACTIVITY_HLT;
2863 vmx->nested.nested_vmx_misc_high = 0;
2864
2865 /*
2866 * This MSR reports some information about VMX support. We
2867 * should return information about the VMX we emulate for the
2868 * guest, and the VMCS structure we give it - not about the
2869 * VMX support of the underlying hardware.
2870 */
2871 vmx->nested.nested_vmx_basic =
2872 VMCS12_REVISION |
2873 VMX_BASIC_TRUE_CTLS |
2874 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2875 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2876
2877 if (cpu_has_vmx_basic_inout())
2878 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2879
2880 /*
2881 * These MSRs specify bits which the guest must keep fixed on
2882 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2883 * We picked the standard core2 setting.
2884 */
2885 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2886 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2887 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2888 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2889
2890 /* These MSRs specify bits which the guest must keep fixed off. */
2891 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2892 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2893
2894 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2895 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2896 }
2897
2898 /*
2899 * if fixed0[i] == 1: val[i] must be 1
2900 * if fixed1[i] == 0: val[i] must be 0
2901 */
2902 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2903 {
2904 return ((val & fixed1) | fixed0) == val;
2905 }
2906
2907 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2908 {
2909 return fixed_bits_valid(control, low, high);
2910 }
2911
2912 static inline u64 vmx_control_msr(u32 low, u32 high)
2913 {
2914 return low | ((u64)high << 32);
2915 }
2916
2917 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2918 {
2919 superset &= mask;
2920 subset &= mask;
2921
2922 return (superset | subset) == superset;
2923 }
2924
2925 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2926 {
2927 const u64 feature_and_reserved =
2928 /* feature (except bit 48; see below) */
2929 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2930 /* reserved */
2931 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2932 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2933
2934 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2935 return -EINVAL;
2936
2937 /*
2938 * KVM does not emulate a version of VMX that constrains physical
2939 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2940 */
2941 if (data & BIT_ULL(48))
2942 return -EINVAL;
2943
2944 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2945 vmx_basic_vmcs_revision_id(data))
2946 return -EINVAL;
2947
2948 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2949 return -EINVAL;
2950
2951 vmx->nested.nested_vmx_basic = data;
2952 return 0;
2953 }
2954
2955 static int
2956 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2957 {
2958 u64 supported;
2959 u32 *lowp, *highp;
2960
2961 switch (msr_index) {
2962 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2963 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2964 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2965 break;
2966 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2967 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2968 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2969 break;
2970 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2971 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2972 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2973 break;
2974 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2975 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2976 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2977 break;
2978 case MSR_IA32_VMX_PROCBASED_CTLS2:
2979 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2980 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2981 break;
2982 default:
2983 BUG();
2984 }
2985
2986 supported = vmx_control_msr(*lowp, *highp);
2987
2988 /* Check must-be-1 bits are still 1. */
2989 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2990 return -EINVAL;
2991
2992 /* Check must-be-0 bits are still 0. */
2993 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2994 return -EINVAL;
2995
2996 *lowp = data;
2997 *highp = data >> 32;
2998 return 0;
2999 }
3000
3001 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3002 {
3003 const u64 feature_and_reserved_bits =
3004 /* feature */
3005 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3006 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3007 /* reserved */
3008 GENMASK_ULL(13, 9) | BIT_ULL(31);
3009 u64 vmx_misc;
3010
3011 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3012 vmx->nested.nested_vmx_misc_high);
3013
3014 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3015 return -EINVAL;
3016
3017 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3018 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3019 vmx_misc_preemption_timer_rate(data) !=
3020 vmx_misc_preemption_timer_rate(vmx_misc))
3021 return -EINVAL;
3022
3023 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3024 return -EINVAL;
3025
3026 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3027 return -EINVAL;
3028
3029 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3030 return -EINVAL;
3031
3032 vmx->nested.nested_vmx_misc_low = data;
3033 vmx->nested.nested_vmx_misc_high = data >> 32;
3034 return 0;
3035 }
3036
3037 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3038 {
3039 u64 vmx_ept_vpid_cap;
3040
3041 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3042 vmx->nested.nested_vmx_vpid_caps);
3043
3044 /* Every bit is either reserved or a feature bit. */
3045 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3046 return -EINVAL;
3047
3048 vmx->nested.nested_vmx_ept_caps = data;
3049 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3050 return 0;
3051 }
3052
3053 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3054 {
3055 u64 *msr;
3056
3057 switch (msr_index) {
3058 case MSR_IA32_VMX_CR0_FIXED0:
3059 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3060 break;
3061 case MSR_IA32_VMX_CR4_FIXED0:
3062 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3063 break;
3064 default:
3065 BUG();
3066 }
3067
3068 /*
3069 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3070 * must be 1 in the restored value.
3071 */
3072 if (!is_bitwise_subset(data, *msr, -1ULL))
3073 return -EINVAL;
3074
3075 *msr = data;
3076 return 0;
3077 }
3078
3079 /*
3080 * Called when userspace is restoring VMX MSRs.
3081 *
3082 * Returns 0 on success, non-0 otherwise.
3083 */
3084 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3085 {
3086 struct vcpu_vmx *vmx = to_vmx(vcpu);
3087
3088 switch (msr_index) {
3089 case MSR_IA32_VMX_BASIC:
3090 return vmx_restore_vmx_basic(vmx, data);
3091 case MSR_IA32_VMX_PINBASED_CTLS:
3092 case MSR_IA32_VMX_PROCBASED_CTLS:
3093 case MSR_IA32_VMX_EXIT_CTLS:
3094 case MSR_IA32_VMX_ENTRY_CTLS:
3095 /*
3096 * The "non-true" VMX capability MSRs are generated from the
3097 * "true" MSRs, so we do not support restoring them directly.
3098 *
3099 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3100 * should restore the "true" MSRs with the must-be-1 bits
3101 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3102 * DEFAULT SETTINGS".
3103 */
3104 return -EINVAL;
3105 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3106 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3107 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3108 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3109 case MSR_IA32_VMX_PROCBASED_CTLS2:
3110 return vmx_restore_control_msr(vmx, msr_index, data);
3111 case MSR_IA32_VMX_MISC:
3112 return vmx_restore_vmx_misc(vmx, data);
3113 case MSR_IA32_VMX_CR0_FIXED0:
3114 case MSR_IA32_VMX_CR4_FIXED0:
3115 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3116 case MSR_IA32_VMX_CR0_FIXED1:
3117 case MSR_IA32_VMX_CR4_FIXED1:
3118 /*
3119 * These MSRs are generated based on the vCPU's CPUID, so we
3120 * do not support restoring them directly.
3121 */
3122 return -EINVAL;
3123 case MSR_IA32_VMX_EPT_VPID_CAP:
3124 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3125 case MSR_IA32_VMX_VMCS_ENUM:
3126 vmx->nested.nested_vmx_vmcs_enum = data;
3127 return 0;
3128 default:
3129 /*
3130 * The rest of the VMX capability MSRs do not support restore.
3131 */
3132 return -EINVAL;
3133 }
3134 }
3135
3136 /* Returns 0 on success, non-0 otherwise. */
3137 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3138 {
3139 struct vcpu_vmx *vmx = to_vmx(vcpu);
3140
3141 switch (msr_index) {
3142 case MSR_IA32_VMX_BASIC:
3143 *pdata = vmx->nested.nested_vmx_basic;
3144 break;
3145 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3146 case MSR_IA32_VMX_PINBASED_CTLS:
3147 *pdata = vmx_control_msr(
3148 vmx->nested.nested_vmx_pinbased_ctls_low,
3149 vmx->nested.nested_vmx_pinbased_ctls_high);
3150 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3151 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3152 break;
3153 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3154 case MSR_IA32_VMX_PROCBASED_CTLS:
3155 *pdata = vmx_control_msr(
3156 vmx->nested.nested_vmx_procbased_ctls_low,
3157 vmx->nested.nested_vmx_procbased_ctls_high);
3158 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3159 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3160 break;
3161 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3162 case MSR_IA32_VMX_EXIT_CTLS:
3163 *pdata = vmx_control_msr(
3164 vmx->nested.nested_vmx_exit_ctls_low,
3165 vmx->nested.nested_vmx_exit_ctls_high);
3166 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3167 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3168 break;
3169 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3170 case MSR_IA32_VMX_ENTRY_CTLS:
3171 *pdata = vmx_control_msr(
3172 vmx->nested.nested_vmx_entry_ctls_low,
3173 vmx->nested.nested_vmx_entry_ctls_high);
3174 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3175 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3176 break;
3177 case MSR_IA32_VMX_MISC:
3178 *pdata = vmx_control_msr(
3179 vmx->nested.nested_vmx_misc_low,
3180 vmx->nested.nested_vmx_misc_high);
3181 break;
3182 case MSR_IA32_VMX_CR0_FIXED0:
3183 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3184 break;
3185 case MSR_IA32_VMX_CR0_FIXED1:
3186 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3187 break;
3188 case MSR_IA32_VMX_CR4_FIXED0:
3189 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3190 break;
3191 case MSR_IA32_VMX_CR4_FIXED1:
3192 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3193 break;
3194 case MSR_IA32_VMX_VMCS_ENUM:
3195 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3196 break;
3197 case MSR_IA32_VMX_PROCBASED_CTLS2:
3198 *pdata = vmx_control_msr(
3199 vmx->nested.nested_vmx_secondary_ctls_low,
3200 vmx->nested.nested_vmx_secondary_ctls_high);
3201 break;
3202 case MSR_IA32_VMX_EPT_VPID_CAP:
3203 *pdata = vmx->nested.nested_vmx_ept_caps |
3204 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3205 break;
3206 default:
3207 return 1;
3208 }
3209
3210 return 0;
3211 }
3212
3213 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3214 uint64_t val)
3215 {
3216 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3217
3218 return !(val & ~valid_bits);
3219 }
3220
3221 /*
3222 * Reads an msr value (of 'msr_index') into 'pdata'.
3223 * Returns 0 on success, non-0 otherwise.
3224 * Assumes vcpu_load() was already called.
3225 */
3226 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3227 {
3228 struct shared_msr_entry *msr;
3229
3230 switch (msr_info->index) {
3231 #ifdef CONFIG_X86_64
3232 case MSR_FS_BASE:
3233 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3234 break;
3235 case MSR_GS_BASE:
3236 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3237 break;
3238 case MSR_KERNEL_GS_BASE:
3239 vmx_load_host_state(to_vmx(vcpu));
3240 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3241 break;
3242 #endif
3243 case MSR_EFER:
3244 return kvm_get_msr_common(vcpu, msr_info);
3245 case MSR_IA32_TSC:
3246 msr_info->data = guest_read_tsc(vcpu);
3247 break;
3248 case MSR_IA32_SYSENTER_CS:
3249 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3250 break;
3251 case MSR_IA32_SYSENTER_EIP:
3252 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3253 break;
3254 case MSR_IA32_SYSENTER_ESP:
3255 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3256 break;
3257 case MSR_IA32_BNDCFGS:
3258 if (!kvm_mpx_supported() ||
3259 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3260 return 1;
3261 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3262 break;
3263 case MSR_IA32_MCG_EXT_CTL:
3264 if (!msr_info->host_initiated &&
3265 !(to_vmx(vcpu)->msr_ia32_feature_control &
3266 FEATURE_CONTROL_LMCE))
3267 return 1;
3268 msr_info->data = vcpu->arch.mcg_ext_ctl;
3269 break;
3270 case MSR_IA32_FEATURE_CONTROL:
3271 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3272 break;
3273 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3274 if (!nested_vmx_allowed(vcpu))
3275 return 1;
3276 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3277 case MSR_IA32_XSS:
3278 if (!vmx_xsaves_supported())
3279 return 1;
3280 msr_info->data = vcpu->arch.ia32_xss;
3281 break;
3282 case MSR_TSC_AUX:
3283 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3284 return 1;
3285 /* Otherwise falls through */
3286 default:
3287 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3288 if (msr) {
3289 msr_info->data = msr->data;
3290 break;
3291 }
3292 return kvm_get_msr_common(vcpu, msr_info);
3293 }
3294
3295 return 0;
3296 }
3297
3298 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3299
3300 /*
3301 * Writes msr value into into the appropriate "register".
3302 * Returns 0 on success, non-0 otherwise.
3303 * Assumes vcpu_load() was already called.
3304 */
3305 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3306 {
3307 struct vcpu_vmx *vmx = to_vmx(vcpu);
3308 struct shared_msr_entry *msr;
3309 int ret = 0;
3310 u32 msr_index = msr_info->index;
3311 u64 data = msr_info->data;
3312
3313 switch (msr_index) {
3314 case MSR_EFER:
3315 ret = kvm_set_msr_common(vcpu, msr_info);
3316 break;
3317 #ifdef CONFIG_X86_64
3318 case MSR_FS_BASE:
3319 vmx_segment_cache_clear(vmx);
3320 vmcs_writel(GUEST_FS_BASE, data);
3321 break;
3322 case MSR_GS_BASE:
3323 vmx_segment_cache_clear(vmx);
3324 vmcs_writel(GUEST_GS_BASE, data);
3325 break;
3326 case MSR_KERNEL_GS_BASE:
3327 vmx_load_host_state(vmx);
3328 vmx->msr_guest_kernel_gs_base = data;
3329 break;
3330 #endif
3331 case MSR_IA32_SYSENTER_CS:
3332 vmcs_write32(GUEST_SYSENTER_CS, data);
3333 break;
3334 case MSR_IA32_SYSENTER_EIP:
3335 vmcs_writel(GUEST_SYSENTER_EIP, data);
3336 break;
3337 case MSR_IA32_SYSENTER_ESP:
3338 vmcs_writel(GUEST_SYSENTER_ESP, data);
3339 break;
3340 case MSR_IA32_BNDCFGS:
3341 if (!kvm_mpx_supported() ||
3342 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3343 return 1;
3344 if (is_noncanonical_address(data & PAGE_MASK) ||
3345 (data & MSR_IA32_BNDCFGS_RSVD))
3346 return 1;
3347 vmcs_write64(GUEST_BNDCFGS, data);
3348 break;
3349 case MSR_IA32_TSC:
3350 kvm_write_tsc(vcpu, msr_info);
3351 break;
3352 case MSR_IA32_CR_PAT:
3353 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3354 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3355 return 1;
3356 vmcs_write64(GUEST_IA32_PAT, data);
3357 vcpu->arch.pat = data;
3358 break;
3359 }
3360 ret = kvm_set_msr_common(vcpu, msr_info);
3361 break;
3362 case MSR_IA32_TSC_ADJUST:
3363 ret = kvm_set_msr_common(vcpu, msr_info);
3364 break;
3365 case MSR_IA32_MCG_EXT_CTL:
3366 if ((!msr_info->host_initiated &&
3367 !(to_vmx(vcpu)->msr_ia32_feature_control &
3368 FEATURE_CONTROL_LMCE)) ||
3369 (data & ~MCG_EXT_CTL_LMCE_EN))
3370 return 1;
3371 vcpu->arch.mcg_ext_ctl = data;
3372 break;
3373 case MSR_IA32_FEATURE_CONTROL:
3374 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3375 (to_vmx(vcpu)->msr_ia32_feature_control &
3376 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3377 return 1;
3378 vmx->msr_ia32_feature_control = data;
3379 if (msr_info->host_initiated && data == 0)
3380 vmx_leave_nested(vcpu);
3381 break;
3382 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3383 if (!msr_info->host_initiated)
3384 return 1; /* they are read-only */
3385 if (!nested_vmx_allowed(vcpu))
3386 return 1;
3387 return vmx_set_vmx_msr(vcpu, msr_index, data);
3388 case MSR_IA32_XSS:
3389 if (!vmx_xsaves_supported())
3390 return 1;
3391 /*
3392 * The only supported bit as of Skylake is bit 8, but
3393 * it is not supported on KVM.
3394 */
3395 if (data != 0)
3396 return 1;
3397 vcpu->arch.ia32_xss = data;
3398 if (vcpu->arch.ia32_xss != host_xss)
3399 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3400 vcpu->arch.ia32_xss, host_xss);
3401 else
3402 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3403 break;
3404 case MSR_TSC_AUX:
3405 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3406 return 1;
3407 /* Check reserved bit, higher 32 bits should be zero */
3408 if ((data >> 32) != 0)
3409 return 1;
3410 /* Otherwise falls through */
3411 default:
3412 msr = find_msr_entry(vmx, msr_index);
3413 if (msr) {
3414 u64 old_msr_data = msr->data;
3415 msr->data = data;
3416 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3417 preempt_disable();
3418 ret = kvm_set_shared_msr(msr->index, msr->data,
3419 msr->mask);
3420 preempt_enable();
3421 if (ret)
3422 msr->data = old_msr_data;
3423 }
3424 break;
3425 }
3426 ret = kvm_set_msr_common(vcpu, msr_info);
3427 }
3428
3429 return ret;
3430 }
3431
3432 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3433 {
3434 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3435 switch (reg) {
3436 case VCPU_REGS_RSP:
3437 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3438 break;
3439 case VCPU_REGS_RIP:
3440 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3441 break;
3442 case VCPU_EXREG_PDPTR:
3443 if (enable_ept)
3444 ept_save_pdptrs(vcpu);
3445 break;
3446 default:
3447 break;
3448 }
3449 }
3450
3451 static __init int cpu_has_kvm_support(void)
3452 {
3453 return cpu_has_vmx();
3454 }
3455
3456 static __init int vmx_disabled_by_bios(void)
3457 {
3458 u64 msr;
3459
3460 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3461 if (msr & FEATURE_CONTROL_LOCKED) {
3462 /* launched w/ TXT and VMX disabled */
3463 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3464 && tboot_enabled())
3465 return 1;
3466 /* launched w/o TXT and VMX only enabled w/ TXT */
3467 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3468 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3469 && !tboot_enabled()) {
3470 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3471 "activate TXT before enabling KVM\n");
3472 return 1;
3473 }
3474 /* launched w/o TXT and VMX disabled */
3475 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3476 && !tboot_enabled())
3477 return 1;
3478 }
3479
3480 return 0;
3481 }
3482
3483 static void kvm_cpu_vmxon(u64 addr)
3484 {
3485 cr4_set_bits(X86_CR4_VMXE);
3486 intel_pt_handle_vmx(1);
3487
3488 asm volatile (ASM_VMX_VMXON_RAX
3489 : : "a"(&addr), "m"(addr)
3490 : "memory", "cc");
3491 }
3492
3493 static int hardware_enable(void)
3494 {
3495 int cpu = raw_smp_processor_id();
3496 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3497 u64 old, test_bits;
3498
3499 if (cr4_read_shadow() & X86_CR4_VMXE)
3500 return -EBUSY;
3501
3502 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3503 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3504 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3505
3506 /*
3507 * Now we can enable the vmclear operation in kdump
3508 * since the loaded_vmcss_on_cpu list on this cpu
3509 * has been initialized.
3510 *
3511 * Though the cpu is not in VMX operation now, there
3512 * is no problem to enable the vmclear operation
3513 * for the loaded_vmcss_on_cpu list is empty!
3514 */
3515 crash_enable_local_vmclear(cpu);
3516
3517 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3518
3519 test_bits = FEATURE_CONTROL_LOCKED;
3520 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3521 if (tboot_enabled())
3522 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3523
3524 if ((old & test_bits) != test_bits) {
3525 /* enable and lock */
3526 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3527 }
3528 kvm_cpu_vmxon(phys_addr);
3529 ept_sync_global();
3530
3531 return 0;
3532 }
3533
3534 static void vmclear_local_loaded_vmcss(void)
3535 {
3536 int cpu = raw_smp_processor_id();
3537 struct loaded_vmcs *v, *n;
3538
3539 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3540 loaded_vmcss_on_cpu_link)
3541 __loaded_vmcs_clear(v);
3542 }
3543
3544
3545 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3546 * tricks.
3547 */
3548 static void kvm_cpu_vmxoff(void)
3549 {
3550 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3551
3552 intel_pt_handle_vmx(0);
3553 cr4_clear_bits(X86_CR4_VMXE);
3554 }
3555
3556 static void hardware_disable(void)
3557 {
3558 vmclear_local_loaded_vmcss();
3559 kvm_cpu_vmxoff();
3560 }
3561
3562 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3563 u32 msr, u32 *result)
3564 {
3565 u32 vmx_msr_low, vmx_msr_high;
3566 u32 ctl = ctl_min | ctl_opt;
3567
3568 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3569
3570 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3571 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3572
3573 /* Ensure minimum (required) set of control bits are supported. */
3574 if (ctl_min & ~ctl)
3575 return -EIO;
3576
3577 *result = ctl;
3578 return 0;
3579 }
3580
3581 static __init bool allow_1_setting(u32 msr, u32 ctl)
3582 {
3583 u32 vmx_msr_low, vmx_msr_high;
3584
3585 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3586 return vmx_msr_high & ctl;
3587 }
3588
3589 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3590 {
3591 u32 vmx_msr_low, vmx_msr_high;
3592 u32 min, opt, min2, opt2;
3593 u32 _pin_based_exec_control = 0;
3594 u32 _cpu_based_exec_control = 0;
3595 u32 _cpu_based_2nd_exec_control = 0;
3596 u32 _vmexit_control = 0;
3597 u32 _vmentry_control = 0;
3598
3599 min = CPU_BASED_HLT_EXITING |
3600 #ifdef CONFIG_X86_64
3601 CPU_BASED_CR8_LOAD_EXITING |
3602 CPU_BASED_CR8_STORE_EXITING |
3603 #endif
3604 CPU_BASED_CR3_LOAD_EXITING |
3605 CPU_BASED_CR3_STORE_EXITING |
3606 CPU_BASED_USE_IO_BITMAPS |
3607 CPU_BASED_MOV_DR_EXITING |
3608 CPU_BASED_USE_TSC_OFFSETING |
3609 CPU_BASED_INVLPG_EXITING |
3610 CPU_BASED_RDPMC_EXITING;
3611
3612 if (!kvm_mwait_in_guest())
3613 min |= CPU_BASED_MWAIT_EXITING |
3614 CPU_BASED_MONITOR_EXITING;
3615
3616 opt = CPU_BASED_TPR_SHADOW |
3617 CPU_BASED_USE_MSR_BITMAPS |
3618 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3619 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3620 &_cpu_based_exec_control) < 0)
3621 return -EIO;
3622 #ifdef CONFIG_X86_64
3623 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3624 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3625 ~CPU_BASED_CR8_STORE_EXITING;
3626 #endif
3627 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3628 min2 = 0;
3629 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3630 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3631 SECONDARY_EXEC_WBINVD_EXITING |
3632 SECONDARY_EXEC_ENABLE_VPID |
3633 SECONDARY_EXEC_ENABLE_EPT |
3634 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3635 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3636 SECONDARY_EXEC_RDTSCP |
3637 SECONDARY_EXEC_ENABLE_INVPCID |
3638 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3639 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3640 SECONDARY_EXEC_SHADOW_VMCS |
3641 SECONDARY_EXEC_XSAVES |
3642 SECONDARY_EXEC_ENABLE_PML |
3643 SECONDARY_EXEC_TSC_SCALING;
3644 if (adjust_vmx_controls(min2, opt2,
3645 MSR_IA32_VMX_PROCBASED_CTLS2,
3646 &_cpu_based_2nd_exec_control) < 0)
3647 return -EIO;
3648 }
3649 #ifndef CONFIG_X86_64
3650 if (!(_cpu_based_2nd_exec_control &
3651 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3652 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3653 #endif
3654
3655 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3656 _cpu_based_2nd_exec_control &= ~(
3657 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3658 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3659 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3660
3661 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3662 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3663 enabled */
3664 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3665 CPU_BASED_CR3_STORE_EXITING |
3666 CPU_BASED_INVLPG_EXITING);
3667 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3668 vmx_capability.ept, vmx_capability.vpid);
3669 }
3670
3671 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3672 #ifdef CONFIG_X86_64
3673 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3674 #endif
3675 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3676 VM_EXIT_CLEAR_BNDCFGS;
3677 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3678 &_vmexit_control) < 0)
3679 return -EIO;
3680
3681 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3682 PIN_BASED_VIRTUAL_NMIS;
3683 opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3684 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3685 &_pin_based_exec_control) < 0)
3686 return -EIO;
3687
3688 if (cpu_has_broken_vmx_preemption_timer())
3689 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3690 if (!(_cpu_based_2nd_exec_control &
3691 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3692 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3693
3694 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3695 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3696 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3697 &_vmentry_control) < 0)
3698 return -EIO;
3699
3700 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3701
3702 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3703 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3704 return -EIO;
3705
3706 #ifdef CONFIG_X86_64
3707 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3708 if (vmx_msr_high & (1u<<16))
3709 return -EIO;
3710 #endif
3711
3712 /* Require Write-Back (WB) memory type for VMCS accesses. */
3713 if (((vmx_msr_high >> 18) & 15) != 6)
3714 return -EIO;
3715
3716 vmcs_conf->size = vmx_msr_high & 0x1fff;
3717 vmcs_conf->order = get_order(vmcs_conf->size);
3718 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3719 vmcs_conf->revision_id = vmx_msr_low;
3720
3721 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3722 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3723 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3724 vmcs_conf->vmexit_ctrl = _vmexit_control;
3725 vmcs_conf->vmentry_ctrl = _vmentry_control;
3726
3727 cpu_has_load_ia32_efer =
3728 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3729 VM_ENTRY_LOAD_IA32_EFER)
3730 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3731 VM_EXIT_LOAD_IA32_EFER);
3732
3733 cpu_has_load_perf_global_ctrl =
3734 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3735 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3736 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3737 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3738
3739 /*
3740 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3741 * but due to errata below it can't be used. Workaround is to use
3742 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3743 *
3744 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3745 *
3746 * AAK155 (model 26)
3747 * AAP115 (model 30)
3748 * AAT100 (model 37)
3749 * BC86,AAY89,BD102 (model 44)
3750 * BA97 (model 46)
3751 *
3752 */
3753 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3754 switch (boot_cpu_data.x86_model) {
3755 case 26:
3756 case 30:
3757 case 37:
3758 case 44:
3759 case 46:
3760 cpu_has_load_perf_global_ctrl = false;
3761 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3762 "does not work properly. Using workaround\n");
3763 break;
3764 default:
3765 break;
3766 }
3767 }
3768
3769 if (boot_cpu_has(X86_FEATURE_XSAVES))
3770 rdmsrl(MSR_IA32_XSS, host_xss);
3771
3772 return 0;
3773 }
3774
3775 static struct vmcs *alloc_vmcs_cpu(int cpu)
3776 {
3777 int node = cpu_to_node(cpu);
3778 struct page *pages;
3779 struct vmcs *vmcs;
3780
3781 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3782 if (!pages)
3783 return NULL;
3784 vmcs = page_address(pages);
3785 memset(vmcs, 0, vmcs_config.size);
3786 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3787 return vmcs;
3788 }
3789
3790 static struct vmcs *alloc_vmcs(void)
3791 {
3792 return alloc_vmcs_cpu(raw_smp_processor_id());
3793 }
3794
3795 static void free_vmcs(struct vmcs *vmcs)
3796 {
3797 free_pages((unsigned long)vmcs, vmcs_config.order);
3798 }
3799
3800 /*
3801 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3802 */
3803 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3804 {
3805 if (!loaded_vmcs->vmcs)
3806 return;
3807 loaded_vmcs_clear(loaded_vmcs);
3808 free_vmcs(loaded_vmcs->vmcs);
3809 loaded_vmcs->vmcs = NULL;
3810 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3811 }
3812
3813 static void free_kvm_area(void)
3814 {
3815 int cpu;
3816
3817 for_each_possible_cpu(cpu) {
3818 free_vmcs(per_cpu(vmxarea, cpu));
3819 per_cpu(vmxarea, cpu) = NULL;
3820 }
3821 }
3822
3823 enum vmcs_field_type {
3824 VMCS_FIELD_TYPE_U16 = 0,
3825 VMCS_FIELD_TYPE_U64 = 1,
3826 VMCS_FIELD_TYPE_U32 = 2,
3827 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3828 };
3829
3830 static inline int vmcs_field_type(unsigned long field)
3831 {
3832 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
3833 return VMCS_FIELD_TYPE_U32;
3834 return (field >> 13) & 0x3 ;
3835 }
3836
3837 static inline int vmcs_field_readonly(unsigned long field)
3838 {
3839 return (((field >> 10) & 0x3) == 1);
3840 }
3841
3842 static void init_vmcs_shadow_fields(void)
3843 {
3844 int i, j;
3845
3846 /* No checks for read only fields yet */
3847
3848 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3849 switch (shadow_read_write_fields[i]) {
3850 case GUEST_BNDCFGS:
3851 if (!kvm_mpx_supported())
3852 continue;
3853 break;
3854 default:
3855 break;
3856 }
3857
3858 if (j < i)
3859 shadow_read_write_fields[j] =
3860 shadow_read_write_fields[i];
3861 j++;
3862 }
3863 max_shadow_read_write_fields = j;
3864
3865 /* shadowed fields guest access without vmexit */
3866 for (i = 0; i < max_shadow_read_write_fields; i++) {
3867 unsigned long field = shadow_read_write_fields[i];
3868
3869 clear_bit(field, vmx_vmwrite_bitmap);
3870 clear_bit(field, vmx_vmread_bitmap);
3871 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3872 clear_bit(field + 1, vmx_vmwrite_bitmap);
3873 clear_bit(field + 1, vmx_vmread_bitmap);
3874 }
3875 }
3876 for (i = 0; i < max_shadow_read_only_fields; i++) {
3877 unsigned long field = shadow_read_only_fields[i];
3878
3879 clear_bit(field, vmx_vmread_bitmap);
3880 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3881 clear_bit(field + 1, vmx_vmread_bitmap);
3882 }
3883 }
3884
3885 static __init int alloc_kvm_area(void)
3886 {
3887 int cpu;
3888
3889 for_each_possible_cpu(cpu) {
3890 struct vmcs *vmcs;
3891
3892 vmcs = alloc_vmcs_cpu(cpu);
3893 if (!vmcs) {
3894 free_kvm_area();
3895 return -ENOMEM;
3896 }
3897
3898 per_cpu(vmxarea, cpu) = vmcs;
3899 }
3900 return 0;
3901 }
3902
3903 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3904 struct kvm_segment *save)
3905 {
3906 if (!emulate_invalid_guest_state) {
3907 /*
3908 * CS and SS RPL should be equal during guest entry according
3909 * to VMX spec, but in reality it is not always so. Since vcpu
3910 * is in the middle of the transition from real mode to
3911 * protected mode it is safe to assume that RPL 0 is a good
3912 * default value.
3913 */
3914 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3915 save->selector &= ~SEGMENT_RPL_MASK;
3916 save->dpl = save->selector & SEGMENT_RPL_MASK;
3917 save->s = 1;
3918 }
3919 vmx_set_segment(vcpu, save, seg);
3920 }
3921
3922 static void enter_pmode(struct kvm_vcpu *vcpu)
3923 {
3924 unsigned long flags;
3925 struct vcpu_vmx *vmx = to_vmx(vcpu);
3926
3927 /*
3928 * Update real mode segment cache. It may be not up-to-date if sement
3929 * register was written while vcpu was in a guest mode.
3930 */
3931 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3932 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3933 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3934 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3935 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3936 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3937
3938 vmx->rmode.vm86_active = 0;
3939
3940 vmx_segment_cache_clear(vmx);
3941
3942 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3943
3944 flags = vmcs_readl(GUEST_RFLAGS);
3945 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3946 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3947 vmcs_writel(GUEST_RFLAGS, flags);
3948
3949 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3950 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3951
3952 update_exception_bitmap(vcpu);
3953
3954 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3955 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3956 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3957 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3958 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3959 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3960 }
3961
3962 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3963 {
3964 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3965 struct kvm_segment var = *save;
3966
3967 var.dpl = 0x3;
3968 if (seg == VCPU_SREG_CS)
3969 var.type = 0x3;
3970
3971 if (!emulate_invalid_guest_state) {
3972 var.selector = var.base >> 4;
3973 var.base = var.base & 0xffff0;
3974 var.limit = 0xffff;
3975 var.g = 0;
3976 var.db = 0;
3977 var.present = 1;
3978 var.s = 1;
3979 var.l = 0;
3980 var.unusable = 0;
3981 var.type = 0x3;
3982 var.avl = 0;
3983 if (save->base & 0xf)
3984 printk_once(KERN_WARNING "kvm: segment base is not "
3985 "paragraph aligned when entering "
3986 "protected mode (seg=%d)", seg);
3987 }
3988
3989 vmcs_write16(sf->selector, var.selector);
3990 vmcs_writel(sf->base, var.base);
3991 vmcs_write32(sf->limit, var.limit);
3992 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3993 }
3994
3995 static void enter_rmode(struct kvm_vcpu *vcpu)
3996 {
3997 unsigned long flags;
3998 struct vcpu_vmx *vmx = to_vmx(vcpu);
3999
4000 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4001 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4002 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4003 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4004 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4005 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4006 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4007
4008 vmx->rmode.vm86_active = 1;
4009
4010 /*
4011 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4012 * vcpu. Warn the user that an update is overdue.
4013 */
4014 if (!vcpu->kvm->arch.tss_addr)
4015 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4016 "called before entering vcpu\n");
4017
4018 vmx_segment_cache_clear(vmx);
4019
4020 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4021 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4022 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4023
4024 flags = vmcs_readl(GUEST_RFLAGS);
4025 vmx->rmode.save_rflags = flags;
4026
4027 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4028
4029 vmcs_writel(GUEST_RFLAGS, flags);
4030 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4031 update_exception_bitmap(vcpu);
4032
4033 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4034 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4035 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4036 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4037 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4038 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4039
4040 kvm_mmu_reset_context(vcpu);
4041 }
4042
4043 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4044 {
4045 struct vcpu_vmx *vmx = to_vmx(vcpu);
4046 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4047
4048 if (!msr)
4049 return;
4050
4051 /*
4052 * Force kernel_gs_base reloading before EFER changes, as control
4053 * of this msr depends on is_long_mode().
4054 */
4055 vmx_load_host_state(to_vmx(vcpu));
4056 vcpu->arch.efer = efer;
4057 if (efer & EFER_LMA) {
4058 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4059 msr->data = efer;
4060 } else {
4061 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4062
4063 msr->data = efer & ~EFER_LME;
4064 }
4065 setup_msrs(vmx);
4066 }
4067
4068 #ifdef CONFIG_X86_64
4069
4070 static void enter_lmode(struct kvm_vcpu *vcpu)
4071 {
4072 u32 guest_tr_ar;
4073
4074 vmx_segment_cache_clear(to_vmx(vcpu));
4075
4076 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4077 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4078 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4079 __func__);
4080 vmcs_write32(GUEST_TR_AR_BYTES,
4081 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4082 | VMX_AR_TYPE_BUSY_64_TSS);
4083 }
4084 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4085 }
4086
4087 static void exit_lmode(struct kvm_vcpu *vcpu)
4088 {
4089 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4090 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4091 }
4092
4093 #endif
4094
4095 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4096 {
4097 if (enable_ept) {
4098 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4099 return;
4100 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4101 } else {
4102 vpid_sync_context(vpid);
4103 }
4104 }
4105
4106 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4107 {
4108 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4109 }
4110
4111 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4112 {
4113 if (enable_ept)
4114 vmx_flush_tlb(vcpu);
4115 }
4116
4117 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4118 {
4119 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4120
4121 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4122 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4123 }
4124
4125 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4126 {
4127 if (enable_ept && is_paging(vcpu))
4128 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4129 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4130 }
4131
4132 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4133 {
4134 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4135
4136 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4137 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4138 }
4139
4140 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4141 {
4142 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4143
4144 if (!test_bit(VCPU_EXREG_PDPTR,
4145 (unsigned long *)&vcpu->arch.regs_dirty))
4146 return;
4147
4148 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4149 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4150 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4151 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4152 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4153 }
4154 }
4155
4156 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4157 {
4158 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4159
4160 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4161 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4162 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4163 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4164 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4165 }
4166
4167 __set_bit(VCPU_EXREG_PDPTR,
4168 (unsigned long *)&vcpu->arch.regs_avail);
4169 __set_bit(VCPU_EXREG_PDPTR,
4170 (unsigned long *)&vcpu->arch.regs_dirty);
4171 }
4172
4173 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4174 {
4175 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4176 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4177 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4178
4179 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4180 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4181 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4182 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4183
4184 return fixed_bits_valid(val, fixed0, fixed1);
4185 }
4186
4187 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4188 {
4189 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4190 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4191
4192 return fixed_bits_valid(val, fixed0, fixed1);
4193 }
4194
4195 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4196 {
4197 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4198 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4199
4200 return fixed_bits_valid(val, fixed0, fixed1);
4201 }
4202
4203 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4204 #define nested_guest_cr4_valid nested_cr4_valid
4205 #define nested_host_cr4_valid nested_cr4_valid
4206
4207 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4208
4209 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4210 unsigned long cr0,
4211 struct kvm_vcpu *vcpu)
4212 {
4213 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4214 vmx_decache_cr3(vcpu);
4215 if (!(cr0 & X86_CR0_PG)) {
4216 /* From paging/starting to nonpaging */
4217 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4218 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4219 (CPU_BASED_CR3_LOAD_EXITING |
4220 CPU_BASED_CR3_STORE_EXITING));
4221 vcpu->arch.cr0 = cr0;
4222 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4223 } else if (!is_paging(vcpu)) {
4224 /* From nonpaging to paging */
4225 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4226 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4227 ~(CPU_BASED_CR3_LOAD_EXITING |
4228 CPU_BASED_CR3_STORE_EXITING));
4229 vcpu->arch.cr0 = cr0;
4230 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4231 }
4232
4233 if (!(cr0 & X86_CR0_WP))
4234 *hw_cr0 &= ~X86_CR0_WP;
4235 }
4236
4237 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4238 {
4239 struct vcpu_vmx *vmx = to_vmx(vcpu);
4240 unsigned long hw_cr0;
4241
4242 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4243 if (enable_unrestricted_guest)
4244 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4245 else {
4246 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4247
4248 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4249 enter_pmode(vcpu);
4250
4251 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4252 enter_rmode(vcpu);
4253 }
4254
4255 #ifdef CONFIG_X86_64
4256 if (vcpu->arch.efer & EFER_LME) {
4257 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4258 enter_lmode(vcpu);
4259 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4260 exit_lmode(vcpu);
4261 }
4262 #endif
4263
4264 if (enable_ept)
4265 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4266
4267 vmcs_writel(CR0_READ_SHADOW, cr0);
4268 vmcs_writel(GUEST_CR0, hw_cr0);
4269 vcpu->arch.cr0 = cr0;
4270
4271 /* depends on vcpu->arch.cr0 to be set to a new value */
4272 vmx->emulation_required = emulation_required(vcpu);
4273 }
4274
4275 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4276 {
4277 u64 eptp;
4278
4279 /* TODO write the value reading from MSR */
4280 eptp = VMX_EPT_DEFAULT_MT |
4281 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4282 if (enable_ept_ad_bits &&
4283 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4284 eptp |= VMX_EPT_AD_ENABLE_BIT;
4285 eptp |= (root_hpa & PAGE_MASK);
4286
4287 return eptp;
4288 }
4289
4290 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4291 {
4292 unsigned long guest_cr3;
4293 u64 eptp;
4294
4295 guest_cr3 = cr3;
4296 if (enable_ept) {
4297 eptp = construct_eptp(vcpu, cr3);
4298 vmcs_write64(EPT_POINTER, eptp);
4299 if (is_paging(vcpu) || is_guest_mode(vcpu))
4300 guest_cr3 = kvm_read_cr3(vcpu);
4301 else
4302 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4303 ept_load_pdptrs(vcpu);
4304 }
4305
4306 vmx_flush_tlb(vcpu);
4307 vmcs_writel(GUEST_CR3, guest_cr3);
4308 }
4309
4310 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4311 {
4312 /*
4313 * Pass through host's Machine Check Enable value to hw_cr4, which
4314 * is in force while we are in guest mode. Do not let guests control
4315 * this bit, even if host CR4.MCE == 0.
4316 */
4317 unsigned long hw_cr4 =
4318 (cr4_read_shadow() & X86_CR4_MCE) |
4319 (cr4 & ~X86_CR4_MCE) |
4320 (to_vmx(vcpu)->rmode.vm86_active ?
4321 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4322
4323 if (cr4 & X86_CR4_VMXE) {
4324 /*
4325 * To use VMXON (and later other VMX instructions), a guest
4326 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4327 * So basically the check on whether to allow nested VMX
4328 * is here.
4329 */
4330 if (!nested_vmx_allowed(vcpu))
4331 return 1;
4332 }
4333
4334 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4335 return 1;
4336
4337 vcpu->arch.cr4 = cr4;
4338 if (enable_ept) {
4339 if (!is_paging(vcpu)) {
4340 hw_cr4 &= ~X86_CR4_PAE;
4341 hw_cr4 |= X86_CR4_PSE;
4342 } else if (!(cr4 & X86_CR4_PAE)) {
4343 hw_cr4 &= ~X86_CR4_PAE;
4344 }
4345 }
4346
4347 if (!enable_unrestricted_guest && !is_paging(vcpu))
4348 /*
4349 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4350 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4351 * to be manually disabled when guest switches to non-paging
4352 * mode.
4353 *
4354 * If !enable_unrestricted_guest, the CPU is always running
4355 * with CR0.PG=1 and CR4 needs to be modified.
4356 * If enable_unrestricted_guest, the CPU automatically
4357 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4358 */
4359 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4360
4361 vmcs_writel(CR4_READ_SHADOW, cr4);
4362 vmcs_writel(GUEST_CR4, hw_cr4);
4363 return 0;
4364 }
4365
4366 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4367 struct kvm_segment *var, int seg)
4368 {
4369 struct vcpu_vmx *vmx = to_vmx(vcpu);
4370 u32 ar;
4371
4372 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4373 *var = vmx->rmode.segs[seg];
4374 if (seg == VCPU_SREG_TR
4375 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4376 return;
4377 var->base = vmx_read_guest_seg_base(vmx, seg);
4378 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4379 return;
4380 }
4381 var->base = vmx_read_guest_seg_base(vmx, seg);
4382 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4383 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4384 ar = vmx_read_guest_seg_ar(vmx, seg);
4385 var->unusable = (ar >> 16) & 1;
4386 var->type = ar & 15;
4387 var->s = (ar >> 4) & 1;
4388 var->dpl = (ar >> 5) & 3;
4389 /*
4390 * Some userspaces do not preserve unusable property. Since usable
4391 * segment has to be present according to VMX spec we can use present
4392 * property to amend userspace bug by making unusable segment always
4393 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4394 * segment as unusable.
4395 */
4396 var->present = !var->unusable;
4397 var->avl = (ar >> 12) & 1;
4398 var->l = (ar >> 13) & 1;
4399 var->db = (ar >> 14) & 1;
4400 var->g = (ar >> 15) & 1;
4401 }
4402
4403 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4404 {
4405 struct kvm_segment s;
4406
4407 if (to_vmx(vcpu)->rmode.vm86_active) {
4408 vmx_get_segment(vcpu, &s, seg);
4409 return s.base;
4410 }
4411 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4412 }
4413
4414 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4415 {
4416 struct vcpu_vmx *vmx = to_vmx(vcpu);
4417
4418 if (unlikely(vmx->rmode.vm86_active))
4419 return 0;
4420 else {
4421 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4422 return VMX_AR_DPL(ar);
4423 }
4424 }
4425
4426 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4427 {
4428 u32 ar;
4429
4430 if (var->unusable || !var->present)
4431 ar = 1 << 16;
4432 else {
4433 ar = var->type & 15;
4434 ar |= (var->s & 1) << 4;
4435 ar |= (var->dpl & 3) << 5;
4436 ar |= (var->present & 1) << 7;
4437 ar |= (var->avl & 1) << 12;
4438 ar |= (var->l & 1) << 13;
4439 ar |= (var->db & 1) << 14;
4440 ar |= (var->g & 1) << 15;
4441 }
4442
4443 return ar;
4444 }
4445
4446 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4447 struct kvm_segment *var, int seg)
4448 {
4449 struct vcpu_vmx *vmx = to_vmx(vcpu);
4450 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4451
4452 vmx_segment_cache_clear(vmx);
4453
4454 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4455 vmx->rmode.segs[seg] = *var;
4456 if (seg == VCPU_SREG_TR)
4457 vmcs_write16(sf->selector, var->selector);
4458 else if (var->s)
4459 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4460 goto out;
4461 }
4462
4463 vmcs_writel(sf->base, var->base);
4464 vmcs_write32(sf->limit, var->limit);
4465 vmcs_write16(sf->selector, var->selector);
4466
4467 /*
4468 * Fix the "Accessed" bit in AR field of segment registers for older
4469 * qemu binaries.
4470 * IA32 arch specifies that at the time of processor reset the
4471 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4472 * is setting it to 0 in the userland code. This causes invalid guest
4473 * state vmexit when "unrestricted guest" mode is turned on.
4474 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4475 * tree. Newer qemu binaries with that qemu fix would not need this
4476 * kvm hack.
4477 */
4478 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4479 var->type |= 0x1; /* Accessed */
4480
4481 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4482
4483 out:
4484 vmx->emulation_required = emulation_required(vcpu);
4485 }
4486
4487 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4488 {
4489 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4490
4491 *db = (ar >> 14) & 1;
4492 *l = (ar >> 13) & 1;
4493 }
4494
4495 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4496 {
4497 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4498 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4499 }
4500
4501 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4502 {
4503 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4504 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4505 }
4506
4507 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4508 {
4509 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4510 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4511 }
4512
4513 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4514 {
4515 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4516 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4517 }
4518
4519 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4520 {
4521 struct kvm_segment var;
4522 u32 ar;
4523
4524 vmx_get_segment(vcpu, &var, seg);
4525 var.dpl = 0x3;
4526 if (seg == VCPU_SREG_CS)
4527 var.type = 0x3;
4528 ar = vmx_segment_access_rights(&var);
4529
4530 if (var.base != (var.selector << 4))
4531 return false;
4532 if (var.limit != 0xffff)
4533 return false;
4534 if (ar != 0xf3)
4535 return false;
4536
4537 return true;
4538 }
4539
4540 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4541 {
4542 struct kvm_segment cs;
4543 unsigned int cs_rpl;
4544
4545 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4546 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4547
4548 if (cs.unusable)
4549 return false;
4550 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4551 return false;
4552 if (!cs.s)
4553 return false;
4554 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4555 if (cs.dpl > cs_rpl)
4556 return false;
4557 } else {
4558 if (cs.dpl != cs_rpl)
4559 return false;
4560 }
4561 if (!cs.present)
4562 return false;
4563
4564 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4565 return true;
4566 }
4567
4568 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4569 {
4570 struct kvm_segment ss;
4571 unsigned int ss_rpl;
4572
4573 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4574 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4575
4576 if (ss.unusable)
4577 return true;
4578 if (ss.type != 3 && ss.type != 7)
4579 return false;
4580 if (!ss.s)
4581 return false;
4582 if (ss.dpl != ss_rpl) /* DPL != RPL */
4583 return false;
4584 if (!ss.present)
4585 return false;
4586
4587 return true;
4588 }
4589
4590 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4591 {
4592 struct kvm_segment var;
4593 unsigned int rpl;
4594
4595 vmx_get_segment(vcpu, &var, seg);
4596 rpl = var.selector & SEGMENT_RPL_MASK;
4597
4598 if (var.unusable)
4599 return true;
4600 if (!var.s)
4601 return false;
4602 if (!var.present)
4603 return false;
4604 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4605 if (var.dpl < rpl) /* DPL < RPL */
4606 return false;
4607 }
4608
4609 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4610 * rights flags
4611 */
4612 return true;
4613 }
4614
4615 static bool tr_valid(struct kvm_vcpu *vcpu)
4616 {
4617 struct kvm_segment tr;
4618
4619 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4620
4621 if (tr.unusable)
4622 return false;
4623 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4624 return false;
4625 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4626 return false;
4627 if (!tr.present)
4628 return false;
4629
4630 return true;
4631 }
4632
4633 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4634 {
4635 struct kvm_segment ldtr;
4636
4637 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4638
4639 if (ldtr.unusable)
4640 return true;
4641 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4642 return false;
4643 if (ldtr.type != 2)
4644 return false;
4645 if (!ldtr.present)
4646 return false;
4647
4648 return true;
4649 }
4650
4651 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4652 {
4653 struct kvm_segment cs, ss;
4654
4655 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4656 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4657
4658 return ((cs.selector & SEGMENT_RPL_MASK) ==
4659 (ss.selector & SEGMENT_RPL_MASK));
4660 }
4661
4662 /*
4663 * Check if guest state is valid. Returns true if valid, false if
4664 * not.
4665 * We assume that registers are always usable
4666 */
4667 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4668 {
4669 if (enable_unrestricted_guest)
4670 return true;
4671
4672 /* real mode guest state checks */
4673 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4674 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4675 return false;
4676 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4677 return false;
4678 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4679 return false;
4680 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4681 return false;
4682 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4683 return false;
4684 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4685 return false;
4686 } else {
4687 /* protected mode guest state checks */
4688 if (!cs_ss_rpl_check(vcpu))
4689 return false;
4690 if (!code_segment_valid(vcpu))
4691 return false;
4692 if (!stack_segment_valid(vcpu))
4693 return false;
4694 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4695 return false;
4696 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4697 return false;
4698 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4699 return false;
4700 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4701 return false;
4702 if (!tr_valid(vcpu))
4703 return false;
4704 if (!ldtr_valid(vcpu))
4705 return false;
4706 }
4707 /* TODO:
4708 * - Add checks on RIP
4709 * - Add checks on RFLAGS
4710 */
4711
4712 return true;
4713 }
4714
4715 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4716 {
4717 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4718 }
4719
4720 static int init_rmode_tss(struct kvm *kvm)
4721 {
4722 gfn_t fn;
4723 u16 data = 0;
4724 int idx, r;
4725
4726 idx = srcu_read_lock(&kvm->srcu);
4727 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4728 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4729 if (r < 0)
4730 goto out;
4731 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4732 r = kvm_write_guest_page(kvm, fn++, &data,
4733 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4734 if (r < 0)
4735 goto out;
4736 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4737 if (r < 0)
4738 goto out;
4739 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4740 if (r < 0)
4741 goto out;
4742 data = ~0;
4743 r = kvm_write_guest_page(kvm, fn, &data,
4744 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4745 sizeof(u8));
4746 out:
4747 srcu_read_unlock(&kvm->srcu, idx);
4748 return r;
4749 }
4750
4751 static int init_rmode_identity_map(struct kvm *kvm)
4752 {
4753 int i, idx, r = 0;
4754 kvm_pfn_t identity_map_pfn;
4755 u32 tmp;
4756
4757 if (!enable_ept)
4758 return 0;
4759
4760 /* Protect kvm->arch.ept_identity_pagetable_done. */
4761 mutex_lock(&kvm->slots_lock);
4762
4763 if (likely(kvm->arch.ept_identity_pagetable_done))
4764 goto out2;
4765
4766 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4767
4768 r = alloc_identity_pagetable(kvm);
4769 if (r < 0)
4770 goto out2;
4771
4772 idx = srcu_read_lock(&kvm->srcu);
4773 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4774 if (r < 0)
4775 goto out;
4776 /* Set up identity-mapping pagetable for EPT in real mode */
4777 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4778 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4779 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4780 r = kvm_write_guest_page(kvm, identity_map_pfn,
4781 &tmp, i * sizeof(tmp), sizeof(tmp));
4782 if (r < 0)
4783 goto out;
4784 }
4785 kvm->arch.ept_identity_pagetable_done = true;
4786
4787 out:
4788 srcu_read_unlock(&kvm->srcu, idx);
4789
4790 out2:
4791 mutex_unlock(&kvm->slots_lock);
4792 return r;
4793 }
4794
4795 static void seg_setup(int seg)
4796 {
4797 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4798 unsigned int ar;
4799
4800 vmcs_write16(sf->selector, 0);
4801 vmcs_writel(sf->base, 0);
4802 vmcs_write32(sf->limit, 0xffff);
4803 ar = 0x93;
4804 if (seg == VCPU_SREG_CS)
4805 ar |= 0x08; /* code segment */
4806
4807 vmcs_write32(sf->ar_bytes, ar);
4808 }
4809
4810 static int alloc_apic_access_page(struct kvm *kvm)
4811 {
4812 struct page *page;
4813 int r = 0;
4814
4815 mutex_lock(&kvm->slots_lock);
4816 if (kvm->arch.apic_access_page_done)
4817 goto out;
4818 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4819 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4820 if (r)
4821 goto out;
4822
4823 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4824 if (is_error_page(page)) {
4825 r = -EFAULT;
4826 goto out;
4827 }
4828
4829 /*
4830 * Do not pin the page in memory, so that memory hot-unplug
4831 * is able to migrate it.
4832 */
4833 put_page(page);
4834 kvm->arch.apic_access_page_done = true;
4835 out:
4836 mutex_unlock(&kvm->slots_lock);
4837 return r;
4838 }
4839
4840 static int alloc_identity_pagetable(struct kvm *kvm)
4841 {
4842 /* Called with kvm->slots_lock held. */
4843
4844 int r = 0;
4845
4846 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4847
4848 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4849 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4850
4851 return r;
4852 }
4853
4854 static int allocate_vpid(void)
4855 {
4856 int vpid;
4857
4858 if (!enable_vpid)
4859 return 0;
4860 spin_lock(&vmx_vpid_lock);
4861 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4862 if (vpid < VMX_NR_VPIDS)
4863 __set_bit(vpid, vmx_vpid_bitmap);
4864 else
4865 vpid = 0;
4866 spin_unlock(&vmx_vpid_lock);
4867 return vpid;
4868 }
4869
4870 static void free_vpid(int vpid)
4871 {
4872 if (!enable_vpid || vpid == 0)
4873 return;
4874 spin_lock(&vmx_vpid_lock);
4875 __clear_bit(vpid, vmx_vpid_bitmap);
4876 spin_unlock(&vmx_vpid_lock);
4877 }
4878
4879 #define MSR_TYPE_R 1
4880 #define MSR_TYPE_W 2
4881 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4882 u32 msr, int type)
4883 {
4884 int f = sizeof(unsigned long);
4885
4886 if (!cpu_has_vmx_msr_bitmap())
4887 return;
4888
4889 /*
4890 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4891 * have the write-low and read-high bitmap offsets the wrong way round.
4892 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4893 */
4894 if (msr <= 0x1fff) {
4895 if (type & MSR_TYPE_R)
4896 /* read-low */
4897 __clear_bit(msr, msr_bitmap + 0x000 / f);
4898
4899 if (type & MSR_TYPE_W)
4900 /* write-low */
4901 __clear_bit(msr, msr_bitmap + 0x800 / f);
4902
4903 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4904 msr &= 0x1fff;
4905 if (type & MSR_TYPE_R)
4906 /* read-high */
4907 __clear_bit(msr, msr_bitmap + 0x400 / f);
4908
4909 if (type & MSR_TYPE_W)
4910 /* write-high */
4911 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4912
4913 }
4914 }
4915
4916 /*
4917 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4918 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4919 */
4920 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4921 unsigned long *msr_bitmap_nested,
4922 u32 msr, int type)
4923 {
4924 int f = sizeof(unsigned long);
4925
4926 if (!cpu_has_vmx_msr_bitmap()) {
4927 WARN_ON(1);
4928 return;
4929 }
4930
4931 /*
4932 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4933 * have the write-low and read-high bitmap offsets the wrong way round.
4934 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4935 */
4936 if (msr <= 0x1fff) {
4937 if (type & MSR_TYPE_R &&
4938 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4939 /* read-low */
4940 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4941
4942 if (type & MSR_TYPE_W &&
4943 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4944 /* write-low */
4945 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4946
4947 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4948 msr &= 0x1fff;
4949 if (type & MSR_TYPE_R &&
4950 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4951 /* read-high */
4952 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4953
4954 if (type & MSR_TYPE_W &&
4955 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4956 /* write-high */
4957 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4958
4959 }
4960 }
4961
4962 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4963 {
4964 if (!longmode_only)
4965 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4966 msr, MSR_TYPE_R | MSR_TYPE_W);
4967 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4968 msr, MSR_TYPE_R | MSR_TYPE_W);
4969 }
4970
4971 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4972 {
4973 if (apicv_active) {
4974 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4975 msr, type);
4976 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4977 msr, type);
4978 } else {
4979 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4980 msr, type);
4981 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4982 msr, type);
4983 }
4984 }
4985
4986 static bool vmx_get_enable_apicv(void)
4987 {
4988 return enable_apicv;
4989 }
4990
4991 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
4992 {
4993 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4994 gfn_t gfn;
4995
4996 /*
4997 * Don't need to mark the APIC access page dirty; it is never
4998 * written to by the CPU during APIC virtualization.
4999 */
5000
5001 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5002 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5003 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5004 }
5005
5006 if (nested_cpu_has_posted_intr(vmcs12)) {
5007 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5008 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5009 }
5010 }
5011
5012
5013 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5014 {
5015 struct vcpu_vmx *vmx = to_vmx(vcpu);
5016 int max_irr;
5017 void *vapic_page;
5018 u16 status;
5019
5020 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5021 return;
5022
5023 vmx->nested.pi_pending = false;
5024 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5025 return;
5026
5027 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5028 if (max_irr != 256) {
5029 vapic_page = kmap(vmx->nested.virtual_apic_page);
5030 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5031 kunmap(vmx->nested.virtual_apic_page);
5032
5033 status = vmcs_read16(GUEST_INTR_STATUS);
5034 if ((u8)max_irr > ((u8)status & 0xff)) {
5035 status &= ~0xff;
5036 status |= (u8)max_irr;
5037 vmcs_write16(GUEST_INTR_STATUS, status);
5038 }
5039 }
5040
5041 nested_mark_vmcs12_pages_dirty(vcpu);
5042 }
5043
5044 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5045 bool nested)
5046 {
5047 #ifdef CONFIG_SMP
5048 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5049
5050 if (vcpu->mode == IN_GUEST_MODE) {
5051 struct vcpu_vmx *vmx = to_vmx(vcpu);
5052
5053 /*
5054 * Currently, we don't support urgent interrupt,
5055 * all interrupts are recognized as non-urgent
5056 * interrupt, so we cannot post interrupts when
5057 * 'SN' is set.
5058 *
5059 * If the vcpu is in guest mode, it means it is
5060 * running instead of being scheduled out and
5061 * waiting in the run queue, and that's the only
5062 * case when 'SN' is set currently, warning if
5063 * 'SN' is set.
5064 */
5065 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5066
5067 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5068 return true;
5069 }
5070 #endif
5071 return false;
5072 }
5073
5074 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5075 int vector)
5076 {
5077 struct vcpu_vmx *vmx = to_vmx(vcpu);
5078
5079 if (is_guest_mode(vcpu) &&
5080 vector == vmx->nested.posted_intr_nv) {
5081 /* the PIR and ON have been set by L1. */
5082 kvm_vcpu_trigger_posted_interrupt(vcpu, true);
5083 /*
5084 * If a posted intr is not recognized by hardware,
5085 * we will accomplish it in the next vmentry.
5086 */
5087 vmx->nested.pi_pending = true;
5088 kvm_make_request(KVM_REQ_EVENT, vcpu);
5089 return 0;
5090 }
5091 return -1;
5092 }
5093 /*
5094 * Send interrupt to vcpu via posted interrupt way.
5095 * 1. If target vcpu is running(non-root mode), send posted interrupt
5096 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5097 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5098 * interrupt from PIR in next vmentry.
5099 */
5100 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5101 {
5102 struct vcpu_vmx *vmx = to_vmx(vcpu);
5103 int r;
5104
5105 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5106 if (!r)
5107 return;
5108
5109 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5110 return;
5111
5112 /* If a previous notification has sent the IPI, nothing to do. */
5113 if (pi_test_and_set_on(&vmx->pi_desc))
5114 return;
5115
5116 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5117 kvm_vcpu_kick(vcpu);
5118 }
5119
5120 /*
5121 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5122 * will not change in the lifetime of the guest.
5123 * Note that host-state that does change is set elsewhere. E.g., host-state
5124 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5125 */
5126 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5127 {
5128 u32 low32, high32;
5129 unsigned long tmpl;
5130 struct desc_ptr dt;
5131 unsigned long cr0, cr3, cr4;
5132
5133 cr0 = read_cr0();
5134 WARN_ON(cr0 & X86_CR0_TS);
5135 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5136
5137 /*
5138 * Save the most likely value for this task's CR3 in the VMCS.
5139 * We can't use __get_current_cr3_fast() because we're not atomic.
5140 */
5141 cr3 = __read_cr3();
5142 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5143 vmx->host_state.vmcs_host_cr3 = cr3;
5144
5145 /* Save the most likely value for this task's CR4 in the VMCS. */
5146 cr4 = cr4_read_shadow();
5147 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5148 vmx->host_state.vmcs_host_cr4 = cr4;
5149
5150 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5151 #ifdef CONFIG_X86_64
5152 /*
5153 * Load null selectors, so we can avoid reloading them in
5154 * __vmx_load_host_state(), in case userspace uses the null selectors
5155 * too (the expected case).
5156 */
5157 vmcs_write16(HOST_DS_SELECTOR, 0);
5158 vmcs_write16(HOST_ES_SELECTOR, 0);
5159 #else
5160 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5161 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5162 #endif
5163 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5164 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5165
5166 native_store_idt(&dt);
5167 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5168 vmx->host_idt_base = dt.address;
5169
5170 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5171
5172 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5173 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5174 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5175 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5176
5177 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5178 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5179 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5180 }
5181 }
5182
5183 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5184 {
5185 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5186 if (enable_ept)
5187 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5188 if (is_guest_mode(&vmx->vcpu))
5189 vmx->vcpu.arch.cr4_guest_owned_bits &=
5190 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5191 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5192 }
5193
5194 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5195 {
5196 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5197
5198 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5199 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5200 /* Enable the preemption timer dynamically */
5201 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5202 return pin_based_exec_ctrl;
5203 }
5204
5205 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5206 {
5207 struct vcpu_vmx *vmx = to_vmx(vcpu);
5208
5209 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5210 if (cpu_has_secondary_exec_ctrls()) {
5211 if (kvm_vcpu_apicv_active(vcpu))
5212 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5213 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5214 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5215 else
5216 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5217 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5218 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5219 }
5220
5221 if (cpu_has_vmx_msr_bitmap())
5222 vmx_set_msr_bitmap(vcpu);
5223 }
5224
5225 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5226 {
5227 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5228
5229 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5230 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5231
5232 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5233 exec_control &= ~CPU_BASED_TPR_SHADOW;
5234 #ifdef CONFIG_X86_64
5235 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5236 CPU_BASED_CR8_LOAD_EXITING;
5237 #endif
5238 }
5239 if (!enable_ept)
5240 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5241 CPU_BASED_CR3_LOAD_EXITING |
5242 CPU_BASED_INVLPG_EXITING;
5243 return exec_control;
5244 }
5245
5246 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5247 {
5248 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5249 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5250 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5251 if (vmx->vpid == 0)
5252 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5253 if (!enable_ept) {
5254 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5255 enable_unrestricted_guest = 0;
5256 /* Enable INVPCID for non-ept guests may cause performance regression. */
5257 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5258 }
5259 if (!enable_unrestricted_guest)
5260 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5261 if (!ple_gap)
5262 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5263 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5264 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5265 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5266 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5267 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5268 (handle_vmptrld).
5269 We can NOT enable shadow_vmcs here because we don't have yet
5270 a current VMCS12
5271 */
5272 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5273
5274 if (!enable_pml)
5275 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5276
5277 return exec_control;
5278 }
5279
5280 static void ept_set_mmio_spte_mask(void)
5281 {
5282 /*
5283 * EPT Misconfigurations can be generated if the value of bits 2:0
5284 * of an EPT paging-structure entry is 110b (write/execute).
5285 */
5286 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5287 VMX_EPT_MISCONFIG_WX_VALUE);
5288 }
5289
5290 #define VMX_XSS_EXIT_BITMAP 0
5291 /*
5292 * Sets up the vmcs for emulated real mode.
5293 */
5294 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5295 {
5296 #ifdef CONFIG_X86_64
5297 unsigned long a;
5298 #endif
5299 int i;
5300
5301 /* I/O */
5302 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5303 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5304
5305 if (enable_shadow_vmcs) {
5306 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5307 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5308 }
5309 if (cpu_has_vmx_msr_bitmap())
5310 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5311
5312 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5313
5314 /* Control */
5315 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5316 vmx->hv_deadline_tsc = -1;
5317
5318 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5319
5320 if (cpu_has_secondary_exec_ctrls()) {
5321 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5322 vmx_secondary_exec_control(vmx));
5323 }
5324
5325 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5326 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5327 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5328 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5329 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5330
5331 vmcs_write16(GUEST_INTR_STATUS, 0);
5332
5333 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5334 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5335 }
5336
5337 if (ple_gap) {
5338 vmcs_write32(PLE_GAP, ple_gap);
5339 vmx->ple_window = ple_window;
5340 vmx->ple_window_dirty = true;
5341 }
5342
5343 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5344 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5345 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5346
5347 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5348 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5349 vmx_set_constant_host_state(vmx);
5350 #ifdef CONFIG_X86_64
5351 rdmsrl(MSR_FS_BASE, a);
5352 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5353 rdmsrl(MSR_GS_BASE, a);
5354 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5355 #else
5356 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5357 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5358 #endif
5359
5360 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5361 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5362 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5363 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5364 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5365
5366 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5367 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5368
5369 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5370 u32 index = vmx_msr_index[i];
5371 u32 data_low, data_high;
5372 int j = vmx->nmsrs;
5373
5374 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5375 continue;
5376 if (wrmsr_safe(index, data_low, data_high) < 0)
5377 continue;
5378 vmx->guest_msrs[j].index = i;
5379 vmx->guest_msrs[j].data = 0;
5380 vmx->guest_msrs[j].mask = -1ull;
5381 ++vmx->nmsrs;
5382 }
5383
5384
5385 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5386
5387 /* 22.2.1, 20.8.1 */
5388 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5389
5390 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5391 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5392
5393 set_cr4_guest_host_mask(vmx);
5394
5395 if (vmx_xsaves_supported())
5396 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5397
5398 if (enable_pml) {
5399 ASSERT(vmx->pml_pg);
5400 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5401 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5402 }
5403
5404 return 0;
5405 }
5406
5407 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5408 {
5409 struct vcpu_vmx *vmx = to_vmx(vcpu);
5410 struct msr_data apic_base_msr;
5411 u64 cr0;
5412
5413 vmx->rmode.vm86_active = 0;
5414
5415 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5416 kvm_set_cr8(vcpu, 0);
5417
5418 if (!init_event) {
5419 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5420 MSR_IA32_APICBASE_ENABLE;
5421 if (kvm_vcpu_is_reset_bsp(vcpu))
5422 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5423 apic_base_msr.host_initiated = true;
5424 kvm_set_apic_base(vcpu, &apic_base_msr);
5425 }
5426
5427 vmx_segment_cache_clear(vmx);
5428
5429 seg_setup(VCPU_SREG_CS);
5430 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5431 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5432
5433 seg_setup(VCPU_SREG_DS);
5434 seg_setup(VCPU_SREG_ES);
5435 seg_setup(VCPU_SREG_FS);
5436 seg_setup(VCPU_SREG_GS);
5437 seg_setup(VCPU_SREG_SS);
5438
5439 vmcs_write16(GUEST_TR_SELECTOR, 0);
5440 vmcs_writel(GUEST_TR_BASE, 0);
5441 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5442 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5443
5444 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5445 vmcs_writel(GUEST_LDTR_BASE, 0);
5446 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5447 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5448
5449 if (!init_event) {
5450 vmcs_write32(GUEST_SYSENTER_CS, 0);
5451 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5452 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5453 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5454 }
5455
5456 vmcs_writel(GUEST_RFLAGS, 0x02);
5457 kvm_rip_write(vcpu, 0xfff0);
5458
5459 vmcs_writel(GUEST_GDTR_BASE, 0);
5460 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5461
5462 vmcs_writel(GUEST_IDTR_BASE, 0);
5463 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5464
5465 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5466 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5467 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5468
5469 setup_msrs(vmx);
5470
5471 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5472
5473 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5474 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5475 if (cpu_need_tpr_shadow(vcpu))
5476 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5477 __pa(vcpu->arch.apic->regs));
5478 vmcs_write32(TPR_THRESHOLD, 0);
5479 }
5480
5481 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5482
5483 if (kvm_vcpu_apicv_active(vcpu))
5484 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5485
5486 if (vmx->vpid != 0)
5487 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5488
5489 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5490 vmx->vcpu.arch.cr0 = cr0;
5491 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5492 vmx_set_cr4(vcpu, 0);
5493 vmx_set_efer(vcpu, 0);
5494
5495 update_exception_bitmap(vcpu);
5496
5497 vpid_sync_context(vmx->vpid);
5498 }
5499
5500 /*
5501 * In nested virtualization, check if L1 asked to exit on external interrupts.
5502 * For most existing hypervisors, this will always return true.
5503 */
5504 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5505 {
5506 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5507 PIN_BASED_EXT_INTR_MASK;
5508 }
5509
5510 /*
5511 * In nested virtualization, check if L1 has set
5512 * VM_EXIT_ACK_INTR_ON_EXIT
5513 */
5514 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5515 {
5516 return get_vmcs12(vcpu)->vm_exit_controls &
5517 VM_EXIT_ACK_INTR_ON_EXIT;
5518 }
5519
5520 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5521 {
5522 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5523 PIN_BASED_NMI_EXITING;
5524 }
5525
5526 static void enable_irq_window(struct kvm_vcpu *vcpu)
5527 {
5528 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5529 CPU_BASED_VIRTUAL_INTR_PENDING);
5530 }
5531
5532 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5533 {
5534 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5535 enable_irq_window(vcpu);
5536 return;
5537 }
5538
5539 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5540 CPU_BASED_VIRTUAL_NMI_PENDING);
5541 }
5542
5543 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5544 {
5545 struct vcpu_vmx *vmx = to_vmx(vcpu);
5546 uint32_t intr;
5547 int irq = vcpu->arch.interrupt.nr;
5548
5549 trace_kvm_inj_virq(irq);
5550
5551 ++vcpu->stat.irq_injections;
5552 if (vmx->rmode.vm86_active) {
5553 int inc_eip = 0;
5554 if (vcpu->arch.interrupt.soft)
5555 inc_eip = vcpu->arch.event_exit_inst_len;
5556 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5557 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5558 return;
5559 }
5560 intr = irq | INTR_INFO_VALID_MASK;
5561 if (vcpu->arch.interrupt.soft) {
5562 intr |= INTR_TYPE_SOFT_INTR;
5563 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5564 vmx->vcpu.arch.event_exit_inst_len);
5565 } else
5566 intr |= INTR_TYPE_EXT_INTR;
5567 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5568 }
5569
5570 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5571 {
5572 struct vcpu_vmx *vmx = to_vmx(vcpu);
5573
5574 ++vcpu->stat.nmi_injections;
5575 vmx->loaded_vmcs->nmi_known_unmasked = false;
5576
5577 if (vmx->rmode.vm86_active) {
5578 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5579 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5580 return;
5581 }
5582
5583 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5584 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5585 }
5586
5587 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5588 {
5589 struct vcpu_vmx *vmx = to_vmx(vcpu);
5590 bool masked;
5591
5592 if (vmx->loaded_vmcs->nmi_known_unmasked)
5593 return false;
5594 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5595 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5596 return masked;
5597 }
5598
5599 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5600 {
5601 struct vcpu_vmx *vmx = to_vmx(vcpu);
5602
5603 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5604 if (masked)
5605 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5606 GUEST_INTR_STATE_NMI);
5607 else
5608 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5609 GUEST_INTR_STATE_NMI);
5610 }
5611
5612 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5613 {
5614 if (to_vmx(vcpu)->nested.nested_run_pending)
5615 return 0;
5616
5617 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5618 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5619 | GUEST_INTR_STATE_NMI));
5620 }
5621
5622 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5623 {
5624 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5625 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5626 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5627 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5628 }
5629
5630 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5631 {
5632 int ret;
5633
5634 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5635 PAGE_SIZE * 3);
5636 if (ret)
5637 return ret;
5638 kvm->arch.tss_addr = addr;
5639 return init_rmode_tss(kvm);
5640 }
5641
5642 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5643 {
5644 switch (vec) {
5645 case BP_VECTOR:
5646 /*
5647 * Update instruction length as we may reinject the exception
5648 * from user space while in guest debugging mode.
5649 */
5650 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5651 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5652 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5653 return false;
5654 /* fall through */
5655 case DB_VECTOR:
5656 if (vcpu->guest_debug &
5657 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5658 return false;
5659 /* fall through */
5660 case DE_VECTOR:
5661 case OF_VECTOR:
5662 case BR_VECTOR:
5663 case UD_VECTOR:
5664 case DF_VECTOR:
5665 case SS_VECTOR:
5666 case GP_VECTOR:
5667 case MF_VECTOR:
5668 return true;
5669 break;
5670 }
5671 return false;
5672 }
5673
5674 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5675 int vec, u32 err_code)
5676 {
5677 /*
5678 * Instruction with address size override prefix opcode 0x67
5679 * Cause the #SS fault with 0 error code in VM86 mode.
5680 */
5681 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5682 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5683 if (vcpu->arch.halt_request) {
5684 vcpu->arch.halt_request = 0;
5685 return kvm_vcpu_halt(vcpu);
5686 }
5687 return 1;
5688 }
5689 return 0;
5690 }
5691
5692 /*
5693 * Forward all other exceptions that are valid in real mode.
5694 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5695 * the required debugging infrastructure rework.
5696 */
5697 kvm_queue_exception(vcpu, vec);
5698 return 1;
5699 }
5700
5701 /*
5702 * Trigger machine check on the host. We assume all the MSRs are already set up
5703 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5704 * We pass a fake environment to the machine check handler because we want
5705 * the guest to be always treated like user space, no matter what context
5706 * it used internally.
5707 */
5708 static void kvm_machine_check(void)
5709 {
5710 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5711 struct pt_regs regs = {
5712 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5713 .flags = X86_EFLAGS_IF,
5714 };
5715
5716 do_machine_check(&regs, 0);
5717 #endif
5718 }
5719
5720 static int handle_machine_check(struct kvm_vcpu *vcpu)
5721 {
5722 /* already handled by vcpu_run */
5723 return 1;
5724 }
5725
5726 static int handle_exception(struct kvm_vcpu *vcpu)
5727 {
5728 struct vcpu_vmx *vmx = to_vmx(vcpu);
5729 struct kvm_run *kvm_run = vcpu->run;
5730 u32 intr_info, ex_no, error_code;
5731 unsigned long cr2, rip, dr6;
5732 u32 vect_info;
5733 enum emulation_result er;
5734
5735 vect_info = vmx->idt_vectoring_info;
5736 intr_info = vmx->exit_intr_info;
5737
5738 if (is_machine_check(intr_info))
5739 return handle_machine_check(vcpu);
5740
5741 if (is_nmi(intr_info))
5742 return 1; /* already handled by vmx_vcpu_run() */
5743
5744 if (is_invalid_opcode(intr_info)) {
5745 if (is_guest_mode(vcpu)) {
5746 kvm_queue_exception(vcpu, UD_VECTOR);
5747 return 1;
5748 }
5749 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5750 if (er != EMULATE_DONE)
5751 kvm_queue_exception(vcpu, UD_VECTOR);
5752 return 1;
5753 }
5754
5755 error_code = 0;
5756 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5757 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5758
5759 /*
5760 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5761 * MMIO, it is better to report an internal error.
5762 * See the comments in vmx_handle_exit.
5763 */
5764 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5765 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5766 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5767 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5768 vcpu->run->internal.ndata = 3;
5769 vcpu->run->internal.data[0] = vect_info;
5770 vcpu->run->internal.data[1] = intr_info;
5771 vcpu->run->internal.data[2] = error_code;
5772 return 0;
5773 }
5774
5775 if (is_page_fault(intr_info)) {
5776 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5777 /* EPT won't cause page fault directly */
5778 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5779 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5780 true);
5781 }
5782
5783 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5784
5785 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5786 return handle_rmode_exception(vcpu, ex_no, error_code);
5787
5788 switch (ex_no) {
5789 case AC_VECTOR:
5790 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5791 return 1;
5792 case DB_VECTOR:
5793 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5794 if (!(vcpu->guest_debug &
5795 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5796 vcpu->arch.dr6 &= ~15;
5797 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5798 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5799 skip_emulated_instruction(vcpu);
5800
5801 kvm_queue_exception(vcpu, DB_VECTOR);
5802 return 1;
5803 }
5804 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5805 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5806 /* fall through */
5807 case BP_VECTOR:
5808 /*
5809 * Update instruction length as we may reinject #BP from
5810 * user space while in guest debugging mode. Reading it for
5811 * #DB as well causes no harm, it is not used in that case.
5812 */
5813 vmx->vcpu.arch.event_exit_inst_len =
5814 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5815 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5816 rip = kvm_rip_read(vcpu);
5817 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5818 kvm_run->debug.arch.exception = ex_no;
5819 break;
5820 default:
5821 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5822 kvm_run->ex.exception = ex_no;
5823 kvm_run->ex.error_code = error_code;
5824 break;
5825 }
5826 return 0;
5827 }
5828
5829 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5830 {
5831 ++vcpu->stat.irq_exits;
5832 return 1;
5833 }
5834
5835 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5836 {
5837 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5838 return 0;
5839 }
5840
5841 static int handle_io(struct kvm_vcpu *vcpu)
5842 {
5843 unsigned long exit_qualification;
5844 int size, in, string, ret;
5845 unsigned port;
5846
5847 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5848 string = (exit_qualification & 16) != 0;
5849 in = (exit_qualification & 8) != 0;
5850
5851 ++vcpu->stat.io_exits;
5852
5853 if (string || in)
5854 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5855
5856 port = exit_qualification >> 16;
5857 size = (exit_qualification & 7) + 1;
5858
5859 ret = kvm_skip_emulated_instruction(vcpu);
5860
5861 /*
5862 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5863 * KVM_EXIT_DEBUG here.
5864 */
5865 return kvm_fast_pio_out(vcpu, size, port) && ret;
5866 }
5867
5868 static void
5869 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5870 {
5871 /*
5872 * Patch in the VMCALL instruction:
5873 */
5874 hypercall[0] = 0x0f;
5875 hypercall[1] = 0x01;
5876 hypercall[2] = 0xc1;
5877 }
5878
5879 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5880 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5881 {
5882 if (is_guest_mode(vcpu)) {
5883 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5884 unsigned long orig_val = val;
5885
5886 /*
5887 * We get here when L2 changed cr0 in a way that did not change
5888 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5889 * but did change L0 shadowed bits. So we first calculate the
5890 * effective cr0 value that L1 would like to write into the
5891 * hardware. It consists of the L2-owned bits from the new
5892 * value combined with the L1-owned bits from L1's guest_cr0.
5893 */
5894 val = (val & ~vmcs12->cr0_guest_host_mask) |
5895 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5896
5897 if (!nested_guest_cr0_valid(vcpu, val))
5898 return 1;
5899
5900 if (kvm_set_cr0(vcpu, val))
5901 return 1;
5902 vmcs_writel(CR0_READ_SHADOW, orig_val);
5903 return 0;
5904 } else {
5905 if (to_vmx(vcpu)->nested.vmxon &&
5906 !nested_host_cr0_valid(vcpu, val))
5907 return 1;
5908
5909 return kvm_set_cr0(vcpu, val);
5910 }
5911 }
5912
5913 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5914 {
5915 if (is_guest_mode(vcpu)) {
5916 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5917 unsigned long orig_val = val;
5918
5919 /* analogously to handle_set_cr0 */
5920 val = (val & ~vmcs12->cr4_guest_host_mask) |
5921 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5922 if (kvm_set_cr4(vcpu, val))
5923 return 1;
5924 vmcs_writel(CR4_READ_SHADOW, orig_val);
5925 return 0;
5926 } else
5927 return kvm_set_cr4(vcpu, val);
5928 }
5929
5930 static int handle_cr(struct kvm_vcpu *vcpu)
5931 {
5932 unsigned long exit_qualification, val;
5933 int cr;
5934 int reg;
5935 int err;
5936 int ret;
5937
5938 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5939 cr = exit_qualification & 15;
5940 reg = (exit_qualification >> 8) & 15;
5941 switch ((exit_qualification >> 4) & 3) {
5942 case 0: /* mov to cr */
5943 val = kvm_register_readl(vcpu, reg);
5944 trace_kvm_cr_write(cr, val);
5945 switch (cr) {
5946 case 0:
5947 err = handle_set_cr0(vcpu, val);
5948 return kvm_complete_insn_gp(vcpu, err);
5949 case 3:
5950 err = kvm_set_cr3(vcpu, val);
5951 return kvm_complete_insn_gp(vcpu, err);
5952 case 4:
5953 err = handle_set_cr4(vcpu, val);
5954 return kvm_complete_insn_gp(vcpu, err);
5955 case 8: {
5956 u8 cr8_prev = kvm_get_cr8(vcpu);
5957 u8 cr8 = (u8)val;
5958 err = kvm_set_cr8(vcpu, cr8);
5959 ret = kvm_complete_insn_gp(vcpu, err);
5960 if (lapic_in_kernel(vcpu))
5961 return ret;
5962 if (cr8_prev <= cr8)
5963 return ret;
5964 /*
5965 * TODO: we might be squashing a
5966 * KVM_GUESTDBG_SINGLESTEP-triggered
5967 * KVM_EXIT_DEBUG here.
5968 */
5969 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5970 return 0;
5971 }
5972 }
5973 break;
5974 case 2: /* clts */
5975 WARN_ONCE(1, "Guest should always own CR0.TS");
5976 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5977 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5978 return kvm_skip_emulated_instruction(vcpu);
5979 case 1: /*mov from cr*/
5980 switch (cr) {
5981 case 3:
5982 val = kvm_read_cr3(vcpu);
5983 kvm_register_write(vcpu, reg, val);
5984 trace_kvm_cr_read(cr, val);
5985 return kvm_skip_emulated_instruction(vcpu);
5986 case 8:
5987 val = kvm_get_cr8(vcpu);
5988 kvm_register_write(vcpu, reg, val);
5989 trace_kvm_cr_read(cr, val);
5990 return kvm_skip_emulated_instruction(vcpu);
5991 }
5992 break;
5993 case 3: /* lmsw */
5994 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5995 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5996 kvm_lmsw(vcpu, val);
5997
5998 return kvm_skip_emulated_instruction(vcpu);
5999 default:
6000 break;
6001 }
6002 vcpu->run->exit_reason = 0;
6003 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6004 (int)(exit_qualification >> 4) & 3, cr);
6005 return 0;
6006 }
6007
6008 static int handle_dr(struct kvm_vcpu *vcpu)
6009 {
6010 unsigned long exit_qualification;
6011 int dr, dr7, reg;
6012
6013 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6014 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6015
6016 /* First, if DR does not exist, trigger UD */
6017 if (!kvm_require_dr(vcpu, dr))
6018 return 1;
6019
6020 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6021 if (!kvm_require_cpl(vcpu, 0))
6022 return 1;
6023 dr7 = vmcs_readl(GUEST_DR7);
6024 if (dr7 & DR7_GD) {
6025 /*
6026 * As the vm-exit takes precedence over the debug trap, we
6027 * need to emulate the latter, either for the host or the
6028 * guest debugging itself.
6029 */
6030 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6031 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6032 vcpu->run->debug.arch.dr7 = dr7;
6033 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6034 vcpu->run->debug.arch.exception = DB_VECTOR;
6035 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6036 return 0;
6037 } else {
6038 vcpu->arch.dr6 &= ~15;
6039 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6040 kvm_queue_exception(vcpu, DB_VECTOR);
6041 return 1;
6042 }
6043 }
6044
6045 if (vcpu->guest_debug == 0) {
6046 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6047 CPU_BASED_MOV_DR_EXITING);
6048
6049 /*
6050 * No more DR vmexits; force a reload of the debug registers
6051 * and reenter on this instruction. The next vmexit will
6052 * retrieve the full state of the debug registers.
6053 */
6054 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6055 return 1;
6056 }
6057
6058 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6059 if (exit_qualification & TYPE_MOV_FROM_DR) {
6060 unsigned long val;
6061
6062 if (kvm_get_dr(vcpu, dr, &val))
6063 return 1;
6064 kvm_register_write(vcpu, reg, val);
6065 } else
6066 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6067 return 1;
6068
6069 return kvm_skip_emulated_instruction(vcpu);
6070 }
6071
6072 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6073 {
6074 return vcpu->arch.dr6;
6075 }
6076
6077 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6078 {
6079 }
6080
6081 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6082 {
6083 get_debugreg(vcpu->arch.db[0], 0);
6084 get_debugreg(vcpu->arch.db[1], 1);
6085 get_debugreg(vcpu->arch.db[2], 2);
6086 get_debugreg(vcpu->arch.db[3], 3);
6087 get_debugreg(vcpu->arch.dr6, 6);
6088 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6089
6090 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6091 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6092 }
6093
6094 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6095 {
6096 vmcs_writel(GUEST_DR7, val);
6097 }
6098
6099 static int handle_cpuid(struct kvm_vcpu *vcpu)
6100 {
6101 return kvm_emulate_cpuid(vcpu);
6102 }
6103
6104 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6105 {
6106 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6107 struct msr_data msr_info;
6108
6109 msr_info.index = ecx;
6110 msr_info.host_initiated = false;
6111 if (vmx_get_msr(vcpu, &msr_info)) {
6112 trace_kvm_msr_read_ex(ecx);
6113 kvm_inject_gp(vcpu, 0);
6114 return 1;
6115 }
6116
6117 trace_kvm_msr_read(ecx, msr_info.data);
6118
6119 /* FIXME: handling of bits 32:63 of rax, rdx */
6120 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6121 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6122 return kvm_skip_emulated_instruction(vcpu);
6123 }
6124
6125 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6126 {
6127 struct msr_data msr;
6128 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6129 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6130 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6131
6132 msr.data = data;
6133 msr.index = ecx;
6134 msr.host_initiated = false;
6135 if (kvm_set_msr(vcpu, &msr) != 0) {
6136 trace_kvm_msr_write_ex(ecx, data);
6137 kvm_inject_gp(vcpu, 0);
6138 return 1;
6139 }
6140
6141 trace_kvm_msr_write(ecx, data);
6142 return kvm_skip_emulated_instruction(vcpu);
6143 }
6144
6145 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6146 {
6147 kvm_apic_update_ppr(vcpu);
6148 return 1;
6149 }
6150
6151 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6152 {
6153 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6154 CPU_BASED_VIRTUAL_INTR_PENDING);
6155
6156 kvm_make_request(KVM_REQ_EVENT, vcpu);
6157
6158 ++vcpu->stat.irq_window_exits;
6159 return 1;
6160 }
6161
6162 static int handle_halt(struct kvm_vcpu *vcpu)
6163 {
6164 return kvm_emulate_halt(vcpu);
6165 }
6166
6167 static int handle_vmcall(struct kvm_vcpu *vcpu)
6168 {
6169 return kvm_emulate_hypercall(vcpu);
6170 }
6171
6172 static int handle_invd(struct kvm_vcpu *vcpu)
6173 {
6174 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6175 }
6176
6177 static int handle_invlpg(struct kvm_vcpu *vcpu)
6178 {
6179 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6180
6181 kvm_mmu_invlpg(vcpu, exit_qualification);
6182 return kvm_skip_emulated_instruction(vcpu);
6183 }
6184
6185 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6186 {
6187 int err;
6188
6189 err = kvm_rdpmc(vcpu);
6190 return kvm_complete_insn_gp(vcpu, err);
6191 }
6192
6193 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6194 {
6195 return kvm_emulate_wbinvd(vcpu);
6196 }
6197
6198 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6199 {
6200 u64 new_bv = kvm_read_edx_eax(vcpu);
6201 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6202
6203 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6204 return kvm_skip_emulated_instruction(vcpu);
6205 return 1;
6206 }
6207
6208 static int handle_xsaves(struct kvm_vcpu *vcpu)
6209 {
6210 kvm_skip_emulated_instruction(vcpu);
6211 WARN(1, "this should never happen\n");
6212 return 1;
6213 }
6214
6215 static int handle_xrstors(struct kvm_vcpu *vcpu)
6216 {
6217 kvm_skip_emulated_instruction(vcpu);
6218 WARN(1, "this should never happen\n");
6219 return 1;
6220 }
6221
6222 static int handle_apic_access(struct kvm_vcpu *vcpu)
6223 {
6224 if (likely(fasteoi)) {
6225 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6226 int access_type, offset;
6227
6228 access_type = exit_qualification & APIC_ACCESS_TYPE;
6229 offset = exit_qualification & APIC_ACCESS_OFFSET;
6230 /*
6231 * Sane guest uses MOV to write EOI, with written value
6232 * not cared. So make a short-circuit here by avoiding
6233 * heavy instruction emulation.
6234 */
6235 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6236 (offset == APIC_EOI)) {
6237 kvm_lapic_set_eoi(vcpu);
6238 return kvm_skip_emulated_instruction(vcpu);
6239 }
6240 }
6241 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6242 }
6243
6244 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6245 {
6246 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6247 int vector = exit_qualification & 0xff;
6248
6249 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6250 kvm_apic_set_eoi_accelerated(vcpu, vector);
6251 return 1;
6252 }
6253
6254 static int handle_apic_write(struct kvm_vcpu *vcpu)
6255 {
6256 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6257 u32 offset = exit_qualification & 0xfff;
6258
6259 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6260 kvm_apic_write_nodecode(vcpu, offset);
6261 return 1;
6262 }
6263
6264 static int handle_task_switch(struct kvm_vcpu *vcpu)
6265 {
6266 struct vcpu_vmx *vmx = to_vmx(vcpu);
6267 unsigned long exit_qualification;
6268 bool has_error_code = false;
6269 u32 error_code = 0;
6270 u16 tss_selector;
6271 int reason, type, idt_v, idt_index;
6272
6273 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6274 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6275 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6276
6277 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6278
6279 reason = (u32)exit_qualification >> 30;
6280 if (reason == TASK_SWITCH_GATE && idt_v) {
6281 switch (type) {
6282 case INTR_TYPE_NMI_INTR:
6283 vcpu->arch.nmi_injected = false;
6284 vmx_set_nmi_mask(vcpu, true);
6285 break;
6286 case INTR_TYPE_EXT_INTR:
6287 case INTR_TYPE_SOFT_INTR:
6288 kvm_clear_interrupt_queue(vcpu);
6289 break;
6290 case INTR_TYPE_HARD_EXCEPTION:
6291 if (vmx->idt_vectoring_info &
6292 VECTORING_INFO_DELIVER_CODE_MASK) {
6293 has_error_code = true;
6294 error_code =
6295 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6296 }
6297 /* fall through */
6298 case INTR_TYPE_SOFT_EXCEPTION:
6299 kvm_clear_exception_queue(vcpu);
6300 break;
6301 default:
6302 break;
6303 }
6304 }
6305 tss_selector = exit_qualification;
6306
6307 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6308 type != INTR_TYPE_EXT_INTR &&
6309 type != INTR_TYPE_NMI_INTR))
6310 skip_emulated_instruction(vcpu);
6311
6312 if (kvm_task_switch(vcpu, tss_selector,
6313 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6314 has_error_code, error_code) == EMULATE_FAIL) {
6315 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6316 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6317 vcpu->run->internal.ndata = 0;
6318 return 0;
6319 }
6320
6321 /*
6322 * TODO: What about debug traps on tss switch?
6323 * Are we supposed to inject them and update dr6?
6324 */
6325
6326 return 1;
6327 }
6328
6329 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6330 {
6331 unsigned long exit_qualification;
6332 gpa_t gpa;
6333 u32 error_code;
6334
6335 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6336
6337 /*
6338 * EPT violation happened while executing iret from NMI,
6339 * "blocked by NMI" bit has to be set before next VM entry.
6340 * There are errata that may cause this bit to not be set:
6341 * AAK134, BY25.
6342 */
6343 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6344 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6345 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6346
6347 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6348 trace_kvm_page_fault(gpa, exit_qualification);
6349
6350 /* Is it a read fault? */
6351 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6352 ? PFERR_USER_MASK : 0;
6353 /* Is it a write fault? */
6354 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6355 ? PFERR_WRITE_MASK : 0;
6356 /* Is it a fetch fault? */
6357 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6358 ? PFERR_FETCH_MASK : 0;
6359 /* ept page table entry is present? */
6360 error_code |= (exit_qualification &
6361 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6362 EPT_VIOLATION_EXECUTABLE))
6363 ? PFERR_PRESENT_MASK : 0;
6364
6365 vcpu->arch.gpa_available = true;
6366 vcpu->arch.exit_qualification = exit_qualification;
6367
6368 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6369 }
6370
6371 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6372 {
6373 int ret;
6374 gpa_t gpa;
6375
6376 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6377 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6378 trace_kvm_fast_mmio(gpa);
6379 return kvm_skip_emulated_instruction(vcpu);
6380 }
6381
6382 ret = handle_mmio_page_fault(vcpu, gpa, true);
6383 vcpu->arch.gpa_available = true;
6384 if (likely(ret == RET_MMIO_PF_EMULATE))
6385 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6386 EMULATE_DONE;
6387
6388 if (unlikely(ret == RET_MMIO_PF_INVALID))
6389 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6390
6391 if (unlikely(ret == RET_MMIO_PF_RETRY))
6392 return 1;
6393
6394 /* It is the real ept misconfig */
6395 WARN_ON(1);
6396
6397 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6398 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6399
6400 return 0;
6401 }
6402
6403 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6404 {
6405 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6406 CPU_BASED_VIRTUAL_NMI_PENDING);
6407 ++vcpu->stat.nmi_window_exits;
6408 kvm_make_request(KVM_REQ_EVENT, vcpu);
6409
6410 return 1;
6411 }
6412
6413 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6414 {
6415 struct vcpu_vmx *vmx = to_vmx(vcpu);
6416 enum emulation_result err = EMULATE_DONE;
6417 int ret = 1;
6418 u32 cpu_exec_ctrl;
6419 bool intr_window_requested;
6420 unsigned count = 130;
6421
6422 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6423 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6424
6425 while (vmx->emulation_required && count-- != 0) {
6426 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6427 return handle_interrupt_window(&vmx->vcpu);
6428
6429 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6430 return 1;
6431
6432 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6433
6434 if (err == EMULATE_USER_EXIT) {
6435 ++vcpu->stat.mmio_exits;
6436 ret = 0;
6437 goto out;
6438 }
6439
6440 if (err != EMULATE_DONE) {
6441 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6442 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6443 vcpu->run->internal.ndata = 0;
6444 return 0;
6445 }
6446
6447 if (vcpu->arch.halt_request) {
6448 vcpu->arch.halt_request = 0;
6449 ret = kvm_vcpu_halt(vcpu);
6450 goto out;
6451 }
6452
6453 if (signal_pending(current))
6454 goto out;
6455 if (need_resched())
6456 schedule();
6457 }
6458
6459 out:
6460 return ret;
6461 }
6462
6463 static int __grow_ple_window(int val)
6464 {
6465 if (ple_window_grow < 1)
6466 return ple_window;
6467
6468 val = min(val, ple_window_actual_max);
6469
6470 if (ple_window_grow < ple_window)
6471 val *= ple_window_grow;
6472 else
6473 val += ple_window_grow;
6474
6475 return val;
6476 }
6477
6478 static int __shrink_ple_window(int val, int modifier, int minimum)
6479 {
6480 if (modifier < 1)
6481 return ple_window;
6482
6483 if (modifier < ple_window)
6484 val /= modifier;
6485 else
6486 val -= modifier;
6487
6488 return max(val, minimum);
6489 }
6490
6491 static void grow_ple_window(struct kvm_vcpu *vcpu)
6492 {
6493 struct vcpu_vmx *vmx = to_vmx(vcpu);
6494 int old = vmx->ple_window;
6495
6496 vmx->ple_window = __grow_ple_window(old);
6497
6498 if (vmx->ple_window != old)
6499 vmx->ple_window_dirty = true;
6500
6501 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6502 }
6503
6504 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6505 {
6506 struct vcpu_vmx *vmx = to_vmx(vcpu);
6507 int old = vmx->ple_window;
6508
6509 vmx->ple_window = __shrink_ple_window(old,
6510 ple_window_shrink, ple_window);
6511
6512 if (vmx->ple_window != old)
6513 vmx->ple_window_dirty = true;
6514
6515 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6516 }
6517
6518 /*
6519 * ple_window_actual_max is computed to be one grow_ple_window() below
6520 * ple_window_max. (See __grow_ple_window for the reason.)
6521 * This prevents overflows, because ple_window_max is int.
6522 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6523 * this process.
6524 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6525 */
6526 static void update_ple_window_actual_max(void)
6527 {
6528 ple_window_actual_max =
6529 __shrink_ple_window(max(ple_window_max, ple_window),
6530 ple_window_grow, INT_MIN);
6531 }
6532
6533 /*
6534 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6535 */
6536 static void wakeup_handler(void)
6537 {
6538 struct kvm_vcpu *vcpu;
6539 int cpu = smp_processor_id();
6540
6541 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6542 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6543 blocked_vcpu_list) {
6544 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6545
6546 if (pi_test_on(pi_desc) == 1)
6547 kvm_vcpu_kick(vcpu);
6548 }
6549 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6550 }
6551
6552 void vmx_enable_tdp(void)
6553 {
6554 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6555 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6556 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6557 0ull, VMX_EPT_EXECUTABLE_MASK,
6558 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6559 VMX_EPT_RWX_MASK);
6560
6561 ept_set_mmio_spte_mask();
6562 kvm_enable_tdp();
6563 }
6564
6565 static __init int hardware_setup(void)
6566 {
6567 int r = -ENOMEM, i, msr;
6568
6569 rdmsrl_safe(MSR_EFER, &host_efer);
6570
6571 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6572 kvm_define_shared_msr(i, vmx_msr_index[i]);
6573
6574 for (i = 0; i < VMX_BITMAP_NR; i++) {
6575 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6576 if (!vmx_bitmap[i])
6577 goto out;
6578 }
6579
6580 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6581 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6582 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6583
6584 /*
6585 * Allow direct access to the PC debug port (it is often used for I/O
6586 * delays, but the vmexits simply slow things down).
6587 */
6588 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6589 clear_bit(0x80, vmx_io_bitmap_a);
6590
6591 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6592
6593 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6594 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6595
6596 if (setup_vmcs_config(&vmcs_config) < 0) {
6597 r = -EIO;
6598 goto out;
6599 }
6600
6601 if (boot_cpu_has(X86_FEATURE_NX))
6602 kvm_enable_efer_bits(EFER_NX);
6603
6604 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6605 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6606 enable_vpid = 0;
6607
6608 if (!cpu_has_vmx_shadow_vmcs())
6609 enable_shadow_vmcs = 0;
6610 if (enable_shadow_vmcs)
6611 init_vmcs_shadow_fields();
6612
6613 if (!cpu_has_vmx_ept() ||
6614 !cpu_has_vmx_ept_4levels()) {
6615 enable_ept = 0;
6616 enable_unrestricted_guest = 0;
6617 enable_ept_ad_bits = 0;
6618 }
6619
6620 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6621 enable_ept_ad_bits = 0;
6622
6623 if (!cpu_has_vmx_unrestricted_guest())
6624 enable_unrestricted_guest = 0;
6625
6626 if (!cpu_has_vmx_flexpriority())
6627 flexpriority_enabled = 0;
6628
6629 /*
6630 * set_apic_access_page_addr() is used to reload apic access
6631 * page upon invalidation. No need to do anything if not
6632 * using the APIC_ACCESS_ADDR VMCS field.
6633 */
6634 if (!flexpriority_enabled)
6635 kvm_x86_ops->set_apic_access_page_addr = NULL;
6636
6637 if (!cpu_has_vmx_tpr_shadow())
6638 kvm_x86_ops->update_cr8_intercept = NULL;
6639
6640 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6641 kvm_disable_largepages();
6642
6643 if (!cpu_has_vmx_ple())
6644 ple_gap = 0;
6645
6646 if (!cpu_has_vmx_apicv()) {
6647 enable_apicv = 0;
6648 kvm_x86_ops->sync_pir_to_irr = NULL;
6649 }
6650
6651 if (cpu_has_vmx_tsc_scaling()) {
6652 kvm_has_tsc_control = true;
6653 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6654 kvm_tsc_scaling_ratio_frac_bits = 48;
6655 }
6656
6657 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6658 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6659 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6660 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6661 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6662 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6663
6664 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6665 vmx_msr_bitmap_legacy, PAGE_SIZE);
6666 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6667 vmx_msr_bitmap_longmode, PAGE_SIZE);
6668 memcpy(vmx_msr_bitmap_legacy_x2apic,
6669 vmx_msr_bitmap_legacy, PAGE_SIZE);
6670 memcpy(vmx_msr_bitmap_longmode_x2apic,
6671 vmx_msr_bitmap_longmode, PAGE_SIZE);
6672
6673 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6674
6675 for (msr = 0x800; msr <= 0x8ff; msr++) {
6676 if (msr == 0x839 /* TMCCT */)
6677 continue;
6678 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6679 }
6680
6681 /*
6682 * TPR reads and writes can be virtualized even if virtual interrupt
6683 * delivery is not in use.
6684 */
6685 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6686 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6687
6688 /* EOI */
6689 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6690 /* SELF-IPI */
6691 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6692
6693 if (enable_ept)
6694 vmx_enable_tdp();
6695 else
6696 kvm_disable_tdp();
6697
6698 update_ple_window_actual_max();
6699
6700 /*
6701 * Only enable PML when hardware supports PML feature, and both EPT
6702 * and EPT A/D bit features are enabled -- PML depends on them to work.
6703 */
6704 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6705 enable_pml = 0;
6706
6707 if (!enable_pml) {
6708 kvm_x86_ops->slot_enable_log_dirty = NULL;
6709 kvm_x86_ops->slot_disable_log_dirty = NULL;
6710 kvm_x86_ops->flush_log_dirty = NULL;
6711 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6712 }
6713
6714 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6715 u64 vmx_msr;
6716
6717 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6718 cpu_preemption_timer_multi =
6719 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6720 } else {
6721 kvm_x86_ops->set_hv_timer = NULL;
6722 kvm_x86_ops->cancel_hv_timer = NULL;
6723 }
6724
6725 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6726
6727 kvm_mce_cap_supported |= MCG_LMCE_P;
6728
6729 return alloc_kvm_area();
6730
6731 out:
6732 for (i = 0; i < VMX_BITMAP_NR; i++)
6733 free_page((unsigned long)vmx_bitmap[i]);
6734
6735 return r;
6736 }
6737
6738 static __exit void hardware_unsetup(void)
6739 {
6740 int i;
6741
6742 for (i = 0; i < VMX_BITMAP_NR; i++)
6743 free_page((unsigned long)vmx_bitmap[i]);
6744
6745 free_kvm_area();
6746 }
6747
6748 /*
6749 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6750 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6751 */
6752 static int handle_pause(struct kvm_vcpu *vcpu)
6753 {
6754 if (ple_gap)
6755 grow_ple_window(vcpu);
6756
6757 kvm_vcpu_on_spin(vcpu);
6758 return kvm_skip_emulated_instruction(vcpu);
6759 }
6760
6761 static int handle_nop(struct kvm_vcpu *vcpu)
6762 {
6763 return kvm_skip_emulated_instruction(vcpu);
6764 }
6765
6766 static int handle_mwait(struct kvm_vcpu *vcpu)
6767 {
6768 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6769 return handle_nop(vcpu);
6770 }
6771
6772 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6773 {
6774 return 1;
6775 }
6776
6777 static int handle_monitor(struct kvm_vcpu *vcpu)
6778 {
6779 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6780 return handle_nop(vcpu);
6781 }
6782
6783 /*
6784 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6785 * We could reuse a single VMCS for all the L2 guests, but we also want the
6786 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6787 * allows keeping them loaded on the processor, and in the future will allow
6788 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6789 * every entry if they never change.
6790 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6791 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6792 *
6793 * The following functions allocate and free a vmcs02 in this pool.
6794 */
6795
6796 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6797 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6798 {
6799 struct vmcs02_list *item;
6800 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6801 if (item->vmptr == vmx->nested.current_vmptr) {
6802 list_move(&item->list, &vmx->nested.vmcs02_pool);
6803 return &item->vmcs02;
6804 }
6805
6806 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6807 /* Recycle the least recently used VMCS. */
6808 item = list_last_entry(&vmx->nested.vmcs02_pool,
6809 struct vmcs02_list, list);
6810 item->vmptr = vmx->nested.current_vmptr;
6811 list_move(&item->list, &vmx->nested.vmcs02_pool);
6812 return &item->vmcs02;
6813 }
6814
6815 /* Create a new VMCS */
6816 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6817 if (!item)
6818 return NULL;
6819 item->vmcs02.vmcs = alloc_vmcs();
6820 item->vmcs02.shadow_vmcs = NULL;
6821 if (!item->vmcs02.vmcs) {
6822 kfree(item);
6823 return NULL;
6824 }
6825 loaded_vmcs_init(&item->vmcs02);
6826 item->vmptr = vmx->nested.current_vmptr;
6827 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6828 vmx->nested.vmcs02_num++;
6829 return &item->vmcs02;
6830 }
6831
6832 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6833 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6834 {
6835 struct vmcs02_list *item;
6836 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6837 if (item->vmptr == vmptr) {
6838 free_loaded_vmcs(&item->vmcs02);
6839 list_del(&item->list);
6840 kfree(item);
6841 vmx->nested.vmcs02_num--;
6842 return;
6843 }
6844 }
6845
6846 /*
6847 * Free all VMCSs saved for this vcpu, except the one pointed by
6848 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6849 * must be &vmx->vmcs01.
6850 */
6851 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6852 {
6853 struct vmcs02_list *item, *n;
6854
6855 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6856 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6857 /*
6858 * Something will leak if the above WARN triggers. Better than
6859 * a use-after-free.
6860 */
6861 if (vmx->loaded_vmcs == &item->vmcs02)
6862 continue;
6863
6864 free_loaded_vmcs(&item->vmcs02);
6865 list_del(&item->list);
6866 kfree(item);
6867 vmx->nested.vmcs02_num--;
6868 }
6869 }
6870
6871 /*
6872 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6873 * set the success or error code of an emulated VMX instruction, as specified
6874 * by Vol 2B, VMX Instruction Reference, "Conventions".
6875 */
6876 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6877 {
6878 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6879 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6880 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6881 }
6882
6883 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6884 {
6885 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6886 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6887 X86_EFLAGS_SF | X86_EFLAGS_OF))
6888 | X86_EFLAGS_CF);
6889 }
6890
6891 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6892 u32 vm_instruction_error)
6893 {
6894 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6895 /*
6896 * failValid writes the error number to the current VMCS, which
6897 * can't be done there isn't a current VMCS.
6898 */
6899 nested_vmx_failInvalid(vcpu);
6900 return;
6901 }
6902 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6903 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6904 X86_EFLAGS_SF | X86_EFLAGS_OF))
6905 | X86_EFLAGS_ZF);
6906 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6907 /*
6908 * We don't need to force a shadow sync because
6909 * VM_INSTRUCTION_ERROR is not shadowed
6910 */
6911 }
6912
6913 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6914 {
6915 /* TODO: not to reset guest simply here. */
6916 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6917 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6918 }
6919
6920 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6921 {
6922 struct vcpu_vmx *vmx =
6923 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6924
6925 vmx->nested.preemption_timer_expired = true;
6926 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6927 kvm_vcpu_kick(&vmx->vcpu);
6928
6929 return HRTIMER_NORESTART;
6930 }
6931
6932 /*
6933 * Decode the memory-address operand of a vmx instruction, as recorded on an
6934 * exit caused by such an instruction (run by a guest hypervisor).
6935 * On success, returns 0. When the operand is invalid, returns 1 and throws
6936 * #UD or #GP.
6937 */
6938 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6939 unsigned long exit_qualification,
6940 u32 vmx_instruction_info, bool wr, gva_t *ret)
6941 {
6942 gva_t off;
6943 bool exn;
6944 struct kvm_segment s;
6945
6946 /*
6947 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6948 * Execution", on an exit, vmx_instruction_info holds most of the
6949 * addressing components of the operand. Only the displacement part
6950 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6951 * For how an actual address is calculated from all these components,
6952 * refer to Vol. 1, "Operand Addressing".
6953 */
6954 int scaling = vmx_instruction_info & 3;
6955 int addr_size = (vmx_instruction_info >> 7) & 7;
6956 bool is_reg = vmx_instruction_info & (1u << 10);
6957 int seg_reg = (vmx_instruction_info >> 15) & 7;
6958 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6959 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6960 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6961 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6962
6963 if (is_reg) {
6964 kvm_queue_exception(vcpu, UD_VECTOR);
6965 return 1;
6966 }
6967
6968 /* Addr = segment_base + offset */
6969 /* offset = base + [index * scale] + displacement */
6970 off = exit_qualification; /* holds the displacement */
6971 if (base_is_valid)
6972 off += kvm_register_read(vcpu, base_reg);
6973 if (index_is_valid)
6974 off += kvm_register_read(vcpu, index_reg)<<scaling;
6975 vmx_get_segment(vcpu, &s, seg_reg);
6976 *ret = s.base + off;
6977
6978 if (addr_size == 1) /* 32 bit */
6979 *ret &= 0xffffffff;
6980
6981 /* Checks for #GP/#SS exceptions. */
6982 exn = false;
6983 if (is_long_mode(vcpu)) {
6984 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6985 * non-canonical form. This is the only check on the memory
6986 * destination for long mode!
6987 */
6988 exn = is_noncanonical_address(*ret);
6989 } else if (is_protmode(vcpu)) {
6990 /* Protected mode: apply checks for segment validity in the
6991 * following order:
6992 * - segment type check (#GP(0) may be thrown)
6993 * - usability check (#GP(0)/#SS(0))
6994 * - limit check (#GP(0)/#SS(0))
6995 */
6996 if (wr)
6997 /* #GP(0) if the destination operand is located in a
6998 * read-only data segment or any code segment.
6999 */
7000 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7001 else
7002 /* #GP(0) if the source operand is located in an
7003 * execute-only code segment
7004 */
7005 exn = ((s.type & 0xa) == 8);
7006 if (exn) {
7007 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7008 return 1;
7009 }
7010 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7011 */
7012 exn = (s.unusable != 0);
7013 /* Protected mode: #GP(0)/#SS(0) if the memory
7014 * operand is outside the segment limit.
7015 */
7016 exn = exn || (off + sizeof(u64) > s.limit);
7017 }
7018 if (exn) {
7019 kvm_queue_exception_e(vcpu,
7020 seg_reg == VCPU_SREG_SS ?
7021 SS_VECTOR : GP_VECTOR,
7022 0);
7023 return 1;
7024 }
7025
7026 return 0;
7027 }
7028
7029 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7030 {
7031 gva_t gva;
7032 struct x86_exception e;
7033
7034 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7035 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7036 return 1;
7037
7038 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7039 sizeof(*vmpointer), &e)) {
7040 kvm_inject_page_fault(vcpu, &e);
7041 return 1;
7042 }
7043
7044 return 0;
7045 }
7046
7047 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7048 {
7049 struct vcpu_vmx *vmx = to_vmx(vcpu);
7050 struct vmcs *shadow_vmcs;
7051
7052 if (cpu_has_vmx_msr_bitmap()) {
7053 vmx->nested.msr_bitmap =
7054 (unsigned long *)__get_free_page(GFP_KERNEL);
7055 if (!vmx->nested.msr_bitmap)
7056 goto out_msr_bitmap;
7057 }
7058
7059 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7060 if (!vmx->nested.cached_vmcs12)
7061 goto out_cached_vmcs12;
7062
7063 if (enable_shadow_vmcs) {
7064 shadow_vmcs = alloc_vmcs();
7065 if (!shadow_vmcs)
7066 goto out_shadow_vmcs;
7067 /* mark vmcs as shadow */
7068 shadow_vmcs->revision_id |= (1u << 31);
7069 /* init shadow vmcs */
7070 vmcs_clear(shadow_vmcs);
7071 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7072 }
7073
7074 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7075 vmx->nested.vmcs02_num = 0;
7076
7077 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7078 HRTIMER_MODE_REL_PINNED);
7079 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7080
7081 vmx->nested.vmxon = true;
7082 return 0;
7083
7084 out_shadow_vmcs:
7085 kfree(vmx->nested.cached_vmcs12);
7086
7087 out_cached_vmcs12:
7088 free_page((unsigned long)vmx->nested.msr_bitmap);
7089
7090 out_msr_bitmap:
7091 return -ENOMEM;
7092 }
7093
7094 /*
7095 * Emulate the VMXON instruction.
7096 * Currently, we just remember that VMX is active, and do not save or even
7097 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7098 * do not currently need to store anything in that guest-allocated memory
7099 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7100 * argument is different from the VMXON pointer (which the spec says they do).
7101 */
7102 static int handle_vmon(struct kvm_vcpu *vcpu)
7103 {
7104 int ret;
7105 gpa_t vmptr;
7106 struct page *page;
7107 struct vcpu_vmx *vmx = to_vmx(vcpu);
7108 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7109 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7110
7111 /*
7112 * The Intel VMX Instruction Reference lists a bunch of bits that are
7113 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7114 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7115 * Otherwise, we should fail with #UD. But most faulting conditions
7116 * have already been checked by hardware, prior to the VM-exit for
7117 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7118 * that bit set to 1 in non-root mode.
7119 */
7120 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7121 kvm_queue_exception(vcpu, UD_VECTOR);
7122 return 1;
7123 }
7124
7125 if (vmx->nested.vmxon) {
7126 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7127 return kvm_skip_emulated_instruction(vcpu);
7128 }
7129
7130 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7131 != VMXON_NEEDED_FEATURES) {
7132 kvm_inject_gp(vcpu, 0);
7133 return 1;
7134 }
7135
7136 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7137 return 1;
7138
7139 /*
7140 * SDM 3: 24.11.5
7141 * The first 4 bytes of VMXON region contain the supported
7142 * VMCS revision identifier
7143 *
7144 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7145 * which replaces physical address width with 32
7146 */
7147 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7148 nested_vmx_failInvalid(vcpu);
7149 return kvm_skip_emulated_instruction(vcpu);
7150 }
7151
7152 page = nested_get_page(vcpu, vmptr);
7153 if (page == NULL) {
7154 nested_vmx_failInvalid(vcpu);
7155 return kvm_skip_emulated_instruction(vcpu);
7156 }
7157 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7158 kunmap(page);
7159 nested_release_page_clean(page);
7160 nested_vmx_failInvalid(vcpu);
7161 return kvm_skip_emulated_instruction(vcpu);
7162 }
7163 kunmap(page);
7164 nested_release_page_clean(page);
7165
7166 vmx->nested.vmxon_ptr = vmptr;
7167 ret = enter_vmx_operation(vcpu);
7168 if (ret)
7169 return ret;
7170
7171 nested_vmx_succeed(vcpu);
7172 return kvm_skip_emulated_instruction(vcpu);
7173 }
7174
7175 /*
7176 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7177 * for running VMX instructions (except VMXON, whose prerequisites are
7178 * slightly different). It also specifies what exception to inject otherwise.
7179 * Note that many of these exceptions have priority over VM exits, so they
7180 * don't have to be checked again here.
7181 */
7182 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7183 {
7184 if (!to_vmx(vcpu)->nested.vmxon) {
7185 kvm_queue_exception(vcpu, UD_VECTOR);
7186 return 0;
7187 }
7188 return 1;
7189 }
7190
7191 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7192 {
7193 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7194 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7195 }
7196
7197 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7198 {
7199 if (vmx->nested.current_vmptr == -1ull)
7200 return;
7201
7202 if (enable_shadow_vmcs) {
7203 /* copy to memory all shadowed fields in case
7204 they were modified */
7205 copy_shadow_to_vmcs12(vmx);
7206 vmx->nested.sync_shadow_vmcs = false;
7207 vmx_disable_shadow_vmcs(vmx);
7208 }
7209 vmx->nested.posted_intr_nv = -1;
7210
7211 /* Flush VMCS12 to guest memory */
7212 kvm_vcpu_write_guest_page(&vmx->vcpu,
7213 vmx->nested.current_vmptr >> PAGE_SHIFT,
7214 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7215
7216 vmx->nested.current_vmptr = -1ull;
7217 }
7218
7219 /*
7220 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7221 * just stops using VMX.
7222 */
7223 static void free_nested(struct vcpu_vmx *vmx)
7224 {
7225 if (!vmx->nested.vmxon)
7226 return;
7227
7228 vmx->nested.vmxon = false;
7229 free_vpid(vmx->nested.vpid02);
7230 vmx->nested.posted_intr_nv = -1;
7231 vmx->nested.current_vmptr = -1ull;
7232 if (vmx->nested.msr_bitmap) {
7233 free_page((unsigned long)vmx->nested.msr_bitmap);
7234 vmx->nested.msr_bitmap = NULL;
7235 }
7236 if (enable_shadow_vmcs) {
7237 vmx_disable_shadow_vmcs(vmx);
7238 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7239 free_vmcs(vmx->vmcs01.shadow_vmcs);
7240 vmx->vmcs01.shadow_vmcs = NULL;
7241 }
7242 kfree(vmx->nested.cached_vmcs12);
7243 /* Unpin physical memory we referred to in current vmcs02 */
7244 if (vmx->nested.apic_access_page) {
7245 nested_release_page(vmx->nested.apic_access_page);
7246 vmx->nested.apic_access_page = NULL;
7247 }
7248 if (vmx->nested.virtual_apic_page) {
7249 nested_release_page(vmx->nested.virtual_apic_page);
7250 vmx->nested.virtual_apic_page = NULL;
7251 }
7252 if (vmx->nested.pi_desc_page) {
7253 kunmap(vmx->nested.pi_desc_page);
7254 nested_release_page(vmx->nested.pi_desc_page);
7255 vmx->nested.pi_desc_page = NULL;
7256 vmx->nested.pi_desc = NULL;
7257 }
7258
7259 nested_free_all_saved_vmcss(vmx);
7260 }
7261
7262 /* Emulate the VMXOFF instruction */
7263 static int handle_vmoff(struct kvm_vcpu *vcpu)
7264 {
7265 if (!nested_vmx_check_permission(vcpu))
7266 return 1;
7267 free_nested(to_vmx(vcpu));
7268 nested_vmx_succeed(vcpu);
7269 return kvm_skip_emulated_instruction(vcpu);
7270 }
7271
7272 /* Emulate the VMCLEAR instruction */
7273 static int handle_vmclear(struct kvm_vcpu *vcpu)
7274 {
7275 struct vcpu_vmx *vmx = to_vmx(vcpu);
7276 u32 zero = 0;
7277 gpa_t vmptr;
7278
7279 if (!nested_vmx_check_permission(vcpu))
7280 return 1;
7281
7282 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7283 return 1;
7284
7285 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7286 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7287 return kvm_skip_emulated_instruction(vcpu);
7288 }
7289
7290 if (vmptr == vmx->nested.vmxon_ptr) {
7291 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7292 return kvm_skip_emulated_instruction(vcpu);
7293 }
7294
7295 if (vmptr == vmx->nested.current_vmptr)
7296 nested_release_vmcs12(vmx);
7297
7298 kvm_vcpu_write_guest(vcpu,
7299 vmptr + offsetof(struct vmcs12, launch_state),
7300 &zero, sizeof(zero));
7301
7302 nested_free_vmcs02(vmx, vmptr);
7303
7304 nested_vmx_succeed(vcpu);
7305 return kvm_skip_emulated_instruction(vcpu);
7306 }
7307
7308 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7309
7310 /* Emulate the VMLAUNCH instruction */
7311 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7312 {
7313 return nested_vmx_run(vcpu, true);
7314 }
7315
7316 /* Emulate the VMRESUME instruction */
7317 static int handle_vmresume(struct kvm_vcpu *vcpu)
7318 {
7319
7320 return nested_vmx_run(vcpu, false);
7321 }
7322
7323 /*
7324 * Read a vmcs12 field. Since these can have varying lengths and we return
7325 * one type, we chose the biggest type (u64) and zero-extend the return value
7326 * to that size. Note that the caller, handle_vmread, might need to use only
7327 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7328 * 64-bit fields are to be returned).
7329 */
7330 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7331 unsigned long field, u64 *ret)
7332 {
7333 short offset = vmcs_field_to_offset(field);
7334 char *p;
7335
7336 if (offset < 0)
7337 return offset;
7338
7339 p = ((char *)(get_vmcs12(vcpu))) + offset;
7340
7341 switch (vmcs_field_type(field)) {
7342 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7343 *ret = *((natural_width *)p);
7344 return 0;
7345 case VMCS_FIELD_TYPE_U16:
7346 *ret = *((u16 *)p);
7347 return 0;
7348 case VMCS_FIELD_TYPE_U32:
7349 *ret = *((u32 *)p);
7350 return 0;
7351 case VMCS_FIELD_TYPE_U64:
7352 *ret = *((u64 *)p);
7353 return 0;
7354 default:
7355 WARN_ON(1);
7356 return -ENOENT;
7357 }
7358 }
7359
7360
7361 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7362 unsigned long field, u64 field_value){
7363 short offset = vmcs_field_to_offset(field);
7364 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7365 if (offset < 0)
7366 return offset;
7367
7368 switch (vmcs_field_type(field)) {
7369 case VMCS_FIELD_TYPE_U16:
7370 *(u16 *)p = field_value;
7371 return 0;
7372 case VMCS_FIELD_TYPE_U32:
7373 *(u32 *)p = field_value;
7374 return 0;
7375 case VMCS_FIELD_TYPE_U64:
7376 *(u64 *)p = field_value;
7377 return 0;
7378 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7379 *(natural_width *)p = field_value;
7380 return 0;
7381 default:
7382 WARN_ON(1);
7383 return -ENOENT;
7384 }
7385
7386 }
7387
7388 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7389 {
7390 int i;
7391 unsigned long field;
7392 u64 field_value;
7393 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7394 const unsigned long *fields = shadow_read_write_fields;
7395 const int num_fields = max_shadow_read_write_fields;
7396
7397 preempt_disable();
7398
7399 vmcs_load(shadow_vmcs);
7400
7401 for (i = 0; i < num_fields; i++) {
7402 field = fields[i];
7403 switch (vmcs_field_type(field)) {
7404 case VMCS_FIELD_TYPE_U16:
7405 field_value = vmcs_read16(field);
7406 break;
7407 case VMCS_FIELD_TYPE_U32:
7408 field_value = vmcs_read32(field);
7409 break;
7410 case VMCS_FIELD_TYPE_U64:
7411 field_value = vmcs_read64(field);
7412 break;
7413 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7414 field_value = vmcs_readl(field);
7415 break;
7416 default:
7417 WARN_ON(1);
7418 continue;
7419 }
7420 vmcs12_write_any(&vmx->vcpu, field, field_value);
7421 }
7422
7423 vmcs_clear(shadow_vmcs);
7424 vmcs_load(vmx->loaded_vmcs->vmcs);
7425
7426 preempt_enable();
7427 }
7428
7429 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7430 {
7431 const unsigned long *fields[] = {
7432 shadow_read_write_fields,
7433 shadow_read_only_fields
7434 };
7435 const int max_fields[] = {
7436 max_shadow_read_write_fields,
7437 max_shadow_read_only_fields
7438 };
7439 int i, q;
7440 unsigned long field;
7441 u64 field_value = 0;
7442 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7443
7444 vmcs_load(shadow_vmcs);
7445
7446 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7447 for (i = 0; i < max_fields[q]; i++) {
7448 field = fields[q][i];
7449 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7450
7451 switch (vmcs_field_type(field)) {
7452 case VMCS_FIELD_TYPE_U16:
7453 vmcs_write16(field, (u16)field_value);
7454 break;
7455 case VMCS_FIELD_TYPE_U32:
7456 vmcs_write32(field, (u32)field_value);
7457 break;
7458 case VMCS_FIELD_TYPE_U64:
7459 vmcs_write64(field, (u64)field_value);
7460 break;
7461 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7462 vmcs_writel(field, (long)field_value);
7463 break;
7464 default:
7465 WARN_ON(1);
7466 break;
7467 }
7468 }
7469 }
7470
7471 vmcs_clear(shadow_vmcs);
7472 vmcs_load(vmx->loaded_vmcs->vmcs);
7473 }
7474
7475 /*
7476 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7477 * used before) all generate the same failure when it is missing.
7478 */
7479 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7480 {
7481 struct vcpu_vmx *vmx = to_vmx(vcpu);
7482 if (vmx->nested.current_vmptr == -1ull) {
7483 nested_vmx_failInvalid(vcpu);
7484 return 0;
7485 }
7486 return 1;
7487 }
7488
7489 static int handle_vmread(struct kvm_vcpu *vcpu)
7490 {
7491 unsigned long field;
7492 u64 field_value;
7493 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7494 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7495 gva_t gva = 0;
7496
7497 if (!nested_vmx_check_permission(vcpu))
7498 return 1;
7499
7500 if (!nested_vmx_check_vmcs12(vcpu))
7501 return kvm_skip_emulated_instruction(vcpu);
7502
7503 /* Decode instruction info and find the field to read */
7504 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7505 /* Read the field, zero-extended to a u64 field_value */
7506 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7507 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7508 return kvm_skip_emulated_instruction(vcpu);
7509 }
7510 /*
7511 * Now copy part of this value to register or memory, as requested.
7512 * Note that the number of bits actually copied is 32 or 64 depending
7513 * on the guest's mode (32 or 64 bit), not on the given field's length.
7514 */
7515 if (vmx_instruction_info & (1u << 10)) {
7516 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7517 field_value);
7518 } else {
7519 if (get_vmx_mem_address(vcpu, exit_qualification,
7520 vmx_instruction_info, true, &gva))
7521 return 1;
7522 /* _system ok, as hardware has verified cpl=0 */
7523 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7524 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7525 }
7526
7527 nested_vmx_succeed(vcpu);
7528 return kvm_skip_emulated_instruction(vcpu);
7529 }
7530
7531
7532 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7533 {
7534 unsigned long field;
7535 gva_t gva;
7536 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7537 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7538 /* The value to write might be 32 or 64 bits, depending on L1's long
7539 * mode, and eventually we need to write that into a field of several
7540 * possible lengths. The code below first zero-extends the value to 64
7541 * bit (field_value), and then copies only the appropriate number of
7542 * bits into the vmcs12 field.
7543 */
7544 u64 field_value = 0;
7545 struct x86_exception e;
7546
7547 if (!nested_vmx_check_permission(vcpu))
7548 return 1;
7549
7550 if (!nested_vmx_check_vmcs12(vcpu))
7551 return kvm_skip_emulated_instruction(vcpu);
7552
7553 if (vmx_instruction_info & (1u << 10))
7554 field_value = kvm_register_readl(vcpu,
7555 (((vmx_instruction_info) >> 3) & 0xf));
7556 else {
7557 if (get_vmx_mem_address(vcpu, exit_qualification,
7558 vmx_instruction_info, false, &gva))
7559 return 1;
7560 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7561 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7562 kvm_inject_page_fault(vcpu, &e);
7563 return 1;
7564 }
7565 }
7566
7567
7568 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7569 if (vmcs_field_readonly(field)) {
7570 nested_vmx_failValid(vcpu,
7571 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7572 return kvm_skip_emulated_instruction(vcpu);
7573 }
7574
7575 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7576 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7577 return kvm_skip_emulated_instruction(vcpu);
7578 }
7579
7580 nested_vmx_succeed(vcpu);
7581 return kvm_skip_emulated_instruction(vcpu);
7582 }
7583
7584 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7585 {
7586 vmx->nested.current_vmptr = vmptr;
7587 if (enable_shadow_vmcs) {
7588 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7589 SECONDARY_EXEC_SHADOW_VMCS);
7590 vmcs_write64(VMCS_LINK_POINTER,
7591 __pa(vmx->vmcs01.shadow_vmcs));
7592 vmx->nested.sync_shadow_vmcs = true;
7593 }
7594 }
7595
7596 /* Emulate the VMPTRLD instruction */
7597 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7598 {
7599 struct vcpu_vmx *vmx = to_vmx(vcpu);
7600 gpa_t vmptr;
7601
7602 if (!nested_vmx_check_permission(vcpu))
7603 return 1;
7604
7605 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7606 return 1;
7607
7608 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7609 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7610 return kvm_skip_emulated_instruction(vcpu);
7611 }
7612
7613 if (vmptr == vmx->nested.vmxon_ptr) {
7614 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7615 return kvm_skip_emulated_instruction(vcpu);
7616 }
7617
7618 if (vmx->nested.current_vmptr != vmptr) {
7619 struct vmcs12 *new_vmcs12;
7620 struct page *page;
7621 page = nested_get_page(vcpu, vmptr);
7622 if (page == NULL) {
7623 nested_vmx_failInvalid(vcpu);
7624 return kvm_skip_emulated_instruction(vcpu);
7625 }
7626 new_vmcs12 = kmap(page);
7627 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7628 kunmap(page);
7629 nested_release_page_clean(page);
7630 nested_vmx_failValid(vcpu,
7631 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7632 return kvm_skip_emulated_instruction(vcpu);
7633 }
7634
7635 nested_release_vmcs12(vmx);
7636 /*
7637 * Load VMCS12 from guest memory since it is not already
7638 * cached.
7639 */
7640 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7641 kunmap(page);
7642 nested_release_page_clean(page);
7643
7644 set_current_vmptr(vmx, vmptr);
7645 }
7646
7647 nested_vmx_succeed(vcpu);
7648 return kvm_skip_emulated_instruction(vcpu);
7649 }
7650
7651 /* Emulate the VMPTRST instruction */
7652 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7653 {
7654 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7655 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7656 gva_t vmcs_gva;
7657 struct x86_exception e;
7658
7659 if (!nested_vmx_check_permission(vcpu))
7660 return 1;
7661
7662 if (get_vmx_mem_address(vcpu, exit_qualification,
7663 vmx_instruction_info, true, &vmcs_gva))
7664 return 1;
7665 /* ok to use *_system, as hardware has verified cpl=0 */
7666 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7667 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7668 sizeof(u64), &e)) {
7669 kvm_inject_page_fault(vcpu, &e);
7670 return 1;
7671 }
7672 nested_vmx_succeed(vcpu);
7673 return kvm_skip_emulated_instruction(vcpu);
7674 }
7675
7676 /* Emulate the INVEPT instruction */
7677 static int handle_invept(struct kvm_vcpu *vcpu)
7678 {
7679 struct vcpu_vmx *vmx = to_vmx(vcpu);
7680 u32 vmx_instruction_info, types;
7681 unsigned long type;
7682 gva_t gva;
7683 struct x86_exception e;
7684 struct {
7685 u64 eptp, gpa;
7686 } operand;
7687
7688 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7689 SECONDARY_EXEC_ENABLE_EPT) ||
7690 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7691 kvm_queue_exception(vcpu, UD_VECTOR);
7692 return 1;
7693 }
7694
7695 if (!nested_vmx_check_permission(vcpu))
7696 return 1;
7697
7698 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7699 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7700
7701 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7702
7703 if (type >= 32 || !(types & (1 << type))) {
7704 nested_vmx_failValid(vcpu,
7705 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7706 return kvm_skip_emulated_instruction(vcpu);
7707 }
7708
7709 /* According to the Intel VMX instruction reference, the memory
7710 * operand is read even if it isn't needed (e.g., for type==global)
7711 */
7712 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7713 vmx_instruction_info, false, &gva))
7714 return 1;
7715 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7716 sizeof(operand), &e)) {
7717 kvm_inject_page_fault(vcpu, &e);
7718 return 1;
7719 }
7720
7721 switch (type) {
7722 case VMX_EPT_EXTENT_GLOBAL:
7723 /*
7724 * TODO: track mappings and invalidate
7725 * single context requests appropriately
7726 */
7727 case VMX_EPT_EXTENT_CONTEXT:
7728 kvm_mmu_sync_roots(vcpu);
7729 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7730 nested_vmx_succeed(vcpu);
7731 break;
7732 default:
7733 BUG_ON(1);
7734 break;
7735 }
7736
7737 return kvm_skip_emulated_instruction(vcpu);
7738 }
7739
7740 static int handle_invvpid(struct kvm_vcpu *vcpu)
7741 {
7742 struct vcpu_vmx *vmx = to_vmx(vcpu);
7743 u32 vmx_instruction_info;
7744 unsigned long type, types;
7745 gva_t gva;
7746 struct x86_exception e;
7747 struct {
7748 u64 vpid;
7749 u64 gla;
7750 } operand;
7751
7752 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7753 SECONDARY_EXEC_ENABLE_VPID) ||
7754 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7755 kvm_queue_exception(vcpu, UD_VECTOR);
7756 return 1;
7757 }
7758
7759 if (!nested_vmx_check_permission(vcpu))
7760 return 1;
7761
7762 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7763 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7764
7765 types = (vmx->nested.nested_vmx_vpid_caps &
7766 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7767
7768 if (type >= 32 || !(types & (1 << type))) {
7769 nested_vmx_failValid(vcpu,
7770 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7771 return kvm_skip_emulated_instruction(vcpu);
7772 }
7773
7774 /* according to the intel vmx instruction reference, the memory
7775 * operand is read even if it isn't needed (e.g., for type==global)
7776 */
7777 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7778 vmx_instruction_info, false, &gva))
7779 return 1;
7780 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7781 sizeof(operand), &e)) {
7782 kvm_inject_page_fault(vcpu, &e);
7783 return 1;
7784 }
7785 if (operand.vpid >> 16) {
7786 nested_vmx_failValid(vcpu,
7787 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7788 return kvm_skip_emulated_instruction(vcpu);
7789 }
7790
7791 switch (type) {
7792 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7793 if (is_noncanonical_address(operand.gla)) {
7794 nested_vmx_failValid(vcpu,
7795 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7796 return kvm_skip_emulated_instruction(vcpu);
7797 }
7798 /* fall through */
7799 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7800 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7801 if (!operand.vpid) {
7802 nested_vmx_failValid(vcpu,
7803 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7804 return kvm_skip_emulated_instruction(vcpu);
7805 }
7806 break;
7807 case VMX_VPID_EXTENT_ALL_CONTEXT:
7808 break;
7809 default:
7810 WARN_ON_ONCE(1);
7811 return kvm_skip_emulated_instruction(vcpu);
7812 }
7813
7814 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7815 nested_vmx_succeed(vcpu);
7816
7817 return kvm_skip_emulated_instruction(vcpu);
7818 }
7819
7820 static int handle_pml_full(struct kvm_vcpu *vcpu)
7821 {
7822 unsigned long exit_qualification;
7823
7824 trace_kvm_pml_full(vcpu->vcpu_id);
7825
7826 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7827
7828 /*
7829 * PML buffer FULL happened while executing iret from NMI,
7830 * "blocked by NMI" bit has to be set before next VM entry.
7831 */
7832 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7833 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7834 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7835 GUEST_INTR_STATE_NMI);
7836
7837 /*
7838 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7839 * here.., and there's no userspace involvement needed for PML.
7840 */
7841 return 1;
7842 }
7843
7844 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7845 {
7846 kvm_lapic_expired_hv_timer(vcpu);
7847 return 1;
7848 }
7849
7850 /*
7851 * The exit handlers return 1 if the exit was handled fully and guest execution
7852 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7853 * to be done to userspace and return 0.
7854 */
7855 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7856 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7857 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7858 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7859 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7860 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7861 [EXIT_REASON_CR_ACCESS] = handle_cr,
7862 [EXIT_REASON_DR_ACCESS] = handle_dr,
7863 [EXIT_REASON_CPUID] = handle_cpuid,
7864 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7865 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7866 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7867 [EXIT_REASON_HLT] = handle_halt,
7868 [EXIT_REASON_INVD] = handle_invd,
7869 [EXIT_REASON_INVLPG] = handle_invlpg,
7870 [EXIT_REASON_RDPMC] = handle_rdpmc,
7871 [EXIT_REASON_VMCALL] = handle_vmcall,
7872 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7873 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7874 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7875 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7876 [EXIT_REASON_VMREAD] = handle_vmread,
7877 [EXIT_REASON_VMRESUME] = handle_vmresume,
7878 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7879 [EXIT_REASON_VMOFF] = handle_vmoff,
7880 [EXIT_REASON_VMON] = handle_vmon,
7881 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7882 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7883 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7884 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7885 [EXIT_REASON_WBINVD] = handle_wbinvd,
7886 [EXIT_REASON_XSETBV] = handle_xsetbv,
7887 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7888 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7889 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7890 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7891 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7892 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7893 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7894 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7895 [EXIT_REASON_INVEPT] = handle_invept,
7896 [EXIT_REASON_INVVPID] = handle_invvpid,
7897 [EXIT_REASON_XSAVES] = handle_xsaves,
7898 [EXIT_REASON_XRSTORS] = handle_xrstors,
7899 [EXIT_REASON_PML_FULL] = handle_pml_full,
7900 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
7901 };
7902
7903 static const int kvm_vmx_max_exit_handlers =
7904 ARRAY_SIZE(kvm_vmx_exit_handlers);
7905
7906 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7907 struct vmcs12 *vmcs12)
7908 {
7909 unsigned long exit_qualification;
7910 gpa_t bitmap, last_bitmap;
7911 unsigned int port;
7912 int size;
7913 u8 b;
7914
7915 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7916 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7917
7918 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7919
7920 port = exit_qualification >> 16;
7921 size = (exit_qualification & 7) + 1;
7922
7923 last_bitmap = (gpa_t)-1;
7924 b = -1;
7925
7926 while (size > 0) {
7927 if (port < 0x8000)
7928 bitmap = vmcs12->io_bitmap_a;
7929 else if (port < 0x10000)
7930 bitmap = vmcs12->io_bitmap_b;
7931 else
7932 return true;
7933 bitmap += (port & 0x7fff) / 8;
7934
7935 if (last_bitmap != bitmap)
7936 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7937 return true;
7938 if (b & (1 << (port & 7)))
7939 return true;
7940
7941 port++;
7942 size--;
7943 last_bitmap = bitmap;
7944 }
7945
7946 return false;
7947 }
7948
7949 /*
7950 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7951 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7952 * disinterest in the current event (read or write a specific MSR) by using an
7953 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7954 */
7955 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7956 struct vmcs12 *vmcs12, u32 exit_reason)
7957 {
7958 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7959 gpa_t bitmap;
7960
7961 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7962 return true;
7963
7964 /*
7965 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7966 * for the four combinations of read/write and low/high MSR numbers.
7967 * First we need to figure out which of the four to use:
7968 */
7969 bitmap = vmcs12->msr_bitmap;
7970 if (exit_reason == EXIT_REASON_MSR_WRITE)
7971 bitmap += 2048;
7972 if (msr_index >= 0xc0000000) {
7973 msr_index -= 0xc0000000;
7974 bitmap += 1024;
7975 }
7976
7977 /* Then read the msr_index'th bit from this bitmap: */
7978 if (msr_index < 1024*8) {
7979 unsigned char b;
7980 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7981 return true;
7982 return 1 & (b >> (msr_index & 7));
7983 } else
7984 return true; /* let L1 handle the wrong parameter */
7985 }
7986
7987 /*
7988 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7989 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7990 * intercept (via guest_host_mask etc.) the current event.
7991 */
7992 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7993 struct vmcs12 *vmcs12)
7994 {
7995 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7996 int cr = exit_qualification & 15;
7997 int reg;
7998 unsigned long val;
7999
8000 switch ((exit_qualification >> 4) & 3) {
8001 case 0: /* mov to cr */
8002 reg = (exit_qualification >> 8) & 15;
8003 val = kvm_register_readl(vcpu, reg);
8004 switch (cr) {
8005 case 0:
8006 if (vmcs12->cr0_guest_host_mask &
8007 (val ^ vmcs12->cr0_read_shadow))
8008 return true;
8009 break;
8010 case 3:
8011 if ((vmcs12->cr3_target_count >= 1 &&
8012 vmcs12->cr3_target_value0 == val) ||
8013 (vmcs12->cr3_target_count >= 2 &&
8014 vmcs12->cr3_target_value1 == val) ||
8015 (vmcs12->cr3_target_count >= 3 &&
8016 vmcs12->cr3_target_value2 == val) ||
8017 (vmcs12->cr3_target_count >= 4 &&
8018 vmcs12->cr3_target_value3 == val))
8019 return false;
8020 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8021 return true;
8022 break;
8023 case 4:
8024 if (vmcs12->cr4_guest_host_mask &
8025 (vmcs12->cr4_read_shadow ^ val))
8026 return true;
8027 break;
8028 case 8:
8029 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8030 return true;
8031 break;
8032 }
8033 break;
8034 case 2: /* clts */
8035 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8036 (vmcs12->cr0_read_shadow & X86_CR0_TS))
8037 return true;
8038 break;
8039 case 1: /* mov from cr */
8040 switch (cr) {
8041 case 3:
8042 if (vmcs12->cpu_based_vm_exec_control &
8043 CPU_BASED_CR3_STORE_EXITING)
8044 return true;
8045 break;
8046 case 8:
8047 if (vmcs12->cpu_based_vm_exec_control &
8048 CPU_BASED_CR8_STORE_EXITING)
8049 return true;
8050 break;
8051 }
8052 break;
8053 case 3: /* lmsw */
8054 /*
8055 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8056 * cr0. Other attempted changes are ignored, with no exit.
8057 */
8058 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8059 if (vmcs12->cr0_guest_host_mask & 0xe &
8060 (val ^ vmcs12->cr0_read_shadow))
8061 return true;
8062 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8063 !(vmcs12->cr0_read_shadow & 0x1) &&
8064 (val & 0x1))
8065 return true;
8066 break;
8067 }
8068 return false;
8069 }
8070
8071 /*
8072 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8073 * should handle it ourselves in L0 (and then continue L2). Only call this
8074 * when in is_guest_mode (L2).
8075 */
8076 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8077 {
8078 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8079 struct vcpu_vmx *vmx = to_vmx(vcpu);
8080 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8081
8082 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8083 vmcs_readl(EXIT_QUALIFICATION),
8084 vmx->idt_vectoring_info,
8085 intr_info,
8086 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8087 KVM_ISA_VMX);
8088
8089 /*
8090 * The host physical addresses of some pages of guest memory
8091 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8092 * may write to these pages via their host physical address while
8093 * L2 is running, bypassing any address-translation-based dirty
8094 * tracking (e.g. EPT write protection).
8095 *
8096 * Mark them dirty on every exit from L2 to prevent them from
8097 * getting out of sync with dirty tracking.
8098 */
8099 nested_mark_vmcs12_pages_dirty(vcpu);
8100
8101 if (vmx->nested.nested_run_pending)
8102 return false;
8103
8104 if (unlikely(vmx->fail)) {
8105 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8106 vmcs_read32(VM_INSTRUCTION_ERROR));
8107 return true;
8108 }
8109
8110 switch (exit_reason) {
8111 case EXIT_REASON_EXCEPTION_NMI:
8112 if (is_nmi(intr_info))
8113 return false;
8114 else if (is_page_fault(intr_info))
8115 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8116 else if (is_no_device(intr_info) &&
8117 !(vmcs12->guest_cr0 & X86_CR0_TS))
8118 return false;
8119 else if (is_debug(intr_info) &&
8120 vcpu->guest_debug &
8121 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8122 return false;
8123 else if (is_breakpoint(intr_info) &&
8124 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8125 return false;
8126 return vmcs12->exception_bitmap &
8127 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8128 case EXIT_REASON_EXTERNAL_INTERRUPT:
8129 return false;
8130 case EXIT_REASON_TRIPLE_FAULT:
8131 return true;
8132 case EXIT_REASON_PENDING_INTERRUPT:
8133 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8134 case EXIT_REASON_NMI_WINDOW:
8135 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8136 case EXIT_REASON_TASK_SWITCH:
8137 return true;
8138 case EXIT_REASON_CPUID:
8139 return true;
8140 case EXIT_REASON_HLT:
8141 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8142 case EXIT_REASON_INVD:
8143 return true;
8144 case EXIT_REASON_INVLPG:
8145 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8146 case EXIT_REASON_RDPMC:
8147 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8148 case EXIT_REASON_RDRAND:
8149 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8150 case EXIT_REASON_RDSEED:
8151 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8152 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8153 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8154 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8155 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8156 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8157 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8158 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8159 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8160 /*
8161 * VMX instructions trap unconditionally. This allows L1 to
8162 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8163 */
8164 return true;
8165 case EXIT_REASON_CR_ACCESS:
8166 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8167 case EXIT_REASON_DR_ACCESS:
8168 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8169 case EXIT_REASON_IO_INSTRUCTION:
8170 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8171 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8172 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8173 case EXIT_REASON_MSR_READ:
8174 case EXIT_REASON_MSR_WRITE:
8175 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8176 case EXIT_REASON_INVALID_STATE:
8177 return true;
8178 case EXIT_REASON_MWAIT_INSTRUCTION:
8179 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8180 case EXIT_REASON_MONITOR_TRAP_FLAG:
8181 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8182 case EXIT_REASON_MONITOR_INSTRUCTION:
8183 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8184 case EXIT_REASON_PAUSE_INSTRUCTION:
8185 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8186 nested_cpu_has2(vmcs12,
8187 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8188 case EXIT_REASON_MCE_DURING_VMENTRY:
8189 return false;
8190 case EXIT_REASON_TPR_BELOW_THRESHOLD:
8191 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8192 case EXIT_REASON_APIC_ACCESS:
8193 return nested_cpu_has2(vmcs12,
8194 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8195 case EXIT_REASON_APIC_WRITE:
8196 case EXIT_REASON_EOI_INDUCED:
8197 /* apic_write and eoi_induced should exit unconditionally. */
8198 return true;
8199 case EXIT_REASON_EPT_VIOLATION:
8200 /*
8201 * L0 always deals with the EPT violation. If nested EPT is
8202 * used, and the nested mmu code discovers that the address is
8203 * missing in the guest EPT table (EPT12), the EPT violation
8204 * will be injected with nested_ept_inject_page_fault()
8205 */
8206 return false;
8207 case EXIT_REASON_EPT_MISCONFIG:
8208 /*
8209 * L2 never uses directly L1's EPT, but rather L0's own EPT
8210 * table (shadow on EPT) or a merged EPT table that L0 built
8211 * (EPT on EPT). So any problems with the structure of the
8212 * table is L0's fault.
8213 */
8214 return false;
8215 case EXIT_REASON_WBINVD:
8216 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8217 case EXIT_REASON_XSETBV:
8218 return true;
8219 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8220 /*
8221 * This should never happen, since it is not possible to
8222 * set XSS to a non-zero value---neither in L1 nor in L2.
8223 * If if it were, XSS would have to be checked against
8224 * the XSS exit bitmap in vmcs12.
8225 */
8226 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8227 case EXIT_REASON_PREEMPTION_TIMER:
8228 return false;
8229 case EXIT_REASON_PML_FULL:
8230 /* We emulate PML support to L1. */
8231 return false;
8232 default:
8233 return true;
8234 }
8235 }
8236
8237 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8238 {
8239 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8240
8241 /*
8242 * At this point, the exit interruption info in exit_intr_info
8243 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8244 * we need to query the in-kernel LAPIC.
8245 */
8246 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8247 if ((exit_intr_info &
8248 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8249 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8250 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8251 vmcs12->vm_exit_intr_error_code =
8252 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8253 }
8254
8255 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8256 vmcs_readl(EXIT_QUALIFICATION));
8257 return 1;
8258 }
8259
8260 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8261 {
8262 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8263 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8264 }
8265
8266 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8267 {
8268 if (vmx->pml_pg) {
8269 __free_page(vmx->pml_pg);
8270 vmx->pml_pg = NULL;
8271 }
8272 }
8273
8274 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8275 {
8276 struct vcpu_vmx *vmx = to_vmx(vcpu);
8277 u64 *pml_buf;
8278 u16 pml_idx;
8279
8280 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8281
8282 /* Do nothing if PML buffer is empty */
8283 if (pml_idx == (PML_ENTITY_NUM - 1))
8284 return;
8285
8286 /* PML index always points to next available PML buffer entity */
8287 if (pml_idx >= PML_ENTITY_NUM)
8288 pml_idx = 0;
8289 else
8290 pml_idx++;
8291
8292 pml_buf = page_address(vmx->pml_pg);
8293 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8294 u64 gpa;
8295
8296 gpa = pml_buf[pml_idx];
8297 WARN_ON(gpa & (PAGE_SIZE - 1));
8298 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8299 }
8300
8301 /* reset PML index */
8302 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8303 }
8304
8305 /*
8306 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8307 * Called before reporting dirty_bitmap to userspace.
8308 */
8309 static void kvm_flush_pml_buffers(struct kvm *kvm)
8310 {
8311 int i;
8312 struct kvm_vcpu *vcpu;
8313 /*
8314 * We only need to kick vcpu out of guest mode here, as PML buffer
8315 * is flushed at beginning of all VMEXITs, and it's obvious that only
8316 * vcpus running in guest are possible to have unflushed GPAs in PML
8317 * buffer.
8318 */
8319 kvm_for_each_vcpu(i, vcpu, kvm)
8320 kvm_vcpu_kick(vcpu);
8321 }
8322
8323 static void vmx_dump_sel(char *name, uint32_t sel)
8324 {
8325 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8326 name, vmcs_read16(sel),
8327 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8328 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8329 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8330 }
8331
8332 static void vmx_dump_dtsel(char *name, uint32_t limit)
8333 {
8334 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8335 name, vmcs_read32(limit),
8336 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8337 }
8338
8339 static void dump_vmcs(void)
8340 {
8341 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8342 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8343 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8344 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8345 u32 secondary_exec_control = 0;
8346 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8347 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8348 int i, n;
8349
8350 if (cpu_has_secondary_exec_ctrls())
8351 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8352
8353 pr_err("*** Guest State ***\n");
8354 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8355 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8356 vmcs_readl(CR0_GUEST_HOST_MASK));
8357 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8358 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8359 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8360 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8361 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8362 {
8363 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8364 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8365 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8366 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8367 }
8368 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8369 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8370 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8371 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8372 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8373 vmcs_readl(GUEST_SYSENTER_ESP),
8374 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8375 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8376 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8377 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8378 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8379 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8380 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8381 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8382 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8383 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8384 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8385 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8386 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8387 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8388 efer, vmcs_read64(GUEST_IA32_PAT));
8389 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8390 vmcs_read64(GUEST_IA32_DEBUGCTL),
8391 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8392 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8393 pr_err("PerfGlobCtl = 0x%016llx\n",
8394 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8395 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8396 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8397 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8398 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8399 vmcs_read32(GUEST_ACTIVITY_STATE));
8400 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8401 pr_err("InterruptStatus = %04x\n",
8402 vmcs_read16(GUEST_INTR_STATUS));
8403
8404 pr_err("*** Host State ***\n");
8405 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8406 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8407 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8408 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8409 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8410 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8411 vmcs_read16(HOST_TR_SELECTOR));
8412 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8413 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8414 vmcs_readl(HOST_TR_BASE));
8415 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8416 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8417 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8418 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8419 vmcs_readl(HOST_CR4));
8420 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8421 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8422 vmcs_read32(HOST_IA32_SYSENTER_CS),
8423 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8424 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8425 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8426 vmcs_read64(HOST_IA32_EFER),
8427 vmcs_read64(HOST_IA32_PAT));
8428 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8429 pr_err("PerfGlobCtl = 0x%016llx\n",
8430 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8431
8432 pr_err("*** Control State ***\n");
8433 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8434 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8435 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8436 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8437 vmcs_read32(EXCEPTION_BITMAP),
8438 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8439 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8440 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8441 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8442 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8443 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8444 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8445 vmcs_read32(VM_EXIT_INTR_INFO),
8446 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8447 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8448 pr_err(" reason=%08x qualification=%016lx\n",
8449 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8450 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8451 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8452 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8453 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8454 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8455 pr_err("TSC Multiplier = 0x%016llx\n",
8456 vmcs_read64(TSC_MULTIPLIER));
8457 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8458 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8459 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8460 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8461 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8462 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8463 n = vmcs_read32(CR3_TARGET_COUNT);
8464 for (i = 0; i + 1 < n; i += 4)
8465 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8466 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8467 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8468 if (i < n)
8469 pr_err("CR3 target%u=%016lx\n",
8470 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8471 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8472 pr_err("PLE Gap=%08x Window=%08x\n",
8473 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8474 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8475 pr_err("Virtual processor ID = 0x%04x\n",
8476 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8477 }
8478
8479 /*
8480 * The guest has exited. See if we can fix it or if we need userspace
8481 * assistance.
8482 */
8483 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8484 {
8485 struct vcpu_vmx *vmx = to_vmx(vcpu);
8486 u32 exit_reason = vmx->exit_reason;
8487 u32 vectoring_info = vmx->idt_vectoring_info;
8488
8489 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8490 vcpu->arch.gpa_available = false;
8491
8492 /*
8493 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8494 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8495 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8496 * mode as if vcpus is in root mode, the PML buffer must has been
8497 * flushed already.
8498 */
8499 if (enable_pml)
8500 vmx_flush_pml_buffer(vcpu);
8501
8502 /* If guest state is invalid, start emulating */
8503 if (vmx->emulation_required)
8504 return handle_invalid_guest_state(vcpu);
8505
8506 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8507 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8508
8509 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8510 dump_vmcs();
8511 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8512 vcpu->run->fail_entry.hardware_entry_failure_reason
8513 = exit_reason;
8514 return 0;
8515 }
8516
8517 if (unlikely(vmx->fail)) {
8518 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8519 vcpu->run->fail_entry.hardware_entry_failure_reason
8520 = vmcs_read32(VM_INSTRUCTION_ERROR);
8521 return 0;
8522 }
8523
8524 /*
8525 * Note:
8526 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8527 * delivery event since it indicates guest is accessing MMIO.
8528 * The vm-exit can be triggered again after return to guest that
8529 * will cause infinite loop.
8530 */
8531 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8532 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8533 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8534 exit_reason != EXIT_REASON_PML_FULL &&
8535 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8536 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8537 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8538 vcpu->run->internal.ndata = 3;
8539 vcpu->run->internal.data[0] = vectoring_info;
8540 vcpu->run->internal.data[1] = exit_reason;
8541 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8542 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8543 vcpu->run->internal.ndata++;
8544 vcpu->run->internal.data[3] =
8545 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8546 }
8547 return 0;
8548 }
8549
8550 if (exit_reason < kvm_vmx_max_exit_handlers
8551 && kvm_vmx_exit_handlers[exit_reason])
8552 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8553 else {
8554 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8555 exit_reason);
8556 kvm_queue_exception(vcpu, UD_VECTOR);
8557 return 1;
8558 }
8559 }
8560
8561 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8562 {
8563 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8564
8565 if (is_guest_mode(vcpu) &&
8566 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8567 return;
8568
8569 if (irr == -1 || tpr < irr) {
8570 vmcs_write32(TPR_THRESHOLD, 0);
8571 return;
8572 }
8573
8574 vmcs_write32(TPR_THRESHOLD, irr);
8575 }
8576
8577 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8578 {
8579 u32 sec_exec_control;
8580
8581 /* Postpone execution until vmcs01 is the current VMCS. */
8582 if (is_guest_mode(vcpu)) {
8583 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8584 return;
8585 }
8586
8587 if (!cpu_has_vmx_virtualize_x2apic_mode())
8588 return;
8589
8590 if (!cpu_need_tpr_shadow(vcpu))
8591 return;
8592
8593 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8594
8595 if (set) {
8596 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8597 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8598 } else {
8599 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8600 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8601 vmx_flush_tlb_ept_only(vcpu);
8602 }
8603 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8604
8605 vmx_set_msr_bitmap(vcpu);
8606 }
8607
8608 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8609 {
8610 struct vcpu_vmx *vmx = to_vmx(vcpu);
8611
8612 /*
8613 * Currently we do not handle the nested case where L2 has an
8614 * APIC access page of its own; that page is still pinned.
8615 * Hence, we skip the case where the VCPU is in guest mode _and_
8616 * L1 prepared an APIC access page for L2.
8617 *
8618 * For the case where L1 and L2 share the same APIC access page
8619 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8620 * in the vmcs12), this function will only update either the vmcs01
8621 * or the vmcs02. If the former, the vmcs02 will be updated by
8622 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8623 * the next L2->L1 exit.
8624 */
8625 if (!is_guest_mode(vcpu) ||
8626 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8627 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8628 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8629 vmx_flush_tlb_ept_only(vcpu);
8630 }
8631 }
8632
8633 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8634 {
8635 u16 status;
8636 u8 old;
8637
8638 if (max_isr == -1)
8639 max_isr = 0;
8640
8641 status = vmcs_read16(GUEST_INTR_STATUS);
8642 old = status >> 8;
8643 if (max_isr != old) {
8644 status &= 0xff;
8645 status |= max_isr << 8;
8646 vmcs_write16(GUEST_INTR_STATUS, status);
8647 }
8648 }
8649
8650 static void vmx_set_rvi(int vector)
8651 {
8652 u16 status;
8653 u8 old;
8654
8655 if (vector == -1)
8656 vector = 0;
8657
8658 status = vmcs_read16(GUEST_INTR_STATUS);
8659 old = (u8)status & 0xff;
8660 if ((u8)vector != old) {
8661 status &= ~0xff;
8662 status |= (u8)vector;
8663 vmcs_write16(GUEST_INTR_STATUS, status);
8664 }
8665 }
8666
8667 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8668 {
8669 if (!is_guest_mode(vcpu)) {
8670 vmx_set_rvi(max_irr);
8671 return;
8672 }
8673
8674 if (max_irr == -1)
8675 return;
8676
8677 /*
8678 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8679 * handles it.
8680 */
8681 if (nested_exit_on_intr(vcpu))
8682 return;
8683
8684 /*
8685 * Else, fall back to pre-APICv interrupt injection since L2
8686 * is run without virtual interrupt delivery.
8687 */
8688 if (!kvm_event_needs_reinjection(vcpu) &&
8689 vmx_interrupt_allowed(vcpu)) {
8690 kvm_queue_interrupt(vcpu, max_irr, false);
8691 vmx_inject_irq(vcpu);
8692 }
8693 }
8694
8695 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8696 {
8697 struct vcpu_vmx *vmx = to_vmx(vcpu);
8698 int max_irr;
8699
8700 WARN_ON(!vcpu->arch.apicv_active);
8701 if (pi_test_on(&vmx->pi_desc)) {
8702 pi_clear_on(&vmx->pi_desc);
8703 /*
8704 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8705 * But on x86 this is just a compiler barrier anyway.
8706 */
8707 smp_mb__after_atomic();
8708 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8709 } else {
8710 max_irr = kvm_lapic_find_highest_irr(vcpu);
8711 }
8712 vmx_hwapic_irr_update(vcpu, max_irr);
8713 return max_irr;
8714 }
8715
8716 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8717 {
8718 if (!kvm_vcpu_apicv_active(vcpu))
8719 return;
8720
8721 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8722 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8723 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8724 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8725 }
8726
8727 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8728 {
8729 struct vcpu_vmx *vmx = to_vmx(vcpu);
8730
8731 pi_clear_on(&vmx->pi_desc);
8732 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8733 }
8734
8735 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8736 {
8737 u32 exit_intr_info = 0;
8738 u16 basic_exit_reason = (u16)vmx->exit_reason;
8739
8740 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8741 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
8742 return;
8743
8744 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
8745 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8746 vmx->exit_intr_info = exit_intr_info;
8747
8748 /* if exit due to PF check for async PF */
8749 if (is_page_fault(exit_intr_info))
8750 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
8751
8752 /* Handle machine checks before interrupts are enabled */
8753 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
8754 is_machine_check(exit_intr_info))
8755 kvm_machine_check();
8756
8757 /* We need to handle NMIs before interrupts are enabled */
8758 if (is_nmi(exit_intr_info)) {
8759 kvm_before_handle_nmi(&vmx->vcpu);
8760 asm("int $2");
8761 kvm_after_handle_nmi(&vmx->vcpu);
8762 }
8763 }
8764
8765 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8766 {
8767 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8768 register void *__sp asm(_ASM_SP);
8769
8770 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8771 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8772 unsigned int vector;
8773 unsigned long entry;
8774 gate_desc *desc;
8775 struct vcpu_vmx *vmx = to_vmx(vcpu);
8776 #ifdef CONFIG_X86_64
8777 unsigned long tmp;
8778 #endif
8779
8780 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8781 desc = (gate_desc *)vmx->host_idt_base + vector;
8782 entry = gate_offset(*desc);
8783 asm volatile(
8784 #ifdef CONFIG_X86_64
8785 "mov %%" _ASM_SP ", %[sp]\n\t"
8786 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8787 "push $%c[ss]\n\t"
8788 "push %[sp]\n\t"
8789 #endif
8790 "pushf\n\t"
8791 __ASM_SIZE(push) " $%c[cs]\n\t"
8792 "call *%[entry]\n\t"
8793 :
8794 #ifdef CONFIG_X86_64
8795 [sp]"=&r"(tmp),
8796 #endif
8797 "+r"(__sp)
8798 :
8799 [entry]"r"(entry),
8800 [ss]"i"(__KERNEL_DS),
8801 [cs]"i"(__KERNEL_CS)
8802 );
8803 }
8804 }
8805 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
8806
8807 static bool vmx_has_high_real_mode_segbase(void)
8808 {
8809 return enable_unrestricted_guest || emulate_invalid_guest_state;
8810 }
8811
8812 static bool vmx_mpx_supported(void)
8813 {
8814 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8815 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8816 }
8817
8818 static bool vmx_xsaves_supported(void)
8819 {
8820 return vmcs_config.cpu_based_2nd_exec_ctrl &
8821 SECONDARY_EXEC_XSAVES;
8822 }
8823
8824 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8825 {
8826 u32 exit_intr_info;
8827 bool unblock_nmi;
8828 u8 vector;
8829 bool idtv_info_valid;
8830
8831 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8832
8833 if (vmx->loaded_vmcs->nmi_known_unmasked)
8834 return;
8835 /*
8836 * Can't use vmx->exit_intr_info since we're not sure what
8837 * the exit reason is.
8838 */
8839 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8840 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8841 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8842 /*
8843 * SDM 3: 27.7.1.2 (September 2008)
8844 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8845 * a guest IRET fault.
8846 * SDM 3: 23.2.2 (September 2008)
8847 * Bit 12 is undefined in any of the following cases:
8848 * If the VM exit sets the valid bit in the IDT-vectoring
8849 * information field.
8850 * If the VM exit is due to a double fault.
8851 */
8852 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8853 vector != DF_VECTOR && !idtv_info_valid)
8854 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8855 GUEST_INTR_STATE_NMI);
8856 else
8857 vmx->loaded_vmcs->nmi_known_unmasked =
8858 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8859 & GUEST_INTR_STATE_NMI);
8860 }
8861
8862 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8863 u32 idt_vectoring_info,
8864 int instr_len_field,
8865 int error_code_field)
8866 {
8867 u8 vector;
8868 int type;
8869 bool idtv_info_valid;
8870
8871 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8872
8873 vcpu->arch.nmi_injected = false;
8874 kvm_clear_exception_queue(vcpu);
8875 kvm_clear_interrupt_queue(vcpu);
8876
8877 if (!idtv_info_valid)
8878 return;
8879
8880 kvm_make_request(KVM_REQ_EVENT, vcpu);
8881
8882 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8883 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8884
8885 switch (type) {
8886 case INTR_TYPE_NMI_INTR:
8887 vcpu->arch.nmi_injected = true;
8888 /*
8889 * SDM 3: 27.7.1.2 (September 2008)
8890 * Clear bit "block by NMI" before VM entry if a NMI
8891 * delivery faulted.
8892 */
8893 vmx_set_nmi_mask(vcpu, false);
8894 break;
8895 case INTR_TYPE_SOFT_EXCEPTION:
8896 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8897 /* fall through */
8898 case INTR_TYPE_HARD_EXCEPTION:
8899 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8900 u32 err = vmcs_read32(error_code_field);
8901 kvm_requeue_exception_e(vcpu, vector, err);
8902 } else
8903 kvm_requeue_exception(vcpu, vector);
8904 break;
8905 case INTR_TYPE_SOFT_INTR:
8906 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8907 /* fall through */
8908 case INTR_TYPE_EXT_INTR:
8909 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8910 break;
8911 default:
8912 break;
8913 }
8914 }
8915
8916 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8917 {
8918 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8919 VM_EXIT_INSTRUCTION_LEN,
8920 IDT_VECTORING_ERROR_CODE);
8921 }
8922
8923 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8924 {
8925 __vmx_complete_interrupts(vcpu,
8926 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8927 VM_ENTRY_INSTRUCTION_LEN,
8928 VM_ENTRY_EXCEPTION_ERROR_CODE);
8929
8930 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8931 }
8932
8933 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8934 {
8935 int i, nr_msrs;
8936 struct perf_guest_switch_msr *msrs;
8937
8938 msrs = perf_guest_get_msrs(&nr_msrs);
8939
8940 if (!msrs)
8941 return;
8942
8943 for (i = 0; i < nr_msrs; i++)
8944 if (msrs[i].host == msrs[i].guest)
8945 clear_atomic_switch_msr(vmx, msrs[i].msr);
8946 else
8947 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8948 msrs[i].host);
8949 }
8950
8951 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8952 {
8953 struct vcpu_vmx *vmx = to_vmx(vcpu);
8954 u64 tscl;
8955 u32 delta_tsc;
8956
8957 if (vmx->hv_deadline_tsc == -1)
8958 return;
8959
8960 tscl = rdtsc();
8961 if (vmx->hv_deadline_tsc > tscl)
8962 /* sure to be 32 bit only because checked on set_hv_timer */
8963 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8964 cpu_preemption_timer_multi);
8965 else
8966 delta_tsc = 0;
8967
8968 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8969 }
8970
8971 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8972 {
8973 struct vcpu_vmx *vmx = to_vmx(vcpu);
8974 unsigned long debugctlmsr, cr3, cr4;
8975
8976 /* Don't enter VMX if guest state is invalid, let the exit handler
8977 start emulation until we arrive back to a valid state */
8978 if (vmx->emulation_required)
8979 return;
8980
8981 if (vmx->ple_window_dirty) {
8982 vmx->ple_window_dirty = false;
8983 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8984 }
8985
8986 if (vmx->nested.sync_shadow_vmcs) {
8987 copy_vmcs12_to_shadow(vmx);
8988 vmx->nested.sync_shadow_vmcs = false;
8989 }
8990
8991 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8992 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8993 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8994 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8995
8996 cr3 = __get_current_cr3_fast();
8997 if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8998 vmcs_writel(HOST_CR3, cr3);
8999 vmx->host_state.vmcs_host_cr3 = cr3;
9000 }
9001
9002 cr4 = cr4_read_shadow();
9003 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
9004 vmcs_writel(HOST_CR4, cr4);
9005 vmx->host_state.vmcs_host_cr4 = cr4;
9006 }
9007
9008 /* When single-stepping over STI and MOV SS, we must clear the
9009 * corresponding interruptibility bits in the guest state. Otherwise
9010 * vmentry fails as it then expects bit 14 (BS) in pending debug
9011 * exceptions being set, but that's not correct for the guest debugging
9012 * case. */
9013 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9014 vmx_set_interrupt_shadow(vcpu, 0);
9015
9016 if (static_cpu_has(X86_FEATURE_PKU) &&
9017 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9018 vcpu->arch.pkru != vmx->host_pkru)
9019 __write_pkru(vcpu->arch.pkru);
9020
9021 atomic_switch_perf_msrs(vmx);
9022 debugctlmsr = get_debugctlmsr();
9023
9024 vmx_arm_hv_timer(vcpu);
9025
9026 vmx->__launched = vmx->loaded_vmcs->launched;
9027 asm(
9028 /* Store host registers */
9029 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9030 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9031 "push %%" _ASM_CX " \n\t"
9032 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9033 "je 1f \n\t"
9034 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9035 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9036 "1: \n\t"
9037 /* Reload cr2 if changed */
9038 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9039 "mov %%cr2, %%" _ASM_DX " \n\t"
9040 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9041 "je 2f \n\t"
9042 "mov %%" _ASM_AX", %%cr2 \n\t"
9043 "2: \n\t"
9044 /* Check if vmlaunch of vmresume is needed */
9045 "cmpl $0, %c[launched](%0) \n\t"
9046 /* Load guest registers. Don't clobber flags. */
9047 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9048 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9049 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9050 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9051 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9052 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9053 #ifdef CONFIG_X86_64
9054 "mov %c[r8](%0), %%r8 \n\t"
9055 "mov %c[r9](%0), %%r9 \n\t"
9056 "mov %c[r10](%0), %%r10 \n\t"
9057 "mov %c[r11](%0), %%r11 \n\t"
9058 "mov %c[r12](%0), %%r12 \n\t"
9059 "mov %c[r13](%0), %%r13 \n\t"
9060 "mov %c[r14](%0), %%r14 \n\t"
9061 "mov %c[r15](%0), %%r15 \n\t"
9062 #endif
9063 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9064
9065 /* Enter guest mode */
9066 "jne 1f \n\t"
9067 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9068 "jmp 2f \n\t"
9069 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9070 "2: "
9071 /* Save guest registers, load host registers, keep flags */
9072 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9073 "pop %0 \n\t"
9074 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9075 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9076 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9077 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9078 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9079 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9080 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9081 #ifdef CONFIG_X86_64
9082 "mov %%r8, %c[r8](%0) \n\t"
9083 "mov %%r9, %c[r9](%0) \n\t"
9084 "mov %%r10, %c[r10](%0) \n\t"
9085 "mov %%r11, %c[r11](%0) \n\t"
9086 "mov %%r12, %c[r12](%0) \n\t"
9087 "mov %%r13, %c[r13](%0) \n\t"
9088 "mov %%r14, %c[r14](%0) \n\t"
9089 "mov %%r15, %c[r15](%0) \n\t"
9090 #endif
9091 "mov %%cr2, %%" _ASM_AX " \n\t"
9092 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9093
9094 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
9095 "setbe %c[fail](%0) \n\t"
9096 ".pushsection .rodata \n\t"
9097 ".global vmx_return \n\t"
9098 "vmx_return: " _ASM_PTR " 2b \n\t"
9099 ".popsection"
9100 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9101 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9102 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9103 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9104 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9105 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9106 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9107 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9108 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9109 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9110 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9111 #ifdef CONFIG_X86_64
9112 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9113 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9114 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9115 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9116 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9117 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9118 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9119 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9120 #endif
9121 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9122 [wordsize]"i"(sizeof(ulong))
9123 : "cc", "memory"
9124 #ifdef CONFIG_X86_64
9125 , "rax", "rbx", "rdi", "rsi"
9126 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9127 #else
9128 , "eax", "ebx", "edi", "esi"
9129 #endif
9130 );
9131
9132 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9133 if (debugctlmsr)
9134 update_debugctlmsr(debugctlmsr);
9135
9136 #ifndef CONFIG_X86_64
9137 /*
9138 * The sysexit path does not restore ds/es, so we must set them to
9139 * a reasonable value ourselves.
9140 *
9141 * We can't defer this to vmx_load_host_state() since that function
9142 * may be executed in interrupt context, which saves and restore segments
9143 * around it, nullifying its effect.
9144 */
9145 loadsegment(ds, __USER_DS);
9146 loadsegment(es, __USER_DS);
9147 #endif
9148
9149 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9150 | (1 << VCPU_EXREG_RFLAGS)
9151 | (1 << VCPU_EXREG_PDPTR)
9152 | (1 << VCPU_EXREG_SEGMENTS)
9153 | (1 << VCPU_EXREG_CR3));
9154 vcpu->arch.regs_dirty = 0;
9155
9156 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9157
9158 vmx->loaded_vmcs->launched = 1;
9159
9160 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9161
9162 /*
9163 * eager fpu is enabled if PKEY is supported and CR4 is switched
9164 * back on host, so it is safe to read guest PKRU from current
9165 * XSAVE.
9166 */
9167 if (static_cpu_has(X86_FEATURE_PKU) &&
9168 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9169 vcpu->arch.pkru = __read_pkru();
9170 if (vcpu->arch.pkru != vmx->host_pkru)
9171 __write_pkru(vmx->host_pkru);
9172 }
9173
9174 /*
9175 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9176 * we did not inject a still-pending event to L1 now because of
9177 * nested_run_pending, we need to re-enable this bit.
9178 */
9179 if (vmx->nested.nested_run_pending)
9180 kvm_make_request(KVM_REQ_EVENT, vcpu);
9181
9182 vmx->nested.nested_run_pending = 0;
9183
9184 vmx_complete_atomic_exit(vmx);
9185 vmx_recover_nmi_blocking(vmx);
9186 vmx_complete_interrupts(vmx);
9187 }
9188 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9189
9190 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9191 {
9192 struct vcpu_vmx *vmx = to_vmx(vcpu);
9193 int cpu;
9194
9195 if (vmx->loaded_vmcs == vmcs)
9196 return;
9197
9198 cpu = get_cpu();
9199 vmx->loaded_vmcs = vmcs;
9200 vmx_vcpu_put(vcpu);
9201 vmx_vcpu_load(vcpu, cpu);
9202 vcpu->cpu = cpu;
9203 put_cpu();
9204 }
9205
9206 /*
9207 * Ensure that the current vmcs of the logical processor is the
9208 * vmcs01 of the vcpu before calling free_nested().
9209 */
9210 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9211 {
9212 struct vcpu_vmx *vmx = to_vmx(vcpu);
9213 int r;
9214
9215 r = vcpu_load(vcpu);
9216 BUG_ON(r);
9217 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9218 free_nested(vmx);
9219 vcpu_put(vcpu);
9220 }
9221
9222 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9223 {
9224 struct vcpu_vmx *vmx = to_vmx(vcpu);
9225
9226 if (enable_pml)
9227 vmx_destroy_pml_buffer(vmx);
9228 free_vpid(vmx->vpid);
9229 leave_guest_mode(vcpu);
9230 vmx_free_vcpu_nested(vcpu);
9231 free_loaded_vmcs(vmx->loaded_vmcs);
9232 kfree(vmx->guest_msrs);
9233 kvm_vcpu_uninit(vcpu);
9234 kmem_cache_free(kvm_vcpu_cache, vmx);
9235 }
9236
9237 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9238 {
9239 int err;
9240 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9241 int cpu;
9242
9243 if (!vmx)
9244 return ERR_PTR(-ENOMEM);
9245
9246 vmx->vpid = allocate_vpid();
9247
9248 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9249 if (err)
9250 goto free_vcpu;
9251
9252 err = -ENOMEM;
9253
9254 /*
9255 * If PML is turned on, failure on enabling PML just results in failure
9256 * of creating the vcpu, therefore we can simplify PML logic (by
9257 * avoiding dealing with cases, such as enabling PML partially on vcpus
9258 * for the guest, etc.
9259 */
9260 if (enable_pml) {
9261 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9262 if (!vmx->pml_pg)
9263 goto uninit_vcpu;
9264 }
9265
9266 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9267 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9268 > PAGE_SIZE);
9269
9270 if (!vmx->guest_msrs)
9271 goto free_pml;
9272
9273 vmx->loaded_vmcs = &vmx->vmcs01;
9274 vmx->loaded_vmcs->vmcs = alloc_vmcs();
9275 vmx->loaded_vmcs->shadow_vmcs = NULL;
9276 if (!vmx->loaded_vmcs->vmcs)
9277 goto free_msrs;
9278 loaded_vmcs_init(vmx->loaded_vmcs);
9279
9280 cpu = get_cpu();
9281 vmx_vcpu_load(&vmx->vcpu, cpu);
9282 vmx->vcpu.cpu = cpu;
9283 err = vmx_vcpu_setup(vmx);
9284 vmx_vcpu_put(&vmx->vcpu);
9285 put_cpu();
9286 if (err)
9287 goto free_vmcs;
9288 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9289 err = alloc_apic_access_page(kvm);
9290 if (err)
9291 goto free_vmcs;
9292 }
9293
9294 if (enable_ept) {
9295 if (!kvm->arch.ept_identity_map_addr)
9296 kvm->arch.ept_identity_map_addr =
9297 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9298 err = init_rmode_identity_map(kvm);
9299 if (err)
9300 goto free_vmcs;
9301 }
9302
9303 if (nested) {
9304 nested_vmx_setup_ctls_msrs(vmx);
9305 vmx->nested.vpid02 = allocate_vpid();
9306 }
9307
9308 vmx->nested.posted_intr_nv = -1;
9309 vmx->nested.current_vmptr = -1ull;
9310
9311 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9312
9313 return &vmx->vcpu;
9314
9315 free_vmcs:
9316 free_vpid(vmx->nested.vpid02);
9317 free_loaded_vmcs(vmx->loaded_vmcs);
9318 free_msrs:
9319 kfree(vmx->guest_msrs);
9320 free_pml:
9321 vmx_destroy_pml_buffer(vmx);
9322 uninit_vcpu:
9323 kvm_vcpu_uninit(&vmx->vcpu);
9324 free_vcpu:
9325 free_vpid(vmx->vpid);
9326 kmem_cache_free(kvm_vcpu_cache, vmx);
9327 return ERR_PTR(err);
9328 }
9329
9330 static void __init vmx_check_processor_compat(void *rtn)
9331 {
9332 struct vmcs_config vmcs_conf;
9333
9334 *(int *)rtn = 0;
9335 if (setup_vmcs_config(&vmcs_conf) < 0)
9336 *(int *)rtn = -EIO;
9337 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9338 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9339 smp_processor_id());
9340 *(int *)rtn = -EIO;
9341 }
9342 }
9343
9344 static int get_ept_level(void)
9345 {
9346 return VMX_EPT_DEFAULT_GAW + 1;
9347 }
9348
9349 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9350 {
9351 u8 cache;
9352 u64 ipat = 0;
9353
9354 /* For VT-d and EPT combination
9355 * 1. MMIO: always map as UC
9356 * 2. EPT with VT-d:
9357 * a. VT-d without snooping control feature: can't guarantee the
9358 * result, try to trust guest.
9359 * b. VT-d with snooping control feature: snooping control feature of
9360 * VT-d engine can guarantee the cache correctness. Just set it
9361 * to WB to keep consistent with host. So the same as item 3.
9362 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9363 * consistent with host MTRR
9364 */
9365 if (is_mmio) {
9366 cache = MTRR_TYPE_UNCACHABLE;
9367 goto exit;
9368 }
9369
9370 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9371 ipat = VMX_EPT_IPAT_BIT;
9372 cache = MTRR_TYPE_WRBACK;
9373 goto exit;
9374 }
9375
9376 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9377 ipat = VMX_EPT_IPAT_BIT;
9378 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9379 cache = MTRR_TYPE_WRBACK;
9380 else
9381 cache = MTRR_TYPE_UNCACHABLE;
9382 goto exit;
9383 }
9384
9385 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9386
9387 exit:
9388 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9389 }
9390
9391 static int vmx_get_lpage_level(void)
9392 {
9393 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9394 return PT_DIRECTORY_LEVEL;
9395 else
9396 /* For shadow and EPT supported 1GB page */
9397 return PT_PDPE_LEVEL;
9398 }
9399
9400 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9401 {
9402 /*
9403 * These bits in the secondary execution controls field
9404 * are dynamic, the others are mostly based on the hypervisor
9405 * architecture and the guest's CPUID. Do not touch the
9406 * dynamic bits.
9407 */
9408 u32 mask =
9409 SECONDARY_EXEC_SHADOW_VMCS |
9410 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9411 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9412
9413 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9414
9415 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9416 (new_ctl & ~mask) | (cur_ctl & mask));
9417 }
9418
9419 /*
9420 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9421 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9422 */
9423 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9424 {
9425 struct vcpu_vmx *vmx = to_vmx(vcpu);
9426 struct kvm_cpuid_entry2 *entry;
9427
9428 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9429 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9430
9431 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9432 if (entry && (entry->_reg & (_cpuid_mask))) \
9433 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9434 } while (0)
9435
9436 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9437 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9438 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9439 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9440 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9441 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9442 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9443 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9444 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9445 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9446 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9447 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9448 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9449 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9450 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9451
9452 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9453 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9454 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9455 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9456 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9457 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9458 cr4_fixed1_update(bit(11), ecx, bit(2));
9459
9460 #undef cr4_fixed1_update
9461 }
9462
9463 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9464 {
9465 struct kvm_cpuid_entry2 *best;
9466 struct vcpu_vmx *vmx = to_vmx(vcpu);
9467 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9468
9469 if (vmx_rdtscp_supported()) {
9470 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9471 if (!rdtscp_enabled)
9472 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9473
9474 if (nested) {
9475 if (rdtscp_enabled)
9476 vmx->nested.nested_vmx_secondary_ctls_high |=
9477 SECONDARY_EXEC_RDTSCP;
9478 else
9479 vmx->nested.nested_vmx_secondary_ctls_high &=
9480 ~SECONDARY_EXEC_RDTSCP;
9481 }
9482 }
9483
9484 /* Exposing INVPCID only when PCID is exposed */
9485 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9486 if (vmx_invpcid_supported() &&
9487 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9488 !guest_cpuid_has_pcid(vcpu))) {
9489 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9490
9491 if (best)
9492 best->ebx &= ~bit(X86_FEATURE_INVPCID);
9493 }
9494
9495 if (cpu_has_secondary_exec_ctrls())
9496 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9497
9498 if (nested_vmx_allowed(vcpu))
9499 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9500 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9501 else
9502 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9503 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9504
9505 if (nested_vmx_allowed(vcpu))
9506 nested_vmx_cr_fixed1_bits_update(vcpu);
9507 }
9508
9509 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9510 {
9511 if (func == 1 && nested)
9512 entry->ecx |= bit(X86_FEATURE_VMX);
9513 }
9514
9515 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9516 struct x86_exception *fault)
9517 {
9518 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9519 struct vcpu_vmx *vmx = to_vmx(vcpu);
9520 u32 exit_reason;
9521 unsigned long exit_qualification = vcpu->arch.exit_qualification;
9522
9523 if (vmx->nested.pml_full) {
9524 exit_reason = EXIT_REASON_PML_FULL;
9525 vmx->nested.pml_full = false;
9526 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9527 } else if (fault->error_code & PFERR_RSVD_MASK)
9528 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9529 else
9530 exit_reason = EXIT_REASON_EPT_VIOLATION;
9531
9532 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9533 vmcs12->guest_physical_address = fault->address;
9534 }
9535
9536 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9537 {
9538 return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9539 }
9540
9541 /* Callbacks for nested_ept_init_mmu_context: */
9542
9543 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9544 {
9545 /* return the page table to be shadowed - in our case, EPT12 */
9546 return get_vmcs12(vcpu)->ept_pointer;
9547 }
9548
9549 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9550 {
9551 bool wants_ad;
9552
9553 WARN_ON(mmu_is_nested(vcpu));
9554 wants_ad = nested_ept_ad_enabled(vcpu);
9555 if (wants_ad && !enable_ept_ad_bits)
9556 return 1;
9557
9558 kvm_mmu_unload(vcpu);
9559 kvm_init_shadow_ept_mmu(vcpu,
9560 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9561 VMX_EPT_EXECUTE_ONLY_BIT,
9562 wants_ad);
9563 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9564 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9565 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9566
9567 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9568 return 0;
9569 }
9570
9571 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9572 {
9573 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9574 }
9575
9576 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9577 u16 error_code)
9578 {
9579 bool inequality, bit;
9580
9581 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9582 inequality =
9583 (error_code & vmcs12->page_fault_error_code_mask) !=
9584 vmcs12->page_fault_error_code_match;
9585 return inequality ^ bit;
9586 }
9587
9588 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9589 struct x86_exception *fault)
9590 {
9591 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9592
9593 WARN_ON(!is_guest_mode(vcpu));
9594
9595 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code)) {
9596 vmcs12->vm_exit_intr_error_code = fault->error_code;
9597 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9598 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
9599 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
9600 fault->address);
9601 } else {
9602 kvm_inject_page_fault(vcpu, fault);
9603 }
9604 }
9605
9606 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9607 struct vmcs12 *vmcs12);
9608
9609 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9610 struct vmcs12 *vmcs12)
9611 {
9612 struct vcpu_vmx *vmx = to_vmx(vcpu);
9613 u64 hpa;
9614
9615 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9616 /*
9617 * Translate L1 physical address to host physical
9618 * address for vmcs02. Keep the page pinned, so this
9619 * physical address remains valid. We keep a reference
9620 * to it so we can release it later.
9621 */
9622 if (vmx->nested.apic_access_page) /* shouldn't happen */
9623 nested_release_page(vmx->nested.apic_access_page);
9624 vmx->nested.apic_access_page =
9625 nested_get_page(vcpu, vmcs12->apic_access_addr);
9626 /*
9627 * If translation failed, no matter: This feature asks
9628 * to exit when accessing the given address, and if it
9629 * can never be accessed, this feature won't do
9630 * anything anyway.
9631 */
9632 if (vmx->nested.apic_access_page) {
9633 hpa = page_to_phys(vmx->nested.apic_access_page);
9634 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9635 } else {
9636 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9637 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9638 }
9639 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9640 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9641 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9642 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9643 kvm_vcpu_reload_apic_access_page(vcpu);
9644 }
9645
9646 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9647 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9648 nested_release_page(vmx->nested.virtual_apic_page);
9649 vmx->nested.virtual_apic_page =
9650 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9651
9652 /*
9653 * If translation failed, VM entry will fail because
9654 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9655 * Failing the vm entry is _not_ what the processor
9656 * does but it's basically the only possibility we
9657 * have. We could still enter the guest if CR8 load
9658 * exits are enabled, CR8 store exits are enabled, and
9659 * virtualize APIC access is disabled; in this case
9660 * the processor would never use the TPR shadow and we
9661 * could simply clear the bit from the execution
9662 * control. But such a configuration is useless, so
9663 * let's keep the code simple.
9664 */
9665 if (vmx->nested.virtual_apic_page) {
9666 hpa = page_to_phys(vmx->nested.virtual_apic_page);
9667 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9668 }
9669 }
9670
9671 if (nested_cpu_has_posted_intr(vmcs12)) {
9672 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9673 kunmap(vmx->nested.pi_desc_page);
9674 nested_release_page(vmx->nested.pi_desc_page);
9675 }
9676 vmx->nested.pi_desc_page =
9677 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9678 vmx->nested.pi_desc =
9679 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9680 if (!vmx->nested.pi_desc) {
9681 nested_release_page_clean(vmx->nested.pi_desc_page);
9682 return;
9683 }
9684 vmx->nested.pi_desc =
9685 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9686 (unsigned long)(vmcs12->posted_intr_desc_addr &
9687 (PAGE_SIZE - 1)));
9688 vmcs_write64(POSTED_INTR_DESC_ADDR,
9689 page_to_phys(vmx->nested.pi_desc_page) +
9690 (unsigned long)(vmcs12->posted_intr_desc_addr &
9691 (PAGE_SIZE - 1)));
9692 }
9693 if (cpu_has_vmx_msr_bitmap() &&
9694 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9695 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9696 ;
9697 else
9698 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9699 CPU_BASED_USE_MSR_BITMAPS);
9700 }
9701
9702 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9703 {
9704 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9705 struct vcpu_vmx *vmx = to_vmx(vcpu);
9706
9707 if (vcpu->arch.virtual_tsc_khz == 0)
9708 return;
9709
9710 /* Make sure short timeouts reliably trigger an immediate vmexit.
9711 * hrtimer_start does not guarantee this. */
9712 if (preemption_timeout <= 1) {
9713 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9714 return;
9715 }
9716
9717 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9718 preemption_timeout *= 1000000;
9719 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9720 hrtimer_start(&vmx->nested.preemption_timer,
9721 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9722 }
9723
9724 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9725 struct vmcs12 *vmcs12)
9726 {
9727 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9728 return 0;
9729
9730 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9731 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9732 return -EINVAL;
9733
9734 return 0;
9735 }
9736
9737 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9738 struct vmcs12 *vmcs12)
9739 {
9740 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9741 return 0;
9742
9743 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
9744 return -EINVAL;
9745
9746 return 0;
9747 }
9748
9749 /*
9750 * Merge L0's and L1's MSR bitmap, return false to indicate that
9751 * we do not use the hardware.
9752 */
9753 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9754 struct vmcs12 *vmcs12)
9755 {
9756 int msr;
9757 struct page *page;
9758 unsigned long *msr_bitmap_l1;
9759 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9760
9761 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9762 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9763 return false;
9764
9765 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9766 if (!page)
9767 return false;
9768 msr_bitmap_l1 = (unsigned long *)kmap(page);
9769
9770 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9771
9772 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9773 if (nested_cpu_has_apic_reg_virt(vmcs12))
9774 for (msr = 0x800; msr <= 0x8ff; msr++)
9775 nested_vmx_disable_intercept_for_msr(
9776 msr_bitmap_l1, msr_bitmap_l0,
9777 msr, MSR_TYPE_R);
9778
9779 nested_vmx_disable_intercept_for_msr(
9780 msr_bitmap_l1, msr_bitmap_l0,
9781 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9782 MSR_TYPE_R | MSR_TYPE_W);
9783
9784 if (nested_cpu_has_vid(vmcs12)) {
9785 nested_vmx_disable_intercept_for_msr(
9786 msr_bitmap_l1, msr_bitmap_l0,
9787 APIC_BASE_MSR + (APIC_EOI >> 4),
9788 MSR_TYPE_W);
9789 nested_vmx_disable_intercept_for_msr(
9790 msr_bitmap_l1, msr_bitmap_l0,
9791 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9792 MSR_TYPE_W);
9793 }
9794 }
9795 kunmap(page);
9796 nested_release_page_clean(page);
9797
9798 return true;
9799 }
9800
9801 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9802 struct vmcs12 *vmcs12)
9803 {
9804 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9805 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9806 !nested_cpu_has_vid(vmcs12) &&
9807 !nested_cpu_has_posted_intr(vmcs12))
9808 return 0;
9809
9810 /*
9811 * If virtualize x2apic mode is enabled,
9812 * virtualize apic access must be disabled.
9813 */
9814 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9815 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9816 return -EINVAL;
9817
9818 /*
9819 * If virtual interrupt delivery is enabled,
9820 * we must exit on external interrupts.
9821 */
9822 if (nested_cpu_has_vid(vmcs12) &&
9823 !nested_exit_on_intr(vcpu))
9824 return -EINVAL;
9825
9826 /*
9827 * bits 15:8 should be zero in posted_intr_nv,
9828 * the descriptor address has been already checked
9829 * in nested_get_vmcs12_pages.
9830 */
9831 if (nested_cpu_has_posted_intr(vmcs12) &&
9832 (!nested_cpu_has_vid(vmcs12) ||
9833 !nested_exit_intr_ack_set(vcpu) ||
9834 vmcs12->posted_intr_nv & 0xff00))
9835 return -EINVAL;
9836
9837 /* tpr shadow is needed by all apicv features. */
9838 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9839 return -EINVAL;
9840
9841 return 0;
9842 }
9843
9844 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9845 unsigned long count_field,
9846 unsigned long addr_field)
9847 {
9848 int maxphyaddr;
9849 u64 count, addr;
9850
9851 if (vmcs12_read_any(vcpu, count_field, &count) ||
9852 vmcs12_read_any(vcpu, addr_field, &addr)) {
9853 WARN_ON(1);
9854 return -EINVAL;
9855 }
9856 if (count == 0)
9857 return 0;
9858 maxphyaddr = cpuid_maxphyaddr(vcpu);
9859 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9860 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9861 pr_debug_ratelimited(
9862 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9863 addr_field, maxphyaddr, count, addr);
9864 return -EINVAL;
9865 }
9866 return 0;
9867 }
9868
9869 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9870 struct vmcs12 *vmcs12)
9871 {
9872 if (vmcs12->vm_exit_msr_load_count == 0 &&
9873 vmcs12->vm_exit_msr_store_count == 0 &&
9874 vmcs12->vm_entry_msr_load_count == 0)
9875 return 0; /* Fast path */
9876 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9877 VM_EXIT_MSR_LOAD_ADDR) ||
9878 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9879 VM_EXIT_MSR_STORE_ADDR) ||
9880 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9881 VM_ENTRY_MSR_LOAD_ADDR))
9882 return -EINVAL;
9883 return 0;
9884 }
9885
9886 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9887 struct vmcs12 *vmcs12)
9888 {
9889 u64 address = vmcs12->pml_address;
9890 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9891
9892 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9893 if (!nested_cpu_has_ept(vmcs12) ||
9894 !IS_ALIGNED(address, 4096) ||
9895 address >> maxphyaddr)
9896 return -EINVAL;
9897 }
9898
9899 return 0;
9900 }
9901
9902 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9903 struct vmx_msr_entry *e)
9904 {
9905 /* x2APIC MSR accesses are not allowed */
9906 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9907 return -EINVAL;
9908 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9909 e->index == MSR_IA32_UCODE_REV)
9910 return -EINVAL;
9911 if (e->reserved != 0)
9912 return -EINVAL;
9913 return 0;
9914 }
9915
9916 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9917 struct vmx_msr_entry *e)
9918 {
9919 if (e->index == MSR_FS_BASE ||
9920 e->index == MSR_GS_BASE ||
9921 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9922 nested_vmx_msr_check_common(vcpu, e))
9923 return -EINVAL;
9924 return 0;
9925 }
9926
9927 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9928 struct vmx_msr_entry *e)
9929 {
9930 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9931 nested_vmx_msr_check_common(vcpu, e))
9932 return -EINVAL;
9933 return 0;
9934 }
9935
9936 /*
9937 * Load guest's/host's msr at nested entry/exit.
9938 * return 0 for success, entry index for failure.
9939 */
9940 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9941 {
9942 u32 i;
9943 struct vmx_msr_entry e;
9944 struct msr_data msr;
9945
9946 msr.host_initiated = false;
9947 for (i = 0; i < count; i++) {
9948 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9949 &e, sizeof(e))) {
9950 pr_debug_ratelimited(
9951 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9952 __func__, i, gpa + i * sizeof(e));
9953 goto fail;
9954 }
9955 if (nested_vmx_load_msr_check(vcpu, &e)) {
9956 pr_debug_ratelimited(
9957 "%s check failed (%u, 0x%x, 0x%x)\n",
9958 __func__, i, e.index, e.reserved);
9959 goto fail;
9960 }
9961 msr.index = e.index;
9962 msr.data = e.value;
9963 if (kvm_set_msr(vcpu, &msr)) {
9964 pr_debug_ratelimited(
9965 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9966 __func__, i, e.index, e.value);
9967 goto fail;
9968 }
9969 }
9970 return 0;
9971 fail:
9972 return i + 1;
9973 }
9974
9975 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9976 {
9977 u32 i;
9978 struct vmx_msr_entry e;
9979
9980 for (i = 0; i < count; i++) {
9981 struct msr_data msr_info;
9982 if (kvm_vcpu_read_guest(vcpu,
9983 gpa + i * sizeof(e),
9984 &e, 2 * sizeof(u32))) {
9985 pr_debug_ratelimited(
9986 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9987 __func__, i, gpa + i * sizeof(e));
9988 return -EINVAL;
9989 }
9990 if (nested_vmx_store_msr_check(vcpu, &e)) {
9991 pr_debug_ratelimited(
9992 "%s check failed (%u, 0x%x, 0x%x)\n",
9993 __func__, i, e.index, e.reserved);
9994 return -EINVAL;
9995 }
9996 msr_info.host_initiated = false;
9997 msr_info.index = e.index;
9998 if (kvm_get_msr(vcpu, &msr_info)) {
9999 pr_debug_ratelimited(
10000 "%s cannot read MSR (%u, 0x%x)\n",
10001 __func__, i, e.index);
10002 return -EINVAL;
10003 }
10004 if (kvm_vcpu_write_guest(vcpu,
10005 gpa + i * sizeof(e) +
10006 offsetof(struct vmx_msr_entry, value),
10007 &msr_info.data, sizeof(msr_info.data))) {
10008 pr_debug_ratelimited(
10009 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10010 __func__, i, e.index, msr_info.data);
10011 return -EINVAL;
10012 }
10013 }
10014 return 0;
10015 }
10016
10017 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10018 {
10019 unsigned long invalid_mask;
10020
10021 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10022 return (val & invalid_mask) == 0;
10023 }
10024
10025 /*
10026 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10027 * emulating VM entry into a guest with EPT enabled.
10028 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10029 * is assigned to entry_failure_code on failure.
10030 */
10031 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10032 u32 *entry_failure_code)
10033 {
10034 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10035 if (!nested_cr3_valid(vcpu, cr3)) {
10036 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10037 return 1;
10038 }
10039
10040 /*
10041 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10042 * must not be dereferenced.
10043 */
10044 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10045 !nested_ept) {
10046 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10047 *entry_failure_code = ENTRY_FAIL_PDPTE;
10048 return 1;
10049 }
10050 }
10051
10052 vcpu->arch.cr3 = cr3;
10053 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10054 }
10055
10056 kvm_mmu_reset_context(vcpu);
10057 return 0;
10058 }
10059
10060 /*
10061 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10062 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10063 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10064 * guest in a way that will both be appropriate to L1's requests, and our
10065 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10066 * function also has additional necessary side-effects, like setting various
10067 * vcpu->arch fields.
10068 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10069 * is assigned to entry_failure_code on failure.
10070 */
10071 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10072 bool from_vmentry, u32 *entry_failure_code)
10073 {
10074 struct vcpu_vmx *vmx = to_vmx(vcpu);
10075 u32 exec_control, vmcs12_exec_ctrl;
10076
10077 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10078 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10079 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10080 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10081 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10082 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10083 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10084 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10085 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10086 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10087 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10088 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10089 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10090 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10091 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10092 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10093 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10094 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10095 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10096 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10097 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10098 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10099 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10100 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10101 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10102 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10103 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10104 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10105 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10106 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10107 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10108 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10109 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10110 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10111 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10112 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10113
10114 if (from_vmentry &&
10115 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10116 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10117 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10118 } else {
10119 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10120 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10121 }
10122 if (from_vmentry) {
10123 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10124 vmcs12->vm_entry_intr_info_field);
10125 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10126 vmcs12->vm_entry_exception_error_code);
10127 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10128 vmcs12->vm_entry_instruction_len);
10129 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10130 vmcs12->guest_interruptibility_info);
10131 vmx->loaded_vmcs->nmi_known_unmasked =
10132 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10133 } else {
10134 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10135 }
10136 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10137 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10138 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10139 vmcs12->guest_pending_dbg_exceptions);
10140 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10141 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10142
10143 if (nested_cpu_has_xsaves(vmcs12))
10144 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10145 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10146
10147 exec_control = vmcs12->pin_based_vm_exec_control;
10148
10149 /* Preemption timer setting is only taken from vmcs01. */
10150 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10151 exec_control |= vmcs_config.pin_based_exec_ctrl;
10152 if (vmx->hv_deadline_tsc == -1)
10153 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10154
10155 /* Posted interrupts setting is only taken from vmcs12. */
10156 if (nested_cpu_has_posted_intr(vmcs12)) {
10157 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10158 vmx->nested.pi_pending = false;
10159 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10160 } else {
10161 exec_control &= ~PIN_BASED_POSTED_INTR;
10162 }
10163
10164 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10165
10166 vmx->nested.preemption_timer_expired = false;
10167 if (nested_cpu_has_preemption_timer(vmcs12))
10168 vmx_start_preemption_timer(vcpu);
10169
10170 /*
10171 * Whether page-faults are trapped is determined by a combination of
10172 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10173 * If enable_ept, L0 doesn't care about page faults and we should
10174 * set all of these to L1's desires. However, if !enable_ept, L0 does
10175 * care about (at least some) page faults, and because it is not easy
10176 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10177 * to exit on each and every L2 page fault. This is done by setting
10178 * MASK=MATCH=0 and (see below) EB.PF=1.
10179 * Note that below we don't need special code to set EB.PF beyond the
10180 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10181 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10182 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10183 */
10184 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10185 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10186 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10187 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10188
10189 if (cpu_has_secondary_exec_ctrls()) {
10190 exec_control = vmx_secondary_exec_control(vmx);
10191
10192 /* Take the following fields only from vmcs12 */
10193 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10194 SECONDARY_EXEC_RDTSCP |
10195 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10196 SECONDARY_EXEC_APIC_REGISTER_VIRT);
10197 if (nested_cpu_has(vmcs12,
10198 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10199 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10200 ~SECONDARY_EXEC_ENABLE_PML;
10201 exec_control |= vmcs12_exec_ctrl;
10202 }
10203
10204 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10205 vmcs_write64(EOI_EXIT_BITMAP0,
10206 vmcs12->eoi_exit_bitmap0);
10207 vmcs_write64(EOI_EXIT_BITMAP1,
10208 vmcs12->eoi_exit_bitmap1);
10209 vmcs_write64(EOI_EXIT_BITMAP2,
10210 vmcs12->eoi_exit_bitmap2);
10211 vmcs_write64(EOI_EXIT_BITMAP3,
10212 vmcs12->eoi_exit_bitmap3);
10213 vmcs_write16(GUEST_INTR_STATUS,
10214 vmcs12->guest_intr_status);
10215 }
10216
10217 /*
10218 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10219 * nested_get_vmcs12_pages will either fix it up or
10220 * remove the VM execution control.
10221 */
10222 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10223 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10224
10225 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10226 }
10227
10228
10229 /*
10230 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10231 * Some constant fields are set here by vmx_set_constant_host_state().
10232 * Other fields are different per CPU, and will be set later when
10233 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10234 */
10235 vmx_set_constant_host_state(vmx);
10236
10237 /*
10238 * Set the MSR load/store lists to match L0's settings.
10239 */
10240 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10241 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10242 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10243 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10244 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10245
10246 /*
10247 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10248 * entry, but only if the current (host) sp changed from the value
10249 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10250 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10251 * here we just force the write to happen on entry.
10252 */
10253 vmx->host_rsp = 0;
10254
10255 exec_control = vmx_exec_control(vmx); /* L0's desires */
10256 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10257 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10258 exec_control &= ~CPU_BASED_TPR_SHADOW;
10259 exec_control |= vmcs12->cpu_based_vm_exec_control;
10260
10261 /*
10262 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10263 * nested_get_vmcs12_pages can't fix it up, the illegal value
10264 * will result in a VM entry failure.
10265 */
10266 if (exec_control & CPU_BASED_TPR_SHADOW) {
10267 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10268 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10269 }
10270
10271 /*
10272 * Merging of IO bitmap not currently supported.
10273 * Rather, exit every time.
10274 */
10275 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10276 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10277
10278 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10279
10280 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10281 * bitwise-or of what L1 wants to trap for L2, and what we want to
10282 * trap. Note that CR0.TS also needs updating - we do this later.
10283 */
10284 update_exception_bitmap(vcpu);
10285 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10286 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10287
10288 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10289 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10290 * bits are further modified by vmx_set_efer() below.
10291 */
10292 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10293
10294 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10295 * emulated by vmx_set_efer(), below.
10296 */
10297 vm_entry_controls_init(vmx,
10298 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10299 ~VM_ENTRY_IA32E_MODE) |
10300 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10301
10302 if (from_vmentry &&
10303 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10304 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10305 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10306 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10307 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10308 }
10309
10310 set_cr4_guest_host_mask(vmx);
10311
10312 if (from_vmentry &&
10313 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10314 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10315
10316 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10317 vmcs_write64(TSC_OFFSET,
10318 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10319 else
10320 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10321 if (kvm_has_tsc_control)
10322 decache_tsc_multiplier(vmx);
10323
10324 if (enable_vpid) {
10325 /*
10326 * There is no direct mapping between vpid02 and vpid12, the
10327 * vpid02 is per-vCPU for L0 and reused while the value of
10328 * vpid12 is changed w/ one invvpid during nested vmentry.
10329 * The vpid12 is allocated by L1 for L2, so it will not
10330 * influence global bitmap(for vpid01 and vpid02 allocation)
10331 * even if spawn a lot of nested vCPUs.
10332 */
10333 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10334 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10335 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10336 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10337 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10338 }
10339 } else {
10340 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10341 vmx_flush_tlb(vcpu);
10342 }
10343
10344 }
10345
10346 if (enable_pml) {
10347 /*
10348 * Conceptually we want to copy the PML address and index from
10349 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10350 * since we always flush the log on each vmexit, this happens
10351 * to be equivalent to simply resetting the fields in vmcs02.
10352 */
10353 ASSERT(vmx->pml_pg);
10354 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10355 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10356 }
10357
10358 if (nested_cpu_has_ept(vmcs12)) {
10359 if (nested_ept_init_mmu_context(vcpu)) {
10360 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10361 return 1;
10362 }
10363 } else if (nested_cpu_has2(vmcs12,
10364 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10365 vmx_flush_tlb_ept_only(vcpu);
10366 }
10367
10368 /*
10369 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10370 * bits which we consider mandatory enabled.
10371 * The CR0_READ_SHADOW is what L2 should have expected to read given
10372 * the specifications by L1; It's not enough to take
10373 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10374 * have more bits than L1 expected.
10375 */
10376 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10377 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10378
10379 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10380 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10381
10382 if (from_vmentry &&
10383 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10384 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10385 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10386 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10387 else
10388 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10389 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10390 vmx_set_efer(vcpu, vcpu->arch.efer);
10391
10392 /* Shadow page tables on either EPT or shadow page tables. */
10393 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10394 entry_failure_code))
10395 return 1;
10396
10397 if (!enable_ept)
10398 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10399
10400 /*
10401 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10402 */
10403 if (enable_ept) {
10404 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10405 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10406 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10407 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10408 }
10409
10410 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10411 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10412 return 0;
10413 }
10414
10415 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10416 {
10417 struct vcpu_vmx *vmx = to_vmx(vcpu);
10418
10419 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10420 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10421 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10422
10423 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10424 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10425
10426 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10427 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10428
10429 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10430 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10431
10432 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10433 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10434
10435 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10436 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10437
10438 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10439 vmx->nested.nested_vmx_procbased_ctls_low,
10440 vmx->nested.nested_vmx_procbased_ctls_high) ||
10441 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10442 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10443 vmx->nested.nested_vmx_secondary_ctls_low,
10444 vmx->nested.nested_vmx_secondary_ctls_high)) ||
10445 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10446 vmx->nested.nested_vmx_pinbased_ctls_low,
10447 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10448 !vmx_control_verify(vmcs12->vm_exit_controls,
10449 vmx->nested.nested_vmx_exit_ctls_low,
10450 vmx->nested.nested_vmx_exit_ctls_high) ||
10451 !vmx_control_verify(vmcs12->vm_entry_controls,
10452 vmx->nested.nested_vmx_entry_ctls_low,
10453 vmx->nested.nested_vmx_entry_ctls_high))
10454 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10455
10456 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10457 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10458
10459 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10460 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10461 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10462 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10463
10464 return 0;
10465 }
10466
10467 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10468 u32 *exit_qual)
10469 {
10470 bool ia32e;
10471
10472 *exit_qual = ENTRY_FAIL_DEFAULT;
10473
10474 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10475 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10476 return 1;
10477
10478 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10479 vmcs12->vmcs_link_pointer != -1ull) {
10480 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10481 return 1;
10482 }
10483
10484 /*
10485 * If the load IA32_EFER VM-entry control is 1, the following checks
10486 * are performed on the field for the IA32_EFER MSR:
10487 * - Bits reserved in the IA32_EFER MSR must be 0.
10488 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10489 * the IA-32e mode guest VM-exit control. It must also be identical
10490 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10491 * CR0.PG) is 1.
10492 */
10493 if (to_vmx(vcpu)->nested.nested_run_pending &&
10494 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10495 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10496 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10497 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10498 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10499 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10500 return 1;
10501 }
10502
10503 /*
10504 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10505 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10506 * the values of the LMA and LME bits in the field must each be that of
10507 * the host address-space size VM-exit control.
10508 */
10509 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10510 ia32e = (vmcs12->vm_exit_controls &
10511 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10512 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10513 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10514 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10515 return 1;
10516 }
10517
10518 return 0;
10519 }
10520
10521 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10522 {
10523 struct vcpu_vmx *vmx = to_vmx(vcpu);
10524 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10525 struct loaded_vmcs *vmcs02;
10526 u32 msr_entry_idx;
10527 u32 exit_qual;
10528
10529 vmcs02 = nested_get_current_vmcs02(vmx);
10530 if (!vmcs02)
10531 return -ENOMEM;
10532
10533 enter_guest_mode(vcpu);
10534
10535 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10536 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10537
10538 vmx_switch_vmcs(vcpu, vmcs02);
10539 vmx_segment_cache_clear(vmx);
10540
10541 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10542 leave_guest_mode(vcpu);
10543 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10544 nested_vmx_entry_failure(vcpu, vmcs12,
10545 EXIT_REASON_INVALID_STATE, exit_qual);
10546 return 1;
10547 }
10548
10549 nested_get_vmcs12_pages(vcpu, vmcs12);
10550
10551 msr_entry_idx = nested_vmx_load_msr(vcpu,
10552 vmcs12->vm_entry_msr_load_addr,
10553 vmcs12->vm_entry_msr_load_count);
10554 if (msr_entry_idx) {
10555 leave_guest_mode(vcpu);
10556 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10557 nested_vmx_entry_failure(vcpu, vmcs12,
10558 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10559 return 1;
10560 }
10561
10562 /*
10563 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10564 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10565 * returned as far as L1 is concerned. It will only return (and set
10566 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10567 */
10568 return 0;
10569 }
10570
10571 /*
10572 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10573 * for running an L2 nested guest.
10574 */
10575 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10576 {
10577 struct vmcs12 *vmcs12;
10578 struct vcpu_vmx *vmx = to_vmx(vcpu);
10579 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
10580 u32 exit_qual;
10581 int ret;
10582
10583 if (!nested_vmx_check_permission(vcpu))
10584 return 1;
10585
10586 if (!nested_vmx_check_vmcs12(vcpu))
10587 goto out;
10588
10589 vmcs12 = get_vmcs12(vcpu);
10590
10591 if (enable_shadow_vmcs)
10592 copy_shadow_to_vmcs12(vmx);
10593
10594 /*
10595 * The nested entry process starts with enforcing various prerequisites
10596 * on vmcs12 as required by the Intel SDM, and act appropriately when
10597 * they fail: As the SDM explains, some conditions should cause the
10598 * instruction to fail, while others will cause the instruction to seem
10599 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10600 * To speed up the normal (success) code path, we should avoid checking
10601 * for misconfigurations which will anyway be caught by the processor
10602 * when using the merged vmcs02.
10603 */
10604 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10605 nested_vmx_failValid(vcpu,
10606 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10607 goto out;
10608 }
10609
10610 if (vmcs12->launch_state == launch) {
10611 nested_vmx_failValid(vcpu,
10612 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10613 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10614 goto out;
10615 }
10616
10617 ret = check_vmentry_prereqs(vcpu, vmcs12);
10618 if (ret) {
10619 nested_vmx_failValid(vcpu, ret);
10620 goto out;
10621 }
10622
10623 /*
10624 * After this point, the trap flag no longer triggers a singlestep trap
10625 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10626 * This is not 100% correct; for performance reasons, we delegate most
10627 * of the checks on host state to the processor. If those fail,
10628 * the singlestep trap is missed.
10629 */
10630 skip_emulated_instruction(vcpu);
10631
10632 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10633 if (ret) {
10634 nested_vmx_entry_failure(vcpu, vmcs12,
10635 EXIT_REASON_INVALID_STATE, exit_qual);
10636 return 1;
10637 }
10638
10639 /*
10640 * We're finally done with prerequisite checking, and can start with
10641 * the nested entry.
10642 */
10643
10644 ret = enter_vmx_non_root_mode(vcpu, true);
10645 if (ret)
10646 return ret;
10647
10648 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10649 return kvm_vcpu_halt(vcpu);
10650
10651 vmx->nested.nested_run_pending = 1;
10652
10653 return 1;
10654
10655 out:
10656 return kvm_skip_emulated_instruction(vcpu);
10657 }
10658
10659 /*
10660 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10661 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10662 * This function returns the new value we should put in vmcs12.guest_cr0.
10663 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10664 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10665 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10666 * didn't trap the bit, because if L1 did, so would L0).
10667 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10668 * been modified by L2, and L1 knows it. So just leave the old value of
10669 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10670 * isn't relevant, because if L0 traps this bit it can set it to anything.
10671 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10672 * changed these bits, and therefore they need to be updated, but L0
10673 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10674 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10675 */
10676 static inline unsigned long
10677 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10678 {
10679 return
10680 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10681 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10682 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10683 vcpu->arch.cr0_guest_owned_bits));
10684 }
10685
10686 static inline unsigned long
10687 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10688 {
10689 return
10690 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10691 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10692 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10693 vcpu->arch.cr4_guest_owned_bits));
10694 }
10695
10696 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10697 struct vmcs12 *vmcs12)
10698 {
10699 u32 idt_vectoring;
10700 unsigned int nr;
10701
10702 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10703 nr = vcpu->arch.exception.nr;
10704 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10705
10706 if (kvm_exception_is_soft(nr)) {
10707 vmcs12->vm_exit_instruction_len =
10708 vcpu->arch.event_exit_inst_len;
10709 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10710 } else
10711 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10712
10713 if (vcpu->arch.exception.has_error_code) {
10714 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10715 vmcs12->idt_vectoring_error_code =
10716 vcpu->arch.exception.error_code;
10717 }
10718
10719 vmcs12->idt_vectoring_info_field = idt_vectoring;
10720 } else if (vcpu->arch.nmi_injected) {
10721 vmcs12->idt_vectoring_info_field =
10722 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10723 } else if (vcpu->arch.interrupt.pending) {
10724 nr = vcpu->arch.interrupt.nr;
10725 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10726
10727 if (vcpu->arch.interrupt.soft) {
10728 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10729 vmcs12->vm_entry_instruction_len =
10730 vcpu->arch.event_exit_inst_len;
10731 } else
10732 idt_vectoring |= INTR_TYPE_EXT_INTR;
10733
10734 vmcs12->idt_vectoring_info_field = idt_vectoring;
10735 }
10736 }
10737
10738 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10739 {
10740 struct vcpu_vmx *vmx = to_vmx(vcpu);
10741
10742 if (vcpu->arch.exception.pending ||
10743 vcpu->arch.nmi_injected ||
10744 vcpu->arch.interrupt.pending)
10745 return -EBUSY;
10746
10747 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10748 vmx->nested.preemption_timer_expired) {
10749 if (vmx->nested.nested_run_pending)
10750 return -EBUSY;
10751 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10752 return 0;
10753 }
10754
10755 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10756 if (vmx->nested.nested_run_pending)
10757 return -EBUSY;
10758 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10759 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10760 INTR_INFO_VALID_MASK, 0);
10761 /*
10762 * The NMI-triggered VM exit counts as injection:
10763 * clear this one and block further NMIs.
10764 */
10765 vcpu->arch.nmi_pending = 0;
10766 vmx_set_nmi_mask(vcpu, true);
10767 return 0;
10768 }
10769
10770 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10771 nested_exit_on_intr(vcpu)) {
10772 if (vmx->nested.nested_run_pending)
10773 return -EBUSY;
10774 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10775 return 0;
10776 }
10777
10778 vmx_complete_nested_posted_interrupt(vcpu);
10779 return 0;
10780 }
10781
10782 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10783 {
10784 ktime_t remaining =
10785 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10786 u64 value;
10787
10788 if (ktime_to_ns(remaining) <= 0)
10789 return 0;
10790
10791 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10792 do_div(value, 1000000);
10793 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10794 }
10795
10796 /*
10797 * Update the guest state fields of vmcs12 to reflect changes that
10798 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10799 * VM-entry controls is also updated, since this is really a guest
10800 * state bit.)
10801 */
10802 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10803 {
10804 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10805 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10806
10807 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10808 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10809 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10810
10811 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10812 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10813 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10814 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10815 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10816 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10817 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10818 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10819 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10820 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10821 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10822 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10823 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10824 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10825 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10826 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10827 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10828 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10829 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10830 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10831 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10832 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10833 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10834 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10835 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10836 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10837 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10838 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10839 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10840 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10841 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10842 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10843 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10844 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10845 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10846 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10847
10848 vmcs12->guest_interruptibility_info =
10849 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10850 vmcs12->guest_pending_dbg_exceptions =
10851 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10852 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10853 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10854 else
10855 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10856
10857 if (nested_cpu_has_preemption_timer(vmcs12)) {
10858 if (vmcs12->vm_exit_controls &
10859 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10860 vmcs12->vmx_preemption_timer_value =
10861 vmx_get_preemption_timer_value(vcpu);
10862 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10863 }
10864
10865 /*
10866 * In some cases (usually, nested EPT), L2 is allowed to change its
10867 * own CR3 without exiting. If it has changed it, we must keep it.
10868 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10869 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10870 *
10871 * Additionally, restore L2's PDPTR to vmcs12.
10872 */
10873 if (enable_ept) {
10874 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10875 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10876 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10877 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10878 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10879 }
10880
10881 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10882
10883 if (nested_cpu_has_vid(vmcs12))
10884 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10885
10886 vmcs12->vm_entry_controls =
10887 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10888 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10889
10890 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10891 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10892 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10893 }
10894
10895 /* TODO: These cannot have changed unless we have MSR bitmaps and
10896 * the relevant bit asks not to trap the change */
10897 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10898 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10899 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10900 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10901 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10902 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10903 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10904 if (kvm_mpx_supported())
10905 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10906 }
10907
10908 /*
10909 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10910 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10911 * and this function updates it to reflect the changes to the guest state while
10912 * L2 was running (and perhaps made some exits which were handled directly by L0
10913 * without going back to L1), and to reflect the exit reason.
10914 * Note that we do not have to copy here all VMCS fields, just those that
10915 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10916 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10917 * which already writes to vmcs12 directly.
10918 */
10919 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10920 u32 exit_reason, u32 exit_intr_info,
10921 unsigned long exit_qualification)
10922 {
10923 /* update guest state fields: */
10924 sync_vmcs12(vcpu, vmcs12);
10925
10926 /* update exit information fields: */
10927
10928 vmcs12->vm_exit_reason = exit_reason;
10929 vmcs12->exit_qualification = exit_qualification;
10930 vmcs12->vm_exit_intr_info = exit_intr_info;
10931
10932 vmcs12->idt_vectoring_info_field = 0;
10933 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10934 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10935
10936 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10937 vmcs12->launch_state = 1;
10938
10939 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10940 * instead of reading the real value. */
10941 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10942
10943 /*
10944 * Transfer the event that L0 or L1 may wanted to inject into
10945 * L2 to IDT_VECTORING_INFO_FIELD.
10946 */
10947 vmcs12_save_pending_event(vcpu, vmcs12);
10948 }
10949
10950 /*
10951 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10952 * preserved above and would only end up incorrectly in L1.
10953 */
10954 vcpu->arch.nmi_injected = false;
10955 kvm_clear_exception_queue(vcpu);
10956 kvm_clear_interrupt_queue(vcpu);
10957 }
10958
10959 /*
10960 * A part of what we need to when the nested L2 guest exits and we want to
10961 * run its L1 parent, is to reset L1's guest state to the host state specified
10962 * in vmcs12.
10963 * This function is to be called not only on normal nested exit, but also on
10964 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10965 * Failures During or After Loading Guest State").
10966 * This function should be called when the active VMCS is L1's (vmcs01).
10967 */
10968 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10969 struct vmcs12 *vmcs12)
10970 {
10971 struct kvm_segment seg;
10972 u32 entry_failure_code;
10973
10974 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10975 vcpu->arch.efer = vmcs12->host_ia32_efer;
10976 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10977 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10978 else
10979 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10980 vmx_set_efer(vcpu, vcpu->arch.efer);
10981
10982 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10983 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10984 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10985 /*
10986 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10987 * actually changed, because vmx_set_cr0 refers to efer set above.
10988 *
10989 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10990 * (KVM doesn't change it);
10991 */
10992 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10993 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10994
10995 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
10996 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10997 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10998
10999 nested_ept_uninit_mmu_context(vcpu);
11000
11001 /*
11002 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11003 * couldn't have changed.
11004 */
11005 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11006 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11007
11008 if (!enable_ept)
11009 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11010
11011 if (enable_vpid) {
11012 /*
11013 * Trivially support vpid by letting L2s share their parent
11014 * L1's vpid. TODO: move to a more elaborate solution, giving
11015 * each L2 its own vpid and exposing the vpid feature to L1.
11016 */
11017 vmx_flush_tlb(vcpu);
11018 }
11019 /* Restore posted intr vector. */
11020 if (nested_cpu_has_posted_intr(vmcs12))
11021 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
11022
11023 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11024 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11025 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11026 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11027 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11028
11029 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11030 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11031 vmcs_write64(GUEST_BNDCFGS, 0);
11032
11033 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11034 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11035 vcpu->arch.pat = vmcs12->host_ia32_pat;
11036 }
11037 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11038 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11039 vmcs12->host_ia32_perf_global_ctrl);
11040
11041 /* Set L1 segment info according to Intel SDM
11042 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11043 seg = (struct kvm_segment) {
11044 .base = 0,
11045 .limit = 0xFFFFFFFF,
11046 .selector = vmcs12->host_cs_selector,
11047 .type = 11,
11048 .present = 1,
11049 .s = 1,
11050 .g = 1
11051 };
11052 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11053 seg.l = 1;
11054 else
11055 seg.db = 1;
11056 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11057 seg = (struct kvm_segment) {
11058 .base = 0,
11059 .limit = 0xFFFFFFFF,
11060 .type = 3,
11061 .present = 1,
11062 .s = 1,
11063 .db = 1,
11064 .g = 1
11065 };
11066 seg.selector = vmcs12->host_ds_selector;
11067 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11068 seg.selector = vmcs12->host_es_selector;
11069 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11070 seg.selector = vmcs12->host_ss_selector;
11071 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11072 seg.selector = vmcs12->host_fs_selector;
11073 seg.base = vmcs12->host_fs_base;
11074 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11075 seg.selector = vmcs12->host_gs_selector;
11076 seg.base = vmcs12->host_gs_base;
11077 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11078 seg = (struct kvm_segment) {
11079 .base = vmcs12->host_tr_base,
11080 .limit = 0x67,
11081 .selector = vmcs12->host_tr_selector,
11082 .type = 11,
11083 .present = 1
11084 };
11085 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11086
11087 kvm_set_dr(vcpu, 7, 0x400);
11088 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11089
11090 if (cpu_has_vmx_msr_bitmap())
11091 vmx_set_msr_bitmap(vcpu);
11092
11093 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11094 vmcs12->vm_exit_msr_load_count))
11095 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11096 }
11097
11098 /*
11099 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11100 * and modify vmcs12 to make it see what it would expect to see there if
11101 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11102 */
11103 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11104 u32 exit_intr_info,
11105 unsigned long exit_qualification)
11106 {
11107 struct vcpu_vmx *vmx = to_vmx(vcpu);
11108 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11109 u32 vm_inst_error = 0;
11110
11111 /* trying to cancel vmlaunch/vmresume is a bug */
11112 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11113
11114 leave_guest_mode(vcpu);
11115 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11116 exit_qualification);
11117
11118 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11119 vmcs12->vm_exit_msr_store_count))
11120 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11121
11122 if (unlikely(vmx->fail))
11123 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11124
11125 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11126
11127 /*
11128 * TODO: SDM says that with acknowledge interrupt on exit, bit 31 of
11129 * the VM-exit interrupt information (valid interrupt) is always set to
11130 * 1 on EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't need
11131 * kvm_cpu_has_interrupt(). See the commit message for details.
11132 */
11133 if (nested_exit_intr_ack_set(vcpu) &&
11134 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11135 kvm_cpu_has_interrupt(vcpu)) {
11136 int irq = kvm_cpu_get_interrupt(vcpu);
11137 WARN_ON(irq < 0);
11138 vmcs12->vm_exit_intr_info = irq |
11139 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11140 }
11141
11142 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11143 vmcs12->exit_qualification,
11144 vmcs12->idt_vectoring_info_field,
11145 vmcs12->vm_exit_intr_info,
11146 vmcs12->vm_exit_intr_error_code,
11147 KVM_ISA_VMX);
11148
11149 vm_entry_controls_reset_shadow(vmx);
11150 vm_exit_controls_reset_shadow(vmx);
11151 vmx_segment_cache_clear(vmx);
11152
11153 /* if no vmcs02 cache requested, remove the one we used */
11154 if (VMCS02_POOL_SIZE == 0)
11155 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11156
11157 load_vmcs12_host_state(vcpu, vmcs12);
11158
11159 /* Update any VMCS fields that might have changed while L2 ran */
11160 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11161 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11162 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11163 if (vmx->hv_deadline_tsc == -1)
11164 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11165 PIN_BASED_VMX_PREEMPTION_TIMER);
11166 else
11167 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11168 PIN_BASED_VMX_PREEMPTION_TIMER);
11169 if (kvm_has_tsc_control)
11170 decache_tsc_multiplier(vmx);
11171
11172 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11173 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11174 vmx_set_virtual_x2apic_mode(vcpu,
11175 vcpu->arch.apic_base & X2APIC_ENABLE);
11176 } else if (!nested_cpu_has_ept(vmcs12) &&
11177 nested_cpu_has2(vmcs12,
11178 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11179 vmx_flush_tlb_ept_only(vcpu);
11180 }
11181
11182 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11183 vmx->host_rsp = 0;
11184
11185 /* Unpin physical memory we referred to in vmcs02 */
11186 if (vmx->nested.apic_access_page) {
11187 nested_release_page(vmx->nested.apic_access_page);
11188 vmx->nested.apic_access_page = NULL;
11189 }
11190 if (vmx->nested.virtual_apic_page) {
11191 nested_release_page(vmx->nested.virtual_apic_page);
11192 vmx->nested.virtual_apic_page = NULL;
11193 }
11194 if (vmx->nested.pi_desc_page) {
11195 kunmap(vmx->nested.pi_desc_page);
11196 nested_release_page(vmx->nested.pi_desc_page);
11197 vmx->nested.pi_desc_page = NULL;
11198 vmx->nested.pi_desc = NULL;
11199 }
11200
11201 /*
11202 * We are now running in L2, mmu_notifier will force to reload the
11203 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11204 */
11205 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11206
11207 /*
11208 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11209 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11210 * success or failure flag accordingly.
11211 */
11212 if (unlikely(vmx->fail)) {
11213 vmx->fail = 0;
11214 nested_vmx_failValid(vcpu, vm_inst_error);
11215 } else
11216 nested_vmx_succeed(vcpu);
11217 if (enable_shadow_vmcs)
11218 vmx->nested.sync_shadow_vmcs = true;
11219
11220 /* in case we halted in L2 */
11221 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11222 }
11223
11224 /*
11225 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11226 */
11227 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11228 {
11229 if (is_guest_mode(vcpu)) {
11230 to_vmx(vcpu)->nested.nested_run_pending = 0;
11231 nested_vmx_vmexit(vcpu, -1, 0, 0);
11232 }
11233 free_nested(to_vmx(vcpu));
11234 }
11235
11236 /*
11237 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11238 * 23.7 "VM-entry failures during or after loading guest state" (this also
11239 * lists the acceptable exit-reason and exit-qualification parameters).
11240 * It should only be called before L2 actually succeeded to run, and when
11241 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11242 */
11243 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11244 struct vmcs12 *vmcs12,
11245 u32 reason, unsigned long qualification)
11246 {
11247 load_vmcs12_host_state(vcpu, vmcs12);
11248 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11249 vmcs12->exit_qualification = qualification;
11250 nested_vmx_succeed(vcpu);
11251 if (enable_shadow_vmcs)
11252 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11253 }
11254
11255 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11256 struct x86_instruction_info *info,
11257 enum x86_intercept_stage stage)
11258 {
11259 return X86EMUL_CONTINUE;
11260 }
11261
11262 #ifdef CONFIG_X86_64
11263 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11264 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11265 u64 divisor, u64 *result)
11266 {
11267 u64 low = a << shift, high = a >> (64 - shift);
11268
11269 /* To avoid the overflow on divq */
11270 if (high >= divisor)
11271 return 1;
11272
11273 /* Low hold the result, high hold rem which is discarded */
11274 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11275 "rm" (divisor), "0" (low), "1" (high));
11276 *result = low;
11277
11278 return 0;
11279 }
11280
11281 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11282 {
11283 struct vcpu_vmx *vmx = to_vmx(vcpu);
11284 u64 tscl = rdtsc();
11285 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11286 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11287
11288 /* Convert to host delta tsc if tsc scaling is enabled */
11289 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11290 u64_shl_div_u64(delta_tsc,
11291 kvm_tsc_scaling_ratio_frac_bits,
11292 vcpu->arch.tsc_scaling_ratio,
11293 &delta_tsc))
11294 return -ERANGE;
11295
11296 /*
11297 * If the delta tsc can't fit in the 32 bit after the multi shift,
11298 * we can't use the preemption timer.
11299 * It's possible that it fits on later vmentries, but checking
11300 * on every vmentry is costly so we just use an hrtimer.
11301 */
11302 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11303 return -ERANGE;
11304
11305 vmx->hv_deadline_tsc = tscl + delta_tsc;
11306 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11307 PIN_BASED_VMX_PREEMPTION_TIMER);
11308
11309 return delta_tsc == 0;
11310 }
11311
11312 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11313 {
11314 struct vcpu_vmx *vmx = to_vmx(vcpu);
11315 vmx->hv_deadline_tsc = -1;
11316 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11317 PIN_BASED_VMX_PREEMPTION_TIMER);
11318 }
11319 #endif
11320
11321 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11322 {
11323 if (ple_gap)
11324 shrink_ple_window(vcpu);
11325 }
11326
11327 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11328 struct kvm_memory_slot *slot)
11329 {
11330 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11331 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11332 }
11333
11334 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11335 struct kvm_memory_slot *slot)
11336 {
11337 kvm_mmu_slot_set_dirty(kvm, slot);
11338 }
11339
11340 static void vmx_flush_log_dirty(struct kvm *kvm)
11341 {
11342 kvm_flush_pml_buffers(kvm);
11343 }
11344
11345 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11346 {
11347 struct vmcs12 *vmcs12;
11348 struct vcpu_vmx *vmx = to_vmx(vcpu);
11349 gpa_t gpa;
11350 struct page *page = NULL;
11351 u64 *pml_address;
11352
11353 if (is_guest_mode(vcpu)) {
11354 WARN_ON_ONCE(vmx->nested.pml_full);
11355
11356 /*
11357 * Check if PML is enabled for the nested guest.
11358 * Whether eptp bit 6 is set is already checked
11359 * as part of A/D emulation.
11360 */
11361 vmcs12 = get_vmcs12(vcpu);
11362 if (!nested_cpu_has_pml(vmcs12))
11363 return 0;
11364
11365 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11366 vmx->nested.pml_full = true;
11367 return 1;
11368 }
11369
11370 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11371
11372 page = nested_get_page(vcpu, vmcs12->pml_address);
11373 if (!page)
11374 return 0;
11375
11376 pml_address = kmap(page);
11377 pml_address[vmcs12->guest_pml_index--] = gpa;
11378 kunmap(page);
11379 nested_release_page_clean(page);
11380 }
11381
11382 return 0;
11383 }
11384
11385 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11386 struct kvm_memory_slot *memslot,
11387 gfn_t offset, unsigned long mask)
11388 {
11389 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11390 }
11391
11392 static void __pi_post_block(struct kvm_vcpu *vcpu)
11393 {
11394 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11395 struct pi_desc old, new;
11396 unsigned int dest;
11397 unsigned long flags;
11398
11399 do {
11400 old.control = new.control = pi_desc->control;
11401
11402 dest = cpu_physical_id(vcpu->cpu);
11403
11404 if (x2apic_enabled())
11405 new.ndst = dest;
11406 else
11407 new.ndst = (dest << 8) & 0xFF00;
11408
11409 /* Allow posting non-urgent interrupts */
11410 new.sn = 0;
11411
11412 /* set 'NV' to 'notification vector' */
11413 new.nv = POSTED_INTR_VECTOR;
11414 } while (cmpxchg(&pi_desc->control, old.control,
11415 new.control) != old.control);
11416
11417 if(vcpu->pre_pcpu != -1) {
11418 spin_lock_irqsave(
11419 &per_cpu(blocked_vcpu_on_cpu_lock,
11420 vcpu->pre_pcpu), flags);
11421 list_del(&vcpu->blocked_vcpu_list);
11422 spin_unlock_irqrestore(
11423 &per_cpu(blocked_vcpu_on_cpu_lock,
11424 vcpu->pre_pcpu), flags);
11425 vcpu->pre_pcpu = -1;
11426 }
11427 }
11428
11429 /*
11430 * This routine does the following things for vCPU which is going
11431 * to be blocked if VT-d PI is enabled.
11432 * - Store the vCPU to the wakeup list, so when interrupts happen
11433 * we can find the right vCPU to wake up.
11434 * - Change the Posted-interrupt descriptor as below:
11435 * 'NDST' <-- vcpu->pre_pcpu
11436 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11437 * - If 'ON' is set during this process, which means at least one
11438 * interrupt is posted for this vCPU, we cannot block it, in
11439 * this case, return 1, otherwise, return 0.
11440 *
11441 */
11442 static int pi_pre_block(struct kvm_vcpu *vcpu)
11443 {
11444 unsigned long flags;
11445 unsigned int dest;
11446 struct pi_desc old, new;
11447 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11448
11449 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11450 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11451 !kvm_vcpu_apicv_active(vcpu))
11452 return 0;
11453
11454 vcpu->pre_pcpu = vcpu->cpu;
11455 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11456 vcpu->pre_pcpu), flags);
11457 list_add_tail(&vcpu->blocked_vcpu_list,
11458 &per_cpu(blocked_vcpu_on_cpu,
11459 vcpu->pre_pcpu));
11460 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11461 vcpu->pre_pcpu), flags);
11462
11463 do {
11464 old.control = new.control = pi_desc->control;
11465
11466 /*
11467 * We should not block the vCPU if
11468 * an interrupt is posted for it.
11469 */
11470 if (pi_test_on(pi_desc) == 1) {
11471 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11472 vcpu->pre_pcpu), flags);
11473 list_del(&vcpu->blocked_vcpu_list);
11474 spin_unlock_irqrestore(
11475 &per_cpu(blocked_vcpu_on_cpu_lock,
11476 vcpu->pre_pcpu), flags);
11477 vcpu->pre_pcpu = -1;
11478
11479 return 1;
11480 }
11481
11482 WARN((pi_desc->sn == 1),
11483 "Warning: SN field of posted-interrupts "
11484 "is set before blocking\n");
11485
11486 /*
11487 * Since vCPU can be preempted during this process,
11488 * vcpu->cpu could be different with pre_pcpu, we
11489 * need to set pre_pcpu as the destination of wakeup
11490 * notification event, then we can find the right vCPU
11491 * to wakeup in wakeup handler if interrupts happen
11492 * when the vCPU is in blocked state.
11493 */
11494 dest = cpu_physical_id(vcpu->pre_pcpu);
11495
11496 if (x2apic_enabled())
11497 new.ndst = dest;
11498 else
11499 new.ndst = (dest << 8) & 0xFF00;
11500
11501 /* set 'NV' to 'wakeup vector' */
11502 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11503 } while (cmpxchg(&pi_desc->control, old.control,
11504 new.control) != old.control);
11505
11506 return 0;
11507 }
11508
11509 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11510 {
11511 if (pi_pre_block(vcpu))
11512 return 1;
11513
11514 if (kvm_lapic_hv_timer_in_use(vcpu))
11515 kvm_lapic_switch_to_sw_timer(vcpu);
11516
11517 return 0;
11518 }
11519
11520 static void pi_post_block(struct kvm_vcpu *vcpu)
11521 {
11522 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11523 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11524 !kvm_vcpu_apicv_active(vcpu))
11525 return;
11526
11527 __pi_post_block(vcpu);
11528 }
11529
11530 static void vmx_post_block(struct kvm_vcpu *vcpu)
11531 {
11532 if (kvm_x86_ops->set_hv_timer)
11533 kvm_lapic_switch_to_hv_timer(vcpu);
11534
11535 pi_post_block(vcpu);
11536 }
11537
11538 /*
11539 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11540 *
11541 * @kvm: kvm
11542 * @host_irq: host irq of the interrupt
11543 * @guest_irq: gsi of the interrupt
11544 * @set: set or unset PI
11545 * returns 0 on success, < 0 on failure
11546 */
11547 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11548 uint32_t guest_irq, bool set)
11549 {
11550 struct kvm_kernel_irq_routing_entry *e;
11551 struct kvm_irq_routing_table *irq_rt;
11552 struct kvm_lapic_irq irq;
11553 struct kvm_vcpu *vcpu;
11554 struct vcpu_data vcpu_info;
11555 int idx, ret = 0;
11556
11557 if (!kvm_arch_has_assigned_device(kvm) ||
11558 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11559 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11560 return 0;
11561
11562 idx = srcu_read_lock(&kvm->irq_srcu);
11563 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11564 if (guest_irq >= irq_rt->nr_rt_entries ||
11565 hlist_empty(&irq_rt->map[guest_irq])) {
11566 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11567 guest_irq, irq_rt->nr_rt_entries);
11568 goto out;
11569 }
11570
11571 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11572 if (e->type != KVM_IRQ_ROUTING_MSI)
11573 continue;
11574 /*
11575 * VT-d PI cannot support posting multicast/broadcast
11576 * interrupts to a vCPU, we still use interrupt remapping
11577 * for these kind of interrupts.
11578 *
11579 * For lowest-priority interrupts, we only support
11580 * those with single CPU as the destination, e.g. user
11581 * configures the interrupts via /proc/irq or uses
11582 * irqbalance to make the interrupts single-CPU.
11583 *
11584 * We will support full lowest-priority interrupt later.
11585 */
11586
11587 kvm_set_msi_irq(kvm, e, &irq);
11588 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11589 /*
11590 * Make sure the IRTE is in remapped mode if
11591 * we don't handle it in posted mode.
11592 */
11593 ret = irq_set_vcpu_affinity(host_irq, NULL);
11594 if (ret < 0) {
11595 printk(KERN_INFO
11596 "failed to back to remapped mode, irq: %u\n",
11597 host_irq);
11598 goto out;
11599 }
11600
11601 continue;
11602 }
11603
11604 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11605 vcpu_info.vector = irq.vector;
11606
11607 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11608 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11609
11610 if (set)
11611 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11612 else {
11613 /* suppress notification event before unposting */
11614 pi_set_sn(vcpu_to_pi_desc(vcpu));
11615 ret = irq_set_vcpu_affinity(host_irq, NULL);
11616 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11617 }
11618
11619 if (ret < 0) {
11620 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11621 __func__);
11622 goto out;
11623 }
11624 }
11625
11626 ret = 0;
11627 out:
11628 srcu_read_unlock(&kvm->irq_srcu, idx);
11629 return ret;
11630 }
11631
11632 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11633 {
11634 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11635 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11636 FEATURE_CONTROL_LMCE;
11637 else
11638 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11639 ~FEATURE_CONTROL_LMCE;
11640 }
11641
11642 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11643 .cpu_has_kvm_support = cpu_has_kvm_support,
11644 .disabled_by_bios = vmx_disabled_by_bios,
11645 .hardware_setup = hardware_setup,
11646 .hardware_unsetup = hardware_unsetup,
11647 .check_processor_compatibility = vmx_check_processor_compat,
11648 .hardware_enable = hardware_enable,
11649 .hardware_disable = hardware_disable,
11650 .cpu_has_accelerated_tpr = report_flexpriority,
11651 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11652
11653 .vcpu_create = vmx_create_vcpu,
11654 .vcpu_free = vmx_free_vcpu,
11655 .vcpu_reset = vmx_vcpu_reset,
11656
11657 .prepare_guest_switch = vmx_save_host_state,
11658 .vcpu_load = vmx_vcpu_load,
11659 .vcpu_put = vmx_vcpu_put,
11660
11661 .update_bp_intercept = update_exception_bitmap,
11662 .get_msr = vmx_get_msr,
11663 .set_msr = vmx_set_msr,
11664 .get_segment_base = vmx_get_segment_base,
11665 .get_segment = vmx_get_segment,
11666 .set_segment = vmx_set_segment,
11667 .get_cpl = vmx_get_cpl,
11668 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11669 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11670 .decache_cr3 = vmx_decache_cr3,
11671 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11672 .set_cr0 = vmx_set_cr0,
11673 .set_cr3 = vmx_set_cr3,
11674 .set_cr4 = vmx_set_cr4,
11675 .set_efer = vmx_set_efer,
11676 .get_idt = vmx_get_idt,
11677 .set_idt = vmx_set_idt,
11678 .get_gdt = vmx_get_gdt,
11679 .set_gdt = vmx_set_gdt,
11680 .get_dr6 = vmx_get_dr6,
11681 .set_dr6 = vmx_set_dr6,
11682 .set_dr7 = vmx_set_dr7,
11683 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11684 .cache_reg = vmx_cache_reg,
11685 .get_rflags = vmx_get_rflags,
11686 .set_rflags = vmx_set_rflags,
11687
11688 .tlb_flush = vmx_flush_tlb,
11689
11690 .run = vmx_vcpu_run,
11691 .handle_exit = vmx_handle_exit,
11692 .skip_emulated_instruction = skip_emulated_instruction,
11693 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11694 .get_interrupt_shadow = vmx_get_interrupt_shadow,
11695 .patch_hypercall = vmx_patch_hypercall,
11696 .set_irq = vmx_inject_irq,
11697 .set_nmi = vmx_inject_nmi,
11698 .queue_exception = vmx_queue_exception,
11699 .cancel_injection = vmx_cancel_injection,
11700 .interrupt_allowed = vmx_interrupt_allowed,
11701 .nmi_allowed = vmx_nmi_allowed,
11702 .get_nmi_mask = vmx_get_nmi_mask,
11703 .set_nmi_mask = vmx_set_nmi_mask,
11704 .enable_nmi_window = enable_nmi_window,
11705 .enable_irq_window = enable_irq_window,
11706 .update_cr8_intercept = update_cr8_intercept,
11707 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11708 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11709 .get_enable_apicv = vmx_get_enable_apicv,
11710 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11711 .load_eoi_exitmap = vmx_load_eoi_exitmap,
11712 .apicv_post_state_restore = vmx_apicv_post_state_restore,
11713 .hwapic_irr_update = vmx_hwapic_irr_update,
11714 .hwapic_isr_update = vmx_hwapic_isr_update,
11715 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11716 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11717
11718 .set_tss_addr = vmx_set_tss_addr,
11719 .get_tdp_level = get_ept_level,
11720 .get_mt_mask = vmx_get_mt_mask,
11721
11722 .get_exit_info = vmx_get_exit_info,
11723
11724 .get_lpage_level = vmx_get_lpage_level,
11725
11726 .cpuid_update = vmx_cpuid_update,
11727
11728 .rdtscp_supported = vmx_rdtscp_supported,
11729 .invpcid_supported = vmx_invpcid_supported,
11730
11731 .set_supported_cpuid = vmx_set_supported_cpuid,
11732
11733 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11734
11735 .write_tsc_offset = vmx_write_tsc_offset,
11736
11737 .set_tdp_cr3 = vmx_set_cr3,
11738
11739 .check_intercept = vmx_check_intercept,
11740 .handle_external_intr = vmx_handle_external_intr,
11741 .mpx_supported = vmx_mpx_supported,
11742 .xsaves_supported = vmx_xsaves_supported,
11743
11744 .check_nested_events = vmx_check_nested_events,
11745
11746 .sched_in = vmx_sched_in,
11747
11748 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11749 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11750 .flush_log_dirty = vmx_flush_log_dirty,
11751 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11752 .write_log_dirty = vmx_write_pml_buffer,
11753
11754 .pre_block = vmx_pre_block,
11755 .post_block = vmx_post_block,
11756
11757 .pmu_ops = &intel_pmu_ops,
11758
11759 .update_pi_irte = vmx_update_pi_irte,
11760
11761 #ifdef CONFIG_X86_64
11762 .set_hv_timer = vmx_set_hv_timer,
11763 .cancel_hv_timer = vmx_cancel_hv_timer,
11764 #endif
11765
11766 .setup_mce = vmx_setup_mce,
11767 };
11768
11769 static int __init vmx_init(void)
11770 {
11771 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11772 __alignof__(struct vcpu_vmx), THIS_MODULE);
11773 if (r)
11774 return r;
11775
11776 #ifdef CONFIG_KEXEC_CORE
11777 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11778 crash_vmclear_local_loaded_vmcss);
11779 #endif
11780
11781 return 0;
11782 }
11783
11784 static void __exit vmx_exit(void)
11785 {
11786 #ifdef CONFIG_KEXEC_CORE
11787 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11788 synchronize_rcu();
11789 #endif
11790
11791 kvm_exit();
11792 }
11793
11794 module_init(vmx_init)
11795 module_exit(vmx_exit)