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KVM: nVMX: Validate EFER values for VM_ENTRY/EXIT_LOAD_IA32_EFER
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 bool kvm_has_tsc_control;
98 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99 u32 kvm_max_guest_tsc_khz;
100 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
102 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103 static u32 tsc_tolerance_ppm = 250;
104 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
106 #define KVM_NR_SHARED_MSRS 16
107
108 struct kvm_shared_msrs_global {
109 int nr;
110 u32 msrs[KVM_NR_SHARED_MSRS];
111 };
112
113 struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
120 };
121
122 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123 static struct kvm_shared_msrs __percpu *shared_msrs;
124
125 struct kvm_stats_debugfs_item debugfs_entries[] = {
126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
138 { "hypercalls", VCPU_STAT(hypercalls) },
139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
146 { "irq_injections", VCPU_STAT(irq_injections) },
147 { "nmi_injections", VCPU_STAT(nmi_injections) },
148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
155 { "mmu_unsync", VM_STAT(mmu_unsync) },
156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
157 { "largepages", VM_STAT(lpages) },
158 { NULL }
159 };
160
161 u64 __read_mostly host_xcr0;
162
163 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
164
165 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166 {
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170 }
171
172 static void kvm_on_user_return(struct user_return_notifier *urn)
173 {
174 unsigned slot;
175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
177 struct kvm_shared_msr_values *values;
178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188 }
189
190 static void shared_msr_update(unsigned slot, u32 msr)
191 {
192 u64 value;
193 unsigned int cpu = smp_processor_id();
194 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
195
196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205 }
206
207 void kvm_define_shared_msr(unsigned slot, u32 msr)
208 {
209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
214 }
215 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217 static void kvm_shared_msr_cpu_online(void)
218 {
219 unsigned i;
220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
222 shared_msr_update(i, shared_msrs_global.msrs[i]);
223 }
224
225 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
226 {
227 unsigned int cpu = smp_processor_id();
228 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
229
230 if (((value ^ smsr->values[slot].curr) & mask) == 0)
231 return;
232 smsr->values[slot].curr = value;
233 wrmsrl(shared_msrs_global.msrs[slot], value);
234 if (!smsr->registered) {
235 smsr->urn.on_user_return = kvm_on_user_return;
236 user_return_notifier_register(&smsr->urn);
237 smsr->registered = true;
238 }
239 }
240 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
241
242 static void drop_user_return_notifiers(void *ignore)
243 {
244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249 }
250
251 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252 {
253 return vcpu->arch.apic_base;
254 }
255 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258 {
259 /* TODO: reserve bits check */
260 kvm_lapic_set_base(vcpu, data);
261 }
262 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
264 asmlinkage void kvm_spurious_fault(void)
265 {
266 /* Fault while not rebooting. We want the trace. */
267 BUG();
268 }
269 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
270
271 #define EXCPT_BENIGN 0
272 #define EXCPT_CONTRIBUTORY 1
273 #define EXCPT_PF 2
274
275 static int exception_class(int vector)
276 {
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290 }
291
292 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
293 unsigned nr, bool has_error, u32 error_code,
294 bool reinject)
295 {
296 u32 prev_nr;
297 int class1, class2;
298
299 kvm_make_request(KVM_REQ_EVENT, vcpu);
300
301 if (!vcpu->arch.exception.pending) {
302 queue:
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
307 vcpu->arch.exception.reinject = reinject;
308 return;
309 }
310
311 /* to check exception */
312 prev_nr = vcpu->arch.exception.nr;
313 if (prev_nr == DF_VECTOR) {
314 /* triple fault -> shutdown */
315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
316 return;
317 }
318 class1 = exception_class(prev_nr);
319 class2 = exception_class(nr);
320 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322 /* generate double fault per SDM Table 5-5 */
323 vcpu->arch.exception.pending = true;
324 vcpu->arch.exception.has_error_code = true;
325 vcpu->arch.exception.nr = DF_VECTOR;
326 vcpu->arch.exception.error_code = 0;
327 } else
328 /* replace previous exception with a new one in a hope
329 that instruction re-execution will regenerate lost
330 exception */
331 goto queue;
332 }
333
334 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335 {
336 kvm_multiple_exception(vcpu, nr, false, 0, false);
337 }
338 EXPORT_SYMBOL_GPL(kvm_queue_exception);
339
340 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
341 {
342 kvm_multiple_exception(vcpu, nr, false, 0, true);
343 }
344 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
345
346 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
347 {
348 if (err)
349 kvm_inject_gp(vcpu, 0);
350 else
351 kvm_x86_ops->skip_emulated_instruction(vcpu);
352 }
353 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
354
355 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
356 {
357 ++vcpu->stat.pf_guest;
358 vcpu->arch.cr2 = fault->address;
359 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
360 }
361 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
362
363 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
364 {
365 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
367 else
368 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
369 }
370
371 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
372 {
373 atomic_inc(&vcpu->arch.nmi_queued);
374 kvm_make_request(KVM_REQ_NMI, vcpu);
375 }
376 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
377
378 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379 {
380 kvm_multiple_exception(vcpu, nr, true, error_code, false);
381 }
382 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
383
384 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
385 {
386 kvm_multiple_exception(vcpu, nr, true, error_code, true);
387 }
388 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
389
390 /*
391 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
392 * a #GP and return false.
393 */
394 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
395 {
396 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
397 return true;
398 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
399 return false;
400 }
401 EXPORT_SYMBOL_GPL(kvm_require_cpl);
402
403 /*
404 * This function will be used to read from the physical memory of the currently
405 * running guest. The difference to kvm_read_guest_page is that this function
406 * can read from guest physical or from the guest's guest physical memory.
407 */
408 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409 gfn_t ngfn, void *data, int offset, int len,
410 u32 access)
411 {
412 gfn_t real_gfn;
413 gpa_t ngpa;
414
415 ngpa = gfn_to_gpa(ngfn);
416 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417 if (real_gfn == UNMAPPED_GVA)
418 return -EFAULT;
419
420 real_gfn = gpa_to_gfn(real_gfn);
421
422 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
423 }
424 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
425
426 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427 void *data, int offset, int len, u32 access)
428 {
429 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430 data, offset, len, access);
431 }
432
433 /*
434 * Load the pae pdptrs. Return true is they are all valid.
435 */
436 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
437 {
438 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
440 int i;
441 int ret;
442 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
443
444 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445 offset * sizeof(u64), sizeof(pdpte),
446 PFERR_USER_MASK|PFERR_WRITE_MASK);
447 if (ret < 0) {
448 ret = 0;
449 goto out;
450 }
451 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
452 if (is_present_gpte(pdpte[i]) &&
453 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
454 ret = 0;
455 goto out;
456 }
457 }
458 ret = 1;
459
460 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
461 __set_bit(VCPU_EXREG_PDPTR,
462 (unsigned long *)&vcpu->arch.regs_avail);
463 __set_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_dirty);
465 out:
466
467 return ret;
468 }
469 EXPORT_SYMBOL_GPL(load_pdptrs);
470
471 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
472 {
473 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
474 bool changed = true;
475 int offset;
476 gfn_t gfn;
477 int r;
478
479 if (is_long_mode(vcpu) || !is_pae(vcpu))
480 return false;
481
482 if (!test_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail))
484 return true;
485
486 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
488 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489 PFERR_USER_MASK | PFERR_WRITE_MASK);
490 if (r < 0)
491 goto out;
492 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
493 out:
494
495 return changed;
496 }
497
498 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
499 {
500 unsigned long old_cr0 = kvm_read_cr0(vcpu);
501 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502 X86_CR0_CD | X86_CR0_NW;
503
504 cr0 |= X86_CR0_ET;
505
506 #ifdef CONFIG_X86_64
507 if (cr0 & 0xffffffff00000000UL)
508 return 1;
509 #endif
510
511 cr0 &= ~CR0_RESERVED_BITS;
512
513 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
514 return 1;
515
516 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
517 return 1;
518
519 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
520 #ifdef CONFIG_X86_64
521 if ((vcpu->arch.efer & EFER_LME)) {
522 int cs_db, cs_l;
523
524 if (!is_pae(vcpu))
525 return 1;
526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
527 if (cs_l)
528 return 1;
529 } else
530 #endif
531 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
532 kvm_read_cr3(vcpu)))
533 return 1;
534 }
535
536 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
537 return 1;
538
539 kvm_x86_ops->set_cr0(vcpu, cr0);
540
541 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
542 kvm_clear_async_pf_completion_queue(vcpu);
543 kvm_async_pf_hash_reset(vcpu);
544 }
545
546 if ((cr0 ^ old_cr0) & update_bits)
547 kvm_mmu_reset_context(vcpu);
548 return 0;
549 }
550 EXPORT_SYMBOL_GPL(kvm_set_cr0);
551
552 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
553 {
554 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
555 }
556 EXPORT_SYMBOL_GPL(kvm_lmsw);
557
558 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
559 {
560 u64 xcr0;
561
562 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
563 if (index != XCR_XFEATURE_ENABLED_MASK)
564 return 1;
565 xcr0 = xcr;
566 if (kvm_x86_ops->get_cpl(vcpu) != 0)
567 return 1;
568 if (!(xcr0 & XSTATE_FP))
569 return 1;
570 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
571 return 1;
572 if (xcr0 & ~host_xcr0)
573 return 1;
574 vcpu->arch.xcr0 = xcr0;
575 vcpu->guest_xcr0_loaded = 0;
576 return 0;
577 }
578
579 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
580 {
581 if (__kvm_set_xcr(vcpu, index, xcr)) {
582 kvm_inject_gp(vcpu, 0);
583 return 1;
584 }
585 return 0;
586 }
587 EXPORT_SYMBOL_GPL(kvm_set_xcr);
588
589 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
590 {
591 unsigned long old_cr4 = kvm_read_cr4(vcpu);
592 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
593 X86_CR4_PAE | X86_CR4_SMEP;
594 if (cr4 & CR4_RESERVED_BITS)
595 return 1;
596
597 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
598 return 1;
599
600 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
601 return 1;
602
603 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
604 return 1;
605
606 if (is_long_mode(vcpu)) {
607 if (!(cr4 & X86_CR4_PAE))
608 return 1;
609 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
610 && ((cr4 ^ old_cr4) & pdptr_bits)
611 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
612 kvm_read_cr3(vcpu)))
613 return 1;
614
615 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
616 if (!guest_cpuid_has_pcid(vcpu))
617 return 1;
618
619 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
620 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
621 return 1;
622 }
623
624 if (kvm_x86_ops->set_cr4(vcpu, cr4))
625 return 1;
626
627 if (((cr4 ^ old_cr4) & pdptr_bits) ||
628 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
629 kvm_mmu_reset_context(vcpu);
630
631 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
632 kvm_update_cpuid(vcpu);
633
634 return 0;
635 }
636 EXPORT_SYMBOL_GPL(kvm_set_cr4);
637
638 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
639 {
640 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
641 kvm_mmu_sync_roots(vcpu);
642 kvm_mmu_flush_tlb(vcpu);
643 return 0;
644 }
645
646 if (is_long_mode(vcpu)) {
647 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
648 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
649 return 1;
650 } else
651 if (cr3 & CR3_L_MODE_RESERVED_BITS)
652 return 1;
653 } else {
654 if (is_pae(vcpu)) {
655 if (cr3 & CR3_PAE_RESERVED_BITS)
656 return 1;
657 if (is_paging(vcpu) &&
658 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
659 return 1;
660 }
661 /*
662 * We don't check reserved bits in nonpae mode, because
663 * this isn't enforced, and VMware depends on this.
664 */
665 }
666
667 /*
668 * Does the new cr3 value map to physical memory? (Note, we
669 * catch an invalid cr3 even in real-mode, because it would
670 * cause trouble later on when we turn on paging anyway.)
671 *
672 * A real CPU would silently accept an invalid cr3 and would
673 * attempt to use it - with largely undefined (and often hard
674 * to debug) behavior on the guest side.
675 */
676 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
677 return 1;
678 vcpu->arch.cr3 = cr3;
679 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
680 vcpu->arch.mmu.new_cr3(vcpu);
681 return 0;
682 }
683 EXPORT_SYMBOL_GPL(kvm_set_cr3);
684
685 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
686 {
687 if (cr8 & CR8_RESERVED_BITS)
688 return 1;
689 if (irqchip_in_kernel(vcpu->kvm))
690 kvm_lapic_set_tpr(vcpu, cr8);
691 else
692 vcpu->arch.cr8 = cr8;
693 return 0;
694 }
695 EXPORT_SYMBOL_GPL(kvm_set_cr8);
696
697 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
698 {
699 if (irqchip_in_kernel(vcpu->kvm))
700 return kvm_lapic_get_cr8(vcpu);
701 else
702 return vcpu->arch.cr8;
703 }
704 EXPORT_SYMBOL_GPL(kvm_get_cr8);
705
706 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
707 {
708 unsigned long dr7;
709
710 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
711 dr7 = vcpu->arch.guest_debug_dr7;
712 else
713 dr7 = vcpu->arch.dr7;
714 kvm_x86_ops->set_dr7(vcpu, dr7);
715 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
716 }
717
718 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
719 {
720 switch (dr) {
721 case 0 ... 3:
722 vcpu->arch.db[dr] = val;
723 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
724 vcpu->arch.eff_db[dr] = val;
725 break;
726 case 4:
727 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
728 return 1; /* #UD */
729 /* fall through */
730 case 6:
731 if (val & 0xffffffff00000000ULL)
732 return -1; /* #GP */
733 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
734 break;
735 case 5:
736 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
737 return 1; /* #UD */
738 /* fall through */
739 default: /* 7 */
740 if (val & 0xffffffff00000000ULL)
741 return -1; /* #GP */
742 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
743 kvm_update_dr7(vcpu);
744 break;
745 }
746
747 return 0;
748 }
749
750 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
751 {
752 int res;
753
754 res = __kvm_set_dr(vcpu, dr, val);
755 if (res > 0)
756 kvm_queue_exception(vcpu, UD_VECTOR);
757 else if (res < 0)
758 kvm_inject_gp(vcpu, 0);
759
760 return res;
761 }
762 EXPORT_SYMBOL_GPL(kvm_set_dr);
763
764 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
765 {
766 switch (dr) {
767 case 0 ... 3:
768 *val = vcpu->arch.db[dr];
769 break;
770 case 4:
771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
772 return 1;
773 /* fall through */
774 case 6:
775 *val = vcpu->arch.dr6;
776 break;
777 case 5:
778 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
779 return 1;
780 /* fall through */
781 default: /* 7 */
782 *val = vcpu->arch.dr7;
783 break;
784 }
785
786 return 0;
787 }
788
789 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
790 {
791 if (_kvm_get_dr(vcpu, dr, val)) {
792 kvm_queue_exception(vcpu, UD_VECTOR);
793 return 1;
794 }
795 return 0;
796 }
797 EXPORT_SYMBOL_GPL(kvm_get_dr);
798
799 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
800 {
801 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
802 u64 data;
803 int err;
804
805 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
806 if (err)
807 return err;
808 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
809 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
810 return err;
811 }
812 EXPORT_SYMBOL_GPL(kvm_rdpmc);
813
814 /*
815 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
816 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
817 *
818 * This list is modified at module load time to reflect the
819 * capabilities of the host cpu. This capabilities test skips MSRs that are
820 * kvm-specific. Those are put in the beginning of the list.
821 */
822
823 #define KVM_SAVE_MSRS_BEGIN 10
824 static u32 msrs_to_save[] = {
825 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
826 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
827 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
828 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
829 MSR_KVM_PV_EOI_EN,
830 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
831 MSR_STAR,
832 #ifdef CONFIG_X86_64
833 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
834 #endif
835 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
836 };
837
838 static unsigned num_msrs_to_save;
839
840 static const u32 emulated_msrs[] = {
841 MSR_IA32_TSC_ADJUST,
842 MSR_IA32_TSCDEADLINE,
843 MSR_IA32_MISC_ENABLE,
844 MSR_IA32_MCG_STATUS,
845 MSR_IA32_MCG_CTL,
846 };
847
848 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
849 {
850 if (efer & efer_reserved_bits)
851 return false;
852
853 if (efer & EFER_FFXSR) {
854 struct kvm_cpuid_entry2 *feat;
855
856 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
857 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
858 return false;
859 }
860
861 if (efer & EFER_SVME) {
862 struct kvm_cpuid_entry2 *feat;
863
864 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
865 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
866 return false;
867 }
868
869 return true;
870 }
871 EXPORT_SYMBOL_GPL(kvm_valid_efer);
872
873 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
874 {
875 u64 old_efer = vcpu->arch.efer;
876
877 if (!kvm_valid_efer(vcpu, efer))
878 return 1;
879
880 if (is_paging(vcpu)
881 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
882 return 1;
883
884 efer &= ~EFER_LMA;
885 efer |= vcpu->arch.efer & EFER_LMA;
886
887 kvm_x86_ops->set_efer(vcpu, efer);
888
889 /* Update reserved bits */
890 if ((efer ^ old_efer) & EFER_NX)
891 kvm_mmu_reset_context(vcpu);
892
893 return 0;
894 }
895
896 void kvm_enable_efer_bits(u64 mask)
897 {
898 efer_reserved_bits &= ~mask;
899 }
900 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
901
902
903 /*
904 * Writes msr value into into the appropriate "register".
905 * Returns 0 on success, non-0 otherwise.
906 * Assumes vcpu_load() was already called.
907 */
908 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
909 {
910 return kvm_x86_ops->set_msr(vcpu, msr);
911 }
912
913 /*
914 * Adapt set_msr() to msr_io()'s calling convention
915 */
916 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
917 {
918 struct msr_data msr;
919
920 msr.data = *data;
921 msr.index = index;
922 msr.host_initiated = true;
923 return kvm_set_msr(vcpu, &msr);
924 }
925
926 #ifdef CONFIG_X86_64
927 struct pvclock_gtod_data {
928 seqcount_t seq;
929
930 struct { /* extract of a clocksource struct */
931 int vclock_mode;
932 cycle_t cycle_last;
933 cycle_t mask;
934 u32 mult;
935 u32 shift;
936 } clock;
937
938 /* open coded 'struct timespec' */
939 u64 monotonic_time_snsec;
940 time_t monotonic_time_sec;
941 };
942
943 static struct pvclock_gtod_data pvclock_gtod_data;
944
945 static void update_pvclock_gtod(struct timekeeper *tk)
946 {
947 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
948
949 write_seqcount_begin(&vdata->seq);
950
951 /* copy pvclock gtod data */
952 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
953 vdata->clock.cycle_last = tk->clock->cycle_last;
954 vdata->clock.mask = tk->clock->mask;
955 vdata->clock.mult = tk->mult;
956 vdata->clock.shift = tk->shift;
957
958 vdata->monotonic_time_sec = tk->xtime_sec
959 + tk->wall_to_monotonic.tv_sec;
960 vdata->monotonic_time_snsec = tk->xtime_nsec
961 + (tk->wall_to_monotonic.tv_nsec
962 << tk->shift);
963 while (vdata->monotonic_time_snsec >=
964 (((u64)NSEC_PER_SEC) << tk->shift)) {
965 vdata->monotonic_time_snsec -=
966 ((u64)NSEC_PER_SEC) << tk->shift;
967 vdata->monotonic_time_sec++;
968 }
969
970 write_seqcount_end(&vdata->seq);
971 }
972 #endif
973
974
975 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
976 {
977 int version;
978 int r;
979 struct pvclock_wall_clock wc;
980 struct timespec boot;
981
982 if (!wall_clock)
983 return;
984
985 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
986 if (r)
987 return;
988
989 if (version & 1)
990 ++version; /* first time write, random junk */
991
992 ++version;
993
994 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
995
996 /*
997 * The guest calculates current wall clock time by adding
998 * system time (updated by kvm_guest_time_update below) to the
999 * wall clock specified here. guest system time equals host
1000 * system time for us, thus we must fill in host boot time here.
1001 */
1002 getboottime(&boot);
1003
1004 if (kvm->arch.kvmclock_offset) {
1005 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1006 boot = timespec_sub(boot, ts);
1007 }
1008 wc.sec = boot.tv_sec;
1009 wc.nsec = boot.tv_nsec;
1010 wc.version = version;
1011
1012 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1013
1014 version++;
1015 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1016 }
1017
1018 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1019 {
1020 uint32_t quotient, remainder;
1021
1022 /* Don't try to replace with do_div(), this one calculates
1023 * "(dividend << 32) / divisor" */
1024 __asm__ ( "divl %4"
1025 : "=a" (quotient), "=d" (remainder)
1026 : "0" (0), "1" (dividend), "r" (divisor) );
1027 return quotient;
1028 }
1029
1030 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1031 s8 *pshift, u32 *pmultiplier)
1032 {
1033 uint64_t scaled64;
1034 int32_t shift = 0;
1035 uint64_t tps64;
1036 uint32_t tps32;
1037
1038 tps64 = base_khz * 1000LL;
1039 scaled64 = scaled_khz * 1000LL;
1040 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1041 tps64 >>= 1;
1042 shift--;
1043 }
1044
1045 tps32 = (uint32_t)tps64;
1046 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1047 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1048 scaled64 >>= 1;
1049 else
1050 tps32 <<= 1;
1051 shift++;
1052 }
1053
1054 *pshift = shift;
1055 *pmultiplier = div_frac(scaled64, tps32);
1056
1057 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1058 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1059 }
1060
1061 static inline u64 get_kernel_ns(void)
1062 {
1063 struct timespec ts;
1064
1065 WARN_ON(preemptible());
1066 ktime_get_ts(&ts);
1067 monotonic_to_bootbased(&ts);
1068 return timespec_to_ns(&ts);
1069 }
1070
1071 #ifdef CONFIG_X86_64
1072 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1073 #endif
1074
1075 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1076 unsigned long max_tsc_khz;
1077
1078 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1079 {
1080 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1081 vcpu->arch.virtual_tsc_shift);
1082 }
1083
1084 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1085 {
1086 u64 v = (u64)khz * (1000000 + ppm);
1087 do_div(v, 1000000);
1088 return v;
1089 }
1090
1091 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1092 {
1093 u32 thresh_lo, thresh_hi;
1094 int use_scaling = 0;
1095
1096 /* tsc_khz can be zero if TSC calibration fails */
1097 if (this_tsc_khz == 0)
1098 return;
1099
1100 /* Compute a scale to convert nanoseconds in TSC cycles */
1101 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1102 &vcpu->arch.virtual_tsc_shift,
1103 &vcpu->arch.virtual_tsc_mult);
1104 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1105
1106 /*
1107 * Compute the variation in TSC rate which is acceptable
1108 * within the range of tolerance and decide if the
1109 * rate being applied is within that bounds of the hardware
1110 * rate. If so, no scaling or compensation need be done.
1111 */
1112 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1113 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1114 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1115 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1116 use_scaling = 1;
1117 }
1118 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1119 }
1120
1121 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1122 {
1123 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1124 vcpu->arch.virtual_tsc_mult,
1125 vcpu->arch.virtual_tsc_shift);
1126 tsc += vcpu->arch.this_tsc_write;
1127 return tsc;
1128 }
1129
1130 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1131 {
1132 #ifdef CONFIG_X86_64
1133 bool vcpus_matched;
1134 bool do_request = false;
1135 struct kvm_arch *ka = &vcpu->kvm->arch;
1136 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1137
1138 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1139 atomic_read(&vcpu->kvm->online_vcpus));
1140
1141 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1142 if (!ka->use_master_clock)
1143 do_request = 1;
1144
1145 if (!vcpus_matched && ka->use_master_clock)
1146 do_request = 1;
1147
1148 if (do_request)
1149 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1150
1151 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1152 atomic_read(&vcpu->kvm->online_vcpus),
1153 ka->use_master_clock, gtod->clock.vclock_mode);
1154 #endif
1155 }
1156
1157 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1158 {
1159 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1160 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1161 }
1162
1163 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1164 {
1165 struct kvm *kvm = vcpu->kvm;
1166 u64 offset, ns, elapsed;
1167 unsigned long flags;
1168 s64 usdiff;
1169 bool matched;
1170 u64 data = msr->data;
1171
1172 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1173 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1174 ns = get_kernel_ns();
1175 elapsed = ns - kvm->arch.last_tsc_nsec;
1176
1177 if (vcpu->arch.virtual_tsc_khz) {
1178 /* n.b - signed multiplication and division required */
1179 usdiff = data - kvm->arch.last_tsc_write;
1180 #ifdef CONFIG_X86_64
1181 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1182 #else
1183 /* do_div() only does unsigned */
1184 asm("idivl %2; xor %%edx, %%edx"
1185 : "=A"(usdiff)
1186 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1187 #endif
1188 do_div(elapsed, 1000);
1189 usdiff -= elapsed;
1190 if (usdiff < 0)
1191 usdiff = -usdiff;
1192 } else
1193 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1194
1195 /*
1196 * Special case: TSC write with a small delta (1 second) of virtual
1197 * cycle time against real time is interpreted as an attempt to
1198 * synchronize the CPU.
1199 *
1200 * For a reliable TSC, we can match TSC offsets, and for an unstable
1201 * TSC, we add elapsed time in this computation. We could let the
1202 * compensation code attempt to catch up if we fall behind, but
1203 * it's better to try to match offsets from the beginning.
1204 */
1205 if (usdiff < USEC_PER_SEC &&
1206 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1207 if (!check_tsc_unstable()) {
1208 offset = kvm->arch.cur_tsc_offset;
1209 pr_debug("kvm: matched tsc offset for %llu\n", data);
1210 } else {
1211 u64 delta = nsec_to_cycles(vcpu, elapsed);
1212 data += delta;
1213 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1214 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1215 }
1216 matched = true;
1217 } else {
1218 /*
1219 * We split periods of matched TSC writes into generations.
1220 * For each generation, we track the original measured
1221 * nanosecond time, offset, and write, so if TSCs are in
1222 * sync, we can match exact offset, and if not, we can match
1223 * exact software computation in compute_guest_tsc()
1224 *
1225 * These values are tracked in kvm->arch.cur_xxx variables.
1226 */
1227 kvm->arch.cur_tsc_generation++;
1228 kvm->arch.cur_tsc_nsec = ns;
1229 kvm->arch.cur_tsc_write = data;
1230 kvm->arch.cur_tsc_offset = offset;
1231 matched = false;
1232 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1233 kvm->arch.cur_tsc_generation, data);
1234 }
1235
1236 /*
1237 * We also track th most recent recorded KHZ, write and time to
1238 * allow the matching interval to be extended at each write.
1239 */
1240 kvm->arch.last_tsc_nsec = ns;
1241 kvm->arch.last_tsc_write = data;
1242 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1243
1244 /* Reset of TSC must disable overshoot protection below */
1245 vcpu->arch.hv_clock.tsc_timestamp = 0;
1246 vcpu->arch.last_guest_tsc = data;
1247
1248 /* Keep track of which generation this VCPU has synchronized to */
1249 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1250 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1251 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1252
1253 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1254 update_ia32_tsc_adjust_msr(vcpu, offset);
1255 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1256 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1257
1258 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1259 if (matched)
1260 kvm->arch.nr_vcpus_matched_tsc++;
1261 else
1262 kvm->arch.nr_vcpus_matched_tsc = 0;
1263
1264 kvm_track_tsc_matching(vcpu);
1265 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1266 }
1267
1268 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1269
1270 #ifdef CONFIG_X86_64
1271
1272 static cycle_t read_tsc(void)
1273 {
1274 cycle_t ret;
1275 u64 last;
1276
1277 /*
1278 * Empirically, a fence (of type that depends on the CPU)
1279 * before rdtsc is enough to ensure that rdtsc is ordered
1280 * with respect to loads. The various CPU manuals are unclear
1281 * as to whether rdtsc can be reordered with later loads,
1282 * but no one has ever seen it happen.
1283 */
1284 rdtsc_barrier();
1285 ret = (cycle_t)vget_cycles();
1286
1287 last = pvclock_gtod_data.clock.cycle_last;
1288
1289 if (likely(ret >= last))
1290 return ret;
1291
1292 /*
1293 * GCC likes to generate cmov here, but this branch is extremely
1294 * predictable (it's just a funciton of time and the likely is
1295 * very likely) and there's a data dependence, so force GCC
1296 * to generate a branch instead. I don't barrier() because
1297 * we don't actually need a barrier, and if this function
1298 * ever gets inlined it will generate worse code.
1299 */
1300 asm volatile ("");
1301 return last;
1302 }
1303
1304 static inline u64 vgettsc(cycle_t *cycle_now)
1305 {
1306 long v;
1307 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1308
1309 *cycle_now = read_tsc();
1310
1311 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1312 return v * gtod->clock.mult;
1313 }
1314
1315 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1316 {
1317 unsigned long seq;
1318 u64 ns;
1319 int mode;
1320 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1321
1322 ts->tv_nsec = 0;
1323 do {
1324 seq = read_seqcount_begin(&gtod->seq);
1325 mode = gtod->clock.vclock_mode;
1326 ts->tv_sec = gtod->monotonic_time_sec;
1327 ns = gtod->monotonic_time_snsec;
1328 ns += vgettsc(cycle_now);
1329 ns >>= gtod->clock.shift;
1330 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1331 timespec_add_ns(ts, ns);
1332
1333 return mode;
1334 }
1335
1336 /* returns true if host is using tsc clocksource */
1337 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1338 {
1339 struct timespec ts;
1340
1341 /* checked again under seqlock below */
1342 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1343 return false;
1344
1345 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1346 return false;
1347
1348 monotonic_to_bootbased(&ts);
1349 *kernel_ns = timespec_to_ns(&ts);
1350
1351 return true;
1352 }
1353 #endif
1354
1355 /*
1356 *
1357 * Assuming a stable TSC across physical CPUS, and a stable TSC
1358 * across virtual CPUs, the following condition is possible.
1359 * Each numbered line represents an event visible to both
1360 * CPUs at the next numbered event.
1361 *
1362 * "timespecX" represents host monotonic time. "tscX" represents
1363 * RDTSC value.
1364 *
1365 * VCPU0 on CPU0 | VCPU1 on CPU1
1366 *
1367 * 1. read timespec0,tsc0
1368 * 2. | timespec1 = timespec0 + N
1369 * | tsc1 = tsc0 + M
1370 * 3. transition to guest | transition to guest
1371 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1372 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1373 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1374 *
1375 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1376 *
1377 * - ret0 < ret1
1378 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1379 * ...
1380 * - 0 < N - M => M < N
1381 *
1382 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1383 * always the case (the difference between two distinct xtime instances
1384 * might be smaller then the difference between corresponding TSC reads,
1385 * when updating guest vcpus pvclock areas).
1386 *
1387 * To avoid that problem, do not allow visibility of distinct
1388 * system_timestamp/tsc_timestamp values simultaneously: use a master
1389 * copy of host monotonic time values. Update that master copy
1390 * in lockstep.
1391 *
1392 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1393 *
1394 */
1395
1396 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1397 {
1398 #ifdef CONFIG_X86_64
1399 struct kvm_arch *ka = &kvm->arch;
1400 int vclock_mode;
1401 bool host_tsc_clocksource, vcpus_matched;
1402
1403 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1404 atomic_read(&kvm->online_vcpus));
1405
1406 /*
1407 * If the host uses TSC clock, then passthrough TSC as stable
1408 * to the guest.
1409 */
1410 host_tsc_clocksource = kvm_get_time_and_clockread(
1411 &ka->master_kernel_ns,
1412 &ka->master_cycle_now);
1413
1414 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1415
1416 if (ka->use_master_clock)
1417 atomic_set(&kvm_guest_has_master_clock, 1);
1418
1419 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1420 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1421 vcpus_matched);
1422 #endif
1423 }
1424
1425 static int kvm_guest_time_update(struct kvm_vcpu *v)
1426 {
1427 unsigned long flags, this_tsc_khz;
1428 struct kvm_vcpu_arch *vcpu = &v->arch;
1429 struct kvm_arch *ka = &v->kvm->arch;
1430 s64 kernel_ns, max_kernel_ns;
1431 u64 tsc_timestamp, host_tsc;
1432 struct pvclock_vcpu_time_info guest_hv_clock;
1433 u8 pvclock_flags;
1434 bool use_master_clock;
1435
1436 kernel_ns = 0;
1437 host_tsc = 0;
1438
1439 /*
1440 * If the host uses TSC clock, then passthrough TSC as stable
1441 * to the guest.
1442 */
1443 spin_lock(&ka->pvclock_gtod_sync_lock);
1444 use_master_clock = ka->use_master_clock;
1445 if (use_master_clock) {
1446 host_tsc = ka->master_cycle_now;
1447 kernel_ns = ka->master_kernel_ns;
1448 }
1449 spin_unlock(&ka->pvclock_gtod_sync_lock);
1450
1451 /* Keep irq disabled to prevent changes to the clock */
1452 local_irq_save(flags);
1453 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1454 if (unlikely(this_tsc_khz == 0)) {
1455 local_irq_restore(flags);
1456 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1457 return 1;
1458 }
1459 if (!use_master_clock) {
1460 host_tsc = native_read_tsc();
1461 kernel_ns = get_kernel_ns();
1462 }
1463
1464 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1465
1466 /*
1467 * We may have to catch up the TSC to match elapsed wall clock
1468 * time for two reasons, even if kvmclock is used.
1469 * 1) CPU could have been running below the maximum TSC rate
1470 * 2) Broken TSC compensation resets the base at each VCPU
1471 * entry to avoid unknown leaps of TSC even when running
1472 * again on the same CPU. This may cause apparent elapsed
1473 * time to disappear, and the guest to stand still or run
1474 * very slowly.
1475 */
1476 if (vcpu->tsc_catchup) {
1477 u64 tsc = compute_guest_tsc(v, kernel_ns);
1478 if (tsc > tsc_timestamp) {
1479 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1480 tsc_timestamp = tsc;
1481 }
1482 }
1483
1484 local_irq_restore(flags);
1485
1486 if (!vcpu->pv_time_enabled)
1487 return 0;
1488
1489 /*
1490 * Time as measured by the TSC may go backwards when resetting the base
1491 * tsc_timestamp. The reason for this is that the TSC resolution is
1492 * higher than the resolution of the other clock scales. Thus, many
1493 * possible measurments of the TSC correspond to one measurement of any
1494 * other clock, and so a spread of values is possible. This is not a
1495 * problem for the computation of the nanosecond clock; with TSC rates
1496 * around 1GHZ, there can only be a few cycles which correspond to one
1497 * nanosecond value, and any path through this code will inevitably
1498 * take longer than that. However, with the kernel_ns value itself,
1499 * the precision may be much lower, down to HZ granularity. If the
1500 * first sampling of TSC against kernel_ns ends in the low part of the
1501 * range, and the second in the high end of the range, we can get:
1502 *
1503 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1504 *
1505 * As the sampling errors potentially range in the thousands of cycles,
1506 * it is possible such a time value has already been observed by the
1507 * guest. To protect against this, we must compute the system time as
1508 * observed by the guest and ensure the new system time is greater.
1509 */
1510 max_kernel_ns = 0;
1511 if (vcpu->hv_clock.tsc_timestamp) {
1512 max_kernel_ns = vcpu->last_guest_tsc -
1513 vcpu->hv_clock.tsc_timestamp;
1514 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1515 vcpu->hv_clock.tsc_to_system_mul,
1516 vcpu->hv_clock.tsc_shift);
1517 max_kernel_ns += vcpu->last_kernel_ns;
1518 }
1519
1520 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1521 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1522 &vcpu->hv_clock.tsc_shift,
1523 &vcpu->hv_clock.tsc_to_system_mul);
1524 vcpu->hw_tsc_khz = this_tsc_khz;
1525 }
1526
1527 /* with a master <monotonic time, tsc value> tuple,
1528 * pvclock clock reads always increase at the (scaled) rate
1529 * of guest TSC - no need to deal with sampling errors.
1530 */
1531 if (!use_master_clock) {
1532 if (max_kernel_ns > kernel_ns)
1533 kernel_ns = max_kernel_ns;
1534 }
1535 /* With all the info we got, fill in the values */
1536 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1537 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1538 vcpu->last_kernel_ns = kernel_ns;
1539 vcpu->last_guest_tsc = tsc_timestamp;
1540
1541 /*
1542 * The interface expects us to write an even number signaling that the
1543 * update is finished. Since the guest won't see the intermediate
1544 * state, we just increase by 2 at the end.
1545 */
1546 vcpu->hv_clock.version += 2;
1547
1548 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1549 &guest_hv_clock, sizeof(guest_hv_clock))))
1550 return 0;
1551
1552 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1553 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1554
1555 if (vcpu->pvclock_set_guest_stopped_request) {
1556 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1557 vcpu->pvclock_set_guest_stopped_request = false;
1558 }
1559
1560 /* If the host uses TSC clocksource, then it is stable */
1561 if (use_master_clock)
1562 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1563
1564 vcpu->hv_clock.flags = pvclock_flags;
1565
1566 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1567 &vcpu->hv_clock,
1568 sizeof(vcpu->hv_clock));
1569 return 0;
1570 }
1571
1572 static bool msr_mtrr_valid(unsigned msr)
1573 {
1574 switch (msr) {
1575 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1576 case MSR_MTRRfix64K_00000:
1577 case MSR_MTRRfix16K_80000:
1578 case MSR_MTRRfix16K_A0000:
1579 case MSR_MTRRfix4K_C0000:
1580 case MSR_MTRRfix4K_C8000:
1581 case MSR_MTRRfix4K_D0000:
1582 case MSR_MTRRfix4K_D8000:
1583 case MSR_MTRRfix4K_E0000:
1584 case MSR_MTRRfix4K_E8000:
1585 case MSR_MTRRfix4K_F0000:
1586 case MSR_MTRRfix4K_F8000:
1587 case MSR_MTRRdefType:
1588 case MSR_IA32_CR_PAT:
1589 return true;
1590 case 0x2f8:
1591 return true;
1592 }
1593 return false;
1594 }
1595
1596 static bool valid_pat_type(unsigned t)
1597 {
1598 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1599 }
1600
1601 static bool valid_mtrr_type(unsigned t)
1602 {
1603 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1604 }
1605
1606 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1607 {
1608 int i;
1609
1610 if (!msr_mtrr_valid(msr))
1611 return false;
1612
1613 if (msr == MSR_IA32_CR_PAT) {
1614 for (i = 0; i < 8; i++)
1615 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1616 return false;
1617 return true;
1618 } else if (msr == MSR_MTRRdefType) {
1619 if (data & ~0xcff)
1620 return false;
1621 return valid_mtrr_type(data & 0xff);
1622 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1623 for (i = 0; i < 8 ; i++)
1624 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1625 return false;
1626 return true;
1627 }
1628
1629 /* variable MTRRs */
1630 return valid_mtrr_type(data & 0xff);
1631 }
1632
1633 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1634 {
1635 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1636
1637 if (!mtrr_valid(vcpu, msr, data))
1638 return 1;
1639
1640 if (msr == MSR_MTRRdefType) {
1641 vcpu->arch.mtrr_state.def_type = data;
1642 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1643 } else if (msr == MSR_MTRRfix64K_00000)
1644 p[0] = data;
1645 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1646 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1647 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1648 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1649 else if (msr == MSR_IA32_CR_PAT)
1650 vcpu->arch.pat = data;
1651 else { /* Variable MTRRs */
1652 int idx, is_mtrr_mask;
1653 u64 *pt;
1654
1655 idx = (msr - 0x200) / 2;
1656 is_mtrr_mask = msr - 0x200 - 2 * idx;
1657 if (!is_mtrr_mask)
1658 pt =
1659 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1660 else
1661 pt =
1662 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1663 *pt = data;
1664 }
1665
1666 kvm_mmu_reset_context(vcpu);
1667 return 0;
1668 }
1669
1670 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1671 {
1672 u64 mcg_cap = vcpu->arch.mcg_cap;
1673 unsigned bank_num = mcg_cap & 0xff;
1674
1675 switch (msr) {
1676 case MSR_IA32_MCG_STATUS:
1677 vcpu->arch.mcg_status = data;
1678 break;
1679 case MSR_IA32_MCG_CTL:
1680 if (!(mcg_cap & MCG_CTL_P))
1681 return 1;
1682 if (data != 0 && data != ~(u64)0)
1683 return -1;
1684 vcpu->arch.mcg_ctl = data;
1685 break;
1686 default:
1687 if (msr >= MSR_IA32_MC0_CTL &&
1688 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1689 u32 offset = msr - MSR_IA32_MC0_CTL;
1690 /* only 0 or all 1s can be written to IA32_MCi_CTL
1691 * some Linux kernels though clear bit 10 in bank 4 to
1692 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1693 * this to avoid an uncatched #GP in the guest
1694 */
1695 if ((offset & 0x3) == 0 &&
1696 data != 0 && (data | (1 << 10)) != ~(u64)0)
1697 return -1;
1698 vcpu->arch.mce_banks[offset] = data;
1699 break;
1700 }
1701 return 1;
1702 }
1703 return 0;
1704 }
1705
1706 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1707 {
1708 struct kvm *kvm = vcpu->kvm;
1709 int lm = is_long_mode(vcpu);
1710 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1711 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1712 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1713 : kvm->arch.xen_hvm_config.blob_size_32;
1714 u32 page_num = data & ~PAGE_MASK;
1715 u64 page_addr = data & PAGE_MASK;
1716 u8 *page;
1717 int r;
1718
1719 r = -E2BIG;
1720 if (page_num >= blob_size)
1721 goto out;
1722 r = -ENOMEM;
1723 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1724 if (IS_ERR(page)) {
1725 r = PTR_ERR(page);
1726 goto out;
1727 }
1728 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1729 goto out_free;
1730 r = 0;
1731 out_free:
1732 kfree(page);
1733 out:
1734 return r;
1735 }
1736
1737 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1738 {
1739 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1740 }
1741
1742 static bool kvm_hv_msr_partition_wide(u32 msr)
1743 {
1744 bool r = false;
1745 switch (msr) {
1746 case HV_X64_MSR_GUEST_OS_ID:
1747 case HV_X64_MSR_HYPERCALL:
1748 r = true;
1749 break;
1750 }
1751
1752 return r;
1753 }
1754
1755 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1756 {
1757 struct kvm *kvm = vcpu->kvm;
1758
1759 switch (msr) {
1760 case HV_X64_MSR_GUEST_OS_ID:
1761 kvm->arch.hv_guest_os_id = data;
1762 /* setting guest os id to zero disables hypercall page */
1763 if (!kvm->arch.hv_guest_os_id)
1764 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1765 break;
1766 case HV_X64_MSR_HYPERCALL: {
1767 u64 gfn;
1768 unsigned long addr;
1769 u8 instructions[4];
1770
1771 /* if guest os id is not set hypercall should remain disabled */
1772 if (!kvm->arch.hv_guest_os_id)
1773 break;
1774 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1775 kvm->arch.hv_hypercall = data;
1776 break;
1777 }
1778 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1779 addr = gfn_to_hva(kvm, gfn);
1780 if (kvm_is_error_hva(addr))
1781 return 1;
1782 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1783 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1784 if (__copy_to_user((void __user *)addr, instructions, 4))
1785 return 1;
1786 kvm->arch.hv_hypercall = data;
1787 break;
1788 }
1789 default:
1790 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1791 "data 0x%llx\n", msr, data);
1792 return 1;
1793 }
1794 return 0;
1795 }
1796
1797 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1798 {
1799 switch (msr) {
1800 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1801 unsigned long addr;
1802
1803 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1804 vcpu->arch.hv_vapic = data;
1805 break;
1806 }
1807 addr = gfn_to_hva(vcpu->kvm, data >>
1808 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1809 if (kvm_is_error_hva(addr))
1810 return 1;
1811 if (__clear_user((void __user *)addr, PAGE_SIZE))
1812 return 1;
1813 vcpu->arch.hv_vapic = data;
1814 break;
1815 }
1816 case HV_X64_MSR_EOI:
1817 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1818 case HV_X64_MSR_ICR:
1819 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1820 case HV_X64_MSR_TPR:
1821 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1822 default:
1823 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1824 "data 0x%llx\n", msr, data);
1825 return 1;
1826 }
1827
1828 return 0;
1829 }
1830
1831 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1832 {
1833 gpa_t gpa = data & ~0x3f;
1834
1835 /* Bits 2:5 are reserved, Should be zero */
1836 if (data & 0x3c)
1837 return 1;
1838
1839 vcpu->arch.apf.msr_val = data;
1840
1841 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1842 kvm_clear_async_pf_completion_queue(vcpu);
1843 kvm_async_pf_hash_reset(vcpu);
1844 return 0;
1845 }
1846
1847 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1848 return 1;
1849
1850 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1851 kvm_async_pf_wakeup_all(vcpu);
1852 return 0;
1853 }
1854
1855 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1856 {
1857 vcpu->arch.pv_time_enabled = false;
1858 }
1859
1860 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1861 {
1862 u64 delta;
1863
1864 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1865 return;
1866
1867 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1868 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1869 vcpu->arch.st.accum_steal = delta;
1870 }
1871
1872 static void record_steal_time(struct kvm_vcpu *vcpu)
1873 {
1874 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1875 return;
1876
1877 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1878 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1879 return;
1880
1881 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1882 vcpu->arch.st.steal.version += 2;
1883 vcpu->arch.st.accum_steal = 0;
1884
1885 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1886 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1887 }
1888
1889 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1890 {
1891 bool pr = false;
1892 u32 msr = msr_info->index;
1893 u64 data = msr_info->data;
1894
1895 switch (msr) {
1896 case MSR_AMD64_NB_CFG:
1897 case MSR_IA32_UCODE_REV:
1898 case MSR_IA32_UCODE_WRITE:
1899 case MSR_VM_HSAVE_PA:
1900 case MSR_AMD64_PATCH_LOADER:
1901 case MSR_AMD64_BU_CFG2:
1902 break;
1903
1904 case MSR_EFER:
1905 return set_efer(vcpu, data);
1906 case MSR_K7_HWCR:
1907 data &= ~(u64)0x40; /* ignore flush filter disable */
1908 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1909 data &= ~(u64)0x8; /* ignore TLB cache disable */
1910 if (data != 0) {
1911 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1912 data);
1913 return 1;
1914 }
1915 break;
1916 case MSR_FAM10H_MMIO_CONF_BASE:
1917 if (data != 0) {
1918 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1919 "0x%llx\n", data);
1920 return 1;
1921 }
1922 break;
1923 case MSR_IA32_DEBUGCTLMSR:
1924 if (!data) {
1925 /* We support the non-activated case already */
1926 break;
1927 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1928 /* Values other than LBR and BTF are vendor-specific,
1929 thus reserved and should throw a #GP */
1930 return 1;
1931 }
1932 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1933 __func__, data);
1934 break;
1935 case 0x200 ... 0x2ff:
1936 return set_msr_mtrr(vcpu, msr, data);
1937 case MSR_IA32_APICBASE:
1938 kvm_set_apic_base(vcpu, data);
1939 break;
1940 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1941 return kvm_x2apic_msr_write(vcpu, msr, data);
1942 case MSR_IA32_TSCDEADLINE:
1943 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1944 break;
1945 case MSR_IA32_TSC_ADJUST:
1946 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1947 if (!msr_info->host_initiated) {
1948 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1949 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1950 }
1951 vcpu->arch.ia32_tsc_adjust_msr = data;
1952 }
1953 break;
1954 case MSR_IA32_MISC_ENABLE:
1955 vcpu->arch.ia32_misc_enable_msr = data;
1956 break;
1957 case MSR_KVM_WALL_CLOCK_NEW:
1958 case MSR_KVM_WALL_CLOCK:
1959 vcpu->kvm->arch.wall_clock = data;
1960 kvm_write_wall_clock(vcpu->kvm, data);
1961 break;
1962 case MSR_KVM_SYSTEM_TIME_NEW:
1963 case MSR_KVM_SYSTEM_TIME: {
1964 u64 gpa_offset;
1965 kvmclock_reset(vcpu);
1966
1967 vcpu->arch.time = data;
1968 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1969
1970 /* we verify if the enable bit is set... */
1971 if (!(data & 1))
1972 break;
1973
1974 gpa_offset = data & ~(PAGE_MASK | 1);
1975
1976 /* Check that the address is 32-byte aligned. */
1977 if (gpa_offset & (sizeof(struct pvclock_vcpu_time_info) - 1))
1978 break;
1979
1980 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1981 &vcpu->arch.pv_time, data & ~1ULL))
1982 vcpu->arch.pv_time_enabled = false;
1983 else
1984 vcpu->arch.pv_time_enabled = true;
1985
1986 break;
1987 }
1988 case MSR_KVM_ASYNC_PF_EN:
1989 if (kvm_pv_enable_async_pf(vcpu, data))
1990 return 1;
1991 break;
1992 case MSR_KVM_STEAL_TIME:
1993
1994 if (unlikely(!sched_info_on()))
1995 return 1;
1996
1997 if (data & KVM_STEAL_RESERVED_MASK)
1998 return 1;
1999
2000 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2001 data & KVM_STEAL_VALID_BITS))
2002 return 1;
2003
2004 vcpu->arch.st.msr_val = data;
2005
2006 if (!(data & KVM_MSR_ENABLED))
2007 break;
2008
2009 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2010
2011 preempt_disable();
2012 accumulate_steal_time(vcpu);
2013 preempt_enable();
2014
2015 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2016
2017 break;
2018 case MSR_KVM_PV_EOI_EN:
2019 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2020 return 1;
2021 break;
2022
2023 case MSR_IA32_MCG_CTL:
2024 case MSR_IA32_MCG_STATUS:
2025 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2026 return set_msr_mce(vcpu, msr, data);
2027
2028 /* Performance counters are not protected by a CPUID bit,
2029 * so we should check all of them in the generic path for the sake of
2030 * cross vendor migration.
2031 * Writing a zero into the event select MSRs disables them,
2032 * which we perfectly emulate ;-). Any other value should be at least
2033 * reported, some guests depend on them.
2034 */
2035 case MSR_K7_EVNTSEL0:
2036 case MSR_K7_EVNTSEL1:
2037 case MSR_K7_EVNTSEL2:
2038 case MSR_K7_EVNTSEL3:
2039 if (data != 0)
2040 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2041 "0x%x data 0x%llx\n", msr, data);
2042 break;
2043 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2044 * so we ignore writes to make it happy.
2045 */
2046 case MSR_K7_PERFCTR0:
2047 case MSR_K7_PERFCTR1:
2048 case MSR_K7_PERFCTR2:
2049 case MSR_K7_PERFCTR3:
2050 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2051 "0x%x data 0x%llx\n", msr, data);
2052 break;
2053 case MSR_P6_PERFCTR0:
2054 case MSR_P6_PERFCTR1:
2055 pr = true;
2056 case MSR_P6_EVNTSEL0:
2057 case MSR_P6_EVNTSEL1:
2058 if (kvm_pmu_msr(vcpu, msr))
2059 return kvm_pmu_set_msr(vcpu, msr_info);
2060
2061 if (pr || data != 0)
2062 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2063 "0x%x data 0x%llx\n", msr, data);
2064 break;
2065 case MSR_K7_CLK_CTL:
2066 /*
2067 * Ignore all writes to this no longer documented MSR.
2068 * Writes are only relevant for old K7 processors,
2069 * all pre-dating SVM, but a recommended workaround from
2070 * AMD for these chips. It is possible to specify the
2071 * affected processor models on the command line, hence
2072 * the need to ignore the workaround.
2073 */
2074 break;
2075 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2076 if (kvm_hv_msr_partition_wide(msr)) {
2077 int r;
2078 mutex_lock(&vcpu->kvm->lock);
2079 r = set_msr_hyperv_pw(vcpu, msr, data);
2080 mutex_unlock(&vcpu->kvm->lock);
2081 return r;
2082 } else
2083 return set_msr_hyperv(vcpu, msr, data);
2084 break;
2085 case MSR_IA32_BBL_CR_CTL3:
2086 /* Drop writes to this legacy MSR -- see rdmsr
2087 * counterpart for further detail.
2088 */
2089 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2090 break;
2091 case MSR_AMD64_OSVW_ID_LENGTH:
2092 if (!guest_cpuid_has_osvw(vcpu))
2093 return 1;
2094 vcpu->arch.osvw.length = data;
2095 break;
2096 case MSR_AMD64_OSVW_STATUS:
2097 if (!guest_cpuid_has_osvw(vcpu))
2098 return 1;
2099 vcpu->arch.osvw.status = data;
2100 break;
2101 default:
2102 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2103 return xen_hvm_config(vcpu, data);
2104 if (kvm_pmu_msr(vcpu, msr))
2105 return kvm_pmu_set_msr(vcpu, msr_info);
2106 if (!ignore_msrs) {
2107 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2108 msr, data);
2109 return 1;
2110 } else {
2111 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2112 msr, data);
2113 break;
2114 }
2115 }
2116 return 0;
2117 }
2118 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2119
2120
2121 /*
2122 * Reads an msr value (of 'msr_index') into 'pdata'.
2123 * Returns 0 on success, non-0 otherwise.
2124 * Assumes vcpu_load() was already called.
2125 */
2126 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2127 {
2128 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2129 }
2130
2131 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2132 {
2133 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2134
2135 if (!msr_mtrr_valid(msr))
2136 return 1;
2137
2138 if (msr == MSR_MTRRdefType)
2139 *pdata = vcpu->arch.mtrr_state.def_type +
2140 (vcpu->arch.mtrr_state.enabled << 10);
2141 else if (msr == MSR_MTRRfix64K_00000)
2142 *pdata = p[0];
2143 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2144 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2145 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2146 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2147 else if (msr == MSR_IA32_CR_PAT)
2148 *pdata = vcpu->arch.pat;
2149 else { /* Variable MTRRs */
2150 int idx, is_mtrr_mask;
2151 u64 *pt;
2152
2153 idx = (msr - 0x200) / 2;
2154 is_mtrr_mask = msr - 0x200 - 2 * idx;
2155 if (!is_mtrr_mask)
2156 pt =
2157 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2158 else
2159 pt =
2160 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2161 *pdata = *pt;
2162 }
2163
2164 return 0;
2165 }
2166
2167 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2168 {
2169 u64 data;
2170 u64 mcg_cap = vcpu->arch.mcg_cap;
2171 unsigned bank_num = mcg_cap & 0xff;
2172
2173 switch (msr) {
2174 case MSR_IA32_P5_MC_ADDR:
2175 case MSR_IA32_P5_MC_TYPE:
2176 data = 0;
2177 break;
2178 case MSR_IA32_MCG_CAP:
2179 data = vcpu->arch.mcg_cap;
2180 break;
2181 case MSR_IA32_MCG_CTL:
2182 if (!(mcg_cap & MCG_CTL_P))
2183 return 1;
2184 data = vcpu->arch.mcg_ctl;
2185 break;
2186 case MSR_IA32_MCG_STATUS:
2187 data = vcpu->arch.mcg_status;
2188 break;
2189 default:
2190 if (msr >= MSR_IA32_MC0_CTL &&
2191 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2192 u32 offset = msr - MSR_IA32_MC0_CTL;
2193 data = vcpu->arch.mce_banks[offset];
2194 break;
2195 }
2196 return 1;
2197 }
2198 *pdata = data;
2199 return 0;
2200 }
2201
2202 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2203 {
2204 u64 data = 0;
2205 struct kvm *kvm = vcpu->kvm;
2206
2207 switch (msr) {
2208 case HV_X64_MSR_GUEST_OS_ID:
2209 data = kvm->arch.hv_guest_os_id;
2210 break;
2211 case HV_X64_MSR_HYPERCALL:
2212 data = kvm->arch.hv_hypercall;
2213 break;
2214 default:
2215 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2216 return 1;
2217 }
2218
2219 *pdata = data;
2220 return 0;
2221 }
2222
2223 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2224 {
2225 u64 data = 0;
2226
2227 switch (msr) {
2228 case HV_X64_MSR_VP_INDEX: {
2229 int r;
2230 struct kvm_vcpu *v;
2231 kvm_for_each_vcpu(r, v, vcpu->kvm)
2232 if (v == vcpu)
2233 data = r;
2234 break;
2235 }
2236 case HV_X64_MSR_EOI:
2237 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2238 case HV_X64_MSR_ICR:
2239 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2240 case HV_X64_MSR_TPR:
2241 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2242 case HV_X64_MSR_APIC_ASSIST_PAGE:
2243 data = vcpu->arch.hv_vapic;
2244 break;
2245 default:
2246 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2247 return 1;
2248 }
2249 *pdata = data;
2250 return 0;
2251 }
2252
2253 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2254 {
2255 u64 data;
2256
2257 switch (msr) {
2258 case MSR_IA32_PLATFORM_ID:
2259 case MSR_IA32_EBL_CR_POWERON:
2260 case MSR_IA32_DEBUGCTLMSR:
2261 case MSR_IA32_LASTBRANCHFROMIP:
2262 case MSR_IA32_LASTBRANCHTOIP:
2263 case MSR_IA32_LASTINTFROMIP:
2264 case MSR_IA32_LASTINTTOIP:
2265 case MSR_K8_SYSCFG:
2266 case MSR_K7_HWCR:
2267 case MSR_VM_HSAVE_PA:
2268 case MSR_K7_EVNTSEL0:
2269 case MSR_K7_PERFCTR0:
2270 case MSR_K8_INT_PENDING_MSG:
2271 case MSR_AMD64_NB_CFG:
2272 case MSR_FAM10H_MMIO_CONF_BASE:
2273 case MSR_AMD64_BU_CFG2:
2274 data = 0;
2275 break;
2276 case MSR_P6_PERFCTR0:
2277 case MSR_P6_PERFCTR1:
2278 case MSR_P6_EVNTSEL0:
2279 case MSR_P6_EVNTSEL1:
2280 if (kvm_pmu_msr(vcpu, msr))
2281 return kvm_pmu_get_msr(vcpu, msr, pdata);
2282 data = 0;
2283 break;
2284 case MSR_IA32_UCODE_REV:
2285 data = 0x100000000ULL;
2286 break;
2287 case MSR_MTRRcap:
2288 data = 0x500 | KVM_NR_VAR_MTRR;
2289 break;
2290 case 0x200 ... 0x2ff:
2291 return get_msr_mtrr(vcpu, msr, pdata);
2292 case 0xcd: /* fsb frequency */
2293 data = 3;
2294 break;
2295 /*
2296 * MSR_EBC_FREQUENCY_ID
2297 * Conservative value valid for even the basic CPU models.
2298 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2299 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2300 * and 266MHz for model 3, or 4. Set Core Clock
2301 * Frequency to System Bus Frequency Ratio to 1 (bits
2302 * 31:24) even though these are only valid for CPU
2303 * models > 2, however guests may end up dividing or
2304 * multiplying by zero otherwise.
2305 */
2306 case MSR_EBC_FREQUENCY_ID:
2307 data = 1 << 24;
2308 break;
2309 case MSR_IA32_APICBASE:
2310 data = kvm_get_apic_base(vcpu);
2311 break;
2312 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2313 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2314 break;
2315 case MSR_IA32_TSCDEADLINE:
2316 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2317 break;
2318 case MSR_IA32_TSC_ADJUST:
2319 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2320 break;
2321 case MSR_IA32_MISC_ENABLE:
2322 data = vcpu->arch.ia32_misc_enable_msr;
2323 break;
2324 case MSR_IA32_PERF_STATUS:
2325 /* TSC increment by tick */
2326 data = 1000ULL;
2327 /* CPU multiplier */
2328 data |= (((uint64_t)4ULL) << 40);
2329 break;
2330 case MSR_EFER:
2331 data = vcpu->arch.efer;
2332 break;
2333 case MSR_KVM_WALL_CLOCK:
2334 case MSR_KVM_WALL_CLOCK_NEW:
2335 data = vcpu->kvm->arch.wall_clock;
2336 break;
2337 case MSR_KVM_SYSTEM_TIME:
2338 case MSR_KVM_SYSTEM_TIME_NEW:
2339 data = vcpu->arch.time;
2340 break;
2341 case MSR_KVM_ASYNC_PF_EN:
2342 data = vcpu->arch.apf.msr_val;
2343 break;
2344 case MSR_KVM_STEAL_TIME:
2345 data = vcpu->arch.st.msr_val;
2346 break;
2347 case MSR_KVM_PV_EOI_EN:
2348 data = vcpu->arch.pv_eoi.msr_val;
2349 break;
2350 case MSR_IA32_P5_MC_ADDR:
2351 case MSR_IA32_P5_MC_TYPE:
2352 case MSR_IA32_MCG_CAP:
2353 case MSR_IA32_MCG_CTL:
2354 case MSR_IA32_MCG_STATUS:
2355 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2356 return get_msr_mce(vcpu, msr, pdata);
2357 case MSR_K7_CLK_CTL:
2358 /*
2359 * Provide expected ramp-up count for K7. All other
2360 * are set to zero, indicating minimum divisors for
2361 * every field.
2362 *
2363 * This prevents guest kernels on AMD host with CPU
2364 * type 6, model 8 and higher from exploding due to
2365 * the rdmsr failing.
2366 */
2367 data = 0x20000000;
2368 break;
2369 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2370 if (kvm_hv_msr_partition_wide(msr)) {
2371 int r;
2372 mutex_lock(&vcpu->kvm->lock);
2373 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2374 mutex_unlock(&vcpu->kvm->lock);
2375 return r;
2376 } else
2377 return get_msr_hyperv(vcpu, msr, pdata);
2378 break;
2379 case MSR_IA32_BBL_CR_CTL3:
2380 /* This legacy MSR exists but isn't fully documented in current
2381 * silicon. It is however accessed by winxp in very narrow
2382 * scenarios where it sets bit #19, itself documented as
2383 * a "reserved" bit. Best effort attempt to source coherent
2384 * read data here should the balance of the register be
2385 * interpreted by the guest:
2386 *
2387 * L2 cache control register 3: 64GB range, 256KB size,
2388 * enabled, latency 0x1, configured
2389 */
2390 data = 0xbe702111;
2391 break;
2392 case MSR_AMD64_OSVW_ID_LENGTH:
2393 if (!guest_cpuid_has_osvw(vcpu))
2394 return 1;
2395 data = vcpu->arch.osvw.length;
2396 break;
2397 case MSR_AMD64_OSVW_STATUS:
2398 if (!guest_cpuid_has_osvw(vcpu))
2399 return 1;
2400 data = vcpu->arch.osvw.status;
2401 break;
2402 default:
2403 if (kvm_pmu_msr(vcpu, msr))
2404 return kvm_pmu_get_msr(vcpu, msr, pdata);
2405 if (!ignore_msrs) {
2406 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2407 return 1;
2408 } else {
2409 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2410 data = 0;
2411 }
2412 break;
2413 }
2414 *pdata = data;
2415 return 0;
2416 }
2417 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2418
2419 /*
2420 * Read or write a bunch of msrs. All parameters are kernel addresses.
2421 *
2422 * @return number of msrs set successfully.
2423 */
2424 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2425 struct kvm_msr_entry *entries,
2426 int (*do_msr)(struct kvm_vcpu *vcpu,
2427 unsigned index, u64 *data))
2428 {
2429 int i, idx;
2430
2431 idx = srcu_read_lock(&vcpu->kvm->srcu);
2432 for (i = 0; i < msrs->nmsrs; ++i)
2433 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2434 break;
2435 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2436
2437 return i;
2438 }
2439
2440 /*
2441 * Read or write a bunch of msrs. Parameters are user addresses.
2442 *
2443 * @return number of msrs set successfully.
2444 */
2445 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2446 int (*do_msr)(struct kvm_vcpu *vcpu,
2447 unsigned index, u64 *data),
2448 int writeback)
2449 {
2450 struct kvm_msrs msrs;
2451 struct kvm_msr_entry *entries;
2452 int r, n;
2453 unsigned size;
2454
2455 r = -EFAULT;
2456 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2457 goto out;
2458
2459 r = -E2BIG;
2460 if (msrs.nmsrs >= MAX_IO_MSRS)
2461 goto out;
2462
2463 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2464 entries = memdup_user(user_msrs->entries, size);
2465 if (IS_ERR(entries)) {
2466 r = PTR_ERR(entries);
2467 goto out;
2468 }
2469
2470 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2471 if (r < 0)
2472 goto out_free;
2473
2474 r = -EFAULT;
2475 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2476 goto out_free;
2477
2478 r = n;
2479
2480 out_free:
2481 kfree(entries);
2482 out:
2483 return r;
2484 }
2485
2486 int kvm_dev_ioctl_check_extension(long ext)
2487 {
2488 int r;
2489
2490 switch (ext) {
2491 case KVM_CAP_IRQCHIP:
2492 case KVM_CAP_HLT:
2493 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2494 case KVM_CAP_SET_TSS_ADDR:
2495 case KVM_CAP_EXT_CPUID:
2496 case KVM_CAP_CLOCKSOURCE:
2497 case KVM_CAP_PIT:
2498 case KVM_CAP_NOP_IO_DELAY:
2499 case KVM_CAP_MP_STATE:
2500 case KVM_CAP_SYNC_MMU:
2501 case KVM_CAP_USER_NMI:
2502 case KVM_CAP_REINJECT_CONTROL:
2503 case KVM_CAP_IRQ_INJECT_STATUS:
2504 case KVM_CAP_ASSIGN_DEV_IRQ:
2505 case KVM_CAP_IRQFD:
2506 case KVM_CAP_IOEVENTFD:
2507 case KVM_CAP_PIT2:
2508 case KVM_CAP_PIT_STATE2:
2509 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2510 case KVM_CAP_XEN_HVM:
2511 case KVM_CAP_ADJUST_CLOCK:
2512 case KVM_CAP_VCPU_EVENTS:
2513 case KVM_CAP_HYPERV:
2514 case KVM_CAP_HYPERV_VAPIC:
2515 case KVM_CAP_HYPERV_SPIN:
2516 case KVM_CAP_PCI_SEGMENT:
2517 case KVM_CAP_DEBUGREGS:
2518 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2519 case KVM_CAP_XSAVE:
2520 case KVM_CAP_ASYNC_PF:
2521 case KVM_CAP_GET_TSC_KHZ:
2522 case KVM_CAP_PCI_2_3:
2523 case KVM_CAP_KVMCLOCK_CTRL:
2524 case KVM_CAP_READONLY_MEM:
2525 case KVM_CAP_IRQFD_RESAMPLE:
2526 r = 1;
2527 break;
2528 case KVM_CAP_COALESCED_MMIO:
2529 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2530 break;
2531 case KVM_CAP_VAPIC:
2532 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2533 break;
2534 case KVM_CAP_NR_VCPUS:
2535 r = KVM_SOFT_MAX_VCPUS;
2536 break;
2537 case KVM_CAP_MAX_VCPUS:
2538 r = KVM_MAX_VCPUS;
2539 break;
2540 case KVM_CAP_NR_MEMSLOTS:
2541 r = KVM_USER_MEM_SLOTS;
2542 break;
2543 case KVM_CAP_PV_MMU: /* obsolete */
2544 r = 0;
2545 break;
2546 case KVM_CAP_IOMMU:
2547 r = iommu_present(&pci_bus_type);
2548 break;
2549 case KVM_CAP_MCE:
2550 r = KVM_MAX_MCE_BANKS;
2551 break;
2552 case KVM_CAP_XCRS:
2553 r = cpu_has_xsave;
2554 break;
2555 case KVM_CAP_TSC_CONTROL:
2556 r = kvm_has_tsc_control;
2557 break;
2558 case KVM_CAP_TSC_DEADLINE_TIMER:
2559 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2560 break;
2561 default:
2562 r = 0;
2563 break;
2564 }
2565 return r;
2566
2567 }
2568
2569 long kvm_arch_dev_ioctl(struct file *filp,
2570 unsigned int ioctl, unsigned long arg)
2571 {
2572 void __user *argp = (void __user *)arg;
2573 long r;
2574
2575 switch (ioctl) {
2576 case KVM_GET_MSR_INDEX_LIST: {
2577 struct kvm_msr_list __user *user_msr_list = argp;
2578 struct kvm_msr_list msr_list;
2579 unsigned n;
2580
2581 r = -EFAULT;
2582 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2583 goto out;
2584 n = msr_list.nmsrs;
2585 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2586 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2587 goto out;
2588 r = -E2BIG;
2589 if (n < msr_list.nmsrs)
2590 goto out;
2591 r = -EFAULT;
2592 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2593 num_msrs_to_save * sizeof(u32)))
2594 goto out;
2595 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2596 &emulated_msrs,
2597 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2598 goto out;
2599 r = 0;
2600 break;
2601 }
2602 case KVM_GET_SUPPORTED_CPUID: {
2603 struct kvm_cpuid2 __user *cpuid_arg = argp;
2604 struct kvm_cpuid2 cpuid;
2605
2606 r = -EFAULT;
2607 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2608 goto out;
2609 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2610 cpuid_arg->entries);
2611 if (r)
2612 goto out;
2613
2614 r = -EFAULT;
2615 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2616 goto out;
2617 r = 0;
2618 break;
2619 }
2620 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2621 u64 mce_cap;
2622
2623 mce_cap = KVM_MCE_CAP_SUPPORTED;
2624 r = -EFAULT;
2625 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2626 goto out;
2627 r = 0;
2628 break;
2629 }
2630 default:
2631 r = -EINVAL;
2632 }
2633 out:
2634 return r;
2635 }
2636
2637 static void wbinvd_ipi(void *garbage)
2638 {
2639 wbinvd();
2640 }
2641
2642 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2643 {
2644 return vcpu->kvm->arch.iommu_domain &&
2645 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2646 }
2647
2648 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2649 {
2650 /* Address WBINVD may be executed by guest */
2651 if (need_emulate_wbinvd(vcpu)) {
2652 if (kvm_x86_ops->has_wbinvd_exit())
2653 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2654 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2655 smp_call_function_single(vcpu->cpu,
2656 wbinvd_ipi, NULL, 1);
2657 }
2658
2659 kvm_x86_ops->vcpu_load(vcpu, cpu);
2660
2661 /* Apply any externally detected TSC adjustments (due to suspend) */
2662 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2663 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2664 vcpu->arch.tsc_offset_adjustment = 0;
2665 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2666 }
2667
2668 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2669 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2670 native_read_tsc() - vcpu->arch.last_host_tsc;
2671 if (tsc_delta < 0)
2672 mark_tsc_unstable("KVM discovered backwards TSC");
2673 if (check_tsc_unstable()) {
2674 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2675 vcpu->arch.last_guest_tsc);
2676 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2677 vcpu->arch.tsc_catchup = 1;
2678 }
2679 /*
2680 * On a host with synchronized TSC, there is no need to update
2681 * kvmclock on vcpu->cpu migration
2682 */
2683 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2684 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2685 if (vcpu->cpu != cpu)
2686 kvm_migrate_timers(vcpu);
2687 vcpu->cpu = cpu;
2688 }
2689
2690 accumulate_steal_time(vcpu);
2691 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2692 }
2693
2694 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2695 {
2696 kvm_x86_ops->vcpu_put(vcpu);
2697 kvm_put_guest_fpu(vcpu);
2698 vcpu->arch.last_host_tsc = native_read_tsc();
2699 }
2700
2701 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2702 struct kvm_lapic_state *s)
2703 {
2704 kvm_x86_ops->sync_pir_to_irr(vcpu);
2705 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2706
2707 return 0;
2708 }
2709
2710 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2711 struct kvm_lapic_state *s)
2712 {
2713 kvm_apic_post_state_restore(vcpu, s);
2714 update_cr8_intercept(vcpu);
2715
2716 return 0;
2717 }
2718
2719 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2720 struct kvm_interrupt *irq)
2721 {
2722 if (irq->irq >= KVM_NR_INTERRUPTS)
2723 return -EINVAL;
2724 if (irqchip_in_kernel(vcpu->kvm))
2725 return -ENXIO;
2726
2727 kvm_queue_interrupt(vcpu, irq->irq, false);
2728 kvm_make_request(KVM_REQ_EVENT, vcpu);
2729
2730 return 0;
2731 }
2732
2733 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2734 {
2735 kvm_inject_nmi(vcpu);
2736
2737 return 0;
2738 }
2739
2740 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2741 struct kvm_tpr_access_ctl *tac)
2742 {
2743 if (tac->flags)
2744 return -EINVAL;
2745 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2746 return 0;
2747 }
2748
2749 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2750 u64 mcg_cap)
2751 {
2752 int r;
2753 unsigned bank_num = mcg_cap & 0xff, bank;
2754
2755 r = -EINVAL;
2756 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2757 goto out;
2758 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2759 goto out;
2760 r = 0;
2761 vcpu->arch.mcg_cap = mcg_cap;
2762 /* Init IA32_MCG_CTL to all 1s */
2763 if (mcg_cap & MCG_CTL_P)
2764 vcpu->arch.mcg_ctl = ~(u64)0;
2765 /* Init IA32_MCi_CTL to all 1s */
2766 for (bank = 0; bank < bank_num; bank++)
2767 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2768 out:
2769 return r;
2770 }
2771
2772 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2773 struct kvm_x86_mce *mce)
2774 {
2775 u64 mcg_cap = vcpu->arch.mcg_cap;
2776 unsigned bank_num = mcg_cap & 0xff;
2777 u64 *banks = vcpu->arch.mce_banks;
2778
2779 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2780 return -EINVAL;
2781 /*
2782 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2783 * reporting is disabled
2784 */
2785 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2786 vcpu->arch.mcg_ctl != ~(u64)0)
2787 return 0;
2788 banks += 4 * mce->bank;
2789 /*
2790 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2791 * reporting is disabled for the bank
2792 */
2793 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2794 return 0;
2795 if (mce->status & MCI_STATUS_UC) {
2796 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2797 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2798 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2799 return 0;
2800 }
2801 if (banks[1] & MCI_STATUS_VAL)
2802 mce->status |= MCI_STATUS_OVER;
2803 banks[2] = mce->addr;
2804 banks[3] = mce->misc;
2805 vcpu->arch.mcg_status = mce->mcg_status;
2806 banks[1] = mce->status;
2807 kvm_queue_exception(vcpu, MC_VECTOR);
2808 } else if (!(banks[1] & MCI_STATUS_VAL)
2809 || !(banks[1] & MCI_STATUS_UC)) {
2810 if (banks[1] & MCI_STATUS_VAL)
2811 mce->status |= MCI_STATUS_OVER;
2812 banks[2] = mce->addr;
2813 banks[3] = mce->misc;
2814 banks[1] = mce->status;
2815 } else
2816 banks[1] |= MCI_STATUS_OVER;
2817 return 0;
2818 }
2819
2820 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2821 struct kvm_vcpu_events *events)
2822 {
2823 process_nmi(vcpu);
2824 events->exception.injected =
2825 vcpu->arch.exception.pending &&
2826 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2827 events->exception.nr = vcpu->arch.exception.nr;
2828 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2829 events->exception.pad = 0;
2830 events->exception.error_code = vcpu->arch.exception.error_code;
2831
2832 events->interrupt.injected =
2833 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2834 events->interrupt.nr = vcpu->arch.interrupt.nr;
2835 events->interrupt.soft = 0;
2836 events->interrupt.shadow =
2837 kvm_x86_ops->get_interrupt_shadow(vcpu,
2838 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2839
2840 events->nmi.injected = vcpu->arch.nmi_injected;
2841 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2842 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2843 events->nmi.pad = 0;
2844
2845 events->sipi_vector = 0; /* never valid when reporting to user space */
2846
2847 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2848 | KVM_VCPUEVENT_VALID_SHADOW);
2849 memset(&events->reserved, 0, sizeof(events->reserved));
2850 }
2851
2852 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2853 struct kvm_vcpu_events *events)
2854 {
2855 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2856 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2857 | KVM_VCPUEVENT_VALID_SHADOW))
2858 return -EINVAL;
2859
2860 process_nmi(vcpu);
2861 vcpu->arch.exception.pending = events->exception.injected;
2862 vcpu->arch.exception.nr = events->exception.nr;
2863 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2864 vcpu->arch.exception.error_code = events->exception.error_code;
2865
2866 vcpu->arch.interrupt.pending = events->interrupt.injected;
2867 vcpu->arch.interrupt.nr = events->interrupt.nr;
2868 vcpu->arch.interrupt.soft = events->interrupt.soft;
2869 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2870 kvm_x86_ops->set_interrupt_shadow(vcpu,
2871 events->interrupt.shadow);
2872
2873 vcpu->arch.nmi_injected = events->nmi.injected;
2874 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2875 vcpu->arch.nmi_pending = events->nmi.pending;
2876 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2877
2878 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2879 kvm_vcpu_has_lapic(vcpu))
2880 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2881
2882 kvm_make_request(KVM_REQ_EVENT, vcpu);
2883
2884 return 0;
2885 }
2886
2887 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2888 struct kvm_debugregs *dbgregs)
2889 {
2890 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2891 dbgregs->dr6 = vcpu->arch.dr6;
2892 dbgregs->dr7 = vcpu->arch.dr7;
2893 dbgregs->flags = 0;
2894 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2895 }
2896
2897 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2898 struct kvm_debugregs *dbgregs)
2899 {
2900 if (dbgregs->flags)
2901 return -EINVAL;
2902
2903 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2904 vcpu->arch.dr6 = dbgregs->dr6;
2905 vcpu->arch.dr7 = dbgregs->dr7;
2906
2907 return 0;
2908 }
2909
2910 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2911 struct kvm_xsave *guest_xsave)
2912 {
2913 if (cpu_has_xsave)
2914 memcpy(guest_xsave->region,
2915 &vcpu->arch.guest_fpu.state->xsave,
2916 xstate_size);
2917 else {
2918 memcpy(guest_xsave->region,
2919 &vcpu->arch.guest_fpu.state->fxsave,
2920 sizeof(struct i387_fxsave_struct));
2921 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2922 XSTATE_FPSSE;
2923 }
2924 }
2925
2926 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2927 struct kvm_xsave *guest_xsave)
2928 {
2929 u64 xstate_bv =
2930 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2931
2932 if (cpu_has_xsave)
2933 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2934 guest_xsave->region, xstate_size);
2935 else {
2936 if (xstate_bv & ~XSTATE_FPSSE)
2937 return -EINVAL;
2938 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2939 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2940 }
2941 return 0;
2942 }
2943
2944 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2945 struct kvm_xcrs *guest_xcrs)
2946 {
2947 if (!cpu_has_xsave) {
2948 guest_xcrs->nr_xcrs = 0;
2949 return;
2950 }
2951
2952 guest_xcrs->nr_xcrs = 1;
2953 guest_xcrs->flags = 0;
2954 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2955 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2956 }
2957
2958 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2959 struct kvm_xcrs *guest_xcrs)
2960 {
2961 int i, r = 0;
2962
2963 if (!cpu_has_xsave)
2964 return -EINVAL;
2965
2966 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2967 return -EINVAL;
2968
2969 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2970 /* Only support XCR0 currently */
2971 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2972 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2973 guest_xcrs->xcrs[0].value);
2974 break;
2975 }
2976 if (r)
2977 r = -EINVAL;
2978 return r;
2979 }
2980
2981 /*
2982 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2983 * stopped by the hypervisor. This function will be called from the host only.
2984 * EINVAL is returned when the host attempts to set the flag for a guest that
2985 * does not support pv clocks.
2986 */
2987 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2988 {
2989 if (!vcpu->arch.pv_time_enabled)
2990 return -EINVAL;
2991 vcpu->arch.pvclock_set_guest_stopped_request = true;
2992 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2993 return 0;
2994 }
2995
2996 long kvm_arch_vcpu_ioctl(struct file *filp,
2997 unsigned int ioctl, unsigned long arg)
2998 {
2999 struct kvm_vcpu *vcpu = filp->private_data;
3000 void __user *argp = (void __user *)arg;
3001 int r;
3002 union {
3003 struct kvm_lapic_state *lapic;
3004 struct kvm_xsave *xsave;
3005 struct kvm_xcrs *xcrs;
3006 void *buffer;
3007 } u;
3008
3009 u.buffer = NULL;
3010 switch (ioctl) {
3011 case KVM_GET_LAPIC: {
3012 r = -EINVAL;
3013 if (!vcpu->arch.apic)
3014 goto out;
3015 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3016
3017 r = -ENOMEM;
3018 if (!u.lapic)
3019 goto out;
3020 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3021 if (r)
3022 goto out;
3023 r = -EFAULT;
3024 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3025 goto out;
3026 r = 0;
3027 break;
3028 }
3029 case KVM_SET_LAPIC: {
3030 r = -EINVAL;
3031 if (!vcpu->arch.apic)
3032 goto out;
3033 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3034 if (IS_ERR(u.lapic))
3035 return PTR_ERR(u.lapic);
3036
3037 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3038 break;
3039 }
3040 case KVM_INTERRUPT: {
3041 struct kvm_interrupt irq;
3042
3043 r = -EFAULT;
3044 if (copy_from_user(&irq, argp, sizeof irq))
3045 goto out;
3046 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3047 break;
3048 }
3049 case KVM_NMI: {
3050 r = kvm_vcpu_ioctl_nmi(vcpu);
3051 break;
3052 }
3053 case KVM_SET_CPUID: {
3054 struct kvm_cpuid __user *cpuid_arg = argp;
3055 struct kvm_cpuid cpuid;
3056
3057 r = -EFAULT;
3058 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3059 goto out;
3060 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3061 break;
3062 }
3063 case KVM_SET_CPUID2: {
3064 struct kvm_cpuid2 __user *cpuid_arg = argp;
3065 struct kvm_cpuid2 cpuid;
3066
3067 r = -EFAULT;
3068 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3069 goto out;
3070 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3071 cpuid_arg->entries);
3072 break;
3073 }
3074 case KVM_GET_CPUID2: {
3075 struct kvm_cpuid2 __user *cpuid_arg = argp;
3076 struct kvm_cpuid2 cpuid;
3077
3078 r = -EFAULT;
3079 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3080 goto out;
3081 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3082 cpuid_arg->entries);
3083 if (r)
3084 goto out;
3085 r = -EFAULT;
3086 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3087 goto out;
3088 r = 0;
3089 break;
3090 }
3091 case KVM_GET_MSRS:
3092 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3093 break;
3094 case KVM_SET_MSRS:
3095 r = msr_io(vcpu, argp, do_set_msr, 0);
3096 break;
3097 case KVM_TPR_ACCESS_REPORTING: {
3098 struct kvm_tpr_access_ctl tac;
3099
3100 r = -EFAULT;
3101 if (copy_from_user(&tac, argp, sizeof tac))
3102 goto out;
3103 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3104 if (r)
3105 goto out;
3106 r = -EFAULT;
3107 if (copy_to_user(argp, &tac, sizeof tac))
3108 goto out;
3109 r = 0;
3110 break;
3111 };
3112 case KVM_SET_VAPIC_ADDR: {
3113 struct kvm_vapic_addr va;
3114
3115 r = -EINVAL;
3116 if (!irqchip_in_kernel(vcpu->kvm))
3117 goto out;
3118 r = -EFAULT;
3119 if (copy_from_user(&va, argp, sizeof va))
3120 goto out;
3121 r = 0;
3122 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3123 break;
3124 }
3125 case KVM_X86_SETUP_MCE: {
3126 u64 mcg_cap;
3127
3128 r = -EFAULT;
3129 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3130 goto out;
3131 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3132 break;
3133 }
3134 case KVM_X86_SET_MCE: {
3135 struct kvm_x86_mce mce;
3136
3137 r = -EFAULT;
3138 if (copy_from_user(&mce, argp, sizeof mce))
3139 goto out;
3140 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3141 break;
3142 }
3143 case KVM_GET_VCPU_EVENTS: {
3144 struct kvm_vcpu_events events;
3145
3146 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3147
3148 r = -EFAULT;
3149 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3150 break;
3151 r = 0;
3152 break;
3153 }
3154 case KVM_SET_VCPU_EVENTS: {
3155 struct kvm_vcpu_events events;
3156
3157 r = -EFAULT;
3158 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3159 break;
3160
3161 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3162 break;
3163 }
3164 case KVM_GET_DEBUGREGS: {
3165 struct kvm_debugregs dbgregs;
3166
3167 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3168
3169 r = -EFAULT;
3170 if (copy_to_user(argp, &dbgregs,
3171 sizeof(struct kvm_debugregs)))
3172 break;
3173 r = 0;
3174 break;
3175 }
3176 case KVM_SET_DEBUGREGS: {
3177 struct kvm_debugregs dbgregs;
3178
3179 r = -EFAULT;
3180 if (copy_from_user(&dbgregs, argp,
3181 sizeof(struct kvm_debugregs)))
3182 break;
3183
3184 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3185 break;
3186 }
3187 case KVM_GET_XSAVE: {
3188 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3189 r = -ENOMEM;
3190 if (!u.xsave)
3191 break;
3192
3193 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3194
3195 r = -EFAULT;
3196 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3197 break;
3198 r = 0;
3199 break;
3200 }
3201 case KVM_SET_XSAVE: {
3202 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3203 if (IS_ERR(u.xsave))
3204 return PTR_ERR(u.xsave);
3205
3206 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3207 break;
3208 }
3209 case KVM_GET_XCRS: {
3210 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3211 r = -ENOMEM;
3212 if (!u.xcrs)
3213 break;
3214
3215 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3216
3217 r = -EFAULT;
3218 if (copy_to_user(argp, u.xcrs,
3219 sizeof(struct kvm_xcrs)))
3220 break;
3221 r = 0;
3222 break;
3223 }
3224 case KVM_SET_XCRS: {
3225 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3226 if (IS_ERR(u.xcrs))
3227 return PTR_ERR(u.xcrs);
3228
3229 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3230 break;
3231 }
3232 case KVM_SET_TSC_KHZ: {
3233 u32 user_tsc_khz;
3234
3235 r = -EINVAL;
3236 user_tsc_khz = (u32)arg;
3237
3238 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3239 goto out;
3240
3241 if (user_tsc_khz == 0)
3242 user_tsc_khz = tsc_khz;
3243
3244 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3245
3246 r = 0;
3247 goto out;
3248 }
3249 case KVM_GET_TSC_KHZ: {
3250 r = vcpu->arch.virtual_tsc_khz;
3251 goto out;
3252 }
3253 case KVM_KVMCLOCK_CTRL: {
3254 r = kvm_set_guest_paused(vcpu);
3255 goto out;
3256 }
3257 default:
3258 r = -EINVAL;
3259 }
3260 out:
3261 kfree(u.buffer);
3262 return r;
3263 }
3264
3265 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3266 {
3267 return VM_FAULT_SIGBUS;
3268 }
3269
3270 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3271 {
3272 int ret;
3273
3274 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3275 return -EINVAL;
3276 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3277 return ret;
3278 }
3279
3280 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3281 u64 ident_addr)
3282 {
3283 kvm->arch.ept_identity_map_addr = ident_addr;
3284 return 0;
3285 }
3286
3287 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3288 u32 kvm_nr_mmu_pages)
3289 {
3290 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3291 return -EINVAL;
3292
3293 mutex_lock(&kvm->slots_lock);
3294
3295 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3296 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3297
3298 mutex_unlock(&kvm->slots_lock);
3299 return 0;
3300 }
3301
3302 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3303 {
3304 return kvm->arch.n_max_mmu_pages;
3305 }
3306
3307 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3308 {
3309 int r;
3310
3311 r = 0;
3312 switch (chip->chip_id) {
3313 case KVM_IRQCHIP_PIC_MASTER:
3314 memcpy(&chip->chip.pic,
3315 &pic_irqchip(kvm)->pics[0],
3316 sizeof(struct kvm_pic_state));
3317 break;
3318 case KVM_IRQCHIP_PIC_SLAVE:
3319 memcpy(&chip->chip.pic,
3320 &pic_irqchip(kvm)->pics[1],
3321 sizeof(struct kvm_pic_state));
3322 break;
3323 case KVM_IRQCHIP_IOAPIC:
3324 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3325 break;
3326 default:
3327 r = -EINVAL;
3328 break;
3329 }
3330 return r;
3331 }
3332
3333 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3334 {
3335 int r;
3336
3337 r = 0;
3338 switch (chip->chip_id) {
3339 case KVM_IRQCHIP_PIC_MASTER:
3340 spin_lock(&pic_irqchip(kvm)->lock);
3341 memcpy(&pic_irqchip(kvm)->pics[0],
3342 &chip->chip.pic,
3343 sizeof(struct kvm_pic_state));
3344 spin_unlock(&pic_irqchip(kvm)->lock);
3345 break;
3346 case KVM_IRQCHIP_PIC_SLAVE:
3347 spin_lock(&pic_irqchip(kvm)->lock);
3348 memcpy(&pic_irqchip(kvm)->pics[1],
3349 &chip->chip.pic,
3350 sizeof(struct kvm_pic_state));
3351 spin_unlock(&pic_irqchip(kvm)->lock);
3352 break;
3353 case KVM_IRQCHIP_IOAPIC:
3354 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3355 break;
3356 default:
3357 r = -EINVAL;
3358 break;
3359 }
3360 kvm_pic_update_irq(pic_irqchip(kvm));
3361 return r;
3362 }
3363
3364 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3365 {
3366 int r = 0;
3367
3368 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3369 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3370 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3371 return r;
3372 }
3373
3374 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3375 {
3376 int r = 0;
3377
3378 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3379 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3380 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3381 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3382 return r;
3383 }
3384
3385 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3386 {
3387 int r = 0;
3388
3389 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3390 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3391 sizeof(ps->channels));
3392 ps->flags = kvm->arch.vpit->pit_state.flags;
3393 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3394 memset(&ps->reserved, 0, sizeof(ps->reserved));
3395 return r;
3396 }
3397
3398 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3399 {
3400 int r = 0, start = 0;
3401 u32 prev_legacy, cur_legacy;
3402 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3403 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3404 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3405 if (!prev_legacy && cur_legacy)
3406 start = 1;
3407 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3408 sizeof(kvm->arch.vpit->pit_state.channels));
3409 kvm->arch.vpit->pit_state.flags = ps->flags;
3410 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3411 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3412 return r;
3413 }
3414
3415 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3416 struct kvm_reinject_control *control)
3417 {
3418 if (!kvm->arch.vpit)
3419 return -ENXIO;
3420 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3421 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3422 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3423 return 0;
3424 }
3425
3426 /**
3427 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3428 * @kvm: kvm instance
3429 * @log: slot id and address to which we copy the log
3430 *
3431 * We need to keep it in mind that VCPU threads can write to the bitmap
3432 * concurrently. So, to avoid losing data, we keep the following order for
3433 * each bit:
3434 *
3435 * 1. Take a snapshot of the bit and clear it if needed.
3436 * 2. Write protect the corresponding page.
3437 * 3. Flush TLB's if needed.
3438 * 4. Copy the snapshot to the userspace.
3439 *
3440 * Between 2 and 3, the guest may write to the page using the remaining TLB
3441 * entry. This is not a problem because the page will be reported dirty at
3442 * step 4 using the snapshot taken before and step 3 ensures that successive
3443 * writes will be logged for the next call.
3444 */
3445 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3446 {
3447 int r;
3448 struct kvm_memory_slot *memslot;
3449 unsigned long n, i;
3450 unsigned long *dirty_bitmap;
3451 unsigned long *dirty_bitmap_buffer;
3452 bool is_dirty = false;
3453
3454 mutex_lock(&kvm->slots_lock);
3455
3456 r = -EINVAL;
3457 if (log->slot >= KVM_USER_MEM_SLOTS)
3458 goto out;
3459
3460 memslot = id_to_memslot(kvm->memslots, log->slot);
3461
3462 dirty_bitmap = memslot->dirty_bitmap;
3463 r = -ENOENT;
3464 if (!dirty_bitmap)
3465 goto out;
3466
3467 n = kvm_dirty_bitmap_bytes(memslot);
3468
3469 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3470 memset(dirty_bitmap_buffer, 0, n);
3471
3472 spin_lock(&kvm->mmu_lock);
3473
3474 for (i = 0; i < n / sizeof(long); i++) {
3475 unsigned long mask;
3476 gfn_t offset;
3477
3478 if (!dirty_bitmap[i])
3479 continue;
3480
3481 is_dirty = true;
3482
3483 mask = xchg(&dirty_bitmap[i], 0);
3484 dirty_bitmap_buffer[i] = mask;
3485
3486 offset = i * BITS_PER_LONG;
3487 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3488 }
3489 if (is_dirty)
3490 kvm_flush_remote_tlbs(kvm);
3491
3492 spin_unlock(&kvm->mmu_lock);
3493
3494 r = -EFAULT;
3495 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3496 goto out;
3497
3498 r = 0;
3499 out:
3500 mutex_unlock(&kvm->slots_lock);
3501 return r;
3502 }
3503
3504 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3505 bool line_status)
3506 {
3507 if (!irqchip_in_kernel(kvm))
3508 return -ENXIO;
3509
3510 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3511 irq_event->irq, irq_event->level,
3512 line_status);
3513 return 0;
3514 }
3515
3516 long kvm_arch_vm_ioctl(struct file *filp,
3517 unsigned int ioctl, unsigned long arg)
3518 {
3519 struct kvm *kvm = filp->private_data;
3520 void __user *argp = (void __user *)arg;
3521 int r = -ENOTTY;
3522 /*
3523 * This union makes it completely explicit to gcc-3.x
3524 * that these two variables' stack usage should be
3525 * combined, not added together.
3526 */
3527 union {
3528 struct kvm_pit_state ps;
3529 struct kvm_pit_state2 ps2;
3530 struct kvm_pit_config pit_config;
3531 } u;
3532
3533 switch (ioctl) {
3534 case KVM_SET_TSS_ADDR:
3535 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3536 break;
3537 case KVM_SET_IDENTITY_MAP_ADDR: {
3538 u64 ident_addr;
3539
3540 r = -EFAULT;
3541 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3542 goto out;
3543 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3544 break;
3545 }
3546 case KVM_SET_NR_MMU_PAGES:
3547 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3548 break;
3549 case KVM_GET_NR_MMU_PAGES:
3550 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3551 break;
3552 case KVM_CREATE_IRQCHIP: {
3553 struct kvm_pic *vpic;
3554
3555 mutex_lock(&kvm->lock);
3556 r = -EEXIST;
3557 if (kvm->arch.vpic)
3558 goto create_irqchip_unlock;
3559 r = -EINVAL;
3560 if (atomic_read(&kvm->online_vcpus))
3561 goto create_irqchip_unlock;
3562 r = -ENOMEM;
3563 vpic = kvm_create_pic(kvm);
3564 if (vpic) {
3565 r = kvm_ioapic_init(kvm);
3566 if (r) {
3567 mutex_lock(&kvm->slots_lock);
3568 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3569 &vpic->dev_master);
3570 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3571 &vpic->dev_slave);
3572 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3573 &vpic->dev_eclr);
3574 mutex_unlock(&kvm->slots_lock);
3575 kfree(vpic);
3576 goto create_irqchip_unlock;
3577 }
3578 } else
3579 goto create_irqchip_unlock;
3580 smp_wmb();
3581 kvm->arch.vpic = vpic;
3582 smp_wmb();
3583 r = kvm_setup_default_irq_routing(kvm);
3584 if (r) {
3585 mutex_lock(&kvm->slots_lock);
3586 mutex_lock(&kvm->irq_lock);
3587 kvm_ioapic_destroy(kvm);
3588 kvm_destroy_pic(kvm);
3589 mutex_unlock(&kvm->irq_lock);
3590 mutex_unlock(&kvm->slots_lock);
3591 }
3592 create_irqchip_unlock:
3593 mutex_unlock(&kvm->lock);
3594 break;
3595 }
3596 case KVM_CREATE_PIT:
3597 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3598 goto create_pit;
3599 case KVM_CREATE_PIT2:
3600 r = -EFAULT;
3601 if (copy_from_user(&u.pit_config, argp,
3602 sizeof(struct kvm_pit_config)))
3603 goto out;
3604 create_pit:
3605 mutex_lock(&kvm->slots_lock);
3606 r = -EEXIST;
3607 if (kvm->arch.vpit)
3608 goto create_pit_unlock;
3609 r = -ENOMEM;
3610 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3611 if (kvm->arch.vpit)
3612 r = 0;
3613 create_pit_unlock:
3614 mutex_unlock(&kvm->slots_lock);
3615 break;
3616 case KVM_GET_IRQCHIP: {
3617 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3618 struct kvm_irqchip *chip;
3619
3620 chip = memdup_user(argp, sizeof(*chip));
3621 if (IS_ERR(chip)) {
3622 r = PTR_ERR(chip);
3623 goto out;
3624 }
3625
3626 r = -ENXIO;
3627 if (!irqchip_in_kernel(kvm))
3628 goto get_irqchip_out;
3629 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3630 if (r)
3631 goto get_irqchip_out;
3632 r = -EFAULT;
3633 if (copy_to_user(argp, chip, sizeof *chip))
3634 goto get_irqchip_out;
3635 r = 0;
3636 get_irqchip_out:
3637 kfree(chip);
3638 break;
3639 }
3640 case KVM_SET_IRQCHIP: {
3641 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3642 struct kvm_irqchip *chip;
3643
3644 chip = memdup_user(argp, sizeof(*chip));
3645 if (IS_ERR(chip)) {
3646 r = PTR_ERR(chip);
3647 goto out;
3648 }
3649
3650 r = -ENXIO;
3651 if (!irqchip_in_kernel(kvm))
3652 goto set_irqchip_out;
3653 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3654 if (r)
3655 goto set_irqchip_out;
3656 r = 0;
3657 set_irqchip_out:
3658 kfree(chip);
3659 break;
3660 }
3661 case KVM_GET_PIT: {
3662 r = -EFAULT;
3663 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3664 goto out;
3665 r = -ENXIO;
3666 if (!kvm->arch.vpit)
3667 goto out;
3668 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3669 if (r)
3670 goto out;
3671 r = -EFAULT;
3672 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3673 goto out;
3674 r = 0;
3675 break;
3676 }
3677 case KVM_SET_PIT: {
3678 r = -EFAULT;
3679 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3680 goto out;
3681 r = -ENXIO;
3682 if (!kvm->arch.vpit)
3683 goto out;
3684 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3685 break;
3686 }
3687 case KVM_GET_PIT2: {
3688 r = -ENXIO;
3689 if (!kvm->arch.vpit)
3690 goto out;
3691 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3692 if (r)
3693 goto out;
3694 r = -EFAULT;
3695 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3696 goto out;
3697 r = 0;
3698 break;
3699 }
3700 case KVM_SET_PIT2: {
3701 r = -EFAULT;
3702 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3703 goto out;
3704 r = -ENXIO;
3705 if (!kvm->arch.vpit)
3706 goto out;
3707 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3708 break;
3709 }
3710 case KVM_REINJECT_CONTROL: {
3711 struct kvm_reinject_control control;
3712 r = -EFAULT;
3713 if (copy_from_user(&control, argp, sizeof(control)))
3714 goto out;
3715 r = kvm_vm_ioctl_reinject(kvm, &control);
3716 break;
3717 }
3718 case KVM_XEN_HVM_CONFIG: {
3719 r = -EFAULT;
3720 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3721 sizeof(struct kvm_xen_hvm_config)))
3722 goto out;
3723 r = -EINVAL;
3724 if (kvm->arch.xen_hvm_config.flags)
3725 goto out;
3726 r = 0;
3727 break;
3728 }
3729 case KVM_SET_CLOCK: {
3730 struct kvm_clock_data user_ns;
3731 u64 now_ns;
3732 s64 delta;
3733
3734 r = -EFAULT;
3735 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3736 goto out;
3737
3738 r = -EINVAL;
3739 if (user_ns.flags)
3740 goto out;
3741
3742 r = 0;
3743 local_irq_disable();
3744 now_ns = get_kernel_ns();
3745 delta = user_ns.clock - now_ns;
3746 local_irq_enable();
3747 kvm->arch.kvmclock_offset = delta;
3748 break;
3749 }
3750 case KVM_GET_CLOCK: {
3751 struct kvm_clock_data user_ns;
3752 u64 now_ns;
3753
3754 local_irq_disable();
3755 now_ns = get_kernel_ns();
3756 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3757 local_irq_enable();
3758 user_ns.flags = 0;
3759 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3760
3761 r = -EFAULT;
3762 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3763 goto out;
3764 r = 0;
3765 break;
3766 }
3767
3768 default:
3769 ;
3770 }
3771 out:
3772 return r;
3773 }
3774
3775 static void kvm_init_msr_list(void)
3776 {
3777 u32 dummy[2];
3778 unsigned i, j;
3779
3780 /* skip the first msrs in the list. KVM-specific */
3781 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3782 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3783 continue;
3784 if (j < i)
3785 msrs_to_save[j] = msrs_to_save[i];
3786 j++;
3787 }
3788 num_msrs_to_save = j;
3789 }
3790
3791 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3792 const void *v)
3793 {
3794 int handled = 0;
3795 int n;
3796
3797 do {
3798 n = min(len, 8);
3799 if (!(vcpu->arch.apic &&
3800 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3801 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3802 break;
3803 handled += n;
3804 addr += n;
3805 len -= n;
3806 v += n;
3807 } while (len);
3808
3809 return handled;
3810 }
3811
3812 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3813 {
3814 int handled = 0;
3815 int n;
3816
3817 do {
3818 n = min(len, 8);
3819 if (!(vcpu->arch.apic &&
3820 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3821 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3822 break;
3823 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3824 handled += n;
3825 addr += n;
3826 len -= n;
3827 v += n;
3828 } while (len);
3829
3830 return handled;
3831 }
3832
3833 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3834 struct kvm_segment *var, int seg)
3835 {
3836 kvm_x86_ops->set_segment(vcpu, var, seg);
3837 }
3838
3839 void kvm_get_segment(struct kvm_vcpu *vcpu,
3840 struct kvm_segment *var, int seg)
3841 {
3842 kvm_x86_ops->get_segment(vcpu, var, seg);
3843 }
3844
3845 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3846 {
3847 gpa_t t_gpa;
3848 struct x86_exception exception;
3849
3850 BUG_ON(!mmu_is_nested(vcpu));
3851
3852 /* NPT walks are always user-walks */
3853 access |= PFERR_USER_MASK;
3854 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3855
3856 return t_gpa;
3857 }
3858
3859 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3860 struct x86_exception *exception)
3861 {
3862 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3863 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3864 }
3865
3866 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3867 struct x86_exception *exception)
3868 {
3869 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3870 access |= PFERR_FETCH_MASK;
3871 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3872 }
3873
3874 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3875 struct x86_exception *exception)
3876 {
3877 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3878 access |= PFERR_WRITE_MASK;
3879 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3880 }
3881
3882 /* uses this to access any guest's mapped memory without checking CPL */
3883 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3884 struct x86_exception *exception)
3885 {
3886 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3887 }
3888
3889 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3890 struct kvm_vcpu *vcpu, u32 access,
3891 struct x86_exception *exception)
3892 {
3893 void *data = val;
3894 int r = X86EMUL_CONTINUE;
3895
3896 while (bytes) {
3897 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3898 exception);
3899 unsigned offset = addr & (PAGE_SIZE-1);
3900 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3901 int ret;
3902
3903 if (gpa == UNMAPPED_GVA)
3904 return X86EMUL_PROPAGATE_FAULT;
3905 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3906 if (ret < 0) {
3907 r = X86EMUL_IO_NEEDED;
3908 goto out;
3909 }
3910
3911 bytes -= toread;
3912 data += toread;
3913 addr += toread;
3914 }
3915 out:
3916 return r;
3917 }
3918
3919 /* used for instruction fetching */
3920 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3921 gva_t addr, void *val, unsigned int bytes,
3922 struct x86_exception *exception)
3923 {
3924 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3925 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3926
3927 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3928 access | PFERR_FETCH_MASK,
3929 exception);
3930 }
3931
3932 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3933 gva_t addr, void *val, unsigned int bytes,
3934 struct x86_exception *exception)
3935 {
3936 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3937 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3938
3939 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3940 exception);
3941 }
3942 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3943
3944 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3945 gva_t addr, void *val, unsigned int bytes,
3946 struct x86_exception *exception)
3947 {
3948 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3949 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3950 }
3951
3952 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3953 gva_t addr, void *val,
3954 unsigned int bytes,
3955 struct x86_exception *exception)
3956 {
3957 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3958 void *data = val;
3959 int r = X86EMUL_CONTINUE;
3960
3961 while (bytes) {
3962 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3963 PFERR_WRITE_MASK,
3964 exception);
3965 unsigned offset = addr & (PAGE_SIZE-1);
3966 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3967 int ret;
3968
3969 if (gpa == UNMAPPED_GVA)
3970 return X86EMUL_PROPAGATE_FAULT;
3971 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3972 if (ret < 0) {
3973 r = X86EMUL_IO_NEEDED;
3974 goto out;
3975 }
3976
3977 bytes -= towrite;
3978 data += towrite;
3979 addr += towrite;
3980 }
3981 out:
3982 return r;
3983 }
3984 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3985
3986 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3987 gpa_t *gpa, struct x86_exception *exception,
3988 bool write)
3989 {
3990 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3991 | (write ? PFERR_WRITE_MASK : 0);
3992
3993 if (vcpu_match_mmio_gva(vcpu, gva)
3994 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
3995 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3996 (gva & (PAGE_SIZE - 1));
3997 trace_vcpu_match_mmio(gva, *gpa, write, false);
3998 return 1;
3999 }
4000
4001 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4002
4003 if (*gpa == UNMAPPED_GVA)
4004 return -1;
4005
4006 /* For APIC access vmexit */
4007 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4008 return 1;
4009
4010 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4011 trace_vcpu_match_mmio(gva, *gpa, write, true);
4012 return 1;
4013 }
4014
4015 return 0;
4016 }
4017
4018 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4019 const void *val, int bytes)
4020 {
4021 int ret;
4022
4023 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4024 if (ret < 0)
4025 return 0;
4026 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4027 return 1;
4028 }
4029
4030 struct read_write_emulator_ops {
4031 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4032 int bytes);
4033 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4034 void *val, int bytes);
4035 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4036 int bytes, void *val);
4037 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4038 void *val, int bytes);
4039 bool write;
4040 };
4041
4042 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4043 {
4044 if (vcpu->mmio_read_completed) {
4045 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4046 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4047 vcpu->mmio_read_completed = 0;
4048 return 1;
4049 }
4050
4051 return 0;
4052 }
4053
4054 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4055 void *val, int bytes)
4056 {
4057 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4058 }
4059
4060 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4061 void *val, int bytes)
4062 {
4063 return emulator_write_phys(vcpu, gpa, val, bytes);
4064 }
4065
4066 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4067 {
4068 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4069 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4070 }
4071
4072 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4073 void *val, int bytes)
4074 {
4075 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4076 return X86EMUL_IO_NEEDED;
4077 }
4078
4079 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4080 void *val, int bytes)
4081 {
4082 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4083
4084 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4085 return X86EMUL_CONTINUE;
4086 }
4087
4088 static const struct read_write_emulator_ops read_emultor = {
4089 .read_write_prepare = read_prepare,
4090 .read_write_emulate = read_emulate,
4091 .read_write_mmio = vcpu_mmio_read,
4092 .read_write_exit_mmio = read_exit_mmio,
4093 };
4094
4095 static const struct read_write_emulator_ops write_emultor = {
4096 .read_write_emulate = write_emulate,
4097 .read_write_mmio = write_mmio,
4098 .read_write_exit_mmio = write_exit_mmio,
4099 .write = true,
4100 };
4101
4102 static int emulator_read_write_onepage(unsigned long addr, void *val,
4103 unsigned int bytes,
4104 struct x86_exception *exception,
4105 struct kvm_vcpu *vcpu,
4106 const struct read_write_emulator_ops *ops)
4107 {
4108 gpa_t gpa;
4109 int handled, ret;
4110 bool write = ops->write;
4111 struct kvm_mmio_fragment *frag;
4112
4113 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4114
4115 if (ret < 0)
4116 return X86EMUL_PROPAGATE_FAULT;
4117
4118 /* For APIC access vmexit */
4119 if (ret)
4120 goto mmio;
4121
4122 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4123 return X86EMUL_CONTINUE;
4124
4125 mmio:
4126 /*
4127 * Is this MMIO handled locally?
4128 */
4129 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4130 if (handled == bytes)
4131 return X86EMUL_CONTINUE;
4132
4133 gpa += handled;
4134 bytes -= handled;
4135 val += handled;
4136
4137 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4138 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4139 frag->gpa = gpa;
4140 frag->data = val;
4141 frag->len = bytes;
4142 return X86EMUL_CONTINUE;
4143 }
4144
4145 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4146 void *val, unsigned int bytes,
4147 struct x86_exception *exception,
4148 const struct read_write_emulator_ops *ops)
4149 {
4150 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4151 gpa_t gpa;
4152 int rc;
4153
4154 if (ops->read_write_prepare &&
4155 ops->read_write_prepare(vcpu, val, bytes))
4156 return X86EMUL_CONTINUE;
4157
4158 vcpu->mmio_nr_fragments = 0;
4159
4160 /* Crossing a page boundary? */
4161 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4162 int now;
4163
4164 now = -addr & ~PAGE_MASK;
4165 rc = emulator_read_write_onepage(addr, val, now, exception,
4166 vcpu, ops);
4167
4168 if (rc != X86EMUL_CONTINUE)
4169 return rc;
4170 addr += now;
4171 val += now;
4172 bytes -= now;
4173 }
4174
4175 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4176 vcpu, ops);
4177 if (rc != X86EMUL_CONTINUE)
4178 return rc;
4179
4180 if (!vcpu->mmio_nr_fragments)
4181 return rc;
4182
4183 gpa = vcpu->mmio_fragments[0].gpa;
4184
4185 vcpu->mmio_needed = 1;
4186 vcpu->mmio_cur_fragment = 0;
4187
4188 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4189 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4190 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4191 vcpu->run->mmio.phys_addr = gpa;
4192
4193 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4194 }
4195
4196 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4197 unsigned long addr,
4198 void *val,
4199 unsigned int bytes,
4200 struct x86_exception *exception)
4201 {
4202 return emulator_read_write(ctxt, addr, val, bytes,
4203 exception, &read_emultor);
4204 }
4205
4206 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4207 unsigned long addr,
4208 const void *val,
4209 unsigned int bytes,
4210 struct x86_exception *exception)
4211 {
4212 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4213 exception, &write_emultor);
4214 }
4215
4216 #define CMPXCHG_TYPE(t, ptr, old, new) \
4217 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4218
4219 #ifdef CONFIG_X86_64
4220 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4221 #else
4222 # define CMPXCHG64(ptr, old, new) \
4223 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4224 #endif
4225
4226 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4227 unsigned long addr,
4228 const void *old,
4229 const void *new,
4230 unsigned int bytes,
4231 struct x86_exception *exception)
4232 {
4233 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4234 gpa_t gpa;
4235 struct page *page;
4236 char *kaddr;
4237 bool exchanged;
4238
4239 /* guests cmpxchg8b have to be emulated atomically */
4240 if (bytes > 8 || (bytes & (bytes - 1)))
4241 goto emul_write;
4242
4243 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4244
4245 if (gpa == UNMAPPED_GVA ||
4246 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4247 goto emul_write;
4248
4249 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4250 goto emul_write;
4251
4252 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4253 if (is_error_page(page))
4254 goto emul_write;
4255
4256 kaddr = kmap_atomic(page);
4257 kaddr += offset_in_page(gpa);
4258 switch (bytes) {
4259 case 1:
4260 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4261 break;
4262 case 2:
4263 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4264 break;
4265 case 4:
4266 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4267 break;
4268 case 8:
4269 exchanged = CMPXCHG64(kaddr, old, new);
4270 break;
4271 default:
4272 BUG();
4273 }
4274 kunmap_atomic(kaddr);
4275 kvm_release_page_dirty(page);
4276
4277 if (!exchanged)
4278 return X86EMUL_CMPXCHG_FAILED;
4279
4280 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4281
4282 return X86EMUL_CONTINUE;
4283
4284 emul_write:
4285 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4286
4287 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4288 }
4289
4290 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4291 {
4292 /* TODO: String I/O for in kernel device */
4293 int r;
4294
4295 if (vcpu->arch.pio.in)
4296 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4297 vcpu->arch.pio.size, pd);
4298 else
4299 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4300 vcpu->arch.pio.port, vcpu->arch.pio.size,
4301 pd);
4302 return r;
4303 }
4304
4305 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4306 unsigned short port, void *val,
4307 unsigned int count, bool in)
4308 {
4309 trace_kvm_pio(!in, port, size, count);
4310
4311 vcpu->arch.pio.port = port;
4312 vcpu->arch.pio.in = in;
4313 vcpu->arch.pio.count = count;
4314 vcpu->arch.pio.size = size;
4315
4316 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4317 vcpu->arch.pio.count = 0;
4318 return 1;
4319 }
4320
4321 vcpu->run->exit_reason = KVM_EXIT_IO;
4322 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4323 vcpu->run->io.size = size;
4324 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4325 vcpu->run->io.count = count;
4326 vcpu->run->io.port = port;
4327
4328 return 0;
4329 }
4330
4331 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4332 int size, unsigned short port, void *val,
4333 unsigned int count)
4334 {
4335 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4336 int ret;
4337
4338 if (vcpu->arch.pio.count)
4339 goto data_avail;
4340
4341 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4342 if (ret) {
4343 data_avail:
4344 memcpy(val, vcpu->arch.pio_data, size * count);
4345 vcpu->arch.pio.count = 0;
4346 return 1;
4347 }
4348
4349 return 0;
4350 }
4351
4352 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4353 int size, unsigned short port,
4354 const void *val, unsigned int count)
4355 {
4356 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4357
4358 memcpy(vcpu->arch.pio_data, val, size * count);
4359 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4360 }
4361
4362 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4363 {
4364 return kvm_x86_ops->get_segment_base(vcpu, seg);
4365 }
4366
4367 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4368 {
4369 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4370 }
4371
4372 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4373 {
4374 if (!need_emulate_wbinvd(vcpu))
4375 return X86EMUL_CONTINUE;
4376
4377 if (kvm_x86_ops->has_wbinvd_exit()) {
4378 int cpu = get_cpu();
4379
4380 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4381 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4382 wbinvd_ipi, NULL, 1);
4383 put_cpu();
4384 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4385 } else
4386 wbinvd();
4387 return X86EMUL_CONTINUE;
4388 }
4389 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4390
4391 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4392 {
4393 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4394 }
4395
4396 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4397 {
4398 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4399 }
4400
4401 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4402 {
4403
4404 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4405 }
4406
4407 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4408 {
4409 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4410 }
4411
4412 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4413 {
4414 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4415 unsigned long value;
4416
4417 switch (cr) {
4418 case 0:
4419 value = kvm_read_cr0(vcpu);
4420 break;
4421 case 2:
4422 value = vcpu->arch.cr2;
4423 break;
4424 case 3:
4425 value = kvm_read_cr3(vcpu);
4426 break;
4427 case 4:
4428 value = kvm_read_cr4(vcpu);
4429 break;
4430 case 8:
4431 value = kvm_get_cr8(vcpu);
4432 break;
4433 default:
4434 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4435 return 0;
4436 }
4437
4438 return value;
4439 }
4440
4441 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4442 {
4443 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4444 int res = 0;
4445
4446 switch (cr) {
4447 case 0:
4448 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4449 break;
4450 case 2:
4451 vcpu->arch.cr2 = val;
4452 break;
4453 case 3:
4454 res = kvm_set_cr3(vcpu, val);
4455 break;
4456 case 4:
4457 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4458 break;
4459 case 8:
4460 res = kvm_set_cr8(vcpu, val);
4461 break;
4462 default:
4463 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4464 res = -1;
4465 }
4466
4467 return res;
4468 }
4469
4470 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4471 {
4472 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4473 }
4474
4475 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4476 {
4477 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4478 }
4479
4480 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4481 {
4482 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4483 }
4484
4485 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4486 {
4487 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4488 }
4489
4490 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4491 {
4492 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4493 }
4494
4495 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4496 {
4497 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4498 }
4499
4500 static unsigned long emulator_get_cached_segment_base(
4501 struct x86_emulate_ctxt *ctxt, int seg)
4502 {
4503 return get_segment_base(emul_to_vcpu(ctxt), seg);
4504 }
4505
4506 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4507 struct desc_struct *desc, u32 *base3,
4508 int seg)
4509 {
4510 struct kvm_segment var;
4511
4512 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4513 *selector = var.selector;
4514
4515 if (var.unusable) {
4516 memset(desc, 0, sizeof(*desc));
4517 return false;
4518 }
4519
4520 if (var.g)
4521 var.limit >>= 12;
4522 set_desc_limit(desc, var.limit);
4523 set_desc_base(desc, (unsigned long)var.base);
4524 #ifdef CONFIG_X86_64
4525 if (base3)
4526 *base3 = var.base >> 32;
4527 #endif
4528 desc->type = var.type;
4529 desc->s = var.s;
4530 desc->dpl = var.dpl;
4531 desc->p = var.present;
4532 desc->avl = var.avl;
4533 desc->l = var.l;
4534 desc->d = var.db;
4535 desc->g = var.g;
4536
4537 return true;
4538 }
4539
4540 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4541 struct desc_struct *desc, u32 base3,
4542 int seg)
4543 {
4544 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4545 struct kvm_segment var;
4546
4547 var.selector = selector;
4548 var.base = get_desc_base(desc);
4549 #ifdef CONFIG_X86_64
4550 var.base |= ((u64)base3) << 32;
4551 #endif
4552 var.limit = get_desc_limit(desc);
4553 if (desc->g)
4554 var.limit = (var.limit << 12) | 0xfff;
4555 var.type = desc->type;
4556 var.present = desc->p;
4557 var.dpl = desc->dpl;
4558 var.db = desc->d;
4559 var.s = desc->s;
4560 var.l = desc->l;
4561 var.g = desc->g;
4562 var.avl = desc->avl;
4563 var.present = desc->p;
4564 var.unusable = !var.present;
4565 var.padding = 0;
4566
4567 kvm_set_segment(vcpu, &var, seg);
4568 return;
4569 }
4570
4571 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4572 u32 msr_index, u64 *pdata)
4573 {
4574 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4575 }
4576
4577 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4578 u32 msr_index, u64 data)
4579 {
4580 struct msr_data msr;
4581
4582 msr.data = data;
4583 msr.index = msr_index;
4584 msr.host_initiated = false;
4585 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4586 }
4587
4588 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4589 u32 pmc, u64 *pdata)
4590 {
4591 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4592 }
4593
4594 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4595 {
4596 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4597 }
4598
4599 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4600 {
4601 preempt_disable();
4602 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4603 /*
4604 * CR0.TS may reference the host fpu state, not the guest fpu state,
4605 * so it may be clear at this point.
4606 */
4607 clts();
4608 }
4609
4610 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4611 {
4612 preempt_enable();
4613 }
4614
4615 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4616 struct x86_instruction_info *info,
4617 enum x86_intercept_stage stage)
4618 {
4619 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4620 }
4621
4622 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4623 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4624 {
4625 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4626 }
4627
4628 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4629 {
4630 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4631 }
4632
4633 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4634 {
4635 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4636 }
4637
4638 static const struct x86_emulate_ops emulate_ops = {
4639 .read_gpr = emulator_read_gpr,
4640 .write_gpr = emulator_write_gpr,
4641 .read_std = kvm_read_guest_virt_system,
4642 .write_std = kvm_write_guest_virt_system,
4643 .fetch = kvm_fetch_guest_virt,
4644 .read_emulated = emulator_read_emulated,
4645 .write_emulated = emulator_write_emulated,
4646 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4647 .invlpg = emulator_invlpg,
4648 .pio_in_emulated = emulator_pio_in_emulated,
4649 .pio_out_emulated = emulator_pio_out_emulated,
4650 .get_segment = emulator_get_segment,
4651 .set_segment = emulator_set_segment,
4652 .get_cached_segment_base = emulator_get_cached_segment_base,
4653 .get_gdt = emulator_get_gdt,
4654 .get_idt = emulator_get_idt,
4655 .set_gdt = emulator_set_gdt,
4656 .set_idt = emulator_set_idt,
4657 .get_cr = emulator_get_cr,
4658 .set_cr = emulator_set_cr,
4659 .set_rflags = emulator_set_rflags,
4660 .cpl = emulator_get_cpl,
4661 .get_dr = emulator_get_dr,
4662 .set_dr = emulator_set_dr,
4663 .set_msr = emulator_set_msr,
4664 .get_msr = emulator_get_msr,
4665 .read_pmc = emulator_read_pmc,
4666 .halt = emulator_halt,
4667 .wbinvd = emulator_wbinvd,
4668 .fix_hypercall = emulator_fix_hypercall,
4669 .get_fpu = emulator_get_fpu,
4670 .put_fpu = emulator_put_fpu,
4671 .intercept = emulator_intercept,
4672 .get_cpuid = emulator_get_cpuid,
4673 };
4674
4675 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4676 {
4677 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4678 /*
4679 * an sti; sti; sequence only disable interrupts for the first
4680 * instruction. So, if the last instruction, be it emulated or
4681 * not, left the system with the INT_STI flag enabled, it
4682 * means that the last instruction is an sti. We should not
4683 * leave the flag on in this case. The same goes for mov ss
4684 */
4685 if (!(int_shadow & mask))
4686 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4687 }
4688
4689 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4690 {
4691 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4692 if (ctxt->exception.vector == PF_VECTOR)
4693 kvm_propagate_fault(vcpu, &ctxt->exception);
4694 else if (ctxt->exception.error_code_valid)
4695 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4696 ctxt->exception.error_code);
4697 else
4698 kvm_queue_exception(vcpu, ctxt->exception.vector);
4699 }
4700
4701 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4702 {
4703 memset(&ctxt->twobyte, 0,
4704 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4705
4706 ctxt->fetch.start = 0;
4707 ctxt->fetch.end = 0;
4708 ctxt->io_read.pos = 0;
4709 ctxt->io_read.end = 0;
4710 ctxt->mem_read.pos = 0;
4711 ctxt->mem_read.end = 0;
4712 }
4713
4714 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4715 {
4716 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4717 int cs_db, cs_l;
4718
4719 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4720
4721 ctxt->eflags = kvm_get_rflags(vcpu);
4722 ctxt->eip = kvm_rip_read(vcpu);
4723 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4724 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4725 cs_l ? X86EMUL_MODE_PROT64 :
4726 cs_db ? X86EMUL_MODE_PROT32 :
4727 X86EMUL_MODE_PROT16;
4728 ctxt->guest_mode = is_guest_mode(vcpu);
4729
4730 init_decode_cache(ctxt);
4731 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4732 }
4733
4734 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4735 {
4736 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4737 int ret;
4738
4739 init_emulate_ctxt(vcpu);
4740
4741 ctxt->op_bytes = 2;
4742 ctxt->ad_bytes = 2;
4743 ctxt->_eip = ctxt->eip + inc_eip;
4744 ret = emulate_int_real(ctxt, irq);
4745
4746 if (ret != X86EMUL_CONTINUE)
4747 return EMULATE_FAIL;
4748
4749 ctxt->eip = ctxt->_eip;
4750 kvm_rip_write(vcpu, ctxt->eip);
4751 kvm_set_rflags(vcpu, ctxt->eflags);
4752
4753 if (irq == NMI_VECTOR)
4754 vcpu->arch.nmi_pending = 0;
4755 else
4756 vcpu->arch.interrupt.pending = false;
4757
4758 return EMULATE_DONE;
4759 }
4760 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4761
4762 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4763 {
4764 int r = EMULATE_DONE;
4765
4766 ++vcpu->stat.insn_emulation_fail;
4767 trace_kvm_emulate_insn_failed(vcpu);
4768 if (!is_guest_mode(vcpu)) {
4769 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4770 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4771 vcpu->run->internal.ndata = 0;
4772 r = EMULATE_FAIL;
4773 }
4774 kvm_queue_exception(vcpu, UD_VECTOR);
4775
4776 return r;
4777 }
4778
4779 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4780 bool write_fault_to_shadow_pgtable,
4781 int emulation_type)
4782 {
4783 gpa_t gpa = cr2;
4784 pfn_t pfn;
4785
4786 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4787 return false;
4788
4789 if (!vcpu->arch.mmu.direct_map) {
4790 /*
4791 * Write permission should be allowed since only
4792 * write access need to be emulated.
4793 */
4794 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4795
4796 /*
4797 * If the mapping is invalid in guest, let cpu retry
4798 * it to generate fault.
4799 */
4800 if (gpa == UNMAPPED_GVA)
4801 return true;
4802 }
4803
4804 /*
4805 * Do not retry the unhandleable instruction if it faults on the
4806 * readonly host memory, otherwise it will goto a infinite loop:
4807 * retry instruction -> write #PF -> emulation fail -> retry
4808 * instruction -> ...
4809 */
4810 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4811
4812 /*
4813 * If the instruction failed on the error pfn, it can not be fixed,
4814 * report the error to userspace.
4815 */
4816 if (is_error_noslot_pfn(pfn))
4817 return false;
4818
4819 kvm_release_pfn_clean(pfn);
4820
4821 /* The instructions are well-emulated on direct mmu. */
4822 if (vcpu->arch.mmu.direct_map) {
4823 unsigned int indirect_shadow_pages;
4824
4825 spin_lock(&vcpu->kvm->mmu_lock);
4826 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4827 spin_unlock(&vcpu->kvm->mmu_lock);
4828
4829 if (indirect_shadow_pages)
4830 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4831
4832 return true;
4833 }
4834
4835 /*
4836 * if emulation was due to access to shadowed page table
4837 * and it failed try to unshadow page and re-enter the
4838 * guest to let CPU execute the instruction.
4839 */
4840 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4841
4842 /*
4843 * If the access faults on its page table, it can not
4844 * be fixed by unprotecting shadow page and it should
4845 * be reported to userspace.
4846 */
4847 return !write_fault_to_shadow_pgtable;
4848 }
4849
4850 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4851 unsigned long cr2, int emulation_type)
4852 {
4853 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4854 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4855
4856 last_retry_eip = vcpu->arch.last_retry_eip;
4857 last_retry_addr = vcpu->arch.last_retry_addr;
4858
4859 /*
4860 * If the emulation is caused by #PF and it is non-page_table
4861 * writing instruction, it means the VM-EXIT is caused by shadow
4862 * page protected, we can zap the shadow page and retry this
4863 * instruction directly.
4864 *
4865 * Note: if the guest uses a non-page-table modifying instruction
4866 * on the PDE that points to the instruction, then we will unmap
4867 * the instruction and go to an infinite loop. So, we cache the
4868 * last retried eip and the last fault address, if we meet the eip
4869 * and the address again, we can break out of the potential infinite
4870 * loop.
4871 */
4872 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4873
4874 if (!(emulation_type & EMULTYPE_RETRY))
4875 return false;
4876
4877 if (x86_page_table_writing_insn(ctxt))
4878 return false;
4879
4880 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4881 return false;
4882
4883 vcpu->arch.last_retry_eip = ctxt->eip;
4884 vcpu->arch.last_retry_addr = cr2;
4885
4886 if (!vcpu->arch.mmu.direct_map)
4887 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4888
4889 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4890
4891 return true;
4892 }
4893
4894 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4895 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4896
4897 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4898 unsigned long cr2,
4899 int emulation_type,
4900 void *insn,
4901 int insn_len)
4902 {
4903 int r;
4904 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4905 bool writeback = true;
4906 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
4907
4908 /*
4909 * Clear write_fault_to_shadow_pgtable here to ensure it is
4910 * never reused.
4911 */
4912 vcpu->arch.write_fault_to_shadow_pgtable = false;
4913 kvm_clear_exception_queue(vcpu);
4914
4915 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4916 init_emulate_ctxt(vcpu);
4917 ctxt->interruptibility = 0;
4918 ctxt->have_exception = false;
4919 ctxt->perm_ok = false;
4920
4921 ctxt->only_vendor_specific_insn
4922 = emulation_type & EMULTYPE_TRAP_UD;
4923
4924 r = x86_decode_insn(ctxt, insn, insn_len);
4925
4926 trace_kvm_emulate_insn_start(vcpu);
4927 ++vcpu->stat.insn_emulation;
4928 if (r != EMULATION_OK) {
4929 if (emulation_type & EMULTYPE_TRAP_UD)
4930 return EMULATE_FAIL;
4931 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4932 emulation_type))
4933 return EMULATE_DONE;
4934 if (emulation_type & EMULTYPE_SKIP)
4935 return EMULATE_FAIL;
4936 return handle_emulation_failure(vcpu);
4937 }
4938 }
4939
4940 if (emulation_type & EMULTYPE_SKIP) {
4941 kvm_rip_write(vcpu, ctxt->_eip);
4942 return EMULATE_DONE;
4943 }
4944
4945 if (retry_instruction(ctxt, cr2, emulation_type))
4946 return EMULATE_DONE;
4947
4948 /* this is needed for vmware backdoor interface to work since it
4949 changes registers values during IO operation */
4950 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4951 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4952 emulator_invalidate_register_cache(ctxt);
4953 }
4954
4955 restart:
4956 r = x86_emulate_insn(ctxt);
4957
4958 if (r == EMULATION_INTERCEPTED)
4959 return EMULATE_DONE;
4960
4961 if (r == EMULATION_FAILED) {
4962 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4963 emulation_type))
4964 return EMULATE_DONE;
4965
4966 return handle_emulation_failure(vcpu);
4967 }
4968
4969 if (ctxt->have_exception) {
4970 inject_emulated_exception(vcpu);
4971 r = EMULATE_DONE;
4972 } else if (vcpu->arch.pio.count) {
4973 if (!vcpu->arch.pio.in)
4974 vcpu->arch.pio.count = 0;
4975 else {
4976 writeback = false;
4977 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4978 }
4979 r = EMULATE_DO_MMIO;
4980 } else if (vcpu->mmio_needed) {
4981 if (!vcpu->mmio_is_write)
4982 writeback = false;
4983 r = EMULATE_DO_MMIO;
4984 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
4985 } else if (r == EMULATION_RESTART)
4986 goto restart;
4987 else
4988 r = EMULATE_DONE;
4989
4990 if (writeback) {
4991 toggle_interruptibility(vcpu, ctxt->interruptibility);
4992 kvm_set_rflags(vcpu, ctxt->eflags);
4993 kvm_make_request(KVM_REQ_EVENT, vcpu);
4994 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4995 kvm_rip_write(vcpu, ctxt->eip);
4996 } else
4997 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4998
4999 return r;
5000 }
5001 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5002
5003 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5004 {
5005 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5006 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5007 size, port, &val, 1);
5008 /* do not return to emulator after return from userspace */
5009 vcpu->arch.pio.count = 0;
5010 return ret;
5011 }
5012 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5013
5014 static void tsc_bad(void *info)
5015 {
5016 __this_cpu_write(cpu_tsc_khz, 0);
5017 }
5018
5019 static void tsc_khz_changed(void *data)
5020 {
5021 struct cpufreq_freqs *freq = data;
5022 unsigned long khz = 0;
5023
5024 if (data)
5025 khz = freq->new;
5026 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5027 khz = cpufreq_quick_get(raw_smp_processor_id());
5028 if (!khz)
5029 khz = tsc_khz;
5030 __this_cpu_write(cpu_tsc_khz, khz);
5031 }
5032
5033 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5034 void *data)
5035 {
5036 struct cpufreq_freqs *freq = data;
5037 struct kvm *kvm;
5038 struct kvm_vcpu *vcpu;
5039 int i, send_ipi = 0;
5040
5041 /*
5042 * We allow guests to temporarily run on slowing clocks,
5043 * provided we notify them after, or to run on accelerating
5044 * clocks, provided we notify them before. Thus time never
5045 * goes backwards.
5046 *
5047 * However, we have a problem. We can't atomically update
5048 * the frequency of a given CPU from this function; it is
5049 * merely a notifier, which can be called from any CPU.
5050 * Changing the TSC frequency at arbitrary points in time
5051 * requires a recomputation of local variables related to
5052 * the TSC for each VCPU. We must flag these local variables
5053 * to be updated and be sure the update takes place with the
5054 * new frequency before any guests proceed.
5055 *
5056 * Unfortunately, the combination of hotplug CPU and frequency
5057 * change creates an intractable locking scenario; the order
5058 * of when these callouts happen is undefined with respect to
5059 * CPU hotplug, and they can race with each other. As such,
5060 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5061 * undefined; you can actually have a CPU frequency change take
5062 * place in between the computation of X and the setting of the
5063 * variable. To protect against this problem, all updates of
5064 * the per_cpu tsc_khz variable are done in an interrupt
5065 * protected IPI, and all callers wishing to update the value
5066 * must wait for a synchronous IPI to complete (which is trivial
5067 * if the caller is on the CPU already). This establishes the
5068 * necessary total order on variable updates.
5069 *
5070 * Note that because a guest time update may take place
5071 * anytime after the setting of the VCPU's request bit, the
5072 * correct TSC value must be set before the request. However,
5073 * to ensure the update actually makes it to any guest which
5074 * starts running in hardware virtualization between the set
5075 * and the acquisition of the spinlock, we must also ping the
5076 * CPU after setting the request bit.
5077 *
5078 */
5079
5080 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5081 return 0;
5082 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5083 return 0;
5084
5085 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5086
5087 raw_spin_lock(&kvm_lock);
5088 list_for_each_entry(kvm, &vm_list, vm_list) {
5089 kvm_for_each_vcpu(i, vcpu, kvm) {
5090 if (vcpu->cpu != freq->cpu)
5091 continue;
5092 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5093 if (vcpu->cpu != smp_processor_id())
5094 send_ipi = 1;
5095 }
5096 }
5097 raw_spin_unlock(&kvm_lock);
5098
5099 if (freq->old < freq->new && send_ipi) {
5100 /*
5101 * We upscale the frequency. Must make the guest
5102 * doesn't see old kvmclock values while running with
5103 * the new frequency, otherwise we risk the guest sees
5104 * time go backwards.
5105 *
5106 * In case we update the frequency for another cpu
5107 * (which might be in guest context) send an interrupt
5108 * to kick the cpu out of guest context. Next time
5109 * guest context is entered kvmclock will be updated,
5110 * so the guest will not see stale values.
5111 */
5112 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5113 }
5114 return 0;
5115 }
5116
5117 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5118 .notifier_call = kvmclock_cpufreq_notifier
5119 };
5120
5121 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5122 unsigned long action, void *hcpu)
5123 {
5124 unsigned int cpu = (unsigned long)hcpu;
5125
5126 switch (action) {
5127 case CPU_ONLINE:
5128 case CPU_DOWN_FAILED:
5129 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5130 break;
5131 case CPU_DOWN_PREPARE:
5132 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5133 break;
5134 }
5135 return NOTIFY_OK;
5136 }
5137
5138 static struct notifier_block kvmclock_cpu_notifier_block = {
5139 .notifier_call = kvmclock_cpu_notifier,
5140 .priority = -INT_MAX
5141 };
5142
5143 static void kvm_timer_init(void)
5144 {
5145 int cpu;
5146
5147 max_tsc_khz = tsc_khz;
5148 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5149 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5150 #ifdef CONFIG_CPU_FREQ
5151 struct cpufreq_policy policy;
5152 memset(&policy, 0, sizeof(policy));
5153 cpu = get_cpu();
5154 cpufreq_get_policy(&policy, cpu);
5155 if (policy.cpuinfo.max_freq)
5156 max_tsc_khz = policy.cpuinfo.max_freq;
5157 put_cpu();
5158 #endif
5159 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5160 CPUFREQ_TRANSITION_NOTIFIER);
5161 }
5162 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5163 for_each_online_cpu(cpu)
5164 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5165 }
5166
5167 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5168
5169 int kvm_is_in_guest(void)
5170 {
5171 return __this_cpu_read(current_vcpu) != NULL;
5172 }
5173
5174 static int kvm_is_user_mode(void)
5175 {
5176 int user_mode = 3;
5177
5178 if (__this_cpu_read(current_vcpu))
5179 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5180
5181 return user_mode != 0;
5182 }
5183
5184 static unsigned long kvm_get_guest_ip(void)
5185 {
5186 unsigned long ip = 0;
5187
5188 if (__this_cpu_read(current_vcpu))
5189 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5190
5191 return ip;
5192 }
5193
5194 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5195 .is_in_guest = kvm_is_in_guest,
5196 .is_user_mode = kvm_is_user_mode,
5197 .get_guest_ip = kvm_get_guest_ip,
5198 };
5199
5200 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5201 {
5202 __this_cpu_write(current_vcpu, vcpu);
5203 }
5204 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5205
5206 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5207 {
5208 __this_cpu_write(current_vcpu, NULL);
5209 }
5210 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5211
5212 static void kvm_set_mmio_spte_mask(void)
5213 {
5214 u64 mask;
5215 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5216
5217 /*
5218 * Set the reserved bits and the present bit of an paging-structure
5219 * entry to generate page fault with PFER.RSV = 1.
5220 */
5221 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5222 mask |= 1ull;
5223
5224 #ifdef CONFIG_X86_64
5225 /*
5226 * If reserved bit is not supported, clear the present bit to disable
5227 * mmio page fault.
5228 */
5229 if (maxphyaddr == 52)
5230 mask &= ~1ull;
5231 #endif
5232
5233 kvm_mmu_set_mmio_spte_mask(mask);
5234 }
5235
5236 #ifdef CONFIG_X86_64
5237 static void pvclock_gtod_update_fn(struct work_struct *work)
5238 {
5239 struct kvm *kvm;
5240
5241 struct kvm_vcpu *vcpu;
5242 int i;
5243
5244 raw_spin_lock(&kvm_lock);
5245 list_for_each_entry(kvm, &vm_list, vm_list)
5246 kvm_for_each_vcpu(i, vcpu, kvm)
5247 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5248 atomic_set(&kvm_guest_has_master_clock, 0);
5249 raw_spin_unlock(&kvm_lock);
5250 }
5251
5252 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5253
5254 /*
5255 * Notification about pvclock gtod data update.
5256 */
5257 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5258 void *priv)
5259 {
5260 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5261 struct timekeeper *tk = priv;
5262
5263 update_pvclock_gtod(tk);
5264
5265 /* disable master clock if host does not trust, or does not
5266 * use, TSC clocksource
5267 */
5268 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5269 atomic_read(&kvm_guest_has_master_clock) != 0)
5270 queue_work(system_long_wq, &pvclock_gtod_work);
5271
5272 return 0;
5273 }
5274
5275 static struct notifier_block pvclock_gtod_notifier = {
5276 .notifier_call = pvclock_gtod_notify,
5277 };
5278 #endif
5279
5280 int kvm_arch_init(void *opaque)
5281 {
5282 int r;
5283 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5284
5285 if (kvm_x86_ops) {
5286 printk(KERN_ERR "kvm: already loaded the other module\n");
5287 r = -EEXIST;
5288 goto out;
5289 }
5290
5291 if (!ops->cpu_has_kvm_support()) {
5292 printk(KERN_ERR "kvm: no hardware support\n");
5293 r = -EOPNOTSUPP;
5294 goto out;
5295 }
5296 if (ops->disabled_by_bios()) {
5297 printk(KERN_ERR "kvm: disabled by bios\n");
5298 r = -EOPNOTSUPP;
5299 goto out;
5300 }
5301
5302 r = -ENOMEM;
5303 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5304 if (!shared_msrs) {
5305 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5306 goto out;
5307 }
5308
5309 r = kvm_mmu_module_init();
5310 if (r)
5311 goto out_free_percpu;
5312
5313 kvm_set_mmio_spte_mask();
5314 kvm_init_msr_list();
5315
5316 kvm_x86_ops = ops;
5317 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5318 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5319
5320 kvm_timer_init();
5321
5322 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5323
5324 if (cpu_has_xsave)
5325 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5326
5327 kvm_lapic_init();
5328 #ifdef CONFIG_X86_64
5329 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5330 #endif
5331
5332 return 0;
5333
5334 out_free_percpu:
5335 free_percpu(shared_msrs);
5336 out:
5337 return r;
5338 }
5339
5340 void kvm_arch_exit(void)
5341 {
5342 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5343
5344 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5345 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5346 CPUFREQ_TRANSITION_NOTIFIER);
5347 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5348 #ifdef CONFIG_X86_64
5349 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5350 #endif
5351 kvm_x86_ops = NULL;
5352 kvm_mmu_module_exit();
5353 free_percpu(shared_msrs);
5354 }
5355
5356 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5357 {
5358 ++vcpu->stat.halt_exits;
5359 if (irqchip_in_kernel(vcpu->kvm)) {
5360 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5361 return 1;
5362 } else {
5363 vcpu->run->exit_reason = KVM_EXIT_HLT;
5364 return 0;
5365 }
5366 }
5367 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5368
5369 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5370 {
5371 u64 param, ingpa, outgpa, ret;
5372 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5373 bool fast, longmode;
5374 int cs_db, cs_l;
5375
5376 /*
5377 * hypercall generates UD from non zero cpl and real mode
5378 * per HYPER-V spec
5379 */
5380 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5381 kvm_queue_exception(vcpu, UD_VECTOR);
5382 return 0;
5383 }
5384
5385 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5386 longmode = is_long_mode(vcpu) && cs_l == 1;
5387
5388 if (!longmode) {
5389 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5390 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5391 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5392 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5393 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5394 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5395 }
5396 #ifdef CONFIG_X86_64
5397 else {
5398 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5399 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5400 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5401 }
5402 #endif
5403
5404 code = param & 0xffff;
5405 fast = (param >> 16) & 0x1;
5406 rep_cnt = (param >> 32) & 0xfff;
5407 rep_idx = (param >> 48) & 0xfff;
5408
5409 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5410
5411 switch (code) {
5412 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5413 kvm_vcpu_on_spin(vcpu);
5414 break;
5415 default:
5416 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5417 break;
5418 }
5419
5420 ret = res | (((u64)rep_done & 0xfff) << 32);
5421 if (longmode) {
5422 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5423 } else {
5424 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5425 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5426 }
5427
5428 return 1;
5429 }
5430
5431 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5432 {
5433 unsigned long nr, a0, a1, a2, a3, ret;
5434 int r = 1;
5435
5436 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5437 return kvm_hv_hypercall(vcpu);
5438
5439 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5440 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5441 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5442 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5443 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5444
5445 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5446
5447 if (!is_long_mode(vcpu)) {
5448 nr &= 0xFFFFFFFF;
5449 a0 &= 0xFFFFFFFF;
5450 a1 &= 0xFFFFFFFF;
5451 a2 &= 0xFFFFFFFF;
5452 a3 &= 0xFFFFFFFF;
5453 }
5454
5455 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5456 ret = -KVM_EPERM;
5457 goto out;
5458 }
5459
5460 switch (nr) {
5461 case KVM_HC_VAPIC_POLL_IRQ:
5462 ret = 0;
5463 break;
5464 default:
5465 ret = -KVM_ENOSYS;
5466 break;
5467 }
5468 out:
5469 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5470 ++vcpu->stat.hypercalls;
5471 return r;
5472 }
5473 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5474
5475 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5476 {
5477 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5478 char instruction[3];
5479 unsigned long rip = kvm_rip_read(vcpu);
5480
5481 /*
5482 * Blow out the MMU to ensure that no other VCPU has an active mapping
5483 * to ensure that the updated hypercall appears atomically across all
5484 * VCPUs.
5485 */
5486 kvm_mmu_zap_all(vcpu->kvm);
5487
5488 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5489
5490 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5491 }
5492
5493 /*
5494 * Check if userspace requested an interrupt window, and that the
5495 * interrupt window is open.
5496 *
5497 * No need to exit to userspace if we already have an interrupt queued.
5498 */
5499 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5500 {
5501 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5502 vcpu->run->request_interrupt_window &&
5503 kvm_arch_interrupt_allowed(vcpu));
5504 }
5505
5506 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5507 {
5508 struct kvm_run *kvm_run = vcpu->run;
5509
5510 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5511 kvm_run->cr8 = kvm_get_cr8(vcpu);
5512 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5513 if (irqchip_in_kernel(vcpu->kvm))
5514 kvm_run->ready_for_interrupt_injection = 1;
5515 else
5516 kvm_run->ready_for_interrupt_injection =
5517 kvm_arch_interrupt_allowed(vcpu) &&
5518 !kvm_cpu_has_interrupt(vcpu) &&
5519 !kvm_event_needs_reinjection(vcpu);
5520 }
5521
5522 static int vapic_enter(struct kvm_vcpu *vcpu)
5523 {
5524 struct kvm_lapic *apic = vcpu->arch.apic;
5525 struct page *page;
5526
5527 if (!apic || !apic->vapic_addr)
5528 return 0;
5529
5530 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5531 if (is_error_page(page))
5532 return -EFAULT;
5533
5534 vcpu->arch.apic->vapic_page = page;
5535 return 0;
5536 }
5537
5538 static void vapic_exit(struct kvm_vcpu *vcpu)
5539 {
5540 struct kvm_lapic *apic = vcpu->arch.apic;
5541 int idx;
5542
5543 if (!apic || !apic->vapic_addr)
5544 return;
5545
5546 idx = srcu_read_lock(&vcpu->kvm->srcu);
5547 kvm_release_page_dirty(apic->vapic_page);
5548 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5549 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5550 }
5551
5552 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5553 {
5554 int max_irr, tpr;
5555
5556 if (!kvm_x86_ops->update_cr8_intercept)
5557 return;
5558
5559 if (!vcpu->arch.apic)
5560 return;
5561
5562 if (!vcpu->arch.apic->vapic_addr)
5563 max_irr = kvm_lapic_find_highest_irr(vcpu);
5564 else
5565 max_irr = -1;
5566
5567 if (max_irr != -1)
5568 max_irr >>= 4;
5569
5570 tpr = kvm_lapic_get_cr8(vcpu);
5571
5572 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5573 }
5574
5575 static void inject_pending_event(struct kvm_vcpu *vcpu)
5576 {
5577 /* try to reinject previous events if any */
5578 if (vcpu->arch.exception.pending) {
5579 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5580 vcpu->arch.exception.has_error_code,
5581 vcpu->arch.exception.error_code);
5582 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5583 vcpu->arch.exception.has_error_code,
5584 vcpu->arch.exception.error_code,
5585 vcpu->arch.exception.reinject);
5586 return;
5587 }
5588
5589 if (vcpu->arch.nmi_injected) {
5590 kvm_x86_ops->set_nmi(vcpu);
5591 return;
5592 }
5593
5594 if (vcpu->arch.interrupt.pending) {
5595 kvm_x86_ops->set_irq(vcpu);
5596 return;
5597 }
5598
5599 /* try to inject new event if pending */
5600 if (vcpu->arch.nmi_pending) {
5601 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5602 --vcpu->arch.nmi_pending;
5603 vcpu->arch.nmi_injected = true;
5604 kvm_x86_ops->set_nmi(vcpu);
5605 }
5606 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5607 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5608 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5609 false);
5610 kvm_x86_ops->set_irq(vcpu);
5611 }
5612 }
5613 }
5614
5615 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5616 {
5617 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5618 !vcpu->guest_xcr0_loaded) {
5619 /* kvm_set_xcr() also depends on this */
5620 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5621 vcpu->guest_xcr0_loaded = 1;
5622 }
5623 }
5624
5625 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5626 {
5627 if (vcpu->guest_xcr0_loaded) {
5628 if (vcpu->arch.xcr0 != host_xcr0)
5629 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5630 vcpu->guest_xcr0_loaded = 0;
5631 }
5632 }
5633
5634 static void process_nmi(struct kvm_vcpu *vcpu)
5635 {
5636 unsigned limit = 2;
5637
5638 /*
5639 * x86 is limited to one NMI running, and one NMI pending after it.
5640 * If an NMI is already in progress, limit further NMIs to just one.
5641 * Otherwise, allow two (and we'll inject the first one immediately).
5642 */
5643 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5644 limit = 1;
5645
5646 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5647 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5648 kvm_make_request(KVM_REQ_EVENT, vcpu);
5649 }
5650
5651 static void kvm_gen_update_masterclock(struct kvm *kvm)
5652 {
5653 #ifdef CONFIG_X86_64
5654 int i;
5655 struct kvm_vcpu *vcpu;
5656 struct kvm_arch *ka = &kvm->arch;
5657
5658 spin_lock(&ka->pvclock_gtod_sync_lock);
5659 kvm_make_mclock_inprogress_request(kvm);
5660 /* no guest entries from this point */
5661 pvclock_update_vm_gtod_copy(kvm);
5662
5663 kvm_for_each_vcpu(i, vcpu, kvm)
5664 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5665
5666 /* guest entries allowed */
5667 kvm_for_each_vcpu(i, vcpu, kvm)
5668 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5669
5670 spin_unlock(&ka->pvclock_gtod_sync_lock);
5671 #endif
5672 }
5673
5674 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5675 {
5676 u64 eoi_exit_bitmap[4];
5677 u32 tmr[8];
5678
5679 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5680 return;
5681
5682 memset(eoi_exit_bitmap, 0, 32);
5683 memset(tmr, 0, 32);
5684
5685 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5686 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5687 kvm_apic_update_tmr(vcpu, tmr);
5688 }
5689
5690 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5691 {
5692 int r;
5693 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5694 vcpu->run->request_interrupt_window;
5695 bool req_immediate_exit = 0;
5696
5697 if (vcpu->requests) {
5698 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5699 kvm_mmu_unload(vcpu);
5700 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5701 __kvm_migrate_timers(vcpu);
5702 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5703 kvm_gen_update_masterclock(vcpu->kvm);
5704 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5705 r = kvm_guest_time_update(vcpu);
5706 if (unlikely(r))
5707 goto out;
5708 }
5709 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5710 kvm_mmu_sync_roots(vcpu);
5711 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5712 kvm_x86_ops->tlb_flush(vcpu);
5713 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5714 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5715 r = 0;
5716 goto out;
5717 }
5718 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5719 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5720 r = 0;
5721 goto out;
5722 }
5723 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5724 vcpu->fpu_active = 0;
5725 kvm_x86_ops->fpu_deactivate(vcpu);
5726 }
5727 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5728 /* Page is swapped out. Do synthetic halt */
5729 vcpu->arch.apf.halted = true;
5730 r = 1;
5731 goto out;
5732 }
5733 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5734 record_steal_time(vcpu);
5735 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5736 process_nmi(vcpu);
5737 req_immediate_exit =
5738 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5739 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5740 kvm_handle_pmu_event(vcpu);
5741 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5742 kvm_deliver_pmi(vcpu);
5743 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5744 vcpu_scan_ioapic(vcpu);
5745 }
5746
5747 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5748 kvm_apic_accept_events(vcpu);
5749 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5750 r = 1;
5751 goto out;
5752 }
5753
5754 inject_pending_event(vcpu);
5755
5756 /* enable NMI/IRQ window open exits if needed */
5757 if (vcpu->arch.nmi_pending)
5758 kvm_x86_ops->enable_nmi_window(vcpu);
5759 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5760 kvm_x86_ops->enable_irq_window(vcpu);
5761
5762 if (kvm_lapic_enabled(vcpu)) {
5763 /*
5764 * Update architecture specific hints for APIC
5765 * virtual interrupt delivery.
5766 */
5767 if (kvm_x86_ops->hwapic_irr_update)
5768 kvm_x86_ops->hwapic_irr_update(vcpu,
5769 kvm_lapic_find_highest_irr(vcpu));
5770 update_cr8_intercept(vcpu);
5771 kvm_lapic_sync_to_vapic(vcpu);
5772 }
5773 }
5774
5775 r = kvm_mmu_reload(vcpu);
5776 if (unlikely(r)) {
5777 goto cancel_injection;
5778 }
5779
5780 preempt_disable();
5781
5782 kvm_x86_ops->prepare_guest_switch(vcpu);
5783 if (vcpu->fpu_active)
5784 kvm_load_guest_fpu(vcpu);
5785 kvm_load_guest_xcr0(vcpu);
5786
5787 vcpu->mode = IN_GUEST_MODE;
5788
5789 /* We should set ->mode before check ->requests,
5790 * see the comment in make_all_cpus_request.
5791 */
5792 smp_mb();
5793
5794 local_irq_disable();
5795
5796 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5797 || need_resched() || signal_pending(current)) {
5798 vcpu->mode = OUTSIDE_GUEST_MODE;
5799 smp_wmb();
5800 local_irq_enable();
5801 preempt_enable();
5802 r = 1;
5803 goto cancel_injection;
5804 }
5805
5806 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5807
5808 if (req_immediate_exit)
5809 smp_send_reschedule(vcpu->cpu);
5810
5811 kvm_guest_enter();
5812
5813 if (unlikely(vcpu->arch.switch_db_regs)) {
5814 set_debugreg(0, 7);
5815 set_debugreg(vcpu->arch.eff_db[0], 0);
5816 set_debugreg(vcpu->arch.eff_db[1], 1);
5817 set_debugreg(vcpu->arch.eff_db[2], 2);
5818 set_debugreg(vcpu->arch.eff_db[3], 3);
5819 }
5820
5821 trace_kvm_entry(vcpu->vcpu_id);
5822 kvm_x86_ops->run(vcpu);
5823
5824 /*
5825 * If the guest has used debug registers, at least dr7
5826 * will be disabled while returning to the host.
5827 * If we don't have active breakpoints in the host, we don't
5828 * care about the messed up debug address registers. But if
5829 * we have some of them active, restore the old state.
5830 */
5831 if (hw_breakpoint_active())
5832 hw_breakpoint_restore();
5833
5834 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5835 native_read_tsc());
5836
5837 vcpu->mode = OUTSIDE_GUEST_MODE;
5838 smp_wmb();
5839
5840 /* Interrupt is enabled by handle_external_intr() */
5841 kvm_x86_ops->handle_external_intr(vcpu);
5842
5843 ++vcpu->stat.exits;
5844
5845 /*
5846 * We must have an instruction between local_irq_enable() and
5847 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5848 * the interrupt shadow. The stat.exits increment will do nicely.
5849 * But we need to prevent reordering, hence this barrier():
5850 */
5851 barrier();
5852
5853 kvm_guest_exit();
5854
5855 preempt_enable();
5856
5857 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5858
5859 /*
5860 * Profile KVM exit RIPs:
5861 */
5862 if (unlikely(prof_on == KVM_PROFILING)) {
5863 unsigned long rip = kvm_rip_read(vcpu);
5864 profile_hit(KVM_PROFILING, (void *)rip);
5865 }
5866
5867 if (unlikely(vcpu->arch.tsc_always_catchup))
5868 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5869
5870 if (vcpu->arch.apic_attention)
5871 kvm_lapic_sync_from_vapic(vcpu);
5872
5873 r = kvm_x86_ops->handle_exit(vcpu);
5874 return r;
5875
5876 cancel_injection:
5877 kvm_x86_ops->cancel_injection(vcpu);
5878 if (unlikely(vcpu->arch.apic_attention))
5879 kvm_lapic_sync_from_vapic(vcpu);
5880 out:
5881 return r;
5882 }
5883
5884
5885 static int __vcpu_run(struct kvm_vcpu *vcpu)
5886 {
5887 int r;
5888 struct kvm *kvm = vcpu->kvm;
5889
5890 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5891 r = vapic_enter(vcpu);
5892 if (r) {
5893 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5894 return r;
5895 }
5896
5897 r = 1;
5898 while (r > 0) {
5899 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5900 !vcpu->arch.apf.halted)
5901 r = vcpu_enter_guest(vcpu);
5902 else {
5903 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5904 kvm_vcpu_block(vcpu);
5905 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5906 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5907 kvm_apic_accept_events(vcpu);
5908 switch(vcpu->arch.mp_state) {
5909 case KVM_MP_STATE_HALTED:
5910 vcpu->arch.mp_state =
5911 KVM_MP_STATE_RUNNABLE;
5912 case KVM_MP_STATE_RUNNABLE:
5913 vcpu->arch.apf.halted = false;
5914 break;
5915 case KVM_MP_STATE_INIT_RECEIVED:
5916 break;
5917 default:
5918 r = -EINTR;
5919 break;
5920 }
5921 }
5922 }
5923
5924 if (r <= 0)
5925 break;
5926
5927 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5928 if (kvm_cpu_has_pending_timer(vcpu))
5929 kvm_inject_pending_timer_irqs(vcpu);
5930
5931 if (dm_request_for_irq_injection(vcpu)) {
5932 r = -EINTR;
5933 vcpu->run->exit_reason = KVM_EXIT_INTR;
5934 ++vcpu->stat.request_irq_exits;
5935 }
5936
5937 kvm_check_async_pf_completion(vcpu);
5938
5939 if (signal_pending(current)) {
5940 r = -EINTR;
5941 vcpu->run->exit_reason = KVM_EXIT_INTR;
5942 ++vcpu->stat.signal_exits;
5943 }
5944 if (need_resched()) {
5945 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5946 kvm_resched(vcpu);
5947 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5948 }
5949 }
5950
5951 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5952
5953 vapic_exit(vcpu);
5954
5955 return r;
5956 }
5957
5958 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5959 {
5960 int r;
5961 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5962 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5963 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5964 if (r != EMULATE_DONE)
5965 return 0;
5966 return 1;
5967 }
5968
5969 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5970 {
5971 BUG_ON(!vcpu->arch.pio.count);
5972
5973 return complete_emulated_io(vcpu);
5974 }
5975
5976 /*
5977 * Implements the following, as a state machine:
5978 *
5979 * read:
5980 * for each fragment
5981 * for each mmio piece in the fragment
5982 * write gpa, len
5983 * exit
5984 * copy data
5985 * execute insn
5986 *
5987 * write:
5988 * for each fragment
5989 * for each mmio piece in the fragment
5990 * write gpa, len
5991 * copy data
5992 * exit
5993 */
5994 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5995 {
5996 struct kvm_run *run = vcpu->run;
5997 struct kvm_mmio_fragment *frag;
5998 unsigned len;
5999
6000 BUG_ON(!vcpu->mmio_needed);
6001
6002 /* Complete previous fragment */
6003 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6004 len = min(8u, frag->len);
6005 if (!vcpu->mmio_is_write)
6006 memcpy(frag->data, run->mmio.data, len);
6007
6008 if (frag->len <= 8) {
6009 /* Switch to the next fragment. */
6010 frag++;
6011 vcpu->mmio_cur_fragment++;
6012 } else {
6013 /* Go forward to the next mmio piece. */
6014 frag->data += len;
6015 frag->gpa += len;
6016 frag->len -= len;
6017 }
6018
6019 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6020 vcpu->mmio_needed = 0;
6021 if (vcpu->mmio_is_write)
6022 return 1;
6023 vcpu->mmio_read_completed = 1;
6024 return complete_emulated_io(vcpu);
6025 }
6026
6027 run->exit_reason = KVM_EXIT_MMIO;
6028 run->mmio.phys_addr = frag->gpa;
6029 if (vcpu->mmio_is_write)
6030 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6031 run->mmio.len = min(8u, frag->len);
6032 run->mmio.is_write = vcpu->mmio_is_write;
6033 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6034 return 0;
6035 }
6036
6037
6038 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6039 {
6040 int r;
6041 sigset_t sigsaved;
6042
6043 if (!tsk_used_math(current) && init_fpu(current))
6044 return -ENOMEM;
6045
6046 if (vcpu->sigset_active)
6047 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6048
6049 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6050 kvm_vcpu_block(vcpu);
6051 kvm_apic_accept_events(vcpu);
6052 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6053 r = -EAGAIN;
6054 goto out;
6055 }
6056
6057 /* re-sync apic's tpr */
6058 if (!irqchip_in_kernel(vcpu->kvm)) {
6059 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6060 r = -EINVAL;
6061 goto out;
6062 }
6063 }
6064
6065 if (unlikely(vcpu->arch.complete_userspace_io)) {
6066 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6067 vcpu->arch.complete_userspace_io = NULL;
6068 r = cui(vcpu);
6069 if (r <= 0)
6070 goto out;
6071 } else
6072 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6073
6074 r = __vcpu_run(vcpu);
6075
6076 out:
6077 post_kvm_run_save(vcpu);
6078 if (vcpu->sigset_active)
6079 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6080
6081 return r;
6082 }
6083
6084 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6085 {
6086 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6087 /*
6088 * We are here if userspace calls get_regs() in the middle of
6089 * instruction emulation. Registers state needs to be copied
6090 * back from emulation context to vcpu. Userspace shouldn't do
6091 * that usually, but some bad designed PV devices (vmware
6092 * backdoor interface) need this to work
6093 */
6094 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6095 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6096 }
6097 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6098 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6099 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6100 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6101 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6102 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6103 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6104 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6105 #ifdef CONFIG_X86_64
6106 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6107 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6108 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6109 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6110 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6111 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6112 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6113 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6114 #endif
6115
6116 regs->rip = kvm_rip_read(vcpu);
6117 regs->rflags = kvm_get_rflags(vcpu);
6118
6119 return 0;
6120 }
6121
6122 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6123 {
6124 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6125 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6126
6127 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6128 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6129 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6130 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6131 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6132 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6133 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6134 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6135 #ifdef CONFIG_X86_64
6136 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6137 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6138 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6139 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6140 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6141 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6142 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6143 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6144 #endif
6145
6146 kvm_rip_write(vcpu, regs->rip);
6147 kvm_set_rflags(vcpu, regs->rflags);
6148
6149 vcpu->arch.exception.pending = false;
6150
6151 kvm_make_request(KVM_REQ_EVENT, vcpu);
6152
6153 return 0;
6154 }
6155
6156 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6157 {
6158 struct kvm_segment cs;
6159
6160 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6161 *db = cs.db;
6162 *l = cs.l;
6163 }
6164 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6165
6166 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6167 struct kvm_sregs *sregs)
6168 {
6169 struct desc_ptr dt;
6170
6171 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6172 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6173 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6174 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6175 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6176 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6177
6178 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6179 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6180
6181 kvm_x86_ops->get_idt(vcpu, &dt);
6182 sregs->idt.limit = dt.size;
6183 sregs->idt.base = dt.address;
6184 kvm_x86_ops->get_gdt(vcpu, &dt);
6185 sregs->gdt.limit = dt.size;
6186 sregs->gdt.base = dt.address;
6187
6188 sregs->cr0 = kvm_read_cr0(vcpu);
6189 sregs->cr2 = vcpu->arch.cr2;
6190 sregs->cr3 = kvm_read_cr3(vcpu);
6191 sregs->cr4 = kvm_read_cr4(vcpu);
6192 sregs->cr8 = kvm_get_cr8(vcpu);
6193 sregs->efer = vcpu->arch.efer;
6194 sregs->apic_base = kvm_get_apic_base(vcpu);
6195
6196 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6197
6198 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6199 set_bit(vcpu->arch.interrupt.nr,
6200 (unsigned long *)sregs->interrupt_bitmap);
6201
6202 return 0;
6203 }
6204
6205 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6206 struct kvm_mp_state *mp_state)
6207 {
6208 kvm_apic_accept_events(vcpu);
6209 mp_state->mp_state = vcpu->arch.mp_state;
6210 return 0;
6211 }
6212
6213 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6214 struct kvm_mp_state *mp_state)
6215 {
6216 if (!kvm_vcpu_has_lapic(vcpu) &&
6217 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6218 return -EINVAL;
6219
6220 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6221 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6222 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6223 } else
6224 vcpu->arch.mp_state = mp_state->mp_state;
6225 kvm_make_request(KVM_REQ_EVENT, vcpu);
6226 return 0;
6227 }
6228
6229 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6230 int reason, bool has_error_code, u32 error_code)
6231 {
6232 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6233 int ret;
6234
6235 init_emulate_ctxt(vcpu);
6236
6237 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6238 has_error_code, error_code);
6239
6240 if (ret)
6241 return EMULATE_FAIL;
6242
6243 kvm_rip_write(vcpu, ctxt->eip);
6244 kvm_set_rflags(vcpu, ctxt->eflags);
6245 kvm_make_request(KVM_REQ_EVENT, vcpu);
6246 return EMULATE_DONE;
6247 }
6248 EXPORT_SYMBOL_GPL(kvm_task_switch);
6249
6250 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6251 struct kvm_sregs *sregs)
6252 {
6253 int mmu_reset_needed = 0;
6254 int pending_vec, max_bits, idx;
6255 struct desc_ptr dt;
6256
6257 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6258 return -EINVAL;
6259
6260 dt.size = sregs->idt.limit;
6261 dt.address = sregs->idt.base;
6262 kvm_x86_ops->set_idt(vcpu, &dt);
6263 dt.size = sregs->gdt.limit;
6264 dt.address = sregs->gdt.base;
6265 kvm_x86_ops->set_gdt(vcpu, &dt);
6266
6267 vcpu->arch.cr2 = sregs->cr2;
6268 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6269 vcpu->arch.cr3 = sregs->cr3;
6270 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6271
6272 kvm_set_cr8(vcpu, sregs->cr8);
6273
6274 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6275 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6276 kvm_set_apic_base(vcpu, sregs->apic_base);
6277
6278 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6279 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6280 vcpu->arch.cr0 = sregs->cr0;
6281
6282 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6283 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6284 if (sregs->cr4 & X86_CR4_OSXSAVE)
6285 kvm_update_cpuid(vcpu);
6286
6287 idx = srcu_read_lock(&vcpu->kvm->srcu);
6288 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6289 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6290 mmu_reset_needed = 1;
6291 }
6292 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6293
6294 if (mmu_reset_needed)
6295 kvm_mmu_reset_context(vcpu);
6296
6297 max_bits = KVM_NR_INTERRUPTS;
6298 pending_vec = find_first_bit(
6299 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6300 if (pending_vec < max_bits) {
6301 kvm_queue_interrupt(vcpu, pending_vec, false);
6302 pr_debug("Set back pending irq %d\n", pending_vec);
6303 }
6304
6305 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6306 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6307 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6308 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6309 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6310 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6311
6312 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6313 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6314
6315 update_cr8_intercept(vcpu);
6316
6317 /* Older userspace won't unhalt the vcpu on reset. */
6318 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6319 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6320 !is_protmode(vcpu))
6321 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6322
6323 kvm_make_request(KVM_REQ_EVENT, vcpu);
6324
6325 return 0;
6326 }
6327
6328 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6329 struct kvm_guest_debug *dbg)
6330 {
6331 unsigned long rflags;
6332 int i, r;
6333
6334 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6335 r = -EBUSY;
6336 if (vcpu->arch.exception.pending)
6337 goto out;
6338 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6339 kvm_queue_exception(vcpu, DB_VECTOR);
6340 else
6341 kvm_queue_exception(vcpu, BP_VECTOR);
6342 }
6343
6344 /*
6345 * Read rflags as long as potentially injected trace flags are still
6346 * filtered out.
6347 */
6348 rflags = kvm_get_rflags(vcpu);
6349
6350 vcpu->guest_debug = dbg->control;
6351 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6352 vcpu->guest_debug = 0;
6353
6354 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6355 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6356 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6357 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6358 } else {
6359 for (i = 0; i < KVM_NR_DB_REGS; i++)
6360 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6361 }
6362 kvm_update_dr7(vcpu);
6363
6364 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6365 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6366 get_segment_base(vcpu, VCPU_SREG_CS);
6367
6368 /*
6369 * Trigger an rflags update that will inject or remove the trace
6370 * flags.
6371 */
6372 kvm_set_rflags(vcpu, rflags);
6373
6374 kvm_x86_ops->update_db_bp_intercept(vcpu);
6375
6376 r = 0;
6377
6378 out:
6379
6380 return r;
6381 }
6382
6383 /*
6384 * Translate a guest virtual address to a guest physical address.
6385 */
6386 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6387 struct kvm_translation *tr)
6388 {
6389 unsigned long vaddr = tr->linear_address;
6390 gpa_t gpa;
6391 int idx;
6392
6393 idx = srcu_read_lock(&vcpu->kvm->srcu);
6394 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6395 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6396 tr->physical_address = gpa;
6397 tr->valid = gpa != UNMAPPED_GVA;
6398 tr->writeable = 1;
6399 tr->usermode = 0;
6400
6401 return 0;
6402 }
6403
6404 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6405 {
6406 struct i387_fxsave_struct *fxsave =
6407 &vcpu->arch.guest_fpu.state->fxsave;
6408
6409 memcpy(fpu->fpr, fxsave->st_space, 128);
6410 fpu->fcw = fxsave->cwd;
6411 fpu->fsw = fxsave->swd;
6412 fpu->ftwx = fxsave->twd;
6413 fpu->last_opcode = fxsave->fop;
6414 fpu->last_ip = fxsave->rip;
6415 fpu->last_dp = fxsave->rdp;
6416 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6417
6418 return 0;
6419 }
6420
6421 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6422 {
6423 struct i387_fxsave_struct *fxsave =
6424 &vcpu->arch.guest_fpu.state->fxsave;
6425
6426 memcpy(fxsave->st_space, fpu->fpr, 128);
6427 fxsave->cwd = fpu->fcw;
6428 fxsave->swd = fpu->fsw;
6429 fxsave->twd = fpu->ftwx;
6430 fxsave->fop = fpu->last_opcode;
6431 fxsave->rip = fpu->last_ip;
6432 fxsave->rdp = fpu->last_dp;
6433 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6434
6435 return 0;
6436 }
6437
6438 int fx_init(struct kvm_vcpu *vcpu)
6439 {
6440 int err;
6441
6442 err = fpu_alloc(&vcpu->arch.guest_fpu);
6443 if (err)
6444 return err;
6445
6446 fpu_finit(&vcpu->arch.guest_fpu);
6447
6448 /*
6449 * Ensure guest xcr0 is valid for loading
6450 */
6451 vcpu->arch.xcr0 = XSTATE_FP;
6452
6453 vcpu->arch.cr0 |= X86_CR0_ET;
6454
6455 return 0;
6456 }
6457 EXPORT_SYMBOL_GPL(fx_init);
6458
6459 static void fx_free(struct kvm_vcpu *vcpu)
6460 {
6461 fpu_free(&vcpu->arch.guest_fpu);
6462 }
6463
6464 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6465 {
6466 if (vcpu->guest_fpu_loaded)
6467 return;
6468
6469 /*
6470 * Restore all possible states in the guest,
6471 * and assume host would use all available bits.
6472 * Guest xcr0 would be loaded later.
6473 */
6474 kvm_put_guest_xcr0(vcpu);
6475 vcpu->guest_fpu_loaded = 1;
6476 __kernel_fpu_begin();
6477 fpu_restore_checking(&vcpu->arch.guest_fpu);
6478 trace_kvm_fpu(1);
6479 }
6480
6481 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6482 {
6483 kvm_put_guest_xcr0(vcpu);
6484
6485 if (!vcpu->guest_fpu_loaded)
6486 return;
6487
6488 vcpu->guest_fpu_loaded = 0;
6489 fpu_save_init(&vcpu->arch.guest_fpu);
6490 __kernel_fpu_end();
6491 ++vcpu->stat.fpu_reload;
6492 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6493 trace_kvm_fpu(0);
6494 }
6495
6496 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6497 {
6498 kvmclock_reset(vcpu);
6499
6500 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6501 fx_free(vcpu);
6502 kvm_x86_ops->vcpu_free(vcpu);
6503 }
6504
6505 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6506 unsigned int id)
6507 {
6508 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6509 printk_once(KERN_WARNING
6510 "kvm: SMP vm created on host with unstable TSC; "
6511 "guest TSC will not be reliable\n");
6512 return kvm_x86_ops->vcpu_create(kvm, id);
6513 }
6514
6515 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6516 {
6517 int r;
6518
6519 vcpu->arch.mtrr_state.have_fixed = 1;
6520 r = vcpu_load(vcpu);
6521 if (r)
6522 return r;
6523 kvm_vcpu_reset(vcpu);
6524 r = kvm_mmu_setup(vcpu);
6525 vcpu_put(vcpu);
6526
6527 return r;
6528 }
6529
6530 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6531 {
6532 int r;
6533 struct msr_data msr;
6534
6535 r = vcpu_load(vcpu);
6536 if (r)
6537 return r;
6538 msr.data = 0x0;
6539 msr.index = MSR_IA32_TSC;
6540 msr.host_initiated = true;
6541 kvm_write_tsc(vcpu, &msr);
6542 vcpu_put(vcpu);
6543
6544 return r;
6545 }
6546
6547 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6548 {
6549 int r;
6550 vcpu->arch.apf.msr_val = 0;
6551
6552 r = vcpu_load(vcpu);
6553 BUG_ON(r);
6554 kvm_mmu_unload(vcpu);
6555 vcpu_put(vcpu);
6556
6557 fx_free(vcpu);
6558 kvm_x86_ops->vcpu_free(vcpu);
6559 }
6560
6561 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6562 {
6563 atomic_set(&vcpu->arch.nmi_queued, 0);
6564 vcpu->arch.nmi_pending = 0;
6565 vcpu->arch.nmi_injected = false;
6566
6567 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6568 vcpu->arch.dr6 = DR6_FIXED_1;
6569 vcpu->arch.dr7 = DR7_FIXED_1;
6570 kvm_update_dr7(vcpu);
6571
6572 kvm_make_request(KVM_REQ_EVENT, vcpu);
6573 vcpu->arch.apf.msr_val = 0;
6574 vcpu->arch.st.msr_val = 0;
6575
6576 kvmclock_reset(vcpu);
6577
6578 kvm_clear_async_pf_completion_queue(vcpu);
6579 kvm_async_pf_hash_reset(vcpu);
6580 vcpu->arch.apf.halted = false;
6581
6582 kvm_pmu_reset(vcpu);
6583
6584 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6585 vcpu->arch.regs_avail = ~0;
6586 vcpu->arch.regs_dirty = ~0;
6587
6588 kvm_x86_ops->vcpu_reset(vcpu);
6589 }
6590
6591 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6592 {
6593 struct kvm_segment cs;
6594
6595 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6596 cs.selector = vector << 8;
6597 cs.base = vector << 12;
6598 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6599 kvm_rip_write(vcpu, 0);
6600 }
6601
6602 int kvm_arch_hardware_enable(void *garbage)
6603 {
6604 struct kvm *kvm;
6605 struct kvm_vcpu *vcpu;
6606 int i;
6607 int ret;
6608 u64 local_tsc;
6609 u64 max_tsc = 0;
6610 bool stable, backwards_tsc = false;
6611
6612 kvm_shared_msr_cpu_online();
6613 ret = kvm_x86_ops->hardware_enable(garbage);
6614 if (ret != 0)
6615 return ret;
6616
6617 local_tsc = native_read_tsc();
6618 stable = !check_tsc_unstable();
6619 list_for_each_entry(kvm, &vm_list, vm_list) {
6620 kvm_for_each_vcpu(i, vcpu, kvm) {
6621 if (!stable && vcpu->cpu == smp_processor_id())
6622 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6623 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6624 backwards_tsc = true;
6625 if (vcpu->arch.last_host_tsc > max_tsc)
6626 max_tsc = vcpu->arch.last_host_tsc;
6627 }
6628 }
6629 }
6630
6631 /*
6632 * Sometimes, even reliable TSCs go backwards. This happens on
6633 * platforms that reset TSC during suspend or hibernate actions, but
6634 * maintain synchronization. We must compensate. Fortunately, we can
6635 * detect that condition here, which happens early in CPU bringup,
6636 * before any KVM threads can be running. Unfortunately, we can't
6637 * bring the TSCs fully up to date with real time, as we aren't yet far
6638 * enough into CPU bringup that we know how much real time has actually
6639 * elapsed; our helper function, get_kernel_ns() will be using boot
6640 * variables that haven't been updated yet.
6641 *
6642 * So we simply find the maximum observed TSC above, then record the
6643 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6644 * the adjustment will be applied. Note that we accumulate
6645 * adjustments, in case multiple suspend cycles happen before some VCPU
6646 * gets a chance to run again. In the event that no KVM threads get a
6647 * chance to run, we will miss the entire elapsed period, as we'll have
6648 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6649 * loose cycle time. This isn't too big a deal, since the loss will be
6650 * uniform across all VCPUs (not to mention the scenario is extremely
6651 * unlikely). It is possible that a second hibernate recovery happens
6652 * much faster than a first, causing the observed TSC here to be
6653 * smaller; this would require additional padding adjustment, which is
6654 * why we set last_host_tsc to the local tsc observed here.
6655 *
6656 * N.B. - this code below runs only on platforms with reliable TSC,
6657 * as that is the only way backwards_tsc is set above. Also note
6658 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6659 * have the same delta_cyc adjustment applied if backwards_tsc
6660 * is detected. Note further, this adjustment is only done once,
6661 * as we reset last_host_tsc on all VCPUs to stop this from being
6662 * called multiple times (one for each physical CPU bringup).
6663 *
6664 * Platforms with unreliable TSCs don't have to deal with this, they
6665 * will be compensated by the logic in vcpu_load, which sets the TSC to
6666 * catchup mode. This will catchup all VCPUs to real time, but cannot
6667 * guarantee that they stay in perfect synchronization.
6668 */
6669 if (backwards_tsc) {
6670 u64 delta_cyc = max_tsc - local_tsc;
6671 list_for_each_entry(kvm, &vm_list, vm_list) {
6672 kvm_for_each_vcpu(i, vcpu, kvm) {
6673 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6674 vcpu->arch.last_host_tsc = local_tsc;
6675 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6676 &vcpu->requests);
6677 }
6678
6679 /*
6680 * We have to disable TSC offset matching.. if you were
6681 * booting a VM while issuing an S4 host suspend....
6682 * you may have some problem. Solving this issue is
6683 * left as an exercise to the reader.
6684 */
6685 kvm->arch.last_tsc_nsec = 0;
6686 kvm->arch.last_tsc_write = 0;
6687 }
6688
6689 }
6690 return 0;
6691 }
6692
6693 void kvm_arch_hardware_disable(void *garbage)
6694 {
6695 kvm_x86_ops->hardware_disable(garbage);
6696 drop_user_return_notifiers(garbage);
6697 }
6698
6699 int kvm_arch_hardware_setup(void)
6700 {
6701 return kvm_x86_ops->hardware_setup();
6702 }
6703
6704 void kvm_arch_hardware_unsetup(void)
6705 {
6706 kvm_x86_ops->hardware_unsetup();
6707 }
6708
6709 void kvm_arch_check_processor_compat(void *rtn)
6710 {
6711 kvm_x86_ops->check_processor_compatibility(rtn);
6712 }
6713
6714 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6715 {
6716 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6717 }
6718
6719 struct static_key kvm_no_apic_vcpu __read_mostly;
6720
6721 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6722 {
6723 struct page *page;
6724 struct kvm *kvm;
6725 int r;
6726
6727 BUG_ON(vcpu->kvm == NULL);
6728 kvm = vcpu->kvm;
6729
6730 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6731 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6732 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6733 else
6734 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6735
6736 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6737 if (!page) {
6738 r = -ENOMEM;
6739 goto fail;
6740 }
6741 vcpu->arch.pio_data = page_address(page);
6742
6743 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6744
6745 r = kvm_mmu_create(vcpu);
6746 if (r < 0)
6747 goto fail_free_pio_data;
6748
6749 if (irqchip_in_kernel(kvm)) {
6750 r = kvm_create_lapic(vcpu);
6751 if (r < 0)
6752 goto fail_mmu_destroy;
6753 } else
6754 static_key_slow_inc(&kvm_no_apic_vcpu);
6755
6756 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6757 GFP_KERNEL);
6758 if (!vcpu->arch.mce_banks) {
6759 r = -ENOMEM;
6760 goto fail_free_lapic;
6761 }
6762 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6763
6764 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6765 r = -ENOMEM;
6766 goto fail_free_mce_banks;
6767 }
6768
6769 r = fx_init(vcpu);
6770 if (r)
6771 goto fail_free_wbinvd_dirty_mask;
6772
6773 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6774 vcpu->arch.pv_time_enabled = false;
6775 kvm_async_pf_hash_reset(vcpu);
6776 kvm_pmu_init(vcpu);
6777
6778 return 0;
6779 fail_free_wbinvd_dirty_mask:
6780 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6781 fail_free_mce_banks:
6782 kfree(vcpu->arch.mce_banks);
6783 fail_free_lapic:
6784 kvm_free_lapic(vcpu);
6785 fail_mmu_destroy:
6786 kvm_mmu_destroy(vcpu);
6787 fail_free_pio_data:
6788 free_page((unsigned long)vcpu->arch.pio_data);
6789 fail:
6790 return r;
6791 }
6792
6793 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6794 {
6795 int idx;
6796
6797 kvm_pmu_destroy(vcpu);
6798 kfree(vcpu->arch.mce_banks);
6799 kvm_free_lapic(vcpu);
6800 idx = srcu_read_lock(&vcpu->kvm->srcu);
6801 kvm_mmu_destroy(vcpu);
6802 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6803 free_page((unsigned long)vcpu->arch.pio_data);
6804 if (!irqchip_in_kernel(vcpu->kvm))
6805 static_key_slow_dec(&kvm_no_apic_vcpu);
6806 }
6807
6808 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6809 {
6810 if (type)
6811 return -EINVAL;
6812
6813 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6814 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6815
6816 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6817 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6818 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6819 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6820 &kvm->arch.irq_sources_bitmap);
6821
6822 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6823 mutex_init(&kvm->arch.apic_map_lock);
6824 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6825
6826 pvclock_update_vm_gtod_copy(kvm);
6827
6828 return 0;
6829 }
6830
6831 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6832 {
6833 int r;
6834 r = vcpu_load(vcpu);
6835 BUG_ON(r);
6836 kvm_mmu_unload(vcpu);
6837 vcpu_put(vcpu);
6838 }
6839
6840 static void kvm_free_vcpus(struct kvm *kvm)
6841 {
6842 unsigned int i;
6843 struct kvm_vcpu *vcpu;
6844
6845 /*
6846 * Unpin any mmu pages first.
6847 */
6848 kvm_for_each_vcpu(i, vcpu, kvm) {
6849 kvm_clear_async_pf_completion_queue(vcpu);
6850 kvm_unload_vcpu_mmu(vcpu);
6851 }
6852 kvm_for_each_vcpu(i, vcpu, kvm)
6853 kvm_arch_vcpu_free(vcpu);
6854
6855 mutex_lock(&kvm->lock);
6856 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6857 kvm->vcpus[i] = NULL;
6858
6859 atomic_set(&kvm->online_vcpus, 0);
6860 mutex_unlock(&kvm->lock);
6861 }
6862
6863 void kvm_arch_sync_events(struct kvm *kvm)
6864 {
6865 kvm_free_all_assigned_devices(kvm);
6866 kvm_free_pit(kvm);
6867 }
6868
6869 void kvm_arch_destroy_vm(struct kvm *kvm)
6870 {
6871 if (current->mm == kvm->mm) {
6872 /*
6873 * Free memory regions allocated on behalf of userspace,
6874 * unless the the memory map has changed due to process exit
6875 * or fd copying.
6876 */
6877 struct kvm_userspace_memory_region mem;
6878 memset(&mem, 0, sizeof(mem));
6879 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
6880 kvm_set_memory_region(kvm, &mem);
6881
6882 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
6883 kvm_set_memory_region(kvm, &mem);
6884
6885 mem.slot = TSS_PRIVATE_MEMSLOT;
6886 kvm_set_memory_region(kvm, &mem);
6887 }
6888 kvm_iommu_unmap_guest(kvm);
6889 kfree(kvm->arch.vpic);
6890 kfree(kvm->arch.vioapic);
6891 kvm_free_vcpus(kvm);
6892 if (kvm->arch.apic_access_page)
6893 put_page(kvm->arch.apic_access_page);
6894 if (kvm->arch.ept_identity_pagetable)
6895 put_page(kvm->arch.ept_identity_pagetable);
6896 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
6897 }
6898
6899 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6900 struct kvm_memory_slot *dont)
6901 {
6902 int i;
6903
6904 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6905 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6906 kvm_kvfree(free->arch.rmap[i]);
6907 free->arch.rmap[i] = NULL;
6908 }
6909 if (i == 0)
6910 continue;
6911
6912 if (!dont || free->arch.lpage_info[i - 1] !=
6913 dont->arch.lpage_info[i - 1]) {
6914 kvm_kvfree(free->arch.lpage_info[i - 1]);
6915 free->arch.lpage_info[i - 1] = NULL;
6916 }
6917 }
6918 }
6919
6920 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6921 {
6922 int i;
6923
6924 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6925 unsigned long ugfn;
6926 int lpages;
6927 int level = i + 1;
6928
6929 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6930 slot->base_gfn, level) + 1;
6931
6932 slot->arch.rmap[i] =
6933 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6934 if (!slot->arch.rmap[i])
6935 goto out_free;
6936 if (i == 0)
6937 continue;
6938
6939 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6940 sizeof(*slot->arch.lpage_info[i - 1]));
6941 if (!slot->arch.lpage_info[i - 1])
6942 goto out_free;
6943
6944 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6945 slot->arch.lpage_info[i - 1][0].write_count = 1;
6946 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6947 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
6948 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6949 /*
6950 * If the gfn and userspace address are not aligned wrt each
6951 * other, or if explicitly asked to, disable large page
6952 * support for this slot
6953 */
6954 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6955 !kvm_largepages_enabled()) {
6956 unsigned long j;
6957
6958 for (j = 0; j < lpages; ++j)
6959 slot->arch.lpage_info[i - 1][j].write_count = 1;
6960 }
6961 }
6962
6963 return 0;
6964
6965 out_free:
6966 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6967 kvm_kvfree(slot->arch.rmap[i]);
6968 slot->arch.rmap[i] = NULL;
6969 if (i == 0)
6970 continue;
6971
6972 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6973 slot->arch.lpage_info[i - 1] = NULL;
6974 }
6975 return -ENOMEM;
6976 }
6977
6978 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6979 struct kvm_memory_slot *memslot,
6980 struct kvm_userspace_memory_region *mem,
6981 enum kvm_mr_change change)
6982 {
6983 /*
6984 * Only private memory slots need to be mapped here since
6985 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
6986 */
6987 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
6988 unsigned long userspace_addr;
6989
6990 /*
6991 * MAP_SHARED to prevent internal slot pages from being moved
6992 * by fork()/COW.
6993 */
6994 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
6995 PROT_READ | PROT_WRITE,
6996 MAP_SHARED | MAP_ANONYMOUS, 0);
6997
6998 if (IS_ERR((void *)userspace_addr))
6999 return PTR_ERR((void *)userspace_addr);
7000
7001 memslot->userspace_addr = userspace_addr;
7002 }
7003
7004 return 0;
7005 }
7006
7007 void kvm_arch_commit_memory_region(struct kvm *kvm,
7008 struct kvm_userspace_memory_region *mem,
7009 const struct kvm_memory_slot *old,
7010 enum kvm_mr_change change)
7011 {
7012
7013 int nr_mmu_pages = 0;
7014
7015 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7016 int ret;
7017
7018 ret = vm_munmap(old->userspace_addr,
7019 old->npages * PAGE_SIZE);
7020 if (ret < 0)
7021 printk(KERN_WARNING
7022 "kvm_vm_ioctl_set_memory_region: "
7023 "failed to munmap memory\n");
7024 }
7025
7026 if (!kvm->arch.n_requested_mmu_pages)
7027 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7028
7029 if (nr_mmu_pages)
7030 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7031 /*
7032 * Write protect all pages for dirty logging.
7033 * Existing largepage mappings are destroyed here and new ones will
7034 * not be created until the end of the logging.
7035 */
7036 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7037 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7038 /*
7039 * If memory slot is created, or moved, we need to clear all
7040 * mmio sptes.
7041 */
7042 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
7043 kvm_mmu_zap_mmio_sptes(kvm);
7044 kvm_reload_remote_mmus(kvm);
7045 }
7046 }
7047
7048 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7049 {
7050 kvm_mmu_zap_all(kvm);
7051 kvm_reload_remote_mmus(kvm);
7052 }
7053
7054 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7055 struct kvm_memory_slot *slot)
7056 {
7057 kvm_arch_flush_shadow_all(kvm);
7058 }
7059
7060 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7061 {
7062 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7063 !vcpu->arch.apf.halted)
7064 || !list_empty_careful(&vcpu->async_pf.done)
7065 || kvm_apic_has_events(vcpu)
7066 || atomic_read(&vcpu->arch.nmi_queued) ||
7067 (kvm_arch_interrupt_allowed(vcpu) &&
7068 kvm_cpu_has_interrupt(vcpu));
7069 }
7070
7071 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7072 {
7073 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7074 }
7075
7076 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7077 {
7078 return kvm_x86_ops->interrupt_allowed(vcpu);
7079 }
7080
7081 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7082 {
7083 unsigned long current_rip = kvm_rip_read(vcpu) +
7084 get_segment_base(vcpu, VCPU_SREG_CS);
7085
7086 return current_rip == linear_rip;
7087 }
7088 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7089
7090 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7091 {
7092 unsigned long rflags;
7093
7094 rflags = kvm_x86_ops->get_rflags(vcpu);
7095 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7096 rflags &= ~X86_EFLAGS_TF;
7097 return rflags;
7098 }
7099 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7100
7101 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7102 {
7103 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7104 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7105 rflags |= X86_EFLAGS_TF;
7106 kvm_x86_ops->set_rflags(vcpu, rflags);
7107 kvm_make_request(KVM_REQ_EVENT, vcpu);
7108 }
7109 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7110
7111 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7112 {
7113 int r;
7114
7115 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7116 is_error_page(work->page))
7117 return;
7118
7119 r = kvm_mmu_reload(vcpu);
7120 if (unlikely(r))
7121 return;
7122
7123 if (!vcpu->arch.mmu.direct_map &&
7124 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7125 return;
7126
7127 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7128 }
7129
7130 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7131 {
7132 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7133 }
7134
7135 static inline u32 kvm_async_pf_next_probe(u32 key)
7136 {
7137 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7138 }
7139
7140 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7141 {
7142 u32 key = kvm_async_pf_hash_fn(gfn);
7143
7144 while (vcpu->arch.apf.gfns[key] != ~0)
7145 key = kvm_async_pf_next_probe(key);
7146
7147 vcpu->arch.apf.gfns[key] = gfn;
7148 }
7149
7150 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7151 {
7152 int i;
7153 u32 key = kvm_async_pf_hash_fn(gfn);
7154
7155 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7156 (vcpu->arch.apf.gfns[key] != gfn &&
7157 vcpu->arch.apf.gfns[key] != ~0); i++)
7158 key = kvm_async_pf_next_probe(key);
7159
7160 return key;
7161 }
7162
7163 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7164 {
7165 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7166 }
7167
7168 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7169 {
7170 u32 i, j, k;
7171
7172 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7173 while (true) {
7174 vcpu->arch.apf.gfns[i] = ~0;
7175 do {
7176 j = kvm_async_pf_next_probe(j);
7177 if (vcpu->arch.apf.gfns[j] == ~0)
7178 return;
7179 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7180 /*
7181 * k lies cyclically in ]i,j]
7182 * | i.k.j |
7183 * |....j i.k.| or |.k..j i...|
7184 */
7185 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7186 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7187 i = j;
7188 }
7189 }
7190
7191 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7192 {
7193
7194 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7195 sizeof(val));
7196 }
7197
7198 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7199 struct kvm_async_pf *work)
7200 {
7201 struct x86_exception fault;
7202
7203 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7204 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7205
7206 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7207 (vcpu->arch.apf.send_user_only &&
7208 kvm_x86_ops->get_cpl(vcpu) == 0))
7209 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7210 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7211 fault.vector = PF_VECTOR;
7212 fault.error_code_valid = true;
7213 fault.error_code = 0;
7214 fault.nested_page_fault = false;
7215 fault.address = work->arch.token;
7216 kvm_inject_page_fault(vcpu, &fault);
7217 }
7218 }
7219
7220 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7221 struct kvm_async_pf *work)
7222 {
7223 struct x86_exception fault;
7224
7225 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7226 if (is_error_page(work->page))
7227 work->arch.token = ~0; /* broadcast wakeup */
7228 else
7229 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7230
7231 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7232 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7233 fault.vector = PF_VECTOR;
7234 fault.error_code_valid = true;
7235 fault.error_code = 0;
7236 fault.nested_page_fault = false;
7237 fault.address = work->arch.token;
7238 kvm_inject_page_fault(vcpu, &fault);
7239 }
7240 vcpu->arch.apf.halted = false;
7241 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7242 }
7243
7244 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7245 {
7246 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7247 return true;
7248 else
7249 return !kvm_event_needs_reinjection(vcpu) &&
7250 kvm_x86_ops->interrupt_allowed(vcpu);
7251 }
7252
7253 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7254 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7255 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7256 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7257 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7258 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7259 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7260 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7261 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7262 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7263 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7264 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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