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x86: Delay skip of emulated hypercall instruction
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "pmu.h"
31 #include "hyperv.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
58
59 #include <trace/events/kvm.h>
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70
71 #define CREATE_TRACE_POINTS
72 #include "trace.h"
73
74 #define MAX_IO_MSRS 256
75 #define KVM_MAX_MCE_BANKS 32
76 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
78
79 #define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
82 /* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86 #ifdef CONFIG_X86_64
87 static
88 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
89 #else
90 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
91 #endif
92
93 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
95
96 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
98
99 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
100 static void process_nmi(struct kvm_vcpu *vcpu);
101 static void enter_smm(struct kvm_vcpu *vcpu);
102 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
103
104 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
105 EXPORT_SYMBOL_GPL(kvm_x86_ops);
106
107 static bool __read_mostly ignore_msrs = 0;
108 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
109
110 static bool __read_mostly report_ignored_msrs = true;
111 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
113 unsigned int min_timer_period_us = 500;
114 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
116 static bool __read_mostly kvmclock_periodic_sync = true;
117 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
119 bool __read_mostly kvm_has_tsc_control;
120 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
121 u32 __read_mostly kvm_max_guest_tsc_khz;
122 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
123 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125 u64 __read_mostly kvm_max_tsc_scaling_ratio;
126 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
127 u64 __read_mostly kvm_default_tsc_scaling_ratio;
128 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
129
130 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
131 static u32 __read_mostly tsc_tolerance_ppm = 250;
132 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
134 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
135 unsigned int __read_mostly lapic_timer_advance_ns = 0;
136 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
138 static bool __read_mostly vector_hashing = true;
139 module_param(vector_hashing, bool, S_IRUGO);
140
141 #define KVM_NR_SHARED_MSRS 16
142
143 struct kvm_shared_msrs_global {
144 int nr;
145 u32 msrs[KVM_NR_SHARED_MSRS];
146 };
147
148 struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
155 };
156
157 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
158 static struct kvm_shared_msrs __percpu *shared_msrs;
159
160 struct kvm_stats_debugfs_item debugfs_entries[] = {
161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
171 { "halt_exits", VCPU_STAT(halt_exits) },
172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
176 { "hypercalls", VCPU_STAT(hypercalls) },
177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
184 { "irq_injections", VCPU_STAT(irq_injections) },
185 { "nmi_injections", VCPU_STAT(nmi_injections) },
186 { "req_event", VCPU_STAT(req_event) },
187 { "l1d_flush", VCPU_STAT(l1d_flush) },
188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
189 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
192 { "mmu_flooded", VM_STAT(mmu_flooded) },
193 { "mmu_recycled", VM_STAT(mmu_recycled) },
194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
195 { "mmu_unsync", VM_STAT(mmu_unsync) },
196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
197 { "largepages", VM_STAT(lpages) },
198 { "max_mmu_page_hash_collisions",
199 VM_STAT(max_mmu_page_hash_collisions) },
200 { NULL }
201 };
202
203 u64 __read_mostly host_xcr0;
204
205 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
206
207 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
208 {
209 int i;
210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
211 vcpu->arch.apf.gfns[i] = ~0;
212 }
213
214 static void kvm_on_user_return(struct user_return_notifier *urn)
215 {
216 unsigned slot;
217 struct kvm_shared_msrs *locals
218 = container_of(urn, struct kvm_shared_msrs, urn);
219 struct kvm_shared_msr_values *values;
220 unsigned long flags;
221
222 /*
223 * Disabling irqs at this point since the following code could be
224 * interrupted and executed through kvm_arch_hardware_disable()
225 */
226 local_irq_save(flags);
227 if (locals->registered) {
228 locals->registered = false;
229 user_return_notifier_unregister(urn);
230 }
231 local_irq_restore(flags);
232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
233 values = &locals->values[slot];
234 if (values->host != values->curr) {
235 wrmsrl(shared_msrs_global.msrs[slot], values->host);
236 values->curr = values->host;
237 }
238 }
239 }
240
241 static void shared_msr_update(unsigned slot, u32 msr)
242 {
243 u64 value;
244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
246
247 /* only read, and nobody should modify it at this time,
248 * so don't need lock */
249 if (slot >= shared_msrs_global.nr) {
250 printk(KERN_ERR "kvm: invalid MSR slot!");
251 return;
252 }
253 rdmsrl_safe(msr, &value);
254 smsr->values[slot].host = value;
255 smsr->values[slot].curr = value;
256 }
257
258 void kvm_define_shared_msr(unsigned slot, u32 msr)
259 {
260 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
261 shared_msrs_global.msrs[slot] = msr;
262 if (slot >= shared_msrs_global.nr)
263 shared_msrs_global.nr = slot + 1;
264 }
265 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266
267 static void kvm_shared_msr_cpu_online(void)
268 {
269 unsigned i;
270
271 for (i = 0; i < shared_msrs_global.nr; ++i)
272 shared_msr_update(i, shared_msrs_global.msrs[i]);
273 }
274
275 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
276 {
277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
279 int err;
280
281 if (((value ^ smsr->values[slot].curr) & mask) == 0)
282 return 0;
283 smsr->values[slot].curr = value;
284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (err)
286 return 1;
287
288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
292 }
293 return 0;
294 }
295 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296
297 static void drop_user_return_notifiers(void)
298 {
299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
301
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
304 }
305
306 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307 {
308 return vcpu->arch.apic_base;
309 }
310 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311
312 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313 {
314 u64 old_state = vcpu->arch.apic_base &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 new_state = msr_info->data &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
320
321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 return 1;
323 if (!msr_info->host_initiated &&
324 ((new_state == MSR_IA32_APICBASE_ENABLE &&
325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 old_state == 0)))
328 return 1;
329
330 kvm_lapic_set_base(vcpu, msr_info->data);
331 return 0;
332 }
333 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334
335 asmlinkage __visible void kvm_spurious_fault(void)
336 {
337 /* Fault while not rebooting. We want the trace. */
338 BUG();
339 }
340 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341
342 #define EXCPT_BENIGN 0
343 #define EXCPT_CONTRIBUTORY 1
344 #define EXCPT_PF 2
345
346 static int exception_class(int vector)
347 {
348 switch (vector) {
349 case PF_VECTOR:
350 return EXCPT_PF;
351 case DE_VECTOR:
352 case TS_VECTOR:
353 case NP_VECTOR:
354 case SS_VECTOR:
355 case GP_VECTOR:
356 return EXCPT_CONTRIBUTORY;
357 default:
358 break;
359 }
360 return EXCPT_BENIGN;
361 }
362
363 #define EXCPT_FAULT 0
364 #define EXCPT_TRAP 1
365 #define EXCPT_ABORT 2
366 #define EXCPT_INTERRUPT 3
367
368 static int exception_type(int vector)
369 {
370 unsigned int mask;
371
372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
373 return EXCPT_INTERRUPT;
374
375 mask = 1 << vector;
376
377 /* #DB is trap, as instruction watchpoints are handled elsewhere */
378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
379 return EXCPT_TRAP;
380
381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
382 return EXCPT_ABORT;
383
384 /* Reserved exceptions will result in fault */
385 return EXCPT_FAULT;
386 }
387
388 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
389 unsigned nr, bool has_error, u32 error_code,
390 bool reinject)
391 {
392 u32 prev_nr;
393 int class1, class2;
394
395 kvm_make_request(KVM_REQ_EVENT, vcpu);
396
397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
398 queue:
399 if (has_error && !is_protmode(vcpu))
400 has_error = false;
401 if (reinject) {
402 /*
403 * On vmentry, vcpu->arch.exception.pending is only
404 * true if an event injection was blocked by
405 * nested_run_pending. In that case, however,
406 * vcpu_enter_guest requests an immediate exit,
407 * and the guest shouldn't proceed far enough to
408 * need reinjection.
409 */
410 WARN_ON_ONCE(vcpu->arch.exception.pending);
411 vcpu->arch.exception.injected = true;
412 } else {
413 vcpu->arch.exception.pending = true;
414 vcpu->arch.exception.injected = false;
415 }
416 vcpu->arch.exception.has_error_code = has_error;
417 vcpu->arch.exception.nr = nr;
418 vcpu->arch.exception.error_code = error_code;
419 return;
420 }
421
422 /* to check exception */
423 prev_nr = vcpu->arch.exception.nr;
424 if (prev_nr == DF_VECTOR) {
425 /* triple fault -> shutdown */
426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
427 return;
428 }
429 class1 = exception_class(prev_nr);
430 class2 = exception_class(nr);
431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
433 /*
434 * Generate double fault per SDM Table 5-5. Set
435 * exception.pending = true so that the double fault
436 * can trigger a nested vmexit.
437 */
438 vcpu->arch.exception.pending = true;
439 vcpu->arch.exception.injected = false;
440 vcpu->arch.exception.has_error_code = true;
441 vcpu->arch.exception.nr = DF_VECTOR;
442 vcpu->arch.exception.error_code = 0;
443 } else
444 /* replace previous exception with a new one in a hope
445 that instruction re-execution will regenerate lost
446 exception */
447 goto queue;
448 }
449
450 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451 {
452 kvm_multiple_exception(vcpu, nr, false, 0, false);
453 }
454 EXPORT_SYMBOL_GPL(kvm_queue_exception);
455
456 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457 {
458 kvm_multiple_exception(vcpu, nr, false, 0, true);
459 }
460 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461
462 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
463 {
464 if (err)
465 kvm_inject_gp(vcpu, 0);
466 else
467 return kvm_skip_emulated_instruction(vcpu);
468
469 return 1;
470 }
471 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
472
473 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
474 {
475 ++vcpu->stat.pf_guest;
476 vcpu->arch.exception.nested_apf =
477 is_guest_mode(vcpu) && fault->async_page_fault;
478 if (vcpu->arch.exception.nested_apf)
479 vcpu->arch.apf.nested_apf_token = fault->address;
480 else
481 vcpu->arch.cr2 = fault->address;
482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
483 }
484 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
485
486 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
487 {
488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
490 else
491 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
492
493 return fault->nested_page_fault;
494 }
495
496 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497 {
498 atomic_inc(&vcpu->arch.nmi_queued);
499 kvm_make_request(KVM_REQ_NMI, vcpu);
500 }
501 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502
503 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504 {
505 kvm_multiple_exception(vcpu, nr, true, error_code, false);
506 }
507 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508
509 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510 {
511 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512 }
513 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
514
515 /*
516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
517 * a #GP and return false.
518 */
519 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
520 {
521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 return true;
523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
524 return false;
525 }
526 EXPORT_SYMBOL_GPL(kvm_require_cpl);
527
528 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529 {
530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
531 return true;
532
533 kvm_queue_exception(vcpu, UD_VECTOR);
534 return false;
535 }
536 EXPORT_SYMBOL_GPL(kvm_require_dr);
537
538 /*
539 * This function will be used to read from the physical memory of the currently
540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
541 * can read from guest physical or from the guest's guest physical memory.
542 */
543 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
544 gfn_t ngfn, void *data, int offset, int len,
545 u32 access)
546 {
547 struct x86_exception exception;
548 gfn_t real_gfn;
549 gpa_t ngpa;
550
551 ngpa = gfn_to_gpa(ngfn);
552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
553 if (real_gfn == UNMAPPED_GVA)
554 return -EFAULT;
555
556 real_gfn = gpa_to_gfn(real_gfn);
557
558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
559 }
560 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561
562 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
563 void *data, int offset, int len, u32 access)
564 {
565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
566 data, offset, len, access);
567 }
568
569 /*
570 * Load the pae pdptrs. Return true is they are all valid.
571 */
572 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
573 {
574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
576 int i;
577 int ret;
578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
579
580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
581 offset * sizeof(u64), sizeof(pdpte),
582 PFERR_USER_MASK|PFERR_WRITE_MASK);
583 if (ret < 0) {
584 ret = 0;
585 goto out;
586 }
587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
588 if ((pdpte[i] & PT_PRESENT_MASK) &&
589 (pdpte[i] &
590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
591 ret = 0;
592 goto out;
593 }
594 }
595 ret = 1;
596
597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
598 __set_bit(VCPU_EXREG_PDPTR,
599 (unsigned long *)&vcpu->arch.regs_avail);
600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_dirty);
602 out:
603
604 return ret;
605 }
606 EXPORT_SYMBOL_GPL(load_pdptrs);
607
608 bool pdptrs_changed(struct kvm_vcpu *vcpu)
609 {
610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
611 bool changed = true;
612 int offset;
613 gfn_t gfn;
614 int r;
615
616 if (is_long_mode(vcpu) || !is_pae(vcpu))
617 return false;
618
619 if (!test_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_avail))
621 return true;
622
623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
626 PFERR_USER_MASK | PFERR_WRITE_MASK);
627 if (r < 0)
628 goto out;
629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
630 out:
631
632 return changed;
633 }
634 EXPORT_SYMBOL_GPL(pdptrs_changed);
635
636 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
637 {
638 unsigned long old_cr0 = kvm_read_cr0(vcpu);
639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
640
641 cr0 |= X86_CR0_ET;
642
643 #ifdef CONFIG_X86_64
644 if (cr0 & 0xffffffff00000000UL)
645 return 1;
646 #endif
647
648 cr0 &= ~CR0_RESERVED_BITS;
649
650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
651 return 1;
652
653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
654 return 1;
655
656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657 #ifdef CONFIG_X86_64
658 if ((vcpu->arch.efer & EFER_LME)) {
659 int cs_db, cs_l;
660
661 if (!is_pae(vcpu))
662 return 1;
663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
664 if (cs_l)
665 return 1;
666 } else
667 #endif
668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
669 kvm_read_cr3(vcpu)))
670 return 1;
671 }
672
673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
674 return 1;
675
676 kvm_x86_ops->set_cr0(vcpu, cr0);
677
678 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
679 kvm_clear_async_pf_completion_queue(vcpu);
680 kvm_async_pf_hash_reset(vcpu);
681 }
682
683 if ((cr0 ^ old_cr0) & update_bits)
684 kvm_mmu_reset_context(vcpu);
685
686 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
687 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
690
691 return 0;
692 }
693 EXPORT_SYMBOL_GPL(kvm_set_cr0);
694
695 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
696 {
697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
698 }
699 EXPORT_SYMBOL_GPL(kvm_lmsw);
700
701 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702 {
703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
704 !vcpu->guest_xcr0_loaded) {
705 /* kvm_set_xcr() also depends on this */
706 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
707 vcpu->guest_xcr0_loaded = 1;
708 }
709 }
710
711 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
712 {
713 if (vcpu->guest_xcr0_loaded) {
714 if (vcpu->arch.xcr0 != host_xcr0)
715 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
716 vcpu->guest_xcr0_loaded = 0;
717 }
718 }
719
720 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
721 {
722 u64 xcr0 = xcr;
723 u64 old_xcr0 = vcpu->arch.xcr0;
724 u64 valid_bits;
725
726 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
727 if (index != XCR_XFEATURE_ENABLED_MASK)
728 return 1;
729 if (!(xcr0 & XFEATURE_MASK_FP))
730 return 1;
731 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
732 return 1;
733
734 /*
735 * Do not allow the guest to set bits that we do not support
736 * saving. However, xcr0 bit 0 is always set, even if the
737 * emulated CPU does not support XSAVE (see fx_init).
738 */
739 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
740 if (xcr0 & ~valid_bits)
741 return 1;
742
743 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
744 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
745 return 1;
746
747 if (xcr0 & XFEATURE_MASK_AVX512) {
748 if (!(xcr0 & XFEATURE_MASK_YMM))
749 return 1;
750 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
751 return 1;
752 }
753 vcpu->arch.xcr0 = xcr0;
754
755 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
756 kvm_update_cpuid(vcpu);
757 return 0;
758 }
759
760 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
761 {
762 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
763 __kvm_set_xcr(vcpu, index, xcr)) {
764 kvm_inject_gp(vcpu, 0);
765 return 1;
766 }
767 return 0;
768 }
769 EXPORT_SYMBOL_GPL(kvm_set_xcr);
770
771 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
772 {
773 unsigned long old_cr4 = kvm_read_cr4(vcpu);
774 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
775 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
776
777 if (cr4 & CR4_RESERVED_BITS)
778 return 1;
779
780 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
781 return 1;
782
783 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
784 return 1;
785
786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
787 return 1;
788
789 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
790 return 1;
791
792 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
793 return 1;
794
795 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
796 return 1;
797
798 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
799 return 1;
800
801 if (is_long_mode(vcpu)) {
802 if (!(cr4 & X86_CR4_PAE))
803 return 1;
804 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
805 && ((cr4 ^ old_cr4) & pdptr_bits)
806 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
807 kvm_read_cr3(vcpu)))
808 return 1;
809
810 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
811 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
812 return 1;
813
814 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
815 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
816 return 1;
817 }
818
819 if (kvm_x86_ops->set_cr4(vcpu, cr4))
820 return 1;
821
822 if (((cr4 ^ old_cr4) & pdptr_bits) ||
823 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
824 kvm_mmu_reset_context(vcpu);
825
826 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
827 kvm_update_cpuid(vcpu);
828
829 return 0;
830 }
831 EXPORT_SYMBOL_GPL(kvm_set_cr4);
832
833 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
834 {
835 #ifdef CONFIG_X86_64
836 cr3 &= ~CR3_PCID_INVD;
837 #endif
838
839 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
840 kvm_mmu_sync_roots(vcpu);
841 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
842 return 0;
843 }
844
845 if (is_long_mode(vcpu) &&
846 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
847 return 1;
848 else if (is_pae(vcpu) && is_paging(vcpu) &&
849 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
850 return 1;
851
852 vcpu->arch.cr3 = cr3;
853 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
854 kvm_mmu_new_cr3(vcpu);
855 return 0;
856 }
857 EXPORT_SYMBOL_GPL(kvm_set_cr3);
858
859 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
860 {
861 if (cr8 & CR8_RESERVED_BITS)
862 return 1;
863 if (lapic_in_kernel(vcpu))
864 kvm_lapic_set_tpr(vcpu, cr8);
865 else
866 vcpu->arch.cr8 = cr8;
867 return 0;
868 }
869 EXPORT_SYMBOL_GPL(kvm_set_cr8);
870
871 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
872 {
873 if (lapic_in_kernel(vcpu))
874 return kvm_lapic_get_cr8(vcpu);
875 else
876 return vcpu->arch.cr8;
877 }
878 EXPORT_SYMBOL_GPL(kvm_get_cr8);
879
880 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
881 {
882 int i;
883
884 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
885 for (i = 0; i < KVM_NR_DB_REGS; i++)
886 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
887 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
888 }
889 }
890
891 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
892 {
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
895 }
896
897 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
898 {
899 unsigned long dr7;
900
901 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
902 dr7 = vcpu->arch.guest_debug_dr7;
903 else
904 dr7 = vcpu->arch.dr7;
905 kvm_x86_ops->set_dr7(vcpu, dr7);
906 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
907 if (dr7 & DR7_BP_EN_MASK)
908 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
909 }
910
911 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
912 {
913 u64 fixed = DR6_FIXED_1;
914
915 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
916 fixed |= DR6_RTM;
917 return fixed;
918 }
919
920 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
921 {
922 switch (dr) {
923 case 0 ... 3:
924 vcpu->arch.db[dr] = val;
925 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
926 vcpu->arch.eff_db[dr] = val;
927 break;
928 case 4:
929 /* fall through */
930 case 6:
931 if (val & 0xffffffff00000000ULL)
932 return -1; /* #GP */
933 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
934 kvm_update_dr6(vcpu);
935 break;
936 case 5:
937 /* fall through */
938 default: /* 7 */
939 if (val & 0xffffffff00000000ULL)
940 return -1; /* #GP */
941 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
942 kvm_update_dr7(vcpu);
943 break;
944 }
945
946 return 0;
947 }
948
949 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
950 {
951 if (__kvm_set_dr(vcpu, dr, val)) {
952 kvm_inject_gp(vcpu, 0);
953 return 1;
954 }
955 return 0;
956 }
957 EXPORT_SYMBOL_GPL(kvm_set_dr);
958
959 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
960 {
961 switch (dr) {
962 case 0 ... 3:
963 *val = vcpu->arch.db[dr];
964 break;
965 case 4:
966 /* fall through */
967 case 6:
968 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
969 *val = vcpu->arch.dr6;
970 else
971 *val = kvm_x86_ops->get_dr6(vcpu);
972 break;
973 case 5:
974 /* fall through */
975 default: /* 7 */
976 *val = vcpu->arch.dr7;
977 break;
978 }
979 return 0;
980 }
981 EXPORT_SYMBOL_GPL(kvm_get_dr);
982
983 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
984 {
985 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
986 u64 data;
987 int err;
988
989 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
990 if (err)
991 return err;
992 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
993 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
994 return err;
995 }
996 EXPORT_SYMBOL_GPL(kvm_rdpmc);
997
998 /*
999 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1000 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1001 *
1002 * This list is modified at module load time to reflect the
1003 * capabilities of the host cpu. This capabilities test skips MSRs that are
1004 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1005 * may depend on host virtualization features rather than host cpu features.
1006 */
1007
1008 static u32 msrs_to_save[] = {
1009 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1010 MSR_STAR,
1011 #ifdef CONFIG_X86_64
1012 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1013 #endif
1014 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1015 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1016 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
1017 };
1018
1019 static unsigned num_msrs_to_save;
1020
1021 static u32 emulated_msrs[] = {
1022 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1023 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1024 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1025 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1026 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1027 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1028 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1029 HV_X64_MSR_RESET,
1030 HV_X64_MSR_VP_INDEX,
1031 HV_X64_MSR_VP_RUNTIME,
1032 HV_X64_MSR_SCONTROL,
1033 HV_X64_MSR_STIMER0_CONFIG,
1034 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1035 MSR_KVM_PV_EOI_EN,
1036
1037 MSR_IA32_TSC_ADJUST,
1038 MSR_IA32_TSCDEADLINE,
1039 MSR_IA32_MISC_ENABLE,
1040 MSR_IA32_MCG_STATUS,
1041 MSR_IA32_MCG_CTL,
1042 MSR_IA32_MCG_EXT_CTL,
1043 MSR_IA32_SMBASE,
1044 MSR_PLATFORM_INFO,
1045 MSR_MISC_FEATURES_ENABLES,
1046 MSR_AMD64_VIRT_SPEC_CTRL,
1047 };
1048
1049 static unsigned num_emulated_msrs;
1050
1051 /*
1052 * List of msr numbers which are used to expose MSR-based features that
1053 * can be used by a hypervisor to validate requested CPU features.
1054 */
1055 static u32 msr_based_features[] = {
1056 MSR_IA32_ARCH_CAPABILITIES,
1057 };
1058
1059 static unsigned int num_msr_based_features;
1060
1061 u64 kvm_get_arch_capabilities(void)
1062 {
1063 u64 data;
1064
1065 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1066
1067 /*
1068 * If we're doing cache flushes (either "always" or "cond")
1069 * we will do one whenever the guest does a vmlaunch/vmresume.
1070 * If an outer hypervisor is doing the cache flush for us
1071 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1072 * capability to the guest too, and if EPT is disabled we're not
1073 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1074 * require a nested hypervisor to do a flush of its own.
1075 */
1076 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1077 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1078
1079 return data;
1080 }
1081 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1082
1083 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1084 {
1085 switch (msr->index) {
1086 case MSR_IA32_ARCH_CAPABILITIES:
1087 msr->data = kvm_get_arch_capabilities();
1088 break;
1089 default:
1090 if (kvm_x86_ops->get_msr_feature(msr))
1091 return 1;
1092 }
1093 return 0;
1094 }
1095
1096 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1097 {
1098 struct kvm_msr_entry msr;
1099 int r;
1100
1101 msr.index = index;
1102 r = kvm_get_msr_feature(&msr);
1103 if (r)
1104 return r;
1105
1106 *data = msr.data;
1107
1108 return 0;
1109 }
1110
1111 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1112 {
1113 if (efer & efer_reserved_bits)
1114 return false;
1115
1116 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1117 return false;
1118
1119 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1120 return false;
1121
1122 return true;
1123 }
1124 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1125
1126 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1127 {
1128 u64 old_efer = vcpu->arch.efer;
1129
1130 if (!kvm_valid_efer(vcpu, efer))
1131 return 1;
1132
1133 if (is_paging(vcpu)
1134 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1135 return 1;
1136
1137 efer &= ~EFER_LMA;
1138 efer |= vcpu->arch.efer & EFER_LMA;
1139
1140 kvm_x86_ops->set_efer(vcpu, efer);
1141
1142 /* Update reserved bits */
1143 if ((efer ^ old_efer) & EFER_NX)
1144 kvm_mmu_reset_context(vcpu);
1145
1146 return 0;
1147 }
1148
1149 void kvm_enable_efer_bits(u64 mask)
1150 {
1151 efer_reserved_bits &= ~mask;
1152 }
1153 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1154
1155 /*
1156 * Writes msr value into into the appropriate "register".
1157 * Returns 0 on success, non-0 otherwise.
1158 * Assumes vcpu_load() was already called.
1159 */
1160 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1161 {
1162 switch (msr->index) {
1163 case MSR_FS_BASE:
1164 case MSR_GS_BASE:
1165 case MSR_KERNEL_GS_BASE:
1166 case MSR_CSTAR:
1167 case MSR_LSTAR:
1168 if (is_noncanonical_address(msr->data, vcpu))
1169 return 1;
1170 break;
1171 case MSR_IA32_SYSENTER_EIP:
1172 case MSR_IA32_SYSENTER_ESP:
1173 /*
1174 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1175 * non-canonical address is written on Intel but not on
1176 * AMD (which ignores the top 32-bits, because it does
1177 * not implement 64-bit SYSENTER).
1178 *
1179 * 64-bit code should hence be able to write a non-canonical
1180 * value on AMD. Making the address canonical ensures that
1181 * vmentry does not fail on Intel after writing a non-canonical
1182 * value, and that something deterministic happens if the guest
1183 * invokes 64-bit SYSENTER.
1184 */
1185 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1186 }
1187 return kvm_x86_ops->set_msr(vcpu, msr);
1188 }
1189 EXPORT_SYMBOL_GPL(kvm_set_msr);
1190
1191 /*
1192 * Adapt set_msr() to msr_io()'s calling convention
1193 */
1194 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1195 {
1196 struct msr_data msr;
1197 int r;
1198
1199 msr.index = index;
1200 msr.host_initiated = true;
1201 r = kvm_get_msr(vcpu, &msr);
1202 if (r)
1203 return r;
1204
1205 *data = msr.data;
1206 return 0;
1207 }
1208
1209 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1210 {
1211 struct msr_data msr;
1212
1213 msr.data = *data;
1214 msr.index = index;
1215 msr.host_initiated = true;
1216 return kvm_set_msr(vcpu, &msr);
1217 }
1218
1219 #ifdef CONFIG_X86_64
1220 struct pvclock_gtod_data {
1221 seqcount_t seq;
1222
1223 struct { /* extract of a clocksource struct */
1224 int vclock_mode;
1225 u64 cycle_last;
1226 u64 mask;
1227 u32 mult;
1228 u32 shift;
1229 } clock;
1230
1231 u64 boot_ns;
1232 u64 nsec_base;
1233 u64 wall_time_sec;
1234 };
1235
1236 static struct pvclock_gtod_data pvclock_gtod_data;
1237
1238 static void update_pvclock_gtod(struct timekeeper *tk)
1239 {
1240 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1241 u64 boot_ns;
1242
1243 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1244
1245 write_seqcount_begin(&vdata->seq);
1246
1247 /* copy pvclock gtod data */
1248 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1249 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1250 vdata->clock.mask = tk->tkr_mono.mask;
1251 vdata->clock.mult = tk->tkr_mono.mult;
1252 vdata->clock.shift = tk->tkr_mono.shift;
1253
1254 vdata->boot_ns = boot_ns;
1255 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1256
1257 vdata->wall_time_sec = tk->xtime_sec;
1258
1259 write_seqcount_end(&vdata->seq);
1260 }
1261 #endif
1262
1263 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1264 {
1265 /*
1266 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1267 * vcpu_enter_guest. This function is only called from
1268 * the physical CPU that is running vcpu.
1269 */
1270 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1271 }
1272
1273 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1274 {
1275 int version;
1276 int r;
1277 struct pvclock_wall_clock wc;
1278 struct timespec64 boot;
1279
1280 if (!wall_clock)
1281 return;
1282
1283 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1284 if (r)
1285 return;
1286
1287 if (version & 1)
1288 ++version; /* first time write, random junk */
1289
1290 ++version;
1291
1292 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1293 return;
1294
1295 /*
1296 * The guest calculates current wall clock time by adding
1297 * system time (updated by kvm_guest_time_update below) to the
1298 * wall clock specified here. guest system time equals host
1299 * system time for us, thus we must fill in host boot time here.
1300 */
1301 getboottime64(&boot);
1302
1303 if (kvm->arch.kvmclock_offset) {
1304 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1305 boot = timespec64_sub(boot, ts);
1306 }
1307 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1308 wc.nsec = boot.tv_nsec;
1309 wc.version = version;
1310
1311 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1312
1313 version++;
1314 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1315 }
1316
1317 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1318 {
1319 do_shl32_div32(dividend, divisor);
1320 return dividend;
1321 }
1322
1323 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1324 s8 *pshift, u32 *pmultiplier)
1325 {
1326 uint64_t scaled64;
1327 int32_t shift = 0;
1328 uint64_t tps64;
1329 uint32_t tps32;
1330
1331 tps64 = base_hz;
1332 scaled64 = scaled_hz;
1333 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1334 tps64 >>= 1;
1335 shift--;
1336 }
1337
1338 tps32 = (uint32_t)tps64;
1339 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1340 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1341 scaled64 >>= 1;
1342 else
1343 tps32 <<= 1;
1344 shift++;
1345 }
1346
1347 *pshift = shift;
1348 *pmultiplier = div_frac(scaled64, tps32);
1349
1350 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1351 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1352 }
1353
1354 #ifdef CONFIG_X86_64
1355 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1356 #endif
1357
1358 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1359 static unsigned long max_tsc_khz;
1360
1361 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1362 {
1363 u64 v = (u64)khz * (1000000 + ppm);
1364 do_div(v, 1000000);
1365 return v;
1366 }
1367
1368 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1369 {
1370 u64 ratio;
1371
1372 /* Guest TSC same frequency as host TSC? */
1373 if (!scale) {
1374 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1375 return 0;
1376 }
1377
1378 /* TSC scaling supported? */
1379 if (!kvm_has_tsc_control) {
1380 if (user_tsc_khz > tsc_khz) {
1381 vcpu->arch.tsc_catchup = 1;
1382 vcpu->arch.tsc_always_catchup = 1;
1383 return 0;
1384 } else {
1385 WARN(1, "user requested TSC rate below hardware speed\n");
1386 return -1;
1387 }
1388 }
1389
1390 /* TSC scaling required - calculate ratio */
1391 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1392 user_tsc_khz, tsc_khz);
1393
1394 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1395 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1396 user_tsc_khz);
1397 return -1;
1398 }
1399
1400 vcpu->arch.tsc_scaling_ratio = ratio;
1401 return 0;
1402 }
1403
1404 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1405 {
1406 u32 thresh_lo, thresh_hi;
1407 int use_scaling = 0;
1408
1409 /* tsc_khz can be zero if TSC calibration fails */
1410 if (user_tsc_khz == 0) {
1411 /* set tsc_scaling_ratio to a safe value */
1412 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1413 return -1;
1414 }
1415
1416 /* Compute a scale to convert nanoseconds in TSC cycles */
1417 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1418 &vcpu->arch.virtual_tsc_shift,
1419 &vcpu->arch.virtual_tsc_mult);
1420 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1421
1422 /*
1423 * Compute the variation in TSC rate which is acceptable
1424 * within the range of tolerance and decide if the
1425 * rate being applied is within that bounds of the hardware
1426 * rate. If so, no scaling or compensation need be done.
1427 */
1428 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1429 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1430 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1431 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1432 use_scaling = 1;
1433 }
1434 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1435 }
1436
1437 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1438 {
1439 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1440 vcpu->arch.virtual_tsc_mult,
1441 vcpu->arch.virtual_tsc_shift);
1442 tsc += vcpu->arch.this_tsc_write;
1443 return tsc;
1444 }
1445
1446 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1447 {
1448 #ifdef CONFIG_X86_64
1449 bool vcpus_matched;
1450 struct kvm_arch *ka = &vcpu->kvm->arch;
1451 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1452
1453 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1454 atomic_read(&vcpu->kvm->online_vcpus));
1455
1456 /*
1457 * Once the masterclock is enabled, always perform request in
1458 * order to update it.
1459 *
1460 * In order to enable masterclock, the host clocksource must be TSC
1461 * and the vcpus need to have matched TSCs. When that happens,
1462 * perform request to enable masterclock.
1463 */
1464 if (ka->use_master_clock ||
1465 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1466 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1467
1468 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1469 atomic_read(&vcpu->kvm->online_vcpus),
1470 ka->use_master_clock, gtod->clock.vclock_mode);
1471 #endif
1472 }
1473
1474 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1475 {
1476 u64 curr_offset = vcpu->arch.tsc_offset;
1477 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1478 }
1479
1480 /*
1481 * Multiply tsc by a fixed point number represented by ratio.
1482 *
1483 * The most significant 64-N bits (mult) of ratio represent the
1484 * integral part of the fixed point number; the remaining N bits
1485 * (frac) represent the fractional part, ie. ratio represents a fixed
1486 * point number (mult + frac * 2^(-N)).
1487 *
1488 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1489 */
1490 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1491 {
1492 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1493 }
1494
1495 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1496 {
1497 u64 _tsc = tsc;
1498 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1499
1500 if (ratio != kvm_default_tsc_scaling_ratio)
1501 _tsc = __scale_tsc(ratio, tsc);
1502
1503 return _tsc;
1504 }
1505 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1506
1507 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1508 {
1509 u64 tsc;
1510
1511 tsc = kvm_scale_tsc(vcpu, rdtsc());
1512
1513 return target_tsc - tsc;
1514 }
1515
1516 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1517 {
1518 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1519 }
1520 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1521
1522 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1523 {
1524 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1525 vcpu->arch.tsc_offset = offset;
1526 }
1527
1528 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1529 {
1530 struct kvm *kvm = vcpu->kvm;
1531 u64 offset, ns, elapsed;
1532 unsigned long flags;
1533 bool matched;
1534 bool already_matched;
1535 u64 data = msr->data;
1536 bool synchronizing = false;
1537
1538 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1539 offset = kvm_compute_tsc_offset(vcpu, data);
1540 ns = ktime_get_boot_ns();
1541 elapsed = ns - kvm->arch.last_tsc_nsec;
1542
1543 if (vcpu->arch.virtual_tsc_khz) {
1544 if (data == 0 && msr->host_initiated) {
1545 /*
1546 * detection of vcpu initialization -- need to sync
1547 * with other vCPUs. This particularly helps to keep
1548 * kvm_clock stable after CPU hotplug
1549 */
1550 synchronizing = true;
1551 } else {
1552 u64 tsc_exp = kvm->arch.last_tsc_write +
1553 nsec_to_cycles(vcpu, elapsed);
1554 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1555 /*
1556 * Special case: TSC write with a small delta (1 second)
1557 * of virtual cycle time against real time is
1558 * interpreted as an attempt to synchronize the CPU.
1559 */
1560 synchronizing = data < tsc_exp + tsc_hz &&
1561 data + tsc_hz > tsc_exp;
1562 }
1563 }
1564
1565 /*
1566 * For a reliable TSC, we can match TSC offsets, and for an unstable
1567 * TSC, we add elapsed time in this computation. We could let the
1568 * compensation code attempt to catch up if we fall behind, but
1569 * it's better to try to match offsets from the beginning.
1570 */
1571 if (synchronizing &&
1572 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1573 if (!check_tsc_unstable()) {
1574 offset = kvm->arch.cur_tsc_offset;
1575 pr_debug("kvm: matched tsc offset for %llu\n", data);
1576 } else {
1577 u64 delta = nsec_to_cycles(vcpu, elapsed);
1578 data += delta;
1579 offset = kvm_compute_tsc_offset(vcpu, data);
1580 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1581 }
1582 matched = true;
1583 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1584 } else {
1585 /*
1586 * We split periods of matched TSC writes into generations.
1587 * For each generation, we track the original measured
1588 * nanosecond time, offset, and write, so if TSCs are in
1589 * sync, we can match exact offset, and if not, we can match
1590 * exact software computation in compute_guest_tsc()
1591 *
1592 * These values are tracked in kvm->arch.cur_xxx variables.
1593 */
1594 kvm->arch.cur_tsc_generation++;
1595 kvm->arch.cur_tsc_nsec = ns;
1596 kvm->arch.cur_tsc_write = data;
1597 kvm->arch.cur_tsc_offset = offset;
1598 matched = false;
1599 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1600 kvm->arch.cur_tsc_generation, data);
1601 }
1602
1603 /*
1604 * We also track th most recent recorded KHZ, write and time to
1605 * allow the matching interval to be extended at each write.
1606 */
1607 kvm->arch.last_tsc_nsec = ns;
1608 kvm->arch.last_tsc_write = data;
1609 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1610
1611 vcpu->arch.last_guest_tsc = data;
1612
1613 /* Keep track of which generation this VCPU has synchronized to */
1614 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1615 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1616 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1617
1618 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1619 update_ia32_tsc_adjust_msr(vcpu, offset);
1620
1621 kvm_vcpu_write_tsc_offset(vcpu, offset);
1622 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1623
1624 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1625 if (!matched) {
1626 kvm->arch.nr_vcpus_matched_tsc = 0;
1627 } else if (!already_matched) {
1628 kvm->arch.nr_vcpus_matched_tsc++;
1629 }
1630
1631 kvm_track_tsc_matching(vcpu);
1632 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1633 }
1634
1635 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1636
1637 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1638 s64 adjustment)
1639 {
1640 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1641 }
1642
1643 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1644 {
1645 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1646 WARN_ON(adjustment < 0);
1647 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1648 adjust_tsc_offset_guest(vcpu, adjustment);
1649 }
1650
1651 #ifdef CONFIG_X86_64
1652
1653 static u64 read_tsc(void)
1654 {
1655 u64 ret = (u64)rdtsc_ordered();
1656 u64 last = pvclock_gtod_data.clock.cycle_last;
1657
1658 if (likely(ret >= last))
1659 return ret;
1660
1661 /*
1662 * GCC likes to generate cmov here, but this branch is extremely
1663 * predictable (it's just a function of time and the likely is
1664 * very likely) and there's a data dependence, so force GCC
1665 * to generate a branch instead. I don't barrier() because
1666 * we don't actually need a barrier, and if this function
1667 * ever gets inlined it will generate worse code.
1668 */
1669 asm volatile ("");
1670 return last;
1671 }
1672
1673 static inline u64 vgettsc(u64 *cycle_now)
1674 {
1675 long v;
1676 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1677
1678 *cycle_now = read_tsc();
1679
1680 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1681 return v * gtod->clock.mult;
1682 }
1683
1684 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1685 {
1686 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1687 unsigned long seq;
1688 int mode;
1689 u64 ns;
1690
1691 do {
1692 seq = read_seqcount_begin(&gtod->seq);
1693 mode = gtod->clock.vclock_mode;
1694 ns = gtod->nsec_base;
1695 ns += vgettsc(cycle_now);
1696 ns >>= gtod->clock.shift;
1697 ns += gtod->boot_ns;
1698 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1699 *t = ns;
1700
1701 return mode;
1702 }
1703
1704 static int do_realtime(struct timespec *ts, u64 *cycle_now)
1705 {
1706 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1707 unsigned long seq;
1708 int mode;
1709 u64 ns;
1710
1711 do {
1712 seq = read_seqcount_begin(&gtod->seq);
1713 mode = gtod->clock.vclock_mode;
1714 ts->tv_sec = gtod->wall_time_sec;
1715 ns = gtod->nsec_base;
1716 ns += vgettsc(cycle_now);
1717 ns >>= gtod->clock.shift;
1718 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1719
1720 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1721 ts->tv_nsec = ns;
1722
1723 return mode;
1724 }
1725
1726 /* returns true if host is using tsc clocksource */
1727 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1728 {
1729 /* checked again under seqlock below */
1730 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1731 return false;
1732
1733 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1734 }
1735
1736 /* returns true if host is using tsc clocksource */
1737 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1738 u64 *cycle_now)
1739 {
1740 /* checked again under seqlock below */
1741 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1742 return false;
1743
1744 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1745 }
1746 #endif
1747
1748 /*
1749 *
1750 * Assuming a stable TSC across physical CPUS, and a stable TSC
1751 * across virtual CPUs, the following condition is possible.
1752 * Each numbered line represents an event visible to both
1753 * CPUs at the next numbered event.
1754 *
1755 * "timespecX" represents host monotonic time. "tscX" represents
1756 * RDTSC value.
1757 *
1758 * VCPU0 on CPU0 | VCPU1 on CPU1
1759 *
1760 * 1. read timespec0,tsc0
1761 * 2. | timespec1 = timespec0 + N
1762 * | tsc1 = tsc0 + M
1763 * 3. transition to guest | transition to guest
1764 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1765 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1766 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1767 *
1768 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1769 *
1770 * - ret0 < ret1
1771 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1772 * ...
1773 * - 0 < N - M => M < N
1774 *
1775 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1776 * always the case (the difference between two distinct xtime instances
1777 * might be smaller then the difference between corresponding TSC reads,
1778 * when updating guest vcpus pvclock areas).
1779 *
1780 * To avoid that problem, do not allow visibility of distinct
1781 * system_timestamp/tsc_timestamp values simultaneously: use a master
1782 * copy of host monotonic time values. Update that master copy
1783 * in lockstep.
1784 *
1785 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1786 *
1787 */
1788
1789 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1790 {
1791 #ifdef CONFIG_X86_64
1792 struct kvm_arch *ka = &kvm->arch;
1793 int vclock_mode;
1794 bool host_tsc_clocksource, vcpus_matched;
1795
1796 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1797 atomic_read(&kvm->online_vcpus));
1798
1799 /*
1800 * If the host uses TSC clock, then passthrough TSC as stable
1801 * to the guest.
1802 */
1803 host_tsc_clocksource = kvm_get_time_and_clockread(
1804 &ka->master_kernel_ns,
1805 &ka->master_cycle_now);
1806
1807 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1808 && !ka->backwards_tsc_observed
1809 && !ka->boot_vcpu_runs_old_kvmclock;
1810
1811 if (ka->use_master_clock)
1812 atomic_set(&kvm_guest_has_master_clock, 1);
1813
1814 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1815 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1816 vcpus_matched);
1817 #endif
1818 }
1819
1820 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1821 {
1822 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1823 }
1824
1825 static void kvm_gen_update_masterclock(struct kvm *kvm)
1826 {
1827 #ifdef CONFIG_X86_64
1828 int i;
1829 struct kvm_vcpu *vcpu;
1830 struct kvm_arch *ka = &kvm->arch;
1831
1832 spin_lock(&ka->pvclock_gtod_sync_lock);
1833 kvm_make_mclock_inprogress_request(kvm);
1834 /* no guest entries from this point */
1835 pvclock_update_vm_gtod_copy(kvm);
1836
1837 kvm_for_each_vcpu(i, vcpu, kvm)
1838 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1839
1840 /* guest entries allowed */
1841 kvm_for_each_vcpu(i, vcpu, kvm)
1842 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1843
1844 spin_unlock(&ka->pvclock_gtod_sync_lock);
1845 #endif
1846 }
1847
1848 u64 get_kvmclock_ns(struct kvm *kvm)
1849 {
1850 struct kvm_arch *ka = &kvm->arch;
1851 struct pvclock_vcpu_time_info hv_clock;
1852 u64 ret;
1853
1854 spin_lock(&ka->pvclock_gtod_sync_lock);
1855 if (!ka->use_master_clock) {
1856 spin_unlock(&ka->pvclock_gtod_sync_lock);
1857 return ktime_get_boot_ns() + ka->kvmclock_offset;
1858 }
1859
1860 hv_clock.tsc_timestamp = ka->master_cycle_now;
1861 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1862 spin_unlock(&ka->pvclock_gtod_sync_lock);
1863
1864 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1865 get_cpu();
1866
1867 if (__this_cpu_read(cpu_tsc_khz)) {
1868 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1869 &hv_clock.tsc_shift,
1870 &hv_clock.tsc_to_system_mul);
1871 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1872 } else
1873 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
1874
1875 put_cpu();
1876
1877 return ret;
1878 }
1879
1880 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1881 {
1882 struct kvm_vcpu_arch *vcpu = &v->arch;
1883 struct pvclock_vcpu_time_info guest_hv_clock;
1884
1885 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1886 &guest_hv_clock, sizeof(guest_hv_clock))))
1887 return;
1888
1889 /* This VCPU is paused, but it's legal for a guest to read another
1890 * VCPU's kvmclock, so we really have to follow the specification where
1891 * it says that version is odd if data is being modified, and even after
1892 * it is consistent.
1893 *
1894 * Version field updates must be kept separate. This is because
1895 * kvm_write_guest_cached might use a "rep movs" instruction, and
1896 * writes within a string instruction are weakly ordered. So there
1897 * are three writes overall.
1898 *
1899 * As a small optimization, only write the version field in the first
1900 * and third write. The vcpu->pv_time cache is still valid, because the
1901 * version field is the first in the struct.
1902 */
1903 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1904
1905 if (guest_hv_clock.version & 1)
1906 ++guest_hv_clock.version; /* first time write, random junk */
1907
1908 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1909 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1910 &vcpu->hv_clock,
1911 sizeof(vcpu->hv_clock.version));
1912
1913 smp_wmb();
1914
1915 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1916 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1917
1918 if (vcpu->pvclock_set_guest_stopped_request) {
1919 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1920 vcpu->pvclock_set_guest_stopped_request = false;
1921 }
1922
1923 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1924
1925 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1926 &vcpu->hv_clock,
1927 sizeof(vcpu->hv_clock));
1928
1929 smp_wmb();
1930
1931 vcpu->hv_clock.version++;
1932 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1933 &vcpu->hv_clock,
1934 sizeof(vcpu->hv_clock.version));
1935 }
1936
1937 static int kvm_guest_time_update(struct kvm_vcpu *v)
1938 {
1939 unsigned long flags, tgt_tsc_khz;
1940 struct kvm_vcpu_arch *vcpu = &v->arch;
1941 struct kvm_arch *ka = &v->kvm->arch;
1942 s64 kernel_ns;
1943 u64 tsc_timestamp, host_tsc;
1944 u8 pvclock_flags;
1945 bool use_master_clock;
1946
1947 kernel_ns = 0;
1948 host_tsc = 0;
1949
1950 /*
1951 * If the host uses TSC clock, then passthrough TSC as stable
1952 * to the guest.
1953 */
1954 spin_lock(&ka->pvclock_gtod_sync_lock);
1955 use_master_clock = ka->use_master_clock;
1956 if (use_master_clock) {
1957 host_tsc = ka->master_cycle_now;
1958 kernel_ns = ka->master_kernel_ns;
1959 }
1960 spin_unlock(&ka->pvclock_gtod_sync_lock);
1961
1962 /* Keep irq disabled to prevent changes to the clock */
1963 local_irq_save(flags);
1964 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1965 if (unlikely(tgt_tsc_khz == 0)) {
1966 local_irq_restore(flags);
1967 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1968 return 1;
1969 }
1970 if (!use_master_clock) {
1971 host_tsc = rdtsc();
1972 kernel_ns = ktime_get_boot_ns();
1973 }
1974
1975 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1976
1977 /*
1978 * We may have to catch up the TSC to match elapsed wall clock
1979 * time for two reasons, even if kvmclock is used.
1980 * 1) CPU could have been running below the maximum TSC rate
1981 * 2) Broken TSC compensation resets the base at each VCPU
1982 * entry to avoid unknown leaps of TSC even when running
1983 * again on the same CPU. This may cause apparent elapsed
1984 * time to disappear, and the guest to stand still or run
1985 * very slowly.
1986 */
1987 if (vcpu->tsc_catchup) {
1988 u64 tsc = compute_guest_tsc(v, kernel_ns);
1989 if (tsc > tsc_timestamp) {
1990 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1991 tsc_timestamp = tsc;
1992 }
1993 }
1994
1995 local_irq_restore(flags);
1996
1997 /* With all the info we got, fill in the values */
1998
1999 if (kvm_has_tsc_control)
2000 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2001
2002 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2003 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2004 &vcpu->hv_clock.tsc_shift,
2005 &vcpu->hv_clock.tsc_to_system_mul);
2006 vcpu->hw_tsc_khz = tgt_tsc_khz;
2007 }
2008
2009 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2010 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2011 vcpu->last_guest_tsc = tsc_timestamp;
2012
2013 /* If the host uses TSC clocksource, then it is stable */
2014 pvclock_flags = 0;
2015 if (use_master_clock)
2016 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2017
2018 vcpu->hv_clock.flags = pvclock_flags;
2019
2020 if (vcpu->pv_time_enabled)
2021 kvm_setup_pvclock_page(v);
2022 if (v == kvm_get_vcpu(v->kvm, 0))
2023 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2024 return 0;
2025 }
2026
2027 /*
2028 * kvmclock updates which are isolated to a given vcpu, such as
2029 * vcpu->cpu migration, should not allow system_timestamp from
2030 * the rest of the vcpus to remain static. Otherwise ntp frequency
2031 * correction applies to one vcpu's system_timestamp but not
2032 * the others.
2033 *
2034 * So in those cases, request a kvmclock update for all vcpus.
2035 * We need to rate-limit these requests though, as they can
2036 * considerably slow guests that have a large number of vcpus.
2037 * The time for a remote vcpu to update its kvmclock is bound
2038 * by the delay we use to rate-limit the updates.
2039 */
2040
2041 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2042
2043 static void kvmclock_update_fn(struct work_struct *work)
2044 {
2045 int i;
2046 struct delayed_work *dwork = to_delayed_work(work);
2047 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2048 kvmclock_update_work);
2049 struct kvm *kvm = container_of(ka, struct kvm, arch);
2050 struct kvm_vcpu *vcpu;
2051
2052 kvm_for_each_vcpu(i, vcpu, kvm) {
2053 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2054 kvm_vcpu_kick(vcpu);
2055 }
2056 }
2057
2058 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2059 {
2060 struct kvm *kvm = v->kvm;
2061
2062 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2063 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2064 KVMCLOCK_UPDATE_DELAY);
2065 }
2066
2067 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2068
2069 static void kvmclock_sync_fn(struct work_struct *work)
2070 {
2071 struct delayed_work *dwork = to_delayed_work(work);
2072 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2073 kvmclock_sync_work);
2074 struct kvm *kvm = container_of(ka, struct kvm, arch);
2075
2076 if (!kvmclock_periodic_sync)
2077 return;
2078
2079 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2080 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2081 KVMCLOCK_SYNC_PERIOD);
2082 }
2083
2084 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2085 {
2086 u64 mcg_cap = vcpu->arch.mcg_cap;
2087 unsigned bank_num = mcg_cap & 0xff;
2088 u32 msr = msr_info->index;
2089 u64 data = msr_info->data;
2090
2091 switch (msr) {
2092 case MSR_IA32_MCG_STATUS:
2093 vcpu->arch.mcg_status = data;
2094 break;
2095 case MSR_IA32_MCG_CTL:
2096 if (!(mcg_cap & MCG_CTL_P))
2097 return 1;
2098 if (data != 0 && data != ~(u64)0)
2099 return -1;
2100 vcpu->arch.mcg_ctl = data;
2101 break;
2102 default:
2103 if (msr >= MSR_IA32_MC0_CTL &&
2104 msr < MSR_IA32_MCx_CTL(bank_num)) {
2105 u32 offset = msr - MSR_IA32_MC0_CTL;
2106 /* only 0 or all 1s can be written to IA32_MCi_CTL
2107 * some Linux kernels though clear bit 10 in bank 4 to
2108 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2109 * this to avoid an uncatched #GP in the guest
2110 */
2111 if ((offset & 0x3) == 0 &&
2112 data != 0 && (data | (1 << 10)) != ~(u64)0)
2113 return -1;
2114 if (!msr_info->host_initiated &&
2115 (offset & 0x3) == 1 && data != 0)
2116 return -1;
2117 vcpu->arch.mce_banks[offset] = data;
2118 break;
2119 }
2120 return 1;
2121 }
2122 return 0;
2123 }
2124
2125 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2126 {
2127 struct kvm *kvm = vcpu->kvm;
2128 int lm = is_long_mode(vcpu);
2129 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2130 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2131 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2132 : kvm->arch.xen_hvm_config.blob_size_32;
2133 u32 page_num = data & ~PAGE_MASK;
2134 u64 page_addr = data & PAGE_MASK;
2135 u8 *page;
2136 int r;
2137
2138 r = -E2BIG;
2139 if (page_num >= blob_size)
2140 goto out;
2141 r = -ENOMEM;
2142 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2143 if (IS_ERR(page)) {
2144 r = PTR_ERR(page);
2145 goto out;
2146 }
2147 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2148 goto out_free;
2149 r = 0;
2150 out_free:
2151 kfree(page);
2152 out:
2153 return r;
2154 }
2155
2156 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2157 {
2158 gpa_t gpa = data & ~0x3f;
2159
2160 /* Bits 3:5 are reserved, Should be zero */
2161 if (data & 0x38)
2162 return 1;
2163
2164 vcpu->arch.apf.msr_val = data;
2165
2166 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2167 kvm_clear_async_pf_completion_queue(vcpu);
2168 kvm_async_pf_hash_reset(vcpu);
2169 return 0;
2170 }
2171
2172 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2173 sizeof(u32)))
2174 return 1;
2175
2176 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2177 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2178 kvm_async_pf_wakeup_all(vcpu);
2179 return 0;
2180 }
2181
2182 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2183 {
2184 vcpu->arch.pv_time_enabled = false;
2185 }
2186
2187 static void record_steal_time(struct kvm_vcpu *vcpu)
2188 {
2189 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2190 return;
2191
2192 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2193 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2194 return;
2195
2196 vcpu->arch.st.steal.preempted = 0;
2197
2198 if (vcpu->arch.st.steal.version & 1)
2199 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2200
2201 vcpu->arch.st.steal.version += 1;
2202
2203 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2204 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2205
2206 smp_wmb();
2207
2208 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2209 vcpu->arch.st.last_steal;
2210 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2211
2212 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2213 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2214
2215 smp_wmb();
2216
2217 vcpu->arch.st.steal.version += 1;
2218
2219 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2220 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2221 }
2222
2223 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2224 {
2225 bool pr = false;
2226 u32 msr = msr_info->index;
2227 u64 data = msr_info->data;
2228
2229 switch (msr) {
2230 case MSR_AMD64_NB_CFG:
2231 case MSR_IA32_UCODE_REV:
2232 case MSR_IA32_UCODE_WRITE:
2233 case MSR_VM_HSAVE_PA:
2234 case MSR_AMD64_PATCH_LOADER:
2235 case MSR_AMD64_BU_CFG2:
2236 case MSR_AMD64_DC_CFG:
2237 break;
2238
2239 case MSR_EFER:
2240 return set_efer(vcpu, data);
2241 case MSR_K7_HWCR:
2242 data &= ~(u64)0x40; /* ignore flush filter disable */
2243 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2244 data &= ~(u64)0x8; /* ignore TLB cache disable */
2245 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2246 if (data != 0) {
2247 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2248 data);
2249 return 1;
2250 }
2251 break;
2252 case MSR_FAM10H_MMIO_CONF_BASE:
2253 if (data != 0) {
2254 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2255 "0x%llx\n", data);
2256 return 1;
2257 }
2258 break;
2259 case MSR_IA32_DEBUGCTLMSR:
2260 if (!data) {
2261 /* We support the non-activated case already */
2262 break;
2263 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2264 /* Values other than LBR and BTF are vendor-specific,
2265 thus reserved and should throw a #GP */
2266 return 1;
2267 }
2268 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2269 __func__, data);
2270 break;
2271 case 0x200 ... 0x2ff:
2272 return kvm_mtrr_set_msr(vcpu, msr, data);
2273 case MSR_IA32_APICBASE:
2274 return kvm_set_apic_base(vcpu, msr_info);
2275 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2276 return kvm_x2apic_msr_write(vcpu, msr, data);
2277 case MSR_IA32_TSCDEADLINE:
2278 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2279 break;
2280 case MSR_IA32_TSC_ADJUST:
2281 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2282 if (!msr_info->host_initiated) {
2283 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2284 adjust_tsc_offset_guest(vcpu, adj);
2285 }
2286 vcpu->arch.ia32_tsc_adjust_msr = data;
2287 }
2288 break;
2289 case MSR_IA32_MISC_ENABLE:
2290 vcpu->arch.ia32_misc_enable_msr = data;
2291 break;
2292 case MSR_IA32_SMBASE:
2293 if (!msr_info->host_initiated)
2294 return 1;
2295 vcpu->arch.smbase = data;
2296 break;
2297 case MSR_KVM_WALL_CLOCK_NEW:
2298 case MSR_KVM_WALL_CLOCK:
2299 vcpu->kvm->arch.wall_clock = data;
2300 kvm_write_wall_clock(vcpu->kvm, data);
2301 break;
2302 case MSR_KVM_SYSTEM_TIME_NEW:
2303 case MSR_KVM_SYSTEM_TIME: {
2304 struct kvm_arch *ka = &vcpu->kvm->arch;
2305
2306 kvmclock_reset(vcpu);
2307
2308 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2309 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2310
2311 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2312 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2313
2314 ka->boot_vcpu_runs_old_kvmclock = tmp;
2315 }
2316
2317 vcpu->arch.time = data;
2318 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2319
2320 /* we verify if the enable bit is set... */
2321 if (!(data & 1))
2322 break;
2323
2324 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2325 &vcpu->arch.pv_time, data & ~1ULL,
2326 sizeof(struct pvclock_vcpu_time_info)))
2327 vcpu->arch.pv_time_enabled = false;
2328 else
2329 vcpu->arch.pv_time_enabled = true;
2330
2331 break;
2332 }
2333 case MSR_KVM_ASYNC_PF_EN:
2334 if (kvm_pv_enable_async_pf(vcpu, data))
2335 return 1;
2336 break;
2337 case MSR_KVM_STEAL_TIME:
2338
2339 if (unlikely(!sched_info_on()))
2340 return 1;
2341
2342 if (data & KVM_STEAL_RESERVED_MASK)
2343 return 1;
2344
2345 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2346 data & KVM_STEAL_VALID_BITS,
2347 sizeof(struct kvm_steal_time)))
2348 return 1;
2349
2350 vcpu->arch.st.msr_val = data;
2351
2352 if (!(data & KVM_MSR_ENABLED))
2353 break;
2354
2355 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2356
2357 break;
2358 case MSR_KVM_PV_EOI_EN:
2359 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2360 return 1;
2361 break;
2362
2363 case MSR_IA32_MCG_CTL:
2364 case MSR_IA32_MCG_STATUS:
2365 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2366 return set_msr_mce(vcpu, msr_info);
2367
2368 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2369 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2370 pr = true; /* fall through */
2371 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2372 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2373 if (kvm_pmu_is_valid_msr(vcpu, msr))
2374 return kvm_pmu_set_msr(vcpu, msr_info);
2375
2376 if (pr || data != 0)
2377 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2378 "0x%x data 0x%llx\n", msr, data);
2379 break;
2380 case MSR_K7_CLK_CTL:
2381 /*
2382 * Ignore all writes to this no longer documented MSR.
2383 * Writes are only relevant for old K7 processors,
2384 * all pre-dating SVM, but a recommended workaround from
2385 * AMD for these chips. It is possible to specify the
2386 * affected processor models on the command line, hence
2387 * the need to ignore the workaround.
2388 */
2389 break;
2390 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2391 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2392 case HV_X64_MSR_CRASH_CTL:
2393 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2394 return kvm_hv_set_msr_common(vcpu, msr, data,
2395 msr_info->host_initiated);
2396 case MSR_IA32_BBL_CR_CTL3:
2397 /* Drop writes to this legacy MSR -- see rdmsr
2398 * counterpart for further detail.
2399 */
2400 if (report_ignored_msrs)
2401 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2402 msr, data);
2403 break;
2404 case MSR_AMD64_OSVW_ID_LENGTH:
2405 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2406 return 1;
2407 vcpu->arch.osvw.length = data;
2408 break;
2409 case MSR_AMD64_OSVW_STATUS:
2410 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2411 return 1;
2412 vcpu->arch.osvw.status = data;
2413 break;
2414 case MSR_PLATFORM_INFO:
2415 if (!msr_info->host_initiated ||
2416 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2417 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2418 cpuid_fault_enabled(vcpu)))
2419 return 1;
2420 vcpu->arch.msr_platform_info = data;
2421 break;
2422 case MSR_MISC_FEATURES_ENABLES:
2423 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2424 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2425 !supports_cpuid_fault(vcpu)))
2426 return 1;
2427 vcpu->arch.msr_misc_features_enables = data;
2428 break;
2429 default:
2430 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2431 return xen_hvm_config(vcpu, data);
2432 if (kvm_pmu_is_valid_msr(vcpu, msr))
2433 return kvm_pmu_set_msr(vcpu, msr_info);
2434 if (!ignore_msrs) {
2435 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2436 msr, data);
2437 return 1;
2438 } else {
2439 if (report_ignored_msrs)
2440 vcpu_unimpl(vcpu,
2441 "ignored wrmsr: 0x%x data 0x%llx\n",
2442 msr, data);
2443 break;
2444 }
2445 }
2446 return 0;
2447 }
2448 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2449
2450
2451 /*
2452 * Reads an msr value (of 'msr_index') into 'pdata'.
2453 * Returns 0 on success, non-0 otherwise.
2454 * Assumes vcpu_load() was already called.
2455 */
2456 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2457 {
2458 return kvm_x86_ops->get_msr(vcpu, msr);
2459 }
2460 EXPORT_SYMBOL_GPL(kvm_get_msr);
2461
2462 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2463 {
2464 u64 data;
2465 u64 mcg_cap = vcpu->arch.mcg_cap;
2466 unsigned bank_num = mcg_cap & 0xff;
2467
2468 switch (msr) {
2469 case MSR_IA32_P5_MC_ADDR:
2470 case MSR_IA32_P5_MC_TYPE:
2471 data = 0;
2472 break;
2473 case MSR_IA32_MCG_CAP:
2474 data = vcpu->arch.mcg_cap;
2475 break;
2476 case MSR_IA32_MCG_CTL:
2477 if (!(mcg_cap & MCG_CTL_P))
2478 return 1;
2479 data = vcpu->arch.mcg_ctl;
2480 break;
2481 case MSR_IA32_MCG_STATUS:
2482 data = vcpu->arch.mcg_status;
2483 break;
2484 default:
2485 if (msr >= MSR_IA32_MC0_CTL &&
2486 msr < MSR_IA32_MCx_CTL(bank_num)) {
2487 u32 offset = msr - MSR_IA32_MC0_CTL;
2488 data = vcpu->arch.mce_banks[offset];
2489 break;
2490 }
2491 return 1;
2492 }
2493 *pdata = data;
2494 return 0;
2495 }
2496
2497 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2498 {
2499 switch (msr_info->index) {
2500 case MSR_IA32_PLATFORM_ID:
2501 case MSR_IA32_EBL_CR_POWERON:
2502 case MSR_IA32_DEBUGCTLMSR:
2503 case MSR_IA32_LASTBRANCHFROMIP:
2504 case MSR_IA32_LASTBRANCHTOIP:
2505 case MSR_IA32_LASTINTFROMIP:
2506 case MSR_IA32_LASTINTTOIP:
2507 case MSR_K8_SYSCFG:
2508 case MSR_K8_TSEG_ADDR:
2509 case MSR_K8_TSEG_MASK:
2510 case MSR_K7_HWCR:
2511 case MSR_VM_HSAVE_PA:
2512 case MSR_K8_INT_PENDING_MSG:
2513 case MSR_AMD64_NB_CFG:
2514 case MSR_FAM10H_MMIO_CONF_BASE:
2515 case MSR_AMD64_BU_CFG2:
2516 case MSR_IA32_PERF_CTL:
2517 case MSR_AMD64_DC_CFG:
2518 msr_info->data = 0;
2519 break;
2520 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2521 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2522 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2523 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2524 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2525 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2526 msr_info->data = 0;
2527 break;
2528 case MSR_IA32_UCODE_REV:
2529 msr_info->data = 0x100000000ULL;
2530 break;
2531 case MSR_MTRRcap:
2532 case 0x200 ... 0x2ff:
2533 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2534 case 0xcd: /* fsb frequency */
2535 msr_info->data = 3;
2536 break;
2537 /*
2538 * MSR_EBC_FREQUENCY_ID
2539 * Conservative value valid for even the basic CPU models.
2540 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2541 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2542 * and 266MHz for model 3, or 4. Set Core Clock
2543 * Frequency to System Bus Frequency Ratio to 1 (bits
2544 * 31:24) even though these are only valid for CPU
2545 * models > 2, however guests may end up dividing or
2546 * multiplying by zero otherwise.
2547 */
2548 case MSR_EBC_FREQUENCY_ID:
2549 msr_info->data = 1 << 24;
2550 break;
2551 case MSR_IA32_APICBASE:
2552 msr_info->data = kvm_get_apic_base(vcpu);
2553 break;
2554 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2555 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2556 break;
2557 case MSR_IA32_TSCDEADLINE:
2558 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2559 break;
2560 case MSR_IA32_TSC_ADJUST:
2561 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2562 break;
2563 case MSR_IA32_MISC_ENABLE:
2564 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2565 break;
2566 case MSR_IA32_SMBASE:
2567 if (!msr_info->host_initiated)
2568 return 1;
2569 msr_info->data = vcpu->arch.smbase;
2570 break;
2571 case MSR_IA32_PERF_STATUS:
2572 /* TSC increment by tick */
2573 msr_info->data = 1000ULL;
2574 /* CPU multiplier */
2575 msr_info->data |= (((uint64_t)4ULL) << 40);
2576 break;
2577 case MSR_EFER:
2578 msr_info->data = vcpu->arch.efer;
2579 break;
2580 case MSR_KVM_WALL_CLOCK:
2581 case MSR_KVM_WALL_CLOCK_NEW:
2582 msr_info->data = vcpu->kvm->arch.wall_clock;
2583 break;
2584 case MSR_KVM_SYSTEM_TIME:
2585 case MSR_KVM_SYSTEM_TIME_NEW:
2586 msr_info->data = vcpu->arch.time;
2587 break;
2588 case MSR_KVM_ASYNC_PF_EN:
2589 msr_info->data = vcpu->arch.apf.msr_val;
2590 break;
2591 case MSR_KVM_STEAL_TIME:
2592 msr_info->data = vcpu->arch.st.msr_val;
2593 break;
2594 case MSR_KVM_PV_EOI_EN:
2595 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2596 break;
2597 case MSR_IA32_P5_MC_ADDR:
2598 case MSR_IA32_P5_MC_TYPE:
2599 case MSR_IA32_MCG_CAP:
2600 case MSR_IA32_MCG_CTL:
2601 case MSR_IA32_MCG_STATUS:
2602 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2603 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2604 case MSR_K7_CLK_CTL:
2605 /*
2606 * Provide expected ramp-up count for K7. All other
2607 * are set to zero, indicating minimum divisors for
2608 * every field.
2609 *
2610 * This prevents guest kernels on AMD host with CPU
2611 * type 6, model 8 and higher from exploding due to
2612 * the rdmsr failing.
2613 */
2614 msr_info->data = 0x20000000;
2615 break;
2616 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2617 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2618 case HV_X64_MSR_CRASH_CTL:
2619 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2620 return kvm_hv_get_msr_common(vcpu,
2621 msr_info->index, &msr_info->data);
2622 break;
2623 case MSR_IA32_BBL_CR_CTL3:
2624 /* This legacy MSR exists but isn't fully documented in current
2625 * silicon. It is however accessed by winxp in very narrow
2626 * scenarios where it sets bit #19, itself documented as
2627 * a "reserved" bit. Best effort attempt to source coherent
2628 * read data here should the balance of the register be
2629 * interpreted by the guest:
2630 *
2631 * L2 cache control register 3: 64GB range, 256KB size,
2632 * enabled, latency 0x1, configured
2633 */
2634 msr_info->data = 0xbe702111;
2635 break;
2636 case MSR_AMD64_OSVW_ID_LENGTH:
2637 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2638 return 1;
2639 msr_info->data = vcpu->arch.osvw.length;
2640 break;
2641 case MSR_AMD64_OSVW_STATUS:
2642 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2643 return 1;
2644 msr_info->data = vcpu->arch.osvw.status;
2645 break;
2646 case MSR_PLATFORM_INFO:
2647 msr_info->data = vcpu->arch.msr_platform_info;
2648 break;
2649 case MSR_MISC_FEATURES_ENABLES:
2650 msr_info->data = vcpu->arch.msr_misc_features_enables;
2651 break;
2652 default:
2653 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2654 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2655 if (!ignore_msrs) {
2656 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2657 msr_info->index);
2658 return 1;
2659 } else {
2660 if (report_ignored_msrs)
2661 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2662 msr_info->index);
2663 msr_info->data = 0;
2664 }
2665 break;
2666 }
2667 return 0;
2668 }
2669 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2670
2671 /*
2672 * Read or write a bunch of msrs. All parameters are kernel addresses.
2673 *
2674 * @return number of msrs set successfully.
2675 */
2676 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2677 struct kvm_msr_entry *entries,
2678 int (*do_msr)(struct kvm_vcpu *vcpu,
2679 unsigned index, u64 *data))
2680 {
2681 int i;
2682
2683 for (i = 0; i < msrs->nmsrs; ++i)
2684 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2685 break;
2686
2687 return i;
2688 }
2689
2690 /*
2691 * Read or write a bunch of msrs. Parameters are user addresses.
2692 *
2693 * @return number of msrs set successfully.
2694 */
2695 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2696 int (*do_msr)(struct kvm_vcpu *vcpu,
2697 unsigned index, u64 *data),
2698 int writeback)
2699 {
2700 struct kvm_msrs msrs;
2701 struct kvm_msr_entry *entries;
2702 int r, n;
2703 unsigned size;
2704
2705 r = -EFAULT;
2706 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2707 goto out;
2708
2709 r = -E2BIG;
2710 if (msrs.nmsrs >= MAX_IO_MSRS)
2711 goto out;
2712
2713 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2714 entries = memdup_user(user_msrs->entries, size);
2715 if (IS_ERR(entries)) {
2716 r = PTR_ERR(entries);
2717 goto out;
2718 }
2719
2720 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2721 if (r < 0)
2722 goto out_free;
2723
2724 r = -EFAULT;
2725 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2726 goto out_free;
2727
2728 r = n;
2729
2730 out_free:
2731 kfree(entries);
2732 out:
2733 return r;
2734 }
2735
2736 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2737 {
2738 int r;
2739
2740 switch (ext) {
2741 case KVM_CAP_IRQCHIP:
2742 case KVM_CAP_HLT:
2743 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2744 case KVM_CAP_SET_TSS_ADDR:
2745 case KVM_CAP_EXT_CPUID:
2746 case KVM_CAP_EXT_EMUL_CPUID:
2747 case KVM_CAP_CLOCKSOURCE:
2748 case KVM_CAP_PIT:
2749 case KVM_CAP_NOP_IO_DELAY:
2750 case KVM_CAP_MP_STATE:
2751 case KVM_CAP_SYNC_MMU:
2752 case KVM_CAP_USER_NMI:
2753 case KVM_CAP_REINJECT_CONTROL:
2754 case KVM_CAP_IRQ_INJECT_STATUS:
2755 case KVM_CAP_IOEVENTFD:
2756 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2757 case KVM_CAP_PIT2:
2758 case KVM_CAP_PIT_STATE2:
2759 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2760 case KVM_CAP_XEN_HVM:
2761 case KVM_CAP_VCPU_EVENTS:
2762 case KVM_CAP_HYPERV:
2763 case KVM_CAP_HYPERV_VAPIC:
2764 case KVM_CAP_HYPERV_SPIN:
2765 case KVM_CAP_HYPERV_SYNIC:
2766 case KVM_CAP_HYPERV_SYNIC2:
2767 case KVM_CAP_HYPERV_VP_INDEX:
2768 case KVM_CAP_PCI_SEGMENT:
2769 case KVM_CAP_DEBUGREGS:
2770 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2771 case KVM_CAP_XSAVE:
2772 case KVM_CAP_ASYNC_PF:
2773 case KVM_CAP_GET_TSC_KHZ:
2774 case KVM_CAP_KVMCLOCK_CTRL:
2775 case KVM_CAP_READONLY_MEM:
2776 case KVM_CAP_HYPERV_TIME:
2777 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2778 case KVM_CAP_TSC_DEADLINE_TIMER:
2779 case KVM_CAP_ENABLE_CAP_VM:
2780 case KVM_CAP_DISABLE_QUIRKS:
2781 case KVM_CAP_SET_BOOT_CPU_ID:
2782 case KVM_CAP_SPLIT_IRQCHIP:
2783 case KVM_CAP_IMMEDIATE_EXIT:
2784 case KVM_CAP_GET_MSR_FEATURES:
2785 r = 1;
2786 break;
2787 case KVM_CAP_ADJUST_CLOCK:
2788 r = KVM_CLOCK_TSC_STABLE;
2789 break;
2790 case KVM_CAP_X86_GUEST_MWAIT:
2791 r = kvm_mwait_in_guest();
2792 break;
2793 case KVM_CAP_X86_SMM:
2794 /* SMBASE is usually relocated above 1M on modern chipsets,
2795 * and SMM handlers might indeed rely on 4G segment limits,
2796 * so do not report SMM to be available if real mode is
2797 * emulated via vm86 mode. Still, do not go to great lengths
2798 * to avoid userspace's usage of the feature, because it is a
2799 * fringe case that is not enabled except via specific settings
2800 * of the module parameters.
2801 */
2802 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
2803 break;
2804 case KVM_CAP_VAPIC:
2805 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2806 break;
2807 case KVM_CAP_NR_VCPUS:
2808 r = KVM_SOFT_MAX_VCPUS;
2809 break;
2810 case KVM_CAP_MAX_VCPUS:
2811 r = KVM_MAX_VCPUS;
2812 break;
2813 case KVM_CAP_NR_MEMSLOTS:
2814 r = KVM_USER_MEM_SLOTS;
2815 break;
2816 case KVM_CAP_PV_MMU: /* obsolete */
2817 r = 0;
2818 break;
2819 case KVM_CAP_MCE:
2820 r = KVM_MAX_MCE_BANKS;
2821 break;
2822 case KVM_CAP_XCRS:
2823 r = boot_cpu_has(X86_FEATURE_XSAVE);
2824 break;
2825 case KVM_CAP_TSC_CONTROL:
2826 r = kvm_has_tsc_control;
2827 break;
2828 case KVM_CAP_X2APIC_API:
2829 r = KVM_X2APIC_API_VALID_FLAGS;
2830 break;
2831 default:
2832 r = 0;
2833 break;
2834 }
2835 return r;
2836
2837 }
2838
2839 long kvm_arch_dev_ioctl(struct file *filp,
2840 unsigned int ioctl, unsigned long arg)
2841 {
2842 void __user *argp = (void __user *)arg;
2843 long r;
2844
2845 switch (ioctl) {
2846 case KVM_GET_MSR_INDEX_LIST: {
2847 struct kvm_msr_list __user *user_msr_list = argp;
2848 struct kvm_msr_list msr_list;
2849 unsigned n;
2850
2851 r = -EFAULT;
2852 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2853 goto out;
2854 n = msr_list.nmsrs;
2855 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2856 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2857 goto out;
2858 r = -E2BIG;
2859 if (n < msr_list.nmsrs)
2860 goto out;
2861 r = -EFAULT;
2862 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2863 num_msrs_to_save * sizeof(u32)))
2864 goto out;
2865 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2866 &emulated_msrs,
2867 num_emulated_msrs * sizeof(u32)))
2868 goto out;
2869 r = 0;
2870 break;
2871 }
2872 case KVM_GET_SUPPORTED_CPUID:
2873 case KVM_GET_EMULATED_CPUID: {
2874 struct kvm_cpuid2 __user *cpuid_arg = argp;
2875 struct kvm_cpuid2 cpuid;
2876
2877 r = -EFAULT;
2878 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2879 goto out;
2880
2881 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2882 ioctl);
2883 if (r)
2884 goto out;
2885
2886 r = -EFAULT;
2887 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2888 goto out;
2889 r = 0;
2890 break;
2891 }
2892 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2893 r = -EFAULT;
2894 if (copy_to_user(argp, &kvm_mce_cap_supported,
2895 sizeof(kvm_mce_cap_supported)))
2896 goto out;
2897 r = 0;
2898 break;
2899 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2900 struct kvm_msr_list __user *user_msr_list = argp;
2901 struct kvm_msr_list msr_list;
2902 unsigned int n;
2903
2904 r = -EFAULT;
2905 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2906 goto out;
2907 n = msr_list.nmsrs;
2908 msr_list.nmsrs = num_msr_based_features;
2909 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2910 goto out;
2911 r = -E2BIG;
2912 if (n < msr_list.nmsrs)
2913 goto out;
2914 r = -EFAULT;
2915 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2916 num_msr_based_features * sizeof(u32)))
2917 goto out;
2918 r = 0;
2919 break;
2920 }
2921 case KVM_GET_MSRS:
2922 r = msr_io(NULL, argp, do_get_msr_feature, 1);
2923 break;
2924 }
2925 default:
2926 r = -EINVAL;
2927 }
2928 out:
2929 return r;
2930 }
2931
2932 static void wbinvd_ipi(void *garbage)
2933 {
2934 wbinvd();
2935 }
2936
2937 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2938 {
2939 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2940 }
2941
2942 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2943 {
2944 /* Address WBINVD may be executed by guest */
2945 if (need_emulate_wbinvd(vcpu)) {
2946 if (kvm_x86_ops->has_wbinvd_exit())
2947 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2948 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2949 smp_call_function_single(vcpu->cpu,
2950 wbinvd_ipi, NULL, 1);
2951 }
2952
2953 kvm_x86_ops->vcpu_load(vcpu, cpu);
2954
2955 /* Apply any externally detected TSC adjustments (due to suspend) */
2956 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2957 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2958 vcpu->arch.tsc_offset_adjustment = 0;
2959 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2960 }
2961
2962 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2963 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2964 rdtsc() - vcpu->arch.last_host_tsc;
2965 if (tsc_delta < 0)
2966 mark_tsc_unstable("KVM discovered backwards TSC");
2967
2968 if (check_tsc_unstable()) {
2969 u64 offset = kvm_compute_tsc_offset(vcpu,
2970 vcpu->arch.last_guest_tsc);
2971 kvm_vcpu_write_tsc_offset(vcpu, offset);
2972 vcpu->arch.tsc_catchup = 1;
2973 }
2974
2975 if (kvm_lapic_hv_timer_in_use(vcpu))
2976 kvm_lapic_restart_hv_timer(vcpu);
2977
2978 /*
2979 * On a host with synchronized TSC, there is no need to update
2980 * kvmclock on vcpu->cpu migration
2981 */
2982 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2983 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2984 if (vcpu->cpu != cpu)
2985 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
2986 vcpu->cpu = cpu;
2987 }
2988
2989 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2990 }
2991
2992 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2993 {
2994 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2995 return;
2996
2997 vcpu->arch.st.steal.preempted = 1;
2998
2999 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3000 &vcpu->arch.st.steal.preempted,
3001 offsetof(struct kvm_steal_time, preempted),
3002 sizeof(vcpu->arch.st.steal.preempted));
3003 }
3004
3005 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3006 {
3007 int idx;
3008
3009 if (vcpu->preempted)
3010 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3011
3012 /*
3013 * Disable page faults because we're in atomic context here.
3014 * kvm_write_guest_offset_cached() would call might_fault()
3015 * that relies on pagefault_disable() to tell if there's a
3016 * bug. NOTE: the write to guest memory may not go through if
3017 * during postcopy live migration or if there's heavy guest
3018 * paging.
3019 */
3020 pagefault_disable();
3021 /*
3022 * kvm_memslots() will be called by
3023 * kvm_write_guest_offset_cached() so take the srcu lock.
3024 */
3025 idx = srcu_read_lock(&vcpu->kvm->srcu);
3026 kvm_steal_time_set_preempted(vcpu);
3027 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3028 pagefault_enable();
3029 kvm_x86_ops->vcpu_put(vcpu);
3030 vcpu->arch.last_host_tsc = rdtsc();
3031 /*
3032 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3033 * on every vmexit, but if not, we might have a stale dr6 from the
3034 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3035 */
3036 set_debugreg(0, 6);
3037 }
3038
3039 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3040 struct kvm_lapic_state *s)
3041 {
3042 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
3043 kvm_x86_ops->sync_pir_to_irr(vcpu);
3044
3045 return kvm_apic_get_state(vcpu, s);
3046 }
3047
3048 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3049 struct kvm_lapic_state *s)
3050 {
3051 int r;
3052
3053 r = kvm_apic_set_state(vcpu, s);
3054 if (r)
3055 return r;
3056 update_cr8_intercept(vcpu);
3057
3058 return 0;
3059 }
3060
3061 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3062 {
3063 return (!lapic_in_kernel(vcpu) ||
3064 kvm_apic_accept_pic_intr(vcpu));
3065 }
3066
3067 /*
3068 * if userspace requested an interrupt window, check that the
3069 * interrupt window is open.
3070 *
3071 * No need to exit to userspace if we already have an interrupt queued.
3072 */
3073 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3074 {
3075 return kvm_arch_interrupt_allowed(vcpu) &&
3076 !kvm_cpu_has_interrupt(vcpu) &&
3077 !kvm_event_needs_reinjection(vcpu) &&
3078 kvm_cpu_accept_dm_intr(vcpu);
3079 }
3080
3081 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3082 struct kvm_interrupt *irq)
3083 {
3084 if (irq->irq >= KVM_NR_INTERRUPTS)
3085 return -EINVAL;
3086
3087 if (!irqchip_in_kernel(vcpu->kvm)) {
3088 kvm_queue_interrupt(vcpu, irq->irq, false);
3089 kvm_make_request(KVM_REQ_EVENT, vcpu);
3090 return 0;
3091 }
3092
3093 /*
3094 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3095 * fail for in-kernel 8259.
3096 */
3097 if (pic_in_kernel(vcpu->kvm))
3098 return -ENXIO;
3099
3100 if (vcpu->arch.pending_external_vector != -1)
3101 return -EEXIST;
3102
3103 vcpu->arch.pending_external_vector = irq->irq;
3104 kvm_make_request(KVM_REQ_EVENT, vcpu);
3105 return 0;
3106 }
3107
3108 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3109 {
3110 kvm_inject_nmi(vcpu);
3111
3112 return 0;
3113 }
3114
3115 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3116 {
3117 kvm_make_request(KVM_REQ_SMI, vcpu);
3118
3119 return 0;
3120 }
3121
3122 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3123 struct kvm_tpr_access_ctl *tac)
3124 {
3125 if (tac->flags)
3126 return -EINVAL;
3127 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3128 return 0;
3129 }
3130
3131 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3132 u64 mcg_cap)
3133 {
3134 int r;
3135 unsigned bank_num = mcg_cap & 0xff, bank;
3136
3137 r = -EINVAL;
3138 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3139 goto out;
3140 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3141 goto out;
3142 r = 0;
3143 vcpu->arch.mcg_cap = mcg_cap;
3144 /* Init IA32_MCG_CTL to all 1s */
3145 if (mcg_cap & MCG_CTL_P)
3146 vcpu->arch.mcg_ctl = ~(u64)0;
3147 /* Init IA32_MCi_CTL to all 1s */
3148 for (bank = 0; bank < bank_num; bank++)
3149 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3150
3151 if (kvm_x86_ops->setup_mce)
3152 kvm_x86_ops->setup_mce(vcpu);
3153 out:
3154 return r;
3155 }
3156
3157 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3158 struct kvm_x86_mce *mce)
3159 {
3160 u64 mcg_cap = vcpu->arch.mcg_cap;
3161 unsigned bank_num = mcg_cap & 0xff;
3162 u64 *banks = vcpu->arch.mce_banks;
3163
3164 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3165 return -EINVAL;
3166 /*
3167 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3168 * reporting is disabled
3169 */
3170 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3171 vcpu->arch.mcg_ctl != ~(u64)0)
3172 return 0;
3173 banks += 4 * mce->bank;
3174 /*
3175 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3176 * reporting is disabled for the bank
3177 */
3178 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3179 return 0;
3180 if (mce->status & MCI_STATUS_UC) {
3181 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3182 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3183 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3184 return 0;
3185 }
3186 if (banks[1] & MCI_STATUS_VAL)
3187 mce->status |= MCI_STATUS_OVER;
3188 banks[2] = mce->addr;
3189 banks[3] = mce->misc;
3190 vcpu->arch.mcg_status = mce->mcg_status;
3191 banks[1] = mce->status;
3192 kvm_queue_exception(vcpu, MC_VECTOR);
3193 } else if (!(banks[1] & MCI_STATUS_VAL)
3194 || !(banks[1] & MCI_STATUS_UC)) {
3195 if (banks[1] & MCI_STATUS_VAL)
3196 mce->status |= MCI_STATUS_OVER;
3197 banks[2] = mce->addr;
3198 banks[3] = mce->misc;
3199 banks[1] = mce->status;
3200 } else
3201 banks[1] |= MCI_STATUS_OVER;
3202 return 0;
3203 }
3204
3205 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3206 struct kvm_vcpu_events *events)
3207 {
3208 process_nmi(vcpu);
3209 /*
3210 * FIXME: pass injected and pending separately. This is only
3211 * needed for nested virtualization, whose state cannot be
3212 * migrated yet. For now we can combine them.
3213 */
3214 events->exception.injected =
3215 (vcpu->arch.exception.pending ||
3216 vcpu->arch.exception.injected) &&
3217 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3218 events->exception.nr = vcpu->arch.exception.nr;
3219 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3220 events->exception.pad = 0;
3221 events->exception.error_code = vcpu->arch.exception.error_code;
3222
3223 events->interrupt.injected =
3224 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3225 events->interrupt.nr = vcpu->arch.interrupt.nr;
3226 events->interrupt.soft = 0;
3227 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3228
3229 events->nmi.injected = vcpu->arch.nmi_injected;
3230 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3231 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3232 events->nmi.pad = 0;
3233
3234 events->sipi_vector = 0; /* never valid when reporting to user space */
3235
3236 events->smi.smm = is_smm(vcpu);
3237 events->smi.pending = vcpu->arch.smi_pending;
3238 events->smi.smm_inside_nmi =
3239 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3240 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3241
3242 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3243 | KVM_VCPUEVENT_VALID_SHADOW
3244 | KVM_VCPUEVENT_VALID_SMM);
3245 memset(&events->reserved, 0, sizeof(events->reserved));
3246 }
3247
3248 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3249
3250 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3251 struct kvm_vcpu_events *events)
3252 {
3253 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3254 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3255 | KVM_VCPUEVENT_VALID_SHADOW
3256 | KVM_VCPUEVENT_VALID_SMM))
3257 return -EINVAL;
3258
3259 if (events->exception.injected &&
3260 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3261 is_guest_mode(vcpu)))
3262 return -EINVAL;
3263
3264 /* INITs are latched while in SMM */
3265 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3266 (events->smi.smm || events->smi.pending) &&
3267 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3268 return -EINVAL;
3269
3270 process_nmi(vcpu);
3271 vcpu->arch.exception.injected = false;
3272 vcpu->arch.exception.pending = events->exception.injected;
3273 vcpu->arch.exception.nr = events->exception.nr;
3274 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3275 vcpu->arch.exception.error_code = events->exception.error_code;
3276
3277 vcpu->arch.interrupt.pending = events->interrupt.injected;
3278 vcpu->arch.interrupt.nr = events->interrupt.nr;
3279 vcpu->arch.interrupt.soft = events->interrupt.soft;
3280 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3281 kvm_x86_ops->set_interrupt_shadow(vcpu,
3282 events->interrupt.shadow);
3283
3284 vcpu->arch.nmi_injected = events->nmi.injected;
3285 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3286 vcpu->arch.nmi_pending = events->nmi.pending;
3287 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3288
3289 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3290 lapic_in_kernel(vcpu))
3291 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3292
3293 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3294 u32 hflags = vcpu->arch.hflags;
3295 if (events->smi.smm)
3296 hflags |= HF_SMM_MASK;
3297 else
3298 hflags &= ~HF_SMM_MASK;
3299 kvm_set_hflags(vcpu, hflags);
3300
3301 vcpu->arch.smi_pending = events->smi.pending;
3302
3303 if (events->smi.smm) {
3304 if (events->smi.smm_inside_nmi)
3305 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3306 else
3307 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3308 if (lapic_in_kernel(vcpu)) {
3309 if (events->smi.latched_init)
3310 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3311 else
3312 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3313 }
3314 }
3315 }
3316
3317 kvm_make_request(KVM_REQ_EVENT, vcpu);
3318
3319 return 0;
3320 }
3321
3322 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3323 struct kvm_debugregs *dbgregs)
3324 {
3325 unsigned long val;
3326
3327 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3328 kvm_get_dr(vcpu, 6, &val);
3329 dbgregs->dr6 = val;
3330 dbgregs->dr7 = vcpu->arch.dr7;
3331 dbgregs->flags = 0;
3332 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3333 }
3334
3335 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3336 struct kvm_debugregs *dbgregs)
3337 {
3338 if (dbgregs->flags)
3339 return -EINVAL;
3340
3341 if (dbgregs->dr6 & ~0xffffffffull)
3342 return -EINVAL;
3343 if (dbgregs->dr7 & ~0xffffffffull)
3344 return -EINVAL;
3345
3346 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3347 kvm_update_dr0123(vcpu);
3348 vcpu->arch.dr6 = dbgregs->dr6;
3349 kvm_update_dr6(vcpu);
3350 vcpu->arch.dr7 = dbgregs->dr7;
3351 kvm_update_dr7(vcpu);
3352
3353 return 0;
3354 }
3355
3356 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3357
3358 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3359 {
3360 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3361 u64 xstate_bv = xsave->header.xfeatures;
3362 u64 valid;
3363
3364 /*
3365 * Copy legacy XSAVE area, to avoid complications with CPUID
3366 * leaves 0 and 1 in the loop below.
3367 */
3368 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3369
3370 /* Set XSTATE_BV */
3371 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3372 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3373
3374 /*
3375 * Copy each region from the possibly compacted offset to the
3376 * non-compacted offset.
3377 */
3378 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3379 while (valid) {
3380 u64 feature = valid & -valid;
3381 int index = fls64(feature) - 1;
3382 void *src = get_xsave_addr(xsave, feature);
3383
3384 if (src) {
3385 u32 size, offset, ecx, edx;
3386 cpuid_count(XSTATE_CPUID, index,
3387 &size, &offset, &ecx, &edx);
3388 if (feature == XFEATURE_MASK_PKRU)
3389 memcpy(dest + offset, &vcpu->arch.pkru,
3390 sizeof(vcpu->arch.pkru));
3391 else
3392 memcpy(dest + offset, src, size);
3393
3394 }
3395
3396 valid -= feature;
3397 }
3398 }
3399
3400 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3401 {
3402 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3403 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3404 u64 valid;
3405
3406 /*
3407 * Copy legacy XSAVE area, to avoid complications with CPUID
3408 * leaves 0 and 1 in the loop below.
3409 */
3410 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3411
3412 /* Set XSTATE_BV and possibly XCOMP_BV. */
3413 xsave->header.xfeatures = xstate_bv;
3414 if (boot_cpu_has(X86_FEATURE_XSAVES))
3415 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3416
3417 /*
3418 * Copy each region from the non-compacted offset to the
3419 * possibly compacted offset.
3420 */
3421 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3422 while (valid) {
3423 u64 feature = valid & -valid;
3424 int index = fls64(feature) - 1;
3425 void *dest = get_xsave_addr(xsave, feature);
3426
3427 if (dest) {
3428 u32 size, offset, ecx, edx;
3429 cpuid_count(XSTATE_CPUID, index,
3430 &size, &offset, &ecx, &edx);
3431 if (feature == XFEATURE_MASK_PKRU)
3432 memcpy(&vcpu->arch.pkru, src + offset,
3433 sizeof(vcpu->arch.pkru));
3434 else
3435 memcpy(dest, src + offset, size);
3436 }
3437
3438 valid -= feature;
3439 }
3440 }
3441
3442 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3443 struct kvm_xsave *guest_xsave)
3444 {
3445 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3446 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3447 fill_xsave((u8 *) guest_xsave->region, vcpu);
3448 } else {
3449 memcpy(guest_xsave->region,
3450 &vcpu->arch.guest_fpu.state.fxsave,
3451 sizeof(struct fxregs_state));
3452 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3453 XFEATURE_MASK_FPSSE;
3454 }
3455 }
3456
3457 #define XSAVE_MXCSR_OFFSET 24
3458
3459 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3460 struct kvm_xsave *guest_xsave)
3461 {
3462 u64 xstate_bv =
3463 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3464 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3465
3466 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3467 /*
3468 * Here we allow setting states that are not present in
3469 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3470 * with old userspace.
3471 */
3472 if (xstate_bv & ~kvm_supported_xcr0() ||
3473 mxcsr & ~mxcsr_feature_mask)
3474 return -EINVAL;
3475 load_xsave(vcpu, (u8 *)guest_xsave->region);
3476 } else {
3477 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3478 mxcsr & ~mxcsr_feature_mask)
3479 return -EINVAL;
3480 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3481 guest_xsave->region, sizeof(struct fxregs_state));
3482 }
3483 return 0;
3484 }
3485
3486 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3487 struct kvm_xcrs *guest_xcrs)
3488 {
3489 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3490 guest_xcrs->nr_xcrs = 0;
3491 return;
3492 }
3493
3494 guest_xcrs->nr_xcrs = 1;
3495 guest_xcrs->flags = 0;
3496 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3497 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3498 }
3499
3500 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3501 struct kvm_xcrs *guest_xcrs)
3502 {
3503 int i, r = 0;
3504
3505 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3506 return -EINVAL;
3507
3508 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3509 return -EINVAL;
3510
3511 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3512 /* Only support XCR0 currently */
3513 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3514 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3515 guest_xcrs->xcrs[i].value);
3516 break;
3517 }
3518 if (r)
3519 r = -EINVAL;
3520 return r;
3521 }
3522
3523 /*
3524 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3525 * stopped by the hypervisor. This function will be called from the host only.
3526 * EINVAL is returned when the host attempts to set the flag for a guest that
3527 * does not support pv clocks.
3528 */
3529 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3530 {
3531 if (!vcpu->arch.pv_time_enabled)
3532 return -EINVAL;
3533 vcpu->arch.pvclock_set_guest_stopped_request = true;
3534 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3535 return 0;
3536 }
3537
3538 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3539 struct kvm_enable_cap *cap)
3540 {
3541 if (cap->flags)
3542 return -EINVAL;
3543
3544 switch (cap->cap) {
3545 case KVM_CAP_HYPERV_SYNIC2:
3546 if (cap->args[0])
3547 return -EINVAL;
3548 case KVM_CAP_HYPERV_SYNIC:
3549 if (!irqchip_in_kernel(vcpu->kvm))
3550 return -EINVAL;
3551 return kvm_hv_activate_synic(vcpu, cap->cap ==
3552 KVM_CAP_HYPERV_SYNIC2);
3553 default:
3554 return -EINVAL;
3555 }
3556 }
3557
3558 long kvm_arch_vcpu_ioctl(struct file *filp,
3559 unsigned int ioctl, unsigned long arg)
3560 {
3561 struct kvm_vcpu *vcpu = filp->private_data;
3562 void __user *argp = (void __user *)arg;
3563 int r;
3564 union {
3565 struct kvm_lapic_state *lapic;
3566 struct kvm_xsave *xsave;
3567 struct kvm_xcrs *xcrs;
3568 void *buffer;
3569 } u;
3570
3571 u.buffer = NULL;
3572 switch (ioctl) {
3573 case KVM_GET_LAPIC: {
3574 r = -EINVAL;
3575 if (!lapic_in_kernel(vcpu))
3576 goto out;
3577 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3578
3579 r = -ENOMEM;
3580 if (!u.lapic)
3581 goto out;
3582 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3583 if (r)
3584 goto out;
3585 r = -EFAULT;
3586 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3587 goto out;
3588 r = 0;
3589 break;
3590 }
3591 case KVM_SET_LAPIC: {
3592 r = -EINVAL;
3593 if (!lapic_in_kernel(vcpu))
3594 goto out;
3595 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3596 if (IS_ERR(u.lapic))
3597 return PTR_ERR(u.lapic);
3598
3599 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3600 break;
3601 }
3602 case KVM_INTERRUPT: {
3603 struct kvm_interrupt irq;
3604
3605 r = -EFAULT;
3606 if (copy_from_user(&irq, argp, sizeof irq))
3607 goto out;
3608 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3609 break;
3610 }
3611 case KVM_NMI: {
3612 r = kvm_vcpu_ioctl_nmi(vcpu);
3613 break;
3614 }
3615 case KVM_SMI: {
3616 r = kvm_vcpu_ioctl_smi(vcpu);
3617 break;
3618 }
3619 case KVM_SET_CPUID: {
3620 struct kvm_cpuid __user *cpuid_arg = argp;
3621 struct kvm_cpuid cpuid;
3622
3623 r = -EFAULT;
3624 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3625 goto out;
3626 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3627 break;
3628 }
3629 case KVM_SET_CPUID2: {
3630 struct kvm_cpuid2 __user *cpuid_arg = argp;
3631 struct kvm_cpuid2 cpuid;
3632
3633 r = -EFAULT;
3634 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3635 goto out;
3636 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3637 cpuid_arg->entries);
3638 break;
3639 }
3640 case KVM_GET_CPUID2: {
3641 struct kvm_cpuid2 __user *cpuid_arg = argp;
3642 struct kvm_cpuid2 cpuid;
3643
3644 r = -EFAULT;
3645 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3646 goto out;
3647 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3648 cpuid_arg->entries);
3649 if (r)
3650 goto out;
3651 r = -EFAULT;
3652 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3653 goto out;
3654 r = 0;
3655 break;
3656 }
3657 case KVM_GET_MSRS: {
3658 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3659 r = msr_io(vcpu, argp, do_get_msr, 1);
3660 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3661 break;
3662 }
3663 case KVM_SET_MSRS: {
3664 int idx = srcu_read_lock(&vcpu->kvm->srcu);
3665 r = msr_io(vcpu, argp, do_set_msr, 0);
3666 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3667 break;
3668 }
3669 case KVM_TPR_ACCESS_REPORTING: {
3670 struct kvm_tpr_access_ctl tac;
3671
3672 r = -EFAULT;
3673 if (copy_from_user(&tac, argp, sizeof tac))
3674 goto out;
3675 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3676 if (r)
3677 goto out;
3678 r = -EFAULT;
3679 if (copy_to_user(argp, &tac, sizeof tac))
3680 goto out;
3681 r = 0;
3682 break;
3683 };
3684 case KVM_SET_VAPIC_ADDR: {
3685 struct kvm_vapic_addr va;
3686 int idx;
3687
3688 r = -EINVAL;
3689 if (!lapic_in_kernel(vcpu))
3690 goto out;
3691 r = -EFAULT;
3692 if (copy_from_user(&va, argp, sizeof va))
3693 goto out;
3694 idx = srcu_read_lock(&vcpu->kvm->srcu);
3695 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3696 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3697 break;
3698 }
3699 case KVM_X86_SETUP_MCE: {
3700 u64 mcg_cap;
3701
3702 r = -EFAULT;
3703 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3704 goto out;
3705 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3706 break;
3707 }
3708 case KVM_X86_SET_MCE: {
3709 struct kvm_x86_mce mce;
3710
3711 r = -EFAULT;
3712 if (copy_from_user(&mce, argp, sizeof mce))
3713 goto out;
3714 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3715 break;
3716 }
3717 case KVM_GET_VCPU_EVENTS: {
3718 struct kvm_vcpu_events events;
3719
3720 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3721
3722 r = -EFAULT;
3723 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3724 break;
3725 r = 0;
3726 break;
3727 }
3728 case KVM_SET_VCPU_EVENTS: {
3729 struct kvm_vcpu_events events;
3730
3731 r = -EFAULT;
3732 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3733 break;
3734
3735 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3736 break;
3737 }
3738 case KVM_GET_DEBUGREGS: {
3739 struct kvm_debugregs dbgregs;
3740
3741 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3742
3743 r = -EFAULT;
3744 if (copy_to_user(argp, &dbgregs,
3745 sizeof(struct kvm_debugregs)))
3746 break;
3747 r = 0;
3748 break;
3749 }
3750 case KVM_SET_DEBUGREGS: {
3751 struct kvm_debugregs dbgregs;
3752
3753 r = -EFAULT;
3754 if (copy_from_user(&dbgregs, argp,
3755 sizeof(struct kvm_debugregs)))
3756 break;
3757
3758 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3759 break;
3760 }
3761 case KVM_GET_XSAVE: {
3762 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3763 r = -ENOMEM;
3764 if (!u.xsave)
3765 break;
3766
3767 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3768
3769 r = -EFAULT;
3770 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3771 break;
3772 r = 0;
3773 break;
3774 }
3775 case KVM_SET_XSAVE: {
3776 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3777 if (IS_ERR(u.xsave))
3778 return PTR_ERR(u.xsave);
3779
3780 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3781 break;
3782 }
3783 case KVM_GET_XCRS: {
3784 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3785 r = -ENOMEM;
3786 if (!u.xcrs)
3787 break;
3788
3789 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3790
3791 r = -EFAULT;
3792 if (copy_to_user(argp, u.xcrs,
3793 sizeof(struct kvm_xcrs)))
3794 break;
3795 r = 0;
3796 break;
3797 }
3798 case KVM_SET_XCRS: {
3799 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3800 if (IS_ERR(u.xcrs))
3801 return PTR_ERR(u.xcrs);
3802
3803 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3804 break;
3805 }
3806 case KVM_SET_TSC_KHZ: {
3807 u32 user_tsc_khz;
3808
3809 r = -EINVAL;
3810 user_tsc_khz = (u32)arg;
3811
3812 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3813 goto out;
3814
3815 if (user_tsc_khz == 0)
3816 user_tsc_khz = tsc_khz;
3817
3818 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3819 r = 0;
3820
3821 goto out;
3822 }
3823 case KVM_GET_TSC_KHZ: {
3824 r = vcpu->arch.virtual_tsc_khz;
3825 goto out;
3826 }
3827 case KVM_KVMCLOCK_CTRL: {
3828 r = kvm_set_guest_paused(vcpu);
3829 goto out;
3830 }
3831 case KVM_ENABLE_CAP: {
3832 struct kvm_enable_cap cap;
3833
3834 r = -EFAULT;
3835 if (copy_from_user(&cap, argp, sizeof(cap)))
3836 goto out;
3837 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3838 break;
3839 }
3840 default:
3841 r = -EINVAL;
3842 }
3843 out:
3844 kfree(u.buffer);
3845 return r;
3846 }
3847
3848 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3849 {
3850 return VM_FAULT_SIGBUS;
3851 }
3852
3853 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3854 {
3855 int ret;
3856
3857 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3858 return -EINVAL;
3859 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3860 return ret;
3861 }
3862
3863 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3864 u64 ident_addr)
3865 {
3866 kvm->arch.ept_identity_map_addr = ident_addr;
3867 return 0;
3868 }
3869
3870 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3871 u32 kvm_nr_mmu_pages)
3872 {
3873 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3874 return -EINVAL;
3875
3876 mutex_lock(&kvm->slots_lock);
3877
3878 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3879 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3880
3881 mutex_unlock(&kvm->slots_lock);
3882 return 0;
3883 }
3884
3885 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3886 {
3887 return kvm->arch.n_max_mmu_pages;
3888 }
3889
3890 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3891 {
3892 struct kvm_pic *pic = kvm->arch.vpic;
3893 int r;
3894
3895 r = 0;
3896 switch (chip->chip_id) {
3897 case KVM_IRQCHIP_PIC_MASTER:
3898 memcpy(&chip->chip.pic, &pic->pics[0],
3899 sizeof(struct kvm_pic_state));
3900 break;
3901 case KVM_IRQCHIP_PIC_SLAVE:
3902 memcpy(&chip->chip.pic, &pic->pics[1],
3903 sizeof(struct kvm_pic_state));
3904 break;
3905 case KVM_IRQCHIP_IOAPIC:
3906 kvm_get_ioapic(kvm, &chip->chip.ioapic);
3907 break;
3908 default:
3909 r = -EINVAL;
3910 break;
3911 }
3912 return r;
3913 }
3914
3915 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3916 {
3917 struct kvm_pic *pic = kvm->arch.vpic;
3918 int r;
3919
3920 r = 0;
3921 switch (chip->chip_id) {
3922 case KVM_IRQCHIP_PIC_MASTER:
3923 spin_lock(&pic->lock);
3924 memcpy(&pic->pics[0], &chip->chip.pic,
3925 sizeof(struct kvm_pic_state));
3926 spin_unlock(&pic->lock);
3927 break;
3928 case KVM_IRQCHIP_PIC_SLAVE:
3929 spin_lock(&pic->lock);
3930 memcpy(&pic->pics[1], &chip->chip.pic,
3931 sizeof(struct kvm_pic_state));
3932 spin_unlock(&pic->lock);
3933 break;
3934 case KVM_IRQCHIP_IOAPIC:
3935 kvm_set_ioapic(kvm, &chip->chip.ioapic);
3936 break;
3937 default:
3938 r = -EINVAL;
3939 break;
3940 }
3941 kvm_pic_update_irq(pic);
3942 return r;
3943 }
3944
3945 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3946 {
3947 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3948
3949 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3950
3951 mutex_lock(&kps->lock);
3952 memcpy(ps, &kps->channels, sizeof(*ps));
3953 mutex_unlock(&kps->lock);
3954 return 0;
3955 }
3956
3957 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3958 {
3959 int i;
3960 struct kvm_pit *pit = kvm->arch.vpit;
3961
3962 mutex_lock(&pit->pit_state.lock);
3963 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3964 for (i = 0; i < 3; i++)
3965 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3966 mutex_unlock(&pit->pit_state.lock);
3967 return 0;
3968 }
3969
3970 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3971 {
3972 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3973 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3974 sizeof(ps->channels));
3975 ps->flags = kvm->arch.vpit->pit_state.flags;
3976 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3977 memset(&ps->reserved, 0, sizeof(ps->reserved));
3978 return 0;
3979 }
3980
3981 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3982 {
3983 int start = 0;
3984 int i;
3985 u32 prev_legacy, cur_legacy;
3986 struct kvm_pit *pit = kvm->arch.vpit;
3987
3988 mutex_lock(&pit->pit_state.lock);
3989 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3990 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3991 if (!prev_legacy && cur_legacy)
3992 start = 1;
3993 memcpy(&pit->pit_state.channels, &ps->channels,
3994 sizeof(pit->pit_state.channels));
3995 pit->pit_state.flags = ps->flags;
3996 for (i = 0; i < 3; i++)
3997 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3998 start && i == 0);
3999 mutex_unlock(&pit->pit_state.lock);
4000 return 0;
4001 }
4002
4003 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4004 struct kvm_reinject_control *control)
4005 {
4006 struct kvm_pit *pit = kvm->arch.vpit;
4007
4008 if (!pit)
4009 return -ENXIO;
4010
4011 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4012 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4013 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4014 */
4015 mutex_lock(&pit->pit_state.lock);
4016 kvm_pit_set_reinject(pit, control->pit_reinject);
4017 mutex_unlock(&pit->pit_state.lock);
4018
4019 return 0;
4020 }
4021
4022 /**
4023 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4024 * @kvm: kvm instance
4025 * @log: slot id and address to which we copy the log
4026 *
4027 * Steps 1-4 below provide general overview of dirty page logging. See
4028 * kvm_get_dirty_log_protect() function description for additional details.
4029 *
4030 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4031 * always flush the TLB (step 4) even if previous step failed and the dirty
4032 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4033 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4034 * writes will be marked dirty for next log read.
4035 *
4036 * 1. Take a snapshot of the bit and clear it if needed.
4037 * 2. Write protect the corresponding page.
4038 * 3. Copy the snapshot to the userspace.
4039 * 4. Flush TLB's if needed.
4040 */
4041 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4042 {
4043 bool is_dirty = false;
4044 int r;
4045
4046 mutex_lock(&kvm->slots_lock);
4047
4048 /*
4049 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4050 */
4051 if (kvm_x86_ops->flush_log_dirty)
4052 kvm_x86_ops->flush_log_dirty(kvm);
4053
4054 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
4055
4056 /*
4057 * All the TLBs can be flushed out of mmu lock, see the comments in
4058 * kvm_mmu_slot_remove_write_access().
4059 */
4060 lockdep_assert_held(&kvm->slots_lock);
4061 if (is_dirty)
4062 kvm_flush_remote_tlbs(kvm);
4063
4064 mutex_unlock(&kvm->slots_lock);
4065 return r;
4066 }
4067
4068 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4069 bool line_status)
4070 {
4071 if (!irqchip_in_kernel(kvm))
4072 return -ENXIO;
4073
4074 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4075 irq_event->irq, irq_event->level,
4076 line_status);
4077 return 0;
4078 }
4079
4080 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4081 struct kvm_enable_cap *cap)
4082 {
4083 int r;
4084
4085 if (cap->flags)
4086 return -EINVAL;
4087
4088 switch (cap->cap) {
4089 case KVM_CAP_DISABLE_QUIRKS:
4090 kvm->arch.disabled_quirks = cap->args[0];
4091 r = 0;
4092 break;
4093 case KVM_CAP_SPLIT_IRQCHIP: {
4094 mutex_lock(&kvm->lock);
4095 r = -EINVAL;
4096 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4097 goto split_irqchip_unlock;
4098 r = -EEXIST;
4099 if (irqchip_in_kernel(kvm))
4100 goto split_irqchip_unlock;
4101 if (kvm->created_vcpus)
4102 goto split_irqchip_unlock;
4103 r = kvm_setup_empty_irq_routing(kvm);
4104 if (r)
4105 goto split_irqchip_unlock;
4106 /* Pairs with irqchip_in_kernel. */
4107 smp_wmb();
4108 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4109 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4110 r = 0;
4111 split_irqchip_unlock:
4112 mutex_unlock(&kvm->lock);
4113 break;
4114 }
4115 case KVM_CAP_X2APIC_API:
4116 r = -EINVAL;
4117 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4118 break;
4119
4120 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4121 kvm->arch.x2apic_format = true;
4122 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4123 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4124
4125 r = 0;
4126 break;
4127 default:
4128 r = -EINVAL;
4129 break;
4130 }
4131 return r;
4132 }
4133
4134 long kvm_arch_vm_ioctl(struct file *filp,
4135 unsigned int ioctl, unsigned long arg)
4136 {
4137 struct kvm *kvm = filp->private_data;
4138 void __user *argp = (void __user *)arg;
4139 int r = -ENOTTY;
4140 /*
4141 * This union makes it completely explicit to gcc-3.x
4142 * that these two variables' stack usage should be
4143 * combined, not added together.
4144 */
4145 union {
4146 struct kvm_pit_state ps;
4147 struct kvm_pit_state2 ps2;
4148 struct kvm_pit_config pit_config;
4149 } u;
4150
4151 switch (ioctl) {
4152 case KVM_SET_TSS_ADDR:
4153 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4154 break;
4155 case KVM_SET_IDENTITY_MAP_ADDR: {
4156 u64 ident_addr;
4157
4158 mutex_lock(&kvm->lock);
4159 r = -EINVAL;
4160 if (kvm->created_vcpus)
4161 goto set_identity_unlock;
4162 r = -EFAULT;
4163 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4164 goto set_identity_unlock;
4165 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4166 set_identity_unlock:
4167 mutex_unlock(&kvm->lock);
4168 break;
4169 }
4170 case KVM_SET_NR_MMU_PAGES:
4171 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4172 break;
4173 case KVM_GET_NR_MMU_PAGES:
4174 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4175 break;
4176 case KVM_CREATE_IRQCHIP: {
4177 mutex_lock(&kvm->lock);
4178
4179 r = -EEXIST;
4180 if (irqchip_in_kernel(kvm))
4181 goto create_irqchip_unlock;
4182
4183 r = -EINVAL;
4184 if (kvm->created_vcpus)
4185 goto create_irqchip_unlock;
4186
4187 r = kvm_pic_init(kvm);
4188 if (r)
4189 goto create_irqchip_unlock;
4190
4191 r = kvm_ioapic_init(kvm);
4192 if (r) {
4193 kvm_pic_destroy(kvm);
4194 goto create_irqchip_unlock;
4195 }
4196
4197 r = kvm_setup_default_irq_routing(kvm);
4198 if (r) {
4199 kvm_ioapic_destroy(kvm);
4200 kvm_pic_destroy(kvm);
4201 goto create_irqchip_unlock;
4202 }
4203 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4204 smp_wmb();
4205 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4206 create_irqchip_unlock:
4207 mutex_unlock(&kvm->lock);
4208 break;
4209 }
4210 case KVM_CREATE_PIT:
4211 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4212 goto create_pit;
4213 case KVM_CREATE_PIT2:
4214 r = -EFAULT;
4215 if (copy_from_user(&u.pit_config, argp,
4216 sizeof(struct kvm_pit_config)))
4217 goto out;
4218 create_pit:
4219 mutex_lock(&kvm->lock);
4220 r = -EEXIST;
4221 if (kvm->arch.vpit)
4222 goto create_pit_unlock;
4223 r = -ENOMEM;
4224 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4225 if (kvm->arch.vpit)
4226 r = 0;
4227 create_pit_unlock:
4228 mutex_unlock(&kvm->lock);
4229 break;
4230 case KVM_GET_IRQCHIP: {
4231 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4232 struct kvm_irqchip *chip;
4233
4234 chip = memdup_user(argp, sizeof(*chip));
4235 if (IS_ERR(chip)) {
4236 r = PTR_ERR(chip);
4237 goto out;
4238 }
4239
4240 r = -ENXIO;
4241 if (!irqchip_kernel(kvm))
4242 goto get_irqchip_out;
4243 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4244 if (r)
4245 goto get_irqchip_out;
4246 r = -EFAULT;
4247 if (copy_to_user(argp, chip, sizeof *chip))
4248 goto get_irqchip_out;
4249 r = 0;
4250 get_irqchip_out:
4251 kfree(chip);
4252 break;
4253 }
4254 case KVM_SET_IRQCHIP: {
4255 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4256 struct kvm_irqchip *chip;
4257
4258 chip = memdup_user(argp, sizeof(*chip));
4259 if (IS_ERR(chip)) {
4260 r = PTR_ERR(chip);
4261 goto out;
4262 }
4263
4264 r = -ENXIO;
4265 if (!irqchip_kernel(kvm))
4266 goto set_irqchip_out;
4267 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4268 if (r)
4269 goto set_irqchip_out;
4270 r = 0;
4271 set_irqchip_out:
4272 kfree(chip);
4273 break;
4274 }
4275 case KVM_GET_PIT: {
4276 r = -EFAULT;
4277 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4278 goto out;
4279 r = -ENXIO;
4280 if (!kvm->arch.vpit)
4281 goto out;
4282 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4283 if (r)
4284 goto out;
4285 r = -EFAULT;
4286 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4287 goto out;
4288 r = 0;
4289 break;
4290 }
4291 case KVM_SET_PIT: {
4292 r = -EFAULT;
4293 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4294 goto out;
4295 r = -ENXIO;
4296 if (!kvm->arch.vpit)
4297 goto out;
4298 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4299 break;
4300 }
4301 case KVM_GET_PIT2: {
4302 r = -ENXIO;
4303 if (!kvm->arch.vpit)
4304 goto out;
4305 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4306 if (r)
4307 goto out;
4308 r = -EFAULT;
4309 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4310 goto out;
4311 r = 0;
4312 break;
4313 }
4314 case KVM_SET_PIT2: {
4315 r = -EFAULT;
4316 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4317 goto out;
4318 r = -ENXIO;
4319 if (!kvm->arch.vpit)
4320 goto out;
4321 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4322 break;
4323 }
4324 case KVM_REINJECT_CONTROL: {
4325 struct kvm_reinject_control control;
4326 r = -EFAULT;
4327 if (copy_from_user(&control, argp, sizeof(control)))
4328 goto out;
4329 r = kvm_vm_ioctl_reinject(kvm, &control);
4330 break;
4331 }
4332 case KVM_SET_BOOT_CPU_ID:
4333 r = 0;
4334 mutex_lock(&kvm->lock);
4335 if (kvm->created_vcpus)
4336 r = -EBUSY;
4337 else
4338 kvm->arch.bsp_vcpu_id = arg;
4339 mutex_unlock(&kvm->lock);
4340 break;
4341 case KVM_XEN_HVM_CONFIG: {
4342 struct kvm_xen_hvm_config xhc;
4343 r = -EFAULT;
4344 if (copy_from_user(&xhc, argp, sizeof(xhc)))
4345 goto out;
4346 r = -EINVAL;
4347 if (xhc.flags)
4348 goto out;
4349 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4350 r = 0;
4351 break;
4352 }
4353 case KVM_SET_CLOCK: {
4354 struct kvm_clock_data user_ns;
4355 u64 now_ns;
4356
4357 r = -EFAULT;
4358 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4359 goto out;
4360
4361 r = -EINVAL;
4362 if (user_ns.flags)
4363 goto out;
4364
4365 r = 0;
4366 /*
4367 * TODO: userspace has to take care of races with VCPU_RUN, so
4368 * kvm_gen_update_masterclock() can be cut down to locked
4369 * pvclock_update_vm_gtod_copy().
4370 */
4371 kvm_gen_update_masterclock(kvm);
4372 now_ns = get_kvmclock_ns(kvm);
4373 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4374 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4375 break;
4376 }
4377 case KVM_GET_CLOCK: {
4378 struct kvm_clock_data user_ns;
4379 u64 now_ns;
4380
4381 now_ns = get_kvmclock_ns(kvm);
4382 user_ns.clock = now_ns;
4383 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4384 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4385
4386 r = -EFAULT;
4387 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4388 goto out;
4389 r = 0;
4390 break;
4391 }
4392 case KVM_ENABLE_CAP: {
4393 struct kvm_enable_cap cap;
4394
4395 r = -EFAULT;
4396 if (copy_from_user(&cap, argp, sizeof(cap)))
4397 goto out;
4398 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4399 break;
4400 }
4401 default:
4402 r = -ENOTTY;
4403 }
4404 out:
4405 return r;
4406 }
4407
4408 static void kvm_init_msr_list(void)
4409 {
4410 u32 dummy[2];
4411 unsigned i, j;
4412
4413 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4414 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4415 continue;
4416
4417 /*
4418 * Even MSRs that are valid in the host may not be exposed
4419 * to the guests in some cases.
4420 */
4421 switch (msrs_to_save[i]) {
4422 case MSR_IA32_BNDCFGS:
4423 if (!kvm_x86_ops->mpx_supported())
4424 continue;
4425 break;
4426 case MSR_TSC_AUX:
4427 if (!kvm_x86_ops->rdtscp_supported())
4428 continue;
4429 break;
4430 default:
4431 break;
4432 }
4433
4434 if (j < i)
4435 msrs_to_save[j] = msrs_to_save[i];
4436 j++;
4437 }
4438 num_msrs_to_save = j;
4439
4440 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4441 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4442 continue;
4443
4444 if (j < i)
4445 emulated_msrs[j] = emulated_msrs[i];
4446 j++;
4447 }
4448 num_emulated_msrs = j;
4449
4450 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4451 struct kvm_msr_entry msr;
4452
4453 msr.index = msr_based_features[i];
4454 if (kvm_get_msr_feature(&msr))
4455 continue;
4456
4457 if (j < i)
4458 msr_based_features[j] = msr_based_features[i];
4459 j++;
4460 }
4461 num_msr_based_features = j;
4462 }
4463
4464 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4465 const void *v)
4466 {
4467 int handled = 0;
4468 int n;
4469
4470 do {
4471 n = min(len, 8);
4472 if (!(lapic_in_kernel(vcpu) &&
4473 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4474 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4475 break;
4476 handled += n;
4477 addr += n;
4478 len -= n;
4479 v += n;
4480 } while (len);
4481
4482 return handled;
4483 }
4484
4485 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4486 {
4487 int handled = 0;
4488 int n;
4489
4490 do {
4491 n = min(len, 8);
4492 if (!(lapic_in_kernel(vcpu) &&
4493 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4494 addr, n, v))
4495 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4496 break;
4497 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4498 handled += n;
4499 addr += n;
4500 len -= n;
4501 v += n;
4502 } while (len);
4503
4504 return handled;
4505 }
4506
4507 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4508 struct kvm_segment *var, int seg)
4509 {
4510 kvm_x86_ops->set_segment(vcpu, var, seg);
4511 }
4512
4513 void kvm_get_segment(struct kvm_vcpu *vcpu,
4514 struct kvm_segment *var, int seg)
4515 {
4516 kvm_x86_ops->get_segment(vcpu, var, seg);
4517 }
4518
4519 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4520 struct x86_exception *exception)
4521 {
4522 gpa_t t_gpa;
4523
4524 BUG_ON(!mmu_is_nested(vcpu));
4525
4526 /* NPT walks are always user-walks */
4527 access |= PFERR_USER_MASK;
4528 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4529
4530 return t_gpa;
4531 }
4532
4533 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4534 struct x86_exception *exception)
4535 {
4536 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4537 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4538 }
4539
4540 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4541 struct x86_exception *exception)
4542 {
4543 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4544 access |= PFERR_FETCH_MASK;
4545 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4546 }
4547
4548 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4549 struct x86_exception *exception)
4550 {
4551 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4552 access |= PFERR_WRITE_MASK;
4553 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4554 }
4555
4556 /* uses this to access any guest's mapped memory without checking CPL */
4557 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4558 struct x86_exception *exception)
4559 {
4560 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4561 }
4562
4563 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4564 struct kvm_vcpu *vcpu, u32 access,
4565 struct x86_exception *exception)
4566 {
4567 void *data = val;
4568 int r = X86EMUL_CONTINUE;
4569
4570 while (bytes) {
4571 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4572 exception);
4573 unsigned offset = addr & (PAGE_SIZE-1);
4574 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4575 int ret;
4576
4577 if (gpa == UNMAPPED_GVA)
4578 return X86EMUL_PROPAGATE_FAULT;
4579 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4580 offset, toread);
4581 if (ret < 0) {
4582 r = X86EMUL_IO_NEEDED;
4583 goto out;
4584 }
4585
4586 bytes -= toread;
4587 data += toread;
4588 addr += toread;
4589 }
4590 out:
4591 return r;
4592 }
4593
4594 /* used for instruction fetching */
4595 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4596 gva_t addr, void *val, unsigned int bytes,
4597 struct x86_exception *exception)
4598 {
4599 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4600 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4601 unsigned offset;
4602 int ret;
4603
4604 /* Inline kvm_read_guest_virt_helper for speed. */
4605 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4606 exception);
4607 if (unlikely(gpa == UNMAPPED_GVA))
4608 return X86EMUL_PROPAGATE_FAULT;
4609
4610 offset = addr & (PAGE_SIZE-1);
4611 if (WARN_ON(offset + bytes > PAGE_SIZE))
4612 bytes = (unsigned)PAGE_SIZE - offset;
4613 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4614 offset, bytes);
4615 if (unlikely(ret < 0))
4616 return X86EMUL_IO_NEEDED;
4617
4618 return X86EMUL_CONTINUE;
4619 }
4620
4621 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
4622 gva_t addr, void *val, unsigned int bytes,
4623 struct x86_exception *exception)
4624 {
4625 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4626
4627 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4628 exception);
4629 }
4630 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4631
4632 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4633 gva_t addr, void *val, unsigned int bytes,
4634 struct x86_exception *exception, bool system)
4635 {
4636 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4637 u32 access = 0;
4638
4639 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4640 access |= PFERR_USER_MASK;
4641
4642 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
4643 }
4644
4645 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4646 unsigned long addr, void *val, unsigned int bytes)
4647 {
4648 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4649 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4650
4651 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4652 }
4653
4654 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4655 struct kvm_vcpu *vcpu, u32 access,
4656 struct x86_exception *exception)
4657 {
4658 void *data = val;
4659 int r = X86EMUL_CONTINUE;
4660
4661 /* kvm_write_guest_virt_system can pull in tons of pages. */
4662 vcpu->arch.l1tf_flush_l1d = true;
4663
4664 while (bytes) {
4665 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4666 access,
4667 exception);
4668 unsigned offset = addr & (PAGE_SIZE-1);
4669 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4670 int ret;
4671
4672 if (gpa == UNMAPPED_GVA)
4673 return X86EMUL_PROPAGATE_FAULT;
4674 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4675 if (ret < 0) {
4676 r = X86EMUL_IO_NEEDED;
4677 goto out;
4678 }
4679
4680 bytes -= towrite;
4681 data += towrite;
4682 addr += towrite;
4683 }
4684 out:
4685 return r;
4686 }
4687
4688 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
4689 unsigned int bytes, struct x86_exception *exception,
4690 bool system)
4691 {
4692 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4693 u32 access = PFERR_WRITE_MASK;
4694
4695 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4696 access |= PFERR_USER_MASK;
4697
4698 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4699 access, exception);
4700 }
4701
4702 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4703 unsigned int bytes, struct x86_exception *exception)
4704 {
4705 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4706 PFERR_WRITE_MASK, exception);
4707 }
4708 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4709
4710 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4711 gpa_t gpa, bool write)
4712 {
4713 /* For APIC access vmexit */
4714 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4715 return 1;
4716
4717 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4718 trace_vcpu_match_mmio(gva, gpa, write, true);
4719 return 1;
4720 }
4721
4722 return 0;
4723 }
4724
4725 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4726 gpa_t *gpa, struct x86_exception *exception,
4727 bool write)
4728 {
4729 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4730 | (write ? PFERR_WRITE_MASK : 0);
4731
4732 /*
4733 * currently PKRU is only applied to ept enabled guest so
4734 * there is no pkey in EPT page table for L1 guest or EPT
4735 * shadow page table for L2 guest.
4736 */
4737 if (vcpu_match_mmio_gva(vcpu, gva)
4738 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4739 vcpu->arch.access, 0, access)) {
4740 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4741 (gva & (PAGE_SIZE - 1));
4742 trace_vcpu_match_mmio(gva, *gpa, write, false);
4743 return 1;
4744 }
4745
4746 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4747
4748 if (*gpa == UNMAPPED_GVA)
4749 return -1;
4750
4751 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4752 }
4753
4754 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4755 const void *val, int bytes)
4756 {
4757 int ret;
4758
4759 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4760 if (ret < 0)
4761 return 0;
4762 kvm_page_track_write(vcpu, gpa, val, bytes);
4763 return 1;
4764 }
4765
4766 struct read_write_emulator_ops {
4767 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4768 int bytes);
4769 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4770 void *val, int bytes);
4771 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4772 int bytes, void *val);
4773 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4774 void *val, int bytes);
4775 bool write;
4776 };
4777
4778 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4779 {
4780 if (vcpu->mmio_read_completed) {
4781 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4782 vcpu->mmio_fragments[0].gpa, val);
4783 vcpu->mmio_read_completed = 0;
4784 return 1;
4785 }
4786
4787 return 0;
4788 }
4789
4790 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4791 void *val, int bytes)
4792 {
4793 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4794 }
4795
4796 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4797 void *val, int bytes)
4798 {
4799 return emulator_write_phys(vcpu, gpa, val, bytes);
4800 }
4801
4802 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4803 {
4804 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
4805 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4806 }
4807
4808 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4809 void *val, int bytes)
4810 {
4811 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
4812 return X86EMUL_IO_NEEDED;
4813 }
4814
4815 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4816 void *val, int bytes)
4817 {
4818 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4819
4820 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4821 return X86EMUL_CONTINUE;
4822 }
4823
4824 static const struct read_write_emulator_ops read_emultor = {
4825 .read_write_prepare = read_prepare,
4826 .read_write_emulate = read_emulate,
4827 .read_write_mmio = vcpu_mmio_read,
4828 .read_write_exit_mmio = read_exit_mmio,
4829 };
4830
4831 static const struct read_write_emulator_ops write_emultor = {
4832 .read_write_emulate = write_emulate,
4833 .read_write_mmio = write_mmio,
4834 .read_write_exit_mmio = write_exit_mmio,
4835 .write = true,
4836 };
4837
4838 static int emulator_read_write_onepage(unsigned long addr, void *val,
4839 unsigned int bytes,
4840 struct x86_exception *exception,
4841 struct kvm_vcpu *vcpu,
4842 const struct read_write_emulator_ops *ops)
4843 {
4844 gpa_t gpa;
4845 int handled, ret;
4846 bool write = ops->write;
4847 struct kvm_mmio_fragment *frag;
4848 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4849
4850 /*
4851 * If the exit was due to a NPF we may already have a GPA.
4852 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4853 * Note, this cannot be used on string operations since string
4854 * operation using rep will only have the initial GPA from the NPF
4855 * occurred.
4856 */
4857 if (vcpu->arch.gpa_available &&
4858 emulator_can_use_gpa(ctxt) &&
4859 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4860 gpa = vcpu->arch.gpa_val;
4861 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4862 } else {
4863 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4864 if (ret < 0)
4865 return X86EMUL_PROPAGATE_FAULT;
4866 }
4867
4868 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
4869 return X86EMUL_CONTINUE;
4870
4871 /*
4872 * Is this MMIO handled locally?
4873 */
4874 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4875 if (handled == bytes)
4876 return X86EMUL_CONTINUE;
4877
4878 gpa += handled;
4879 bytes -= handled;
4880 val += handled;
4881
4882 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4883 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4884 frag->gpa = gpa;
4885 frag->data = val;
4886 frag->len = bytes;
4887 return X86EMUL_CONTINUE;
4888 }
4889
4890 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4891 unsigned long addr,
4892 void *val, unsigned int bytes,
4893 struct x86_exception *exception,
4894 const struct read_write_emulator_ops *ops)
4895 {
4896 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4897 gpa_t gpa;
4898 int rc;
4899
4900 if (ops->read_write_prepare &&
4901 ops->read_write_prepare(vcpu, val, bytes))
4902 return X86EMUL_CONTINUE;
4903
4904 vcpu->mmio_nr_fragments = 0;
4905
4906 /* Crossing a page boundary? */
4907 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4908 int now;
4909
4910 now = -addr & ~PAGE_MASK;
4911 rc = emulator_read_write_onepage(addr, val, now, exception,
4912 vcpu, ops);
4913
4914 if (rc != X86EMUL_CONTINUE)
4915 return rc;
4916 addr += now;
4917 if (ctxt->mode != X86EMUL_MODE_PROT64)
4918 addr = (u32)addr;
4919 val += now;
4920 bytes -= now;
4921 }
4922
4923 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4924 vcpu, ops);
4925 if (rc != X86EMUL_CONTINUE)
4926 return rc;
4927
4928 if (!vcpu->mmio_nr_fragments)
4929 return rc;
4930
4931 gpa = vcpu->mmio_fragments[0].gpa;
4932
4933 vcpu->mmio_needed = 1;
4934 vcpu->mmio_cur_fragment = 0;
4935
4936 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4937 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4938 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4939 vcpu->run->mmio.phys_addr = gpa;
4940
4941 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4942 }
4943
4944 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4945 unsigned long addr,
4946 void *val,
4947 unsigned int bytes,
4948 struct x86_exception *exception)
4949 {
4950 return emulator_read_write(ctxt, addr, val, bytes,
4951 exception, &read_emultor);
4952 }
4953
4954 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4955 unsigned long addr,
4956 const void *val,
4957 unsigned int bytes,
4958 struct x86_exception *exception)
4959 {
4960 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4961 exception, &write_emultor);
4962 }
4963
4964 #define CMPXCHG_TYPE(t, ptr, old, new) \
4965 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4966
4967 #ifdef CONFIG_X86_64
4968 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4969 #else
4970 # define CMPXCHG64(ptr, old, new) \
4971 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4972 #endif
4973
4974 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4975 unsigned long addr,
4976 const void *old,
4977 const void *new,
4978 unsigned int bytes,
4979 struct x86_exception *exception)
4980 {
4981 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4982 gpa_t gpa;
4983 struct page *page;
4984 char *kaddr;
4985 bool exchanged;
4986
4987 /* guests cmpxchg8b have to be emulated atomically */
4988 if (bytes > 8 || (bytes & (bytes - 1)))
4989 goto emul_write;
4990
4991 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4992
4993 if (gpa == UNMAPPED_GVA ||
4994 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4995 goto emul_write;
4996
4997 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4998 goto emul_write;
4999
5000 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
5001 if (is_error_page(page))
5002 goto emul_write;
5003
5004 kaddr = kmap_atomic(page);
5005 kaddr += offset_in_page(gpa);
5006 switch (bytes) {
5007 case 1:
5008 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5009 break;
5010 case 2:
5011 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5012 break;
5013 case 4:
5014 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5015 break;
5016 case 8:
5017 exchanged = CMPXCHG64(kaddr, old, new);
5018 break;
5019 default:
5020 BUG();
5021 }
5022 kunmap_atomic(kaddr);
5023 kvm_release_page_dirty(page);
5024
5025 if (!exchanged)
5026 return X86EMUL_CMPXCHG_FAILED;
5027
5028 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5029 kvm_page_track_write(vcpu, gpa, new, bytes);
5030
5031 return X86EMUL_CONTINUE;
5032
5033 emul_write:
5034 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5035
5036 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5037 }
5038
5039 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5040 {
5041 int r = 0, i;
5042
5043 for (i = 0; i < vcpu->arch.pio.count; i++) {
5044 if (vcpu->arch.pio.in)
5045 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5046 vcpu->arch.pio.size, pd);
5047 else
5048 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5049 vcpu->arch.pio.port, vcpu->arch.pio.size,
5050 pd);
5051 if (r)
5052 break;
5053 pd += vcpu->arch.pio.size;
5054 }
5055 return r;
5056 }
5057
5058 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5059 unsigned short port, void *val,
5060 unsigned int count, bool in)
5061 {
5062 vcpu->arch.pio.port = port;
5063 vcpu->arch.pio.in = in;
5064 vcpu->arch.pio.count = count;
5065 vcpu->arch.pio.size = size;
5066
5067 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5068 vcpu->arch.pio.count = 0;
5069 return 1;
5070 }
5071
5072 vcpu->run->exit_reason = KVM_EXIT_IO;
5073 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5074 vcpu->run->io.size = size;
5075 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5076 vcpu->run->io.count = count;
5077 vcpu->run->io.port = port;
5078
5079 return 0;
5080 }
5081
5082 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5083 int size, unsigned short port, void *val,
5084 unsigned int count)
5085 {
5086 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5087 int ret;
5088
5089 if (vcpu->arch.pio.count)
5090 goto data_avail;
5091
5092 memset(vcpu->arch.pio_data, 0, size * count);
5093
5094 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5095 if (ret) {
5096 data_avail:
5097 memcpy(val, vcpu->arch.pio_data, size * count);
5098 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5099 vcpu->arch.pio.count = 0;
5100 return 1;
5101 }
5102
5103 return 0;
5104 }
5105
5106 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5107 int size, unsigned short port,
5108 const void *val, unsigned int count)
5109 {
5110 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5111
5112 memcpy(vcpu->arch.pio_data, val, size * count);
5113 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5114 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5115 }
5116
5117 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5118 {
5119 return kvm_x86_ops->get_segment_base(vcpu, seg);
5120 }
5121
5122 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5123 {
5124 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5125 }
5126
5127 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5128 {
5129 if (!need_emulate_wbinvd(vcpu))
5130 return X86EMUL_CONTINUE;
5131
5132 if (kvm_x86_ops->has_wbinvd_exit()) {
5133 int cpu = get_cpu();
5134
5135 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5136 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5137 wbinvd_ipi, NULL, 1);
5138 put_cpu();
5139 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5140 } else
5141 wbinvd();
5142 return X86EMUL_CONTINUE;
5143 }
5144
5145 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5146 {
5147 kvm_emulate_wbinvd_noskip(vcpu);
5148 return kvm_skip_emulated_instruction(vcpu);
5149 }
5150 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5151
5152
5153
5154 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5155 {
5156 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5157 }
5158
5159 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5160 unsigned long *dest)
5161 {
5162 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5163 }
5164
5165 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5166 unsigned long value)
5167 {
5168
5169 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5170 }
5171
5172 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5173 {
5174 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5175 }
5176
5177 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5178 {
5179 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5180 unsigned long value;
5181
5182 switch (cr) {
5183 case 0:
5184 value = kvm_read_cr0(vcpu);
5185 break;
5186 case 2:
5187 value = vcpu->arch.cr2;
5188 break;
5189 case 3:
5190 value = kvm_read_cr3(vcpu);
5191 break;
5192 case 4:
5193 value = kvm_read_cr4(vcpu);
5194 break;
5195 case 8:
5196 value = kvm_get_cr8(vcpu);
5197 break;
5198 default:
5199 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5200 return 0;
5201 }
5202
5203 return value;
5204 }
5205
5206 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5207 {
5208 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5209 int res = 0;
5210
5211 switch (cr) {
5212 case 0:
5213 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5214 break;
5215 case 2:
5216 vcpu->arch.cr2 = val;
5217 break;
5218 case 3:
5219 res = kvm_set_cr3(vcpu, val);
5220 break;
5221 case 4:
5222 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5223 break;
5224 case 8:
5225 res = kvm_set_cr8(vcpu, val);
5226 break;
5227 default:
5228 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5229 res = -1;
5230 }
5231
5232 return res;
5233 }
5234
5235 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5236 {
5237 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5238 }
5239
5240 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5241 {
5242 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5243 }
5244
5245 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5246 {
5247 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5248 }
5249
5250 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5251 {
5252 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5253 }
5254
5255 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5256 {
5257 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5258 }
5259
5260 static unsigned long emulator_get_cached_segment_base(
5261 struct x86_emulate_ctxt *ctxt, int seg)
5262 {
5263 return get_segment_base(emul_to_vcpu(ctxt), seg);
5264 }
5265
5266 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5267 struct desc_struct *desc, u32 *base3,
5268 int seg)
5269 {
5270 struct kvm_segment var;
5271
5272 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5273 *selector = var.selector;
5274
5275 if (var.unusable) {
5276 memset(desc, 0, sizeof(*desc));
5277 if (base3)
5278 *base3 = 0;
5279 return false;
5280 }
5281
5282 if (var.g)
5283 var.limit >>= 12;
5284 set_desc_limit(desc, var.limit);
5285 set_desc_base(desc, (unsigned long)var.base);
5286 #ifdef CONFIG_X86_64
5287 if (base3)
5288 *base3 = var.base >> 32;
5289 #endif
5290 desc->type = var.type;
5291 desc->s = var.s;
5292 desc->dpl = var.dpl;
5293 desc->p = var.present;
5294 desc->avl = var.avl;
5295 desc->l = var.l;
5296 desc->d = var.db;
5297 desc->g = var.g;
5298
5299 return true;
5300 }
5301
5302 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5303 struct desc_struct *desc, u32 base3,
5304 int seg)
5305 {
5306 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5307 struct kvm_segment var;
5308
5309 var.selector = selector;
5310 var.base = get_desc_base(desc);
5311 #ifdef CONFIG_X86_64
5312 var.base |= ((u64)base3) << 32;
5313 #endif
5314 var.limit = get_desc_limit(desc);
5315 if (desc->g)
5316 var.limit = (var.limit << 12) | 0xfff;
5317 var.type = desc->type;
5318 var.dpl = desc->dpl;
5319 var.db = desc->d;
5320 var.s = desc->s;
5321 var.l = desc->l;
5322 var.g = desc->g;
5323 var.avl = desc->avl;
5324 var.present = desc->p;
5325 var.unusable = !var.present;
5326 var.padding = 0;
5327
5328 kvm_set_segment(vcpu, &var, seg);
5329 return;
5330 }
5331
5332 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5333 u32 msr_index, u64 *pdata)
5334 {
5335 struct msr_data msr;
5336 int r;
5337
5338 msr.index = msr_index;
5339 msr.host_initiated = false;
5340 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5341 if (r)
5342 return r;
5343
5344 *pdata = msr.data;
5345 return 0;
5346 }
5347
5348 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5349 u32 msr_index, u64 data)
5350 {
5351 struct msr_data msr;
5352
5353 msr.data = data;
5354 msr.index = msr_index;
5355 msr.host_initiated = false;
5356 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5357 }
5358
5359 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5360 {
5361 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5362
5363 return vcpu->arch.smbase;
5364 }
5365
5366 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5367 {
5368 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5369
5370 vcpu->arch.smbase = smbase;
5371 }
5372
5373 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5374 u32 pmc)
5375 {
5376 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5377 }
5378
5379 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5380 u32 pmc, u64 *pdata)
5381 {
5382 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5383 }
5384
5385 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5386 {
5387 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5388 }
5389
5390 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5391 struct x86_instruction_info *info,
5392 enum x86_intercept_stage stage)
5393 {
5394 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5395 }
5396
5397 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5398 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5399 {
5400 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5401 }
5402
5403 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5404 {
5405 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5406 }
5407
5408 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5409 {
5410 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5411 }
5412
5413 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5414 {
5415 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5416 }
5417
5418 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5419 {
5420 return emul_to_vcpu(ctxt)->arch.hflags;
5421 }
5422
5423 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5424 {
5425 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5426 }
5427
5428 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5429 {
5430 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5431 }
5432
5433 static const struct x86_emulate_ops emulate_ops = {
5434 .read_gpr = emulator_read_gpr,
5435 .write_gpr = emulator_write_gpr,
5436 .read_std = emulator_read_std,
5437 .write_std = emulator_write_std,
5438 .read_phys = kvm_read_guest_phys_system,
5439 .fetch = kvm_fetch_guest_virt,
5440 .read_emulated = emulator_read_emulated,
5441 .write_emulated = emulator_write_emulated,
5442 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5443 .invlpg = emulator_invlpg,
5444 .pio_in_emulated = emulator_pio_in_emulated,
5445 .pio_out_emulated = emulator_pio_out_emulated,
5446 .get_segment = emulator_get_segment,
5447 .set_segment = emulator_set_segment,
5448 .get_cached_segment_base = emulator_get_cached_segment_base,
5449 .get_gdt = emulator_get_gdt,
5450 .get_idt = emulator_get_idt,
5451 .set_gdt = emulator_set_gdt,
5452 .set_idt = emulator_set_idt,
5453 .get_cr = emulator_get_cr,
5454 .set_cr = emulator_set_cr,
5455 .cpl = emulator_get_cpl,
5456 .get_dr = emulator_get_dr,
5457 .set_dr = emulator_set_dr,
5458 .get_smbase = emulator_get_smbase,
5459 .set_smbase = emulator_set_smbase,
5460 .set_msr = emulator_set_msr,
5461 .get_msr = emulator_get_msr,
5462 .check_pmc = emulator_check_pmc,
5463 .read_pmc = emulator_read_pmc,
5464 .halt = emulator_halt,
5465 .wbinvd = emulator_wbinvd,
5466 .fix_hypercall = emulator_fix_hypercall,
5467 .intercept = emulator_intercept,
5468 .get_cpuid = emulator_get_cpuid,
5469 .set_nmi_mask = emulator_set_nmi_mask,
5470 .get_hflags = emulator_get_hflags,
5471 .set_hflags = emulator_set_hflags,
5472 .pre_leave_smm = emulator_pre_leave_smm,
5473 };
5474
5475 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5476 {
5477 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5478 /*
5479 * an sti; sti; sequence only disable interrupts for the first
5480 * instruction. So, if the last instruction, be it emulated or
5481 * not, left the system with the INT_STI flag enabled, it
5482 * means that the last instruction is an sti. We should not
5483 * leave the flag on in this case. The same goes for mov ss
5484 */
5485 if (int_shadow & mask)
5486 mask = 0;
5487 if (unlikely(int_shadow || mask)) {
5488 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5489 if (!mask)
5490 kvm_make_request(KVM_REQ_EVENT, vcpu);
5491 }
5492 }
5493
5494 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5495 {
5496 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5497 if (ctxt->exception.vector == PF_VECTOR)
5498 return kvm_propagate_fault(vcpu, &ctxt->exception);
5499
5500 if (ctxt->exception.error_code_valid)
5501 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5502 ctxt->exception.error_code);
5503 else
5504 kvm_queue_exception(vcpu, ctxt->exception.vector);
5505 return false;
5506 }
5507
5508 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5509 {
5510 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5511 int cs_db, cs_l;
5512
5513 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5514
5515 ctxt->eflags = kvm_get_rflags(vcpu);
5516 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5517
5518 ctxt->eip = kvm_rip_read(vcpu);
5519 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5520 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5521 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5522 cs_db ? X86EMUL_MODE_PROT32 :
5523 X86EMUL_MODE_PROT16;
5524 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5525 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5526 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5527
5528 init_decode_cache(ctxt);
5529 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5530 }
5531
5532 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5533 {
5534 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5535 int ret;
5536
5537 init_emulate_ctxt(vcpu);
5538
5539 ctxt->op_bytes = 2;
5540 ctxt->ad_bytes = 2;
5541 ctxt->_eip = ctxt->eip + inc_eip;
5542 ret = emulate_int_real(ctxt, irq);
5543
5544 if (ret != X86EMUL_CONTINUE)
5545 return EMULATE_FAIL;
5546
5547 ctxt->eip = ctxt->_eip;
5548 kvm_rip_write(vcpu, ctxt->eip);
5549 kvm_set_rflags(vcpu, ctxt->eflags);
5550
5551 if (irq == NMI_VECTOR)
5552 vcpu->arch.nmi_pending = 0;
5553 else
5554 vcpu->arch.interrupt.pending = false;
5555
5556 return EMULATE_DONE;
5557 }
5558 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5559
5560 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5561 {
5562 int r = EMULATE_DONE;
5563
5564 ++vcpu->stat.insn_emulation_fail;
5565 trace_kvm_emulate_insn_failed(vcpu);
5566 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5567 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5568 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5569 vcpu->run->internal.ndata = 0;
5570 r = EMULATE_USER_EXIT;
5571 }
5572 kvm_queue_exception(vcpu, UD_VECTOR);
5573
5574 return r;
5575 }
5576
5577 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5578 bool write_fault_to_shadow_pgtable,
5579 int emulation_type)
5580 {
5581 gpa_t gpa = cr2;
5582 kvm_pfn_t pfn;
5583
5584 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5585 return false;
5586
5587 if (!vcpu->arch.mmu.direct_map) {
5588 /*
5589 * Write permission should be allowed since only
5590 * write access need to be emulated.
5591 */
5592 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5593
5594 /*
5595 * If the mapping is invalid in guest, let cpu retry
5596 * it to generate fault.
5597 */
5598 if (gpa == UNMAPPED_GVA)
5599 return true;
5600 }
5601
5602 /*
5603 * Do not retry the unhandleable instruction if it faults on the
5604 * readonly host memory, otherwise it will goto a infinite loop:
5605 * retry instruction -> write #PF -> emulation fail -> retry
5606 * instruction -> ...
5607 */
5608 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5609
5610 /*
5611 * If the instruction failed on the error pfn, it can not be fixed,
5612 * report the error to userspace.
5613 */
5614 if (is_error_noslot_pfn(pfn))
5615 return false;
5616
5617 kvm_release_pfn_clean(pfn);
5618
5619 /* The instructions are well-emulated on direct mmu. */
5620 if (vcpu->arch.mmu.direct_map) {
5621 unsigned int indirect_shadow_pages;
5622
5623 spin_lock(&vcpu->kvm->mmu_lock);
5624 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5625 spin_unlock(&vcpu->kvm->mmu_lock);
5626
5627 if (indirect_shadow_pages)
5628 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5629
5630 return true;
5631 }
5632
5633 /*
5634 * if emulation was due to access to shadowed page table
5635 * and it failed try to unshadow page and re-enter the
5636 * guest to let CPU execute the instruction.
5637 */
5638 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5639
5640 /*
5641 * If the access faults on its page table, it can not
5642 * be fixed by unprotecting shadow page and it should
5643 * be reported to userspace.
5644 */
5645 return !write_fault_to_shadow_pgtable;
5646 }
5647
5648 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5649 unsigned long cr2, int emulation_type)
5650 {
5651 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5652 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5653
5654 last_retry_eip = vcpu->arch.last_retry_eip;
5655 last_retry_addr = vcpu->arch.last_retry_addr;
5656
5657 /*
5658 * If the emulation is caused by #PF and it is non-page_table
5659 * writing instruction, it means the VM-EXIT is caused by shadow
5660 * page protected, we can zap the shadow page and retry this
5661 * instruction directly.
5662 *
5663 * Note: if the guest uses a non-page-table modifying instruction
5664 * on the PDE that points to the instruction, then we will unmap
5665 * the instruction and go to an infinite loop. So, we cache the
5666 * last retried eip and the last fault address, if we meet the eip
5667 * and the address again, we can break out of the potential infinite
5668 * loop.
5669 */
5670 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5671
5672 if (!(emulation_type & EMULTYPE_RETRY))
5673 return false;
5674
5675 if (x86_page_table_writing_insn(ctxt))
5676 return false;
5677
5678 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5679 return false;
5680
5681 vcpu->arch.last_retry_eip = ctxt->eip;
5682 vcpu->arch.last_retry_addr = cr2;
5683
5684 if (!vcpu->arch.mmu.direct_map)
5685 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5686
5687 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5688
5689 return true;
5690 }
5691
5692 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5693 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5694
5695 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5696 {
5697 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5698 /* This is a good place to trace that we are exiting SMM. */
5699 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5700
5701 /* Process a latched INIT or SMI, if any. */
5702 kvm_make_request(KVM_REQ_EVENT, vcpu);
5703 }
5704
5705 kvm_mmu_reset_context(vcpu);
5706 }
5707
5708 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5709 {
5710 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5711
5712 vcpu->arch.hflags = emul_flags;
5713
5714 if (changed & HF_SMM_MASK)
5715 kvm_smm_changed(vcpu);
5716 }
5717
5718 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5719 unsigned long *db)
5720 {
5721 u32 dr6 = 0;
5722 int i;
5723 u32 enable, rwlen;
5724
5725 enable = dr7;
5726 rwlen = dr7 >> 16;
5727 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5728 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5729 dr6 |= (1 << i);
5730 return dr6;
5731 }
5732
5733 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
5734 {
5735 struct kvm_run *kvm_run = vcpu->run;
5736
5737 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5738 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5739 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5740 kvm_run->debug.arch.exception = DB_VECTOR;
5741 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5742 *r = EMULATE_USER_EXIT;
5743 } else {
5744 /*
5745 * "Certain debug exceptions may clear bit 0-3. The
5746 * remaining contents of the DR6 register are never
5747 * cleared by the processor".
5748 */
5749 vcpu->arch.dr6 &= ~15;
5750 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5751 kvm_queue_exception(vcpu, DB_VECTOR);
5752 }
5753 }
5754
5755 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5756 {
5757 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5758 int r = EMULATE_DONE;
5759
5760 kvm_x86_ops->skip_emulated_instruction(vcpu);
5761
5762 /*
5763 * rflags is the old, "raw" value of the flags. The new value has
5764 * not been saved yet.
5765 *
5766 * This is correct even for TF set by the guest, because "the
5767 * processor will not generate this exception after the instruction
5768 * that sets the TF flag".
5769 */
5770 if (unlikely(rflags & X86_EFLAGS_TF))
5771 kvm_vcpu_do_singlestep(vcpu, &r);
5772 return r == EMULATE_DONE;
5773 }
5774 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5775
5776 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5777 {
5778 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5779 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5780 struct kvm_run *kvm_run = vcpu->run;
5781 unsigned long eip = kvm_get_linear_rip(vcpu);
5782 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5783 vcpu->arch.guest_debug_dr7,
5784 vcpu->arch.eff_db);
5785
5786 if (dr6 != 0) {
5787 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5788 kvm_run->debug.arch.pc = eip;
5789 kvm_run->debug.arch.exception = DB_VECTOR;
5790 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5791 *r = EMULATE_USER_EXIT;
5792 return true;
5793 }
5794 }
5795
5796 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5797 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5798 unsigned long eip = kvm_get_linear_rip(vcpu);
5799 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5800 vcpu->arch.dr7,
5801 vcpu->arch.db);
5802
5803 if (dr6 != 0) {
5804 vcpu->arch.dr6 &= ~15;
5805 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5806 kvm_queue_exception(vcpu, DB_VECTOR);
5807 *r = EMULATE_DONE;
5808 return true;
5809 }
5810 }
5811
5812 return false;
5813 }
5814
5815 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5816 unsigned long cr2,
5817 int emulation_type,
5818 void *insn,
5819 int insn_len)
5820 {
5821 int r;
5822 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5823 bool writeback = true;
5824 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5825
5826 vcpu->arch.l1tf_flush_l1d = true;
5827
5828 /*
5829 * Clear write_fault_to_shadow_pgtable here to ensure it is
5830 * never reused.
5831 */
5832 vcpu->arch.write_fault_to_shadow_pgtable = false;
5833 kvm_clear_exception_queue(vcpu);
5834
5835 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5836 init_emulate_ctxt(vcpu);
5837
5838 /*
5839 * We will reenter on the same instruction since
5840 * we do not set complete_userspace_io. This does not
5841 * handle watchpoints yet, those would be handled in
5842 * the emulate_ops.
5843 */
5844 if (!(emulation_type & EMULTYPE_SKIP) &&
5845 kvm_vcpu_check_breakpoint(vcpu, &r))
5846 return r;
5847
5848 ctxt->interruptibility = 0;
5849 ctxt->have_exception = false;
5850 ctxt->exception.vector = -1;
5851 ctxt->perm_ok = false;
5852
5853 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5854
5855 r = x86_decode_insn(ctxt, insn, insn_len);
5856
5857 trace_kvm_emulate_insn_start(vcpu);
5858 ++vcpu->stat.insn_emulation;
5859 if (r != EMULATION_OK) {
5860 if (emulation_type & EMULTYPE_TRAP_UD)
5861 return EMULATE_FAIL;
5862 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5863 emulation_type))
5864 return EMULATE_DONE;
5865 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5866 return EMULATE_DONE;
5867 if (emulation_type & EMULTYPE_SKIP)
5868 return EMULATE_FAIL;
5869 return handle_emulation_failure(vcpu);
5870 }
5871 }
5872
5873 if (emulation_type & EMULTYPE_SKIP) {
5874 kvm_rip_write(vcpu, ctxt->_eip);
5875 if (ctxt->eflags & X86_EFLAGS_RF)
5876 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5877 return EMULATE_DONE;
5878 }
5879
5880 if (retry_instruction(ctxt, cr2, emulation_type))
5881 return EMULATE_DONE;
5882
5883 /* this is needed for vmware backdoor interface to work since it
5884 changes registers values during IO operation */
5885 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5886 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5887 emulator_invalidate_register_cache(ctxt);
5888 }
5889
5890 restart:
5891 /* Save the faulting GPA (cr2) in the address field */
5892 ctxt->exception.address = cr2;
5893
5894 r = x86_emulate_insn(ctxt);
5895
5896 if (r == EMULATION_INTERCEPTED)
5897 return EMULATE_DONE;
5898
5899 if (r == EMULATION_FAILED) {
5900 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5901 emulation_type))
5902 return EMULATE_DONE;
5903
5904 return handle_emulation_failure(vcpu);
5905 }
5906
5907 if (ctxt->have_exception) {
5908 r = EMULATE_DONE;
5909 if (inject_emulated_exception(vcpu))
5910 return r;
5911 } else if (vcpu->arch.pio.count) {
5912 if (!vcpu->arch.pio.in) {
5913 /* FIXME: return into emulator if single-stepping. */
5914 vcpu->arch.pio.count = 0;
5915 } else {
5916 writeback = false;
5917 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5918 }
5919 r = EMULATE_USER_EXIT;
5920 } else if (vcpu->mmio_needed) {
5921 if (!vcpu->mmio_is_write)
5922 writeback = false;
5923 r = EMULATE_USER_EXIT;
5924 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5925 } else if (r == EMULATION_RESTART)
5926 goto restart;
5927 else
5928 r = EMULATE_DONE;
5929
5930 if (writeback) {
5931 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5932 toggle_interruptibility(vcpu, ctxt->interruptibility);
5933 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5934 kvm_rip_write(vcpu, ctxt->eip);
5935 if (r == EMULATE_DONE &&
5936 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5937 kvm_vcpu_do_singlestep(vcpu, &r);
5938 if (!ctxt->have_exception ||
5939 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5940 __kvm_set_rflags(vcpu, ctxt->eflags);
5941
5942 /*
5943 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5944 * do nothing, and it will be requested again as soon as
5945 * the shadow expires. But we still need to check here,
5946 * because POPF has no interrupt shadow.
5947 */
5948 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5949 kvm_make_request(KVM_REQ_EVENT, vcpu);
5950 } else
5951 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5952
5953 return r;
5954 }
5955 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5956
5957 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5958 {
5959 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5960 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5961 size, port, &val, 1);
5962 /* do not return to emulator after return from userspace */
5963 vcpu->arch.pio.count = 0;
5964 return ret;
5965 }
5966 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5967
5968 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5969 {
5970 unsigned long val;
5971
5972 /* We should only ever be called with arch.pio.count equal to 1 */
5973 BUG_ON(vcpu->arch.pio.count != 1);
5974
5975 /* For size less than 4 we merge, else we zero extend */
5976 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5977 : 0;
5978
5979 /*
5980 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5981 * the copy and tracing
5982 */
5983 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5984 vcpu->arch.pio.port, &val, 1);
5985 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5986
5987 return 1;
5988 }
5989
5990 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5991 {
5992 unsigned long val;
5993 int ret;
5994
5995 /* For size less than 4 we merge, else we zero extend */
5996 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5997
5998 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5999 &val, 1);
6000 if (ret) {
6001 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6002 return ret;
6003 }
6004
6005 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6006
6007 return 0;
6008 }
6009 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
6010
6011 static int kvmclock_cpu_down_prep(unsigned int cpu)
6012 {
6013 __this_cpu_write(cpu_tsc_khz, 0);
6014 return 0;
6015 }
6016
6017 static void tsc_khz_changed(void *data)
6018 {
6019 struct cpufreq_freqs *freq = data;
6020 unsigned long khz = 0;
6021
6022 if (data)
6023 khz = freq->new;
6024 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6025 khz = cpufreq_quick_get(raw_smp_processor_id());
6026 if (!khz)
6027 khz = tsc_khz;
6028 __this_cpu_write(cpu_tsc_khz, khz);
6029 }
6030
6031 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6032 void *data)
6033 {
6034 struct cpufreq_freqs *freq = data;
6035 struct kvm *kvm;
6036 struct kvm_vcpu *vcpu;
6037 int i, send_ipi = 0;
6038
6039 /*
6040 * We allow guests to temporarily run on slowing clocks,
6041 * provided we notify them after, or to run on accelerating
6042 * clocks, provided we notify them before. Thus time never
6043 * goes backwards.
6044 *
6045 * However, we have a problem. We can't atomically update
6046 * the frequency of a given CPU from this function; it is
6047 * merely a notifier, which can be called from any CPU.
6048 * Changing the TSC frequency at arbitrary points in time
6049 * requires a recomputation of local variables related to
6050 * the TSC for each VCPU. We must flag these local variables
6051 * to be updated and be sure the update takes place with the
6052 * new frequency before any guests proceed.
6053 *
6054 * Unfortunately, the combination of hotplug CPU and frequency
6055 * change creates an intractable locking scenario; the order
6056 * of when these callouts happen is undefined with respect to
6057 * CPU hotplug, and they can race with each other. As such,
6058 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6059 * undefined; you can actually have a CPU frequency change take
6060 * place in between the computation of X and the setting of the
6061 * variable. To protect against this problem, all updates of
6062 * the per_cpu tsc_khz variable are done in an interrupt
6063 * protected IPI, and all callers wishing to update the value
6064 * must wait for a synchronous IPI to complete (which is trivial
6065 * if the caller is on the CPU already). This establishes the
6066 * necessary total order on variable updates.
6067 *
6068 * Note that because a guest time update may take place
6069 * anytime after the setting of the VCPU's request bit, the
6070 * correct TSC value must be set before the request. However,
6071 * to ensure the update actually makes it to any guest which
6072 * starts running in hardware virtualization between the set
6073 * and the acquisition of the spinlock, we must also ping the
6074 * CPU after setting the request bit.
6075 *
6076 */
6077
6078 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6079 return 0;
6080 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6081 return 0;
6082
6083 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6084
6085 spin_lock(&kvm_lock);
6086 list_for_each_entry(kvm, &vm_list, vm_list) {
6087 kvm_for_each_vcpu(i, vcpu, kvm) {
6088 if (vcpu->cpu != freq->cpu)
6089 continue;
6090 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6091 if (vcpu->cpu != smp_processor_id())
6092 send_ipi = 1;
6093 }
6094 }
6095 spin_unlock(&kvm_lock);
6096
6097 if (freq->old < freq->new && send_ipi) {
6098 /*
6099 * We upscale the frequency. Must make the guest
6100 * doesn't see old kvmclock values while running with
6101 * the new frequency, otherwise we risk the guest sees
6102 * time go backwards.
6103 *
6104 * In case we update the frequency for another cpu
6105 * (which might be in guest context) send an interrupt
6106 * to kick the cpu out of guest context. Next time
6107 * guest context is entered kvmclock will be updated,
6108 * so the guest will not see stale values.
6109 */
6110 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6111 }
6112 return 0;
6113 }
6114
6115 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6116 .notifier_call = kvmclock_cpufreq_notifier
6117 };
6118
6119 static int kvmclock_cpu_online(unsigned int cpu)
6120 {
6121 tsc_khz_changed(NULL);
6122 return 0;
6123 }
6124
6125 static void kvm_timer_init(void)
6126 {
6127 max_tsc_khz = tsc_khz;
6128
6129 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6130 #ifdef CONFIG_CPU_FREQ
6131 struct cpufreq_policy policy;
6132 int cpu;
6133
6134 memset(&policy, 0, sizeof(policy));
6135 cpu = get_cpu();
6136 cpufreq_get_policy(&policy, cpu);
6137 if (policy.cpuinfo.max_freq)
6138 max_tsc_khz = policy.cpuinfo.max_freq;
6139 put_cpu();
6140 #endif
6141 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6142 CPUFREQ_TRANSITION_NOTIFIER);
6143 }
6144 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6145
6146 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6147 kvmclock_cpu_online, kvmclock_cpu_down_prep);
6148 }
6149
6150 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6151
6152 int kvm_is_in_guest(void)
6153 {
6154 return __this_cpu_read(current_vcpu) != NULL;
6155 }
6156
6157 static int kvm_is_user_mode(void)
6158 {
6159 int user_mode = 3;
6160
6161 if (__this_cpu_read(current_vcpu))
6162 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6163
6164 return user_mode != 0;
6165 }
6166
6167 static unsigned long kvm_get_guest_ip(void)
6168 {
6169 unsigned long ip = 0;
6170
6171 if (__this_cpu_read(current_vcpu))
6172 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6173
6174 return ip;
6175 }
6176
6177 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6178 .is_in_guest = kvm_is_in_guest,
6179 .is_user_mode = kvm_is_user_mode,
6180 .get_guest_ip = kvm_get_guest_ip,
6181 };
6182
6183 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6184 {
6185 __this_cpu_write(current_vcpu, vcpu);
6186 }
6187 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6188
6189 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6190 {
6191 __this_cpu_write(current_vcpu, NULL);
6192 }
6193 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6194
6195 static void kvm_set_mmio_spte_mask(void)
6196 {
6197 u64 mask;
6198 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6199
6200 /*
6201 * Set the reserved bits and the present bit of an paging-structure
6202 * entry to generate page fault with PFER.RSV = 1.
6203 */
6204 /* Mask the reserved physical address bits. */
6205 mask = rsvd_bits(maxphyaddr, 51);
6206
6207 /* Set the present bit. */
6208 mask |= 1ull;
6209
6210 #ifdef CONFIG_X86_64
6211 /*
6212 * If reserved bit is not supported, clear the present bit to disable
6213 * mmio page fault.
6214 */
6215 if (maxphyaddr == 52)
6216 mask &= ~1ull;
6217 #endif
6218
6219 kvm_mmu_set_mmio_spte_mask(mask, mask);
6220 }
6221
6222 #ifdef CONFIG_X86_64
6223 static void pvclock_gtod_update_fn(struct work_struct *work)
6224 {
6225 struct kvm *kvm;
6226
6227 struct kvm_vcpu *vcpu;
6228 int i;
6229
6230 spin_lock(&kvm_lock);
6231 list_for_each_entry(kvm, &vm_list, vm_list)
6232 kvm_for_each_vcpu(i, vcpu, kvm)
6233 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6234 atomic_set(&kvm_guest_has_master_clock, 0);
6235 spin_unlock(&kvm_lock);
6236 }
6237
6238 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6239
6240 /*
6241 * Notification about pvclock gtod data update.
6242 */
6243 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6244 void *priv)
6245 {
6246 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6247 struct timekeeper *tk = priv;
6248
6249 update_pvclock_gtod(tk);
6250
6251 /* disable master clock if host does not trust, or does not
6252 * use, TSC clocksource
6253 */
6254 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6255 atomic_read(&kvm_guest_has_master_clock) != 0)
6256 queue_work(system_long_wq, &pvclock_gtod_work);
6257
6258 return 0;
6259 }
6260
6261 static struct notifier_block pvclock_gtod_notifier = {
6262 .notifier_call = pvclock_gtod_notify,
6263 };
6264 #endif
6265
6266 int kvm_arch_init(void *opaque)
6267 {
6268 int r;
6269 struct kvm_x86_ops *ops = opaque;
6270
6271 if (kvm_x86_ops) {
6272 printk(KERN_ERR "kvm: already loaded the other module\n");
6273 r = -EEXIST;
6274 goto out;
6275 }
6276
6277 if (!ops->cpu_has_kvm_support()) {
6278 printk(KERN_ERR "kvm: no hardware support\n");
6279 r = -EOPNOTSUPP;
6280 goto out;
6281 }
6282 if (ops->disabled_by_bios()) {
6283 printk(KERN_WARNING "kvm: disabled by bios\n");
6284 r = -EOPNOTSUPP;
6285 goto out;
6286 }
6287
6288 r = -ENOMEM;
6289 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6290 if (!shared_msrs) {
6291 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6292 goto out;
6293 }
6294
6295 r = kvm_mmu_module_init();
6296 if (r)
6297 goto out_free_percpu;
6298
6299 kvm_set_mmio_spte_mask();
6300
6301 kvm_x86_ops = ops;
6302
6303 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6304 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6305 PT_PRESENT_MASK, 0, sme_me_mask);
6306 kvm_timer_init();
6307
6308 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6309
6310 if (boot_cpu_has(X86_FEATURE_XSAVE))
6311 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6312
6313 kvm_lapic_init();
6314 #ifdef CONFIG_X86_64
6315 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6316 #endif
6317
6318 return 0;
6319
6320 out_free_percpu:
6321 free_percpu(shared_msrs);
6322 out:
6323 return r;
6324 }
6325
6326 void kvm_arch_exit(void)
6327 {
6328 kvm_lapic_exit();
6329 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6330
6331 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6332 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6333 CPUFREQ_TRANSITION_NOTIFIER);
6334 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6335 #ifdef CONFIG_X86_64
6336 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6337 #endif
6338 kvm_x86_ops = NULL;
6339 kvm_mmu_module_exit();
6340 free_percpu(shared_msrs);
6341 }
6342
6343 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6344 {
6345 ++vcpu->stat.halt_exits;
6346 if (lapic_in_kernel(vcpu)) {
6347 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6348 return 1;
6349 } else {
6350 vcpu->run->exit_reason = KVM_EXIT_HLT;
6351 return 0;
6352 }
6353 }
6354 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6355
6356 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6357 {
6358 int ret = kvm_skip_emulated_instruction(vcpu);
6359 /*
6360 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6361 * KVM_EXIT_DEBUG here.
6362 */
6363 return kvm_vcpu_halt(vcpu) && ret;
6364 }
6365 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6366
6367 #ifdef CONFIG_X86_64
6368 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6369 unsigned long clock_type)
6370 {
6371 struct kvm_clock_pairing clock_pairing;
6372 struct timespec ts;
6373 u64 cycle;
6374 int ret;
6375
6376 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6377 return -KVM_EOPNOTSUPP;
6378
6379 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6380 return -KVM_EOPNOTSUPP;
6381
6382 clock_pairing.sec = ts.tv_sec;
6383 clock_pairing.nsec = ts.tv_nsec;
6384 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6385 clock_pairing.flags = 0;
6386
6387 ret = 0;
6388 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6389 sizeof(struct kvm_clock_pairing)))
6390 ret = -KVM_EFAULT;
6391
6392 return ret;
6393 }
6394 #endif
6395
6396 /*
6397 * kvm_pv_kick_cpu_op: Kick a vcpu.
6398 *
6399 * @apicid - apicid of vcpu to be kicked.
6400 */
6401 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6402 {
6403 struct kvm_lapic_irq lapic_irq;
6404
6405 lapic_irq.shorthand = 0;
6406 lapic_irq.dest_mode = 0;
6407 lapic_irq.level = 0;
6408 lapic_irq.dest_id = apicid;
6409 lapic_irq.msi_redir_hint = false;
6410
6411 lapic_irq.delivery_mode = APIC_DM_REMRD;
6412 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6413 }
6414
6415 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6416 {
6417 vcpu->arch.apicv_active = false;
6418 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6419 }
6420
6421 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6422 {
6423 unsigned long nr, a0, a1, a2, a3, ret;
6424 int op_64_bit;
6425
6426 if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
6427 if (!kvm_hv_hypercall(vcpu))
6428 return 0;
6429 goto out;
6430 }
6431
6432 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6433 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6434 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6435 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6436 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6437
6438 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6439
6440 op_64_bit = is_64_bit_mode(vcpu);
6441 if (!op_64_bit) {
6442 nr &= 0xFFFFFFFF;
6443 a0 &= 0xFFFFFFFF;
6444 a1 &= 0xFFFFFFFF;
6445 a2 &= 0xFFFFFFFF;
6446 a3 &= 0xFFFFFFFF;
6447 }
6448
6449 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6450 ret = -KVM_EPERM;
6451 goto out_error;
6452 }
6453
6454 switch (nr) {
6455 case KVM_HC_VAPIC_POLL_IRQ:
6456 ret = 0;
6457 break;
6458 case KVM_HC_KICK_CPU:
6459 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6460 ret = 0;
6461 break;
6462 #ifdef CONFIG_X86_64
6463 case KVM_HC_CLOCK_PAIRING:
6464 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6465 break;
6466 #endif
6467 default:
6468 ret = -KVM_ENOSYS;
6469 break;
6470 }
6471 out_error:
6472 if (!op_64_bit)
6473 ret = (u32)ret;
6474 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6475
6476 out:
6477 ++vcpu->stat.hypercalls;
6478 return kvm_skip_emulated_instruction(vcpu);
6479 }
6480 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6481
6482 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6483 {
6484 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6485 char instruction[3];
6486 unsigned long rip = kvm_rip_read(vcpu);
6487
6488 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6489
6490 return emulator_write_emulated(ctxt, rip, instruction, 3,
6491 &ctxt->exception);
6492 }
6493
6494 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6495 {
6496 return vcpu->run->request_interrupt_window &&
6497 likely(!pic_in_kernel(vcpu->kvm));
6498 }
6499
6500 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6501 {
6502 struct kvm_run *kvm_run = vcpu->run;
6503
6504 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6505 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6506 kvm_run->cr8 = kvm_get_cr8(vcpu);
6507 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6508 kvm_run->ready_for_interrupt_injection =
6509 pic_in_kernel(vcpu->kvm) ||
6510 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6511 }
6512
6513 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6514 {
6515 int max_irr, tpr;
6516
6517 if (!kvm_x86_ops->update_cr8_intercept)
6518 return;
6519
6520 if (!lapic_in_kernel(vcpu))
6521 return;
6522
6523 if (vcpu->arch.apicv_active)
6524 return;
6525
6526 if (!vcpu->arch.apic->vapic_addr)
6527 max_irr = kvm_lapic_find_highest_irr(vcpu);
6528 else
6529 max_irr = -1;
6530
6531 if (max_irr != -1)
6532 max_irr >>= 4;
6533
6534 tpr = kvm_lapic_get_cr8(vcpu);
6535
6536 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6537 }
6538
6539 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6540 {
6541 int r;
6542
6543 /* try to reinject previous events if any */
6544 if (vcpu->arch.exception.injected) {
6545 kvm_x86_ops->queue_exception(vcpu);
6546 return 0;
6547 }
6548
6549 /*
6550 * Exceptions must be injected immediately, or the exception
6551 * frame will have the address of the NMI or interrupt handler.
6552 */
6553 if (!vcpu->arch.exception.pending) {
6554 if (vcpu->arch.nmi_injected) {
6555 kvm_x86_ops->set_nmi(vcpu);
6556 return 0;
6557 }
6558
6559 if (vcpu->arch.interrupt.pending) {
6560 kvm_x86_ops->set_irq(vcpu);
6561 return 0;
6562 }
6563 }
6564
6565 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6566 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6567 if (r != 0)
6568 return r;
6569 }
6570
6571 /* try to inject new event if pending */
6572 if (vcpu->arch.exception.pending) {
6573 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6574 vcpu->arch.exception.has_error_code,
6575 vcpu->arch.exception.error_code);
6576
6577 vcpu->arch.exception.pending = false;
6578 vcpu->arch.exception.injected = true;
6579
6580 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6581 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6582 X86_EFLAGS_RF);
6583
6584 if (vcpu->arch.exception.nr == DB_VECTOR &&
6585 (vcpu->arch.dr7 & DR7_GD)) {
6586 vcpu->arch.dr7 &= ~DR7_GD;
6587 kvm_update_dr7(vcpu);
6588 }
6589
6590 kvm_x86_ops->queue_exception(vcpu);
6591 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
6592 vcpu->arch.smi_pending = false;
6593 enter_smm(vcpu);
6594 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6595 --vcpu->arch.nmi_pending;
6596 vcpu->arch.nmi_injected = true;
6597 kvm_x86_ops->set_nmi(vcpu);
6598 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6599 /*
6600 * Because interrupts can be injected asynchronously, we are
6601 * calling check_nested_events again here to avoid a race condition.
6602 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6603 * proposal and current concerns. Perhaps we should be setting
6604 * KVM_REQ_EVENT only on certain events and not unconditionally?
6605 */
6606 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6607 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6608 if (r != 0)
6609 return r;
6610 }
6611 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6612 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6613 false);
6614 kvm_x86_ops->set_irq(vcpu);
6615 }
6616 }
6617
6618 return 0;
6619 }
6620
6621 static void process_nmi(struct kvm_vcpu *vcpu)
6622 {
6623 unsigned limit = 2;
6624
6625 /*
6626 * x86 is limited to one NMI running, and one NMI pending after it.
6627 * If an NMI is already in progress, limit further NMIs to just one.
6628 * Otherwise, allow two (and we'll inject the first one immediately).
6629 */
6630 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6631 limit = 1;
6632
6633 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6634 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6635 kvm_make_request(KVM_REQ_EVENT, vcpu);
6636 }
6637
6638 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6639 {
6640 u32 flags = 0;
6641 flags |= seg->g << 23;
6642 flags |= seg->db << 22;
6643 flags |= seg->l << 21;
6644 flags |= seg->avl << 20;
6645 flags |= seg->present << 15;
6646 flags |= seg->dpl << 13;
6647 flags |= seg->s << 12;
6648 flags |= seg->type << 8;
6649 return flags;
6650 }
6651
6652 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6653 {
6654 struct kvm_segment seg;
6655 int offset;
6656
6657 kvm_get_segment(vcpu, &seg, n);
6658 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6659
6660 if (n < 3)
6661 offset = 0x7f84 + n * 12;
6662 else
6663 offset = 0x7f2c + (n - 3) * 12;
6664
6665 put_smstate(u32, buf, offset + 8, seg.base);
6666 put_smstate(u32, buf, offset + 4, seg.limit);
6667 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6668 }
6669
6670 #ifdef CONFIG_X86_64
6671 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6672 {
6673 struct kvm_segment seg;
6674 int offset;
6675 u16 flags;
6676
6677 kvm_get_segment(vcpu, &seg, n);
6678 offset = 0x7e00 + n * 16;
6679
6680 flags = enter_smm_get_segment_flags(&seg) >> 8;
6681 put_smstate(u16, buf, offset, seg.selector);
6682 put_smstate(u16, buf, offset + 2, flags);
6683 put_smstate(u32, buf, offset + 4, seg.limit);
6684 put_smstate(u64, buf, offset + 8, seg.base);
6685 }
6686 #endif
6687
6688 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6689 {
6690 struct desc_ptr dt;
6691 struct kvm_segment seg;
6692 unsigned long val;
6693 int i;
6694
6695 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6696 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6697 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6698 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6699
6700 for (i = 0; i < 8; i++)
6701 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6702
6703 kvm_get_dr(vcpu, 6, &val);
6704 put_smstate(u32, buf, 0x7fcc, (u32)val);
6705 kvm_get_dr(vcpu, 7, &val);
6706 put_smstate(u32, buf, 0x7fc8, (u32)val);
6707
6708 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6709 put_smstate(u32, buf, 0x7fc4, seg.selector);
6710 put_smstate(u32, buf, 0x7f64, seg.base);
6711 put_smstate(u32, buf, 0x7f60, seg.limit);
6712 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6713
6714 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6715 put_smstate(u32, buf, 0x7fc0, seg.selector);
6716 put_smstate(u32, buf, 0x7f80, seg.base);
6717 put_smstate(u32, buf, 0x7f7c, seg.limit);
6718 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6719
6720 kvm_x86_ops->get_gdt(vcpu, &dt);
6721 put_smstate(u32, buf, 0x7f74, dt.address);
6722 put_smstate(u32, buf, 0x7f70, dt.size);
6723
6724 kvm_x86_ops->get_idt(vcpu, &dt);
6725 put_smstate(u32, buf, 0x7f58, dt.address);
6726 put_smstate(u32, buf, 0x7f54, dt.size);
6727
6728 for (i = 0; i < 6; i++)
6729 enter_smm_save_seg_32(vcpu, buf, i);
6730
6731 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6732
6733 /* revision id */
6734 put_smstate(u32, buf, 0x7efc, 0x00020000);
6735 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6736 }
6737
6738 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6739 {
6740 #ifdef CONFIG_X86_64
6741 struct desc_ptr dt;
6742 struct kvm_segment seg;
6743 unsigned long val;
6744 int i;
6745
6746 for (i = 0; i < 16; i++)
6747 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6748
6749 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6750 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6751
6752 kvm_get_dr(vcpu, 6, &val);
6753 put_smstate(u64, buf, 0x7f68, val);
6754 kvm_get_dr(vcpu, 7, &val);
6755 put_smstate(u64, buf, 0x7f60, val);
6756
6757 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6758 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6759 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6760
6761 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6762
6763 /* revision id */
6764 put_smstate(u32, buf, 0x7efc, 0x00020064);
6765
6766 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6767
6768 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6769 put_smstate(u16, buf, 0x7e90, seg.selector);
6770 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6771 put_smstate(u32, buf, 0x7e94, seg.limit);
6772 put_smstate(u64, buf, 0x7e98, seg.base);
6773
6774 kvm_x86_ops->get_idt(vcpu, &dt);
6775 put_smstate(u32, buf, 0x7e84, dt.size);
6776 put_smstate(u64, buf, 0x7e88, dt.address);
6777
6778 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6779 put_smstate(u16, buf, 0x7e70, seg.selector);
6780 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6781 put_smstate(u32, buf, 0x7e74, seg.limit);
6782 put_smstate(u64, buf, 0x7e78, seg.base);
6783
6784 kvm_x86_ops->get_gdt(vcpu, &dt);
6785 put_smstate(u32, buf, 0x7e64, dt.size);
6786 put_smstate(u64, buf, 0x7e68, dt.address);
6787
6788 for (i = 0; i < 6; i++)
6789 enter_smm_save_seg_64(vcpu, buf, i);
6790 #else
6791 WARN_ON_ONCE(1);
6792 #endif
6793 }
6794
6795 static void enter_smm(struct kvm_vcpu *vcpu)
6796 {
6797 struct kvm_segment cs, ds;
6798 struct desc_ptr dt;
6799 char buf[512];
6800 u32 cr0;
6801
6802 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6803 memset(buf, 0, 512);
6804 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6805 enter_smm_save_state_64(vcpu, buf);
6806 else
6807 enter_smm_save_state_32(vcpu, buf);
6808
6809 /*
6810 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6811 * vCPU state (e.g. leave guest mode) after we've saved the state into
6812 * the SMM state-save area.
6813 */
6814 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6815
6816 vcpu->arch.hflags |= HF_SMM_MASK;
6817 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6818
6819 if (kvm_x86_ops->get_nmi_mask(vcpu))
6820 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6821 else
6822 kvm_x86_ops->set_nmi_mask(vcpu, true);
6823
6824 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6825 kvm_rip_write(vcpu, 0x8000);
6826
6827 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6828 kvm_x86_ops->set_cr0(vcpu, cr0);
6829 vcpu->arch.cr0 = cr0;
6830
6831 kvm_x86_ops->set_cr4(vcpu, 0);
6832
6833 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6834 dt.address = dt.size = 0;
6835 kvm_x86_ops->set_idt(vcpu, &dt);
6836
6837 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6838
6839 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6840 cs.base = vcpu->arch.smbase;
6841
6842 ds.selector = 0;
6843 ds.base = 0;
6844
6845 cs.limit = ds.limit = 0xffffffff;
6846 cs.type = ds.type = 0x3;
6847 cs.dpl = ds.dpl = 0;
6848 cs.db = ds.db = 0;
6849 cs.s = ds.s = 1;
6850 cs.l = ds.l = 0;
6851 cs.g = ds.g = 1;
6852 cs.avl = ds.avl = 0;
6853 cs.present = ds.present = 1;
6854 cs.unusable = ds.unusable = 0;
6855 cs.padding = ds.padding = 0;
6856
6857 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6858 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6859 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6860 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6861 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6862 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6863
6864 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
6865 kvm_x86_ops->set_efer(vcpu, 0);
6866
6867 kvm_update_cpuid(vcpu);
6868 kvm_mmu_reset_context(vcpu);
6869 }
6870
6871 static void process_smi(struct kvm_vcpu *vcpu)
6872 {
6873 vcpu->arch.smi_pending = true;
6874 kvm_make_request(KVM_REQ_EVENT, vcpu);
6875 }
6876
6877 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6878 {
6879 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6880 }
6881
6882 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6883 {
6884 u64 eoi_exit_bitmap[4];
6885
6886 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6887 return;
6888
6889 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6890
6891 if (irqchip_split(vcpu->kvm))
6892 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6893 else {
6894 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6895 kvm_x86_ops->sync_pir_to_irr(vcpu);
6896 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6897 }
6898 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6899 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6900 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6901 }
6902
6903 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6904 {
6905 ++vcpu->stat.tlb_flush;
6906 kvm_x86_ops->tlb_flush(vcpu);
6907 }
6908
6909 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6910 unsigned long start, unsigned long end)
6911 {
6912 unsigned long apic_address;
6913
6914 /*
6915 * The physical address of apic access page is stored in the VMCS.
6916 * Update it when it becomes invalid.
6917 */
6918 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6919 if (start <= apic_address && apic_address < end)
6920 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6921 }
6922
6923 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6924 {
6925 struct page *page = NULL;
6926
6927 if (!lapic_in_kernel(vcpu))
6928 return;
6929
6930 if (!kvm_x86_ops->set_apic_access_page_addr)
6931 return;
6932
6933 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6934 if (is_error_page(page))
6935 return;
6936 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6937
6938 /*
6939 * Do not pin apic access page in memory, the MMU notifier
6940 * will call us again if it is migrated or swapped out.
6941 */
6942 put_page(page);
6943 }
6944 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6945
6946 /*
6947 * Returns 1 to let vcpu_run() continue the guest execution loop without
6948 * exiting to the userspace. Otherwise, the value will be returned to the
6949 * userspace.
6950 */
6951 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6952 {
6953 int r;
6954 bool req_int_win =
6955 dm_request_for_irq_injection(vcpu) &&
6956 kvm_cpu_accept_dm_intr(vcpu);
6957
6958 bool req_immediate_exit = false;
6959
6960 if (kvm_request_pending(vcpu)) {
6961 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6962 kvm_mmu_unload(vcpu);
6963 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6964 __kvm_migrate_timers(vcpu);
6965 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6966 kvm_gen_update_masterclock(vcpu->kvm);
6967 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6968 kvm_gen_kvmclock_update(vcpu);
6969 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6970 r = kvm_guest_time_update(vcpu);
6971 if (unlikely(r))
6972 goto out;
6973 }
6974 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6975 kvm_mmu_sync_roots(vcpu);
6976 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6977 kvm_vcpu_flush_tlb(vcpu);
6978 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6979 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6980 r = 0;
6981 goto out;
6982 }
6983 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6984 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6985 vcpu->mmio_needed = 0;
6986 r = 0;
6987 goto out;
6988 }
6989 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6990 /* Page is swapped out. Do synthetic halt */
6991 vcpu->arch.apf.halted = true;
6992 r = 1;
6993 goto out;
6994 }
6995 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6996 record_steal_time(vcpu);
6997 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6998 process_smi(vcpu);
6999 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7000 process_nmi(vcpu);
7001 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7002 kvm_pmu_handle_event(vcpu);
7003 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7004 kvm_pmu_deliver_pmi(vcpu);
7005 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7006 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7007 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7008 vcpu->arch.ioapic_handled_vectors)) {
7009 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7010 vcpu->run->eoi.vector =
7011 vcpu->arch.pending_ioapic_eoi;
7012 r = 0;
7013 goto out;
7014 }
7015 }
7016 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7017 vcpu_scan_ioapic(vcpu);
7018 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7019 kvm_vcpu_reload_apic_access_page(vcpu);
7020 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7021 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7022 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7023 r = 0;
7024 goto out;
7025 }
7026 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7027 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7028 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7029 r = 0;
7030 goto out;
7031 }
7032 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7033 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7034 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7035 r = 0;
7036 goto out;
7037 }
7038
7039 /*
7040 * KVM_REQ_HV_STIMER has to be processed after
7041 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7042 * depend on the guest clock being up-to-date
7043 */
7044 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7045 kvm_hv_process_stimers(vcpu);
7046 }
7047
7048 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7049 ++vcpu->stat.req_event;
7050 kvm_apic_accept_events(vcpu);
7051 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7052 r = 1;
7053 goto out;
7054 }
7055
7056 if (inject_pending_event(vcpu, req_int_win) != 0)
7057 req_immediate_exit = true;
7058 else {
7059 /* Enable SMI/NMI/IRQ window open exits if needed.
7060 *
7061 * SMIs have three cases:
7062 * 1) They can be nested, and then there is nothing to
7063 * do here because RSM will cause a vmexit anyway.
7064 * 2) There is an ISA-specific reason why SMI cannot be
7065 * injected, and the moment when this changes can be
7066 * intercepted.
7067 * 3) Or the SMI can be pending because
7068 * inject_pending_event has completed the injection
7069 * of an IRQ or NMI from the previous vmexit, and
7070 * then we request an immediate exit to inject the
7071 * SMI.
7072 */
7073 if (vcpu->arch.smi_pending && !is_smm(vcpu))
7074 if (!kvm_x86_ops->enable_smi_window(vcpu))
7075 req_immediate_exit = true;
7076 if (vcpu->arch.nmi_pending)
7077 kvm_x86_ops->enable_nmi_window(vcpu);
7078 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7079 kvm_x86_ops->enable_irq_window(vcpu);
7080 WARN_ON(vcpu->arch.exception.pending);
7081 }
7082
7083 if (kvm_lapic_enabled(vcpu)) {
7084 update_cr8_intercept(vcpu);
7085 kvm_lapic_sync_to_vapic(vcpu);
7086 }
7087 }
7088
7089 r = kvm_mmu_reload(vcpu);
7090 if (unlikely(r)) {
7091 goto cancel_injection;
7092 }
7093
7094 preempt_disable();
7095
7096 kvm_x86_ops->prepare_guest_switch(vcpu);
7097
7098 /*
7099 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7100 * IPI are then delayed after guest entry, which ensures that they
7101 * result in virtual interrupt delivery.
7102 */
7103 local_irq_disable();
7104 vcpu->mode = IN_GUEST_MODE;
7105
7106 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7107
7108 /*
7109 * 1) We should set ->mode before checking ->requests. Please see
7110 * the comment in kvm_vcpu_exiting_guest_mode().
7111 *
7112 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7113 * pairs with the memory barrier implicit in pi_test_and_set_on
7114 * (see vmx_deliver_posted_interrupt).
7115 *
7116 * 3) This also orders the write to mode from any reads to the page
7117 * tables done while the VCPU is running. Please see the comment
7118 * in kvm_flush_remote_tlbs.
7119 */
7120 smp_mb__after_srcu_read_unlock();
7121
7122 /*
7123 * This handles the case where a posted interrupt was
7124 * notified with kvm_vcpu_kick.
7125 */
7126 if (kvm_lapic_enabled(vcpu)) {
7127 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7128 kvm_x86_ops->sync_pir_to_irr(vcpu);
7129 }
7130
7131 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7132 || need_resched() || signal_pending(current)) {
7133 vcpu->mode = OUTSIDE_GUEST_MODE;
7134 smp_wmb();
7135 local_irq_enable();
7136 preempt_enable();
7137 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7138 r = 1;
7139 goto cancel_injection;
7140 }
7141
7142 kvm_load_guest_xcr0(vcpu);
7143
7144 if (req_immediate_exit) {
7145 kvm_make_request(KVM_REQ_EVENT, vcpu);
7146 smp_send_reschedule(vcpu->cpu);
7147 }
7148
7149 trace_kvm_entry(vcpu->vcpu_id);
7150 wait_lapic_expire(vcpu);
7151 guest_enter_irqoff();
7152
7153 if (unlikely(vcpu->arch.switch_db_regs)) {
7154 set_debugreg(0, 7);
7155 set_debugreg(vcpu->arch.eff_db[0], 0);
7156 set_debugreg(vcpu->arch.eff_db[1], 1);
7157 set_debugreg(vcpu->arch.eff_db[2], 2);
7158 set_debugreg(vcpu->arch.eff_db[3], 3);
7159 set_debugreg(vcpu->arch.dr6, 6);
7160 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7161 }
7162
7163 kvm_x86_ops->run(vcpu);
7164
7165 /*
7166 * Do this here before restoring debug registers on the host. And
7167 * since we do this before handling the vmexit, a DR access vmexit
7168 * can (a) read the correct value of the debug registers, (b) set
7169 * KVM_DEBUGREG_WONT_EXIT again.
7170 */
7171 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7172 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7173 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7174 kvm_update_dr0123(vcpu);
7175 kvm_update_dr6(vcpu);
7176 kvm_update_dr7(vcpu);
7177 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7178 }
7179
7180 /*
7181 * If the guest has used debug registers, at least dr7
7182 * will be disabled while returning to the host.
7183 * If we don't have active breakpoints in the host, we don't
7184 * care about the messed up debug address registers. But if
7185 * we have some of them active, restore the old state.
7186 */
7187 if (hw_breakpoint_active())
7188 hw_breakpoint_restore();
7189
7190 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7191
7192 vcpu->mode = OUTSIDE_GUEST_MODE;
7193 smp_wmb();
7194
7195 kvm_put_guest_xcr0(vcpu);
7196
7197 kvm_x86_ops->handle_external_intr(vcpu);
7198
7199 ++vcpu->stat.exits;
7200
7201 guest_exit_irqoff();
7202
7203 local_irq_enable();
7204 preempt_enable();
7205
7206 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7207
7208 /*
7209 * Profile KVM exit RIPs:
7210 */
7211 if (unlikely(prof_on == KVM_PROFILING)) {
7212 unsigned long rip = kvm_rip_read(vcpu);
7213 profile_hit(KVM_PROFILING, (void *)rip);
7214 }
7215
7216 if (unlikely(vcpu->arch.tsc_always_catchup))
7217 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7218
7219 if (vcpu->arch.apic_attention)
7220 kvm_lapic_sync_from_vapic(vcpu);
7221
7222 vcpu->arch.gpa_available = false;
7223 r = kvm_x86_ops->handle_exit(vcpu);
7224 return r;
7225
7226 cancel_injection:
7227 kvm_x86_ops->cancel_injection(vcpu);
7228 if (unlikely(vcpu->arch.apic_attention))
7229 kvm_lapic_sync_from_vapic(vcpu);
7230 out:
7231 return r;
7232 }
7233
7234 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7235 {
7236 if (!kvm_arch_vcpu_runnable(vcpu) &&
7237 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7238 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7239 kvm_vcpu_block(vcpu);
7240 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7241
7242 if (kvm_x86_ops->post_block)
7243 kvm_x86_ops->post_block(vcpu);
7244
7245 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7246 return 1;
7247 }
7248
7249 kvm_apic_accept_events(vcpu);
7250 switch(vcpu->arch.mp_state) {
7251 case KVM_MP_STATE_HALTED:
7252 vcpu->arch.pv.pv_unhalted = false;
7253 vcpu->arch.mp_state =
7254 KVM_MP_STATE_RUNNABLE;
7255 case KVM_MP_STATE_RUNNABLE:
7256 vcpu->arch.apf.halted = false;
7257 break;
7258 case KVM_MP_STATE_INIT_RECEIVED:
7259 break;
7260 default:
7261 return -EINTR;
7262 break;
7263 }
7264 return 1;
7265 }
7266
7267 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7268 {
7269 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7270 kvm_x86_ops->check_nested_events(vcpu, false);
7271
7272 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7273 !vcpu->arch.apf.halted);
7274 }
7275
7276 static int vcpu_run(struct kvm_vcpu *vcpu)
7277 {
7278 int r;
7279 struct kvm *kvm = vcpu->kvm;
7280
7281 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7282 vcpu->arch.l1tf_flush_l1d = true;
7283
7284 for (;;) {
7285 if (kvm_vcpu_running(vcpu)) {
7286 r = vcpu_enter_guest(vcpu);
7287 } else {
7288 r = vcpu_block(kvm, vcpu);
7289 }
7290
7291 if (r <= 0)
7292 break;
7293
7294 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7295 if (kvm_cpu_has_pending_timer(vcpu))
7296 kvm_inject_pending_timer_irqs(vcpu);
7297
7298 if (dm_request_for_irq_injection(vcpu) &&
7299 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7300 r = 0;
7301 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7302 ++vcpu->stat.request_irq_exits;
7303 break;
7304 }
7305
7306 kvm_check_async_pf_completion(vcpu);
7307
7308 if (signal_pending(current)) {
7309 r = -EINTR;
7310 vcpu->run->exit_reason = KVM_EXIT_INTR;
7311 ++vcpu->stat.signal_exits;
7312 break;
7313 }
7314 if (need_resched()) {
7315 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7316 cond_resched();
7317 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7318 }
7319 }
7320
7321 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7322
7323 return r;
7324 }
7325
7326 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7327 {
7328 int r;
7329 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7330 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7331 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7332 if (r != EMULATE_DONE)
7333 return 0;
7334 return 1;
7335 }
7336
7337 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7338 {
7339 BUG_ON(!vcpu->arch.pio.count);
7340
7341 return complete_emulated_io(vcpu);
7342 }
7343
7344 /*
7345 * Implements the following, as a state machine:
7346 *
7347 * read:
7348 * for each fragment
7349 * for each mmio piece in the fragment
7350 * write gpa, len
7351 * exit
7352 * copy data
7353 * execute insn
7354 *
7355 * write:
7356 * for each fragment
7357 * for each mmio piece in the fragment
7358 * write gpa, len
7359 * copy data
7360 * exit
7361 */
7362 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7363 {
7364 struct kvm_run *run = vcpu->run;
7365 struct kvm_mmio_fragment *frag;
7366 unsigned len;
7367
7368 BUG_ON(!vcpu->mmio_needed);
7369
7370 /* Complete previous fragment */
7371 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7372 len = min(8u, frag->len);
7373 if (!vcpu->mmio_is_write)
7374 memcpy(frag->data, run->mmio.data, len);
7375
7376 if (frag->len <= 8) {
7377 /* Switch to the next fragment. */
7378 frag++;
7379 vcpu->mmio_cur_fragment++;
7380 } else {
7381 /* Go forward to the next mmio piece. */
7382 frag->data += len;
7383 frag->gpa += len;
7384 frag->len -= len;
7385 }
7386
7387 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7388 vcpu->mmio_needed = 0;
7389
7390 /* FIXME: return into emulator if single-stepping. */
7391 if (vcpu->mmio_is_write)
7392 return 1;
7393 vcpu->mmio_read_completed = 1;
7394 return complete_emulated_io(vcpu);
7395 }
7396
7397 run->exit_reason = KVM_EXIT_MMIO;
7398 run->mmio.phys_addr = frag->gpa;
7399 if (vcpu->mmio_is_write)
7400 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7401 run->mmio.len = min(8u, frag->len);
7402 run->mmio.is_write = vcpu->mmio_is_write;
7403 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7404 return 0;
7405 }
7406
7407
7408 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7409 {
7410 int r;
7411
7412 kvm_sigset_activate(vcpu);
7413
7414 kvm_load_guest_fpu(vcpu);
7415
7416 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7417 if (kvm_run->immediate_exit) {
7418 r = -EINTR;
7419 goto out;
7420 }
7421 kvm_vcpu_block(vcpu);
7422 kvm_apic_accept_events(vcpu);
7423 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
7424 r = -EAGAIN;
7425 if (signal_pending(current)) {
7426 r = -EINTR;
7427 vcpu->run->exit_reason = KVM_EXIT_INTR;
7428 ++vcpu->stat.signal_exits;
7429 }
7430 goto out;
7431 }
7432
7433 /* re-sync apic's tpr */
7434 if (!lapic_in_kernel(vcpu)) {
7435 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7436 r = -EINVAL;
7437 goto out;
7438 }
7439 }
7440
7441 if (unlikely(vcpu->arch.complete_userspace_io)) {
7442 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7443 vcpu->arch.complete_userspace_io = NULL;
7444 r = cui(vcpu);
7445 if (r <= 0)
7446 goto out;
7447 } else
7448 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7449
7450 if (kvm_run->immediate_exit)
7451 r = -EINTR;
7452 else
7453 r = vcpu_run(vcpu);
7454
7455 out:
7456 kvm_put_guest_fpu(vcpu);
7457 post_kvm_run_save(vcpu);
7458 kvm_sigset_deactivate(vcpu);
7459
7460 return r;
7461 }
7462
7463 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7464 {
7465 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7466 /*
7467 * We are here if userspace calls get_regs() in the middle of
7468 * instruction emulation. Registers state needs to be copied
7469 * back from emulation context to vcpu. Userspace shouldn't do
7470 * that usually, but some bad designed PV devices (vmware
7471 * backdoor interface) need this to work
7472 */
7473 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7474 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7475 }
7476 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7477 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7478 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7479 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7480 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7481 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7482 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7483 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7484 #ifdef CONFIG_X86_64
7485 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7486 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7487 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7488 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7489 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7490 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7491 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7492 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7493 #endif
7494
7495 regs->rip = kvm_rip_read(vcpu);
7496 regs->rflags = kvm_get_rflags(vcpu);
7497
7498 return 0;
7499 }
7500
7501 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7502 {
7503 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7504 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7505
7506 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7507 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7508 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7509 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7510 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7511 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7512 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7513 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7514 #ifdef CONFIG_X86_64
7515 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7516 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7517 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7518 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7519 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7520 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7521 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7522 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7523 #endif
7524
7525 kvm_rip_write(vcpu, regs->rip);
7526 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
7527
7528 vcpu->arch.exception.pending = false;
7529
7530 kvm_make_request(KVM_REQ_EVENT, vcpu);
7531
7532 return 0;
7533 }
7534
7535 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7536 {
7537 struct kvm_segment cs;
7538
7539 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7540 *db = cs.db;
7541 *l = cs.l;
7542 }
7543 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7544
7545 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7546 struct kvm_sregs *sregs)
7547 {
7548 struct desc_ptr dt;
7549
7550 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7551 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7552 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7553 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7554 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7555 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7556
7557 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7558 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7559
7560 kvm_x86_ops->get_idt(vcpu, &dt);
7561 sregs->idt.limit = dt.size;
7562 sregs->idt.base = dt.address;
7563 kvm_x86_ops->get_gdt(vcpu, &dt);
7564 sregs->gdt.limit = dt.size;
7565 sregs->gdt.base = dt.address;
7566
7567 sregs->cr0 = kvm_read_cr0(vcpu);
7568 sregs->cr2 = vcpu->arch.cr2;
7569 sregs->cr3 = kvm_read_cr3(vcpu);
7570 sregs->cr4 = kvm_read_cr4(vcpu);
7571 sregs->cr8 = kvm_get_cr8(vcpu);
7572 sregs->efer = vcpu->arch.efer;
7573 sregs->apic_base = kvm_get_apic_base(vcpu);
7574
7575 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7576
7577 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7578 set_bit(vcpu->arch.interrupt.nr,
7579 (unsigned long *)sregs->interrupt_bitmap);
7580
7581 return 0;
7582 }
7583
7584 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7585 struct kvm_mp_state *mp_state)
7586 {
7587 kvm_apic_accept_events(vcpu);
7588 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7589 vcpu->arch.pv.pv_unhalted)
7590 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7591 else
7592 mp_state->mp_state = vcpu->arch.mp_state;
7593
7594 return 0;
7595 }
7596
7597 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7598 struct kvm_mp_state *mp_state)
7599 {
7600 if (!lapic_in_kernel(vcpu) &&
7601 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7602 return -EINVAL;
7603
7604 /* INITs are latched while in SMM */
7605 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7606 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7607 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7608 return -EINVAL;
7609
7610 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7611 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7612 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7613 } else
7614 vcpu->arch.mp_state = mp_state->mp_state;
7615 kvm_make_request(KVM_REQ_EVENT, vcpu);
7616 return 0;
7617 }
7618
7619 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7620 int reason, bool has_error_code, u32 error_code)
7621 {
7622 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7623 int ret;
7624
7625 init_emulate_ctxt(vcpu);
7626
7627 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7628 has_error_code, error_code);
7629
7630 if (ret)
7631 return EMULATE_FAIL;
7632
7633 kvm_rip_write(vcpu, ctxt->eip);
7634 kvm_set_rflags(vcpu, ctxt->eflags);
7635 kvm_make_request(KVM_REQ_EVENT, vcpu);
7636 return EMULATE_DONE;
7637 }
7638 EXPORT_SYMBOL_GPL(kvm_task_switch);
7639
7640 int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7641 {
7642 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
7643 /*
7644 * When EFER.LME and CR0.PG are set, the processor is in
7645 * 64-bit mode (though maybe in a 32-bit code segment).
7646 * CR4.PAE and EFER.LMA must be set.
7647 */
7648 if (!(sregs->cr4 & X86_CR4_PAE)
7649 || !(sregs->efer & EFER_LMA))
7650 return -EINVAL;
7651 } else {
7652 /*
7653 * Not in 64-bit mode: EFER.LMA is clear and the code
7654 * segment cannot be 64-bit.
7655 */
7656 if (sregs->efer & EFER_LMA || sregs->cs.l)
7657 return -EINVAL;
7658 }
7659
7660 return 0;
7661 }
7662
7663 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7664 struct kvm_sregs *sregs)
7665 {
7666 struct msr_data apic_base_msr;
7667 int mmu_reset_needed = 0;
7668 int cpuid_update_needed = 0;
7669 int pending_vec, max_bits, idx;
7670 struct desc_ptr dt;
7671
7672 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7673 (sregs->cr4 & X86_CR4_OSXSAVE))
7674 return -EINVAL;
7675
7676 if (kvm_valid_sregs(vcpu, sregs))
7677 return -EINVAL;
7678
7679 apic_base_msr.data = sregs->apic_base;
7680 apic_base_msr.host_initiated = true;
7681 if (kvm_set_apic_base(vcpu, &apic_base_msr))
7682 return -EINVAL;
7683
7684 dt.size = sregs->idt.limit;
7685 dt.address = sregs->idt.base;
7686 kvm_x86_ops->set_idt(vcpu, &dt);
7687 dt.size = sregs->gdt.limit;
7688 dt.address = sregs->gdt.base;
7689 kvm_x86_ops->set_gdt(vcpu, &dt);
7690
7691 vcpu->arch.cr2 = sregs->cr2;
7692 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7693 vcpu->arch.cr3 = sregs->cr3;
7694 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7695
7696 kvm_set_cr8(vcpu, sregs->cr8);
7697
7698 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7699 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7700
7701 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7702 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7703 vcpu->arch.cr0 = sregs->cr0;
7704
7705 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7706 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
7707 (X86_CR4_OSXSAVE | X86_CR4_PKE));
7708 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7709 if (cpuid_update_needed)
7710 kvm_update_cpuid(vcpu);
7711
7712 idx = srcu_read_lock(&vcpu->kvm->srcu);
7713 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7714 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7715 mmu_reset_needed = 1;
7716 }
7717 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7718
7719 if (mmu_reset_needed)
7720 kvm_mmu_reset_context(vcpu);
7721
7722 max_bits = KVM_NR_INTERRUPTS;
7723 pending_vec = find_first_bit(
7724 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7725 if (pending_vec < max_bits) {
7726 kvm_queue_interrupt(vcpu, pending_vec, false);
7727 pr_debug("Set back pending irq %d\n", pending_vec);
7728 }
7729
7730 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7731 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7732 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7733 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7734 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7735 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7736
7737 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7738 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7739
7740 update_cr8_intercept(vcpu);
7741
7742 /* Older userspace won't unhalt the vcpu on reset. */
7743 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7744 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7745 !is_protmode(vcpu))
7746 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7747
7748 kvm_make_request(KVM_REQ_EVENT, vcpu);
7749
7750 return 0;
7751 }
7752
7753 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7754 struct kvm_guest_debug *dbg)
7755 {
7756 unsigned long rflags;
7757 int i, r;
7758
7759 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7760 r = -EBUSY;
7761 if (vcpu->arch.exception.pending)
7762 goto out;
7763 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7764 kvm_queue_exception(vcpu, DB_VECTOR);
7765 else
7766 kvm_queue_exception(vcpu, BP_VECTOR);
7767 }
7768
7769 /*
7770 * Read rflags as long as potentially injected trace flags are still
7771 * filtered out.
7772 */
7773 rflags = kvm_get_rflags(vcpu);
7774
7775 vcpu->guest_debug = dbg->control;
7776 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7777 vcpu->guest_debug = 0;
7778
7779 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7780 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7781 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7782 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7783 } else {
7784 for (i = 0; i < KVM_NR_DB_REGS; i++)
7785 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7786 }
7787 kvm_update_dr7(vcpu);
7788
7789 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7790 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7791 get_segment_base(vcpu, VCPU_SREG_CS);
7792
7793 /*
7794 * Trigger an rflags update that will inject or remove the trace
7795 * flags.
7796 */
7797 kvm_set_rflags(vcpu, rflags);
7798
7799 kvm_x86_ops->update_bp_intercept(vcpu);
7800
7801 r = 0;
7802
7803 out:
7804
7805 return r;
7806 }
7807
7808 /*
7809 * Translate a guest virtual address to a guest physical address.
7810 */
7811 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7812 struct kvm_translation *tr)
7813 {
7814 unsigned long vaddr = tr->linear_address;
7815 gpa_t gpa;
7816 int idx;
7817
7818 idx = srcu_read_lock(&vcpu->kvm->srcu);
7819 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7820 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7821 tr->physical_address = gpa;
7822 tr->valid = gpa != UNMAPPED_GVA;
7823 tr->writeable = 1;
7824 tr->usermode = 0;
7825
7826 return 0;
7827 }
7828
7829 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7830 {
7831 struct fxregs_state *fxsave =
7832 &vcpu->arch.guest_fpu.state.fxsave;
7833
7834 memcpy(fpu->fpr, fxsave->st_space, 128);
7835 fpu->fcw = fxsave->cwd;
7836 fpu->fsw = fxsave->swd;
7837 fpu->ftwx = fxsave->twd;
7838 fpu->last_opcode = fxsave->fop;
7839 fpu->last_ip = fxsave->rip;
7840 fpu->last_dp = fxsave->rdp;
7841 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7842
7843 return 0;
7844 }
7845
7846 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7847 {
7848 struct fxregs_state *fxsave =
7849 &vcpu->arch.guest_fpu.state.fxsave;
7850
7851 memcpy(fxsave->st_space, fpu->fpr, 128);
7852 fxsave->cwd = fpu->fcw;
7853 fxsave->swd = fpu->fsw;
7854 fxsave->twd = fpu->ftwx;
7855 fxsave->fop = fpu->last_opcode;
7856 fxsave->rip = fpu->last_ip;
7857 fxsave->rdp = fpu->last_dp;
7858 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7859
7860 return 0;
7861 }
7862
7863 static void fx_init(struct kvm_vcpu *vcpu)
7864 {
7865 fpstate_init(&vcpu->arch.guest_fpu.state);
7866 if (boot_cpu_has(X86_FEATURE_XSAVES))
7867 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7868 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7869
7870 /*
7871 * Ensure guest xcr0 is valid for loading
7872 */
7873 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7874
7875 vcpu->arch.cr0 |= X86_CR0_ET;
7876 }
7877
7878 /* Swap (qemu) user FPU context for the guest FPU context. */
7879 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7880 {
7881 preempt_disable();
7882 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7883 /* PKRU is separately restored in kvm_x86_ops->run. */
7884 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7885 ~XFEATURE_MASK_PKRU);
7886 preempt_enable();
7887 trace_kvm_fpu(1);
7888 }
7889
7890 /* When vcpu_run ends, restore user space FPU context. */
7891 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7892 {
7893 preempt_disable();
7894 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7895 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7896 preempt_enable();
7897 ++vcpu->stat.fpu_reload;
7898 trace_kvm_fpu(0);
7899 }
7900
7901 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7902 {
7903 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7904
7905 kvmclock_reset(vcpu);
7906
7907 kvm_x86_ops->vcpu_free(vcpu);
7908 free_cpumask_var(wbinvd_dirty_mask);
7909 }
7910
7911 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7912 unsigned int id)
7913 {
7914 struct kvm_vcpu *vcpu;
7915
7916 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7917 printk_once(KERN_WARNING
7918 "kvm: SMP vm created on host with unstable TSC; "
7919 "guest TSC will not be reliable\n");
7920
7921 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7922
7923 return vcpu;
7924 }
7925
7926 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7927 {
7928 int r;
7929
7930 kvm_vcpu_mtrr_init(vcpu);
7931 r = vcpu_load(vcpu);
7932 if (r)
7933 return r;
7934 kvm_vcpu_reset(vcpu, false);
7935 kvm_mmu_setup(vcpu);
7936 vcpu_put(vcpu);
7937 return r;
7938 }
7939
7940 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7941 {
7942 struct msr_data msr;
7943 struct kvm *kvm = vcpu->kvm;
7944
7945 kvm_hv_vcpu_postcreate(vcpu);
7946
7947 if (vcpu_load(vcpu))
7948 return;
7949 msr.data = 0x0;
7950 msr.index = MSR_IA32_TSC;
7951 msr.host_initiated = true;
7952 kvm_write_tsc(vcpu, &msr);
7953 vcpu_put(vcpu);
7954
7955 if (!kvmclock_periodic_sync)
7956 return;
7957
7958 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7959 KVMCLOCK_SYNC_PERIOD);
7960 }
7961
7962 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7963 {
7964 int r;
7965 vcpu->arch.apf.msr_val = 0;
7966
7967 r = vcpu_load(vcpu);
7968 BUG_ON(r);
7969 kvm_mmu_unload(vcpu);
7970 vcpu_put(vcpu);
7971
7972 kvm_x86_ops->vcpu_free(vcpu);
7973 }
7974
7975 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7976 {
7977 kvm_lapic_reset(vcpu, init_event);
7978
7979 vcpu->arch.hflags = 0;
7980
7981 vcpu->arch.smi_pending = 0;
7982 atomic_set(&vcpu->arch.nmi_queued, 0);
7983 vcpu->arch.nmi_pending = 0;
7984 vcpu->arch.nmi_injected = false;
7985 kvm_clear_interrupt_queue(vcpu);
7986 kvm_clear_exception_queue(vcpu);
7987 vcpu->arch.exception.pending = false;
7988
7989 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7990 kvm_update_dr0123(vcpu);
7991 vcpu->arch.dr6 = DR6_INIT;
7992 kvm_update_dr6(vcpu);
7993 vcpu->arch.dr7 = DR7_FIXED_1;
7994 kvm_update_dr7(vcpu);
7995
7996 vcpu->arch.cr2 = 0;
7997
7998 kvm_make_request(KVM_REQ_EVENT, vcpu);
7999 vcpu->arch.apf.msr_val = 0;
8000 vcpu->arch.st.msr_val = 0;
8001
8002 kvmclock_reset(vcpu);
8003
8004 kvm_clear_async_pf_completion_queue(vcpu);
8005 kvm_async_pf_hash_reset(vcpu);
8006 vcpu->arch.apf.halted = false;
8007
8008 if (kvm_mpx_supported()) {
8009 void *mpx_state_buffer;
8010
8011 /*
8012 * To avoid have the INIT path from kvm_apic_has_events() that be
8013 * called with loaded FPU and does not let userspace fix the state.
8014 */
8015 if (init_event)
8016 kvm_put_guest_fpu(vcpu);
8017 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8018 XFEATURE_MASK_BNDREGS);
8019 if (mpx_state_buffer)
8020 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8021 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8022 XFEATURE_MASK_BNDCSR);
8023 if (mpx_state_buffer)
8024 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
8025 if (init_event)
8026 kvm_load_guest_fpu(vcpu);
8027 }
8028
8029 if (!init_event) {
8030 kvm_pmu_reset(vcpu);
8031 vcpu->arch.smbase = 0x30000;
8032
8033 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8034 vcpu->arch.msr_misc_features_enables = 0;
8035
8036 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8037 }
8038
8039 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8040 vcpu->arch.regs_avail = ~0;
8041 vcpu->arch.regs_dirty = ~0;
8042
8043 vcpu->arch.ia32_xss = 0;
8044
8045 kvm_x86_ops->vcpu_reset(vcpu, init_event);
8046 }
8047
8048 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8049 {
8050 struct kvm_segment cs;
8051
8052 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8053 cs.selector = vector << 8;
8054 cs.base = vector << 12;
8055 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8056 kvm_rip_write(vcpu, 0);
8057 }
8058
8059 int kvm_arch_hardware_enable(void)
8060 {
8061 struct kvm *kvm;
8062 struct kvm_vcpu *vcpu;
8063 int i;
8064 int ret;
8065 u64 local_tsc;
8066 u64 max_tsc = 0;
8067 bool stable, backwards_tsc = false;
8068
8069 kvm_shared_msr_cpu_online();
8070 ret = kvm_x86_ops->hardware_enable();
8071 if (ret != 0)
8072 return ret;
8073
8074 local_tsc = rdtsc();
8075 stable = !check_tsc_unstable();
8076 list_for_each_entry(kvm, &vm_list, vm_list) {
8077 kvm_for_each_vcpu(i, vcpu, kvm) {
8078 if (!stable && vcpu->cpu == smp_processor_id())
8079 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8080 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8081 backwards_tsc = true;
8082 if (vcpu->arch.last_host_tsc > max_tsc)
8083 max_tsc = vcpu->arch.last_host_tsc;
8084 }
8085 }
8086 }
8087
8088 /*
8089 * Sometimes, even reliable TSCs go backwards. This happens on
8090 * platforms that reset TSC during suspend or hibernate actions, but
8091 * maintain synchronization. We must compensate. Fortunately, we can
8092 * detect that condition here, which happens early in CPU bringup,
8093 * before any KVM threads can be running. Unfortunately, we can't
8094 * bring the TSCs fully up to date with real time, as we aren't yet far
8095 * enough into CPU bringup that we know how much real time has actually
8096 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
8097 * variables that haven't been updated yet.
8098 *
8099 * So we simply find the maximum observed TSC above, then record the
8100 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8101 * the adjustment will be applied. Note that we accumulate
8102 * adjustments, in case multiple suspend cycles happen before some VCPU
8103 * gets a chance to run again. In the event that no KVM threads get a
8104 * chance to run, we will miss the entire elapsed period, as we'll have
8105 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8106 * loose cycle time. This isn't too big a deal, since the loss will be
8107 * uniform across all VCPUs (not to mention the scenario is extremely
8108 * unlikely). It is possible that a second hibernate recovery happens
8109 * much faster than a first, causing the observed TSC here to be
8110 * smaller; this would require additional padding adjustment, which is
8111 * why we set last_host_tsc to the local tsc observed here.
8112 *
8113 * N.B. - this code below runs only on platforms with reliable TSC,
8114 * as that is the only way backwards_tsc is set above. Also note
8115 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8116 * have the same delta_cyc adjustment applied if backwards_tsc
8117 * is detected. Note further, this adjustment is only done once,
8118 * as we reset last_host_tsc on all VCPUs to stop this from being
8119 * called multiple times (one for each physical CPU bringup).
8120 *
8121 * Platforms with unreliable TSCs don't have to deal with this, they
8122 * will be compensated by the logic in vcpu_load, which sets the TSC to
8123 * catchup mode. This will catchup all VCPUs to real time, but cannot
8124 * guarantee that they stay in perfect synchronization.
8125 */
8126 if (backwards_tsc) {
8127 u64 delta_cyc = max_tsc - local_tsc;
8128 list_for_each_entry(kvm, &vm_list, vm_list) {
8129 kvm->arch.backwards_tsc_observed = true;
8130 kvm_for_each_vcpu(i, vcpu, kvm) {
8131 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8132 vcpu->arch.last_host_tsc = local_tsc;
8133 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8134 }
8135
8136 /*
8137 * We have to disable TSC offset matching.. if you were
8138 * booting a VM while issuing an S4 host suspend....
8139 * you may have some problem. Solving this issue is
8140 * left as an exercise to the reader.
8141 */
8142 kvm->arch.last_tsc_nsec = 0;
8143 kvm->arch.last_tsc_write = 0;
8144 }
8145
8146 }
8147 return 0;
8148 }
8149
8150 void kvm_arch_hardware_disable(void)
8151 {
8152 kvm_x86_ops->hardware_disable();
8153 drop_user_return_notifiers();
8154 }
8155
8156 int kvm_arch_hardware_setup(void)
8157 {
8158 int r;
8159
8160 r = kvm_x86_ops->hardware_setup();
8161 if (r != 0)
8162 return r;
8163
8164 if (kvm_has_tsc_control) {
8165 /*
8166 * Make sure the user can only configure tsc_khz values that
8167 * fit into a signed integer.
8168 * A min value is not calculated needed because it will always
8169 * be 1 on all machines.
8170 */
8171 u64 max = min(0x7fffffffULL,
8172 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8173 kvm_max_guest_tsc_khz = max;
8174
8175 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
8176 }
8177
8178 kvm_init_msr_list();
8179 return 0;
8180 }
8181
8182 void kvm_arch_hardware_unsetup(void)
8183 {
8184 kvm_x86_ops->hardware_unsetup();
8185 }
8186
8187 void kvm_arch_check_processor_compat(void *rtn)
8188 {
8189 kvm_x86_ops->check_processor_compatibility(rtn);
8190 }
8191
8192 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8193 {
8194 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8195 }
8196 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8197
8198 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8199 {
8200 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
8201 }
8202
8203 struct static_key kvm_no_apic_vcpu __read_mostly;
8204 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
8205
8206 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8207 {
8208 struct page *page;
8209 int r;
8210
8211 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
8212 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
8213 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
8214 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8215 else
8216 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
8217
8218 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8219 if (!page) {
8220 r = -ENOMEM;
8221 goto fail;
8222 }
8223 vcpu->arch.pio_data = page_address(page);
8224
8225 kvm_set_tsc_khz(vcpu, max_tsc_khz);
8226
8227 r = kvm_mmu_create(vcpu);
8228 if (r < 0)
8229 goto fail_free_pio_data;
8230
8231 if (irqchip_in_kernel(vcpu->kvm)) {
8232 r = kvm_create_lapic(vcpu);
8233 if (r < 0)
8234 goto fail_mmu_destroy;
8235 } else
8236 static_key_slow_inc(&kvm_no_apic_vcpu);
8237
8238 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8239 GFP_KERNEL);
8240 if (!vcpu->arch.mce_banks) {
8241 r = -ENOMEM;
8242 goto fail_free_lapic;
8243 }
8244 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8245
8246 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8247 r = -ENOMEM;
8248 goto fail_free_mce_banks;
8249 }
8250
8251 fx_init(vcpu);
8252
8253 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
8254
8255 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8256
8257 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8258
8259 kvm_async_pf_hash_reset(vcpu);
8260 kvm_pmu_init(vcpu);
8261
8262 vcpu->arch.pending_external_vector = -1;
8263 vcpu->arch.preempted_in_kernel = false;
8264
8265 kvm_hv_vcpu_init(vcpu);
8266
8267 return 0;
8268
8269 fail_free_mce_banks:
8270 kfree(vcpu->arch.mce_banks);
8271 fail_free_lapic:
8272 kvm_free_lapic(vcpu);
8273 fail_mmu_destroy:
8274 kvm_mmu_destroy(vcpu);
8275 fail_free_pio_data:
8276 free_page((unsigned long)vcpu->arch.pio_data);
8277 fail:
8278 return r;
8279 }
8280
8281 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8282 {
8283 int idx;
8284
8285 kvm_hv_vcpu_uninit(vcpu);
8286 kvm_pmu_destroy(vcpu);
8287 kfree(vcpu->arch.mce_banks);
8288 kvm_free_lapic(vcpu);
8289 idx = srcu_read_lock(&vcpu->kvm->srcu);
8290 kvm_mmu_destroy(vcpu);
8291 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8292 free_page((unsigned long)vcpu->arch.pio_data);
8293 if (!lapic_in_kernel(vcpu))
8294 static_key_slow_dec(&kvm_no_apic_vcpu);
8295 }
8296
8297 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8298 {
8299 vcpu->arch.l1tf_flush_l1d = true;
8300 kvm_x86_ops->sched_in(vcpu, cpu);
8301 }
8302
8303 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
8304 {
8305 if (type)
8306 return -EINVAL;
8307
8308 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
8309 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
8310 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
8311 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
8312 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
8313
8314 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8315 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
8316 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8317 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8318 &kvm->arch.irq_sources_bitmap);
8319
8320 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
8321 mutex_init(&kvm->arch.apic_map_lock);
8322 mutex_init(&kvm->arch.hyperv.hv_lock);
8323 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8324
8325 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
8326 pvclock_update_vm_gtod_copy(kvm);
8327
8328 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
8329 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
8330
8331 kvm_page_track_init(kvm);
8332 kvm_mmu_init_vm(kvm);
8333
8334 if (kvm_x86_ops->vm_init)
8335 return kvm_x86_ops->vm_init(kvm);
8336
8337 return 0;
8338 }
8339
8340 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8341 {
8342 int r;
8343 r = vcpu_load(vcpu);
8344 BUG_ON(r);
8345 kvm_mmu_unload(vcpu);
8346 vcpu_put(vcpu);
8347 }
8348
8349 static void kvm_free_vcpus(struct kvm *kvm)
8350 {
8351 unsigned int i;
8352 struct kvm_vcpu *vcpu;
8353
8354 /*
8355 * Unpin any mmu pages first.
8356 */
8357 kvm_for_each_vcpu(i, vcpu, kvm) {
8358 kvm_clear_async_pf_completion_queue(vcpu);
8359 kvm_unload_vcpu_mmu(vcpu);
8360 }
8361 kvm_for_each_vcpu(i, vcpu, kvm)
8362 kvm_arch_vcpu_free(vcpu);
8363
8364 mutex_lock(&kvm->lock);
8365 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8366 kvm->vcpus[i] = NULL;
8367
8368 atomic_set(&kvm->online_vcpus, 0);
8369 mutex_unlock(&kvm->lock);
8370 }
8371
8372 void kvm_arch_sync_events(struct kvm *kvm)
8373 {
8374 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
8375 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
8376 kvm_free_pit(kvm);
8377 }
8378
8379 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8380 {
8381 int i, r;
8382 unsigned long hva;
8383 struct kvm_memslots *slots = kvm_memslots(kvm);
8384 struct kvm_memory_slot *slot, old;
8385
8386 /* Called with kvm->slots_lock held. */
8387 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8388 return -EINVAL;
8389
8390 slot = id_to_memslot(slots, id);
8391 if (size) {
8392 if (slot->npages)
8393 return -EEXIST;
8394
8395 /*
8396 * MAP_SHARED to prevent internal slot pages from being moved
8397 * by fork()/COW.
8398 */
8399 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8400 MAP_SHARED | MAP_ANONYMOUS, 0);
8401 if (IS_ERR((void *)hva))
8402 return PTR_ERR((void *)hva);
8403 } else {
8404 if (!slot->npages)
8405 return 0;
8406
8407 hva = 0;
8408 }
8409
8410 old = *slot;
8411 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8412 struct kvm_userspace_memory_region m;
8413
8414 m.slot = id | (i << 16);
8415 m.flags = 0;
8416 m.guest_phys_addr = gpa;
8417 m.userspace_addr = hva;
8418 m.memory_size = size;
8419 r = __kvm_set_memory_region(kvm, &m);
8420 if (r < 0)
8421 return r;
8422 }
8423
8424 if (!size)
8425 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8426
8427 return 0;
8428 }
8429 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8430
8431 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8432 {
8433 int r;
8434
8435 mutex_lock(&kvm->slots_lock);
8436 r = __x86_set_memory_region(kvm, id, gpa, size);
8437 mutex_unlock(&kvm->slots_lock);
8438
8439 return r;
8440 }
8441 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8442
8443 void kvm_arch_destroy_vm(struct kvm *kvm)
8444 {
8445 if (current->mm == kvm->mm) {
8446 /*
8447 * Free memory regions allocated on behalf of userspace,
8448 * unless the the memory map has changed due to process exit
8449 * or fd copying.
8450 */
8451 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8452 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8453 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8454 }
8455 if (kvm_x86_ops->vm_destroy)
8456 kvm_x86_ops->vm_destroy(kvm);
8457 kvm_pic_destroy(kvm);
8458 kvm_ioapic_destroy(kvm);
8459 kvm_free_vcpus(kvm);
8460 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8461 kvm_mmu_uninit_vm(kvm);
8462 kvm_page_track_cleanup(kvm);
8463 }
8464
8465 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8466 struct kvm_memory_slot *dont)
8467 {
8468 int i;
8469
8470 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8471 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8472 kvfree(free->arch.rmap[i]);
8473 free->arch.rmap[i] = NULL;
8474 }
8475 if (i == 0)
8476 continue;
8477
8478 if (!dont || free->arch.lpage_info[i - 1] !=
8479 dont->arch.lpage_info[i - 1]) {
8480 kvfree(free->arch.lpage_info[i - 1]);
8481 free->arch.lpage_info[i - 1] = NULL;
8482 }
8483 }
8484
8485 kvm_page_track_free_memslot(free, dont);
8486 }
8487
8488 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8489 unsigned long npages)
8490 {
8491 int i;
8492
8493 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8494 struct kvm_lpage_info *linfo;
8495 unsigned long ugfn;
8496 int lpages;
8497 int level = i + 1;
8498
8499 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8500 slot->base_gfn, level) + 1;
8501
8502 slot->arch.rmap[i] =
8503 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
8504 if (!slot->arch.rmap[i])
8505 goto out_free;
8506 if (i == 0)
8507 continue;
8508
8509 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
8510 if (!linfo)
8511 goto out_free;
8512
8513 slot->arch.lpage_info[i - 1] = linfo;
8514
8515 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8516 linfo[0].disallow_lpage = 1;
8517 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8518 linfo[lpages - 1].disallow_lpage = 1;
8519 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8520 /*
8521 * If the gfn and userspace address are not aligned wrt each
8522 * other, or if explicitly asked to, disable large page
8523 * support for this slot
8524 */
8525 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8526 !kvm_largepages_enabled()) {
8527 unsigned long j;
8528
8529 for (j = 0; j < lpages; ++j)
8530 linfo[j].disallow_lpage = 1;
8531 }
8532 }
8533
8534 if (kvm_page_track_create_memslot(slot, npages))
8535 goto out_free;
8536
8537 return 0;
8538
8539 out_free:
8540 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8541 kvfree(slot->arch.rmap[i]);
8542 slot->arch.rmap[i] = NULL;
8543 if (i == 0)
8544 continue;
8545
8546 kvfree(slot->arch.lpage_info[i - 1]);
8547 slot->arch.lpage_info[i - 1] = NULL;
8548 }
8549 return -ENOMEM;
8550 }
8551
8552 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8553 {
8554 /*
8555 * memslots->generation has been incremented.
8556 * mmio generation may have reached its maximum value.
8557 */
8558 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8559 }
8560
8561 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8562 struct kvm_memory_slot *memslot,
8563 const struct kvm_userspace_memory_region *mem,
8564 enum kvm_mr_change change)
8565 {
8566 return 0;
8567 }
8568
8569 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8570 struct kvm_memory_slot *new)
8571 {
8572 /* Still write protect RO slot */
8573 if (new->flags & KVM_MEM_READONLY) {
8574 kvm_mmu_slot_remove_write_access(kvm, new);
8575 return;
8576 }
8577
8578 /*
8579 * Call kvm_x86_ops dirty logging hooks when they are valid.
8580 *
8581 * kvm_x86_ops->slot_disable_log_dirty is called when:
8582 *
8583 * - KVM_MR_CREATE with dirty logging is disabled
8584 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8585 *
8586 * The reason is, in case of PML, we need to set D-bit for any slots
8587 * with dirty logging disabled in order to eliminate unnecessary GPA
8588 * logging in PML buffer (and potential PML buffer full VMEXT). This
8589 * guarantees leaving PML enabled during guest's lifetime won't have
8590 * any additonal overhead from PML when guest is running with dirty
8591 * logging disabled for memory slots.
8592 *
8593 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8594 * to dirty logging mode.
8595 *
8596 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8597 *
8598 * In case of write protect:
8599 *
8600 * Write protect all pages for dirty logging.
8601 *
8602 * All the sptes including the large sptes which point to this
8603 * slot are set to readonly. We can not create any new large
8604 * spte on this slot until the end of the logging.
8605 *
8606 * See the comments in fast_page_fault().
8607 */
8608 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8609 if (kvm_x86_ops->slot_enable_log_dirty)
8610 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8611 else
8612 kvm_mmu_slot_remove_write_access(kvm, new);
8613 } else {
8614 if (kvm_x86_ops->slot_disable_log_dirty)
8615 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8616 }
8617 }
8618
8619 void kvm_arch_commit_memory_region(struct kvm *kvm,
8620 const struct kvm_userspace_memory_region *mem,
8621 const struct kvm_memory_slot *old,
8622 const struct kvm_memory_slot *new,
8623 enum kvm_mr_change change)
8624 {
8625 int nr_mmu_pages = 0;
8626
8627 if (!kvm->arch.n_requested_mmu_pages)
8628 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8629
8630 if (nr_mmu_pages)
8631 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8632
8633 /*
8634 * Dirty logging tracks sptes in 4k granularity, meaning that large
8635 * sptes have to be split. If live migration is successful, the guest
8636 * in the source machine will be destroyed and large sptes will be
8637 * created in the destination. However, if the guest continues to run
8638 * in the source machine (for example if live migration fails), small
8639 * sptes will remain around and cause bad performance.
8640 *
8641 * Scan sptes if dirty logging has been stopped, dropping those
8642 * which can be collapsed into a single large-page spte. Later
8643 * page faults will create the large-page sptes.
8644 */
8645 if ((change != KVM_MR_DELETE) &&
8646 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8647 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8648 kvm_mmu_zap_collapsible_sptes(kvm, new);
8649
8650 /*
8651 * Set up write protection and/or dirty logging for the new slot.
8652 *
8653 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8654 * been zapped so no dirty logging staff is needed for old slot. For
8655 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8656 * new and it's also covered when dealing with the new slot.
8657 *
8658 * FIXME: const-ify all uses of struct kvm_memory_slot.
8659 */
8660 if (change != KVM_MR_DELETE)
8661 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8662 }
8663
8664 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8665 {
8666 kvm_mmu_invalidate_zap_all_pages(kvm);
8667 }
8668
8669 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8670 struct kvm_memory_slot *slot)
8671 {
8672 kvm_page_track_flush_slot(kvm, slot);
8673 }
8674
8675 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8676 {
8677 if (!list_empty_careful(&vcpu->async_pf.done))
8678 return true;
8679
8680 if (kvm_apic_has_events(vcpu))
8681 return true;
8682
8683 if (vcpu->arch.pv.pv_unhalted)
8684 return true;
8685
8686 if (vcpu->arch.exception.pending)
8687 return true;
8688
8689 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8690 (vcpu->arch.nmi_pending &&
8691 kvm_x86_ops->nmi_allowed(vcpu)))
8692 return true;
8693
8694 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8695 (vcpu->arch.smi_pending && !is_smm(vcpu)))
8696 return true;
8697
8698 if (kvm_arch_interrupt_allowed(vcpu) &&
8699 kvm_cpu_has_interrupt(vcpu))
8700 return true;
8701
8702 if (kvm_hv_has_stimer_pending(vcpu))
8703 return true;
8704
8705 return false;
8706 }
8707
8708 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8709 {
8710 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8711 }
8712
8713 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8714 {
8715 return vcpu->arch.preempted_in_kernel;
8716 }
8717
8718 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8719 {
8720 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8721 }
8722
8723 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8724 {
8725 return kvm_x86_ops->interrupt_allowed(vcpu);
8726 }
8727
8728 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8729 {
8730 if (is_64_bit_mode(vcpu))
8731 return kvm_rip_read(vcpu);
8732 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8733 kvm_rip_read(vcpu));
8734 }
8735 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8736
8737 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8738 {
8739 return kvm_get_linear_rip(vcpu) == linear_rip;
8740 }
8741 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8742
8743 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8744 {
8745 unsigned long rflags;
8746
8747 rflags = kvm_x86_ops->get_rflags(vcpu);
8748 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8749 rflags &= ~X86_EFLAGS_TF;
8750 return rflags;
8751 }
8752 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8753
8754 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8755 {
8756 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8757 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8758 rflags |= X86_EFLAGS_TF;
8759 kvm_x86_ops->set_rflags(vcpu, rflags);
8760 }
8761
8762 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8763 {
8764 __kvm_set_rflags(vcpu, rflags);
8765 kvm_make_request(KVM_REQ_EVENT, vcpu);
8766 }
8767 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8768
8769 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8770 {
8771 int r;
8772
8773 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8774 work->wakeup_all)
8775 return;
8776
8777 r = kvm_mmu_reload(vcpu);
8778 if (unlikely(r))
8779 return;
8780
8781 if (!vcpu->arch.mmu.direct_map &&
8782 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8783 return;
8784
8785 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8786 }
8787
8788 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8789 {
8790 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8791 }
8792
8793 static inline u32 kvm_async_pf_next_probe(u32 key)
8794 {
8795 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8796 }
8797
8798 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8799 {
8800 u32 key = kvm_async_pf_hash_fn(gfn);
8801
8802 while (vcpu->arch.apf.gfns[key] != ~0)
8803 key = kvm_async_pf_next_probe(key);
8804
8805 vcpu->arch.apf.gfns[key] = gfn;
8806 }
8807
8808 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8809 {
8810 int i;
8811 u32 key = kvm_async_pf_hash_fn(gfn);
8812
8813 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8814 (vcpu->arch.apf.gfns[key] != gfn &&
8815 vcpu->arch.apf.gfns[key] != ~0); i++)
8816 key = kvm_async_pf_next_probe(key);
8817
8818 return key;
8819 }
8820
8821 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8822 {
8823 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8824 }
8825
8826 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8827 {
8828 u32 i, j, k;
8829
8830 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8831 while (true) {
8832 vcpu->arch.apf.gfns[i] = ~0;
8833 do {
8834 j = kvm_async_pf_next_probe(j);
8835 if (vcpu->arch.apf.gfns[j] == ~0)
8836 return;
8837 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8838 /*
8839 * k lies cyclically in ]i,j]
8840 * | i.k.j |
8841 * |....j i.k.| or |.k..j i...|
8842 */
8843 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8844 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8845 i = j;
8846 }
8847 }
8848
8849 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8850 {
8851
8852 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8853 sizeof(val));
8854 }
8855
8856 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8857 {
8858
8859 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8860 sizeof(u32));
8861 }
8862
8863 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8864 struct kvm_async_pf *work)
8865 {
8866 struct x86_exception fault;
8867
8868 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8869 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8870
8871 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8872 (vcpu->arch.apf.send_user_only &&
8873 kvm_x86_ops->get_cpl(vcpu) == 0))
8874 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8875 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8876 fault.vector = PF_VECTOR;
8877 fault.error_code_valid = true;
8878 fault.error_code = 0;
8879 fault.nested_page_fault = false;
8880 fault.address = work->arch.token;
8881 fault.async_page_fault = true;
8882 kvm_inject_page_fault(vcpu, &fault);
8883 }
8884 }
8885
8886 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8887 struct kvm_async_pf *work)
8888 {
8889 struct x86_exception fault;
8890 u32 val;
8891
8892 if (work->wakeup_all)
8893 work->arch.token = ~0; /* broadcast wakeup */
8894 else
8895 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8896 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8897
8898 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8899 !apf_get_user(vcpu, &val)) {
8900 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8901 vcpu->arch.exception.pending &&
8902 vcpu->arch.exception.nr == PF_VECTOR &&
8903 !apf_put_user(vcpu, 0)) {
8904 vcpu->arch.exception.injected = false;
8905 vcpu->arch.exception.pending = false;
8906 vcpu->arch.exception.nr = 0;
8907 vcpu->arch.exception.has_error_code = false;
8908 vcpu->arch.exception.error_code = 0;
8909 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8910 fault.vector = PF_VECTOR;
8911 fault.error_code_valid = true;
8912 fault.error_code = 0;
8913 fault.nested_page_fault = false;
8914 fault.address = work->arch.token;
8915 fault.async_page_fault = true;
8916 kvm_inject_page_fault(vcpu, &fault);
8917 }
8918 }
8919 vcpu->arch.apf.halted = false;
8920 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8921 }
8922
8923 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8924 {
8925 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8926 return true;
8927 else
8928 return kvm_can_do_async_pf(vcpu);
8929 }
8930
8931 void kvm_arch_start_assignment(struct kvm *kvm)
8932 {
8933 atomic_inc(&kvm->arch.assigned_device_count);
8934 }
8935 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8936
8937 void kvm_arch_end_assignment(struct kvm *kvm)
8938 {
8939 atomic_dec(&kvm->arch.assigned_device_count);
8940 }
8941 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8942
8943 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8944 {
8945 return atomic_read(&kvm->arch.assigned_device_count);
8946 }
8947 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8948
8949 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8950 {
8951 atomic_inc(&kvm->arch.noncoherent_dma_count);
8952 }
8953 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8954
8955 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8956 {
8957 atomic_dec(&kvm->arch.noncoherent_dma_count);
8958 }
8959 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8960
8961 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8962 {
8963 return atomic_read(&kvm->arch.noncoherent_dma_count);
8964 }
8965 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8966
8967 bool kvm_arch_has_irq_bypass(void)
8968 {
8969 return kvm_x86_ops->update_pi_irte != NULL;
8970 }
8971
8972 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8973 struct irq_bypass_producer *prod)
8974 {
8975 struct kvm_kernel_irqfd *irqfd =
8976 container_of(cons, struct kvm_kernel_irqfd, consumer);
8977
8978 irqfd->producer = prod;
8979
8980 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8981 prod->irq, irqfd->gsi, 1);
8982 }
8983
8984 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8985 struct irq_bypass_producer *prod)
8986 {
8987 int ret;
8988 struct kvm_kernel_irqfd *irqfd =
8989 container_of(cons, struct kvm_kernel_irqfd, consumer);
8990
8991 WARN_ON(irqfd->producer != prod);
8992 irqfd->producer = NULL;
8993
8994 /*
8995 * When producer of consumer is unregistered, we change back to
8996 * remapped mode, so we can re-use the current implementation
8997 * when the irq is masked/disabled or the consumer side (KVM
8998 * int this case doesn't want to receive the interrupts.
8999 */
9000 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9001 if (ret)
9002 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9003 " fails: %d\n", irqfd->consumer.token, ret);
9004 }
9005
9006 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9007 uint32_t guest_irq, bool set)
9008 {
9009 if (!kvm_x86_ops->update_pi_irte)
9010 return -EINVAL;
9011
9012 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9013 }
9014
9015 bool kvm_vector_hashing_enabled(void)
9016 {
9017 return vector_hashing;
9018 }
9019 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9020
9021 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9022 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9023 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9024 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9025 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9026 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9027 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9028 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9029 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9030 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9031 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9032 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9033 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9034 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9035 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9036 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9037 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9038 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9039 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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