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[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <trace/events/kvm.h>
57
58 #define CREATE_TRACE_POINTS
59 #include "trace.h"
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70
71 #define MAX_IO_MSRS 256
72 #define KVM_MAX_MCE_BANKS 32
73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
74
75 #define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
78 /* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82 #ifdef CONFIG_X86_64
83 static
84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
85 #else
86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
87 #endif
88
89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
91
92 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
93 static void process_nmi(struct kvm_vcpu *vcpu);
94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
95
96 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
97 EXPORT_SYMBOL_GPL(kvm_x86_ops);
98
99 static bool __read_mostly ignore_msrs = 0;
100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
102 unsigned int min_timer_period_us = 500;
103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
105 static bool __read_mostly kvmclock_periodic_sync = true;
106 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
108 bool __read_mostly kvm_has_tsc_control;
109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
110 u32 __read_mostly kvm_max_guest_tsc_khz;
111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114 u64 __read_mostly kvm_max_tsc_scaling_ratio;
115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
116 static u64 __read_mostly kvm_default_tsc_scaling_ratio;
117
118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
119 static u32 __read_mostly tsc_tolerance_ppm = 250;
120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
123 unsigned int __read_mostly lapic_timer_advance_ns = 0;
124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
126 static bool __read_mostly vector_hashing = true;
127 module_param(vector_hashing, bool, S_IRUGO);
128
129 static bool __read_mostly backwards_tsc_observed = false;
130
131 #define KVM_NR_SHARED_MSRS 16
132
133 struct kvm_shared_msrs_global {
134 int nr;
135 u32 msrs[KVM_NR_SHARED_MSRS];
136 };
137
138 struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
145 };
146
147 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
148 static struct kvm_shared_msrs __percpu *shared_msrs;
149
150 struct kvm_stats_debugfs_item debugfs_entries[] = {
151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
161 { "halt_exits", VCPU_STAT(halt_exits) },
162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
164 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
165 { "hypercalls", VCPU_STAT(hypercalls) },
166 { "request_irq", VCPU_STAT(request_irq_exits) },
167 { "irq_exits", VCPU_STAT(irq_exits) },
168 { "host_state_reload", VCPU_STAT(host_state_reload) },
169 { "efer_reload", VCPU_STAT(efer_reload) },
170 { "fpu_reload", VCPU_STAT(fpu_reload) },
171 { "insn_emulation", VCPU_STAT(insn_emulation) },
172 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
173 { "irq_injections", VCPU_STAT(irq_injections) },
174 { "nmi_injections", VCPU_STAT(nmi_injections) },
175 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
176 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
177 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
178 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
179 { "mmu_flooded", VM_STAT(mmu_flooded) },
180 { "mmu_recycled", VM_STAT(mmu_recycled) },
181 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
182 { "mmu_unsync", VM_STAT(mmu_unsync) },
183 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
184 { "largepages", VM_STAT(lpages) },
185 { NULL }
186 };
187
188 u64 __read_mostly host_xcr0;
189
190 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
191
192 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
193 {
194 int i;
195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
196 vcpu->arch.apf.gfns[i] = ~0;
197 }
198
199 static void kvm_on_user_return(struct user_return_notifier *urn)
200 {
201 unsigned slot;
202 struct kvm_shared_msrs *locals
203 = container_of(urn, struct kvm_shared_msrs, urn);
204 struct kvm_shared_msr_values *values;
205
206 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
207 values = &locals->values[slot];
208 if (values->host != values->curr) {
209 wrmsrl(shared_msrs_global.msrs[slot], values->host);
210 values->curr = values->host;
211 }
212 }
213 locals->registered = false;
214 user_return_notifier_unregister(urn);
215 }
216
217 static void shared_msr_update(unsigned slot, u32 msr)
218 {
219 u64 value;
220 unsigned int cpu = smp_processor_id();
221 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
222
223 /* only read, and nobody should modify it at this time,
224 * so don't need lock */
225 if (slot >= shared_msrs_global.nr) {
226 printk(KERN_ERR "kvm: invalid MSR slot!");
227 return;
228 }
229 rdmsrl_safe(msr, &value);
230 smsr->values[slot].host = value;
231 smsr->values[slot].curr = value;
232 }
233
234 void kvm_define_shared_msr(unsigned slot, u32 msr)
235 {
236 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
237 shared_msrs_global.msrs[slot] = msr;
238 if (slot >= shared_msrs_global.nr)
239 shared_msrs_global.nr = slot + 1;
240 }
241 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
242
243 static void kvm_shared_msr_cpu_online(void)
244 {
245 unsigned i;
246
247 for (i = 0; i < shared_msrs_global.nr; ++i)
248 shared_msr_update(i, shared_msrs_global.msrs[i]);
249 }
250
251 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
252 {
253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
255 int err;
256
257 if (((value ^ smsr->values[slot].curr) & mask) == 0)
258 return 0;
259 smsr->values[slot].curr = value;
260 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
261 if (err)
262 return 1;
263
264 if (!smsr->registered) {
265 smsr->urn.on_user_return = kvm_on_user_return;
266 user_return_notifier_register(&smsr->urn);
267 smsr->registered = true;
268 }
269 return 0;
270 }
271 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
272
273 static void drop_user_return_notifiers(void)
274 {
275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
277
278 if (smsr->registered)
279 kvm_on_user_return(&smsr->urn);
280 }
281
282 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
283 {
284 return vcpu->arch.apic_base;
285 }
286 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
287
288 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
289 {
290 u64 old_state = vcpu->arch.apic_base &
291 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
292 u64 new_state = msr_info->data &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
295 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
296
297 if (!msr_info->host_initiated &&
298 ((msr_info->data & reserved_bits) != 0 ||
299 new_state == X2APIC_ENABLE ||
300 (new_state == MSR_IA32_APICBASE_ENABLE &&
301 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
302 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
303 old_state == 0)))
304 return 1;
305
306 kvm_lapic_set_base(vcpu, msr_info->data);
307 return 0;
308 }
309 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
310
311 asmlinkage __visible void kvm_spurious_fault(void)
312 {
313 /* Fault while not rebooting. We want the trace. */
314 BUG();
315 }
316 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
317
318 #define EXCPT_BENIGN 0
319 #define EXCPT_CONTRIBUTORY 1
320 #define EXCPT_PF 2
321
322 static int exception_class(int vector)
323 {
324 switch (vector) {
325 case PF_VECTOR:
326 return EXCPT_PF;
327 case DE_VECTOR:
328 case TS_VECTOR:
329 case NP_VECTOR:
330 case SS_VECTOR:
331 case GP_VECTOR:
332 return EXCPT_CONTRIBUTORY;
333 default:
334 break;
335 }
336 return EXCPT_BENIGN;
337 }
338
339 #define EXCPT_FAULT 0
340 #define EXCPT_TRAP 1
341 #define EXCPT_ABORT 2
342 #define EXCPT_INTERRUPT 3
343
344 static int exception_type(int vector)
345 {
346 unsigned int mask;
347
348 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
349 return EXCPT_INTERRUPT;
350
351 mask = 1 << vector;
352
353 /* #DB is trap, as instruction watchpoints are handled elsewhere */
354 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
355 return EXCPT_TRAP;
356
357 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
358 return EXCPT_ABORT;
359
360 /* Reserved exceptions will result in fault */
361 return EXCPT_FAULT;
362 }
363
364 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
365 unsigned nr, bool has_error, u32 error_code,
366 bool reinject)
367 {
368 u32 prev_nr;
369 int class1, class2;
370
371 kvm_make_request(KVM_REQ_EVENT, vcpu);
372
373 if (!vcpu->arch.exception.pending) {
374 queue:
375 if (has_error && !is_protmode(vcpu))
376 has_error = false;
377 vcpu->arch.exception.pending = true;
378 vcpu->arch.exception.has_error_code = has_error;
379 vcpu->arch.exception.nr = nr;
380 vcpu->arch.exception.error_code = error_code;
381 vcpu->arch.exception.reinject = reinject;
382 return;
383 }
384
385 /* to check exception */
386 prev_nr = vcpu->arch.exception.nr;
387 if (prev_nr == DF_VECTOR) {
388 /* triple fault -> shutdown */
389 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
390 return;
391 }
392 class1 = exception_class(prev_nr);
393 class2 = exception_class(nr);
394 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
395 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
396 /* generate double fault per SDM Table 5-5 */
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = true;
399 vcpu->arch.exception.nr = DF_VECTOR;
400 vcpu->arch.exception.error_code = 0;
401 } else
402 /* replace previous exception with a new one in a hope
403 that instruction re-execution will regenerate lost
404 exception */
405 goto queue;
406 }
407
408 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
409 {
410 kvm_multiple_exception(vcpu, nr, false, 0, false);
411 }
412 EXPORT_SYMBOL_GPL(kvm_queue_exception);
413
414 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
415 {
416 kvm_multiple_exception(vcpu, nr, false, 0, true);
417 }
418 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
419
420 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
421 {
422 if (err)
423 kvm_inject_gp(vcpu, 0);
424 else
425 kvm_x86_ops->skip_emulated_instruction(vcpu);
426 }
427 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
428
429 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
430 {
431 ++vcpu->stat.pf_guest;
432 vcpu->arch.cr2 = fault->address;
433 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
434 }
435 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
436
437 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
438 {
439 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
440 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
441 else
442 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
443
444 return fault->nested_page_fault;
445 }
446
447 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
448 {
449 atomic_inc(&vcpu->arch.nmi_queued);
450 kvm_make_request(KVM_REQ_NMI, vcpu);
451 }
452 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
453
454 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
455 {
456 kvm_multiple_exception(vcpu, nr, true, error_code, false);
457 }
458 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
459
460 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
461 {
462 kvm_multiple_exception(vcpu, nr, true, error_code, true);
463 }
464 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
465
466 /*
467 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
468 * a #GP and return false.
469 */
470 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
471 {
472 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
473 return true;
474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
475 return false;
476 }
477 EXPORT_SYMBOL_GPL(kvm_require_cpl);
478
479 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
480 {
481 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
482 return true;
483
484 kvm_queue_exception(vcpu, UD_VECTOR);
485 return false;
486 }
487 EXPORT_SYMBOL_GPL(kvm_require_dr);
488
489 /*
490 * This function will be used to read from the physical memory of the currently
491 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
492 * can read from guest physical or from the guest's guest physical memory.
493 */
494 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
495 gfn_t ngfn, void *data, int offset, int len,
496 u32 access)
497 {
498 struct x86_exception exception;
499 gfn_t real_gfn;
500 gpa_t ngpa;
501
502 ngpa = gfn_to_gpa(ngfn);
503 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
504 if (real_gfn == UNMAPPED_GVA)
505 return -EFAULT;
506
507 real_gfn = gpa_to_gfn(real_gfn);
508
509 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
510 }
511 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
512
513 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
514 void *data, int offset, int len, u32 access)
515 {
516 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
517 data, offset, len, access);
518 }
519
520 /*
521 * Load the pae pdptrs. Return true is they are all valid.
522 */
523 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
524 {
525 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
526 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
527 int i;
528 int ret;
529 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
530
531 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
532 offset * sizeof(u64), sizeof(pdpte),
533 PFERR_USER_MASK|PFERR_WRITE_MASK);
534 if (ret < 0) {
535 ret = 0;
536 goto out;
537 }
538 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
539 if (is_present_gpte(pdpte[i]) &&
540 (pdpte[i] &
541 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
542 ret = 0;
543 goto out;
544 }
545 }
546 ret = 1;
547
548 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
549 __set_bit(VCPU_EXREG_PDPTR,
550 (unsigned long *)&vcpu->arch.regs_avail);
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_dirty);
553 out:
554
555 return ret;
556 }
557 EXPORT_SYMBOL_GPL(load_pdptrs);
558
559 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
560 {
561 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
562 bool changed = true;
563 int offset;
564 gfn_t gfn;
565 int r;
566
567 if (is_long_mode(vcpu) || !is_pae(vcpu))
568 return false;
569
570 if (!test_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail))
572 return true;
573
574 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
575 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
576 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
577 PFERR_USER_MASK | PFERR_WRITE_MASK);
578 if (r < 0)
579 goto out;
580 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
581 out:
582
583 return changed;
584 }
585
586 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
587 {
588 unsigned long old_cr0 = kvm_read_cr0(vcpu);
589 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
590
591 cr0 |= X86_CR0_ET;
592
593 #ifdef CONFIG_X86_64
594 if (cr0 & 0xffffffff00000000UL)
595 return 1;
596 #endif
597
598 cr0 &= ~CR0_RESERVED_BITS;
599
600 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
601 return 1;
602
603 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
604 return 1;
605
606 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
607 #ifdef CONFIG_X86_64
608 if ((vcpu->arch.efer & EFER_LME)) {
609 int cs_db, cs_l;
610
611 if (!is_pae(vcpu))
612 return 1;
613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
614 if (cs_l)
615 return 1;
616 } else
617 #endif
618 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
619 kvm_read_cr3(vcpu)))
620 return 1;
621 }
622
623 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
624 return 1;
625
626 kvm_x86_ops->set_cr0(vcpu, cr0);
627
628 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
629 kvm_clear_async_pf_completion_queue(vcpu);
630 kvm_async_pf_hash_reset(vcpu);
631 }
632
633 if ((cr0 ^ old_cr0) & update_bits)
634 kvm_mmu_reset_context(vcpu);
635
636 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
637 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
638 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
639 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
640
641 return 0;
642 }
643 EXPORT_SYMBOL_GPL(kvm_set_cr0);
644
645 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
646 {
647 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
648 }
649 EXPORT_SYMBOL_GPL(kvm_lmsw);
650
651 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
652 {
653 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
654 !vcpu->guest_xcr0_loaded) {
655 /* kvm_set_xcr() also depends on this */
656 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
657 vcpu->guest_xcr0_loaded = 1;
658 }
659 }
660
661 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
662 {
663 if (vcpu->guest_xcr0_loaded) {
664 if (vcpu->arch.xcr0 != host_xcr0)
665 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
666 vcpu->guest_xcr0_loaded = 0;
667 }
668 }
669
670 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
671 {
672 u64 xcr0 = xcr;
673 u64 old_xcr0 = vcpu->arch.xcr0;
674 u64 valid_bits;
675
676 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
677 if (index != XCR_XFEATURE_ENABLED_MASK)
678 return 1;
679 if (!(xcr0 & XFEATURE_MASK_FP))
680 return 1;
681 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
682 return 1;
683
684 /*
685 * Do not allow the guest to set bits that we do not support
686 * saving. However, xcr0 bit 0 is always set, even if the
687 * emulated CPU does not support XSAVE (see fx_init).
688 */
689 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
690 if (xcr0 & ~valid_bits)
691 return 1;
692
693 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
694 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
695 return 1;
696
697 if (xcr0 & XFEATURE_MASK_AVX512) {
698 if (!(xcr0 & XFEATURE_MASK_YMM))
699 return 1;
700 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
701 return 1;
702 }
703 kvm_put_guest_xcr0(vcpu);
704 vcpu->arch.xcr0 = xcr0;
705
706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
707 kvm_update_cpuid(vcpu);
708 return 0;
709 }
710
711 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
712 {
713 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
714 __kvm_set_xcr(vcpu, index, xcr)) {
715 kvm_inject_gp(vcpu, 0);
716 return 1;
717 }
718 return 0;
719 }
720 EXPORT_SYMBOL_GPL(kvm_set_xcr);
721
722 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
723 {
724 unsigned long old_cr4 = kvm_read_cr4(vcpu);
725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
726 X86_CR4_SMEP | X86_CR4_SMAP;
727
728 if (cr4 & CR4_RESERVED_BITS)
729 return 1;
730
731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
732 return 1;
733
734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
735 return 1;
736
737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
738 return 1;
739
740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
741 return 1;
742
743 if (is_long_mode(vcpu)) {
744 if (!(cr4 & X86_CR4_PAE))
745 return 1;
746 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
747 && ((cr4 ^ old_cr4) & pdptr_bits)
748 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
749 kvm_read_cr3(vcpu)))
750 return 1;
751
752 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
753 if (!guest_cpuid_has_pcid(vcpu))
754 return 1;
755
756 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
757 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
758 return 1;
759 }
760
761 if (kvm_x86_ops->set_cr4(vcpu, cr4))
762 return 1;
763
764 if (((cr4 ^ old_cr4) & pdptr_bits) ||
765 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
766 kvm_mmu_reset_context(vcpu);
767
768 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
769 kvm_update_cpuid(vcpu);
770
771 return 0;
772 }
773 EXPORT_SYMBOL_GPL(kvm_set_cr4);
774
775 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
776 {
777 #ifdef CONFIG_X86_64
778 cr3 &= ~CR3_PCID_INVD;
779 #endif
780
781 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
782 kvm_mmu_sync_roots(vcpu);
783 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
784 return 0;
785 }
786
787 if (is_long_mode(vcpu)) {
788 if (cr3 & CR3_L_MODE_RESERVED_BITS)
789 return 1;
790 } else if (is_pae(vcpu) && is_paging(vcpu) &&
791 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
792 return 1;
793
794 vcpu->arch.cr3 = cr3;
795 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
796 kvm_mmu_new_cr3(vcpu);
797 return 0;
798 }
799 EXPORT_SYMBOL_GPL(kvm_set_cr3);
800
801 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
802 {
803 if (cr8 & CR8_RESERVED_BITS)
804 return 1;
805 if (lapic_in_kernel(vcpu))
806 kvm_lapic_set_tpr(vcpu, cr8);
807 else
808 vcpu->arch.cr8 = cr8;
809 return 0;
810 }
811 EXPORT_SYMBOL_GPL(kvm_set_cr8);
812
813 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
814 {
815 if (lapic_in_kernel(vcpu))
816 return kvm_lapic_get_cr8(vcpu);
817 else
818 return vcpu->arch.cr8;
819 }
820 EXPORT_SYMBOL_GPL(kvm_get_cr8);
821
822 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
823 {
824 int i;
825
826 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
827 for (i = 0; i < KVM_NR_DB_REGS; i++)
828 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
829 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
830 }
831 }
832
833 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
834 {
835 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
836 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
837 }
838
839 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
840 {
841 unsigned long dr7;
842
843 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
844 dr7 = vcpu->arch.guest_debug_dr7;
845 else
846 dr7 = vcpu->arch.dr7;
847 kvm_x86_ops->set_dr7(vcpu, dr7);
848 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
849 if (dr7 & DR7_BP_EN_MASK)
850 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
851 }
852
853 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
854 {
855 u64 fixed = DR6_FIXED_1;
856
857 if (!guest_cpuid_has_rtm(vcpu))
858 fixed |= DR6_RTM;
859 return fixed;
860 }
861
862 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
863 {
864 switch (dr) {
865 case 0 ... 3:
866 vcpu->arch.db[dr] = val;
867 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
868 vcpu->arch.eff_db[dr] = val;
869 break;
870 case 4:
871 /* fall through */
872 case 6:
873 if (val & 0xffffffff00000000ULL)
874 return -1; /* #GP */
875 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
876 kvm_update_dr6(vcpu);
877 break;
878 case 5:
879 /* fall through */
880 default: /* 7 */
881 if (val & 0xffffffff00000000ULL)
882 return -1; /* #GP */
883 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
884 kvm_update_dr7(vcpu);
885 break;
886 }
887
888 return 0;
889 }
890
891 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
892 {
893 if (__kvm_set_dr(vcpu, dr, val)) {
894 kvm_inject_gp(vcpu, 0);
895 return 1;
896 }
897 return 0;
898 }
899 EXPORT_SYMBOL_GPL(kvm_set_dr);
900
901 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
902 {
903 switch (dr) {
904 case 0 ... 3:
905 *val = vcpu->arch.db[dr];
906 break;
907 case 4:
908 /* fall through */
909 case 6:
910 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
911 *val = vcpu->arch.dr6;
912 else
913 *val = kvm_x86_ops->get_dr6(vcpu);
914 break;
915 case 5:
916 /* fall through */
917 default: /* 7 */
918 *val = vcpu->arch.dr7;
919 break;
920 }
921 return 0;
922 }
923 EXPORT_SYMBOL_GPL(kvm_get_dr);
924
925 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
926 {
927 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
928 u64 data;
929 int err;
930
931 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
932 if (err)
933 return err;
934 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
935 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
936 return err;
937 }
938 EXPORT_SYMBOL_GPL(kvm_rdpmc);
939
940 /*
941 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
942 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
943 *
944 * This list is modified at module load time to reflect the
945 * capabilities of the host cpu. This capabilities test skips MSRs that are
946 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
947 * may depend on host virtualization features rather than host cpu features.
948 */
949
950 static u32 msrs_to_save[] = {
951 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
952 MSR_STAR,
953 #ifdef CONFIG_X86_64
954 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
955 #endif
956 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
957 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
958 };
959
960 static unsigned num_msrs_to_save;
961
962 static u32 emulated_msrs[] = {
963 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
964 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
965 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
966 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
967 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
968 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
969 HV_X64_MSR_RESET,
970 HV_X64_MSR_VP_INDEX,
971 HV_X64_MSR_VP_RUNTIME,
972 HV_X64_MSR_SCONTROL,
973 HV_X64_MSR_STIMER0_CONFIG,
974 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
975 MSR_KVM_PV_EOI_EN,
976
977 MSR_IA32_TSC_ADJUST,
978 MSR_IA32_TSCDEADLINE,
979 MSR_IA32_MISC_ENABLE,
980 MSR_IA32_MCG_STATUS,
981 MSR_IA32_MCG_CTL,
982 MSR_IA32_SMBASE,
983 };
984
985 static unsigned num_emulated_msrs;
986
987 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
988 {
989 if (efer & efer_reserved_bits)
990 return false;
991
992 if (efer & EFER_FFXSR) {
993 struct kvm_cpuid_entry2 *feat;
994
995 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
996 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
997 return false;
998 }
999
1000 if (efer & EFER_SVME) {
1001 struct kvm_cpuid_entry2 *feat;
1002
1003 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1004 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1005 return false;
1006 }
1007
1008 return true;
1009 }
1010 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1011
1012 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1013 {
1014 u64 old_efer = vcpu->arch.efer;
1015
1016 if (!kvm_valid_efer(vcpu, efer))
1017 return 1;
1018
1019 if (is_paging(vcpu)
1020 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1021 return 1;
1022
1023 efer &= ~EFER_LMA;
1024 efer |= vcpu->arch.efer & EFER_LMA;
1025
1026 kvm_x86_ops->set_efer(vcpu, efer);
1027
1028 /* Update reserved bits */
1029 if ((efer ^ old_efer) & EFER_NX)
1030 kvm_mmu_reset_context(vcpu);
1031
1032 return 0;
1033 }
1034
1035 void kvm_enable_efer_bits(u64 mask)
1036 {
1037 efer_reserved_bits &= ~mask;
1038 }
1039 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1040
1041 /*
1042 * Writes msr value into into the appropriate "register".
1043 * Returns 0 on success, non-0 otherwise.
1044 * Assumes vcpu_load() was already called.
1045 */
1046 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1047 {
1048 switch (msr->index) {
1049 case MSR_FS_BASE:
1050 case MSR_GS_BASE:
1051 case MSR_KERNEL_GS_BASE:
1052 case MSR_CSTAR:
1053 case MSR_LSTAR:
1054 if (is_noncanonical_address(msr->data))
1055 return 1;
1056 break;
1057 case MSR_IA32_SYSENTER_EIP:
1058 case MSR_IA32_SYSENTER_ESP:
1059 /*
1060 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1061 * non-canonical address is written on Intel but not on
1062 * AMD (which ignores the top 32-bits, because it does
1063 * not implement 64-bit SYSENTER).
1064 *
1065 * 64-bit code should hence be able to write a non-canonical
1066 * value on AMD. Making the address canonical ensures that
1067 * vmentry does not fail on Intel after writing a non-canonical
1068 * value, and that something deterministic happens if the guest
1069 * invokes 64-bit SYSENTER.
1070 */
1071 msr->data = get_canonical(msr->data);
1072 }
1073 return kvm_x86_ops->set_msr(vcpu, msr);
1074 }
1075 EXPORT_SYMBOL_GPL(kvm_set_msr);
1076
1077 /*
1078 * Adapt set_msr() to msr_io()'s calling convention
1079 */
1080 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1081 {
1082 struct msr_data msr;
1083 int r;
1084
1085 msr.index = index;
1086 msr.host_initiated = true;
1087 r = kvm_get_msr(vcpu, &msr);
1088 if (r)
1089 return r;
1090
1091 *data = msr.data;
1092 return 0;
1093 }
1094
1095 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1096 {
1097 struct msr_data msr;
1098
1099 msr.data = *data;
1100 msr.index = index;
1101 msr.host_initiated = true;
1102 return kvm_set_msr(vcpu, &msr);
1103 }
1104
1105 #ifdef CONFIG_X86_64
1106 struct pvclock_gtod_data {
1107 seqcount_t seq;
1108
1109 struct { /* extract of a clocksource struct */
1110 int vclock_mode;
1111 cycle_t cycle_last;
1112 cycle_t mask;
1113 u32 mult;
1114 u32 shift;
1115 } clock;
1116
1117 u64 boot_ns;
1118 u64 nsec_base;
1119 };
1120
1121 static struct pvclock_gtod_data pvclock_gtod_data;
1122
1123 static void update_pvclock_gtod(struct timekeeper *tk)
1124 {
1125 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1126 u64 boot_ns;
1127
1128 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1129
1130 write_seqcount_begin(&vdata->seq);
1131
1132 /* copy pvclock gtod data */
1133 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1134 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1135 vdata->clock.mask = tk->tkr_mono.mask;
1136 vdata->clock.mult = tk->tkr_mono.mult;
1137 vdata->clock.shift = tk->tkr_mono.shift;
1138
1139 vdata->boot_ns = boot_ns;
1140 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1141
1142 write_seqcount_end(&vdata->seq);
1143 }
1144 #endif
1145
1146 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1147 {
1148 /*
1149 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1150 * vcpu_enter_guest. This function is only called from
1151 * the physical CPU that is running vcpu.
1152 */
1153 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1154 }
1155
1156 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1157 {
1158 int version;
1159 int r;
1160 struct pvclock_wall_clock wc;
1161 struct timespec boot;
1162
1163 if (!wall_clock)
1164 return;
1165
1166 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1167 if (r)
1168 return;
1169
1170 if (version & 1)
1171 ++version; /* first time write, random junk */
1172
1173 ++version;
1174
1175 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1176 return;
1177
1178 /*
1179 * The guest calculates current wall clock time by adding
1180 * system time (updated by kvm_guest_time_update below) to the
1181 * wall clock specified here. guest system time equals host
1182 * system time for us, thus we must fill in host boot time here.
1183 */
1184 getboottime(&boot);
1185
1186 if (kvm->arch.kvmclock_offset) {
1187 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1188 boot = timespec_sub(boot, ts);
1189 }
1190 wc.sec = boot.tv_sec;
1191 wc.nsec = boot.tv_nsec;
1192 wc.version = version;
1193
1194 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1195
1196 version++;
1197 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1198 }
1199
1200 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1201 {
1202 do_shl32_div32(dividend, divisor);
1203 return dividend;
1204 }
1205
1206 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1207 s8 *pshift, u32 *pmultiplier)
1208 {
1209 uint64_t scaled64;
1210 int32_t shift = 0;
1211 uint64_t tps64;
1212 uint32_t tps32;
1213
1214 tps64 = base_hz;
1215 scaled64 = scaled_hz;
1216 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1217 tps64 >>= 1;
1218 shift--;
1219 }
1220
1221 tps32 = (uint32_t)tps64;
1222 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1223 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1224 scaled64 >>= 1;
1225 else
1226 tps32 <<= 1;
1227 shift++;
1228 }
1229
1230 *pshift = shift;
1231 *pmultiplier = div_frac(scaled64, tps32);
1232
1233 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1234 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1235 }
1236
1237 #ifdef CONFIG_X86_64
1238 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1239 #endif
1240
1241 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1242 static unsigned long max_tsc_khz;
1243
1244 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1245 {
1246 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1247 vcpu->arch.virtual_tsc_shift);
1248 }
1249
1250 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1251 {
1252 u64 v = (u64)khz * (1000000 + ppm);
1253 do_div(v, 1000000);
1254 return v;
1255 }
1256
1257 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1258 {
1259 u64 ratio;
1260
1261 /* Guest TSC same frequency as host TSC? */
1262 if (!scale) {
1263 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1264 return 0;
1265 }
1266
1267 /* TSC scaling supported? */
1268 if (!kvm_has_tsc_control) {
1269 if (user_tsc_khz > tsc_khz) {
1270 vcpu->arch.tsc_catchup = 1;
1271 vcpu->arch.tsc_always_catchup = 1;
1272 return 0;
1273 } else {
1274 WARN(1, "user requested TSC rate below hardware speed\n");
1275 return -1;
1276 }
1277 }
1278
1279 /* TSC scaling required - calculate ratio */
1280 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1281 user_tsc_khz, tsc_khz);
1282
1283 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1284 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1285 user_tsc_khz);
1286 return -1;
1287 }
1288
1289 vcpu->arch.tsc_scaling_ratio = ratio;
1290 return 0;
1291 }
1292
1293 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1294 {
1295 u32 thresh_lo, thresh_hi;
1296 int use_scaling = 0;
1297
1298 /* tsc_khz can be zero if TSC calibration fails */
1299 if (user_tsc_khz == 0) {
1300 /* set tsc_scaling_ratio to a safe value */
1301 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1302 return -1;
1303 }
1304
1305 /* Compute a scale to convert nanoseconds in TSC cycles */
1306 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1307 &vcpu->arch.virtual_tsc_shift,
1308 &vcpu->arch.virtual_tsc_mult);
1309 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1310
1311 /*
1312 * Compute the variation in TSC rate which is acceptable
1313 * within the range of tolerance and decide if the
1314 * rate being applied is within that bounds of the hardware
1315 * rate. If so, no scaling or compensation need be done.
1316 */
1317 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1318 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1319 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1320 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1321 use_scaling = 1;
1322 }
1323 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1324 }
1325
1326 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1327 {
1328 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1329 vcpu->arch.virtual_tsc_mult,
1330 vcpu->arch.virtual_tsc_shift);
1331 tsc += vcpu->arch.this_tsc_write;
1332 return tsc;
1333 }
1334
1335 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1336 {
1337 #ifdef CONFIG_X86_64
1338 bool vcpus_matched;
1339 struct kvm_arch *ka = &vcpu->kvm->arch;
1340 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1341
1342 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1343 atomic_read(&vcpu->kvm->online_vcpus));
1344
1345 /*
1346 * Once the masterclock is enabled, always perform request in
1347 * order to update it.
1348 *
1349 * In order to enable masterclock, the host clocksource must be TSC
1350 * and the vcpus need to have matched TSCs. When that happens,
1351 * perform request to enable masterclock.
1352 */
1353 if (ka->use_master_clock ||
1354 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1355 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1356
1357 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1358 atomic_read(&vcpu->kvm->online_vcpus),
1359 ka->use_master_clock, gtod->clock.vclock_mode);
1360 #endif
1361 }
1362
1363 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1364 {
1365 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1366 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1367 }
1368
1369 /*
1370 * Multiply tsc by a fixed point number represented by ratio.
1371 *
1372 * The most significant 64-N bits (mult) of ratio represent the
1373 * integral part of the fixed point number; the remaining N bits
1374 * (frac) represent the fractional part, ie. ratio represents a fixed
1375 * point number (mult + frac * 2^(-N)).
1376 *
1377 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1378 */
1379 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1380 {
1381 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1382 }
1383
1384 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1385 {
1386 u64 _tsc = tsc;
1387 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1388
1389 if (ratio != kvm_default_tsc_scaling_ratio)
1390 _tsc = __scale_tsc(ratio, tsc);
1391
1392 return _tsc;
1393 }
1394 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1395
1396 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1397 {
1398 u64 tsc;
1399
1400 tsc = kvm_scale_tsc(vcpu, rdtsc());
1401
1402 return target_tsc - tsc;
1403 }
1404
1405 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1406 {
1407 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1408 }
1409 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1410
1411 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1412 {
1413 struct kvm *kvm = vcpu->kvm;
1414 u64 offset, ns, elapsed;
1415 unsigned long flags;
1416 s64 usdiff;
1417 bool matched;
1418 bool already_matched;
1419 u64 data = msr->data;
1420
1421 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1422 offset = kvm_compute_tsc_offset(vcpu, data);
1423 ns = get_kernel_ns();
1424 elapsed = ns - kvm->arch.last_tsc_nsec;
1425
1426 if (vcpu->arch.virtual_tsc_khz) {
1427 int faulted = 0;
1428
1429 /* n.b - signed multiplication and division required */
1430 usdiff = data - kvm->arch.last_tsc_write;
1431 #ifdef CONFIG_X86_64
1432 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1433 #else
1434 /* do_div() only does unsigned */
1435 asm("1: idivl %[divisor]\n"
1436 "2: xor %%edx, %%edx\n"
1437 " movl $0, %[faulted]\n"
1438 "3:\n"
1439 ".section .fixup,\"ax\"\n"
1440 "4: movl $1, %[faulted]\n"
1441 " jmp 3b\n"
1442 ".previous\n"
1443
1444 _ASM_EXTABLE(1b, 4b)
1445
1446 : "=A"(usdiff), [faulted] "=r" (faulted)
1447 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1448
1449 #endif
1450 do_div(elapsed, 1000);
1451 usdiff -= elapsed;
1452 if (usdiff < 0)
1453 usdiff = -usdiff;
1454
1455 /* idivl overflow => difference is larger than USEC_PER_SEC */
1456 if (faulted)
1457 usdiff = USEC_PER_SEC;
1458 } else
1459 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1460
1461 /*
1462 * Special case: TSC write with a small delta (1 second) of virtual
1463 * cycle time against real time is interpreted as an attempt to
1464 * synchronize the CPU.
1465 *
1466 * For a reliable TSC, we can match TSC offsets, and for an unstable
1467 * TSC, we add elapsed time in this computation. We could let the
1468 * compensation code attempt to catch up if we fall behind, but
1469 * it's better to try to match offsets from the beginning.
1470 */
1471 if (usdiff < USEC_PER_SEC &&
1472 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1473 if (!check_tsc_unstable()) {
1474 offset = kvm->arch.cur_tsc_offset;
1475 pr_debug("kvm: matched tsc offset for %llu\n", data);
1476 } else {
1477 u64 delta = nsec_to_cycles(vcpu, elapsed);
1478 data += delta;
1479 offset = kvm_compute_tsc_offset(vcpu, data);
1480 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1481 }
1482 matched = true;
1483 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1484 } else {
1485 /*
1486 * We split periods of matched TSC writes into generations.
1487 * For each generation, we track the original measured
1488 * nanosecond time, offset, and write, so if TSCs are in
1489 * sync, we can match exact offset, and if not, we can match
1490 * exact software computation in compute_guest_tsc()
1491 *
1492 * These values are tracked in kvm->arch.cur_xxx variables.
1493 */
1494 kvm->arch.cur_tsc_generation++;
1495 kvm->arch.cur_tsc_nsec = ns;
1496 kvm->arch.cur_tsc_write = data;
1497 kvm->arch.cur_tsc_offset = offset;
1498 matched = false;
1499 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1500 kvm->arch.cur_tsc_generation, data);
1501 }
1502
1503 /*
1504 * We also track th most recent recorded KHZ, write and time to
1505 * allow the matching interval to be extended at each write.
1506 */
1507 kvm->arch.last_tsc_nsec = ns;
1508 kvm->arch.last_tsc_write = data;
1509 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1510
1511 vcpu->arch.last_guest_tsc = data;
1512
1513 /* Keep track of which generation this VCPU has synchronized to */
1514 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1515 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1516 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1517
1518 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1519 update_ia32_tsc_adjust_msr(vcpu, offset);
1520 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1521 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1522
1523 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1524 if (!matched) {
1525 kvm->arch.nr_vcpus_matched_tsc = 0;
1526 } else if (!already_matched) {
1527 kvm->arch.nr_vcpus_matched_tsc++;
1528 }
1529
1530 kvm_track_tsc_matching(vcpu);
1531 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1532 }
1533
1534 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1535
1536 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1537 s64 adjustment)
1538 {
1539 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1540 }
1541
1542 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1543 {
1544 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1545 WARN_ON(adjustment < 0);
1546 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1547 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1548 }
1549
1550 #ifdef CONFIG_X86_64
1551
1552 static cycle_t read_tsc(void)
1553 {
1554 cycle_t ret = (cycle_t)rdtsc_ordered();
1555 u64 last = pvclock_gtod_data.clock.cycle_last;
1556
1557 if (likely(ret >= last))
1558 return ret;
1559
1560 /*
1561 * GCC likes to generate cmov here, but this branch is extremely
1562 * predictable (it's just a funciton of time and the likely is
1563 * very likely) and there's a data dependence, so force GCC
1564 * to generate a branch instead. I don't barrier() because
1565 * we don't actually need a barrier, and if this function
1566 * ever gets inlined it will generate worse code.
1567 */
1568 asm volatile ("");
1569 return last;
1570 }
1571
1572 static inline u64 vgettsc(cycle_t *cycle_now)
1573 {
1574 long v;
1575 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1576
1577 *cycle_now = read_tsc();
1578
1579 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1580 return v * gtod->clock.mult;
1581 }
1582
1583 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1584 {
1585 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1586 unsigned long seq;
1587 int mode;
1588 u64 ns;
1589
1590 do {
1591 seq = read_seqcount_begin(&gtod->seq);
1592 mode = gtod->clock.vclock_mode;
1593 ns = gtod->nsec_base;
1594 ns += vgettsc(cycle_now);
1595 ns >>= gtod->clock.shift;
1596 ns += gtod->boot_ns;
1597 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1598 *t = ns;
1599
1600 return mode;
1601 }
1602
1603 /* returns true if host is using tsc clocksource */
1604 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1605 {
1606 /* checked again under seqlock below */
1607 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1608 return false;
1609
1610 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1611 }
1612 #endif
1613
1614 /*
1615 *
1616 * Assuming a stable TSC across physical CPUS, and a stable TSC
1617 * across virtual CPUs, the following condition is possible.
1618 * Each numbered line represents an event visible to both
1619 * CPUs at the next numbered event.
1620 *
1621 * "timespecX" represents host monotonic time. "tscX" represents
1622 * RDTSC value.
1623 *
1624 * VCPU0 on CPU0 | VCPU1 on CPU1
1625 *
1626 * 1. read timespec0,tsc0
1627 * 2. | timespec1 = timespec0 + N
1628 * | tsc1 = tsc0 + M
1629 * 3. transition to guest | transition to guest
1630 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1631 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1632 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1633 *
1634 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1635 *
1636 * - ret0 < ret1
1637 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1638 * ...
1639 * - 0 < N - M => M < N
1640 *
1641 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1642 * always the case (the difference between two distinct xtime instances
1643 * might be smaller then the difference between corresponding TSC reads,
1644 * when updating guest vcpus pvclock areas).
1645 *
1646 * To avoid that problem, do not allow visibility of distinct
1647 * system_timestamp/tsc_timestamp values simultaneously: use a master
1648 * copy of host monotonic time values. Update that master copy
1649 * in lockstep.
1650 *
1651 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1652 *
1653 */
1654
1655 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1656 {
1657 #ifdef CONFIG_X86_64
1658 struct kvm_arch *ka = &kvm->arch;
1659 int vclock_mode;
1660 bool host_tsc_clocksource, vcpus_matched;
1661
1662 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1663 atomic_read(&kvm->online_vcpus));
1664
1665 /*
1666 * If the host uses TSC clock, then passthrough TSC as stable
1667 * to the guest.
1668 */
1669 host_tsc_clocksource = kvm_get_time_and_clockread(
1670 &ka->master_kernel_ns,
1671 &ka->master_cycle_now);
1672
1673 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1674 && !backwards_tsc_observed
1675 && !ka->boot_vcpu_runs_old_kvmclock;
1676
1677 if (ka->use_master_clock)
1678 atomic_set(&kvm_guest_has_master_clock, 1);
1679
1680 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1681 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1682 vcpus_matched);
1683 #endif
1684 }
1685
1686 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1687 {
1688 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1689 }
1690
1691 static void kvm_gen_update_masterclock(struct kvm *kvm)
1692 {
1693 #ifdef CONFIG_X86_64
1694 int i;
1695 struct kvm_vcpu *vcpu;
1696 struct kvm_arch *ka = &kvm->arch;
1697
1698 spin_lock(&ka->pvclock_gtod_sync_lock);
1699 kvm_make_mclock_inprogress_request(kvm);
1700 /* no guest entries from this point */
1701 pvclock_update_vm_gtod_copy(kvm);
1702
1703 kvm_for_each_vcpu(i, vcpu, kvm)
1704 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1705
1706 /* guest entries allowed */
1707 kvm_for_each_vcpu(i, vcpu, kvm)
1708 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1709
1710 spin_unlock(&ka->pvclock_gtod_sync_lock);
1711 #endif
1712 }
1713
1714 static int kvm_guest_time_update(struct kvm_vcpu *v)
1715 {
1716 unsigned long flags, tgt_tsc_khz;
1717 struct kvm_vcpu_arch *vcpu = &v->arch;
1718 struct kvm_arch *ka = &v->kvm->arch;
1719 s64 kernel_ns;
1720 u64 tsc_timestamp, host_tsc;
1721 struct pvclock_vcpu_time_info guest_hv_clock;
1722 u8 pvclock_flags;
1723 bool use_master_clock;
1724
1725 kernel_ns = 0;
1726 host_tsc = 0;
1727
1728 /*
1729 * If the host uses TSC clock, then passthrough TSC as stable
1730 * to the guest.
1731 */
1732 spin_lock(&ka->pvclock_gtod_sync_lock);
1733 use_master_clock = ka->use_master_clock;
1734 if (use_master_clock) {
1735 host_tsc = ka->master_cycle_now;
1736 kernel_ns = ka->master_kernel_ns;
1737 }
1738 spin_unlock(&ka->pvclock_gtod_sync_lock);
1739
1740 /* Keep irq disabled to prevent changes to the clock */
1741 local_irq_save(flags);
1742 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1743 if (unlikely(tgt_tsc_khz == 0)) {
1744 local_irq_restore(flags);
1745 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1746 return 1;
1747 }
1748 if (!use_master_clock) {
1749 host_tsc = rdtsc();
1750 kernel_ns = get_kernel_ns();
1751 }
1752
1753 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1754
1755 /*
1756 * We may have to catch up the TSC to match elapsed wall clock
1757 * time for two reasons, even if kvmclock is used.
1758 * 1) CPU could have been running below the maximum TSC rate
1759 * 2) Broken TSC compensation resets the base at each VCPU
1760 * entry to avoid unknown leaps of TSC even when running
1761 * again on the same CPU. This may cause apparent elapsed
1762 * time to disappear, and the guest to stand still or run
1763 * very slowly.
1764 */
1765 if (vcpu->tsc_catchup) {
1766 u64 tsc = compute_guest_tsc(v, kernel_ns);
1767 if (tsc > tsc_timestamp) {
1768 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1769 tsc_timestamp = tsc;
1770 }
1771 }
1772
1773 local_irq_restore(flags);
1774
1775 if (!vcpu->pv_time_enabled)
1776 return 0;
1777
1778 if (kvm_has_tsc_control)
1779 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1780
1781 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1782 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1783 &vcpu->hv_clock.tsc_shift,
1784 &vcpu->hv_clock.tsc_to_system_mul);
1785 vcpu->hw_tsc_khz = tgt_tsc_khz;
1786 }
1787
1788 /* With all the info we got, fill in the values */
1789 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1790 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1791 vcpu->last_guest_tsc = tsc_timestamp;
1792
1793 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1794 &guest_hv_clock, sizeof(guest_hv_clock))))
1795 return 0;
1796
1797 /* This VCPU is paused, but it's legal for a guest to read another
1798 * VCPU's kvmclock, so we really have to follow the specification where
1799 * it says that version is odd if data is being modified, and even after
1800 * it is consistent.
1801 *
1802 * Version field updates must be kept separate. This is because
1803 * kvm_write_guest_cached might use a "rep movs" instruction, and
1804 * writes within a string instruction are weakly ordered. So there
1805 * are three writes overall.
1806 *
1807 * As a small optimization, only write the version field in the first
1808 * and third write. The vcpu->pv_time cache is still valid, because the
1809 * version field is the first in the struct.
1810 */
1811 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1812
1813 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1814 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1815 &vcpu->hv_clock,
1816 sizeof(vcpu->hv_clock.version));
1817
1818 smp_wmb();
1819
1820 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1821 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1822
1823 if (vcpu->pvclock_set_guest_stopped_request) {
1824 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1825 vcpu->pvclock_set_guest_stopped_request = false;
1826 }
1827
1828 /* If the host uses TSC clocksource, then it is stable */
1829 if (use_master_clock)
1830 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1831
1832 vcpu->hv_clock.flags = pvclock_flags;
1833
1834 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1835
1836 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1837 &vcpu->hv_clock,
1838 sizeof(vcpu->hv_clock));
1839
1840 smp_wmb();
1841
1842 vcpu->hv_clock.version++;
1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1844 &vcpu->hv_clock,
1845 sizeof(vcpu->hv_clock.version));
1846 return 0;
1847 }
1848
1849 /*
1850 * kvmclock updates which are isolated to a given vcpu, such as
1851 * vcpu->cpu migration, should not allow system_timestamp from
1852 * the rest of the vcpus to remain static. Otherwise ntp frequency
1853 * correction applies to one vcpu's system_timestamp but not
1854 * the others.
1855 *
1856 * So in those cases, request a kvmclock update for all vcpus.
1857 * We need to rate-limit these requests though, as they can
1858 * considerably slow guests that have a large number of vcpus.
1859 * The time for a remote vcpu to update its kvmclock is bound
1860 * by the delay we use to rate-limit the updates.
1861 */
1862
1863 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1864
1865 static void kvmclock_update_fn(struct work_struct *work)
1866 {
1867 int i;
1868 struct delayed_work *dwork = to_delayed_work(work);
1869 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1870 kvmclock_update_work);
1871 struct kvm *kvm = container_of(ka, struct kvm, arch);
1872 struct kvm_vcpu *vcpu;
1873
1874 kvm_for_each_vcpu(i, vcpu, kvm) {
1875 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1876 kvm_vcpu_kick(vcpu);
1877 }
1878 }
1879
1880 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1881 {
1882 struct kvm *kvm = v->kvm;
1883
1884 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1885 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1886 KVMCLOCK_UPDATE_DELAY);
1887 }
1888
1889 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1890
1891 static void kvmclock_sync_fn(struct work_struct *work)
1892 {
1893 struct delayed_work *dwork = to_delayed_work(work);
1894 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1895 kvmclock_sync_work);
1896 struct kvm *kvm = container_of(ka, struct kvm, arch);
1897
1898 if (!kvmclock_periodic_sync)
1899 return;
1900
1901 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1902 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1903 KVMCLOCK_SYNC_PERIOD);
1904 }
1905
1906 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1907 {
1908 u64 mcg_cap = vcpu->arch.mcg_cap;
1909 unsigned bank_num = mcg_cap & 0xff;
1910
1911 switch (msr) {
1912 case MSR_IA32_MCG_STATUS:
1913 vcpu->arch.mcg_status = data;
1914 break;
1915 case MSR_IA32_MCG_CTL:
1916 if (!(mcg_cap & MCG_CTL_P))
1917 return 1;
1918 if (data != 0 && data != ~(u64)0)
1919 return -1;
1920 vcpu->arch.mcg_ctl = data;
1921 break;
1922 default:
1923 if (msr >= MSR_IA32_MC0_CTL &&
1924 msr < MSR_IA32_MCx_CTL(bank_num)) {
1925 u32 offset = msr - MSR_IA32_MC0_CTL;
1926 /* only 0 or all 1s can be written to IA32_MCi_CTL
1927 * some Linux kernels though clear bit 10 in bank 4 to
1928 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1929 * this to avoid an uncatched #GP in the guest
1930 */
1931 if ((offset & 0x3) == 0 &&
1932 data != 0 && (data | (1 << 10)) != ~(u64)0)
1933 return -1;
1934 vcpu->arch.mce_banks[offset] = data;
1935 break;
1936 }
1937 return 1;
1938 }
1939 return 0;
1940 }
1941
1942 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1943 {
1944 struct kvm *kvm = vcpu->kvm;
1945 int lm = is_long_mode(vcpu);
1946 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1947 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1948 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1949 : kvm->arch.xen_hvm_config.blob_size_32;
1950 u32 page_num = data & ~PAGE_MASK;
1951 u64 page_addr = data & PAGE_MASK;
1952 u8 *page;
1953 int r;
1954
1955 r = -E2BIG;
1956 if (page_num >= blob_size)
1957 goto out;
1958 r = -ENOMEM;
1959 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1960 if (IS_ERR(page)) {
1961 r = PTR_ERR(page);
1962 goto out;
1963 }
1964 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1965 goto out_free;
1966 r = 0;
1967 out_free:
1968 kfree(page);
1969 out:
1970 return r;
1971 }
1972
1973 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1974 {
1975 gpa_t gpa = data & ~0x3f;
1976
1977 /* Bits 2:5 are reserved, Should be zero */
1978 if (data & 0x3c)
1979 return 1;
1980
1981 vcpu->arch.apf.msr_val = data;
1982
1983 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1984 kvm_clear_async_pf_completion_queue(vcpu);
1985 kvm_async_pf_hash_reset(vcpu);
1986 return 0;
1987 }
1988
1989 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1990 sizeof(u32)))
1991 return 1;
1992
1993 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1994 kvm_async_pf_wakeup_all(vcpu);
1995 return 0;
1996 }
1997
1998 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1999 {
2000 vcpu->arch.pv_time_enabled = false;
2001 }
2002
2003 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2004 {
2005 u64 delta;
2006
2007 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2008 return;
2009
2010 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2011 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2012 vcpu->arch.st.accum_steal = delta;
2013 }
2014
2015 static void record_steal_time(struct kvm_vcpu *vcpu)
2016 {
2017 accumulate_steal_time(vcpu);
2018
2019 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2020 return;
2021
2022 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2023 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2024 return;
2025
2026 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2027 vcpu->arch.st.steal.version += 2;
2028 vcpu->arch.st.accum_steal = 0;
2029
2030 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2031 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2032 }
2033
2034 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2035 {
2036 bool pr = false;
2037 u32 msr = msr_info->index;
2038 u64 data = msr_info->data;
2039
2040 switch (msr) {
2041 case MSR_AMD64_NB_CFG:
2042 case MSR_IA32_UCODE_REV:
2043 case MSR_IA32_UCODE_WRITE:
2044 case MSR_VM_HSAVE_PA:
2045 case MSR_AMD64_PATCH_LOADER:
2046 case MSR_AMD64_BU_CFG2:
2047 break;
2048
2049 case MSR_EFER:
2050 return set_efer(vcpu, data);
2051 case MSR_K7_HWCR:
2052 data &= ~(u64)0x40; /* ignore flush filter disable */
2053 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2054 data &= ~(u64)0x8; /* ignore TLB cache disable */
2055 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2056 if (data != 0) {
2057 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2058 data);
2059 return 1;
2060 }
2061 break;
2062 case MSR_FAM10H_MMIO_CONF_BASE:
2063 if (data != 0) {
2064 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2065 "0x%llx\n", data);
2066 return 1;
2067 }
2068 break;
2069 case MSR_IA32_DEBUGCTLMSR:
2070 if (!data) {
2071 /* We support the non-activated case already */
2072 break;
2073 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2074 /* Values other than LBR and BTF are vendor-specific,
2075 thus reserved and should throw a #GP */
2076 return 1;
2077 }
2078 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2079 __func__, data);
2080 break;
2081 case 0x200 ... 0x2ff:
2082 return kvm_mtrr_set_msr(vcpu, msr, data);
2083 case MSR_IA32_APICBASE:
2084 return kvm_set_apic_base(vcpu, msr_info);
2085 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2086 return kvm_x2apic_msr_write(vcpu, msr, data);
2087 case MSR_IA32_TSCDEADLINE:
2088 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2089 break;
2090 case MSR_IA32_TSC_ADJUST:
2091 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2092 if (!msr_info->host_initiated) {
2093 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2094 adjust_tsc_offset_guest(vcpu, adj);
2095 }
2096 vcpu->arch.ia32_tsc_adjust_msr = data;
2097 }
2098 break;
2099 case MSR_IA32_MISC_ENABLE:
2100 vcpu->arch.ia32_misc_enable_msr = data;
2101 break;
2102 case MSR_IA32_SMBASE:
2103 if (!msr_info->host_initiated)
2104 return 1;
2105 vcpu->arch.smbase = data;
2106 break;
2107 case MSR_KVM_WALL_CLOCK_NEW:
2108 case MSR_KVM_WALL_CLOCK:
2109 vcpu->kvm->arch.wall_clock = data;
2110 kvm_write_wall_clock(vcpu->kvm, data);
2111 break;
2112 case MSR_KVM_SYSTEM_TIME_NEW:
2113 case MSR_KVM_SYSTEM_TIME: {
2114 u64 gpa_offset;
2115 struct kvm_arch *ka = &vcpu->kvm->arch;
2116
2117 kvmclock_reset(vcpu);
2118
2119 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2120 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2121
2122 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2123 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2124 &vcpu->requests);
2125
2126 ka->boot_vcpu_runs_old_kvmclock = tmp;
2127 }
2128
2129 vcpu->arch.time = data;
2130 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2131
2132 /* we verify if the enable bit is set... */
2133 if (!(data & 1))
2134 break;
2135
2136 gpa_offset = data & ~(PAGE_MASK | 1);
2137
2138 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2139 &vcpu->arch.pv_time, data & ~1ULL,
2140 sizeof(struct pvclock_vcpu_time_info)))
2141 vcpu->arch.pv_time_enabled = false;
2142 else
2143 vcpu->arch.pv_time_enabled = true;
2144
2145 break;
2146 }
2147 case MSR_KVM_ASYNC_PF_EN:
2148 if (kvm_pv_enable_async_pf(vcpu, data))
2149 return 1;
2150 break;
2151 case MSR_KVM_STEAL_TIME:
2152
2153 if (unlikely(!sched_info_on()))
2154 return 1;
2155
2156 if (data & KVM_STEAL_RESERVED_MASK)
2157 return 1;
2158
2159 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2160 data & KVM_STEAL_VALID_BITS,
2161 sizeof(struct kvm_steal_time)))
2162 return 1;
2163
2164 vcpu->arch.st.msr_val = data;
2165
2166 if (!(data & KVM_MSR_ENABLED))
2167 break;
2168
2169 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2170
2171 break;
2172 case MSR_KVM_PV_EOI_EN:
2173 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2174 return 1;
2175 break;
2176
2177 case MSR_IA32_MCG_CTL:
2178 case MSR_IA32_MCG_STATUS:
2179 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2180 return set_msr_mce(vcpu, msr, data);
2181
2182 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2183 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2184 pr = true; /* fall through */
2185 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2186 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2187 if (kvm_pmu_is_valid_msr(vcpu, msr))
2188 return kvm_pmu_set_msr(vcpu, msr_info);
2189
2190 if (pr || data != 0)
2191 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2192 "0x%x data 0x%llx\n", msr, data);
2193 break;
2194 case MSR_K7_CLK_CTL:
2195 /*
2196 * Ignore all writes to this no longer documented MSR.
2197 * Writes are only relevant for old K7 processors,
2198 * all pre-dating SVM, but a recommended workaround from
2199 * AMD for these chips. It is possible to specify the
2200 * affected processor models on the command line, hence
2201 * the need to ignore the workaround.
2202 */
2203 break;
2204 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2205 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2206 case HV_X64_MSR_CRASH_CTL:
2207 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2208 return kvm_hv_set_msr_common(vcpu, msr, data,
2209 msr_info->host_initiated);
2210 case MSR_IA32_BBL_CR_CTL3:
2211 /* Drop writes to this legacy MSR -- see rdmsr
2212 * counterpart for further detail.
2213 */
2214 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2215 break;
2216 case MSR_AMD64_OSVW_ID_LENGTH:
2217 if (!guest_cpuid_has_osvw(vcpu))
2218 return 1;
2219 vcpu->arch.osvw.length = data;
2220 break;
2221 case MSR_AMD64_OSVW_STATUS:
2222 if (!guest_cpuid_has_osvw(vcpu))
2223 return 1;
2224 vcpu->arch.osvw.status = data;
2225 break;
2226 default:
2227 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2228 return xen_hvm_config(vcpu, data);
2229 if (kvm_pmu_is_valid_msr(vcpu, msr))
2230 return kvm_pmu_set_msr(vcpu, msr_info);
2231 if (!ignore_msrs) {
2232 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2233 msr, data);
2234 return 1;
2235 } else {
2236 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2237 msr, data);
2238 break;
2239 }
2240 }
2241 return 0;
2242 }
2243 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2244
2245
2246 /*
2247 * Reads an msr value (of 'msr_index') into 'pdata'.
2248 * Returns 0 on success, non-0 otherwise.
2249 * Assumes vcpu_load() was already called.
2250 */
2251 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2252 {
2253 return kvm_x86_ops->get_msr(vcpu, msr);
2254 }
2255 EXPORT_SYMBOL_GPL(kvm_get_msr);
2256
2257 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2258 {
2259 u64 data;
2260 u64 mcg_cap = vcpu->arch.mcg_cap;
2261 unsigned bank_num = mcg_cap & 0xff;
2262
2263 switch (msr) {
2264 case MSR_IA32_P5_MC_ADDR:
2265 case MSR_IA32_P5_MC_TYPE:
2266 data = 0;
2267 break;
2268 case MSR_IA32_MCG_CAP:
2269 data = vcpu->arch.mcg_cap;
2270 break;
2271 case MSR_IA32_MCG_CTL:
2272 if (!(mcg_cap & MCG_CTL_P))
2273 return 1;
2274 data = vcpu->arch.mcg_ctl;
2275 break;
2276 case MSR_IA32_MCG_STATUS:
2277 data = vcpu->arch.mcg_status;
2278 break;
2279 default:
2280 if (msr >= MSR_IA32_MC0_CTL &&
2281 msr < MSR_IA32_MCx_CTL(bank_num)) {
2282 u32 offset = msr - MSR_IA32_MC0_CTL;
2283 data = vcpu->arch.mce_banks[offset];
2284 break;
2285 }
2286 return 1;
2287 }
2288 *pdata = data;
2289 return 0;
2290 }
2291
2292 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2293 {
2294 switch (msr_info->index) {
2295 case MSR_IA32_PLATFORM_ID:
2296 case MSR_IA32_EBL_CR_POWERON:
2297 case MSR_IA32_DEBUGCTLMSR:
2298 case MSR_IA32_LASTBRANCHFROMIP:
2299 case MSR_IA32_LASTBRANCHTOIP:
2300 case MSR_IA32_LASTINTFROMIP:
2301 case MSR_IA32_LASTINTTOIP:
2302 case MSR_K8_SYSCFG:
2303 case MSR_K8_TSEG_ADDR:
2304 case MSR_K8_TSEG_MASK:
2305 case MSR_K7_HWCR:
2306 case MSR_VM_HSAVE_PA:
2307 case MSR_K8_INT_PENDING_MSG:
2308 case MSR_AMD64_NB_CFG:
2309 case MSR_FAM10H_MMIO_CONF_BASE:
2310 case MSR_AMD64_BU_CFG2:
2311 msr_info->data = 0;
2312 break;
2313 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2314 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2315 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2316 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2317 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2318 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2319 msr_info->data = 0;
2320 break;
2321 case MSR_IA32_UCODE_REV:
2322 msr_info->data = 0x100000000ULL;
2323 break;
2324 case MSR_MTRRcap:
2325 case 0x200 ... 0x2ff:
2326 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2327 case 0xcd: /* fsb frequency */
2328 msr_info->data = 3;
2329 break;
2330 /*
2331 * MSR_EBC_FREQUENCY_ID
2332 * Conservative value valid for even the basic CPU models.
2333 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2334 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2335 * and 266MHz for model 3, or 4. Set Core Clock
2336 * Frequency to System Bus Frequency Ratio to 1 (bits
2337 * 31:24) even though these are only valid for CPU
2338 * models > 2, however guests may end up dividing or
2339 * multiplying by zero otherwise.
2340 */
2341 case MSR_EBC_FREQUENCY_ID:
2342 msr_info->data = 1 << 24;
2343 break;
2344 case MSR_IA32_APICBASE:
2345 msr_info->data = kvm_get_apic_base(vcpu);
2346 break;
2347 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2348 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2349 break;
2350 case MSR_IA32_TSCDEADLINE:
2351 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2352 break;
2353 case MSR_IA32_TSC_ADJUST:
2354 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2355 break;
2356 case MSR_IA32_MISC_ENABLE:
2357 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2358 break;
2359 case MSR_IA32_SMBASE:
2360 if (!msr_info->host_initiated)
2361 return 1;
2362 msr_info->data = vcpu->arch.smbase;
2363 break;
2364 case MSR_IA32_PERF_STATUS:
2365 /* TSC increment by tick */
2366 msr_info->data = 1000ULL;
2367 /* CPU multiplier */
2368 msr_info->data |= (((uint64_t)4ULL) << 40);
2369 break;
2370 case MSR_EFER:
2371 msr_info->data = vcpu->arch.efer;
2372 break;
2373 case MSR_KVM_WALL_CLOCK:
2374 case MSR_KVM_WALL_CLOCK_NEW:
2375 msr_info->data = vcpu->kvm->arch.wall_clock;
2376 break;
2377 case MSR_KVM_SYSTEM_TIME:
2378 case MSR_KVM_SYSTEM_TIME_NEW:
2379 msr_info->data = vcpu->arch.time;
2380 break;
2381 case MSR_KVM_ASYNC_PF_EN:
2382 msr_info->data = vcpu->arch.apf.msr_val;
2383 break;
2384 case MSR_KVM_STEAL_TIME:
2385 msr_info->data = vcpu->arch.st.msr_val;
2386 break;
2387 case MSR_KVM_PV_EOI_EN:
2388 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2389 break;
2390 case MSR_IA32_P5_MC_ADDR:
2391 case MSR_IA32_P5_MC_TYPE:
2392 case MSR_IA32_MCG_CAP:
2393 case MSR_IA32_MCG_CTL:
2394 case MSR_IA32_MCG_STATUS:
2395 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2396 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2397 case MSR_K7_CLK_CTL:
2398 /*
2399 * Provide expected ramp-up count for K7. All other
2400 * are set to zero, indicating minimum divisors for
2401 * every field.
2402 *
2403 * This prevents guest kernels on AMD host with CPU
2404 * type 6, model 8 and higher from exploding due to
2405 * the rdmsr failing.
2406 */
2407 msr_info->data = 0x20000000;
2408 break;
2409 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2410 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2411 case HV_X64_MSR_CRASH_CTL:
2412 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2413 return kvm_hv_get_msr_common(vcpu,
2414 msr_info->index, &msr_info->data);
2415 break;
2416 case MSR_IA32_BBL_CR_CTL3:
2417 /* This legacy MSR exists but isn't fully documented in current
2418 * silicon. It is however accessed by winxp in very narrow
2419 * scenarios where it sets bit #19, itself documented as
2420 * a "reserved" bit. Best effort attempt to source coherent
2421 * read data here should the balance of the register be
2422 * interpreted by the guest:
2423 *
2424 * L2 cache control register 3: 64GB range, 256KB size,
2425 * enabled, latency 0x1, configured
2426 */
2427 msr_info->data = 0xbe702111;
2428 break;
2429 case MSR_AMD64_OSVW_ID_LENGTH:
2430 if (!guest_cpuid_has_osvw(vcpu))
2431 return 1;
2432 msr_info->data = vcpu->arch.osvw.length;
2433 break;
2434 case MSR_AMD64_OSVW_STATUS:
2435 if (!guest_cpuid_has_osvw(vcpu))
2436 return 1;
2437 msr_info->data = vcpu->arch.osvw.status;
2438 break;
2439 default:
2440 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2441 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2442 if (!ignore_msrs) {
2443 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2444 return 1;
2445 } else {
2446 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2447 msr_info->data = 0;
2448 }
2449 break;
2450 }
2451 return 0;
2452 }
2453 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2454
2455 /*
2456 * Read or write a bunch of msrs. All parameters are kernel addresses.
2457 *
2458 * @return number of msrs set successfully.
2459 */
2460 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2461 struct kvm_msr_entry *entries,
2462 int (*do_msr)(struct kvm_vcpu *vcpu,
2463 unsigned index, u64 *data))
2464 {
2465 int i, idx;
2466
2467 idx = srcu_read_lock(&vcpu->kvm->srcu);
2468 for (i = 0; i < msrs->nmsrs; ++i)
2469 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2470 break;
2471 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2472
2473 return i;
2474 }
2475
2476 /*
2477 * Read or write a bunch of msrs. Parameters are user addresses.
2478 *
2479 * @return number of msrs set successfully.
2480 */
2481 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2482 int (*do_msr)(struct kvm_vcpu *vcpu,
2483 unsigned index, u64 *data),
2484 int writeback)
2485 {
2486 struct kvm_msrs msrs;
2487 struct kvm_msr_entry *entries;
2488 int r, n;
2489 unsigned size;
2490
2491 r = -EFAULT;
2492 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2493 goto out;
2494
2495 r = -E2BIG;
2496 if (msrs.nmsrs >= MAX_IO_MSRS)
2497 goto out;
2498
2499 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2500 entries = memdup_user(user_msrs->entries, size);
2501 if (IS_ERR(entries)) {
2502 r = PTR_ERR(entries);
2503 goto out;
2504 }
2505
2506 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2507 if (r < 0)
2508 goto out_free;
2509
2510 r = -EFAULT;
2511 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2512 goto out_free;
2513
2514 r = n;
2515
2516 out_free:
2517 kfree(entries);
2518 out:
2519 return r;
2520 }
2521
2522 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2523 {
2524 int r;
2525
2526 switch (ext) {
2527 case KVM_CAP_IRQCHIP:
2528 case KVM_CAP_HLT:
2529 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2530 case KVM_CAP_SET_TSS_ADDR:
2531 case KVM_CAP_EXT_CPUID:
2532 case KVM_CAP_EXT_EMUL_CPUID:
2533 case KVM_CAP_CLOCKSOURCE:
2534 case KVM_CAP_PIT:
2535 case KVM_CAP_NOP_IO_DELAY:
2536 case KVM_CAP_MP_STATE:
2537 case KVM_CAP_SYNC_MMU:
2538 case KVM_CAP_USER_NMI:
2539 case KVM_CAP_REINJECT_CONTROL:
2540 case KVM_CAP_IRQ_INJECT_STATUS:
2541 case KVM_CAP_IOEVENTFD:
2542 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2543 case KVM_CAP_PIT2:
2544 case KVM_CAP_PIT_STATE2:
2545 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2546 case KVM_CAP_XEN_HVM:
2547 case KVM_CAP_ADJUST_CLOCK:
2548 case KVM_CAP_VCPU_EVENTS:
2549 case KVM_CAP_HYPERV:
2550 case KVM_CAP_HYPERV_VAPIC:
2551 case KVM_CAP_HYPERV_SPIN:
2552 case KVM_CAP_HYPERV_SYNIC:
2553 case KVM_CAP_PCI_SEGMENT:
2554 case KVM_CAP_DEBUGREGS:
2555 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2556 case KVM_CAP_XSAVE:
2557 case KVM_CAP_ASYNC_PF:
2558 case KVM_CAP_GET_TSC_KHZ:
2559 case KVM_CAP_KVMCLOCK_CTRL:
2560 case KVM_CAP_READONLY_MEM:
2561 case KVM_CAP_HYPERV_TIME:
2562 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2563 case KVM_CAP_TSC_DEADLINE_TIMER:
2564 case KVM_CAP_ENABLE_CAP_VM:
2565 case KVM_CAP_DISABLE_QUIRKS:
2566 case KVM_CAP_SET_BOOT_CPU_ID:
2567 case KVM_CAP_SPLIT_IRQCHIP:
2568 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2569 case KVM_CAP_ASSIGN_DEV_IRQ:
2570 case KVM_CAP_PCI_2_3:
2571 #endif
2572 r = 1;
2573 break;
2574 case KVM_CAP_X86_SMM:
2575 /* SMBASE is usually relocated above 1M on modern chipsets,
2576 * and SMM handlers might indeed rely on 4G segment limits,
2577 * so do not report SMM to be available if real mode is
2578 * emulated via vm86 mode. Still, do not go to great lengths
2579 * to avoid userspace's usage of the feature, because it is a
2580 * fringe case that is not enabled except via specific settings
2581 * of the module parameters.
2582 */
2583 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2584 break;
2585 case KVM_CAP_COALESCED_MMIO:
2586 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2587 break;
2588 case KVM_CAP_VAPIC:
2589 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2590 break;
2591 case KVM_CAP_NR_VCPUS:
2592 r = KVM_SOFT_MAX_VCPUS;
2593 break;
2594 case KVM_CAP_MAX_VCPUS:
2595 r = KVM_MAX_VCPUS;
2596 break;
2597 case KVM_CAP_NR_MEMSLOTS:
2598 r = KVM_USER_MEM_SLOTS;
2599 break;
2600 case KVM_CAP_PV_MMU: /* obsolete */
2601 r = 0;
2602 break;
2603 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2604 case KVM_CAP_IOMMU:
2605 r = iommu_present(&pci_bus_type);
2606 break;
2607 #endif
2608 case KVM_CAP_MCE:
2609 r = KVM_MAX_MCE_BANKS;
2610 break;
2611 case KVM_CAP_XCRS:
2612 r = cpu_has_xsave;
2613 break;
2614 case KVM_CAP_TSC_CONTROL:
2615 r = kvm_has_tsc_control;
2616 break;
2617 default:
2618 r = 0;
2619 break;
2620 }
2621 return r;
2622
2623 }
2624
2625 long kvm_arch_dev_ioctl(struct file *filp,
2626 unsigned int ioctl, unsigned long arg)
2627 {
2628 void __user *argp = (void __user *)arg;
2629 long r;
2630
2631 switch (ioctl) {
2632 case KVM_GET_MSR_INDEX_LIST: {
2633 struct kvm_msr_list __user *user_msr_list = argp;
2634 struct kvm_msr_list msr_list;
2635 unsigned n;
2636
2637 r = -EFAULT;
2638 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2639 goto out;
2640 n = msr_list.nmsrs;
2641 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2642 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2643 goto out;
2644 r = -E2BIG;
2645 if (n < msr_list.nmsrs)
2646 goto out;
2647 r = -EFAULT;
2648 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2649 num_msrs_to_save * sizeof(u32)))
2650 goto out;
2651 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2652 &emulated_msrs,
2653 num_emulated_msrs * sizeof(u32)))
2654 goto out;
2655 r = 0;
2656 break;
2657 }
2658 case KVM_GET_SUPPORTED_CPUID:
2659 case KVM_GET_EMULATED_CPUID: {
2660 struct kvm_cpuid2 __user *cpuid_arg = argp;
2661 struct kvm_cpuid2 cpuid;
2662
2663 r = -EFAULT;
2664 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2665 goto out;
2666
2667 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2668 ioctl);
2669 if (r)
2670 goto out;
2671
2672 r = -EFAULT;
2673 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2674 goto out;
2675 r = 0;
2676 break;
2677 }
2678 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2679 u64 mce_cap;
2680
2681 mce_cap = KVM_MCE_CAP_SUPPORTED;
2682 r = -EFAULT;
2683 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2684 goto out;
2685 r = 0;
2686 break;
2687 }
2688 default:
2689 r = -EINVAL;
2690 }
2691 out:
2692 return r;
2693 }
2694
2695 static void wbinvd_ipi(void *garbage)
2696 {
2697 wbinvd();
2698 }
2699
2700 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2701 {
2702 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2703 }
2704
2705 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2706 {
2707 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2708 }
2709
2710 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2711 {
2712 /* Address WBINVD may be executed by guest */
2713 if (need_emulate_wbinvd(vcpu)) {
2714 if (kvm_x86_ops->has_wbinvd_exit())
2715 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2716 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2717 smp_call_function_single(vcpu->cpu,
2718 wbinvd_ipi, NULL, 1);
2719 }
2720
2721 kvm_x86_ops->vcpu_load(vcpu, cpu);
2722
2723 /* Apply any externally detected TSC adjustments (due to suspend) */
2724 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2725 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2726 vcpu->arch.tsc_offset_adjustment = 0;
2727 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2728 }
2729
2730 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2731 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2732 rdtsc() - vcpu->arch.last_host_tsc;
2733 if (tsc_delta < 0)
2734 mark_tsc_unstable("KVM discovered backwards TSC");
2735 if (check_tsc_unstable()) {
2736 u64 offset = kvm_compute_tsc_offset(vcpu,
2737 vcpu->arch.last_guest_tsc);
2738 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2739 vcpu->arch.tsc_catchup = 1;
2740 }
2741 /*
2742 * On a host with synchronized TSC, there is no need to update
2743 * kvmclock on vcpu->cpu migration
2744 */
2745 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2746 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2747 if (vcpu->cpu != cpu)
2748 kvm_migrate_timers(vcpu);
2749 vcpu->cpu = cpu;
2750 }
2751
2752 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2753 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
2754 }
2755
2756 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2757 {
2758 kvm_x86_ops->vcpu_put(vcpu);
2759 kvm_put_guest_fpu(vcpu);
2760 vcpu->arch.last_host_tsc = rdtsc();
2761 }
2762
2763 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2764 struct kvm_lapic_state *s)
2765 {
2766 if (vcpu->arch.apicv_active)
2767 kvm_x86_ops->sync_pir_to_irr(vcpu);
2768
2769 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2770
2771 return 0;
2772 }
2773
2774 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2775 struct kvm_lapic_state *s)
2776 {
2777 kvm_apic_post_state_restore(vcpu, s);
2778 update_cr8_intercept(vcpu);
2779
2780 return 0;
2781 }
2782
2783 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2784 {
2785 return (!lapic_in_kernel(vcpu) ||
2786 kvm_apic_accept_pic_intr(vcpu));
2787 }
2788
2789 /*
2790 * if userspace requested an interrupt window, check that the
2791 * interrupt window is open.
2792 *
2793 * No need to exit to userspace if we already have an interrupt queued.
2794 */
2795 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2796 {
2797 return kvm_arch_interrupt_allowed(vcpu) &&
2798 !kvm_cpu_has_interrupt(vcpu) &&
2799 !kvm_event_needs_reinjection(vcpu) &&
2800 kvm_cpu_accept_dm_intr(vcpu);
2801 }
2802
2803 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2804 struct kvm_interrupt *irq)
2805 {
2806 if (irq->irq >= KVM_NR_INTERRUPTS)
2807 return -EINVAL;
2808
2809 if (!irqchip_in_kernel(vcpu->kvm)) {
2810 kvm_queue_interrupt(vcpu, irq->irq, false);
2811 kvm_make_request(KVM_REQ_EVENT, vcpu);
2812 return 0;
2813 }
2814
2815 /*
2816 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2817 * fail for in-kernel 8259.
2818 */
2819 if (pic_in_kernel(vcpu->kvm))
2820 return -ENXIO;
2821
2822 if (vcpu->arch.pending_external_vector != -1)
2823 return -EEXIST;
2824
2825 vcpu->arch.pending_external_vector = irq->irq;
2826 kvm_make_request(KVM_REQ_EVENT, vcpu);
2827 return 0;
2828 }
2829
2830 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2831 {
2832 kvm_inject_nmi(vcpu);
2833
2834 return 0;
2835 }
2836
2837 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2838 {
2839 kvm_make_request(KVM_REQ_SMI, vcpu);
2840
2841 return 0;
2842 }
2843
2844 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2845 struct kvm_tpr_access_ctl *tac)
2846 {
2847 if (tac->flags)
2848 return -EINVAL;
2849 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2850 return 0;
2851 }
2852
2853 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2854 u64 mcg_cap)
2855 {
2856 int r;
2857 unsigned bank_num = mcg_cap & 0xff, bank;
2858
2859 r = -EINVAL;
2860 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2861 goto out;
2862 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2863 goto out;
2864 r = 0;
2865 vcpu->arch.mcg_cap = mcg_cap;
2866 /* Init IA32_MCG_CTL to all 1s */
2867 if (mcg_cap & MCG_CTL_P)
2868 vcpu->arch.mcg_ctl = ~(u64)0;
2869 /* Init IA32_MCi_CTL to all 1s */
2870 for (bank = 0; bank < bank_num; bank++)
2871 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2872 out:
2873 return r;
2874 }
2875
2876 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2877 struct kvm_x86_mce *mce)
2878 {
2879 u64 mcg_cap = vcpu->arch.mcg_cap;
2880 unsigned bank_num = mcg_cap & 0xff;
2881 u64 *banks = vcpu->arch.mce_banks;
2882
2883 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2884 return -EINVAL;
2885 /*
2886 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2887 * reporting is disabled
2888 */
2889 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2890 vcpu->arch.mcg_ctl != ~(u64)0)
2891 return 0;
2892 banks += 4 * mce->bank;
2893 /*
2894 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2895 * reporting is disabled for the bank
2896 */
2897 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2898 return 0;
2899 if (mce->status & MCI_STATUS_UC) {
2900 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2901 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2902 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2903 return 0;
2904 }
2905 if (banks[1] & MCI_STATUS_VAL)
2906 mce->status |= MCI_STATUS_OVER;
2907 banks[2] = mce->addr;
2908 banks[3] = mce->misc;
2909 vcpu->arch.mcg_status = mce->mcg_status;
2910 banks[1] = mce->status;
2911 kvm_queue_exception(vcpu, MC_VECTOR);
2912 } else if (!(banks[1] & MCI_STATUS_VAL)
2913 || !(banks[1] & MCI_STATUS_UC)) {
2914 if (banks[1] & MCI_STATUS_VAL)
2915 mce->status |= MCI_STATUS_OVER;
2916 banks[2] = mce->addr;
2917 banks[3] = mce->misc;
2918 banks[1] = mce->status;
2919 } else
2920 banks[1] |= MCI_STATUS_OVER;
2921 return 0;
2922 }
2923
2924 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2925 struct kvm_vcpu_events *events)
2926 {
2927 process_nmi(vcpu);
2928 events->exception.injected =
2929 vcpu->arch.exception.pending &&
2930 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2931 events->exception.nr = vcpu->arch.exception.nr;
2932 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2933 events->exception.pad = 0;
2934 events->exception.error_code = vcpu->arch.exception.error_code;
2935
2936 events->interrupt.injected =
2937 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2938 events->interrupt.nr = vcpu->arch.interrupt.nr;
2939 events->interrupt.soft = 0;
2940 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2941
2942 events->nmi.injected = vcpu->arch.nmi_injected;
2943 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2944 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2945 events->nmi.pad = 0;
2946
2947 events->sipi_vector = 0; /* never valid when reporting to user space */
2948
2949 events->smi.smm = is_smm(vcpu);
2950 events->smi.pending = vcpu->arch.smi_pending;
2951 events->smi.smm_inside_nmi =
2952 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2953 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2954
2955 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2956 | KVM_VCPUEVENT_VALID_SHADOW
2957 | KVM_VCPUEVENT_VALID_SMM);
2958 memset(&events->reserved, 0, sizeof(events->reserved));
2959 }
2960
2961 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2962 struct kvm_vcpu_events *events)
2963 {
2964 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2965 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2966 | KVM_VCPUEVENT_VALID_SHADOW
2967 | KVM_VCPUEVENT_VALID_SMM))
2968 return -EINVAL;
2969
2970 process_nmi(vcpu);
2971 vcpu->arch.exception.pending = events->exception.injected;
2972 vcpu->arch.exception.nr = events->exception.nr;
2973 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2974 vcpu->arch.exception.error_code = events->exception.error_code;
2975
2976 vcpu->arch.interrupt.pending = events->interrupt.injected;
2977 vcpu->arch.interrupt.nr = events->interrupt.nr;
2978 vcpu->arch.interrupt.soft = events->interrupt.soft;
2979 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2980 kvm_x86_ops->set_interrupt_shadow(vcpu,
2981 events->interrupt.shadow);
2982
2983 vcpu->arch.nmi_injected = events->nmi.injected;
2984 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2985 vcpu->arch.nmi_pending = events->nmi.pending;
2986 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2987
2988 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2989 lapic_in_kernel(vcpu))
2990 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2991
2992 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2993 if (events->smi.smm)
2994 vcpu->arch.hflags |= HF_SMM_MASK;
2995 else
2996 vcpu->arch.hflags &= ~HF_SMM_MASK;
2997 vcpu->arch.smi_pending = events->smi.pending;
2998 if (events->smi.smm_inside_nmi)
2999 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3000 else
3001 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3002 if (lapic_in_kernel(vcpu)) {
3003 if (events->smi.latched_init)
3004 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3005 else
3006 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3007 }
3008 }
3009
3010 kvm_make_request(KVM_REQ_EVENT, vcpu);
3011
3012 return 0;
3013 }
3014
3015 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3016 struct kvm_debugregs *dbgregs)
3017 {
3018 unsigned long val;
3019
3020 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3021 kvm_get_dr(vcpu, 6, &val);
3022 dbgregs->dr6 = val;
3023 dbgregs->dr7 = vcpu->arch.dr7;
3024 dbgregs->flags = 0;
3025 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3026 }
3027
3028 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3029 struct kvm_debugregs *dbgregs)
3030 {
3031 if (dbgregs->flags)
3032 return -EINVAL;
3033
3034 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3035 kvm_update_dr0123(vcpu);
3036 vcpu->arch.dr6 = dbgregs->dr6;
3037 kvm_update_dr6(vcpu);
3038 vcpu->arch.dr7 = dbgregs->dr7;
3039 kvm_update_dr7(vcpu);
3040
3041 return 0;
3042 }
3043
3044 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3045
3046 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3047 {
3048 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3049 u64 xstate_bv = xsave->header.xfeatures;
3050 u64 valid;
3051
3052 /*
3053 * Copy legacy XSAVE area, to avoid complications with CPUID
3054 * leaves 0 and 1 in the loop below.
3055 */
3056 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3057
3058 /* Set XSTATE_BV */
3059 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3060
3061 /*
3062 * Copy each region from the possibly compacted offset to the
3063 * non-compacted offset.
3064 */
3065 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3066 while (valid) {
3067 u64 feature = valid & -valid;
3068 int index = fls64(feature) - 1;
3069 void *src = get_xsave_addr(xsave, feature);
3070
3071 if (src) {
3072 u32 size, offset, ecx, edx;
3073 cpuid_count(XSTATE_CPUID, index,
3074 &size, &offset, &ecx, &edx);
3075 memcpy(dest + offset, src, size);
3076 }
3077
3078 valid -= feature;
3079 }
3080 }
3081
3082 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3083 {
3084 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3085 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3086 u64 valid;
3087
3088 /*
3089 * Copy legacy XSAVE area, to avoid complications with CPUID
3090 * leaves 0 and 1 in the loop below.
3091 */
3092 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3093
3094 /* Set XSTATE_BV and possibly XCOMP_BV. */
3095 xsave->header.xfeatures = xstate_bv;
3096 if (cpu_has_xsaves)
3097 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3098
3099 /*
3100 * Copy each region from the non-compacted offset to the
3101 * possibly compacted offset.
3102 */
3103 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3104 while (valid) {
3105 u64 feature = valid & -valid;
3106 int index = fls64(feature) - 1;
3107 void *dest = get_xsave_addr(xsave, feature);
3108
3109 if (dest) {
3110 u32 size, offset, ecx, edx;
3111 cpuid_count(XSTATE_CPUID, index,
3112 &size, &offset, &ecx, &edx);
3113 memcpy(dest, src + offset, size);
3114 }
3115
3116 valid -= feature;
3117 }
3118 }
3119
3120 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3121 struct kvm_xsave *guest_xsave)
3122 {
3123 if (cpu_has_xsave) {
3124 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3125 fill_xsave((u8 *) guest_xsave->region, vcpu);
3126 } else {
3127 memcpy(guest_xsave->region,
3128 &vcpu->arch.guest_fpu.state.fxsave,
3129 sizeof(struct fxregs_state));
3130 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3131 XFEATURE_MASK_FPSSE;
3132 }
3133 }
3134
3135 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3136 struct kvm_xsave *guest_xsave)
3137 {
3138 u64 xstate_bv =
3139 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3140
3141 if (cpu_has_xsave) {
3142 /*
3143 * Here we allow setting states that are not present in
3144 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3145 * with old userspace.
3146 */
3147 if (xstate_bv & ~kvm_supported_xcr0())
3148 return -EINVAL;
3149 load_xsave(vcpu, (u8 *)guest_xsave->region);
3150 } else {
3151 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3152 return -EINVAL;
3153 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3154 guest_xsave->region, sizeof(struct fxregs_state));
3155 }
3156 return 0;
3157 }
3158
3159 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3160 struct kvm_xcrs *guest_xcrs)
3161 {
3162 if (!cpu_has_xsave) {
3163 guest_xcrs->nr_xcrs = 0;
3164 return;
3165 }
3166
3167 guest_xcrs->nr_xcrs = 1;
3168 guest_xcrs->flags = 0;
3169 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3170 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3171 }
3172
3173 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3174 struct kvm_xcrs *guest_xcrs)
3175 {
3176 int i, r = 0;
3177
3178 if (!cpu_has_xsave)
3179 return -EINVAL;
3180
3181 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3182 return -EINVAL;
3183
3184 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3185 /* Only support XCR0 currently */
3186 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3187 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3188 guest_xcrs->xcrs[i].value);
3189 break;
3190 }
3191 if (r)
3192 r = -EINVAL;
3193 return r;
3194 }
3195
3196 /*
3197 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3198 * stopped by the hypervisor. This function will be called from the host only.
3199 * EINVAL is returned when the host attempts to set the flag for a guest that
3200 * does not support pv clocks.
3201 */
3202 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3203 {
3204 if (!vcpu->arch.pv_time_enabled)
3205 return -EINVAL;
3206 vcpu->arch.pvclock_set_guest_stopped_request = true;
3207 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3208 return 0;
3209 }
3210
3211 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3212 struct kvm_enable_cap *cap)
3213 {
3214 if (cap->flags)
3215 return -EINVAL;
3216
3217 switch (cap->cap) {
3218 case KVM_CAP_HYPERV_SYNIC:
3219 return kvm_hv_activate_synic(vcpu);
3220 default:
3221 return -EINVAL;
3222 }
3223 }
3224
3225 long kvm_arch_vcpu_ioctl(struct file *filp,
3226 unsigned int ioctl, unsigned long arg)
3227 {
3228 struct kvm_vcpu *vcpu = filp->private_data;
3229 void __user *argp = (void __user *)arg;
3230 int r;
3231 union {
3232 struct kvm_lapic_state *lapic;
3233 struct kvm_xsave *xsave;
3234 struct kvm_xcrs *xcrs;
3235 void *buffer;
3236 } u;
3237
3238 u.buffer = NULL;
3239 switch (ioctl) {
3240 case KVM_GET_LAPIC: {
3241 r = -EINVAL;
3242 if (!lapic_in_kernel(vcpu))
3243 goto out;
3244 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3245
3246 r = -ENOMEM;
3247 if (!u.lapic)
3248 goto out;
3249 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3250 if (r)
3251 goto out;
3252 r = -EFAULT;
3253 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3254 goto out;
3255 r = 0;
3256 break;
3257 }
3258 case KVM_SET_LAPIC: {
3259 r = -EINVAL;
3260 if (!lapic_in_kernel(vcpu))
3261 goto out;
3262 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3263 if (IS_ERR(u.lapic))
3264 return PTR_ERR(u.lapic);
3265
3266 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3267 break;
3268 }
3269 case KVM_INTERRUPT: {
3270 struct kvm_interrupt irq;
3271
3272 r = -EFAULT;
3273 if (copy_from_user(&irq, argp, sizeof irq))
3274 goto out;
3275 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3276 break;
3277 }
3278 case KVM_NMI: {
3279 r = kvm_vcpu_ioctl_nmi(vcpu);
3280 break;
3281 }
3282 case KVM_SMI: {
3283 r = kvm_vcpu_ioctl_smi(vcpu);
3284 break;
3285 }
3286 case KVM_SET_CPUID: {
3287 struct kvm_cpuid __user *cpuid_arg = argp;
3288 struct kvm_cpuid cpuid;
3289
3290 r = -EFAULT;
3291 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3292 goto out;
3293 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3294 break;
3295 }
3296 case KVM_SET_CPUID2: {
3297 struct kvm_cpuid2 __user *cpuid_arg = argp;
3298 struct kvm_cpuid2 cpuid;
3299
3300 r = -EFAULT;
3301 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3302 goto out;
3303 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3304 cpuid_arg->entries);
3305 break;
3306 }
3307 case KVM_GET_CPUID2: {
3308 struct kvm_cpuid2 __user *cpuid_arg = argp;
3309 struct kvm_cpuid2 cpuid;
3310
3311 r = -EFAULT;
3312 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3313 goto out;
3314 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3315 cpuid_arg->entries);
3316 if (r)
3317 goto out;
3318 r = -EFAULT;
3319 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3320 goto out;
3321 r = 0;
3322 break;
3323 }
3324 case KVM_GET_MSRS:
3325 r = msr_io(vcpu, argp, do_get_msr, 1);
3326 break;
3327 case KVM_SET_MSRS:
3328 r = msr_io(vcpu, argp, do_set_msr, 0);
3329 break;
3330 case KVM_TPR_ACCESS_REPORTING: {
3331 struct kvm_tpr_access_ctl tac;
3332
3333 r = -EFAULT;
3334 if (copy_from_user(&tac, argp, sizeof tac))
3335 goto out;
3336 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3337 if (r)
3338 goto out;
3339 r = -EFAULT;
3340 if (copy_to_user(argp, &tac, sizeof tac))
3341 goto out;
3342 r = 0;
3343 break;
3344 };
3345 case KVM_SET_VAPIC_ADDR: {
3346 struct kvm_vapic_addr va;
3347
3348 r = -EINVAL;
3349 if (!lapic_in_kernel(vcpu))
3350 goto out;
3351 r = -EFAULT;
3352 if (copy_from_user(&va, argp, sizeof va))
3353 goto out;
3354 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3355 break;
3356 }
3357 case KVM_X86_SETUP_MCE: {
3358 u64 mcg_cap;
3359
3360 r = -EFAULT;
3361 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3362 goto out;
3363 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3364 break;
3365 }
3366 case KVM_X86_SET_MCE: {
3367 struct kvm_x86_mce mce;
3368
3369 r = -EFAULT;
3370 if (copy_from_user(&mce, argp, sizeof mce))
3371 goto out;
3372 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3373 break;
3374 }
3375 case KVM_GET_VCPU_EVENTS: {
3376 struct kvm_vcpu_events events;
3377
3378 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3379
3380 r = -EFAULT;
3381 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3382 break;
3383 r = 0;
3384 break;
3385 }
3386 case KVM_SET_VCPU_EVENTS: {
3387 struct kvm_vcpu_events events;
3388
3389 r = -EFAULT;
3390 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3391 break;
3392
3393 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3394 break;
3395 }
3396 case KVM_GET_DEBUGREGS: {
3397 struct kvm_debugregs dbgregs;
3398
3399 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3400
3401 r = -EFAULT;
3402 if (copy_to_user(argp, &dbgregs,
3403 sizeof(struct kvm_debugregs)))
3404 break;
3405 r = 0;
3406 break;
3407 }
3408 case KVM_SET_DEBUGREGS: {
3409 struct kvm_debugregs dbgregs;
3410
3411 r = -EFAULT;
3412 if (copy_from_user(&dbgregs, argp,
3413 sizeof(struct kvm_debugregs)))
3414 break;
3415
3416 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3417 break;
3418 }
3419 case KVM_GET_XSAVE: {
3420 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3421 r = -ENOMEM;
3422 if (!u.xsave)
3423 break;
3424
3425 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3426
3427 r = -EFAULT;
3428 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3429 break;
3430 r = 0;
3431 break;
3432 }
3433 case KVM_SET_XSAVE: {
3434 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3435 if (IS_ERR(u.xsave))
3436 return PTR_ERR(u.xsave);
3437
3438 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3439 break;
3440 }
3441 case KVM_GET_XCRS: {
3442 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3443 r = -ENOMEM;
3444 if (!u.xcrs)
3445 break;
3446
3447 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3448
3449 r = -EFAULT;
3450 if (copy_to_user(argp, u.xcrs,
3451 sizeof(struct kvm_xcrs)))
3452 break;
3453 r = 0;
3454 break;
3455 }
3456 case KVM_SET_XCRS: {
3457 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3458 if (IS_ERR(u.xcrs))
3459 return PTR_ERR(u.xcrs);
3460
3461 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3462 break;
3463 }
3464 case KVM_SET_TSC_KHZ: {
3465 u32 user_tsc_khz;
3466
3467 r = -EINVAL;
3468 user_tsc_khz = (u32)arg;
3469
3470 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3471 goto out;
3472
3473 if (user_tsc_khz == 0)
3474 user_tsc_khz = tsc_khz;
3475
3476 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3477 r = 0;
3478
3479 goto out;
3480 }
3481 case KVM_GET_TSC_KHZ: {
3482 r = vcpu->arch.virtual_tsc_khz;
3483 goto out;
3484 }
3485 case KVM_KVMCLOCK_CTRL: {
3486 r = kvm_set_guest_paused(vcpu);
3487 goto out;
3488 }
3489 case KVM_ENABLE_CAP: {
3490 struct kvm_enable_cap cap;
3491
3492 r = -EFAULT;
3493 if (copy_from_user(&cap, argp, sizeof(cap)))
3494 goto out;
3495 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3496 break;
3497 }
3498 default:
3499 r = -EINVAL;
3500 }
3501 out:
3502 kfree(u.buffer);
3503 return r;
3504 }
3505
3506 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3507 {
3508 return VM_FAULT_SIGBUS;
3509 }
3510
3511 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3512 {
3513 int ret;
3514
3515 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3516 return -EINVAL;
3517 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3518 return ret;
3519 }
3520
3521 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3522 u64 ident_addr)
3523 {
3524 kvm->arch.ept_identity_map_addr = ident_addr;
3525 return 0;
3526 }
3527
3528 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3529 u32 kvm_nr_mmu_pages)
3530 {
3531 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3532 return -EINVAL;
3533
3534 mutex_lock(&kvm->slots_lock);
3535
3536 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3537 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3538
3539 mutex_unlock(&kvm->slots_lock);
3540 return 0;
3541 }
3542
3543 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3544 {
3545 return kvm->arch.n_max_mmu_pages;
3546 }
3547
3548 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3549 {
3550 int r;
3551
3552 r = 0;
3553 switch (chip->chip_id) {
3554 case KVM_IRQCHIP_PIC_MASTER:
3555 memcpy(&chip->chip.pic,
3556 &pic_irqchip(kvm)->pics[0],
3557 sizeof(struct kvm_pic_state));
3558 break;
3559 case KVM_IRQCHIP_PIC_SLAVE:
3560 memcpy(&chip->chip.pic,
3561 &pic_irqchip(kvm)->pics[1],
3562 sizeof(struct kvm_pic_state));
3563 break;
3564 case KVM_IRQCHIP_IOAPIC:
3565 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3566 break;
3567 default:
3568 r = -EINVAL;
3569 break;
3570 }
3571 return r;
3572 }
3573
3574 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3575 {
3576 int r;
3577
3578 r = 0;
3579 switch (chip->chip_id) {
3580 case KVM_IRQCHIP_PIC_MASTER:
3581 spin_lock(&pic_irqchip(kvm)->lock);
3582 memcpy(&pic_irqchip(kvm)->pics[0],
3583 &chip->chip.pic,
3584 sizeof(struct kvm_pic_state));
3585 spin_unlock(&pic_irqchip(kvm)->lock);
3586 break;
3587 case KVM_IRQCHIP_PIC_SLAVE:
3588 spin_lock(&pic_irqchip(kvm)->lock);
3589 memcpy(&pic_irqchip(kvm)->pics[1],
3590 &chip->chip.pic,
3591 sizeof(struct kvm_pic_state));
3592 spin_unlock(&pic_irqchip(kvm)->lock);
3593 break;
3594 case KVM_IRQCHIP_IOAPIC:
3595 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3596 break;
3597 default:
3598 r = -EINVAL;
3599 break;
3600 }
3601 kvm_pic_update_irq(pic_irqchip(kvm));
3602 return r;
3603 }
3604
3605 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3606 {
3607 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3608 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3609 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3610 return 0;
3611 }
3612
3613 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3614 {
3615 int i;
3616 struct kvm_pit *pit = kvm->arch.vpit;
3617
3618 mutex_lock(&pit->pit_state.lock);
3619 memcpy(&pit->pit_state, ps, sizeof(struct kvm_pit_state));
3620 for (i = 0; i < 3; i++)
3621 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3622 mutex_unlock(&pit->pit_state.lock);
3623 return 0;
3624 }
3625
3626 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3627 {
3628 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3629 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3630 sizeof(ps->channels));
3631 ps->flags = kvm->arch.vpit->pit_state.flags;
3632 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3633 memset(&ps->reserved, 0, sizeof(ps->reserved));
3634 return 0;
3635 }
3636
3637 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3638 {
3639 int start = 0;
3640 int i;
3641 u32 prev_legacy, cur_legacy;
3642 struct kvm_pit *pit = kvm->arch.vpit;
3643
3644 mutex_lock(&pit->pit_state.lock);
3645 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3646 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3647 if (!prev_legacy && cur_legacy)
3648 start = 1;
3649 memcpy(&pit->pit_state.channels, &ps->channels,
3650 sizeof(pit->pit_state.channels));
3651 pit->pit_state.flags = ps->flags;
3652 for (i = 0; i < 3; i++)
3653 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3654 start && i == 0);
3655 mutex_unlock(&pit->pit_state.lock);
3656 return 0;
3657 }
3658
3659 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3660 struct kvm_reinject_control *control)
3661 {
3662 struct kvm_pit *pit = kvm->arch.vpit;
3663
3664 if (!pit)
3665 return -ENXIO;
3666
3667 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3668 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3669 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3670 */
3671 mutex_lock(&pit->pit_state.lock);
3672 kvm_pit_set_reinject(pit, control->pit_reinject);
3673 mutex_unlock(&pit->pit_state.lock);
3674
3675 return 0;
3676 }
3677
3678 /**
3679 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3680 * @kvm: kvm instance
3681 * @log: slot id and address to which we copy the log
3682 *
3683 * Steps 1-4 below provide general overview of dirty page logging. See
3684 * kvm_get_dirty_log_protect() function description for additional details.
3685 *
3686 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3687 * always flush the TLB (step 4) even if previous step failed and the dirty
3688 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3689 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3690 * writes will be marked dirty for next log read.
3691 *
3692 * 1. Take a snapshot of the bit and clear it if needed.
3693 * 2. Write protect the corresponding page.
3694 * 3. Copy the snapshot to the userspace.
3695 * 4. Flush TLB's if needed.
3696 */
3697 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3698 {
3699 bool is_dirty = false;
3700 int r;
3701
3702 mutex_lock(&kvm->slots_lock);
3703
3704 /*
3705 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3706 */
3707 if (kvm_x86_ops->flush_log_dirty)
3708 kvm_x86_ops->flush_log_dirty(kvm);
3709
3710 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3711
3712 /*
3713 * All the TLBs can be flushed out of mmu lock, see the comments in
3714 * kvm_mmu_slot_remove_write_access().
3715 */
3716 lockdep_assert_held(&kvm->slots_lock);
3717 if (is_dirty)
3718 kvm_flush_remote_tlbs(kvm);
3719
3720 mutex_unlock(&kvm->slots_lock);
3721 return r;
3722 }
3723
3724 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3725 bool line_status)
3726 {
3727 if (!irqchip_in_kernel(kvm))
3728 return -ENXIO;
3729
3730 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3731 irq_event->irq, irq_event->level,
3732 line_status);
3733 return 0;
3734 }
3735
3736 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3737 struct kvm_enable_cap *cap)
3738 {
3739 int r;
3740
3741 if (cap->flags)
3742 return -EINVAL;
3743
3744 switch (cap->cap) {
3745 case KVM_CAP_DISABLE_QUIRKS:
3746 kvm->arch.disabled_quirks = cap->args[0];
3747 r = 0;
3748 break;
3749 case KVM_CAP_SPLIT_IRQCHIP: {
3750 mutex_lock(&kvm->lock);
3751 r = -EINVAL;
3752 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3753 goto split_irqchip_unlock;
3754 r = -EEXIST;
3755 if (irqchip_in_kernel(kvm))
3756 goto split_irqchip_unlock;
3757 if (atomic_read(&kvm->online_vcpus))
3758 goto split_irqchip_unlock;
3759 r = kvm_setup_empty_irq_routing(kvm);
3760 if (r)
3761 goto split_irqchip_unlock;
3762 /* Pairs with irqchip_in_kernel. */
3763 smp_wmb();
3764 kvm->arch.irqchip_split = true;
3765 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3766 r = 0;
3767 split_irqchip_unlock:
3768 mutex_unlock(&kvm->lock);
3769 break;
3770 }
3771 default:
3772 r = -EINVAL;
3773 break;
3774 }
3775 return r;
3776 }
3777
3778 long kvm_arch_vm_ioctl(struct file *filp,
3779 unsigned int ioctl, unsigned long arg)
3780 {
3781 struct kvm *kvm = filp->private_data;
3782 void __user *argp = (void __user *)arg;
3783 int r = -ENOTTY;
3784 /*
3785 * This union makes it completely explicit to gcc-3.x
3786 * that these two variables' stack usage should be
3787 * combined, not added together.
3788 */
3789 union {
3790 struct kvm_pit_state ps;
3791 struct kvm_pit_state2 ps2;
3792 struct kvm_pit_config pit_config;
3793 } u;
3794
3795 switch (ioctl) {
3796 case KVM_SET_TSS_ADDR:
3797 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3798 break;
3799 case KVM_SET_IDENTITY_MAP_ADDR: {
3800 u64 ident_addr;
3801
3802 r = -EFAULT;
3803 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3804 goto out;
3805 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3806 break;
3807 }
3808 case KVM_SET_NR_MMU_PAGES:
3809 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3810 break;
3811 case KVM_GET_NR_MMU_PAGES:
3812 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3813 break;
3814 case KVM_CREATE_IRQCHIP: {
3815 struct kvm_pic *vpic;
3816
3817 mutex_lock(&kvm->lock);
3818 r = -EEXIST;
3819 if (kvm->arch.vpic)
3820 goto create_irqchip_unlock;
3821 r = -EINVAL;
3822 if (atomic_read(&kvm->online_vcpus))
3823 goto create_irqchip_unlock;
3824 r = -ENOMEM;
3825 vpic = kvm_create_pic(kvm);
3826 if (vpic) {
3827 r = kvm_ioapic_init(kvm);
3828 if (r) {
3829 mutex_lock(&kvm->slots_lock);
3830 kvm_destroy_pic(vpic);
3831 mutex_unlock(&kvm->slots_lock);
3832 goto create_irqchip_unlock;
3833 }
3834 } else
3835 goto create_irqchip_unlock;
3836 r = kvm_setup_default_irq_routing(kvm);
3837 if (r) {
3838 mutex_lock(&kvm->slots_lock);
3839 mutex_lock(&kvm->irq_lock);
3840 kvm_ioapic_destroy(kvm);
3841 kvm_destroy_pic(vpic);
3842 mutex_unlock(&kvm->irq_lock);
3843 mutex_unlock(&kvm->slots_lock);
3844 goto create_irqchip_unlock;
3845 }
3846 /* Write kvm->irq_routing before kvm->arch.vpic. */
3847 smp_wmb();
3848 kvm->arch.vpic = vpic;
3849 create_irqchip_unlock:
3850 mutex_unlock(&kvm->lock);
3851 break;
3852 }
3853 case KVM_CREATE_PIT:
3854 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3855 goto create_pit;
3856 case KVM_CREATE_PIT2:
3857 r = -EFAULT;
3858 if (copy_from_user(&u.pit_config, argp,
3859 sizeof(struct kvm_pit_config)))
3860 goto out;
3861 create_pit:
3862 mutex_lock(&kvm->slots_lock);
3863 r = -EEXIST;
3864 if (kvm->arch.vpit)
3865 goto create_pit_unlock;
3866 r = -ENOMEM;
3867 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3868 if (kvm->arch.vpit)
3869 r = 0;
3870 create_pit_unlock:
3871 mutex_unlock(&kvm->slots_lock);
3872 break;
3873 case KVM_GET_IRQCHIP: {
3874 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3875 struct kvm_irqchip *chip;
3876
3877 chip = memdup_user(argp, sizeof(*chip));
3878 if (IS_ERR(chip)) {
3879 r = PTR_ERR(chip);
3880 goto out;
3881 }
3882
3883 r = -ENXIO;
3884 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3885 goto get_irqchip_out;
3886 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3887 if (r)
3888 goto get_irqchip_out;
3889 r = -EFAULT;
3890 if (copy_to_user(argp, chip, sizeof *chip))
3891 goto get_irqchip_out;
3892 r = 0;
3893 get_irqchip_out:
3894 kfree(chip);
3895 break;
3896 }
3897 case KVM_SET_IRQCHIP: {
3898 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3899 struct kvm_irqchip *chip;
3900
3901 chip = memdup_user(argp, sizeof(*chip));
3902 if (IS_ERR(chip)) {
3903 r = PTR_ERR(chip);
3904 goto out;
3905 }
3906
3907 r = -ENXIO;
3908 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3909 goto set_irqchip_out;
3910 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3911 if (r)
3912 goto set_irqchip_out;
3913 r = 0;
3914 set_irqchip_out:
3915 kfree(chip);
3916 break;
3917 }
3918 case KVM_GET_PIT: {
3919 r = -EFAULT;
3920 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3921 goto out;
3922 r = -ENXIO;
3923 if (!kvm->arch.vpit)
3924 goto out;
3925 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3926 if (r)
3927 goto out;
3928 r = -EFAULT;
3929 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3930 goto out;
3931 r = 0;
3932 break;
3933 }
3934 case KVM_SET_PIT: {
3935 r = -EFAULT;
3936 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3937 goto out;
3938 r = -ENXIO;
3939 if (!kvm->arch.vpit)
3940 goto out;
3941 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3942 break;
3943 }
3944 case KVM_GET_PIT2: {
3945 r = -ENXIO;
3946 if (!kvm->arch.vpit)
3947 goto out;
3948 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3949 if (r)
3950 goto out;
3951 r = -EFAULT;
3952 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3953 goto out;
3954 r = 0;
3955 break;
3956 }
3957 case KVM_SET_PIT2: {
3958 r = -EFAULT;
3959 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3960 goto out;
3961 r = -ENXIO;
3962 if (!kvm->arch.vpit)
3963 goto out;
3964 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3965 break;
3966 }
3967 case KVM_REINJECT_CONTROL: {
3968 struct kvm_reinject_control control;
3969 r = -EFAULT;
3970 if (copy_from_user(&control, argp, sizeof(control)))
3971 goto out;
3972 r = kvm_vm_ioctl_reinject(kvm, &control);
3973 break;
3974 }
3975 case KVM_SET_BOOT_CPU_ID:
3976 r = 0;
3977 mutex_lock(&kvm->lock);
3978 if (atomic_read(&kvm->online_vcpus) != 0)
3979 r = -EBUSY;
3980 else
3981 kvm->arch.bsp_vcpu_id = arg;
3982 mutex_unlock(&kvm->lock);
3983 break;
3984 case KVM_XEN_HVM_CONFIG: {
3985 r = -EFAULT;
3986 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3987 sizeof(struct kvm_xen_hvm_config)))
3988 goto out;
3989 r = -EINVAL;
3990 if (kvm->arch.xen_hvm_config.flags)
3991 goto out;
3992 r = 0;
3993 break;
3994 }
3995 case KVM_SET_CLOCK: {
3996 struct kvm_clock_data user_ns;
3997 u64 now_ns;
3998 s64 delta;
3999
4000 r = -EFAULT;
4001 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4002 goto out;
4003
4004 r = -EINVAL;
4005 if (user_ns.flags)
4006 goto out;
4007
4008 r = 0;
4009 local_irq_disable();
4010 now_ns = get_kernel_ns();
4011 delta = user_ns.clock - now_ns;
4012 local_irq_enable();
4013 kvm->arch.kvmclock_offset = delta;
4014 kvm_gen_update_masterclock(kvm);
4015 break;
4016 }
4017 case KVM_GET_CLOCK: {
4018 struct kvm_clock_data user_ns;
4019 u64 now_ns;
4020
4021 local_irq_disable();
4022 now_ns = get_kernel_ns();
4023 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4024 local_irq_enable();
4025 user_ns.flags = 0;
4026 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4027
4028 r = -EFAULT;
4029 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4030 goto out;
4031 r = 0;
4032 break;
4033 }
4034 case KVM_ENABLE_CAP: {
4035 struct kvm_enable_cap cap;
4036
4037 r = -EFAULT;
4038 if (copy_from_user(&cap, argp, sizeof(cap)))
4039 goto out;
4040 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4041 break;
4042 }
4043 default:
4044 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4045 }
4046 out:
4047 return r;
4048 }
4049
4050 static void kvm_init_msr_list(void)
4051 {
4052 u32 dummy[2];
4053 unsigned i, j;
4054
4055 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4056 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4057 continue;
4058
4059 /*
4060 * Even MSRs that are valid in the host may not be exposed
4061 * to the guests in some cases.
4062 */
4063 switch (msrs_to_save[i]) {
4064 case MSR_IA32_BNDCFGS:
4065 if (!kvm_x86_ops->mpx_supported())
4066 continue;
4067 break;
4068 case MSR_TSC_AUX:
4069 if (!kvm_x86_ops->rdtscp_supported())
4070 continue;
4071 break;
4072 default:
4073 break;
4074 }
4075
4076 if (j < i)
4077 msrs_to_save[j] = msrs_to_save[i];
4078 j++;
4079 }
4080 num_msrs_to_save = j;
4081
4082 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4083 switch (emulated_msrs[i]) {
4084 case MSR_IA32_SMBASE:
4085 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4086 continue;
4087 break;
4088 default:
4089 break;
4090 }
4091
4092 if (j < i)
4093 emulated_msrs[j] = emulated_msrs[i];
4094 j++;
4095 }
4096 num_emulated_msrs = j;
4097 }
4098
4099 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4100 const void *v)
4101 {
4102 int handled = 0;
4103 int n;
4104
4105 do {
4106 n = min(len, 8);
4107 if (!(lapic_in_kernel(vcpu) &&
4108 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4109 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4110 break;
4111 handled += n;
4112 addr += n;
4113 len -= n;
4114 v += n;
4115 } while (len);
4116
4117 return handled;
4118 }
4119
4120 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4121 {
4122 int handled = 0;
4123 int n;
4124
4125 do {
4126 n = min(len, 8);
4127 if (!(lapic_in_kernel(vcpu) &&
4128 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4129 addr, n, v))
4130 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4131 break;
4132 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4133 handled += n;
4134 addr += n;
4135 len -= n;
4136 v += n;
4137 } while (len);
4138
4139 return handled;
4140 }
4141
4142 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4143 struct kvm_segment *var, int seg)
4144 {
4145 kvm_x86_ops->set_segment(vcpu, var, seg);
4146 }
4147
4148 void kvm_get_segment(struct kvm_vcpu *vcpu,
4149 struct kvm_segment *var, int seg)
4150 {
4151 kvm_x86_ops->get_segment(vcpu, var, seg);
4152 }
4153
4154 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4155 struct x86_exception *exception)
4156 {
4157 gpa_t t_gpa;
4158
4159 BUG_ON(!mmu_is_nested(vcpu));
4160
4161 /* NPT walks are always user-walks */
4162 access |= PFERR_USER_MASK;
4163 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4164
4165 return t_gpa;
4166 }
4167
4168 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4169 struct x86_exception *exception)
4170 {
4171 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4172 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4173 }
4174
4175 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4176 struct x86_exception *exception)
4177 {
4178 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4179 access |= PFERR_FETCH_MASK;
4180 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4181 }
4182
4183 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4184 struct x86_exception *exception)
4185 {
4186 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4187 access |= PFERR_WRITE_MASK;
4188 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4189 }
4190
4191 /* uses this to access any guest's mapped memory without checking CPL */
4192 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4193 struct x86_exception *exception)
4194 {
4195 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4196 }
4197
4198 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4199 struct kvm_vcpu *vcpu, u32 access,
4200 struct x86_exception *exception)
4201 {
4202 void *data = val;
4203 int r = X86EMUL_CONTINUE;
4204
4205 while (bytes) {
4206 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4207 exception);
4208 unsigned offset = addr & (PAGE_SIZE-1);
4209 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4210 int ret;
4211
4212 if (gpa == UNMAPPED_GVA)
4213 return X86EMUL_PROPAGATE_FAULT;
4214 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4215 offset, toread);
4216 if (ret < 0) {
4217 r = X86EMUL_IO_NEEDED;
4218 goto out;
4219 }
4220
4221 bytes -= toread;
4222 data += toread;
4223 addr += toread;
4224 }
4225 out:
4226 return r;
4227 }
4228
4229 /* used for instruction fetching */
4230 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4231 gva_t addr, void *val, unsigned int bytes,
4232 struct x86_exception *exception)
4233 {
4234 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4235 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4236 unsigned offset;
4237 int ret;
4238
4239 /* Inline kvm_read_guest_virt_helper for speed. */
4240 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4241 exception);
4242 if (unlikely(gpa == UNMAPPED_GVA))
4243 return X86EMUL_PROPAGATE_FAULT;
4244
4245 offset = addr & (PAGE_SIZE-1);
4246 if (WARN_ON(offset + bytes > PAGE_SIZE))
4247 bytes = (unsigned)PAGE_SIZE - offset;
4248 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4249 offset, bytes);
4250 if (unlikely(ret < 0))
4251 return X86EMUL_IO_NEEDED;
4252
4253 return X86EMUL_CONTINUE;
4254 }
4255
4256 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4257 gva_t addr, void *val, unsigned int bytes,
4258 struct x86_exception *exception)
4259 {
4260 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4261 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4262
4263 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4264 exception);
4265 }
4266 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4267
4268 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4269 gva_t addr, void *val, unsigned int bytes,
4270 struct x86_exception *exception)
4271 {
4272 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4273 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4274 }
4275
4276 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4277 unsigned long addr, void *val, unsigned int bytes)
4278 {
4279 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4280 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4281
4282 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4283 }
4284
4285 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4286 gva_t addr, void *val,
4287 unsigned int bytes,
4288 struct x86_exception *exception)
4289 {
4290 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4291 void *data = val;
4292 int r = X86EMUL_CONTINUE;
4293
4294 while (bytes) {
4295 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4296 PFERR_WRITE_MASK,
4297 exception);
4298 unsigned offset = addr & (PAGE_SIZE-1);
4299 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4300 int ret;
4301
4302 if (gpa == UNMAPPED_GVA)
4303 return X86EMUL_PROPAGATE_FAULT;
4304 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4305 if (ret < 0) {
4306 r = X86EMUL_IO_NEEDED;
4307 goto out;
4308 }
4309
4310 bytes -= towrite;
4311 data += towrite;
4312 addr += towrite;
4313 }
4314 out:
4315 return r;
4316 }
4317 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4318
4319 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4320 gpa_t *gpa, struct x86_exception *exception,
4321 bool write)
4322 {
4323 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4324 | (write ? PFERR_WRITE_MASK : 0);
4325
4326 if (vcpu_match_mmio_gva(vcpu, gva)
4327 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4328 vcpu->arch.access, access)) {
4329 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4330 (gva & (PAGE_SIZE - 1));
4331 trace_vcpu_match_mmio(gva, *gpa, write, false);
4332 return 1;
4333 }
4334
4335 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4336
4337 if (*gpa == UNMAPPED_GVA)
4338 return -1;
4339
4340 /* For APIC access vmexit */
4341 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4342 return 1;
4343
4344 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4345 trace_vcpu_match_mmio(gva, *gpa, write, true);
4346 return 1;
4347 }
4348
4349 return 0;
4350 }
4351
4352 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4353 const void *val, int bytes)
4354 {
4355 int ret;
4356
4357 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4358 if (ret < 0)
4359 return 0;
4360 kvm_page_track_write(vcpu, gpa, val, bytes);
4361 return 1;
4362 }
4363
4364 struct read_write_emulator_ops {
4365 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4366 int bytes);
4367 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4368 void *val, int bytes);
4369 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4370 int bytes, void *val);
4371 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4372 void *val, int bytes);
4373 bool write;
4374 };
4375
4376 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4377 {
4378 if (vcpu->mmio_read_completed) {
4379 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4380 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4381 vcpu->mmio_read_completed = 0;
4382 return 1;
4383 }
4384
4385 return 0;
4386 }
4387
4388 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4389 void *val, int bytes)
4390 {
4391 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4392 }
4393
4394 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4395 void *val, int bytes)
4396 {
4397 return emulator_write_phys(vcpu, gpa, val, bytes);
4398 }
4399
4400 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4401 {
4402 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4403 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4404 }
4405
4406 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4407 void *val, int bytes)
4408 {
4409 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4410 return X86EMUL_IO_NEEDED;
4411 }
4412
4413 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4414 void *val, int bytes)
4415 {
4416 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4417
4418 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4419 return X86EMUL_CONTINUE;
4420 }
4421
4422 static const struct read_write_emulator_ops read_emultor = {
4423 .read_write_prepare = read_prepare,
4424 .read_write_emulate = read_emulate,
4425 .read_write_mmio = vcpu_mmio_read,
4426 .read_write_exit_mmio = read_exit_mmio,
4427 };
4428
4429 static const struct read_write_emulator_ops write_emultor = {
4430 .read_write_emulate = write_emulate,
4431 .read_write_mmio = write_mmio,
4432 .read_write_exit_mmio = write_exit_mmio,
4433 .write = true,
4434 };
4435
4436 static int emulator_read_write_onepage(unsigned long addr, void *val,
4437 unsigned int bytes,
4438 struct x86_exception *exception,
4439 struct kvm_vcpu *vcpu,
4440 const struct read_write_emulator_ops *ops)
4441 {
4442 gpa_t gpa;
4443 int handled, ret;
4444 bool write = ops->write;
4445 struct kvm_mmio_fragment *frag;
4446
4447 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4448
4449 if (ret < 0)
4450 return X86EMUL_PROPAGATE_FAULT;
4451
4452 /* For APIC access vmexit */
4453 if (ret)
4454 goto mmio;
4455
4456 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4457 return X86EMUL_CONTINUE;
4458
4459 mmio:
4460 /*
4461 * Is this MMIO handled locally?
4462 */
4463 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4464 if (handled == bytes)
4465 return X86EMUL_CONTINUE;
4466
4467 gpa += handled;
4468 bytes -= handled;
4469 val += handled;
4470
4471 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4472 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4473 frag->gpa = gpa;
4474 frag->data = val;
4475 frag->len = bytes;
4476 return X86EMUL_CONTINUE;
4477 }
4478
4479 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4480 unsigned long addr,
4481 void *val, unsigned int bytes,
4482 struct x86_exception *exception,
4483 const struct read_write_emulator_ops *ops)
4484 {
4485 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4486 gpa_t gpa;
4487 int rc;
4488
4489 if (ops->read_write_prepare &&
4490 ops->read_write_prepare(vcpu, val, bytes))
4491 return X86EMUL_CONTINUE;
4492
4493 vcpu->mmio_nr_fragments = 0;
4494
4495 /* Crossing a page boundary? */
4496 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4497 int now;
4498
4499 now = -addr & ~PAGE_MASK;
4500 rc = emulator_read_write_onepage(addr, val, now, exception,
4501 vcpu, ops);
4502
4503 if (rc != X86EMUL_CONTINUE)
4504 return rc;
4505 addr += now;
4506 if (ctxt->mode != X86EMUL_MODE_PROT64)
4507 addr = (u32)addr;
4508 val += now;
4509 bytes -= now;
4510 }
4511
4512 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4513 vcpu, ops);
4514 if (rc != X86EMUL_CONTINUE)
4515 return rc;
4516
4517 if (!vcpu->mmio_nr_fragments)
4518 return rc;
4519
4520 gpa = vcpu->mmio_fragments[0].gpa;
4521
4522 vcpu->mmio_needed = 1;
4523 vcpu->mmio_cur_fragment = 0;
4524
4525 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4526 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4527 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4528 vcpu->run->mmio.phys_addr = gpa;
4529
4530 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4531 }
4532
4533 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4534 unsigned long addr,
4535 void *val,
4536 unsigned int bytes,
4537 struct x86_exception *exception)
4538 {
4539 return emulator_read_write(ctxt, addr, val, bytes,
4540 exception, &read_emultor);
4541 }
4542
4543 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4544 unsigned long addr,
4545 const void *val,
4546 unsigned int bytes,
4547 struct x86_exception *exception)
4548 {
4549 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4550 exception, &write_emultor);
4551 }
4552
4553 #define CMPXCHG_TYPE(t, ptr, old, new) \
4554 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4555
4556 #ifdef CONFIG_X86_64
4557 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4558 #else
4559 # define CMPXCHG64(ptr, old, new) \
4560 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4561 #endif
4562
4563 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4564 unsigned long addr,
4565 const void *old,
4566 const void *new,
4567 unsigned int bytes,
4568 struct x86_exception *exception)
4569 {
4570 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4571 gpa_t gpa;
4572 struct page *page;
4573 char *kaddr;
4574 bool exchanged;
4575
4576 /* guests cmpxchg8b have to be emulated atomically */
4577 if (bytes > 8 || (bytes & (bytes - 1)))
4578 goto emul_write;
4579
4580 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4581
4582 if (gpa == UNMAPPED_GVA ||
4583 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4584 goto emul_write;
4585
4586 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4587 goto emul_write;
4588
4589 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4590 if (is_error_page(page))
4591 goto emul_write;
4592
4593 kaddr = kmap_atomic(page);
4594 kaddr += offset_in_page(gpa);
4595 switch (bytes) {
4596 case 1:
4597 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4598 break;
4599 case 2:
4600 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4601 break;
4602 case 4:
4603 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4604 break;
4605 case 8:
4606 exchanged = CMPXCHG64(kaddr, old, new);
4607 break;
4608 default:
4609 BUG();
4610 }
4611 kunmap_atomic(kaddr);
4612 kvm_release_page_dirty(page);
4613
4614 if (!exchanged)
4615 return X86EMUL_CMPXCHG_FAILED;
4616
4617 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4618 kvm_page_track_write(vcpu, gpa, new, bytes);
4619
4620 return X86EMUL_CONTINUE;
4621
4622 emul_write:
4623 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4624
4625 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4626 }
4627
4628 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4629 {
4630 /* TODO: String I/O for in kernel device */
4631 int r;
4632
4633 if (vcpu->arch.pio.in)
4634 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4635 vcpu->arch.pio.size, pd);
4636 else
4637 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4638 vcpu->arch.pio.port, vcpu->arch.pio.size,
4639 pd);
4640 return r;
4641 }
4642
4643 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4644 unsigned short port, void *val,
4645 unsigned int count, bool in)
4646 {
4647 vcpu->arch.pio.port = port;
4648 vcpu->arch.pio.in = in;
4649 vcpu->arch.pio.count = count;
4650 vcpu->arch.pio.size = size;
4651
4652 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4653 vcpu->arch.pio.count = 0;
4654 return 1;
4655 }
4656
4657 vcpu->run->exit_reason = KVM_EXIT_IO;
4658 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4659 vcpu->run->io.size = size;
4660 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4661 vcpu->run->io.count = count;
4662 vcpu->run->io.port = port;
4663
4664 return 0;
4665 }
4666
4667 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4668 int size, unsigned short port, void *val,
4669 unsigned int count)
4670 {
4671 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4672 int ret;
4673
4674 if (vcpu->arch.pio.count)
4675 goto data_avail;
4676
4677 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4678 if (ret) {
4679 data_avail:
4680 memcpy(val, vcpu->arch.pio_data, size * count);
4681 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4682 vcpu->arch.pio.count = 0;
4683 return 1;
4684 }
4685
4686 return 0;
4687 }
4688
4689 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4690 int size, unsigned short port,
4691 const void *val, unsigned int count)
4692 {
4693 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4694
4695 memcpy(vcpu->arch.pio_data, val, size * count);
4696 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4697 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4698 }
4699
4700 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4701 {
4702 return kvm_x86_ops->get_segment_base(vcpu, seg);
4703 }
4704
4705 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4706 {
4707 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4708 }
4709
4710 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4711 {
4712 if (!need_emulate_wbinvd(vcpu))
4713 return X86EMUL_CONTINUE;
4714
4715 if (kvm_x86_ops->has_wbinvd_exit()) {
4716 int cpu = get_cpu();
4717
4718 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4719 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4720 wbinvd_ipi, NULL, 1);
4721 put_cpu();
4722 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4723 } else
4724 wbinvd();
4725 return X86EMUL_CONTINUE;
4726 }
4727
4728 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4729 {
4730 kvm_x86_ops->skip_emulated_instruction(vcpu);
4731 return kvm_emulate_wbinvd_noskip(vcpu);
4732 }
4733 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4734
4735
4736
4737 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4738 {
4739 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4740 }
4741
4742 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4743 unsigned long *dest)
4744 {
4745 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4746 }
4747
4748 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4749 unsigned long value)
4750 {
4751
4752 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4753 }
4754
4755 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4756 {
4757 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4758 }
4759
4760 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4761 {
4762 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4763 unsigned long value;
4764
4765 switch (cr) {
4766 case 0:
4767 value = kvm_read_cr0(vcpu);
4768 break;
4769 case 2:
4770 value = vcpu->arch.cr2;
4771 break;
4772 case 3:
4773 value = kvm_read_cr3(vcpu);
4774 break;
4775 case 4:
4776 value = kvm_read_cr4(vcpu);
4777 break;
4778 case 8:
4779 value = kvm_get_cr8(vcpu);
4780 break;
4781 default:
4782 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4783 return 0;
4784 }
4785
4786 return value;
4787 }
4788
4789 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4790 {
4791 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4792 int res = 0;
4793
4794 switch (cr) {
4795 case 0:
4796 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4797 break;
4798 case 2:
4799 vcpu->arch.cr2 = val;
4800 break;
4801 case 3:
4802 res = kvm_set_cr3(vcpu, val);
4803 break;
4804 case 4:
4805 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4806 break;
4807 case 8:
4808 res = kvm_set_cr8(vcpu, val);
4809 break;
4810 default:
4811 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4812 res = -1;
4813 }
4814
4815 return res;
4816 }
4817
4818 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4819 {
4820 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4821 }
4822
4823 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4824 {
4825 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4826 }
4827
4828 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4829 {
4830 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4831 }
4832
4833 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4834 {
4835 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4836 }
4837
4838 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4839 {
4840 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4841 }
4842
4843 static unsigned long emulator_get_cached_segment_base(
4844 struct x86_emulate_ctxt *ctxt, int seg)
4845 {
4846 return get_segment_base(emul_to_vcpu(ctxt), seg);
4847 }
4848
4849 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4850 struct desc_struct *desc, u32 *base3,
4851 int seg)
4852 {
4853 struct kvm_segment var;
4854
4855 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4856 *selector = var.selector;
4857
4858 if (var.unusable) {
4859 memset(desc, 0, sizeof(*desc));
4860 return false;
4861 }
4862
4863 if (var.g)
4864 var.limit >>= 12;
4865 set_desc_limit(desc, var.limit);
4866 set_desc_base(desc, (unsigned long)var.base);
4867 #ifdef CONFIG_X86_64
4868 if (base3)
4869 *base3 = var.base >> 32;
4870 #endif
4871 desc->type = var.type;
4872 desc->s = var.s;
4873 desc->dpl = var.dpl;
4874 desc->p = var.present;
4875 desc->avl = var.avl;
4876 desc->l = var.l;
4877 desc->d = var.db;
4878 desc->g = var.g;
4879
4880 return true;
4881 }
4882
4883 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4884 struct desc_struct *desc, u32 base3,
4885 int seg)
4886 {
4887 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4888 struct kvm_segment var;
4889
4890 var.selector = selector;
4891 var.base = get_desc_base(desc);
4892 #ifdef CONFIG_X86_64
4893 var.base |= ((u64)base3) << 32;
4894 #endif
4895 var.limit = get_desc_limit(desc);
4896 if (desc->g)
4897 var.limit = (var.limit << 12) | 0xfff;
4898 var.type = desc->type;
4899 var.dpl = desc->dpl;
4900 var.db = desc->d;
4901 var.s = desc->s;
4902 var.l = desc->l;
4903 var.g = desc->g;
4904 var.avl = desc->avl;
4905 var.present = desc->p;
4906 var.unusable = !var.present;
4907 var.padding = 0;
4908
4909 kvm_set_segment(vcpu, &var, seg);
4910 return;
4911 }
4912
4913 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4914 u32 msr_index, u64 *pdata)
4915 {
4916 struct msr_data msr;
4917 int r;
4918
4919 msr.index = msr_index;
4920 msr.host_initiated = false;
4921 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4922 if (r)
4923 return r;
4924
4925 *pdata = msr.data;
4926 return 0;
4927 }
4928
4929 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4930 u32 msr_index, u64 data)
4931 {
4932 struct msr_data msr;
4933
4934 msr.data = data;
4935 msr.index = msr_index;
4936 msr.host_initiated = false;
4937 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4938 }
4939
4940 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4941 {
4942 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4943
4944 return vcpu->arch.smbase;
4945 }
4946
4947 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4948 {
4949 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4950
4951 vcpu->arch.smbase = smbase;
4952 }
4953
4954 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4955 u32 pmc)
4956 {
4957 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4958 }
4959
4960 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4961 u32 pmc, u64 *pdata)
4962 {
4963 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4964 }
4965
4966 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4967 {
4968 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4969 }
4970
4971 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4972 {
4973 preempt_disable();
4974 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4975 /*
4976 * CR0.TS may reference the host fpu state, not the guest fpu state,
4977 * so it may be clear at this point.
4978 */
4979 clts();
4980 }
4981
4982 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4983 {
4984 preempt_enable();
4985 }
4986
4987 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4988 struct x86_instruction_info *info,
4989 enum x86_intercept_stage stage)
4990 {
4991 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4992 }
4993
4994 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4995 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4996 {
4997 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4998 }
4999
5000 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5001 {
5002 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5003 }
5004
5005 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5006 {
5007 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5008 }
5009
5010 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5011 {
5012 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5013 }
5014
5015 static const struct x86_emulate_ops emulate_ops = {
5016 .read_gpr = emulator_read_gpr,
5017 .write_gpr = emulator_write_gpr,
5018 .read_std = kvm_read_guest_virt_system,
5019 .write_std = kvm_write_guest_virt_system,
5020 .read_phys = kvm_read_guest_phys_system,
5021 .fetch = kvm_fetch_guest_virt,
5022 .read_emulated = emulator_read_emulated,
5023 .write_emulated = emulator_write_emulated,
5024 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5025 .invlpg = emulator_invlpg,
5026 .pio_in_emulated = emulator_pio_in_emulated,
5027 .pio_out_emulated = emulator_pio_out_emulated,
5028 .get_segment = emulator_get_segment,
5029 .set_segment = emulator_set_segment,
5030 .get_cached_segment_base = emulator_get_cached_segment_base,
5031 .get_gdt = emulator_get_gdt,
5032 .get_idt = emulator_get_idt,
5033 .set_gdt = emulator_set_gdt,
5034 .set_idt = emulator_set_idt,
5035 .get_cr = emulator_get_cr,
5036 .set_cr = emulator_set_cr,
5037 .cpl = emulator_get_cpl,
5038 .get_dr = emulator_get_dr,
5039 .set_dr = emulator_set_dr,
5040 .get_smbase = emulator_get_smbase,
5041 .set_smbase = emulator_set_smbase,
5042 .set_msr = emulator_set_msr,
5043 .get_msr = emulator_get_msr,
5044 .check_pmc = emulator_check_pmc,
5045 .read_pmc = emulator_read_pmc,
5046 .halt = emulator_halt,
5047 .wbinvd = emulator_wbinvd,
5048 .fix_hypercall = emulator_fix_hypercall,
5049 .get_fpu = emulator_get_fpu,
5050 .put_fpu = emulator_put_fpu,
5051 .intercept = emulator_intercept,
5052 .get_cpuid = emulator_get_cpuid,
5053 .set_nmi_mask = emulator_set_nmi_mask,
5054 };
5055
5056 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5057 {
5058 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5059 /*
5060 * an sti; sti; sequence only disable interrupts for the first
5061 * instruction. So, if the last instruction, be it emulated or
5062 * not, left the system with the INT_STI flag enabled, it
5063 * means that the last instruction is an sti. We should not
5064 * leave the flag on in this case. The same goes for mov ss
5065 */
5066 if (int_shadow & mask)
5067 mask = 0;
5068 if (unlikely(int_shadow || mask)) {
5069 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5070 if (!mask)
5071 kvm_make_request(KVM_REQ_EVENT, vcpu);
5072 }
5073 }
5074
5075 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5076 {
5077 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5078 if (ctxt->exception.vector == PF_VECTOR)
5079 return kvm_propagate_fault(vcpu, &ctxt->exception);
5080
5081 if (ctxt->exception.error_code_valid)
5082 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5083 ctxt->exception.error_code);
5084 else
5085 kvm_queue_exception(vcpu, ctxt->exception.vector);
5086 return false;
5087 }
5088
5089 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5090 {
5091 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5092 int cs_db, cs_l;
5093
5094 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5095
5096 ctxt->eflags = kvm_get_rflags(vcpu);
5097 ctxt->eip = kvm_rip_read(vcpu);
5098 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5099 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5100 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5101 cs_db ? X86EMUL_MODE_PROT32 :
5102 X86EMUL_MODE_PROT16;
5103 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5104 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5105 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5106 ctxt->emul_flags = vcpu->arch.hflags;
5107
5108 init_decode_cache(ctxt);
5109 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5110 }
5111
5112 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5113 {
5114 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5115 int ret;
5116
5117 init_emulate_ctxt(vcpu);
5118
5119 ctxt->op_bytes = 2;
5120 ctxt->ad_bytes = 2;
5121 ctxt->_eip = ctxt->eip + inc_eip;
5122 ret = emulate_int_real(ctxt, irq);
5123
5124 if (ret != X86EMUL_CONTINUE)
5125 return EMULATE_FAIL;
5126
5127 ctxt->eip = ctxt->_eip;
5128 kvm_rip_write(vcpu, ctxt->eip);
5129 kvm_set_rflags(vcpu, ctxt->eflags);
5130
5131 if (irq == NMI_VECTOR)
5132 vcpu->arch.nmi_pending = 0;
5133 else
5134 vcpu->arch.interrupt.pending = false;
5135
5136 return EMULATE_DONE;
5137 }
5138 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5139
5140 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5141 {
5142 int r = EMULATE_DONE;
5143
5144 ++vcpu->stat.insn_emulation_fail;
5145 trace_kvm_emulate_insn_failed(vcpu);
5146 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5147 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5148 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5149 vcpu->run->internal.ndata = 0;
5150 r = EMULATE_FAIL;
5151 }
5152 kvm_queue_exception(vcpu, UD_VECTOR);
5153
5154 return r;
5155 }
5156
5157 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5158 bool write_fault_to_shadow_pgtable,
5159 int emulation_type)
5160 {
5161 gpa_t gpa = cr2;
5162 kvm_pfn_t pfn;
5163
5164 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5165 return false;
5166
5167 if (!vcpu->arch.mmu.direct_map) {
5168 /*
5169 * Write permission should be allowed since only
5170 * write access need to be emulated.
5171 */
5172 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5173
5174 /*
5175 * If the mapping is invalid in guest, let cpu retry
5176 * it to generate fault.
5177 */
5178 if (gpa == UNMAPPED_GVA)
5179 return true;
5180 }
5181
5182 /*
5183 * Do not retry the unhandleable instruction if it faults on the
5184 * readonly host memory, otherwise it will goto a infinite loop:
5185 * retry instruction -> write #PF -> emulation fail -> retry
5186 * instruction -> ...
5187 */
5188 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5189
5190 /*
5191 * If the instruction failed on the error pfn, it can not be fixed,
5192 * report the error to userspace.
5193 */
5194 if (is_error_noslot_pfn(pfn))
5195 return false;
5196
5197 kvm_release_pfn_clean(pfn);
5198
5199 /* The instructions are well-emulated on direct mmu. */
5200 if (vcpu->arch.mmu.direct_map) {
5201 unsigned int indirect_shadow_pages;
5202
5203 spin_lock(&vcpu->kvm->mmu_lock);
5204 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5205 spin_unlock(&vcpu->kvm->mmu_lock);
5206
5207 if (indirect_shadow_pages)
5208 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5209
5210 return true;
5211 }
5212
5213 /*
5214 * if emulation was due to access to shadowed page table
5215 * and it failed try to unshadow page and re-enter the
5216 * guest to let CPU execute the instruction.
5217 */
5218 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5219
5220 /*
5221 * If the access faults on its page table, it can not
5222 * be fixed by unprotecting shadow page and it should
5223 * be reported to userspace.
5224 */
5225 return !write_fault_to_shadow_pgtable;
5226 }
5227
5228 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5229 unsigned long cr2, int emulation_type)
5230 {
5231 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5232 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5233
5234 last_retry_eip = vcpu->arch.last_retry_eip;
5235 last_retry_addr = vcpu->arch.last_retry_addr;
5236
5237 /*
5238 * If the emulation is caused by #PF and it is non-page_table
5239 * writing instruction, it means the VM-EXIT is caused by shadow
5240 * page protected, we can zap the shadow page and retry this
5241 * instruction directly.
5242 *
5243 * Note: if the guest uses a non-page-table modifying instruction
5244 * on the PDE that points to the instruction, then we will unmap
5245 * the instruction and go to an infinite loop. So, we cache the
5246 * last retried eip and the last fault address, if we meet the eip
5247 * and the address again, we can break out of the potential infinite
5248 * loop.
5249 */
5250 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5251
5252 if (!(emulation_type & EMULTYPE_RETRY))
5253 return false;
5254
5255 if (x86_page_table_writing_insn(ctxt))
5256 return false;
5257
5258 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5259 return false;
5260
5261 vcpu->arch.last_retry_eip = ctxt->eip;
5262 vcpu->arch.last_retry_addr = cr2;
5263
5264 if (!vcpu->arch.mmu.direct_map)
5265 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5266
5267 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5268
5269 return true;
5270 }
5271
5272 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5273 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5274
5275 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5276 {
5277 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5278 /* This is a good place to trace that we are exiting SMM. */
5279 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5280
5281 if (unlikely(vcpu->arch.smi_pending)) {
5282 kvm_make_request(KVM_REQ_SMI, vcpu);
5283 vcpu->arch.smi_pending = 0;
5284 } else {
5285 /* Process a latched INIT, if any. */
5286 kvm_make_request(KVM_REQ_EVENT, vcpu);
5287 }
5288 }
5289
5290 kvm_mmu_reset_context(vcpu);
5291 }
5292
5293 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5294 {
5295 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5296
5297 vcpu->arch.hflags = emul_flags;
5298
5299 if (changed & HF_SMM_MASK)
5300 kvm_smm_changed(vcpu);
5301 }
5302
5303 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5304 unsigned long *db)
5305 {
5306 u32 dr6 = 0;
5307 int i;
5308 u32 enable, rwlen;
5309
5310 enable = dr7;
5311 rwlen = dr7 >> 16;
5312 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5313 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5314 dr6 |= (1 << i);
5315 return dr6;
5316 }
5317
5318 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5319 {
5320 struct kvm_run *kvm_run = vcpu->run;
5321
5322 /*
5323 * rflags is the old, "raw" value of the flags. The new value has
5324 * not been saved yet.
5325 *
5326 * This is correct even for TF set by the guest, because "the
5327 * processor will not generate this exception after the instruction
5328 * that sets the TF flag".
5329 */
5330 if (unlikely(rflags & X86_EFLAGS_TF)) {
5331 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5332 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5333 DR6_RTM;
5334 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5335 kvm_run->debug.arch.exception = DB_VECTOR;
5336 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5337 *r = EMULATE_USER_EXIT;
5338 } else {
5339 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5340 /*
5341 * "Certain debug exceptions may clear bit 0-3. The
5342 * remaining contents of the DR6 register are never
5343 * cleared by the processor".
5344 */
5345 vcpu->arch.dr6 &= ~15;
5346 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5347 kvm_queue_exception(vcpu, DB_VECTOR);
5348 }
5349 }
5350 }
5351
5352 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5353 {
5354 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5355 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5356 struct kvm_run *kvm_run = vcpu->run;
5357 unsigned long eip = kvm_get_linear_rip(vcpu);
5358 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5359 vcpu->arch.guest_debug_dr7,
5360 vcpu->arch.eff_db);
5361
5362 if (dr6 != 0) {
5363 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5364 kvm_run->debug.arch.pc = eip;
5365 kvm_run->debug.arch.exception = DB_VECTOR;
5366 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5367 *r = EMULATE_USER_EXIT;
5368 return true;
5369 }
5370 }
5371
5372 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5373 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5374 unsigned long eip = kvm_get_linear_rip(vcpu);
5375 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5376 vcpu->arch.dr7,
5377 vcpu->arch.db);
5378
5379 if (dr6 != 0) {
5380 vcpu->arch.dr6 &= ~15;
5381 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5382 kvm_queue_exception(vcpu, DB_VECTOR);
5383 *r = EMULATE_DONE;
5384 return true;
5385 }
5386 }
5387
5388 return false;
5389 }
5390
5391 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5392 unsigned long cr2,
5393 int emulation_type,
5394 void *insn,
5395 int insn_len)
5396 {
5397 int r;
5398 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5399 bool writeback = true;
5400 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5401
5402 /*
5403 * Clear write_fault_to_shadow_pgtable here to ensure it is
5404 * never reused.
5405 */
5406 vcpu->arch.write_fault_to_shadow_pgtable = false;
5407 kvm_clear_exception_queue(vcpu);
5408
5409 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5410 init_emulate_ctxt(vcpu);
5411
5412 /*
5413 * We will reenter on the same instruction since
5414 * we do not set complete_userspace_io. This does not
5415 * handle watchpoints yet, those would be handled in
5416 * the emulate_ops.
5417 */
5418 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5419 return r;
5420
5421 ctxt->interruptibility = 0;
5422 ctxt->have_exception = false;
5423 ctxt->exception.vector = -1;
5424 ctxt->perm_ok = false;
5425
5426 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5427
5428 r = x86_decode_insn(ctxt, insn, insn_len);
5429
5430 trace_kvm_emulate_insn_start(vcpu);
5431 ++vcpu->stat.insn_emulation;
5432 if (r != EMULATION_OK) {
5433 if (emulation_type & EMULTYPE_TRAP_UD)
5434 return EMULATE_FAIL;
5435 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5436 emulation_type))
5437 return EMULATE_DONE;
5438 if (emulation_type & EMULTYPE_SKIP)
5439 return EMULATE_FAIL;
5440 return handle_emulation_failure(vcpu);
5441 }
5442 }
5443
5444 if (emulation_type & EMULTYPE_SKIP) {
5445 kvm_rip_write(vcpu, ctxt->_eip);
5446 if (ctxt->eflags & X86_EFLAGS_RF)
5447 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5448 return EMULATE_DONE;
5449 }
5450
5451 if (retry_instruction(ctxt, cr2, emulation_type))
5452 return EMULATE_DONE;
5453
5454 /* this is needed for vmware backdoor interface to work since it
5455 changes registers values during IO operation */
5456 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5457 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5458 emulator_invalidate_register_cache(ctxt);
5459 }
5460
5461 restart:
5462 r = x86_emulate_insn(ctxt);
5463
5464 if (r == EMULATION_INTERCEPTED)
5465 return EMULATE_DONE;
5466
5467 if (r == EMULATION_FAILED) {
5468 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5469 emulation_type))
5470 return EMULATE_DONE;
5471
5472 return handle_emulation_failure(vcpu);
5473 }
5474
5475 if (ctxt->have_exception) {
5476 r = EMULATE_DONE;
5477 if (inject_emulated_exception(vcpu))
5478 return r;
5479 } else if (vcpu->arch.pio.count) {
5480 if (!vcpu->arch.pio.in) {
5481 /* FIXME: return into emulator if single-stepping. */
5482 vcpu->arch.pio.count = 0;
5483 } else {
5484 writeback = false;
5485 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5486 }
5487 r = EMULATE_USER_EXIT;
5488 } else if (vcpu->mmio_needed) {
5489 if (!vcpu->mmio_is_write)
5490 writeback = false;
5491 r = EMULATE_USER_EXIT;
5492 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5493 } else if (r == EMULATION_RESTART)
5494 goto restart;
5495 else
5496 r = EMULATE_DONE;
5497
5498 if (writeback) {
5499 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5500 toggle_interruptibility(vcpu, ctxt->interruptibility);
5501 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5502 if (vcpu->arch.hflags != ctxt->emul_flags)
5503 kvm_set_hflags(vcpu, ctxt->emul_flags);
5504 kvm_rip_write(vcpu, ctxt->eip);
5505 if (r == EMULATE_DONE)
5506 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5507 if (!ctxt->have_exception ||
5508 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5509 __kvm_set_rflags(vcpu, ctxt->eflags);
5510
5511 /*
5512 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5513 * do nothing, and it will be requested again as soon as
5514 * the shadow expires. But we still need to check here,
5515 * because POPF has no interrupt shadow.
5516 */
5517 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5518 kvm_make_request(KVM_REQ_EVENT, vcpu);
5519 } else
5520 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5521
5522 return r;
5523 }
5524 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5525
5526 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5527 {
5528 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5529 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5530 size, port, &val, 1);
5531 /* do not return to emulator after return from userspace */
5532 vcpu->arch.pio.count = 0;
5533 return ret;
5534 }
5535 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5536
5537 static void tsc_bad(void *info)
5538 {
5539 __this_cpu_write(cpu_tsc_khz, 0);
5540 }
5541
5542 static void tsc_khz_changed(void *data)
5543 {
5544 struct cpufreq_freqs *freq = data;
5545 unsigned long khz = 0;
5546
5547 if (data)
5548 khz = freq->new;
5549 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5550 khz = cpufreq_quick_get(raw_smp_processor_id());
5551 if (!khz)
5552 khz = tsc_khz;
5553 __this_cpu_write(cpu_tsc_khz, khz);
5554 }
5555
5556 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5557 void *data)
5558 {
5559 struct cpufreq_freqs *freq = data;
5560 struct kvm *kvm;
5561 struct kvm_vcpu *vcpu;
5562 int i, send_ipi = 0;
5563
5564 /*
5565 * We allow guests to temporarily run on slowing clocks,
5566 * provided we notify them after, or to run on accelerating
5567 * clocks, provided we notify them before. Thus time never
5568 * goes backwards.
5569 *
5570 * However, we have a problem. We can't atomically update
5571 * the frequency of a given CPU from this function; it is
5572 * merely a notifier, which can be called from any CPU.
5573 * Changing the TSC frequency at arbitrary points in time
5574 * requires a recomputation of local variables related to
5575 * the TSC for each VCPU. We must flag these local variables
5576 * to be updated and be sure the update takes place with the
5577 * new frequency before any guests proceed.
5578 *
5579 * Unfortunately, the combination of hotplug CPU and frequency
5580 * change creates an intractable locking scenario; the order
5581 * of when these callouts happen is undefined with respect to
5582 * CPU hotplug, and they can race with each other. As such,
5583 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5584 * undefined; you can actually have a CPU frequency change take
5585 * place in between the computation of X and the setting of the
5586 * variable. To protect against this problem, all updates of
5587 * the per_cpu tsc_khz variable are done in an interrupt
5588 * protected IPI, and all callers wishing to update the value
5589 * must wait for a synchronous IPI to complete (which is trivial
5590 * if the caller is on the CPU already). This establishes the
5591 * necessary total order on variable updates.
5592 *
5593 * Note that because a guest time update may take place
5594 * anytime after the setting of the VCPU's request bit, the
5595 * correct TSC value must be set before the request. However,
5596 * to ensure the update actually makes it to any guest which
5597 * starts running in hardware virtualization between the set
5598 * and the acquisition of the spinlock, we must also ping the
5599 * CPU after setting the request bit.
5600 *
5601 */
5602
5603 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5604 return 0;
5605 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5606 return 0;
5607
5608 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5609
5610 spin_lock(&kvm_lock);
5611 list_for_each_entry(kvm, &vm_list, vm_list) {
5612 kvm_for_each_vcpu(i, vcpu, kvm) {
5613 if (vcpu->cpu != freq->cpu)
5614 continue;
5615 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5616 if (vcpu->cpu != smp_processor_id())
5617 send_ipi = 1;
5618 }
5619 }
5620 spin_unlock(&kvm_lock);
5621
5622 if (freq->old < freq->new && send_ipi) {
5623 /*
5624 * We upscale the frequency. Must make the guest
5625 * doesn't see old kvmclock values while running with
5626 * the new frequency, otherwise we risk the guest sees
5627 * time go backwards.
5628 *
5629 * In case we update the frequency for another cpu
5630 * (which might be in guest context) send an interrupt
5631 * to kick the cpu out of guest context. Next time
5632 * guest context is entered kvmclock will be updated,
5633 * so the guest will not see stale values.
5634 */
5635 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5636 }
5637 return 0;
5638 }
5639
5640 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5641 .notifier_call = kvmclock_cpufreq_notifier
5642 };
5643
5644 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5645 unsigned long action, void *hcpu)
5646 {
5647 unsigned int cpu = (unsigned long)hcpu;
5648
5649 switch (action) {
5650 case CPU_ONLINE:
5651 case CPU_DOWN_FAILED:
5652 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5653 break;
5654 case CPU_DOWN_PREPARE:
5655 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5656 break;
5657 }
5658 return NOTIFY_OK;
5659 }
5660
5661 static struct notifier_block kvmclock_cpu_notifier_block = {
5662 .notifier_call = kvmclock_cpu_notifier,
5663 .priority = -INT_MAX
5664 };
5665
5666 static void kvm_timer_init(void)
5667 {
5668 int cpu;
5669
5670 max_tsc_khz = tsc_khz;
5671
5672 cpu_notifier_register_begin();
5673 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5674 #ifdef CONFIG_CPU_FREQ
5675 struct cpufreq_policy policy;
5676 memset(&policy, 0, sizeof(policy));
5677 cpu = get_cpu();
5678 cpufreq_get_policy(&policy, cpu);
5679 if (policy.cpuinfo.max_freq)
5680 max_tsc_khz = policy.cpuinfo.max_freq;
5681 put_cpu();
5682 #endif
5683 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5684 CPUFREQ_TRANSITION_NOTIFIER);
5685 }
5686 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5687 for_each_online_cpu(cpu)
5688 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5689
5690 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5691 cpu_notifier_register_done();
5692
5693 }
5694
5695 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5696
5697 int kvm_is_in_guest(void)
5698 {
5699 return __this_cpu_read(current_vcpu) != NULL;
5700 }
5701
5702 static int kvm_is_user_mode(void)
5703 {
5704 int user_mode = 3;
5705
5706 if (__this_cpu_read(current_vcpu))
5707 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5708
5709 return user_mode != 0;
5710 }
5711
5712 static unsigned long kvm_get_guest_ip(void)
5713 {
5714 unsigned long ip = 0;
5715
5716 if (__this_cpu_read(current_vcpu))
5717 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5718
5719 return ip;
5720 }
5721
5722 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5723 .is_in_guest = kvm_is_in_guest,
5724 .is_user_mode = kvm_is_user_mode,
5725 .get_guest_ip = kvm_get_guest_ip,
5726 };
5727
5728 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5729 {
5730 __this_cpu_write(current_vcpu, vcpu);
5731 }
5732 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5733
5734 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5735 {
5736 __this_cpu_write(current_vcpu, NULL);
5737 }
5738 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5739
5740 static void kvm_set_mmio_spte_mask(void)
5741 {
5742 u64 mask;
5743 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5744
5745 /*
5746 * Set the reserved bits and the present bit of an paging-structure
5747 * entry to generate page fault with PFER.RSV = 1.
5748 */
5749 /* Mask the reserved physical address bits. */
5750 mask = rsvd_bits(maxphyaddr, 51);
5751
5752 /* Bit 62 is always reserved for 32bit host. */
5753 mask |= 0x3ull << 62;
5754
5755 /* Set the present bit. */
5756 mask |= 1ull;
5757
5758 #ifdef CONFIG_X86_64
5759 /*
5760 * If reserved bit is not supported, clear the present bit to disable
5761 * mmio page fault.
5762 */
5763 if (maxphyaddr == 52)
5764 mask &= ~1ull;
5765 #endif
5766
5767 kvm_mmu_set_mmio_spte_mask(mask);
5768 }
5769
5770 #ifdef CONFIG_X86_64
5771 static void pvclock_gtod_update_fn(struct work_struct *work)
5772 {
5773 struct kvm *kvm;
5774
5775 struct kvm_vcpu *vcpu;
5776 int i;
5777
5778 spin_lock(&kvm_lock);
5779 list_for_each_entry(kvm, &vm_list, vm_list)
5780 kvm_for_each_vcpu(i, vcpu, kvm)
5781 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5782 atomic_set(&kvm_guest_has_master_clock, 0);
5783 spin_unlock(&kvm_lock);
5784 }
5785
5786 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5787
5788 /*
5789 * Notification about pvclock gtod data update.
5790 */
5791 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5792 void *priv)
5793 {
5794 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5795 struct timekeeper *tk = priv;
5796
5797 update_pvclock_gtod(tk);
5798
5799 /* disable master clock if host does not trust, or does not
5800 * use, TSC clocksource
5801 */
5802 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5803 atomic_read(&kvm_guest_has_master_clock) != 0)
5804 queue_work(system_long_wq, &pvclock_gtod_work);
5805
5806 return 0;
5807 }
5808
5809 static struct notifier_block pvclock_gtod_notifier = {
5810 .notifier_call = pvclock_gtod_notify,
5811 };
5812 #endif
5813
5814 int kvm_arch_init(void *opaque)
5815 {
5816 int r;
5817 struct kvm_x86_ops *ops = opaque;
5818
5819 if (kvm_x86_ops) {
5820 printk(KERN_ERR "kvm: already loaded the other module\n");
5821 r = -EEXIST;
5822 goto out;
5823 }
5824
5825 if (!ops->cpu_has_kvm_support()) {
5826 printk(KERN_ERR "kvm: no hardware support\n");
5827 r = -EOPNOTSUPP;
5828 goto out;
5829 }
5830 if (ops->disabled_by_bios()) {
5831 printk(KERN_ERR "kvm: disabled by bios\n");
5832 r = -EOPNOTSUPP;
5833 goto out;
5834 }
5835
5836 r = -ENOMEM;
5837 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5838 if (!shared_msrs) {
5839 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5840 goto out;
5841 }
5842
5843 r = kvm_mmu_module_init();
5844 if (r)
5845 goto out_free_percpu;
5846
5847 kvm_set_mmio_spte_mask();
5848
5849 kvm_x86_ops = ops;
5850
5851 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5852 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5853
5854 kvm_timer_init();
5855
5856 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5857
5858 if (cpu_has_xsave)
5859 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5860
5861 kvm_lapic_init();
5862 #ifdef CONFIG_X86_64
5863 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5864 #endif
5865
5866 return 0;
5867
5868 out_free_percpu:
5869 free_percpu(shared_msrs);
5870 out:
5871 return r;
5872 }
5873
5874 void kvm_arch_exit(void)
5875 {
5876 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5877
5878 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5879 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5880 CPUFREQ_TRANSITION_NOTIFIER);
5881 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5882 #ifdef CONFIG_X86_64
5883 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5884 #endif
5885 kvm_x86_ops = NULL;
5886 kvm_mmu_module_exit();
5887 free_percpu(shared_msrs);
5888 }
5889
5890 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5891 {
5892 ++vcpu->stat.halt_exits;
5893 if (lapic_in_kernel(vcpu)) {
5894 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5895 return 1;
5896 } else {
5897 vcpu->run->exit_reason = KVM_EXIT_HLT;
5898 return 0;
5899 }
5900 }
5901 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5902
5903 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5904 {
5905 kvm_x86_ops->skip_emulated_instruction(vcpu);
5906 return kvm_vcpu_halt(vcpu);
5907 }
5908 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5909
5910 /*
5911 * kvm_pv_kick_cpu_op: Kick a vcpu.
5912 *
5913 * @apicid - apicid of vcpu to be kicked.
5914 */
5915 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5916 {
5917 struct kvm_lapic_irq lapic_irq;
5918
5919 lapic_irq.shorthand = 0;
5920 lapic_irq.dest_mode = 0;
5921 lapic_irq.dest_id = apicid;
5922 lapic_irq.msi_redir_hint = false;
5923
5924 lapic_irq.delivery_mode = APIC_DM_REMRD;
5925 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5926 }
5927
5928 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5929 {
5930 vcpu->arch.apicv_active = false;
5931 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5932 }
5933
5934 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5935 {
5936 unsigned long nr, a0, a1, a2, a3, ret;
5937 int op_64_bit, r = 1;
5938
5939 kvm_x86_ops->skip_emulated_instruction(vcpu);
5940
5941 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5942 return kvm_hv_hypercall(vcpu);
5943
5944 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5945 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5946 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5947 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5948 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5949
5950 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5951
5952 op_64_bit = is_64_bit_mode(vcpu);
5953 if (!op_64_bit) {
5954 nr &= 0xFFFFFFFF;
5955 a0 &= 0xFFFFFFFF;
5956 a1 &= 0xFFFFFFFF;
5957 a2 &= 0xFFFFFFFF;
5958 a3 &= 0xFFFFFFFF;
5959 }
5960
5961 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5962 ret = -KVM_EPERM;
5963 goto out;
5964 }
5965
5966 switch (nr) {
5967 case KVM_HC_VAPIC_POLL_IRQ:
5968 ret = 0;
5969 break;
5970 case KVM_HC_KICK_CPU:
5971 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5972 ret = 0;
5973 break;
5974 default:
5975 ret = -KVM_ENOSYS;
5976 break;
5977 }
5978 out:
5979 if (!op_64_bit)
5980 ret = (u32)ret;
5981 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5982 ++vcpu->stat.hypercalls;
5983 return r;
5984 }
5985 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5986
5987 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5988 {
5989 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5990 char instruction[3];
5991 unsigned long rip = kvm_rip_read(vcpu);
5992
5993 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5994
5995 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5996 }
5997
5998 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5999 {
6000 return vcpu->run->request_interrupt_window &&
6001 likely(!pic_in_kernel(vcpu->kvm));
6002 }
6003
6004 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6005 {
6006 struct kvm_run *kvm_run = vcpu->run;
6007
6008 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6009 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6010 kvm_run->cr8 = kvm_get_cr8(vcpu);
6011 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6012 kvm_run->ready_for_interrupt_injection =
6013 pic_in_kernel(vcpu->kvm) ||
6014 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6015 }
6016
6017 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6018 {
6019 int max_irr, tpr;
6020
6021 if (!kvm_x86_ops->update_cr8_intercept)
6022 return;
6023
6024 if (!lapic_in_kernel(vcpu))
6025 return;
6026
6027 if (vcpu->arch.apicv_active)
6028 return;
6029
6030 if (!vcpu->arch.apic->vapic_addr)
6031 max_irr = kvm_lapic_find_highest_irr(vcpu);
6032 else
6033 max_irr = -1;
6034
6035 if (max_irr != -1)
6036 max_irr >>= 4;
6037
6038 tpr = kvm_lapic_get_cr8(vcpu);
6039
6040 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6041 }
6042
6043 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6044 {
6045 int r;
6046
6047 /* try to reinject previous events if any */
6048 if (vcpu->arch.exception.pending) {
6049 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6050 vcpu->arch.exception.has_error_code,
6051 vcpu->arch.exception.error_code);
6052
6053 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6054 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6055 X86_EFLAGS_RF);
6056
6057 if (vcpu->arch.exception.nr == DB_VECTOR &&
6058 (vcpu->arch.dr7 & DR7_GD)) {
6059 vcpu->arch.dr7 &= ~DR7_GD;
6060 kvm_update_dr7(vcpu);
6061 }
6062
6063 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6064 vcpu->arch.exception.has_error_code,
6065 vcpu->arch.exception.error_code,
6066 vcpu->arch.exception.reinject);
6067 return 0;
6068 }
6069
6070 if (vcpu->arch.nmi_injected) {
6071 kvm_x86_ops->set_nmi(vcpu);
6072 return 0;
6073 }
6074
6075 if (vcpu->arch.interrupt.pending) {
6076 kvm_x86_ops->set_irq(vcpu);
6077 return 0;
6078 }
6079
6080 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6081 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6082 if (r != 0)
6083 return r;
6084 }
6085
6086 /* try to inject new event if pending */
6087 if (vcpu->arch.nmi_pending) {
6088 if (kvm_x86_ops->nmi_allowed(vcpu)) {
6089 --vcpu->arch.nmi_pending;
6090 vcpu->arch.nmi_injected = true;
6091 kvm_x86_ops->set_nmi(vcpu);
6092 }
6093 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6094 /*
6095 * Because interrupts can be injected asynchronously, we are
6096 * calling check_nested_events again here to avoid a race condition.
6097 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6098 * proposal and current concerns. Perhaps we should be setting
6099 * KVM_REQ_EVENT only on certain events and not unconditionally?
6100 */
6101 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6102 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6103 if (r != 0)
6104 return r;
6105 }
6106 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6107 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6108 false);
6109 kvm_x86_ops->set_irq(vcpu);
6110 }
6111 }
6112 return 0;
6113 }
6114
6115 static void process_nmi(struct kvm_vcpu *vcpu)
6116 {
6117 unsigned limit = 2;
6118
6119 /*
6120 * x86 is limited to one NMI running, and one NMI pending after it.
6121 * If an NMI is already in progress, limit further NMIs to just one.
6122 * Otherwise, allow two (and we'll inject the first one immediately).
6123 */
6124 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6125 limit = 1;
6126
6127 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6128 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6129 kvm_make_request(KVM_REQ_EVENT, vcpu);
6130 }
6131
6132 #define put_smstate(type, buf, offset, val) \
6133 *(type *)((buf) + (offset) - 0x7e00) = val
6134
6135 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6136 {
6137 u32 flags = 0;
6138 flags |= seg->g << 23;
6139 flags |= seg->db << 22;
6140 flags |= seg->l << 21;
6141 flags |= seg->avl << 20;
6142 flags |= seg->present << 15;
6143 flags |= seg->dpl << 13;
6144 flags |= seg->s << 12;
6145 flags |= seg->type << 8;
6146 return flags;
6147 }
6148
6149 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6150 {
6151 struct kvm_segment seg;
6152 int offset;
6153
6154 kvm_get_segment(vcpu, &seg, n);
6155 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6156
6157 if (n < 3)
6158 offset = 0x7f84 + n * 12;
6159 else
6160 offset = 0x7f2c + (n - 3) * 12;
6161
6162 put_smstate(u32, buf, offset + 8, seg.base);
6163 put_smstate(u32, buf, offset + 4, seg.limit);
6164 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6165 }
6166
6167 #ifdef CONFIG_X86_64
6168 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6169 {
6170 struct kvm_segment seg;
6171 int offset;
6172 u16 flags;
6173
6174 kvm_get_segment(vcpu, &seg, n);
6175 offset = 0x7e00 + n * 16;
6176
6177 flags = process_smi_get_segment_flags(&seg) >> 8;
6178 put_smstate(u16, buf, offset, seg.selector);
6179 put_smstate(u16, buf, offset + 2, flags);
6180 put_smstate(u32, buf, offset + 4, seg.limit);
6181 put_smstate(u64, buf, offset + 8, seg.base);
6182 }
6183 #endif
6184
6185 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6186 {
6187 struct desc_ptr dt;
6188 struct kvm_segment seg;
6189 unsigned long val;
6190 int i;
6191
6192 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6193 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6194 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6195 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6196
6197 for (i = 0; i < 8; i++)
6198 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6199
6200 kvm_get_dr(vcpu, 6, &val);
6201 put_smstate(u32, buf, 0x7fcc, (u32)val);
6202 kvm_get_dr(vcpu, 7, &val);
6203 put_smstate(u32, buf, 0x7fc8, (u32)val);
6204
6205 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6206 put_smstate(u32, buf, 0x7fc4, seg.selector);
6207 put_smstate(u32, buf, 0x7f64, seg.base);
6208 put_smstate(u32, buf, 0x7f60, seg.limit);
6209 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6210
6211 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6212 put_smstate(u32, buf, 0x7fc0, seg.selector);
6213 put_smstate(u32, buf, 0x7f80, seg.base);
6214 put_smstate(u32, buf, 0x7f7c, seg.limit);
6215 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6216
6217 kvm_x86_ops->get_gdt(vcpu, &dt);
6218 put_smstate(u32, buf, 0x7f74, dt.address);
6219 put_smstate(u32, buf, 0x7f70, dt.size);
6220
6221 kvm_x86_ops->get_idt(vcpu, &dt);
6222 put_smstate(u32, buf, 0x7f58, dt.address);
6223 put_smstate(u32, buf, 0x7f54, dt.size);
6224
6225 for (i = 0; i < 6; i++)
6226 process_smi_save_seg_32(vcpu, buf, i);
6227
6228 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6229
6230 /* revision id */
6231 put_smstate(u32, buf, 0x7efc, 0x00020000);
6232 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6233 }
6234
6235 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6236 {
6237 #ifdef CONFIG_X86_64
6238 struct desc_ptr dt;
6239 struct kvm_segment seg;
6240 unsigned long val;
6241 int i;
6242
6243 for (i = 0; i < 16; i++)
6244 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6245
6246 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6247 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6248
6249 kvm_get_dr(vcpu, 6, &val);
6250 put_smstate(u64, buf, 0x7f68, val);
6251 kvm_get_dr(vcpu, 7, &val);
6252 put_smstate(u64, buf, 0x7f60, val);
6253
6254 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6255 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6256 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6257
6258 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6259
6260 /* revision id */
6261 put_smstate(u32, buf, 0x7efc, 0x00020064);
6262
6263 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6264
6265 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6266 put_smstate(u16, buf, 0x7e90, seg.selector);
6267 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6268 put_smstate(u32, buf, 0x7e94, seg.limit);
6269 put_smstate(u64, buf, 0x7e98, seg.base);
6270
6271 kvm_x86_ops->get_idt(vcpu, &dt);
6272 put_smstate(u32, buf, 0x7e84, dt.size);
6273 put_smstate(u64, buf, 0x7e88, dt.address);
6274
6275 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6276 put_smstate(u16, buf, 0x7e70, seg.selector);
6277 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6278 put_smstate(u32, buf, 0x7e74, seg.limit);
6279 put_smstate(u64, buf, 0x7e78, seg.base);
6280
6281 kvm_x86_ops->get_gdt(vcpu, &dt);
6282 put_smstate(u32, buf, 0x7e64, dt.size);
6283 put_smstate(u64, buf, 0x7e68, dt.address);
6284
6285 for (i = 0; i < 6; i++)
6286 process_smi_save_seg_64(vcpu, buf, i);
6287 #else
6288 WARN_ON_ONCE(1);
6289 #endif
6290 }
6291
6292 static void process_smi(struct kvm_vcpu *vcpu)
6293 {
6294 struct kvm_segment cs, ds;
6295 struct desc_ptr dt;
6296 char buf[512];
6297 u32 cr0;
6298
6299 if (is_smm(vcpu)) {
6300 vcpu->arch.smi_pending = true;
6301 return;
6302 }
6303
6304 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6305 vcpu->arch.hflags |= HF_SMM_MASK;
6306 memset(buf, 0, 512);
6307 if (guest_cpuid_has_longmode(vcpu))
6308 process_smi_save_state_64(vcpu, buf);
6309 else
6310 process_smi_save_state_32(vcpu, buf);
6311
6312 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6313
6314 if (kvm_x86_ops->get_nmi_mask(vcpu))
6315 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6316 else
6317 kvm_x86_ops->set_nmi_mask(vcpu, true);
6318
6319 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6320 kvm_rip_write(vcpu, 0x8000);
6321
6322 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6323 kvm_x86_ops->set_cr0(vcpu, cr0);
6324 vcpu->arch.cr0 = cr0;
6325
6326 kvm_x86_ops->set_cr4(vcpu, 0);
6327
6328 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6329 dt.address = dt.size = 0;
6330 kvm_x86_ops->set_idt(vcpu, &dt);
6331
6332 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6333
6334 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6335 cs.base = vcpu->arch.smbase;
6336
6337 ds.selector = 0;
6338 ds.base = 0;
6339
6340 cs.limit = ds.limit = 0xffffffff;
6341 cs.type = ds.type = 0x3;
6342 cs.dpl = ds.dpl = 0;
6343 cs.db = ds.db = 0;
6344 cs.s = ds.s = 1;
6345 cs.l = ds.l = 0;
6346 cs.g = ds.g = 1;
6347 cs.avl = ds.avl = 0;
6348 cs.present = ds.present = 1;
6349 cs.unusable = ds.unusable = 0;
6350 cs.padding = ds.padding = 0;
6351
6352 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6353 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6354 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6355 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6356 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6357 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6358
6359 if (guest_cpuid_has_longmode(vcpu))
6360 kvm_x86_ops->set_efer(vcpu, 0);
6361
6362 kvm_update_cpuid(vcpu);
6363 kvm_mmu_reset_context(vcpu);
6364 }
6365
6366 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6367 {
6368 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6369 }
6370
6371 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6372 {
6373 u64 eoi_exit_bitmap[4];
6374
6375 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6376 return;
6377
6378 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6379
6380 if (irqchip_split(vcpu->kvm))
6381 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6382 else {
6383 if (vcpu->arch.apicv_active)
6384 kvm_x86_ops->sync_pir_to_irr(vcpu);
6385 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6386 }
6387 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6388 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6389 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6390 }
6391
6392 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6393 {
6394 ++vcpu->stat.tlb_flush;
6395 kvm_x86_ops->tlb_flush(vcpu);
6396 }
6397
6398 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6399 {
6400 struct page *page = NULL;
6401
6402 if (!lapic_in_kernel(vcpu))
6403 return;
6404
6405 if (!kvm_x86_ops->set_apic_access_page_addr)
6406 return;
6407
6408 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6409 if (is_error_page(page))
6410 return;
6411 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6412
6413 /*
6414 * Do not pin apic access page in memory, the MMU notifier
6415 * will call us again if it is migrated or swapped out.
6416 */
6417 put_page(page);
6418 }
6419 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6420
6421 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6422 unsigned long address)
6423 {
6424 /*
6425 * The physical address of apic access page is stored in the VMCS.
6426 * Update it when it becomes invalid.
6427 */
6428 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6429 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6430 }
6431
6432 /*
6433 * Returns 1 to let vcpu_run() continue the guest execution loop without
6434 * exiting to the userspace. Otherwise, the value will be returned to the
6435 * userspace.
6436 */
6437 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6438 {
6439 int r;
6440 bool req_int_win =
6441 dm_request_for_irq_injection(vcpu) &&
6442 kvm_cpu_accept_dm_intr(vcpu);
6443
6444 bool req_immediate_exit = false;
6445
6446 if (vcpu->requests) {
6447 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6448 kvm_mmu_unload(vcpu);
6449 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6450 __kvm_migrate_timers(vcpu);
6451 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6452 kvm_gen_update_masterclock(vcpu->kvm);
6453 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6454 kvm_gen_kvmclock_update(vcpu);
6455 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6456 r = kvm_guest_time_update(vcpu);
6457 if (unlikely(r))
6458 goto out;
6459 }
6460 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6461 kvm_mmu_sync_roots(vcpu);
6462 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6463 kvm_vcpu_flush_tlb(vcpu);
6464 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6465 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6466 r = 0;
6467 goto out;
6468 }
6469 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6470 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6471 r = 0;
6472 goto out;
6473 }
6474 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6475 vcpu->fpu_active = 0;
6476 kvm_x86_ops->fpu_deactivate(vcpu);
6477 }
6478 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6479 /* Page is swapped out. Do synthetic halt */
6480 vcpu->arch.apf.halted = true;
6481 r = 1;
6482 goto out;
6483 }
6484 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6485 record_steal_time(vcpu);
6486 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6487 process_smi(vcpu);
6488 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6489 process_nmi(vcpu);
6490 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6491 kvm_pmu_handle_event(vcpu);
6492 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6493 kvm_pmu_deliver_pmi(vcpu);
6494 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6495 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6496 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6497 vcpu->arch.ioapic_handled_vectors)) {
6498 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6499 vcpu->run->eoi.vector =
6500 vcpu->arch.pending_ioapic_eoi;
6501 r = 0;
6502 goto out;
6503 }
6504 }
6505 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6506 vcpu_scan_ioapic(vcpu);
6507 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6508 kvm_vcpu_reload_apic_access_page(vcpu);
6509 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6510 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6511 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6512 r = 0;
6513 goto out;
6514 }
6515 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6516 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6517 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6518 r = 0;
6519 goto out;
6520 }
6521 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6522 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6523 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6524 r = 0;
6525 goto out;
6526 }
6527
6528 /*
6529 * KVM_REQ_HV_STIMER has to be processed after
6530 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6531 * depend on the guest clock being up-to-date
6532 */
6533 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6534 kvm_hv_process_stimers(vcpu);
6535 }
6536
6537 /*
6538 * KVM_REQ_EVENT is not set when posted interrupts are set by
6539 * VT-d hardware, so we have to update RVI unconditionally.
6540 */
6541 if (kvm_lapic_enabled(vcpu)) {
6542 /*
6543 * Update architecture specific hints for APIC
6544 * virtual interrupt delivery.
6545 */
6546 if (vcpu->arch.apicv_active)
6547 kvm_x86_ops->hwapic_irr_update(vcpu,
6548 kvm_lapic_find_highest_irr(vcpu));
6549 }
6550
6551 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6552 kvm_apic_accept_events(vcpu);
6553 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6554 r = 1;
6555 goto out;
6556 }
6557
6558 if (inject_pending_event(vcpu, req_int_win) != 0)
6559 req_immediate_exit = true;
6560 /* enable NMI/IRQ window open exits if needed */
6561 else if (vcpu->arch.nmi_pending)
6562 kvm_x86_ops->enable_nmi_window(vcpu);
6563 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6564 kvm_x86_ops->enable_irq_window(vcpu);
6565
6566 if (kvm_lapic_enabled(vcpu)) {
6567 update_cr8_intercept(vcpu);
6568 kvm_lapic_sync_to_vapic(vcpu);
6569 }
6570 }
6571
6572 r = kvm_mmu_reload(vcpu);
6573 if (unlikely(r)) {
6574 goto cancel_injection;
6575 }
6576
6577 preempt_disable();
6578
6579 kvm_x86_ops->prepare_guest_switch(vcpu);
6580 if (vcpu->fpu_active)
6581 kvm_load_guest_fpu(vcpu);
6582 kvm_load_guest_xcr0(vcpu);
6583
6584 vcpu->mode = IN_GUEST_MODE;
6585
6586 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6587
6588 /* We should set ->mode before check ->requests,
6589 * see the comment in make_all_cpus_request.
6590 */
6591 smp_mb__after_srcu_read_unlock();
6592
6593 local_irq_disable();
6594
6595 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6596 || need_resched() || signal_pending(current)) {
6597 vcpu->mode = OUTSIDE_GUEST_MODE;
6598 smp_wmb();
6599 local_irq_enable();
6600 preempt_enable();
6601 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6602 r = 1;
6603 goto cancel_injection;
6604 }
6605
6606 if (req_immediate_exit)
6607 smp_send_reschedule(vcpu->cpu);
6608
6609 trace_kvm_entry(vcpu->vcpu_id);
6610 wait_lapic_expire(vcpu);
6611 __kvm_guest_enter();
6612
6613 if (unlikely(vcpu->arch.switch_db_regs)) {
6614 set_debugreg(0, 7);
6615 set_debugreg(vcpu->arch.eff_db[0], 0);
6616 set_debugreg(vcpu->arch.eff_db[1], 1);
6617 set_debugreg(vcpu->arch.eff_db[2], 2);
6618 set_debugreg(vcpu->arch.eff_db[3], 3);
6619 set_debugreg(vcpu->arch.dr6, 6);
6620 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6621 }
6622
6623 kvm_x86_ops->run(vcpu);
6624
6625 /*
6626 * Do this here before restoring debug registers on the host. And
6627 * since we do this before handling the vmexit, a DR access vmexit
6628 * can (a) read the correct value of the debug registers, (b) set
6629 * KVM_DEBUGREG_WONT_EXIT again.
6630 */
6631 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6632 int i;
6633
6634 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6635 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6636 for (i = 0; i < KVM_NR_DB_REGS; i++)
6637 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6638 }
6639
6640 /*
6641 * If the guest has used debug registers, at least dr7
6642 * will be disabled while returning to the host.
6643 * If we don't have active breakpoints in the host, we don't
6644 * care about the messed up debug address registers. But if
6645 * we have some of them active, restore the old state.
6646 */
6647 if (hw_breakpoint_active())
6648 hw_breakpoint_restore();
6649
6650 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6651
6652 vcpu->mode = OUTSIDE_GUEST_MODE;
6653 smp_wmb();
6654
6655 /* Interrupt is enabled by handle_external_intr() */
6656 kvm_x86_ops->handle_external_intr(vcpu);
6657
6658 ++vcpu->stat.exits;
6659
6660 /*
6661 * We must have an instruction between local_irq_enable() and
6662 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6663 * the interrupt shadow. The stat.exits increment will do nicely.
6664 * But we need to prevent reordering, hence this barrier():
6665 */
6666 barrier();
6667
6668 kvm_guest_exit();
6669
6670 preempt_enable();
6671
6672 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6673
6674 /*
6675 * Profile KVM exit RIPs:
6676 */
6677 if (unlikely(prof_on == KVM_PROFILING)) {
6678 unsigned long rip = kvm_rip_read(vcpu);
6679 profile_hit(KVM_PROFILING, (void *)rip);
6680 }
6681
6682 if (unlikely(vcpu->arch.tsc_always_catchup))
6683 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6684
6685 if (vcpu->arch.apic_attention)
6686 kvm_lapic_sync_from_vapic(vcpu);
6687
6688 r = kvm_x86_ops->handle_exit(vcpu);
6689 return r;
6690
6691 cancel_injection:
6692 kvm_x86_ops->cancel_injection(vcpu);
6693 if (unlikely(vcpu->arch.apic_attention))
6694 kvm_lapic_sync_from_vapic(vcpu);
6695 out:
6696 return r;
6697 }
6698
6699 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6700 {
6701 if (!kvm_arch_vcpu_runnable(vcpu) &&
6702 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6703 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6704 kvm_vcpu_block(vcpu);
6705 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6706
6707 if (kvm_x86_ops->post_block)
6708 kvm_x86_ops->post_block(vcpu);
6709
6710 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6711 return 1;
6712 }
6713
6714 kvm_apic_accept_events(vcpu);
6715 switch(vcpu->arch.mp_state) {
6716 case KVM_MP_STATE_HALTED:
6717 vcpu->arch.pv.pv_unhalted = false;
6718 vcpu->arch.mp_state =
6719 KVM_MP_STATE_RUNNABLE;
6720 case KVM_MP_STATE_RUNNABLE:
6721 vcpu->arch.apf.halted = false;
6722 break;
6723 case KVM_MP_STATE_INIT_RECEIVED:
6724 break;
6725 default:
6726 return -EINTR;
6727 break;
6728 }
6729 return 1;
6730 }
6731
6732 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6733 {
6734 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6735 !vcpu->arch.apf.halted);
6736 }
6737
6738 static int vcpu_run(struct kvm_vcpu *vcpu)
6739 {
6740 int r;
6741 struct kvm *kvm = vcpu->kvm;
6742
6743 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6744
6745 for (;;) {
6746 if (kvm_vcpu_running(vcpu)) {
6747 r = vcpu_enter_guest(vcpu);
6748 } else {
6749 r = vcpu_block(kvm, vcpu);
6750 }
6751
6752 if (r <= 0)
6753 break;
6754
6755 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6756 if (kvm_cpu_has_pending_timer(vcpu))
6757 kvm_inject_pending_timer_irqs(vcpu);
6758
6759 if (dm_request_for_irq_injection(vcpu) &&
6760 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6761 r = 0;
6762 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6763 ++vcpu->stat.request_irq_exits;
6764 break;
6765 }
6766
6767 kvm_check_async_pf_completion(vcpu);
6768
6769 if (signal_pending(current)) {
6770 r = -EINTR;
6771 vcpu->run->exit_reason = KVM_EXIT_INTR;
6772 ++vcpu->stat.signal_exits;
6773 break;
6774 }
6775 if (need_resched()) {
6776 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6777 cond_resched();
6778 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6779 }
6780 }
6781
6782 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6783
6784 return r;
6785 }
6786
6787 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6788 {
6789 int r;
6790 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6791 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6792 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6793 if (r != EMULATE_DONE)
6794 return 0;
6795 return 1;
6796 }
6797
6798 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6799 {
6800 BUG_ON(!vcpu->arch.pio.count);
6801
6802 return complete_emulated_io(vcpu);
6803 }
6804
6805 /*
6806 * Implements the following, as a state machine:
6807 *
6808 * read:
6809 * for each fragment
6810 * for each mmio piece in the fragment
6811 * write gpa, len
6812 * exit
6813 * copy data
6814 * execute insn
6815 *
6816 * write:
6817 * for each fragment
6818 * for each mmio piece in the fragment
6819 * write gpa, len
6820 * copy data
6821 * exit
6822 */
6823 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6824 {
6825 struct kvm_run *run = vcpu->run;
6826 struct kvm_mmio_fragment *frag;
6827 unsigned len;
6828
6829 BUG_ON(!vcpu->mmio_needed);
6830
6831 /* Complete previous fragment */
6832 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6833 len = min(8u, frag->len);
6834 if (!vcpu->mmio_is_write)
6835 memcpy(frag->data, run->mmio.data, len);
6836
6837 if (frag->len <= 8) {
6838 /* Switch to the next fragment. */
6839 frag++;
6840 vcpu->mmio_cur_fragment++;
6841 } else {
6842 /* Go forward to the next mmio piece. */
6843 frag->data += len;
6844 frag->gpa += len;
6845 frag->len -= len;
6846 }
6847
6848 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6849 vcpu->mmio_needed = 0;
6850
6851 /* FIXME: return into emulator if single-stepping. */
6852 if (vcpu->mmio_is_write)
6853 return 1;
6854 vcpu->mmio_read_completed = 1;
6855 return complete_emulated_io(vcpu);
6856 }
6857
6858 run->exit_reason = KVM_EXIT_MMIO;
6859 run->mmio.phys_addr = frag->gpa;
6860 if (vcpu->mmio_is_write)
6861 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6862 run->mmio.len = min(8u, frag->len);
6863 run->mmio.is_write = vcpu->mmio_is_write;
6864 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6865 return 0;
6866 }
6867
6868
6869 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6870 {
6871 struct fpu *fpu = &current->thread.fpu;
6872 int r;
6873 sigset_t sigsaved;
6874
6875 fpu__activate_curr(fpu);
6876
6877 if (vcpu->sigset_active)
6878 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6879
6880 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6881 kvm_vcpu_block(vcpu);
6882 kvm_apic_accept_events(vcpu);
6883 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6884 r = -EAGAIN;
6885 goto out;
6886 }
6887
6888 /* re-sync apic's tpr */
6889 if (!lapic_in_kernel(vcpu)) {
6890 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6891 r = -EINVAL;
6892 goto out;
6893 }
6894 }
6895
6896 if (unlikely(vcpu->arch.complete_userspace_io)) {
6897 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6898 vcpu->arch.complete_userspace_io = NULL;
6899 r = cui(vcpu);
6900 if (r <= 0)
6901 goto out;
6902 } else
6903 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6904
6905 r = vcpu_run(vcpu);
6906
6907 out:
6908 post_kvm_run_save(vcpu);
6909 if (vcpu->sigset_active)
6910 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6911
6912 return r;
6913 }
6914
6915 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6916 {
6917 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6918 /*
6919 * We are here if userspace calls get_regs() in the middle of
6920 * instruction emulation. Registers state needs to be copied
6921 * back from emulation context to vcpu. Userspace shouldn't do
6922 * that usually, but some bad designed PV devices (vmware
6923 * backdoor interface) need this to work
6924 */
6925 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6926 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6927 }
6928 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6929 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6930 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6931 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6932 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6933 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6934 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6935 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6936 #ifdef CONFIG_X86_64
6937 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6938 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6939 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6940 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6941 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6942 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6943 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6944 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6945 #endif
6946
6947 regs->rip = kvm_rip_read(vcpu);
6948 regs->rflags = kvm_get_rflags(vcpu);
6949
6950 return 0;
6951 }
6952
6953 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6954 {
6955 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6956 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6957
6958 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6959 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6960 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6961 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6962 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6963 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6964 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6965 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6966 #ifdef CONFIG_X86_64
6967 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6968 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6969 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6970 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6971 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6972 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6973 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6974 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6975 #endif
6976
6977 kvm_rip_write(vcpu, regs->rip);
6978 kvm_set_rflags(vcpu, regs->rflags);
6979
6980 vcpu->arch.exception.pending = false;
6981
6982 kvm_make_request(KVM_REQ_EVENT, vcpu);
6983
6984 return 0;
6985 }
6986
6987 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6988 {
6989 struct kvm_segment cs;
6990
6991 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6992 *db = cs.db;
6993 *l = cs.l;
6994 }
6995 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6996
6997 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6998 struct kvm_sregs *sregs)
6999 {
7000 struct desc_ptr dt;
7001
7002 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7003 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7004 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7005 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7006 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7007 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7008
7009 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7010 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7011
7012 kvm_x86_ops->get_idt(vcpu, &dt);
7013 sregs->idt.limit = dt.size;
7014 sregs->idt.base = dt.address;
7015 kvm_x86_ops->get_gdt(vcpu, &dt);
7016 sregs->gdt.limit = dt.size;
7017 sregs->gdt.base = dt.address;
7018
7019 sregs->cr0 = kvm_read_cr0(vcpu);
7020 sregs->cr2 = vcpu->arch.cr2;
7021 sregs->cr3 = kvm_read_cr3(vcpu);
7022 sregs->cr4 = kvm_read_cr4(vcpu);
7023 sregs->cr8 = kvm_get_cr8(vcpu);
7024 sregs->efer = vcpu->arch.efer;
7025 sregs->apic_base = kvm_get_apic_base(vcpu);
7026
7027 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7028
7029 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7030 set_bit(vcpu->arch.interrupt.nr,
7031 (unsigned long *)sregs->interrupt_bitmap);
7032
7033 return 0;
7034 }
7035
7036 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7037 struct kvm_mp_state *mp_state)
7038 {
7039 kvm_apic_accept_events(vcpu);
7040 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7041 vcpu->arch.pv.pv_unhalted)
7042 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7043 else
7044 mp_state->mp_state = vcpu->arch.mp_state;
7045
7046 return 0;
7047 }
7048
7049 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7050 struct kvm_mp_state *mp_state)
7051 {
7052 if (!lapic_in_kernel(vcpu) &&
7053 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7054 return -EINVAL;
7055
7056 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7057 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7058 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7059 } else
7060 vcpu->arch.mp_state = mp_state->mp_state;
7061 kvm_make_request(KVM_REQ_EVENT, vcpu);
7062 return 0;
7063 }
7064
7065 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7066 int reason, bool has_error_code, u32 error_code)
7067 {
7068 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7069 int ret;
7070
7071 init_emulate_ctxt(vcpu);
7072
7073 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7074 has_error_code, error_code);
7075
7076 if (ret)
7077 return EMULATE_FAIL;
7078
7079 kvm_rip_write(vcpu, ctxt->eip);
7080 kvm_set_rflags(vcpu, ctxt->eflags);
7081 kvm_make_request(KVM_REQ_EVENT, vcpu);
7082 return EMULATE_DONE;
7083 }
7084 EXPORT_SYMBOL_GPL(kvm_task_switch);
7085
7086 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7087 struct kvm_sregs *sregs)
7088 {
7089 struct msr_data apic_base_msr;
7090 int mmu_reset_needed = 0;
7091 int pending_vec, max_bits, idx;
7092 struct desc_ptr dt;
7093
7094 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7095 return -EINVAL;
7096
7097 dt.size = sregs->idt.limit;
7098 dt.address = sregs->idt.base;
7099 kvm_x86_ops->set_idt(vcpu, &dt);
7100 dt.size = sregs->gdt.limit;
7101 dt.address = sregs->gdt.base;
7102 kvm_x86_ops->set_gdt(vcpu, &dt);
7103
7104 vcpu->arch.cr2 = sregs->cr2;
7105 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7106 vcpu->arch.cr3 = sregs->cr3;
7107 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7108
7109 kvm_set_cr8(vcpu, sregs->cr8);
7110
7111 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7112 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7113 apic_base_msr.data = sregs->apic_base;
7114 apic_base_msr.host_initiated = true;
7115 kvm_set_apic_base(vcpu, &apic_base_msr);
7116
7117 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7118 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7119 vcpu->arch.cr0 = sregs->cr0;
7120
7121 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7122 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7123 if (sregs->cr4 & X86_CR4_OSXSAVE)
7124 kvm_update_cpuid(vcpu);
7125
7126 idx = srcu_read_lock(&vcpu->kvm->srcu);
7127 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7128 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7129 mmu_reset_needed = 1;
7130 }
7131 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7132
7133 if (mmu_reset_needed)
7134 kvm_mmu_reset_context(vcpu);
7135
7136 max_bits = KVM_NR_INTERRUPTS;
7137 pending_vec = find_first_bit(
7138 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7139 if (pending_vec < max_bits) {
7140 kvm_queue_interrupt(vcpu, pending_vec, false);
7141 pr_debug("Set back pending irq %d\n", pending_vec);
7142 }
7143
7144 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7145 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7146 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7147 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7148 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7149 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7150
7151 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7152 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7153
7154 update_cr8_intercept(vcpu);
7155
7156 /* Older userspace won't unhalt the vcpu on reset. */
7157 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7158 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7159 !is_protmode(vcpu))
7160 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7161
7162 kvm_make_request(KVM_REQ_EVENT, vcpu);
7163
7164 return 0;
7165 }
7166
7167 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7168 struct kvm_guest_debug *dbg)
7169 {
7170 unsigned long rflags;
7171 int i, r;
7172
7173 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7174 r = -EBUSY;
7175 if (vcpu->arch.exception.pending)
7176 goto out;
7177 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7178 kvm_queue_exception(vcpu, DB_VECTOR);
7179 else
7180 kvm_queue_exception(vcpu, BP_VECTOR);
7181 }
7182
7183 /*
7184 * Read rflags as long as potentially injected trace flags are still
7185 * filtered out.
7186 */
7187 rflags = kvm_get_rflags(vcpu);
7188
7189 vcpu->guest_debug = dbg->control;
7190 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7191 vcpu->guest_debug = 0;
7192
7193 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7194 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7195 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7196 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7197 } else {
7198 for (i = 0; i < KVM_NR_DB_REGS; i++)
7199 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7200 }
7201 kvm_update_dr7(vcpu);
7202
7203 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7204 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7205 get_segment_base(vcpu, VCPU_SREG_CS);
7206
7207 /*
7208 * Trigger an rflags update that will inject or remove the trace
7209 * flags.
7210 */
7211 kvm_set_rflags(vcpu, rflags);
7212
7213 kvm_x86_ops->update_bp_intercept(vcpu);
7214
7215 r = 0;
7216
7217 out:
7218
7219 return r;
7220 }
7221
7222 /*
7223 * Translate a guest virtual address to a guest physical address.
7224 */
7225 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7226 struct kvm_translation *tr)
7227 {
7228 unsigned long vaddr = tr->linear_address;
7229 gpa_t gpa;
7230 int idx;
7231
7232 idx = srcu_read_lock(&vcpu->kvm->srcu);
7233 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7234 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7235 tr->physical_address = gpa;
7236 tr->valid = gpa != UNMAPPED_GVA;
7237 tr->writeable = 1;
7238 tr->usermode = 0;
7239
7240 return 0;
7241 }
7242
7243 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7244 {
7245 struct fxregs_state *fxsave =
7246 &vcpu->arch.guest_fpu.state.fxsave;
7247
7248 memcpy(fpu->fpr, fxsave->st_space, 128);
7249 fpu->fcw = fxsave->cwd;
7250 fpu->fsw = fxsave->swd;
7251 fpu->ftwx = fxsave->twd;
7252 fpu->last_opcode = fxsave->fop;
7253 fpu->last_ip = fxsave->rip;
7254 fpu->last_dp = fxsave->rdp;
7255 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7256
7257 return 0;
7258 }
7259
7260 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7261 {
7262 struct fxregs_state *fxsave =
7263 &vcpu->arch.guest_fpu.state.fxsave;
7264
7265 memcpy(fxsave->st_space, fpu->fpr, 128);
7266 fxsave->cwd = fpu->fcw;
7267 fxsave->swd = fpu->fsw;
7268 fxsave->twd = fpu->ftwx;
7269 fxsave->fop = fpu->last_opcode;
7270 fxsave->rip = fpu->last_ip;
7271 fxsave->rdp = fpu->last_dp;
7272 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7273
7274 return 0;
7275 }
7276
7277 static void fx_init(struct kvm_vcpu *vcpu)
7278 {
7279 fpstate_init(&vcpu->arch.guest_fpu.state);
7280 if (cpu_has_xsaves)
7281 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7282 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7283
7284 /*
7285 * Ensure guest xcr0 is valid for loading
7286 */
7287 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7288
7289 vcpu->arch.cr0 |= X86_CR0_ET;
7290 }
7291
7292 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7293 {
7294 if (vcpu->guest_fpu_loaded)
7295 return;
7296
7297 /*
7298 * Restore all possible states in the guest,
7299 * and assume host would use all available bits.
7300 * Guest xcr0 would be loaded later.
7301 */
7302 kvm_put_guest_xcr0(vcpu);
7303 vcpu->guest_fpu_loaded = 1;
7304 __kernel_fpu_begin();
7305 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7306 trace_kvm_fpu(1);
7307 }
7308
7309 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7310 {
7311 kvm_put_guest_xcr0(vcpu);
7312
7313 if (!vcpu->guest_fpu_loaded) {
7314 vcpu->fpu_counter = 0;
7315 return;
7316 }
7317
7318 vcpu->guest_fpu_loaded = 0;
7319 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7320 __kernel_fpu_end();
7321 ++vcpu->stat.fpu_reload;
7322 /*
7323 * If using eager FPU mode, or if the guest is a frequent user
7324 * of the FPU, just leave the FPU active for next time.
7325 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7326 * the FPU in bursts will revert to loading it on demand.
7327 */
7328 if (!vcpu->arch.eager_fpu) {
7329 if (++vcpu->fpu_counter < 5)
7330 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7331 }
7332 trace_kvm_fpu(0);
7333 }
7334
7335 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7336 {
7337 kvmclock_reset(vcpu);
7338
7339 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7340 kvm_x86_ops->vcpu_free(vcpu);
7341 }
7342
7343 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7344 unsigned int id)
7345 {
7346 struct kvm_vcpu *vcpu;
7347
7348 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7349 printk_once(KERN_WARNING
7350 "kvm: SMP vm created on host with unstable TSC; "
7351 "guest TSC will not be reliable\n");
7352
7353 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7354
7355 return vcpu;
7356 }
7357
7358 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7359 {
7360 int r;
7361
7362 kvm_vcpu_mtrr_init(vcpu);
7363 r = vcpu_load(vcpu);
7364 if (r)
7365 return r;
7366 kvm_vcpu_reset(vcpu, false);
7367 kvm_mmu_setup(vcpu);
7368 vcpu_put(vcpu);
7369 return r;
7370 }
7371
7372 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7373 {
7374 struct msr_data msr;
7375 struct kvm *kvm = vcpu->kvm;
7376
7377 if (vcpu_load(vcpu))
7378 return;
7379 msr.data = 0x0;
7380 msr.index = MSR_IA32_TSC;
7381 msr.host_initiated = true;
7382 kvm_write_tsc(vcpu, &msr);
7383 vcpu_put(vcpu);
7384
7385 if (!kvmclock_periodic_sync)
7386 return;
7387
7388 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7389 KVMCLOCK_SYNC_PERIOD);
7390 }
7391
7392 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7393 {
7394 int r;
7395 vcpu->arch.apf.msr_val = 0;
7396
7397 r = vcpu_load(vcpu);
7398 BUG_ON(r);
7399 kvm_mmu_unload(vcpu);
7400 vcpu_put(vcpu);
7401
7402 kvm_x86_ops->vcpu_free(vcpu);
7403 }
7404
7405 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7406 {
7407 vcpu->arch.hflags = 0;
7408
7409 atomic_set(&vcpu->arch.nmi_queued, 0);
7410 vcpu->arch.nmi_pending = 0;
7411 vcpu->arch.nmi_injected = false;
7412 kvm_clear_interrupt_queue(vcpu);
7413 kvm_clear_exception_queue(vcpu);
7414
7415 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7416 kvm_update_dr0123(vcpu);
7417 vcpu->arch.dr6 = DR6_INIT;
7418 kvm_update_dr6(vcpu);
7419 vcpu->arch.dr7 = DR7_FIXED_1;
7420 kvm_update_dr7(vcpu);
7421
7422 vcpu->arch.cr2 = 0;
7423
7424 kvm_make_request(KVM_REQ_EVENT, vcpu);
7425 vcpu->arch.apf.msr_val = 0;
7426 vcpu->arch.st.msr_val = 0;
7427
7428 kvmclock_reset(vcpu);
7429
7430 kvm_clear_async_pf_completion_queue(vcpu);
7431 kvm_async_pf_hash_reset(vcpu);
7432 vcpu->arch.apf.halted = false;
7433
7434 if (!init_event) {
7435 kvm_pmu_reset(vcpu);
7436 vcpu->arch.smbase = 0x30000;
7437 }
7438
7439 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7440 vcpu->arch.regs_avail = ~0;
7441 vcpu->arch.regs_dirty = ~0;
7442
7443 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7444 }
7445
7446 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7447 {
7448 struct kvm_segment cs;
7449
7450 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7451 cs.selector = vector << 8;
7452 cs.base = vector << 12;
7453 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7454 kvm_rip_write(vcpu, 0);
7455 }
7456
7457 int kvm_arch_hardware_enable(void)
7458 {
7459 struct kvm *kvm;
7460 struct kvm_vcpu *vcpu;
7461 int i;
7462 int ret;
7463 u64 local_tsc;
7464 u64 max_tsc = 0;
7465 bool stable, backwards_tsc = false;
7466
7467 kvm_shared_msr_cpu_online();
7468 ret = kvm_x86_ops->hardware_enable();
7469 if (ret != 0)
7470 return ret;
7471
7472 local_tsc = rdtsc();
7473 stable = !check_tsc_unstable();
7474 list_for_each_entry(kvm, &vm_list, vm_list) {
7475 kvm_for_each_vcpu(i, vcpu, kvm) {
7476 if (!stable && vcpu->cpu == smp_processor_id())
7477 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7478 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7479 backwards_tsc = true;
7480 if (vcpu->arch.last_host_tsc > max_tsc)
7481 max_tsc = vcpu->arch.last_host_tsc;
7482 }
7483 }
7484 }
7485
7486 /*
7487 * Sometimes, even reliable TSCs go backwards. This happens on
7488 * platforms that reset TSC during suspend or hibernate actions, but
7489 * maintain synchronization. We must compensate. Fortunately, we can
7490 * detect that condition here, which happens early in CPU bringup,
7491 * before any KVM threads can be running. Unfortunately, we can't
7492 * bring the TSCs fully up to date with real time, as we aren't yet far
7493 * enough into CPU bringup that we know how much real time has actually
7494 * elapsed; our helper function, get_kernel_ns() will be using boot
7495 * variables that haven't been updated yet.
7496 *
7497 * So we simply find the maximum observed TSC above, then record the
7498 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7499 * the adjustment will be applied. Note that we accumulate
7500 * adjustments, in case multiple suspend cycles happen before some VCPU
7501 * gets a chance to run again. In the event that no KVM threads get a
7502 * chance to run, we will miss the entire elapsed period, as we'll have
7503 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7504 * loose cycle time. This isn't too big a deal, since the loss will be
7505 * uniform across all VCPUs (not to mention the scenario is extremely
7506 * unlikely). It is possible that a second hibernate recovery happens
7507 * much faster than a first, causing the observed TSC here to be
7508 * smaller; this would require additional padding adjustment, which is
7509 * why we set last_host_tsc to the local tsc observed here.
7510 *
7511 * N.B. - this code below runs only on platforms with reliable TSC,
7512 * as that is the only way backwards_tsc is set above. Also note
7513 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7514 * have the same delta_cyc adjustment applied if backwards_tsc
7515 * is detected. Note further, this adjustment is only done once,
7516 * as we reset last_host_tsc on all VCPUs to stop this from being
7517 * called multiple times (one for each physical CPU bringup).
7518 *
7519 * Platforms with unreliable TSCs don't have to deal with this, they
7520 * will be compensated by the logic in vcpu_load, which sets the TSC to
7521 * catchup mode. This will catchup all VCPUs to real time, but cannot
7522 * guarantee that they stay in perfect synchronization.
7523 */
7524 if (backwards_tsc) {
7525 u64 delta_cyc = max_tsc - local_tsc;
7526 backwards_tsc_observed = true;
7527 list_for_each_entry(kvm, &vm_list, vm_list) {
7528 kvm_for_each_vcpu(i, vcpu, kvm) {
7529 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7530 vcpu->arch.last_host_tsc = local_tsc;
7531 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7532 }
7533
7534 /*
7535 * We have to disable TSC offset matching.. if you were
7536 * booting a VM while issuing an S4 host suspend....
7537 * you may have some problem. Solving this issue is
7538 * left as an exercise to the reader.
7539 */
7540 kvm->arch.last_tsc_nsec = 0;
7541 kvm->arch.last_tsc_write = 0;
7542 }
7543
7544 }
7545 return 0;
7546 }
7547
7548 void kvm_arch_hardware_disable(void)
7549 {
7550 kvm_x86_ops->hardware_disable();
7551 drop_user_return_notifiers();
7552 }
7553
7554 int kvm_arch_hardware_setup(void)
7555 {
7556 int r;
7557
7558 r = kvm_x86_ops->hardware_setup();
7559 if (r != 0)
7560 return r;
7561
7562 if (kvm_has_tsc_control) {
7563 /*
7564 * Make sure the user can only configure tsc_khz values that
7565 * fit into a signed integer.
7566 * A min value is not calculated needed because it will always
7567 * be 1 on all machines.
7568 */
7569 u64 max = min(0x7fffffffULL,
7570 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7571 kvm_max_guest_tsc_khz = max;
7572
7573 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7574 }
7575
7576 kvm_init_msr_list();
7577 return 0;
7578 }
7579
7580 void kvm_arch_hardware_unsetup(void)
7581 {
7582 kvm_x86_ops->hardware_unsetup();
7583 }
7584
7585 void kvm_arch_check_processor_compat(void *rtn)
7586 {
7587 kvm_x86_ops->check_processor_compatibility(rtn);
7588 }
7589
7590 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7591 {
7592 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7593 }
7594 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7595
7596 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7597 {
7598 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7599 }
7600
7601 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7602 {
7603 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7604 }
7605
7606 struct static_key kvm_no_apic_vcpu __read_mostly;
7607 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7608
7609 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7610 {
7611 struct page *page;
7612 struct kvm *kvm;
7613 int r;
7614
7615 BUG_ON(vcpu->kvm == NULL);
7616 kvm = vcpu->kvm;
7617
7618 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7619 vcpu->arch.pv.pv_unhalted = false;
7620 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7621 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7622 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7623 else
7624 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7625
7626 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7627 if (!page) {
7628 r = -ENOMEM;
7629 goto fail;
7630 }
7631 vcpu->arch.pio_data = page_address(page);
7632
7633 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7634
7635 r = kvm_mmu_create(vcpu);
7636 if (r < 0)
7637 goto fail_free_pio_data;
7638
7639 if (irqchip_in_kernel(kvm)) {
7640 r = kvm_create_lapic(vcpu);
7641 if (r < 0)
7642 goto fail_mmu_destroy;
7643 } else
7644 static_key_slow_inc(&kvm_no_apic_vcpu);
7645
7646 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7647 GFP_KERNEL);
7648 if (!vcpu->arch.mce_banks) {
7649 r = -ENOMEM;
7650 goto fail_free_lapic;
7651 }
7652 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7653
7654 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7655 r = -ENOMEM;
7656 goto fail_free_mce_banks;
7657 }
7658
7659 fx_init(vcpu);
7660
7661 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7662 vcpu->arch.pv_time_enabled = false;
7663
7664 vcpu->arch.guest_supported_xcr0 = 0;
7665 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7666
7667 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7668
7669 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7670
7671 kvm_async_pf_hash_reset(vcpu);
7672 kvm_pmu_init(vcpu);
7673
7674 vcpu->arch.pending_external_vector = -1;
7675
7676 kvm_hv_vcpu_init(vcpu);
7677
7678 return 0;
7679
7680 fail_free_mce_banks:
7681 kfree(vcpu->arch.mce_banks);
7682 fail_free_lapic:
7683 kvm_free_lapic(vcpu);
7684 fail_mmu_destroy:
7685 kvm_mmu_destroy(vcpu);
7686 fail_free_pio_data:
7687 free_page((unsigned long)vcpu->arch.pio_data);
7688 fail:
7689 return r;
7690 }
7691
7692 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7693 {
7694 int idx;
7695
7696 kvm_hv_vcpu_uninit(vcpu);
7697 kvm_pmu_destroy(vcpu);
7698 kfree(vcpu->arch.mce_banks);
7699 kvm_free_lapic(vcpu);
7700 idx = srcu_read_lock(&vcpu->kvm->srcu);
7701 kvm_mmu_destroy(vcpu);
7702 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7703 free_page((unsigned long)vcpu->arch.pio_data);
7704 if (!lapic_in_kernel(vcpu))
7705 static_key_slow_dec(&kvm_no_apic_vcpu);
7706 }
7707
7708 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7709 {
7710 kvm_x86_ops->sched_in(vcpu, cpu);
7711 }
7712
7713 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7714 {
7715 if (type)
7716 return -EINVAL;
7717
7718 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7719 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7720 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7721 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7722 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7723
7724 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7725 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7726 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7727 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7728 &kvm->arch.irq_sources_bitmap);
7729
7730 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7731 mutex_init(&kvm->arch.apic_map_lock);
7732 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7733
7734 pvclock_update_vm_gtod_copy(kvm);
7735
7736 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7737 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7738
7739 kvm_page_track_init(kvm);
7740 kvm_mmu_init_vm(kvm);
7741
7742 return 0;
7743 }
7744
7745 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7746 {
7747 int r;
7748 r = vcpu_load(vcpu);
7749 BUG_ON(r);
7750 kvm_mmu_unload(vcpu);
7751 vcpu_put(vcpu);
7752 }
7753
7754 static void kvm_free_vcpus(struct kvm *kvm)
7755 {
7756 unsigned int i;
7757 struct kvm_vcpu *vcpu;
7758
7759 /*
7760 * Unpin any mmu pages first.
7761 */
7762 kvm_for_each_vcpu(i, vcpu, kvm) {
7763 kvm_clear_async_pf_completion_queue(vcpu);
7764 kvm_unload_vcpu_mmu(vcpu);
7765 }
7766 kvm_for_each_vcpu(i, vcpu, kvm)
7767 kvm_arch_vcpu_free(vcpu);
7768
7769 mutex_lock(&kvm->lock);
7770 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7771 kvm->vcpus[i] = NULL;
7772
7773 atomic_set(&kvm->online_vcpus, 0);
7774 mutex_unlock(&kvm->lock);
7775 }
7776
7777 void kvm_arch_sync_events(struct kvm *kvm)
7778 {
7779 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7780 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7781 kvm_free_all_assigned_devices(kvm);
7782 kvm_free_pit(kvm);
7783 }
7784
7785 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7786 {
7787 int i, r;
7788 unsigned long hva;
7789 struct kvm_memslots *slots = kvm_memslots(kvm);
7790 struct kvm_memory_slot *slot, old;
7791
7792 /* Called with kvm->slots_lock held. */
7793 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7794 return -EINVAL;
7795
7796 slot = id_to_memslot(slots, id);
7797 if (size) {
7798 if (WARN_ON(slot->npages))
7799 return -EEXIST;
7800
7801 /*
7802 * MAP_SHARED to prevent internal slot pages from being moved
7803 * by fork()/COW.
7804 */
7805 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7806 MAP_SHARED | MAP_ANONYMOUS, 0);
7807 if (IS_ERR((void *)hva))
7808 return PTR_ERR((void *)hva);
7809 } else {
7810 if (!slot->npages)
7811 return 0;
7812
7813 hva = 0;
7814 }
7815
7816 old = *slot;
7817 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7818 struct kvm_userspace_memory_region m;
7819
7820 m.slot = id | (i << 16);
7821 m.flags = 0;
7822 m.guest_phys_addr = gpa;
7823 m.userspace_addr = hva;
7824 m.memory_size = size;
7825 r = __kvm_set_memory_region(kvm, &m);
7826 if (r < 0)
7827 return r;
7828 }
7829
7830 if (!size) {
7831 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7832 WARN_ON(r < 0);
7833 }
7834
7835 return 0;
7836 }
7837 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7838
7839 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7840 {
7841 int r;
7842
7843 mutex_lock(&kvm->slots_lock);
7844 r = __x86_set_memory_region(kvm, id, gpa, size);
7845 mutex_unlock(&kvm->slots_lock);
7846
7847 return r;
7848 }
7849 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7850
7851 void kvm_arch_destroy_vm(struct kvm *kvm)
7852 {
7853 if (current->mm == kvm->mm) {
7854 /*
7855 * Free memory regions allocated on behalf of userspace,
7856 * unless the the memory map has changed due to process exit
7857 * or fd copying.
7858 */
7859 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7860 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7861 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7862 }
7863 kvm_iommu_unmap_guest(kvm);
7864 kfree(kvm->arch.vpic);
7865 kfree(kvm->arch.vioapic);
7866 kvm_free_vcpus(kvm);
7867 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7868 kvm_mmu_uninit_vm(kvm);
7869 }
7870
7871 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7872 struct kvm_memory_slot *dont)
7873 {
7874 int i;
7875
7876 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7877 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7878 kvfree(free->arch.rmap[i]);
7879 free->arch.rmap[i] = NULL;
7880 }
7881 if (i == 0)
7882 continue;
7883
7884 if (!dont || free->arch.lpage_info[i - 1] !=
7885 dont->arch.lpage_info[i - 1]) {
7886 kvfree(free->arch.lpage_info[i - 1]);
7887 free->arch.lpage_info[i - 1] = NULL;
7888 }
7889 }
7890
7891 kvm_page_track_free_memslot(free, dont);
7892 }
7893
7894 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7895 unsigned long npages)
7896 {
7897 int i;
7898
7899 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7900 struct kvm_lpage_info *linfo;
7901 unsigned long ugfn;
7902 int lpages;
7903 int level = i + 1;
7904
7905 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7906 slot->base_gfn, level) + 1;
7907
7908 slot->arch.rmap[i] =
7909 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7910 if (!slot->arch.rmap[i])
7911 goto out_free;
7912 if (i == 0)
7913 continue;
7914
7915 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7916 if (!linfo)
7917 goto out_free;
7918
7919 slot->arch.lpage_info[i - 1] = linfo;
7920
7921 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7922 linfo[0].disallow_lpage = 1;
7923 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7924 linfo[lpages - 1].disallow_lpage = 1;
7925 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7926 /*
7927 * If the gfn and userspace address are not aligned wrt each
7928 * other, or if explicitly asked to, disable large page
7929 * support for this slot
7930 */
7931 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7932 !kvm_largepages_enabled()) {
7933 unsigned long j;
7934
7935 for (j = 0; j < lpages; ++j)
7936 linfo[j].disallow_lpage = 1;
7937 }
7938 }
7939
7940 if (kvm_page_track_create_memslot(slot, npages))
7941 goto out_free;
7942
7943 return 0;
7944
7945 out_free:
7946 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7947 kvfree(slot->arch.rmap[i]);
7948 slot->arch.rmap[i] = NULL;
7949 if (i == 0)
7950 continue;
7951
7952 kvfree(slot->arch.lpage_info[i - 1]);
7953 slot->arch.lpage_info[i - 1] = NULL;
7954 }
7955 return -ENOMEM;
7956 }
7957
7958 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7959 {
7960 /*
7961 * memslots->generation has been incremented.
7962 * mmio generation may have reached its maximum value.
7963 */
7964 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7965 }
7966
7967 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7968 struct kvm_memory_slot *memslot,
7969 const struct kvm_userspace_memory_region *mem,
7970 enum kvm_mr_change change)
7971 {
7972 return 0;
7973 }
7974
7975 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7976 struct kvm_memory_slot *new)
7977 {
7978 /* Still write protect RO slot */
7979 if (new->flags & KVM_MEM_READONLY) {
7980 kvm_mmu_slot_remove_write_access(kvm, new);
7981 return;
7982 }
7983
7984 /*
7985 * Call kvm_x86_ops dirty logging hooks when they are valid.
7986 *
7987 * kvm_x86_ops->slot_disable_log_dirty is called when:
7988 *
7989 * - KVM_MR_CREATE with dirty logging is disabled
7990 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7991 *
7992 * The reason is, in case of PML, we need to set D-bit for any slots
7993 * with dirty logging disabled in order to eliminate unnecessary GPA
7994 * logging in PML buffer (and potential PML buffer full VMEXT). This
7995 * guarantees leaving PML enabled during guest's lifetime won't have
7996 * any additonal overhead from PML when guest is running with dirty
7997 * logging disabled for memory slots.
7998 *
7999 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8000 * to dirty logging mode.
8001 *
8002 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8003 *
8004 * In case of write protect:
8005 *
8006 * Write protect all pages for dirty logging.
8007 *
8008 * All the sptes including the large sptes which point to this
8009 * slot are set to readonly. We can not create any new large
8010 * spte on this slot until the end of the logging.
8011 *
8012 * See the comments in fast_page_fault().
8013 */
8014 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8015 if (kvm_x86_ops->slot_enable_log_dirty)
8016 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8017 else
8018 kvm_mmu_slot_remove_write_access(kvm, new);
8019 } else {
8020 if (kvm_x86_ops->slot_disable_log_dirty)
8021 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8022 }
8023 }
8024
8025 void kvm_arch_commit_memory_region(struct kvm *kvm,
8026 const struct kvm_userspace_memory_region *mem,
8027 const struct kvm_memory_slot *old,
8028 const struct kvm_memory_slot *new,
8029 enum kvm_mr_change change)
8030 {
8031 int nr_mmu_pages = 0;
8032
8033 if (!kvm->arch.n_requested_mmu_pages)
8034 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8035
8036 if (nr_mmu_pages)
8037 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8038
8039 /*
8040 * Dirty logging tracks sptes in 4k granularity, meaning that large
8041 * sptes have to be split. If live migration is successful, the guest
8042 * in the source machine will be destroyed and large sptes will be
8043 * created in the destination. However, if the guest continues to run
8044 * in the source machine (for example if live migration fails), small
8045 * sptes will remain around and cause bad performance.
8046 *
8047 * Scan sptes if dirty logging has been stopped, dropping those
8048 * which can be collapsed into a single large-page spte. Later
8049 * page faults will create the large-page sptes.
8050 */
8051 if ((change != KVM_MR_DELETE) &&
8052 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8053 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8054 kvm_mmu_zap_collapsible_sptes(kvm, new);
8055
8056 /*
8057 * Set up write protection and/or dirty logging for the new slot.
8058 *
8059 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8060 * been zapped so no dirty logging staff is needed for old slot. For
8061 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8062 * new and it's also covered when dealing with the new slot.
8063 *
8064 * FIXME: const-ify all uses of struct kvm_memory_slot.
8065 */
8066 if (change != KVM_MR_DELETE)
8067 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8068 }
8069
8070 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8071 {
8072 kvm_mmu_invalidate_zap_all_pages(kvm);
8073 }
8074
8075 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8076 struct kvm_memory_slot *slot)
8077 {
8078 kvm_mmu_invalidate_zap_all_pages(kvm);
8079 }
8080
8081 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8082 {
8083 if (!list_empty_careful(&vcpu->async_pf.done))
8084 return true;
8085
8086 if (kvm_apic_has_events(vcpu))
8087 return true;
8088
8089 if (vcpu->arch.pv.pv_unhalted)
8090 return true;
8091
8092 if (atomic_read(&vcpu->arch.nmi_queued))
8093 return true;
8094
8095 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8096 return true;
8097
8098 if (kvm_arch_interrupt_allowed(vcpu) &&
8099 kvm_cpu_has_interrupt(vcpu))
8100 return true;
8101
8102 if (kvm_hv_has_stimer_pending(vcpu))
8103 return true;
8104
8105 return false;
8106 }
8107
8108 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8109 {
8110 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8111 kvm_x86_ops->check_nested_events(vcpu, false);
8112
8113 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8114 }
8115
8116 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8117 {
8118 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8119 }
8120
8121 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8122 {
8123 return kvm_x86_ops->interrupt_allowed(vcpu);
8124 }
8125
8126 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8127 {
8128 if (is_64_bit_mode(vcpu))
8129 return kvm_rip_read(vcpu);
8130 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8131 kvm_rip_read(vcpu));
8132 }
8133 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8134
8135 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8136 {
8137 return kvm_get_linear_rip(vcpu) == linear_rip;
8138 }
8139 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8140
8141 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8142 {
8143 unsigned long rflags;
8144
8145 rflags = kvm_x86_ops->get_rflags(vcpu);
8146 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8147 rflags &= ~X86_EFLAGS_TF;
8148 return rflags;
8149 }
8150 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8151
8152 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8153 {
8154 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8155 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8156 rflags |= X86_EFLAGS_TF;
8157 kvm_x86_ops->set_rflags(vcpu, rflags);
8158 }
8159
8160 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8161 {
8162 __kvm_set_rflags(vcpu, rflags);
8163 kvm_make_request(KVM_REQ_EVENT, vcpu);
8164 }
8165 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8166
8167 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8168 {
8169 int r;
8170
8171 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8172 work->wakeup_all)
8173 return;
8174
8175 r = kvm_mmu_reload(vcpu);
8176 if (unlikely(r))
8177 return;
8178
8179 if (!vcpu->arch.mmu.direct_map &&
8180 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8181 return;
8182
8183 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8184 }
8185
8186 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8187 {
8188 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8189 }
8190
8191 static inline u32 kvm_async_pf_next_probe(u32 key)
8192 {
8193 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8194 }
8195
8196 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8197 {
8198 u32 key = kvm_async_pf_hash_fn(gfn);
8199
8200 while (vcpu->arch.apf.gfns[key] != ~0)
8201 key = kvm_async_pf_next_probe(key);
8202
8203 vcpu->arch.apf.gfns[key] = gfn;
8204 }
8205
8206 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8207 {
8208 int i;
8209 u32 key = kvm_async_pf_hash_fn(gfn);
8210
8211 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8212 (vcpu->arch.apf.gfns[key] != gfn &&
8213 vcpu->arch.apf.gfns[key] != ~0); i++)
8214 key = kvm_async_pf_next_probe(key);
8215
8216 return key;
8217 }
8218
8219 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8220 {
8221 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8222 }
8223
8224 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8225 {
8226 u32 i, j, k;
8227
8228 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8229 while (true) {
8230 vcpu->arch.apf.gfns[i] = ~0;
8231 do {
8232 j = kvm_async_pf_next_probe(j);
8233 if (vcpu->arch.apf.gfns[j] == ~0)
8234 return;
8235 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8236 /*
8237 * k lies cyclically in ]i,j]
8238 * | i.k.j |
8239 * |....j i.k.| or |.k..j i...|
8240 */
8241 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8242 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8243 i = j;
8244 }
8245 }
8246
8247 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8248 {
8249
8250 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8251 sizeof(val));
8252 }
8253
8254 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8255 struct kvm_async_pf *work)
8256 {
8257 struct x86_exception fault;
8258
8259 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8260 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8261
8262 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8263 (vcpu->arch.apf.send_user_only &&
8264 kvm_x86_ops->get_cpl(vcpu) == 0))
8265 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8266 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8267 fault.vector = PF_VECTOR;
8268 fault.error_code_valid = true;
8269 fault.error_code = 0;
8270 fault.nested_page_fault = false;
8271 fault.address = work->arch.token;
8272 kvm_inject_page_fault(vcpu, &fault);
8273 }
8274 }
8275
8276 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8277 struct kvm_async_pf *work)
8278 {
8279 struct x86_exception fault;
8280
8281 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8282 if (work->wakeup_all)
8283 work->arch.token = ~0; /* broadcast wakeup */
8284 else
8285 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8286
8287 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8288 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8289 fault.vector = PF_VECTOR;
8290 fault.error_code_valid = true;
8291 fault.error_code = 0;
8292 fault.nested_page_fault = false;
8293 fault.address = work->arch.token;
8294 kvm_inject_page_fault(vcpu, &fault);
8295 }
8296 vcpu->arch.apf.halted = false;
8297 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8298 }
8299
8300 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8301 {
8302 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8303 return true;
8304 else
8305 return !kvm_event_needs_reinjection(vcpu) &&
8306 kvm_x86_ops->interrupt_allowed(vcpu);
8307 }
8308
8309 void kvm_arch_start_assignment(struct kvm *kvm)
8310 {
8311 atomic_inc(&kvm->arch.assigned_device_count);
8312 }
8313 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8314
8315 void kvm_arch_end_assignment(struct kvm *kvm)
8316 {
8317 atomic_dec(&kvm->arch.assigned_device_count);
8318 }
8319 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8320
8321 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8322 {
8323 return atomic_read(&kvm->arch.assigned_device_count);
8324 }
8325 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8326
8327 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8328 {
8329 atomic_inc(&kvm->arch.noncoherent_dma_count);
8330 }
8331 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8332
8333 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8334 {
8335 atomic_dec(&kvm->arch.noncoherent_dma_count);
8336 }
8337 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8338
8339 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8340 {
8341 return atomic_read(&kvm->arch.noncoherent_dma_count);
8342 }
8343 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8344
8345 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8346 struct irq_bypass_producer *prod)
8347 {
8348 struct kvm_kernel_irqfd *irqfd =
8349 container_of(cons, struct kvm_kernel_irqfd, consumer);
8350
8351 if (kvm_x86_ops->update_pi_irte) {
8352 irqfd->producer = prod;
8353 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8354 prod->irq, irqfd->gsi, 1);
8355 }
8356
8357 return -EINVAL;
8358 }
8359
8360 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8361 struct irq_bypass_producer *prod)
8362 {
8363 int ret;
8364 struct kvm_kernel_irqfd *irqfd =
8365 container_of(cons, struct kvm_kernel_irqfd, consumer);
8366
8367 if (!kvm_x86_ops->update_pi_irte) {
8368 WARN_ON(irqfd->producer != NULL);
8369 return;
8370 }
8371
8372 WARN_ON(irqfd->producer != prod);
8373 irqfd->producer = NULL;
8374
8375 /*
8376 * When producer of consumer is unregistered, we change back to
8377 * remapped mode, so we can re-use the current implementation
8378 * when the irq is masked/disabed or the consumer side (KVM
8379 * int this case doesn't want to receive the interrupts.
8380 */
8381 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8382 if (ret)
8383 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8384 " fails: %d\n", irqfd->consumer.token, ret);
8385 }
8386
8387 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8388 uint32_t guest_irq, bool set)
8389 {
8390 if (!kvm_x86_ops->update_pi_irte)
8391 return -EINVAL;
8392
8393 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8394 }
8395
8396 bool kvm_vector_hashing_enabled(void)
8397 {
8398 return vector_hashing;
8399 }
8400 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8401
8402 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8403 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8404 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8405 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8406 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8407 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8408 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8409 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8410 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8411 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8412 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8413 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8414 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8415 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8416 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8417 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8418 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
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