]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - arch/x86/kvm/x86.c
projects / mirror_ubuntu-jammy-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: x86: enable dirty log gradually in small chunks
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19 #include <linux/kvm_host.h>
20 #include "irq.h"
21 #include "mmu.h"
22 #include "i8254.h"
23 #include "tss.h"
24 #include "kvm_cache_regs.h"
25 #include "x86.h"
26 #include "cpuid.h"
27 #include "pmu.h"
28 #include "hyperv.h"
29 #include "lapic.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/export.h>
37 #include <linux/moduleparam.h>
38 #include <linux/mman.h>
39 #include <linux/highmem.h>
40 #include <linux/iommu.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/cpufreq.h>
43 #include <linux/user-return-notifier.h>
44 #include <linux/srcu.h>
45 #include <linux/slab.h>
46 #include <linux/perf_event.h>
47 #include <linux/uaccess.h>
48 #include <linux/hash.h>
49 #include <linux/pci.h>
50 #include <linux/timekeeper_internal.h>
51 #include <linux/pvclock_gtod.h>
52 #include <linux/kvm_irqfd.h>
53 #include <linux/irqbypass.h>
54 #include <linux/sched/stat.h>
55 #include <linux/sched/isolation.h>
56 #include <linux/mem_encrypt.h>
57
58 #include <trace/events/kvm.h>
59
60 #include <asm/debugreg.h>
61 #include <asm/msr.h>
62 #include <asm/desc.h>
63 #include <asm/mce.h>
64 #include <linux/kernel_stat.h>
65 #include <asm/fpu/internal.h> /* Ugh! */
66 #include <asm/pvclock.h>
67 #include <asm/div64.h>
68 #include <asm/irq_remapping.h>
69 #include <asm/mshyperv.h>
70 #include <asm/hypervisor.h>
71 #include <asm/intel_pt.h>
72 #include <asm/emulate_prefix.h>
73 #include <clocksource/hyperv_timer.h>
74
75 #define CREATE_TRACE_POINTS
76 #include "trace.h"
77
78 #define MAX_IO_MSRS 256
79 #define KVM_MAX_MCE_BANKS 32
80 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
81 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
82
83 #define emul_to_vcpu(ctxt) \
84 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
85
86 /* EFER defaults:
87 * - enable syscall per default because its emulated by KVM
88 * - enable LME and LMA per default on 64 bit KVM
89 */
90 #ifdef CONFIG_X86_64
91 static
92 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
93 #else
94 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
95 #endif
96
97 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
98
99 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
100 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
101
102 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
103 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
104
105 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
106 static void process_nmi(struct kvm_vcpu *vcpu);
107 static void enter_smm(struct kvm_vcpu *vcpu);
108 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
109 static void store_regs(struct kvm_vcpu *vcpu);
110 static int sync_regs(struct kvm_vcpu *vcpu);
111
112 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
113 EXPORT_SYMBOL_GPL(kvm_x86_ops);
114
115 static bool __read_mostly ignore_msrs = 0;
116 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
117
118 static bool __read_mostly report_ignored_msrs = true;
119 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
120
121 unsigned int min_timer_period_us = 200;
122 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
123
124 static bool __read_mostly kvmclock_periodic_sync = true;
125 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
126
127 bool __read_mostly kvm_has_tsc_control;
128 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
129 u32 __read_mostly kvm_max_guest_tsc_khz;
130 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
131 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
132 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
133 u64 __read_mostly kvm_max_tsc_scaling_ratio;
134 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
135 u64 __read_mostly kvm_default_tsc_scaling_ratio;
136 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
137
138 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
139 static u32 __read_mostly tsc_tolerance_ppm = 250;
140 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
141
142 /*
143 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
144 * adaptive tuning starting from default advancment of 1000ns. '0' disables
145 * advancement entirely. Any other value is used as-is and disables adaptive
146 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
147 */
148 static int __read_mostly lapic_timer_advance_ns = -1;
149 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
150
151 static bool __read_mostly vector_hashing = true;
152 module_param(vector_hashing, bool, S_IRUGO);
153
154 bool __read_mostly enable_vmware_backdoor = false;
155 module_param(enable_vmware_backdoor, bool, S_IRUGO);
156 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
157
158 static bool __read_mostly force_emulation_prefix = false;
159 module_param(force_emulation_prefix, bool, S_IRUGO);
160
161 int __read_mostly pi_inject_timer = -1;
162 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
163
164 #define KVM_NR_SHARED_MSRS 16
165
166 struct kvm_shared_msrs_global {
167 int nr;
168 u32 msrs[KVM_NR_SHARED_MSRS];
169 };
170
171 struct kvm_shared_msrs {
172 struct user_return_notifier urn;
173 bool registered;
174 struct kvm_shared_msr_values {
175 u64 host;
176 u64 curr;
177 } values[KVM_NR_SHARED_MSRS];
178 };
179
180 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
181 static struct kvm_shared_msrs __percpu *shared_msrs;
182
183 static u64 __read_mostly host_xss;
184
185 struct kvm_stats_debugfs_item debugfs_entries[] = {
186 { "pf_fixed", VCPU_STAT(pf_fixed) },
187 { "pf_guest", VCPU_STAT(pf_guest) },
188 { "tlb_flush", VCPU_STAT(tlb_flush) },
189 { "invlpg", VCPU_STAT(invlpg) },
190 { "exits", VCPU_STAT(exits) },
191 { "io_exits", VCPU_STAT(io_exits) },
192 { "mmio_exits", VCPU_STAT(mmio_exits) },
193 { "signal_exits", VCPU_STAT(signal_exits) },
194 { "irq_window", VCPU_STAT(irq_window_exits) },
195 { "nmi_window", VCPU_STAT(nmi_window_exits) },
196 { "halt_exits", VCPU_STAT(halt_exits) },
197 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
198 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
199 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
200 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
201 { "hypercalls", VCPU_STAT(hypercalls) },
202 { "request_irq", VCPU_STAT(request_irq_exits) },
203 { "irq_exits", VCPU_STAT(irq_exits) },
204 { "host_state_reload", VCPU_STAT(host_state_reload) },
205 { "fpu_reload", VCPU_STAT(fpu_reload) },
206 { "insn_emulation", VCPU_STAT(insn_emulation) },
207 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
208 { "irq_injections", VCPU_STAT(irq_injections) },
209 { "nmi_injections", VCPU_STAT(nmi_injections) },
210 { "req_event", VCPU_STAT(req_event) },
211 { "l1d_flush", VCPU_STAT(l1d_flush) },
212 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
213 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
214 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
215 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
216 { "mmu_flooded", VM_STAT(mmu_flooded) },
217 { "mmu_recycled", VM_STAT(mmu_recycled) },
218 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
219 { "mmu_unsync", VM_STAT(mmu_unsync) },
220 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
221 { "largepages", VM_STAT(lpages, .mode = 0444) },
222 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
223 { "max_mmu_page_hash_collisions",
224 VM_STAT(max_mmu_page_hash_collisions) },
225 { NULL }
226 };
227
228 u64 __read_mostly host_xcr0;
229
230 struct kmem_cache *x86_fpu_cache;
231 EXPORT_SYMBOL_GPL(x86_fpu_cache);
232
233 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
234
235 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
236 {
237 int i;
238 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
239 vcpu->arch.apf.gfns[i] = ~0;
240 }
241
242 static void kvm_on_user_return(struct user_return_notifier *urn)
243 {
244 unsigned slot;
245 struct kvm_shared_msrs *locals
246 = container_of(urn, struct kvm_shared_msrs, urn);
247 struct kvm_shared_msr_values *values;
248 unsigned long flags;
249
250 /*
251 * Disabling irqs at this point since the following code could be
252 * interrupted and executed through kvm_arch_hardware_disable()
253 */
254 local_irq_save(flags);
255 if (locals->registered) {
256 locals->registered = false;
257 user_return_notifier_unregister(urn);
258 }
259 local_irq_restore(flags);
260 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
261 values = &locals->values[slot];
262 if (values->host != values->curr) {
263 wrmsrl(shared_msrs_global.msrs[slot], values->host);
264 values->curr = values->host;
265 }
266 }
267 }
268
269 void kvm_define_shared_msr(unsigned slot, u32 msr)
270 {
271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
272 shared_msrs_global.msrs[slot] = msr;
273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
275 }
276 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277
278 static void kvm_shared_msr_cpu_online(void)
279 {
280 unsigned int cpu = smp_processor_id();
281 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
282 u64 value;
283 int i;
284
285 for (i = 0; i < shared_msrs_global.nr; ++i) {
286 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
287 smsr->values[i].host = value;
288 smsr->values[i].curr = value;
289 }
290 }
291
292 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
293 {
294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
296 int err;
297
298 value = (value & mask) | (smsr->values[slot].host & ~mask);
299 if (value == smsr->values[slot].curr)
300 return 0;
301 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
302 if (err)
303 return 1;
304
305 smsr->values[slot].curr = value;
306 if (!smsr->registered) {
307 smsr->urn.on_user_return = kvm_on_user_return;
308 user_return_notifier_register(&smsr->urn);
309 smsr->registered = true;
310 }
311 return 0;
312 }
313 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
314
315 static void drop_user_return_notifiers(void)
316 {
317 unsigned int cpu = smp_processor_id();
318 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
319
320 if (smsr->registered)
321 kvm_on_user_return(&smsr->urn);
322 }
323
324 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
325 {
326 return vcpu->arch.apic_base;
327 }
328 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
329
330 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
331 {
332 return kvm_apic_mode(kvm_get_apic_base(vcpu));
333 }
334 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
335
336 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
337 {
338 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
339 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
340 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
341 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
342
343 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
344 return 1;
345 if (!msr_info->host_initiated) {
346 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
347 return 1;
348 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
349 return 1;
350 }
351
352 kvm_lapic_set_base(vcpu, msr_info->data);
353 return 0;
354 }
355 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
356
357 asmlinkage __visible void kvm_spurious_fault(void)
358 {
359 /* Fault while not rebooting. We want the trace. */
360 BUG_ON(!kvm_rebooting);
361 }
362 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
363
364 #define EXCPT_BENIGN 0
365 #define EXCPT_CONTRIBUTORY 1
366 #define EXCPT_PF 2
367
368 static int exception_class(int vector)
369 {
370 switch (vector) {
371 case PF_VECTOR:
372 return EXCPT_PF;
373 case DE_VECTOR:
374 case TS_VECTOR:
375 case NP_VECTOR:
376 case SS_VECTOR:
377 case GP_VECTOR:
378 return EXCPT_CONTRIBUTORY;
379 default:
380 break;
381 }
382 return EXCPT_BENIGN;
383 }
384
385 #define EXCPT_FAULT 0
386 #define EXCPT_TRAP 1
387 #define EXCPT_ABORT 2
388 #define EXCPT_INTERRUPT 3
389
390 static int exception_type(int vector)
391 {
392 unsigned int mask;
393
394 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
395 return EXCPT_INTERRUPT;
396
397 mask = 1 << vector;
398
399 /* #DB is trap, as instruction watchpoints are handled elsewhere */
400 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
401 return EXCPT_TRAP;
402
403 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
404 return EXCPT_ABORT;
405
406 /* Reserved exceptions will result in fault */
407 return EXCPT_FAULT;
408 }
409
410 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
411 {
412 unsigned nr = vcpu->arch.exception.nr;
413 bool has_payload = vcpu->arch.exception.has_payload;
414 unsigned long payload = vcpu->arch.exception.payload;
415
416 if (!has_payload)
417 return;
418
419 switch (nr) {
420 case DB_VECTOR:
421 /*
422 * "Certain debug exceptions may clear bit 0-3. The
423 * remaining contents of the DR6 register are never
424 * cleared by the processor".
425 */
426 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
427 /*
428 * DR6.RTM is set by all #DB exceptions that don't clear it.
429 */
430 vcpu->arch.dr6 |= DR6_RTM;
431 vcpu->arch.dr6 |= payload;
432 /*
433 * Bit 16 should be set in the payload whenever the #DB
434 * exception should clear DR6.RTM. This makes the payload
435 * compatible with the pending debug exceptions under VMX.
436 * Though not currently documented in the SDM, this also
437 * makes the payload compatible with the exit qualification
438 * for #DB exceptions under VMX.
439 */
440 vcpu->arch.dr6 ^= payload & DR6_RTM;
441
442 /*
443 * The #DB payload is defined as compatible with the 'pending
444 * debug exceptions' field under VMX, not DR6. While bit 12 is
445 * defined in the 'pending debug exceptions' field (enabled
446 * breakpoint), it is reserved and must be zero in DR6.
447 */
448 vcpu->arch.dr6 &= ~BIT(12);
449 break;
450 case PF_VECTOR:
451 vcpu->arch.cr2 = payload;
452 break;
453 }
454
455 vcpu->arch.exception.has_payload = false;
456 vcpu->arch.exception.payload = 0;
457 }
458 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
459
460 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
461 unsigned nr, bool has_error, u32 error_code,
462 bool has_payload, unsigned long payload, bool reinject)
463 {
464 u32 prev_nr;
465 int class1, class2;
466
467 kvm_make_request(KVM_REQ_EVENT, vcpu);
468
469 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
470 queue:
471 if (has_error && !is_protmode(vcpu))
472 has_error = false;
473 if (reinject) {
474 /*
475 * On vmentry, vcpu->arch.exception.pending is only
476 * true if an event injection was blocked by
477 * nested_run_pending. In that case, however,
478 * vcpu_enter_guest requests an immediate exit,
479 * and the guest shouldn't proceed far enough to
480 * need reinjection.
481 */
482 WARN_ON_ONCE(vcpu->arch.exception.pending);
483 vcpu->arch.exception.injected = true;
484 if (WARN_ON_ONCE(has_payload)) {
485 /*
486 * A reinjected event has already
487 * delivered its payload.
488 */
489 has_payload = false;
490 payload = 0;
491 }
492 } else {
493 vcpu->arch.exception.pending = true;
494 vcpu->arch.exception.injected = false;
495 }
496 vcpu->arch.exception.has_error_code = has_error;
497 vcpu->arch.exception.nr = nr;
498 vcpu->arch.exception.error_code = error_code;
499 vcpu->arch.exception.has_payload = has_payload;
500 vcpu->arch.exception.payload = payload;
501 if (!is_guest_mode(vcpu))
502 kvm_deliver_exception_payload(vcpu);
503 return;
504 }
505
506 /* to check exception */
507 prev_nr = vcpu->arch.exception.nr;
508 if (prev_nr == DF_VECTOR) {
509 /* triple fault -> shutdown */
510 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
511 return;
512 }
513 class1 = exception_class(prev_nr);
514 class2 = exception_class(nr);
515 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
516 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
517 /*
518 * Generate double fault per SDM Table 5-5. Set
519 * exception.pending = true so that the double fault
520 * can trigger a nested vmexit.
521 */
522 vcpu->arch.exception.pending = true;
523 vcpu->arch.exception.injected = false;
524 vcpu->arch.exception.has_error_code = true;
525 vcpu->arch.exception.nr = DF_VECTOR;
526 vcpu->arch.exception.error_code = 0;
527 vcpu->arch.exception.has_payload = false;
528 vcpu->arch.exception.payload = 0;
529 } else
530 /* replace previous exception with a new one in a hope
531 that instruction re-execution will regenerate lost
532 exception */
533 goto queue;
534 }
535
536 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
537 {
538 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
539 }
540 EXPORT_SYMBOL_GPL(kvm_queue_exception);
541
542 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
543 {
544 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
545 }
546 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
547
548 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
549 unsigned long payload)
550 {
551 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
552 }
553
554 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
555 u32 error_code, unsigned long payload)
556 {
557 kvm_multiple_exception(vcpu, nr, true, error_code,
558 true, payload, false);
559 }
560
561 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
562 {
563 if (err)
564 kvm_inject_gp(vcpu, 0);
565 else
566 return kvm_skip_emulated_instruction(vcpu);
567
568 return 1;
569 }
570 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
571
572 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
573 {
574 ++vcpu->stat.pf_guest;
575 vcpu->arch.exception.nested_apf =
576 is_guest_mode(vcpu) && fault->async_page_fault;
577 if (vcpu->arch.exception.nested_apf) {
578 vcpu->arch.apf.nested_apf_token = fault->address;
579 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
580 } else {
581 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
582 fault->address);
583 }
584 }
585 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
586
587 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
588 {
589 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
590 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
591 else
592 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
593
594 return fault->nested_page_fault;
595 }
596
597 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
598 {
599 atomic_inc(&vcpu->arch.nmi_queued);
600 kvm_make_request(KVM_REQ_NMI, vcpu);
601 }
602 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
603
604 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
605 {
606 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
607 }
608 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
609
610 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
611 {
612 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
613 }
614 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
615
616 /*
617 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
618 * a #GP and return false.
619 */
620 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
621 {
622 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
623 return true;
624 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
625 return false;
626 }
627 EXPORT_SYMBOL_GPL(kvm_require_cpl);
628
629 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
630 {
631 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
632 return true;
633
634 kvm_queue_exception(vcpu, UD_VECTOR);
635 return false;
636 }
637 EXPORT_SYMBOL_GPL(kvm_require_dr);
638
639 /*
640 * This function will be used to read from the physical memory of the currently
641 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
642 * can read from guest physical or from the guest's guest physical memory.
643 */
644 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
645 gfn_t ngfn, void *data, int offset, int len,
646 u32 access)
647 {
648 struct x86_exception exception;
649 gfn_t real_gfn;
650 gpa_t ngpa;
651
652 ngpa = gfn_to_gpa(ngfn);
653 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
654 if (real_gfn == UNMAPPED_GVA)
655 return -EFAULT;
656
657 real_gfn = gpa_to_gfn(real_gfn);
658
659 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
660 }
661 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
662
663 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
664 void *data, int offset, int len, u32 access)
665 {
666 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
667 data, offset, len, access);
668 }
669
670 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
671 {
672 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
673 rsvd_bits(1, 2);
674 }
675
676 /*
677 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
678 */
679 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
680 {
681 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
682 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
683 int i;
684 int ret;
685 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
686
687 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
688 offset * sizeof(u64), sizeof(pdpte),
689 PFERR_USER_MASK|PFERR_WRITE_MASK);
690 if (ret < 0) {
691 ret = 0;
692 goto out;
693 }
694 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
695 if ((pdpte[i] & PT_PRESENT_MASK) &&
696 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
697 ret = 0;
698 goto out;
699 }
700 }
701 ret = 1;
702
703 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
704 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
705
706 out:
707
708 return ret;
709 }
710 EXPORT_SYMBOL_GPL(load_pdptrs);
711
712 bool pdptrs_changed(struct kvm_vcpu *vcpu)
713 {
714 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
715 int offset;
716 gfn_t gfn;
717 int r;
718
719 if (!is_pae_paging(vcpu))
720 return false;
721
722 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
723 return true;
724
725 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
726 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
727 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
728 PFERR_USER_MASK | PFERR_WRITE_MASK);
729 if (r < 0)
730 return true;
731
732 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
733 }
734 EXPORT_SYMBOL_GPL(pdptrs_changed);
735
736 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
737 {
738 unsigned long old_cr0 = kvm_read_cr0(vcpu);
739 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
740
741 cr0 |= X86_CR0_ET;
742
743 #ifdef CONFIG_X86_64
744 if (cr0 & 0xffffffff00000000UL)
745 return 1;
746 #endif
747
748 cr0 &= ~CR0_RESERVED_BITS;
749
750 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
751 return 1;
752
753 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
754 return 1;
755
756 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
757 #ifdef CONFIG_X86_64
758 if ((vcpu->arch.efer & EFER_LME)) {
759 int cs_db, cs_l;
760
761 if (!is_pae(vcpu))
762 return 1;
763 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
764 if (cs_l)
765 return 1;
766 } else
767 #endif
768 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
769 kvm_read_cr3(vcpu)))
770 return 1;
771 }
772
773 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
774 return 1;
775
776 kvm_x86_ops->set_cr0(vcpu, cr0);
777
778 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
779 kvm_clear_async_pf_completion_queue(vcpu);
780 kvm_async_pf_hash_reset(vcpu);
781 }
782
783 if ((cr0 ^ old_cr0) & update_bits)
784 kvm_mmu_reset_context(vcpu);
785
786 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
787 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
788 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
789 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
790
791 return 0;
792 }
793 EXPORT_SYMBOL_GPL(kvm_set_cr0);
794
795 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
796 {
797 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
798 }
799 EXPORT_SYMBOL_GPL(kvm_lmsw);
800
801 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
802 {
803 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
804
805 if (vcpu->arch.xcr0 != host_xcr0)
806 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
807
808 if (vcpu->arch.xsaves_enabled &&
809 vcpu->arch.ia32_xss != host_xss)
810 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
811 }
812 }
813 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
814
815 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
816 {
817 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
818
819 if (vcpu->arch.xcr0 != host_xcr0)
820 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
821
822 if (vcpu->arch.xsaves_enabled &&
823 vcpu->arch.ia32_xss != host_xss)
824 wrmsrl(MSR_IA32_XSS, host_xss);
825 }
826
827 }
828 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
829
830 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
831 {
832 u64 xcr0 = xcr;
833 u64 old_xcr0 = vcpu->arch.xcr0;
834 u64 valid_bits;
835
836 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
837 if (index != XCR_XFEATURE_ENABLED_MASK)
838 return 1;
839 if (!(xcr0 & XFEATURE_MASK_FP))
840 return 1;
841 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
842 return 1;
843
844 /*
845 * Do not allow the guest to set bits that we do not support
846 * saving. However, xcr0 bit 0 is always set, even if the
847 * emulated CPU does not support XSAVE (see fx_init).
848 */
849 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
850 if (xcr0 & ~valid_bits)
851 return 1;
852
853 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
854 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
855 return 1;
856
857 if (xcr0 & XFEATURE_MASK_AVX512) {
858 if (!(xcr0 & XFEATURE_MASK_YMM))
859 return 1;
860 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
861 return 1;
862 }
863 vcpu->arch.xcr0 = xcr0;
864
865 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
866 kvm_update_cpuid(vcpu);
867 return 0;
868 }
869
870 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
871 {
872 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
873 __kvm_set_xcr(vcpu, index, xcr)) {
874 kvm_inject_gp(vcpu, 0);
875 return 1;
876 }
877 return 0;
878 }
879 EXPORT_SYMBOL_GPL(kvm_set_xcr);
880
881 #define __cr4_reserved_bits(__cpu_has, __c) \
882 ({ \
883 u64 __reserved_bits = CR4_RESERVED_BITS; \
884 \
885 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
886 __reserved_bits |= X86_CR4_OSXSAVE; \
887 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
888 __reserved_bits |= X86_CR4_SMEP; \
889 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
890 __reserved_bits |= X86_CR4_SMAP; \
891 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
892 __reserved_bits |= X86_CR4_FSGSBASE; \
893 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
894 __reserved_bits |= X86_CR4_PKE; \
895 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
896 __reserved_bits |= X86_CR4_LA57; \
897 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
898 __reserved_bits |= X86_CR4_UMIP; \
899 __reserved_bits; \
900 })
901
902 static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
903 {
904 u64 reserved_bits = __cr4_reserved_bits(cpu_has, c);
905
906 if (cpuid_ecx(0x7) & feature_bit(LA57))
907 reserved_bits &= ~X86_CR4_LA57;
908
909 if (kvm_x86_ops->umip_emulated())
910 reserved_bits &= ~X86_CR4_UMIP;
911
912 return reserved_bits;
913 }
914
915 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
916 {
917 if (cr4 & cr4_reserved_bits)
918 return -EINVAL;
919
920 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
921 return -EINVAL;
922
923 return 0;
924 }
925
926 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
927 {
928 unsigned long old_cr4 = kvm_read_cr4(vcpu);
929 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
930 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
931
932 if (kvm_valid_cr4(vcpu, cr4))
933 return 1;
934
935 if (is_long_mode(vcpu)) {
936 if (!(cr4 & X86_CR4_PAE))
937 return 1;
938 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
939 && ((cr4 ^ old_cr4) & pdptr_bits)
940 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
941 kvm_read_cr3(vcpu)))
942 return 1;
943
944 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
945 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
946 return 1;
947
948 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
949 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
950 return 1;
951 }
952
953 if (kvm_x86_ops->set_cr4(vcpu, cr4))
954 return 1;
955
956 if (((cr4 ^ old_cr4) & pdptr_bits) ||
957 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
958 kvm_mmu_reset_context(vcpu);
959
960 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
961 kvm_update_cpuid(vcpu);
962
963 return 0;
964 }
965 EXPORT_SYMBOL_GPL(kvm_set_cr4);
966
967 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
968 {
969 bool skip_tlb_flush = false;
970 #ifdef CONFIG_X86_64
971 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
972
973 if (pcid_enabled) {
974 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
975 cr3 &= ~X86_CR3_PCID_NOFLUSH;
976 }
977 #endif
978
979 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
980 if (!skip_tlb_flush) {
981 kvm_mmu_sync_roots(vcpu);
982 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
983 }
984 return 0;
985 }
986
987 if (is_long_mode(vcpu) &&
988 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
989 return 1;
990 else if (is_pae_paging(vcpu) &&
991 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
992 return 1;
993
994 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
995 vcpu->arch.cr3 = cr3;
996 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
997
998 return 0;
999 }
1000 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1001
1002 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1003 {
1004 if (cr8 & CR8_RESERVED_BITS)
1005 return 1;
1006 if (lapic_in_kernel(vcpu))
1007 kvm_lapic_set_tpr(vcpu, cr8);
1008 else
1009 vcpu->arch.cr8 = cr8;
1010 return 0;
1011 }
1012 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1013
1014 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1015 {
1016 if (lapic_in_kernel(vcpu))
1017 return kvm_lapic_get_cr8(vcpu);
1018 else
1019 return vcpu->arch.cr8;
1020 }
1021 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1022
1023 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1024 {
1025 int i;
1026
1027 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1028 for (i = 0; i < KVM_NR_DB_REGS; i++)
1029 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1030 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1031 }
1032 }
1033
1034 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1035 {
1036 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1037 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1038 }
1039
1040 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1041 {
1042 unsigned long dr7;
1043
1044 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1045 dr7 = vcpu->arch.guest_debug_dr7;
1046 else
1047 dr7 = vcpu->arch.dr7;
1048 kvm_x86_ops->set_dr7(vcpu, dr7);
1049 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1050 if (dr7 & DR7_BP_EN_MASK)
1051 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1052 }
1053
1054 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1055 {
1056 u64 fixed = DR6_FIXED_1;
1057
1058 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1059 fixed |= DR6_RTM;
1060 return fixed;
1061 }
1062
1063 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1064 {
1065 size_t size = ARRAY_SIZE(vcpu->arch.db);
1066
1067 switch (dr) {
1068 case 0 ... 3:
1069 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1070 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1071 vcpu->arch.eff_db[dr] = val;
1072 break;
1073 case 4:
1074 /* fall through */
1075 case 6:
1076 if (val & 0xffffffff00000000ULL)
1077 return -1; /* #GP */
1078 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1079 kvm_update_dr6(vcpu);
1080 break;
1081 case 5:
1082 /* fall through */
1083 default: /* 7 */
1084 if (!kvm_dr7_valid(val))
1085 return -1; /* #GP */
1086 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1087 kvm_update_dr7(vcpu);
1088 break;
1089 }
1090
1091 return 0;
1092 }
1093
1094 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1095 {
1096 if (__kvm_set_dr(vcpu, dr, val)) {
1097 kvm_inject_gp(vcpu, 0);
1098 return 1;
1099 }
1100 return 0;
1101 }
1102 EXPORT_SYMBOL_GPL(kvm_set_dr);
1103
1104 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1105 {
1106 size_t size = ARRAY_SIZE(vcpu->arch.db);
1107
1108 switch (dr) {
1109 case 0 ... 3:
1110 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1111 break;
1112 case 4:
1113 /* fall through */
1114 case 6:
1115 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1116 *val = vcpu->arch.dr6;
1117 else
1118 *val = kvm_x86_ops->get_dr6(vcpu);
1119 break;
1120 case 5:
1121 /* fall through */
1122 default: /* 7 */
1123 *val = vcpu->arch.dr7;
1124 break;
1125 }
1126 return 0;
1127 }
1128 EXPORT_SYMBOL_GPL(kvm_get_dr);
1129
1130 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1131 {
1132 u32 ecx = kvm_rcx_read(vcpu);
1133 u64 data;
1134 int err;
1135
1136 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1137 if (err)
1138 return err;
1139 kvm_rax_write(vcpu, (u32)data);
1140 kvm_rdx_write(vcpu, data >> 32);
1141 return err;
1142 }
1143 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1144
1145 /*
1146 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1147 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1148 *
1149 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1150 * extract the supported MSRs from the related const lists.
1151 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1152 * capabilities of the host cpu. This capabilities test skips MSRs that are
1153 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1154 * may depend on host virtualization features rather than host cpu features.
1155 */
1156
1157 static const u32 msrs_to_save_all[] = {
1158 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1159 MSR_STAR,
1160 #ifdef CONFIG_X86_64
1161 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1162 #endif
1163 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1164 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1165 MSR_IA32_SPEC_CTRL,
1166 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1167 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1168 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1169 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1170 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1171 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1172 MSR_IA32_UMWAIT_CONTROL,
1173
1174 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1175 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1176 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1177 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1178 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1179 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1180 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1181 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1182 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1183 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1184 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1185 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1186 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1187 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1188 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1189 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1190 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1191 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1192 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1193 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1194 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1195 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1196 };
1197
1198 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1199 static unsigned num_msrs_to_save;
1200
1201 static const u32 emulated_msrs_all[] = {
1202 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1203 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1204 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1205 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1206 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1207 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1208 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1209 HV_X64_MSR_RESET,
1210 HV_X64_MSR_VP_INDEX,
1211 HV_X64_MSR_VP_RUNTIME,
1212 HV_X64_MSR_SCONTROL,
1213 HV_X64_MSR_STIMER0_CONFIG,
1214 HV_X64_MSR_VP_ASSIST_PAGE,
1215 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1216 HV_X64_MSR_TSC_EMULATION_STATUS,
1217
1218 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1219 MSR_KVM_PV_EOI_EN,
1220
1221 MSR_IA32_TSC_ADJUST,
1222 MSR_IA32_TSCDEADLINE,
1223 MSR_IA32_ARCH_CAPABILITIES,
1224 MSR_IA32_MISC_ENABLE,
1225 MSR_IA32_MCG_STATUS,
1226 MSR_IA32_MCG_CTL,
1227 MSR_IA32_MCG_EXT_CTL,
1228 MSR_IA32_SMBASE,
1229 MSR_SMI_COUNT,
1230 MSR_PLATFORM_INFO,
1231 MSR_MISC_FEATURES_ENABLES,
1232 MSR_AMD64_VIRT_SPEC_CTRL,
1233 MSR_IA32_POWER_CTL,
1234 MSR_IA32_UCODE_REV,
1235
1236 /*
1237 * The following list leaves out MSRs whose values are determined
1238 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1239 * We always support the "true" VMX control MSRs, even if the host
1240 * processor does not, so I am putting these registers here rather
1241 * than in msrs_to_save_all.
1242 */
1243 MSR_IA32_VMX_BASIC,
1244 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1245 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1246 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1247 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1248 MSR_IA32_VMX_MISC,
1249 MSR_IA32_VMX_CR0_FIXED0,
1250 MSR_IA32_VMX_CR4_FIXED0,
1251 MSR_IA32_VMX_VMCS_ENUM,
1252 MSR_IA32_VMX_PROCBASED_CTLS2,
1253 MSR_IA32_VMX_EPT_VPID_CAP,
1254 MSR_IA32_VMX_VMFUNC,
1255
1256 MSR_K7_HWCR,
1257 MSR_KVM_POLL_CONTROL,
1258 };
1259
1260 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1261 static unsigned num_emulated_msrs;
1262
1263 /*
1264 * List of msr numbers which are used to expose MSR-based features that
1265 * can be used by a hypervisor to validate requested CPU features.
1266 */
1267 static const u32 msr_based_features_all[] = {
1268 MSR_IA32_VMX_BASIC,
1269 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1270 MSR_IA32_VMX_PINBASED_CTLS,
1271 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1272 MSR_IA32_VMX_PROCBASED_CTLS,
1273 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1274 MSR_IA32_VMX_EXIT_CTLS,
1275 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1276 MSR_IA32_VMX_ENTRY_CTLS,
1277 MSR_IA32_VMX_MISC,
1278 MSR_IA32_VMX_CR0_FIXED0,
1279 MSR_IA32_VMX_CR0_FIXED1,
1280 MSR_IA32_VMX_CR4_FIXED0,
1281 MSR_IA32_VMX_CR4_FIXED1,
1282 MSR_IA32_VMX_VMCS_ENUM,
1283 MSR_IA32_VMX_PROCBASED_CTLS2,
1284 MSR_IA32_VMX_EPT_VPID_CAP,
1285 MSR_IA32_VMX_VMFUNC,
1286
1287 MSR_F10H_DECFG,
1288 MSR_IA32_UCODE_REV,
1289 MSR_IA32_ARCH_CAPABILITIES,
1290 };
1291
1292 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1293 static unsigned int num_msr_based_features;
1294
1295 static u64 kvm_get_arch_capabilities(void)
1296 {
1297 u64 data = 0;
1298
1299 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1300 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1301
1302 /*
1303 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1304 * the nested hypervisor runs with NX huge pages. If it is not,
1305 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1306 * L1 guests, so it need not worry about its own (L2) guests.
1307 */
1308 data |= ARCH_CAP_PSCHANGE_MC_NO;
1309
1310 /*
1311 * If we're doing cache flushes (either "always" or "cond")
1312 * we will do one whenever the guest does a vmlaunch/vmresume.
1313 * If an outer hypervisor is doing the cache flush for us
1314 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1315 * capability to the guest too, and if EPT is disabled we're not
1316 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1317 * require a nested hypervisor to do a flush of its own.
1318 */
1319 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1320 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1321
1322 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1323 data |= ARCH_CAP_RDCL_NO;
1324 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1325 data |= ARCH_CAP_SSB_NO;
1326 if (!boot_cpu_has_bug(X86_BUG_MDS))
1327 data |= ARCH_CAP_MDS_NO;
1328
1329 /*
1330 * On TAA affected systems:
1331 * - nothing to do if TSX is disabled on the host.
1332 * - we emulate TSX_CTRL if present on the host.
1333 * This lets the guest use VERW to clear CPU buffers.
1334 */
1335 if (!boot_cpu_has(X86_FEATURE_RTM))
1336 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1337 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1338 data |= ARCH_CAP_TAA_NO;
1339
1340 return data;
1341 }
1342
1343 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1344 {
1345 switch (msr->index) {
1346 case MSR_IA32_ARCH_CAPABILITIES:
1347 msr->data = kvm_get_arch_capabilities();
1348 break;
1349 case MSR_IA32_UCODE_REV:
1350 rdmsrl_safe(msr->index, &msr->data);
1351 break;
1352 default:
1353 if (kvm_x86_ops->get_msr_feature(msr))
1354 return 1;
1355 }
1356 return 0;
1357 }
1358
1359 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1360 {
1361 struct kvm_msr_entry msr;
1362 int r;
1363
1364 msr.index = index;
1365 r = kvm_get_msr_feature(&msr);
1366 if (r)
1367 return r;
1368
1369 *data = msr.data;
1370
1371 return 0;
1372 }
1373
1374 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1375 {
1376 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1377 return false;
1378
1379 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1380 return false;
1381
1382 if (efer & (EFER_LME | EFER_LMA) &&
1383 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1384 return false;
1385
1386 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1387 return false;
1388
1389 return true;
1390
1391 }
1392 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1393 {
1394 if (efer & efer_reserved_bits)
1395 return false;
1396
1397 return __kvm_valid_efer(vcpu, efer);
1398 }
1399 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1400
1401 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1402 {
1403 u64 old_efer = vcpu->arch.efer;
1404 u64 efer = msr_info->data;
1405
1406 if (efer & efer_reserved_bits)
1407 return 1;
1408
1409 if (!msr_info->host_initiated) {
1410 if (!__kvm_valid_efer(vcpu, efer))
1411 return 1;
1412
1413 if (is_paging(vcpu) &&
1414 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1415 return 1;
1416 }
1417
1418 efer &= ~EFER_LMA;
1419 efer |= vcpu->arch.efer & EFER_LMA;
1420
1421 kvm_x86_ops->set_efer(vcpu, efer);
1422
1423 /* Update reserved bits */
1424 if ((efer ^ old_efer) & EFER_NX)
1425 kvm_mmu_reset_context(vcpu);
1426
1427 return 0;
1428 }
1429
1430 void kvm_enable_efer_bits(u64 mask)
1431 {
1432 efer_reserved_bits &= ~mask;
1433 }
1434 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1435
1436 /*
1437 * Write @data into the MSR specified by @index. Select MSR specific fault
1438 * checks are bypassed if @host_initiated is %true.
1439 * Returns 0 on success, non-0 otherwise.
1440 * Assumes vcpu_load() was already called.
1441 */
1442 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1443 bool host_initiated)
1444 {
1445 struct msr_data msr;
1446
1447 switch (index) {
1448 case MSR_FS_BASE:
1449 case MSR_GS_BASE:
1450 case MSR_KERNEL_GS_BASE:
1451 case MSR_CSTAR:
1452 case MSR_LSTAR:
1453 if (is_noncanonical_address(data, vcpu))
1454 return 1;
1455 break;
1456 case MSR_IA32_SYSENTER_EIP:
1457 case MSR_IA32_SYSENTER_ESP:
1458 /*
1459 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1460 * non-canonical address is written on Intel but not on
1461 * AMD (which ignores the top 32-bits, because it does
1462 * not implement 64-bit SYSENTER).
1463 *
1464 * 64-bit code should hence be able to write a non-canonical
1465 * value on AMD. Making the address canonical ensures that
1466 * vmentry does not fail on Intel after writing a non-canonical
1467 * value, and that something deterministic happens if the guest
1468 * invokes 64-bit SYSENTER.
1469 */
1470 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1471 }
1472
1473 msr.data = data;
1474 msr.index = index;
1475 msr.host_initiated = host_initiated;
1476
1477 return kvm_x86_ops->set_msr(vcpu, &msr);
1478 }
1479
1480 /*
1481 * Read the MSR specified by @index into @data. Select MSR specific fault
1482 * checks are bypassed if @host_initiated is %true.
1483 * Returns 0 on success, non-0 otherwise.
1484 * Assumes vcpu_load() was already called.
1485 */
1486 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1487 bool host_initiated)
1488 {
1489 struct msr_data msr;
1490 int ret;
1491
1492 msr.index = index;
1493 msr.host_initiated = host_initiated;
1494
1495 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1496 if (!ret)
1497 *data = msr.data;
1498 return ret;
1499 }
1500
1501 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1502 {
1503 return __kvm_get_msr(vcpu, index, data, false);
1504 }
1505 EXPORT_SYMBOL_GPL(kvm_get_msr);
1506
1507 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1508 {
1509 return __kvm_set_msr(vcpu, index, data, false);
1510 }
1511 EXPORT_SYMBOL_GPL(kvm_set_msr);
1512
1513 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1514 {
1515 u32 ecx = kvm_rcx_read(vcpu);
1516 u64 data;
1517
1518 if (kvm_get_msr(vcpu, ecx, &data)) {
1519 trace_kvm_msr_read_ex(ecx);
1520 kvm_inject_gp(vcpu, 0);
1521 return 1;
1522 }
1523
1524 trace_kvm_msr_read(ecx, data);
1525
1526 kvm_rax_write(vcpu, data & -1u);
1527 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1528 return kvm_skip_emulated_instruction(vcpu);
1529 }
1530 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1531
1532 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1533 {
1534 u32 ecx = kvm_rcx_read(vcpu);
1535 u64 data = kvm_read_edx_eax(vcpu);
1536
1537 if (kvm_set_msr(vcpu, ecx, data)) {
1538 trace_kvm_msr_write_ex(ecx, data);
1539 kvm_inject_gp(vcpu, 0);
1540 return 1;
1541 }
1542
1543 trace_kvm_msr_write(ecx, data);
1544 return kvm_skip_emulated_instruction(vcpu);
1545 }
1546 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1547
1548 /*
1549 * The fast path for frequent and performance sensitive wrmsr emulation,
1550 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1551 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1552 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1553 * other cases which must be called after interrupts are enabled on the host.
1554 */
1555 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1556 {
1557 if (lapic_in_kernel(vcpu) && apic_x2apic_mode(vcpu->arch.apic) &&
1558 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1559 ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) {
1560
1561 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1562 return kvm_lapic_reg_write(vcpu->arch.apic, APIC_ICR, (u32)data);
1563 }
1564
1565 return 1;
1566 }
1567
1568 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1569 {
1570 u32 msr = kvm_rcx_read(vcpu);
1571 u64 data = kvm_read_edx_eax(vcpu);
1572 int ret = 0;
1573
1574 switch (msr) {
1575 case APIC_BASE_MSR + (APIC_ICR >> 4):
1576 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1577 break;
1578 default:
1579 return EXIT_FASTPATH_NONE;
1580 }
1581
1582 if (!ret) {
1583 trace_kvm_msr_write(msr, data);
1584 return EXIT_FASTPATH_SKIP_EMUL_INS;
1585 }
1586
1587 return EXIT_FASTPATH_NONE;
1588 }
1589 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1590
1591 /*
1592 * Adapt set_msr() to msr_io()'s calling convention
1593 */
1594 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1595 {
1596 return __kvm_get_msr(vcpu, index, data, true);
1597 }
1598
1599 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1600 {
1601 return __kvm_set_msr(vcpu, index, *data, true);
1602 }
1603
1604 #ifdef CONFIG_X86_64
1605 struct pvclock_clock {
1606 int vclock_mode;
1607 u64 cycle_last;
1608 u64 mask;
1609 u32 mult;
1610 u32 shift;
1611 u64 base_cycles;
1612 u64 offset;
1613 };
1614
1615 struct pvclock_gtod_data {
1616 seqcount_t seq;
1617
1618 struct pvclock_clock clock; /* extract of a clocksource struct */
1619 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1620
1621 ktime_t offs_boot;
1622 u64 wall_time_sec;
1623 };
1624
1625 static struct pvclock_gtod_data pvclock_gtod_data;
1626
1627 static void update_pvclock_gtod(struct timekeeper *tk)
1628 {
1629 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1630
1631 write_seqcount_begin(&vdata->seq);
1632
1633 /* copy pvclock gtod data */
1634 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1635 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1636 vdata->clock.mask = tk->tkr_mono.mask;
1637 vdata->clock.mult = tk->tkr_mono.mult;
1638 vdata->clock.shift = tk->tkr_mono.shift;
1639 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1640 vdata->clock.offset = tk->tkr_mono.base;
1641
1642 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->archdata.vclock_mode;
1643 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1644 vdata->raw_clock.mask = tk->tkr_raw.mask;
1645 vdata->raw_clock.mult = tk->tkr_raw.mult;
1646 vdata->raw_clock.shift = tk->tkr_raw.shift;
1647 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1648 vdata->raw_clock.offset = tk->tkr_raw.base;
1649
1650 vdata->wall_time_sec = tk->xtime_sec;
1651
1652 vdata->offs_boot = tk->offs_boot;
1653
1654 write_seqcount_end(&vdata->seq);
1655 }
1656
1657 static s64 get_kvmclock_base_ns(void)
1658 {
1659 /* Count up from boot time, but with the frequency of the raw clock. */
1660 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1661 }
1662 #else
1663 static s64 get_kvmclock_base_ns(void)
1664 {
1665 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1666 return ktime_get_boottime_ns();
1667 }
1668 #endif
1669
1670 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1671 {
1672 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1673 kvm_vcpu_kick(vcpu);
1674 }
1675
1676 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1677 {
1678 int version;
1679 int r;
1680 struct pvclock_wall_clock wc;
1681 u64 wall_nsec;
1682
1683 if (!wall_clock)
1684 return;
1685
1686 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1687 if (r)
1688 return;
1689
1690 if (version & 1)
1691 ++version; /* first time write, random junk */
1692
1693 ++version;
1694
1695 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1696 return;
1697
1698 /*
1699 * The guest calculates current wall clock time by adding
1700 * system time (updated by kvm_guest_time_update below) to the
1701 * wall clock specified here. We do the reverse here.
1702 */
1703 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1704
1705 wc.nsec = do_div(wall_nsec, 1000000000);
1706 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1707 wc.version = version;
1708
1709 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1710
1711 version++;
1712 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1713 }
1714
1715 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1716 {
1717 do_shl32_div32(dividend, divisor);
1718 return dividend;
1719 }
1720
1721 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1722 s8 *pshift, u32 *pmultiplier)
1723 {
1724 uint64_t scaled64;
1725 int32_t shift = 0;
1726 uint64_t tps64;
1727 uint32_t tps32;
1728
1729 tps64 = base_hz;
1730 scaled64 = scaled_hz;
1731 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1732 tps64 >>= 1;
1733 shift--;
1734 }
1735
1736 tps32 = (uint32_t)tps64;
1737 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1738 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1739 scaled64 >>= 1;
1740 else
1741 tps32 <<= 1;
1742 shift++;
1743 }
1744
1745 *pshift = shift;
1746 *pmultiplier = div_frac(scaled64, tps32);
1747 }
1748
1749 #ifdef CONFIG_X86_64
1750 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1751 #endif
1752
1753 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1754 static unsigned long max_tsc_khz;
1755
1756 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1757 {
1758 u64 v = (u64)khz * (1000000 + ppm);
1759 do_div(v, 1000000);
1760 return v;
1761 }
1762
1763 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1764 {
1765 u64 ratio;
1766
1767 /* Guest TSC same frequency as host TSC? */
1768 if (!scale) {
1769 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1770 return 0;
1771 }
1772
1773 /* TSC scaling supported? */
1774 if (!kvm_has_tsc_control) {
1775 if (user_tsc_khz > tsc_khz) {
1776 vcpu->arch.tsc_catchup = 1;
1777 vcpu->arch.tsc_always_catchup = 1;
1778 return 0;
1779 } else {
1780 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1781 return -1;
1782 }
1783 }
1784
1785 /* TSC scaling required - calculate ratio */
1786 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1787 user_tsc_khz, tsc_khz);
1788
1789 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1790 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1791 user_tsc_khz);
1792 return -1;
1793 }
1794
1795 vcpu->arch.tsc_scaling_ratio = ratio;
1796 return 0;
1797 }
1798
1799 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1800 {
1801 u32 thresh_lo, thresh_hi;
1802 int use_scaling = 0;
1803
1804 /* tsc_khz can be zero if TSC calibration fails */
1805 if (user_tsc_khz == 0) {
1806 /* set tsc_scaling_ratio to a safe value */
1807 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1808 return -1;
1809 }
1810
1811 /* Compute a scale to convert nanoseconds in TSC cycles */
1812 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1813 &vcpu->arch.virtual_tsc_shift,
1814 &vcpu->arch.virtual_tsc_mult);
1815 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1816
1817 /*
1818 * Compute the variation in TSC rate which is acceptable
1819 * within the range of tolerance and decide if the
1820 * rate being applied is within that bounds of the hardware
1821 * rate. If so, no scaling or compensation need be done.
1822 */
1823 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1824 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1825 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1826 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1827 use_scaling = 1;
1828 }
1829 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1830 }
1831
1832 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1833 {
1834 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1835 vcpu->arch.virtual_tsc_mult,
1836 vcpu->arch.virtual_tsc_shift);
1837 tsc += vcpu->arch.this_tsc_write;
1838 return tsc;
1839 }
1840
1841 static inline int gtod_is_based_on_tsc(int mode)
1842 {
1843 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1844 }
1845
1846 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1847 {
1848 #ifdef CONFIG_X86_64
1849 bool vcpus_matched;
1850 struct kvm_arch *ka = &vcpu->kvm->arch;
1851 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1852
1853 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1854 atomic_read(&vcpu->kvm->online_vcpus));
1855
1856 /*
1857 * Once the masterclock is enabled, always perform request in
1858 * order to update it.
1859 *
1860 * In order to enable masterclock, the host clocksource must be TSC
1861 * and the vcpus need to have matched TSCs. When that happens,
1862 * perform request to enable masterclock.
1863 */
1864 if (ka->use_master_clock ||
1865 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1866 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1867
1868 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1869 atomic_read(&vcpu->kvm->online_vcpus),
1870 ka->use_master_clock, gtod->clock.vclock_mode);
1871 #endif
1872 }
1873
1874 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1875 {
1876 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1877 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1878 }
1879
1880 /*
1881 * Multiply tsc by a fixed point number represented by ratio.
1882 *
1883 * The most significant 64-N bits (mult) of ratio represent the
1884 * integral part of the fixed point number; the remaining N bits
1885 * (frac) represent the fractional part, ie. ratio represents a fixed
1886 * point number (mult + frac * 2^(-N)).
1887 *
1888 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1889 */
1890 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1891 {
1892 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1893 }
1894
1895 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1896 {
1897 u64 _tsc = tsc;
1898 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1899
1900 if (ratio != kvm_default_tsc_scaling_ratio)
1901 _tsc = __scale_tsc(ratio, tsc);
1902
1903 return _tsc;
1904 }
1905 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1906
1907 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1908 {
1909 u64 tsc;
1910
1911 tsc = kvm_scale_tsc(vcpu, rdtsc());
1912
1913 return target_tsc - tsc;
1914 }
1915
1916 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1917 {
1918 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1919
1920 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1921 }
1922 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1923
1924 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1925 {
1926 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1927 }
1928
1929 static inline bool kvm_check_tsc_unstable(void)
1930 {
1931 #ifdef CONFIG_X86_64
1932 /*
1933 * TSC is marked unstable when we're running on Hyper-V,
1934 * 'TSC page' clocksource is good.
1935 */
1936 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1937 return false;
1938 #endif
1939 return check_tsc_unstable();
1940 }
1941
1942 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1943 {
1944 struct kvm *kvm = vcpu->kvm;
1945 u64 offset, ns, elapsed;
1946 unsigned long flags;
1947 bool matched;
1948 bool already_matched;
1949 u64 data = msr->data;
1950 bool synchronizing = false;
1951
1952 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1953 offset = kvm_compute_tsc_offset(vcpu, data);
1954 ns = get_kvmclock_base_ns();
1955 elapsed = ns - kvm->arch.last_tsc_nsec;
1956
1957 if (vcpu->arch.virtual_tsc_khz) {
1958 if (data == 0 && msr->host_initiated) {
1959 /*
1960 * detection of vcpu initialization -- need to sync
1961 * with other vCPUs. This particularly helps to keep
1962 * kvm_clock stable after CPU hotplug
1963 */
1964 synchronizing = true;
1965 } else {
1966 u64 tsc_exp = kvm->arch.last_tsc_write +
1967 nsec_to_cycles(vcpu, elapsed);
1968 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1969 /*
1970 * Special case: TSC write with a small delta (1 second)
1971 * of virtual cycle time against real time is
1972 * interpreted as an attempt to synchronize the CPU.
1973 */
1974 synchronizing = data < tsc_exp + tsc_hz &&
1975 data + tsc_hz > tsc_exp;
1976 }
1977 }
1978
1979 /*
1980 * For a reliable TSC, we can match TSC offsets, and for an unstable
1981 * TSC, we add elapsed time in this computation. We could let the
1982 * compensation code attempt to catch up if we fall behind, but
1983 * it's better to try to match offsets from the beginning.
1984 */
1985 if (synchronizing &&
1986 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1987 if (!kvm_check_tsc_unstable()) {
1988 offset = kvm->arch.cur_tsc_offset;
1989 } else {
1990 u64 delta = nsec_to_cycles(vcpu, elapsed);
1991 data += delta;
1992 offset = kvm_compute_tsc_offset(vcpu, data);
1993 }
1994 matched = true;
1995 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1996 } else {
1997 /*
1998 * We split periods of matched TSC writes into generations.
1999 * For each generation, we track the original measured
2000 * nanosecond time, offset, and write, so if TSCs are in
2001 * sync, we can match exact offset, and if not, we can match
2002 * exact software computation in compute_guest_tsc()
2003 *
2004 * These values are tracked in kvm->arch.cur_xxx variables.
2005 */
2006 kvm->arch.cur_tsc_generation++;
2007 kvm->arch.cur_tsc_nsec = ns;
2008 kvm->arch.cur_tsc_write = data;
2009 kvm->arch.cur_tsc_offset = offset;
2010 matched = false;
2011 }
2012
2013 /*
2014 * We also track th most recent recorded KHZ, write and time to
2015 * allow the matching interval to be extended at each write.
2016 */
2017 kvm->arch.last_tsc_nsec = ns;
2018 kvm->arch.last_tsc_write = data;
2019 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2020
2021 vcpu->arch.last_guest_tsc = data;
2022
2023 /* Keep track of which generation this VCPU has synchronized to */
2024 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2025 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2026 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2027
2028 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2029 update_ia32_tsc_adjust_msr(vcpu, offset);
2030
2031 kvm_vcpu_write_tsc_offset(vcpu, offset);
2032 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2033
2034 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2035 if (!matched) {
2036 kvm->arch.nr_vcpus_matched_tsc = 0;
2037 } else if (!already_matched) {
2038 kvm->arch.nr_vcpus_matched_tsc++;
2039 }
2040
2041 kvm_track_tsc_matching(vcpu);
2042 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2043 }
2044
2045 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2046
2047 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2048 s64 adjustment)
2049 {
2050 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
2051 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2052 }
2053
2054 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2055 {
2056 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2057 WARN_ON(adjustment < 0);
2058 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2059 adjust_tsc_offset_guest(vcpu, adjustment);
2060 }
2061
2062 #ifdef CONFIG_X86_64
2063
2064 static u64 read_tsc(void)
2065 {
2066 u64 ret = (u64)rdtsc_ordered();
2067 u64 last = pvclock_gtod_data.clock.cycle_last;
2068
2069 if (likely(ret >= last))
2070 return ret;
2071
2072 /*
2073 * GCC likes to generate cmov here, but this branch is extremely
2074 * predictable (it's just a function of time and the likely is
2075 * very likely) and there's a data dependence, so force GCC
2076 * to generate a branch instead. I don't barrier() because
2077 * we don't actually need a barrier, and if this function
2078 * ever gets inlined it will generate worse code.
2079 */
2080 asm volatile ("");
2081 return last;
2082 }
2083
2084 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2085 int *mode)
2086 {
2087 long v;
2088 u64 tsc_pg_val;
2089
2090 switch (clock->vclock_mode) {
2091 case VCLOCK_HVCLOCK:
2092 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2093 tsc_timestamp);
2094 if (tsc_pg_val != U64_MAX) {
2095 /* TSC page valid */
2096 *mode = VCLOCK_HVCLOCK;
2097 v = (tsc_pg_val - clock->cycle_last) &
2098 clock->mask;
2099 } else {
2100 /* TSC page invalid */
2101 *mode = VCLOCK_NONE;
2102 }
2103 break;
2104 case VCLOCK_TSC:
2105 *mode = VCLOCK_TSC;
2106 *tsc_timestamp = read_tsc();
2107 v = (*tsc_timestamp - clock->cycle_last) &
2108 clock->mask;
2109 break;
2110 default:
2111 *mode = VCLOCK_NONE;
2112 }
2113
2114 if (*mode == VCLOCK_NONE)
2115 *tsc_timestamp = v = 0;
2116
2117 return v * clock->mult;
2118 }
2119
2120 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2121 {
2122 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2123 unsigned long seq;
2124 int mode;
2125 u64 ns;
2126
2127 do {
2128 seq = read_seqcount_begin(&gtod->seq);
2129 ns = gtod->raw_clock.base_cycles;
2130 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2131 ns >>= gtod->raw_clock.shift;
2132 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2133 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2134 *t = ns;
2135
2136 return mode;
2137 }
2138
2139 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2140 {
2141 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2142 unsigned long seq;
2143 int mode;
2144 u64 ns;
2145
2146 do {
2147 seq = read_seqcount_begin(&gtod->seq);
2148 ts->tv_sec = gtod->wall_time_sec;
2149 ns = gtod->clock.base_cycles;
2150 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2151 ns >>= gtod->clock.shift;
2152 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2153
2154 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2155 ts->tv_nsec = ns;
2156
2157 return mode;
2158 }
2159
2160 /* returns true if host is using TSC based clocksource */
2161 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2162 {
2163 /* checked again under seqlock below */
2164 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2165 return false;
2166
2167 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2168 tsc_timestamp));
2169 }
2170
2171 /* returns true if host is using TSC based clocksource */
2172 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2173 u64 *tsc_timestamp)
2174 {
2175 /* checked again under seqlock below */
2176 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2177 return false;
2178
2179 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2180 }
2181 #endif
2182
2183 /*
2184 *
2185 * Assuming a stable TSC across physical CPUS, and a stable TSC
2186 * across virtual CPUs, the following condition is possible.
2187 * Each numbered line represents an event visible to both
2188 * CPUs at the next numbered event.
2189 *
2190 * "timespecX" represents host monotonic time. "tscX" represents
2191 * RDTSC value.
2192 *
2193 * VCPU0 on CPU0 | VCPU1 on CPU1
2194 *
2195 * 1. read timespec0,tsc0
2196 * 2. | timespec1 = timespec0 + N
2197 * | tsc1 = tsc0 + M
2198 * 3. transition to guest | transition to guest
2199 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2200 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2201 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2202 *
2203 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2204 *
2205 * - ret0 < ret1
2206 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2207 * ...
2208 * - 0 < N - M => M < N
2209 *
2210 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2211 * always the case (the difference between two distinct xtime instances
2212 * might be smaller then the difference between corresponding TSC reads,
2213 * when updating guest vcpus pvclock areas).
2214 *
2215 * To avoid that problem, do not allow visibility of distinct
2216 * system_timestamp/tsc_timestamp values simultaneously: use a master
2217 * copy of host monotonic time values. Update that master copy
2218 * in lockstep.
2219 *
2220 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2221 *
2222 */
2223
2224 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2225 {
2226 #ifdef CONFIG_X86_64
2227 struct kvm_arch *ka = &kvm->arch;
2228 int vclock_mode;
2229 bool host_tsc_clocksource, vcpus_matched;
2230
2231 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2232 atomic_read(&kvm->online_vcpus));
2233
2234 /*
2235 * If the host uses TSC clock, then passthrough TSC as stable
2236 * to the guest.
2237 */
2238 host_tsc_clocksource = kvm_get_time_and_clockread(
2239 &ka->master_kernel_ns,
2240 &ka->master_cycle_now);
2241
2242 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2243 && !ka->backwards_tsc_observed
2244 && !ka->boot_vcpu_runs_old_kvmclock;
2245
2246 if (ka->use_master_clock)
2247 atomic_set(&kvm_guest_has_master_clock, 1);
2248
2249 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2250 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2251 vcpus_matched);
2252 #endif
2253 }
2254
2255 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2256 {
2257 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2258 }
2259
2260 static void kvm_gen_update_masterclock(struct kvm *kvm)
2261 {
2262 #ifdef CONFIG_X86_64
2263 int i;
2264 struct kvm_vcpu *vcpu;
2265 struct kvm_arch *ka = &kvm->arch;
2266
2267 spin_lock(&ka->pvclock_gtod_sync_lock);
2268 kvm_make_mclock_inprogress_request(kvm);
2269 /* no guest entries from this point */
2270 pvclock_update_vm_gtod_copy(kvm);
2271
2272 kvm_for_each_vcpu(i, vcpu, kvm)
2273 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2274
2275 /* guest entries allowed */
2276 kvm_for_each_vcpu(i, vcpu, kvm)
2277 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2278
2279 spin_unlock(&ka->pvclock_gtod_sync_lock);
2280 #endif
2281 }
2282
2283 u64 get_kvmclock_ns(struct kvm *kvm)
2284 {
2285 struct kvm_arch *ka = &kvm->arch;
2286 struct pvclock_vcpu_time_info hv_clock;
2287 u64 ret;
2288
2289 spin_lock(&ka->pvclock_gtod_sync_lock);
2290 if (!ka->use_master_clock) {
2291 spin_unlock(&ka->pvclock_gtod_sync_lock);
2292 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2293 }
2294
2295 hv_clock.tsc_timestamp = ka->master_cycle_now;
2296 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2297 spin_unlock(&ka->pvclock_gtod_sync_lock);
2298
2299 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2300 get_cpu();
2301
2302 if (__this_cpu_read(cpu_tsc_khz)) {
2303 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2304 &hv_clock.tsc_shift,
2305 &hv_clock.tsc_to_system_mul);
2306 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2307 } else
2308 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2309
2310 put_cpu();
2311
2312 return ret;
2313 }
2314
2315 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2316 {
2317 struct kvm_vcpu_arch *vcpu = &v->arch;
2318 struct pvclock_vcpu_time_info guest_hv_clock;
2319
2320 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2321 &guest_hv_clock, sizeof(guest_hv_clock))))
2322 return;
2323
2324 /* This VCPU is paused, but it's legal for a guest to read another
2325 * VCPU's kvmclock, so we really have to follow the specification where
2326 * it says that version is odd if data is being modified, and even after
2327 * it is consistent.
2328 *
2329 * Version field updates must be kept separate. This is because
2330 * kvm_write_guest_cached might use a "rep movs" instruction, and
2331 * writes within a string instruction are weakly ordered. So there
2332 * are three writes overall.
2333 *
2334 * As a small optimization, only write the version field in the first
2335 * and third write. The vcpu->pv_time cache is still valid, because the
2336 * version field is the first in the struct.
2337 */
2338 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2339
2340 if (guest_hv_clock.version & 1)
2341 ++guest_hv_clock.version; /* first time write, random junk */
2342
2343 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2344 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2345 &vcpu->hv_clock,
2346 sizeof(vcpu->hv_clock.version));
2347
2348 smp_wmb();
2349
2350 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2351 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2352
2353 if (vcpu->pvclock_set_guest_stopped_request) {
2354 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2355 vcpu->pvclock_set_guest_stopped_request = false;
2356 }
2357
2358 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2359
2360 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2361 &vcpu->hv_clock,
2362 sizeof(vcpu->hv_clock));
2363
2364 smp_wmb();
2365
2366 vcpu->hv_clock.version++;
2367 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2368 &vcpu->hv_clock,
2369 sizeof(vcpu->hv_clock.version));
2370 }
2371
2372 static int kvm_guest_time_update(struct kvm_vcpu *v)
2373 {
2374 unsigned long flags, tgt_tsc_khz;
2375 struct kvm_vcpu_arch *vcpu = &v->arch;
2376 struct kvm_arch *ka = &v->kvm->arch;
2377 s64 kernel_ns;
2378 u64 tsc_timestamp, host_tsc;
2379 u8 pvclock_flags;
2380 bool use_master_clock;
2381
2382 kernel_ns = 0;
2383 host_tsc = 0;
2384
2385 /*
2386 * If the host uses TSC clock, then passthrough TSC as stable
2387 * to the guest.
2388 */
2389 spin_lock(&ka->pvclock_gtod_sync_lock);
2390 use_master_clock = ka->use_master_clock;
2391 if (use_master_clock) {
2392 host_tsc = ka->master_cycle_now;
2393 kernel_ns = ka->master_kernel_ns;
2394 }
2395 spin_unlock(&ka->pvclock_gtod_sync_lock);
2396
2397 /* Keep irq disabled to prevent changes to the clock */
2398 local_irq_save(flags);
2399 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2400 if (unlikely(tgt_tsc_khz == 0)) {
2401 local_irq_restore(flags);
2402 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2403 return 1;
2404 }
2405 if (!use_master_clock) {
2406 host_tsc = rdtsc();
2407 kernel_ns = get_kvmclock_base_ns();
2408 }
2409
2410 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2411
2412 /*
2413 * We may have to catch up the TSC to match elapsed wall clock
2414 * time for two reasons, even if kvmclock is used.
2415 * 1) CPU could have been running below the maximum TSC rate
2416 * 2) Broken TSC compensation resets the base at each VCPU
2417 * entry to avoid unknown leaps of TSC even when running
2418 * again on the same CPU. This may cause apparent elapsed
2419 * time to disappear, and the guest to stand still or run
2420 * very slowly.
2421 */
2422 if (vcpu->tsc_catchup) {
2423 u64 tsc = compute_guest_tsc(v, kernel_ns);
2424 if (tsc > tsc_timestamp) {
2425 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2426 tsc_timestamp = tsc;
2427 }
2428 }
2429
2430 local_irq_restore(flags);
2431
2432 /* With all the info we got, fill in the values */
2433
2434 if (kvm_has_tsc_control)
2435 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2436
2437 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2438 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2439 &vcpu->hv_clock.tsc_shift,
2440 &vcpu->hv_clock.tsc_to_system_mul);
2441 vcpu->hw_tsc_khz = tgt_tsc_khz;
2442 }
2443
2444 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2445 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2446 vcpu->last_guest_tsc = tsc_timestamp;
2447 WARN_ON((s64)vcpu->hv_clock.system_time < 0);
2448
2449 /* If the host uses TSC clocksource, then it is stable */
2450 pvclock_flags = 0;
2451 if (use_master_clock)
2452 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2453
2454 vcpu->hv_clock.flags = pvclock_flags;
2455
2456 if (vcpu->pv_time_enabled)
2457 kvm_setup_pvclock_page(v);
2458 if (v == kvm_get_vcpu(v->kvm, 0))
2459 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2460 return 0;
2461 }
2462
2463 /*
2464 * kvmclock updates which are isolated to a given vcpu, such as
2465 * vcpu->cpu migration, should not allow system_timestamp from
2466 * the rest of the vcpus to remain static. Otherwise ntp frequency
2467 * correction applies to one vcpu's system_timestamp but not
2468 * the others.
2469 *
2470 * So in those cases, request a kvmclock update for all vcpus.
2471 * We need to rate-limit these requests though, as they can
2472 * considerably slow guests that have a large number of vcpus.
2473 * The time for a remote vcpu to update its kvmclock is bound
2474 * by the delay we use to rate-limit the updates.
2475 */
2476
2477 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2478
2479 static void kvmclock_update_fn(struct work_struct *work)
2480 {
2481 int i;
2482 struct delayed_work *dwork = to_delayed_work(work);
2483 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2484 kvmclock_update_work);
2485 struct kvm *kvm = container_of(ka, struct kvm, arch);
2486 struct kvm_vcpu *vcpu;
2487
2488 kvm_for_each_vcpu(i, vcpu, kvm) {
2489 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2490 kvm_vcpu_kick(vcpu);
2491 }
2492 }
2493
2494 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2495 {
2496 struct kvm *kvm = v->kvm;
2497
2498 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2499 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2500 KVMCLOCK_UPDATE_DELAY);
2501 }
2502
2503 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2504
2505 static void kvmclock_sync_fn(struct work_struct *work)
2506 {
2507 struct delayed_work *dwork = to_delayed_work(work);
2508 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2509 kvmclock_sync_work);
2510 struct kvm *kvm = container_of(ka, struct kvm, arch);
2511
2512 if (!kvmclock_periodic_sync)
2513 return;
2514
2515 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2516 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2517 KVMCLOCK_SYNC_PERIOD);
2518 }
2519
2520 /*
2521 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2522 */
2523 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2524 {
2525 /* McStatusWrEn enabled? */
2526 if (guest_cpuid_is_amd(vcpu))
2527 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2528
2529 return false;
2530 }
2531
2532 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2533 {
2534 u64 mcg_cap = vcpu->arch.mcg_cap;
2535 unsigned bank_num = mcg_cap & 0xff;
2536 u32 msr = msr_info->index;
2537 u64 data = msr_info->data;
2538
2539 switch (msr) {
2540 case MSR_IA32_MCG_STATUS:
2541 vcpu->arch.mcg_status = data;
2542 break;
2543 case MSR_IA32_MCG_CTL:
2544 if (!(mcg_cap & MCG_CTL_P) &&
2545 (data || !msr_info->host_initiated))
2546 return 1;
2547 if (data != 0 && data != ~(u64)0)
2548 return 1;
2549 vcpu->arch.mcg_ctl = data;
2550 break;
2551 default:
2552 if (msr >= MSR_IA32_MC0_CTL &&
2553 msr < MSR_IA32_MCx_CTL(bank_num)) {
2554 u32 offset = array_index_nospec(
2555 msr - MSR_IA32_MC0_CTL,
2556 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2557
2558 /* only 0 or all 1s can be written to IA32_MCi_CTL
2559 * some Linux kernels though clear bit 10 in bank 4 to
2560 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2561 * this to avoid an uncatched #GP in the guest
2562 */
2563 if ((offset & 0x3) == 0 &&
2564 data != 0 && (data | (1 << 10)) != ~(u64)0)
2565 return -1;
2566
2567 /* MCi_STATUS */
2568 if (!msr_info->host_initiated &&
2569 (offset & 0x3) == 1 && data != 0) {
2570 if (!can_set_mci_status(vcpu))
2571 return -1;
2572 }
2573
2574 vcpu->arch.mce_banks[offset] = data;
2575 break;
2576 }
2577 return 1;
2578 }
2579 return 0;
2580 }
2581
2582 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2583 {
2584 struct kvm *kvm = vcpu->kvm;
2585 int lm = is_long_mode(vcpu);
2586 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2587 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2588 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2589 : kvm->arch.xen_hvm_config.blob_size_32;
2590 u32 page_num = data & ~PAGE_MASK;
2591 u64 page_addr = data & PAGE_MASK;
2592 u8 *page;
2593 int r;
2594
2595 r = -E2BIG;
2596 if (page_num >= blob_size)
2597 goto out;
2598 r = -ENOMEM;
2599 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2600 if (IS_ERR(page)) {
2601 r = PTR_ERR(page);
2602 goto out;
2603 }
2604 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2605 goto out_free;
2606 r = 0;
2607 out_free:
2608 kfree(page);
2609 out:
2610 return r;
2611 }
2612
2613 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2614 {
2615 gpa_t gpa = data & ~0x3f;
2616
2617 /* Bits 3:5 are reserved, Should be zero */
2618 if (data & 0x38)
2619 return 1;
2620
2621 vcpu->arch.apf.msr_val = data;
2622
2623 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2624 kvm_clear_async_pf_completion_queue(vcpu);
2625 kvm_async_pf_hash_reset(vcpu);
2626 return 0;
2627 }
2628
2629 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2630 sizeof(u32)))
2631 return 1;
2632
2633 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2634 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2635 kvm_async_pf_wakeup_all(vcpu);
2636 return 0;
2637 }
2638
2639 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2640 {
2641 vcpu->arch.pv_time_enabled = false;
2642 vcpu->arch.time = 0;
2643 }
2644
2645 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2646 {
2647 ++vcpu->stat.tlb_flush;
2648 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2649 }
2650
2651 static void record_steal_time(struct kvm_vcpu *vcpu)
2652 {
2653 struct kvm_host_map map;
2654 struct kvm_steal_time *st;
2655
2656 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2657 return;
2658
2659 /* -EAGAIN is returned in atomic context so we can just return. */
2660 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2661 &map, &vcpu->arch.st.cache, false))
2662 return;
2663
2664 st = map.hva +
2665 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2666
2667 /*
2668 * Doing a TLB flush here, on the guest's behalf, can avoid
2669 * expensive IPIs.
2670 */
2671 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2672 st->preempted & KVM_VCPU_FLUSH_TLB);
2673 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2674 kvm_vcpu_flush_tlb(vcpu, false);
2675
2676 vcpu->arch.st.preempted = 0;
2677
2678 if (st->version & 1)
2679 st->version += 1; /* first time write, random junk */
2680
2681 st->version += 1;
2682
2683 smp_wmb();
2684
2685 st->steal += current->sched_info.run_delay -
2686 vcpu->arch.st.last_steal;
2687 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2688
2689 smp_wmb();
2690
2691 st->version += 1;
2692
2693 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2694 }
2695
2696 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2697 {
2698 bool pr = false;
2699 u32 msr = msr_info->index;
2700 u64 data = msr_info->data;
2701
2702 switch (msr) {
2703 case MSR_AMD64_NB_CFG:
2704 case MSR_IA32_UCODE_WRITE:
2705 case MSR_VM_HSAVE_PA:
2706 case MSR_AMD64_PATCH_LOADER:
2707 case MSR_AMD64_BU_CFG2:
2708 case MSR_AMD64_DC_CFG:
2709 case MSR_F15H_EX_CFG:
2710 break;
2711
2712 case MSR_IA32_UCODE_REV:
2713 if (msr_info->host_initiated)
2714 vcpu->arch.microcode_version = data;
2715 break;
2716 case MSR_IA32_ARCH_CAPABILITIES:
2717 if (!msr_info->host_initiated)
2718 return 1;
2719 vcpu->arch.arch_capabilities = data;
2720 break;
2721 case MSR_EFER:
2722 return set_efer(vcpu, msr_info);
2723 case MSR_K7_HWCR:
2724 data &= ~(u64)0x40; /* ignore flush filter disable */
2725 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2726 data &= ~(u64)0x8; /* ignore TLB cache disable */
2727
2728 /* Handle McStatusWrEn */
2729 if (data == BIT_ULL(18)) {
2730 vcpu->arch.msr_hwcr = data;
2731 } else if (data != 0) {
2732 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2733 data);
2734 return 1;
2735 }
2736 break;
2737 case MSR_FAM10H_MMIO_CONF_BASE:
2738 if (data != 0) {
2739 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2740 "0x%llx\n", data);
2741 return 1;
2742 }
2743 break;
2744 case MSR_IA32_DEBUGCTLMSR:
2745 if (!data) {
2746 /* We support the non-activated case already */
2747 break;
2748 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2749 /* Values other than LBR and BTF are vendor-specific,
2750 thus reserved and should throw a #GP */
2751 return 1;
2752 }
2753 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2754 __func__, data);
2755 break;
2756 case 0x200 ... 0x2ff:
2757 return kvm_mtrr_set_msr(vcpu, msr, data);
2758 case MSR_IA32_APICBASE:
2759 return kvm_set_apic_base(vcpu, msr_info);
2760 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2761 return kvm_x2apic_msr_write(vcpu, msr, data);
2762 case MSR_IA32_TSCDEADLINE:
2763 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2764 break;
2765 case MSR_IA32_TSC_ADJUST:
2766 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2767 if (!msr_info->host_initiated) {
2768 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2769 adjust_tsc_offset_guest(vcpu, adj);
2770 }
2771 vcpu->arch.ia32_tsc_adjust_msr = data;
2772 }
2773 break;
2774 case MSR_IA32_MISC_ENABLE:
2775 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2776 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2777 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2778 return 1;
2779 vcpu->arch.ia32_misc_enable_msr = data;
2780 kvm_update_cpuid(vcpu);
2781 } else {
2782 vcpu->arch.ia32_misc_enable_msr = data;
2783 }
2784 break;
2785 case MSR_IA32_SMBASE:
2786 if (!msr_info->host_initiated)
2787 return 1;
2788 vcpu->arch.smbase = data;
2789 break;
2790 case MSR_IA32_POWER_CTL:
2791 vcpu->arch.msr_ia32_power_ctl = data;
2792 break;
2793 case MSR_IA32_TSC:
2794 kvm_write_tsc(vcpu, msr_info);
2795 break;
2796 case MSR_IA32_XSS:
2797 if (!msr_info->host_initiated &&
2798 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2799 return 1;
2800 /*
2801 * We do support PT if kvm_x86_ops->pt_supported(), but we do
2802 * not support IA32_XSS[bit 8]. Guests will have to use
2803 * RDMSR/WRMSR rather than XSAVES/XRSTORS to save/restore PT
2804 * MSRs.
2805 */
2806 if (data != 0)
2807 return 1;
2808 vcpu->arch.ia32_xss = data;
2809 break;
2810 case MSR_SMI_COUNT:
2811 if (!msr_info->host_initiated)
2812 return 1;
2813 vcpu->arch.smi_count = data;
2814 break;
2815 case MSR_KVM_WALL_CLOCK_NEW:
2816 case MSR_KVM_WALL_CLOCK:
2817 vcpu->kvm->arch.wall_clock = data;
2818 kvm_write_wall_clock(vcpu->kvm, data);
2819 break;
2820 case MSR_KVM_SYSTEM_TIME_NEW:
2821 case MSR_KVM_SYSTEM_TIME: {
2822 struct kvm_arch *ka = &vcpu->kvm->arch;
2823
2824 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2825 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2826
2827 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2828 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2829
2830 ka->boot_vcpu_runs_old_kvmclock = tmp;
2831 }
2832
2833 vcpu->arch.time = data;
2834 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2835
2836 /* we verify if the enable bit is set... */
2837 vcpu->arch.pv_time_enabled = false;
2838 if (!(data & 1))
2839 break;
2840
2841 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2842 &vcpu->arch.pv_time, data & ~1ULL,
2843 sizeof(struct pvclock_vcpu_time_info)))
2844 vcpu->arch.pv_time_enabled = true;
2845
2846 break;
2847 }
2848 case MSR_KVM_ASYNC_PF_EN:
2849 if (kvm_pv_enable_async_pf(vcpu, data))
2850 return 1;
2851 break;
2852 case MSR_KVM_STEAL_TIME:
2853
2854 if (unlikely(!sched_info_on()))
2855 return 1;
2856
2857 if (data & KVM_STEAL_RESERVED_MASK)
2858 return 1;
2859
2860 vcpu->arch.st.msr_val = data;
2861
2862 if (!(data & KVM_MSR_ENABLED))
2863 break;
2864
2865 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2866
2867 break;
2868 case MSR_KVM_PV_EOI_EN:
2869 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2870 return 1;
2871 break;
2872
2873 case MSR_KVM_POLL_CONTROL:
2874 /* only enable bit supported */
2875 if (data & (-1ULL << 1))
2876 return 1;
2877
2878 vcpu->arch.msr_kvm_poll_control = data;
2879 break;
2880
2881 case MSR_IA32_MCG_CTL:
2882 case MSR_IA32_MCG_STATUS:
2883 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2884 return set_msr_mce(vcpu, msr_info);
2885
2886 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2887 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2888 pr = true; /* fall through */
2889 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2890 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2891 if (kvm_pmu_is_valid_msr(vcpu, msr))
2892 return kvm_pmu_set_msr(vcpu, msr_info);
2893
2894 if (pr || data != 0)
2895 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2896 "0x%x data 0x%llx\n", msr, data);
2897 break;
2898 case MSR_K7_CLK_CTL:
2899 /*
2900 * Ignore all writes to this no longer documented MSR.
2901 * Writes are only relevant for old K7 processors,
2902 * all pre-dating SVM, but a recommended workaround from
2903 * AMD for these chips. It is possible to specify the
2904 * affected processor models on the command line, hence
2905 * the need to ignore the workaround.
2906 */
2907 break;
2908 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2909 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2910 case HV_X64_MSR_CRASH_CTL:
2911 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2912 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2913 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2914 case HV_X64_MSR_TSC_EMULATION_STATUS:
2915 return kvm_hv_set_msr_common(vcpu, msr, data,
2916 msr_info->host_initiated);
2917 case MSR_IA32_BBL_CR_CTL3:
2918 /* Drop writes to this legacy MSR -- see rdmsr
2919 * counterpart for further detail.
2920 */
2921 if (report_ignored_msrs)
2922 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2923 msr, data);
2924 break;
2925 case MSR_AMD64_OSVW_ID_LENGTH:
2926 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2927 return 1;
2928 vcpu->arch.osvw.length = data;
2929 break;
2930 case MSR_AMD64_OSVW_STATUS:
2931 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2932 return 1;
2933 vcpu->arch.osvw.status = data;
2934 break;
2935 case MSR_PLATFORM_INFO:
2936 if (!msr_info->host_initiated ||
2937 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2938 cpuid_fault_enabled(vcpu)))
2939 return 1;
2940 vcpu->arch.msr_platform_info = data;
2941 break;
2942 case MSR_MISC_FEATURES_ENABLES:
2943 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2944 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2945 !supports_cpuid_fault(vcpu)))
2946 return 1;
2947 vcpu->arch.msr_misc_features_enables = data;
2948 break;
2949 default:
2950 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2951 return xen_hvm_config(vcpu, data);
2952 if (kvm_pmu_is_valid_msr(vcpu, msr))
2953 return kvm_pmu_set_msr(vcpu, msr_info);
2954 if (!ignore_msrs) {
2955 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2956 msr, data);
2957 return 1;
2958 } else {
2959 if (report_ignored_msrs)
2960 vcpu_unimpl(vcpu,
2961 "ignored wrmsr: 0x%x data 0x%llx\n",
2962 msr, data);
2963 break;
2964 }
2965 }
2966 return 0;
2967 }
2968 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2969
2970 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2971 {
2972 u64 data;
2973 u64 mcg_cap = vcpu->arch.mcg_cap;
2974 unsigned bank_num = mcg_cap & 0xff;
2975
2976 switch (msr) {
2977 case MSR_IA32_P5_MC_ADDR:
2978 case MSR_IA32_P5_MC_TYPE:
2979 data = 0;
2980 break;
2981 case MSR_IA32_MCG_CAP:
2982 data = vcpu->arch.mcg_cap;
2983 break;
2984 case MSR_IA32_MCG_CTL:
2985 if (!(mcg_cap & MCG_CTL_P) && !host)
2986 return 1;
2987 data = vcpu->arch.mcg_ctl;
2988 break;
2989 case MSR_IA32_MCG_STATUS:
2990 data = vcpu->arch.mcg_status;
2991 break;
2992 default:
2993 if (msr >= MSR_IA32_MC0_CTL &&
2994 msr < MSR_IA32_MCx_CTL(bank_num)) {
2995 u32 offset = array_index_nospec(
2996 msr - MSR_IA32_MC0_CTL,
2997 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2998
2999 data = vcpu->arch.mce_banks[offset];
3000 break;
3001 }
3002 return 1;
3003 }
3004 *pdata = data;
3005 return 0;
3006 }
3007
3008 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3009 {
3010 switch (msr_info->index) {
3011 case MSR_IA32_PLATFORM_ID:
3012 case MSR_IA32_EBL_CR_POWERON:
3013 case MSR_IA32_DEBUGCTLMSR:
3014 case MSR_IA32_LASTBRANCHFROMIP:
3015 case MSR_IA32_LASTBRANCHTOIP:
3016 case MSR_IA32_LASTINTFROMIP:
3017 case MSR_IA32_LASTINTTOIP:
3018 case MSR_K8_SYSCFG:
3019 case MSR_K8_TSEG_ADDR:
3020 case MSR_K8_TSEG_MASK:
3021 case MSR_VM_HSAVE_PA:
3022 case MSR_K8_INT_PENDING_MSG:
3023 case MSR_AMD64_NB_CFG:
3024 case MSR_FAM10H_MMIO_CONF_BASE:
3025 case MSR_AMD64_BU_CFG2:
3026 case MSR_IA32_PERF_CTL:
3027 case MSR_AMD64_DC_CFG:
3028 case MSR_F15H_EX_CFG:
3029 msr_info->data = 0;
3030 break;
3031 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3032 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3033 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3034 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3035 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3036 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3037 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3038 msr_info->data = 0;
3039 break;
3040 case MSR_IA32_UCODE_REV:
3041 msr_info->data = vcpu->arch.microcode_version;
3042 break;
3043 case MSR_IA32_ARCH_CAPABILITIES:
3044 if (!msr_info->host_initiated &&
3045 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3046 return 1;
3047 msr_info->data = vcpu->arch.arch_capabilities;
3048 break;
3049 case MSR_IA32_POWER_CTL:
3050 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3051 break;
3052 case MSR_IA32_TSC:
3053 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3054 break;
3055 case MSR_MTRRcap:
3056 case 0x200 ... 0x2ff:
3057 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3058 case 0xcd: /* fsb frequency */
3059 msr_info->data = 3;
3060 break;
3061 /*
3062 * MSR_EBC_FREQUENCY_ID
3063 * Conservative value valid for even the basic CPU models.
3064 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3065 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3066 * and 266MHz for model 3, or 4. Set Core Clock
3067 * Frequency to System Bus Frequency Ratio to 1 (bits
3068 * 31:24) even though these are only valid for CPU
3069 * models > 2, however guests may end up dividing or
3070 * multiplying by zero otherwise.
3071 */
3072 case MSR_EBC_FREQUENCY_ID:
3073 msr_info->data = 1 << 24;
3074 break;
3075 case MSR_IA32_APICBASE:
3076 msr_info->data = kvm_get_apic_base(vcpu);
3077 break;
3078 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3079 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3080 case MSR_IA32_TSCDEADLINE:
3081 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3082 break;
3083 case MSR_IA32_TSC_ADJUST:
3084 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3085 break;
3086 case MSR_IA32_MISC_ENABLE:
3087 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3088 break;
3089 case MSR_IA32_SMBASE:
3090 if (!msr_info->host_initiated)
3091 return 1;
3092 msr_info->data = vcpu->arch.smbase;
3093 break;
3094 case MSR_SMI_COUNT:
3095 msr_info->data = vcpu->arch.smi_count;
3096 break;
3097 case MSR_IA32_PERF_STATUS:
3098 /* TSC increment by tick */
3099 msr_info->data = 1000ULL;
3100 /* CPU multiplier */
3101 msr_info->data |= (((uint64_t)4ULL) << 40);
3102 break;
3103 case MSR_EFER:
3104 msr_info->data = vcpu->arch.efer;
3105 break;
3106 case MSR_KVM_WALL_CLOCK:
3107 case MSR_KVM_WALL_CLOCK_NEW:
3108 msr_info->data = vcpu->kvm->arch.wall_clock;
3109 break;
3110 case MSR_KVM_SYSTEM_TIME:
3111 case MSR_KVM_SYSTEM_TIME_NEW:
3112 msr_info->data = vcpu->arch.time;
3113 break;
3114 case MSR_KVM_ASYNC_PF_EN:
3115 msr_info->data = vcpu->arch.apf.msr_val;
3116 break;
3117 case MSR_KVM_STEAL_TIME:
3118 msr_info->data = vcpu->arch.st.msr_val;
3119 break;
3120 case MSR_KVM_PV_EOI_EN:
3121 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3122 break;
3123 case MSR_KVM_POLL_CONTROL:
3124 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3125 break;
3126 case MSR_IA32_P5_MC_ADDR:
3127 case MSR_IA32_P5_MC_TYPE:
3128 case MSR_IA32_MCG_CAP:
3129 case MSR_IA32_MCG_CTL:
3130 case MSR_IA32_MCG_STATUS:
3131 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3132 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3133 msr_info->host_initiated);
3134 case MSR_IA32_XSS:
3135 if (!msr_info->host_initiated &&
3136 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3137 return 1;
3138 msr_info->data = vcpu->arch.ia32_xss;
3139 break;
3140 case MSR_K7_CLK_CTL:
3141 /*
3142 * Provide expected ramp-up count for K7. All other
3143 * are set to zero, indicating minimum divisors for
3144 * every field.
3145 *
3146 * This prevents guest kernels on AMD host with CPU
3147 * type 6, model 8 and higher from exploding due to
3148 * the rdmsr failing.
3149 */
3150 msr_info->data = 0x20000000;
3151 break;
3152 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3153 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3154 case HV_X64_MSR_CRASH_CTL:
3155 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3156 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3157 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3158 case HV_X64_MSR_TSC_EMULATION_STATUS:
3159 return kvm_hv_get_msr_common(vcpu,
3160 msr_info->index, &msr_info->data,
3161 msr_info->host_initiated);
3162 case MSR_IA32_BBL_CR_CTL3:
3163 /* This legacy MSR exists but isn't fully documented in current
3164 * silicon. It is however accessed by winxp in very narrow
3165 * scenarios where it sets bit #19, itself documented as
3166 * a "reserved" bit. Best effort attempt to source coherent
3167 * read data here should the balance of the register be
3168 * interpreted by the guest:
3169 *
3170 * L2 cache control register 3: 64GB range, 256KB size,
3171 * enabled, latency 0x1, configured
3172 */
3173 msr_info->data = 0xbe702111;
3174 break;
3175 case MSR_AMD64_OSVW_ID_LENGTH:
3176 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3177 return 1;
3178 msr_info->data = vcpu->arch.osvw.length;
3179 break;
3180 case MSR_AMD64_OSVW_STATUS:
3181 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3182 return 1;
3183 msr_info->data = vcpu->arch.osvw.status;
3184 break;
3185 case MSR_PLATFORM_INFO:
3186 if (!msr_info->host_initiated &&
3187 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3188 return 1;
3189 msr_info->data = vcpu->arch.msr_platform_info;
3190 break;
3191 case MSR_MISC_FEATURES_ENABLES:
3192 msr_info->data = vcpu->arch.msr_misc_features_enables;
3193 break;
3194 case MSR_K7_HWCR:
3195 msr_info->data = vcpu->arch.msr_hwcr;
3196 break;
3197 default:
3198 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3199 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3200 if (!ignore_msrs) {
3201 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3202 msr_info->index);
3203 return 1;
3204 } else {
3205 if (report_ignored_msrs)
3206 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3207 msr_info->index);
3208 msr_info->data = 0;
3209 }
3210 break;
3211 }
3212 return 0;
3213 }
3214 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3215
3216 /*
3217 * Read or write a bunch of msrs. All parameters are kernel addresses.
3218 *
3219 * @return number of msrs set successfully.
3220 */
3221 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3222 struct kvm_msr_entry *entries,
3223 int (*do_msr)(struct kvm_vcpu *vcpu,
3224 unsigned index, u64 *data))
3225 {
3226 int i;
3227
3228 for (i = 0; i < msrs->nmsrs; ++i)
3229 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3230 break;
3231
3232 return i;
3233 }
3234
3235 /*
3236 * Read or write a bunch of msrs. Parameters are user addresses.
3237 *
3238 * @return number of msrs set successfully.
3239 */
3240 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3241 int (*do_msr)(struct kvm_vcpu *vcpu,
3242 unsigned index, u64 *data),
3243 int writeback)
3244 {
3245 struct kvm_msrs msrs;
3246 struct kvm_msr_entry *entries;
3247 int r, n;
3248 unsigned size;
3249
3250 r = -EFAULT;
3251 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3252 goto out;
3253
3254 r = -E2BIG;
3255 if (msrs.nmsrs >= MAX_IO_MSRS)
3256 goto out;
3257
3258 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3259 entries = memdup_user(user_msrs->entries, size);
3260 if (IS_ERR(entries)) {
3261 r = PTR_ERR(entries);
3262 goto out;
3263 }
3264
3265 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3266 if (r < 0)
3267 goto out_free;
3268
3269 r = -EFAULT;
3270 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3271 goto out_free;
3272
3273 r = n;
3274
3275 out_free:
3276 kfree(entries);
3277 out:
3278 return r;
3279 }
3280
3281 static inline bool kvm_can_mwait_in_guest(void)
3282 {
3283 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3284 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3285 boot_cpu_has(X86_FEATURE_ARAT);
3286 }
3287
3288 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3289 {
3290 int r = 0;
3291
3292 switch (ext) {
3293 case KVM_CAP_IRQCHIP:
3294 case KVM_CAP_HLT:
3295 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3296 case KVM_CAP_SET_TSS_ADDR:
3297 case KVM_CAP_EXT_CPUID:
3298 case KVM_CAP_EXT_EMUL_CPUID:
3299 case KVM_CAP_CLOCKSOURCE:
3300 case KVM_CAP_PIT:
3301 case KVM_CAP_NOP_IO_DELAY:
3302 case KVM_CAP_MP_STATE:
3303 case KVM_CAP_SYNC_MMU:
3304 case KVM_CAP_USER_NMI:
3305 case KVM_CAP_REINJECT_CONTROL:
3306 case KVM_CAP_IRQ_INJECT_STATUS:
3307 case KVM_CAP_IOEVENTFD:
3308 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3309 case KVM_CAP_PIT2:
3310 case KVM_CAP_PIT_STATE2:
3311 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3312 case KVM_CAP_XEN_HVM:
3313 case KVM_CAP_VCPU_EVENTS:
3314 case KVM_CAP_HYPERV:
3315 case KVM_CAP_HYPERV_VAPIC:
3316 case KVM_CAP_HYPERV_SPIN:
3317 case KVM_CAP_HYPERV_SYNIC:
3318 case KVM_CAP_HYPERV_SYNIC2:
3319 case KVM_CAP_HYPERV_VP_INDEX:
3320 case KVM_CAP_HYPERV_EVENTFD:
3321 case KVM_CAP_HYPERV_TLBFLUSH:
3322 case KVM_CAP_HYPERV_SEND_IPI:
3323 case KVM_CAP_HYPERV_CPUID:
3324 case KVM_CAP_PCI_SEGMENT:
3325 case KVM_CAP_DEBUGREGS:
3326 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3327 case KVM_CAP_XSAVE:
3328 case KVM_CAP_ASYNC_PF:
3329 case KVM_CAP_GET_TSC_KHZ:
3330 case KVM_CAP_KVMCLOCK_CTRL:
3331 case KVM_CAP_READONLY_MEM:
3332 case KVM_CAP_HYPERV_TIME:
3333 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3334 case KVM_CAP_TSC_DEADLINE_TIMER:
3335 case KVM_CAP_DISABLE_QUIRKS:
3336 case KVM_CAP_SET_BOOT_CPU_ID:
3337 case KVM_CAP_SPLIT_IRQCHIP:
3338 case KVM_CAP_IMMEDIATE_EXIT:
3339 case KVM_CAP_PMU_EVENT_FILTER:
3340 case KVM_CAP_GET_MSR_FEATURES:
3341 case KVM_CAP_MSR_PLATFORM_INFO:
3342 case KVM_CAP_EXCEPTION_PAYLOAD:
3343 r = 1;
3344 break;
3345 case KVM_CAP_SYNC_REGS:
3346 r = KVM_SYNC_X86_VALID_FIELDS;
3347 break;
3348 case KVM_CAP_ADJUST_CLOCK:
3349 r = KVM_CLOCK_TSC_STABLE;
3350 break;
3351 case KVM_CAP_X86_DISABLE_EXITS:
3352 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3353 KVM_X86_DISABLE_EXITS_CSTATE;
3354 if(kvm_can_mwait_in_guest())
3355 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3356 break;
3357 case KVM_CAP_X86_SMM:
3358 /* SMBASE is usually relocated above 1M on modern chipsets,
3359 * and SMM handlers might indeed rely on 4G segment limits,
3360 * so do not report SMM to be available if real mode is
3361 * emulated via vm86 mode. Still, do not go to great lengths
3362 * to avoid userspace's usage of the feature, because it is a
3363 * fringe case that is not enabled except via specific settings
3364 * of the module parameters.
3365 */
3366 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3367 break;
3368 case KVM_CAP_VAPIC:
3369 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3370 break;
3371 case KVM_CAP_NR_VCPUS:
3372 r = KVM_SOFT_MAX_VCPUS;
3373 break;
3374 case KVM_CAP_MAX_VCPUS:
3375 r = KVM_MAX_VCPUS;
3376 break;
3377 case KVM_CAP_MAX_VCPU_ID:
3378 r = KVM_MAX_VCPU_ID;
3379 break;
3380 case KVM_CAP_PV_MMU: /* obsolete */
3381 r = 0;
3382 break;
3383 case KVM_CAP_MCE:
3384 r = KVM_MAX_MCE_BANKS;
3385 break;
3386 case KVM_CAP_XCRS:
3387 r = boot_cpu_has(X86_FEATURE_XSAVE);
3388 break;
3389 case KVM_CAP_TSC_CONTROL:
3390 r = kvm_has_tsc_control;
3391 break;
3392 case KVM_CAP_X2APIC_API:
3393 r = KVM_X2APIC_API_VALID_FLAGS;
3394 break;
3395 case KVM_CAP_NESTED_STATE:
3396 r = kvm_x86_ops->get_nested_state ?
3397 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3398 break;
3399 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3400 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3401 break;
3402 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3403 r = kvm_x86_ops->nested_enable_evmcs != NULL;
3404 break;
3405 default:
3406 break;
3407 }
3408 return r;
3409
3410 }
3411
3412 long kvm_arch_dev_ioctl(struct file *filp,
3413 unsigned int ioctl, unsigned long arg)
3414 {
3415 void __user *argp = (void __user *)arg;
3416 long r;
3417
3418 switch (ioctl) {
3419 case KVM_GET_MSR_INDEX_LIST: {
3420 struct kvm_msr_list __user *user_msr_list = argp;
3421 struct kvm_msr_list msr_list;
3422 unsigned n;
3423
3424 r = -EFAULT;
3425 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3426 goto out;
3427 n = msr_list.nmsrs;
3428 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3429 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3430 goto out;
3431 r = -E2BIG;
3432 if (n < msr_list.nmsrs)
3433 goto out;
3434 r = -EFAULT;
3435 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3436 num_msrs_to_save * sizeof(u32)))
3437 goto out;
3438 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3439 &emulated_msrs,
3440 num_emulated_msrs * sizeof(u32)))
3441 goto out;
3442 r = 0;
3443 break;
3444 }
3445 case KVM_GET_SUPPORTED_CPUID:
3446 case KVM_GET_EMULATED_CPUID: {
3447 struct kvm_cpuid2 __user *cpuid_arg = argp;
3448 struct kvm_cpuid2 cpuid;
3449
3450 r = -EFAULT;
3451 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3452 goto out;
3453
3454 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3455 ioctl);
3456 if (r)
3457 goto out;
3458
3459 r = -EFAULT;
3460 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3461 goto out;
3462 r = 0;
3463 break;
3464 }
3465 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3466 r = -EFAULT;
3467 if (copy_to_user(argp, &kvm_mce_cap_supported,
3468 sizeof(kvm_mce_cap_supported)))
3469 goto out;
3470 r = 0;
3471 break;
3472 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3473 struct kvm_msr_list __user *user_msr_list = argp;
3474 struct kvm_msr_list msr_list;
3475 unsigned int n;
3476
3477 r = -EFAULT;
3478 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3479 goto out;
3480 n = msr_list.nmsrs;
3481 msr_list.nmsrs = num_msr_based_features;
3482 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3483 goto out;
3484 r = -E2BIG;
3485 if (n < msr_list.nmsrs)
3486 goto out;
3487 r = -EFAULT;
3488 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3489 num_msr_based_features * sizeof(u32)))
3490 goto out;
3491 r = 0;
3492 break;
3493 }
3494 case KVM_GET_MSRS:
3495 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3496 break;
3497 }
3498 default:
3499 r = -EINVAL;
3500 }
3501 out:
3502 return r;
3503 }
3504
3505 static void wbinvd_ipi(void *garbage)
3506 {
3507 wbinvd();
3508 }
3509
3510 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3511 {
3512 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3513 }
3514
3515 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3516 {
3517 /* Address WBINVD may be executed by guest */
3518 if (need_emulate_wbinvd(vcpu)) {
3519 if (kvm_x86_ops->has_wbinvd_exit())
3520 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3521 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3522 smp_call_function_single(vcpu->cpu,
3523 wbinvd_ipi, NULL, 1);
3524 }
3525
3526 kvm_x86_ops->vcpu_load(vcpu, cpu);
3527
3528 /* Apply any externally detected TSC adjustments (due to suspend) */
3529 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3530 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3531 vcpu->arch.tsc_offset_adjustment = 0;
3532 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3533 }
3534
3535 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3536 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3537 rdtsc() - vcpu->arch.last_host_tsc;
3538 if (tsc_delta < 0)
3539 mark_tsc_unstable("KVM discovered backwards TSC");
3540
3541 if (kvm_check_tsc_unstable()) {
3542 u64 offset = kvm_compute_tsc_offset(vcpu,
3543 vcpu->arch.last_guest_tsc);
3544 kvm_vcpu_write_tsc_offset(vcpu, offset);
3545 vcpu->arch.tsc_catchup = 1;
3546 }
3547
3548 if (kvm_lapic_hv_timer_in_use(vcpu))
3549 kvm_lapic_restart_hv_timer(vcpu);
3550
3551 /*
3552 * On a host with synchronized TSC, there is no need to update
3553 * kvmclock on vcpu->cpu migration
3554 */
3555 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3556 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3557 if (vcpu->cpu != cpu)
3558 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3559 vcpu->cpu = cpu;
3560 }
3561
3562 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3563 }
3564
3565 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3566 {
3567 struct kvm_host_map map;
3568 struct kvm_steal_time *st;
3569
3570 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3571 return;
3572
3573 if (vcpu->arch.st.preempted)
3574 return;
3575
3576 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3577 &vcpu->arch.st.cache, true))
3578 return;
3579
3580 st = map.hva +
3581 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3582
3583 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3584
3585 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3586 }
3587
3588 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3589 {
3590 int idx;
3591
3592 if (vcpu->preempted)
3593 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3594
3595 /*
3596 * Disable page faults because we're in atomic context here.
3597 * kvm_write_guest_offset_cached() would call might_fault()
3598 * that relies on pagefault_disable() to tell if there's a
3599 * bug. NOTE: the write to guest memory may not go through if
3600 * during postcopy live migration or if there's heavy guest
3601 * paging.
3602 */
3603 pagefault_disable();
3604 /*
3605 * kvm_memslots() will be called by
3606 * kvm_write_guest_offset_cached() so take the srcu lock.
3607 */
3608 idx = srcu_read_lock(&vcpu->kvm->srcu);
3609 kvm_steal_time_set_preempted(vcpu);
3610 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3611 pagefault_enable();
3612 kvm_x86_ops->vcpu_put(vcpu);
3613 vcpu->arch.last_host_tsc = rdtsc();
3614 /*
3615 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3616 * on every vmexit, but if not, we might have a stale dr6 from the
3617 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3618 */
3619 set_debugreg(0, 6);
3620 }
3621
3622 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3623 struct kvm_lapic_state *s)
3624 {
3625 if (vcpu->arch.apicv_active)
3626 kvm_x86_ops->sync_pir_to_irr(vcpu);
3627
3628 return kvm_apic_get_state(vcpu, s);
3629 }
3630
3631 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3632 struct kvm_lapic_state *s)
3633 {
3634 int r;
3635
3636 r = kvm_apic_set_state(vcpu, s);
3637 if (r)
3638 return r;
3639 update_cr8_intercept(vcpu);
3640
3641 return 0;
3642 }
3643
3644 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3645 {
3646 return (!lapic_in_kernel(vcpu) ||
3647 kvm_apic_accept_pic_intr(vcpu));
3648 }
3649
3650 /*
3651 * if userspace requested an interrupt window, check that the
3652 * interrupt window is open.
3653 *
3654 * No need to exit to userspace if we already have an interrupt queued.
3655 */
3656 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3657 {
3658 return kvm_arch_interrupt_allowed(vcpu) &&
3659 !kvm_cpu_has_interrupt(vcpu) &&
3660 !kvm_event_needs_reinjection(vcpu) &&
3661 kvm_cpu_accept_dm_intr(vcpu);
3662 }
3663
3664 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3665 struct kvm_interrupt *irq)
3666 {
3667 if (irq->irq >= KVM_NR_INTERRUPTS)
3668 return -EINVAL;
3669
3670 if (!irqchip_in_kernel(vcpu->kvm)) {
3671 kvm_queue_interrupt(vcpu, irq->irq, false);
3672 kvm_make_request(KVM_REQ_EVENT, vcpu);
3673 return 0;
3674 }
3675
3676 /*
3677 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3678 * fail for in-kernel 8259.
3679 */
3680 if (pic_in_kernel(vcpu->kvm))
3681 return -ENXIO;
3682
3683 if (vcpu->arch.pending_external_vector != -1)
3684 return -EEXIST;
3685
3686 vcpu->arch.pending_external_vector = irq->irq;
3687 kvm_make_request(KVM_REQ_EVENT, vcpu);
3688 return 0;
3689 }
3690
3691 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3692 {
3693 kvm_inject_nmi(vcpu);
3694
3695 return 0;
3696 }
3697
3698 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3699 {
3700 kvm_make_request(KVM_REQ_SMI, vcpu);
3701
3702 return 0;
3703 }
3704
3705 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3706 struct kvm_tpr_access_ctl *tac)
3707 {
3708 if (tac->flags)
3709 return -EINVAL;
3710 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3711 return 0;
3712 }
3713
3714 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3715 u64 mcg_cap)
3716 {
3717 int r;
3718 unsigned bank_num = mcg_cap & 0xff, bank;
3719
3720 r = -EINVAL;
3721 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3722 goto out;
3723 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3724 goto out;
3725 r = 0;
3726 vcpu->arch.mcg_cap = mcg_cap;
3727 /* Init IA32_MCG_CTL to all 1s */
3728 if (mcg_cap & MCG_CTL_P)
3729 vcpu->arch.mcg_ctl = ~(u64)0;
3730 /* Init IA32_MCi_CTL to all 1s */
3731 for (bank = 0; bank < bank_num; bank++)
3732 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3733
3734 kvm_x86_ops->setup_mce(vcpu);
3735 out:
3736 return r;
3737 }
3738
3739 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3740 struct kvm_x86_mce *mce)
3741 {
3742 u64 mcg_cap = vcpu->arch.mcg_cap;
3743 unsigned bank_num = mcg_cap & 0xff;
3744 u64 *banks = vcpu->arch.mce_banks;
3745
3746 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3747 return -EINVAL;
3748 /*
3749 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3750 * reporting is disabled
3751 */
3752 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3753 vcpu->arch.mcg_ctl != ~(u64)0)
3754 return 0;
3755 banks += 4 * mce->bank;
3756 /*
3757 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3758 * reporting is disabled for the bank
3759 */
3760 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3761 return 0;
3762 if (mce->status & MCI_STATUS_UC) {
3763 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3764 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3765 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3766 return 0;
3767 }
3768 if (banks[1] & MCI_STATUS_VAL)
3769 mce->status |= MCI_STATUS_OVER;
3770 banks[2] = mce->addr;
3771 banks[3] = mce->misc;
3772 vcpu->arch.mcg_status = mce->mcg_status;
3773 banks[1] = mce->status;
3774 kvm_queue_exception(vcpu, MC_VECTOR);
3775 } else if (!(banks[1] & MCI_STATUS_VAL)
3776 || !(banks[1] & MCI_STATUS_UC)) {
3777 if (banks[1] & MCI_STATUS_VAL)
3778 mce->status |= MCI_STATUS_OVER;
3779 banks[2] = mce->addr;
3780 banks[3] = mce->misc;
3781 banks[1] = mce->status;
3782 } else
3783 banks[1] |= MCI_STATUS_OVER;
3784 return 0;
3785 }
3786
3787 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3788 struct kvm_vcpu_events *events)
3789 {
3790 process_nmi(vcpu);
3791
3792 /*
3793 * In guest mode, payload delivery should be deferred,
3794 * so that the L1 hypervisor can intercept #PF before
3795 * CR2 is modified (or intercept #DB before DR6 is
3796 * modified under nVMX). Unless the per-VM capability,
3797 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3798 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3799 * opportunistically defer the exception payload, deliver it if the
3800 * capability hasn't been requested before processing a
3801 * KVM_GET_VCPU_EVENTS.
3802 */
3803 if (!vcpu->kvm->arch.exception_payload_enabled &&
3804 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3805 kvm_deliver_exception_payload(vcpu);
3806
3807 /*
3808 * The API doesn't provide the instruction length for software
3809 * exceptions, so don't report them. As long as the guest RIP
3810 * isn't advanced, we should expect to encounter the exception
3811 * again.
3812 */
3813 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3814 events->exception.injected = 0;
3815 events->exception.pending = 0;
3816 } else {
3817 events->exception.injected = vcpu->arch.exception.injected;
3818 events->exception.pending = vcpu->arch.exception.pending;
3819 /*
3820 * For ABI compatibility, deliberately conflate
3821 * pending and injected exceptions when
3822 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3823 */
3824 if (!vcpu->kvm->arch.exception_payload_enabled)
3825 events->exception.injected |=
3826 vcpu->arch.exception.pending;
3827 }
3828 events->exception.nr = vcpu->arch.exception.nr;
3829 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3830 events->exception.error_code = vcpu->arch.exception.error_code;
3831 events->exception_has_payload = vcpu->arch.exception.has_payload;
3832 events->exception_payload = vcpu->arch.exception.payload;
3833
3834 events->interrupt.injected =
3835 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3836 events->interrupt.nr = vcpu->arch.interrupt.nr;
3837 events->interrupt.soft = 0;
3838 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3839
3840 events->nmi.injected = vcpu->arch.nmi_injected;
3841 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3842 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3843 events->nmi.pad = 0;
3844
3845 events->sipi_vector = 0; /* never valid when reporting to user space */
3846
3847 events->smi.smm = is_smm(vcpu);
3848 events->smi.pending = vcpu->arch.smi_pending;
3849 events->smi.smm_inside_nmi =
3850 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3851 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3852
3853 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3854 | KVM_VCPUEVENT_VALID_SHADOW
3855 | KVM_VCPUEVENT_VALID_SMM);
3856 if (vcpu->kvm->arch.exception_payload_enabled)
3857 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3858
3859 memset(&events->reserved, 0, sizeof(events->reserved));
3860 }
3861
3862 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3863
3864 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3865 struct kvm_vcpu_events *events)
3866 {
3867 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3868 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3869 | KVM_VCPUEVENT_VALID_SHADOW
3870 | KVM_VCPUEVENT_VALID_SMM
3871 | KVM_VCPUEVENT_VALID_PAYLOAD))
3872 return -EINVAL;
3873
3874 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3875 if (!vcpu->kvm->arch.exception_payload_enabled)
3876 return -EINVAL;
3877 if (events->exception.pending)
3878 events->exception.injected = 0;
3879 else
3880 events->exception_has_payload = 0;
3881 } else {
3882 events->exception.pending = 0;
3883 events->exception_has_payload = 0;
3884 }
3885
3886 if ((events->exception.injected || events->exception.pending) &&
3887 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3888 return -EINVAL;
3889
3890 /* INITs are latched while in SMM */
3891 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3892 (events->smi.smm || events->smi.pending) &&
3893 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3894 return -EINVAL;
3895
3896 process_nmi(vcpu);
3897 vcpu->arch.exception.injected = events->exception.injected;
3898 vcpu->arch.exception.pending = events->exception.pending;
3899 vcpu->arch.exception.nr = events->exception.nr;
3900 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3901 vcpu->arch.exception.error_code = events->exception.error_code;
3902 vcpu->arch.exception.has_payload = events->exception_has_payload;
3903 vcpu->arch.exception.payload = events->exception_payload;
3904
3905 vcpu->arch.interrupt.injected = events->interrupt.injected;
3906 vcpu->arch.interrupt.nr = events->interrupt.nr;
3907 vcpu->arch.interrupt.soft = events->interrupt.soft;
3908 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3909 kvm_x86_ops->set_interrupt_shadow(vcpu,
3910 events->interrupt.shadow);
3911
3912 vcpu->arch.nmi_injected = events->nmi.injected;
3913 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3914 vcpu->arch.nmi_pending = events->nmi.pending;
3915 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3916
3917 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3918 lapic_in_kernel(vcpu))
3919 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3920
3921 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3922 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3923 if (events->smi.smm)
3924 vcpu->arch.hflags |= HF_SMM_MASK;
3925 else
3926 vcpu->arch.hflags &= ~HF_SMM_MASK;
3927 kvm_smm_changed(vcpu);
3928 }
3929
3930 vcpu->arch.smi_pending = events->smi.pending;
3931
3932 if (events->smi.smm) {
3933 if (events->smi.smm_inside_nmi)
3934 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3935 else
3936 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3937 }
3938
3939 if (lapic_in_kernel(vcpu)) {
3940 if (events->smi.latched_init)
3941 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3942 else
3943 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3944 }
3945 }
3946
3947 kvm_make_request(KVM_REQ_EVENT, vcpu);
3948
3949 return 0;
3950 }
3951
3952 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3953 struct kvm_debugregs *dbgregs)
3954 {
3955 unsigned long val;
3956
3957 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3958 kvm_get_dr(vcpu, 6, &val);
3959 dbgregs->dr6 = val;
3960 dbgregs->dr7 = vcpu->arch.dr7;
3961 dbgregs->flags = 0;
3962 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3963 }
3964
3965 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3966 struct kvm_debugregs *dbgregs)
3967 {
3968 if (dbgregs->flags)
3969 return -EINVAL;
3970
3971 if (dbgregs->dr6 & ~0xffffffffull)
3972 return -EINVAL;
3973 if (dbgregs->dr7 & ~0xffffffffull)
3974 return -EINVAL;
3975
3976 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3977 kvm_update_dr0123(vcpu);
3978 vcpu->arch.dr6 = dbgregs->dr6;
3979 kvm_update_dr6(vcpu);
3980 vcpu->arch.dr7 = dbgregs->dr7;
3981 kvm_update_dr7(vcpu);
3982
3983 return 0;
3984 }
3985
3986 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3987
3988 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3989 {
3990 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3991 u64 xstate_bv = xsave->header.xfeatures;
3992 u64 valid;
3993
3994 /*
3995 * Copy legacy XSAVE area, to avoid complications with CPUID
3996 * leaves 0 and 1 in the loop below.
3997 */
3998 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3999
4000 /* Set XSTATE_BV */
4001 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4002 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4003
4004 /*
4005 * Copy each region from the possibly compacted offset to the
4006 * non-compacted offset.
4007 */
4008 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4009 while (valid) {
4010 u64 xfeature_mask = valid & -valid;
4011 int xfeature_nr = fls64(xfeature_mask) - 1;
4012 void *src = get_xsave_addr(xsave, xfeature_nr);
4013
4014 if (src) {
4015 u32 size, offset, ecx, edx;
4016 cpuid_count(XSTATE_CPUID, xfeature_nr,
4017 &size, &offset, &ecx, &edx);
4018 if (xfeature_nr == XFEATURE_PKRU)
4019 memcpy(dest + offset, &vcpu->arch.pkru,
4020 sizeof(vcpu->arch.pkru));
4021 else
4022 memcpy(dest + offset, src, size);
4023
4024 }
4025
4026 valid -= xfeature_mask;
4027 }
4028 }
4029
4030 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4031 {
4032 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4033 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4034 u64 valid;
4035
4036 /*
4037 * Copy legacy XSAVE area, to avoid complications with CPUID
4038 * leaves 0 and 1 in the loop below.
4039 */
4040 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4041
4042 /* Set XSTATE_BV and possibly XCOMP_BV. */
4043 xsave->header.xfeatures = xstate_bv;
4044 if (boot_cpu_has(X86_FEATURE_XSAVES))
4045 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4046
4047 /*
4048 * Copy each region from the non-compacted offset to the
4049 * possibly compacted offset.
4050 */
4051 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4052 while (valid) {
4053 u64 xfeature_mask = valid & -valid;
4054 int xfeature_nr = fls64(xfeature_mask) - 1;
4055 void *dest = get_xsave_addr(xsave, xfeature_nr);
4056
4057 if (dest) {
4058 u32 size, offset, ecx, edx;
4059 cpuid_count(XSTATE_CPUID, xfeature_nr,
4060 &size, &offset, &ecx, &edx);
4061 if (xfeature_nr == XFEATURE_PKRU)
4062 memcpy(&vcpu->arch.pkru, src + offset,
4063 sizeof(vcpu->arch.pkru));
4064 else
4065 memcpy(dest, src + offset, size);
4066 }
4067
4068 valid -= xfeature_mask;
4069 }
4070 }
4071
4072 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4073 struct kvm_xsave *guest_xsave)
4074 {
4075 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4076 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4077 fill_xsave((u8 *) guest_xsave->region, vcpu);
4078 } else {
4079 memcpy(guest_xsave->region,
4080 &vcpu->arch.guest_fpu->state.fxsave,
4081 sizeof(struct fxregs_state));
4082 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4083 XFEATURE_MASK_FPSSE;
4084 }
4085 }
4086
4087 #define XSAVE_MXCSR_OFFSET 24
4088
4089 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4090 struct kvm_xsave *guest_xsave)
4091 {
4092 u64 xstate_bv =
4093 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4094 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4095
4096 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4097 /*
4098 * Here we allow setting states that are not present in
4099 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4100 * with old userspace.
4101 */
4102 if (xstate_bv & ~kvm_supported_xcr0() ||
4103 mxcsr & ~mxcsr_feature_mask)
4104 return -EINVAL;
4105 load_xsave(vcpu, (u8 *)guest_xsave->region);
4106 } else {
4107 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4108 mxcsr & ~mxcsr_feature_mask)
4109 return -EINVAL;
4110 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4111 guest_xsave->region, sizeof(struct fxregs_state));
4112 }
4113 return 0;
4114 }
4115
4116 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4117 struct kvm_xcrs *guest_xcrs)
4118 {
4119 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4120 guest_xcrs->nr_xcrs = 0;
4121 return;
4122 }
4123
4124 guest_xcrs->nr_xcrs = 1;
4125 guest_xcrs->flags = 0;
4126 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4127 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4128 }
4129
4130 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4131 struct kvm_xcrs *guest_xcrs)
4132 {
4133 int i, r = 0;
4134
4135 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4136 return -EINVAL;
4137
4138 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4139 return -EINVAL;
4140
4141 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4142 /* Only support XCR0 currently */
4143 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4144 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4145 guest_xcrs->xcrs[i].value);
4146 break;
4147 }
4148 if (r)
4149 r = -EINVAL;
4150 return r;
4151 }
4152
4153 /*
4154 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4155 * stopped by the hypervisor. This function will be called from the host only.
4156 * EINVAL is returned when the host attempts to set the flag for a guest that
4157 * does not support pv clocks.
4158 */
4159 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4160 {
4161 if (!vcpu->arch.pv_time_enabled)
4162 return -EINVAL;
4163 vcpu->arch.pvclock_set_guest_stopped_request = true;
4164 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4165 return 0;
4166 }
4167
4168 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4169 struct kvm_enable_cap *cap)
4170 {
4171 int r;
4172 uint16_t vmcs_version;
4173 void __user *user_ptr;
4174
4175 if (cap->flags)
4176 return -EINVAL;
4177
4178 switch (cap->cap) {
4179 case KVM_CAP_HYPERV_SYNIC2:
4180 if (cap->args[0])
4181 return -EINVAL;
4182 /* fall through */
4183
4184 case KVM_CAP_HYPERV_SYNIC:
4185 if (!irqchip_in_kernel(vcpu->kvm))
4186 return -EINVAL;
4187 return kvm_hv_activate_synic(vcpu, cap->cap ==
4188 KVM_CAP_HYPERV_SYNIC2);
4189 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4190 if (!kvm_x86_ops->nested_enable_evmcs)
4191 return -ENOTTY;
4192 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4193 if (!r) {
4194 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4195 if (copy_to_user(user_ptr, &vmcs_version,
4196 sizeof(vmcs_version)))
4197 r = -EFAULT;
4198 }
4199 return r;
4200 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4201 if (!kvm_x86_ops->enable_direct_tlbflush)
4202 return -ENOTTY;
4203
4204 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
4205
4206 default:
4207 return -EINVAL;
4208 }
4209 }
4210
4211 long kvm_arch_vcpu_ioctl(struct file *filp,
4212 unsigned int ioctl, unsigned long arg)
4213 {
4214 struct kvm_vcpu *vcpu = filp->private_data;
4215 void __user *argp = (void __user *)arg;
4216 int r;
4217 union {
4218 struct kvm_lapic_state *lapic;
4219 struct kvm_xsave *xsave;
4220 struct kvm_xcrs *xcrs;
4221 void *buffer;
4222 } u;
4223
4224 vcpu_load(vcpu);
4225
4226 u.buffer = NULL;
4227 switch (ioctl) {
4228 case KVM_GET_LAPIC: {
4229 r = -EINVAL;
4230 if (!lapic_in_kernel(vcpu))
4231 goto out;
4232 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4233 GFP_KERNEL_ACCOUNT);
4234
4235 r = -ENOMEM;
4236 if (!u.lapic)
4237 goto out;
4238 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4239 if (r)
4240 goto out;
4241 r = -EFAULT;
4242 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4243 goto out;
4244 r = 0;
4245 break;
4246 }
4247 case KVM_SET_LAPIC: {
4248 r = -EINVAL;
4249 if (!lapic_in_kernel(vcpu))
4250 goto out;
4251 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4252 if (IS_ERR(u.lapic)) {
4253 r = PTR_ERR(u.lapic);
4254 goto out_nofree;
4255 }
4256
4257 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4258 break;
4259 }
4260 case KVM_INTERRUPT: {
4261 struct kvm_interrupt irq;
4262
4263 r = -EFAULT;
4264 if (copy_from_user(&irq, argp, sizeof(irq)))
4265 goto out;
4266 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4267 break;
4268 }
4269 case KVM_NMI: {
4270 r = kvm_vcpu_ioctl_nmi(vcpu);
4271 break;
4272 }
4273 case KVM_SMI: {
4274 r = kvm_vcpu_ioctl_smi(vcpu);
4275 break;
4276 }
4277 case KVM_SET_CPUID: {
4278 struct kvm_cpuid __user *cpuid_arg = argp;
4279 struct kvm_cpuid cpuid;
4280
4281 r = -EFAULT;
4282 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4283 goto out;
4284 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4285 break;
4286 }
4287 case KVM_SET_CPUID2: {
4288 struct kvm_cpuid2 __user *cpuid_arg = argp;
4289 struct kvm_cpuid2 cpuid;
4290
4291 r = -EFAULT;
4292 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4293 goto out;
4294 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4295 cpuid_arg->entries);
4296 break;
4297 }
4298 case KVM_GET_CPUID2: {
4299 struct kvm_cpuid2 __user *cpuid_arg = argp;
4300 struct kvm_cpuid2 cpuid;
4301
4302 r = -EFAULT;
4303 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4304 goto out;
4305 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4306 cpuid_arg->entries);
4307 if (r)
4308 goto out;
4309 r = -EFAULT;
4310 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4311 goto out;
4312 r = 0;
4313 break;
4314 }
4315 case KVM_GET_MSRS: {
4316 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4317 r = msr_io(vcpu, argp, do_get_msr, 1);
4318 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4319 break;
4320 }
4321 case KVM_SET_MSRS: {
4322 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4323 r = msr_io(vcpu, argp, do_set_msr, 0);
4324 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4325 break;
4326 }
4327 case KVM_TPR_ACCESS_REPORTING: {
4328 struct kvm_tpr_access_ctl tac;
4329
4330 r = -EFAULT;
4331 if (copy_from_user(&tac, argp, sizeof(tac)))
4332 goto out;
4333 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4334 if (r)
4335 goto out;
4336 r = -EFAULT;
4337 if (copy_to_user(argp, &tac, sizeof(tac)))
4338 goto out;
4339 r = 0;
4340 break;
4341 };
4342 case KVM_SET_VAPIC_ADDR: {
4343 struct kvm_vapic_addr va;
4344 int idx;
4345
4346 r = -EINVAL;
4347 if (!lapic_in_kernel(vcpu))
4348 goto out;
4349 r = -EFAULT;
4350 if (copy_from_user(&va, argp, sizeof(va)))
4351 goto out;
4352 idx = srcu_read_lock(&vcpu->kvm->srcu);
4353 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4354 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4355 break;
4356 }
4357 case KVM_X86_SETUP_MCE: {
4358 u64 mcg_cap;
4359
4360 r = -EFAULT;
4361 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4362 goto out;
4363 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4364 break;
4365 }
4366 case KVM_X86_SET_MCE: {
4367 struct kvm_x86_mce mce;
4368
4369 r = -EFAULT;
4370 if (copy_from_user(&mce, argp, sizeof(mce)))
4371 goto out;
4372 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4373 break;
4374 }
4375 case KVM_GET_VCPU_EVENTS: {
4376 struct kvm_vcpu_events events;
4377
4378 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4379
4380 r = -EFAULT;
4381 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4382 break;
4383 r = 0;
4384 break;
4385 }
4386 case KVM_SET_VCPU_EVENTS: {
4387 struct kvm_vcpu_events events;
4388
4389 r = -EFAULT;
4390 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4391 break;
4392
4393 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4394 break;
4395 }
4396 case KVM_GET_DEBUGREGS: {
4397 struct kvm_debugregs dbgregs;
4398
4399 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4400
4401 r = -EFAULT;
4402 if (copy_to_user(argp, &dbgregs,
4403 sizeof(struct kvm_debugregs)))
4404 break;
4405 r = 0;
4406 break;
4407 }
4408 case KVM_SET_DEBUGREGS: {
4409 struct kvm_debugregs dbgregs;
4410
4411 r = -EFAULT;
4412 if (copy_from_user(&dbgregs, argp,
4413 sizeof(struct kvm_debugregs)))
4414 break;
4415
4416 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4417 break;
4418 }
4419 case KVM_GET_XSAVE: {
4420 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4421 r = -ENOMEM;
4422 if (!u.xsave)
4423 break;
4424
4425 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4426
4427 r = -EFAULT;
4428 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4429 break;
4430 r = 0;
4431 break;
4432 }
4433 case KVM_SET_XSAVE: {
4434 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4435 if (IS_ERR(u.xsave)) {
4436 r = PTR_ERR(u.xsave);
4437 goto out_nofree;
4438 }
4439
4440 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4441 break;
4442 }
4443 case KVM_GET_XCRS: {
4444 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4445 r = -ENOMEM;
4446 if (!u.xcrs)
4447 break;
4448
4449 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4450
4451 r = -EFAULT;
4452 if (copy_to_user(argp, u.xcrs,
4453 sizeof(struct kvm_xcrs)))
4454 break;
4455 r = 0;
4456 break;
4457 }
4458 case KVM_SET_XCRS: {
4459 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4460 if (IS_ERR(u.xcrs)) {
4461 r = PTR_ERR(u.xcrs);
4462 goto out_nofree;
4463 }
4464
4465 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4466 break;
4467 }
4468 case KVM_SET_TSC_KHZ: {
4469 u32 user_tsc_khz;
4470
4471 r = -EINVAL;
4472 user_tsc_khz = (u32)arg;
4473
4474 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4475 goto out;
4476
4477 if (user_tsc_khz == 0)
4478 user_tsc_khz = tsc_khz;
4479
4480 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4481 r = 0;
4482
4483 goto out;
4484 }
4485 case KVM_GET_TSC_KHZ: {
4486 r = vcpu->arch.virtual_tsc_khz;
4487 goto out;
4488 }
4489 case KVM_KVMCLOCK_CTRL: {
4490 r = kvm_set_guest_paused(vcpu);
4491 goto out;
4492 }
4493 case KVM_ENABLE_CAP: {
4494 struct kvm_enable_cap cap;
4495
4496 r = -EFAULT;
4497 if (copy_from_user(&cap, argp, sizeof(cap)))
4498 goto out;
4499 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4500 break;
4501 }
4502 case KVM_GET_NESTED_STATE: {
4503 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4504 u32 user_data_size;
4505
4506 r = -EINVAL;
4507 if (!kvm_x86_ops->get_nested_state)
4508 break;
4509
4510 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4511 r = -EFAULT;
4512 if (get_user(user_data_size, &user_kvm_nested_state->size))
4513 break;
4514
4515 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4516 user_data_size);
4517 if (r < 0)
4518 break;
4519
4520 if (r > user_data_size) {
4521 if (put_user(r, &user_kvm_nested_state->size))
4522 r = -EFAULT;
4523 else
4524 r = -E2BIG;
4525 break;
4526 }
4527
4528 r = 0;
4529 break;
4530 }
4531 case KVM_SET_NESTED_STATE: {
4532 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4533 struct kvm_nested_state kvm_state;
4534 int idx;
4535
4536 r = -EINVAL;
4537 if (!kvm_x86_ops->set_nested_state)
4538 break;
4539
4540 r = -EFAULT;
4541 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4542 break;
4543
4544 r = -EINVAL;
4545 if (kvm_state.size < sizeof(kvm_state))
4546 break;
4547
4548 if (kvm_state.flags &
4549 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4550 | KVM_STATE_NESTED_EVMCS))
4551 break;
4552
4553 /* nested_run_pending implies guest_mode. */
4554 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4555 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4556 break;
4557
4558 idx = srcu_read_lock(&vcpu->kvm->srcu);
4559 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4561 break;
4562 }
4563 case KVM_GET_SUPPORTED_HV_CPUID: {
4564 struct kvm_cpuid2 __user *cpuid_arg = argp;
4565 struct kvm_cpuid2 cpuid;
4566
4567 r = -EFAULT;
4568 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4569 goto out;
4570
4571 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4572 cpuid_arg->entries);
4573 if (r)
4574 goto out;
4575
4576 r = -EFAULT;
4577 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4578 goto out;
4579 r = 0;
4580 break;
4581 }
4582 default:
4583 r = -EINVAL;
4584 }
4585 out:
4586 kfree(u.buffer);
4587 out_nofree:
4588 vcpu_put(vcpu);
4589 return r;
4590 }
4591
4592 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4593 {
4594 return VM_FAULT_SIGBUS;
4595 }
4596
4597 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4598 {
4599 int ret;
4600
4601 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4602 return -EINVAL;
4603 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4604 return ret;
4605 }
4606
4607 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4608 u64 ident_addr)
4609 {
4610 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4611 }
4612
4613 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4614 unsigned long kvm_nr_mmu_pages)
4615 {
4616 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4617 return -EINVAL;
4618
4619 mutex_lock(&kvm->slots_lock);
4620
4621 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4622 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4623
4624 mutex_unlock(&kvm->slots_lock);
4625 return 0;
4626 }
4627
4628 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4629 {
4630 return kvm->arch.n_max_mmu_pages;
4631 }
4632
4633 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4634 {
4635 struct kvm_pic *pic = kvm->arch.vpic;
4636 int r;
4637
4638 r = 0;
4639 switch (chip->chip_id) {
4640 case KVM_IRQCHIP_PIC_MASTER:
4641 memcpy(&chip->chip.pic, &pic->pics[0],
4642 sizeof(struct kvm_pic_state));
4643 break;
4644 case KVM_IRQCHIP_PIC_SLAVE:
4645 memcpy(&chip->chip.pic, &pic->pics[1],
4646 sizeof(struct kvm_pic_state));
4647 break;
4648 case KVM_IRQCHIP_IOAPIC:
4649 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4650 break;
4651 default:
4652 r = -EINVAL;
4653 break;
4654 }
4655 return r;
4656 }
4657
4658 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4659 {
4660 struct kvm_pic *pic = kvm->arch.vpic;
4661 int r;
4662
4663 r = 0;
4664 switch (chip->chip_id) {
4665 case KVM_IRQCHIP_PIC_MASTER:
4666 spin_lock(&pic->lock);
4667 memcpy(&pic->pics[0], &chip->chip.pic,
4668 sizeof(struct kvm_pic_state));
4669 spin_unlock(&pic->lock);
4670 break;
4671 case KVM_IRQCHIP_PIC_SLAVE:
4672 spin_lock(&pic->lock);
4673 memcpy(&pic->pics[1], &chip->chip.pic,
4674 sizeof(struct kvm_pic_state));
4675 spin_unlock(&pic->lock);
4676 break;
4677 case KVM_IRQCHIP_IOAPIC:
4678 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4679 break;
4680 default:
4681 r = -EINVAL;
4682 break;
4683 }
4684 kvm_pic_update_irq(pic);
4685 return r;
4686 }
4687
4688 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4689 {
4690 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4691
4692 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4693
4694 mutex_lock(&kps->lock);
4695 memcpy(ps, &kps->channels, sizeof(*ps));
4696 mutex_unlock(&kps->lock);
4697 return 0;
4698 }
4699
4700 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4701 {
4702 int i;
4703 struct kvm_pit *pit = kvm->arch.vpit;
4704
4705 mutex_lock(&pit->pit_state.lock);
4706 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4707 for (i = 0; i < 3; i++)
4708 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4709 mutex_unlock(&pit->pit_state.lock);
4710 return 0;
4711 }
4712
4713 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4714 {
4715 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4716 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4717 sizeof(ps->channels));
4718 ps->flags = kvm->arch.vpit->pit_state.flags;
4719 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4720 memset(&ps->reserved, 0, sizeof(ps->reserved));
4721 return 0;
4722 }
4723
4724 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4725 {
4726 int start = 0;
4727 int i;
4728 u32 prev_legacy, cur_legacy;
4729 struct kvm_pit *pit = kvm->arch.vpit;
4730
4731 mutex_lock(&pit->pit_state.lock);
4732 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4733 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4734 if (!prev_legacy && cur_legacy)
4735 start = 1;
4736 memcpy(&pit->pit_state.channels, &ps->channels,
4737 sizeof(pit->pit_state.channels));
4738 pit->pit_state.flags = ps->flags;
4739 for (i = 0; i < 3; i++)
4740 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4741 start && i == 0);
4742 mutex_unlock(&pit->pit_state.lock);
4743 return 0;
4744 }
4745
4746 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4747 struct kvm_reinject_control *control)
4748 {
4749 struct kvm_pit *pit = kvm->arch.vpit;
4750
4751 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4752 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4753 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4754 */
4755 mutex_lock(&pit->pit_state.lock);
4756 kvm_pit_set_reinject(pit, control->pit_reinject);
4757 mutex_unlock(&pit->pit_state.lock);
4758
4759 return 0;
4760 }
4761
4762 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4763 {
4764 /*
4765 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4766 */
4767 if (kvm_x86_ops->flush_log_dirty)
4768 kvm_x86_ops->flush_log_dirty(kvm);
4769 }
4770
4771 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4772 bool line_status)
4773 {
4774 if (!irqchip_in_kernel(kvm))
4775 return -ENXIO;
4776
4777 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4778 irq_event->irq, irq_event->level,
4779 line_status);
4780 return 0;
4781 }
4782
4783 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4784 struct kvm_enable_cap *cap)
4785 {
4786 int r;
4787
4788 if (cap->flags)
4789 return -EINVAL;
4790
4791 switch (cap->cap) {
4792 case KVM_CAP_DISABLE_QUIRKS:
4793 kvm->arch.disabled_quirks = cap->args[0];
4794 r = 0;
4795 break;
4796 case KVM_CAP_SPLIT_IRQCHIP: {
4797 mutex_lock(&kvm->lock);
4798 r = -EINVAL;
4799 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4800 goto split_irqchip_unlock;
4801 r = -EEXIST;
4802 if (irqchip_in_kernel(kvm))
4803 goto split_irqchip_unlock;
4804 if (kvm->created_vcpus)
4805 goto split_irqchip_unlock;
4806 r = kvm_setup_empty_irq_routing(kvm);
4807 if (r)
4808 goto split_irqchip_unlock;
4809 /* Pairs with irqchip_in_kernel. */
4810 smp_wmb();
4811 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4812 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4813 r = 0;
4814 split_irqchip_unlock:
4815 mutex_unlock(&kvm->lock);
4816 break;
4817 }
4818 case KVM_CAP_X2APIC_API:
4819 r = -EINVAL;
4820 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4821 break;
4822
4823 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4824 kvm->arch.x2apic_format = true;
4825 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4826 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4827
4828 r = 0;
4829 break;
4830 case KVM_CAP_X86_DISABLE_EXITS:
4831 r = -EINVAL;
4832 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4833 break;
4834
4835 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4836 kvm_can_mwait_in_guest())
4837 kvm->arch.mwait_in_guest = true;
4838 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4839 kvm->arch.hlt_in_guest = true;
4840 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4841 kvm->arch.pause_in_guest = true;
4842 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4843 kvm->arch.cstate_in_guest = true;
4844 r = 0;
4845 break;
4846 case KVM_CAP_MSR_PLATFORM_INFO:
4847 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4848 r = 0;
4849 break;
4850 case KVM_CAP_EXCEPTION_PAYLOAD:
4851 kvm->arch.exception_payload_enabled = cap->args[0];
4852 r = 0;
4853 break;
4854 default:
4855 r = -EINVAL;
4856 break;
4857 }
4858 return r;
4859 }
4860
4861 long kvm_arch_vm_ioctl(struct file *filp,
4862 unsigned int ioctl, unsigned long arg)
4863 {
4864 struct kvm *kvm = filp->private_data;
4865 void __user *argp = (void __user *)arg;
4866 int r = -ENOTTY;
4867 /*
4868 * This union makes it completely explicit to gcc-3.x
4869 * that these two variables' stack usage should be
4870 * combined, not added together.
4871 */
4872 union {
4873 struct kvm_pit_state ps;
4874 struct kvm_pit_state2 ps2;
4875 struct kvm_pit_config pit_config;
4876 } u;
4877
4878 switch (ioctl) {
4879 case KVM_SET_TSS_ADDR:
4880 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4881 break;
4882 case KVM_SET_IDENTITY_MAP_ADDR: {
4883 u64 ident_addr;
4884
4885 mutex_lock(&kvm->lock);
4886 r = -EINVAL;
4887 if (kvm->created_vcpus)
4888 goto set_identity_unlock;
4889 r = -EFAULT;
4890 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4891 goto set_identity_unlock;
4892 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4893 set_identity_unlock:
4894 mutex_unlock(&kvm->lock);
4895 break;
4896 }
4897 case KVM_SET_NR_MMU_PAGES:
4898 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4899 break;
4900 case KVM_GET_NR_MMU_PAGES:
4901 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4902 break;
4903 case KVM_CREATE_IRQCHIP: {
4904 mutex_lock(&kvm->lock);
4905
4906 r = -EEXIST;
4907 if (irqchip_in_kernel(kvm))
4908 goto create_irqchip_unlock;
4909
4910 r = -EINVAL;
4911 if (kvm->created_vcpus)
4912 goto create_irqchip_unlock;
4913
4914 r = kvm_pic_init(kvm);
4915 if (r)
4916 goto create_irqchip_unlock;
4917
4918 r = kvm_ioapic_init(kvm);
4919 if (r) {
4920 kvm_pic_destroy(kvm);
4921 goto create_irqchip_unlock;
4922 }
4923
4924 r = kvm_setup_default_irq_routing(kvm);
4925 if (r) {
4926 kvm_ioapic_destroy(kvm);
4927 kvm_pic_destroy(kvm);
4928 goto create_irqchip_unlock;
4929 }
4930 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4931 smp_wmb();
4932 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4933 create_irqchip_unlock:
4934 mutex_unlock(&kvm->lock);
4935 break;
4936 }
4937 case KVM_CREATE_PIT:
4938 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4939 goto create_pit;
4940 case KVM_CREATE_PIT2:
4941 r = -EFAULT;
4942 if (copy_from_user(&u.pit_config, argp,
4943 sizeof(struct kvm_pit_config)))
4944 goto out;
4945 create_pit:
4946 mutex_lock(&kvm->lock);
4947 r = -EEXIST;
4948 if (kvm->arch.vpit)
4949 goto create_pit_unlock;
4950 r = -ENOMEM;
4951 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4952 if (kvm->arch.vpit)
4953 r = 0;
4954 create_pit_unlock:
4955 mutex_unlock(&kvm->lock);
4956 break;
4957 case KVM_GET_IRQCHIP: {
4958 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4959 struct kvm_irqchip *chip;
4960
4961 chip = memdup_user(argp, sizeof(*chip));
4962 if (IS_ERR(chip)) {
4963 r = PTR_ERR(chip);
4964 goto out;
4965 }
4966
4967 r = -ENXIO;
4968 if (!irqchip_kernel(kvm))
4969 goto get_irqchip_out;
4970 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4971 if (r)
4972 goto get_irqchip_out;
4973 r = -EFAULT;
4974 if (copy_to_user(argp, chip, sizeof(*chip)))
4975 goto get_irqchip_out;
4976 r = 0;
4977 get_irqchip_out:
4978 kfree(chip);
4979 break;
4980 }
4981 case KVM_SET_IRQCHIP: {
4982 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4983 struct kvm_irqchip *chip;
4984
4985 chip = memdup_user(argp, sizeof(*chip));
4986 if (IS_ERR(chip)) {
4987 r = PTR_ERR(chip);
4988 goto out;
4989 }
4990
4991 r = -ENXIO;
4992 if (!irqchip_kernel(kvm))
4993 goto set_irqchip_out;
4994 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4995 set_irqchip_out:
4996 kfree(chip);
4997 break;
4998 }
4999 case KVM_GET_PIT: {
5000 r = -EFAULT;
5001 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5002 goto out;
5003 r = -ENXIO;
5004 if (!kvm->arch.vpit)
5005 goto out;
5006 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5007 if (r)
5008 goto out;
5009 r = -EFAULT;
5010 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5011 goto out;
5012 r = 0;
5013 break;
5014 }
5015 case KVM_SET_PIT: {
5016 r = -EFAULT;
5017 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5018 goto out;
5019 r = -ENXIO;
5020 if (!kvm->arch.vpit)
5021 goto out;
5022 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5023 break;
5024 }
5025 case KVM_GET_PIT2: {
5026 r = -ENXIO;
5027 if (!kvm->arch.vpit)
5028 goto out;
5029 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5030 if (r)
5031 goto out;
5032 r = -EFAULT;
5033 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5034 goto out;
5035 r = 0;
5036 break;
5037 }
5038 case KVM_SET_PIT2: {
5039 r = -EFAULT;
5040 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5041 goto out;
5042 r = -ENXIO;
5043 if (!kvm->arch.vpit)
5044 goto out;
5045 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5046 break;
5047 }
5048 case KVM_REINJECT_CONTROL: {
5049 struct kvm_reinject_control control;
5050 r = -EFAULT;
5051 if (copy_from_user(&control, argp, sizeof(control)))
5052 goto out;
5053 r = -ENXIO;
5054 if (!kvm->arch.vpit)
5055 goto out;
5056 r = kvm_vm_ioctl_reinject(kvm, &control);
5057 break;
5058 }
5059 case KVM_SET_BOOT_CPU_ID:
5060 r = 0;
5061 mutex_lock(&kvm->lock);
5062 if (kvm->created_vcpus)
5063 r = -EBUSY;
5064 else
5065 kvm->arch.bsp_vcpu_id = arg;
5066 mutex_unlock(&kvm->lock);
5067 break;
5068 case KVM_XEN_HVM_CONFIG: {
5069 struct kvm_xen_hvm_config xhc;
5070 r = -EFAULT;
5071 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5072 goto out;
5073 r = -EINVAL;
5074 if (xhc.flags)
5075 goto out;
5076 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5077 r = 0;
5078 break;
5079 }
5080 case KVM_SET_CLOCK: {
5081 struct kvm_clock_data user_ns;
5082 u64 now_ns;
5083
5084 r = -EFAULT;
5085 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5086 goto out;
5087
5088 r = -EINVAL;
5089 if (user_ns.flags)
5090 goto out;
5091
5092 r = 0;
5093 /*
5094 * TODO: userspace has to take care of races with VCPU_RUN, so
5095 * kvm_gen_update_masterclock() can be cut down to locked
5096 * pvclock_update_vm_gtod_copy().
5097 */
5098 kvm_gen_update_masterclock(kvm);
5099 now_ns = get_kvmclock_ns(kvm);
5100 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5101 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5102 break;
5103 }
5104 case KVM_GET_CLOCK: {
5105 struct kvm_clock_data user_ns;
5106 u64 now_ns;
5107
5108 now_ns = get_kvmclock_ns(kvm);
5109 user_ns.clock = now_ns;
5110 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5111 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5112
5113 r = -EFAULT;
5114 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5115 goto out;
5116 r = 0;
5117 break;
5118 }
5119 case KVM_MEMORY_ENCRYPT_OP: {
5120 r = -ENOTTY;
5121 if (kvm_x86_ops->mem_enc_op)
5122 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5123 break;
5124 }
5125 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5126 struct kvm_enc_region region;
5127
5128 r = -EFAULT;
5129 if (copy_from_user(&region, argp, sizeof(region)))
5130 goto out;
5131
5132 r = -ENOTTY;
5133 if (kvm_x86_ops->mem_enc_reg_region)
5134 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5135 break;
5136 }
5137 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5138 struct kvm_enc_region region;
5139
5140 r = -EFAULT;
5141 if (copy_from_user(&region, argp, sizeof(region)))
5142 goto out;
5143
5144 r = -ENOTTY;
5145 if (kvm_x86_ops->mem_enc_unreg_region)
5146 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5147 break;
5148 }
5149 case KVM_HYPERV_EVENTFD: {
5150 struct kvm_hyperv_eventfd hvevfd;
5151
5152 r = -EFAULT;
5153 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5154 goto out;
5155 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5156 break;
5157 }
5158 case KVM_SET_PMU_EVENT_FILTER:
5159 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5160 break;
5161 default:
5162 r = -ENOTTY;
5163 }
5164 out:
5165 return r;
5166 }
5167
5168 static void kvm_init_msr_list(void)
5169 {
5170 struct x86_pmu_capability x86_pmu;
5171 u32 dummy[2];
5172 unsigned i;
5173
5174 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5175 "Please update the fixed PMCs in msrs_to_saved_all[]");
5176
5177 perf_get_x86_pmu_capability(&x86_pmu);
5178
5179 num_msrs_to_save = 0;
5180 num_emulated_msrs = 0;
5181 num_msr_based_features = 0;
5182
5183 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5184 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5185 continue;
5186
5187 /*
5188 * Even MSRs that are valid in the host may not be exposed
5189 * to the guests in some cases.
5190 */
5191 switch (msrs_to_save_all[i]) {
5192 case MSR_IA32_BNDCFGS:
5193 if (!kvm_mpx_supported())
5194 continue;
5195 break;
5196 case MSR_TSC_AUX:
5197 if (!kvm_x86_ops->rdtscp_supported())
5198 continue;
5199 break;
5200 case MSR_IA32_RTIT_CTL:
5201 case MSR_IA32_RTIT_STATUS:
5202 if (!kvm_x86_ops->pt_supported())
5203 continue;
5204 break;
5205 case MSR_IA32_RTIT_CR3_MATCH:
5206 if (!kvm_x86_ops->pt_supported() ||
5207 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5208 continue;
5209 break;
5210 case MSR_IA32_RTIT_OUTPUT_BASE:
5211 case MSR_IA32_RTIT_OUTPUT_MASK:
5212 if (!kvm_x86_ops->pt_supported() ||
5213 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5214 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5215 continue;
5216 break;
5217 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5218 if (!kvm_x86_ops->pt_supported() ||
5219 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5220 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5221 continue;
5222 break;
5223 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5224 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5225 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5226 continue;
5227 break;
5228 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5229 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5230 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5231 continue;
5232 }
5233 default:
5234 break;
5235 }
5236
5237 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5238 }
5239
5240 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5241 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs_all[i]))
5242 continue;
5243
5244 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5245 }
5246
5247 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5248 struct kvm_msr_entry msr;
5249
5250 msr.index = msr_based_features_all[i];
5251 if (kvm_get_msr_feature(&msr))
5252 continue;
5253
5254 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5255 }
5256 }
5257
5258 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5259 const void *v)
5260 {
5261 int handled = 0;
5262 int n;
5263
5264 do {
5265 n = min(len, 8);
5266 if (!(lapic_in_kernel(vcpu) &&
5267 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5268 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5269 break;
5270 handled += n;
5271 addr += n;
5272 len -= n;
5273 v += n;
5274 } while (len);
5275
5276 return handled;
5277 }
5278
5279 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5280 {
5281 int handled = 0;
5282 int n;
5283
5284 do {
5285 n = min(len, 8);
5286 if (!(lapic_in_kernel(vcpu) &&
5287 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5288 addr, n, v))
5289 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5290 break;
5291 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5292 handled += n;
5293 addr += n;
5294 len -= n;
5295 v += n;
5296 } while (len);
5297
5298 return handled;
5299 }
5300
5301 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5302 struct kvm_segment *var, int seg)
5303 {
5304 kvm_x86_ops->set_segment(vcpu, var, seg);
5305 }
5306
5307 void kvm_get_segment(struct kvm_vcpu *vcpu,
5308 struct kvm_segment *var, int seg)
5309 {
5310 kvm_x86_ops->get_segment(vcpu, var, seg);
5311 }
5312
5313 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5314 struct x86_exception *exception)
5315 {
5316 gpa_t t_gpa;
5317
5318 BUG_ON(!mmu_is_nested(vcpu));
5319
5320 /* NPT walks are always user-walks */
5321 access |= PFERR_USER_MASK;
5322 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5323
5324 return t_gpa;
5325 }
5326
5327 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5328 struct x86_exception *exception)
5329 {
5330 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5331 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5332 }
5333
5334 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5335 struct x86_exception *exception)
5336 {
5337 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5338 access |= PFERR_FETCH_MASK;
5339 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5340 }
5341
5342 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5343 struct x86_exception *exception)
5344 {
5345 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5346 access |= PFERR_WRITE_MASK;
5347 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5348 }
5349
5350 /* uses this to access any guest's mapped memory without checking CPL */
5351 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5352 struct x86_exception *exception)
5353 {
5354 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5355 }
5356
5357 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5358 struct kvm_vcpu *vcpu, u32 access,
5359 struct x86_exception *exception)
5360 {
5361 void *data = val;
5362 int r = X86EMUL_CONTINUE;
5363
5364 while (bytes) {
5365 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5366 exception);
5367 unsigned offset = addr & (PAGE_SIZE-1);
5368 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5369 int ret;
5370
5371 if (gpa == UNMAPPED_GVA)
5372 return X86EMUL_PROPAGATE_FAULT;
5373 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5374 offset, toread);
5375 if (ret < 0) {
5376 r = X86EMUL_IO_NEEDED;
5377 goto out;
5378 }
5379
5380 bytes -= toread;
5381 data += toread;
5382 addr += toread;
5383 }
5384 out:
5385 return r;
5386 }
5387
5388 /* used for instruction fetching */
5389 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5390 gva_t addr, void *val, unsigned int bytes,
5391 struct x86_exception *exception)
5392 {
5393 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5394 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5395 unsigned offset;
5396 int ret;
5397
5398 /* Inline kvm_read_guest_virt_helper for speed. */
5399 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5400 exception);
5401 if (unlikely(gpa == UNMAPPED_GVA))
5402 return X86EMUL_PROPAGATE_FAULT;
5403
5404 offset = addr & (PAGE_SIZE-1);
5405 if (WARN_ON(offset + bytes > PAGE_SIZE))
5406 bytes = (unsigned)PAGE_SIZE - offset;
5407 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5408 offset, bytes);
5409 if (unlikely(ret < 0))
5410 return X86EMUL_IO_NEEDED;
5411
5412 return X86EMUL_CONTINUE;
5413 }
5414
5415 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5416 gva_t addr, void *val, unsigned int bytes,
5417 struct x86_exception *exception)
5418 {
5419 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5420
5421 /*
5422 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5423 * is returned, but our callers are not ready for that and they blindly
5424 * call kvm_inject_page_fault. Ensure that they at least do not leak
5425 * uninitialized kernel stack memory into cr2 and error code.
5426 */
5427 memset(exception, 0, sizeof(*exception));
5428 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5429 exception);
5430 }
5431 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5432
5433 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5434 gva_t addr, void *val, unsigned int bytes,
5435 struct x86_exception *exception, bool system)
5436 {
5437 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5438 u32 access = 0;
5439
5440 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5441 access |= PFERR_USER_MASK;
5442
5443 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5444 }
5445
5446 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5447 unsigned long addr, void *val, unsigned int bytes)
5448 {
5449 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5450 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5451
5452 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5453 }
5454
5455 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5456 struct kvm_vcpu *vcpu, u32 access,
5457 struct x86_exception *exception)
5458 {
5459 void *data = val;
5460 int r = X86EMUL_CONTINUE;
5461
5462 while (bytes) {
5463 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5464 access,
5465 exception);
5466 unsigned offset = addr & (PAGE_SIZE-1);
5467 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5468 int ret;
5469
5470 if (gpa == UNMAPPED_GVA)
5471 return X86EMUL_PROPAGATE_FAULT;
5472 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5473 if (ret < 0) {
5474 r = X86EMUL_IO_NEEDED;
5475 goto out;
5476 }
5477
5478 bytes -= towrite;
5479 data += towrite;
5480 addr += towrite;
5481 }
5482 out:
5483 return r;
5484 }
5485
5486 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5487 unsigned int bytes, struct x86_exception *exception,
5488 bool system)
5489 {
5490 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5491 u32 access = PFERR_WRITE_MASK;
5492
5493 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5494 access |= PFERR_USER_MASK;
5495
5496 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5497 access, exception);
5498 }
5499
5500 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5501 unsigned int bytes, struct x86_exception *exception)
5502 {
5503 /* kvm_write_guest_virt_system can pull in tons of pages. */
5504 vcpu->arch.l1tf_flush_l1d = true;
5505
5506 /*
5507 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5508 * is returned, but our callers are not ready for that and they blindly
5509 * call kvm_inject_page_fault. Ensure that they at least do not leak
5510 * uninitialized kernel stack memory into cr2 and error code.
5511 */
5512 memset(exception, 0, sizeof(*exception));
5513 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5514 PFERR_WRITE_MASK, exception);
5515 }
5516 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5517
5518 int handle_ud(struct kvm_vcpu *vcpu)
5519 {
5520 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5521 int emul_type = EMULTYPE_TRAP_UD;
5522 char sig[5]; /* ud2; .ascii "kvm" */
5523 struct x86_exception e;
5524
5525 if (force_emulation_prefix &&
5526 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5527 sig, sizeof(sig), &e) == 0 &&
5528 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5529 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5530 emul_type = EMULTYPE_TRAP_UD_FORCED;
5531 }
5532
5533 return kvm_emulate_instruction(vcpu, emul_type);
5534 }
5535 EXPORT_SYMBOL_GPL(handle_ud);
5536
5537 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5538 gpa_t gpa, bool write)
5539 {
5540 /* For APIC access vmexit */
5541 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5542 return 1;
5543
5544 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5545 trace_vcpu_match_mmio(gva, gpa, write, true);
5546 return 1;
5547 }
5548
5549 return 0;
5550 }
5551
5552 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5553 gpa_t *gpa, struct x86_exception *exception,
5554 bool write)
5555 {
5556 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5557 | (write ? PFERR_WRITE_MASK : 0);
5558
5559 /*
5560 * currently PKRU is only applied to ept enabled guest so
5561 * there is no pkey in EPT page table for L1 guest or EPT
5562 * shadow page table for L2 guest.
5563 */
5564 if (vcpu_match_mmio_gva(vcpu, gva)
5565 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5566 vcpu->arch.mmio_access, 0, access)) {
5567 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5568 (gva & (PAGE_SIZE - 1));
5569 trace_vcpu_match_mmio(gva, *gpa, write, false);
5570 return 1;
5571 }
5572
5573 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5574
5575 if (*gpa == UNMAPPED_GVA)
5576 return -1;
5577
5578 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5579 }
5580
5581 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5582 const void *val, int bytes)
5583 {
5584 int ret;
5585
5586 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5587 if (ret < 0)
5588 return 0;
5589 kvm_page_track_write(vcpu, gpa, val, bytes);
5590 return 1;
5591 }
5592
5593 struct read_write_emulator_ops {
5594 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5595 int bytes);
5596 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5597 void *val, int bytes);
5598 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5599 int bytes, void *val);
5600 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5601 void *val, int bytes);
5602 bool write;
5603 };
5604
5605 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5606 {
5607 if (vcpu->mmio_read_completed) {
5608 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5609 vcpu->mmio_fragments[0].gpa, val);
5610 vcpu->mmio_read_completed = 0;
5611 return 1;
5612 }
5613
5614 return 0;
5615 }
5616
5617 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5618 void *val, int bytes)
5619 {
5620 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5621 }
5622
5623 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5624 void *val, int bytes)
5625 {
5626 return emulator_write_phys(vcpu, gpa, val, bytes);
5627 }
5628
5629 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5630 {
5631 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5632 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5633 }
5634
5635 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5636 void *val, int bytes)
5637 {
5638 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5639 return X86EMUL_IO_NEEDED;
5640 }
5641
5642 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5643 void *val, int bytes)
5644 {
5645 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5646
5647 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5648 return X86EMUL_CONTINUE;
5649 }
5650
5651 static const struct read_write_emulator_ops read_emultor = {
5652 .read_write_prepare = read_prepare,
5653 .read_write_emulate = read_emulate,
5654 .read_write_mmio = vcpu_mmio_read,
5655 .read_write_exit_mmio = read_exit_mmio,
5656 };
5657
5658 static const struct read_write_emulator_ops write_emultor = {
5659 .read_write_emulate = write_emulate,
5660 .read_write_mmio = write_mmio,
5661 .read_write_exit_mmio = write_exit_mmio,
5662 .write = true,
5663 };
5664
5665 static int emulator_read_write_onepage(unsigned long addr, void *val,
5666 unsigned int bytes,
5667 struct x86_exception *exception,
5668 struct kvm_vcpu *vcpu,
5669 const struct read_write_emulator_ops *ops)
5670 {
5671 gpa_t gpa;
5672 int handled, ret;
5673 bool write = ops->write;
5674 struct kvm_mmio_fragment *frag;
5675 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5676
5677 /*
5678 * If the exit was due to a NPF we may already have a GPA.
5679 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5680 * Note, this cannot be used on string operations since string
5681 * operation using rep will only have the initial GPA from the NPF
5682 * occurred.
5683 */
5684 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5685 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5686 gpa = ctxt->gpa_val;
5687 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5688 } else {
5689 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5690 if (ret < 0)
5691 return X86EMUL_PROPAGATE_FAULT;
5692 }
5693
5694 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5695 return X86EMUL_CONTINUE;
5696
5697 /*
5698 * Is this MMIO handled locally?
5699 */
5700 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5701 if (handled == bytes)
5702 return X86EMUL_CONTINUE;
5703
5704 gpa += handled;
5705 bytes -= handled;
5706 val += handled;
5707
5708 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5709 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5710 frag->gpa = gpa;
5711 frag->data = val;
5712 frag->len = bytes;
5713 return X86EMUL_CONTINUE;
5714 }
5715
5716 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5717 unsigned long addr,
5718 void *val, unsigned int bytes,
5719 struct x86_exception *exception,
5720 const struct read_write_emulator_ops *ops)
5721 {
5722 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5723 gpa_t gpa;
5724 int rc;
5725
5726 if (ops->read_write_prepare &&
5727 ops->read_write_prepare(vcpu, val, bytes))
5728 return X86EMUL_CONTINUE;
5729
5730 vcpu->mmio_nr_fragments = 0;
5731
5732 /* Crossing a page boundary? */
5733 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5734 int now;
5735
5736 now = -addr & ~PAGE_MASK;
5737 rc = emulator_read_write_onepage(addr, val, now, exception,
5738 vcpu, ops);
5739
5740 if (rc != X86EMUL_CONTINUE)
5741 return rc;
5742 addr += now;
5743 if (ctxt->mode != X86EMUL_MODE_PROT64)
5744 addr = (u32)addr;
5745 val += now;
5746 bytes -= now;
5747 }
5748
5749 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5750 vcpu, ops);
5751 if (rc != X86EMUL_CONTINUE)
5752 return rc;
5753
5754 if (!vcpu->mmio_nr_fragments)
5755 return rc;
5756
5757 gpa = vcpu->mmio_fragments[0].gpa;
5758
5759 vcpu->mmio_needed = 1;
5760 vcpu->mmio_cur_fragment = 0;
5761
5762 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5763 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5764 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5765 vcpu->run->mmio.phys_addr = gpa;
5766
5767 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5768 }
5769
5770 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5771 unsigned long addr,
5772 void *val,
5773 unsigned int bytes,
5774 struct x86_exception *exception)
5775 {
5776 return emulator_read_write(ctxt, addr, val, bytes,
5777 exception, &read_emultor);
5778 }
5779
5780 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5781 unsigned long addr,
5782 const void *val,
5783 unsigned int bytes,
5784 struct x86_exception *exception)
5785 {
5786 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5787 exception, &write_emultor);
5788 }
5789
5790 #define CMPXCHG_TYPE(t, ptr, old, new) \
5791 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5792
5793 #ifdef CONFIG_X86_64
5794 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5795 #else
5796 # define CMPXCHG64(ptr, old, new) \
5797 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5798 #endif
5799
5800 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5801 unsigned long addr,
5802 const void *old,
5803 const void *new,
5804 unsigned int bytes,
5805 struct x86_exception *exception)
5806 {
5807 struct kvm_host_map map;
5808 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5809 gpa_t gpa;
5810 char *kaddr;
5811 bool exchanged;
5812
5813 /* guests cmpxchg8b have to be emulated atomically */
5814 if (bytes > 8 || (bytes & (bytes - 1)))
5815 goto emul_write;
5816
5817 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5818
5819 if (gpa == UNMAPPED_GVA ||
5820 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5821 goto emul_write;
5822
5823 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5824 goto emul_write;
5825
5826 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5827 goto emul_write;
5828
5829 kaddr = map.hva + offset_in_page(gpa);
5830
5831 switch (bytes) {
5832 case 1:
5833 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5834 break;
5835 case 2:
5836 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5837 break;
5838 case 4:
5839 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5840 break;
5841 case 8:
5842 exchanged = CMPXCHG64(kaddr, old, new);
5843 break;
5844 default:
5845 BUG();
5846 }
5847
5848 kvm_vcpu_unmap(vcpu, &map, true);
5849
5850 if (!exchanged)
5851 return X86EMUL_CMPXCHG_FAILED;
5852
5853 kvm_page_track_write(vcpu, gpa, new, bytes);
5854
5855 return X86EMUL_CONTINUE;
5856
5857 emul_write:
5858 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5859
5860 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5861 }
5862
5863 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5864 {
5865 int r = 0, i;
5866
5867 for (i = 0; i < vcpu->arch.pio.count; i++) {
5868 if (vcpu->arch.pio.in)
5869 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5870 vcpu->arch.pio.size, pd);
5871 else
5872 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5873 vcpu->arch.pio.port, vcpu->arch.pio.size,
5874 pd);
5875 if (r)
5876 break;
5877 pd += vcpu->arch.pio.size;
5878 }
5879 return r;
5880 }
5881
5882 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5883 unsigned short port, void *val,
5884 unsigned int count, bool in)
5885 {
5886 vcpu->arch.pio.port = port;
5887 vcpu->arch.pio.in = in;
5888 vcpu->arch.pio.count = count;
5889 vcpu->arch.pio.size = size;
5890
5891 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5892 vcpu->arch.pio.count = 0;
5893 return 1;
5894 }
5895
5896 vcpu->run->exit_reason = KVM_EXIT_IO;
5897 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5898 vcpu->run->io.size = size;
5899 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5900 vcpu->run->io.count = count;
5901 vcpu->run->io.port = port;
5902
5903 return 0;
5904 }
5905
5906 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5907 int size, unsigned short port, void *val,
5908 unsigned int count)
5909 {
5910 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5911 int ret;
5912
5913 if (vcpu->arch.pio.count)
5914 goto data_avail;
5915
5916 memset(vcpu->arch.pio_data, 0, size * count);
5917
5918 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5919 if (ret) {
5920 data_avail:
5921 memcpy(val, vcpu->arch.pio_data, size * count);
5922 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5923 vcpu->arch.pio.count = 0;
5924 return 1;
5925 }
5926
5927 return 0;
5928 }
5929
5930 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5931 int size, unsigned short port,
5932 const void *val, unsigned int count)
5933 {
5934 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5935
5936 memcpy(vcpu->arch.pio_data, val, size * count);
5937 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5938 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5939 }
5940
5941 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5942 {
5943 return kvm_x86_ops->get_segment_base(vcpu, seg);
5944 }
5945
5946 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5947 {
5948 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5949 }
5950
5951 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5952 {
5953 if (!need_emulate_wbinvd(vcpu))
5954 return X86EMUL_CONTINUE;
5955
5956 if (kvm_x86_ops->has_wbinvd_exit()) {
5957 int cpu = get_cpu();
5958
5959 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5960 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5961 wbinvd_ipi, NULL, 1);
5962 put_cpu();
5963 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5964 } else
5965 wbinvd();
5966 return X86EMUL_CONTINUE;
5967 }
5968
5969 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5970 {
5971 kvm_emulate_wbinvd_noskip(vcpu);
5972 return kvm_skip_emulated_instruction(vcpu);
5973 }
5974 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5975
5976
5977
5978 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5979 {
5980 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5981 }
5982
5983 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5984 unsigned long *dest)
5985 {
5986 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5987 }
5988
5989 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5990 unsigned long value)
5991 {
5992
5993 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5994 }
5995
5996 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5997 {
5998 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5999 }
6000
6001 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6002 {
6003 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6004 unsigned long value;
6005
6006 switch (cr) {
6007 case 0:
6008 value = kvm_read_cr0(vcpu);
6009 break;
6010 case 2:
6011 value = vcpu->arch.cr2;
6012 break;
6013 case 3:
6014 value = kvm_read_cr3(vcpu);
6015 break;
6016 case 4:
6017 value = kvm_read_cr4(vcpu);
6018 break;
6019 case 8:
6020 value = kvm_get_cr8(vcpu);
6021 break;
6022 default:
6023 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6024 return 0;
6025 }
6026
6027 return value;
6028 }
6029
6030 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6031 {
6032 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6033 int res = 0;
6034
6035 switch (cr) {
6036 case 0:
6037 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6038 break;
6039 case 2:
6040 vcpu->arch.cr2 = val;
6041 break;
6042 case 3:
6043 res = kvm_set_cr3(vcpu, val);
6044 break;
6045 case 4:
6046 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6047 break;
6048 case 8:
6049 res = kvm_set_cr8(vcpu, val);
6050 break;
6051 default:
6052 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6053 res = -1;
6054 }
6055
6056 return res;
6057 }
6058
6059 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6060 {
6061 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
6062 }
6063
6064 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6065 {
6066 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
6067 }
6068
6069 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6070 {
6071 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
6072 }
6073
6074 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6075 {
6076 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6077 }
6078
6079 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6080 {
6081 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6082 }
6083
6084 static unsigned long emulator_get_cached_segment_base(
6085 struct x86_emulate_ctxt *ctxt, int seg)
6086 {
6087 return get_segment_base(emul_to_vcpu(ctxt), seg);
6088 }
6089
6090 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6091 struct desc_struct *desc, u32 *base3,
6092 int seg)
6093 {
6094 struct kvm_segment var;
6095
6096 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6097 *selector = var.selector;
6098
6099 if (var.unusable) {
6100 memset(desc, 0, sizeof(*desc));
6101 if (base3)
6102 *base3 = 0;
6103 return false;
6104 }
6105
6106 if (var.g)
6107 var.limit >>= 12;
6108 set_desc_limit(desc, var.limit);
6109 set_desc_base(desc, (unsigned long)var.base);
6110 #ifdef CONFIG_X86_64
6111 if (base3)
6112 *base3 = var.base >> 32;
6113 #endif
6114 desc->type = var.type;
6115 desc->s = var.s;
6116 desc->dpl = var.dpl;
6117 desc->p = var.present;
6118 desc->avl = var.avl;
6119 desc->l = var.l;
6120 desc->d = var.db;
6121 desc->g = var.g;
6122
6123 return true;
6124 }
6125
6126 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6127 struct desc_struct *desc, u32 base3,
6128 int seg)
6129 {
6130 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6131 struct kvm_segment var;
6132
6133 var.selector = selector;
6134 var.base = get_desc_base(desc);
6135 #ifdef CONFIG_X86_64
6136 var.base |= ((u64)base3) << 32;
6137 #endif
6138 var.limit = get_desc_limit(desc);
6139 if (desc->g)
6140 var.limit = (var.limit << 12) | 0xfff;
6141 var.type = desc->type;
6142 var.dpl = desc->dpl;
6143 var.db = desc->d;
6144 var.s = desc->s;
6145 var.l = desc->l;
6146 var.g = desc->g;
6147 var.avl = desc->avl;
6148 var.present = desc->p;
6149 var.unusable = !var.present;
6150 var.padding = 0;
6151
6152 kvm_set_segment(vcpu, &var, seg);
6153 return;
6154 }
6155
6156 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6157 u32 msr_index, u64 *pdata)
6158 {
6159 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6160 }
6161
6162 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6163 u32 msr_index, u64 data)
6164 {
6165 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6166 }
6167
6168 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6169 {
6170 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6171
6172 return vcpu->arch.smbase;
6173 }
6174
6175 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6176 {
6177 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6178
6179 vcpu->arch.smbase = smbase;
6180 }
6181
6182 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6183 u32 pmc)
6184 {
6185 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6186 }
6187
6188 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6189 u32 pmc, u64 *pdata)
6190 {
6191 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6192 }
6193
6194 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6195 {
6196 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6197 }
6198
6199 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6200 struct x86_instruction_info *info,
6201 enum x86_intercept_stage stage)
6202 {
6203 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6204 }
6205
6206 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6207 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6208 {
6209 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6210 }
6211
6212 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6213 {
6214 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6215 }
6216
6217 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6218 {
6219 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6220 }
6221
6222 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6223 {
6224 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6225 }
6226
6227 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6228 {
6229 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6230 }
6231
6232 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6233 {
6234 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6235 }
6236
6237 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6238 {
6239 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6240 }
6241
6242 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6243 {
6244 return emul_to_vcpu(ctxt)->arch.hflags;
6245 }
6246
6247 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6248 {
6249 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6250 }
6251
6252 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6253 const char *smstate)
6254 {
6255 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6256 }
6257
6258 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6259 {
6260 kvm_smm_changed(emul_to_vcpu(ctxt));
6261 }
6262
6263 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6264 {
6265 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6266 }
6267
6268 static const struct x86_emulate_ops emulate_ops = {
6269 .read_gpr = emulator_read_gpr,
6270 .write_gpr = emulator_write_gpr,
6271 .read_std = emulator_read_std,
6272 .write_std = emulator_write_std,
6273 .read_phys = kvm_read_guest_phys_system,
6274 .fetch = kvm_fetch_guest_virt,
6275 .read_emulated = emulator_read_emulated,
6276 .write_emulated = emulator_write_emulated,
6277 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6278 .invlpg = emulator_invlpg,
6279 .pio_in_emulated = emulator_pio_in_emulated,
6280 .pio_out_emulated = emulator_pio_out_emulated,
6281 .get_segment = emulator_get_segment,
6282 .set_segment = emulator_set_segment,
6283 .get_cached_segment_base = emulator_get_cached_segment_base,
6284 .get_gdt = emulator_get_gdt,
6285 .get_idt = emulator_get_idt,
6286 .set_gdt = emulator_set_gdt,
6287 .set_idt = emulator_set_idt,
6288 .get_cr = emulator_get_cr,
6289 .set_cr = emulator_set_cr,
6290 .cpl = emulator_get_cpl,
6291 .get_dr = emulator_get_dr,
6292 .set_dr = emulator_set_dr,
6293 .get_smbase = emulator_get_smbase,
6294 .set_smbase = emulator_set_smbase,
6295 .set_msr = emulator_set_msr,
6296 .get_msr = emulator_get_msr,
6297 .check_pmc = emulator_check_pmc,
6298 .read_pmc = emulator_read_pmc,
6299 .halt = emulator_halt,
6300 .wbinvd = emulator_wbinvd,
6301 .fix_hypercall = emulator_fix_hypercall,
6302 .intercept = emulator_intercept,
6303 .get_cpuid = emulator_get_cpuid,
6304 .guest_has_long_mode = emulator_guest_has_long_mode,
6305 .guest_has_movbe = emulator_guest_has_movbe,
6306 .guest_has_fxsr = emulator_guest_has_fxsr,
6307 .set_nmi_mask = emulator_set_nmi_mask,
6308 .get_hflags = emulator_get_hflags,
6309 .set_hflags = emulator_set_hflags,
6310 .pre_leave_smm = emulator_pre_leave_smm,
6311 .post_leave_smm = emulator_post_leave_smm,
6312 .set_xcr = emulator_set_xcr,
6313 };
6314
6315 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6316 {
6317 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6318 /*
6319 * an sti; sti; sequence only disable interrupts for the first
6320 * instruction. So, if the last instruction, be it emulated or
6321 * not, left the system with the INT_STI flag enabled, it
6322 * means that the last instruction is an sti. We should not
6323 * leave the flag on in this case. The same goes for mov ss
6324 */
6325 if (int_shadow & mask)
6326 mask = 0;
6327 if (unlikely(int_shadow || mask)) {
6328 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6329 if (!mask)
6330 kvm_make_request(KVM_REQ_EVENT, vcpu);
6331 }
6332 }
6333
6334 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6335 {
6336 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6337 if (ctxt->exception.vector == PF_VECTOR)
6338 return kvm_propagate_fault(vcpu, &ctxt->exception);
6339
6340 if (ctxt->exception.error_code_valid)
6341 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6342 ctxt->exception.error_code);
6343 else
6344 kvm_queue_exception(vcpu, ctxt->exception.vector);
6345 return false;
6346 }
6347
6348 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6349 {
6350 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6351 int cs_db, cs_l;
6352
6353 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6354
6355 ctxt->gpa_available = false;
6356 ctxt->eflags = kvm_get_rflags(vcpu);
6357 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6358
6359 ctxt->eip = kvm_rip_read(vcpu);
6360 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6361 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6362 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6363 cs_db ? X86EMUL_MODE_PROT32 :
6364 X86EMUL_MODE_PROT16;
6365 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6366 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6367 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6368
6369 init_decode_cache(ctxt);
6370 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6371 }
6372
6373 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6374 {
6375 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6376 int ret;
6377
6378 init_emulate_ctxt(vcpu);
6379
6380 ctxt->op_bytes = 2;
6381 ctxt->ad_bytes = 2;
6382 ctxt->_eip = ctxt->eip + inc_eip;
6383 ret = emulate_int_real(ctxt, irq);
6384
6385 if (ret != X86EMUL_CONTINUE) {
6386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6387 } else {
6388 ctxt->eip = ctxt->_eip;
6389 kvm_rip_write(vcpu, ctxt->eip);
6390 kvm_set_rflags(vcpu, ctxt->eflags);
6391 }
6392 }
6393 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6394
6395 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6396 {
6397 ++vcpu->stat.insn_emulation_fail;
6398 trace_kvm_emulate_insn_failed(vcpu);
6399
6400 if (emulation_type & EMULTYPE_VMWARE_GP) {
6401 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6402 return 1;
6403 }
6404
6405 if (emulation_type & EMULTYPE_SKIP) {
6406 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6407 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6408 vcpu->run->internal.ndata = 0;
6409 return 0;
6410 }
6411
6412 kvm_queue_exception(vcpu, UD_VECTOR);
6413
6414 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6415 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6416 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6417 vcpu->run->internal.ndata = 0;
6418 return 0;
6419 }
6420
6421 return 1;
6422 }
6423
6424 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6425 bool write_fault_to_shadow_pgtable,
6426 int emulation_type)
6427 {
6428 gpa_t gpa = cr2_or_gpa;
6429 kvm_pfn_t pfn;
6430
6431 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6432 return false;
6433
6434 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6435 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6436 return false;
6437
6438 if (!vcpu->arch.mmu->direct_map) {
6439 /*
6440 * Write permission should be allowed since only
6441 * write access need to be emulated.
6442 */
6443 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6444
6445 /*
6446 * If the mapping is invalid in guest, let cpu retry
6447 * it to generate fault.
6448 */
6449 if (gpa == UNMAPPED_GVA)
6450 return true;
6451 }
6452
6453 /*
6454 * Do not retry the unhandleable instruction if it faults on the
6455 * readonly host memory, otherwise it will goto a infinite loop:
6456 * retry instruction -> write #PF -> emulation fail -> retry
6457 * instruction -> ...
6458 */
6459 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6460
6461 /*
6462 * If the instruction failed on the error pfn, it can not be fixed,
6463 * report the error to userspace.
6464 */
6465 if (is_error_noslot_pfn(pfn))
6466 return false;
6467
6468 kvm_release_pfn_clean(pfn);
6469
6470 /* The instructions are well-emulated on direct mmu. */
6471 if (vcpu->arch.mmu->direct_map) {
6472 unsigned int indirect_shadow_pages;
6473
6474 spin_lock(&vcpu->kvm->mmu_lock);
6475 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6476 spin_unlock(&vcpu->kvm->mmu_lock);
6477
6478 if (indirect_shadow_pages)
6479 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6480
6481 return true;
6482 }
6483
6484 /*
6485 * if emulation was due to access to shadowed page table
6486 * and it failed try to unshadow page and re-enter the
6487 * guest to let CPU execute the instruction.
6488 */
6489 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6490
6491 /*
6492 * If the access faults on its page table, it can not
6493 * be fixed by unprotecting shadow page and it should
6494 * be reported to userspace.
6495 */
6496 return !write_fault_to_shadow_pgtable;
6497 }
6498
6499 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6500 gpa_t cr2_or_gpa, int emulation_type)
6501 {
6502 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6503 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6504
6505 last_retry_eip = vcpu->arch.last_retry_eip;
6506 last_retry_addr = vcpu->arch.last_retry_addr;
6507
6508 /*
6509 * If the emulation is caused by #PF and it is non-page_table
6510 * writing instruction, it means the VM-EXIT is caused by shadow
6511 * page protected, we can zap the shadow page and retry this
6512 * instruction directly.
6513 *
6514 * Note: if the guest uses a non-page-table modifying instruction
6515 * on the PDE that points to the instruction, then we will unmap
6516 * the instruction and go to an infinite loop. So, we cache the
6517 * last retried eip and the last fault address, if we meet the eip
6518 * and the address again, we can break out of the potential infinite
6519 * loop.
6520 */
6521 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6522
6523 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6524 return false;
6525
6526 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6527 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6528 return false;
6529
6530 if (x86_page_table_writing_insn(ctxt))
6531 return false;
6532
6533 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6534 return false;
6535
6536 vcpu->arch.last_retry_eip = ctxt->eip;
6537 vcpu->arch.last_retry_addr = cr2_or_gpa;
6538
6539 if (!vcpu->arch.mmu->direct_map)
6540 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6541
6542 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6543
6544 return true;
6545 }
6546
6547 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6548 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6549
6550 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6551 {
6552 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6553 /* This is a good place to trace that we are exiting SMM. */
6554 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6555
6556 /* Process a latched INIT or SMI, if any. */
6557 kvm_make_request(KVM_REQ_EVENT, vcpu);
6558 }
6559
6560 kvm_mmu_reset_context(vcpu);
6561 }
6562
6563 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6564 unsigned long *db)
6565 {
6566 u32 dr6 = 0;
6567 int i;
6568 u32 enable, rwlen;
6569
6570 enable = dr7;
6571 rwlen = dr7 >> 16;
6572 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6573 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6574 dr6 |= (1 << i);
6575 return dr6;
6576 }
6577
6578 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6579 {
6580 struct kvm_run *kvm_run = vcpu->run;
6581
6582 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6583 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6584 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6585 kvm_run->debug.arch.exception = DB_VECTOR;
6586 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6587 return 0;
6588 }
6589 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6590 return 1;
6591 }
6592
6593 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6594 {
6595 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6596 int r;
6597
6598 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6599 if (unlikely(!r))
6600 return 0;
6601
6602 /*
6603 * rflags is the old, "raw" value of the flags. The new value has
6604 * not been saved yet.
6605 *
6606 * This is correct even for TF set by the guest, because "the
6607 * processor will not generate this exception after the instruction
6608 * that sets the TF flag".
6609 */
6610 if (unlikely(rflags & X86_EFLAGS_TF))
6611 r = kvm_vcpu_do_singlestep(vcpu);
6612 return r;
6613 }
6614 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6615
6616 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6617 {
6618 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6619 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6620 struct kvm_run *kvm_run = vcpu->run;
6621 unsigned long eip = kvm_get_linear_rip(vcpu);
6622 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6623 vcpu->arch.guest_debug_dr7,
6624 vcpu->arch.eff_db);
6625
6626 if (dr6 != 0) {
6627 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6628 kvm_run->debug.arch.pc = eip;
6629 kvm_run->debug.arch.exception = DB_VECTOR;
6630 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6631 *r = 0;
6632 return true;
6633 }
6634 }
6635
6636 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6637 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6638 unsigned long eip = kvm_get_linear_rip(vcpu);
6639 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6640 vcpu->arch.dr7,
6641 vcpu->arch.db);
6642
6643 if (dr6 != 0) {
6644 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6645 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6646 kvm_queue_exception(vcpu, DB_VECTOR);
6647 *r = 1;
6648 return true;
6649 }
6650 }
6651
6652 return false;
6653 }
6654
6655 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6656 {
6657 switch (ctxt->opcode_len) {
6658 case 1:
6659 switch (ctxt->b) {
6660 case 0xe4: /* IN */
6661 case 0xe5:
6662 case 0xec:
6663 case 0xed:
6664 case 0xe6: /* OUT */
6665 case 0xe7:
6666 case 0xee:
6667 case 0xef:
6668 case 0x6c: /* INS */
6669 case 0x6d:
6670 case 0x6e: /* OUTS */
6671 case 0x6f:
6672 return true;
6673 }
6674 break;
6675 case 2:
6676 switch (ctxt->b) {
6677 case 0x33: /* RDPMC */
6678 return true;
6679 }
6680 break;
6681 }
6682
6683 return false;
6684 }
6685
6686 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6687 int emulation_type, void *insn, int insn_len)
6688 {
6689 int r;
6690 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6691 bool writeback = true;
6692 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6693
6694 vcpu->arch.l1tf_flush_l1d = true;
6695
6696 /*
6697 * Clear write_fault_to_shadow_pgtable here to ensure it is
6698 * never reused.
6699 */
6700 vcpu->arch.write_fault_to_shadow_pgtable = false;
6701 kvm_clear_exception_queue(vcpu);
6702
6703 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6704 init_emulate_ctxt(vcpu);
6705
6706 /*
6707 * We will reenter on the same instruction since
6708 * we do not set complete_userspace_io. This does not
6709 * handle watchpoints yet, those would be handled in
6710 * the emulate_ops.
6711 */
6712 if (!(emulation_type & EMULTYPE_SKIP) &&
6713 kvm_vcpu_check_breakpoint(vcpu, &r))
6714 return r;
6715
6716 ctxt->interruptibility = 0;
6717 ctxt->have_exception = false;
6718 ctxt->exception.vector = -1;
6719 ctxt->perm_ok = false;
6720
6721 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6722
6723 r = x86_decode_insn(ctxt, insn, insn_len);
6724
6725 trace_kvm_emulate_insn_start(vcpu);
6726 ++vcpu->stat.insn_emulation;
6727 if (r != EMULATION_OK) {
6728 if ((emulation_type & EMULTYPE_TRAP_UD) ||
6729 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6730 kvm_queue_exception(vcpu, UD_VECTOR);
6731 return 1;
6732 }
6733 if (reexecute_instruction(vcpu, cr2_or_gpa,
6734 write_fault_to_spt,
6735 emulation_type))
6736 return 1;
6737 if (ctxt->have_exception) {
6738 /*
6739 * #UD should result in just EMULATION_FAILED, and trap-like
6740 * exception should not be encountered during decode.
6741 */
6742 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6743 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6744 inject_emulated_exception(vcpu);
6745 return 1;
6746 }
6747 return handle_emulation_failure(vcpu, emulation_type);
6748 }
6749 }
6750
6751 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6752 !is_vmware_backdoor_opcode(ctxt)) {
6753 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6754 return 1;
6755 }
6756
6757 /*
6758 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6759 * for kvm_skip_emulated_instruction(). The caller is responsible for
6760 * updating interruptibility state and injecting single-step #DBs.
6761 */
6762 if (emulation_type & EMULTYPE_SKIP) {
6763 kvm_rip_write(vcpu, ctxt->_eip);
6764 if (ctxt->eflags & X86_EFLAGS_RF)
6765 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6766 return 1;
6767 }
6768
6769 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6770 return 1;
6771
6772 /* this is needed for vmware backdoor interface to work since it
6773 changes registers values during IO operation */
6774 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6775 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6776 emulator_invalidate_register_cache(ctxt);
6777 }
6778
6779 restart:
6780 if (emulation_type & EMULTYPE_PF) {
6781 /* Save the faulting GPA (cr2) in the address field */
6782 ctxt->exception.address = cr2_or_gpa;
6783
6784 /* With shadow page tables, cr2 contains a GVA or nGPA. */
6785 if (vcpu->arch.mmu->direct_map) {
6786 ctxt->gpa_available = true;
6787 ctxt->gpa_val = cr2_or_gpa;
6788 }
6789 } else {
6790 /* Sanitize the address out of an abundance of paranoia. */
6791 ctxt->exception.address = 0;
6792 }
6793
6794 r = x86_emulate_insn(ctxt);
6795
6796 if (r == EMULATION_INTERCEPTED)
6797 return 1;
6798
6799 if (r == EMULATION_FAILED) {
6800 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6801 emulation_type))
6802 return 1;
6803
6804 return handle_emulation_failure(vcpu, emulation_type);
6805 }
6806
6807 if (ctxt->have_exception) {
6808 r = 1;
6809 if (inject_emulated_exception(vcpu))
6810 return r;
6811 } else if (vcpu->arch.pio.count) {
6812 if (!vcpu->arch.pio.in) {
6813 /* FIXME: return into emulator if single-stepping. */
6814 vcpu->arch.pio.count = 0;
6815 } else {
6816 writeback = false;
6817 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6818 }
6819 r = 0;
6820 } else if (vcpu->mmio_needed) {
6821 ++vcpu->stat.mmio_exits;
6822
6823 if (!vcpu->mmio_is_write)
6824 writeback = false;
6825 r = 0;
6826 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6827 } else if (r == EMULATION_RESTART)
6828 goto restart;
6829 else
6830 r = 1;
6831
6832 if (writeback) {
6833 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6834 toggle_interruptibility(vcpu, ctxt->interruptibility);
6835 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6836 if (!ctxt->have_exception ||
6837 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6838 kvm_rip_write(vcpu, ctxt->eip);
6839 if (r && ctxt->tf)
6840 r = kvm_vcpu_do_singlestep(vcpu);
6841 if (kvm_x86_ops->update_emulated_instruction)
6842 kvm_x86_ops->update_emulated_instruction(vcpu);
6843 __kvm_set_rflags(vcpu, ctxt->eflags);
6844 }
6845
6846 /*
6847 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6848 * do nothing, and it will be requested again as soon as
6849 * the shadow expires. But we still need to check here,
6850 * because POPF has no interrupt shadow.
6851 */
6852 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6853 kvm_make_request(KVM_REQ_EVENT, vcpu);
6854 } else
6855 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6856
6857 return r;
6858 }
6859
6860 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6861 {
6862 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6863 }
6864 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6865
6866 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6867 void *insn, int insn_len)
6868 {
6869 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6870 }
6871 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6872
6873 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6874 {
6875 vcpu->arch.pio.count = 0;
6876 return 1;
6877 }
6878
6879 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6880 {
6881 vcpu->arch.pio.count = 0;
6882
6883 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6884 return 1;
6885
6886 return kvm_skip_emulated_instruction(vcpu);
6887 }
6888
6889 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6890 unsigned short port)
6891 {
6892 unsigned long val = kvm_rax_read(vcpu);
6893 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6894 size, port, &val, 1);
6895 if (ret)
6896 return ret;
6897
6898 /*
6899 * Workaround userspace that relies on old KVM behavior of %rip being
6900 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6901 */
6902 if (port == 0x7e &&
6903 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6904 vcpu->arch.complete_userspace_io =
6905 complete_fast_pio_out_port_0x7e;
6906 kvm_skip_emulated_instruction(vcpu);
6907 } else {
6908 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6909 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6910 }
6911 return 0;
6912 }
6913
6914 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6915 {
6916 unsigned long val;
6917
6918 /* We should only ever be called with arch.pio.count equal to 1 */
6919 BUG_ON(vcpu->arch.pio.count != 1);
6920
6921 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6922 vcpu->arch.pio.count = 0;
6923 return 1;
6924 }
6925
6926 /* For size less than 4 we merge, else we zero extend */
6927 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6928
6929 /*
6930 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6931 * the copy and tracing
6932 */
6933 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6934 vcpu->arch.pio.port, &val, 1);
6935 kvm_rax_write(vcpu, val);
6936
6937 return kvm_skip_emulated_instruction(vcpu);
6938 }
6939
6940 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6941 unsigned short port)
6942 {
6943 unsigned long val;
6944 int ret;
6945
6946 /* For size less than 4 we merge, else we zero extend */
6947 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6948
6949 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6950 &val, 1);
6951 if (ret) {
6952 kvm_rax_write(vcpu, val);
6953 return ret;
6954 }
6955
6956 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6957 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6958
6959 return 0;
6960 }
6961
6962 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6963 {
6964 int ret;
6965
6966 if (in)
6967 ret = kvm_fast_pio_in(vcpu, size, port);
6968 else
6969 ret = kvm_fast_pio_out(vcpu, size, port);
6970 return ret && kvm_skip_emulated_instruction(vcpu);
6971 }
6972 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6973
6974 static int kvmclock_cpu_down_prep(unsigned int cpu)
6975 {
6976 __this_cpu_write(cpu_tsc_khz, 0);
6977 return 0;
6978 }
6979
6980 static void tsc_khz_changed(void *data)
6981 {
6982 struct cpufreq_freqs *freq = data;
6983 unsigned long khz = 0;
6984
6985 if (data)
6986 khz = freq->new;
6987 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6988 khz = cpufreq_quick_get(raw_smp_processor_id());
6989 if (!khz)
6990 khz = tsc_khz;
6991 __this_cpu_write(cpu_tsc_khz, khz);
6992 }
6993
6994 #ifdef CONFIG_X86_64
6995 static void kvm_hyperv_tsc_notifier(void)
6996 {
6997 struct kvm *kvm;
6998 struct kvm_vcpu *vcpu;
6999 int cpu;
7000
7001 mutex_lock(&kvm_lock);
7002 list_for_each_entry(kvm, &vm_list, vm_list)
7003 kvm_make_mclock_inprogress_request(kvm);
7004
7005 hyperv_stop_tsc_emulation();
7006
7007 /* TSC frequency always matches when on Hyper-V */
7008 for_each_present_cpu(cpu)
7009 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7010 kvm_max_guest_tsc_khz = tsc_khz;
7011
7012 list_for_each_entry(kvm, &vm_list, vm_list) {
7013 struct kvm_arch *ka = &kvm->arch;
7014
7015 spin_lock(&ka->pvclock_gtod_sync_lock);
7016
7017 pvclock_update_vm_gtod_copy(kvm);
7018
7019 kvm_for_each_vcpu(cpu, vcpu, kvm)
7020 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7021
7022 kvm_for_each_vcpu(cpu, vcpu, kvm)
7023 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7024
7025 spin_unlock(&ka->pvclock_gtod_sync_lock);
7026 }
7027 mutex_unlock(&kvm_lock);
7028 }
7029 #endif
7030
7031 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7032 {
7033 struct kvm *kvm;
7034 struct kvm_vcpu *vcpu;
7035 int i, send_ipi = 0;
7036
7037 /*
7038 * We allow guests to temporarily run on slowing clocks,
7039 * provided we notify them after, or to run on accelerating
7040 * clocks, provided we notify them before. Thus time never
7041 * goes backwards.
7042 *
7043 * However, we have a problem. We can't atomically update
7044 * the frequency of a given CPU from this function; it is
7045 * merely a notifier, which can be called from any CPU.
7046 * Changing the TSC frequency at arbitrary points in time
7047 * requires a recomputation of local variables related to
7048 * the TSC for each VCPU. We must flag these local variables
7049 * to be updated and be sure the update takes place with the
7050 * new frequency before any guests proceed.
7051 *
7052 * Unfortunately, the combination of hotplug CPU and frequency
7053 * change creates an intractable locking scenario; the order
7054 * of when these callouts happen is undefined with respect to
7055 * CPU hotplug, and they can race with each other. As such,
7056 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7057 * undefined; you can actually have a CPU frequency change take
7058 * place in between the computation of X and the setting of the
7059 * variable. To protect against this problem, all updates of
7060 * the per_cpu tsc_khz variable are done in an interrupt
7061 * protected IPI, and all callers wishing to update the value
7062 * must wait for a synchronous IPI to complete (which is trivial
7063 * if the caller is on the CPU already). This establishes the
7064 * necessary total order on variable updates.
7065 *
7066 * Note that because a guest time update may take place
7067 * anytime after the setting of the VCPU's request bit, the
7068 * correct TSC value must be set before the request. However,
7069 * to ensure the update actually makes it to any guest which
7070 * starts running in hardware virtualization between the set
7071 * and the acquisition of the spinlock, we must also ping the
7072 * CPU after setting the request bit.
7073 *
7074 */
7075
7076 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7077
7078 mutex_lock(&kvm_lock);
7079 list_for_each_entry(kvm, &vm_list, vm_list) {
7080 kvm_for_each_vcpu(i, vcpu, kvm) {
7081 if (vcpu->cpu != cpu)
7082 continue;
7083 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7084 if (vcpu->cpu != raw_smp_processor_id())
7085 send_ipi = 1;
7086 }
7087 }
7088 mutex_unlock(&kvm_lock);
7089
7090 if (freq->old < freq->new && send_ipi) {
7091 /*
7092 * We upscale the frequency. Must make the guest
7093 * doesn't see old kvmclock values while running with
7094 * the new frequency, otherwise we risk the guest sees
7095 * time go backwards.
7096 *
7097 * In case we update the frequency for another cpu
7098 * (which might be in guest context) send an interrupt
7099 * to kick the cpu out of guest context. Next time
7100 * guest context is entered kvmclock will be updated,
7101 * so the guest will not see stale values.
7102 */
7103 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7104 }
7105 }
7106
7107 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7108 void *data)
7109 {
7110 struct cpufreq_freqs *freq = data;
7111 int cpu;
7112
7113 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7114 return 0;
7115 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7116 return 0;
7117
7118 for_each_cpu(cpu, freq->policy->cpus)
7119 __kvmclock_cpufreq_notifier(freq, cpu);
7120
7121 return 0;
7122 }
7123
7124 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7125 .notifier_call = kvmclock_cpufreq_notifier
7126 };
7127
7128 static int kvmclock_cpu_online(unsigned int cpu)
7129 {
7130 tsc_khz_changed(NULL);
7131 return 0;
7132 }
7133
7134 static void kvm_timer_init(void)
7135 {
7136 max_tsc_khz = tsc_khz;
7137
7138 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7139 #ifdef CONFIG_CPU_FREQ
7140 struct cpufreq_policy policy;
7141 int cpu;
7142
7143 memset(&policy, 0, sizeof(policy));
7144 cpu = get_cpu();
7145 cpufreq_get_policy(&policy, cpu);
7146 if (policy.cpuinfo.max_freq)
7147 max_tsc_khz = policy.cpuinfo.max_freq;
7148 put_cpu();
7149 #endif
7150 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7151 CPUFREQ_TRANSITION_NOTIFIER);
7152 }
7153
7154 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7155 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7156 }
7157
7158 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7159 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7160
7161 int kvm_is_in_guest(void)
7162 {
7163 return __this_cpu_read(current_vcpu) != NULL;
7164 }
7165
7166 static int kvm_is_user_mode(void)
7167 {
7168 int user_mode = 3;
7169
7170 if (__this_cpu_read(current_vcpu))
7171 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
7172
7173 return user_mode != 0;
7174 }
7175
7176 static unsigned long kvm_get_guest_ip(void)
7177 {
7178 unsigned long ip = 0;
7179
7180 if (__this_cpu_read(current_vcpu))
7181 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7182
7183 return ip;
7184 }
7185
7186 static void kvm_handle_intel_pt_intr(void)
7187 {
7188 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7189
7190 kvm_make_request(KVM_REQ_PMI, vcpu);
7191 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7192 (unsigned long *)&vcpu->arch.pmu.global_status);
7193 }
7194
7195 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7196 .is_in_guest = kvm_is_in_guest,
7197 .is_user_mode = kvm_is_user_mode,
7198 .get_guest_ip = kvm_get_guest_ip,
7199 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7200 };
7201
7202 #ifdef CONFIG_X86_64
7203 static void pvclock_gtod_update_fn(struct work_struct *work)
7204 {
7205 struct kvm *kvm;
7206
7207 struct kvm_vcpu *vcpu;
7208 int i;
7209
7210 mutex_lock(&kvm_lock);
7211 list_for_each_entry(kvm, &vm_list, vm_list)
7212 kvm_for_each_vcpu(i, vcpu, kvm)
7213 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7214 atomic_set(&kvm_guest_has_master_clock, 0);
7215 mutex_unlock(&kvm_lock);
7216 }
7217
7218 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7219
7220 /*
7221 * Notification about pvclock gtod data update.
7222 */
7223 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7224 void *priv)
7225 {
7226 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7227 struct timekeeper *tk = priv;
7228
7229 update_pvclock_gtod(tk);
7230
7231 /* disable master clock if host does not trust, or does not
7232 * use, TSC based clocksource.
7233 */
7234 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7235 atomic_read(&kvm_guest_has_master_clock) != 0)
7236 queue_work(system_long_wq, &pvclock_gtod_work);
7237
7238 return 0;
7239 }
7240
7241 static struct notifier_block pvclock_gtod_notifier = {
7242 .notifier_call = pvclock_gtod_notify,
7243 };
7244 #endif
7245
7246 int kvm_arch_init(void *opaque)
7247 {
7248 int r;
7249 struct kvm_x86_ops *ops = opaque;
7250
7251 if (kvm_x86_ops) {
7252 printk(KERN_ERR "kvm: already loaded the other module\n");
7253 r = -EEXIST;
7254 goto out;
7255 }
7256
7257 if (!ops->cpu_has_kvm_support()) {
7258 printk(KERN_ERR "kvm: no hardware support\n");
7259 r = -EOPNOTSUPP;
7260 goto out;
7261 }
7262 if (ops->disabled_by_bios()) {
7263 printk(KERN_ERR "kvm: disabled by bios\n");
7264 r = -EOPNOTSUPP;
7265 goto out;
7266 }
7267
7268 /*
7269 * KVM explicitly assumes that the guest has an FPU and
7270 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7271 * vCPU's FPU state as a fxregs_state struct.
7272 */
7273 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7274 printk(KERN_ERR "kvm: inadequate fpu\n");
7275 r = -EOPNOTSUPP;
7276 goto out;
7277 }
7278
7279 r = -ENOMEM;
7280 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7281 __alignof__(struct fpu), SLAB_ACCOUNT,
7282 NULL);
7283 if (!x86_fpu_cache) {
7284 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7285 goto out;
7286 }
7287
7288 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7289 if (!shared_msrs) {
7290 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7291 goto out_free_x86_fpu_cache;
7292 }
7293
7294 r = kvm_mmu_module_init();
7295 if (r)
7296 goto out_free_percpu;
7297
7298 kvm_x86_ops = ops;
7299
7300 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7301 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7302 PT_PRESENT_MASK, 0, sme_me_mask);
7303 kvm_timer_init();
7304
7305 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7306
7307 if (boot_cpu_has(X86_FEATURE_XSAVE))
7308 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7309
7310 kvm_lapic_init();
7311 if (pi_inject_timer == -1)
7312 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7313 #ifdef CONFIG_X86_64
7314 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7315
7316 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7317 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7318 #endif
7319
7320 return 0;
7321
7322 out_free_percpu:
7323 free_percpu(shared_msrs);
7324 out_free_x86_fpu_cache:
7325 kmem_cache_destroy(x86_fpu_cache);
7326 out:
7327 return r;
7328 }
7329
7330 void kvm_arch_exit(void)
7331 {
7332 #ifdef CONFIG_X86_64
7333 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7334 clear_hv_tscchange_cb();
7335 #endif
7336 kvm_lapic_exit();
7337 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7338
7339 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7340 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7341 CPUFREQ_TRANSITION_NOTIFIER);
7342 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7343 #ifdef CONFIG_X86_64
7344 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7345 #endif
7346 kvm_x86_ops = NULL;
7347 kvm_mmu_module_exit();
7348 free_percpu(shared_msrs);
7349 kmem_cache_destroy(x86_fpu_cache);
7350 }
7351
7352 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7353 {
7354 ++vcpu->stat.halt_exits;
7355 if (lapic_in_kernel(vcpu)) {
7356 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7357 return 1;
7358 } else {
7359 vcpu->run->exit_reason = KVM_EXIT_HLT;
7360 return 0;
7361 }
7362 }
7363 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7364
7365 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7366 {
7367 int ret = kvm_skip_emulated_instruction(vcpu);
7368 /*
7369 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7370 * KVM_EXIT_DEBUG here.
7371 */
7372 return kvm_vcpu_halt(vcpu) && ret;
7373 }
7374 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7375
7376 #ifdef CONFIG_X86_64
7377 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7378 unsigned long clock_type)
7379 {
7380 struct kvm_clock_pairing clock_pairing;
7381 struct timespec64 ts;
7382 u64 cycle;
7383 int ret;
7384
7385 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7386 return -KVM_EOPNOTSUPP;
7387
7388 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7389 return -KVM_EOPNOTSUPP;
7390
7391 clock_pairing.sec = ts.tv_sec;
7392 clock_pairing.nsec = ts.tv_nsec;
7393 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7394 clock_pairing.flags = 0;
7395 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7396
7397 ret = 0;
7398 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7399 sizeof(struct kvm_clock_pairing)))
7400 ret = -KVM_EFAULT;
7401
7402 return ret;
7403 }
7404 #endif
7405
7406 /*
7407 * kvm_pv_kick_cpu_op: Kick a vcpu.
7408 *
7409 * @apicid - apicid of vcpu to be kicked.
7410 */
7411 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7412 {
7413 struct kvm_lapic_irq lapic_irq;
7414
7415 lapic_irq.shorthand = APIC_DEST_NOSHORT;
7416 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7417 lapic_irq.level = 0;
7418 lapic_irq.dest_id = apicid;
7419 lapic_irq.msi_redir_hint = false;
7420
7421 lapic_irq.delivery_mode = APIC_DM_REMRD;
7422 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7423 }
7424
7425 bool kvm_apicv_activated(struct kvm *kvm)
7426 {
7427 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7428 }
7429 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7430
7431 void kvm_apicv_init(struct kvm *kvm, bool enable)
7432 {
7433 if (enable)
7434 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7435 &kvm->arch.apicv_inhibit_reasons);
7436 else
7437 set_bit(APICV_INHIBIT_REASON_DISABLE,
7438 &kvm->arch.apicv_inhibit_reasons);
7439 }
7440 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7441
7442 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7443 {
7444 struct kvm_vcpu *target = NULL;
7445 struct kvm_apic_map *map;
7446
7447 rcu_read_lock();
7448 map = rcu_dereference(kvm->arch.apic_map);
7449
7450 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7451 target = map->phys_map[dest_id]->vcpu;
7452
7453 rcu_read_unlock();
7454
7455 if (target && READ_ONCE(target->ready))
7456 kvm_vcpu_yield_to(target);
7457 }
7458
7459 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7460 {
7461 unsigned long nr, a0, a1, a2, a3, ret;
7462 int op_64_bit;
7463
7464 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7465 return kvm_hv_hypercall(vcpu);
7466
7467 nr = kvm_rax_read(vcpu);
7468 a0 = kvm_rbx_read(vcpu);
7469 a1 = kvm_rcx_read(vcpu);
7470 a2 = kvm_rdx_read(vcpu);
7471 a3 = kvm_rsi_read(vcpu);
7472
7473 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7474
7475 op_64_bit = is_64_bit_mode(vcpu);
7476 if (!op_64_bit) {
7477 nr &= 0xFFFFFFFF;
7478 a0 &= 0xFFFFFFFF;
7479 a1 &= 0xFFFFFFFF;
7480 a2 &= 0xFFFFFFFF;
7481 a3 &= 0xFFFFFFFF;
7482 }
7483
7484 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7485 ret = -KVM_EPERM;
7486 goto out;
7487 }
7488
7489 switch (nr) {
7490 case KVM_HC_VAPIC_POLL_IRQ:
7491 ret = 0;
7492 break;
7493 case KVM_HC_KICK_CPU:
7494 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7495 kvm_sched_yield(vcpu->kvm, a1);
7496 ret = 0;
7497 break;
7498 #ifdef CONFIG_X86_64
7499 case KVM_HC_CLOCK_PAIRING:
7500 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7501 break;
7502 #endif
7503 case KVM_HC_SEND_IPI:
7504 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7505 break;
7506 case KVM_HC_SCHED_YIELD:
7507 kvm_sched_yield(vcpu->kvm, a0);
7508 ret = 0;
7509 break;
7510 default:
7511 ret = -KVM_ENOSYS;
7512 break;
7513 }
7514 out:
7515 if (!op_64_bit)
7516 ret = (u32)ret;
7517 kvm_rax_write(vcpu, ret);
7518
7519 ++vcpu->stat.hypercalls;
7520 return kvm_skip_emulated_instruction(vcpu);
7521 }
7522 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7523
7524 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7525 {
7526 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7527 char instruction[3];
7528 unsigned long rip = kvm_rip_read(vcpu);
7529
7530 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7531
7532 return emulator_write_emulated(ctxt, rip, instruction, 3,
7533 &ctxt->exception);
7534 }
7535
7536 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7537 {
7538 return vcpu->run->request_interrupt_window &&
7539 likely(!pic_in_kernel(vcpu->kvm));
7540 }
7541
7542 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7543 {
7544 struct kvm_run *kvm_run = vcpu->run;
7545
7546 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7547 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7548 kvm_run->cr8 = kvm_get_cr8(vcpu);
7549 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7550 kvm_run->ready_for_interrupt_injection =
7551 pic_in_kernel(vcpu->kvm) ||
7552 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7553 }
7554
7555 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7556 {
7557 int max_irr, tpr;
7558
7559 if (!kvm_x86_ops->update_cr8_intercept)
7560 return;
7561
7562 if (!lapic_in_kernel(vcpu))
7563 return;
7564
7565 if (vcpu->arch.apicv_active)
7566 return;
7567
7568 if (!vcpu->arch.apic->vapic_addr)
7569 max_irr = kvm_lapic_find_highest_irr(vcpu);
7570 else
7571 max_irr = -1;
7572
7573 if (max_irr != -1)
7574 max_irr >>= 4;
7575
7576 tpr = kvm_lapic_get_cr8(vcpu);
7577
7578 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7579 }
7580
7581 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7582 {
7583 int r;
7584
7585 /* try to reinject previous events if any */
7586
7587 if (vcpu->arch.exception.injected)
7588 kvm_x86_ops->queue_exception(vcpu);
7589 /*
7590 * Do not inject an NMI or interrupt if there is a pending
7591 * exception. Exceptions and interrupts are recognized at
7592 * instruction boundaries, i.e. the start of an instruction.
7593 * Trap-like exceptions, e.g. #DB, have higher priority than
7594 * NMIs and interrupts, i.e. traps are recognized before an
7595 * NMI/interrupt that's pending on the same instruction.
7596 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7597 * priority, but are only generated (pended) during instruction
7598 * execution, i.e. a pending fault-like exception means the
7599 * fault occurred on the *previous* instruction and must be
7600 * serviced prior to recognizing any new events in order to
7601 * fully complete the previous instruction.
7602 */
7603 else if (!vcpu->arch.exception.pending) {
7604 if (vcpu->arch.nmi_injected)
7605 kvm_x86_ops->set_nmi(vcpu);
7606 else if (vcpu->arch.interrupt.injected)
7607 kvm_x86_ops->set_irq(vcpu);
7608 }
7609
7610 /*
7611 * Call check_nested_events() even if we reinjected a previous event
7612 * in order for caller to determine if it should require immediate-exit
7613 * from L2 to L1 due to pending L1 events which require exit
7614 * from L2 to L1.
7615 */
7616 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7617 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7618 if (r != 0)
7619 return r;
7620 }
7621
7622 /* try to inject new event if pending */
7623 if (vcpu->arch.exception.pending) {
7624 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7625 vcpu->arch.exception.has_error_code,
7626 vcpu->arch.exception.error_code);
7627
7628 WARN_ON_ONCE(vcpu->arch.exception.injected);
7629 vcpu->arch.exception.pending = false;
7630 vcpu->arch.exception.injected = true;
7631
7632 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7633 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7634 X86_EFLAGS_RF);
7635
7636 if (vcpu->arch.exception.nr == DB_VECTOR) {
7637 /*
7638 * This code assumes that nSVM doesn't use
7639 * check_nested_events(). If it does, the
7640 * DR6/DR7 changes should happen before L1
7641 * gets a #VMEXIT for an intercepted #DB in
7642 * L2. (Under VMX, on the other hand, the
7643 * DR6/DR7 changes should not happen in the
7644 * event of a VM-exit to L1 for an intercepted
7645 * #DB in L2.)
7646 */
7647 kvm_deliver_exception_payload(vcpu);
7648 if (vcpu->arch.dr7 & DR7_GD) {
7649 vcpu->arch.dr7 &= ~DR7_GD;
7650 kvm_update_dr7(vcpu);
7651 }
7652 }
7653
7654 kvm_x86_ops->queue_exception(vcpu);
7655 }
7656
7657 /* Don't consider new event if we re-injected an event */
7658 if (kvm_event_needs_reinjection(vcpu))
7659 return 0;
7660
7661 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7662 kvm_x86_ops->smi_allowed(vcpu)) {
7663 vcpu->arch.smi_pending = false;
7664 ++vcpu->arch.smi_count;
7665 enter_smm(vcpu);
7666 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7667 --vcpu->arch.nmi_pending;
7668 vcpu->arch.nmi_injected = true;
7669 kvm_x86_ops->set_nmi(vcpu);
7670 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7671 /*
7672 * Because interrupts can be injected asynchronously, we are
7673 * calling check_nested_events again here to avoid a race condition.
7674 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7675 * proposal and current concerns. Perhaps we should be setting
7676 * KVM_REQ_EVENT only on certain events and not unconditionally?
7677 */
7678 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7679 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7680 if (r != 0)
7681 return r;
7682 }
7683 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7684 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7685 false);
7686 kvm_x86_ops->set_irq(vcpu);
7687 }
7688 }
7689
7690 return 0;
7691 }
7692
7693 static void process_nmi(struct kvm_vcpu *vcpu)
7694 {
7695 unsigned limit = 2;
7696
7697 /*
7698 * x86 is limited to one NMI running, and one NMI pending after it.
7699 * If an NMI is already in progress, limit further NMIs to just one.
7700 * Otherwise, allow two (and we'll inject the first one immediately).
7701 */
7702 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7703 limit = 1;
7704
7705 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7706 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7707 kvm_make_request(KVM_REQ_EVENT, vcpu);
7708 }
7709
7710 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7711 {
7712 u32 flags = 0;
7713 flags |= seg->g << 23;
7714 flags |= seg->db << 22;
7715 flags |= seg->l << 21;
7716 flags |= seg->avl << 20;
7717 flags |= seg->present << 15;
7718 flags |= seg->dpl << 13;
7719 flags |= seg->s << 12;
7720 flags |= seg->type << 8;
7721 return flags;
7722 }
7723
7724 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7725 {
7726 struct kvm_segment seg;
7727 int offset;
7728
7729 kvm_get_segment(vcpu, &seg, n);
7730 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7731
7732 if (n < 3)
7733 offset = 0x7f84 + n * 12;
7734 else
7735 offset = 0x7f2c + (n - 3) * 12;
7736
7737 put_smstate(u32, buf, offset + 8, seg.base);
7738 put_smstate(u32, buf, offset + 4, seg.limit);
7739 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7740 }
7741
7742 #ifdef CONFIG_X86_64
7743 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7744 {
7745 struct kvm_segment seg;
7746 int offset;
7747 u16 flags;
7748
7749 kvm_get_segment(vcpu, &seg, n);
7750 offset = 0x7e00 + n * 16;
7751
7752 flags = enter_smm_get_segment_flags(&seg) >> 8;
7753 put_smstate(u16, buf, offset, seg.selector);
7754 put_smstate(u16, buf, offset + 2, flags);
7755 put_smstate(u32, buf, offset + 4, seg.limit);
7756 put_smstate(u64, buf, offset + 8, seg.base);
7757 }
7758 #endif
7759
7760 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7761 {
7762 struct desc_ptr dt;
7763 struct kvm_segment seg;
7764 unsigned long val;
7765 int i;
7766
7767 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7768 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7769 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7770 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7771
7772 for (i = 0; i < 8; i++)
7773 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7774
7775 kvm_get_dr(vcpu, 6, &val);
7776 put_smstate(u32, buf, 0x7fcc, (u32)val);
7777 kvm_get_dr(vcpu, 7, &val);
7778 put_smstate(u32, buf, 0x7fc8, (u32)val);
7779
7780 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7781 put_smstate(u32, buf, 0x7fc4, seg.selector);
7782 put_smstate(u32, buf, 0x7f64, seg.base);
7783 put_smstate(u32, buf, 0x7f60, seg.limit);
7784 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7785
7786 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7787 put_smstate(u32, buf, 0x7fc0, seg.selector);
7788 put_smstate(u32, buf, 0x7f80, seg.base);
7789 put_smstate(u32, buf, 0x7f7c, seg.limit);
7790 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7791
7792 kvm_x86_ops->get_gdt(vcpu, &dt);
7793 put_smstate(u32, buf, 0x7f74, dt.address);
7794 put_smstate(u32, buf, 0x7f70, dt.size);
7795
7796 kvm_x86_ops->get_idt(vcpu, &dt);
7797 put_smstate(u32, buf, 0x7f58, dt.address);
7798 put_smstate(u32, buf, 0x7f54, dt.size);
7799
7800 for (i = 0; i < 6; i++)
7801 enter_smm_save_seg_32(vcpu, buf, i);
7802
7803 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7804
7805 /* revision id */
7806 put_smstate(u32, buf, 0x7efc, 0x00020000);
7807 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7808 }
7809
7810 #ifdef CONFIG_X86_64
7811 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7812 {
7813 struct desc_ptr dt;
7814 struct kvm_segment seg;
7815 unsigned long val;
7816 int i;
7817
7818 for (i = 0; i < 16; i++)
7819 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7820
7821 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7822 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7823
7824 kvm_get_dr(vcpu, 6, &val);
7825 put_smstate(u64, buf, 0x7f68, val);
7826 kvm_get_dr(vcpu, 7, &val);
7827 put_smstate(u64, buf, 0x7f60, val);
7828
7829 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7830 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7831 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7832
7833 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7834
7835 /* revision id */
7836 put_smstate(u32, buf, 0x7efc, 0x00020064);
7837
7838 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7839
7840 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7841 put_smstate(u16, buf, 0x7e90, seg.selector);
7842 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7843 put_smstate(u32, buf, 0x7e94, seg.limit);
7844 put_smstate(u64, buf, 0x7e98, seg.base);
7845
7846 kvm_x86_ops->get_idt(vcpu, &dt);
7847 put_smstate(u32, buf, 0x7e84, dt.size);
7848 put_smstate(u64, buf, 0x7e88, dt.address);
7849
7850 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7851 put_smstate(u16, buf, 0x7e70, seg.selector);
7852 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7853 put_smstate(u32, buf, 0x7e74, seg.limit);
7854 put_smstate(u64, buf, 0x7e78, seg.base);
7855
7856 kvm_x86_ops->get_gdt(vcpu, &dt);
7857 put_smstate(u32, buf, 0x7e64, dt.size);
7858 put_smstate(u64, buf, 0x7e68, dt.address);
7859
7860 for (i = 0; i < 6; i++)
7861 enter_smm_save_seg_64(vcpu, buf, i);
7862 }
7863 #endif
7864
7865 static void enter_smm(struct kvm_vcpu *vcpu)
7866 {
7867 struct kvm_segment cs, ds;
7868 struct desc_ptr dt;
7869 char buf[512];
7870 u32 cr0;
7871
7872 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7873 memset(buf, 0, 512);
7874 #ifdef CONFIG_X86_64
7875 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7876 enter_smm_save_state_64(vcpu, buf);
7877 else
7878 #endif
7879 enter_smm_save_state_32(vcpu, buf);
7880
7881 /*
7882 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7883 * vCPU state (e.g. leave guest mode) after we've saved the state into
7884 * the SMM state-save area.
7885 */
7886 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7887
7888 vcpu->arch.hflags |= HF_SMM_MASK;
7889 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7890
7891 if (kvm_x86_ops->get_nmi_mask(vcpu))
7892 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7893 else
7894 kvm_x86_ops->set_nmi_mask(vcpu, true);
7895
7896 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7897 kvm_rip_write(vcpu, 0x8000);
7898
7899 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7900 kvm_x86_ops->set_cr0(vcpu, cr0);
7901 vcpu->arch.cr0 = cr0;
7902
7903 kvm_x86_ops->set_cr4(vcpu, 0);
7904
7905 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7906 dt.address = dt.size = 0;
7907 kvm_x86_ops->set_idt(vcpu, &dt);
7908
7909 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7910
7911 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7912 cs.base = vcpu->arch.smbase;
7913
7914 ds.selector = 0;
7915 ds.base = 0;
7916
7917 cs.limit = ds.limit = 0xffffffff;
7918 cs.type = ds.type = 0x3;
7919 cs.dpl = ds.dpl = 0;
7920 cs.db = ds.db = 0;
7921 cs.s = ds.s = 1;
7922 cs.l = ds.l = 0;
7923 cs.g = ds.g = 1;
7924 cs.avl = ds.avl = 0;
7925 cs.present = ds.present = 1;
7926 cs.unusable = ds.unusable = 0;
7927 cs.padding = ds.padding = 0;
7928
7929 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7930 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7931 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7932 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7933 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7934 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7935
7936 #ifdef CONFIG_X86_64
7937 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7938 kvm_x86_ops->set_efer(vcpu, 0);
7939 #endif
7940
7941 kvm_update_cpuid(vcpu);
7942 kvm_mmu_reset_context(vcpu);
7943 }
7944
7945 static void process_smi(struct kvm_vcpu *vcpu)
7946 {
7947 vcpu->arch.smi_pending = true;
7948 kvm_make_request(KVM_REQ_EVENT, vcpu);
7949 }
7950
7951 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
7952 unsigned long *vcpu_bitmap)
7953 {
7954 cpumask_var_t cpus;
7955
7956 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
7957
7958 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
7959 vcpu_bitmap, cpus);
7960
7961 free_cpumask_var(cpus);
7962 }
7963
7964 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7965 {
7966 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7967 }
7968
7969 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
7970 {
7971 if (!lapic_in_kernel(vcpu))
7972 return;
7973
7974 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
7975 kvm_apic_update_apicv(vcpu);
7976 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7977 }
7978 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
7979
7980 /*
7981 * NOTE: Do not hold any lock prior to calling this.
7982 *
7983 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
7984 * locked, because it calls __x86_set_memory_region() which does
7985 * synchronize_srcu(&kvm->srcu).
7986 */
7987 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
7988 {
7989 if (!kvm_x86_ops->check_apicv_inhibit_reasons ||
7990 !kvm_x86_ops->check_apicv_inhibit_reasons(bit))
7991 return;
7992
7993 if (activate) {
7994 if (!test_and_clear_bit(bit, &kvm->arch.apicv_inhibit_reasons) ||
7995 !kvm_apicv_activated(kvm))
7996 return;
7997 } else {
7998 if (test_and_set_bit(bit, &kvm->arch.apicv_inhibit_reasons) ||
7999 kvm_apicv_activated(kvm))
8000 return;
8001 }
8002
8003 trace_kvm_apicv_update_request(activate, bit);
8004 if (kvm_x86_ops->pre_update_apicv_exec_ctrl)
8005 kvm_x86_ops->pre_update_apicv_exec_ctrl(kvm, activate);
8006 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
8007 }
8008 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8009
8010 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8011 {
8012 if (!kvm_apic_present(vcpu))
8013 return;
8014
8015 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8016
8017 if (irqchip_split(vcpu->kvm))
8018 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8019 else {
8020 if (vcpu->arch.apicv_active)
8021 kvm_x86_ops->sync_pir_to_irr(vcpu);
8022 if (ioapic_in_kernel(vcpu->kvm))
8023 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8024 }
8025
8026 if (is_guest_mode(vcpu))
8027 vcpu->arch.load_eoi_exitmap_pending = true;
8028 else
8029 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8030 }
8031
8032 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8033 {
8034 u64 eoi_exit_bitmap[4];
8035
8036 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8037 return;
8038
8039 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8040 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8041 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8042 }
8043
8044 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8045 unsigned long start, unsigned long end,
8046 bool blockable)
8047 {
8048 unsigned long apic_address;
8049
8050 /*
8051 * The physical address of apic access page is stored in the VMCS.
8052 * Update it when it becomes invalid.
8053 */
8054 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8055 if (start <= apic_address && apic_address < end)
8056 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8057
8058 return 0;
8059 }
8060
8061 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8062 {
8063 struct page *page = NULL;
8064
8065 if (!lapic_in_kernel(vcpu))
8066 return;
8067
8068 if (!kvm_x86_ops->set_apic_access_page_addr)
8069 return;
8070
8071 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8072 if (is_error_page(page))
8073 return;
8074 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
8075
8076 /*
8077 * Do not pin apic access page in memory, the MMU notifier
8078 * will call us again if it is migrated or swapped out.
8079 */
8080 put_page(page);
8081 }
8082
8083 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8084 {
8085 smp_send_reschedule(vcpu->cpu);
8086 }
8087 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8088
8089 /*
8090 * Returns 1 to let vcpu_run() continue the guest execution loop without
8091 * exiting to the userspace. Otherwise, the value will be returned to the
8092 * userspace.
8093 */
8094 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8095 {
8096 int r;
8097 bool req_int_win =
8098 dm_request_for_irq_injection(vcpu) &&
8099 kvm_cpu_accept_dm_intr(vcpu);
8100 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
8101
8102 bool req_immediate_exit = false;
8103
8104 if (kvm_request_pending(vcpu)) {
8105 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8106 if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) {
8107 r = 0;
8108 goto out;
8109 }
8110 }
8111 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8112 kvm_mmu_unload(vcpu);
8113 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8114 __kvm_migrate_timers(vcpu);
8115 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8116 kvm_gen_update_masterclock(vcpu->kvm);
8117 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8118 kvm_gen_kvmclock_update(vcpu);
8119 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8120 r = kvm_guest_time_update(vcpu);
8121 if (unlikely(r))
8122 goto out;
8123 }
8124 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8125 kvm_mmu_sync_roots(vcpu);
8126 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
8127 kvm_mmu_load_cr3(vcpu);
8128 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
8129 kvm_vcpu_flush_tlb(vcpu, true);
8130 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8131 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8132 r = 0;
8133 goto out;
8134 }
8135 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8136 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8137 vcpu->mmio_needed = 0;
8138 r = 0;
8139 goto out;
8140 }
8141 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8142 /* Page is swapped out. Do synthetic halt */
8143 vcpu->arch.apf.halted = true;
8144 r = 1;
8145 goto out;
8146 }
8147 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8148 record_steal_time(vcpu);
8149 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8150 process_smi(vcpu);
8151 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8152 process_nmi(vcpu);
8153 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8154 kvm_pmu_handle_event(vcpu);
8155 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8156 kvm_pmu_deliver_pmi(vcpu);
8157 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8158 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8159 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8160 vcpu->arch.ioapic_handled_vectors)) {
8161 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8162 vcpu->run->eoi.vector =
8163 vcpu->arch.pending_ioapic_eoi;
8164 r = 0;
8165 goto out;
8166 }
8167 }
8168 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8169 vcpu_scan_ioapic(vcpu);
8170 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8171 vcpu_load_eoi_exitmap(vcpu);
8172 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8173 kvm_vcpu_reload_apic_access_page(vcpu);
8174 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8175 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8176 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8177 r = 0;
8178 goto out;
8179 }
8180 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8181 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8182 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8183 r = 0;
8184 goto out;
8185 }
8186 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8187 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8188 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8189 r = 0;
8190 goto out;
8191 }
8192
8193 /*
8194 * KVM_REQ_HV_STIMER has to be processed after
8195 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8196 * depend on the guest clock being up-to-date
8197 */
8198 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8199 kvm_hv_process_stimers(vcpu);
8200 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8201 kvm_vcpu_update_apicv(vcpu);
8202 }
8203
8204 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8205 ++vcpu->stat.req_event;
8206 kvm_apic_accept_events(vcpu);
8207 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8208 r = 1;
8209 goto out;
8210 }
8211
8212 if (inject_pending_event(vcpu, req_int_win) != 0)
8213 req_immediate_exit = true;
8214 else {
8215 /* Enable SMI/NMI/IRQ window open exits if needed.
8216 *
8217 * SMIs have three cases:
8218 * 1) They can be nested, and then there is nothing to
8219 * do here because RSM will cause a vmexit anyway.
8220 * 2) There is an ISA-specific reason why SMI cannot be
8221 * injected, and the moment when this changes can be
8222 * intercepted.
8223 * 3) Or the SMI can be pending because
8224 * inject_pending_event has completed the injection
8225 * of an IRQ or NMI from the previous vmexit, and
8226 * then we request an immediate exit to inject the
8227 * SMI.
8228 */
8229 if (vcpu->arch.smi_pending && !is_smm(vcpu))
8230 if (!kvm_x86_ops->enable_smi_window(vcpu))
8231 req_immediate_exit = true;
8232 if (vcpu->arch.nmi_pending)
8233 kvm_x86_ops->enable_nmi_window(vcpu);
8234 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8235 kvm_x86_ops->enable_irq_window(vcpu);
8236 WARN_ON(vcpu->arch.exception.pending);
8237 }
8238
8239 if (kvm_lapic_enabled(vcpu)) {
8240 update_cr8_intercept(vcpu);
8241 kvm_lapic_sync_to_vapic(vcpu);
8242 }
8243 }
8244
8245 r = kvm_mmu_reload(vcpu);
8246 if (unlikely(r)) {
8247 goto cancel_injection;
8248 }
8249
8250 preempt_disable();
8251
8252 kvm_x86_ops->prepare_guest_switch(vcpu);
8253
8254 /*
8255 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8256 * IPI are then delayed after guest entry, which ensures that they
8257 * result in virtual interrupt delivery.
8258 */
8259 local_irq_disable();
8260 vcpu->mode = IN_GUEST_MODE;
8261
8262 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8263
8264 /*
8265 * 1) We should set ->mode before checking ->requests. Please see
8266 * the comment in kvm_vcpu_exiting_guest_mode().
8267 *
8268 * 2) For APICv, we should set ->mode before checking PID.ON. This
8269 * pairs with the memory barrier implicit in pi_test_and_set_on
8270 * (see vmx_deliver_posted_interrupt).
8271 *
8272 * 3) This also orders the write to mode from any reads to the page
8273 * tables done while the VCPU is running. Please see the comment
8274 * in kvm_flush_remote_tlbs.
8275 */
8276 smp_mb__after_srcu_read_unlock();
8277
8278 /*
8279 * This handles the case where a posted interrupt was
8280 * notified with kvm_vcpu_kick.
8281 */
8282 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8283 kvm_x86_ops->sync_pir_to_irr(vcpu);
8284
8285 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8286 || need_resched() || signal_pending(current)) {
8287 vcpu->mode = OUTSIDE_GUEST_MODE;
8288 smp_wmb();
8289 local_irq_enable();
8290 preempt_enable();
8291 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8292 r = 1;
8293 goto cancel_injection;
8294 }
8295
8296 if (req_immediate_exit) {
8297 kvm_make_request(KVM_REQ_EVENT, vcpu);
8298 kvm_x86_ops->request_immediate_exit(vcpu);
8299 }
8300
8301 trace_kvm_entry(vcpu->vcpu_id);
8302 guest_enter_irqoff();
8303
8304 fpregs_assert_state_consistent();
8305 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8306 switch_fpu_return();
8307
8308 if (unlikely(vcpu->arch.switch_db_regs)) {
8309 set_debugreg(0, 7);
8310 set_debugreg(vcpu->arch.eff_db[0], 0);
8311 set_debugreg(vcpu->arch.eff_db[1], 1);
8312 set_debugreg(vcpu->arch.eff_db[2], 2);
8313 set_debugreg(vcpu->arch.eff_db[3], 3);
8314 set_debugreg(vcpu->arch.dr6, 6);
8315 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8316 }
8317
8318 kvm_x86_ops->run(vcpu);
8319
8320 /*
8321 * Do this here before restoring debug registers on the host. And
8322 * since we do this before handling the vmexit, a DR access vmexit
8323 * can (a) read the correct value of the debug registers, (b) set
8324 * KVM_DEBUGREG_WONT_EXIT again.
8325 */
8326 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8327 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8328 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8329 kvm_update_dr0123(vcpu);
8330 kvm_update_dr6(vcpu);
8331 kvm_update_dr7(vcpu);
8332 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8333 }
8334
8335 /*
8336 * If the guest has used debug registers, at least dr7
8337 * will be disabled while returning to the host.
8338 * If we don't have active breakpoints in the host, we don't
8339 * care about the messed up debug address registers. But if
8340 * we have some of them active, restore the old state.
8341 */
8342 if (hw_breakpoint_active())
8343 hw_breakpoint_restore();
8344
8345 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8346
8347 vcpu->mode = OUTSIDE_GUEST_MODE;
8348 smp_wmb();
8349
8350 kvm_x86_ops->handle_exit_irqoff(vcpu, &exit_fastpath);
8351
8352 /*
8353 * Consume any pending interrupts, including the possible source of
8354 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8355 * An instruction is required after local_irq_enable() to fully unblock
8356 * interrupts on processors that implement an interrupt shadow, the
8357 * stat.exits increment will do nicely.
8358 */
8359 kvm_before_interrupt(vcpu);
8360 local_irq_enable();
8361 ++vcpu->stat.exits;
8362 local_irq_disable();
8363 kvm_after_interrupt(vcpu);
8364
8365 guest_exit_irqoff();
8366 if (lapic_in_kernel(vcpu)) {
8367 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8368 if (delta != S64_MIN) {
8369 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8370 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8371 }
8372 }
8373
8374 local_irq_enable();
8375 preempt_enable();
8376
8377 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8378
8379 /*
8380 * Profile KVM exit RIPs:
8381 */
8382 if (unlikely(prof_on == KVM_PROFILING)) {
8383 unsigned long rip = kvm_rip_read(vcpu);
8384 profile_hit(KVM_PROFILING, (void *)rip);
8385 }
8386
8387 if (unlikely(vcpu->arch.tsc_always_catchup))
8388 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8389
8390 if (vcpu->arch.apic_attention)
8391 kvm_lapic_sync_from_vapic(vcpu);
8392
8393 r = kvm_x86_ops->handle_exit(vcpu, exit_fastpath);
8394 return r;
8395
8396 cancel_injection:
8397 kvm_x86_ops->cancel_injection(vcpu);
8398 if (unlikely(vcpu->arch.apic_attention))
8399 kvm_lapic_sync_from_vapic(vcpu);
8400 out:
8401 return r;
8402 }
8403
8404 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8405 {
8406 if (!kvm_arch_vcpu_runnable(vcpu) &&
8407 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8408 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8409 kvm_vcpu_block(vcpu);
8410 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8411
8412 if (kvm_x86_ops->post_block)
8413 kvm_x86_ops->post_block(vcpu);
8414
8415 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8416 return 1;
8417 }
8418
8419 kvm_apic_accept_events(vcpu);
8420 switch(vcpu->arch.mp_state) {
8421 case KVM_MP_STATE_HALTED:
8422 vcpu->arch.pv.pv_unhalted = false;
8423 vcpu->arch.mp_state =
8424 KVM_MP_STATE_RUNNABLE;
8425 /* fall through */
8426 case KVM_MP_STATE_RUNNABLE:
8427 vcpu->arch.apf.halted = false;
8428 break;
8429 case KVM_MP_STATE_INIT_RECEIVED:
8430 break;
8431 default:
8432 return -EINTR;
8433 }
8434 return 1;
8435 }
8436
8437 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8438 {
8439 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8440 kvm_x86_ops->check_nested_events(vcpu, false);
8441
8442 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8443 !vcpu->arch.apf.halted);
8444 }
8445
8446 static int vcpu_run(struct kvm_vcpu *vcpu)
8447 {
8448 int r;
8449 struct kvm *kvm = vcpu->kvm;
8450
8451 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8452 vcpu->arch.l1tf_flush_l1d = true;
8453
8454 for (;;) {
8455 if (kvm_vcpu_running(vcpu)) {
8456 r = vcpu_enter_guest(vcpu);
8457 } else {
8458 r = vcpu_block(kvm, vcpu);
8459 }
8460
8461 if (r <= 0)
8462 break;
8463
8464 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8465 if (kvm_cpu_has_pending_timer(vcpu))
8466 kvm_inject_pending_timer_irqs(vcpu);
8467
8468 if (dm_request_for_irq_injection(vcpu) &&
8469 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8470 r = 0;
8471 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8472 ++vcpu->stat.request_irq_exits;
8473 break;
8474 }
8475
8476 kvm_check_async_pf_completion(vcpu);
8477
8478 if (signal_pending(current)) {
8479 r = -EINTR;
8480 vcpu->run->exit_reason = KVM_EXIT_INTR;
8481 ++vcpu->stat.signal_exits;
8482 break;
8483 }
8484 if (need_resched()) {
8485 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8486 cond_resched();
8487 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8488 }
8489 }
8490
8491 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8492
8493 return r;
8494 }
8495
8496 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8497 {
8498 int r;
8499
8500 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8501 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8502 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8503 return r;
8504 }
8505
8506 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8507 {
8508 BUG_ON(!vcpu->arch.pio.count);
8509
8510 return complete_emulated_io(vcpu);
8511 }
8512
8513 /*
8514 * Implements the following, as a state machine:
8515 *
8516 * read:
8517 * for each fragment
8518 * for each mmio piece in the fragment
8519 * write gpa, len
8520 * exit
8521 * copy data
8522 * execute insn
8523 *
8524 * write:
8525 * for each fragment
8526 * for each mmio piece in the fragment
8527 * write gpa, len
8528 * copy data
8529 * exit
8530 */
8531 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8532 {
8533 struct kvm_run *run = vcpu->run;
8534 struct kvm_mmio_fragment *frag;
8535 unsigned len;
8536
8537 BUG_ON(!vcpu->mmio_needed);
8538
8539 /* Complete previous fragment */
8540 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8541 len = min(8u, frag->len);
8542 if (!vcpu->mmio_is_write)
8543 memcpy(frag->data, run->mmio.data, len);
8544
8545 if (frag->len <= 8) {
8546 /* Switch to the next fragment. */
8547 frag++;
8548 vcpu->mmio_cur_fragment++;
8549 } else {
8550 /* Go forward to the next mmio piece. */
8551 frag->data += len;
8552 frag->gpa += len;
8553 frag->len -= len;
8554 }
8555
8556 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8557 vcpu->mmio_needed = 0;
8558
8559 /* FIXME: return into emulator if single-stepping. */
8560 if (vcpu->mmio_is_write)
8561 return 1;
8562 vcpu->mmio_read_completed = 1;
8563 return complete_emulated_io(vcpu);
8564 }
8565
8566 run->exit_reason = KVM_EXIT_MMIO;
8567 run->mmio.phys_addr = frag->gpa;
8568 if (vcpu->mmio_is_write)
8569 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8570 run->mmio.len = min(8u, frag->len);
8571 run->mmio.is_write = vcpu->mmio_is_write;
8572 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8573 return 0;
8574 }
8575
8576 static void kvm_save_current_fpu(struct fpu *fpu)
8577 {
8578 /*
8579 * If the target FPU state is not resident in the CPU registers, just
8580 * memcpy() from current, else save CPU state directly to the target.
8581 */
8582 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8583 memcpy(&fpu->state, &current->thread.fpu.state,
8584 fpu_kernel_xstate_size);
8585 else
8586 copy_fpregs_to_fpstate(fpu);
8587 }
8588
8589 /* Swap (qemu) user FPU context for the guest FPU context. */
8590 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8591 {
8592 fpregs_lock();
8593
8594 kvm_save_current_fpu(vcpu->arch.user_fpu);
8595
8596 /* PKRU is separately restored in kvm_x86_ops->run. */
8597 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8598 ~XFEATURE_MASK_PKRU);
8599
8600 fpregs_mark_activate();
8601 fpregs_unlock();
8602
8603 trace_kvm_fpu(1);
8604 }
8605
8606 /* When vcpu_run ends, restore user space FPU context. */
8607 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8608 {
8609 fpregs_lock();
8610
8611 kvm_save_current_fpu(vcpu->arch.guest_fpu);
8612
8613 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8614
8615 fpregs_mark_activate();
8616 fpregs_unlock();
8617
8618 ++vcpu->stat.fpu_reload;
8619 trace_kvm_fpu(0);
8620 }
8621
8622 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8623 {
8624 int r;
8625
8626 vcpu_load(vcpu);
8627 kvm_sigset_activate(vcpu);
8628 kvm_load_guest_fpu(vcpu);
8629
8630 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8631 if (kvm_run->immediate_exit) {
8632 r = -EINTR;
8633 goto out;
8634 }
8635 kvm_vcpu_block(vcpu);
8636 kvm_apic_accept_events(vcpu);
8637 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8638 r = -EAGAIN;
8639 if (signal_pending(current)) {
8640 r = -EINTR;
8641 vcpu->run->exit_reason = KVM_EXIT_INTR;
8642 ++vcpu->stat.signal_exits;
8643 }
8644 goto out;
8645 }
8646
8647 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8648 r = -EINVAL;
8649 goto out;
8650 }
8651
8652 if (vcpu->run->kvm_dirty_regs) {
8653 r = sync_regs(vcpu);
8654 if (r != 0)
8655 goto out;
8656 }
8657
8658 /* re-sync apic's tpr */
8659 if (!lapic_in_kernel(vcpu)) {
8660 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8661 r = -EINVAL;
8662 goto out;
8663 }
8664 }
8665
8666 if (unlikely(vcpu->arch.complete_userspace_io)) {
8667 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8668 vcpu->arch.complete_userspace_io = NULL;
8669 r = cui(vcpu);
8670 if (r <= 0)
8671 goto out;
8672 } else
8673 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8674
8675 if (kvm_run->immediate_exit)
8676 r = -EINTR;
8677 else
8678 r = vcpu_run(vcpu);
8679
8680 out:
8681 kvm_put_guest_fpu(vcpu);
8682 if (vcpu->run->kvm_valid_regs)
8683 store_regs(vcpu);
8684 post_kvm_run_save(vcpu);
8685 kvm_sigset_deactivate(vcpu);
8686
8687 vcpu_put(vcpu);
8688 return r;
8689 }
8690
8691 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8692 {
8693 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8694 /*
8695 * We are here if userspace calls get_regs() in the middle of
8696 * instruction emulation. Registers state needs to be copied
8697 * back from emulation context to vcpu. Userspace shouldn't do
8698 * that usually, but some bad designed PV devices (vmware
8699 * backdoor interface) need this to work
8700 */
8701 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8702 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8703 }
8704 regs->rax = kvm_rax_read(vcpu);
8705 regs->rbx = kvm_rbx_read(vcpu);
8706 regs->rcx = kvm_rcx_read(vcpu);
8707 regs->rdx = kvm_rdx_read(vcpu);
8708 regs->rsi = kvm_rsi_read(vcpu);
8709 regs->rdi = kvm_rdi_read(vcpu);
8710 regs->rsp = kvm_rsp_read(vcpu);
8711 regs->rbp = kvm_rbp_read(vcpu);
8712 #ifdef CONFIG_X86_64
8713 regs->r8 = kvm_r8_read(vcpu);
8714 regs->r9 = kvm_r9_read(vcpu);
8715 regs->r10 = kvm_r10_read(vcpu);
8716 regs->r11 = kvm_r11_read(vcpu);
8717 regs->r12 = kvm_r12_read(vcpu);
8718 regs->r13 = kvm_r13_read(vcpu);
8719 regs->r14 = kvm_r14_read(vcpu);
8720 regs->r15 = kvm_r15_read(vcpu);
8721 #endif
8722
8723 regs->rip = kvm_rip_read(vcpu);
8724 regs->rflags = kvm_get_rflags(vcpu);
8725 }
8726
8727 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8728 {
8729 vcpu_load(vcpu);
8730 __get_regs(vcpu, regs);
8731 vcpu_put(vcpu);
8732 return 0;
8733 }
8734
8735 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8736 {
8737 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8738 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8739
8740 kvm_rax_write(vcpu, regs->rax);
8741 kvm_rbx_write(vcpu, regs->rbx);
8742 kvm_rcx_write(vcpu, regs->rcx);
8743 kvm_rdx_write(vcpu, regs->rdx);
8744 kvm_rsi_write(vcpu, regs->rsi);
8745 kvm_rdi_write(vcpu, regs->rdi);
8746 kvm_rsp_write(vcpu, regs->rsp);
8747 kvm_rbp_write(vcpu, regs->rbp);
8748 #ifdef CONFIG_X86_64
8749 kvm_r8_write(vcpu, regs->r8);
8750 kvm_r9_write(vcpu, regs->r9);
8751 kvm_r10_write(vcpu, regs->r10);
8752 kvm_r11_write(vcpu, regs->r11);
8753 kvm_r12_write(vcpu, regs->r12);
8754 kvm_r13_write(vcpu, regs->r13);
8755 kvm_r14_write(vcpu, regs->r14);
8756 kvm_r15_write(vcpu, regs->r15);
8757 #endif
8758
8759 kvm_rip_write(vcpu, regs->rip);
8760 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8761
8762 vcpu->arch.exception.pending = false;
8763
8764 kvm_make_request(KVM_REQ_EVENT, vcpu);
8765 }
8766
8767 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8768 {
8769 vcpu_load(vcpu);
8770 __set_regs(vcpu, regs);
8771 vcpu_put(vcpu);
8772 return 0;
8773 }
8774
8775 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8776 {
8777 struct kvm_segment cs;
8778
8779 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8780 *db = cs.db;
8781 *l = cs.l;
8782 }
8783 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8784
8785 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8786 {
8787 struct desc_ptr dt;
8788
8789 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8790 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8791 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8792 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8793 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8794 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8795
8796 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8797 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8798
8799 kvm_x86_ops->get_idt(vcpu, &dt);
8800 sregs->idt.limit = dt.size;
8801 sregs->idt.base = dt.address;
8802 kvm_x86_ops->get_gdt(vcpu, &dt);
8803 sregs->gdt.limit = dt.size;
8804 sregs->gdt.base = dt.address;
8805
8806 sregs->cr0 = kvm_read_cr0(vcpu);
8807 sregs->cr2 = vcpu->arch.cr2;
8808 sregs->cr3 = kvm_read_cr3(vcpu);
8809 sregs->cr4 = kvm_read_cr4(vcpu);
8810 sregs->cr8 = kvm_get_cr8(vcpu);
8811 sregs->efer = vcpu->arch.efer;
8812 sregs->apic_base = kvm_get_apic_base(vcpu);
8813
8814 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8815
8816 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8817 set_bit(vcpu->arch.interrupt.nr,
8818 (unsigned long *)sregs->interrupt_bitmap);
8819 }
8820
8821 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8822 struct kvm_sregs *sregs)
8823 {
8824 vcpu_load(vcpu);
8825 __get_sregs(vcpu, sregs);
8826 vcpu_put(vcpu);
8827 return 0;
8828 }
8829
8830 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8831 struct kvm_mp_state *mp_state)
8832 {
8833 vcpu_load(vcpu);
8834 if (kvm_mpx_supported())
8835 kvm_load_guest_fpu(vcpu);
8836
8837 kvm_apic_accept_events(vcpu);
8838 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8839 vcpu->arch.pv.pv_unhalted)
8840 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8841 else
8842 mp_state->mp_state = vcpu->arch.mp_state;
8843
8844 if (kvm_mpx_supported())
8845 kvm_put_guest_fpu(vcpu);
8846 vcpu_put(vcpu);
8847 return 0;
8848 }
8849
8850 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8851 struct kvm_mp_state *mp_state)
8852 {
8853 int ret = -EINVAL;
8854
8855 vcpu_load(vcpu);
8856
8857 if (!lapic_in_kernel(vcpu) &&
8858 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8859 goto out;
8860
8861 /*
8862 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8863 * INIT state; latched init should be reported using
8864 * KVM_SET_VCPU_EVENTS, so reject it here.
8865 */
8866 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8867 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8868 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8869 goto out;
8870
8871 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8872 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8873 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8874 } else
8875 vcpu->arch.mp_state = mp_state->mp_state;
8876 kvm_make_request(KVM_REQ_EVENT, vcpu);
8877
8878 ret = 0;
8879 out:
8880 vcpu_put(vcpu);
8881 return ret;
8882 }
8883
8884 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8885 int reason, bool has_error_code, u32 error_code)
8886 {
8887 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8888 int ret;
8889
8890 init_emulate_ctxt(vcpu);
8891
8892 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8893 has_error_code, error_code);
8894 if (ret) {
8895 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8896 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8897 vcpu->run->internal.ndata = 0;
8898 return 0;
8899 }
8900
8901 kvm_rip_write(vcpu, ctxt->eip);
8902 kvm_set_rflags(vcpu, ctxt->eflags);
8903 return 1;
8904 }
8905 EXPORT_SYMBOL_GPL(kvm_task_switch);
8906
8907 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8908 {
8909 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8910 /*
8911 * When EFER.LME and CR0.PG are set, the processor is in
8912 * 64-bit mode (though maybe in a 32-bit code segment).
8913 * CR4.PAE and EFER.LMA must be set.
8914 */
8915 if (!(sregs->cr4 & X86_CR4_PAE)
8916 || !(sregs->efer & EFER_LMA))
8917 return -EINVAL;
8918 } else {
8919 /*
8920 * Not in 64-bit mode: EFER.LMA is clear and the code
8921 * segment cannot be 64-bit.
8922 */
8923 if (sregs->efer & EFER_LMA || sregs->cs.l)
8924 return -EINVAL;
8925 }
8926
8927 return kvm_valid_cr4(vcpu, sregs->cr4);
8928 }
8929
8930 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8931 {
8932 struct msr_data apic_base_msr;
8933 int mmu_reset_needed = 0;
8934 int cpuid_update_needed = 0;
8935 int pending_vec, max_bits, idx;
8936 struct desc_ptr dt;
8937 int ret = -EINVAL;
8938
8939 if (kvm_valid_sregs(vcpu, sregs))
8940 goto out;
8941
8942 apic_base_msr.data = sregs->apic_base;
8943 apic_base_msr.host_initiated = true;
8944 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8945 goto out;
8946
8947 dt.size = sregs->idt.limit;
8948 dt.address = sregs->idt.base;
8949 kvm_x86_ops->set_idt(vcpu, &dt);
8950 dt.size = sregs->gdt.limit;
8951 dt.address = sregs->gdt.base;
8952 kvm_x86_ops->set_gdt(vcpu, &dt);
8953
8954 vcpu->arch.cr2 = sregs->cr2;
8955 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8956 vcpu->arch.cr3 = sregs->cr3;
8957 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
8958
8959 kvm_set_cr8(vcpu, sregs->cr8);
8960
8961 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8962 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8963
8964 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8965 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8966 vcpu->arch.cr0 = sregs->cr0;
8967
8968 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8969 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8970 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8971 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8972 if (cpuid_update_needed)
8973 kvm_update_cpuid(vcpu);
8974
8975 idx = srcu_read_lock(&vcpu->kvm->srcu);
8976 if (is_pae_paging(vcpu)) {
8977 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8978 mmu_reset_needed = 1;
8979 }
8980 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8981
8982 if (mmu_reset_needed)
8983 kvm_mmu_reset_context(vcpu);
8984
8985 max_bits = KVM_NR_INTERRUPTS;
8986 pending_vec = find_first_bit(
8987 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8988 if (pending_vec < max_bits) {
8989 kvm_queue_interrupt(vcpu, pending_vec, false);
8990 pr_debug("Set back pending irq %d\n", pending_vec);
8991 }
8992
8993 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8994 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8995 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8996 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8997 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8998 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8999
9000 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9001 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9002
9003 update_cr8_intercept(vcpu);
9004
9005 /* Older userspace won't unhalt the vcpu on reset. */
9006 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9007 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9008 !is_protmode(vcpu))
9009 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9010
9011 kvm_make_request(KVM_REQ_EVENT, vcpu);
9012
9013 ret = 0;
9014 out:
9015 return ret;
9016 }
9017
9018 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9019 struct kvm_sregs *sregs)
9020 {
9021 int ret;
9022
9023 vcpu_load(vcpu);
9024 ret = __set_sregs(vcpu, sregs);
9025 vcpu_put(vcpu);
9026 return ret;
9027 }
9028
9029 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9030 struct kvm_guest_debug *dbg)
9031 {
9032 unsigned long rflags;
9033 int i, r;
9034
9035 vcpu_load(vcpu);
9036
9037 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9038 r = -EBUSY;
9039 if (vcpu->arch.exception.pending)
9040 goto out;
9041 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9042 kvm_queue_exception(vcpu, DB_VECTOR);
9043 else
9044 kvm_queue_exception(vcpu, BP_VECTOR);
9045 }
9046
9047 /*
9048 * Read rflags as long as potentially injected trace flags are still
9049 * filtered out.
9050 */
9051 rflags = kvm_get_rflags(vcpu);
9052
9053 vcpu->guest_debug = dbg->control;
9054 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9055 vcpu->guest_debug = 0;
9056
9057 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9058 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9059 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9060 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9061 } else {
9062 for (i = 0; i < KVM_NR_DB_REGS; i++)
9063 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9064 }
9065 kvm_update_dr7(vcpu);
9066
9067 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9068 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9069 get_segment_base(vcpu, VCPU_SREG_CS);
9070
9071 /*
9072 * Trigger an rflags update that will inject or remove the trace
9073 * flags.
9074 */
9075 kvm_set_rflags(vcpu, rflags);
9076
9077 kvm_x86_ops->update_bp_intercept(vcpu);
9078
9079 r = 0;
9080
9081 out:
9082 vcpu_put(vcpu);
9083 return r;
9084 }
9085
9086 /*
9087 * Translate a guest virtual address to a guest physical address.
9088 */
9089 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9090 struct kvm_translation *tr)
9091 {
9092 unsigned long vaddr = tr->linear_address;
9093 gpa_t gpa;
9094 int idx;
9095
9096 vcpu_load(vcpu);
9097
9098 idx = srcu_read_lock(&vcpu->kvm->srcu);
9099 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9100 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9101 tr->physical_address = gpa;
9102 tr->valid = gpa != UNMAPPED_GVA;
9103 tr->writeable = 1;
9104 tr->usermode = 0;
9105
9106 vcpu_put(vcpu);
9107 return 0;
9108 }
9109
9110 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9111 {
9112 struct fxregs_state *fxsave;
9113
9114 vcpu_load(vcpu);
9115
9116 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9117 memcpy(fpu->fpr, fxsave->st_space, 128);
9118 fpu->fcw = fxsave->cwd;
9119 fpu->fsw = fxsave->swd;
9120 fpu->ftwx = fxsave->twd;
9121 fpu->last_opcode = fxsave->fop;
9122 fpu->last_ip = fxsave->rip;
9123 fpu->last_dp = fxsave->rdp;
9124 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9125
9126 vcpu_put(vcpu);
9127 return 0;
9128 }
9129
9130 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9131 {
9132 struct fxregs_state *fxsave;
9133
9134 vcpu_load(vcpu);
9135
9136 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9137
9138 memcpy(fxsave->st_space, fpu->fpr, 128);
9139 fxsave->cwd = fpu->fcw;
9140 fxsave->swd = fpu->fsw;
9141 fxsave->twd = fpu->ftwx;
9142 fxsave->fop = fpu->last_opcode;
9143 fxsave->rip = fpu->last_ip;
9144 fxsave->rdp = fpu->last_dp;
9145 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9146
9147 vcpu_put(vcpu);
9148 return 0;
9149 }
9150
9151 static void store_regs(struct kvm_vcpu *vcpu)
9152 {
9153 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9154
9155 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9156 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9157
9158 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9159 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9160
9161 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9162 kvm_vcpu_ioctl_x86_get_vcpu_events(
9163 vcpu, &vcpu->run->s.regs.events);
9164 }
9165
9166 static int sync_regs(struct kvm_vcpu *vcpu)
9167 {
9168 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9169 return -EINVAL;
9170
9171 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9172 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9173 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9174 }
9175 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9176 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9177 return -EINVAL;
9178 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9179 }
9180 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9181 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9182 vcpu, &vcpu->run->s.regs.events))
9183 return -EINVAL;
9184 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9185 }
9186
9187 return 0;
9188 }
9189
9190 static void fx_init(struct kvm_vcpu *vcpu)
9191 {
9192 fpstate_init(&vcpu->arch.guest_fpu->state);
9193 if (boot_cpu_has(X86_FEATURE_XSAVES))
9194 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9195 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9196
9197 /*
9198 * Ensure guest xcr0 is valid for loading
9199 */
9200 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9201
9202 vcpu->arch.cr0 |= X86_CR0_ET;
9203 }
9204
9205 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9206 {
9207 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9208 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9209 "guest TSC will not be reliable\n");
9210
9211 return 0;
9212 }
9213
9214 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9215 {
9216 struct page *page;
9217 int r;
9218
9219 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9220 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9221 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9222 else
9223 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9224
9225 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9226
9227 r = kvm_mmu_create(vcpu);
9228 if (r < 0)
9229 return r;
9230
9231 if (irqchip_in_kernel(vcpu->kvm)) {
9232 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9233 if (r < 0)
9234 goto fail_mmu_destroy;
9235 if (kvm_apicv_activated(vcpu->kvm))
9236 vcpu->arch.apicv_active = true;
9237 } else
9238 static_key_slow_inc(&kvm_no_apic_vcpu);
9239
9240 r = -ENOMEM;
9241
9242 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9243 if (!page)
9244 goto fail_free_lapic;
9245 vcpu->arch.pio_data = page_address(page);
9246
9247 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9248 GFP_KERNEL_ACCOUNT);
9249 if (!vcpu->arch.mce_banks)
9250 goto fail_free_pio_data;
9251 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9252
9253 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9254 GFP_KERNEL_ACCOUNT))
9255 goto fail_free_mce_banks;
9256
9257 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9258 GFP_KERNEL_ACCOUNT);
9259 if (!vcpu->arch.user_fpu) {
9260 pr_err("kvm: failed to allocate userspace's fpu\n");
9261 goto free_wbinvd_dirty_mask;
9262 }
9263
9264 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9265 GFP_KERNEL_ACCOUNT);
9266 if (!vcpu->arch.guest_fpu) {
9267 pr_err("kvm: failed to allocate vcpu's fpu\n");
9268 goto free_user_fpu;
9269 }
9270 fx_init(vcpu);
9271
9272 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9273
9274 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9275
9276 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9277
9278 kvm_async_pf_hash_reset(vcpu);
9279 kvm_pmu_init(vcpu);
9280
9281 vcpu->arch.pending_external_vector = -1;
9282 vcpu->arch.preempted_in_kernel = false;
9283
9284 kvm_hv_vcpu_init(vcpu);
9285
9286 r = kvm_x86_ops->vcpu_create(vcpu);
9287 if (r)
9288 goto free_guest_fpu;
9289
9290 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9291 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9292 kvm_vcpu_mtrr_init(vcpu);
9293 vcpu_load(vcpu);
9294 kvm_vcpu_reset(vcpu, false);
9295 kvm_init_mmu(vcpu, false);
9296 vcpu_put(vcpu);
9297 return 0;
9298
9299 free_guest_fpu:
9300 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9301 free_user_fpu:
9302 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9303 free_wbinvd_dirty_mask:
9304 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9305 fail_free_mce_banks:
9306 kfree(vcpu->arch.mce_banks);
9307 fail_free_pio_data:
9308 free_page((unsigned long)vcpu->arch.pio_data);
9309 fail_free_lapic:
9310 kvm_free_lapic(vcpu);
9311 fail_mmu_destroy:
9312 kvm_mmu_destroy(vcpu);
9313 return r;
9314 }
9315
9316 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9317 {
9318 struct msr_data msr;
9319 struct kvm *kvm = vcpu->kvm;
9320
9321 kvm_hv_vcpu_postcreate(vcpu);
9322
9323 if (mutex_lock_killable(&vcpu->mutex))
9324 return;
9325 vcpu_load(vcpu);
9326 msr.data = 0x0;
9327 msr.index = MSR_IA32_TSC;
9328 msr.host_initiated = true;
9329 kvm_write_tsc(vcpu, &msr);
9330 vcpu_put(vcpu);
9331
9332 /* poll control enabled by default */
9333 vcpu->arch.msr_kvm_poll_control = 1;
9334
9335 mutex_unlock(&vcpu->mutex);
9336
9337 if (!kvmclock_periodic_sync)
9338 return;
9339
9340 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9341 KVMCLOCK_SYNC_PERIOD);
9342 }
9343
9344 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9345 {
9346 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9347 int idx;
9348
9349 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9350
9351 kvmclock_reset(vcpu);
9352
9353 kvm_x86_ops->vcpu_free(vcpu);
9354
9355 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9356 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9357 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9358
9359 kvm_hv_vcpu_uninit(vcpu);
9360 kvm_pmu_destroy(vcpu);
9361 kfree(vcpu->arch.mce_banks);
9362 kvm_free_lapic(vcpu);
9363 idx = srcu_read_lock(&vcpu->kvm->srcu);
9364 kvm_mmu_destroy(vcpu);
9365 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9366 free_page((unsigned long)vcpu->arch.pio_data);
9367 if (!lapic_in_kernel(vcpu))
9368 static_key_slow_dec(&kvm_no_apic_vcpu);
9369 }
9370
9371 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9372 {
9373 kvm_lapic_reset(vcpu, init_event);
9374
9375 vcpu->arch.hflags = 0;
9376
9377 vcpu->arch.smi_pending = 0;
9378 vcpu->arch.smi_count = 0;
9379 atomic_set(&vcpu->arch.nmi_queued, 0);
9380 vcpu->arch.nmi_pending = 0;
9381 vcpu->arch.nmi_injected = false;
9382 kvm_clear_interrupt_queue(vcpu);
9383 kvm_clear_exception_queue(vcpu);
9384
9385 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9386 kvm_update_dr0123(vcpu);
9387 vcpu->arch.dr6 = DR6_INIT;
9388 kvm_update_dr6(vcpu);
9389 vcpu->arch.dr7 = DR7_FIXED_1;
9390 kvm_update_dr7(vcpu);
9391
9392 vcpu->arch.cr2 = 0;
9393
9394 kvm_make_request(KVM_REQ_EVENT, vcpu);
9395 vcpu->arch.apf.msr_val = 0;
9396 vcpu->arch.st.msr_val = 0;
9397
9398 kvmclock_reset(vcpu);
9399
9400 kvm_clear_async_pf_completion_queue(vcpu);
9401 kvm_async_pf_hash_reset(vcpu);
9402 vcpu->arch.apf.halted = false;
9403
9404 if (kvm_mpx_supported()) {
9405 void *mpx_state_buffer;
9406
9407 /*
9408 * To avoid have the INIT path from kvm_apic_has_events() that be
9409 * called with loaded FPU and does not let userspace fix the state.
9410 */
9411 if (init_event)
9412 kvm_put_guest_fpu(vcpu);
9413 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9414 XFEATURE_BNDREGS);
9415 if (mpx_state_buffer)
9416 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9417 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9418 XFEATURE_BNDCSR);
9419 if (mpx_state_buffer)
9420 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9421 if (init_event)
9422 kvm_load_guest_fpu(vcpu);
9423 }
9424
9425 if (!init_event) {
9426 kvm_pmu_reset(vcpu);
9427 vcpu->arch.smbase = 0x30000;
9428
9429 vcpu->arch.msr_misc_features_enables = 0;
9430
9431 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9432 }
9433
9434 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9435 vcpu->arch.regs_avail = ~0;
9436 vcpu->arch.regs_dirty = ~0;
9437
9438 vcpu->arch.ia32_xss = 0;
9439
9440 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9441 }
9442
9443 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9444 {
9445 struct kvm_segment cs;
9446
9447 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9448 cs.selector = vector << 8;
9449 cs.base = vector << 12;
9450 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9451 kvm_rip_write(vcpu, 0);
9452 }
9453
9454 int kvm_arch_hardware_enable(void)
9455 {
9456 struct kvm *kvm;
9457 struct kvm_vcpu *vcpu;
9458 int i;
9459 int ret;
9460 u64 local_tsc;
9461 u64 max_tsc = 0;
9462 bool stable, backwards_tsc = false;
9463
9464 kvm_shared_msr_cpu_online();
9465 ret = kvm_x86_ops->hardware_enable();
9466 if (ret != 0)
9467 return ret;
9468
9469 local_tsc = rdtsc();
9470 stable = !kvm_check_tsc_unstable();
9471 list_for_each_entry(kvm, &vm_list, vm_list) {
9472 kvm_for_each_vcpu(i, vcpu, kvm) {
9473 if (!stable && vcpu->cpu == smp_processor_id())
9474 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9475 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9476 backwards_tsc = true;
9477 if (vcpu->arch.last_host_tsc > max_tsc)
9478 max_tsc = vcpu->arch.last_host_tsc;
9479 }
9480 }
9481 }
9482
9483 /*
9484 * Sometimes, even reliable TSCs go backwards. This happens on
9485 * platforms that reset TSC during suspend or hibernate actions, but
9486 * maintain synchronization. We must compensate. Fortunately, we can
9487 * detect that condition here, which happens early in CPU bringup,
9488 * before any KVM threads can be running. Unfortunately, we can't
9489 * bring the TSCs fully up to date with real time, as we aren't yet far
9490 * enough into CPU bringup that we know how much real time has actually
9491 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9492 * variables that haven't been updated yet.
9493 *
9494 * So we simply find the maximum observed TSC above, then record the
9495 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9496 * the adjustment will be applied. Note that we accumulate
9497 * adjustments, in case multiple suspend cycles happen before some VCPU
9498 * gets a chance to run again. In the event that no KVM threads get a
9499 * chance to run, we will miss the entire elapsed period, as we'll have
9500 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9501 * loose cycle time. This isn't too big a deal, since the loss will be
9502 * uniform across all VCPUs (not to mention the scenario is extremely
9503 * unlikely). It is possible that a second hibernate recovery happens
9504 * much faster than a first, causing the observed TSC here to be
9505 * smaller; this would require additional padding adjustment, which is
9506 * why we set last_host_tsc to the local tsc observed here.
9507 *
9508 * N.B. - this code below runs only on platforms with reliable TSC,
9509 * as that is the only way backwards_tsc is set above. Also note
9510 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9511 * have the same delta_cyc adjustment applied if backwards_tsc
9512 * is detected. Note further, this adjustment is only done once,
9513 * as we reset last_host_tsc on all VCPUs to stop this from being
9514 * called multiple times (one for each physical CPU bringup).
9515 *
9516 * Platforms with unreliable TSCs don't have to deal with this, they
9517 * will be compensated by the logic in vcpu_load, which sets the TSC to
9518 * catchup mode. This will catchup all VCPUs to real time, but cannot
9519 * guarantee that they stay in perfect synchronization.
9520 */
9521 if (backwards_tsc) {
9522 u64 delta_cyc = max_tsc - local_tsc;
9523 list_for_each_entry(kvm, &vm_list, vm_list) {
9524 kvm->arch.backwards_tsc_observed = true;
9525 kvm_for_each_vcpu(i, vcpu, kvm) {
9526 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9527 vcpu->arch.last_host_tsc = local_tsc;
9528 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9529 }
9530
9531 /*
9532 * We have to disable TSC offset matching.. if you were
9533 * booting a VM while issuing an S4 host suspend....
9534 * you may have some problem. Solving this issue is
9535 * left as an exercise to the reader.
9536 */
9537 kvm->arch.last_tsc_nsec = 0;
9538 kvm->arch.last_tsc_write = 0;
9539 }
9540
9541 }
9542 return 0;
9543 }
9544
9545 void kvm_arch_hardware_disable(void)
9546 {
9547 kvm_x86_ops->hardware_disable();
9548 drop_user_return_notifiers();
9549 }
9550
9551 int kvm_arch_hardware_setup(void)
9552 {
9553 int r;
9554
9555 r = kvm_x86_ops->hardware_setup();
9556 if (r != 0)
9557 return r;
9558
9559 cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
9560
9561 if (kvm_has_tsc_control) {
9562 /*
9563 * Make sure the user can only configure tsc_khz values that
9564 * fit into a signed integer.
9565 * A min value is not calculated because it will always
9566 * be 1 on all machines.
9567 */
9568 u64 max = min(0x7fffffffULL,
9569 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9570 kvm_max_guest_tsc_khz = max;
9571
9572 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9573 }
9574
9575 if (boot_cpu_has(X86_FEATURE_XSAVES))
9576 rdmsrl(MSR_IA32_XSS, host_xss);
9577
9578 kvm_init_msr_list();
9579 return 0;
9580 }
9581
9582 void kvm_arch_hardware_unsetup(void)
9583 {
9584 kvm_x86_ops->hardware_unsetup();
9585 }
9586
9587 int kvm_arch_check_processor_compat(void)
9588 {
9589 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9590
9591 WARN_ON(!irqs_disabled());
9592
9593 if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits)
9594 return -EIO;
9595
9596 return kvm_x86_ops->check_processor_compatibility();
9597 }
9598
9599 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9600 {
9601 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9602 }
9603 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9604
9605 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9606 {
9607 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9608 }
9609
9610 struct static_key kvm_no_apic_vcpu __read_mostly;
9611 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9612
9613 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9614 {
9615 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9616
9617 vcpu->arch.l1tf_flush_l1d = true;
9618 if (pmu->version && unlikely(pmu->event_count)) {
9619 pmu->need_cleanup = true;
9620 kvm_make_request(KVM_REQ_PMU, vcpu);
9621 }
9622 kvm_x86_ops->sched_in(vcpu, cpu);
9623 }
9624
9625 void kvm_arch_free_vm(struct kvm *kvm)
9626 {
9627 kfree(kvm->arch.hyperv.hv_pa_pg);
9628 vfree(kvm);
9629 }
9630
9631
9632 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9633 {
9634 if (type)
9635 return -EINVAL;
9636
9637 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9638 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9639 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9640 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9641 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9642 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9643
9644 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9645 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9646 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9647 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9648 &kvm->arch.irq_sources_bitmap);
9649
9650 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9651 mutex_init(&kvm->arch.apic_map_lock);
9652 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9653
9654 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9655 pvclock_update_vm_gtod_copy(kvm);
9656
9657 kvm->arch.guest_can_read_msr_platform_info = true;
9658
9659 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9660 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9661
9662 kvm_hv_init_vm(kvm);
9663 kvm_page_track_init(kvm);
9664 kvm_mmu_init_vm(kvm);
9665
9666 return kvm_x86_ops->vm_init(kvm);
9667 }
9668
9669 int kvm_arch_post_init_vm(struct kvm *kvm)
9670 {
9671 return kvm_mmu_post_init_vm(kvm);
9672 }
9673
9674 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9675 {
9676 vcpu_load(vcpu);
9677 kvm_mmu_unload(vcpu);
9678 vcpu_put(vcpu);
9679 }
9680
9681 static void kvm_free_vcpus(struct kvm *kvm)
9682 {
9683 unsigned int i;
9684 struct kvm_vcpu *vcpu;
9685
9686 /*
9687 * Unpin any mmu pages first.
9688 */
9689 kvm_for_each_vcpu(i, vcpu, kvm) {
9690 kvm_clear_async_pf_completion_queue(vcpu);
9691 kvm_unload_vcpu_mmu(vcpu);
9692 }
9693 kvm_for_each_vcpu(i, vcpu, kvm)
9694 kvm_vcpu_destroy(vcpu);
9695
9696 mutex_lock(&kvm->lock);
9697 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9698 kvm->vcpus[i] = NULL;
9699
9700 atomic_set(&kvm->online_vcpus, 0);
9701 mutex_unlock(&kvm->lock);
9702 }
9703
9704 void kvm_arch_sync_events(struct kvm *kvm)
9705 {
9706 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9707 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9708 kvm_free_pit(kvm);
9709 }
9710
9711 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9712 {
9713 int i, r;
9714 unsigned long hva, uninitialized_var(old_npages);
9715 struct kvm_memslots *slots = kvm_memslots(kvm);
9716 struct kvm_memory_slot *slot;
9717
9718 /* Called with kvm->slots_lock held. */
9719 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9720 return -EINVAL;
9721
9722 slot = id_to_memslot(slots, id);
9723 if (size) {
9724 if (slot && slot->npages)
9725 return -EEXIST;
9726
9727 /*
9728 * MAP_SHARED to prevent internal slot pages from being moved
9729 * by fork()/COW.
9730 */
9731 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9732 MAP_SHARED | MAP_ANONYMOUS, 0);
9733 if (IS_ERR((void *)hva))
9734 return PTR_ERR((void *)hva);
9735 } else {
9736 if (!slot || !slot->npages)
9737 return 0;
9738
9739 /* Stuff a non-canonical value to catch use-after-delete. */
9740 hva = 0xdeadull << 48;
9741 old_npages = slot->npages;
9742 }
9743
9744 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9745 struct kvm_userspace_memory_region m;
9746
9747 m.slot = id | (i << 16);
9748 m.flags = 0;
9749 m.guest_phys_addr = gpa;
9750 m.userspace_addr = hva;
9751 m.memory_size = size;
9752 r = __kvm_set_memory_region(kvm, &m);
9753 if (r < 0)
9754 return r;
9755 }
9756
9757 if (!size)
9758 vm_munmap(hva, old_npages * PAGE_SIZE);
9759
9760 return 0;
9761 }
9762 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9763
9764 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9765 {
9766 kvm_mmu_pre_destroy_vm(kvm);
9767 }
9768
9769 void kvm_arch_destroy_vm(struct kvm *kvm)
9770 {
9771 if (current->mm == kvm->mm) {
9772 /*
9773 * Free memory regions allocated on behalf of userspace,
9774 * unless the the memory map has changed due to process exit
9775 * or fd copying.
9776 */
9777 mutex_lock(&kvm->slots_lock);
9778 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9779 0, 0);
9780 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9781 0, 0);
9782 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9783 mutex_unlock(&kvm->slots_lock);
9784 }
9785 if (kvm_x86_ops->vm_destroy)
9786 kvm_x86_ops->vm_destroy(kvm);
9787 kvm_pic_destroy(kvm);
9788 kvm_ioapic_destroy(kvm);
9789 kvm_free_vcpus(kvm);
9790 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9791 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9792 kvm_mmu_uninit_vm(kvm);
9793 kvm_page_track_cleanup(kvm);
9794 kvm_hv_destroy_vm(kvm);
9795 }
9796
9797 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
9798 {
9799 int i;
9800
9801 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9802 kvfree(slot->arch.rmap[i]);
9803 slot->arch.rmap[i] = NULL;
9804
9805 if (i == 0)
9806 continue;
9807
9808 kvfree(slot->arch.lpage_info[i - 1]);
9809 slot->arch.lpage_info[i - 1] = NULL;
9810 }
9811
9812 kvm_page_track_free_memslot(slot);
9813 }
9814
9815 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
9816 unsigned long npages)
9817 {
9818 int i;
9819
9820 /*
9821 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
9822 * old arrays will be freed by __kvm_set_memory_region() if installing
9823 * the new memslot is successful.
9824 */
9825 memset(&slot->arch, 0, sizeof(slot->arch));
9826
9827 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9828 struct kvm_lpage_info *linfo;
9829 unsigned long ugfn;
9830 int lpages;
9831 int level = i + 1;
9832
9833 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9834 slot->base_gfn, level) + 1;
9835
9836 slot->arch.rmap[i] =
9837 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9838 GFP_KERNEL_ACCOUNT);
9839 if (!slot->arch.rmap[i])
9840 goto out_free;
9841 if (i == 0)
9842 continue;
9843
9844 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9845 if (!linfo)
9846 goto out_free;
9847
9848 slot->arch.lpage_info[i - 1] = linfo;
9849
9850 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9851 linfo[0].disallow_lpage = 1;
9852 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9853 linfo[lpages - 1].disallow_lpage = 1;
9854 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9855 /*
9856 * If the gfn and userspace address are not aligned wrt each
9857 * other, or if explicitly asked to, disable large page
9858 * support for this slot
9859 */
9860 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9861 !kvm_largepages_enabled()) {
9862 unsigned long j;
9863
9864 for (j = 0; j < lpages; ++j)
9865 linfo[j].disallow_lpage = 1;
9866 }
9867 }
9868
9869 if (kvm_page_track_create_memslot(slot, npages))
9870 goto out_free;
9871
9872 return 0;
9873
9874 out_free:
9875 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9876 kvfree(slot->arch.rmap[i]);
9877 slot->arch.rmap[i] = NULL;
9878 if (i == 0)
9879 continue;
9880
9881 kvfree(slot->arch.lpage_info[i - 1]);
9882 slot->arch.lpage_info[i - 1] = NULL;
9883 }
9884 return -ENOMEM;
9885 }
9886
9887 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9888 {
9889 struct kvm_vcpu *vcpu;
9890 int i;
9891
9892 /*
9893 * memslots->generation has been incremented.
9894 * mmio generation may have reached its maximum value.
9895 */
9896 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9897
9898 /* Force re-initialization of steal_time cache */
9899 kvm_for_each_vcpu(i, vcpu, kvm)
9900 kvm_vcpu_kick(vcpu);
9901 }
9902
9903 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9904 struct kvm_memory_slot *memslot,
9905 const struct kvm_userspace_memory_region *mem,
9906 enum kvm_mr_change change)
9907 {
9908 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
9909 return kvm_alloc_memslot_metadata(memslot,
9910 mem->memory_size >> PAGE_SHIFT);
9911 return 0;
9912 }
9913
9914 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9915 struct kvm_memory_slot *new)
9916 {
9917 /* Still write protect RO slot */
9918 if (new->flags & KVM_MEM_READONLY) {
9919 kvm_mmu_slot_remove_write_access(kvm, new, PT_PAGE_TABLE_LEVEL);
9920 return;
9921 }
9922
9923 /*
9924 * Call kvm_x86_ops dirty logging hooks when they are valid.
9925 *
9926 * kvm_x86_ops->slot_disable_log_dirty is called when:
9927 *
9928 * - KVM_MR_CREATE with dirty logging is disabled
9929 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9930 *
9931 * The reason is, in case of PML, we need to set D-bit for any slots
9932 * with dirty logging disabled in order to eliminate unnecessary GPA
9933 * logging in PML buffer (and potential PML buffer full VMEXIT). This
9934 * guarantees leaving PML enabled during guest's lifetime won't have
9935 * any additional overhead from PML when guest is running with dirty
9936 * logging disabled for memory slots.
9937 *
9938 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9939 * to dirty logging mode.
9940 *
9941 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9942 *
9943 * In case of write protect:
9944 *
9945 * Write protect all pages for dirty logging.
9946 *
9947 * All the sptes including the large sptes which point to this
9948 * slot are set to readonly. We can not create any new large
9949 * spte on this slot until the end of the logging.
9950 *
9951 * See the comments in fast_page_fault().
9952 */
9953 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9954 if (kvm_x86_ops->slot_enable_log_dirty) {
9955 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9956 } else {
9957 int level =
9958 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
9959 PT_DIRECTORY_LEVEL : PT_PAGE_TABLE_LEVEL;
9960
9961 /*
9962 * If we're with initial-all-set, we don't need
9963 * to write protect any small page because
9964 * they're reported as dirty already. However
9965 * we still need to write-protect huge pages
9966 * so that the page split can happen lazily on
9967 * the first write to the huge page.
9968 */
9969 kvm_mmu_slot_remove_write_access(kvm, new, level);
9970 }
9971 } else {
9972 if (kvm_x86_ops->slot_disable_log_dirty)
9973 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9974 }
9975 }
9976
9977 void kvm_arch_commit_memory_region(struct kvm *kvm,
9978 const struct kvm_userspace_memory_region *mem,
9979 struct kvm_memory_slot *old,
9980 const struct kvm_memory_slot *new,
9981 enum kvm_mr_change change)
9982 {
9983 if (!kvm->arch.n_requested_mmu_pages)
9984 kvm_mmu_change_mmu_pages(kvm,
9985 kvm_mmu_calculate_default_mmu_pages(kvm));
9986
9987 /*
9988 * Dirty logging tracks sptes in 4k granularity, meaning that large
9989 * sptes have to be split. If live migration is successful, the guest
9990 * in the source machine will be destroyed and large sptes will be
9991 * created in the destination. However, if the guest continues to run
9992 * in the source machine (for example if live migration fails), small
9993 * sptes will remain around and cause bad performance.
9994 *
9995 * Scan sptes if dirty logging has been stopped, dropping those
9996 * which can be collapsed into a single large-page spte. Later
9997 * page faults will create the large-page sptes.
9998 *
9999 * There is no need to do this in any of the following cases:
10000 * CREATE: No dirty mappings will already exist.
10001 * MOVE/DELETE: The old mappings will already have been cleaned up by
10002 * kvm_arch_flush_shadow_memslot()
10003 */
10004 if (change == KVM_MR_FLAGS_ONLY &&
10005 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10006 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10007 kvm_mmu_zap_collapsible_sptes(kvm, new);
10008
10009 /*
10010 * Set up write protection and/or dirty logging for the new slot.
10011 *
10012 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
10013 * been zapped so no dirty logging staff is needed for old slot. For
10014 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
10015 * new and it's also covered when dealing with the new slot.
10016 *
10017 * FIXME: const-ify all uses of struct kvm_memory_slot.
10018 */
10019 if (change != KVM_MR_DELETE)
10020 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
10021
10022 /* Free the arrays associated with the old memslot. */
10023 if (change == KVM_MR_MOVE)
10024 kvm_arch_free_memslot(kvm, old);
10025 }
10026
10027 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10028 {
10029 kvm_mmu_zap_all(kvm);
10030 }
10031
10032 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10033 struct kvm_memory_slot *slot)
10034 {
10035 kvm_page_track_flush_slot(kvm, slot);
10036 }
10037
10038 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10039 {
10040 return (is_guest_mode(vcpu) &&
10041 kvm_x86_ops->guest_apic_has_interrupt &&
10042 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
10043 }
10044
10045 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10046 {
10047 if (!list_empty_careful(&vcpu->async_pf.done))
10048 return true;
10049
10050 if (kvm_apic_has_events(vcpu))
10051 return true;
10052
10053 if (vcpu->arch.pv.pv_unhalted)
10054 return true;
10055
10056 if (vcpu->arch.exception.pending)
10057 return true;
10058
10059 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10060 (vcpu->arch.nmi_pending &&
10061 kvm_x86_ops->nmi_allowed(vcpu)))
10062 return true;
10063
10064 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10065 (vcpu->arch.smi_pending && !is_smm(vcpu)))
10066 return true;
10067
10068 if (kvm_arch_interrupt_allowed(vcpu) &&
10069 (kvm_cpu_has_interrupt(vcpu) ||
10070 kvm_guest_apic_has_interrupt(vcpu)))
10071 return true;
10072
10073 if (kvm_hv_has_stimer_pending(vcpu))
10074 return true;
10075
10076 return false;
10077 }
10078
10079 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10080 {
10081 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10082 }
10083
10084 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10085 {
10086 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10087 return true;
10088
10089 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10090 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10091 kvm_test_request(KVM_REQ_EVENT, vcpu))
10092 return true;
10093
10094 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
10095 return true;
10096
10097 return false;
10098 }
10099
10100 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10101 {
10102 return vcpu->arch.preempted_in_kernel;
10103 }
10104
10105 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10106 {
10107 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10108 }
10109
10110 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10111 {
10112 return kvm_x86_ops->interrupt_allowed(vcpu);
10113 }
10114
10115 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10116 {
10117 if (is_64_bit_mode(vcpu))
10118 return kvm_rip_read(vcpu);
10119 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10120 kvm_rip_read(vcpu));
10121 }
10122 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10123
10124 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10125 {
10126 return kvm_get_linear_rip(vcpu) == linear_rip;
10127 }
10128 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10129
10130 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10131 {
10132 unsigned long rflags;
10133
10134 rflags = kvm_x86_ops->get_rflags(vcpu);
10135 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10136 rflags &= ~X86_EFLAGS_TF;
10137 return rflags;
10138 }
10139 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10140
10141 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10142 {
10143 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10144 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10145 rflags |= X86_EFLAGS_TF;
10146 kvm_x86_ops->set_rflags(vcpu, rflags);
10147 }
10148
10149 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10150 {
10151 __kvm_set_rflags(vcpu, rflags);
10152 kvm_make_request(KVM_REQ_EVENT, vcpu);
10153 }
10154 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10155
10156 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10157 {
10158 int r;
10159
10160 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10161 work->wakeup_all)
10162 return;
10163
10164 r = kvm_mmu_reload(vcpu);
10165 if (unlikely(r))
10166 return;
10167
10168 if (!vcpu->arch.mmu->direct_map &&
10169 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
10170 return;
10171
10172 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10173 }
10174
10175 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10176 {
10177 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10178 }
10179
10180 static inline u32 kvm_async_pf_next_probe(u32 key)
10181 {
10182 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10183 }
10184
10185 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10186 {
10187 u32 key = kvm_async_pf_hash_fn(gfn);
10188
10189 while (vcpu->arch.apf.gfns[key] != ~0)
10190 key = kvm_async_pf_next_probe(key);
10191
10192 vcpu->arch.apf.gfns[key] = gfn;
10193 }
10194
10195 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10196 {
10197 int i;
10198 u32 key = kvm_async_pf_hash_fn(gfn);
10199
10200 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10201 (vcpu->arch.apf.gfns[key] != gfn &&
10202 vcpu->arch.apf.gfns[key] != ~0); i++)
10203 key = kvm_async_pf_next_probe(key);
10204
10205 return key;
10206 }
10207
10208 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10209 {
10210 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10211 }
10212
10213 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10214 {
10215 u32 i, j, k;
10216
10217 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10218 while (true) {
10219 vcpu->arch.apf.gfns[i] = ~0;
10220 do {
10221 j = kvm_async_pf_next_probe(j);
10222 if (vcpu->arch.apf.gfns[j] == ~0)
10223 return;
10224 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10225 /*
10226 * k lies cyclically in ]i,j]
10227 * | i.k.j |
10228 * |....j i.k.| or |.k..j i...|
10229 */
10230 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10231 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10232 i = j;
10233 }
10234 }
10235
10236 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10237 {
10238
10239 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10240 sizeof(val));
10241 }
10242
10243 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10244 {
10245
10246 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10247 sizeof(u32));
10248 }
10249
10250 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10251 {
10252 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10253 return false;
10254
10255 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10256 (vcpu->arch.apf.send_user_only &&
10257 kvm_x86_ops->get_cpl(vcpu) == 0))
10258 return false;
10259
10260 return true;
10261 }
10262
10263 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10264 {
10265 if (unlikely(!lapic_in_kernel(vcpu) ||
10266 kvm_event_needs_reinjection(vcpu) ||
10267 vcpu->arch.exception.pending))
10268 return false;
10269
10270 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10271 return false;
10272
10273 /*
10274 * If interrupts are off we cannot even use an artificial
10275 * halt state.
10276 */
10277 return kvm_x86_ops->interrupt_allowed(vcpu);
10278 }
10279
10280 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10281 struct kvm_async_pf *work)
10282 {
10283 struct x86_exception fault;
10284
10285 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10286 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10287
10288 if (kvm_can_deliver_async_pf(vcpu) &&
10289 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10290 fault.vector = PF_VECTOR;
10291 fault.error_code_valid = true;
10292 fault.error_code = 0;
10293 fault.nested_page_fault = false;
10294 fault.address = work->arch.token;
10295 fault.async_page_fault = true;
10296 kvm_inject_page_fault(vcpu, &fault);
10297 } else {
10298 /*
10299 * It is not possible to deliver a paravirtualized asynchronous
10300 * page fault, but putting the guest in an artificial halt state
10301 * can be beneficial nevertheless: if an interrupt arrives, we
10302 * can deliver it timely and perhaps the guest will schedule
10303 * another process. When the instruction that triggered a page
10304 * fault is retried, hopefully the page will be ready in the host.
10305 */
10306 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10307 }
10308 }
10309
10310 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10311 struct kvm_async_pf *work)
10312 {
10313 struct x86_exception fault;
10314 u32 val;
10315
10316 if (work->wakeup_all)
10317 work->arch.token = ~0; /* broadcast wakeup */
10318 else
10319 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10320 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10321
10322 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10323 !apf_get_user(vcpu, &val)) {
10324 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10325 vcpu->arch.exception.pending &&
10326 vcpu->arch.exception.nr == PF_VECTOR &&
10327 !apf_put_user(vcpu, 0)) {
10328 vcpu->arch.exception.injected = false;
10329 vcpu->arch.exception.pending = false;
10330 vcpu->arch.exception.nr = 0;
10331 vcpu->arch.exception.has_error_code = false;
10332 vcpu->arch.exception.error_code = 0;
10333 vcpu->arch.exception.has_payload = false;
10334 vcpu->arch.exception.payload = 0;
10335 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10336 fault.vector = PF_VECTOR;
10337 fault.error_code_valid = true;
10338 fault.error_code = 0;
10339 fault.nested_page_fault = false;
10340 fault.address = work->arch.token;
10341 fault.async_page_fault = true;
10342 kvm_inject_page_fault(vcpu, &fault);
10343 }
10344 }
10345 vcpu->arch.apf.halted = false;
10346 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10347 }
10348
10349 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10350 {
10351 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10352 return true;
10353 else
10354 return kvm_can_do_async_pf(vcpu);
10355 }
10356
10357 void kvm_arch_start_assignment(struct kvm *kvm)
10358 {
10359 atomic_inc(&kvm->arch.assigned_device_count);
10360 }
10361 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10362
10363 void kvm_arch_end_assignment(struct kvm *kvm)
10364 {
10365 atomic_dec(&kvm->arch.assigned_device_count);
10366 }
10367 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10368
10369 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10370 {
10371 return atomic_read(&kvm->arch.assigned_device_count);
10372 }
10373 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10374
10375 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10376 {
10377 atomic_inc(&kvm->arch.noncoherent_dma_count);
10378 }
10379 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10380
10381 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10382 {
10383 atomic_dec(&kvm->arch.noncoherent_dma_count);
10384 }
10385 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10386
10387 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10388 {
10389 return atomic_read(&kvm->arch.noncoherent_dma_count);
10390 }
10391 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10392
10393 bool kvm_arch_has_irq_bypass(void)
10394 {
10395 return true;
10396 }
10397
10398 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10399 struct irq_bypass_producer *prod)
10400 {
10401 struct kvm_kernel_irqfd *irqfd =
10402 container_of(cons, struct kvm_kernel_irqfd, consumer);
10403
10404 irqfd->producer = prod;
10405
10406 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10407 prod->irq, irqfd->gsi, 1);
10408 }
10409
10410 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10411 struct irq_bypass_producer *prod)
10412 {
10413 int ret;
10414 struct kvm_kernel_irqfd *irqfd =
10415 container_of(cons, struct kvm_kernel_irqfd, consumer);
10416
10417 WARN_ON(irqfd->producer != prod);
10418 irqfd->producer = NULL;
10419
10420 /*
10421 * When producer of consumer is unregistered, we change back to
10422 * remapped mode, so we can re-use the current implementation
10423 * when the irq is masked/disabled or the consumer side (KVM
10424 * int this case doesn't want to receive the interrupts.
10425 */
10426 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10427 if (ret)
10428 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10429 " fails: %d\n", irqfd->consumer.token, ret);
10430 }
10431
10432 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10433 uint32_t guest_irq, bool set)
10434 {
10435 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10436 }
10437
10438 bool kvm_vector_hashing_enabled(void)
10439 {
10440 return vector_hashing;
10441 }
10442
10443 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10444 {
10445 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10446 }
10447 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10448
10449 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10450 {
10451 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10452
10453 /* The STIBP bit doesn't fault even if it's not advertised */
10454 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10455 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10456 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10457 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10458 !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10459 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10460
10461 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10462 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10463 bits &= ~SPEC_CTRL_SSBD;
10464 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10465 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10466 bits &= ~SPEC_CTRL_SSBD;
10467
10468 return bits;
10469 }
10470 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10471
10472 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10473 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10474 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10475 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10476 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10477 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10478 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10479 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10480 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10481 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10482 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10483 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10484 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10485 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10486 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10487 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10488 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10489 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10490 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10491 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10492 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
Ubuntu Jammy Linux kernel mirror