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KVM: host side for eoi optimization
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
50
51 #define CREATE_TRACE_POINTS
52 #include "trace.h"
53
54 #include <asm/debugreg.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <asm/mtrr.h>
58 #include <asm/mce.h>
59 #include <asm/i387.h>
60 #include <asm/fpu-internal.h> /* Ugh! */
61 #include <asm/xcr.h>
62 #include <asm/pvclock.h>
63 #include <asm/div64.h>
64
65 #define MAX_IO_MSRS 256
66 #define KVM_MAX_MCE_BANKS 32
67 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
68
69 #define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
72 /* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76 #ifdef CONFIG_X86_64
77 static
78 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
79 #else
80 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
81 #endif
82
83 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
85
86 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
87 static void process_nmi(struct kvm_vcpu *vcpu);
88
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
91
92 static bool ignore_msrs = 0;
93 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
95 bool kvm_has_tsc_control;
96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97 u32 kvm_max_guest_tsc_khz;
98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
100 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101 static u32 tsc_tolerance_ppm = 250;
102 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
104 #define KVM_NR_SHARED_MSRS 16
105
106 struct kvm_shared_msrs_global {
107 int nr;
108 u32 msrs[KVM_NR_SHARED_MSRS];
109 };
110
111 struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
118 };
119
120 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
123 struct kvm_stats_debugfs_item debugfs_entries[] = {
124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
136 { "hypercalls", VCPU_STAT(hypercalls) },
137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
144 { "irq_injections", VCPU_STAT(irq_injections) },
145 { "nmi_injections", VCPU_STAT(nmi_injections) },
146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
153 { "mmu_unsync", VM_STAT(mmu_unsync) },
154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
155 { "largepages", VM_STAT(lpages) },
156 { NULL }
157 };
158
159 u64 __read_mostly host_xcr0;
160
161 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
163 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164 {
165 int i;
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
168 }
169
170 static void kvm_on_user_return(struct user_return_notifier *urn)
171 {
172 unsigned slot;
173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
175 struct kvm_shared_msr_values *values;
176
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
182 }
183 }
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
186 }
187
188 static void shared_msr_update(unsigned slot, u32 msr)
189 {
190 struct kvm_shared_msrs *smsr;
191 u64 value;
192
193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
198 return;
199 }
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
203 }
204
205 void kvm_define_shared_msr(unsigned slot, u32 msr)
206 {
207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
211 smp_wmb();
212 }
213 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215 static void kvm_shared_msr_cpu_online(void)
216 {
217 unsigned i;
218
219 for (i = 0; i < shared_msrs_global.nr; ++i)
220 shared_msr_update(i, shared_msrs_global.msrs[i]);
221 }
222
223 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
224 {
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
228 return;
229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
235 }
236 }
237 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
239 static void drop_user_return_notifiers(void *ignore)
240 {
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
245 }
246
247 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248 {
249 if (irqchip_in_kernel(vcpu->kvm))
250 return vcpu->arch.apic_base;
251 else
252 return vcpu->arch.apic_base;
253 }
254 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
255
256 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
257 {
258 /* TODO: reserve bits check */
259 if (irqchip_in_kernel(vcpu->kvm))
260 kvm_lapic_set_base(vcpu, data);
261 else
262 vcpu->arch.apic_base = data;
263 }
264 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
266 #define EXCPT_BENIGN 0
267 #define EXCPT_CONTRIBUTORY 1
268 #define EXCPT_PF 2
269
270 static int exception_class(int vector)
271 {
272 switch (vector) {
273 case PF_VECTOR:
274 return EXCPT_PF;
275 case DE_VECTOR:
276 case TS_VECTOR:
277 case NP_VECTOR:
278 case SS_VECTOR:
279 case GP_VECTOR:
280 return EXCPT_CONTRIBUTORY;
281 default:
282 break;
283 }
284 return EXCPT_BENIGN;
285 }
286
287 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
288 unsigned nr, bool has_error, u32 error_code,
289 bool reinject)
290 {
291 u32 prev_nr;
292 int class1, class2;
293
294 kvm_make_request(KVM_REQ_EVENT, vcpu);
295
296 if (!vcpu->arch.exception.pending) {
297 queue:
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
302 vcpu->arch.exception.reinject = reinject;
303 return;
304 }
305
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
311 return;
312 }
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
322 } else
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
325 exception */
326 goto queue;
327 }
328
329 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 {
331 kvm_multiple_exception(vcpu, nr, false, 0, false);
332 }
333 EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
335 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336 {
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
338 }
339 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
341 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
342 {
343 if (err)
344 kvm_inject_gp(vcpu, 0);
345 else
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
347 }
348 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
349
350 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
351 {
352 ++vcpu->stat.pf_guest;
353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
355 }
356 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
357
358 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
359 {
360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
362 else
363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
364 }
365
366 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367 {
368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
370 }
371 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
373 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374 {
375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
376 }
377 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
379 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380 {
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382 }
383 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
385 /*
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
388 */
389 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
390 {
391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 return true;
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394 return false;
395 }
396 EXPORT_SYMBOL_GPL(kvm_require_cpl);
397
398 /*
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
402 */
403 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
405 u32 access)
406 {
407 gfn_t real_gfn;
408 gpa_t ngpa;
409
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
413 return -EFAULT;
414
415 real_gfn = gpa_to_gfn(real_gfn);
416
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418 }
419 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
421 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
423 {
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
426 }
427
428 /*
429 * Load the pae pdptrs. Return true is they are all valid.
430 */
431 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
432 {
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435 int i;
436 int ret;
437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
438
439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
442 if (ret < 0) {
443 ret = 0;
444 goto out;
445 }
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
447 if (is_present_gpte(pdpte[i]) &&
448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
449 ret = 0;
450 goto out;
451 }
452 }
453 ret = 1;
454
455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
460 out:
461
462 return ret;
463 }
464 EXPORT_SYMBOL_GPL(load_pdptrs);
465
466 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467 {
468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
469 bool changed = true;
470 int offset;
471 gfn_t gfn;
472 int r;
473
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
475 return false;
476
477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
479 return true;
480
481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
485 if (r < 0)
486 goto out;
487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
488 out:
489
490 return changed;
491 }
492
493 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
494 {
495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
498
499 cr0 |= X86_CR0_ET;
500
501 #ifdef CONFIG_X86_64
502 if (cr0 & 0xffffffff00000000UL)
503 return 1;
504 #endif
505
506 cr0 &= ~CR0_RESERVED_BITS;
507
508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509 return 1;
510
511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512 return 1;
513
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515 #ifdef CONFIG_X86_64
516 if ((vcpu->arch.efer & EFER_LME)) {
517 int cs_db, cs_l;
518
519 if (!is_pae(vcpu))
520 return 1;
521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
522 if (cs_l)
523 return 1;
524 } else
525 #endif
526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
527 kvm_read_cr3(vcpu)))
528 return 1;
529 }
530
531 kvm_x86_ops->set_cr0(vcpu, cr0);
532
533 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
534 kvm_clear_async_pf_completion_queue(vcpu);
535 kvm_async_pf_hash_reset(vcpu);
536 }
537
538 if ((cr0 ^ old_cr0) & update_bits)
539 kvm_mmu_reset_context(vcpu);
540 return 0;
541 }
542 EXPORT_SYMBOL_GPL(kvm_set_cr0);
543
544 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
545 {
546 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
547 }
548 EXPORT_SYMBOL_GPL(kvm_lmsw);
549
550 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
551 {
552 u64 xcr0;
553
554 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
555 if (index != XCR_XFEATURE_ENABLED_MASK)
556 return 1;
557 xcr0 = xcr;
558 if (kvm_x86_ops->get_cpl(vcpu) != 0)
559 return 1;
560 if (!(xcr0 & XSTATE_FP))
561 return 1;
562 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
563 return 1;
564 if (xcr0 & ~host_xcr0)
565 return 1;
566 vcpu->arch.xcr0 = xcr0;
567 vcpu->guest_xcr0_loaded = 0;
568 return 0;
569 }
570
571 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
572 {
573 if (__kvm_set_xcr(vcpu, index, xcr)) {
574 kvm_inject_gp(vcpu, 0);
575 return 1;
576 }
577 return 0;
578 }
579 EXPORT_SYMBOL_GPL(kvm_set_xcr);
580
581 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
582 {
583 unsigned long old_cr4 = kvm_read_cr4(vcpu);
584 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
585 X86_CR4_PAE | X86_CR4_SMEP;
586 if (cr4 & CR4_RESERVED_BITS)
587 return 1;
588
589 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
590 return 1;
591
592 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
593 return 1;
594
595 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
596 return 1;
597
598 if (is_long_mode(vcpu)) {
599 if (!(cr4 & X86_CR4_PAE))
600 return 1;
601 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
602 && ((cr4 ^ old_cr4) & pdptr_bits)
603 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
604 kvm_read_cr3(vcpu)))
605 return 1;
606
607 if (kvm_x86_ops->set_cr4(vcpu, cr4))
608 return 1;
609
610 if ((cr4 ^ old_cr4) & pdptr_bits)
611 kvm_mmu_reset_context(vcpu);
612
613 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
614 kvm_update_cpuid(vcpu);
615
616 return 0;
617 }
618 EXPORT_SYMBOL_GPL(kvm_set_cr4);
619
620 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
621 {
622 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
623 kvm_mmu_sync_roots(vcpu);
624 kvm_mmu_flush_tlb(vcpu);
625 return 0;
626 }
627
628 if (is_long_mode(vcpu)) {
629 if (cr3 & CR3_L_MODE_RESERVED_BITS)
630 return 1;
631 } else {
632 if (is_pae(vcpu)) {
633 if (cr3 & CR3_PAE_RESERVED_BITS)
634 return 1;
635 if (is_paging(vcpu) &&
636 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
637 return 1;
638 }
639 /*
640 * We don't check reserved bits in nonpae mode, because
641 * this isn't enforced, and VMware depends on this.
642 */
643 }
644
645 /*
646 * Does the new cr3 value map to physical memory? (Note, we
647 * catch an invalid cr3 even in real-mode, because it would
648 * cause trouble later on when we turn on paging anyway.)
649 *
650 * A real CPU would silently accept an invalid cr3 and would
651 * attempt to use it - with largely undefined (and often hard
652 * to debug) behavior on the guest side.
653 */
654 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
655 return 1;
656 vcpu->arch.cr3 = cr3;
657 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
658 vcpu->arch.mmu.new_cr3(vcpu);
659 return 0;
660 }
661 EXPORT_SYMBOL_GPL(kvm_set_cr3);
662
663 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
664 {
665 if (cr8 & CR8_RESERVED_BITS)
666 return 1;
667 if (irqchip_in_kernel(vcpu->kvm))
668 kvm_lapic_set_tpr(vcpu, cr8);
669 else
670 vcpu->arch.cr8 = cr8;
671 return 0;
672 }
673 EXPORT_SYMBOL_GPL(kvm_set_cr8);
674
675 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
676 {
677 if (irqchip_in_kernel(vcpu->kvm))
678 return kvm_lapic_get_cr8(vcpu);
679 else
680 return vcpu->arch.cr8;
681 }
682 EXPORT_SYMBOL_GPL(kvm_get_cr8);
683
684 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
685 {
686 switch (dr) {
687 case 0 ... 3:
688 vcpu->arch.db[dr] = val;
689 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
690 vcpu->arch.eff_db[dr] = val;
691 break;
692 case 4:
693 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
694 return 1; /* #UD */
695 /* fall through */
696 case 6:
697 if (val & 0xffffffff00000000ULL)
698 return -1; /* #GP */
699 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
700 break;
701 case 5:
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
703 return 1; /* #UD */
704 /* fall through */
705 default: /* 7 */
706 if (val & 0xffffffff00000000ULL)
707 return -1; /* #GP */
708 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
709 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
710 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
711 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
712 }
713 break;
714 }
715
716 return 0;
717 }
718
719 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
720 {
721 int res;
722
723 res = __kvm_set_dr(vcpu, dr, val);
724 if (res > 0)
725 kvm_queue_exception(vcpu, UD_VECTOR);
726 else if (res < 0)
727 kvm_inject_gp(vcpu, 0);
728
729 return res;
730 }
731 EXPORT_SYMBOL_GPL(kvm_set_dr);
732
733 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
734 {
735 switch (dr) {
736 case 0 ... 3:
737 *val = vcpu->arch.db[dr];
738 break;
739 case 4:
740 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
741 return 1;
742 /* fall through */
743 case 6:
744 *val = vcpu->arch.dr6;
745 break;
746 case 5:
747 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
748 return 1;
749 /* fall through */
750 default: /* 7 */
751 *val = vcpu->arch.dr7;
752 break;
753 }
754
755 return 0;
756 }
757
758 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
759 {
760 if (_kvm_get_dr(vcpu, dr, val)) {
761 kvm_queue_exception(vcpu, UD_VECTOR);
762 return 1;
763 }
764 return 0;
765 }
766 EXPORT_SYMBOL_GPL(kvm_get_dr);
767
768 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
769 {
770 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
771 u64 data;
772 int err;
773
774 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
775 if (err)
776 return err;
777 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
778 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
779 return err;
780 }
781 EXPORT_SYMBOL_GPL(kvm_rdpmc);
782
783 /*
784 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
785 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
786 *
787 * This list is modified at module load time to reflect the
788 * capabilities of the host cpu. This capabilities test skips MSRs that are
789 * kvm-specific. Those are put in the beginning of the list.
790 */
791
792 #define KVM_SAVE_MSRS_BEGIN 9
793 static u32 msrs_to_save[] = {
794 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
795 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
796 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
797 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
798 MSR_KVM_PV_EOI_EN,
799 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
800 MSR_STAR,
801 #ifdef CONFIG_X86_64
802 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
803 #endif
804 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
805 };
806
807 static unsigned num_msrs_to_save;
808
809 static u32 emulated_msrs[] = {
810 MSR_IA32_TSCDEADLINE,
811 MSR_IA32_MISC_ENABLE,
812 MSR_IA32_MCG_STATUS,
813 MSR_IA32_MCG_CTL,
814 };
815
816 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
817 {
818 u64 old_efer = vcpu->arch.efer;
819
820 if (efer & efer_reserved_bits)
821 return 1;
822
823 if (is_paging(vcpu)
824 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
825 return 1;
826
827 if (efer & EFER_FFXSR) {
828 struct kvm_cpuid_entry2 *feat;
829
830 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
831 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
832 return 1;
833 }
834
835 if (efer & EFER_SVME) {
836 struct kvm_cpuid_entry2 *feat;
837
838 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
839 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
840 return 1;
841 }
842
843 efer &= ~EFER_LMA;
844 efer |= vcpu->arch.efer & EFER_LMA;
845
846 kvm_x86_ops->set_efer(vcpu, efer);
847
848 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
849
850 /* Update reserved bits */
851 if ((efer ^ old_efer) & EFER_NX)
852 kvm_mmu_reset_context(vcpu);
853
854 return 0;
855 }
856
857 void kvm_enable_efer_bits(u64 mask)
858 {
859 efer_reserved_bits &= ~mask;
860 }
861 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
862
863
864 /*
865 * Writes msr value into into the appropriate "register".
866 * Returns 0 on success, non-0 otherwise.
867 * Assumes vcpu_load() was already called.
868 */
869 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
870 {
871 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
872 }
873
874 /*
875 * Adapt set_msr() to msr_io()'s calling convention
876 */
877 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
878 {
879 return kvm_set_msr(vcpu, index, *data);
880 }
881
882 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
883 {
884 int version;
885 int r;
886 struct pvclock_wall_clock wc;
887 struct timespec boot;
888
889 if (!wall_clock)
890 return;
891
892 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
893 if (r)
894 return;
895
896 if (version & 1)
897 ++version; /* first time write, random junk */
898
899 ++version;
900
901 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
902
903 /*
904 * The guest calculates current wall clock time by adding
905 * system time (updated by kvm_guest_time_update below) to the
906 * wall clock specified here. guest system time equals host
907 * system time for us, thus we must fill in host boot time here.
908 */
909 getboottime(&boot);
910
911 wc.sec = boot.tv_sec;
912 wc.nsec = boot.tv_nsec;
913 wc.version = version;
914
915 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
916
917 version++;
918 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
919 }
920
921 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
922 {
923 uint32_t quotient, remainder;
924
925 /* Don't try to replace with do_div(), this one calculates
926 * "(dividend << 32) / divisor" */
927 __asm__ ( "divl %4"
928 : "=a" (quotient), "=d" (remainder)
929 : "0" (0), "1" (dividend), "r" (divisor) );
930 return quotient;
931 }
932
933 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
934 s8 *pshift, u32 *pmultiplier)
935 {
936 uint64_t scaled64;
937 int32_t shift = 0;
938 uint64_t tps64;
939 uint32_t tps32;
940
941 tps64 = base_khz * 1000LL;
942 scaled64 = scaled_khz * 1000LL;
943 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
944 tps64 >>= 1;
945 shift--;
946 }
947
948 tps32 = (uint32_t)tps64;
949 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
950 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
951 scaled64 >>= 1;
952 else
953 tps32 <<= 1;
954 shift++;
955 }
956
957 *pshift = shift;
958 *pmultiplier = div_frac(scaled64, tps32);
959
960 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
961 __func__, base_khz, scaled_khz, shift, *pmultiplier);
962 }
963
964 static inline u64 get_kernel_ns(void)
965 {
966 struct timespec ts;
967
968 WARN_ON(preemptible());
969 ktime_get_ts(&ts);
970 monotonic_to_bootbased(&ts);
971 return timespec_to_ns(&ts);
972 }
973
974 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
975 unsigned long max_tsc_khz;
976
977 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
978 {
979 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
980 vcpu->arch.virtual_tsc_shift);
981 }
982
983 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
984 {
985 u64 v = (u64)khz * (1000000 + ppm);
986 do_div(v, 1000000);
987 return v;
988 }
989
990 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
991 {
992 u32 thresh_lo, thresh_hi;
993 int use_scaling = 0;
994
995 /* Compute a scale to convert nanoseconds in TSC cycles */
996 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
997 &vcpu->arch.virtual_tsc_shift,
998 &vcpu->arch.virtual_tsc_mult);
999 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1000
1001 /*
1002 * Compute the variation in TSC rate which is acceptable
1003 * within the range of tolerance and decide if the
1004 * rate being applied is within that bounds of the hardware
1005 * rate. If so, no scaling or compensation need be done.
1006 */
1007 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1008 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1009 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1010 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1011 use_scaling = 1;
1012 }
1013 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1014 }
1015
1016 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1017 {
1018 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1019 vcpu->arch.virtual_tsc_mult,
1020 vcpu->arch.virtual_tsc_shift);
1021 tsc += vcpu->arch.this_tsc_write;
1022 return tsc;
1023 }
1024
1025 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1026 {
1027 struct kvm *kvm = vcpu->kvm;
1028 u64 offset, ns, elapsed;
1029 unsigned long flags;
1030 s64 usdiff;
1031
1032 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1033 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1034 ns = get_kernel_ns();
1035 elapsed = ns - kvm->arch.last_tsc_nsec;
1036
1037 /* n.b - signed multiplication and division required */
1038 usdiff = data - kvm->arch.last_tsc_write;
1039 #ifdef CONFIG_X86_64
1040 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1041 #else
1042 /* do_div() only does unsigned */
1043 asm("idivl %2; xor %%edx, %%edx"
1044 : "=A"(usdiff)
1045 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1046 #endif
1047 do_div(elapsed, 1000);
1048 usdiff -= elapsed;
1049 if (usdiff < 0)
1050 usdiff = -usdiff;
1051
1052 /*
1053 * Special case: TSC write with a small delta (1 second) of virtual
1054 * cycle time against real time is interpreted as an attempt to
1055 * synchronize the CPU.
1056 *
1057 * For a reliable TSC, we can match TSC offsets, and for an unstable
1058 * TSC, we add elapsed time in this computation. We could let the
1059 * compensation code attempt to catch up if we fall behind, but
1060 * it's better to try to match offsets from the beginning.
1061 */
1062 if (usdiff < USEC_PER_SEC &&
1063 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1064 if (!check_tsc_unstable()) {
1065 offset = kvm->arch.cur_tsc_offset;
1066 pr_debug("kvm: matched tsc offset for %llu\n", data);
1067 } else {
1068 u64 delta = nsec_to_cycles(vcpu, elapsed);
1069 data += delta;
1070 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1071 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1072 }
1073 } else {
1074 /*
1075 * We split periods of matched TSC writes into generations.
1076 * For each generation, we track the original measured
1077 * nanosecond time, offset, and write, so if TSCs are in
1078 * sync, we can match exact offset, and if not, we can match
1079 * exact software computaion in compute_guest_tsc()
1080 *
1081 * These values are tracked in kvm->arch.cur_xxx variables.
1082 */
1083 kvm->arch.cur_tsc_generation++;
1084 kvm->arch.cur_tsc_nsec = ns;
1085 kvm->arch.cur_tsc_write = data;
1086 kvm->arch.cur_tsc_offset = offset;
1087 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1088 kvm->arch.cur_tsc_generation, data);
1089 }
1090
1091 /*
1092 * We also track th most recent recorded KHZ, write and time to
1093 * allow the matching interval to be extended at each write.
1094 */
1095 kvm->arch.last_tsc_nsec = ns;
1096 kvm->arch.last_tsc_write = data;
1097 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1098
1099 /* Reset of TSC must disable overshoot protection below */
1100 vcpu->arch.hv_clock.tsc_timestamp = 0;
1101 vcpu->arch.last_guest_tsc = data;
1102
1103 /* Keep track of which generation this VCPU has synchronized to */
1104 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1105 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1106 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1107
1108 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1109 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1110 }
1111
1112 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1113
1114 static int kvm_guest_time_update(struct kvm_vcpu *v)
1115 {
1116 unsigned long flags;
1117 struct kvm_vcpu_arch *vcpu = &v->arch;
1118 void *shared_kaddr;
1119 unsigned long this_tsc_khz;
1120 s64 kernel_ns, max_kernel_ns;
1121 u64 tsc_timestamp;
1122
1123 /* Keep irq disabled to prevent changes to the clock */
1124 local_irq_save(flags);
1125 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1126 kernel_ns = get_kernel_ns();
1127 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1128 if (unlikely(this_tsc_khz == 0)) {
1129 local_irq_restore(flags);
1130 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1131 return 1;
1132 }
1133
1134 /*
1135 * We may have to catch up the TSC to match elapsed wall clock
1136 * time for two reasons, even if kvmclock is used.
1137 * 1) CPU could have been running below the maximum TSC rate
1138 * 2) Broken TSC compensation resets the base at each VCPU
1139 * entry to avoid unknown leaps of TSC even when running
1140 * again on the same CPU. This may cause apparent elapsed
1141 * time to disappear, and the guest to stand still or run
1142 * very slowly.
1143 */
1144 if (vcpu->tsc_catchup) {
1145 u64 tsc = compute_guest_tsc(v, kernel_ns);
1146 if (tsc > tsc_timestamp) {
1147 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1148 tsc_timestamp = tsc;
1149 }
1150 }
1151
1152 local_irq_restore(flags);
1153
1154 if (!vcpu->time_page)
1155 return 0;
1156
1157 /*
1158 * Time as measured by the TSC may go backwards when resetting the base
1159 * tsc_timestamp. The reason for this is that the TSC resolution is
1160 * higher than the resolution of the other clock scales. Thus, many
1161 * possible measurments of the TSC correspond to one measurement of any
1162 * other clock, and so a spread of values is possible. This is not a
1163 * problem for the computation of the nanosecond clock; with TSC rates
1164 * around 1GHZ, there can only be a few cycles which correspond to one
1165 * nanosecond value, and any path through this code will inevitably
1166 * take longer than that. However, with the kernel_ns value itself,
1167 * the precision may be much lower, down to HZ granularity. If the
1168 * first sampling of TSC against kernel_ns ends in the low part of the
1169 * range, and the second in the high end of the range, we can get:
1170 *
1171 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1172 *
1173 * As the sampling errors potentially range in the thousands of cycles,
1174 * it is possible such a time value has already been observed by the
1175 * guest. To protect against this, we must compute the system time as
1176 * observed by the guest and ensure the new system time is greater.
1177 */
1178 max_kernel_ns = 0;
1179 if (vcpu->hv_clock.tsc_timestamp) {
1180 max_kernel_ns = vcpu->last_guest_tsc -
1181 vcpu->hv_clock.tsc_timestamp;
1182 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1183 vcpu->hv_clock.tsc_to_system_mul,
1184 vcpu->hv_clock.tsc_shift);
1185 max_kernel_ns += vcpu->last_kernel_ns;
1186 }
1187
1188 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1189 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1190 &vcpu->hv_clock.tsc_shift,
1191 &vcpu->hv_clock.tsc_to_system_mul);
1192 vcpu->hw_tsc_khz = this_tsc_khz;
1193 }
1194
1195 if (max_kernel_ns > kernel_ns)
1196 kernel_ns = max_kernel_ns;
1197
1198 /* With all the info we got, fill in the values */
1199 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1200 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1201 vcpu->last_kernel_ns = kernel_ns;
1202 vcpu->last_guest_tsc = tsc_timestamp;
1203 vcpu->hv_clock.flags = 0;
1204
1205 /*
1206 * The interface expects us to write an even number signaling that the
1207 * update is finished. Since the guest won't see the intermediate
1208 * state, we just increase by 2 at the end.
1209 */
1210 vcpu->hv_clock.version += 2;
1211
1212 shared_kaddr = kmap_atomic(vcpu->time_page);
1213
1214 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1215 sizeof(vcpu->hv_clock));
1216
1217 kunmap_atomic(shared_kaddr);
1218
1219 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1220 return 0;
1221 }
1222
1223 static bool msr_mtrr_valid(unsigned msr)
1224 {
1225 switch (msr) {
1226 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1227 case MSR_MTRRfix64K_00000:
1228 case MSR_MTRRfix16K_80000:
1229 case MSR_MTRRfix16K_A0000:
1230 case MSR_MTRRfix4K_C0000:
1231 case MSR_MTRRfix4K_C8000:
1232 case MSR_MTRRfix4K_D0000:
1233 case MSR_MTRRfix4K_D8000:
1234 case MSR_MTRRfix4K_E0000:
1235 case MSR_MTRRfix4K_E8000:
1236 case MSR_MTRRfix4K_F0000:
1237 case MSR_MTRRfix4K_F8000:
1238 case MSR_MTRRdefType:
1239 case MSR_IA32_CR_PAT:
1240 return true;
1241 case 0x2f8:
1242 return true;
1243 }
1244 return false;
1245 }
1246
1247 static bool valid_pat_type(unsigned t)
1248 {
1249 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1250 }
1251
1252 static bool valid_mtrr_type(unsigned t)
1253 {
1254 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1255 }
1256
1257 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1258 {
1259 int i;
1260
1261 if (!msr_mtrr_valid(msr))
1262 return false;
1263
1264 if (msr == MSR_IA32_CR_PAT) {
1265 for (i = 0; i < 8; i++)
1266 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1267 return false;
1268 return true;
1269 } else if (msr == MSR_MTRRdefType) {
1270 if (data & ~0xcff)
1271 return false;
1272 return valid_mtrr_type(data & 0xff);
1273 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1274 for (i = 0; i < 8 ; i++)
1275 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1276 return false;
1277 return true;
1278 }
1279
1280 /* variable MTRRs */
1281 return valid_mtrr_type(data & 0xff);
1282 }
1283
1284 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1285 {
1286 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1287
1288 if (!mtrr_valid(vcpu, msr, data))
1289 return 1;
1290
1291 if (msr == MSR_MTRRdefType) {
1292 vcpu->arch.mtrr_state.def_type = data;
1293 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1294 } else if (msr == MSR_MTRRfix64K_00000)
1295 p[0] = data;
1296 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1297 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1298 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1299 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1300 else if (msr == MSR_IA32_CR_PAT)
1301 vcpu->arch.pat = data;
1302 else { /* Variable MTRRs */
1303 int idx, is_mtrr_mask;
1304 u64 *pt;
1305
1306 idx = (msr - 0x200) / 2;
1307 is_mtrr_mask = msr - 0x200 - 2 * idx;
1308 if (!is_mtrr_mask)
1309 pt =
1310 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1311 else
1312 pt =
1313 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1314 *pt = data;
1315 }
1316
1317 kvm_mmu_reset_context(vcpu);
1318 return 0;
1319 }
1320
1321 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1322 {
1323 u64 mcg_cap = vcpu->arch.mcg_cap;
1324 unsigned bank_num = mcg_cap & 0xff;
1325
1326 switch (msr) {
1327 case MSR_IA32_MCG_STATUS:
1328 vcpu->arch.mcg_status = data;
1329 break;
1330 case MSR_IA32_MCG_CTL:
1331 if (!(mcg_cap & MCG_CTL_P))
1332 return 1;
1333 if (data != 0 && data != ~(u64)0)
1334 return -1;
1335 vcpu->arch.mcg_ctl = data;
1336 break;
1337 default:
1338 if (msr >= MSR_IA32_MC0_CTL &&
1339 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1340 u32 offset = msr - MSR_IA32_MC0_CTL;
1341 /* only 0 or all 1s can be written to IA32_MCi_CTL
1342 * some Linux kernels though clear bit 10 in bank 4 to
1343 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1344 * this to avoid an uncatched #GP in the guest
1345 */
1346 if ((offset & 0x3) == 0 &&
1347 data != 0 && (data | (1 << 10)) != ~(u64)0)
1348 return -1;
1349 vcpu->arch.mce_banks[offset] = data;
1350 break;
1351 }
1352 return 1;
1353 }
1354 return 0;
1355 }
1356
1357 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1358 {
1359 struct kvm *kvm = vcpu->kvm;
1360 int lm = is_long_mode(vcpu);
1361 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1362 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1363 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1364 : kvm->arch.xen_hvm_config.blob_size_32;
1365 u32 page_num = data & ~PAGE_MASK;
1366 u64 page_addr = data & PAGE_MASK;
1367 u8 *page;
1368 int r;
1369
1370 r = -E2BIG;
1371 if (page_num >= blob_size)
1372 goto out;
1373 r = -ENOMEM;
1374 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1375 if (IS_ERR(page)) {
1376 r = PTR_ERR(page);
1377 goto out;
1378 }
1379 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1380 goto out_free;
1381 r = 0;
1382 out_free:
1383 kfree(page);
1384 out:
1385 return r;
1386 }
1387
1388 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1389 {
1390 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1391 }
1392
1393 static bool kvm_hv_msr_partition_wide(u32 msr)
1394 {
1395 bool r = false;
1396 switch (msr) {
1397 case HV_X64_MSR_GUEST_OS_ID:
1398 case HV_X64_MSR_HYPERCALL:
1399 r = true;
1400 break;
1401 }
1402
1403 return r;
1404 }
1405
1406 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1407 {
1408 struct kvm *kvm = vcpu->kvm;
1409
1410 switch (msr) {
1411 case HV_X64_MSR_GUEST_OS_ID:
1412 kvm->arch.hv_guest_os_id = data;
1413 /* setting guest os id to zero disables hypercall page */
1414 if (!kvm->arch.hv_guest_os_id)
1415 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1416 break;
1417 case HV_X64_MSR_HYPERCALL: {
1418 u64 gfn;
1419 unsigned long addr;
1420 u8 instructions[4];
1421
1422 /* if guest os id is not set hypercall should remain disabled */
1423 if (!kvm->arch.hv_guest_os_id)
1424 break;
1425 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1426 kvm->arch.hv_hypercall = data;
1427 break;
1428 }
1429 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1430 addr = gfn_to_hva(kvm, gfn);
1431 if (kvm_is_error_hva(addr))
1432 return 1;
1433 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1434 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1435 if (__copy_to_user((void __user *)addr, instructions, 4))
1436 return 1;
1437 kvm->arch.hv_hypercall = data;
1438 break;
1439 }
1440 default:
1441 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1442 "data 0x%llx\n", msr, data);
1443 return 1;
1444 }
1445 return 0;
1446 }
1447
1448 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1449 {
1450 switch (msr) {
1451 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1452 unsigned long addr;
1453
1454 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1455 vcpu->arch.hv_vapic = data;
1456 break;
1457 }
1458 addr = gfn_to_hva(vcpu->kvm, data >>
1459 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1460 if (kvm_is_error_hva(addr))
1461 return 1;
1462 if (__clear_user((void __user *)addr, PAGE_SIZE))
1463 return 1;
1464 vcpu->arch.hv_vapic = data;
1465 break;
1466 }
1467 case HV_X64_MSR_EOI:
1468 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1469 case HV_X64_MSR_ICR:
1470 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1471 case HV_X64_MSR_TPR:
1472 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1473 default:
1474 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1475 "data 0x%llx\n", msr, data);
1476 return 1;
1477 }
1478
1479 return 0;
1480 }
1481
1482 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1483 {
1484 gpa_t gpa = data & ~0x3f;
1485
1486 /* Bits 2:5 are resrved, Should be zero */
1487 if (data & 0x3c)
1488 return 1;
1489
1490 vcpu->arch.apf.msr_val = data;
1491
1492 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1493 kvm_clear_async_pf_completion_queue(vcpu);
1494 kvm_async_pf_hash_reset(vcpu);
1495 return 0;
1496 }
1497
1498 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1499 return 1;
1500
1501 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1502 kvm_async_pf_wakeup_all(vcpu);
1503 return 0;
1504 }
1505
1506 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1507 {
1508 if (vcpu->arch.time_page) {
1509 kvm_release_page_dirty(vcpu->arch.time_page);
1510 vcpu->arch.time_page = NULL;
1511 }
1512 }
1513
1514 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1515 {
1516 u64 delta;
1517
1518 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1519 return;
1520
1521 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1522 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1523 vcpu->arch.st.accum_steal = delta;
1524 }
1525
1526 static void record_steal_time(struct kvm_vcpu *vcpu)
1527 {
1528 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1529 return;
1530
1531 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1532 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1533 return;
1534
1535 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1536 vcpu->arch.st.steal.version += 2;
1537 vcpu->arch.st.accum_steal = 0;
1538
1539 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1540 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1541 }
1542
1543 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1544 {
1545 bool pr = false;
1546
1547 switch (msr) {
1548 case MSR_EFER:
1549 return set_efer(vcpu, data);
1550 case MSR_K7_HWCR:
1551 data &= ~(u64)0x40; /* ignore flush filter disable */
1552 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1553 data &= ~(u64)0x8; /* ignore TLB cache disable */
1554 if (data != 0) {
1555 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1556 data);
1557 return 1;
1558 }
1559 break;
1560 case MSR_FAM10H_MMIO_CONF_BASE:
1561 if (data != 0) {
1562 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1563 "0x%llx\n", data);
1564 return 1;
1565 }
1566 break;
1567 case MSR_AMD64_NB_CFG:
1568 break;
1569 case MSR_IA32_DEBUGCTLMSR:
1570 if (!data) {
1571 /* We support the non-activated case already */
1572 break;
1573 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1574 /* Values other than LBR and BTF are vendor-specific,
1575 thus reserved and should throw a #GP */
1576 return 1;
1577 }
1578 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1579 __func__, data);
1580 break;
1581 case MSR_IA32_UCODE_REV:
1582 case MSR_IA32_UCODE_WRITE:
1583 case MSR_VM_HSAVE_PA:
1584 case MSR_AMD64_PATCH_LOADER:
1585 break;
1586 case 0x200 ... 0x2ff:
1587 return set_msr_mtrr(vcpu, msr, data);
1588 case MSR_IA32_APICBASE:
1589 kvm_set_apic_base(vcpu, data);
1590 break;
1591 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1592 return kvm_x2apic_msr_write(vcpu, msr, data);
1593 case MSR_IA32_TSCDEADLINE:
1594 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1595 break;
1596 case MSR_IA32_MISC_ENABLE:
1597 vcpu->arch.ia32_misc_enable_msr = data;
1598 break;
1599 case MSR_KVM_WALL_CLOCK_NEW:
1600 case MSR_KVM_WALL_CLOCK:
1601 vcpu->kvm->arch.wall_clock = data;
1602 kvm_write_wall_clock(vcpu->kvm, data);
1603 break;
1604 case MSR_KVM_SYSTEM_TIME_NEW:
1605 case MSR_KVM_SYSTEM_TIME: {
1606 kvmclock_reset(vcpu);
1607
1608 vcpu->arch.time = data;
1609 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1610
1611 /* we verify if the enable bit is set... */
1612 if (!(data & 1))
1613 break;
1614
1615 /* ...but clean it before doing the actual write */
1616 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1617
1618 vcpu->arch.time_page =
1619 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1620
1621 if (is_error_page(vcpu->arch.time_page)) {
1622 kvm_release_page_clean(vcpu->arch.time_page);
1623 vcpu->arch.time_page = NULL;
1624 }
1625 break;
1626 }
1627 case MSR_KVM_ASYNC_PF_EN:
1628 if (kvm_pv_enable_async_pf(vcpu, data))
1629 return 1;
1630 break;
1631 case MSR_KVM_STEAL_TIME:
1632
1633 if (unlikely(!sched_info_on()))
1634 return 1;
1635
1636 if (data & KVM_STEAL_RESERVED_MASK)
1637 return 1;
1638
1639 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1640 data & KVM_STEAL_VALID_BITS))
1641 return 1;
1642
1643 vcpu->arch.st.msr_val = data;
1644
1645 if (!(data & KVM_MSR_ENABLED))
1646 break;
1647
1648 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1649
1650 preempt_disable();
1651 accumulate_steal_time(vcpu);
1652 preempt_enable();
1653
1654 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1655
1656 break;
1657 case MSR_KVM_PV_EOI_EN:
1658 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1659 return 1;
1660 break;
1661
1662 case MSR_IA32_MCG_CTL:
1663 case MSR_IA32_MCG_STATUS:
1664 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1665 return set_msr_mce(vcpu, msr, data);
1666
1667 /* Performance counters are not protected by a CPUID bit,
1668 * so we should check all of them in the generic path for the sake of
1669 * cross vendor migration.
1670 * Writing a zero into the event select MSRs disables them,
1671 * which we perfectly emulate ;-). Any other value should be at least
1672 * reported, some guests depend on them.
1673 */
1674 case MSR_K7_EVNTSEL0:
1675 case MSR_K7_EVNTSEL1:
1676 case MSR_K7_EVNTSEL2:
1677 case MSR_K7_EVNTSEL3:
1678 if (data != 0)
1679 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1680 "0x%x data 0x%llx\n", msr, data);
1681 break;
1682 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1683 * so we ignore writes to make it happy.
1684 */
1685 case MSR_K7_PERFCTR0:
1686 case MSR_K7_PERFCTR1:
1687 case MSR_K7_PERFCTR2:
1688 case MSR_K7_PERFCTR3:
1689 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1690 "0x%x data 0x%llx\n", msr, data);
1691 break;
1692 case MSR_P6_PERFCTR0:
1693 case MSR_P6_PERFCTR1:
1694 pr = true;
1695 case MSR_P6_EVNTSEL0:
1696 case MSR_P6_EVNTSEL1:
1697 if (kvm_pmu_msr(vcpu, msr))
1698 return kvm_pmu_set_msr(vcpu, msr, data);
1699
1700 if (pr || data != 0)
1701 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1702 "0x%x data 0x%llx\n", msr, data);
1703 break;
1704 case MSR_K7_CLK_CTL:
1705 /*
1706 * Ignore all writes to this no longer documented MSR.
1707 * Writes are only relevant for old K7 processors,
1708 * all pre-dating SVM, but a recommended workaround from
1709 * AMD for these chips. It is possible to speicify the
1710 * affected processor models on the command line, hence
1711 * the need to ignore the workaround.
1712 */
1713 break;
1714 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1715 if (kvm_hv_msr_partition_wide(msr)) {
1716 int r;
1717 mutex_lock(&vcpu->kvm->lock);
1718 r = set_msr_hyperv_pw(vcpu, msr, data);
1719 mutex_unlock(&vcpu->kvm->lock);
1720 return r;
1721 } else
1722 return set_msr_hyperv(vcpu, msr, data);
1723 break;
1724 case MSR_IA32_BBL_CR_CTL3:
1725 /* Drop writes to this legacy MSR -- see rdmsr
1726 * counterpart for further detail.
1727 */
1728 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1729 break;
1730 case MSR_AMD64_OSVW_ID_LENGTH:
1731 if (!guest_cpuid_has_osvw(vcpu))
1732 return 1;
1733 vcpu->arch.osvw.length = data;
1734 break;
1735 case MSR_AMD64_OSVW_STATUS:
1736 if (!guest_cpuid_has_osvw(vcpu))
1737 return 1;
1738 vcpu->arch.osvw.status = data;
1739 break;
1740 default:
1741 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1742 return xen_hvm_config(vcpu, data);
1743 if (kvm_pmu_msr(vcpu, msr))
1744 return kvm_pmu_set_msr(vcpu, msr, data);
1745 if (!ignore_msrs) {
1746 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1747 msr, data);
1748 return 1;
1749 } else {
1750 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1751 msr, data);
1752 break;
1753 }
1754 }
1755 return 0;
1756 }
1757 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1758
1759
1760 /*
1761 * Reads an msr value (of 'msr_index') into 'pdata'.
1762 * Returns 0 on success, non-0 otherwise.
1763 * Assumes vcpu_load() was already called.
1764 */
1765 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1766 {
1767 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1768 }
1769
1770 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1771 {
1772 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1773
1774 if (!msr_mtrr_valid(msr))
1775 return 1;
1776
1777 if (msr == MSR_MTRRdefType)
1778 *pdata = vcpu->arch.mtrr_state.def_type +
1779 (vcpu->arch.mtrr_state.enabled << 10);
1780 else if (msr == MSR_MTRRfix64K_00000)
1781 *pdata = p[0];
1782 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1783 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1784 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1785 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1786 else if (msr == MSR_IA32_CR_PAT)
1787 *pdata = vcpu->arch.pat;
1788 else { /* Variable MTRRs */
1789 int idx, is_mtrr_mask;
1790 u64 *pt;
1791
1792 idx = (msr - 0x200) / 2;
1793 is_mtrr_mask = msr - 0x200 - 2 * idx;
1794 if (!is_mtrr_mask)
1795 pt =
1796 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1797 else
1798 pt =
1799 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1800 *pdata = *pt;
1801 }
1802
1803 return 0;
1804 }
1805
1806 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1807 {
1808 u64 data;
1809 u64 mcg_cap = vcpu->arch.mcg_cap;
1810 unsigned bank_num = mcg_cap & 0xff;
1811
1812 switch (msr) {
1813 case MSR_IA32_P5_MC_ADDR:
1814 case MSR_IA32_P5_MC_TYPE:
1815 data = 0;
1816 break;
1817 case MSR_IA32_MCG_CAP:
1818 data = vcpu->arch.mcg_cap;
1819 break;
1820 case MSR_IA32_MCG_CTL:
1821 if (!(mcg_cap & MCG_CTL_P))
1822 return 1;
1823 data = vcpu->arch.mcg_ctl;
1824 break;
1825 case MSR_IA32_MCG_STATUS:
1826 data = vcpu->arch.mcg_status;
1827 break;
1828 default:
1829 if (msr >= MSR_IA32_MC0_CTL &&
1830 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1831 u32 offset = msr - MSR_IA32_MC0_CTL;
1832 data = vcpu->arch.mce_banks[offset];
1833 break;
1834 }
1835 return 1;
1836 }
1837 *pdata = data;
1838 return 0;
1839 }
1840
1841 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1842 {
1843 u64 data = 0;
1844 struct kvm *kvm = vcpu->kvm;
1845
1846 switch (msr) {
1847 case HV_X64_MSR_GUEST_OS_ID:
1848 data = kvm->arch.hv_guest_os_id;
1849 break;
1850 case HV_X64_MSR_HYPERCALL:
1851 data = kvm->arch.hv_hypercall;
1852 break;
1853 default:
1854 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1855 return 1;
1856 }
1857
1858 *pdata = data;
1859 return 0;
1860 }
1861
1862 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1863 {
1864 u64 data = 0;
1865
1866 switch (msr) {
1867 case HV_X64_MSR_VP_INDEX: {
1868 int r;
1869 struct kvm_vcpu *v;
1870 kvm_for_each_vcpu(r, v, vcpu->kvm)
1871 if (v == vcpu)
1872 data = r;
1873 break;
1874 }
1875 case HV_X64_MSR_EOI:
1876 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1877 case HV_X64_MSR_ICR:
1878 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1879 case HV_X64_MSR_TPR:
1880 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1881 case HV_X64_MSR_APIC_ASSIST_PAGE:
1882 data = vcpu->arch.hv_vapic;
1883 break;
1884 default:
1885 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1886 return 1;
1887 }
1888 *pdata = data;
1889 return 0;
1890 }
1891
1892 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1893 {
1894 u64 data;
1895
1896 switch (msr) {
1897 case MSR_IA32_PLATFORM_ID:
1898 case MSR_IA32_EBL_CR_POWERON:
1899 case MSR_IA32_DEBUGCTLMSR:
1900 case MSR_IA32_LASTBRANCHFROMIP:
1901 case MSR_IA32_LASTBRANCHTOIP:
1902 case MSR_IA32_LASTINTFROMIP:
1903 case MSR_IA32_LASTINTTOIP:
1904 case MSR_K8_SYSCFG:
1905 case MSR_K7_HWCR:
1906 case MSR_VM_HSAVE_PA:
1907 case MSR_K7_EVNTSEL0:
1908 case MSR_K7_PERFCTR0:
1909 case MSR_K8_INT_PENDING_MSG:
1910 case MSR_AMD64_NB_CFG:
1911 case MSR_FAM10H_MMIO_CONF_BASE:
1912 data = 0;
1913 break;
1914 case MSR_P6_PERFCTR0:
1915 case MSR_P6_PERFCTR1:
1916 case MSR_P6_EVNTSEL0:
1917 case MSR_P6_EVNTSEL1:
1918 if (kvm_pmu_msr(vcpu, msr))
1919 return kvm_pmu_get_msr(vcpu, msr, pdata);
1920 data = 0;
1921 break;
1922 case MSR_IA32_UCODE_REV:
1923 data = 0x100000000ULL;
1924 break;
1925 case MSR_MTRRcap:
1926 data = 0x500 | KVM_NR_VAR_MTRR;
1927 break;
1928 case 0x200 ... 0x2ff:
1929 return get_msr_mtrr(vcpu, msr, pdata);
1930 case 0xcd: /* fsb frequency */
1931 data = 3;
1932 break;
1933 /*
1934 * MSR_EBC_FREQUENCY_ID
1935 * Conservative value valid for even the basic CPU models.
1936 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1937 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1938 * and 266MHz for model 3, or 4. Set Core Clock
1939 * Frequency to System Bus Frequency Ratio to 1 (bits
1940 * 31:24) even though these are only valid for CPU
1941 * models > 2, however guests may end up dividing or
1942 * multiplying by zero otherwise.
1943 */
1944 case MSR_EBC_FREQUENCY_ID:
1945 data = 1 << 24;
1946 break;
1947 case MSR_IA32_APICBASE:
1948 data = kvm_get_apic_base(vcpu);
1949 break;
1950 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1951 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1952 break;
1953 case MSR_IA32_TSCDEADLINE:
1954 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1955 break;
1956 case MSR_IA32_MISC_ENABLE:
1957 data = vcpu->arch.ia32_misc_enable_msr;
1958 break;
1959 case MSR_IA32_PERF_STATUS:
1960 /* TSC increment by tick */
1961 data = 1000ULL;
1962 /* CPU multiplier */
1963 data |= (((uint64_t)4ULL) << 40);
1964 break;
1965 case MSR_EFER:
1966 data = vcpu->arch.efer;
1967 break;
1968 case MSR_KVM_WALL_CLOCK:
1969 case MSR_KVM_WALL_CLOCK_NEW:
1970 data = vcpu->kvm->arch.wall_clock;
1971 break;
1972 case MSR_KVM_SYSTEM_TIME:
1973 case MSR_KVM_SYSTEM_TIME_NEW:
1974 data = vcpu->arch.time;
1975 break;
1976 case MSR_KVM_ASYNC_PF_EN:
1977 data = vcpu->arch.apf.msr_val;
1978 break;
1979 case MSR_KVM_STEAL_TIME:
1980 data = vcpu->arch.st.msr_val;
1981 break;
1982 case MSR_IA32_P5_MC_ADDR:
1983 case MSR_IA32_P5_MC_TYPE:
1984 case MSR_IA32_MCG_CAP:
1985 case MSR_IA32_MCG_CTL:
1986 case MSR_IA32_MCG_STATUS:
1987 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1988 return get_msr_mce(vcpu, msr, pdata);
1989 case MSR_K7_CLK_CTL:
1990 /*
1991 * Provide expected ramp-up count for K7. All other
1992 * are set to zero, indicating minimum divisors for
1993 * every field.
1994 *
1995 * This prevents guest kernels on AMD host with CPU
1996 * type 6, model 8 and higher from exploding due to
1997 * the rdmsr failing.
1998 */
1999 data = 0x20000000;
2000 break;
2001 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2002 if (kvm_hv_msr_partition_wide(msr)) {
2003 int r;
2004 mutex_lock(&vcpu->kvm->lock);
2005 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2006 mutex_unlock(&vcpu->kvm->lock);
2007 return r;
2008 } else
2009 return get_msr_hyperv(vcpu, msr, pdata);
2010 break;
2011 case MSR_IA32_BBL_CR_CTL3:
2012 /* This legacy MSR exists but isn't fully documented in current
2013 * silicon. It is however accessed by winxp in very narrow
2014 * scenarios where it sets bit #19, itself documented as
2015 * a "reserved" bit. Best effort attempt to source coherent
2016 * read data here should the balance of the register be
2017 * interpreted by the guest:
2018 *
2019 * L2 cache control register 3: 64GB range, 256KB size,
2020 * enabled, latency 0x1, configured
2021 */
2022 data = 0xbe702111;
2023 break;
2024 case MSR_AMD64_OSVW_ID_LENGTH:
2025 if (!guest_cpuid_has_osvw(vcpu))
2026 return 1;
2027 data = vcpu->arch.osvw.length;
2028 break;
2029 case MSR_AMD64_OSVW_STATUS:
2030 if (!guest_cpuid_has_osvw(vcpu))
2031 return 1;
2032 data = vcpu->arch.osvw.status;
2033 break;
2034 default:
2035 if (kvm_pmu_msr(vcpu, msr))
2036 return kvm_pmu_get_msr(vcpu, msr, pdata);
2037 if (!ignore_msrs) {
2038 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2039 return 1;
2040 } else {
2041 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2042 data = 0;
2043 }
2044 break;
2045 }
2046 *pdata = data;
2047 return 0;
2048 }
2049 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2050
2051 /*
2052 * Read or write a bunch of msrs. All parameters are kernel addresses.
2053 *
2054 * @return number of msrs set successfully.
2055 */
2056 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2057 struct kvm_msr_entry *entries,
2058 int (*do_msr)(struct kvm_vcpu *vcpu,
2059 unsigned index, u64 *data))
2060 {
2061 int i, idx;
2062
2063 idx = srcu_read_lock(&vcpu->kvm->srcu);
2064 for (i = 0; i < msrs->nmsrs; ++i)
2065 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2066 break;
2067 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2068
2069 return i;
2070 }
2071
2072 /*
2073 * Read or write a bunch of msrs. Parameters are user addresses.
2074 *
2075 * @return number of msrs set successfully.
2076 */
2077 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2078 int (*do_msr)(struct kvm_vcpu *vcpu,
2079 unsigned index, u64 *data),
2080 int writeback)
2081 {
2082 struct kvm_msrs msrs;
2083 struct kvm_msr_entry *entries;
2084 int r, n;
2085 unsigned size;
2086
2087 r = -EFAULT;
2088 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2089 goto out;
2090
2091 r = -E2BIG;
2092 if (msrs.nmsrs >= MAX_IO_MSRS)
2093 goto out;
2094
2095 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2096 entries = memdup_user(user_msrs->entries, size);
2097 if (IS_ERR(entries)) {
2098 r = PTR_ERR(entries);
2099 goto out;
2100 }
2101
2102 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2103 if (r < 0)
2104 goto out_free;
2105
2106 r = -EFAULT;
2107 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2108 goto out_free;
2109
2110 r = n;
2111
2112 out_free:
2113 kfree(entries);
2114 out:
2115 return r;
2116 }
2117
2118 int kvm_dev_ioctl_check_extension(long ext)
2119 {
2120 int r;
2121
2122 switch (ext) {
2123 case KVM_CAP_IRQCHIP:
2124 case KVM_CAP_HLT:
2125 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2126 case KVM_CAP_SET_TSS_ADDR:
2127 case KVM_CAP_EXT_CPUID:
2128 case KVM_CAP_CLOCKSOURCE:
2129 case KVM_CAP_PIT:
2130 case KVM_CAP_NOP_IO_DELAY:
2131 case KVM_CAP_MP_STATE:
2132 case KVM_CAP_SYNC_MMU:
2133 case KVM_CAP_USER_NMI:
2134 case KVM_CAP_REINJECT_CONTROL:
2135 case KVM_CAP_IRQ_INJECT_STATUS:
2136 case KVM_CAP_ASSIGN_DEV_IRQ:
2137 case KVM_CAP_IRQFD:
2138 case KVM_CAP_IOEVENTFD:
2139 case KVM_CAP_PIT2:
2140 case KVM_CAP_PIT_STATE2:
2141 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2142 case KVM_CAP_XEN_HVM:
2143 case KVM_CAP_ADJUST_CLOCK:
2144 case KVM_CAP_VCPU_EVENTS:
2145 case KVM_CAP_HYPERV:
2146 case KVM_CAP_HYPERV_VAPIC:
2147 case KVM_CAP_HYPERV_SPIN:
2148 case KVM_CAP_PCI_SEGMENT:
2149 case KVM_CAP_DEBUGREGS:
2150 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2151 case KVM_CAP_XSAVE:
2152 case KVM_CAP_ASYNC_PF:
2153 case KVM_CAP_GET_TSC_KHZ:
2154 case KVM_CAP_PCI_2_3:
2155 case KVM_CAP_KVMCLOCK_CTRL:
2156 r = 1;
2157 break;
2158 case KVM_CAP_COALESCED_MMIO:
2159 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2160 break;
2161 case KVM_CAP_VAPIC:
2162 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2163 break;
2164 case KVM_CAP_NR_VCPUS:
2165 r = KVM_SOFT_MAX_VCPUS;
2166 break;
2167 case KVM_CAP_MAX_VCPUS:
2168 r = KVM_MAX_VCPUS;
2169 break;
2170 case KVM_CAP_NR_MEMSLOTS:
2171 r = KVM_MEMORY_SLOTS;
2172 break;
2173 case KVM_CAP_PV_MMU: /* obsolete */
2174 r = 0;
2175 break;
2176 case KVM_CAP_IOMMU:
2177 r = iommu_present(&pci_bus_type);
2178 break;
2179 case KVM_CAP_MCE:
2180 r = KVM_MAX_MCE_BANKS;
2181 break;
2182 case KVM_CAP_XCRS:
2183 r = cpu_has_xsave;
2184 break;
2185 case KVM_CAP_TSC_CONTROL:
2186 r = kvm_has_tsc_control;
2187 break;
2188 case KVM_CAP_TSC_DEADLINE_TIMER:
2189 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2190 break;
2191 default:
2192 r = 0;
2193 break;
2194 }
2195 return r;
2196
2197 }
2198
2199 long kvm_arch_dev_ioctl(struct file *filp,
2200 unsigned int ioctl, unsigned long arg)
2201 {
2202 void __user *argp = (void __user *)arg;
2203 long r;
2204
2205 switch (ioctl) {
2206 case KVM_GET_MSR_INDEX_LIST: {
2207 struct kvm_msr_list __user *user_msr_list = argp;
2208 struct kvm_msr_list msr_list;
2209 unsigned n;
2210
2211 r = -EFAULT;
2212 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2213 goto out;
2214 n = msr_list.nmsrs;
2215 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2216 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2217 goto out;
2218 r = -E2BIG;
2219 if (n < msr_list.nmsrs)
2220 goto out;
2221 r = -EFAULT;
2222 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2223 num_msrs_to_save * sizeof(u32)))
2224 goto out;
2225 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2226 &emulated_msrs,
2227 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2228 goto out;
2229 r = 0;
2230 break;
2231 }
2232 case KVM_GET_SUPPORTED_CPUID: {
2233 struct kvm_cpuid2 __user *cpuid_arg = argp;
2234 struct kvm_cpuid2 cpuid;
2235
2236 r = -EFAULT;
2237 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2238 goto out;
2239 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2240 cpuid_arg->entries);
2241 if (r)
2242 goto out;
2243
2244 r = -EFAULT;
2245 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2246 goto out;
2247 r = 0;
2248 break;
2249 }
2250 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2251 u64 mce_cap;
2252
2253 mce_cap = KVM_MCE_CAP_SUPPORTED;
2254 r = -EFAULT;
2255 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2256 goto out;
2257 r = 0;
2258 break;
2259 }
2260 default:
2261 r = -EINVAL;
2262 }
2263 out:
2264 return r;
2265 }
2266
2267 static void wbinvd_ipi(void *garbage)
2268 {
2269 wbinvd();
2270 }
2271
2272 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2273 {
2274 return vcpu->kvm->arch.iommu_domain &&
2275 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2276 }
2277
2278 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2279 {
2280 /* Address WBINVD may be executed by guest */
2281 if (need_emulate_wbinvd(vcpu)) {
2282 if (kvm_x86_ops->has_wbinvd_exit())
2283 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2284 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2285 smp_call_function_single(vcpu->cpu,
2286 wbinvd_ipi, NULL, 1);
2287 }
2288
2289 kvm_x86_ops->vcpu_load(vcpu, cpu);
2290
2291 /* Apply any externally detected TSC adjustments (due to suspend) */
2292 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2293 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2294 vcpu->arch.tsc_offset_adjustment = 0;
2295 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2296 }
2297
2298 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2299 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2300 native_read_tsc() - vcpu->arch.last_host_tsc;
2301 if (tsc_delta < 0)
2302 mark_tsc_unstable("KVM discovered backwards TSC");
2303 if (check_tsc_unstable()) {
2304 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2305 vcpu->arch.last_guest_tsc);
2306 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2307 vcpu->arch.tsc_catchup = 1;
2308 }
2309 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2310 if (vcpu->cpu != cpu)
2311 kvm_migrate_timers(vcpu);
2312 vcpu->cpu = cpu;
2313 }
2314
2315 accumulate_steal_time(vcpu);
2316 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2317 }
2318
2319 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2320 {
2321 kvm_x86_ops->vcpu_put(vcpu);
2322 kvm_put_guest_fpu(vcpu);
2323 vcpu->arch.last_host_tsc = native_read_tsc();
2324 }
2325
2326 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2327 struct kvm_lapic_state *s)
2328 {
2329 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2330
2331 return 0;
2332 }
2333
2334 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2335 struct kvm_lapic_state *s)
2336 {
2337 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2338 kvm_apic_post_state_restore(vcpu);
2339 update_cr8_intercept(vcpu);
2340
2341 return 0;
2342 }
2343
2344 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2345 struct kvm_interrupt *irq)
2346 {
2347 if (irq->irq < 0 || irq->irq >= 256)
2348 return -EINVAL;
2349 if (irqchip_in_kernel(vcpu->kvm))
2350 return -ENXIO;
2351
2352 kvm_queue_interrupt(vcpu, irq->irq, false);
2353 kvm_make_request(KVM_REQ_EVENT, vcpu);
2354
2355 return 0;
2356 }
2357
2358 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2359 {
2360 kvm_inject_nmi(vcpu);
2361
2362 return 0;
2363 }
2364
2365 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2366 struct kvm_tpr_access_ctl *tac)
2367 {
2368 if (tac->flags)
2369 return -EINVAL;
2370 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2371 return 0;
2372 }
2373
2374 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2375 u64 mcg_cap)
2376 {
2377 int r;
2378 unsigned bank_num = mcg_cap & 0xff, bank;
2379
2380 r = -EINVAL;
2381 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2382 goto out;
2383 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2384 goto out;
2385 r = 0;
2386 vcpu->arch.mcg_cap = mcg_cap;
2387 /* Init IA32_MCG_CTL to all 1s */
2388 if (mcg_cap & MCG_CTL_P)
2389 vcpu->arch.mcg_ctl = ~(u64)0;
2390 /* Init IA32_MCi_CTL to all 1s */
2391 for (bank = 0; bank < bank_num; bank++)
2392 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2393 out:
2394 return r;
2395 }
2396
2397 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2398 struct kvm_x86_mce *mce)
2399 {
2400 u64 mcg_cap = vcpu->arch.mcg_cap;
2401 unsigned bank_num = mcg_cap & 0xff;
2402 u64 *banks = vcpu->arch.mce_banks;
2403
2404 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2405 return -EINVAL;
2406 /*
2407 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2408 * reporting is disabled
2409 */
2410 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2411 vcpu->arch.mcg_ctl != ~(u64)0)
2412 return 0;
2413 banks += 4 * mce->bank;
2414 /*
2415 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2416 * reporting is disabled for the bank
2417 */
2418 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2419 return 0;
2420 if (mce->status & MCI_STATUS_UC) {
2421 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2422 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2423 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2424 return 0;
2425 }
2426 if (banks[1] & MCI_STATUS_VAL)
2427 mce->status |= MCI_STATUS_OVER;
2428 banks[2] = mce->addr;
2429 banks[3] = mce->misc;
2430 vcpu->arch.mcg_status = mce->mcg_status;
2431 banks[1] = mce->status;
2432 kvm_queue_exception(vcpu, MC_VECTOR);
2433 } else if (!(banks[1] & MCI_STATUS_VAL)
2434 || !(banks[1] & MCI_STATUS_UC)) {
2435 if (banks[1] & MCI_STATUS_VAL)
2436 mce->status |= MCI_STATUS_OVER;
2437 banks[2] = mce->addr;
2438 banks[3] = mce->misc;
2439 banks[1] = mce->status;
2440 } else
2441 banks[1] |= MCI_STATUS_OVER;
2442 return 0;
2443 }
2444
2445 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2446 struct kvm_vcpu_events *events)
2447 {
2448 process_nmi(vcpu);
2449 events->exception.injected =
2450 vcpu->arch.exception.pending &&
2451 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2452 events->exception.nr = vcpu->arch.exception.nr;
2453 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2454 events->exception.pad = 0;
2455 events->exception.error_code = vcpu->arch.exception.error_code;
2456
2457 events->interrupt.injected =
2458 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2459 events->interrupt.nr = vcpu->arch.interrupt.nr;
2460 events->interrupt.soft = 0;
2461 events->interrupt.shadow =
2462 kvm_x86_ops->get_interrupt_shadow(vcpu,
2463 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2464
2465 events->nmi.injected = vcpu->arch.nmi_injected;
2466 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2467 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2468 events->nmi.pad = 0;
2469
2470 events->sipi_vector = vcpu->arch.sipi_vector;
2471
2472 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2473 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2474 | KVM_VCPUEVENT_VALID_SHADOW);
2475 memset(&events->reserved, 0, sizeof(events->reserved));
2476 }
2477
2478 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2479 struct kvm_vcpu_events *events)
2480 {
2481 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2482 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2483 | KVM_VCPUEVENT_VALID_SHADOW))
2484 return -EINVAL;
2485
2486 process_nmi(vcpu);
2487 vcpu->arch.exception.pending = events->exception.injected;
2488 vcpu->arch.exception.nr = events->exception.nr;
2489 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2490 vcpu->arch.exception.error_code = events->exception.error_code;
2491
2492 vcpu->arch.interrupt.pending = events->interrupt.injected;
2493 vcpu->arch.interrupt.nr = events->interrupt.nr;
2494 vcpu->arch.interrupt.soft = events->interrupt.soft;
2495 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2496 kvm_x86_ops->set_interrupt_shadow(vcpu,
2497 events->interrupt.shadow);
2498
2499 vcpu->arch.nmi_injected = events->nmi.injected;
2500 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2501 vcpu->arch.nmi_pending = events->nmi.pending;
2502 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2503
2504 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2505 vcpu->arch.sipi_vector = events->sipi_vector;
2506
2507 kvm_make_request(KVM_REQ_EVENT, vcpu);
2508
2509 return 0;
2510 }
2511
2512 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2513 struct kvm_debugregs *dbgregs)
2514 {
2515 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2516 dbgregs->dr6 = vcpu->arch.dr6;
2517 dbgregs->dr7 = vcpu->arch.dr7;
2518 dbgregs->flags = 0;
2519 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2520 }
2521
2522 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2523 struct kvm_debugregs *dbgregs)
2524 {
2525 if (dbgregs->flags)
2526 return -EINVAL;
2527
2528 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2529 vcpu->arch.dr6 = dbgregs->dr6;
2530 vcpu->arch.dr7 = dbgregs->dr7;
2531
2532 return 0;
2533 }
2534
2535 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2536 struct kvm_xsave *guest_xsave)
2537 {
2538 if (cpu_has_xsave)
2539 memcpy(guest_xsave->region,
2540 &vcpu->arch.guest_fpu.state->xsave,
2541 xstate_size);
2542 else {
2543 memcpy(guest_xsave->region,
2544 &vcpu->arch.guest_fpu.state->fxsave,
2545 sizeof(struct i387_fxsave_struct));
2546 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2547 XSTATE_FPSSE;
2548 }
2549 }
2550
2551 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2552 struct kvm_xsave *guest_xsave)
2553 {
2554 u64 xstate_bv =
2555 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2556
2557 if (cpu_has_xsave)
2558 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2559 guest_xsave->region, xstate_size);
2560 else {
2561 if (xstate_bv & ~XSTATE_FPSSE)
2562 return -EINVAL;
2563 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2564 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2565 }
2566 return 0;
2567 }
2568
2569 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2570 struct kvm_xcrs *guest_xcrs)
2571 {
2572 if (!cpu_has_xsave) {
2573 guest_xcrs->nr_xcrs = 0;
2574 return;
2575 }
2576
2577 guest_xcrs->nr_xcrs = 1;
2578 guest_xcrs->flags = 0;
2579 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2580 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2581 }
2582
2583 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2584 struct kvm_xcrs *guest_xcrs)
2585 {
2586 int i, r = 0;
2587
2588 if (!cpu_has_xsave)
2589 return -EINVAL;
2590
2591 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2592 return -EINVAL;
2593
2594 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2595 /* Only support XCR0 currently */
2596 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2597 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2598 guest_xcrs->xcrs[0].value);
2599 break;
2600 }
2601 if (r)
2602 r = -EINVAL;
2603 return r;
2604 }
2605
2606 /*
2607 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2608 * stopped by the hypervisor. This function will be called from the host only.
2609 * EINVAL is returned when the host attempts to set the flag for a guest that
2610 * does not support pv clocks.
2611 */
2612 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2613 {
2614 struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2615 if (!vcpu->arch.time_page)
2616 return -EINVAL;
2617 src->flags |= PVCLOCK_GUEST_STOPPED;
2618 mark_page_dirty(vcpu->kvm, vcpu->arch.time >> PAGE_SHIFT);
2619 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2620 return 0;
2621 }
2622
2623 long kvm_arch_vcpu_ioctl(struct file *filp,
2624 unsigned int ioctl, unsigned long arg)
2625 {
2626 struct kvm_vcpu *vcpu = filp->private_data;
2627 void __user *argp = (void __user *)arg;
2628 int r;
2629 union {
2630 struct kvm_lapic_state *lapic;
2631 struct kvm_xsave *xsave;
2632 struct kvm_xcrs *xcrs;
2633 void *buffer;
2634 } u;
2635
2636 u.buffer = NULL;
2637 switch (ioctl) {
2638 case KVM_GET_LAPIC: {
2639 r = -EINVAL;
2640 if (!vcpu->arch.apic)
2641 goto out;
2642 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2643
2644 r = -ENOMEM;
2645 if (!u.lapic)
2646 goto out;
2647 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2648 if (r)
2649 goto out;
2650 r = -EFAULT;
2651 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2652 goto out;
2653 r = 0;
2654 break;
2655 }
2656 case KVM_SET_LAPIC: {
2657 r = -EINVAL;
2658 if (!vcpu->arch.apic)
2659 goto out;
2660 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2661 if (IS_ERR(u.lapic)) {
2662 r = PTR_ERR(u.lapic);
2663 goto out;
2664 }
2665
2666 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2667 if (r)
2668 goto out;
2669 r = 0;
2670 break;
2671 }
2672 case KVM_INTERRUPT: {
2673 struct kvm_interrupt irq;
2674
2675 r = -EFAULT;
2676 if (copy_from_user(&irq, argp, sizeof irq))
2677 goto out;
2678 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2679 if (r)
2680 goto out;
2681 r = 0;
2682 break;
2683 }
2684 case KVM_NMI: {
2685 r = kvm_vcpu_ioctl_nmi(vcpu);
2686 if (r)
2687 goto out;
2688 r = 0;
2689 break;
2690 }
2691 case KVM_SET_CPUID: {
2692 struct kvm_cpuid __user *cpuid_arg = argp;
2693 struct kvm_cpuid cpuid;
2694
2695 r = -EFAULT;
2696 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2697 goto out;
2698 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2699 if (r)
2700 goto out;
2701 break;
2702 }
2703 case KVM_SET_CPUID2: {
2704 struct kvm_cpuid2 __user *cpuid_arg = argp;
2705 struct kvm_cpuid2 cpuid;
2706
2707 r = -EFAULT;
2708 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2709 goto out;
2710 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2711 cpuid_arg->entries);
2712 if (r)
2713 goto out;
2714 break;
2715 }
2716 case KVM_GET_CPUID2: {
2717 struct kvm_cpuid2 __user *cpuid_arg = argp;
2718 struct kvm_cpuid2 cpuid;
2719
2720 r = -EFAULT;
2721 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2722 goto out;
2723 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2724 cpuid_arg->entries);
2725 if (r)
2726 goto out;
2727 r = -EFAULT;
2728 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2729 goto out;
2730 r = 0;
2731 break;
2732 }
2733 case KVM_GET_MSRS:
2734 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2735 break;
2736 case KVM_SET_MSRS:
2737 r = msr_io(vcpu, argp, do_set_msr, 0);
2738 break;
2739 case KVM_TPR_ACCESS_REPORTING: {
2740 struct kvm_tpr_access_ctl tac;
2741
2742 r = -EFAULT;
2743 if (copy_from_user(&tac, argp, sizeof tac))
2744 goto out;
2745 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2746 if (r)
2747 goto out;
2748 r = -EFAULT;
2749 if (copy_to_user(argp, &tac, sizeof tac))
2750 goto out;
2751 r = 0;
2752 break;
2753 };
2754 case KVM_SET_VAPIC_ADDR: {
2755 struct kvm_vapic_addr va;
2756
2757 r = -EINVAL;
2758 if (!irqchip_in_kernel(vcpu->kvm))
2759 goto out;
2760 r = -EFAULT;
2761 if (copy_from_user(&va, argp, sizeof va))
2762 goto out;
2763 r = 0;
2764 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2765 break;
2766 }
2767 case KVM_X86_SETUP_MCE: {
2768 u64 mcg_cap;
2769
2770 r = -EFAULT;
2771 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2772 goto out;
2773 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2774 break;
2775 }
2776 case KVM_X86_SET_MCE: {
2777 struct kvm_x86_mce mce;
2778
2779 r = -EFAULT;
2780 if (copy_from_user(&mce, argp, sizeof mce))
2781 goto out;
2782 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2783 break;
2784 }
2785 case KVM_GET_VCPU_EVENTS: {
2786 struct kvm_vcpu_events events;
2787
2788 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2789
2790 r = -EFAULT;
2791 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2792 break;
2793 r = 0;
2794 break;
2795 }
2796 case KVM_SET_VCPU_EVENTS: {
2797 struct kvm_vcpu_events events;
2798
2799 r = -EFAULT;
2800 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2801 break;
2802
2803 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2804 break;
2805 }
2806 case KVM_GET_DEBUGREGS: {
2807 struct kvm_debugregs dbgregs;
2808
2809 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2810
2811 r = -EFAULT;
2812 if (copy_to_user(argp, &dbgregs,
2813 sizeof(struct kvm_debugregs)))
2814 break;
2815 r = 0;
2816 break;
2817 }
2818 case KVM_SET_DEBUGREGS: {
2819 struct kvm_debugregs dbgregs;
2820
2821 r = -EFAULT;
2822 if (copy_from_user(&dbgregs, argp,
2823 sizeof(struct kvm_debugregs)))
2824 break;
2825
2826 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2827 break;
2828 }
2829 case KVM_GET_XSAVE: {
2830 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2831 r = -ENOMEM;
2832 if (!u.xsave)
2833 break;
2834
2835 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2836
2837 r = -EFAULT;
2838 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2839 break;
2840 r = 0;
2841 break;
2842 }
2843 case KVM_SET_XSAVE: {
2844 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2845 if (IS_ERR(u.xsave)) {
2846 r = PTR_ERR(u.xsave);
2847 goto out;
2848 }
2849
2850 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2851 break;
2852 }
2853 case KVM_GET_XCRS: {
2854 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2855 r = -ENOMEM;
2856 if (!u.xcrs)
2857 break;
2858
2859 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2860
2861 r = -EFAULT;
2862 if (copy_to_user(argp, u.xcrs,
2863 sizeof(struct kvm_xcrs)))
2864 break;
2865 r = 0;
2866 break;
2867 }
2868 case KVM_SET_XCRS: {
2869 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2870 if (IS_ERR(u.xcrs)) {
2871 r = PTR_ERR(u.xcrs);
2872 goto out;
2873 }
2874
2875 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2876 break;
2877 }
2878 case KVM_SET_TSC_KHZ: {
2879 u32 user_tsc_khz;
2880
2881 r = -EINVAL;
2882 user_tsc_khz = (u32)arg;
2883
2884 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2885 goto out;
2886
2887 if (user_tsc_khz == 0)
2888 user_tsc_khz = tsc_khz;
2889
2890 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2891
2892 r = 0;
2893 goto out;
2894 }
2895 case KVM_GET_TSC_KHZ: {
2896 r = vcpu->arch.virtual_tsc_khz;
2897 goto out;
2898 }
2899 case KVM_KVMCLOCK_CTRL: {
2900 r = kvm_set_guest_paused(vcpu);
2901 goto out;
2902 }
2903 default:
2904 r = -EINVAL;
2905 }
2906 out:
2907 kfree(u.buffer);
2908 return r;
2909 }
2910
2911 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2912 {
2913 return VM_FAULT_SIGBUS;
2914 }
2915
2916 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2917 {
2918 int ret;
2919
2920 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2921 return -1;
2922 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2923 return ret;
2924 }
2925
2926 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2927 u64 ident_addr)
2928 {
2929 kvm->arch.ept_identity_map_addr = ident_addr;
2930 return 0;
2931 }
2932
2933 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2934 u32 kvm_nr_mmu_pages)
2935 {
2936 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2937 return -EINVAL;
2938
2939 mutex_lock(&kvm->slots_lock);
2940 spin_lock(&kvm->mmu_lock);
2941
2942 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2943 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2944
2945 spin_unlock(&kvm->mmu_lock);
2946 mutex_unlock(&kvm->slots_lock);
2947 return 0;
2948 }
2949
2950 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2951 {
2952 return kvm->arch.n_max_mmu_pages;
2953 }
2954
2955 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2956 {
2957 int r;
2958
2959 r = 0;
2960 switch (chip->chip_id) {
2961 case KVM_IRQCHIP_PIC_MASTER:
2962 memcpy(&chip->chip.pic,
2963 &pic_irqchip(kvm)->pics[0],
2964 sizeof(struct kvm_pic_state));
2965 break;
2966 case KVM_IRQCHIP_PIC_SLAVE:
2967 memcpy(&chip->chip.pic,
2968 &pic_irqchip(kvm)->pics[1],
2969 sizeof(struct kvm_pic_state));
2970 break;
2971 case KVM_IRQCHIP_IOAPIC:
2972 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2973 break;
2974 default:
2975 r = -EINVAL;
2976 break;
2977 }
2978 return r;
2979 }
2980
2981 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2982 {
2983 int r;
2984
2985 r = 0;
2986 switch (chip->chip_id) {
2987 case KVM_IRQCHIP_PIC_MASTER:
2988 spin_lock(&pic_irqchip(kvm)->lock);
2989 memcpy(&pic_irqchip(kvm)->pics[0],
2990 &chip->chip.pic,
2991 sizeof(struct kvm_pic_state));
2992 spin_unlock(&pic_irqchip(kvm)->lock);
2993 break;
2994 case KVM_IRQCHIP_PIC_SLAVE:
2995 spin_lock(&pic_irqchip(kvm)->lock);
2996 memcpy(&pic_irqchip(kvm)->pics[1],
2997 &chip->chip.pic,
2998 sizeof(struct kvm_pic_state));
2999 spin_unlock(&pic_irqchip(kvm)->lock);
3000 break;
3001 case KVM_IRQCHIP_IOAPIC:
3002 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3003 break;
3004 default:
3005 r = -EINVAL;
3006 break;
3007 }
3008 kvm_pic_update_irq(pic_irqchip(kvm));
3009 return r;
3010 }
3011
3012 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3013 {
3014 int r = 0;
3015
3016 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3017 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3018 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3019 return r;
3020 }
3021
3022 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3023 {
3024 int r = 0;
3025
3026 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3027 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3028 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3029 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3030 return r;
3031 }
3032
3033 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3034 {
3035 int r = 0;
3036
3037 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3038 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3039 sizeof(ps->channels));
3040 ps->flags = kvm->arch.vpit->pit_state.flags;
3041 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3042 memset(&ps->reserved, 0, sizeof(ps->reserved));
3043 return r;
3044 }
3045
3046 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3047 {
3048 int r = 0, start = 0;
3049 u32 prev_legacy, cur_legacy;
3050 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3051 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3052 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3053 if (!prev_legacy && cur_legacy)
3054 start = 1;
3055 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3056 sizeof(kvm->arch.vpit->pit_state.channels));
3057 kvm->arch.vpit->pit_state.flags = ps->flags;
3058 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3059 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3060 return r;
3061 }
3062
3063 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3064 struct kvm_reinject_control *control)
3065 {
3066 if (!kvm->arch.vpit)
3067 return -ENXIO;
3068 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3069 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3070 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3071 return 0;
3072 }
3073
3074 /**
3075 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3076 * @kvm: kvm instance
3077 * @log: slot id and address to which we copy the log
3078 *
3079 * We need to keep it in mind that VCPU threads can write to the bitmap
3080 * concurrently. So, to avoid losing data, we keep the following order for
3081 * each bit:
3082 *
3083 * 1. Take a snapshot of the bit and clear it if needed.
3084 * 2. Write protect the corresponding page.
3085 * 3. Flush TLB's if needed.
3086 * 4. Copy the snapshot to the userspace.
3087 *
3088 * Between 2 and 3, the guest may write to the page using the remaining TLB
3089 * entry. This is not a problem because the page will be reported dirty at
3090 * step 4 using the snapshot taken before and step 3 ensures that successive
3091 * writes will be logged for the next call.
3092 */
3093 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3094 {
3095 int r;
3096 struct kvm_memory_slot *memslot;
3097 unsigned long n, i;
3098 unsigned long *dirty_bitmap;
3099 unsigned long *dirty_bitmap_buffer;
3100 bool is_dirty = false;
3101
3102 mutex_lock(&kvm->slots_lock);
3103
3104 r = -EINVAL;
3105 if (log->slot >= KVM_MEMORY_SLOTS)
3106 goto out;
3107
3108 memslot = id_to_memslot(kvm->memslots, log->slot);
3109
3110 dirty_bitmap = memslot->dirty_bitmap;
3111 r = -ENOENT;
3112 if (!dirty_bitmap)
3113 goto out;
3114
3115 n = kvm_dirty_bitmap_bytes(memslot);
3116
3117 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3118 memset(dirty_bitmap_buffer, 0, n);
3119
3120 spin_lock(&kvm->mmu_lock);
3121
3122 for (i = 0; i < n / sizeof(long); i++) {
3123 unsigned long mask;
3124 gfn_t offset;
3125
3126 if (!dirty_bitmap[i])
3127 continue;
3128
3129 is_dirty = true;
3130
3131 mask = xchg(&dirty_bitmap[i], 0);
3132 dirty_bitmap_buffer[i] = mask;
3133
3134 offset = i * BITS_PER_LONG;
3135 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3136 }
3137 if (is_dirty)
3138 kvm_flush_remote_tlbs(kvm);
3139
3140 spin_unlock(&kvm->mmu_lock);
3141
3142 r = -EFAULT;
3143 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3144 goto out;
3145
3146 r = 0;
3147 out:
3148 mutex_unlock(&kvm->slots_lock);
3149 return r;
3150 }
3151
3152 long kvm_arch_vm_ioctl(struct file *filp,
3153 unsigned int ioctl, unsigned long arg)
3154 {
3155 struct kvm *kvm = filp->private_data;
3156 void __user *argp = (void __user *)arg;
3157 int r = -ENOTTY;
3158 /*
3159 * This union makes it completely explicit to gcc-3.x
3160 * that these two variables' stack usage should be
3161 * combined, not added together.
3162 */
3163 union {
3164 struct kvm_pit_state ps;
3165 struct kvm_pit_state2 ps2;
3166 struct kvm_pit_config pit_config;
3167 } u;
3168
3169 switch (ioctl) {
3170 case KVM_SET_TSS_ADDR:
3171 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3172 if (r < 0)
3173 goto out;
3174 break;
3175 case KVM_SET_IDENTITY_MAP_ADDR: {
3176 u64 ident_addr;
3177
3178 r = -EFAULT;
3179 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3180 goto out;
3181 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3182 if (r < 0)
3183 goto out;
3184 break;
3185 }
3186 case KVM_SET_NR_MMU_PAGES:
3187 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3188 if (r)
3189 goto out;
3190 break;
3191 case KVM_GET_NR_MMU_PAGES:
3192 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3193 break;
3194 case KVM_CREATE_IRQCHIP: {
3195 struct kvm_pic *vpic;
3196
3197 mutex_lock(&kvm->lock);
3198 r = -EEXIST;
3199 if (kvm->arch.vpic)
3200 goto create_irqchip_unlock;
3201 r = -EINVAL;
3202 if (atomic_read(&kvm->online_vcpus))
3203 goto create_irqchip_unlock;
3204 r = -ENOMEM;
3205 vpic = kvm_create_pic(kvm);
3206 if (vpic) {
3207 r = kvm_ioapic_init(kvm);
3208 if (r) {
3209 mutex_lock(&kvm->slots_lock);
3210 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3211 &vpic->dev_master);
3212 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3213 &vpic->dev_slave);
3214 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3215 &vpic->dev_eclr);
3216 mutex_unlock(&kvm->slots_lock);
3217 kfree(vpic);
3218 goto create_irqchip_unlock;
3219 }
3220 } else
3221 goto create_irqchip_unlock;
3222 smp_wmb();
3223 kvm->arch.vpic = vpic;
3224 smp_wmb();
3225 r = kvm_setup_default_irq_routing(kvm);
3226 if (r) {
3227 mutex_lock(&kvm->slots_lock);
3228 mutex_lock(&kvm->irq_lock);
3229 kvm_ioapic_destroy(kvm);
3230 kvm_destroy_pic(kvm);
3231 mutex_unlock(&kvm->irq_lock);
3232 mutex_unlock(&kvm->slots_lock);
3233 }
3234 create_irqchip_unlock:
3235 mutex_unlock(&kvm->lock);
3236 break;
3237 }
3238 case KVM_CREATE_PIT:
3239 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3240 goto create_pit;
3241 case KVM_CREATE_PIT2:
3242 r = -EFAULT;
3243 if (copy_from_user(&u.pit_config, argp,
3244 sizeof(struct kvm_pit_config)))
3245 goto out;
3246 create_pit:
3247 mutex_lock(&kvm->slots_lock);
3248 r = -EEXIST;
3249 if (kvm->arch.vpit)
3250 goto create_pit_unlock;
3251 r = -ENOMEM;
3252 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3253 if (kvm->arch.vpit)
3254 r = 0;
3255 create_pit_unlock:
3256 mutex_unlock(&kvm->slots_lock);
3257 break;
3258 case KVM_IRQ_LINE_STATUS:
3259 case KVM_IRQ_LINE: {
3260 struct kvm_irq_level irq_event;
3261
3262 r = -EFAULT;
3263 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3264 goto out;
3265 r = -ENXIO;
3266 if (irqchip_in_kernel(kvm)) {
3267 __s32 status;
3268 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3269 irq_event.irq, irq_event.level);
3270 if (ioctl == KVM_IRQ_LINE_STATUS) {
3271 r = -EFAULT;
3272 irq_event.status = status;
3273 if (copy_to_user(argp, &irq_event,
3274 sizeof irq_event))
3275 goto out;
3276 }
3277 r = 0;
3278 }
3279 break;
3280 }
3281 case KVM_GET_IRQCHIP: {
3282 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3283 struct kvm_irqchip *chip;
3284
3285 chip = memdup_user(argp, sizeof(*chip));
3286 if (IS_ERR(chip)) {
3287 r = PTR_ERR(chip);
3288 goto out;
3289 }
3290
3291 r = -ENXIO;
3292 if (!irqchip_in_kernel(kvm))
3293 goto get_irqchip_out;
3294 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3295 if (r)
3296 goto get_irqchip_out;
3297 r = -EFAULT;
3298 if (copy_to_user(argp, chip, sizeof *chip))
3299 goto get_irqchip_out;
3300 r = 0;
3301 get_irqchip_out:
3302 kfree(chip);
3303 if (r)
3304 goto out;
3305 break;
3306 }
3307 case KVM_SET_IRQCHIP: {
3308 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3309 struct kvm_irqchip *chip;
3310
3311 chip = memdup_user(argp, sizeof(*chip));
3312 if (IS_ERR(chip)) {
3313 r = PTR_ERR(chip);
3314 goto out;
3315 }
3316
3317 r = -ENXIO;
3318 if (!irqchip_in_kernel(kvm))
3319 goto set_irqchip_out;
3320 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3321 if (r)
3322 goto set_irqchip_out;
3323 r = 0;
3324 set_irqchip_out:
3325 kfree(chip);
3326 if (r)
3327 goto out;
3328 break;
3329 }
3330 case KVM_GET_PIT: {
3331 r = -EFAULT;
3332 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3333 goto out;
3334 r = -ENXIO;
3335 if (!kvm->arch.vpit)
3336 goto out;
3337 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3338 if (r)
3339 goto out;
3340 r = -EFAULT;
3341 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3342 goto out;
3343 r = 0;
3344 break;
3345 }
3346 case KVM_SET_PIT: {
3347 r = -EFAULT;
3348 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3349 goto out;
3350 r = -ENXIO;
3351 if (!kvm->arch.vpit)
3352 goto out;
3353 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3354 if (r)
3355 goto out;
3356 r = 0;
3357 break;
3358 }
3359 case KVM_GET_PIT2: {
3360 r = -ENXIO;
3361 if (!kvm->arch.vpit)
3362 goto out;
3363 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3364 if (r)
3365 goto out;
3366 r = -EFAULT;
3367 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3368 goto out;
3369 r = 0;
3370 break;
3371 }
3372 case KVM_SET_PIT2: {
3373 r = -EFAULT;
3374 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3375 goto out;
3376 r = -ENXIO;
3377 if (!kvm->arch.vpit)
3378 goto out;
3379 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3380 if (r)
3381 goto out;
3382 r = 0;
3383 break;
3384 }
3385 case KVM_REINJECT_CONTROL: {
3386 struct kvm_reinject_control control;
3387 r = -EFAULT;
3388 if (copy_from_user(&control, argp, sizeof(control)))
3389 goto out;
3390 r = kvm_vm_ioctl_reinject(kvm, &control);
3391 if (r)
3392 goto out;
3393 r = 0;
3394 break;
3395 }
3396 case KVM_XEN_HVM_CONFIG: {
3397 r = -EFAULT;
3398 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3399 sizeof(struct kvm_xen_hvm_config)))
3400 goto out;
3401 r = -EINVAL;
3402 if (kvm->arch.xen_hvm_config.flags)
3403 goto out;
3404 r = 0;
3405 break;
3406 }
3407 case KVM_SET_CLOCK: {
3408 struct kvm_clock_data user_ns;
3409 u64 now_ns;
3410 s64 delta;
3411
3412 r = -EFAULT;
3413 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3414 goto out;
3415
3416 r = -EINVAL;
3417 if (user_ns.flags)
3418 goto out;
3419
3420 r = 0;
3421 local_irq_disable();
3422 now_ns = get_kernel_ns();
3423 delta = user_ns.clock - now_ns;
3424 local_irq_enable();
3425 kvm->arch.kvmclock_offset = delta;
3426 break;
3427 }
3428 case KVM_GET_CLOCK: {
3429 struct kvm_clock_data user_ns;
3430 u64 now_ns;
3431
3432 local_irq_disable();
3433 now_ns = get_kernel_ns();
3434 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3435 local_irq_enable();
3436 user_ns.flags = 0;
3437 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3438
3439 r = -EFAULT;
3440 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3441 goto out;
3442 r = 0;
3443 break;
3444 }
3445
3446 default:
3447 ;
3448 }
3449 out:
3450 return r;
3451 }
3452
3453 static void kvm_init_msr_list(void)
3454 {
3455 u32 dummy[2];
3456 unsigned i, j;
3457
3458 /* skip the first msrs in the list. KVM-specific */
3459 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3460 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3461 continue;
3462 if (j < i)
3463 msrs_to_save[j] = msrs_to_save[i];
3464 j++;
3465 }
3466 num_msrs_to_save = j;
3467 }
3468
3469 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3470 const void *v)
3471 {
3472 int handled = 0;
3473 int n;
3474
3475 do {
3476 n = min(len, 8);
3477 if (!(vcpu->arch.apic &&
3478 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3479 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3480 break;
3481 handled += n;
3482 addr += n;
3483 len -= n;
3484 v += n;
3485 } while (len);
3486
3487 return handled;
3488 }
3489
3490 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3491 {
3492 int handled = 0;
3493 int n;
3494
3495 do {
3496 n = min(len, 8);
3497 if (!(vcpu->arch.apic &&
3498 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3499 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3500 break;
3501 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3502 handled += n;
3503 addr += n;
3504 len -= n;
3505 v += n;
3506 } while (len);
3507
3508 return handled;
3509 }
3510
3511 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3512 struct kvm_segment *var, int seg)
3513 {
3514 kvm_x86_ops->set_segment(vcpu, var, seg);
3515 }
3516
3517 void kvm_get_segment(struct kvm_vcpu *vcpu,
3518 struct kvm_segment *var, int seg)
3519 {
3520 kvm_x86_ops->get_segment(vcpu, var, seg);
3521 }
3522
3523 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3524 {
3525 gpa_t t_gpa;
3526 struct x86_exception exception;
3527
3528 BUG_ON(!mmu_is_nested(vcpu));
3529
3530 /* NPT walks are always user-walks */
3531 access |= PFERR_USER_MASK;
3532 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3533
3534 return t_gpa;
3535 }
3536
3537 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3538 struct x86_exception *exception)
3539 {
3540 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3541 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3542 }
3543
3544 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3545 struct x86_exception *exception)
3546 {
3547 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3548 access |= PFERR_FETCH_MASK;
3549 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3550 }
3551
3552 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3553 struct x86_exception *exception)
3554 {
3555 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3556 access |= PFERR_WRITE_MASK;
3557 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3558 }
3559
3560 /* uses this to access any guest's mapped memory without checking CPL */
3561 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3562 struct x86_exception *exception)
3563 {
3564 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3565 }
3566
3567 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3568 struct kvm_vcpu *vcpu, u32 access,
3569 struct x86_exception *exception)
3570 {
3571 void *data = val;
3572 int r = X86EMUL_CONTINUE;
3573
3574 while (bytes) {
3575 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3576 exception);
3577 unsigned offset = addr & (PAGE_SIZE-1);
3578 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3579 int ret;
3580
3581 if (gpa == UNMAPPED_GVA)
3582 return X86EMUL_PROPAGATE_FAULT;
3583 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3584 if (ret < 0) {
3585 r = X86EMUL_IO_NEEDED;
3586 goto out;
3587 }
3588
3589 bytes -= toread;
3590 data += toread;
3591 addr += toread;
3592 }
3593 out:
3594 return r;
3595 }
3596
3597 /* used for instruction fetching */
3598 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3599 gva_t addr, void *val, unsigned int bytes,
3600 struct x86_exception *exception)
3601 {
3602 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3603 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3604
3605 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3606 access | PFERR_FETCH_MASK,
3607 exception);
3608 }
3609
3610 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3611 gva_t addr, void *val, unsigned int bytes,
3612 struct x86_exception *exception)
3613 {
3614 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3615 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3616
3617 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3618 exception);
3619 }
3620 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3621
3622 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3623 gva_t addr, void *val, unsigned int bytes,
3624 struct x86_exception *exception)
3625 {
3626 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3627 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3628 }
3629
3630 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3631 gva_t addr, void *val,
3632 unsigned int bytes,
3633 struct x86_exception *exception)
3634 {
3635 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3636 void *data = val;
3637 int r = X86EMUL_CONTINUE;
3638
3639 while (bytes) {
3640 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3641 PFERR_WRITE_MASK,
3642 exception);
3643 unsigned offset = addr & (PAGE_SIZE-1);
3644 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3645 int ret;
3646
3647 if (gpa == UNMAPPED_GVA)
3648 return X86EMUL_PROPAGATE_FAULT;
3649 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3650 if (ret < 0) {
3651 r = X86EMUL_IO_NEEDED;
3652 goto out;
3653 }
3654
3655 bytes -= towrite;
3656 data += towrite;
3657 addr += towrite;
3658 }
3659 out:
3660 return r;
3661 }
3662 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3663
3664 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3665 gpa_t *gpa, struct x86_exception *exception,
3666 bool write)
3667 {
3668 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3669
3670 if (vcpu_match_mmio_gva(vcpu, gva) &&
3671 check_write_user_access(vcpu, write, access,
3672 vcpu->arch.access)) {
3673 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3674 (gva & (PAGE_SIZE - 1));
3675 trace_vcpu_match_mmio(gva, *gpa, write, false);
3676 return 1;
3677 }
3678
3679 if (write)
3680 access |= PFERR_WRITE_MASK;
3681
3682 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3683
3684 if (*gpa == UNMAPPED_GVA)
3685 return -1;
3686
3687 /* For APIC access vmexit */
3688 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3689 return 1;
3690
3691 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3692 trace_vcpu_match_mmio(gva, *gpa, write, true);
3693 return 1;
3694 }
3695
3696 return 0;
3697 }
3698
3699 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3700 const void *val, int bytes)
3701 {
3702 int ret;
3703
3704 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3705 if (ret < 0)
3706 return 0;
3707 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3708 return 1;
3709 }
3710
3711 struct read_write_emulator_ops {
3712 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3713 int bytes);
3714 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3715 void *val, int bytes);
3716 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3717 int bytes, void *val);
3718 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3719 void *val, int bytes);
3720 bool write;
3721 };
3722
3723 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3724 {
3725 if (vcpu->mmio_read_completed) {
3726 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3727 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
3728 vcpu->mmio_read_completed = 0;
3729 return 1;
3730 }
3731
3732 return 0;
3733 }
3734
3735 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3736 void *val, int bytes)
3737 {
3738 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3739 }
3740
3741 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3742 void *val, int bytes)
3743 {
3744 return emulator_write_phys(vcpu, gpa, val, bytes);
3745 }
3746
3747 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3748 {
3749 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3750 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3751 }
3752
3753 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3754 void *val, int bytes)
3755 {
3756 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3757 return X86EMUL_IO_NEEDED;
3758 }
3759
3760 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3761 void *val, int bytes)
3762 {
3763 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3764
3765 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
3766 return X86EMUL_CONTINUE;
3767 }
3768
3769 static struct read_write_emulator_ops read_emultor = {
3770 .read_write_prepare = read_prepare,
3771 .read_write_emulate = read_emulate,
3772 .read_write_mmio = vcpu_mmio_read,
3773 .read_write_exit_mmio = read_exit_mmio,
3774 };
3775
3776 static struct read_write_emulator_ops write_emultor = {
3777 .read_write_emulate = write_emulate,
3778 .read_write_mmio = write_mmio,
3779 .read_write_exit_mmio = write_exit_mmio,
3780 .write = true,
3781 };
3782
3783 static int emulator_read_write_onepage(unsigned long addr, void *val,
3784 unsigned int bytes,
3785 struct x86_exception *exception,
3786 struct kvm_vcpu *vcpu,
3787 struct read_write_emulator_ops *ops)
3788 {
3789 gpa_t gpa;
3790 int handled, ret;
3791 bool write = ops->write;
3792 struct kvm_mmio_fragment *frag;
3793
3794 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3795
3796 if (ret < 0)
3797 return X86EMUL_PROPAGATE_FAULT;
3798
3799 /* For APIC access vmexit */
3800 if (ret)
3801 goto mmio;
3802
3803 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3804 return X86EMUL_CONTINUE;
3805
3806 mmio:
3807 /*
3808 * Is this MMIO handled locally?
3809 */
3810 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3811 if (handled == bytes)
3812 return X86EMUL_CONTINUE;
3813
3814 gpa += handled;
3815 bytes -= handled;
3816 val += handled;
3817
3818 while (bytes) {
3819 unsigned now = min(bytes, 8U);
3820
3821 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3822 frag->gpa = gpa;
3823 frag->data = val;
3824 frag->len = now;
3825
3826 gpa += now;
3827 val += now;
3828 bytes -= now;
3829 }
3830 return X86EMUL_CONTINUE;
3831 }
3832
3833 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3834 void *val, unsigned int bytes,
3835 struct x86_exception *exception,
3836 struct read_write_emulator_ops *ops)
3837 {
3838 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3839 gpa_t gpa;
3840 int rc;
3841
3842 if (ops->read_write_prepare &&
3843 ops->read_write_prepare(vcpu, val, bytes))
3844 return X86EMUL_CONTINUE;
3845
3846 vcpu->mmio_nr_fragments = 0;
3847
3848 /* Crossing a page boundary? */
3849 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3850 int now;
3851
3852 now = -addr & ~PAGE_MASK;
3853 rc = emulator_read_write_onepage(addr, val, now, exception,
3854 vcpu, ops);
3855
3856 if (rc != X86EMUL_CONTINUE)
3857 return rc;
3858 addr += now;
3859 val += now;
3860 bytes -= now;
3861 }
3862
3863 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3864 vcpu, ops);
3865 if (rc != X86EMUL_CONTINUE)
3866 return rc;
3867
3868 if (!vcpu->mmio_nr_fragments)
3869 return rc;
3870
3871 gpa = vcpu->mmio_fragments[0].gpa;
3872
3873 vcpu->mmio_needed = 1;
3874 vcpu->mmio_cur_fragment = 0;
3875
3876 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3877 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3878 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3879 vcpu->run->mmio.phys_addr = gpa;
3880
3881 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3882 }
3883
3884 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3885 unsigned long addr,
3886 void *val,
3887 unsigned int bytes,
3888 struct x86_exception *exception)
3889 {
3890 return emulator_read_write(ctxt, addr, val, bytes,
3891 exception, &read_emultor);
3892 }
3893
3894 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3895 unsigned long addr,
3896 const void *val,
3897 unsigned int bytes,
3898 struct x86_exception *exception)
3899 {
3900 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3901 exception, &write_emultor);
3902 }
3903
3904 #define CMPXCHG_TYPE(t, ptr, old, new) \
3905 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3906
3907 #ifdef CONFIG_X86_64
3908 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3909 #else
3910 # define CMPXCHG64(ptr, old, new) \
3911 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3912 #endif
3913
3914 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3915 unsigned long addr,
3916 const void *old,
3917 const void *new,
3918 unsigned int bytes,
3919 struct x86_exception *exception)
3920 {
3921 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3922 gpa_t gpa;
3923 struct page *page;
3924 char *kaddr;
3925 bool exchanged;
3926
3927 /* guests cmpxchg8b have to be emulated atomically */
3928 if (bytes > 8 || (bytes & (bytes - 1)))
3929 goto emul_write;
3930
3931 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3932
3933 if (gpa == UNMAPPED_GVA ||
3934 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3935 goto emul_write;
3936
3937 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3938 goto emul_write;
3939
3940 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3941 if (is_error_page(page)) {
3942 kvm_release_page_clean(page);
3943 goto emul_write;
3944 }
3945
3946 kaddr = kmap_atomic(page);
3947 kaddr += offset_in_page(gpa);
3948 switch (bytes) {
3949 case 1:
3950 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3951 break;
3952 case 2:
3953 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3954 break;
3955 case 4:
3956 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3957 break;
3958 case 8:
3959 exchanged = CMPXCHG64(kaddr, old, new);
3960 break;
3961 default:
3962 BUG();
3963 }
3964 kunmap_atomic(kaddr);
3965 kvm_release_page_dirty(page);
3966
3967 if (!exchanged)
3968 return X86EMUL_CMPXCHG_FAILED;
3969
3970 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3971
3972 return X86EMUL_CONTINUE;
3973
3974 emul_write:
3975 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3976
3977 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
3978 }
3979
3980 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3981 {
3982 /* TODO: String I/O for in kernel device */
3983 int r;
3984
3985 if (vcpu->arch.pio.in)
3986 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3987 vcpu->arch.pio.size, pd);
3988 else
3989 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3990 vcpu->arch.pio.port, vcpu->arch.pio.size,
3991 pd);
3992 return r;
3993 }
3994
3995 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3996 unsigned short port, void *val,
3997 unsigned int count, bool in)
3998 {
3999 trace_kvm_pio(!in, port, size, count);
4000
4001 vcpu->arch.pio.port = port;
4002 vcpu->arch.pio.in = in;
4003 vcpu->arch.pio.count = count;
4004 vcpu->arch.pio.size = size;
4005
4006 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4007 vcpu->arch.pio.count = 0;
4008 return 1;
4009 }
4010
4011 vcpu->run->exit_reason = KVM_EXIT_IO;
4012 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4013 vcpu->run->io.size = size;
4014 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4015 vcpu->run->io.count = count;
4016 vcpu->run->io.port = port;
4017
4018 return 0;
4019 }
4020
4021 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4022 int size, unsigned short port, void *val,
4023 unsigned int count)
4024 {
4025 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4026 int ret;
4027
4028 if (vcpu->arch.pio.count)
4029 goto data_avail;
4030
4031 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4032 if (ret) {
4033 data_avail:
4034 memcpy(val, vcpu->arch.pio_data, size * count);
4035 vcpu->arch.pio.count = 0;
4036 return 1;
4037 }
4038
4039 return 0;
4040 }
4041
4042 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4043 int size, unsigned short port,
4044 const void *val, unsigned int count)
4045 {
4046 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4047
4048 memcpy(vcpu->arch.pio_data, val, size * count);
4049 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4050 }
4051
4052 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4053 {
4054 return kvm_x86_ops->get_segment_base(vcpu, seg);
4055 }
4056
4057 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4058 {
4059 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4060 }
4061
4062 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4063 {
4064 if (!need_emulate_wbinvd(vcpu))
4065 return X86EMUL_CONTINUE;
4066
4067 if (kvm_x86_ops->has_wbinvd_exit()) {
4068 int cpu = get_cpu();
4069
4070 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4071 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4072 wbinvd_ipi, NULL, 1);
4073 put_cpu();
4074 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4075 } else
4076 wbinvd();
4077 return X86EMUL_CONTINUE;
4078 }
4079 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4080
4081 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4082 {
4083 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4084 }
4085
4086 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4087 {
4088 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4089 }
4090
4091 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4092 {
4093
4094 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4095 }
4096
4097 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4098 {
4099 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4100 }
4101
4102 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4103 {
4104 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4105 unsigned long value;
4106
4107 switch (cr) {
4108 case 0:
4109 value = kvm_read_cr0(vcpu);
4110 break;
4111 case 2:
4112 value = vcpu->arch.cr2;
4113 break;
4114 case 3:
4115 value = kvm_read_cr3(vcpu);
4116 break;
4117 case 4:
4118 value = kvm_read_cr4(vcpu);
4119 break;
4120 case 8:
4121 value = kvm_get_cr8(vcpu);
4122 break;
4123 default:
4124 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4125 return 0;
4126 }
4127
4128 return value;
4129 }
4130
4131 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4132 {
4133 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4134 int res = 0;
4135
4136 switch (cr) {
4137 case 0:
4138 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4139 break;
4140 case 2:
4141 vcpu->arch.cr2 = val;
4142 break;
4143 case 3:
4144 res = kvm_set_cr3(vcpu, val);
4145 break;
4146 case 4:
4147 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4148 break;
4149 case 8:
4150 res = kvm_set_cr8(vcpu, val);
4151 break;
4152 default:
4153 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4154 res = -1;
4155 }
4156
4157 return res;
4158 }
4159
4160 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4161 {
4162 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4163 }
4164
4165 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4166 {
4167 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4168 }
4169
4170 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4171 {
4172 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4173 }
4174
4175 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4176 {
4177 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4178 }
4179
4180 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4181 {
4182 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4183 }
4184
4185 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4186 {
4187 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4188 }
4189
4190 static unsigned long emulator_get_cached_segment_base(
4191 struct x86_emulate_ctxt *ctxt, int seg)
4192 {
4193 return get_segment_base(emul_to_vcpu(ctxt), seg);
4194 }
4195
4196 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4197 struct desc_struct *desc, u32 *base3,
4198 int seg)
4199 {
4200 struct kvm_segment var;
4201
4202 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4203 *selector = var.selector;
4204
4205 if (var.unusable)
4206 return false;
4207
4208 if (var.g)
4209 var.limit >>= 12;
4210 set_desc_limit(desc, var.limit);
4211 set_desc_base(desc, (unsigned long)var.base);
4212 #ifdef CONFIG_X86_64
4213 if (base3)
4214 *base3 = var.base >> 32;
4215 #endif
4216 desc->type = var.type;
4217 desc->s = var.s;
4218 desc->dpl = var.dpl;
4219 desc->p = var.present;
4220 desc->avl = var.avl;
4221 desc->l = var.l;
4222 desc->d = var.db;
4223 desc->g = var.g;
4224
4225 return true;
4226 }
4227
4228 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4229 struct desc_struct *desc, u32 base3,
4230 int seg)
4231 {
4232 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4233 struct kvm_segment var;
4234
4235 var.selector = selector;
4236 var.base = get_desc_base(desc);
4237 #ifdef CONFIG_X86_64
4238 var.base |= ((u64)base3) << 32;
4239 #endif
4240 var.limit = get_desc_limit(desc);
4241 if (desc->g)
4242 var.limit = (var.limit << 12) | 0xfff;
4243 var.type = desc->type;
4244 var.present = desc->p;
4245 var.dpl = desc->dpl;
4246 var.db = desc->d;
4247 var.s = desc->s;
4248 var.l = desc->l;
4249 var.g = desc->g;
4250 var.avl = desc->avl;
4251 var.present = desc->p;
4252 var.unusable = !var.present;
4253 var.padding = 0;
4254
4255 kvm_set_segment(vcpu, &var, seg);
4256 return;
4257 }
4258
4259 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4260 u32 msr_index, u64 *pdata)
4261 {
4262 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4263 }
4264
4265 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4266 u32 msr_index, u64 data)
4267 {
4268 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4269 }
4270
4271 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4272 u32 pmc, u64 *pdata)
4273 {
4274 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4275 }
4276
4277 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4278 {
4279 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4280 }
4281
4282 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4283 {
4284 preempt_disable();
4285 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4286 /*
4287 * CR0.TS may reference the host fpu state, not the guest fpu state,
4288 * so it may be clear at this point.
4289 */
4290 clts();
4291 }
4292
4293 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4294 {
4295 preempt_enable();
4296 }
4297
4298 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4299 struct x86_instruction_info *info,
4300 enum x86_intercept_stage stage)
4301 {
4302 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4303 }
4304
4305 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4306 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4307 {
4308 struct kvm_cpuid_entry2 *cpuid = NULL;
4309
4310 if (eax && ecx)
4311 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4312 *eax, *ecx);
4313
4314 if (cpuid) {
4315 *eax = cpuid->eax;
4316 *ecx = cpuid->ecx;
4317 if (ebx)
4318 *ebx = cpuid->ebx;
4319 if (edx)
4320 *edx = cpuid->edx;
4321 return true;
4322 }
4323
4324 return false;
4325 }
4326
4327 static struct x86_emulate_ops emulate_ops = {
4328 .read_std = kvm_read_guest_virt_system,
4329 .write_std = kvm_write_guest_virt_system,
4330 .fetch = kvm_fetch_guest_virt,
4331 .read_emulated = emulator_read_emulated,
4332 .write_emulated = emulator_write_emulated,
4333 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4334 .invlpg = emulator_invlpg,
4335 .pio_in_emulated = emulator_pio_in_emulated,
4336 .pio_out_emulated = emulator_pio_out_emulated,
4337 .get_segment = emulator_get_segment,
4338 .set_segment = emulator_set_segment,
4339 .get_cached_segment_base = emulator_get_cached_segment_base,
4340 .get_gdt = emulator_get_gdt,
4341 .get_idt = emulator_get_idt,
4342 .set_gdt = emulator_set_gdt,
4343 .set_idt = emulator_set_idt,
4344 .get_cr = emulator_get_cr,
4345 .set_cr = emulator_set_cr,
4346 .set_rflags = emulator_set_rflags,
4347 .cpl = emulator_get_cpl,
4348 .get_dr = emulator_get_dr,
4349 .set_dr = emulator_set_dr,
4350 .set_msr = emulator_set_msr,
4351 .get_msr = emulator_get_msr,
4352 .read_pmc = emulator_read_pmc,
4353 .halt = emulator_halt,
4354 .wbinvd = emulator_wbinvd,
4355 .fix_hypercall = emulator_fix_hypercall,
4356 .get_fpu = emulator_get_fpu,
4357 .put_fpu = emulator_put_fpu,
4358 .intercept = emulator_intercept,
4359 .get_cpuid = emulator_get_cpuid,
4360 };
4361
4362 static void cache_all_regs(struct kvm_vcpu *vcpu)
4363 {
4364 kvm_register_read(vcpu, VCPU_REGS_RAX);
4365 kvm_register_read(vcpu, VCPU_REGS_RSP);
4366 kvm_register_read(vcpu, VCPU_REGS_RIP);
4367 vcpu->arch.regs_dirty = ~0;
4368 }
4369
4370 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4371 {
4372 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4373 /*
4374 * an sti; sti; sequence only disable interrupts for the first
4375 * instruction. So, if the last instruction, be it emulated or
4376 * not, left the system with the INT_STI flag enabled, it
4377 * means that the last instruction is an sti. We should not
4378 * leave the flag on in this case. The same goes for mov ss
4379 */
4380 if (!(int_shadow & mask))
4381 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4382 }
4383
4384 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4385 {
4386 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4387 if (ctxt->exception.vector == PF_VECTOR)
4388 kvm_propagate_fault(vcpu, &ctxt->exception);
4389 else if (ctxt->exception.error_code_valid)
4390 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4391 ctxt->exception.error_code);
4392 else
4393 kvm_queue_exception(vcpu, ctxt->exception.vector);
4394 }
4395
4396 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4397 const unsigned long *regs)
4398 {
4399 memset(&ctxt->twobyte, 0,
4400 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4401 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4402
4403 ctxt->fetch.start = 0;
4404 ctxt->fetch.end = 0;
4405 ctxt->io_read.pos = 0;
4406 ctxt->io_read.end = 0;
4407 ctxt->mem_read.pos = 0;
4408 ctxt->mem_read.end = 0;
4409 }
4410
4411 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4412 {
4413 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4414 int cs_db, cs_l;
4415
4416 /*
4417 * TODO: fix emulate.c to use guest_read/write_register
4418 * instead of direct ->regs accesses, can save hundred cycles
4419 * on Intel for instructions that don't read/change RSP, for
4420 * for example.
4421 */
4422 cache_all_regs(vcpu);
4423
4424 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4425
4426 ctxt->eflags = kvm_get_rflags(vcpu);
4427 ctxt->eip = kvm_rip_read(vcpu);
4428 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4429 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4430 cs_l ? X86EMUL_MODE_PROT64 :
4431 cs_db ? X86EMUL_MODE_PROT32 :
4432 X86EMUL_MODE_PROT16;
4433 ctxt->guest_mode = is_guest_mode(vcpu);
4434
4435 init_decode_cache(ctxt, vcpu->arch.regs);
4436 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4437 }
4438
4439 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4440 {
4441 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4442 int ret;
4443
4444 init_emulate_ctxt(vcpu);
4445
4446 ctxt->op_bytes = 2;
4447 ctxt->ad_bytes = 2;
4448 ctxt->_eip = ctxt->eip + inc_eip;
4449 ret = emulate_int_real(ctxt, irq);
4450
4451 if (ret != X86EMUL_CONTINUE)
4452 return EMULATE_FAIL;
4453
4454 ctxt->eip = ctxt->_eip;
4455 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4456 kvm_rip_write(vcpu, ctxt->eip);
4457 kvm_set_rflags(vcpu, ctxt->eflags);
4458
4459 if (irq == NMI_VECTOR)
4460 vcpu->arch.nmi_pending = 0;
4461 else
4462 vcpu->arch.interrupt.pending = false;
4463
4464 return EMULATE_DONE;
4465 }
4466 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4467
4468 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4469 {
4470 int r = EMULATE_DONE;
4471
4472 ++vcpu->stat.insn_emulation_fail;
4473 trace_kvm_emulate_insn_failed(vcpu);
4474 if (!is_guest_mode(vcpu)) {
4475 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4476 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4477 vcpu->run->internal.ndata = 0;
4478 r = EMULATE_FAIL;
4479 }
4480 kvm_queue_exception(vcpu, UD_VECTOR);
4481
4482 return r;
4483 }
4484
4485 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4486 {
4487 gpa_t gpa;
4488
4489 if (tdp_enabled)
4490 return false;
4491
4492 /*
4493 * if emulation was due to access to shadowed page table
4494 * and it failed try to unshadow page and re-entetr the
4495 * guest to let CPU execute the instruction.
4496 */
4497 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4498 return true;
4499
4500 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4501
4502 if (gpa == UNMAPPED_GVA)
4503 return true; /* let cpu generate fault */
4504
4505 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4506 return true;
4507
4508 return false;
4509 }
4510
4511 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4512 unsigned long cr2, int emulation_type)
4513 {
4514 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4515 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4516
4517 last_retry_eip = vcpu->arch.last_retry_eip;
4518 last_retry_addr = vcpu->arch.last_retry_addr;
4519
4520 /*
4521 * If the emulation is caused by #PF and it is non-page_table
4522 * writing instruction, it means the VM-EXIT is caused by shadow
4523 * page protected, we can zap the shadow page and retry this
4524 * instruction directly.
4525 *
4526 * Note: if the guest uses a non-page-table modifying instruction
4527 * on the PDE that points to the instruction, then we will unmap
4528 * the instruction and go to an infinite loop. So, we cache the
4529 * last retried eip and the last fault address, if we meet the eip
4530 * and the address again, we can break out of the potential infinite
4531 * loop.
4532 */
4533 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4534
4535 if (!(emulation_type & EMULTYPE_RETRY))
4536 return false;
4537
4538 if (x86_page_table_writing_insn(ctxt))
4539 return false;
4540
4541 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4542 return false;
4543
4544 vcpu->arch.last_retry_eip = ctxt->eip;
4545 vcpu->arch.last_retry_addr = cr2;
4546
4547 if (!vcpu->arch.mmu.direct_map)
4548 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4549
4550 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4551
4552 return true;
4553 }
4554
4555 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4556 unsigned long cr2,
4557 int emulation_type,
4558 void *insn,
4559 int insn_len)
4560 {
4561 int r;
4562 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4563 bool writeback = true;
4564
4565 kvm_clear_exception_queue(vcpu);
4566
4567 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4568 init_emulate_ctxt(vcpu);
4569 ctxt->interruptibility = 0;
4570 ctxt->have_exception = false;
4571 ctxt->perm_ok = false;
4572
4573 ctxt->only_vendor_specific_insn
4574 = emulation_type & EMULTYPE_TRAP_UD;
4575
4576 r = x86_decode_insn(ctxt, insn, insn_len);
4577
4578 trace_kvm_emulate_insn_start(vcpu);
4579 ++vcpu->stat.insn_emulation;
4580 if (r != EMULATION_OK) {
4581 if (emulation_type & EMULTYPE_TRAP_UD)
4582 return EMULATE_FAIL;
4583 if (reexecute_instruction(vcpu, cr2))
4584 return EMULATE_DONE;
4585 if (emulation_type & EMULTYPE_SKIP)
4586 return EMULATE_FAIL;
4587 return handle_emulation_failure(vcpu);
4588 }
4589 }
4590
4591 if (emulation_type & EMULTYPE_SKIP) {
4592 kvm_rip_write(vcpu, ctxt->_eip);
4593 return EMULATE_DONE;
4594 }
4595
4596 if (retry_instruction(ctxt, cr2, emulation_type))
4597 return EMULATE_DONE;
4598
4599 /* this is needed for vmware backdoor interface to work since it
4600 changes registers values during IO operation */
4601 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4602 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4603 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4604 }
4605
4606 restart:
4607 r = x86_emulate_insn(ctxt);
4608
4609 if (r == EMULATION_INTERCEPTED)
4610 return EMULATE_DONE;
4611
4612 if (r == EMULATION_FAILED) {
4613 if (reexecute_instruction(vcpu, cr2))
4614 return EMULATE_DONE;
4615
4616 return handle_emulation_failure(vcpu);
4617 }
4618
4619 if (ctxt->have_exception) {
4620 inject_emulated_exception(vcpu);
4621 r = EMULATE_DONE;
4622 } else if (vcpu->arch.pio.count) {
4623 if (!vcpu->arch.pio.in)
4624 vcpu->arch.pio.count = 0;
4625 else
4626 writeback = false;
4627 r = EMULATE_DO_MMIO;
4628 } else if (vcpu->mmio_needed) {
4629 if (!vcpu->mmio_is_write)
4630 writeback = false;
4631 r = EMULATE_DO_MMIO;
4632 } else if (r == EMULATION_RESTART)
4633 goto restart;
4634 else
4635 r = EMULATE_DONE;
4636
4637 if (writeback) {
4638 toggle_interruptibility(vcpu, ctxt->interruptibility);
4639 kvm_set_rflags(vcpu, ctxt->eflags);
4640 kvm_make_request(KVM_REQ_EVENT, vcpu);
4641 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4642 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4643 kvm_rip_write(vcpu, ctxt->eip);
4644 } else
4645 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4646
4647 return r;
4648 }
4649 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4650
4651 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4652 {
4653 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4654 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4655 size, port, &val, 1);
4656 /* do not return to emulator after return from userspace */
4657 vcpu->arch.pio.count = 0;
4658 return ret;
4659 }
4660 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4661
4662 static void tsc_bad(void *info)
4663 {
4664 __this_cpu_write(cpu_tsc_khz, 0);
4665 }
4666
4667 static void tsc_khz_changed(void *data)
4668 {
4669 struct cpufreq_freqs *freq = data;
4670 unsigned long khz = 0;
4671
4672 if (data)
4673 khz = freq->new;
4674 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4675 khz = cpufreq_quick_get(raw_smp_processor_id());
4676 if (!khz)
4677 khz = tsc_khz;
4678 __this_cpu_write(cpu_tsc_khz, khz);
4679 }
4680
4681 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4682 void *data)
4683 {
4684 struct cpufreq_freqs *freq = data;
4685 struct kvm *kvm;
4686 struct kvm_vcpu *vcpu;
4687 int i, send_ipi = 0;
4688
4689 /*
4690 * We allow guests to temporarily run on slowing clocks,
4691 * provided we notify them after, or to run on accelerating
4692 * clocks, provided we notify them before. Thus time never
4693 * goes backwards.
4694 *
4695 * However, we have a problem. We can't atomically update
4696 * the frequency of a given CPU from this function; it is
4697 * merely a notifier, which can be called from any CPU.
4698 * Changing the TSC frequency at arbitrary points in time
4699 * requires a recomputation of local variables related to
4700 * the TSC for each VCPU. We must flag these local variables
4701 * to be updated and be sure the update takes place with the
4702 * new frequency before any guests proceed.
4703 *
4704 * Unfortunately, the combination of hotplug CPU and frequency
4705 * change creates an intractable locking scenario; the order
4706 * of when these callouts happen is undefined with respect to
4707 * CPU hotplug, and they can race with each other. As such,
4708 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4709 * undefined; you can actually have a CPU frequency change take
4710 * place in between the computation of X and the setting of the
4711 * variable. To protect against this problem, all updates of
4712 * the per_cpu tsc_khz variable are done in an interrupt
4713 * protected IPI, and all callers wishing to update the value
4714 * must wait for a synchronous IPI to complete (which is trivial
4715 * if the caller is on the CPU already). This establishes the
4716 * necessary total order on variable updates.
4717 *
4718 * Note that because a guest time update may take place
4719 * anytime after the setting of the VCPU's request bit, the
4720 * correct TSC value must be set before the request. However,
4721 * to ensure the update actually makes it to any guest which
4722 * starts running in hardware virtualization between the set
4723 * and the acquisition of the spinlock, we must also ping the
4724 * CPU after setting the request bit.
4725 *
4726 */
4727
4728 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4729 return 0;
4730 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4731 return 0;
4732
4733 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4734
4735 raw_spin_lock(&kvm_lock);
4736 list_for_each_entry(kvm, &vm_list, vm_list) {
4737 kvm_for_each_vcpu(i, vcpu, kvm) {
4738 if (vcpu->cpu != freq->cpu)
4739 continue;
4740 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4741 if (vcpu->cpu != smp_processor_id())
4742 send_ipi = 1;
4743 }
4744 }
4745 raw_spin_unlock(&kvm_lock);
4746
4747 if (freq->old < freq->new && send_ipi) {
4748 /*
4749 * We upscale the frequency. Must make the guest
4750 * doesn't see old kvmclock values while running with
4751 * the new frequency, otherwise we risk the guest sees
4752 * time go backwards.
4753 *
4754 * In case we update the frequency for another cpu
4755 * (which might be in guest context) send an interrupt
4756 * to kick the cpu out of guest context. Next time
4757 * guest context is entered kvmclock will be updated,
4758 * so the guest will not see stale values.
4759 */
4760 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4761 }
4762 return 0;
4763 }
4764
4765 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4766 .notifier_call = kvmclock_cpufreq_notifier
4767 };
4768
4769 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4770 unsigned long action, void *hcpu)
4771 {
4772 unsigned int cpu = (unsigned long)hcpu;
4773
4774 switch (action) {
4775 case CPU_ONLINE:
4776 case CPU_DOWN_FAILED:
4777 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4778 break;
4779 case CPU_DOWN_PREPARE:
4780 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4781 break;
4782 }
4783 return NOTIFY_OK;
4784 }
4785
4786 static struct notifier_block kvmclock_cpu_notifier_block = {
4787 .notifier_call = kvmclock_cpu_notifier,
4788 .priority = -INT_MAX
4789 };
4790
4791 static void kvm_timer_init(void)
4792 {
4793 int cpu;
4794
4795 max_tsc_khz = tsc_khz;
4796 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4797 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4798 #ifdef CONFIG_CPU_FREQ
4799 struct cpufreq_policy policy;
4800 memset(&policy, 0, sizeof(policy));
4801 cpu = get_cpu();
4802 cpufreq_get_policy(&policy, cpu);
4803 if (policy.cpuinfo.max_freq)
4804 max_tsc_khz = policy.cpuinfo.max_freq;
4805 put_cpu();
4806 #endif
4807 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4808 CPUFREQ_TRANSITION_NOTIFIER);
4809 }
4810 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4811 for_each_online_cpu(cpu)
4812 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4813 }
4814
4815 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4816
4817 int kvm_is_in_guest(void)
4818 {
4819 return __this_cpu_read(current_vcpu) != NULL;
4820 }
4821
4822 static int kvm_is_user_mode(void)
4823 {
4824 int user_mode = 3;
4825
4826 if (__this_cpu_read(current_vcpu))
4827 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4828
4829 return user_mode != 0;
4830 }
4831
4832 static unsigned long kvm_get_guest_ip(void)
4833 {
4834 unsigned long ip = 0;
4835
4836 if (__this_cpu_read(current_vcpu))
4837 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4838
4839 return ip;
4840 }
4841
4842 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4843 .is_in_guest = kvm_is_in_guest,
4844 .is_user_mode = kvm_is_user_mode,
4845 .get_guest_ip = kvm_get_guest_ip,
4846 };
4847
4848 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4849 {
4850 __this_cpu_write(current_vcpu, vcpu);
4851 }
4852 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4853
4854 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4855 {
4856 __this_cpu_write(current_vcpu, NULL);
4857 }
4858 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4859
4860 static void kvm_set_mmio_spte_mask(void)
4861 {
4862 u64 mask;
4863 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4864
4865 /*
4866 * Set the reserved bits and the present bit of an paging-structure
4867 * entry to generate page fault with PFER.RSV = 1.
4868 */
4869 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4870 mask |= 1ull;
4871
4872 #ifdef CONFIG_X86_64
4873 /*
4874 * If reserved bit is not supported, clear the present bit to disable
4875 * mmio page fault.
4876 */
4877 if (maxphyaddr == 52)
4878 mask &= ~1ull;
4879 #endif
4880
4881 kvm_mmu_set_mmio_spte_mask(mask);
4882 }
4883
4884 int kvm_arch_init(void *opaque)
4885 {
4886 int r;
4887 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4888
4889 if (kvm_x86_ops) {
4890 printk(KERN_ERR "kvm: already loaded the other module\n");
4891 r = -EEXIST;
4892 goto out;
4893 }
4894
4895 if (!ops->cpu_has_kvm_support()) {
4896 printk(KERN_ERR "kvm: no hardware support\n");
4897 r = -EOPNOTSUPP;
4898 goto out;
4899 }
4900 if (ops->disabled_by_bios()) {
4901 printk(KERN_ERR "kvm: disabled by bios\n");
4902 r = -EOPNOTSUPP;
4903 goto out;
4904 }
4905
4906 r = kvm_mmu_module_init();
4907 if (r)
4908 goto out;
4909
4910 kvm_set_mmio_spte_mask();
4911 kvm_init_msr_list();
4912
4913 kvm_x86_ops = ops;
4914 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4915 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4916
4917 kvm_timer_init();
4918
4919 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4920
4921 if (cpu_has_xsave)
4922 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4923
4924 return 0;
4925
4926 out:
4927 return r;
4928 }
4929
4930 void kvm_arch_exit(void)
4931 {
4932 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4933
4934 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4935 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4936 CPUFREQ_TRANSITION_NOTIFIER);
4937 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4938 kvm_x86_ops = NULL;
4939 kvm_mmu_module_exit();
4940 }
4941
4942 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4943 {
4944 ++vcpu->stat.halt_exits;
4945 if (irqchip_in_kernel(vcpu->kvm)) {
4946 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4947 return 1;
4948 } else {
4949 vcpu->run->exit_reason = KVM_EXIT_HLT;
4950 return 0;
4951 }
4952 }
4953 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4954
4955 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4956 {
4957 u64 param, ingpa, outgpa, ret;
4958 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4959 bool fast, longmode;
4960 int cs_db, cs_l;
4961
4962 /*
4963 * hypercall generates UD from non zero cpl and real mode
4964 * per HYPER-V spec
4965 */
4966 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4967 kvm_queue_exception(vcpu, UD_VECTOR);
4968 return 0;
4969 }
4970
4971 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4972 longmode = is_long_mode(vcpu) && cs_l == 1;
4973
4974 if (!longmode) {
4975 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4976 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4977 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4978 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4979 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4980 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4981 }
4982 #ifdef CONFIG_X86_64
4983 else {
4984 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4985 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4986 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4987 }
4988 #endif
4989
4990 code = param & 0xffff;
4991 fast = (param >> 16) & 0x1;
4992 rep_cnt = (param >> 32) & 0xfff;
4993 rep_idx = (param >> 48) & 0xfff;
4994
4995 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4996
4997 switch (code) {
4998 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4999 kvm_vcpu_on_spin(vcpu);
5000 break;
5001 default:
5002 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5003 break;
5004 }
5005
5006 ret = res | (((u64)rep_done & 0xfff) << 32);
5007 if (longmode) {
5008 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5009 } else {
5010 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5011 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5012 }
5013
5014 return 1;
5015 }
5016
5017 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5018 {
5019 unsigned long nr, a0, a1, a2, a3, ret;
5020 int r = 1;
5021
5022 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5023 return kvm_hv_hypercall(vcpu);
5024
5025 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5026 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5027 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5028 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5029 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5030
5031 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5032
5033 if (!is_long_mode(vcpu)) {
5034 nr &= 0xFFFFFFFF;
5035 a0 &= 0xFFFFFFFF;
5036 a1 &= 0xFFFFFFFF;
5037 a2 &= 0xFFFFFFFF;
5038 a3 &= 0xFFFFFFFF;
5039 }
5040
5041 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5042 ret = -KVM_EPERM;
5043 goto out;
5044 }
5045
5046 switch (nr) {
5047 case KVM_HC_VAPIC_POLL_IRQ:
5048 ret = 0;
5049 break;
5050 default:
5051 ret = -KVM_ENOSYS;
5052 break;
5053 }
5054 out:
5055 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5056 ++vcpu->stat.hypercalls;
5057 return r;
5058 }
5059 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5060
5061 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5062 {
5063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5064 char instruction[3];
5065 unsigned long rip = kvm_rip_read(vcpu);
5066
5067 /*
5068 * Blow out the MMU to ensure that no other VCPU has an active mapping
5069 * to ensure that the updated hypercall appears atomically across all
5070 * VCPUs.
5071 */
5072 kvm_mmu_zap_all(vcpu->kvm);
5073
5074 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5075
5076 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5077 }
5078
5079 /*
5080 * Check if userspace requested an interrupt window, and that the
5081 * interrupt window is open.
5082 *
5083 * No need to exit to userspace if we already have an interrupt queued.
5084 */
5085 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5086 {
5087 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5088 vcpu->run->request_interrupt_window &&
5089 kvm_arch_interrupt_allowed(vcpu));
5090 }
5091
5092 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5093 {
5094 struct kvm_run *kvm_run = vcpu->run;
5095
5096 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5097 kvm_run->cr8 = kvm_get_cr8(vcpu);
5098 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5099 if (irqchip_in_kernel(vcpu->kvm))
5100 kvm_run->ready_for_interrupt_injection = 1;
5101 else
5102 kvm_run->ready_for_interrupt_injection =
5103 kvm_arch_interrupt_allowed(vcpu) &&
5104 !kvm_cpu_has_interrupt(vcpu) &&
5105 !kvm_event_needs_reinjection(vcpu);
5106 }
5107
5108 static void vapic_enter(struct kvm_vcpu *vcpu)
5109 {
5110 struct kvm_lapic *apic = vcpu->arch.apic;
5111 struct page *page;
5112
5113 if (!apic || !apic->vapic_addr)
5114 return;
5115
5116 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5117
5118 vcpu->arch.apic->vapic_page = page;
5119 }
5120
5121 static void vapic_exit(struct kvm_vcpu *vcpu)
5122 {
5123 struct kvm_lapic *apic = vcpu->arch.apic;
5124 int idx;
5125
5126 if (!apic || !apic->vapic_addr)
5127 return;
5128
5129 idx = srcu_read_lock(&vcpu->kvm->srcu);
5130 kvm_release_page_dirty(apic->vapic_page);
5131 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5132 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5133 }
5134
5135 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5136 {
5137 int max_irr, tpr;
5138
5139 if (!kvm_x86_ops->update_cr8_intercept)
5140 return;
5141
5142 if (!vcpu->arch.apic)
5143 return;
5144
5145 if (!vcpu->arch.apic->vapic_addr)
5146 max_irr = kvm_lapic_find_highest_irr(vcpu);
5147 else
5148 max_irr = -1;
5149
5150 if (max_irr != -1)
5151 max_irr >>= 4;
5152
5153 tpr = kvm_lapic_get_cr8(vcpu);
5154
5155 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5156 }
5157
5158 static void inject_pending_event(struct kvm_vcpu *vcpu)
5159 {
5160 /* try to reinject previous events if any */
5161 if (vcpu->arch.exception.pending) {
5162 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5163 vcpu->arch.exception.has_error_code,
5164 vcpu->arch.exception.error_code);
5165 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5166 vcpu->arch.exception.has_error_code,
5167 vcpu->arch.exception.error_code,
5168 vcpu->arch.exception.reinject);
5169 return;
5170 }
5171
5172 if (vcpu->arch.nmi_injected) {
5173 kvm_x86_ops->set_nmi(vcpu);
5174 return;
5175 }
5176
5177 if (vcpu->arch.interrupt.pending) {
5178 kvm_x86_ops->set_irq(vcpu);
5179 return;
5180 }
5181
5182 /* try to inject new event if pending */
5183 if (vcpu->arch.nmi_pending) {
5184 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5185 --vcpu->arch.nmi_pending;
5186 vcpu->arch.nmi_injected = true;
5187 kvm_x86_ops->set_nmi(vcpu);
5188 }
5189 } else if (kvm_cpu_has_interrupt(vcpu)) {
5190 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5191 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5192 false);
5193 kvm_x86_ops->set_irq(vcpu);
5194 }
5195 }
5196 }
5197
5198 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5199 {
5200 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5201 !vcpu->guest_xcr0_loaded) {
5202 /* kvm_set_xcr() also depends on this */
5203 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5204 vcpu->guest_xcr0_loaded = 1;
5205 }
5206 }
5207
5208 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5209 {
5210 if (vcpu->guest_xcr0_loaded) {
5211 if (vcpu->arch.xcr0 != host_xcr0)
5212 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5213 vcpu->guest_xcr0_loaded = 0;
5214 }
5215 }
5216
5217 static void process_nmi(struct kvm_vcpu *vcpu)
5218 {
5219 unsigned limit = 2;
5220
5221 /*
5222 * x86 is limited to one NMI running, and one NMI pending after it.
5223 * If an NMI is already in progress, limit further NMIs to just one.
5224 * Otherwise, allow two (and we'll inject the first one immediately).
5225 */
5226 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5227 limit = 1;
5228
5229 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5230 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5231 kvm_make_request(KVM_REQ_EVENT, vcpu);
5232 }
5233
5234 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5235 {
5236 int r;
5237 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5238 vcpu->run->request_interrupt_window;
5239 bool req_immediate_exit = 0;
5240
5241 if (vcpu->requests) {
5242 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5243 kvm_mmu_unload(vcpu);
5244 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5245 __kvm_migrate_timers(vcpu);
5246 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5247 r = kvm_guest_time_update(vcpu);
5248 if (unlikely(r))
5249 goto out;
5250 }
5251 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5252 kvm_mmu_sync_roots(vcpu);
5253 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5254 kvm_x86_ops->tlb_flush(vcpu);
5255 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5256 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5257 r = 0;
5258 goto out;
5259 }
5260 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5261 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5262 r = 0;
5263 goto out;
5264 }
5265 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5266 vcpu->fpu_active = 0;
5267 kvm_x86_ops->fpu_deactivate(vcpu);
5268 }
5269 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5270 /* Page is swapped out. Do synthetic halt */
5271 vcpu->arch.apf.halted = true;
5272 r = 1;
5273 goto out;
5274 }
5275 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5276 record_steal_time(vcpu);
5277 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5278 process_nmi(vcpu);
5279 req_immediate_exit =
5280 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5281 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5282 kvm_handle_pmu_event(vcpu);
5283 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5284 kvm_deliver_pmi(vcpu);
5285 }
5286
5287 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5288 inject_pending_event(vcpu);
5289
5290 /* enable NMI/IRQ window open exits if needed */
5291 if (vcpu->arch.nmi_pending)
5292 kvm_x86_ops->enable_nmi_window(vcpu);
5293 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5294 kvm_x86_ops->enable_irq_window(vcpu);
5295
5296 if (kvm_lapic_enabled(vcpu)) {
5297 update_cr8_intercept(vcpu);
5298 kvm_lapic_sync_to_vapic(vcpu);
5299 }
5300 }
5301
5302 r = kvm_mmu_reload(vcpu);
5303 if (unlikely(r)) {
5304 goto cancel_injection;
5305 }
5306
5307 preempt_disable();
5308
5309 kvm_x86_ops->prepare_guest_switch(vcpu);
5310 if (vcpu->fpu_active)
5311 kvm_load_guest_fpu(vcpu);
5312 kvm_load_guest_xcr0(vcpu);
5313
5314 vcpu->mode = IN_GUEST_MODE;
5315
5316 /* We should set ->mode before check ->requests,
5317 * see the comment in make_all_cpus_request.
5318 */
5319 smp_mb();
5320
5321 local_irq_disable();
5322
5323 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5324 || need_resched() || signal_pending(current)) {
5325 vcpu->mode = OUTSIDE_GUEST_MODE;
5326 smp_wmb();
5327 local_irq_enable();
5328 preempt_enable();
5329 r = 1;
5330 goto cancel_injection;
5331 }
5332
5333 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5334
5335 if (req_immediate_exit)
5336 smp_send_reschedule(vcpu->cpu);
5337
5338 kvm_guest_enter();
5339
5340 if (unlikely(vcpu->arch.switch_db_regs)) {
5341 set_debugreg(0, 7);
5342 set_debugreg(vcpu->arch.eff_db[0], 0);
5343 set_debugreg(vcpu->arch.eff_db[1], 1);
5344 set_debugreg(vcpu->arch.eff_db[2], 2);
5345 set_debugreg(vcpu->arch.eff_db[3], 3);
5346 }
5347
5348 trace_kvm_entry(vcpu->vcpu_id);
5349 kvm_x86_ops->run(vcpu);
5350
5351 /*
5352 * If the guest has used debug registers, at least dr7
5353 * will be disabled while returning to the host.
5354 * If we don't have active breakpoints in the host, we don't
5355 * care about the messed up debug address registers. But if
5356 * we have some of them active, restore the old state.
5357 */
5358 if (hw_breakpoint_active())
5359 hw_breakpoint_restore();
5360
5361 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5362
5363 vcpu->mode = OUTSIDE_GUEST_MODE;
5364 smp_wmb();
5365 local_irq_enable();
5366
5367 ++vcpu->stat.exits;
5368
5369 /*
5370 * We must have an instruction between local_irq_enable() and
5371 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5372 * the interrupt shadow. The stat.exits increment will do nicely.
5373 * But we need to prevent reordering, hence this barrier():
5374 */
5375 barrier();
5376
5377 kvm_guest_exit();
5378
5379 preempt_enable();
5380
5381 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5382
5383 /*
5384 * Profile KVM exit RIPs:
5385 */
5386 if (unlikely(prof_on == KVM_PROFILING)) {
5387 unsigned long rip = kvm_rip_read(vcpu);
5388 profile_hit(KVM_PROFILING, (void *)rip);
5389 }
5390
5391 if (unlikely(vcpu->arch.tsc_always_catchup))
5392 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5393
5394 if (vcpu->arch.apic_attention)
5395 kvm_lapic_sync_from_vapic(vcpu);
5396
5397 r = kvm_x86_ops->handle_exit(vcpu);
5398 return r;
5399
5400 cancel_injection:
5401 kvm_x86_ops->cancel_injection(vcpu);
5402 if (unlikely(vcpu->arch.apic_attention))
5403 kvm_lapic_sync_from_vapic(vcpu);
5404 out:
5405 return r;
5406 }
5407
5408
5409 static int __vcpu_run(struct kvm_vcpu *vcpu)
5410 {
5411 int r;
5412 struct kvm *kvm = vcpu->kvm;
5413
5414 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5415 pr_debug("vcpu %d received sipi with vector # %x\n",
5416 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5417 kvm_lapic_reset(vcpu);
5418 r = kvm_arch_vcpu_reset(vcpu);
5419 if (r)
5420 return r;
5421 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5422 }
5423
5424 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5425 vapic_enter(vcpu);
5426
5427 r = 1;
5428 while (r > 0) {
5429 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5430 !vcpu->arch.apf.halted)
5431 r = vcpu_enter_guest(vcpu);
5432 else {
5433 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5434 kvm_vcpu_block(vcpu);
5435 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5436 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5437 {
5438 switch(vcpu->arch.mp_state) {
5439 case KVM_MP_STATE_HALTED:
5440 vcpu->arch.mp_state =
5441 KVM_MP_STATE_RUNNABLE;
5442 case KVM_MP_STATE_RUNNABLE:
5443 vcpu->arch.apf.halted = false;
5444 break;
5445 case KVM_MP_STATE_SIPI_RECEIVED:
5446 default:
5447 r = -EINTR;
5448 break;
5449 }
5450 }
5451 }
5452
5453 if (r <= 0)
5454 break;
5455
5456 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5457 if (kvm_cpu_has_pending_timer(vcpu))
5458 kvm_inject_pending_timer_irqs(vcpu);
5459
5460 if (dm_request_for_irq_injection(vcpu)) {
5461 r = -EINTR;
5462 vcpu->run->exit_reason = KVM_EXIT_INTR;
5463 ++vcpu->stat.request_irq_exits;
5464 }
5465
5466 kvm_check_async_pf_completion(vcpu);
5467
5468 if (signal_pending(current)) {
5469 r = -EINTR;
5470 vcpu->run->exit_reason = KVM_EXIT_INTR;
5471 ++vcpu->stat.signal_exits;
5472 }
5473 if (need_resched()) {
5474 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5475 kvm_resched(vcpu);
5476 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5477 }
5478 }
5479
5480 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5481
5482 vapic_exit(vcpu);
5483
5484 return r;
5485 }
5486
5487 /*
5488 * Implements the following, as a state machine:
5489 *
5490 * read:
5491 * for each fragment
5492 * write gpa, len
5493 * exit
5494 * copy data
5495 * execute insn
5496 *
5497 * write:
5498 * for each fragment
5499 * write gpa, len
5500 * copy data
5501 * exit
5502 */
5503 static int complete_mmio(struct kvm_vcpu *vcpu)
5504 {
5505 struct kvm_run *run = vcpu->run;
5506 struct kvm_mmio_fragment *frag;
5507 int r;
5508
5509 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5510 return 1;
5511
5512 if (vcpu->mmio_needed) {
5513 /* Complete previous fragment */
5514 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5515 if (!vcpu->mmio_is_write)
5516 memcpy(frag->data, run->mmio.data, frag->len);
5517 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5518 vcpu->mmio_needed = 0;
5519 if (vcpu->mmio_is_write)
5520 return 1;
5521 vcpu->mmio_read_completed = 1;
5522 goto done;
5523 }
5524 /* Initiate next fragment */
5525 ++frag;
5526 run->exit_reason = KVM_EXIT_MMIO;
5527 run->mmio.phys_addr = frag->gpa;
5528 if (vcpu->mmio_is_write)
5529 memcpy(run->mmio.data, frag->data, frag->len);
5530 run->mmio.len = frag->len;
5531 run->mmio.is_write = vcpu->mmio_is_write;
5532 return 0;
5533
5534 }
5535 done:
5536 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5537 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5538 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5539 if (r != EMULATE_DONE)
5540 return 0;
5541 return 1;
5542 }
5543
5544 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5545 {
5546 int r;
5547 sigset_t sigsaved;
5548
5549 if (!tsk_used_math(current) && init_fpu(current))
5550 return -ENOMEM;
5551
5552 if (vcpu->sigset_active)
5553 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5554
5555 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5556 kvm_vcpu_block(vcpu);
5557 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5558 r = -EAGAIN;
5559 goto out;
5560 }
5561
5562 /* re-sync apic's tpr */
5563 if (!irqchip_in_kernel(vcpu->kvm)) {
5564 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5565 r = -EINVAL;
5566 goto out;
5567 }
5568 }
5569
5570 r = complete_mmio(vcpu);
5571 if (r <= 0)
5572 goto out;
5573
5574 r = __vcpu_run(vcpu);
5575
5576 out:
5577 post_kvm_run_save(vcpu);
5578 if (vcpu->sigset_active)
5579 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5580
5581 return r;
5582 }
5583
5584 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5585 {
5586 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5587 /*
5588 * We are here if userspace calls get_regs() in the middle of
5589 * instruction emulation. Registers state needs to be copied
5590 * back from emulation context to vcpu. Usrapace shouldn't do
5591 * that usually, but some bad designed PV devices (vmware
5592 * backdoor interface) need this to work
5593 */
5594 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5595 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5596 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5597 }
5598 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5599 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5600 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5601 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5602 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5603 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5604 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5605 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5606 #ifdef CONFIG_X86_64
5607 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5608 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5609 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5610 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5611 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5612 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5613 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5614 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5615 #endif
5616
5617 regs->rip = kvm_rip_read(vcpu);
5618 regs->rflags = kvm_get_rflags(vcpu);
5619
5620 return 0;
5621 }
5622
5623 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5624 {
5625 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5626 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5627
5628 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5629 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5630 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5631 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5632 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5633 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5634 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5635 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5636 #ifdef CONFIG_X86_64
5637 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5638 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5639 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5640 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5641 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5642 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5643 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5644 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5645 #endif
5646
5647 kvm_rip_write(vcpu, regs->rip);
5648 kvm_set_rflags(vcpu, regs->rflags);
5649
5650 vcpu->arch.exception.pending = false;
5651
5652 kvm_make_request(KVM_REQ_EVENT, vcpu);
5653
5654 return 0;
5655 }
5656
5657 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5658 {
5659 struct kvm_segment cs;
5660
5661 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5662 *db = cs.db;
5663 *l = cs.l;
5664 }
5665 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5666
5667 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5668 struct kvm_sregs *sregs)
5669 {
5670 struct desc_ptr dt;
5671
5672 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5673 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5674 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5675 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5676 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5677 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5678
5679 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5680 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5681
5682 kvm_x86_ops->get_idt(vcpu, &dt);
5683 sregs->idt.limit = dt.size;
5684 sregs->idt.base = dt.address;
5685 kvm_x86_ops->get_gdt(vcpu, &dt);
5686 sregs->gdt.limit = dt.size;
5687 sregs->gdt.base = dt.address;
5688
5689 sregs->cr0 = kvm_read_cr0(vcpu);
5690 sregs->cr2 = vcpu->arch.cr2;
5691 sregs->cr3 = kvm_read_cr3(vcpu);
5692 sregs->cr4 = kvm_read_cr4(vcpu);
5693 sregs->cr8 = kvm_get_cr8(vcpu);
5694 sregs->efer = vcpu->arch.efer;
5695 sregs->apic_base = kvm_get_apic_base(vcpu);
5696
5697 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5698
5699 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5700 set_bit(vcpu->arch.interrupt.nr,
5701 (unsigned long *)sregs->interrupt_bitmap);
5702
5703 return 0;
5704 }
5705
5706 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5707 struct kvm_mp_state *mp_state)
5708 {
5709 mp_state->mp_state = vcpu->arch.mp_state;
5710 return 0;
5711 }
5712
5713 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5714 struct kvm_mp_state *mp_state)
5715 {
5716 vcpu->arch.mp_state = mp_state->mp_state;
5717 kvm_make_request(KVM_REQ_EVENT, vcpu);
5718 return 0;
5719 }
5720
5721 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5722 int reason, bool has_error_code, u32 error_code)
5723 {
5724 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5725 int ret;
5726
5727 init_emulate_ctxt(vcpu);
5728
5729 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
5730 has_error_code, error_code);
5731
5732 if (ret)
5733 return EMULATE_FAIL;
5734
5735 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5736 kvm_rip_write(vcpu, ctxt->eip);
5737 kvm_set_rflags(vcpu, ctxt->eflags);
5738 kvm_make_request(KVM_REQ_EVENT, vcpu);
5739 return EMULATE_DONE;
5740 }
5741 EXPORT_SYMBOL_GPL(kvm_task_switch);
5742
5743 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5744 struct kvm_sregs *sregs)
5745 {
5746 int mmu_reset_needed = 0;
5747 int pending_vec, max_bits, idx;
5748 struct desc_ptr dt;
5749
5750 dt.size = sregs->idt.limit;
5751 dt.address = sregs->idt.base;
5752 kvm_x86_ops->set_idt(vcpu, &dt);
5753 dt.size = sregs->gdt.limit;
5754 dt.address = sregs->gdt.base;
5755 kvm_x86_ops->set_gdt(vcpu, &dt);
5756
5757 vcpu->arch.cr2 = sregs->cr2;
5758 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5759 vcpu->arch.cr3 = sregs->cr3;
5760 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5761
5762 kvm_set_cr8(vcpu, sregs->cr8);
5763
5764 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5765 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5766 kvm_set_apic_base(vcpu, sregs->apic_base);
5767
5768 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5769 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5770 vcpu->arch.cr0 = sregs->cr0;
5771
5772 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5773 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5774 if (sregs->cr4 & X86_CR4_OSXSAVE)
5775 kvm_update_cpuid(vcpu);
5776
5777 idx = srcu_read_lock(&vcpu->kvm->srcu);
5778 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5779 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5780 mmu_reset_needed = 1;
5781 }
5782 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5783
5784 if (mmu_reset_needed)
5785 kvm_mmu_reset_context(vcpu);
5786
5787 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5788 pending_vec = find_first_bit(
5789 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5790 if (pending_vec < max_bits) {
5791 kvm_queue_interrupt(vcpu, pending_vec, false);
5792 pr_debug("Set back pending irq %d\n", pending_vec);
5793 }
5794
5795 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5796 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5797 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5798 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5799 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5800 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5801
5802 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5803 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5804
5805 update_cr8_intercept(vcpu);
5806
5807 /* Older userspace won't unhalt the vcpu on reset. */
5808 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5809 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5810 !is_protmode(vcpu))
5811 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5812
5813 kvm_make_request(KVM_REQ_EVENT, vcpu);
5814
5815 return 0;
5816 }
5817
5818 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5819 struct kvm_guest_debug *dbg)
5820 {
5821 unsigned long rflags;
5822 int i, r;
5823
5824 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5825 r = -EBUSY;
5826 if (vcpu->arch.exception.pending)
5827 goto out;
5828 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5829 kvm_queue_exception(vcpu, DB_VECTOR);
5830 else
5831 kvm_queue_exception(vcpu, BP_VECTOR);
5832 }
5833
5834 /*
5835 * Read rflags as long as potentially injected trace flags are still
5836 * filtered out.
5837 */
5838 rflags = kvm_get_rflags(vcpu);
5839
5840 vcpu->guest_debug = dbg->control;
5841 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5842 vcpu->guest_debug = 0;
5843
5844 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5845 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5846 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5847 vcpu->arch.switch_db_regs =
5848 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5849 } else {
5850 for (i = 0; i < KVM_NR_DB_REGS; i++)
5851 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5852 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5853 }
5854
5855 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5856 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5857 get_segment_base(vcpu, VCPU_SREG_CS);
5858
5859 /*
5860 * Trigger an rflags update that will inject or remove the trace
5861 * flags.
5862 */
5863 kvm_set_rflags(vcpu, rflags);
5864
5865 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5866
5867 r = 0;
5868
5869 out:
5870
5871 return r;
5872 }
5873
5874 /*
5875 * Translate a guest virtual address to a guest physical address.
5876 */
5877 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5878 struct kvm_translation *tr)
5879 {
5880 unsigned long vaddr = tr->linear_address;
5881 gpa_t gpa;
5882 int idx;
5883
5884 idx = srcu_read_lock(&vcpu->kvm->srcu);
5885 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5886 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5887 tr->physical_address = gpa;
5888 tr->valid = gpa != UNMAPPED_GVA;
5889 tr->writeable = 1;
5890 tr->usermode = 0;
5891
5892 return 0;
5893 }
5894
5895 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5896 {
5897 struct i387_fxsave_struct *fxsave =
5898 &vcpu->arch.guest_fpu.state->fxsave;
5899
5900 memcpy(fpu->fpr, fxsave->st_space, 128);
5901 fpu->fcw = fxsave->cwd;
5902 fpu->fsw = fxsave->swd;
5903 fpu->ftwx = fxsave->twd;
5904 fpu->last_opcode = fxsave->fop;
5905 fpu->last_ip = fxsave->rip;
5906 fpu->last_dp = fxsave->rdp;
5907 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5908
5909 return 0;
5910 }
5911
5912 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5913 {
5914 struct i387_fxsave_struct *fxsave =
5915 &vcpu->arch.guest_fpu.state->fxsave;
5916
5917 memcpy(fxsave->st_space, fpu->fpr, 128);
5918 fxsave->cwd = fpu->fcw;
5919 fxsave->swd = fpu->fsw;
5920 fxsave->twd = fpu->ftwx;
5921 fxsave->fop = fpu->last_opcode;
5922 fxsave->rip = fpu->last_ip;
5923 fxsave->rdp = fpu->last_dp;
5924 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5925
5926 return 0;
5927 }
5928
5929 int fx_init(struct kvm_vcpu *vcpu)
5930 {
5931 int err;
5932
5933 err = fpu_alloc(&vcpu->arch.guest_fpu);
5934 if (err)
5935 return err;
5936
5937 fpu_finit(&vcpu->arch.guest_fpu);
5938
5939 /*
5940 * Ensure guest xcr0 is valid for loading
5941 */
5942 vcpu->arch.xcr0 = XSTATE_FP;
5943
5944 vcpu->arch.cr0 |= X86_CR0_ET;
5945
5946 return 0;
5947 }
5948 EXPORT_SYMBOL_GPL(fx_init);
5949
5950 static void fx_free(struct kvm_vcpu *vcpu)
5951 {
5952 fpu_free(&vcpu->arch.guest_fpu);
5953 }
5954
5955 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5956 {
5957 if (vcpu->guest_fpu_loaded)
5958 return;
5959
5960 /*
5961 * Restore all possible states in the guest,
5962 * and assume host would use all available bits.
5963 * Guest xcr0 would be loaded later.
5964 */
5965 kvm_put_guest_xcr0(vcpu);
5966 vcpu->guest_fpu_loaded = 1;
5967 unlazy_fpu(current);
5968 fpu_restore_checking(&vcpu->arch.guest_fpu);
5969 trace_kvm_fpu(1);
5970 }
5971
5972 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5973 {
5974 kvm_put_guest_xcr0(vcpu);
5975
5976 if (!vcpu->guest_fpu_loaded)
5977 return;
5978
5979 vcpu->guest_fpu_loaded = 0;
5980 fpu_save_init(&vcpu->arch.guest_fpu);
5981 ++vcpu->stat.fpu_reload;
5982 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5983 trace_kvm_fpu(0);
5984 }
5985
5986 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5987 {
5988 kvmclock_reset(vcpu);
5989
5990 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5991 fx_free(vcpu);
5992 kvm_x86_ops->vcpu_free(vcpu);
5993 }
5994
5995 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5996 unsigned int id)
5997 {
5998 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5999 printk_once(KERN_WARNING
6000 "kvm: SMP vm created on host with unstable TSC; "
6001 "guest TSC will not be reliable\n");
6002 return kvm_x86_ops->vcpu_create(kvm, id);
6003 }
6004
6005 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6006 {
6007 int r;
6008
6009 vcpu->arch.mtrr_state.have_fixed = 1;
6010 vcpu_load(vcpu);
6011 r = kvm_arch_vcpu_reset(vcpu);
6012 if (r == 0)
6013 r = kvm_mmu_setup(vcpu);
6014 vcpu_put(vcpu);
6015
6016 return r;
6017 }
6018
6019 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6020 {
6021 vcpu->arch.apf.msr_val = 0;
6022
6023 vcpu_load(vcpu);
6024 kvm_mmu_unload(vcpu);
6025 vcpu_put(vcpu);
6026
6027 fx_free(vcpu);
6028 kvm_x86_ops->vcpu_free(vcpu);
6029 }
6030
6031 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6032 {
6033 atomic_set(&vcpu->arch.nmi_queued, 0);
6034 vcpu->arch.nmi_pending = 0;
6035 vcpu->arch.nmi_injected = false;
6036
6037 vcpu->arch.switch_db_regs = 0;
6038 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6039 vcpu->arch.dr6 = DR6_FIXED_1;
6040 vcpu->arch.dr7 = DR7_FIXED_1;
6041
6042 kvm_make_request(KVM_REQ_EVENT, vcpu);
6043 vcpu->arch.apf.msr_val = 0;
6044 vcpu->arch.st.msr_val = 0;
6045
6046 kvmclock_reset(vcpu);
6047
6048 kvm_clear_async_pf_completion_queue(vcpu);
6049 kvm_async_pf_hash_reset(vcpu);
6050 vcpu->arch.apf.halted = false;
6051
6052 kvm_pmu_reset(vcpu);
6053
6054 return kvm_x86_ops->vcpu_reset(vcpu);
6055 }
6056
6057 int kvm_arch_hardware_enable(void *garbage)
6058 {
6059 struct kvm *kvm;
6060 struct kvm_vcpu *vcpu;
6061 int i;
6062 int ret;
6063 u64 local_tsc;
6064 u64 max_tsc = 0;
6065 bool stable, backwards_tsc = false;
6066
6067 kvm_shared_msr_cpu_online();
6068 ret = kvm_x86_ops->hardware_enable(garbage);
6069 if (ret != 0)
6070 return ret;
6071
6072 local_tsc = native_read_tsc();
6073 stable = !check_tsc_unstable();
6074 list_for_each_entry(kvm, &vm_list, vm_list) {
6075 kvm_for_each_vcpu(i, vcpu, kvm) {
6076 if (!stable && vcpu->cpu == smp_processor_id())
6077 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6078 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6079 backwards_tsc = true;
6080 if (vcpu->arch.last_host_tsc > max_tsc)
6081 max_tsc = vcpu->arch.last_host_tsc;
6082 }
6083 }
6084 }
6085
6086 /*
6087 * Sometimes, even reliable TSCs go backwards. This happens on
6088 * platforms that reset TSC during suspend or hibernate actions, but
6089 * maintain synchronization. We must compensate. Fortunately, we can
6090 * detect that condition here, which happens early in CPU bringup,
6091 * before any KVM threads can be running. Unfortunately, we can't
6092 * bring the TSCs fully up to date with real time, as we aren't yet far
6093 * enough into CPU bringup that we know how much real time has actually
6094 * elapsed; our helper function, get_kernel_ns() will be using boot
6095 * variables that haven't been updated yet.
6096 *
6097 * So we simply find the maximum observed TSC above, then record the
6098 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6099 * the adjustment will be applied. Note that we accumulate
6100 * adjustments, in case multiple suspend cycles happen before some VCPU
6101 * gets a chance to run again. In the event that no KVM threads get a
6102 * chance to run, we will miss the entire elapsed period, as we'll have
6103 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6104 * loose cycle time. This isn't too big a deal, since the loss will be
6105 * uniform across all VCPUs (not to mention the scenario is extremely
6106 * unlikely). It is possible that a second hibernate recovery happens
6107 * much faster than a first, causing the observed TSC here to be
6108 * smaller; this would require additional padding adjustment, which is
6109 * why we set last_host_tsc to the local tsc observed here.
6110 *
6111 * N.B. - this code below runs only on platforms with reliable TSC,
6112 * as that is the only way backwards_tsc is set above. Also note
6113 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6114 * have the same delta_cyc adjustment applied if backwards_tsc
6115 * is detected. Note further, this adjustment is only done once,
6116 * as we reset last_host_tsc on all VCPUs to stop this from being
6117 * called multiple times (one for each physical CPU bringup).
6118 *
6119 * Platforms with unnreliable TSCs don't have to deal with this, they
6120 * will be compensated by the logic in vcpu_load, which sets the TSC to
6121 * catchup mode. This will catchup all VCPUs to real time, but cannot
6122 * guarantee that they stay in perfect synchronization.
6123 */
6124 if (backwards_tsc) {
6125 u64 delta_cyc = max_tsc - local_tsc;
6126 list_for_each_entry(kvm, &vm_list, vm_list) {
6127 kvm_for_each_vcpu(i, vcpu, kvm) {
6128 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6129 vcpu->arch.last_host_tsc = local_tsc;
6130 }
6131
6132 /*
6133 * We have to disable TSC offset matching.. if you were
6134 * booting a VM while issuing an S4 host suspend....
6135 * you may have some problem. Solving this issue is
6136 * left as an exercise to the reader.
6137 */
6138 kvm->arch.last_tsc_nsec = 0;
6139 kvm->arch.last_tsc_write = 0;
6140 }
6141
6142 }
6143 return 0;
6144 }
6145
6146 void kvm_arch_hardware_disable(void *garbage)
6147 {
6148 kvm_x86_ops->hardware_disable(garbage);
6149 drop_user_return_notifiers(garbage);
6150 }
6151
6152 int kvm_arch_hardware_setup(void)
6153 {
6154 return kvm_x86_ops->hardware_setup();
6155 }
6156
6157 void kvm_arch_hardware_unsetup(void)
6158 {
6159 kvm_x86_ops->hardware_unsetup();
6160 }
6161
6162 void kvm_arch_check_processor_compat(void *rtn)
6163 {
6164 kvm_x86_ops->check_processor_compatibility(rtn);
6165 }
6166
6167 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6168 {
6169 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6170 }
6171
6172 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6173 {
6174 struct page *page;
6175 struct kvm *kvm;
6176 int r;
6177
6178 BUG_ON(vcpu->kvm == NULL);
6179 kvm = vcpu->kvm;
6180
6181 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6182 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6183 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6184 else
6185 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6186
6187 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6188 if (!page) {
6189 r = -ENOMEM;
6190 goto fail;
6191 }
6192 vcpu->arch.pio_data = page_address(page);
6193
6194 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6195
6196 r = kvm_mmu_create(vcpu);
6197 if (r < 0)
6198 goto fail_free_pio_data;
6199
6200 if (irqchip_in_kernel(kvm)) {
6201 r = kvm_create_lapic(vcpu);
6202 if (r < 0)
6203 goto fail_mmu_destroy;
6204 }
6205
6206 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6207 GFP_KERNEL);
6208 if (!vcpu->arch.mce_banks) {
6209 r = -ENOMEM;
6210 goto fail_free_lapic;
6211 }
6212 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6213
6214 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6215 goto fail_free_mce_banks;
6216
6217 kvm_async_pf_hash_reset(vcpu);
6218 kvm_pmu_init(vcpu);
6219
6220 return 0;
6221 fail_free_mce_banks:
6222 kfree(vcpu->arch.mce_banks);
6223 fail_free_lapic:
6224 kvm_free_lapic(vcpu);
6225 fail_mmu_destroy:
6226 kvm_mmu_destroy(vcpu);
6227 fail_free_pio_data:
6228 free_page((unsigned long)vcpu->arch.pio_data);
6229 fail:
6230 return r;
6231 }
6232
6233 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6234 {
6235 int idx;
6236
6237 kvm_pmu_destroy(vcpu);
6238 kfree(vcpu->arch.mce_banks);
6239 kvm_free_lapic(vcpu);
6240 idx = srcu_read_lock(&vcpu->kvm->srcu);
6241 kvm_mmu_destroy(vcpu);
6242 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6243 free_page((unsigned long)vcpu->arch.pio_data);
6244 }
6245
6246 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6247 {
6248 if (type)
6249 return -EINVAL;
6250
6251 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6252 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6253
6254 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6255 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6256
6257 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6258
6259 return 0;
6260 }
6261
6262 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6263 {
6264 vcpu_load(vcpu);
6265 kvm_mmu_unload(vcpu);
6266 vcpu_put(vcpu);
6267 }
6268
6269 static void kvm_free_vcpus(struct kvm *kvm)
6270 {
6271 unsigned int i;
6272 struct kvm_vcpu *vcpu;
6273
6274 /*
6275 * Unpin any mmu pages first.
6276 */
6277 kvm_for_each_vcpu(i, vcpu, kvm) {
6278 kvm_clear_async_pf_completion_queue(vcpu);
6279 kvm_unload_vcpu_mmu(vcpu);
6280 }
6281 kvm_for_each_vcpu(i, vcpu, kvm)
6282 kvm_arch_vcpu_free(vcpu);
6283
6284 mutex_lock(&kvm->lock);
6285 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6286 kvm->vcpus[i] = NULL;
6287
6288 atomic_set(&kvm->online_vcpus, 0);
6289 mutex_unlock(&kvm->lock);
6290 }
6291
6292 void kvm_arch_sync_events(struct kvm *kvm)
6293 {
6294 kvm_free_all_assigned_devices(kvm);
6295 kvm_free_pit(kvm);
6296 }
6297
6298 void kvm_arch_destroy_vm(struct kvm *kvm)
6299 {
6300 kvm_iommu_unmap_guest(kvm);
6301 kfree(kvm->arch.vpic);
6302 kfree(kvm->arch.vioapic);
6303 kvm_free_vcpus(kvm);
6304 if (kvm->arch.apic_access_page)
6305 put_page(kvm->arch.apic_access_page);
6306 if (kvm->arch.ept_identity_pagetable)
6307 put_page(kvm->arch.ept_identity_pagetable);
6308 }
6309
6310 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6311 struct kvm_memory_slot *dont)
6312 {
6313 int i;
6314
6315 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6316 if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) {
6317 kvm_kvfree(free->arch.lpage_info[i]);
6318 free->arch.lpage_info[i] = NULL;
6319 }
6320 }
6321 }
6322
6323 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6324 {
6325 int i;
6326
6327 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6328 unsigned long ugfn;
6329 int lpages;
6330 int level = i + 2;
6331
6332 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6333 slot->base_gfn, level) + 1;
6334
6335 slot->arch.lpage_info[i] =
6336 kvm_kvzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
6337 if (!slot->arch.lpage_info[i])
6338 goto out_free;
6339
6340 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6341 slot->arch.lpage_info[i][0].write_count = 1;
6342 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6343 slot->arch.lpage_info[i][lpages - 1].write_count = 1;
6344 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6345 /*
6346 * If the gfn and userspace address are not aligned wrt each
6347 * other, or if explicitly asked to, disable large page
6348 * support for this slot
6349 */
6350 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6351 !kvm_largepages_enabled()) {
6352 unsigned long j;
6353
6354 for (j = 0; j < lpages; ++j)
6355 slot->arch.lpage_info[i][j].write_count = 1;
6356 }
6357 }
6358
6359 return 0;
6360
6361 out_free:
6362 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6363 kvm_kvfree(slot->arch.lpage_info[i]);
6364 slot->arch.lpage_info[i] = NULL;
6365 }
6366 return -ENOMEM;
6367 }
6368
6369 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6370 struct kvm_memory_slot *memslot,
6371 struct kvm_memory_slot old,
6372 struct kvm_userspace_memory_region *mem,
6373 int user_alloc)
6374 {
6375 int npages = memslot->npages;
6376 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6377
6378 /* Prevent internal slot pages from being moved by fork()/COW. */
6379 if (memslot->id >= KVM_MEMORY_SLOTS)
6380 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6381
6382 /*To keep backward compatibility with older userspace,
6383 *x86 needs to hanlde !user_alloc case.
6384 */
6385 if (!user_alloc) {
6386 if (npages && !old.rmap) {
6387 unsigned long userspace_addr;
6388
6389 userspace_addr = vm_mmap(NULL, 0,
6390 npages * PAGE_SIZE,
6391 PROT_READ | PROT_WRITE,
6392 map_flags,
6393 0);
6394
6395 if (IS_ERR((void *)userspace_addr))
6396 return PTR_ERR((void *)userspace_addr);
6397
6398 memslot->userspace_addr = userspace_addr;
6399 }
6400 }
6401
6402
6403 return 0;
6404 }
6405
6406 void kvm_arch_commit_memory_region(struct kvm *kvm,
6407 struct kvm_userspace_memory_region *mem,
6408 struct kvm_memory_slot old,
6409 int user_alloc)
6410 {
6411
6412 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6413
6414 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6415 int ret;
6416
6417 ret = vm_munmap(old.userspace_addr,
6418 old.npages * PAGE_SIZE);
6419 if (ret < 0)
6420 printk(KERN_WARNING
6421 "kvm_vm_ioctl_set_memory_region: "
6422 "failed to munmap memory\n");
6423 }
6424
6425 if (!kvm->arch.n_requested_mmu_pages)
6426 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6427
6428 spin_lock(&kvm->mmu_lock);
6429 if (nr_mmu_pages)
6430 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6431 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6432 spin_unlock(&kvm->mmu_lock);
6433 }
6434
6435 void kvm_arch_flush_shadow(struct kvm *kvm)
6436 {
6437 kvm_mmu_zap_all(kvm);
6438 kvm_reload_remote_mmus(kvm);
6439 }
6440
6441 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6442 {
6443 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6444 !vcpu->arch.apf.halted)
6445 || !list_empty_careful(&vcpu->async_pf.done)
6446 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6447 || atomic_read(&vcpu->arch.nmi_queued) ||
6448 (kvm_arch_interrupt_allowed(vcpu) &&
6449 kvm_cpu_has_interrupt(vcpu));
6450 }
6451
6452 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
6453 {
6454 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
6455 }
6456
6457 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6458 {
6459 return kvm_x86_ops->interrupt_allowed(vcpu);
6460 }
6461
6462 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6463 {
6464 unsigned long current_rip = kvm_rip_read(vcpu) +
6465 get_segment_base(vcpu, VCPU_SREG_CS);
6466
6467 return current_rip == linear_rip;
6468 }
6469 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6470
6471 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6472 {
6473 unsigned long rflags;
6474
6475 rflags = kvm_x86_ops->get_rflags(vcpu);
6476 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6477 rflags &= ~X86_EFLAGS_TF;
6478 return rflags;
6479 }
6480 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6481
6482 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6483 {
6484 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6485 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6486 rflags |= X86_EFLAGS_TF;
6487 kvm_x86_ops->set_rflags(vcpu, rflags);
6488 kvm_make_request(KVM_REQ_EVENT, vcpu);
6489 }
6490 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6491
6492 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6493 {
6494 int r;
6495
6496 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6497 is_error_page(work->page))
6498 return;
6499
6500 r = kvm_mmu_reload(vcpu);
6501 if (unlikely(r))
6502 return;
6503
6504 if (!vcpu->arch.mmu.direct_map &&
6505 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6506 return;
6507
6508 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6509 }
6510
6511 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6512 {
6513 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6514 }
6515
6516 static inline u32 kvm_async_pf_next_probe(u32 key)
6517 {
6518 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6519 }
6520
6521 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6522 {
6523 u32 key = kvm_async_pf_hash_fn(gfn);
6524
6525 while (vcpu->arch.apf.gfns[key] != ~0)
6526 key = kvm_async_pf_next_probe(key);
6527
6528 vcpu->arch.apf.gfns[key] = gfn;
6529 }
6530
6531 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6532 {
6533 int i;
6534 u32 key = kvm_async_pf_hash_fn(gfn);
6535
6536 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6537 (vcpu->arch.apf.gfns[key] != gfn &&
6538 vcpu->arch.apf.gfns[key] != ~0); i++)
6539 key = kvm_async_pf_next_probe(key);
6540
6541 return key;
6542 }
6543
6544 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6545 {
6546 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6547 }
6548
6549 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6550 {
6551 u32 i, j, k;
6552
6553 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6554 while (true) {
6555 vcpu->arch.apf.gfns[i] = ~0;
6556 do {
6557 j = kvm_async_pf_next_probe(j);
6558 if (vcpu->arch.apf.gfns[j] == ~0)
6559 return;
6560 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6561 /*
6562 * k lies cyclically in ]i,j]
6563 * | i.k.j |
6564 * |....j i.k.| or |.k..j i...|
6565 */
6566 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6567 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6568 i = j;
6569 }
6570 }
6571
6572 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6573 {
6574
6575 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6576 sizeof(val));
6577 }
6578
6579 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6580 struct kvm_async_pf *work)
6581 {
6582 struct x86_exception fault;
6583
6584 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6585 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6586
6587 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6588 (vcpu->arch.apf.send_user_only &&
6589 kvm_x86_ops->get_cpl(vcpu) == 0))
6590 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6591 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6592 fault.vector = PF_VECTOR;
6593 fault.error_code_valid = true;
6594 fault.error_code = 0;
6595 fault.nested_page_fault = false;
6596 fault.address = work->arch.token;
6597 kvm_inject_page_fault(vcpu, &fault);
6598 }
6599 }
6600
6601 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6602 struct kvm_async_pf *work)
6603 {
6604 struct x86_exception fault;
6605
6606 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6607 if (is_error_page(work->page))
6608 work->arch.token = ~0; /* broadcast wakeup */
6609 else
6610 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6611
6612 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6613 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6614 fault.vector = PF_VECTOR;
6615 fault.error_code_valid = true;
6616 fault.error_code = 0;
6617 fault.nested_page_fault = false;
6618 fault.address = work->arch.token;
6619 kvm_inject_page_fault(vcpu, &fault);
6620 }
6621 vcpu->arch.apf.halted = false;
6622 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6623 }
6624
6625 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6626 {
6627 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6628 return true;
6629 else
6630 return !kvm_event_needs_reinjection(vcpu) &&
6631 kvm_x86_ops->interrupt_allowed(vcpu);
6632 }
6633
6634 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6635 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6636 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6637 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6638 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6639 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6640 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6641 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6642 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6643 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6644 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6645 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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