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[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 bool kvm_has_tsc_control;
98 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99 u32 kvm_max_guest_tsc_khz;
100 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
102 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103 static u32 tsc_tolerance_ppm = 250;
104 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
106 #define KVM_NR_SHARED_MSRS 16
107
108 struct kvm_shared_msrs_global {
109 int nr;
110 u32 msrs[KVM_NR_SHARED_MSRS];
111 };
112
113 struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
120 };
121
122 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123 static struct kvm_shared_msrs __percpu *shared_msrs;
124
125 struct kvm_stats_debugfs_item debugfs_entries[] = {
126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
138 { "hypercalls", VCPU_STAT(hypercalls) },
139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
146 { "irq_injections", VCPU_STAT(irq_injections) },
147 { "nmi_injections", VCPU_STAT(nmi_injections) },
148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
155 { "mmu_unsync", VM_STAT(mmu_unsync) },
156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
157 { "largepages", VM_STAT(lpages) },
158 { NULL }
159 };
160
161 u64 __read_mostly host_xcr0;
162
163 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
164
165 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166 {
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170 }
171
172 static void kvm_on_user_return(struct user_return_notifier *urn)
173 {
174 unsigned slot;
175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
177 struct kvm_shared_msr_values *values;
178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188 }
189
190 static void shared_msr_update(unsigned slot, u32 msr)
191 {
192 u64 value;
193 unsigned int cpu = smp_processor_id();
194 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
195
196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205 }
206
207 void kvm_define_shared_msr(unsigned slot, u32 msr)
208 {
209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
214 }
215 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217 static void kvm_shared_msr_cpu_online(void)
218 {
219 unsigned i;
220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
222 shared_msr_update(i, shared_msrs_global.msrs[i]);
223 }
224
225 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
226 {
227 unsigned int cpu = smp_processor_id();
228 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
229
230 if (((value ^ smsr->values[slot].curr) & mask) == 0)
231 return;
232 smsr->values[slot].curr = value;
233 wrmsrl(shared_msrs_global.msrs[slot], value);
234 if (!smsr->registered) {
235 smsr->urn.on_user_return = kvm_on_user_return;
236 user_return_notifier_register(&smsr->urn);
237 smsr->registered = true;
238 }
239 }
240 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
241
242 static void drop_user_return_notifiers(void *ignore)
243 {
244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249 }
250
251 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252 {
253 return vcpu->arch.apic_base;
254 }
255 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258 {
259 /* TODO: reserve bits check */
260 kvm_lapic_set_base(vcpu, data);
261 }
262 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
264 asmlinkage void kvm_spurious_fault(void)
265 {
266 /* Fault while not rebooting. We want the trace. */
267 BUG();
268 }
269 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
270
271 #define EXCPT_BENIGN 0
272 #define EXCPT_CONTRIBUTORY 1
273 #define EXCPT_PF 2
274
275 static int exception_class(int vector)
276 {
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290 }
291
292 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
293 unsigned nr, bool has_error, u32 error_code,
294 bool reinject)
295 {
296 u32 prev_nr;
297 int class1, class2;
298
299 kvm_make_request(KVM_REQ_EVENT, vcpu);
300
301 if (!vcpu->arch.exception.pending) {
302 queue:
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
307 vcpu->arch.exception.reinject = reinject;
308 return;
309 }
310
311 /* to check exception */
312 prev_nr = vcpu->arch.exception.nr;
313 if (prev_nr == DF_VECTOR) {
314 /* triple fault -> shutdown */
315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
316 return;
317 }
318 class1 = exception_class(prev_nr);
319 class2 = exception_class(nr);
320 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322 /* generate double fault per SDM Table 5-5 */
323 vcpu->arch.exception.pending = true;
324 vcpu->arch.exception.has_error_code = true;
325 vcpu->arch.exception.nr = DF_VECTOR;
326 vcpu->arch.exception.error_code = 0;
327 } else
328 /* replace previous exception with a new one in a hope
329 that instruction re-execution will regenerate lost
330 exception */
331 goto queue;
332 }
333
334 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335 {
336 kvm_multiple_exception(vcpu, nr, false, 0, false);
337 }
338 EXPORT_SYMBOL_GPL(kvm_queue_exception);
339
340 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
341 {
342 kvm_multiple_exception(vcpu, nr, false, 0, true);
343 }
344 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
345
346 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
347 {
348 if (err)
349 kvm_inject_gp(vcpu, 0);
350 else
351 kvm_x86_ops->skip_emulated_instruction(vcpu);
352 }
353 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
354
355 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
356 {
357 ++vcpu->stat.pf_guest;
358 vcpu->arch.cr2 = fault->address;
359 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
360 }
361 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
362
363 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
364 {
365 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
367 else
368 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
369 }
370
371 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
372 {
373 atomic_inc(&vcpu->arch.nmi_queued);
374 kvm_make_request(KVM_REQ_NMI, vcpu);
375 }
376 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
377
378 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379 {
380 kvm_multiple_exception(vcpu, nr, true, error_code, false);
381 }
382 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
383
384 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
385 {
386 kvm_multiple_exception(vcpu, nr, true, error_code, true);
387 }
388 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
389
390 /*
391 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
392 * a #GP and return false.
393 */
394 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
395 {
396 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
397 return true;
398 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
399 return false;
400 }
401 EXPORT_SYMBOL_GPL(kvm_require_cpl);
402
403 /*
404 * This function will be used to read from the physical memory of the currently
405 * running guest. The difference to kvm_read_guest_page is that this function
406 * can read from guest physical or from the guest's guest physical memory.
407 */
408 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409 gfn_t ngfn, void *data, int offset, int len,
410 u32 access)
411 {
412 gfn_t real_gfn;
413 gpa_t ngpa;
414
415 ngpa = gfn_to_gpa(ngfn);
416 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417 if (real_gfn == UNMAPPED_GVA)
418 return -EFAULT;
419
420 real_gfn = gpa_to_gfn(real_gfn);
421
422 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
423 }
424 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
425
426 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427 void *data, int offset, int len, u32 access)
428 {
429 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430 data, offset, len, access);
431 }
432
433 /*
434 * Load the pae pdptrs. Return true is they are all valid.
435 */
436 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
437 {
438 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
440 int i;
441 int ret;
442 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
443
444 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445 offset * sizeof(u64), sizeof(pdpte),
446 PFERR_USER_MASK|PFERR_WRITE_MASK);
447 if (ret < 0) {
448 ret = 0;
449 goto out;
450 }
451 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
452 if (is_present_gpte(pdpte[i]) &&
453 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
454 ret = 0;
455 goto out;
456 }
457 }
458 ret = 1;
459
460 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
461 __set_bit(VCPU_EXREG_PDPTR,
462 (unsigned long *)&vcpu->arch.regs_avail);
463 __set_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_dirty);
465 out:
466
467 return ret;
468 }
469 EXPORT_SYMBOL_GPL(load_pdptrs);
470
471 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
472 {
473 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
474 bool changed = true;
475 int offset;
476 gfn_t gfn;
477 int r;
478
479 if (is_long_mode(vcpu) || !is_pae(vcpu))
480 return false;
481
482 if (!test_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail))
484 return true;
485
486 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
488 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489 PFERR_USER_MASK | PFERR_WRITE_MASK);
490 if (r < 0)
491 goto out;
492 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
493 out:
494
495 return changed;
496 }
497
498 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
499 {
500 unsigned long old_cr0 = kvm_read_cr0(vcpu);
501 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502 X86_CR0_CD | X86_CR0_NW;
503
504 cr0 |= X86_CR0_ET;
505
506 #ifdef CONFIG_X86_64
507 if (cr0 & 0xffffffff00000000UL)
508 return 1;
509 #endif
510
511 cr0 &= ~CR0_RESERVED_BITS;
512
513 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
514 return 1;
515
516 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
517 return 1;
518
519 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
520 #ifdef CONFIG_X86_64
521 if ((vcpu->arch.efer & EFER_LME)) {
522 int cs_db, cs_l;
523
524 if (!is_pae(vcpu))
525 return 1;
526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
527 if (cs_l)
528 return 1;
529 } else
530 #endif
531 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
532 kvm_read_cr3(vcpu)))
533 return 1;
534 }
535
536 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
537 return 1;
538
539 kvm_x86_ops->set_cr0(vcpu, cr0);
540
541 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
542 kvm_clear_async_pf_completion_queue(vcpu);
543 kvm_async_pf_hash_reset(vcpu);
544 }
545
546 if ((cr0 ^ old_cr0) & update_bits)
547 kvm_mmu_reset_context(vcpu);
548 return 0;
549 }
550 EXPORT_SYMBOL_GPL(kvm_set_cr0);
551
552 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
553 {
554 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
555 }
556 EXPORT_SYMBOL_GPL(kvm_lmsw);
557
558 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
559 {
560 u64 xcr0;
561
562 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
563 if (index != XCR_XFEATURE_ENABLED_MASK)
564 return 1;
565 xcr0 = xcr;
566 if (kvm_x86_ops->get_cpl(vcpu) != 0)
567 return 1;
568 if (!(xcr0 & XSTATE_FP))
569 return 1;
570 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
571 return 1;
572 if (xcr0 & ~host_xcr0)
573 return 1;
574 vcpu->arch.xcr0 = xcr0;
575 vcpu->guest_xcr0_loaded = 0;
576 return 0;
577 }
578
579 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
580 {
581 if (__kvm_set_xcr(vcpu, index, xcr)) {
582 kvm_inject_gp(vcpu, 0);
583 return 1;
584 }
585 return 0;
586 }
587 EXPORT_SYMBOL_GPL(kvm_set_xcr);
588
589 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
590 {
591 unsigned long old_cr4 = kvm_read_cr4(vcpu);
592 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
593 X86_CR4_PAE | X86_CR4_SMEP;
594 if (cr4 & CR4_RESERVED_BITS)
595 return 1;
596
597 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
598 return 1;
599
600 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
601 return 1;
602
603 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
604 return 1;
605
606 if (is_long_mode(vcpu)) {
607 if (!(cr4 & X86_CR4_PAE))
608 return 1;
609 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
610 && ((cr4 ^ old_cr4) & pdptr_bits)
611 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
612 kvm_read_cr3(vcpu)))
613 return 1;
614
615 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
616 if (!guest_cpuid_has_pcid(vcpu))
617 return 1;
618
619 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
620 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
621 return 1;
622 }
623
624 if (kvm_x86_ops->set_cr4(vcpu, cr4))
625 return 1;
626
627 if (((cr4 ^ old_cr4) & pdptr_bits) ||
628 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
629 kvm_mmu_reset_context(vcpu);
630
631 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
632 kvm_update_cpuid(vcpu);
633
634 return 0;
635 }
636 EXPORT_SYMBOL_GPL(kvm_set_cr4);
637
638 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
639 {
640 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
641 kvm_mmu_sync_roots(vcpu);
642 kvm_mmu_flush_tlb(vcpu);
643 return 0;
644 }
645
646 if (is_long_mode(vcpu)) {
647 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
648 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
649 return 1;
650 } else
651 if (cr3 & CR3_L_MODE_RESERVED_BITS)
652 return 1;
653 } else {
654 if (is_pae(vcpu)) {
655 if (cr3 & CR3_PAE_RESERVED_BITS)
656 return 1;
657 if (is_paging(vcpu) &&
658 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
659 return 1;
660 }
661 /*
662 * We don't check reserved bits in nonpae mode, because
663 * this isn't enforced, and VMware depends on this.
664 */
665 }
666
667 /*
668 * Does the new cr3 value map to physical memory? (Note, we
669 * catch an invalid cr3 even in real-mode, because it would
670 * cause trouble later on when we turn on paging anyway.)
671 *
672 * A real CPU would silently accept an invalid cr3 and would
673 * attempt to use it - with largely undefined (and often hard
674 * to debug) behavior on the guest side.
675 */
676 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
677 return 1;
678 vcpu->arch.cr3 = cr3;
679 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
680 vcpu->arch.mmu.new_cr3(vcpu);
681 return 0;
682 }
683 EXPORT_SYMBOL_GPL(kvm_set_cr3);
684
685 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
686 {
687 if (cr8 & CR8_RESERVED_BITS)
688 return 1;
689 if (irqchip_in_kernel(vcpu->kvm))
690 kvm_lapic_set_tpr(vcpu, cr8);
691 else
692 vcpu->arch.cr8 = cr8;
693 return 0;
694 }
695 EXPORT_SYMBOL_GPL(kvm_set_cr8);
696
697 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
698 {
699 if (irqchip_in_kernel(vcpu->kvm))
700 return kvm_lapic_get_cr8(vcpu);
701 else
702 return vcpu->arch.cr8;
703 }
704 EXPORT_SYMBOL_GPL(kvm_get_cr8);
705
706 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
707 {
708 unsigned long dr7;
709
710 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
711 dr7 = vcpu->arch.guest_debug_dr7;
712 else
713 dr7 = vcpu->arch.dr7;
714 kvm_x86_ops->set_dr7(vcpu, dr7);
715 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
716 }
717
718 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
719 {
720 switch (dr) {
721 case 0 ... 3:
722 vcpu->arch.db[dr] = val;
723 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
724 vcpu->arch.eff_db[dr] = val;
725 break;
726 case 4:
727 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
728 return 1; /* #UD */
729 /* fall through */
730 case 6:
731 if (val & 0xffffffff00000000ULL)
732 return -1; /* #GP */
733 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
734 break;
735 case 5:
736 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
737 return 1; /* #UD */
738 /* fall through */
739 default: /* 7 */
740 if (val & 0xffffffff00000000ULL)
741 return -1; /* #GP */
742 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
743 kvm_update_dr7(vcpu);
744 break;
745 }
746
747 return 0;
748 }
749
750 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
751 {
752 int res;
753
754 res = __kvm_set_dr(vcpu, dr, val);
755 if (res > 0)
756 kvm_queue_exception(vcpu, UD_VECTOR);
757 else if (res < 0)
758 kvm_inject_gp(vcpu, 0);
759
760 return res;
761 }
762 EXPORT_SYMBOL_GPL(kvm_set_dr);
763
764 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
765 {
766 switch (dr) {
767 case 0 ... 3:
768 *val = vcpu->arch.db[dr];
769 break;
770 case 4:
771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
772 return 1;
773 /* fall through */
774 case 6:
775 *val = vcpu->arch.dr6;
776 break;
777 case 5:
778 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
779 return 1;
780 /* fall through */
781 default: /* 7 */
782 *val = vcpu->arch.dr7;
783 break;
784 }
785
786 return 0;
787 }
788
789 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
790 {
791 if (_kvm_get_dr(vcpu, dr, val)) {
792 kvm_queue_exception(vcpu, UD_VECTOR);
793 return 1;
794 }
795 return 0;
796 }
797 EXPORT_SYMBOL_GPL(kvm_get_dr);
798
799 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
800 {
801 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
802 u64 data;
803 int err;
804
805 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
806 if (err)
807 return err;
808 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
809 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
810 return err;
811 }
812 EXPORT_SYMBOL_GPL(kvm_rdpmc);
813
814 /*
815 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
816 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
817 *
818 * This list is modified at module load time to reflect the
819 * capabilities of the host cpu. This capabilities test skips MSRs that are
820 * kvm-specific. Those are put in the beginning of the list.
821 */
822
823 #define KVM_SAVE_MSRS_BEGIN 10
824 static u32 msrs_to_save[] = {
825 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
826 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
827 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
828 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
829 MSR_KVM_PV_EOI_EN,
830 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
831 MSR_STAR,
832 #ifdef CONFIG_X86_64
833 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
834 #endif
835 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
836 };
837
838 static unsigned num_msrs_to_save;
839
840 static const u32 emulated_msrs[] = {
841 MSR_IA32_TSC_ADJUST,
842 MSR_IA32_TSCDEADLINE,
843 MSR_IA32_MISC_ENABLE,
844 MSR_IA32_MCG_STATUS,
845 MSR_IA32_MCG_CTL,
846 };
847
848 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
849 {
850 if (efer & efer_reserved_bits)
851 return false;
852
853 if (efer & EFER_FFXSR) {
854 struct kvm_cpuid_entry2 *feat;
855
856 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
857 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
858 return false;
859 }
860
861 if (efer & EFER_SVME) {
862 struct kvm_cpuid_entry2 *feat;
863
864 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
865 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
866 return false;
867 }
868
869 return true;
870 }
871 EXPORT_SYMBOL_GPL(kvm_valid_efer);
872
873 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
874 {
875 u64 old_efer = vcpu->arch.efer;
876
877 if (!kvm_valid_efer(vcpu, efer))
878 return 1;
879
880 if (is_paging(vcpu)
881 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
882 return 1;
883
884 efer &= ~EFER_LMA;
885 efer |= vcpu->arch.efer & EFER_LMA;
886
887 kvm_x86_ops->set_efer(vcpu, efer);
888
889 /* Update reserved bits */
890 if ((efer ^ old_efer) & EFER_NX)
891 kvm_mmu_reset_context(vcpu);
892
893 return 0;
894 }
895
896 void kvm_enable_efer_bits(u64 mask)
897 {
898 efer_reserved_bits &= ~mask;
899 }
900 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
901
902
903 /*
904 * Writes msr value into into the appropriate "register".
905 * Returns 0 on success, non-0 otherwise.
906 * Assumes vcpu_load() was already called.
907 */
908 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
909 {
910 return kvm_x86_ops->set_msr(vcpu, msr);
911 }
912
913 /*
914 * Adapt set_msr() to msr_io()'s calling convention
915 */
916 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
917 {
918 struct msr_data msr;
919
920 msr.data = *data;
921 msr.index = index;
922 msr.host_initiated = true;
923 return kvm_set_msr(vcpu, &msr);
924 }
925
926 #ifdef CONFIG_X86_64
927 struct pvclock_gtod_data {
928 seqcount_t seq;
929
930 struct { /* extract of a clocksource struct */
931 int vclock_mode;
932 cycle_t cycle_last;
933 cycle_t mask;
934 u32 mult;
935 u32 shift;
936 } clock;
937
938 /* open coded 'struct timespec' */
939 u64 monotonic_time_snsec;
940 time_t monotonic_time_sec;
941 };
942
943 static struct pvclock_gtod_data pvclock_gtod_data;
944
945 static void update_pvclock_gtod(struct timekeeper *tk)
946 {
947 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
948
949 write_seqcount_begin(&vdata->seq);
950
951 /* copy pvclock gtod data */
952 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
953 vdata->clock.cycle_last = tk->clock->cycle_last;
954 vdata->clock.mask = tk->clock->mask;
955 vdata->clock.mult = tk->mult;
956 vdata->clock.shift = tk->shift;
957
958 vdata->monotonic_time_sec = tk->xtime_sec
959 + tk->wall_to_monotonic.tv_sec;
960 vdata->monotonic_time_snsec = tk->xtime_nsec
961 + (tk->wall_to_monotonic.tv_nsec
962 << tk->shift);
963 while (vdata->monotonic_time_snsec >=
964 (((u64)NSEC_PER_SEC) << tk->shift)) {
965 vdata->monotonic_time_snsec -=
966 ((u64)NSEC_PER_SEC) << tk->shift;
967 vdata->monotonic_time_sec++;
968 }
969
970 write_seqcount_end(&vdata->seq);
971 }
972 #endif
973
974
975 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
976 {
977 int version;
978 int r;
979 struct pvclock_wall_clock wc;
980 struct timespec boot;
981
982 if (!wall_clock)
983 return;
984
985 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
986 if (r)
987 return;
988
989 if (version & 1)
990 ++version; /* first time write, random junk */
991
992 ++version;
993
994 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
995
996 /*
997 * The guest calculates current wall clock time by adding
998 * system time (updated by kvm_guest_time_update below) to the
999 * wall clock specified here. guest system time equals host
1000 * system time for us, thus we must fill in host boot time here.
1001 */
1002 getboottime(&boot);
1003
1004 if (kvm->arch.kvmclock_offset) {
1005 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1006 boot = timespec_sub(boot, ts);
1007 }
1008 wc.sec = boot.tv_sec;
1009 wc.nsec = boot.tv_nsec;
1010 wc.version = version;
1011
1012 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1013
1014 version++;
1015 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1016 }
1017
1018 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1019 {
1020 uint32_t quotient, remainder;
1021
1022 /* Don't try to replace with do_div(), this one calculates
1023 * "(dividend << 32) / divisor" */
1024 __asm__ ( "divl %4"
1025 : "=a" (quotient), "=d" (remainder)
1026 : "0" (0), "1" (dividend), "r" (divisor) );
1027 return quotient;
1028 }
1029
1030 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1031 s8 *pshift, u32 *pmultiplier)
1032 {
1033 uint64_t scaled64;
1034 int32_t shift = 0;
1035 uint64_t tps64;
1036 uint32_t tps32;
1037
1038 tps64 = base_khz * 1000LL;
1039 scaled64 = scaled_khz * 1000LL;
1040 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1041 tps64 >>= 1;
1042 shift--;
1043 }
1044
1045 tps32 = (uint32_t)tps64;
1046 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1047 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1048 scaled64 >>= 1;
1049 else
1050 tps32 <<= 1;
1051 shift++;
1052 }
1053
1054 *pshift = shift;
1055 *pmultiplier = div_frac(scaled64, tps32);
1056
1057 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1058 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1059 }
1060
1061 static inline u64 get_kernel_ns(void)
1062 {
1063 struct timespec ts;
1064
1065 WARN_ON(preemptible());
1066 ktime_get_ts(&ts);
1067 monotonic_to_bootbased(&ts);
1068 return timespec_to_ns(&ts);
1069 }
1070
1071 #ifdef CONFIG_X86_64
1072 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1073 #endif
1074
1075 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1076 unsigned long max_tsc_khz;
1077
1078 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1079 {
1080 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1081 vcpu->arch.virtual_tsc_shift);
1082 }
1083
1084 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1085 {
1086 u64 v = (u64)khz * (1000000 + ppm);
1087 do_div(v, 1000000);
1088 return v;
1089 }
1090
1091 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1092 {
1093 u32 thresh_lo, thresh_hi;
1094 int use_scaling = 0;
1095
1096 /* tsc_khz can be zero if TSC calibration fails */
1097 if (this_tsc_khz == 0)
1098 return;
1099
1100 /* Compute a scale to convert nanoseconds in TSC cycles */
1101 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1102 &vcpu->arch.virtual_tsc_shift,
1103 &vcpu->arch.virtual_tsc_mult);
1104 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1105
1106 /*
1107 * Compute the variation in TSC rate which is acceptable
1108 * within the range of tolerance and decide if the
1109 * rate being applied is within that bounds of the hardware
1110 * rate. If so, no scaling or compensation need be done.
1111 */
1112 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1113 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1114 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1115 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1116 use_scaling = 1;
1117 }
1118 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1119 }
1120
1121 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1122 {
1123 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1124 vcpu->arch.virtual_tsc_mult,
1125 vcpu->arch.virtual_tsc_shift);
1126 tsc += vcpu->arch.this_tsc_write;
1127 return tsc;
1128 }
1129
1130 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1131 {
1132 #ifdef CONFIG_X86_64
1133 bool vcpus_matched;
1134 bool do_request = false;
1135 struct kvm_arch *ka = &vcpu->kvm->arch;
1136 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1137
1138 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1139 atomic_read(&vcpu->kvm->online_vcpus));
1140
1141 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1142 if (!ka->use_master_clock)
1143 do_request = 1;
1144
1145 if (!vcpus_matched && ka->use_master_clock)
1146 do_request = 1;
1147
1148 if (do_request)
1149 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1150
1151 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1152 atomic_read(&vcpu->kvm->online_vcpus),
1153 ka->use_master_clock, gtod->clock.vclock_mode);
1154 #endif
1155 }
1156
1157 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1158 {
1159 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1160 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1161 }
1162
1163 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1164 {
1165 struct kvm *kvm = vcpu->kvm;
1166 u64 offset, ns, elapsed;
1167 unsigned long flags;
1168 s64 usdiff;
1169 bool matched;
1170 u64 data = msr->data;
1171
1172 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1173 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1174 ns = get_kernel_ns();
1175 elapsed = ns - kvm->arch.last_tsc_nsec;
1176
1177 if (vcpu->arch.virtual_tsc_khz) {
1178 /* n.b - signed multiplication and division required */
1179 usdiff = data - kvm->arch.last_tsc_write;
1180 #ifdef CONFIG_X86_64
1181 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1182 #else
1183 /* do_div() only does unsigned */
1184 asm("idivl %2; xor %%edx, %%edx"
1185 : "=A"(usdiff)
1186 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1187 #endif
1188 do_div(elapsed, 1000);
1189 usdiff -= elapsed;
1190 if (usdiff < 0)
1191 usdiff = -usdiff;
1192 } else
1193 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1194
1195 /*
1196 * Special case: TSC write with a small delta (1 second) of virtual
1197 * cycle time against real time is interpreted as an attempt to
1198 * synchronize the CPU.
1199 *
1200 * For a reliable TSC, we can match TSC offsets, and for an unstable
1201 * TSC, we add elapsed time in this computation. We could let the
1202 * compensation code attempt to catch up if we fall behind, but
1203 * it's better to try to match offsets from the beginning.
1204 */
1205 if (usdiff < USEC_PER_SEC &&
1206 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1207 if (!check_tsc_unstable()) {
1208 offset = kvm->arch.cur_tsc_offset;
1209 pr_debug("kvm: matched tsc offset for %llu\n", data);
1210 } else {
1211 u64 delta = nsec_to_cycles(vcpu, elapsed);
1212 data += delta;
1213 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1214 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1215 }
1216 matched = true;
1217 } else {
1218 /*
1219 * We split periods of matched TSC writes into generations.
1220 * For each generation, we track the original measured
1221 * nanosecond time, offset, and write, so if TSCs are in
1222 * sync, we can match exact offset, and if not, we can match
1223 * exact software computation in compute_guest_tsc()
1224 *
1225 * These values are tracked in kvm->arch.cur_xxx variables.
1226 */
1227 kvm->arch.cur_tsc_generation++;
1228 kvm->arch.cur_tsc_nsec = ns;
1229 kvm->arch.cur_tsc_write = data;
1230 kvm->arch.cur_tsc_offset = offset;
1231 matched = false;
1232 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1233 kvm->arch.cur_tsc_generation, data);
1234 }
1235
1236 /*
1237 * We also track th most recent recorded KHZ, write and time to
1238 * allow the matching interval to be extended at each write.
1239 */
1240 kvm->arch.last_tsc_nsec = ns;
1241 kvm->arch.last_tsc_write = data;
1242 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1243
1244 /* Reset of TSC must disable overshoot protection below */
1245 vcpu->arch.hv_clock.tsc_timestamp = 0;
1246 vcpu->arch.last_guest_tsc = data;
1247
1248 /* Keep track of which generation this VCPU has synchronized to */
1249 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1250 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1251 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1252
1253 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1254 update_ia32_tsc_adjust_msr(vcpu, offset);
1255 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1256 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1257
1258 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1259 if (matched)
1260 kvm->arch.nr_vcpus_matched_tsc++;
1261 else
1262 kvm->arch.nr_vcpus_matched_tsc = 0;
1263
1264 kvm_track_tsc_matching(vcpu);
1265 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1266 }
1267
1268 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1269
1270 #ifdef CONFIG_X86_64
1271
1272 static cycle_t read_tsc(void)
1273 {
1274 cycle_t ret;
1275 u64 last;
1276
1277 /*
1278 * Empirically, a fence (of type that depends on the CPU)
1279 * before rdtsc is enough to ensure that rdtsc is ordered
1280 * with respect to loads. The various CPU manuals are unclear
1281 * as to whether rdtsc can be reordered with later loads,
1282 * but no one has ever seen it happen.
1283 */
1284 rdtsc_barrier();
1285 ret = (cycle_t)vget_cycles();
1286
1287 last = pvclock_gtod_data.clock.cycle_last;
1288
1289 if (likely(ret >= last))
1290 return ret;
1291
1292 /*
1293 * GCC likes to generate cmov here, but this branch is extremely
1294 * predictable (it's just a funciton of time and the likely is
1295 * very likely) and there's a data dependence, so force GCC
1296 * to generate a branch instead. I don't barrier() because
1297 * we don't actually need a barrier, and if this function
1298 * ever gets inlined it will generate worse code.
1299 */
1300 asm volatile ("");
1301 return last;
1302 }
1303
1304 static inline u64 vgettsc(cycle_t *cycle_now)
1305 {
1306 long v;
1307 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1308
1309 *cycle_now = read_tsc();
1310
1311 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1312 return v * gtod->clock.mult;
1313 }
1314
1315 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1316 {
1317 unsigned long seq;
1318 u64 ns;
1319 int mode;
1320 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1321
1322 ts->tv_nsec = 0;
1323 do {
1324 seq = read_seqcount_begin(&gtod->seq);
1325 mode = gtod->clock.vclock_mode;
1326 ts->tv_sec = gtod->monotonic_time_sec;
1327 ns = gtod->monotonic_time_snsec;
1328 ns += vgettsc(cycle_now);
1329 ns >>= gtod->clock.shift;
1330 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1331 timespec_add_ns(ts, ns);
1332
1333 return mode;
1334 }
1335
1336 /* returns true if host is using tsc clocksource */
1337 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1338 {
1339 struct timespec ts;
1340
1341 /* checked again under seqlock below */
1342 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1343 return false;
1344
1345 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1346 return false;
1347
1348 monotonic_to_bootbased(&ts);
1349 *kernel_ns = timespec_to_ns(&ts);
1350
1351 return true;
1352 }
1353 #endif
1354
1355 /*
1356 *
1357 * Assuming a stable TSC across physical CPUS, and a stable TSC
1358 * across virtual CPUs, the following condition is possible.
1359 * Each numbered line represents an event visible to both
1360 * CPUs at the next numbered event.
1361 *
1362 * "timespecX" represents host monotonic time. "tscX" represents
1363 * RDTSC value.
1364 *
1365 * VCPU0 on CPU0 | VCPU1 on CPU1
1366 *
1367 * 1. read timespec0,tsc0
1368 * 2. | timespec1 = timespec0 + N
1369 * | tsc1 = tsc0 + M
1370 * 3. transition to guest | transition to guest
1371 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1372 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1373 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1374 *
1375 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1376 *
1377 * - ret0 < ret1
1378 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1379 * ...
1380 * - 0 < N - M => M < N
1381 *
1382 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1383 * always the case (the difference between two distinct xtime instances
1384 * might be smaller then the difference between corresponding TSC reads,
1385 * when updating guest vcpus pvclock areas).
1386 *
1387 * To avoid that problem, do not allow visibility of distinct
1388 * system_timestamp/tsc_timestamp values simultaneously: use a master
1389 * copy of host monotonic time values. Update that master copy
1390 * in lockstep.
1391 *
1392 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1393 *
1394 */
1395
1396 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1397 {
1398 #ifdef CONFIG_X86_64
1399 struct kvm_arch *ka = &kvm->arch;
1400 int vclock_mode;
1401 bool host_tsc_clocksource, vcpus_matched;
1402
1403 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1404 atomic_read(&kvm->online_vcpus));
1405
1406 /*
1407 * If the host uses TSC clock, then passthrough TSC as stable
1408 * to the guest.
1409 */
1410 host_tsc_clocksource = kvm_get_time_and_clockread(
1411 &ka->master_kernel_ns,
1412 &ka->master_cycle_now);
1413
1414 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1415
1416 if (ka->use_master_clock)
1417 atomic_set(&kvm_guest_has_master_clock, 1);
1418
1419 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1420 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1421 vcpus_matched);
1422 #endif
1423 }
1424
1425 static int kvm_guest_time_update(struct kvm_vcpu *v)
1426 {
1427 unsigned long flags, this_tsc_khz;
1428 struct kvm_vcpu_arch *vcpu = &v->arch;
1429 struct kvm_arch *ka = &v->kvm->arch;
1430 s64 kernel_ns, max_kernel_ns;
1431 u64 tsc_timestamp, host_tsc;
1432 struct pvclock_vcpu_time_info guest_hv_clock;
1433 u8 pvclock_flags;
1434 bool use_master_clock;
1435
1436 kernel_ns = 0;
1437 host_tsc = 0;
1438
1439 /*
1440 * If the host uses TSC clock, then passthrough TSC as stable
1441 * to the guest.
1442 */
1443 spin_lock(&ka->pvclock_gtod_sync_lock);
1444 use_master_clock = ka->use_master_clock;
1445 if (use_master_clock) {
1446 host_tsc = ka->master_cycle_now;
1447 kernel_ns = ka->master_kernel_ns;
1448 }
1449 spin_unlock(&ka->pvclock_gtod_sync_lock);
1450
1451 /* Keep irq disabled to prevent changes to the clock */
1452 local_irq_save(flags);
1453 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1454 if (unlikely(this_tsc_khz == 0)) {
1455 local_irq_restore(flags);
1456 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1457 return 1;
1458 }
1459 if (!use_master_clock) {
1460 host_tsc = native_read_tsc();
1461 kernel_ns = get_kernel_ns();
1462 }
1463
1464 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1465
1466 /*
1467 * We may have to catch up the TSC to match elapsed wall clock
1468 * time for two reasons, even if kvmclock is used.
1469 * 1) CPU could have been running below the maximum TSC rate
1470 * 2) Broken TSC compensation resets the base at each VCPU
1471 * entry to avoid unknown leaps of TSC even when running
1472 * again on the same CPU. This may cause apparent elapsed
1473 * time to disappear, and the guest to stand still or run
1474 * very slowly.
1475 */
1476 if (vcpu->tsc_catchup) {
1477 u64 tsc = compute_guest_tsc(v, kernel_ns);
1478 if (tsc > tsc_timestamp) {
1479 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1480 tsc_timestamp = tsc;
1481 }
1482 }
1483
1484 local_irq_restore(flags);
1485
1486 if (!vcpu->pv_time_enabled)
1487 return 0;
1488
1489 /*
1490 * Time as measured by the TSC may go backwards when resetting the base
1491 * tsc_timestamp. The reason for this is that the TSC resolution is
1492 * higher than the resolution of the other clock scales. Thus, many
1493 * possible measurments of the TSC correspond to one measurement of any
1494 * other clock, and so a spread of values is possible. This is not a
1495 * problem for the computation of the nanosecond clock; with TSC rates
1496 * around 1GHZ, there can only be a few cycles which correspond to one
1497 * nanosecond value, and any path through this code will inevitably
1498 * take longer than that. However, with the kernel_ns value itself,
1499 * the precision may be much lower, down to HZ granularity. If the
1500 * first sampling of TSC against kernel_ns ends in the low part of the
1501 * range, and the second in the high end of the range, we can get:
1502 *
1503 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1504 *
1505 * As the sampling errors potentially range in the thousands of cycles,
1506 * it is possible such a time value has already been observed by the
1507 * guest. To protect against this, we must compute the system time as
1508 * observed by the guest and ensure the new system time is greater.
1509 */
1510 max_kernel_ns = 0;
1511 if (vcpu->hv_clock.tsc_timestamp) {
1512 max_kernel_ns = vcpu->last_guest_tsc -
1513 vcpu->hv_clock.tsc_timestamp;
1514 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1515 vcpu->hv_clock.tsc_to_system_mul,
1516 vcpu->hv_clock.tsc_shift);
1517 max_kernel_ns += vcpu->last_kernel_ns;
1518 }
1519
1520 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1521 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1522 &vcpu->hv_clock.tsc_shift,
1523 &vcpu->hv_clock.tsc_to_system_mul);
1524 vcpu->hw_tsc_khz = this_tsc_khz;
1525 }
1526
1527 /* with a master <monotonic time, tsc value> tuple,
1528 * pvclock clock reads always increase at the (scaled) rate
1529 * of guest TSC - no need to deal with sampling errors.
1530 */
1531 if (!use_master_clock) {
1532 if (max_kernel_ns > kernel_ns)
1533 kernel_ns = max_kernel_ns;
1534 }
1535 /* With all the info we got, fill in the values */
1536 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1537 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1538 vcpu->last_kernel_ns = kernel_ns;
1539 vcpu->last_guest_tsc = tsc_timestamp;
1540
1541 /*
1542 * The interface expects us to write an even number signaling that the
1543 * update is finished. Since the guest won't see the intermediate
1544 * state, we just increase by 2 at the end.
1545 */
1546 vcpu->hv_clock.version += 2;
1547
1548 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1549 &guest_hv_clock, sizeof(guest_hv_clock))))
1550 return 0;
1551
1552 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1553 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1554
1555 if (vcpu->pvclock_set_guest_stopped_request) {
1556 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1557 vcpu->pvclock_set_guest_stopped_request = false;
1558 }
1559
1560 /* If the host uses TSC clocksource, then it is stable */
1561 if (use_master_clock)
1562 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1563
1564 vcpu->hv_clock.flags = pvclock_flags;
1565
1566 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1567 &vcpu->hv_clock,
1568 sizeof(vcpu->hv_clock));
1569 return 0;
1570 }
1571
1572 static bool msr_mtrr_valid(unsigned msr)
1573 {
1574 switch (msr) {
1575 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1576 case MSR_MTRRfix64K_00000:
1577 case MSR_MTRRfix16K_80000:
1578 case MSR_MTRRfix16K_A0000:
1579 case MSR_MTRRfix4K_C0000:
1580 case MSR_MTRRfix4K_C8000:
1581 case MSR_MTRRfix4K_D0000:
1582 case MSR_MTRRfix4K_D8000:
1583 case MSR_MTRRfix4K_E0000:
1584 case MSR_MTRRfix4K_E8000:
1585 case MSR_MTRRfix4K_F0000:
1586 case MSR_MTRRfix4K_F8000:
1587 case MSR_MTRRdefType:
1588 case MSR_IA32_CR_PAT:
1589 return true;
1590 case 0x2f8:
1591 return true;
1592 }
1593 return false;
1594 }
1595
1596 static bool valid_pat_type(unsigned t)
1597 {
1598 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1599 }
1600
1601 static bool valid_mtrr_type(unsigned t)
1602 {
1603 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1604 }
1605
1606 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1607 {
1608 int i;
1609
1610 if (!msr_mtrr_valid(msr))
1611 return false;
1612
1613 if (msr == MSR_IA32_CR_PAT) {
1614 for (i = 0; i < 8; i++)
1615 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1616 return false;
1617 return true;
1618 } else if (msr == MSR_MTRRdefType) {
1619 if (data & ~0xcff)
1620 return false;
1621 return valid_mtrr_type(data & 0xff);
1622 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1623 for (i = 0; i < 8 ; i++)
1624 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1625 return false;
1626 return true;
1627 }
1628
1629 /* variable MTRRs */
1630 return valid_mtrr_type(data & 0xff);
1631 }
1632
1633 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1634 {
1635 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1636
1637 if (!mtrr_valid(vcpu, msr, data))
1638 return 1;
1639
1640 if (msr == MSR_MTRRdefType) {
1641 vcpu->arch.mtrr_state.def_type = data;
1642 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1643 } else if (msr == MSR_MTRRfix64K_00000)
1644 p[0] = data;
1645 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1646 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1647 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1648 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1649 else if (msr == MSR_IA32_CR_PAT)
1650 vcpu->arch.pat = data;
1651 else { /* Variable MTRRs */
1652 int idx, is_mtrr_mask;
1653 u64 *pt;
1654
1655 idx = (msr - 0x200) / 2;
1656 is_mtrr_mask = msr - 0x200 - 2 * idx;
1657 if (!is_mtrr_mask)
1658 pt =
1659 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1660 else
1661 pt =
1662 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1663 *pt = data;
1664 }
1665
1666 kvm_mmu_reset_context(vcpu);
1667 return 0;
1668 }
1669
1670 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1671 {
1672 u64 mcg_cap = vcpu->arch.mcg_cap;
1673 unsigned bank_num = mcg_cap & 0xff;
1674
1675 switch (msr) {
1676 case MSR_IA32_MCG_STATUS:
1677 vcpu->arch.mcg_status = data;
1678 break;
1679 case MSR_IA32_MCG_CTL:
1680 if (!(mcg_cap & MCG_CTL_P))
1681 return 1;
1682 if (data != 0 && data != ~(u64)0)
1683 return -1;
1684 vcpu->arch.mcg_ctl = data;
1685 break;
1686 default:
1687 if (msr >= MSR_IA32_MC0_CTL &&
1688 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1689 u32 offset = msr - MSR_IA32_MC0_CTL;
1690 /* only 0 or all 1s can be written to IA32_MCi_CTL
1691 * some Linux kernels though clear bit 10 in bank 4 to
1692 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1693 * this to avoid an uncatched #GP in the guest
1694 */
1695 if ((offset & 0x3) == 0 &&
1696 data != 0 && (data | (1 << 10)) != ~(u64)0)
1697 return -1;
1698 vcpu->arch.mce_banks[offset] = data;
1699 break;
1700 }
1701 return 1;
1702 }
1703 return 0;
1704 }
1705
1706 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1707 {
1708 struct kvm *kvm = vcpu->kvm;
1709 int lm = is_long_mode(vcpu);
1710 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1711 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1712 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1713 : kvm->arch.xen_hvm_config.blob_size_32;
1714 u32 page_num = data & ~PAGE_MASK;
1715 u64 page_addr = data & PAGE_MASK;
1716 u8 *page;
1717 int r;
1718
1719 r = -E2BIG;
1720 if (page_num >= blob_size)
1721 goto out;
1722 r = -ENOMEM;
1723 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1724 if (IS_ERR(page)) {
1725 r = PTR_ERR(page);
1726 goto out;
1727 }
1728 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1729 goto out_free;
1730 r = 0;
1731 out_free:
1732 kfree(page);
1733 out:
1734 return r;
1735 }
1736
1737 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1738 {
1739 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1740 }
1741
1742 static bool kvm_hv_msr_partition_wide(u32 msr)
1743 {
1744 bool r = false;
1745 switch (msr) {
1746 case HV_X64_MSR_GUEST_OS_ID:
1747 case HV_X64_MSR_HYPERCALL:
1748 r = true;
1749 break;
1750 }
1751
1752 return r;
1753 }
1754
1755 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1756 {
1757 struct kvm *kvm = vcpu->kvm;
1758
1759 switch (msr) {
1760 case HV_X64_MSR_GUEST_OS_ID:
1761 kvm->arch.hv_guest_os_id = data;
1762 /* setting guest os id to zero disables hypercall page */
1763 if (!kvm->arch.hv_guest_os_id)
1764 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1765 break;
1766 case HV_X64_MSR_HYPERCALL: {
1767 u64 gfn;
1768 unsigned long addr;
1769 u8 instructions[4];
1770
1771 /* if guest os id is not set hypercall should remain disabled */
1772 if (!kvm->arch.hv_guest_os_id)
1773 break;
1774 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1775 kvm->arch.hv_hypercall = data;
1776 break;
1777 }
1778 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1779 addr = gfn_to_hva(kvm, gfn);
1780 if (kvm_is_error_hva(addr))
1781 return 1;
1782 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1783 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1784 if (__copy_to_user((void __user *)addr, instructions, 4))
1785 return 1;
1786 kvm->arch.hv_hypercall = data;
1787 break;
1788 }
1789 default:
1790 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1791 "data 0x%llx\n", msr, data);
1792 return 1;
1793 }
1794 return 0;
1795 }
1796
1797 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1798 {
1799 switch (msr) {
1800 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1801 unsigned long addr;
1802
1803 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1804 vcpu->arch.hv_vapic = data;
1805 break;
1806 }
1807 addr = gfn_to_hva(vcpu->kvm, data >>
1808 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1809 if (kvm_is_error_hva(addr))
1810 return 1;
1811 if (__clear_user((void __user *)addr, PAGE_SIZE))
1812 return 1;
1813 vcpu->arch.hv_vapic = data;
1814 break;
1815 }
1816 case HV_X64_MSR_EOI:
1817 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1818 case HV_X64_MSR_ICR:
1819 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1820 case HV_X64_MSR_TPR:
1821 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1822 default:
1823 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1824 "data 0x%llx\n", msr, data);
1825 return 1;
1826 }
1827
1828 return 0;
1829 }
1830
1831 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1832 {
1833 gpa_t gpa = data & ~0x3f;
1834
1835 /* Bits 2:5 are reserved, Should be zero */
1836 if (data & 0x3c)
1837 return 1;
1838
1839 vcpu->arch.apf.msr_val = data;
1840
1841 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1842 kvm_clear_async_pf_completion_queue(vcpu);
1843 kvm_async_pf_hash_reset(vcpu);
1844 return 0;
1845 }
1846
1847 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1848 return 1;
1849
1850 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1851 kvm_async_pf_wakeup_all(vcpu);
1852 return 0;
1853 }
1854
1855 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1856 {
1857 vcpu->arch.pv_time_enabled = false;
1858 }
1859
1860 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1861 {
1862 u64 delta;
1863
1864 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1865 return;
1866
1867 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1868 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1869 vcpu->arch.st.accum_steal = delta;
1870 }
1871
1872 static void record_steal_time(struct kvm_vcpu *vcpu)
1873 {
1874 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1875 return;
1876
1877 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1878 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1879 return;
1880
1881 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1882 vcpu->arch.st.steal.version += 2;
1883 vcpu->arch.st.accum_steal = 0;
1884
1885 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1886 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1887 }
1888
1889 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1890 {
1891 bool pr = false;
1892 u32 msr = msr_info->index;
1893 u64 data = msr_info->data;
1894
1895 switch (msr) {
1896 case MSR_AMD64_NB_CFG:
1897 case MSR_IA32_UCODE_REV:
1898 case MSR_IA32_UCODE_WRITE:
1899 case MSR_VM_HSAVE_PA:
1900 case MSR_AMD64_PATCH_LOADER:
1901 case MSR_AMD64_BU_CFG2:
1902 break;
1903
1904 case MSR_EFER:
1905 return set_efer(vcpu, data);
1906 case MSR_K7_HWCR:
1907 data &= ~(u64)0x40; /* ignore flush filter disable */
1908 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1909 data &= ~(u64)0x8; /* ignore TLB cache disable */
1910 if (data != 0) {
1911 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1912 data);
1913 return 1;
1914 }
1915 break;
1916 case MSR_FAM10H_MMIO_CONF_BASE:
1917 if (data != 0) {
1918 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1919 "0x%llx\n", data);
1920 return 1;
1921 }
1922 break;
1923 case MSR_IA32_DEBUGCTLMSR:
1924 if (!data) {
1925 /* We support the non-activated case already */
1926 break;
1927 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1928 /* Values other than LBR and BTF are vendor-specific,
1929 thus reserved and should throw a #GP */
1930 return 1;
1931 }
1932 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1933 __func__, data);
1934 break;
1935 case 0x200 ... 0x2ff:
1936 return set_msr_mtrr(vcpu, msr, data);
1937 case MSR_IA32_APICBASE:
1938 kvm_set_apic_base(vcpu, data);
1939 break;
1940 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1941 return kvm_x2apic_msr_write(vcpu, msr, data);
1942 case MSR_IA32_TSCDEADLINE:
1943 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1944 break;
1945 case MSR_IA32_TSC_ADJUST:
1946 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1947 if (!msr_info->host_initiated) {
1948 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1949 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1950 }
1951 vcpu->arch.ia32_tsc_adjust_msr = data;
1952 }
1953 break;
1954 case MSR_IA32_MISC_ENABLE:
1955 vcpu->arch.ia32_misc_enable_msr = data;
1956 break;
1957 case MSR_KVM_WALL_CLOCK_NEW:
1958 case MSR_KVM_WALL_CLOCK:
1959 vcpu->kvm->arch.wall_clock = data;
1960 kvm_write_wall_clock(vcpu->kvm, data);
1961 break;
1962 case MSR_KVM_SYSTEM_TIME_NEW:
1963 case MSR_KVM_SYSTEM_TIME: {
1964 u64 gpa_offset;
1965 kvmclock_reset(vcpu);
1966
1967 vcpu->arch.time = data;
1968 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1969
1970 /* we verify if the enable bit is set... */
1971 if (!(data & 1))
1972 break;
1973
1974 gpa_offset = data & ~(PAGE_MASK | 1);
1975
1976 /* Check that the address is 32-byte aligned. */
1977 if (gpa_offset & (sizeof(struct pvclock_vcpu_time_info) - 1))
1978 break;
1979
1980 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1981 &vcpu->arch.pv_time, data & ~1ULL))
1982 vcpu->arch.pv_time_enabled = false;
1983 else
1984 vcpu->arch.pv_time_enabled = true;
1985
1986 break;
1987 }
1988 case MSR_KVM_ASYNC_PF_EN:
1989 if (kvm_pv_enable_async_pf(vcpu, data))
1990 return 1;
1991 break;
1992 case MSR_KVM_STEAL_TIME:
1993
1994 if (unlikely(!sched_info_on()))
1995 return 1;
1996
1997 if (data & KVM_STEAL_RESERVED_MASK)
1998 return 1;
1999
2000 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2001 data & KVM_STEAL_VALID_BITS))
2002 return 1;
2003
2004 vcpu->arch.st.msr_val = data;
2005
2006 if (!(data & KVM_MSR_ENABLED))
2007 break;
2008
2009 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2010
2011 preempt_disable();
2012 accumulate_steal_time(vcpu);
2013 preempt_enable();
2014
2015 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2016
2017 break;
2018 case MSR_KVM_PV_EOI_EN:
2019 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2020 return 1;
2021 break;
2022
2023 case MSR_IA32_MCG_CTL:
2024 case MSR_IA32_MCG_STATUS:
2025 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2026 return set_msr_mce(vcpu, msr, data);
2027
2028 /* Performance counters are not protected by a CPUID bit,
2029 * so we should check all of them in the generic path for the sake of
2030 * cross vendor migration.
2031 * Writing a zero into the event select MSRs disables them,
2032 * which we perfectly emulate ;-). Any other value should be at least
2033 * reported, some guests depend on them.
2034 */
2035 case MSR_K7_EVNTSEL0:
2036 case MSR_K7_EVNTSEL1:
2037 case MSR_K7_EVNTSEL2:
2038 case MSR_K7_EVNTSEL3:
2039 if (data != 0)
2040 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2041 "0x%x data 0x%llx\n", msr, data);
2042 break;
2043 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2044 * so we ignore writes to make it happy.
2045 */
2046 case MSR_K7_PERFCTR0:
2047 case MSR_K7_PERFCTR1:
2048 case MSR_K7_PERFCTR2:
2049 case MSR_K7_PERFCTR3:
2050 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2051 "0x%x data 0x%llx\n", msr, data);
2052 break;
2053 case MSR_P6_PERFCTR0:
2054 case MSR_P6_PERFCTR1:
2055 pr = true;
2056 case MSR_P6_EVNTSEL0:
2057 case MSR_P6_EVNTSEL1:
2058 if (kvm_pmu_msr(vcpu, msr))
2059 return kvm_pmu_set_msr(vcpu, msr_info);
2060
2061 if (pr || data != 0)
2062 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2063 "0x%x data 0x%llx\n", msr, data);
2064 break;
2065 case MSR_K7_CLK_CTL:
2066 /*
2067 * Ignore all writes to this no longer documented MSR.
2068 * Writes are only relevant for old K7 processors,
2069 * all pre-dating SVM, but a recommended workaround from
2070 * AMD for these chips. It is possible to specify the
2071 * affected processor models on the command line, hence
2072 * the need to ignore the workaround.
2073 */
2074 break;
2075 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2076 if (kvm_hv_msr_partition_wide(msr)) {
2077 int r;
2078 mutex_lock(&vcpu->kvm->lock);
2079 r = set_msr_hyperv_pw(vcpu, msr, data);
2080 mutex_unlock(&vcpu->kvm->lock);
2081 return r;
2082 } else
2083 return set_msr_hyperv(vcpu, msr, data);
2084 break;
2085 case MSR_IA32_BBL_CR_CTL3:
2086 /* Drop writes to this legacy MSR -- see rdmsr
2087 * counterpart for further detail.
2088 */
2089 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2090 break;
2091 case MSR_AMD64_OSVW_ID_LENGTH:
2092 if (!guest_cpuid_has_osvw(vcpu))
2093 return 1;
2094 vcpu->arch.osvw.length = data;
2095 break;
2096 case MSR_AMD64_OSVW_STATUS:
2097 if (!guest_cpuid_has_osvw(vcpu))
2098 return 1;
2099 vcpu->arch.osvw.status = data;
2100 break;
2101 default:
2102 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2103 return xen_hvm_config(vcpu, data);
2104 if (kvm_pmu_msr(vcpu, msr))
2105 return kvm_pmu_set_msr(vcpu, msr_info);
2106 if (!ignore_msrs) {
2107 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2108 msr, data);
2109 return 1;
2110 } else {
2111 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2112 msr, data);
2113 break;
2114 }
2115 }
2116 return 0;
2117 }
2118 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2119
2120
2121 /*
2122 * Reads an msr value (of 'msr_index') into 'pdata'.
2123 * Returns 0 on success, non-0 otherwise.
2124 * Assumes vcpu_load() was already called.
2125 */
2126 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2127 {
2128 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2129 }
2130
2131 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2132 {
2133 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2134
2135 if (!msr_mtrr_valid(msr))
2136 return 1;
2137
2138 if (msr == MSR_MTRRdefType)
2139 *pdata = vcpu->arch.mtrr_state.def_type +
2140 (vcpu->arch.mtrr_state.enabled << 10);
2141 else if (msr == MSR_MTRRfix64K_00000)
2142 *pdata = p[0];
2143 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2144 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2145 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2146 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2147 else if (msr == MSR_IA32_CR_PAT)
2148 *pdata = vcpu->arch.pat;
2149 else { /* Variable MTRRs */
2150 int idx, is_mtrr_mask;
2151 u64 *pt;
2152
2153 idx = (msr - 0x200) / 2;
2154 is_mtrr_mask = msr - 0x200 - 2 * idx;
2155 if (!is_mtrr_mask)
2156 pt =
2157 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2158 else
2159 pt =
2160 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2161 *pdata = *pt;
2162 }
2163
2164 return 0;
2165 }
2166
2167 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2168 {
2169 u64 data;
2170 u64 mcg_cap = vcpu->arch.mcg_cap;
2171 unsigned bank_num = mcg_cap & 0xff;
2172
2173 switch (msr) {
2174 case MSR_IA32_P5_MC_ADDR:
2175 case MSR_IA32_P5_MC_TYPE:
2176 data = 0;
2177 break;
2178 case MSR_IA32_MCG_CAP:
2179 data = vcpu->arch.mcg_cap;
2180 break;
2181 case MSR_IA32_MCG_CTL:
2182 if (!(mcg_cap & MCG_CTL_P))
2183 return 1;
2184 data = vcpu->arch.mcg_ctl;
2185 break;
2186 case MSR_IA32_MCG_STATUS:
2187 data = vcpu->arch.mcg_status;
2188 break;
2189 default:
2190 if (msr >= MSR_IA32_MC0_CTL &&
2191 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2192 u32 offset = msr - MSR_IA32_MC0_CTL;
2193 data = vcpu->arch.mce_banks[offset];
2194 break;
2195 }
2196 return 1;
2197 }
2198 *pdata = data;
2199 return 0;
2200 }
2201
2202 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2203 {
2204 u64 data = 0;
2205 struct kvm *kvm = vcpu->kvm;
2206
2207 switch (msr) {
2208 case HV_X64_MSR_GUEST_OS_ID:
2209 data = kvm->arch.hv_guest_os_id;
2210 break;
2211 case HV_X64_MSR_HYPERCALL:
2212 data = kvm->arch.hv_hypercall;
2213 break;
2214 default:
2215 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2216 return 1;
2217 }
2218
2219 *pdata = data;
2220 return 0;
2221 }
2222
2223 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2224 {
2225 u64 data = 0;
2226
2227 switch (msr) {
2228 case HV_X64_MSR_VP_INDEX: {
2229 int r;
2230 struct kvm_vcpu *v;
2231 kvm_for_each_vcpu(r, v, vcpu->kvm)
2232 if (v == vcpu)
2233 data = r;
2234 break;
2235 }
2236 case HV_X64_MSR_EOI:
2237 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2238 case HV_X64_MSR_ICR:
2239 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2240 case HV_X64_MSR_TPR:
2241 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2242 case HV_X64_MSR_APIC_ASSIST_PAGE:
2243 data = vcpu->arch.hv_vapic;
2244 break;
2245 default:
2246 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2247 return 1;
2248 }
2249 *pdata = data;
2250 return 0;
2251 }
2252
2253 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2254 {
2255 u64 data;
2256
2257 switch (msr) {
2258 case MSR_IA32_PLATFORM_ID:
2259 case MSR_IA32_EBL_CR_POWERON:
2260 case MSR_IA32_DEBUGCTLMSR:
2261 case MSR_IA32_LASTBRANCHFROMIP:
2262 case MSR_IA32_LASTBRANCHTOIP:
2263 case MSR_IA32_LASTINTFROMIP:
2264 case MSR_IA32_LASTINTTOIP:
2265 case MSR_K8_SYSCFG:
2266 case MSR_K7_HWCR:
2267 case MSR_VM_HSAVE_PA:
2268 case MSR_K7_EVNTSEL0:
2269 case MSR_K7_PERFCTR0:
2270 case MSR_K8_INT_PENDING_MSG:
2271 case MSR_AMD64_NB_CFG:
2272 case MSR_FAM10H_MMIO_CONF_BASE:
2273 case MSR_AMD64_BU_CFG2:
2274 data = 0;
2275 break;
2276 case MSR_P6_PERFCTR0:
2277 case MSR_P6_PERFCTR1:
2278 case MSR_P6_EVNTSEL0:
2279 case MSR_P6_EVNTSEL1:
2280 if (kvm_pmu_msr(vcpu, msr))
2281 return kvm_pmu_get_msr(vcpu, msr, pdata);
2282 data = 0;
2283 break;
2284 case MSR_IA32_UCODE_REV:
2285 data = 0x100000000ULL;
2286 break;
2287 case MSR_MTRRcap:
2288 data = 0x500 | KVM_NR_VAR_MTRR;
2289 break;
2290 case 0x200 ... 0x2ff:
2291 return get_msr_mtrr(vcpu, msr, pdata);
2292 case 0xcd: /* fsb frequency */
2293 data = 3;
2294 break;
2295 /*
2296 * MSR_EBC_FREQUENCY_ID
2297 * Conservative value valid for even the basic CPU models.
2298 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2299 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2300 * and 266MHz for model 3, or 4. Set Core Clock
2301 * Frequency to System Bus Frequency Ratio to 1 (bits
2302 * 31:24) even though these are only valid for CPU
2303 * models > 2, however guests may end up dividing or
2304 * multiplying by zero otherwise.
2305 */
2306 case MSR_EBC_FREQUENCY_ID:
2307 data = 1 << 24;
2308 break;
2309 case MSR_IA32_APICBASE:
2310 data = kvm_get_apic_base(vcpu);
2311 break;
2312 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2313 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2314 break;
2315 case MSR_IA32_TSCDEADLINE:
2316 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2317 break;
2318 case MSR_IA32_TSC_ADJUST:
2319 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2320 break;
2321 case MSR_IA32_MISC_ENABLE:
2322 data = vcpu->arch.ia32_misc_enable_msr;
2323 break;
2324 case MSR_IA32_PERF_STATUS:
2325 /* TSC increment by tick */
2326 data = 1000ULL;
2327 /* CPU multiplier */
2328 data |= (((uint64_t)4ULL) << 40);
2329 break;
2330 case MSR_EFER:
2331 data = vcpu->arch.efer;
2332 break;
2333 case MSR_KVM_WALL_CLOCK:
2334 case MSR_KVM_WALL_CLOCK_NEW:
2335 data = vcpu->kvm->arch.wall_clock;
2336 break;
2337 case MSR_KVM_SYSTEM_TIME:
2338 case MSR_KVM_SYSTEM_TIME_NEW:
2339 data = vcpu->arch.time;
2340 break;
2341 case MSR_KVM_ASYNC_PF_EN:
2342 data = vcpu->arch.apf.msr_val;
2343 break;
2344 case MSR_KVM_STEAL_TIME:
2345 data = vcpu->arch.st.msr_val;
2346 break;
2347 case MSR_KVM_PV_EOI_EN:
2348 data = vcpu->arch.pv_eoi.msr_val;
2349 break;
2350 case MSR_IA32_P5_MC_ADDR:
2351 case MSR_IA32_P5_MC_TYPE:
2352 case MSR_IA32_MCG_CAP:
2353 case MSR_IA32_MCG_CTL:
2354 case MSR_IA32_MCG_STATUS:
2355 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2356 return get_msr_mce(vcpu, msr, pdata);
2357 case MSR_K7_CLK_CTL:
2358 /*
2359 * Provide expected ramp-up count for K7. All other
2360 * are set to zero, indicating minimum divisors for
2361 * every field.
2362 *
2363 * This prevents guest kernels on AMD host with CPU
2364 * type 6, model 8 and higher from exploding due to
2365 * the rdmsr failing.
2366 */
2367 data = 0x20000000;
2368 break;
2369 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2370 if (kvm_hv_msr_partition_wide(msr)) {
2371 int r;
2372 mutex_lock(&vcpu->kvm->lock);
2373 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2374 mutex_unlock(&vcpu->kvm->lock);
2375 return r;
2376 } else
2377 return get_msr_hyperv(vcpu, msr, pdata);
2378 break;
2379 case MSR_IA32_BBL_CR_CTL3:
2380 /* This legacy MSR exists but isn't fully documented in current
2381 * silicon. It is however accessed by winxp in very narrow
2382 * scenarios where it sets bit #19, itself documented as
2383 * a "reserved" bit. Best effort attempt to source coherent
2384 * read data here should the balance of the register be
2385 * interpreted by the guest:
2386 *
2387 * L2 cache control register 3: 64GB range, 256KB size,
2388 * enabled, latency 0x1, configured
2389 */
2390 data = 0xbe702111;
2391 break;
2392 case MSR_AMD64_OSVW_ID_LENGTH:
2393 if (!guest_cpuid_has_osvw(vcpu))
2394 return 1;
2395 data = vcpu->arch.osvw.length;
2396 break;
2397 case MSR_AMD64_OSVW_STATUS:
2398 if (!guest_cpuid_has_osvw(vcpu))
2399 return 1;
2400 data = vcpu->arch.osvw.status;
2401 break;
2402 default:
2403 if (kvm_pmu_msr(vcpu, msr))
2404 return kvm_pmu_get_msr(vcpu, msr, pdata);
2405 if (!ignore_msrs) {
2406 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2407 return 1;
2408 } else {
2409 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2410 data = 0;
2411 }
2412 break;
2413 }
2414 *pdata = data;
2415 return 0;
2416 }
2417 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2418
2419 /*
2420 * Read or write a bunch of msrs. All parameters are kernel addresses.
2421 *
2422 * @return number of msrs set successfully.
2423 */
2424 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2425 struct kvm_msr_entry *entries,
2426 int (*do_msr)(struct kvm_vcpu *vcpu,
2427 unsigned index, u64 *data))
2428 {
2429 int i, idx;
2430
2431 idx = srcu_read_lock(&vcpu->kvm->srcu);
2432 for (i = 0; i < msrs->nmsrs; ++i)
2433 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2434 break;
2435 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2436
2437 return i;
2438 }
2439
2440 /*
2441 * Read or write a bunch of msrs. Parameters are user addresses.
2442 *
2443 * @return number of msrs set successfully.
2444 */
2445 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2446 int (*do_msr)(struct kvm_vcpu *vcpu,
2447 unsigned index, u64 *data),
2448 int writeback)
2449 {
2450 struct kvm_msrs msrs;
2451 struct kvm_msr_entry *entries;
2452 int r, n;
2453 unsigned size;
2454
2455 r = -EFAULT;
2456 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2457 goto out;
2458
2459 r = -E2BIG;
2460 if (msrs.nmsrs >= MAX_IO_MSRS)
2461 goto out;
2462
2463 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2464 entries = memdup_user(user_msrs->entries, size);
2465 if (IS_ERR(entries)) {
2466 r = PTR_ERR(entries);
2467 goto out;
2468 }
2469
2470 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2471 if (r < 0)
2472 goto out_free;
2473
2474 r = -EFAULT;
2475 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2476 goto out_free;
2477
2478 r = n;
2479
2480 out_free:
2481 kfree(entries);
2482 out:
2483 return r;
2484 }
2485
2486 int kvm_dev_ioctl_check_extension(long ext)
2487 {
2488 int r;
2489
2490 switch (ext) {
2491 case KVM_CAP_IRQCHIP:
2492 case KVM_CAP_HLT:
2493 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2494 case KVM_CAP_SET_TSS_ADDR:
2495 case KVM_CAP_EXT_CPUID:
2496 case KVM_CAP_CLOCKSOURCE:
2497 case KVM_CAP_PIT:
2498 case KVM_CAP_NOP_IO_DELAY:
2499 case KVM_CAP_MP_STATE:
2500 case KVM_CAP_SYNC_MMU:
2501 case KVM_CAP_USER_NMI:
2502 case KVM_CAP_REINJECT_CONTROL:
2503 case KVM_CAP_IRQ_INJECT_STATUS:
2504 case KVM_CAP_IRQFD:
2505 case KVM_CAP_IOEVENTFD:
2506 case KVM_CAP_PIT2:
2507 case KVM_CAP_PIT_STATE2:
2508 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2509 case KVM_CAP_XEN_HVM:
2510 case KVM_CAP_ADJUST_CLOCK:
2511 case KVM_CAP_VCPU_EVENTS:
2512 case KVM_CAP_HYPERV:
2513 case KVM_CAP_HYPERV_VAPIC:
2514 case KVM_CAP_HYPERV_SPIN:
2515 case KVM_CAP_PCI_SEGMENT:
2516 case KVM_CAP_DEBUGREGS:
2517 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2518 case KVM_CAP_XSAVE:
2519 case KVM_CAP_ASYNC_PF:
2520 case KVM_CAP_GET_TSC_KHZ:
2521 case KVM_CAP_KVMCLOCK_CTRL:
2522 case KVM_CAP_READONLY_MEM:
2523 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2524 case KVM_CAP_ASSIGN_DEV_IRQ:
2525 case KVM_CAP_PCI_2_3:
2526 #endif
2527 r = 1;
2528 break;
2529 case KVM_CAP_COALESCED_MMIO:
2530 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2531 break;
2532 case KVM_CAP_VAPIC:
2533 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2534 break;
2535 case KVM_CAP_NR_VCPUS:
2536 r = KVM_SOFT_MAX_VCPUS;
2537 break;
2538 case KVM_CAP_MAX_VCPUS:
2539 r = KVM_MAX_VCPUS;
2540 break;
2541 case KVM_CAP_NR_MEMSLOTS:
2542 r = KVM_USER_MEM_SLOTS;
2543 break;
2544 case KVM_CAP_PV_MMU: /* obsolete */
2545 r = 0;
2546 break;
2547 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2548 case KVM_CAP_IOMMU:
2549 r = iommu_present(&pci_bus_type);
2550 break;
2551 #endif
2552 case KVM_CAP_MCE:
2553 r = KVM_MAX_MCE_BANKS;
2554 break;
2555 case KVM_CAP_XCRS:
2556 r = cpu_has_xsave;
2557 break;
2558 case KVM_CAP_TSC_CONTROL:
2559 r = kvm_has_tsc_control;
2560 break;
2561 case KVM_CAP_TSC_DEADLINE_TIMER:
2562 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2563 break;
2564 default:
2565 r = 0;
2566 break;
2567 }
2568 return r;
2569
2570 }
2571
2572 long kvm_arch_dev_ioctl(struct file *filp,
2573 unsigned int ioctl, unsigned long arg)
2574 {
2575 void __user *argp = (void __user *)arg;
2576 long r;
2577
2578 switch (ioctl) {
2579 case KVM_GET_MSR_INDEX_LIST: {
2580 struct kvm_msr_list __user *user_msr_list = argp;
2581 struct kvm_msr_list msr_list;
2582 unsigned n;
2583
2584 r = -EFAULT;
2585 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2586 goto out;
2587 n = msr_list.nmsrs;
2588 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2589 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2590 goto out;
2591 r = -E2BIG;
2592 if (n < msr_list.nmsrs)
2593 goto out;
2594 r = -EFAULT;
2595 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2596 num_msrs_to_save * sizeof(u32)))
2597 goto out;
2598 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2599 &emulated_msrs,
2600 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2601 goto out;
2602 r = 0;
2603 break;
2604 }
2605 case KVM_GET_SUPPORTED_CPUID: {
2606 struct kvm_cpuid2 __user *cpuid_arg = argp;
2607 struct kvm_cpuid2 cpuid;
2608
2609 r = -EFAULT;
2610 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2611 goto out;
2612 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2613 cpuid_arg->entries);
2614 if (r)
2615 goto out;
2616
2617 r = -EFAULT;
2618 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2619 goto out;
2620 r = 0;
2621 break;
2622 }
2623 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2624 u64 mce_cap;
2625
2626 mce_cap = KVM_MCE_CAP_SUPPORTED;
2627 r = -EFAULT;
2628 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2629 goto out;
2630 r = 0;
2631 break;
2632 }
2633 default:
2634 r = -EINVAL;
2635 }
2636 out:
2637 return r;
2638 }
2639
2640 static void wbinvd_ipi(void *garbage)
2641 {
2642 wbinvd();
2643 }
2644
2645 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2646 {
2647 return vcpu->kvm->arch.iommu_domain &&
2648 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2649 }
2650
2651 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2652 {
2653 /* Address WBINVD may be executed by guest */
2654 if (need_emulate_wbinvd(vcpu)) {
2655 if (kvm_x86_ops->has_wbinvd_exit())
2656 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2657 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2658 smp_call_function_single(vcpu->cpu,
2659 wbinvd_ipi, NULL, 1);
2660 }
2661
2662 kvm_x86_ops->vcpu_load(vcpu, cpu);
2663
2664 /* Apply any externally detected TSC adjustments (due to suspend) */
2665 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2666 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2667 vcpu->arch.tsc_offset_adjustment = 0;
2668 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2669 }
2670
2671 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2672 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2673 native_read_tsc() - vcpu->arch.last_host_tsc;
2674 if (tsc_delta < 0)
2675 mark_tsc_unstable("KVM discovered backwards TSC");
2676 if (check_tsc_unstable()) {
2677 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2678 vcpu->arch.last_guest_tsc);
2679 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2680 vcpu->arch.tsc_catchup = 1;
2681 }
2682 /*
2683 * On a host with synchronized TSC, there is no need to update
2684 * kvmclock on vcpu->cpu migration
2685 */
2686 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2687 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2688 if (vcpu->cpu != cpu)
2689 kvm_migrate_timers(vcpu);
2690 vcpu->cpu = cpu;
2691 }
2692
2693 accumulate_steal_time(vcpu);
2694 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2695 }
2696
2697 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2698 {
2699 kvm_x86_ops->vcpu_put(vcpu);
2700 kvm_put_guest_fpu(vcpu);
2701 vcpu->arch.last_host_tsc = native_read_tsc();
2702 }
2703
2704 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2705 struct kvm_lapic_state *s)
2706 {
2707 kvm_x86_ops->sync_pir_to_irr(vcpu);
2708 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2709
2710 return 0;
2711 }
2712
2713 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2714 struct kvm_lapic_state *s)
2715 {
2716 kvm_apic_post_state_restore(vcpu, s);
2717 update_cr8_intercept(vcpu);
2718
2719 return 0;
2720 }
2721
2722 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2723 struct kvm_interrupt *irq)
2724 {
2725 if (irq->irq >= KVM_NR_INTERRUPTS)
2726 return -EINVAL;
2727 if (irqchip_in_kernel(vcpu->kvm))
2728 return -ENXIO;
2729
2730 kvm_queue_interrupt(vcpu, irq->irq, false);
2731 kvm_make_request(KVM_REQ_EVENT, vcpu);
2732
2733 return 0;
2734 }
2735
2736 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2737 {
2738 kvm_inject_nmi(vcpu);
2739
2740 return 0;
2741 }
2742
2743 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2744 struct kvm_tpr_access_ctl *tac)
2745 {
2746 if (tac->flags)
2747 return -EINVAL;
2748 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2749 return 0;
2750 }
2751
2752 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2753 u64 mcg_cap)
2754 {
2755 int r;
2756 unsigned bank_num = mcg_cap & 0xff, bank;
2757
2758 r = -EINVAL;
2759 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2760 goto out;
2761 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2762 goto out;
2763 r = 0;
2764 vcpu->arch.mcg_cap = mcg_cap;
2765 /* Init IA32_MCG_CTL to all 1s */
2766 if (mcg_cap & MCG_CTL_P)
2767 vcpu->arch.mcg_ctl = ~(u64)0;
2768 /* Init IA32_MCi_CTL to all 1s */
2769 for (bank = 0; bank < bank_num; bank++)
2770 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2771 out:
2772 return r;
2773 }
2774
2775 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2776 struct kvm_x86_mce *mce)
2777 {
2778 u64 mcg_cap = vcpu->arch.mcg_cap;
2779 unsigned bank_num = mcg_cap & 0xff;
2780 u64 *banks = vcpu->arch.mce_banks;
2781
2782 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2783 return -EINVAL;
2784 /*
2785 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2786 * reporting is disabled
2787 */
2788 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2789 vcpu->arch.mcg_ctl != ~(u64)0)
2790 return 0;
2791 banks += 4 * mce->bank;
2792 /*
2793 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2794 * reporting is disabled for the bank
2795 */
2796 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2797 return 0;
2798 if (mce->status & MCI_STATUS_UC) {
2799 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2800 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2801 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2802 return 0;
2803 }
2804 if (banks[1] & MCI_STATUS_VAL)
2805 mce->status |= MCI_STATUS_OVER;
2806 banks[2] = mce->addr;
2807 banks[3] = mce->misc;
2808 vcpu->arch.mcg_status = mce->mcg_status;
2809 banks[1] = mce->status;
2810 kvm_queue_exception(vcpu, MC_VECTOR);
2811 } else if (!(banks[1] & MCI_STATUS_VAL)
2812 || !(banks[1] & MCI_STATUS_UC)) {
2813 if (banks[1] & MCI_STATUS_VAL)
2814 mce->status |= MCI_STATUS_OVER;
2815 banks[2] = mce->addr;
2816 banks[3] = mce->misc;
2817 banks[1] = mce->status;
2818 } else
2819 banks[1] |= MCI_STATUS_OVER;
2820 return 0;
2821 }
2822
2823 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2824 struct kvm_vcpu_events *events)
2825 {
2826 process_nmi(vcpu);
2827 events->exception.injected =
2828 vcpu->arch.exception.pending &&
2829 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2830 events->exception.nr = vcpu->arch.exception.nr;
2831 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2832 events->exception.pad = 0;
2833 events->exception.error_code = vcpu->arch.exception.error_code;
2834
2835 events->interrupt.injected =
2836 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2837 events->interrupt.nr = vcpu->arch.interrupt.nr;
2838 events->interrupt.soft = 0;
2839 events->interrupt.shadow =
2840 kvm_x86_ops->get_interrupt_shadow(vcpu,
2841 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2842
2843 events->nmi.injected = vcpu->arch.nmi_injected;
2844 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2845 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2846 events->nmi.pad = 0;
2847
2848 events->sipi_vector = 0; /* never valid when reporting to user space */
2849
2850 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2851 | KVM_VCPUEVENT_VALID_SHADOW);
2852 memset(&events->reserved, 0, sizeof(events->reserved));
2853 }
2854
2855 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2856 struct kvm_vcpu_events *events)
2857 {
2858 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2859 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2860 | KVM_VCPUEVENT_VALID_SHADOW))
2861 return -EINVAL;
2862
2863 process_nmi(vcpu);
2864 vcpu->arch.exception.pending = events->exception.injected;
2865 vcpu->arch.exception.nr = events->exception.nr;
2866 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2867 vcpu->arch.exception.error_code = events->exception.error_code;
2868
2869 vcpu->arch.interrupt.pending = events->interrupt.injected;
2870 vcpu->arch.interrupt.nr = events->interrupt.nr;
2871 vcpu->arch.interrupt.soft = events->interrupt.soft;
2872 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2873 kvm_x86_ops->set_interrupt_shadow(vcpu,
2874 events->interrupt.shadow);
2875
2876 vcpu->arch.nmi_injected = events->nmi.injected;
2877 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2878 vcpu->arch.nmi_pending = events->nmi.pending;
2879 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2880
2881 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2882 kvm_vcpu_has_lapic(vcpu))
2883 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2884
2885 kvm_make_request(KVM_REQ_EVENT, vcpu);
2886
2887 return 0;
2888 }
2889
2890 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2891 struct kvm_debugregs *dbgregs)
2892 {
2893 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2894 dbgregs->dr6 = vcpu->arch.dr6;
2895 dbgregs->dr7 = vcpu->arch.dr7;
2896 dbgregs->flags = 0;
2897 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2898 }
2899
2900 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2901 struct kvm_debugregs *dbgregs)
2902 {
2903 if (dbgregs->flags)
2904 return -EINVAL;
2905
2906 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2907 vcpu->arch.dr6 = dbgregs->dr6;
2908 vcpu->arch.dr7 = dbgregs->dr7;
2909
2910 return 0;
2911 }
2912
2913 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2914 struct kvm_xsave *guest_xsave)
2915 {
2916 if (cpu_has_xsave)
2917 memcpy(guest_xsave->region,
2918 &vcpu->arch.guest_fpu.state->xsave,
2919 xstate_size);
2920 else {
2921 memcpy(guest_xsave->region,
2922 &vcpu->arch.guest_fpu.state->fxsave,
2923 sizeof(struct i387_fxsave_struct));
2924 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2925 XSTATE_FPSSE;
2926 }
2927 }
2928
2929 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2930 struct kvm_xsave *guest_xsave)
2931 {
2932 u64 xstate_bv =
2933 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2934
2935 if (cpu_has_xsave)
2936 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2937 guest_xsave->region, xstate_size);
2938 else {
2939 if (xstate_bv & ~XSTATE_FPSSE)
2940 return -EINVAL;
2941 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2942 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2943 }
2944 return 0;
2945 }
2946
2947 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2948 struct kvm_xcrs *guest_xcrs)
2949 {
2950 if (!cpu_has_xsave) {
2951 guest_xcrs->nr_xcrs = 0;
2952 return;
2953 }
2954
2955 guest_xcrs->nr_xcrs = 1;
2956 guest_xcrs->flags = 0;
2957 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2958 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2959 }
2960
2961 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2962 struct kvm_xcrs *guest_xcrs)
2963 {
2964 int i, r = 0;
2965
2966 if (!cpu_has_xsave)
2967 return -EINVAL;
2968
2969 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2970 return -EINVAL;
2971
2972 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2973 /* Only support XCR0 currently */
2974 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2975 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2976 guest_xcrs->xcrs[0].value);
2977 break;
2978 }
2979 if (r)
2980 r = -EINVAL;
2981 return r;
2982 }
2983
2984 /*
2985 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2986 * stopped by the hypervisor. This function will be called from the host only.
2987 * EINVAL is returned when the host attempts to set the flag for a guest that
2988 * does not support pv clocks.
2989 */
2990 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2991 {
2992 if (!vcpu->arch.pv_time_enabled)
2993 return -EINVAL;
2994 vcpu->arch.pvclock_set_guest_stopped_request = true;
2995 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2996 return 0;
2997 }
2998
2999 long kvm_arch_vcpu_ioctl(struct file *filp,
3000 unsigned int ioctl, unsigned long arg)
3001 {
3002 struct kvm_vcpu *vcpu = filp->private_data;
3003 void __user *argp = (void __user *)arg;
3004 int r;
3005 union {
3006 struct kvm_lapic_state *lapic;
3007 struct kvm_xsave *xsave;
3008 struct kvm_xcrs *xcrs;
3009 void *buffer;
3010 } u;
3011
3012 u.buffer = NULL;
3013 switch (ioctl) {
3014 case KVM_GET_LAPIC: {
3015 r = -EINVAL;
3016 if (!vcpu->arch.apic)
3017 goto out;
3018 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3019
3020 r = -ENOMEM;
3021 if (!u.lapic)
3022 goto out;
3023 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3024 if (r)
3025 goto out;
3026 r = -EFAULT;
3027 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3028 goto out;
3029 r = 0;
3030 break;
3031 }
3032 case KVM_SET_LAPIC: {
3033 r = -EINVAL;
3034 if (!vcpu->arch.apic)
3035 goto out;
3036 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3037 if (IS_ERR(u.lapic))
3038 return PTR_ERR(u.lapic);
3039
3040 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3041 break;
3042 }
3043 case KVM_INTERRUPT: {
3044 struct kvm_interrupt irq;
3045
3046 r = -EFAULT;
3047 if (copy_from_user(&irq, argp, sizeof irq))
3048 goto out;
3049 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3050 break;
3051 }
3052 case KVM_NMI: {
3053 r = kvm_vcpu_ioctl_nmi(vcpu);
3054 break;
3055 }
3056 case KVM_SET_CPUID: {
3057 struct kvm_cpuid __user *cpuid_arg = argp;
3058 struct kvm_cpuid cpuid;
3059
3060 r = -EFAULT;
3061 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3062 goto out;
3063 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3064 break;
3065 }
3066 case KVM_SET_CPUID2: {
3067 struct kvm_cpuid2 __user *cpuid_arg = argp;
3068 struct kvm_cpuid2 cpuid;
3069
3070 r = -EFAULT;
3071 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3072 goto out;
3073 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3074 cpuid_arg->entries);
3075 break;
3076 }
3077 case KVM_GET_CPUID2: {
3078 struct kvm_cpuid2 __user *cpuid_arg = argp;
3079 struct kvm_cpuid2 cpuid;
3080
3081 r = -EFAULT;
3082 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3083 goto out;
3084 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3085 cpuid_arg->entries);
3086 if (r)
3087 goto out;
3088 r = -EFAULT;
3089 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3090 goto out;
3091 r = 0;
3092 break;
3093 }
3094 case KVM_GET_MSRS:
3095 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3096 break;
3097 case KVM_SET_MSRS:
3098 r = msr_io(vcpu, argp, do_set_msr, 0);
3099 break;
3100 case KVM_TPR_ACCESS_REPORTING: {
3101 struct kvm_tpr_access_ctl tac;
3102
3103 r = -EFAULT;
3104 if (copy_from_user(&tac, argp, sizeof tac))
3105 goto out;
3106 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3107 if (r)
3108 goto out;
3109 r = -EFAULT;
3110 if (copy_to_user(argp, &tac, sizeof tac))
3111 goto out;
3112 r = 0;
3113 break;
3114 };
3115 case KVM_SET_VAPIC_ADDR: {
3116 struct kvm_vapic_addr va;
3117
3118 r = -EINVAL;
3119 if (!irqchip_in_kernel(vcpu->kvm))
3120 goto out;
3121 r = -EFAULT;
3122 if (copy_from_user(&va, argp, sizeof va))
3123 goto out;
3124 r = 0;
3125 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3126 break;
3127 }
3128 case KVM_X86_SETUP_MCE: {
3129 u64 mcg_cap;
3130
3131 r = -EFAULT;
3132 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3133 goto out;
3134 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3135 break;
3136 }
3137 case KVM_X86_SET_MCE: {
3138 struct kvm_x86_mce mce;
3139
3140 r = -EFAULT;
3141 if (copy_from_user(&mce, argp, sizeof mce))
3142 goto out;
3143 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3144 break;
3145 }
3146 case KVM_GET_VCPU_EVENTS: {
3147 struct kvm_vcpu_events events;
3148
3149 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3150
3151 r = -EFAULT;
3152 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3153 break;
3154 r = 0;
3155 break;
3156 }
3157 case KVM_SET_VCPU_EVENTS: {
3158 struct kvm_vcpu_events events;
3159
3160 r = -EFAULT;
3161 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3162 break;
3163
3164 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3165 break;
3166 }
3167 case KVM_GET_DEBUGREGS: {
3168 struct kvm_debugregs dbgregs;
3169
3170 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3171
3172 r = -EFAULT;
3173 if (copy_to_user(argp, &dbgregs,
3174 sizeof(struct kvm_debugregs)))
3175 break;
3176 r = 0;
3177 break;
3178 }
3179 case KVM_SET_DEBUGREGS: {
3180 struct kvm_debugregs dbgregs;
3181
3182 r = -EFAULT;
3183 if (copy_from_user(&dbgregs, argp,
3184 sizeof(struct kvm_debugregs)))
3185 break;
3186
3187 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3188 break;
3189 }
3190 case KVM_GET_XSAVE: {
3191 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3192 r = -ENOMEM;
3193 if (!u.xsave)
3194 break;
3195
3196 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3197
3198 r = -EFAULT;
3199 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3200 break;
3201 r = 0;
3202 break;
3203 }
3204 case KVM_SET_XSAVE: {
3205 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3206 if (IS_ERR(u.xsave))
3207 return PTR_ERR(u.xsave);
3208
3209 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3210 break;
3211 }
3212 case KVM_GET_XCRS: {
3213 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3214 r = -ENOMEM;
3215 if (!u.xcrs)
3216 break;
3217
3218 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3219
3220 r = -EFAULT;
3221 if (copy_to_user(argp, u.xcrs,
3222 sizeof(struct kvm_xcrs)))
3223 break;
3224 r = 0;
3225 break;
3226 }
3227 case KVM_SET_XCRS: {
3228 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3229 if (IS_ERR(u.xcrs))
3230 return PTR_ERR(u.xcrs);
3231
3232 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3233 break;
3234 }
3235 case KVM_SET_TSC_KHZ: {
3236 u32 user_tsc_khz;
3237
3238 r = -EINVAL;
3239 user_tsc_khz = (u32)arg;
3240
3241 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3242 goto out;
3243
3244 if (user_tsc_khz == 0)
3245 user_tsc_khz = tsc_khz;
3246
3247 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3248
3249 r = 0;
3250 goto out;
3251 }
3252 case KVM_GET_TSC_KHZ: {
3253 r = vcpu->arch.virtual_tsc_khz;
3254 goto out;
3255 }
3256 case KVM_KVMCLOCK_CTRL: {
3257 r = kvm_set_guest_paused(vcpu);
3258 goto out;
3259 }
3260 default:
3261 r = -EINVAL;
3262 }
3263 out:
3264 kfree(u.buffer);
3265 return r;
3266 }
3267
3268 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3269 {
3270 return VM_FAULT_SIGBUS;
3271 }
3272
3273 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3274 {
3275 int ret;
3276
3277 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3278 return -EINVAL;
3279 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3280 return ret;
3281 }
3282
3283 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3284 u64 ident_addr)
3285 {
3286 kvm->arch.ept_identity_map_addr = ident_addr;
3287 return 0;
3288 }
3289
3290 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3291 u32 kvm_nr_mmu_pages)
3292 {
3293 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3294 return -EINVAL;
3295
3296 mutex_lock(&kvm->slots_lock);
3297
3298 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3299 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3300
3301 mutex_unlock(&kvm->slots_lock);
3302 return 0;
3303 }
3304
3305 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3306 {
3307 return kvm->arch.n_max_mmu_pages;
3308 }
3309
3310 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3311 {
3312 int r;
3313
3314 r = 0;
3315 switch (chip->chip_id) {
3316 case KVM_IRQCHIP_PIC_MASTER:
3317 memcpy(&chip->chip.pic,
3318 &pic_irqchip(kvm)->pics[0],
3319 sizeof(struct kvm_pic_state));
3320 break;
3321 case KVM_IRQCHIP_PIC_SLAVE:
3322 memcpy(&chip->chip.pic,
3323 &pic_irqchip(kvm)->pics[1],
3324 sizeof(struct kvm_pic_state));
3325 break;
3326 case KVM_IRQCHIP_IOAPIC:
3327 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3328 break;
3329 default:
3330 r = -EINVAL;
3331 break;
3332 }
3333 return r;
3334 }
3335
3336 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3337 {
3338 int r;
3339
3340 r = 0;
3341 switch (chip->chip_id) {
3342 case KVM_IRQCHIP_PIC_MASTER:
3343 spin_lock(&pic_irqchip(kvm)->lock);
3344 memcpy(&pic_irqchip(kvm)->pics[0],
3345 &chip->chip.pic,
3346 sizeof(struct kvm_pic_state));
3347 spin_unlock(&pic_irqchip(kvm)->lock);
3348 break;
3349 case KVM_IRQCHIP_PIC_SLAVE:
3350 spin_lock(&pic_irqchip(kvm)->lock);
3351 memcpy(&pic_irqchip(kvm)->pics[1],
3352 &chip->chip.pic,
3353 sizeof(struct kvm_pic_state));
3354 spin_unlock(&pic_irqchip(kvm)->lock);
3355 break;
3356 case KVM_IRQCHIP_IOAPIC:
3357 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3358 break;
3359 default:
3360 r = -EINVAL;
3361 break;
3362 }
3363 kvm_pic_update_irq(pic_irqchip(kvm));
3364 return r;
3365 }
3366
3367 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3368 {
3369 int r = 0;
3370
3371 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3372 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3373 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3374 return r;
3375 }
3376
3377 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3378 {
3379 int r = 0;
3380
3381 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3382 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3383 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3384 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3385 return r;
3386 }
3387
3388 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3389 {
3390 int r = 0;
3391
3392 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3393 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3394 sizeof(ps->channels));
3395 ps->flags = kvm->arch.vpit->pit_state.flags;
3396 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3397 memset(&ps->reserved, 0, sizeof(ps->reserved));
3398 return r;
3399 }
3400
3401 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3402 {
3403 int r = 0, start = 0;
3404 u32 prev_legacy, cur_legacy;
3405 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3406 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3407 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3408 if (!prev_legacy && cur_legacy)
3409 start = 1;
3410 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3411 sizeof(kvm->arch.vpit->pit_state.channels));
3412 kvm->arch.vpit->pit_state.flags = ps->flags;
3413 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3414 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3415 return r;
3416 }
3417
3418 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3419 struct kvm_reinject_control *control)
3420 {
3421 if (!kvm->arch.vpit)
3422 return -ENXIO;
3423 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3424 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3425 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3426 return 0;
3427 }
3428
3429 /**
3430 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3431 * @kvm: kvm instance
3432 * @log: slot id and address to which we copy the log
3433 *
3434 * We need to keep it in mind that VCPU threads can write to the bitmap
3435 * concurrently. So, to avoid losing data, we keep the following order for
3436 * each bit:
3437 *
3438 * 1. Take a snapshot of the bit and clear it if needed.
3439 * 2. Write protect the corresponding page.
3440 * 3. Flush TLB's if needed.
3441 * 4. Copy the snapshot to the userspace.
3442 *
3443 * Between 2 and 3, the guest may write to the page using the remaining TLB
3444 * entry. This is not a problem because the page will be reported dirty at
3445 * step 4 using the snapshot taken before and step 3 ensures that successive
3446 * writes will be logged for the next call.
3447 */
3448 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3449 {
3450 int r;
3451 struct kvm_memory_slot *memslot;
3452 unsigned long n, i;
3453 unsigned long *dirty_bitmap;
3454 unsigned long *dirty_bitmap_buffer;
3455 bool is_dirty = false;
3456
3457 mutex_lock(&kvm->slots_lock);
3458
3459 r = -EINVAL;
3460 if (log->slot >= KVM_USER_MEM_SLOTS)
3461 goto out;
3462
3463 memslot = id_to_memslot(kvm->memslots, log->slot);
3464
3465 dirty_bitmap = memslot->dirty_bitmap;
3466 r = -ENOENT;
3467 if (!dirty_bitmap)
3468 goto out;
3469
3470 n = kvm_dirty_bitmap_bytes(memslot);
3471
3472 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3473 memset(dirty_bitmap_buffer, 0, n);
3474
3475 spin_lock(&kvm->mmu_lock);
3476
3477 for (i = 0; i < n / sizeof(long); i++) {
3478 unsigned long mask;
3479 gfn_t offset;
3480
3481 if (!dirty_bitmap[i])
3482 continue;
3483
3484 is_dirty = true;
3485
3486 mask = xchg(&dirty_bitmap[i], 0);
3487 dirty_bitmap_buffer[i] = mask;
3488
3489 offset = i * BITS_PER_LONG;
3490 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3491 }
3492 if (is_dirty)
3493 kvm_flush_remote_tlbs(kvm);
3494
3495 spin_unlock(&kvm->mmu_lock);
3496
3497 r = -EFAULT;
3498 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3499 goto out;
3500
3501 r = 0;
3502 out:
3503 mutex_unlock(&kvm->slots_lock);
3504 return r;
3505 }
3506
3507 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3508 bool line_status)
3509 {
3510 if (!irqchip_in_kernel(kvm))
3511 return -ENXIO;
3512
3513 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3514 irq_event->irq, irq_event->level,
3515 line_status);
3516 return 0;
3517 }
3518
3519 long kvm_arch_vm_ioctl(struct file *filp,
3520 unsigned int ioctl, unsigned long arg)
3521 {
3522 struct kvm *kvm = filp->private_data;
3523 void __user *argp = (void __user *)arg;
3524 int r = -ENOTTY;
3525 /*
3526 * This union makes it completely explicit to gcc-3.x
3527 * that these two variables' stack usage should be
3528 * combined, not added together.
3529 */
3530 union {
3531 struct kvm_pit_state ps;
3532 struct kvm_pit_state2 ps2;
3533 struct kvm_pit_config pit_config;
3534 } u;
3535
3536 switch (ioctl) {
3537 case KVM_SET_TSS_ADDR:
3538 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3539 break;
3540 case KVM_SET_IDENTITY_MAP_ADDR: {
3541 u64 ident_addr;
3542
3543 r = -EFAULT;
3544 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3545 goto out;
3546 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3547 break;
3548 }
3549 case KVM_SET_NR_MMU_PAGES:
3550 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3551 break;
3552 case KVM_GET_NR_MMU_PAGES:
3553 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3554 break;
3555 case KVM_CREATE_IRQCHIP: {
3556 struct kvm_pic *vpic;
3557
3558 mutex_lock(&kvm->lock);
3559 r = -EEXIST;
3560 if (kvm->arch.vpic)
3561 goto create_irqchip_unlock;
3562 r = -EINVAL;
3563 if (atomic_read(&kvm->online_vcpus))
3564 goto create_irqchip_unlock;
3565 r = -ENOMEM;
3566 vpic = kvm_create_pic(kvm);
3567 if (vpic) {
3568 r = kvm_ioapic_init(kvm);
3569 if (r) {
3570 mutex_lock(&kvm->slots_lock);
3571 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3572 &vpic->dev_master);
3573 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3574 &vpic->dev_slave);
3575 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3576 &vpic->dev_eclr);
3577 mutex_unlock(&kvm->slots_lock);
3578 kfree(vpic);
3579 goto create_irqchip_unlock;
3580 }
3581 } else
3582 goto create_irqchip_unlock;
3583 smp_wmb();
3584 kvm->arch.vpic = vpic;
3585 smp_wmb();
3586 r = kvm_setup_default_irq_routing(kvm);
3587 if (r) {
3588 mutex_lock(&kvm->slots_lock);
3589 mutex_lock(&kvm->irq_lock);
3590 kvm_ioapic_destroy(kvm);
3591 kvm_destroy_pic(kvm);
3592 mutex_unlock(&kvm->irq_lock);
3593 mutex_unlock(&kvm->slots_lock);
3594 }
3595 create_irqchip_unlock:
3596 mutex_unlock(&kvm->lock);
3597 break;
3598 }
3599 case KVM_CREATE_PIT:
3600 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3601 goto create_pit;
3602 case KVM_CREATE_PIT2:
3603 r = -EFAULT;
3604 if (copy_from_user(&u.pit_config, argp,
3605 sizeof(struct kvm_pit_config)))
3606 goto out;
3607 create_pit:
3608 mutex_lock(&kvm->slots_lock);
3609 r = -EEXIST;
3610 if (kvm->arch.vpit)
3611 goto create_pit_unlock;
3612 r = -ENOMEM;
3613 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3614 if (kvm->arch.vpit)
3615 r = 0;
3616 create_pit_unlock:
3617 mutex_unlock(&kvm->slots_lock);
3618 break;
3619 case KVM_GET_IRQCHIP: {
3620 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3621 struct kvm_irqchip *chip;
3622
3623 chip = memdup_user(argp, sizeof(*chip));
3624 if (IS_ERR(chip)) {
3625 r = PTR_ERR(chip);
3626 goto out;
3627 }
3628
3629 r = -ENXIO;
3630 if (!irqchip_in_kernel(kvm))
3631 goto get_irqchip_out;
3632 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3633 if (r)
3634 goto get_irqchip_out;
3635 r = -EFAULT;
3636 if (copy_to_user(argp, chip, sizeof *chip))
3637 goto get_irqchip_out;
3638 r = 0;
3639 get_irqchip_out:
3640 kfree(chip);
3641 break;
3642 }
3643 case KVM_SET_IRQCHIP: {
3644 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3645 struct kvm_irqchip *chip;
3646
3647 chip = memdup_user(argp, sizeof(*chip));
3648 if (IS_ERR(chip)) {
3649 r = PTR_ERR(chip);
3650 goto out;
3651 }
3652
3653 r = -ENXIO;
3654 if (!irqchip_in_kernel(kvm))
3655 goto set_irqchip_out;
3656 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3657 if (r)
3658 goto set_irqchip_out;
3659 r = 0;
3660 set_irqchip_out:
3661 kfree(chip);
3662 break;
3663 }
3664 case KVM_GET_PIT: {
3665 r = -EFAULT;
3666 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3667 goto out;
3668 r = -ENXIO;
3669 if (!kvm->arch.vpit)
3670 goto out;
3671 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3672 if (r)
3673 goto out;
3674 r = -EFAULT;
3675 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3676 goto out;
3677 r = 0;
3678 break;
3679 }
3680 case KVM_SET_PIT: {
3681 r = -EFAULT;
3682 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3683 goto out;
3684 r = -ENXIO;
3685 if (!kvm->arch.vpit)
3686 goto out;
3687 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3688 break;
3689 }
3690 case KVM_GET_PIT2: {
3691 r = -ENXIO;
3692 if (!kvm->arch.vpit)
3693 goto out;
3694 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3695 if (r)
3696 goto out;
3697 r = -EFAULT;
3698 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3699 goto out;
3700 r = 0;
3701 break;
3702 }
3703 case KVM_SET_PIT2: {
3704 r = -EFAULT;
3705 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3706 goto out;
3707 r = -ENXIO;
3708 if (!kvm->arch.vpit)
3709 goto out;
3710 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3711 break;
3712 }
3713 case KVM_REINJECT_CONTROL: {
3714 struct kvm_reinject_control control;
3715 r = -EFAULT;
3716 if (copy_from_user(&control, argp, sizeof(control)))
3717 goto out;
3718 r = kvm_vm_ioctl_reinject(kvm, &control);
3719 break;
3720 }
3721 case KVM_XEN_HVM_CONFIG: {
3722 r = -EFAULT;
3723 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3724 sizeof(struct kvm_xen_hvm_config)))
3725 goto out;
3726 r = -EINVAL;
3727 if (kvm->arch.xen_hvm_config.flags)
3728 goto out;
3729 r = 0;
3730 break;
3731 }
3732 case KVM_SET_CLOCK: {
3733 struct kvm_clock_data user_ns;
3734 u64 now_ns;
3735 s64 delta;
3736
3737 r = -EFAULT;
3738 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3739 goto out;
3740
3741 r = -EINVAL;
3742 if (user_ns.flags)
3743 goto out;
3744
3745 r = 0;
3746 local_irq_disable();
3747 now_ns = get_kernel_ns();
3748 delta = user_ns.clock - now_ns;
3749 local_irq_enable();
3750 kvm->arch.kvmclock_offset = delta;
3751 break;
3752 }
3753 case KVM_GET_CLOCK: {
3754 struct kvm_clock_data user_ns;
3755 u64 now_ns;
3756
3757 local_irq_disable();
3758 now_ns = get_kernel_ns();
3759 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3760 local_irq_enable();
3761 user_ns.flags = 0;
3762 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3763
3764 r = -EFAULT;
3765 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3766 goto out;
3767 r = 0;
3768 break;
3769 }
3770
3771 default:
3772 ;
3773 }
3774 out:
3775 return r;
3776 }
3777
3778 static void kvm_init_msr_list(void)
3779 {
3780 u32 dummy[2];
3781 unsigned i, j;
3782
3783 /* skip the first msrs in the list. KVM-specific */
3784 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3785 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3786 continue;
3787 if (j < i)
3788 msrs_to_save[j] = msrs_to_save[i];
3789 j++;
3790 }
3791 num_msrs_to_save = j;
3792 }
3793
3794 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3795 const void *v)
3796 {
3797 int handled = 0;
3798 int n;
3799
3800 do {
3801 n = min(len, 8);
3802 if (!(vcpu->arch.apic &&
3803 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3804 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3805 break;
3806 handled += n;
3807 addr += n;
3808 len -= n;
3809 v += n;
3810 } while (len);
3811
3812 return handled;
3813 }
3814
3815 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3816 {
3817 int handled = 0;
3818 int n;
3819
3820 do {
3821 n = min(len, 8);
3822 if (!(vcpu->arch.apic &&
3823 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3824 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3825 break;
3826 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3827 handled += n;
3828 addr += n;
3829 len -= n;
3830 v += n;
3831 } while (len);
3832
3833 return handled;
3834 }
3835
3836 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3837 struct kvm_segment *var, int seg)
3838 {
3839 kvm_x86_ops->set_segment(vcpu, var, seg);
3840 }
3841
3842 void kvm_get_segment(struct kvm_vcpu *vcpu,
3843 struct kvm_segment *var, int seg)
3844 {
3845 kvm_x86_ops->get_segment(vcpu, var, seg);
3846 }
3847
3848 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3849 {
3850 gpa_t t_gpa;
3851 struct x86_exception exception;
3852
3853 BUG_ON(!mmu_is_nested(vcpu));
3854
3855 /* NPT walks are always user-walks */
3856 access |= PFERR_USER_MASK;
3857 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3858
3859 return t_gpa;
3860 }
3861
3862 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3863 struct x86_exception *exception)
3864 {
3865 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3866 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3867 }
3868
3869 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3870 struct x86_exception *exception)
3871 {
3872 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3873 access |= PFERR_FETCH_MASK;
3874 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3875 }
3876
3877 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3878 struct x86_exception *exception)
3879 {
3880 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3881 access |= PFERR_WRITE_MASK;
3882 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3883 }
3884
3885 /* uses this to access any guest's mapped memory without checking CPL */
3886 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3887 struct x86_exception *exception)
3888 {
3889 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3890 }
3891
3892 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3893 struct kvm_vcpu *vcpu, u32 access,
3894 struct x86_exception *exception)
3895 {
3896 void *data = val;
3897 int r = X86EMUL_CONTINUE;
3898
3899 while (bytes) {
3900 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3901 exception);
3902 unsigned offset = addr & (PAGE_SIZE-1);
3903 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3904 int ret;
3905
3906 if (gpa == UNMAPPED_GVA)
3907 return X86EMUL_PROPAGATE_FAULT;
3908 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3909 if (ret < 0) {
3910 r = X86EMUL_IO_NEEDED;
3911 goto out;
3912 }
3913
3914 bytes -= toread;
3915 data += toread;
3916 addr += toread;
3917 }
3918 out:
3919 return r;
3920 }
3921
3922 /* used for instruction fetching */
3923 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3924 gva_t addr, void *val, unsigned int bytes,
3925 struct x86_exception *exception)
3926 {
3927 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3928 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3929
3930 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3931 access | PFERR_FETCH_MASK,
3932 exception);
3933 }
3934
3935 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3936 gva_t addr, void *val, unsigned int bytes,
3937 struct x86_exception *exception)
3938 {
3939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3940 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3941
3942 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3943 exception);
3944 }
3945 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3946
3947 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3948 gva_t addr, void *val, unsigned int bytes,
3949 struct x86_exception *exception)
3950 {
3951 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3952 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3953 }
3954
3955 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3956 gva_t addr, void *val,
3957 unsigned int bytes,
3958 struct x86_exception *exception)
3959 {
3960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3961 void *data = val;
3962 int r = X86EMUL_CONTINUE;
3963
3964 while (bytes) {
3965 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3966 PFERR_WRITE_MASK,
3967 exception);
3968 unsigned offset = addr & (PAGE_SIZE-1);
3969 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3970 int ret;
3971
3972 if (gpa == UNMAPPED_GVA)
3973 return X86EMUL_PROPAGATE_FAULT;
3974 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3975 if (ret < 0) {
3976 r = X86EMUL_IO_NEEDED;
3977 goto out;
3978 }
3979
3980 bytes -= towrite;
3981 data += towrite;
3982 addr += towrite;
3983 }
3984 out:
3985 return r;
3986 }
3987 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3988
3989 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3990 gpa_t *gpa, struct x86_exception *exception,
3991 bool write)
3992 {
3993 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3994 | (write ? PFERR_WRITE_MASK : 0);
3995
3996 if (vcpu_match_mmio_gva(vcpu, gva)
3997 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
3998 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3999 (gva & (PAGE_SIZE - 1));
4000 trace_vcpu_match_mmio(gva, *gpa, write, false);
4001 return 1;
4002 }
4003
4004 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4005
4006 if (*gpa == UNMAPPED_GVA)
4007 return -1;
4008
4009 /* For APIC access vmexit */
4010 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4011 return 1;
4012
4013 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4014 trace_vcpu_match_mmio(gva, *gpa, write, true);
4015 return 1;
4016 }
4017
4018 return 0;
4019 }
4020
4021 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4022 const void *val, int bytes)
4023 {
4024 int ret;
4025
4026 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4027 if (ret < 0)
4028 return 0;
4029 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4030 return 1;
4031 }
4032
4033 struct read_write_emulator_ops {
4034 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4035 int bytes);
4036 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4037 void *val, int bytes);
4038 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4039 int bytes, void *val);
4040 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4041 void *val, int bytes);
4042 bool write;
4043 };
4044
4045 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4046 {
4047 if (vcpu->mmio_read_completed) {
4048 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4049 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4050 vcpu->mmio_read_completed = 0;
4051 return 1;
4052 }
4053
4054 return 0;
4055 }
4056
4057 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4058 void *val, int bytes)
4059 {
4060 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4061 }
4062
4063 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4064 void *val, int bytes)
4065 {
4066 return emulator_write_phys(vcpu, gpa, val, bytes);
4067 }
4068
4069 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4070 {
4071 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4072 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4073 }
4074
4075 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4076 void *val, int bytes)
4077 {
4078 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4079 return X86EMUL_IO_NEEDED;
4080 }
4081
4082 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4083 void *val, int bytes)
4084 {
4085 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4086
4087 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4088 return X86EMUL_CONTINUE;
4089 }
4090
4091 static const struct read_write_emulator_ops read_emultor = {
4092 .read_write_prepare = read_prepare,
4093 .read_write_emulate = read_emulate,
4094 .read_write_mmio = vcpu_mmio_read,
4095 .read_write_exit_mmio = read_exit_mmio,
4096 };
4097
4098 static const struct read_write_emulator_ops write_emultor = {
4099 .read_write_emulate = write_emulate,
4100 .read_write_mmio = write_mmio,
4101 .read_write_exit_mmio = write_exit_mmio,
4102 .write = true,
4103 };
4104
4105 static int emulator_read_write_onepage(unsigned long addr, void *val,
4106 unsigned int bytes,
4107 struct x86_exception *exception,
4108 struct kvm_vcpu *vcpu,
4109 const struct read_write_emulator_ops *ops)
4110 {
4111 gpa_t gpa;
4112 int handled, ret;
4113 bool write = ops->write;
4114 struct kvm_mmio_fragment *frag;
4115
4116 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4117
4118 if (ret < 0)
4119 return X86EMUL_PROPAGATE_FAULT;
4120
4121 /* For APIC access vmexit */
4122 if (ret)
4123 goto mmio;
4124
4125 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4126 return X86EMUL_CONTINUE;
4127
4128 mmio:
4129 /*
4130 * Is this MMIO handled locally?
4131 */
4132 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4133 if (handled == bytes)
4134 return X86EMUL_CONTINUE;
4135
4136 gpa += handled;
4137 bytes -= handled;
4138 val += handled;
4139
4140 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4141 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4142 frag->gpa = gpa;
4143 frag->data = val;
4144 frag->len = bytes;
4145 return X86EMUL_CONTINUE;
4146 }
4147
4148 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4149 void *val, unsigned int bytes,
4150 struct x86_exception *exception,
4151 const struct read_write_emulator_ops *ops)
4152 {
4153 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4154 gpa_t gpa;
4155 int rc;
4156
4157 if (ops->read_write_prepare &&
4158 ops->read_write_prepare(vcpu, val, bytes))
4159 return X86EMUL_CONTINUE;
4160
4161 vcpu->mmio_nr_fragments = 0;
4162
4163 /* Crossing a page boundary? */
4164 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4165 int now;
4166
4167 now = -addr & ~PAGE_MASK;
4168 rc = emulator_read_write_onepage(addr, val, now, exception,
4169 vcpu, ops);
4170
4171 if (rc != X86EMUL_CONTINUE)
4172 return rc;
4173 addr += now;
4174 val += now;
4175 bytes -= now;
4176 }
4177
4178 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4179 vcpu, ops);
4180 if (rc != X86EMUL_CONTINUE)
4181 return rc;
4182
4183 if (!vcpu->mmio_nr_fragments)
4184 return rc;
4185
4186 gpa = vcpu->mmio_fragments[0].gpa;
4187
4188 vcpu->mmio_needed = 1;
4189 vcpu->mmio_cur_fragment = 0;
4190
4191 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4192 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4193 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4194 vcpu->run->mmio.phys_addr = gpa;
4195
4196 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4197 }
4198
4199 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4200 unsigned long addr,
4201 void *val,
4202 unsigned int bytes,
4203 struct x86_exception *exception)
4204 {
4205 return emulator_read_write(ctxt, addr, val, bytes,
4206 exception, &read_emultor);
4207 }
4208
4209 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4210 unsigned long addr,
4211 const void *val,
4212 unsigned int bytes,
4213 struct x86_exception *exception)
4214 {
4215 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4216 exception, &write_emultor);
4217 }
4218
4219 #define CMPXCHG_TYPE(t, ptr, old, new) \
4220 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4221
4222 #ifdef CONFIG_X86_64
4223 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4224 #else
4225 # define CMPXCHG64(ptr, old, new) \
4226 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4227 #endif
4228
4229 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4230 unsigned long addr,
4231 const void *old,
4232 const void *new,
4233 unsigned int bytes,
4234 struct x86_exception *exception)
4235 {
4236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4237 gpa_t gpa;
4238 struct page *page;
4239 char *kaddr;
4240 bool exchanged;
4241
4242 /* guests cmpxchg8b have to be emulated atomically */
4243 if (bytes > 8 || (bytes & (bytes - 1)))
4244 goto emul_write;
4245
4246 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4247
4248 if (gpa == UNMAPPED_GVA ||
4249 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4250 goto emul_write;
4251
4252 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4253 goto emul_write;
4254
4255 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4256 if (is_error_page(page))
4257 goto emul_write;
4258
4259 kaddr = kmap_atomic(page);
4260 kaddr += offset_in_page(gpa);
4261 switch (bytes) {
4262 case 1:
4263 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4264 break;
4265 case 2:
4266 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4267 break;
4268 case 4:
4269 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4270 break;
4271 case 8:
4272 exchanged = CMPXCHG64(kaddr, old, new);
4273 break;
4274 default:
4275 BUG();
4276 }
4277 kunmap_atomic(kaddr);
4278 kvm_release_page_dirty(page);
4279
4280 if (!exchanged)
4281 return X86EMUL_CMPXCHG_FAILED;
4282
4283 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4284
4285 return X86EMUL_CONTINUE;
4286
4287 emul_write:
4288 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4289
4290 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4291 }
4292
4293 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4294 {
4295 /* TODO: String I/O for in kernel device */
4296 int r;
4297
4298 if (vcpu->arch.pio.in)
4299 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4300 vcpu->arch.pio.size, pd);
4301 else
4302 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4303 vcpu->arch.pio.port, vcpu->arch.pio.size,
4304 pd);
4305 return r;
4306 }
4307
4308 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4309 unsigned short port, void *val,
4310 unsigned int count, bool in)
4311 {
4312 trace_kvm_pio(!in, port, size, count);
4313
4314 vcpu->arch.pio.port = port;
4315 vcpu->arch.pio.in = in;
4316 vcpu->arch.pio.count = count;
4317 vcpu->arch.pio.size = size;
4318
4319 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4320 vcpu->arch.pio.count = 0;
4321 return 1;
4322 }
4323
4324 vcpu->run->exit_reason = KVM_EXIT_IO;
4325 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4326 vcpu->run->io.size = size;
4327 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4328 vcpu->run->io.count = count;
4329 vcpu->run->io.port = port;
4330
4331 return 0;
4332 }
4333
4334 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4335 int size, unsigned short port, void *val,
4336 unsigned int count)
4337 {
4338 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4339 int ret;
4340
4341 if (vcpu->arch.pio.count)
4342 goto data_avail;
4343
4344 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4345 if (ret) {
4346 data_avail:
4347 memcpy(val, vcpu->arch.pio_data, size * count);
4348 vcpu->arch.pio.count = 0;
4349 return 1;
4350 }
4351
4352 return 0;
4353 }
4354
4355 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4356 int size, unsigned short port,
4357 const void *val, unsigned int count)
4358 {
4359 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4360
4361 memcpy(vcpu->arch.pio_data, val, size * count);
4362 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4363 }
4364
4365 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4366 {
4367 return kvm_x86_ops->get_segment_base(vcpu, seg);
4368 }
4369
4370 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4371 {
4372 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4373 }
4374
4375 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4376 {
4377 if (!need_emulate_wbinvd(vcpu))
4378 return X86EMUL_CONTINUE;
4379
4380 if (kvm_x86_ops->has_wbinvd_exit()) {
4381 int cpu = get_cpu();
4382
4383 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4384 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4385 wbinvd_ipi, NULL, 1);
4386 put_cpu();
4387 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4388 } else
4389 wbinvd();
4390 return X86EMUL_CONTINUE;
4391 }
4392 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4393
4394 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4395 {
4396 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4397 }
4398
4399 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4400 {
4401 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4402 }
4403
4404 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4405 {
4406
4407 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4408 }
4409
4410 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4411 {
4412 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4413 }
4414
4415 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4416 {
4417 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4418 unsigned long value;
4419
4420 switch (cr) {
4421 case 0:
4422 value = kvm_read_cr0(vcpu);
4423 break;
4424 case 2:
4425 value = vcpu->arch.cr2;
4426 break;
4427 case 3:
4428 value = kvm_read_cr3(vcpu);
4429 break;
4430 case 4:
4431 value = kvm_read_cr4(vcpu);
4432 break;
4433 case 8:
4434 value = kvm_get_cr8(vcpu);
4435 break;
4436 default:
4437 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4438 return 0;
4439 }
4440
4441 return value;
4442 }
4443
4444 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4445 {
4446 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4447 int res = 0;
4448
4449 switch (cr) {
4450 case 0:
4451 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4452 break;
4453 case 2:
4454 vcpu->arch.cr2 = val;
4455 break;
4456 case 3:
4457 res = kvm_set_cr3(vcpu, val);
4458 break;
4459 case 4:
4460 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4461 break;
4462 case 8:
4463 res = kvm_set_cr8(vcpu, val);
4464 break;
4465 default:
4466 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4467 res = -1;
4468 }
4469
4470 return res;
4471 }
4472
4473 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4474 {
4475 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4476 }
4477
4478 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4479 {
4480 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4481 }
4482
4483 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4484 {
4485 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4486 }
4487
4488 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4489 {
4490 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4491 }
4492
4493 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4494 {
4495 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4496 }
4497
4498 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4499 {
4500 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4501 }
4502
4503 static unsigned long emulator_get_cached_segment_base(
4504 struct x86_emulate_ctxt *ctxt, int seg)
4505 {
4506 return get_segment_base(emul_to_vcpu(ctxt), seg);
4507 }
4508
4509 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4510 struct desc_struct *desc, u32 *base3,
4511 int seg)
4512 {
4513 struct kvm_segment var;
4514
4515 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4516 *selector = var.selector;
4517
4518 if (var.unusable) {
4519 memset(desc, 0, sizeof(*desc));
4520 return false;
4521 }
4522
4523 if (var.g)
4524 var.limit >>= 12;
4525 set_desc_limit(desc, var.limit);
4526 set_desc_base(desc, (unsigned long)var.base);
4527 #ifdef CONFIG_X86_64
4528 if (base3)
4529 *base3 = var.base >> 32;
4530 #endif
4531 desc->type = var.type;
4532 desc->s = var.s;
4533 desc->dpl = var.dpl;
4534 desc->p = var.present;
4535 desc->avl = var.avl;
4536 desc->l = var.l;
4537 desc->d = var.db;
4538 desc->g = var.g;
4539
4540 return true;
4541 }
4542
4543 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4544 struct desc_struct *desc, u32 base3,
4545 int seg)
4546 {
4547 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4548 struct kvm_segment var;
4549
4550 var.selector = selector;
4551 var.base = get_desc_base(desc);
4552 #ifdef CONFIG_X86_64
4553 var.base |= ((u64)base3) << 32;
4554 #endif
4555 var.limit = get_desc_limit(desc);
4556 if (desc->g)
4557 var.limit = (var.limit << 12) | 0xfff;
4558 var.type = desc->type;
4559 var.present = desc->p;
4560 var.dpl = desc->dpl;
4561 var.db = desc->d;
4562 var.s = desc->s;
4563 var.l = desc->l;
4564 var.g = desc->g;
4565 var.avl = desc->avl;
4566 var.present = desc->p;
4567 var.unusable = !var.present;
4568 var.padding = 0;
4569
4570 kvm_set_segment(vcpu, &var, seg);
4571 return;
4572 }
4573
4574 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4575 u32 msr_index, u64 *pdata)
4576 {
4577 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4578 }
4579
4580 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4581 u32 msr_index, u64 data)
4582 {
4583 struct msr_data msr;
4584
4585 msr.data = data;
4586 msr.index = msr_index;
4587 msr.host_initiated = false;
4588 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4589 }
4590
4591 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4592 u32 pmc, u64 *pdata)
4593 {
4594 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4595 }
4596
4597 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4598 {
4599 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4600 }
4601
4602 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4603 {
4604 preempt_disable();
4605 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4606 /*
4607 * CR0.TS may reference the host fpu state, not the guest fpu state,
4608 * so it may be clear at this point.
4609 */
4610 clts();
4611 }
4612
4613 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4614 {
4615 preempt_enable();
4616 }
4617
4618 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4619 struct x86_instruction_info *info,
4620 enum x86_intercept_stage stage)
4621 {
4622 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4623 }
4624
4625 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4626 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4627 {
4628 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4629 }
4630
4631 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4632 {
4633 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4634 }
4635
4636 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4637 {
4638 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4639 }
4640
4641 static const struct x86_emulate_ops emulate_ops = {
4642 .read_gpr = emulator_read_gpr,
4643 .write_gpr = emulator_write_gpr,
4644 .read_std = kvm_read_guest_virt_system,
4645 .write_std = kvm_write_guest_virt_system,
4646 .fetch = kvm_fetch_guest_virt,
4647 .read_emulated = emulator_read_emulated,
4648 .write_emulated = emulator_write_emulated,
4649 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4650 .invlpg = emulator_invlpg,
4651 .pio_in_emulated = emulator_pio_in_emulated,
4652 .pio_out_emulated = emulator_pio_out_emulated,
4653 .get_segment = emulator_get_segment,
4654 .set_segment = emulator_set_segment,
4655 .get_cached_segment_base = emulator_get_cached_segment_base,
4656 .get_gdt = emulator_get_gdt,
4657 .get_idt = emulator_get_idt,
4658 .set_gdt = emulator_set_gdt,
4659 .set_idt = emulator_set_idt,
4660 .get_cr = emulator_get_cr,
4661 .set_cr = emulator_set_cr,
4662 .set_rflags = emulator_set_rflags,
4663 .cpl = emulator_get_cpl,
4664 .get_dr = emulator_get_dr,
4665 .set_dr = emulator_set_dr,
4666 .set_msr = emulator_set_msr,
4667 .get_msr = emulator_get_msr,
4668 .read_pmc = emulator_read_pmc,
4669 .halt = emulator_halt,
4670 .wbinvd = emulator_wbinvd,
4671 .fix_hypercall = emulator_fix_hypercall,
4672 .get_fpu = emulator_get_fpu,
4673 .put_fpu = emulator_put_fpu,
4674 .intercept = emulator_intercept,
4675 .get_cpuid = emulator_get_cpuid,
4676 };
4677
4678 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4679 {
4680 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4681 /*
4682 * an sti; sti; sequence only disable interrupts for the first
4683 * instruction. So, if the last instruction, be it emulated or
4684 * not, left the system with the INT_STI flag enabled, it
4685 * means that the last instruction is an sti. We should not
4686 * leave the flag on in this case. The same goes for mov ss
4687 */
4688 if (!(int_shadow & mask))
4689 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4690 }
4691
4692 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4693 {
4694 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4695 if (ctxt->exception.vector == PF_VECTOR)
4696 kvm_propagate_fault(vcpu, &ctxt->exception);
4697 else if (ctxt->exception.error_code_valid)
4698 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4699 ctxt->exception.error_code);
4700 else
4701 kvm_queue_exception(vcpu, ctxt->exception.vector);
4702 }
4703
4704 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4705 {
4706 memset(&ctxt->twobyte, 0,
4707 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4708
4709 ctxt->fetch.start = 0;
4710 ctxt->fetch.end = 0;
4711 ctxt->io_read.pos = 0;
4712 ctxt->io_read.end = 0;
4713 ctxt->mem_read.pos = 0;
4714 ctxt->mem_read.end = 0;
4715 }
4716
4717 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4718 {
4719 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4720 int cs_db, cs_l;
4721
4722 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4723
4724 ctxt->eflags = kvm_get_rflags(vcpu);
4725 ctxt->eip = kvm_rip_read(vcpu);
4726 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4727 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4728 cs_l ? X86EMUL_MODE_PROT64 :
4729 cs_db ? X86EMUL_MODE_PROT32 :
4730 X86EMUL_MODE_PROT16;
4731 ctxt->guest_mode = is_guest_mode(vcpu);
4732
4733 init_decode_cache(ctxt);
4734 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4735 }
4736
4737 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4738 {
4739 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4740 int ret;
4741
4742 init_emulate_ctxt(vcpu);
4743
4744 ctxt->op_bytes = 2;
4745 ctxt->ad_bytes = 2;
4746 ctxt->_eip = ctxt->eip + inc_eip;
4747 ret = emulate_int_real(ctxt, irq);
4748
4749 if (ret != X86EMUL_CONTINUE)
4750 return EMULATE_FAIL;
4751
4752 ctxt->eip = ctxt->_eip;
4753 kvm_rip_write(vcpu, ctxt->eip);
4754 kvm_set_rflags(vcpu, ctxt->eflags);
4755
4756 if (irq == NMI_VECTOR)
4757 vcpu->arch.nmi_pending = 0;
4758 else
4759 vcpu->arch.interrupt.pending = false;
4760
4761 return EMULATE_DONE;
4762 }
4763 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4764
4765 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4766 {
4767 int r = EMULATE_DONE;
4768
4769 ++vcpu->stat.insn_emulation_fail;
4770 trace_kvm_emulate_insn_failed(vcpu);
4771 if (!is_guest_mode(vcpu)) {
4772 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4773 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4774 vcpu->run->internal.ndata = 0;
4775 r = EMULATE_FAIL;
4776 }
4777 kvm_queue_exception(vcpu, UD_VECTOR);
4778
4779 return r;
4780 }
4781
4782 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4783 bool write_fault_to_shadow_pgtable,
4784 int emulation_type)
4785 {
4786 gpa_t gpa = cr2;
4787 pfn_t pfn;
4788
4789 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4790 return false;
4791
4792 if (!vcpu->arch.mmu.direct_map) {
4793 /*
4794 * Write permission should be allowed since only
4795 * write access need to be emulated.
4796 */
4797 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4798
4799 /*
4800 * If the mapping is invalid in guest, let cpu retry
4801 * it to generate fault.
4802 */
4803 if (gpa == UNMAPPED_GVA)
4804 return true;
4805 }
4806
4807 /*
4808 * Do not retry the unhandleable instruction if it faults on the
4809 * readonly host memory, otherwise it will goto a infinite loop:
4810 * retry instruction -> write #PF -> emulation fail -> retry
4811 * instruction -> ...
4812 */
4813 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4814
4815 /*
4816 * If the instruction failed on the error pfn, it can not be fixed,
4817 * report the error to userspace.
4818 */
4819 if (is_error_noslot_pfn(pfn))
4820 return false;
4821
4822 kvm_release_pfn_clean(pfn);
4823
4824 /* The instructions are well-emulated on direct mmu. */
4825 if (vcpu->arch.mmu.direct_map) {
4826 unsigned int indirect_shadow_pages;
4827
4828 spin_lock(&vcpu->kvm->mmu_lock);
4829 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4830 spin_unlock(&vcpu->kvm->mmu_lock);
4831
4832 if (indirect_shadow_pages)
4833 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4834
4835 return true;
4836 }
4837
4838 /*
4839 * if emulation was due to access to shadowed page table
4840 * and it failed try to unshadow page and re-enter the
4841 * guest to let CPU execute the instruction.
4842 */
4843 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4844
4845 /*
4846 * If the access faults on its page table, it can not
4847 * be fixed by unprotecting shadow page and it should
4848 * be reported to userspace.
4849 */
4850 return !write_fault_to_shadow_pgtable;
4851 }
4852
4853 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4854 unsigned long cr2, int emulation_type)
4855 {
4856 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4857 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4858
4859 last_retry_eip = vcpu->arch.last_retry_eip;
4860 last_retry_addr = vcpu->arch.last_retry_addr;
4861
4862 /*
4863 * If the emulation is caused by #PF and it is non-page_table
4864 * writing instruction, it means the VM-EXIT is caused by shadow
4865 * page protected, we can zap the shadow page and retry this
4866 * instruction directly.
4867 *
4868 * Note: if the guest uses a non-page-table modifying instruction
4869 * on the PDE that points to the instruction, then we will unmap
4870 * the instruction and go to an infinite loop. So, we cache the
4871 * last retried eip and the last fault address, if we meet the eip
4872 * and the address again, we can break out of the potential infinite
4873 * loop.
4874 */
4875 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4876
4877 if (!(emulation_type & EMULTYPE_RETRY))
4878 return false;
4879
4880 if (x86_page_table_writing_insn(ctxt))
4881 return false;
4882
4883 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4884 return false;
4885
4886 vcpu->arch.last_retry_eip = ctxt->eip;
4887 vcpu->arch.last_retry_addr = cr2;
4888
4889 if (!vcpu->arch.mmu.direct_map)
4890 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4891
4892 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4893
4894 return true;
4895 }
4896
4897 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4898 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4899
4900 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4901 unsigned long cr2,
4902 int emulation_type,
4903 void *insn,
4904 int insn_len)
4905 {
4906 int r;
4907 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4908 bool writeback = true;
4909 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
4910
4911 /*
4912 * Clear write_fault_to_shadow_pgtable here to ensure it is
4913 * never reused.
4914 */
4915 vcpu->arch.write_fault_to_shadow_pgtable = false;
4916 kvm_clear_exception_queue(vcpu);
4917
4918 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4919 init_emulate_ctxt(vcpu);
4920 ctxt->interruptibility = 0;
4921 ctxt->have_exception = false;
4922 ctxt->perm_ok = false;
4923
4924 ctxt->only_vendor_specific_insn
4925 = emulation_type & EMULTYPE_TRAP_UD;
4926
4927 r = x86_decode_insn(ctxt, insn, insn_len);
4928
4929 trace_kvm_emulate_insn_start(vcpu);
4930 ++vcpu->stat.insn_emulation;
4931 if (r != EMULATION_OK) {
4932 if (emulation_type & EMULTYPE_TRAP_UD)
4933 return EMULATE_FAIL;
4934 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4935 emulation_type))
4936 return EMULATE_DONE;
4937 if (emulation_type & EMULTYPE_SKIP)
4938 return EMULATE_FAIL;
4939 return handle_emulation_failure(vcpu);
4940 }
4941 }
4942
4943 if (emulation_type & EMULTYPE_SKIP) {
4944 kvm_rip_write(vcpu, ctxt->_eip);
4945 return EMULATE_DONE;
4946 }
4947
4948 if (retry_instruction(ctxt, cr2, emulation_type))
4949 return EMULATE_DONE;
4950
4951 /* this is needed for vmware backdoor interface to work since it
4952 changes registers values during IO operation */
4953 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4954 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4955 emulator_invalidate_register_cache(ctxt);
4956 }
4957
4958 restart:
4959 r = x86_emulate_insn(ctxt);
4960
4961 if (r == EMULATION_INTERCEPTED)
4962 return EMULATE_DONE;
4963
4964 if (r == EMULATION_FAILED) {
4965 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4966 emulation_type))
4967 return EMULATE_DONE;
4968
4969 return handle_emulation_failure(vcpu);
4970 }
4971
4972 if (ctxt->have_exception) {
4973 inject_emulated_exception(vcpu);
4974 r = EMULATE_DONE;
4975 } else if (vcpu->arch.pio.count) {
4976 if (!vcpu->arch.pio.in)
4977 vcpu->arch.pio.count = 0;
4978 else {
4979 writeback = false;
4980 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4981 }
4982 r = EMULATE_DO_MMIO;
4983 } else if (vcpu->mmio_needed) {
4984 if (!vcpu->mmio_is_write)
4985 writeback = false;
4986 r = EMULATE_DO_MMIO;
4987 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
4988 } else if (r == EMULATION_RESTART)
4989 goto restart;
4990 else
4991 r = EMULATE_DONE;
4992
4993 if (writeback) {
4994 toggle_interruptibility(vcpu, ctxt->interruptibility);
4995 kvm_set_rflags(vcpu, ctxt->eflags);
4996 kvm_make_request(KVM_REQ_EVENT, vcpu);
4997 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4998 kvm_rip_write(vcpu, ctxt->eip);
4999 } else
5000 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5001
5002 return r;
5003 }
5004 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5005
5006 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5007 {
5008 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5009 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5010 size, port, &val, 1);
5011 /* do not return to emulator after return from userspace */
5012 vcpu->arch.pio.count = 0;
5013 return ret;
5014 }
5015 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5016
5017 static void tsc_bad(void *info)
5018 {
5019 __this_cpu_write(cpu_tsc_khz, 0);
5020 }
5021
5022 static void tsc_khz_changed(void *data)
5023 {
5024 struct cpufreq_freqs *freq = data;
5025 unsigned long khz = 0;
5026
5027 if (data)
5028 khz = freq->new;
5029 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5030 khz = cpufreq_quick_get(raw_smp_processor_id());
5031 if (!khz)
5032 khz = tsc_khz;
5033 __this_cpu_write(cpu_tsc_khz, khz);
5034 }
5035
5036 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5037 void *data)
5038 {
5039 struct cpufreq_freqs *freq = data;
5040 struct kvm *kvm;
5041 struct kvm_vcpu *vcpu;
5042 int i, send_ipi = 0;
5043
5044 /*
5045 * We allow guests to temporarily run on slowing clocks,
5046 * provided we notify them after, or to run on accelerating
5047 * clocks, provided we notify them before. Thus time never
5048 * goes backwards.
5049 *
5050 * However, we have a problem. We can't atomically update
5051 * the frequency of a given CPU from this function; it is
5052 * merely a notifier, which can be called from any CPU.
5053 * Changing the TSC frequency at arbitrary points in time
5054 * requires a recomputation of local variables related to
5055 * the TSC for each VCPU. We must flag these local variables
5056 * to be updated and be sure the update takes place with the
5057 * new frequency before any guests proceed.
5058 *
5059 * Unfortunately, the combination of hotplug CPU and frequency
5060 * change creates an intractable locking scenario; the order
5061 * of when these callouts happen is undefined with respect to
5062 * CPU hotplug, and they can race with each other. As such,
5063 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5064 * undefined; you can actually have a CPU frequency change take
5065 * place in between the computation of X and the setting of the
5066 * variable. To protect against this problem, all updates of
5067 * the per_cpu tsc_khz variable are done in an interrupt
5068 * protected IPI, and all callers wishing to update the value
5069 * must wait for a synchronous IPI to complete (which is trivial
5070 * if the caller is on the CPU already). This establishes the
5071 * necessary total order on variable updates.
5072 *
5073 * Note that because a guest time update may take place
5074 * anytime after the setting of the VCPU's request bit, the
5075 * correct TSC value must be set before the request. However,
5076 * to ensure the update actually makes it to any guest which
5077 * starts running in hardware virtualization between the set
5078 * and the acquisition of the spinlock, we must also ping the
5079 * CPU after setting the request bit.
5080 *
5081 */
5082
5083 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5084 return 0;
5085 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5086 return 0;
5087
5088 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5089
5090 raw_spin_lock(&kvm_lock);
5091 list_for_each_entry(kvm, &vm_list, vm_list) {
5092 kvm_for_each_vcpu(i, vcpu, kvm) {
5093 if (vcpu->cpu != freq->cpu)
5094 continue;
5095 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5096 if (vcpu->cpu != smp_processor_id())
5097 send_ipi = 1;
5098 }
5099 }
5100 raw_spin_unlock(&kvm_lock);
5101
5102 if (freq->old < freq->new && send_ipi) {
5103 /*
5104 * We upscale the frequency. Must make the guest
5105 * doesn't see old kvmclock values while running with
5106 * the new frequency, otherwise we risk the guest sees
5107 * time go backwards.
5108 *
5109 * In case we update the frequency for another cpu
5110 * (which might be in guest context) send an interrupt
5111 * to kick the cpu out of guest context. Next time
5112 * guest context is entered kvmclock will be updated,
5113 * so the guest will not see stale values.
5114 */
5115 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5116 }
5117 return 0;
5118 }
5119
5120 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5121 .notifier_call = kvmclock_cpufreq_notifier
5122 };
5123
5124 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5125 unsigned long action, void *hcpu)
5126 {
5127 unsigned int cpu = (unsigned long)hcpu;
5128
5129 switch (action) {
5130 case CPU_ONLINE:
5131 case CPU_DOWN_FAILED:
5132 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5133 break;
5134 case CPU_DOWN_PREPARE:
5135 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5136 break;
5137 }
5138 return NOTIFY_OK;
5139 }
5140
5141 static struct notifier_block kvmclock_cpu_notifier_block = {
5142 .notifier_call = kvmclock_cpu_notifier,
5143 .priority = -INT_MAX
5144 };
5145
5146 static void kvm_timer_init(void)
5147 {
5148 int cpu;
5149
5150 max_tsc_khz = tsc_khz;
5151 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5152 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5153 #ifdef CONFIG_CPU_FREQ
5154 struct cpufreq_policy policy;
5155 memset(&policy, 0, sizeof(policy));
5156 cpu = get_cpu();
5157 cpufreq_get_policy(&policy, cpu);
5158 if (policy.cpuinfo.max_freq)
5159 max_tsc_khz = policy.cpuinfo.max_freq;
5160 put_cpu();
5161 #endif
5162 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5163 CPUFREQ_TRANSITION_NOTIFIER);
5164 }
5165 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5166 for_each_online_cpu(cpu)
5167 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5168 }
5169
5170 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5171
5172 int kvm_is_in_guest(void)
5173 {
5174 return __this_cpu_read(current_vcpu) != NULL;
5175 }
5176
5177 static int kvm_is_user_mode(void)
5178 {
5179 int user_mode = 3;
5180
5181 if (__this_cpu_read(current_vcpu))
5182 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5183
5184 return user_mode != 0;
5185 }
5186
5187 static unsigned long kvm_get_guest_ip(void)
5188 {
5189 unsigned long ip = 0;
5190
5191 if (__this_cpu_read(current_vcpu))
5192 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5193
5194 return ip;
5195 }
5196
5197 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5198 .is_in_guest = kvm_is_in_guest,
5199 .is_user_mode = kvm_is_user_mode,
5200 .get_guest_ip = kvm_get_guest_ip,
5201 };
5202
5203 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5204 {
5205 __this_cpu_write(current_vcpu, vcpu);
5206 }
5207 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5208
5209 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5210 {
5211 __this_cpu_write(current_vcpu, NULL);
5212 }
5213 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5214
5215 static void kvm_set_mmio_spte_mask(void)
5216 {
5217 u64 mask;
5218 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5219
5220 /*
5221 * Set the reserved bits and the present bit of an paging-structure
5222 * entry to generate page fault with PFER.RSV = 1.
5223 */
5224 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5225 mask |= 1ull;
5226
5227 #ifdef CONFIG_X86_64
5228 /*
5229 * If reserved bit is not supported, clear the present bit to disable
5230 * mmio page fault.
5231 */
5232 if (maxphyaddr == 52)
5233 mask &= ~1ull;
5234 #endif
5235
5236 kvm_mmu_set_mmio_spte_mask(mask);
5237 }
5238
5239 #ifdef CONFIG_X86_64
5240 static void pvclock_gtod_update_fn(struct work_struct *work)
5241 {
5242 struct kvm *kvm;
5243
5244 struct kvm_vcpu *vcpu;
5245 int i;
5246
5247 raw_spin_lock(&kvm_lock);
5248 list_for_each_entry(kvm, &vm_list, vm_list)
5249 kvm_for_each_vcpu(i, vcpu, kvm)
5250 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5251 atomic_set(&kvm_guest_has_master_clock, 0);
5252 raw_spin_unlock(&kvm_lock);
5253 }
5254
5255 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5256
5257 /*
5258 * Notification about pvclock gtod data update.
5259 */
5260 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5261 void *priv)
5262 {
5263 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5264 struct timekeeper *tk = priv;
5265
5266 update_pvclock_gtod(tk);
5267
5268 /* disable master clock if host does not trust, or does not
5269 * use, TSC clocksource
5270 */
5271 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5272 atomic_read(&kvm_guest_has_master_clock) != 0)
5273 queue_work(system_long_wq, &pvclock_gtod_work);
5274
5275 return 0;
5276 }
5277
5278 static struct notifier_block pvclock_gtod_notifier = {
5279 .notifier_call = pvclock_gtod_notify,
5280 };
5281 #endif
5282
5283 int kvm_arch_init(void *opaque)
5284 {
5285 int r;
5286 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5287
5288 if (kvm_x86_ops) {
5289 printk(KERN_ERR "kvm: already loaded the other module\n");
5290 r = -EEXIST;
5291 goto out;
5292 }
5293
5294 if (!ops->cpu_has_kvm_support()) {
5295 printk(KERN_ERR "kvm: no hardware support\n");
5296 r = -EOPNOTSUPP;
5297 goto out;
5298 }
5299 if (ops->disabled_by_bios()) {
5300 printk(KERN_ERR "kvm: disabled by bios\n");
5301 r = -EOPNOTSUPP;
5302 goto out;
5303 }
5304
5305 r = -ENOMEM;
5306 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5307 if (!shared_msrs) {
5308 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5309 goto out;
5310 }
5311
5312 r = kvm_mmu_module_init();
5313 if (r)
5314 goto out_free_percpu;
5315
5316 kvm_set_mmio_spte_mask();
5317 kvm_init_msr_list();
5318
5319 kvm_x86_ops = ops;
5320 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5321 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5322
5323 kvm_timer_init();
5324
5325 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5326
5327 if (cpu_has_xsave)
5328 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5329
5330 kvm_lapic_init();
5331 #ifdef CONFIG_X86_64
5332 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5333 #endif
5334
5335 return 0;
5336
5337 out_free_percpu:
5338 free_percpu(shared_msrs);
5339 out:
5340 return r;
5341 }
5342
5343 void kvm_arch_exit(void)
5344 {
5345 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5346
5347 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5348 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5349 CPUFREQ_TRANSITION_NOTIFIER);
5350 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5351 #ifdef CONFIG_X86_64
5352 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5353 #endif
5354 kvm_x86_ops = NULL;
5355 kvm_mmu_module_exit();
5356 free_percpu(shared_msrs);
5357 }
5358
5359 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5360 {
5361 ++vcpu->stat.halt_exits;
5362 if (irqchip_in_kernel(vcpu->kvm)) {
5363 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5364 return 1;
5365 } else {
5366 vcpu->run->exit_reason = KVM_EXIT_HLT;
5367 return 0;
5368 }
5369 }
5370 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5371
5372 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5373 {
5374 u64 param, ingpa, outgpa, ret;
5375 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5376 bool fast, longmode;
5377 int cs_db, cs_l;
5378
5379 /*
5380 * hypercall generates UD from non zero cpl and real mode
5381 * per HYPER-V spec
5382 */
5383 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5384 kvm_queue_exception(vcpu, UD_VECTOR);
5385 return 0;
5386 }
5387
5388 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5389 longmode = is_long_mode(vcpu) && cs_l == 1;
5390
5391 if (!longmode) {
5392 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5393 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5394 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5395 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5396 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5397 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5398 }
5399 #ifdef CONFIG_X86_64
5400 else {
5401 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5402 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5403 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5404 }
5405 #endif
5406
5407 code = param & 0xffff;
5408 fast = (param >> 16) & 0x1;
5409 rep_cnt = (param >> 32) & 0xfff;
5410 rep_idx = (param >> 48) & 0xfff;
5411
5412 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5413
5414 switch (code) {
5415 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5416 kvm_vcpu_on_spin(vcpu);
5417 break;
5418 default:
5419 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5420 break;
5421 }
5422
5423 ret = res | (((u64)rep_done & 0xfff) << 32);
5424 if (longmode) {
5425 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5426 } else {
5427 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5428 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5429 }
5430
5431 return 1;
5432 }
5433
5434 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5435 {
5436 unsigned long nr, a0, a1, a2, a3, ret;
5437 int r = 1;
5438
5439 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5440 return kvm_hv_hypercall(vcpu);
5441
5442 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5443 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5444 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5445 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5446 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5447
5448 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5449
5450 if (!is_long_mode(vcpu)) {
5451 nr &= 0xFFFFFFFF;
5452 a0 &= 0xFFFFFFFF;
5453 a1 &= 0xFFFFFFFF;
5454 a2 &= 0xFFFFFFFF;
5455 a3 &= 0xFFFFFFFF;
5456 }
5457
5458 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5459 ret = -KVM_EPERM;
5460 goto out;
5461 }
5462
5463 switch (nr) {
5464 case KVM_HC_VAPIC_POLL_IRQ:
5465 ret = 0;
5466 break;
5467 default:
5468 ret = -KVM_ENOSYS;
5469 break;
5470 }
5471 out:
5472 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5473 ++vcpu->stat.hypercalls;
5474 return r;
5475 }
5476 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5477
5478 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5479 {
5480 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5481 char instruction[3];
5482 unsigned long rip = kvm_rip_read(vcpu);
5483
5484 /*
5485 * Blow out the MMU to ensure that no other VCPU has an active mapping
5486 * to ensure that the updated hypercall appears atomically across all
5487 * VCPUs.
5488 */
5489 kvm_mmu_zap_all(vcpu->kvm);
5490
5491 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5492
5493 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5494 }
5495
5496 /*
5497 * Check if userspace requested an interrupt window, and that the
5498 * interrupt window is open.
5499 *
5500 * No need to exit to userspace if we already have an interrupt queued.
5501 */
5502 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5503 {
5504 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5505 vcpu->run->request_interrupt_window &&
5506 kvm_arch_interrupt_allowed(vcpu));
5507 }
5508
5509 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5510 {
5511 struct kvm_run *kvm_run = vcpu->run;
5512
5513 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5514 kvm_run->cr8 = kvm_get_cr8(vcpu);
5515 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5516 if (irqchip_in_kernel(vcpu->kvm))
5517 kvm_run->ready_for_interrupt_injection = 1;
5518 else
5519 kvm_run->ready_for_interrupt_injection =
5520 kvm_arch_interrupt_allowed(vcpu) &&
5521 !kvm_cpu_has_interrupt(vcpu) &&
5522 !kvm_event_needs_reinjection(vcpu);
5523 }
5524
5525 static int vapic_enter(struct kvm_vcpu *vcpu)
5526 {
5527 struct kvm_lapic *apic = vcpu->arch.apic;
5528 struct page *page;
5529
5530 if (!apic || !apic->vapic_addr)
5531 return 0;
5532
5533 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5534 if (is_error_page(page))
5535 return -EFAULT;
5536
5537 vcpu->arch.apic->vapic_page = page;
5538 return 0;
5539 }
5540
5541 static void vapic_exit(struct kvm_vcpu *vcpu)
5542 {
5543 struct kvm_lapic *apic = vcpu->arch.apic;
5544 int idx;
5545
5546 if (!apic || !apic->vapic_addr)
5547 return;
5548
5549 idx = srcu_read_lock(&vcpu->kvm->srcu);
5550 kvm_release_page_dirty(apic->vapic_page);
5551 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5552 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5553 }
5554
5555 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5556 {
5557 int max_irr, tpr;
5558
5559 if (!kvm_x86_ops->update_cr8_intercept)
5560 return;
5561
5562 if (!vcpu->arch.apic)
5563 return;
5564
5565 if (!vcpu->arch.apic->vapic_addr)
5566 max_irr = kvm_lapic_find_highest_irr(vcpu);
5567 else
5568 max_irr = -1;
5569
5570 if (max_irr != -1)
5571 max_irr >>= 4;
5572
5573 tpr = kvm_lapic_get_cr8(vcpu);
5574
5575 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5576 }
5577
5578 static void inject_pending_event(struct kvm_vcpu *vcpu)
5579 {
5580 /* try to reinject previous events if any */
5581 if (vcpu->arch.exception.pending) {
5582 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5583 vcpu->arch.exception.has_error_code,
5584 vcpu->arch.exception.error_code);
5585 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5586 vcpu->arch.exception.has_error_code,
5587 vcpu->arch.exception.error_code,
5588 vcpu->arch.exception.reinject);
5589 return;
5590 }
5591
5592 if (vcpu->arch.nmi_injected) {
5593 kvm_x86_ops->set_nmi(vcpu);
5594 return;
5595 }
5596
5597 if (vcpu->arch.interrupt.pending) {
5598 kvm_x86_ops->set_irq(vcpu);
5599 return;
5600 }
5601
5602 /* try to inject new event if pending */
5603 if (vcpu->arch.nmi_pending) {
5604 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5605 --vcpu->arch.nmi_pending;
5606 vcpu->arch.nmi_injected = true;
5607 kvm_x86_ops->set_nmi(vcpu);
5608 }
5609 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5610 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5611 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5612 false);
5613 kvm_x86_ops->set_irq(vcpu);
5614 }
5615 }
5616 }
5617
5618 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5619 {
5620 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5621 !vcpu->guest_xcr0_loaded) {
5622 /* kvm_set_xcr() also depends on this */
5623 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5624 vcpu->guest_xcr0_loaded = 1;
5625 }
5626 }
5627
5628 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5629 {
5630 if (vcpu->guest_xcr0_loaded) {
5631 if (vcpu->arch.xcr0 != host_xcr0)
5632 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5633 vcpu->guest_xcr0_loaded = 0;
5634 }
5635 }
5636
5637 static void process_nmi(struct kvm_vcpu *vcpu)
5638 {
5639 unsigned limit = 2;
5640
5641 /*
5642 * x86 is limited to one NMI running, and one NMI pending after it.
5643 * If an NMI is already in progress, limit further NMIs to just one.
5644 * Otherwise, allow two (and we'll inject the first one immediately).
5645 */
5646 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5647 limit = 1;
5648
5649 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5650 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5651 kvm_make_request(KVM_REQ_EVENT, vcpu);
5652 }
5653
5654 static void kvm_gen_update_masterclock(struct kvm *kvm)
5655 {
5656 #ifdef CONFIG_X86_64
5657 int i;
5658 struct kvm_vcpu *vcpu;
5659 struct kvm_arch *ka = &kvm->arch;
5660
5661 spin_lock(&ka->pvclock_gtod_sync_lock);
5662 kvm_make_mclock_inprogress_request(kvm);
5663 /* no guest entries from this point */
5664 pvclock_update_vm_gtod_copy(kvm);
5665
5666 kvm_for_each_vcpu(i, vcpu, kvm)
5667 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5668
5669 /* guest entries allowed */
5670 kvm_for_each_vcpu(i, vcpu, kvm)
5671 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5672
5673 spin_unlock(&ka->pvclock_gtod_sync_lock);
5674 #endif
5675 }
5676
5677 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5678 {
5679 u64 eoi_exit_bitmap[4];
5680 u32 tmr[8];
5681
5682 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5683 return;
5684
5685 memset(eoi_exit_bitmap, 0, 32);
5686 memset(tmr, 0, 32);
5687
5688 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5689 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5690 kvm_apic_update_tmr(vcpu, tmr);
5691 }
5692
5693 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5694 {
5695 int r;
5696 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5697 vcpu->run->request_interrupt_window;
5698 bool req_immediate_exit = false;
5699
5700 if (vcpu->requests) {
5701 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5702 kvm_mmu_unload(vcpu);
5703 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5704 __kvm_migrate_timers(vcpu);
5705 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5706 kvm_gen_update_masterclock(vcpu->kvm);
5707 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5708 r = kvm_guest_time_update(vcpu);
5709 if (unlikely(r))
5710 goto out;
5711 }
5712 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5713 kvm_mmu_sync_roots(vcpu);
5714 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5715 kvm_x86_ops->tlb_flush(vcpu);
5716 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5717 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5718 r = 0;
5719 goto out;
5720 }
5721 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5722 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5723 r = 0;
5724 goto out;
5725 }
5726 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5727 vcpu->fpu_active = 0;
5728 kvm_x86_ops->fpu_deactivate(vcpu);
5729 }
5730 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5731 /* Page is swapped out. Do synthetic halt */
5732 vcpu->arch.apf.halted = true;
5733 r = 1;
5734 goto out;
5735 }
5736 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5737 record_steal_time(vcpu);
5738 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5739 process_nmi(vcpu);
5740 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5741 kvm_handle_pmu_event(vcpu);
5742 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5743 kvm_deliver_pmi(vcpu);
5744 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5745 vcpu_scan_ioapic(vcpu);
5746 }
5747
5748 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5749 kvm_apic_accept_events(vcpu);
5750 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5751 r = 1;
5752 goto out;
5753 }
5754
5755 inject_pending_event(vcpu);
5756
5757 /* enable NMI/IRQ window open exits if needed */
5758 if (vcpu->arch.nmi_pending)
5759 req_immediate_exit =
5760 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5761 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5762 req_immediate_exit =
5763 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5764
5765 if (kvm_lapic_enabled(vcpu)) {
5766 /*
5767 * Update architecture specific hints for APIC
5768 * virtual interrupt delivery.
5769 */
5770 if (kvm_x86_ops->hwapic_irr_update)
5771 kvm_x86_ops->hwapic_irr_update(vcpu,
5772 kvm_lapic_find_highest_irr(vcpu));
5773 update_cr8_intercept(vcpu);
5774 kvm_lapic_sync_to_vapic(vcpu);
5775 }
5776 }
5777
5778 r = kvm_mmu_reload(vcpu);
5779 if (unlikely(r)) {
5780 goto cancel_injection;
5781 }
5782
5783 preempt_disable();
5784
5785 kvm_x86_ops->prepare_guest_switch(vcpu);
5786 if (vcpu->fpu_active)
5787 kvm_load_guest_fpu(vcpu);
5788 kvm_load_guest_xcr0(vcpu);
5789
5790 vcpu->mode = IN_GUEST_MODE;
5791
5792 /* We should set ->mode before check ->requests,
5793 * see the comment in make_all_cpus_request.
5794 */
5795 smp_mb();
5796
5797 local_irq_disable();
5798
5799 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5800 || need_resched() || signal_pending(current)) {
5801 vcpu->mode = OUTSIDE_GUEST_MODE;
5802 smp_wmb();
5803 local_irq_enable();
5804 preempt_enable();
5805 r = 1;
5806 goto cancel_injection;
5807 }
5808
5809 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5810
5811 if (req_immediate_exit)
5812 smp_send_reschedule(vcpu->cpu);
5813
5814 kvm_guest_enter();
5815
5816 if (unlikely(vcpu->arch.switch_db_regs)) {
5817 set_debugreg(0, 7);
5818 set_debugreg(vcpu->arch.eff_db[0], 0);
5819 set_debugreg(vcpu->arch.eff_db[1], 1);
5820 set_debugreg(vcpu->arch.eff_db[2], 2);
5821 set_debugreg(vcpu->arch.eff_db[3], 3);
5822 }
5823
5824 trace_kvm_entry(vcpu->vcpu_id);
5825 kvm_x86_ops->run(vcpu);
5826
5827 /*
5828 * If the guest has used debug registers, at least dr7
5829 * will be disabled while returning to the host.
5830 * If we don't have active breakpoints in the host, we don't
5831 * care about the messed up debug address registers. But if
5832 * we have some of them active, restore the old state.
5833 */
5834 if (hw_breakpoint_active())
5835 hw_breakpoint_restore();
5836
5837 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5838 native_read_tsc());
5839
5840 vcpu->mode = OUTSIDE_GUEST_MODE;
5841 smp_wmb();
5842
5843 /* Interrupt is enabled by handle_external_intr() */
5844 kvm_x86_ops->handle_external_intr(vcpu);
5845
5846 ++vcpu->stat.exits;
5847
5848 /*
5849 * We must have an instruction between local_irq_enable() and
5850 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5851 * the interrupt shadow. The stat.exits increment will do nicely.
5852 * But we need to prevent reordering, hence this barrier():
5853 */
5854 barrier();
5855
5856 kvm_guest_exit();
5857
5858 preempt_enable();
5859
5860 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5861
5862 /*
5863 * Profile KVM exit RIPs:
5864 */
5865 if (unlikely(prof_on == KVM_PROFILING)) {
5866 unsigned long rip = kvm_rip_read(vcpu);
5867 profile_hit(KVM_PROFILING, (void *)rip);
5868 }
5869
5870 if (unlikely(vcpu->arch.tsc_always_catchup))
5871 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5872
5873 if (vcpu->arch.apic_attention)
5874 kvm_lapic_sync_from_vapic(vcpu);
5875
5876 r = kvm_x86_ops->handle_exit(vcpu);
5877 return r;
5878
5879 cancel_injection:
5880 kvm_x86_ops->cancel_injection(vcpu);
5881 if (unlikely(vcpu->arch.apic_attention))
5882 kvm_lapic_sync_from_vapic(vcpu);
5883 out:
5884 return r;
5885 }
5886
5887
5888 static int __vcpu_run(struct kvm_vcpu *vcpu)
5889 {
5890 int r;
5891 struct kvm *kvm = vcpu->kvm;
5892
5893 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5894 r = vapic_enter(vcpu);
5895 if (r) {
5896 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5897 return r;
5898 }
5899
5900 r = 1;
5901 while (r > 0) {
5902 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5903 !vcpu->arch.apf.halted)
5904 r = vcpu_enter_guest(vcpu);
5905 else {
5906 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5907 kvm_vcpu_block(vcpu);
5908 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5909 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5910 kvm_apic_accept_events(vcpu);
5911 switch(vcpu->arch.mp_state) {
5912 case KVM_MP_STATE_HALTED:
5913 vcpu->arch.mp_state =
5914 KVM_MP_STATE_RUNNABLE;
5915 case KVM_MP_STATE_RUNNABLE:
5916 vcpu->arch.apf.halted = false;
5917 break;
5918 case KVM_MP_STATE_INIT_RECEIVED:
5919 break;
5920 default:
5921 r = -EINTR;
5922 break;
5923 }
5924 }
5925 }
5926
5927 if (r <= 0)
5928 break;
5929
5930 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5931 if (kvm_cpu_has_pending_timer(vcpu))
5932 kvm_inject_pending_timer_irqs(vcpu);
5933
5934 if (dm_request_for_irq_injection(vcpu)) {
5935 r = -EINTR;
5936 vcpu->run->exit_reason = KVM_EXIT_INTR;
5937 ++vcpu->stat.request_irq_exits;
5938 }
5939
5940 kvm_check_async_pf_completion(vcpu);
5941
5942 if (signal_pending(current)) {
5943 r = -EINTR;
5944 vcpu->run->exit_reason = KVM_EXIT_INTR;
5945 ++vcpu->stat.signal_exits;
5946 }
5947 if (need_resched()) {
5948 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5949 kvm_resched(vcpu);
5950 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5951 }
5952 }
5953
5954 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5955
5956 vapic_exit(vcpu);
5957
5958 return r;
5959 }
5960
5961 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5962 {
5963 int r;
5964 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5965 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5966 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5967 if (r != EMULATE_DONE)
5968 return 0;
5969 return 1;
5970 }
5971
5972 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5973 {
5974 BUG_ON(!vcpu->arch.pio.count);
5975
5976 return complete_emulated_io(vcpu);
5977 }
5978
5979 /*
5980 * Implements the following, as a state machine:
5981 *
5982 * read:
5983 * for each fragment
5984 * for each mmio piece in the fragment
5985 * write gpa, len
5986 * exit
5987 * copy data
5988 * execute insn
5989 *
5990 * write:
5991 * for each fragment
5992 * for each mmio piece in the fragment
5993 * write gpa, len
5994 * copy data
5995 * exit
5996 */
5997 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5998 {
5999 struct kvm_run *run = vcpu->run;
6000 struct kvm_mmio_fragment *frag;
6001 unsigned len;
6002
6003 BUG_ON(!vcpu->mmio_needed);
6004
6005 /* Complete previous fragment */
6006 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6007 len = min(8u, frag->len);
6008 if (!vcpu->mmio_is_write)
6009 memcpy(frag->data, run->mmio.data, len);
6010
6011 if (frag->len <= 8) {
6012 /* Switch to the next fragment. */
6013 frag++;
6014 vcpu->mmio_cur_fragment++;
6015 } else {
6016 /* Go forward to the next mmio piece. */
6017 frag->data += len;
6018 frag->gpa += len;
6019 frag->len -= len;
6020 }
6021
6022 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6023 vcpu->mmio_needed = 0;
6024 if (vcpu->mmio_is_write)
6025 return 1;
6026 vcpu->mmio_read_completed = 1;
6027 return complete_emulated_io(vcpu);
6028 }
6029
6030 run->exit_reason = KVM_EXIT_MMIO;
6031 run->mmio.phys_addr = frag->gpa;
6032 if (vcpu->mmio_is_write)
6033 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6034 run->mmio.len = min(8u, frag->len);
6035 run->mmio.is_write = vcpu->mmio_is_write;
6036 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6037 return 0;
6038 }
6039
6040
6041 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6042 {
6043 int r;
6044 sigset_t sigsaved;
6045
6046 if (!tsk_used_math(current) && init_fpu(current))
6047 return -ENOMEM;
6048
6049 if (vcpu->sigset_active)
6050 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6051
6052 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6053 kvm_vcpu_block(vcpu);
6054 kvm_apic_accept_events(vcpu);
6055 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6056 r = -EAGAIN;
6057 goto out;
6058 }
6059
6060 /* re-sync apic's tpr */
6061 if (!irqchip_in_kernel(vcpu->kvm)) {
6062 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6063 r = -EINVAL;
6064 goto out;
6065 }
6066 }
6067
6068 if (unlikely(vcpu->arch.complete_userspace_io)) {
6069 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6070 vcpu->arch.complete_userspace_io = NULL;
6071 r = cui(vcpu);
6072 if (r <= 0)
6073 goto out;
6074 } else
6075 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6076
6077 r = __vcpu_run(vcpu);
6078
6079 out:
6080 post_kvm_run_save(vcpu);
6081 if (vcpu->sigset_active)
6082 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6083
6084 return r;
6085 }
6086
6087 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6088 {
6089 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6090 /*
6091 * We are here if userspace calls get_regs() in the middle of
6092 * instruction emulation. Registers state needs to be copied
6093 * back from emulation context to vcpu. Userspace shouldn't do
6094 * that usually, but some bad designed PV devices (vmware
6095 * backdoor interface) need this to work
6096 */
6097 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6098 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6099 }
6100 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6101 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6102 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6103 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6104 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6105 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6106 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6107 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6108 #ifdef CONFIG_X86_64
6109 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6110 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6111 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6112 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6113 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6114 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6115 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6116 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6117 #endif
6118
6119 regs->rip = kvm_rip_read(vcpu);
6120 regs->rflags = kvm_get_rflags(vcpu);
6121
6122 return 0;
6123 }
6124
6125 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6126 {
6127 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6128 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6129
6130 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6131 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6132 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6133 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6134 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6135 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6136 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6137 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6138 #ifdef CONFIG_X86_64
6139 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6140 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6141 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6142 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6143 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6144 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6145 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6146 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6147 #endif
6148
6149 kvm_rip_write(vcpu, regs->rip);
6150 kvm_set_rflags(vcpu, regs->rflags);
6151
6152 vcpu->arch.exception.pending = false;
6153
6154 kvm_make_request(KVM_REQ_EVENT, vcpu);
6155
6156 return 0;
6157 }
6158
6159 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6160 {
6161 struct kvm_segment cs;
6162
6163 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6164 *db = cs.db;
6165 *l = cs.l;
6166 }
6167 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6168
6169 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6170 struct kvm_sregs *sregs)
6171 {
6172 struct desc_ptr dt;
6173
6174 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6175 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6176 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6177 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6178 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6179 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6180
6181 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6182 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6183
6184 kvm_x86_ops->get_idt(vcpu, &dt);
6185 sregs->idt.limit = dt.size;
6186 sregs->idt.base = dt.address;
6187 kvm_x86_ops->get_gdt(vcpu, &dt);
6188 sregs->gdt.limit = dt.size;
6189 sregs->gdt.base = dt.address;
6190
6191 sregs->cr0 = kvm_read_cr0(vcpu);
6192 sregs->cr2 = vcpu->arch.cr2;
6193 sregs->cr3 = kvm_read_cr3(vcpu);
6194 sregs->cr4 = kvm_read_cr4(vcpu);
6195 sregs->cr8 = kvm_get_cr8(vcpu);
6196 sregs->efer = vcpu->arch.efer;
6197 sregs->apic_base = kvm_get_apic_base(vcpu);
6198
6199 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6200
6201 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6202 set_bit(vcpu->arch.interrupt.nr,
6203 (unsigned long *)sregs->interrupt_bitmap);
6204
6205 return 0;
6206 }
6207
6208 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6209 struct kvm_mp_state *mp_state)
6210 {
6211 kvm_apic_accept_events(vcpu);
6212 mp_state->mp_state = vcpu->arch.mp_state;
6213 return 0;
6214 }
6215
6216 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6217 struct kvm_mp_state *mp_state)
6218 {
6219 if (!kvm_vcpu_has_lapic(vcpu) &&
6220 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6221 return -EINVAL;
6222
6223 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6224 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6225 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6226 } else
6227 vcpu->arch.mp_state = mp_state->mp_state;
6228 kvm_make_request(KVM_REQ_EVENT, vcpu);
6229 return 0;
6230 }
6231
6232 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6233 int reason, bool has_error_code, u32 error_code)
6234 {
6235 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6236 int ret;
6237
6238 init_emulate_ctxt(vcpu);
6239
6240 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6241 has_error_code, error_code);
6242
6243 if (ret)
6244 return EMULATE_FAIL;
6245
6246 kvm_rip_write(vcpu, ctxt->eip);
6247 kvm_set_rflags(vcpu, ctxt->eflags);
6248 kvm_make_request(KVM_REQ_EVENT, vcpu);
6249 return EMULATE_DONE;
6250 }
6251 EXPORT_SYMBOL_GPL(kvm_task_switch);
6252
6253 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6254 struct kvm_sregs *sregs)
6255 {
6256 int mmu_reset_needed = 0;
6257 int pending_vec, max_bits, idx;
6258 struct desc_ptr dt;
6259
6260 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6261 return -EINVAL;
6262
6263 dt.size = sregs->idt.limit;
6264 dt.address = sregs->idt.base;
6265 kvm_x86_ops->set_idt(vcpu, &dt);
6266 dt.size = sregs->gdt.limit;
6267 dt.address = sregs->gdt.base;
6268 kvm_x86_ops->set_gdt(vcpu, &dt);
6269
6270 vcpu->arch.cr2 = sregs->cr2;
6271 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6272 vcpu->arch.cr3 = sregs->cr3;
6273 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6274
6275 kvm_set_cr8(vcpu, sregs->cr8);
6276
6277 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6278 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6279 kvm_set_apic_base(vcpu, sregs->apic_base);
6280
6281 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6282 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6283 vcpu->arch.cr0 = sregs->cr0;
6284
6285 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6286 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6287 if (sregs->cr4 & X86_CR4_OSXSAVE)
6288 kvm_update_cpuid(vcpu);
6289
6290 idx = srcu_read_lock(&vcpu->kvm->srcu);
6291 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6292 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6293 mmu_reset_needed = 1;
6294 }
6295 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6296
6297 if (mmu_reset_needed)
6298 kvm_mmu_reset_context(vcpu);
6299
6300 max_bits = KVM_NR_INTERRUPTS;
6301 pending_vec = find_first_bit(
6302 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6303 if (pending_vec < max_bits) {
6304 kvm_queue_interrupt(vcpu, pending_vec, false);
6305 pr_debug("Set back pending irq %d\n", pending_vec);
6306 }
6307
6308 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6309 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6310 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6311 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6312 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6313 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6314
6315 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6316 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6317
6318 update_cr8_intercept(vcpu);
6319
6320 /* Older userspace won't unhalt the vcpu on reset. */
6321 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6322 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6323 !is_protmode(vcpu))
6324 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6325
6326 kvm_make_request(KVM_REQ_EVENT, vcpu);
6327
6328 return 0;
6329 }
6330
6331 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6332 struct kvm_guest_debug *dbg)
6333 {
6334 unsigned long rflags;
6335 int i, r;
6336
6337 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6338 r = -EBUSY;
6339 if (vcpu->arch.exception.pending)
6340 goto out;
6341 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6342 kvm_queue_exception(vcpu, DB_VECTOR);
6343 else
6344 kvm_queue_exception(vcpu, BP_VECTOR);
6345 }
6346
6347 /*
6348 * Read rflags as long as potentially injected trace flags are still
6349 * filtered out.
6350 */
6351 rflags = kvm_get_rflags(vcpu);
6352
6353 vcpu->guest_debug = dbg->control;
6354 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6355 vcpu->guest_debug = 0;
6356
6357 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6358 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6359 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6360 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6361 } else {
6362 for (i = 0; i < KVM_NR_DB_REGS; i++)
6363 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6364 }
6365 kvm_update_dr7(vcpu);
6366
6367 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6368 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6369 get_segment_base(vcpu, VCPU_SREG_CS);
6370
6371 /*
6372 * Trigger an rflags update that will inject or remove the trace
6373 * flags.
6374 */
6375 kvm_set_rflags(vcpu, rflags);
6376
6377 kvm_x86_ops->update_db_bp_intercept(vcpu);
6378
6379 r = 0;
6380
6381 out:
6382
6383 return r;
6384 }
6385
6386 /*
6387 * Translate a guest virtual address to a guest physical address.
6388 */
6389 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6390 struct kvm_translation *tr)
6391 {
6392 unsigned long vaddr = tr->linear_address;
6393 gpa_t gpa;
6394 int idx;
6395
6396 idx = srcu_read_lock(&vcpu->kvm->srcu);
6397 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6398 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6399 tr->physical_address = gpa;
6400 tr->valid = gpa != UNMAPPED_GVA;
6401 tr->writeable = 1;
6402 tr->usermode = 0;
6403
6404 return 0;
6405 }
6406
6407 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6408 {
6409 struct i387_fxsave_struct *fxsave =
6410 &vcpu->arch.guest_fpu.state->fxsave;
6411
6412 memcpy(fpu->fpr, fxsave->st_space, 128);
6413 fpu->fcw = fxsave->cwd;
6414 fpu->fsw = fxsave->swd;
6415 fpu->ftwx = fxsave->twd;
6416 fpu->last_opcode = fxsave->fop;
6417 fpu->last_ip = fxsave->rip;
6418 fpu->last_dp = fxsave->rdp;
6419 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6420
6421 return 0;
6422 }
6423
6424 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6425 {
6426 struct i387_fxsave_struct *fxsave =
6427 &vcpu->arch.guest_fpu.state->fxsave;
6428
6429 memcpy(fxsave->st_space, fpu->fpr, 128);
6430 fxsave->cwd = fpu->fcw;
6431 fxsave->swd = fpu->fsw;
6432 fxsave->twd = fpu->ftwx;
6433 fxsave->fop = fpu->last_opcode;
6434 fxsave->rip = fpu->last_ip;
6435 fxsave->rdp = fpu->last_dp;
6436 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6437
6438 return 0;
6439 }
6440
6441 int fx_init(struct kvm_vcpu *vcpu)
6442 {
6443 int err;
6444
6445 err = fpu_alloc(&vcpu->arch.guest_fpu);
6446 if (err)
6447 return err;
6448
6449 fpu_finit(&vcpu->arch.guest_fpu);
6450
6451 /*
6452 * Ensure guest xcr0 is valid for loading
6453 */
6454 vcpu->arch.xcr0 = XSTATE_FP;
6455
6456 vcpu->arch.cr0 |= X86_CR0_ET;
6457
6458 return 0;
6459 }
6460 EXPORT_SYMBOL_GPL(fx_init);
6461
6462 static void fx_free(struct kvm_vcpu *vcpu)
6463 {
6464 fpu_free(&vcpu->arch.guest_fpu);
6465 }
6466
6467 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6468 {
6469 if (vcpu->guest_fpu_loaded)
6470 return;
6471
6472 /*
6473 * Restore all possible states in the guest,
6474 * and assume host would use all available bits.
6475 * Guest xcr0 would be loaded later.
6476 */
6477 kvm_put_guest_xcr0(vcpu);
6478 vcpu->guest_fpu_loaded = 1;
6479 __kernel_fpu_begin();
6480 fpu_restore_checking(&vcpu->arch.guest_fpu);
6481 trace_kvm_fpu(1);
6482 }
6483
6484 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6485 {
6486 kvm_put_guest_xcr0(vcpu);
6487
6488 if (!vcpu->guest_fpu_loaded)
6489 return;
6490
6491 vcpu->guest_fpu_loaded = 0;
6492 fpu_save_init(&vcpu->arch.guest_fpu);
6493 __kernel_fpu_end();
6494 ++vcpu->stat.fpu_reload;
6495 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6496 trace_kvm_fpu(0);
6497 }
6498
6499 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6500 {
6501 kvmclock_reset(vcpu);
6502
6503 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6504 fx_free(vcpu);
6505 kvm_x86_ops->vcpu_free(vcpu);
6506 }
6507
6508 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6509 unsigned int id)
6510 {
6511 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6512 printk_once(KERN_WARNING
6513 "kvm: SMP vm created on host with unstable TSC; "
6514 "guest TSC will not be reliable\n");
6515 return kvm_x86_ops->vcpu_create(kvm, id);
6516 }
6517
6518 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6519 {
6520 int r;
6521
6522 vcpu->arch.mtrr_state.have_fixed = 1;
6523 r = vcpu_load(vcpu);
6524 if (r)
6525 return r;
6526 kvm_vcpu_reset(vcpu);
6527 r = kvm_mmu_setup(vcpu);
6528 vcpu_put(vcpu);
6529
6530 return r;
6531 }
6532
6533 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6534 {
6535 int r;
6536 struct msr_data msr;
6537
6538 r = vcpu_load(vcpu);
6539 if (r)
6540 return r;
6541 msr.data = 0x0;
6542 msr.index = MSR_IA32_TSC;
6543 msr.host_initiated = true;
6544 kvm_write_tsc(vcpu, &msr);
6545 vcpu_put(vcpu);
6546
6547 return r;
6548 }
6549
6550 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6551 {
6552 int r;
6553 vcpu->arch.apf.msr_val = 0;
6554
6555 r = vcpu_load(vcpu);
6556 BUG_ON(r);
6557 kvm_mmu_unload(vcpu);
6558 vcpu_put(vcpu);
6559
6560 fx_free(vcpu);
6561 kvm_x86_ops->vcpu_free(vcpu);
6562 }
6563
6564 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6565 {
6566 atomic_set(&vcpu->arch.nmi_queued, 0);
6567 vcpu->arch.nmi_pending = 0;
6568 vcpu->arch.nmi_injected = false;
6569
6570 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6571 vcpu->arch.dr6 = DR6_FIXED_1;
6572 vcpu->arch.dr7 = DR7_FIXED_1;
6573 kvm_update_dr7(vcpu);
6574
6575 kvm_make_request(KVM_REQ_EVENT, vcpu);
6576 vcpu->arch.apf.msr_val = 0;
6577 vcpu->arch.st.msr_val = 0;
6578
6579 kvmclock_reset(vcpu);
6580
6581 kvm_clear_async_pf_completion_queue(vcpu);
6582 kvm_async_pf_hash_reset(vcpu);
6583 vcpu->arch.apf.halted = false;
6584
6585 kvm_pmu_reset(vcpu);
6586
6587 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6588 vcpu->arch.regs_avail = ~0;
6589 vcpu->arch.regs_dirty = ~0;
6590
6591 kvm_x86_ops->vcpu_reset(vcpu);
6592 }
6593
6594 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6595 {
6596 struct kvm_segment cs;
6597
6598 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6599 cs.selector = vector << 8;
6600 cs.base = vector << 12;
6601 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6602 kvm_rip_write(vcpu, 0);
6603 }
6604
6605 int kvm_arch_hardware_enable(void *garbage)
6606 {
6607 struct kvm *kvm;
6608 struct kvm_vcpu *vcpu;
6609 int i;
6610 int ret;
6611 u64 local_tsc;
6612 u64 max_tsc = 0;
6613 bool stable, backwards_tsc = false;
6614
6615 kvm_shared_msr_cpu_online();
6616 ret = kvm_x86_ops->hardware_enable(garbage);
6617 if (ret != 0)
6618 return ret;
6619
6620 local_tsc = native_read_tsc();
6621 stable = !check_tsc_unstable();
6622 list_for_each_entry(kvm, &vm_list, vm_list) {
6623 kvm_for_each_vcpu(i, vcpu, kvm) {
6624 if (!stable && vcpu->cpu == smp_processor_id())
6625 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6626 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6627 backwards_tsc = true;
6628 if (vcpu->arch.last_host_tsc > max_tsc)
6629 max_tsc = vcpu->arch.last_host_tsc;
6630 }
6631 }
6632 }
6633
6634 /*
6635 * Sometimes, even reliable TSCs go backwards. This happens on
6636 * platforms that reset TSC during suspend or hibernate actions, but
6637 * maintain synchronization. We must compensate. Fortunately, we can
6638 * detect that condition here, which happens early in CPU bringup,
6639 * before any KVM threads can be running. Unfortunately, we can't
6640 * bring the TSCs fully up to date with real time, as we aren't yet far
6641 * enough into CPU bringup that we know how much real time has actually
6642 * elapsed; our helper function, get_kernel_ns() will be using boot
6643 * variables that haven't been updated yet.
6644 *
6645 * So we simply find the maximum observed TSC above, then record the
6646 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6647 * the adjustment will be applied. Note that we accumulate
6648 * adjustments, in case multiple suspend cycles happen before some VCPU
6649 * gets a chance to run again. In the event that no KVM threads get a
6650 * chance to run, we will miss the entire elapsed period, as we'll have
6651 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6652 * loose cycle time. This isn't too big a deal, since the loss will be
6653 * uniform across all VCPUs (not to mention the scenario is extremely
6654 * unlikely). It is possible that a second hibernate recovery happens
6655 * much faster than a first, causing the observed TSC here to be
6656 * smaller; this would require additional padding adjustment, which is
6657 * why we set last_host_tsc to the local tsc observed here.
6658 *
6659 * N.B. - this code below runs only on platforms with reliable TSC,
6660 * as that is the only way backwards_tsc is set above. Also note
6661 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6662 * have the same delta_cyc adjustment applied if backwards_tsc
6663 * is detected. Note further, this adjustment is only done once,
6664 * as we reset last_host_tsc on all VCPUs to stop this from being
6665 * called multiple times (one for each physical CPU bringup).
6666 *
6667 * Platforms with unreliable TSCs don't have to deal with this, they
6668 * will be compensated by the logic in vcpu_load, which sets the TSC to
6669 * catchup mode. This will catchup all VCPUs to real time, but cannot
6670 * guarantee that they stay in perfect synchronization.
6671 */
6672 if (backwards_tsc) {
6673 u64 delta_cyc = max_tsc - local_tsc;
6674 list_for_each_entry(kvm, &vm_list, vm_list) {
6675 kvm_for_each_vcpu(i, vcpu, kvm) {
6676 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6677 vcpu->arch.last_host_tsc = local_tsc;
6678 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6679 &vcpu->requests);
6680 }
6681
6682 /*
6683 * We have to disable TSC offset matching.. if you were
6684 * booting a VM while issuing an S4 host suspend....
6685 * you may have some problem. Solving this issue is
6686 * left as an exercise to the reader.
6687 */
6688 kvm->arch.last_tsc_nsec = 0;
6689 kvm->arch.last_tsc_write = 0;
6690 }
6691
6692 }
6693 return 0;
6694 }
6695
6696 void kvm_arch_hardware_disable(void *garbage)
6697 {
6698 kvm_x86_ops->hardware_disable(garbage);
6699 drop_user_return_notifiers(garbage);
6700 }
6701
6702 int kvm_arch_hardware_setup(void)
6703 {
6704 return kvm_x86_ops->hardware_setup();
6705 }
6706
6707 void kvm_arch_hardware_unsetup(void)
6708 {
6709 kvm_x86_ops->hardware_unsetup();
6710 }
6711
6712 void kvm_arch_check_processor_compat(void *rtn)
6713 {
6714 kvm_x86_ops->check_processor_compatibility(rtn);
6715 }
6716
6717 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6718 {
6719 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6720 }
6721
6722 struct static_key kvm_no_apic_vcpu __read_mostly;
6723
6724 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6725 {
6726 struct page *page;
6727 struct kvm *kvm;
6728 int r;
6729
6730 BUG_ON(vcpu->kvm == NULL);
6731 kvm = vcpu->kvm;
6732
6733 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6734 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6735 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6736 else
6737 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6738
6739 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6740 if (!page) {
6741 r = -ENOMEM;
6742 goto fail;
6743 }
6744 vcpu->arch.pio_data = page_address(page);
6745
6746 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6747
6748 r = kvm_mmu_create(vcpu);
6749 if (r < 0)
6750 goto fail_free_pio_data;
6751
6752 if (irqchip_in_kernel(kvm)) {
6753 r = kvm_create_lapic(vcpu);
6754 if (r < 0)
6755 goto fail_mmu_destroy;
6756 } else
6757 static_key_slow_inc(&kvm_no_apic_vcpu);
6758
6759 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6760 GFP_KERNEL);
6761 if (!vcpu->arch.mce_banks) {
6762 r = -ENOMEM;
6763 goto fail_free_lapic;
6764 }
6765 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6766
6767 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6768 r = -ENOMEM;
6769 goto fail_free_mce_banks;
6770 }
6771
6772 r = fx_init(vcpu);
6773 if (r)
6774 goto fail_free_wbinvd_dirty_mask;
6775
6776 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6777 vcpu->arch.pv_time_enabled = false;
6778 kvm_async_pf_hash_reset(vcpu);
6779 kvm_pmu_init(vcpu);
6780
6781 return 0;
6782 fail_free_wbinvd_dirty_mask:
6783 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6784 fail_free_mce_banks:
6785 kfree(vcpu->arch.mce_banks);
6786 fail_free_lapic:
6787 kvm_free_lapic(vcpu);
6788 fail_mmu_destroy:
6789 kvm_mmu_destroy(vcpu);
6790 fail_free_pio_data:
6791 free_page((unsigned long)vcpu->arch.pio_data);
6792 fail:
6793 return r;
6794 }
6795
6796 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6797 {
6798 int idx;
6799
6800 kvm_pmu_destroy(vcpu);
6801 kfree(vcpu->arch.mce_banks);
6802 kvm_free_lapic(vcpu);
6803 idx = srcu_read_lock(&vcpu->kvm->srcu);
6804 kvm_mmu_destroy(vcpu);
6805 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6806 free_page((unsigned long)vcpu->arch.pio_data);
6807 if (!irqchip_in_kernel(vcpu->kvm))
6808 static_key_slow_dec(&kvm_no_apic_vcpu);
6809 }
6810
6811 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6812 {
6813 if (type)
6814 return -EINVAL;
6815
6816 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6817 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6818
6819 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6820 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6821 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6822 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6823 &kvm->arch.irq_sources_bitmap);
6824
6825 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6826 mutex_init(&kvm->arch.apic_map_lock);
6827 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6828
6829 pvclock_update_vm_gtod_copy(kvm);
6830
6831 return 0;
6832 }
6833
6834 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6835 {
6836 int r;
6837 r = vcpu_load(vcpu);
6838 BUG_ON(r);
6839 kvm_mmu_unload(vcpu);
6840 vcpu_put(vcpu);
6841 }
6842
6843 static void kvm_free_vcpus(struct kvm *kvm)
6844 {
6845 unsigned int i;
6846 struct kvm_vcpu *vcpu;
6847
6848 /*
6849 * Unpin any mmu pages first.
6850 */
6851 kvm_for_each_vcpu(i, vcpu, kvm) {
6852 kvm_clear_async_pf_completion_queue(vcpu);
6853 kvm_unload_vcpu_mmu(vcpu);
6854 }
6855 kvm_for_each_vcpu(i, vcpu, kvm)
6856 kvm_arch_vcpu_free(vcpu);
6857
6858 mutex_lock(&kvm->lock);
6859 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6860 kvm->vcpus[i] = NULL;
6861
6862 atomic_set(&kvm->online_vcpus, 0);
6863 mutex_unlock(&kvm->lock);
6864 }
6865
6866 void kvm_arch_sync_events(struct kvm *kvm)
6867 {
6868 kvm_free_all_assigned_devices(kvm);
6869 kvm_free_pit(kvm);
6870 }
6871
6872 void kvm_arch_destroy_vm(struct kvm *kvm)
6873 {
6874 if (current->mm == kvm->mm) {
6875 /*
6876 * Free memory regions allocated on behalf of userspace,
6877 * unless the the memory map has changed due to process exit
6878 * or fd copying.
6879 */
6880 struct kvm_userspace_memory_region mem;
6881 memset(&mem, 0, sizeof(mem));
6882 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
6883 kvm_set_memory_region(kvm, &mem);
6884
6885 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
6886 kvm_set_memory_region(kvm, &mem);
6887
6888 mem.slot = TSS_PRIVATE_MEMSLOT;
6889 kvm_set_memory_region(kvm, &mem);
6890 }
6891 kvm_iommu_unmap_guest(kvm);
6892 kfree(kvm->arch.vpic);
6893 kfree(kvm->arch.vioapic);
6894 kvm_free_vcpus(kvm);
6895 if (kvm->arch.apic_access_page)
6896 put_page(kvm->arch.apic_access_page);
6897 if (kvm->arch.ept_identity_pagetable)
6898 put_page(kvm->arch.ept_identity_pagetable);
6899 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
6900 }
6901
6902 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6903 struct kvm_memory_slot *dont)
6904 {
6905 int i;
6906
6907 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6908 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6909 kvm_kvfree(free->arch.rmap[i]);
6910 free->arch.rmap[i] = NULL;
6911 }
6912 if (i == 0)
6913 continue;
6914
6915 if (!dont || free->arch.lpage_info[i - 1] !=
6916 dont->arch.lpage_info[i - 1]) {
6917 kvm_kvfree(free->arch.lpage_info[i - 1]);
6918 free->arch.lpage_info[i - 1] = NULL;
6919 }
6920 }
6921 }
6922
6923 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6924 {
6925 int i;
6926
6927 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6928 unsigned long ugfn;
6929 int lpages;
6930 int level = i + 1;
6931
6932 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6933 slot->base_gfn, level) + 1;
6934
6935 slot->arch.rmap[i] =
6936 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6937 if (!slot->arch.rmap[i])
6938 goto out_free;
6939 if (i == 0)
6940 continue;
6941
6942 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6943 sizeof(*slot->arch.lpage_info[i - 1]));
6944 if (!slot->arch.lpage_info[i - 1])
6945 goto out_free;
6946
6947 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6948 slot->arch.lpage_info[i - 1][0].write_count = 1;
6949 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6950 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
6951 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6952 /*
6953 * If the gfn and userspace address are not aligned wrt each
6954 * other, or if explicitly asked to, disable large page
6955 * support for this slot
6956 */
6957 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6958 !kvm_largepages_enabled()) {
6959 unsigned long j;
6960
6961 for (j = 0; j < lpages; ++j)
6962 slot->arch.lpage_info[i - 1][j].write_count = 1;
6963 }
6964 }
6965
6966 return 0;
6967
6968 out_free:
6969 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6970 kvm_kvfree(slot->arch.rmap[i]);
6971 slot->arch.rmap[i] = NULL;
6972 if (i == 0)
6973 continue;
6974
6975 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6976 slot->arch.lpage_info[i - 1] = NULL;
6977 }
6978 return -ENOMEM;
6979 }
6980
6981 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6982 struct kvm_memory_slot *memslot,
6983 struct kvm_userspace_memory_region *mem,
6984 enum kvm_mr_change change)
6985 {
6986 /*
6987 * Only private memory slots need to be mapped here since
6988 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
6989 */
6990 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
6991 unsigned long userspace_addr;
6992
6993 /*
6994 * MAP_SHARED to prevent internal slot pages from being moved
6995 * by fork()/COW.
6996 */
6997 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
6998 PROT_READ | PROT_WRITE,
6999 MAP_SHARED | MAP_ANONYMOUS, 0);
7000
7001 if (IS_ERR((void *)userspace_addr))
7002 return PTR_ERR((void *)userspace_addr);
7003
7004 memslot->userspace_addr = userspace_addr;
7005 }
7006
7007 return 0;
7008 }
7009
7010 void kvm_arch_commit_memory_region(struct kvm *kvm,
7011 struct kvm_userspace_memory_region *mem,
7012 const struct kvm_memory_slot *old,
7013 enum kvm_mr_change change)
7014 {
7015
7016 int nr_mmu_pages = 0;
7017
7018 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7019 int ret;
7020
7021 ret = vm_munmap(old->userspace_addr,
7022 old->npages * PAGE_SIZE);
7023 if (ret < 0)
7024 printk(KERN_WARNING
7025 "kvm_vm_ioctl_set_memory_region: "
7026 "failed to munmap memory\n");
7027 }
7028
7029 if (!kvm->arch.n_requested_mmu_pages)
7030 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7031
7032 if (nr_mmu_pages)
7033 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7034 /*
7035 * Write protect all pages for dirty logging.
7036 * Existing largepage mappings are destroyed here and new ones will
7037 * not be created until the end of the logging.
7038 */
7039 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7040 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7041 /*
7042 * If memory slot is created, or moved, we need to clear all
7043 * mmio sptes.
7044 */
7045 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
7046 kvm_mmu_zap_mmio_sptes(kvm);
7047 kvm_reload_remote_mmus(kvm);
7048 }
7049 }
7050
7051 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7052 {
7053 kvm_mmu_zap_all(kvm);
7054 kvm_reload_remote_mmus(kvm);
7055 }
7056
7057 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7058 struct kvm_memory_slot *slot)
7059 {
7060 kvm_arch_flush_shadow_all(kvm);
7061 }
7062
7063 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7064 {
7065 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7066 !vcpu->arch.apf.halted)
7067 || !list_empty_careful(&vcpu->async_pf.done)
7068 || kvm_apic_has_events(vcpu)
7069 || atomic_read(&vcpu->arch.nmi_queued) ||
7070 (kvm_arch_interrupt_allowed(vcpu) &&
7071 kvm_cpu_has_interrupt(vcpu));
7072 }
7073
7074 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7075 {
7076 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7077 }
7078
7079 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7080 {
7081 return kvm_x86_ops->interrupt_allowed(vcpu);
7082 }
7083
7084 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7085 {
7086 unsigned long current_rip = kvm_rip_read(vcpu) +
7087 get_segment_base(vcpu, VCPU_SREG_CS);
7088
7089 return current_rip == linear_rip;
7090 }
7091 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7092
7093 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7094 {
7095 unsigned long rflags;
7096
7097 rflags = kvm_x86_ops->get_rflags(vcpu);
7098 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7099 rflags &= ~X86_EFLAGS_TF;
7100 return rflags;
7101 }
7102 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7103
7104 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7105 {
7106 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7107 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7108 rflags |= X86_EFLAGS_TF;
7109 kvm_x86_ops->set_rflags(vcpu, rflags);
7110 kvm_make_request(KVM_REQ_EVENT, vcpu);
7111 }
7112 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7113
7114 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7115 {
7116 int r;
7117
7118 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7119 is_error_page(work->page))
7120 return;
7121
7122 r = kvm_mmu_reload(vcpu);
7123 if (unlikely(r))
7124 return;
7125
7126 if (!vcpu->arch.mmu.direct_map &&
7127 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7128 return;
7129
7130 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7131 }
7132
7133 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7134 {
7135 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7136 }
7137
7138 static inline u32 kvm_async_pf_next_probe(u32 key)
7139 {
7140 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7141 }
7142
7143 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7144 {
7145 u32 key = kvm_async_pf_hash_fn(gfn);
7146
7147 while (vcpu->arch.apf.gfns[key] != ~0)
7148 key = kvm_async_pf_next_probe(key);
7149
7150 vcpu->arch.apf.gfns[key] = gfn;
7151 }
7152
7153 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7154 {
7155 int i;
7156 u32 key = kvm_async_pf_hash_fn(gfn);
7157
7158 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7159 (vcpu->arch.apf.gfns[key] != gfn &&
7160 vcpu->arch.apf.gfns[key] != ~0); i++)
7161 key = kvm_async_pf_next_probe(key);
7162
7163 return key;
7164 }
7165
7166 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7167 {
7168 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7169 }
7170
7171 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7172 {
7173 u32 i, j, k;
7174
7175 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7176 while (true) {
7177 vcpu->arch.apf.gfns[i] = ~0;
7178 do {
7179 j = kvm_async_pf_next_probe(j);
7180 if (vcpu->arch.apf.gfns[j] == ~0)
7181 return;
7182 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7183 /*
7184 * k lies cyclically in ]i,j]
7185 * | i.k.j |
7186 * |....j i.k.| or |.k..j i...|
7187 */
7188 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7189 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7190 i = j;
7191 }
7192 }
7193
7194 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7195 {
7196
7197 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7198 sizeof(val));
7199 }
7200
7201 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7202 struct kvm_async_pf *work)
7203 {
7204 struct x86_exception fault;
7205
7206 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7207 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7208
7209 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7210 (vcpu->arch.apf.send_user_only &&
7211 kvm_x86_ops->get_cpl(vcpu) == 0))
7212 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7213 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7214 fault.vector = PF_VECTOR;
7215 fault.error_code_valid = true;
7216 fault.error_code = 0;
7217 fault.nested_page_fault = false;
7218 fault.address = work->arch.token;
7219 kvm_inject_page_fault(vcpu, &fault);
7220 }
7221 }
7222
7223 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7224 struct kvm_async_pf *work)
7225 {
7226 struct x86_exception fault;
7227
7228 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7229 if (is_error_page(work->page))
7230 work->arch.token = ~0; /* broadcast wakeup */
7231 else
7232 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7233
7234 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7235 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7236 fault.vector = PF_VECTOR;
7237 fault.error_code_valid = true;
7238 fault.error_code = 0;
7239 fault.nested_page_fault = false;
7240 fault.address = work->arch.token;
7241 kvm_inject_page_fault(vcpu, &fault);
7242 }
7243 vcpu->arch.apf.halted = false;
7244 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7245 }
7246
7247 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7248 {
7249 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7250 return true;
7251 else
7252 return !kvm_event_needs_reinjection(vcpu) &&
7253 kvm_x86_ops->interrupt_allowed(vcpu);
7254 }
7255
7256 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7257 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7258 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7259 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7260 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7261 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7262 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7263 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7264 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7265 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7266 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7267 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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