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KVM: x86: Add code to track call origin for msr assignment
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 bool kvm_has_tsc_control;
98 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99 u32 kvm_max_guest_tsc_khz;
100 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
102 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103 static u32 tsc_tolerance_ppm = 250;
104 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
106 #define KVM_NR_SHARED_MSRS 16
107
108 struct kvm_shared_msrs_global {
109 int nr;
110 u32 msrs[KVM_NR_SHARED_MSRS];
111 };
112
113 struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
120 };
121
122 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
124
125 struct kvm_stats_debugfs_item debugfs_entries[] = {
126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
138 { "hypercalls", VCPU_STAT(hypercalls) },
139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
146 { "irq_injections", VCPU_STAT(irq_injections) },
147 { "nmi_injections", VCPU_STAT(nmi_injections) },
148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
155 { "mmu_unsync", VM_STAT(mmu_unsync) },
156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
157 { "largepages", VM_STAT(lpages) },
158 { NULL }
159 };
160
161 u64 __read_mostly host_xcr0;
162
163 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
164
165 static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
166
167 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
168 {
169 int i;
170 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
171 vcpu->arch.apf.gfns[i] = ~0;
172 }
173
174 static void kvm_on_user_return(struct user_return_notifier *urn)
175 {
176 unsigned slot;
177 struct kvm_shared_msrs *locals
178 = container_of(urn, struct kvm_shared_msrs, urn);
179 struct kvm_shared_msr_values *values;
180
181 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
182 values = &locals->values[slot];
183 if (values->host != values->curr) {
184 wrmsrl(shared_msrs_global.msrs[slot], values->host);
185 values->curr = values->host;
186 }
187 }
188 locals->registered = false;
189 user_return_notifier_unregister(urn);
190 }
191
192 static void shared_msr_update(unsigned slot, u32 msr)
193 {
194 struct kvm_shared_msrs *smsr;
195 u64 value;
196
197 smsr = &__get_cpu_var(shared_msrs);
198 /* only read, and nobody should modify it at this time,
199 * so don't need lock */
200 if (slot >= shared_msrs_global.nr) {
201 printk(KERN_ERR "kvm: invalid MSR slot!");
202 return;
203 }
204 rdmsrl_safe(msr, &value);
205 smsr->values[slot].host = value;
206 smsr->values[slot].curr = value;
207 }
208
209 void kvm_define_shared_msr(unsigned slot, u32 msr)
210 {
211 if (slot >= shared_msrs_global.nr)
212 shared_msrs_global.nr = slot + 1;
213 shared_msrs_global.msrs[slot] = msr;
214 /* we need ensured the shared_msr_global have been updated */
215 smp_wmb();
216 }
217 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
218
219 static void kvm_shared_msr_cpu_online(void)
220 {
221 unsigned i;
222
223 for (i = 0; i < shared_msrs_global.nr; ++i)
224 shared_msr_update(i, shared_msrs_global.msrs[i]);
225 }
226
227 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
228 {
229 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
230
231 if (((value ^ smsr->values[slot].curr) & mask) == 0)
232 return;
233 smsr->values[slot].curr = value;
234 wrmsrl(shared_msrs_global.msrs[slot], value);
235 if (!smsr->registered) {
236 smsr->urn.on_user_return = kvm_on_user_return;
237 user_return_notifier_register(&smsr->urn);
238 smsr->registered = true;
239 }
240 }
241 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
242
243 static void drop_user_return_notifiers(void *ignore)
244 {
245 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249 }
250
251 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252 {
253 return vcpu->arch.apic_base;
254 }
255 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258 {
259 /* TODO: reserve bits check */
260 kvm_lapic_set_base(vcpu, data);
261 }
262 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
264 #define EXCPT_BENIGN 0
265 #define EXCPT_CONTRIBUTORY 1
266 #define EXCPT_PF 2
267
268 static int exception_class(int vector)
269 {
270 switch (vector) {
271 case PF_VECTOR:
272 return EXCPT_PF;
273 case DE_VECTOR:
274 case TS_VECTOR:
275 case NP_VECTOR:
276 case SS_VECTOR:
277 case GP_VECTOR:
278 return EXCPT_CONTRIBUTORY;
279 default:
280 break;
281 }
282 return EXCPT_BENIGN;
283 }
284
285 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
286 unsigned nr, bool has_error, u32 error_code,
287 bool reinject)
288 {
289 u32 prev_nr;
290 int class1, class2;
291
292 kvm_make_request(KVM_REQ_EVENT, vcpu);
293
294 if (!vcpu->arch.exception.pending) {
295 queue:
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = has_error;
298 vcpu->arch.exception.nr = nr;
299 vcpu->arch.exception.error_code = error_code;
300 vcpu->arch.exception.reinject = reinject;
301 return;
302 }
303
304 /* to check exception */
305 prev_nr = vcpu->arch.exception.nr;
306 if (prev_nr == DF_VECTOR) {
307 /* triple fault -> shutdown */
308 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
309 return;
310 }
311 class1 = exception_class(prev_nr);
312 class2 = exception_class(nr);
313 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
314 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
315 /* generate double fault per SDM Table 5-5 */
316 vcpu->arch.exception.pending = true;
317 vcpu->arch.exception.has_error_code = true;
318 vcpu->arch.exception.nr = DF_VECTOR;
319 vcpu->arch.exception.error_code = 0;
320 } else
321 /* replace previous exception with a new one in a hope
322 that instruction re-execution will regenerate lost
323 exception */
324 goto queue;
325 }
326
327 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
328 {
329 kvm_multiple_exception(vcpu, nr, false, 0, false);
330 }
331 EXPORT_SYMBOL_GPL(kvm_queue_exception);
332
333 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
334 {
335 kvm_multiple_exception(vcpu, nr, false, 0, true);
336 }
337 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
338
339 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
340 {
341 if (err)
342 kvm_inject_gp(vcpu, 0);
343 else
344 kvm_x86_ops->skip_emulated_instruction(vcpu);
345 }
346 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
347
348 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
349 {
350 ++vcpu->stat.pf_guest;
351 vcpu->arch.cr2 = fault->address;
352 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
353 }
354 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
355
356 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
357 {
358 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
359 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
360 else
361 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
362 }
363
364 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
365 {
366 atomic_inc(&vcpu->arch.nmi_queued);
367 kvm_make_request(KVM_REQ_NMI, vcpu);
368 }
369 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
370
371 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
372 {
373 kvm_multiple_exception(vcpu, nr, true, error_code, false);
374 }
375 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
376
377 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
378 {
379 kvm_multiple_exception(vcpu, nr, true, error_code, true);
380 }
381 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
382
383 /*
384 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
385 * a #GP and return false.
386 */
387 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
388 {
389 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
390 return true;
391 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
392 return false;
393 }
394 EXPORT_SYMBOL_GPL(kvm_require_cpl);
395
396 /*
397 * This function will be used to read from the physical memory of the currently
398 * running guest. The difference to kvm_read_guest_page is that this function
399 * can read from guest physical or from the guest's guest physical memory.
400 */
401 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
402 gfn_t ngfn, void *data, int offset, int len,
403 u32 access)
404 {
405 gfn_t real_gfn;
406 gpa_t ngpa;
407
408 ngpa = gfn_to_gpa(ngfn);
409 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
410 if (real_gfn == UNMAPPED_GVA)
411 return -EFAULT;
412
413 real_gfn = gpa_to_gfn(real_gfn);
414
415 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
416 }
417 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
418
419 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
420 void *data, int offset, int len, u32 access)
421 {
422 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
423 data, offset, len, access);
424 }
425
426 /*
427 * Load the pae pdptrs. Return true is they are all valid.
428 */
429 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
430 {
431 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
432 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
433 int i;
434 int ret;
435 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
436
437 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
438 offset * sizeof(u64), sizeof(pdpte),
439 PFERR_USER_MASK|PFERR_WRITE_MASK);
440 if (ret < 0) {
441 ret = 0;
442 goto out;
443 }
444 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
445 if (is_present_gpte(pdpte[i]) &&
446 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
447 ret = 0;
448 goto out;
449 }
450 }
451 ret = 1;
452
453 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
454 __set_bit(VCPU_EXREG_PDPTR,
455 (unsigned long *)&vcpu->arch.regs_avail);
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_dirty);
458 out:
459
460 return ret;
461 }
462 EXPORT_SYMBOL_GPL(load_pdptrs);
463
464 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
465 {
466 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
467 bool changed = true;
468 int offset;
469 gfn_t gfn;
470 int r;
471
472 if (is_long_mode(vcpu) || !is_pae(vcpu))
473 return false;
474
475 if (!test_bit(VCPU_EXREG_PDPTR,
476 (unsigned long *)&vcpu->arch.regs_avail))
477 return true;
478
479 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
480 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
481 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
482 PFERR_USER_MASK | PFERR_WRITE_MASK);
483 if (r < 0)
484 goto out;
485 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
486 out:
487
488 return changed;
489 }
490
491 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
492 {
493 unsigned long old_cr0 = kvm_read_cr0(vcpu);
494 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
495 X86_CR0_CD | X86_CR0_NW;
496
497 cr0 |= X86_CR0_ET;
498
499 #ifdef CONFIG_X86_64
500 if (cr0 & 0xffffffff00000000UL)
501 return 1;
502 #endif
503
504 cr0 &= ~CR0_RESERVED_BITS;
505
506 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
507 return 1;
508
509 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
510 return 1;
511
512 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
513 #ifdef CONFIG_X86_64
514 if ((vcpu->arch.efer & EFER_LME)) {
515 int cs_db, cs_l;
516
517 if (!is_pae(vcpu))
518 return 1;
519 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
520 if (cs_l)
521 return 1;
522 } else
523 #endif
524 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
525 kvm_read_cr3(vcpu)))
526 return 1;
527 }
528
529 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
530 return 1;
531
532 kvm_x86_ops->set_cr0(vcpu, cr0);
533
534 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
535 kvm_clear_async_pf_completion_queue(vcpu);
536 kvm_async_pf_hash_reset(vcpu);
537 }
538
539 if ((cr0 ^ old_cr0) & update_bits)
540 kvm_mmu_reset_context(vcpu);
541 return 0;
542 }
543 EXPORT_SYMBOL_GPL(kvm_set_cr0);
544
545 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
546 {
547 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
548 }
549 EXPORT_SYMBOL_GPL(kvm_lmsw);
550
551 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
552 {
553 u64 xcr0;
554
555 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
556 if (index != XCR_XFEATURE_ENABLED_MASK)
557 return 1;
558 xcr0 = xcr;
559 if (kvm_x86_ops->get_cpl(vcpu) != 0)
560 return 1;
561 if (!(xcr0 & XSTATE_FP))
562 return 1;
563 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
564 return 1;
565 if (xcr0 & ~host_xcr0)
566 return 1;
567 vcpu->arch.xcr0 = xcr0;
568 vcpu->guest_xcr0_loaded = 0;
569 return 0;
570 }
571
572 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
573 {
574 if (__kvm_set_xcr(vcpu, index, xcr)) {
575 kvm_inject_gp(vcpu, 0);
576 return 1;
577 }
578 return 0;
579 }
580 EXPORT_SYMBOL_GPL(kvm_set_xcr);
581
582 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
583 {
584 unsigned long old_cr4 = kvm_read_cr4(vcpu);
585 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
586 X86_CR4_PAE | X86_CR4_SMEP;
587 if (cr4 & CR4_RESERVED_BITS)
588 return 1;
589
590 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
591 return 1;
592
593 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
594 return 1;
595
596 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
597 return 1;
598
599 if (is_long_mode(vcpu)) {
600 if (!(cr4 & X86_CR4_PAE))
601 return 1;
602 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
603 && ((cr4 ^ old_cr4) & pdptr_bits)
604 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
605 kvm_read_cr3(vcpu)))
606 return 1;
607
608 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
609 if (!guest_cpuid_has_pcid(vcpu))
610 return 1;
611
612 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
613 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
614 return 1;
615 }
616
617 if (kvm_x86_ops->set_cr4(vcpu, cr4))
618 return 1;
619
620 if (((cr4 ^ old_cr4) & pdptr_bits) ||
621 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
622 kvm_mmu_reset_context(vcpu);
623
624 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
625 kvm_update_cpuid(vcpu);
626
627 return 0;
628 }
629 EXPORT_SYMBOL_GPL(kvm_set_cr4);
630
631 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
632 {
633 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
634 kvm_mmu_sync_roots(vcpu);
635 kvm_mmu_flush_tlb(vcpu);
636 return 0;
637 }
638
639 if (is_long_mode(vcpu)) {
640 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
641 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
642 return 1;
643 } else
644 if (cr3 & CR3_L_MODE_RESERVED_BITS)
645 return 1;
646 } else {
647 if (is_pae(vcpu)) {
648 if (cr3 & CR3_PAE_RESERVED_BITS)
649 return 1;
650 if (is_paging(vcpu) &&
651 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
652 return 1;
653 }
654 /*
655 * We don't check reserved bits in nonpae mode, because
656 * this isn't enforced, and VMware depends on this.
657 */
658 }
659
660 /*
661 * Does the new cr3 value map to physical memory? (Note, we
662 * catch an invalid cr3 even in real-mode, because it would
663 * cause trouble later on when we turn on paging anyway.)
664 *
665 * A real CPU would silently accept an invalid cr3 and would
666 * attempt to use it - with largely undefined (and often hard
667 * to debug) behavior on the guest side.
668 */
669 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
670 return 1;
671 vcpu->arch.cr3 = cr3;
672 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
673 vcpu->arch.mmu.new_cr3(vcpu);
674 return 0;
675 }
676 EXPORT_SYMBOL_GPL(kvm_set_cr3);
677
678 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
679 {
680 if (cr8 & CR8_RESERVED_BITS)
681 return 1;
682 if (irqchip_in_kernel(vcpu->kvm))
683 kvm_lapic_set_tpr(vcpu, cr8);
684 else
685 vcpu->arch.cr8 = cr8;
686 return 0;
687 }
688 EXPORT_SYMBOL_GPL(kvm_set_cr8);
689
690 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
691 {
692 if (irqchip_in_kernel(vcpu->kvm))
693 return kvm_lapic_get_cr8(vcpu);
694 else
695 return vcpu->arch.cr8;
696 }
697 EXPORT_SYMBOL_GPL(kvm_get_cr8);
698
699 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
700 {
701 unsigned long dr7;
702
703 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
704 dr7 = vcpu->arch.guest_debug_dr7;
705 else
706 dr7 = vcpu->arch.dr7;
707 kvm_x86_ops->set_dr7(vcpu, dr7);
708 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
709 }
710
711 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
712 {
713 switch (dr) {
714 case 0 ... 3:
715 vcpu->arch.db[dr] = val;
716 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
717 vcpu->arch.eff_db[dr] = val;
718 break;
719 case 4:
720 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
721 return 1; /* #UD */
722 /* fall through */
723 case 6:
724 if (val & 0xffffffff00000000ULL)
725 return -1; /* #GP */
726 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
727 break;
728 case 5:
729 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
730 return 1; /* #UD */
731 /* fall through */
732 default: /* 7 */
733 if (val & 0xffffffff00000000ULL)
734 return -1; /* #GP */
735 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
736 kvm_update_dr7(vcpu);
737 break;
738 }
739
740 return 0;
741 }
742
743 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
744 {
745 int res;
746
747 res = __kvm_set_dr(vcpu, dr, val);
748 if (res > 0)
749 kvm_queue_exception(vcpu, UD_VECTOR);
750 else if (res < 0)
751 kvm_inject_gp(vcpu, 0);
752
753 return res;
754 }
755 EXPORT_SYMBOL_GPL(kvm_set_dr);
756
757 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
758 {
759 switch (dr) {
760 case 0 ... 3:
761 *val = vcpu->arch.db[dr];
762 break;
763 case 4:
764 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
765 return 1;
766 /* fall through */
767 case 6:
768 *val = vcpu->arch.dr6;
769 break;
770 case 5:
771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
772 return 1;
773 /* fall through */
774 default: /* 7 */
775 *val = vcpu->arch.dr7;
776 break;
777 }
778
779 return 0;
780 }
781
782 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
783 {
784 if (_kvm_get_dr(vcpu, dr, val)) {
785 kvm_queue_exception(vcpu, UD_VECTOR);
786 return 1;
787 }
788 return 0;
789 }
790 EXPORT_SYMBOL_GPL(kvm_get_dr);
791
792 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
793 {
794 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
795 u64 data;
796 int err;
797
798 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
799 if (err)
800 return err;
801 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
802 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
803 return err;
804 }
805 EXPORT_SYMBOL_GPL(kvm_rdpmc);
806
807 /*
808 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
809 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
810 *
811 * This list is modified at module load time to reflect the
812 * capabilities of the host cpu. This capabilities test skips MSRs that are
813 * kvm-specific. Those are put in the beginning of the list.
814 */
815
816 #define KVM_SAVE_MSRS_BEGIN 10
817 static u32 msrs_to_save[] = {
818 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
819 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
820 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
821 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
822 MSR_KVM_PV_EOI_EN,
823 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
824 MSR_STAR,
825 #ifdef CONFIG_X86_64
826 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
827 #endif
828 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
829 };
830
831 static unsigned num_msrs_to_save;
832
833 static const u32 emulated_msrs[] = {
834 MSR_IA32_TSCDEADLINE,
835 MSR_IA32_MISC_ENABLE,
836 MSR_IA32_MCG_STATUS,
837 MSR_IA32_MCG_CTL,
838 };
839
840 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
841 {
842 u64 old_efer = vcpu->arch.efer;
843
844 if (efer & efer_reserved_bits)
845 return 1;
846
847 if (is_paging(vcpu)
848 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
849 return 1;
850
851 if (efer & EFER_FFXSR) {
852 struct kvm_cpuid_entry2 *feat;
853
854 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
855 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
856 return 1;
857 }
858
859 if (efer & EFER_SVME) {
860 struct kvm_cpuid_entry2 *feat;
861
862 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
863 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
864 return 1;
865 }
866
867 efer &= ~EFER_LMA;
868 efer |= vcpu->arch.efer & EFER_LMA;
869
870 kvm_x86_ops->set_efer(vcpu, efer);
871
872 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
873
874 /* Update reserved bits */
875 if ((efer ^ old_efer) & EFER_NX)
876 kvm_mmu_reset_context(vcpu);
877
878 return 0;
879 }
880
881 void kvm_enable_efer_bits(u64 mask)
882 {
883 efer_reserved_bits &= ~mask;
884 }
885 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
886
887
888 /*
889 * Writes msr value into into the appropriate "register".
890 * Returns 0 on success, non-0 otherwise.
891 * Assumes vcpu_load() was already called.
892 */
893 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
894 {
895 return kvm_x86_ops->set_msr(vcpu, msr);
896 }
897
898 /*
899 * Adapt set_msr() to msr_io()'s calling convention
900 */
901 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
902 {
903 struct msr_data msr;
904
905 msr.data = *data;
906 msr.index = index;
907 msr.host_initiated = true;
908 return kvm_set_msr(vcpu, &msr);
909 }
910
911 #ifdef CONFIG_X86_64
912 struct pvclock_gtod_data {
913 seqcount_t seq;
914
915 struct { /* extract of a clocksource struct */
916 int vclock_mode;
917 cycle_t cycle_last;
918 cycle_t mask;
919 u32 mult;
920 u32 shift;
921 } clock;
922
923 /* open coded 'struct timespec' */
924 u64 monotonic_time_snsec;
925 time_t monotonic_time_sec;
926 };
927
928 static struct pvclock_gtod_data pvclock_gtod_data;
929
930 static void update_pvclock_gtod(struct timekeeper *tk)
931 {
932 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
933
934 write_seqcount_begin(&vdata->seq);
935
936 /* copy pvclock gtod data */
937 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
938 vdata->clock.cycle_last = tk->clock->cycle_last;
939 vdata->clock.mask = tk->clock->mask;
940 vdata->clock.mult = tk->mult;
941 vdata->clock.shift = tk->shift;
942
943 vdata->monotonic_time_sec = tk->xtime_sec
944 + tk->wall_to_monotonic.tv_sec;
945 vdata->monotonic_time_snsec = tk->xtime_nsec
946 + (tk->wall_to_monotonic.tv_nsec
947 << tk->shift);
948 while (vdata->monotonic_time_snsec >=
949 (((u64)NSEC_PER_SEC) << tk->shift)) {
950 vdata->monotonic_time_snsec -=
951 ((u64)NSEC_PER_SEC) << tk->shift;
952 vdata->monotonic_time_sec++;
953 }
954
955 write_seqcount_end(&vdata->seq);
956 }
957 #endif
958
959
960 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
961 {
962 int version;
963 int r;
964 struct pvclock_wall_clock wc;
965 struct timespec boot;
966
967 if (!wall_clock)
968 return;
969
970 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
971 if (r)
972 return;
973
974 if (version & 1)
975 ++version; /* first time write, random junk */
976
977 ++version;
978
979 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
980
981 /*
982 * The guest calculates current wall clock time by adding
983 * system time (updated by kvm_guest_time_update below) to the
984 * wall clock specified here. guest system time equals host
985 * system time for us, thus we must fill in host boot time here.
986 */
987 getboottime(&boot);
988
989 if (kvm->arch.kvmclock_offset) {
990 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
991 boot = timespec_sub(boot, ts);
992 }
993 wc.sec = boot.tv_sec;
994 wc.nsec = boot.tv_nsec;
995 wc.version = version;
996
997 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
998
999 version++;
1000 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1001 }
1002
1003 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1004 {
1005 uint32_t quotient, remainder;
1006
1007 /* Don't try to replace with do_div(), this one calculates
1008 * "(dividend << 32) / divisor" */
1009 __asm__ ( "divl %4"
1010 : "=a" (quotient), "=d" (remainder)
1011 : "0" (0), "1" (dividend), "r" (divisor) );
1012 return quotient;
1013 }
1014
1015 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1016 s8 *pshift, u32 *pmultiplier)
1017 {
1018 uint64_t scaled64;
1019 int32_t shift = 0;
1020 uint64_t tps64;
1021 uint32_t tps32;
1022
1023 tps64 = base_khz * 1000LL;
1024 scaled64 = scaled_khz * 1000LL;
1025 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1026 tps64 >>= 1;
1027 shift--;
1028 }
1029
1030 tps32 = (uint32_t)tps64;
1031 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1032 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1033 scaled64 >>= 1;
1034 else
1035 tps32 <<= 1;
1036 shift++;
1037 }
1038
1039 *pshift = shift;
1040 *pmultiplier = div_frac(scaled64, tps32);
1041
1042 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1043 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1044 }
1045
1046 static inline u64 get_kernel_ns(void)
1047 {
1048 struct timespec ts;
1049
1050 WARN_ON(preemptible());
1051 ktime_get_ts(&ts);
1052 monotonic_to_bootbased(&ts);
1053 return timespec_to_ns(&ts);
1054 }
1055
1056 #ifdef CONFIG_X86_64
1057 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1058 #endif
1059
1060 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1061 unsigned long max_tsc_khz;
1062
1063 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1064 {
1065 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1066 vcpu->arch.virtual_tsc_shift);
1067 }
1068
1069 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1070 {
1071 u64 v = (u64)khz * (1000000 + ppm);
1072 do_div(v, 1000000);
1073 return v;
1074 }
1075
1076 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1077 {
1078 u32 thresh_lo, thresh_hi;
1079 int use_scaling = 0;
1080
1081 /* Compute a scale to convert nanoseconds in TSC cycles */
1082 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1083 &vcpu->arch.virtual_tsc_shift,
1084 &vcpu->arch.virtual_tsc_mult);
1085 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1086
1087 /*
1088 * Compute the variation in TSC rate which is acceptable
1089 * within the range of tolerance and decide if the
1090 * rate being applied is within that bounds of the hardware
1091 * rate. If so, no scaling or compensation need be done.
1092 */
1093 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1094 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1095 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1096 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1097 use_scaling = 1;
1098 }
1099 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1100 }
1101
1102 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1103 {
1104 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1105 vcpu->arch.virtual_tsc_mult,
1106 vcpu->arch.virtual_tsc_shift);
1107 tsc += vcpu->arch.this_tsc_write;
1108 return tsc;
1109 }
1110
1111 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1112 {
1113 #ifdef CONFIG_X86_64
1114 bool vcpus_matched;
1115 bool do_request = false;
1116 struct kvm_arch *ka = &vcpu->kvm->arch;
1117 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1118
1119 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1120 atomic_read(&vcpu->kvm->online_vcpus));
1121
1122 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1123 if (!ka->use_master_clock)
1124 do_request = 1;
1125
1126 if (!vcpus_matched && ka->use_master_clock)
1127 do_request = 1;
1128
1129 if (do_request)
1130 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1131
1132 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1133 atomic_read(&vcpu->kvm->online_vcpus),
1134 ka->use_master_clock, gtod->clock.vclock_mode);
1135 #endif
1136 }
1137
1138 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1139 {
1140 struct kvm *kvm = vcpu->kvm;
1141 u64 offset, ns, elapsed;
1142 unsigned long flags;
1143 s64 usdiff;
1144 bool matched;
1145 u64 data = msr->data;
1146
1147 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1148 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1149 ns = get_kernel_ns();
1150 elapsed = ns - kvm->arch.last_tsc_nsec;
1151
1152 /* n.b - signed multiplication and division required */
1153 usdiff = data - kvm->arch.last_tsc_write;
1154 #ifdef CONFIG_X86_64
1155 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1156 #else
1157 /* do_div() only does unsigned */
1158 asm("idivl %2; xor %%edx, %%edx"
1159 : "=A"(usdiff)
1160 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1161 #endif
1162 do_div(elapsed, 1000);
1163 usdiff -= elapsed;
1164 if (usdiff < 0)
1165 usdiff = -usdiff;
1166
1167 /*
1168 * Special case: TSC write with a small delta (1 second) of virtual
1169 * cycle time against real time is interpreted as an attempt to
1170 * synchronize the CPU.
1171 *
1172 * For a reliable TSC, we can match TSC offsets, and for an unstable
1173 * TSC, we add elapsed time in this computation. We could let the
1174 * compensation code attempt to catch up if we fall behind, but
1175 * it's better to try to match offsets from the beginning.
1176 */
1177 if (usdiff < USEC_PER_SEC &&
1178 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1179 if (!check_tsc_unstable()) {
1180 offset = kvm->arch.cur_tsc_offset;
1181 pr_debug("kvm: matched tsc offset for %llu\n", data);
1182 } else {
1183 u64 delta = nsec_to_cycles(vcpu, elapsed);
1184 data += delta;
1185 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1186 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1187 }
1188 matched = true;
1189 } else {
1190 /*
1191 * We split periods of matched TSC writes into generations.
1192 * For each generation, we track the original measured
1193 * nanosecond time, offset, and write, so if TSCs are in
1194 * sync, we can match exact offset, and if not, we can match
1195 * exact software computation in compute_guest_tsc()
1196 *
1197 * These values are tracked in kvm->arch.cur_xxx variables.
1198 */
1199 kvm->arch.cur_tsc_generation++;
1200 kvm->arch.cur_tsc_nsec = ns;
1201 kvm->arch.cur_tsc_write = data;
1202 kvm->arch.cur_tsc_offset = offset;
1203 matched = false;
1204 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1205 kvm->arch.cur_tsc_generation, data);
1206 }
1207
1208 /*
1209 * We also track th most recent recorded KHZ, write and time to
1210 * allow the matching interval to be extended at each write.
1211 */
1212 kvm->arch.last_tsc_nsec = ns;
1213 kvm->arch.last_tsc_write = data;
1214 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1215
1216 /* Reset of TSC must disable overshoot protection below */
1217 vcpu->arch.hv_clock.tsc_timestamp = 0;
1218 vcpu->arch.last_guest_tsc = data;
1219
1220 /* Keep track of which generation this VCPU has synchronized to */
1221 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1222 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1223 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1224
1225 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1226 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1227
1228 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1229 if (matched)
1230 kvm->arch.nr_vcpus_matched_tsc++;
1231 else
1232 kvm->arch.nr_vcpus_matched_tsc = 0;
1233
1234 kvm_track_tsc_matching(vcpu);
1235 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1236 }
1237
1238 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1239
1240 #ifdef CONFIG_X86_64
1241
1242 static cycle_t read_tsc(void)
1243 {
1244 cycle_t ret;
1245 u64 last;
1246
1247 /*
1248 * Empirically, a fence (of type that depends on the CPU)
1249 * before rdtsc is enough to ensure that rdtsc is ordered
1250 * with respect to loads. The various CPU manuals are unclear
1251 * as to whether rdtsc can be reordered with later loads,
1252 * but no one has ever seen it happen.
1253 */
1254 rdtsc_barrier();
1255 ret = (cycle_t)vget_cycles();
1256
1257 last = pvclock_gtod_data.clock.cycle_last;
1258
1259 if (likely(ret >= last))
1260 return ret;
1261
1262 /*
1263 * GCC likes to generate cmov here, but this branch is extremely
1264 * predictable (it's just a funciton of time and the likely is
1265 * very likely) and there's a data dependence, so force GCC
1266 * to generate a branch instead. I don't barrier() because
1267 * we don't actually need a barrier, and if this function
1268 * ever gets inlined it will generate worse code.
1269 */
1270 asm volatile ("");
1271 return last;
1272 }
1273
1274 static inline u64 vgettsc(cycle_t *cycle_now)
1275 {
1276 long v;
1277 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1278
1279 *cycle_now = read_tsc();
1280
1281 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1282 return v * gtod->clock.mult;
1283 }
1284
1285 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1286 {
1287 unsigned long seq;
1288 u64 ns;
1289 int mode;
1290 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1291
1292 ts->tv_nsec = 0;
1293 do {
1294 seq = read_seqcount_begin(&gtod->seq);
1295 mode = gtod->clock.vclock_mode;
1296 ts->tv_sec = gtod->monotonic_time_sec;
1297 ns = gtod->monotonic_time_snsec;
1298 ns += vgettsc(cycle_now);
1299 ns >>= gtod->clock.shift;
1300 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1301 timespec_add_ns(ts, ns);
1302
1303 return mode;
1304 }
1305
1306 /* returns true if host is using tsc clocksource */
1307 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1308 {
1309 struct timespec ts;
1310
1311 /* checked again under seqlock below */
1312 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1313 return false;
1314
1315 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1316 return false;
1317
1318 monotonic_to_bootbased(&ts);
1319 *kernel_ns = timespec_to_ns(&ts);
1320
1321 return true;
1322 }
1323 #endif
1324
1325 /*
1326 *
1327 * Assuming a stable TSC across physical CPUS, and a stable TSC
1328 * across virtual CPUs, the following condition is possible.
1329 * Each numbered line represents an event visible to both
1330 * CPUs at the next numbered event.
1331 *
1332 * "timespecX" represents host monotonic time. "tscX" represents
1333 * RDTSC value.
1334 *
1335 * VCPU0 on CPU0 | VCPU1 on CPU1
1336 *
1337 * 1. read timespec0,tsc0
1338 * 2. | timespec1 = timespec0 + N
1339 * | tsc1 = tsc0 + M
1340 * 3. transition to guest | transition to guest
1341 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1342 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1343 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1344 *
1345 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1346 *
1347 * - ret0 < ret1
1348 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1349 * ...
1350 * - 0 < N - M => M < N
1351 *
1352 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1353 * always the case (the difference between two distinct xtime instances
1354 * might be smaller then the difference between corresponding TSC reads,
1355 * when updating guest vcpus pvclock areas).
1356 *
1357 * To avoid that problem, do not allow visibility of distinct
1358 * system_timestamp/tsc_timestamp values simultaneously: use a master
1359 * copy of host monotonic time values. Update that master copy
1360 * in lockstep.
1361 *
1362 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1363 *
1364 */
1365
1366 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1367 {
1368 #ifdef CONFIG_X86_64
1369 struct kvm_arch *ka = &kvm->arch;
1370 int vclock_mode;
1371 bool host_tsc_clocksource, vcpus_matched;
1372
1373 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1374 atomic_read(&kvm->online_vcpus));
1375
1376 /*
1377 * If the host uses TSC clock, then passthrough TSC as stable
1378 * to the guest.
1379 */
1380 host_tsc_clocksource = kvm_get_time_and_clockread(
1381 &ka->master_kernel_ns,
1382 &ka->master_cycle_now);
1383
1384 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1385
1386 if (ka->use_master_clock)
1387 atomic_set(&kvm_guest_has_master_clock, 1);
1388
1389 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1390 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1391 vcpus_matched);
1392 #endif
1393 }
1394
1395 static int kvm_guest_time_update(struct kvm_vcpu *v)
1396 {
1397 unsigned long flags, this_tsc_khz;
1398 struct kvm_vcpu_arch *vcpu = &v->arch;
1399 struct kvm_arch *ka = &v->kvm->arch;
1400 void *shared_kaddr;
1401 s64 kernel_ns, max_kernel_ns;
1402 u64 tsc_timestamp, host_tsc;
1403 struct pvclock_vcpu_time_info *guest_hv_clock;
1404 u8 pvclock_flags;
1405 bool use_master_clock;
1406
1407 kernel_ns = 0;
1408 host_tsc = 0;
1409
1410 /* Keep irq disabled to prevent changes to the clock */
1411 local_irq_save(flags);
1412 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1413 if (unlikely(this_tsc_khz == 0)) {
1414 local_irq_restore(flags);
1415 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1416 return 1;
1417 }
1418
1419 /*
1420 * If the host uses TSC clock, then passthrough TSC as stable
1421 * to the guest.
1422 */
1423 spin_lock(&ka->pvclock_gtod_sync_lock);
1424 use_master_clock = ka->use_master_clock;
1425 if (use_master_clock) {
1426 host_tsc = ka->master_cycle_now;
1427 kernel_ns = ka->master_kernel_ns;
1428 }
1429 spin_unlock(&ka->pvclock_gtod_sync_lock);
1430 if (!use_master_clock) {
1431 host_tsc = native_read_tsc();
1432 kernel_ns = get_kernel_ns();
1433 }
1434
1435 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1436
1437 /*
1438 * We may have to catch up the TSC to match elapsed wall clock
1439 * time for two reasons, even if kvmclock is used.
1440 * 1) CPU could have been running below the maximum TSC rate
1441 * 2) Broken TSC compensation resets the base at each VCPU
1442 * entry to avoid unknown leaps of TSC even when running
1443 * again on the same CPU. This may cause apparent elapsed
1444 * time to disappear, and the guest to stand still or run
1445 * very slowly.
1446 */
1447 if (vcpu->tsc_catchup) {
1448 u64 tsc = compute_guest_tsc(v, kernel_ns);
1449 if (tsc > tsc_timestamp) {
1450 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1451 tsc_timestamp = tsc;
1452 }
1453 }
1454
1455 local_irq_restore(flags);
1456
1457 if (!vcpu->time_page)
1458 return 0;
1459
1460 /*
1461 * Time as measured by the TSC may go backwards when resetting the base
1462 * tsc_timestamp. The reason for this is that the TSC resolution is
1463 * higher than the resolution of the other clock scales. Thus, many
1464 * possible measurments of the TSC correspond to one measurement of any
1465 * other clock, and so a spread of values is possible. This is not a
1466 * problem for the computation of the nanosecond clock; with TSC rates
1467 * around 1GHZ, there can only be a few cycles which correspond to one
1468 * nanosecond value, and any path through this code will inevitably
1469 * take longer than that. However, with the kernel_ns value itself,
1470 * the precision may be much lower, down to HZ granularity. If the
1471 * first sampling of TSC against kernel_ns ends in the low part of the
1472 * range, and the second in the high end of the range, we can get:
1473 *
1474 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1475 *
1476 * As the sampling errors potentially range in the thousands of cycles,
1477 * it is possible such a time value has already been observed by the
1478 * guest. To protect against this, we must compute the system time as
1479 * observed by the guest and ensure the new system time is greater.
1480 */
1481 max_kernel_ns = 0;
1482 if (vcpu->hv_clock.tsc_timestamp) {
1483 max_kernel_ns = vcpu->last_guest_tsc -
1484 vcpu->hv_clock.tsc_timestamp;
1485 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1486 vcpu->hv_clock.tsc_to_system_mul,
1487 vcpu->hv_clock.tsc_shift);
1488 max_kernel_ns += vcpu->last_kernel_ns;
1489 }
1490
1491 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1492 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1493 &vcpu->hv_clock.tsc_shift,
1494 &vcpu->hv_clock.tsc_to_system_mul);
1495 vcpu->hw_tsc_khz = this_tsc_khz;
1496 }
1497
1498 /* with a master <monotonic time, tsc value> tuple,
1499 * pvclock clock reads always increase at the (scaled) rate
1500 * of guest TSC - no need to deal with sampling errors.
1501 */
1502 if (!use_master_clock) {
1503 if (max_kernel_ns > kernel_ns)
1504 kernel_ns = max_kernel_ns;
1505 }
1506 /* With all the info we got, fill in the values */
1507 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1508 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1509 vcpu->last_kernel_ns = kernel_ns;
1510 vcpu->last_guest_tsc = tsc_timestamp;
1511
1512 /*
1513 * The interface expects us to write an even number signaling that the
1514 * update is finished. Since the guest won't see the intermediate
1515 * state, we just increase by 2 at the end.
1516 */
1517 vcpu->hv_clock.version += 2;
1518
1519 shared_kaddr = kmap_atomic(vcpu->time_page);
1520
1521 guest_hv_clock = shared_kaddr + vcpu->time_offset;
1522
1523 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1524 pvclock_flags = (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
1525
1526 if (vcpu->pvclock_set_guest_stopped_request) {
1527 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1528 vcpu->pvclock_set_guest_stopped_request = false;
1529 }
1530
1531 /* If the host uses TSC clocksource, then it is stable */
1532 if (use_master_clock)
1533 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1534
1535 vcpu->hv_clock.flags = pvclock_flags;
1536
1537 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1538 sizeof(vcpu->hv_clock));
1539
1540 kunmap_atomic(shared_kaddr);
1541
1542 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1543 return 0;
1544 }
1545
1546 static bool msr_mtrr_valid(unsigned msr)
1547 {
1548 switch (msr) {
1549 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1550 case MSR_MTRRfix64K_00000:
1551 case MSR_MTRRfix16K_80000:
1552 case MSR_MTRRfix16K_A0000:
1553 case MSR_MTRRfix4K_C0000:
1554 case MSR_MTRRfix4K_C8000:
1555 case MSR_MTRRfix4K_D0000:
1556 case MSR_MTRRfix4K_D8000:
1557 case MSR_MTRRfix4K_E0000:
1558 case MSR_MTRRfix4K_E8000:
1559 case MSR_MTRRfix4K_F0000:
1560 case MSR_MTRRfix4K_F8000:
1561 case MSR_MTRRdefType:
1562 case MSR_IA32_CR_PAT:
1563 return true;
1564 case 0x2f8:
1565 return true;
1566 }
1567 return false;
1568 }
1569
1570 static bool valid_pat_type(unsigned t)
1571 {
1572 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1573 }
1574
1575 static bool valid_mtrr_type(unsigned t)
1576 {
1577 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1578 }
1579
1580 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1581 {
1582 int i;
1583
1584 if (!msr_mtrr_valid(msr))
1585 return false;
1586
1587 if (msr == MSR_IA32_CR_PAT) {
1588 for (i = 0; i < 8; i++)
1589 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1590 return false;
1591 return true;
1592 } else if (msr == MSR_MTRRdefType) {
1593 if (data & ~0xcff)
1594 return false;
1595 return valid_mtrr_type(data & 0xff);
1596 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1597 for (i = 0; i < 8 ; i++)
1598 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1599 return false;
1600 return true;
1601 }
1602
1603 /* variable MTRRs */
1604 return valid_mtrr_type(data & 0xff);
1605 }
1606
1607 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1608 {
1609 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1610
1611 if (!mtrr_valid(vcpu, msr, data))
1612 return 1;
1613
1614 if (msr == MSR_MTRRdefType) {
1615 vcpu->arch.mtrr_state.def_type = data;
1616 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1617 } else if (msr == MSR_MTRRfix64K_00000)
1618 p[0] = data;
1619 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1620 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1621 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1622 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1623 else if (msr == MSR_IA32_CR_PAT)
1624 vcpu->arch.pat = data;
1625 else { /* Variable MTRRs */
1626 int idx, is_mtrr_mask;
1627 u64 *pt;
1628
1629 idx = (msr - 0x200) / 2;
1630 is_mtrr_mask = msr - 0x200 - 2 * idx;
1631 if (!is_mtrr_mask)
1632 pt =
1633 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1634 else
1635 pt =
1636 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1637 *pt = data;
1638 }
1639
1640 kvm_mmu_reset_context(vcpu);
1641 return 0;
1642 }
1643
1644 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1645 {
1646 u64 mcg_cap = vcpu->arch.mcg_cap;
1647 unsigned bank_num = mcg_cap & 0xff;
1648
1649 switch (msr) {
1650 case MSR_IA32_MCG_STATUS:
1651 vcpu->arch.mcg_status = data;
1652 break;
1653 case MSR_IA32_MCG_CTL:
1654 if (!(mcg_cap & MCG_CTL_P))
1655 return 1;
1656 if (data != 0 && data != ~(u64)0)
1657 return -1;
1658 vcpu->arch.mcg_ctl = data;
1659 break;
1660 default:
1661 if (msr >= MSR_IA32_MC0_CTL &&
1662 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1663 u32 offset = msr - MSR_IA32_MC0_CTL;
1664 /* only 0 or all 1s can be written to IA32_MCi_CTL
1665 * some Linux kernels though clear bit 10 in bank 4 to
1666 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1667 * this to avoid an uncatched #GP in the guest
1668 */
1669 if ((offset & 0x3) == 0 &&
1670 data != 0 && (data | (1 << 10)) != ~(u64)0)
1671 return -1;
1672 vcpu->arch.mce_banks[offset] = data;
1673 break;
1674 }
1675 return 1;
1676 }
1677 return 0;
1678 }
1679
1680 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1681 {
1682 struct kvm *kvm = vcpu->kvm;
1683 int lm = is_long_mode(vcpu);
1684 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1685 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1686 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1687 : kvm->arch.xen_hvm_config.blob_size_32;
1688 u32 page_num = data & ~PAGE_MASK;
1689 u64 page_addr = data & PAGE_MASK;
1690 u8 *page;
1691 int r;
1692
1693 r = -E2BIG;
1694 if (page_num >= blob_size)
1695 goto out;
1696 r = -ENOMEM;
1697 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1698 if (IS_ERR(page)) {
1699 r = PTR_ERR(page);
1700 goto out;
1701 }
1702 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1703 goto out_free;
1704 r = 0;
1705 out_free:
1706 kfree(page);
1707 out:
1708 return r;
1709 }
1710
1711 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1712 {
1713 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1714 }
1715
1716 static bool kvm_hv_msr_partition_wide(u32 msr)
1717 {
1718 bool r = false;
1719 switch (msr) {
1720 case HV_X64_MSR_GUEST_OS_ID:
1721 case HV_X64_MSR_HYPERCALL:
1722 r = true;
1723 break;
1724 }
1725
1726 return r;
1727 }
1728
1729 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1730 {
1731 struct kvm *kvm = vcpu->kvm;
1732
1733 switch (msr) {
1734 case HV_X64_MSR_GUEST_OS_ID:
1735 kvm->arch.hv_guest_os_id = data;
1736 /* setting guest os id to zero disables hypercall page */
1737 if (!kvm->arch.hv_guest_os_id)
1738 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1739 break;
1740 case HV_X64_MSR_HYPERCALL: {
1741 u64 gfn;
1742 unsigned long addr;
1743 u8 instructions[4];
1744
1745 /* if guest os id is not set hypercall should remain disabled */
1746 if (!kvm->arch.hv_guest_os_id)
1747 break;
1748 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1749 kvm->arch.hv_hypercall = data;
1750 break;
1751 }
1752 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1753 addr = gfn_to_hva(kvm, gfn);
1754 if (kvm_is_error_hva(addr))
1755 return 1;
1756 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1757 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1758 if (__copy_to_user((void __user *)addr, instructions, 4))
1759 return 1;
1760 kvm->arch.hv_hypercall = data;
1761 break;
1762 }
1763 default:
1764 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1765 "data 0x%llx\n", msr, data);
1766 return 1;
1767 }
1768 return 0;
1769 }
1770
1771 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1772 {
1773 switch (msr) {
1774 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1775 unsigned long addr;
1776
1777 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1778 vcpu->arch.hv_vapic = data;
1779 break;
1780 }
1781 addr = gfn_to_hva(vcpu->kvm, data >>
1782 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1783 if (kvm_is_error_hva(addr))
1784 return 1;
1785 if (__clear_user((void __user *)addr, PAGE_SIZE))
1786 return 1;
1787 vcpu->arch.hv_vapic = data;
1788 break;
1789 }
1790 case HV_X64_MSR_EOI:
1791 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1792 case HV_X64_MSR_ICR:
1793 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1794 case HV_X64_MSR_TPR:
1795 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1796 default:
1797 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1798 "data 0x%llx\n", msr, data);
1799 return 1;
1800 }
1801
1802 return 0;
1803 }
1804
1805 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1806 {
1807 gpa_t gpa = data & ~0x3f;
1808
1809 /* Bits 2:5 are reserved, Should be zero */
1810 if (data & 0x3c)
1811 return 1;
1812
1813 vcpu->arch.apf.msr_val = data;
1814
1815 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1816 kvm_clear_async_pf_completion_queue(vcpu);
1817 kvm_async_pf_hash_reset(vcpu);
1818 return 0;
1819 }
1820
1821 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1822 return 1;
1823
1824 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1825 kvm_async_pf_wakeup_all(vcpu);
1826 return 0;
1827 }
1828
1829 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1830 {
1831 if (vcpu->arch.time_page) {
1832 kvm_release_page_dirty(vcpu->arch.time_page);
1833 vcpu->arch.time_page = NULL;
1834 }
1835 }
1836
1837 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1838 {
1839 u64 delta;
1840
1841 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1842 return;
1843
1844 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1845 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1846 vcpu->arch.st.accum_steal = delta;
1847 }
1848
1849 static void record_steal_time(struct kvm_vcpu *vcpu)
1850 {
1851 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1852 return;
1853
1854 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1855 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1856 return;
1857
1858 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1859 vcpu->arch.st.steal.version += 2;
1860 vcpu->arch.st.accum_steal = 0;
1861
1862 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1863 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1864 }
1865
1866 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1867 {
1868 bool pr = false;
1869 u32 msr = msr_info->index;
1870 u64 data = msr_info->data;
1871
1872 switch (msr) {
1873 case MSR_EFER:
1874 return set_efer(vcpu, data);
1875 case MSR_K7_HWCR:
1876 data &= ~(u64)0x40; /* ignore flush filter disable */
1877 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1878 data &= ~(u64)0x8; /* ignore TLB cache disable */
1879 if (data != 0) {
1880 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1881 data);
1882 return 1;
1883 }
1884 break;
1885 case MSR_FAM10H_MMIO_CONF_BASE:
1886 if (data != 0) {
1887 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1888 "0x%llx\n", data);
1889 return 1;
1890 }
1891 break;
1892 case MSR_AMD64_NB_CFG:
1893 break;
1894 case MSR_IA32_DEBUGCTLMSR:
1895 if (!data) {
1896 /* We support the non-activated case already */
1897 break;
1898 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1899 /* Values other than LBR and BTF are vendor-specific,
1900 thus reserved and should throw a #GP */
1901 return 1;
1902 }
1903 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1904 __func__, data);
1905 break;
1906 case MSR_IA32_UCODE_REV:
1907 case MSR_IA32_UCODE_WRITE:
1908 case MSR_VM_HSAVE_PA:
1909 case MSR_AMD64_PATCH_LOADER:
1910 break;
1911 case 0x200 ... 0x2ff:
1912 return set_msr_mtrr(vcpu, msr, data);
1913 case MSR_IA32_APICBASE:
1914 kvm_set_apic_base(vcpu, data);
1915 break;
1916 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1917 return kvm_x2apic_msr_write(vcpu, msr, data);
1918 case MSR_IA32_TSCDEADLINE:
1919 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1920 break;
1921 case MSR_IA32_MISC_ENABLE:
1922 vcpu->arch.ia32_misc_enable_msr = data;
1923 break;
1924 case MSR_KVM_WALL_CLOCK_NEW:
1925 case MSR_KVM_WALL_CLOCK:
1926 vcpu->kvm->arch.wall_clock = data;
1927 kvm_write_wall_clock(vcpu->kvm, data);
1928 break;
1929 case MSR_KVM_SYSTEM_TIME_NEW:
1930 case MSR_KVM_SYSTEM_TIME: {
1931 kvmclock_reset(vcpu);
1932
1933 vcpu->arch.time = data;
1934 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1935
1936 /* we verify if the enable bit is set... */
1937 if (!(data & 1))
1938 break;
1939
1940 /* ...but clean it before doing the actual write */
1941 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1942
1943 vcpu->arch.time_page =
1944 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1945
1946 if (is_error_page(vcpu->arch.time_page))
1947 vcpu->arch.time_page = NULL;
1948
1949 break;
1950 }
1951 case MSR_KVM_ASYNC_PF_EN:
1952 if (kvm_pv_enable_async_pf(vcpu, data))
1953 return 1;
1954 break;
1955 case MSR_KVM_STEAL_TIME:
1956
1957 if (unlikely(!sched_info_on()))
1958 return 1;
1959
1960 if (data & KVM_STEAL_RESERVED_MASK)
1961 return 1;
1962
1963 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1964 data & KVM_STEAL_VALID_BITS))
1965 return 1;
1966
1967 vcpu->arch.st.msr_val = data;
1968
1969 if (!(data & KVM_MSR_ENABLED))
1970 break;
1971
1972 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1973
1974 preempt_disable();
1975 accumulate_steal_time(vcpu);
1976 preempt_enable();
1977
1978 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1979
1980 break;
1981 case MSR_KVM_PV_EOI_EN:
1982 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1983 return 1;
1984 break;
1985
1986 case MSR_IA32_MCG_CTL:
1987 case MSR_IA32_MCG_STATUS:
1988 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1989 return set_msr_mce(vcpu, msr, data);
1990
1991 /* Performance counters are not protected by a CPUID bit,
1992 * so we should check all of them in the generic path for the sake of
1993 * cross vendor migration.
1994 * Writing a zero into the event select MSRs disables them,
1995 * which we perfectly emulate ;-). Any other value should be at least
1996 * reported, some guests depend on them.
1997 */
1998 case MSR_K7_EVNTSEL0:
1999 case MSR_K7_EVNTSEL1:
2000 case MSR_K7_EVNTSEL2:
2001 case MSR_K7_EVNTSEL3:
2002 if (data != 0)
2003 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2004 "0x%x data 0x%llx\n", msr, data);
2005 break;
2006 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2007 * so we ignore writes to make it happy.
2008 */
2009 case MSR_K7_PERFCTR0:
2010 case MSR_K7_PERFCTR1:
2011 case MSR_K7_PERFCTR2:
2012 case MSR_K7_PERFCTR3:
2013 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2014 "0x%x data 0x%llx\n", msr, data);
2015 break;
2016 case MSR_P6_PERFCTR0:
2017 case MSR_P6_PERFCTR1:
2018 pr = true;
2019 case MSR_P6_EVNTSEL0:
2020 case MSR_P6_EVNTSEL1:
2021 if (kvm_pmu_msr(vcpu, msr))
2022 return kvm_pmu_set_msr(vcpu, msr, data);
2023
2024 if (pr || data != 0)
2025 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2026 "0x%x data 0x%llx\n", msr, data);
2027 break;
2028 case MSR_K7_CLK_CTL:
2029 /*
2030 * Ignore all writes to this no longer documented MSR.
2031 * Writes are only relevant for old K7 processors,
2032 * all pre-dating SVM, but a recommended workaround from
2033 * AMD for these chips. It is possible to specify the
2034 * affected processor models on the command line, hence
2035 * the need to ignore the workaround.
2036 */
2037 break;
2038 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2039 if (kvm_hv_msr_partition_wide(msr)) {
2040 int r;
2041 mutex_lock(&vcpu->kvm->lock);
2042 r = set_msr_hyperv_pw(vcpu, msr, data);
2043 mutex_unlock(&vcpu->kvm->lock);
2044 return r;
2045 } else
2046 return set_msr_hyperv(vcpu, msr, data);
2047 break;
2048 case MSR_IA32_BBL_CR_CTL3:
2049 /* Drop writes to this legacy MSR -- see rdmsr
2050 * counterpart for further detail.
2051 */
2052 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2053 break;
2054 case MSR_AMD64_OSVW_ID_LENGTH:
2055 if (!guest_cpuid_has_osvw(vcpu))
2056 return 1;
2057 vcpu->arch.osvw.length = data;
2058 break;
2059 case MSR_AMD64_OSVW_STATUS:
2060 if (!guest_cpuid_has_osvw(vcpu))
2061 return 1;
2062 vcpu->arch.osvw.status = data;
2063 break;
2064 default:
2065 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2066 return xen_hvm_config(vcpu, data);
2067 if (kvm_pmu_msr(vcpu, msr))
2068 return kvm_pmu_set_msr(vcpu, msr, data);
2069 if (!ignore_msrs) {
2070 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2071 msr, data);
2072 return 1;
2073 } else {
2074 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2075 msr, data);
2076 break;
2077 }
2078 }
2079 return 0;
2080 }
2081 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2082
2083
2084 /*
2085 * Reads an msr value (of 'msr_index') into 'pdata'.
2086 * Returns 0 on success, non-0 otherwise.
2087 * Assumes vcpu_load() was already called.
2088 */
2089 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2090 {
2091 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2092 }
2093
2094 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2095 {
2096 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2097
2098 if (!msr_mtrr_valid(msr))
2099 return 1;
2100
2101 if (msr == MSR_MTRRdefType)
2102 *pdata = vcpu->arch.mtrr_state.def_type +
2103 (vcpu->arch.mtrr_state.enabled << 10);
2104 else if (msr == MSR_MTRRfix64K_00000)
2105 *pdata = p[0];
2106 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2107 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2108 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2109 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2110 else if (msr == MSR_IA32_CR_PAT)
2111 *pdata = vcpu->arch.pat;
2112 else { /* Variable MTRRs */
2113 int idx, is_mtrr_mask;
2114 u64 *pt;
2115
2116 idx = (msr - 0x200) / 2;
2117 is_mtrr_mask = msr - 0x200 - 2 * idx;
2118 if (!is_mtrr_mask)
2119 pt =
2120 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2121 else
2122 pt =
2123 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2124 *pdata = *pt;
2125 }
2126
2127 return 0;
2128 }
2129
2130 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2131 {
2132 u64 data;
2133 u64 mcg_cap = vcpu->arch.mcg_cap;
2134 unsigned bank_num = mcg_cap & 0xff;
2135
2136 switch (msr) {
2137 case MSR_IA32_P5_MC_ADDR:
2138 case MSR_IA32_P5_MC_TYPE:
2139 data = 0;
2140 break;
2141 case MSR_IA32_MCG_CAP:
2142 data = vcpu->arch.mcg_cap;
2143 break;
2144 case MSR_IA32_MCG_CTL:
2145 if (!(mcg_cap & MCG_CTL_P))
2146 return 1;
2147 data = vcpu->arch.mcg_ctl;
2148 break;
2149 case MSR_IA32_MCG_STATUS:
2150 data = vcpu->arch.mcg_status;
2151 break;
2152 default:
2153 if (msr >= MSR_IA32_MC0_CTL &&
2154 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2155 u32 offset = msr - MSR_IA32_MC0_CTL;
2156 data = vcpu->arch.mce_banks[offset];
2157 break;
2158 }
2159 return 1;
2160 }
2161 *pdata = data;
2162 return 0;
2163 }
2164
2165 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2166 {
2167 u64 data = 0;
2168 struct kvm *kvm = vcpu->kvm;
2169
2170 switch (msr) {
2171 case HV_X64_MSR_GUEST_OS_ID:
2172 data = kvm->arch.hv_guest_os_id;
2173 break;
2174 case HV_X64_MSR_HYPERCALL:
2175 data = kvm->arch.hv_hypercall;
2176 break;
2177 default:
2178 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2179 return 1;
2180 }
2181
2182 *pdata = data;
2183 return 0;
2184 }
2185
2186 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2187 {
2188 u64 data = 0;
2189
2190 switch (msr) {
2191 case HV_X64_MSR_VP_INDEX: {
2192 int r;
2193 struct kvm_vcpu *v;
2194 kvm_for_each_vcpu(r, v, vcpu->kvm)
2195 if (v == vcpu)
2196 data = r;
2197 break;
2198 }
2199 case HV_X64_MSR_EOI:
2200 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2201 case HV_X64_MSR_ICR:
2202 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2203 case HV_X64_MSR_TPR:
2204 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2205 case HV_X64_MSR_APIC_ASSIST_PAGE:
2206 data = vcpu->arch.hv_vapic;
2207 break;
2208 default:
2209 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2210 return 1;
2211 }
2212 *pdata = data;
2213 return 0;
2214 }
2215
2216 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2217 {
2218 u64 data;
2219
2220 switch (msr) {
2221 case MSR_IA32_PLATFORM_ID:
2222 case MSR_IA32_EBL_CR_POWERON:
2223 case MSR_IA32_DEBUGCTLMSR:
2224 case MSR_IA32_LASTBRANCHFROMIP:
2225 case MSR_IA32_LASTBRANCHTOIP:
2226 case MSR_IA32_LASTINTFROMIP:
2227 case MSR_IA32_LASTINTTOIP:
2228 case MSR_K8_SYSCFG:
2229 case MSR_K7_HWCR:
2230 case MSR_VM_HSAVE_PA:
2231 case MSR_K7_EVNTSEL0:
2232 case MSR_K7_PERFCTR0:
2233 case MSR_K8_INT_PENDING_MSG:
2234 case MSR_AMD64_NB_CFG:
2235 case MSR_FAM10H_MMIO_CONF_BASE:
2236 data = 0;
2237 break;
2238 case MSR_P6_PERFCTR0:
2239 case MSR_P6_PERFCTR1:
2240 case MSR_P6_EVNTSEL0:
2241 case MSR_P6_EVNTSEL1:
2242 if (kvm_pmu_msr(vcpu, msr))
2243 return kvm_pmu_get_msr(vcpu, msr, pdata);
2244 data = 0;
2245 break;
2246 case MSR_IA32_UCODE_REV:
2247 data = 0x100000000ULL;
2248 break;
2249 case MSR_MTRRcap:
2250 data = 0x500 | KVM_NR_VAR_MTRR;
2251 break;
2252 case 0x200 ... 0x2ff:
2253 return get_msr_mtrr(vcpu, msr, pdata);
2254 case 0xcd: /* fsb frequency */
2255 data = 3;
2256 break;
2257 /*
2258 * MSR_EBC_FREQUENCY_ID
2259 * Conservative value valid for even the basic CPU models.
2260 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2261 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2262 * and 266MHz for model 3, or 4. Set Core Clock
2263 * Frequency to System Bus Frequency Ratio to 1 (bits
2264 * 31:24) even though these are only valid for CPU
2265 * models > 2, however guests may end up dividing or
2266 * multiplying by zero otherwise.
2267 */
2268 case MSR_EBC_FREQUENCY_ID:
2269 data = 1 << 24;
2270 break;
2271 case MSR_IA32_APICBASE:
2272 data = kvm_get_apic_base(vcpu);
2273 break;
2274 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2275 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2276 break;
2277 case MSR_IA32_TSCDEADLINE:
2278 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2279 break;
2280 case MSR_IA32_MISC_ENABLE:
2281 data = vcpu->arch.ia32_misc_enable_msr;
2282 break;
2283 case MSR_IA32_PERF_STATUS:
2284 /* TSC increment by tick */
2285 data = 1000ULL;
2286 /* CPU multiplier */
2287 data |= (((uint64_t)4ULL) << 40);
2288 break;
2289 case MSR_EFER:
2290 data = vcpu->arch.efer;
2291 break;
2292 case MSR_KVM_WALL_CLOCK:
2293 case MSR_KVM_WALL_CLOCK_NEW:
2294 data = vcpu->kvm->arch.wall_clock;
2295 break;
2296 case MSR_KVM_SYSTEM_TIME:
2297 case MSR_KVM_SYSTEM_TIME_NEW:
2298 data = vcpu->arch.time;
2299 break;
2300 case MSR_KVM_ASYNC_PF_EN:
2301 data = vcpu->arch.apf.msr_val;
2302 break;
2303 case MSR_KVM_STEAL_TIME:
2304 data = vcpu->arch.st.msr_val;
2305 break;
2306 case MSR_KVM_PV_EOI_EN:
2307 data = vcpu->arch.pv_eoi.msr_val;
2308 break;
2309 case MSR_IA32_P5_MC_ADDR:
2310 case MSR_IA32_P5_MC_TYPE:
2311 case MSR_IA32_MCG_CAP:
2312 case MSR_IA32_MCG_CTL:
2313 case MSR_IA32_MCG_STATUS:
2314 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2315 return get_msr_mce(vcpu, msr, pdata);
2316 case MSR_K7_CLK_CTL:
2317 /*
2318 * Provide expected ramp-up count for K7. All other
2319 * are set to zero, indicating minimum divisors for
2320 * every field.
2321 *
2322 * This prevents guest kernels on AMD host with CPU
2323 * type 6, model 8 and higher from exploding due to
2324 * the rdmsr failing.
2325 */
2326 data = 0x20000000;
2327 break;
2328 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2329 if (kvm_hv_msr_partition_wide(msr)) {
2330 int r;
2331 mutex_lock(&vcpu->kvm->lock);
2332 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2333 mutex_unlock(&vcpu->kvm->lock);
2334 return r;
2335 } else
2336 return get_msr_hyperv(vcpu, msr, pdata);
2337 break;
2338 case MSR_IA32_BBL_CR_CTL3:
2339 /* This legacy MSR exists but isn't fully documented in current
2340 * silicon. It is however accessed by winxp in very narrow
2341 * scenarios where it sets bit #19, itself documented as
2342 * a "reserved" bit. Best effort attempt to source coherent
2343 * read data here should the balance of the register be
2344 * interpreted by the guest:
2345 *
2346 * L2 cache control register 3: 64GB range, 256KB size,
2347 * enabled, latency 0x1, configured
2348 */
2349 data = 0xbe702111;
2350 break;
2351 case MSR_AMD64_OSVW_ID_LENGTH:
2352 if (!guest_cpuid_has_osvw(vcpu))
2353 return 1;
2354 data = vcpu->arch.osvw.length;
2355 break;
2356 case MSR_AMD64_OSVW_STATUS:
2357 if (!guest_cpuid_has_osvw(vcpu))
2358 return 1;
2359 data = vcpu->arch.osvw.status;
2360 break;
2361 default:
2362 if (kvm_pmu_msr(vcpu, msr))
2363 return kvm_pmu_get_msr(vcpu, msr, pdata);
2364 if (!ignore_msrs) {
2365 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2366 return 1;
2367 } else {
2368 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2369 data = 0;
2370 }
2371 break;
2372 }
2373 *pdata = data;
2374 return 0;
2375 }
2376 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2377
2378 /*
2379 * Read or write a bunch of msrs. All parameters are kernel addresses.
2380 *
2381 * @return number of msrs set successfully.
2382 */
2383 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2384 struct kvm_msr_entry *entries,
2385 int (*do_msr)(struct kvm_vcpu *vcpu,
2386 unsigned index, u64 *data))
2387 {
2388 int i, idx;
2389
2390 idx = srcu_read_lock(&vcpu->kvm->srcu);
2391 for (i = 0; i < msrs->nmsrs; ++i)
2392 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2393 break;
2394 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2395
2396 return i;
2397 }
2398
2399 /*
2400 * Read or write a bunch of msrs. Parameters are user addresses.
2401 *
2402 * @return number of msrs set successfully.
2403 */
2404 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2405 int (*do_msr)(struct kvm_vcpu *vcpu,
2406 unsigned index, u64 *data),
2407 int writeback)
2408 {
2409 struct kvm_msrs msrs;
2410 struct kvm_msr_entry *entries;
2411 int r, n;
2412 unsigned size;
2413
2414 r = -EFAULT;
2415 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2416 goto out;
2417
2418 r = -E2BIG;
2419 if (msrs.nmsrs >= MAX_IO_MSRS)
2420 goto out;
2421
2422 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2423 entries = memdup_user(user_msrs->entries, size);
2424 if (IS_ERR(entries)) {
2425 r = PTR_ERR(entries);
2426 goto out;
2427 }
2428
2429 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2430 if (r < 0)
2431 goto out_free;
2432
2433 r = -EFAULT;
2434 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2435 goto out_free;
2436
2437 r = n;
2438
2439 out_free:
2440 kfree(entries);
2441 out:
2442 return r;
2443 }
2444
2445 int kvm_dev_ioctl_check_extension(long ext)
2446 {
2447 int r;
2448
2449 switch (ext) {
2450 case KVM_CAP_IRQCHIP:
2451 case KVM_CAP_HLT:
2452 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2453 case KVM_CAP_SET_TSS_ADDR:
2454 case KVM_CAP_EXT_CPUID:
2455 case KVM_CAP_CLOCKSOURCE:
2456 case KVM_CAP_PIT:
2457 case KVM_CAP_NOP_IO_DELAY:
2458 case KVM_CAP_MP_STATE:
2459 case KVM_CAP_SYNC_MMU:
2460 case KVM_CAP_USER_NMI:
2461 case KVM_CAP_REINJECT_CONTROL:
2462 case KVM_CAP_IRQ_INJECT_STATUS:
2463 case KVM_CAP_ASSIGN_DEV_IRQ:
2464 case KVM_CAP_IRQFD:
2465 case KVM_CAP_IOEVENTFD:
2466 case KVM_CAP_PIT2:
2467 case KVM_CAP_PIT_STATE2:
2468 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2469 case KVM_CAP_XEN_HVM:
2470 case KVM_CAP_ADJUST_CLOCK:
2471 case KVM_CAP_VCPU_EVENTS:
2472 case KVM_CAP_HYPERV:
2473 case KVM_CAP_HYPERV_VAPIC:
2474 case KVM_CAP_HYPERV_SPIN:
2475 case KVM_CAP_PCI_SEGMENT:
2476 case KVM_CAP_DEBUGREGS:
2477 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2478 case KVM_CAP_XSAVE:
2479 case KVM_CAP_ASYNC_PF:
2480 case KVM_CAP_GET_TSC_KHZ:
2481 case KVM_CAP_PCI_2_3:
2482 case KVM_CAP_KVMCLOCK_CTRL:
2483 case KVM_CAP_READONLY_MEM:
2484 case KVM_CAP_IRQFD_RESAMPLE:
2485 r = 1;
2486 break;
2487 case KVM_CAP_COALESCED_MMIO:
2488 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2489 break;
2490 case KVM_CAP_VAPIC:
2491 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2492 break;
2493 case KVM_CAP_NR_VCPUS:
2494 r = KVM_SOFT_MAX_VCPUS;
2495 break;
2496 case KVM_CAP_MAX_VCPUS:
2497 r = KVM_MAX_VCPUS;
2498 break;
2499 case KVM_CAP_NR_MEMSLOTS:
2500 r = KVM_MEMORY_SLOTS;
2501 break;
2502 case KVM_CAP_PV_MMU: /* obsolete */
2503 r = 0;
2504 break;
2505 case KVM_CAP_IOMMU:
2506 r = iommu_present(&pci_bus_type);
2507 break;
2508 case KVM_CAP_MCE:
2509 r = KVM_MAX_MCE_BANKS;
2510 break;
2511 case KVM_CAP_XCRS:
2512 r = cpu_has_xsave;
2513 break;
2514 case KVM_CAP_TSC_CONTROL:
2515 r = kvm_has_tsc_control;
2516 break;
2517 case KVM_CAP_TSC_DEADLINE_TIMER:
2518 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2519 break;
2520 default:
2521 r = 0;
2522 break;
2523 }
2524 return r;
2525
2526 }
2527
2528 long kvm_arch_dev_ioctl(struct file *filp,
2529 unsigned int ioctl, unsigned long arg)
2530 {
2531 void __user *argp = (void __user *)arg;
2532 long r;
2533
2534 switch (ioctl) {
2535 case KVM_GET_MSR_INDEX_LIST: {
2536 struct kvm_msr_list __user *user_msr_list = argp;
2537 struct kvm_msr_list msr_list;
2538 unsigned n;
2539
2540 r = -EFAULT;
2541 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2542 goto out;
2543 n = msr_list.nmsrs;
2544 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2545 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2546 goto out;
2547 r = -E2BIG;
2548 if (n < msr_list.nmsrs)
2549 goto out;
2550 r = -EFAULT;
2551 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2552 num_msrs_to_save * sizeof(u32)))
2553 goto out;
2554 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2555 &emulated_msrs,
2556 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2557 goto out;
2558 r = 0;
2559 break;
2560 }
2561 case KVM_GET_SUPPORTED_CPUID: {
2562 struct kvm_cpuid2 __user *cpuid_arg = argp;
2563 struct kvm_cpuid2 cpuid;
2564
2565 r = -EFAULT;
2566 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2567 goto out;
2568 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2569 cpuid_arg->entries);
2570 if (r)
2571 goto out;
2572
2573 r = -EFAULT;
2574 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2575 goto out;
2576 r = 0;
2577 break;
2578 }
2579 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2580 u64 mce_cap;
2581
2582 mce_cap = KVM_MCE_CAP_SUPPORTED;
2583 r = -EFAULT;
2584 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2585 goto out;
2586 r = 0;
2587 break;
2588 }
2589 default:
2590 r = -EINVAL;
2591 }
2592 out:
2593 return r;
2594 }
2595
2596 static void wbinvd_ipi(void *garbage)
2597 {
2598 wbinvd();
2599 }
2600
2601 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2602 {
2603 return vcpu->kvm->arch.iommu_domain &&
2604 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2605 }
2606
2607 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2608 {
2609 /* Address WBINVD may be executed by guest */
2610 if (need_emulate_wbinvd(vcpu)) {
2611 if (kvm_x86_ops->has_wbinvd_exit())
2612 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2613 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2614 smp_call_function_single(vcpu->cpu,
2615 wbinvd_ipi, NULL, 1);
2616 }
2617
2618 kvm_x86_ops->vcpu_load(vcpu, cpu);
2619
2620 /* Apply any externally detected TSC adjustments (due to suspend) */
2621 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2622 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2623 vcpu->arch.tsc_offset_adjustment = 0;
2624 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2625 }
2626
2627 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2628 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2629 native_read_tsc() - vcpu->arch.last_host_tsc;
2630 if (tsc_delta < 0)
2631 mark_tsc_unstable("KVM discovered backwards TSC");
2632 if (check_tsc_unstable()) {
2633 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2634 vcpu->arch.last_guest_tsc);
2635 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2636 vcpu->arch.tsc_catchup = 1;
2637 }
2638 /*
2639 * On a host with synchronized TSC, there is no need to update
2640 * kvmclock on vcpu->cpu migration
2641 */
2642 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2643 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2644 if (vcpu->cpu != cpu)
2645 kvm_migrate_timers(vcpu);
2646 vcpu->cpu = cpu;
2647 }
2648
2649 accumulate_steal_time(vcpu);
2650 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2651 }
2652
2653 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2654 {
2655 kvm_x86_ops->vcpu_put(vcpu);
2656 kvm_put_guest_fpu(vcpu);
2657 vcpu->arch.last_host_tsc = native_read_tsc();
2658 }
2659
2660 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2661 struct kvm_lapic_state *s)
2662 {
2663 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2664
2665 return 0;
2666 }
2667
2668 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2669 struct kvm_lapic_state *s)
2670 {
2671 kvm_apic_post_state_restore(vcpu, s);
2672 update_cr8_intercept(vcpu);
2673
2674 return 0;
2675 }
2676
2677 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2678 struct kvm_interrupt *irq)
2679 {
2680 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
2681 return -EINVAL;
2682 if (irqchip_in_kernel(vcpu->kvm))
2683 return -ENXIO;
2684
2685 kvm_queue_interrupt(vcpu, irq->irq, false);
2686 kvm_make_request(KVM_REQ_EVENT, vcpu);
2687
2688 return 0;
2689 }
2690
2691 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2692 {
2693 kvm_inject_nmi(vcpu);
2694
2695 return 0;
2696 }
2697
2698 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2699 struct kvm_tpr_access_ctl *tac)
2700 {
2701 if (tac->flags)
2702 return -EINVAL;
2703 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2704 return 0;
2705 }
2706
2707 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2708 u64 mcg_cap)
2709 {
2710 int r;
2711 unsigned bank_num = mcg_cap & 0xff, bank;
2712
2713 r = -EINVAL;
2714 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2715 goto out;
2716 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2717 goto out;
2718 r = 0;
2719 vcpu->arch.mcg_cap = mcg_cap;
2720 /* Init IA32_MCG_CTL to all 1s */
2721 if (mcg_cap & MCG_CTL_P)
2722 vcpu->arch.mcg_ctl = ~(u64)0;
2723 /* Init IA32_MCi_CTL to all 1s */
2724 for (bank = 0; bank < bank_num; bank++)
2725 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2726 out:
2727 return r;
2728 }
2729
2730 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2731 struct kvm_x86_mce *mce)
2732 {
2733 u64 mcg_cap = vcpu->arch.mcg_cap;
2734 unsigned bank_num = mcg_cap & 0xff;
2735 u64 *banks = vcpu->arch.mce_banks;
2736
2737 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2738 return -EINVAL;
2739 /*
2740 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2741 * reporting is disabled
2742 */
2743 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2744 vcpu->arch.mcg_ctl != ~(u64)0)
2745 return 0;
2746 banks += 4 * mce->bank;
2747 /*
2748 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2749 * reporting is disabled for the bank
2750 */
2751 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2752 return 0;
2753 if (mce->status & MCI_STATUS_UC) {
2754 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2755 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2756 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2757 return 0;
2758 }
2759 if (banks[1] & MCI_STATUS_VAL)
2760 mce->status |= MCI_STATUS_OVER;
2761 banks[2] = mce->addr;
2762 banks[3] = mce->misc;
2763 vcpu->arch.mcg_status = mce->mcg_status;
2764 banks[1] = mce->status;
2765 kvm_queue_exception(vcpu, MC_VECTOR);
2766 } else if (!(banks[1] & MCI_STATUS_VAL)
2767 || !(banks[1] & MCI_STATUS_UC)) {
2768 if (banks[1] & MCI_STATUS_VAL)
2769 mce->status |= MCI_STATUS_OVER;
2770 banks[2] = mce->addr;
2771 banks[3] = mce->misc;
2772 banks[1] = mce->status;
2773 } else
2774 banks[1] |= MCI_STATUS_OVER;
2775 return 0;
2776 }
2777
2778 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2779 struct kvm_vcpu_events *events)
2780 {
2781 process_nmi(vcpu);
2782 events->exception.injected =
2783 vcpu->arch.exception.pending &&
2784 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2785 events->exception.nr = vcpu->arch.exception.nr;
2786 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2787 events->exception.pad = 0;
2788 events->exception.error_code = vcpu->arch.exception.error_code;
2789
2790 events->interrupt.injected =
2791 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2792 events->interrupt.nr = vcpu->arch.interrupt.nr;
2793 events->interrupt.soft = 0;
2794 events->interrupt.shadow =
2795 kvm_x86_ops->get_interrupt_shadow(vcpu,
2796 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2797
2798 events->nmi.injected = vcpu->arch.nmi_injected;
2799 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2800 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2801 events->nmi.pad = 0;
2802
2803 events->sipi_vector = vcpu->arch.sipi_vector;
2804
2805 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2806 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2807 | KVM_VCPUEVENT_VALID_SHADOW);
2808 memset(&events->reserved, 0, sizeof(events->reserved));
2809 }
2810
2811 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2812 struct kvm_vcpu_events *events)
2813 {
2814 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2815 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2816 | KVM_VCPUEVENT_VALID_SHADOW))
2817 return -EINVAL;
2818
2819 process_nmi(vcpu);
2820 vcpu->arch.exception.pending = events->exception.injected;
2821 vcpu->arch.exception.nr = events->exception.nr;
2822 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2823 vcpu->arch.exception.error_code = events->exception.error_code;
2824
2825 vcpu->arch.interrupt.pending = events->interrupt.injected;
2826 vcpu->arch.interrupt.nr = events->interrupt.nr;
2827 vcpu->arch.interrupt.soft = events->interrupt.soft;
2828 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2829 kvm_x86_ops->set_interrupt_shadow(vcpu,
2830 events->interrupt.shadow);
2831
2832 vcpu->arch.nmi_injected = events->nmi.injected;
2833 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2834 vcpu->arch.nmi_pending = events->nmi.pending;
2835 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2836
2837 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2838 vcpu->arch.sipi_vector = events->sipi_vector;
2839
2840 kvm_make_request(KVM_REQ_EVENT, vcpu);
2841
2842 return 0;
2843 }
2844
2845 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2846 struct kvm_debugregs *dbgregs)
2847 {
2848 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2849 dbgregs->dr6 = vcpu->arch.dr6;
2850 dbgregs->dr7 = vcpu->arch.dr7;
2851 dbgregs->flags = 0;
2852 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2853 }
2854
2855 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2856 struct kvm_debugregs *dbgregs)
2857 {
2858 if (dbgregs->flags)
2859 return -EINVAL;
2860
2861 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2862 vcpu->arch.dr6 = dbgregs->dr6;
2863 vcpu->arch.dr7 = dbgregs->dr7;
2864
2865 return 0;
2866 }
2867
2868 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2869 struct kvm_xsave *guest_xsave)
2870 {
2871 if (cpu_has_xsave)
2872 memcpy(guest_xsave->region,
2873 &vcpu->arch.guest_fpu.state->xsave,
2874 xstate_size);
2875 else {
2876 memcpy(guest_xsave->region,
2877 &vcpu->arch.guest_fpu.state->fxsave,
2878 sizeof(struct i387_fxsave_struct));
2879 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2880 XSTATE_FPSSE;
2881 }
2882 }
2883
2884 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2885 struct kvm_xsave *guest_xsave)
2886 {
2887 u64 xstate_bv =
2888 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2889
2890 if (cpu_has_xsave)
2891 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2892 guest_xsave->region, xstate_size);
2893 else {
2894 if (xstate_bv & ~XSTATE_FPSSE)
2895 return -EINVAL;
2896 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2897 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2898 }
2899 return 0;
2900 }
2901
2902 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2903 struct kvm_xcrs *guest_xcrs)
2904 {
2905 if (!cpu_has_xsave) {
2906 guest_xcrs->nr_xcrs = 0;
2907 return;
2908 }
2909
2910 guest_xcrs->nr_xcrs = 1;
2911 guest_xcrs->flags = 0;
2912 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2913 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2914 }
2915
2916 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2917 struct kvm_xcrs *guest_xcrs)
2918 {
2919 int i, r = 0;
2920
2921 if (!cpu_has_xsave)
2922 return -EINVAL;
2923
2924 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2925 return -EINVAL;
2926
2927 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2928 /* Only support XCR0 currently */
2929 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2930 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2931 guest_xcrs->xcrs[0].value);
2932 break;
2933 }
2934 if (r)
2935 r = -EINVAL;
2936 return r;
2937 }
2938
2939 /*
2940 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2941 * stopped by the hypervisor. This function will be called from the host only.
2942 * EINVAL is returned when the host attempts to set the flag for a guest that
2943 * does not support pv clocks.
2944 */
2945 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2946 {
2947 if (!vcpu->arch.time_page)
2948 return -EINVAL;
2949 vcpu->arch.pvclock_set_guest_stopped_request = true;
2950 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2951 return 0;
2952 }
2953
2954 long kvm_arch_vcpu_ioctl(struct file *filp,
2955 unsigned int ioctl, unsigned long arg)
2956 {
2957 struct kvm_vcpu *vcpu = filp->private_data;
2958 void __user *argp = (void __user *)arg;
2959 int r;
2960 union {
2961 struct kvm_lapic_state *lapic;
2962 struct kvm_xsave *xsave;
2963 struct kvm_xcrs *xcrs;
2964 void *buffer;
2965 } u;
2966
2967 u.buffer = NULL;
2968 switch (ioctl) {
2969 case KVM_GET_LAPIC: {
2970 r = -EINVAL;
2971 if (!vcpu->arch.apic)
2972 goto out;
2973 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2974
2975 r = -ENOMEM;
2976 if (!u.lapic)
2977 goto out;
2978 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2979 if (r)
2980 goto out;
2981 r = -EFAULT;
2982 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2983 goto out;
2984 r = 0;
2985 break;
2986 }
2987 case KVM_SET_LAPIC: {
2988 if (!vcpu->arch.apic)
2989 goto out;
2990 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2991 if (IS_ERR(u.lapic))
2992 return PTR_ERR(u.lapic);
2993
2994 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2995 break;
2996 }
2997 case KVM_INTERRUPT: {
2998 struct kvm_interrupt irq;
2999
3000 r = -EFAULT;
3001 if (copy_from_user(&irq, argp, sizeof irq))
3002 goto out;
3003 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3004 break;
3005 }
3006 case KVM_NMI: {
3007 r = kvm_vcpu_ioctl_nmi(vcpu);
3008 break;
3009 }
3010 case KVM_SET_CPUID: {
3011 struct kvm_cpuid __user *cpuid_arg = argp;
3012 struct kvm_cpuid cpuid;
3013
3014 r = -EFAULT;
3015 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3016 goto out;
3017 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3018 break;
3019 }
3020 case KVM_SET_CPUID2: {
3021 struct kvm_cpuid2 __user *cpuid_arg = argp;
3022 struct kvm_cpuid2 cpuid;
3023
3024 r = -EFAULT;
3025 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3026 goto out;
3027 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3028 cpuid_arg->entries);
3029 break;
3030 }
3031 case KVM_GET_CPUID2: {
3032 struct kvm_cpuid2 __user *cpuid_arg = argp;
3033 struct kvm_cpuid2 cpuid;
3034
3035 r = -EFAULT;
3036 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3037 goto out;
3038 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3039 cpuid_arg->entries);
3040 if (r)
3041 goto out;
3042 r = -EFAULT;
3043 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3044 goto out;
3045 r = 0;
3046 break;
3047 }
3048 case KVM_GET_MSRS:
3049 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3050 break;
3051 case KVM_SET_MSRS:
3052 r = msr_io(vcpu, argp, do_set_msr, 0);
3053 break;
3054 case KVM_TPR_ACCESS_REPORTING: {
3055 struct kvm_tpr_access_ctl tac;
3056
3057 r = -EFAULT;
3058 if (copy_from_user(&tac, argp, sizeof tac))
3059 goto out;
3060 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3061 if (r)
3062 goto out;
3063 r = -EFAULT;
3064 if (copy_to_user(argp, &tac, sizeof tac))
3065 goto out;
3066 r = 0;
3067 break;
3068 };
3069 case KVM_SET_VAPIC_ADDR: {
3070 struct kvm_vapic_addr va;
3071
3072 r = -EINVAL;
3073 if (!irqchip_in_kernel(vcpu->kvm))
3074 goto out;
3075 r = -EFAULT;
3076 if (copy_from_user(&va, argp, sizeof va))
3077 goto out;
3078 r = 0;
3079 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3080 break;
3081 }
3082 case KVM_X86_SETUP_MCE: {
3083 u64 mcg_cap;
3084
3085 r = -EFAULT;
3086 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3087 goto out;
3088 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3089 break;
3090 }
3091 case KVM_X86_SET_MCE: {
3092 struct kvm_x86_mce mce;
3093
3094 r = -EFAULT;
3095 if (copy_from_user(&mce, argp, sizeof mce))
3096 goto out;
3097 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3098 break;
3099 }
3100 case KVM_GET_VCPU_EVENTS: {
3101 struct kvm_vcpu_events events;
3102
3103 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3104
3105 r = -EFAULT;
3106 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3107 break;
3108 r = 0;
3109 break;
3110 }
3111 case KVM_SET_VCPU_EVENTS: {
3112 struct kvm_vcpu_events events;
3113
3114 r = -EFAULT;
3115 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3116 break;
3117
3118 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3119 break;
3120 }
3121 case KVM_GET_DEBUGREGS: {
3122 struct kvm_debugregs dbgregs;
3123
3124 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3125
3126 r = -EFAULT;
3127 if (copy_to_user(argp, &dbgregs,
3128 sizeof(struct kvm_debugregs)))
3129 break;
3130 r = 0;
3131 break;
3132 }
3133 case KVM_SET_DEBUGREGS: {
3134 struct kvm_debugregs dbgregs;
3135
3136 r = -EFAULT;
3137 if (copy_from_user(&dbgregs, argp,
3138 sizeof(struct kvm_debugregs)))
3139 break;
3140
3141 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3142 break;
3143 }
3144 case KVM_GET_XSAVE: {
3145 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3146 r = -ENOMEM;
3147 if (!u.xsave)
3148 break;
3149
3150 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3151
3152 r = -EFAULT;
3153 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3154 break;
3155 r = 0;
3156 break;
3157 }
3158 case KVM_SET_XSAVE: {
3159 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3160 if (IS_ERR(u.xsave))
3161 return PTR_ERR(u.xsave);
3162
3163 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3164 break;
3165 }
3166 case KVM_GET_XCRS: {
3167 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3168 r = -ENOMEM;
3169 if (!u.xcrs)
3170 break;
3171
3172 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3173
3174 r = -EFAULT;
3175 if (copy_to_user(argp, u.xcrs,
3176 sizeof(struct kvm_xcrs)))
3177 break;
3178 r = 0;
3179 break;
3180 }
3181 case KVM_SET_XCRS: {
3182 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3183 if (IS_ERR(u.xcrs))
3184 return PTR_ERR(u.xcrs);
3185
3186 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3187 break;
3188 }
3189 case KVM_SET_TSC_KHZ: {
3190 u32 user_tsc_khz;
3191
3192 r = -EINVAL;
3193 user_tsc_khz = (u32)arg;
3194
3195 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3196 goto out;
3197
3198 if (user_tsc_khz == 0)
3199 user_tsc_khz = tsc_khz;
3200
3201 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3202
3203 r = 0;
3204 goto out;
3205 }
3206 case KVM_GET_TSC_KHZ: {
3207 r = vcpu->arch.virtual_tsc_khz;
3208 goto out;
3209 }
3210 case KVM_KVMCLOCK_CTRL: {
3211 r = kvm_set_guest_paused(vcpu);
3212 goto out;
3213 }
3214 default:
3215 r = -EINVAL;
3216 }
3217 out:
3218 kfree(u.buffer);
3219 return r;
3220 }
3221
3222 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3223 {
3224 return VM_FAULT_SIGBUS;
3225 }
3226
3227 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3228 {
3229 int ret;
3230
3231 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3232 return -EINVAL;
3233 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3234 return ret;
3235 }
3236
3237 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3238 u64 ident_addr)
3239 {
3240 kvm->arch.ept_identity_map_addr = ident_addr;
3241 return 0;
3242 }
3243
3244 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3245 u32 kvm_nr_mmu_pages)
3246 {
3247 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3248 return -EINVAL;
3249
3250 mutex_lock(&kvm->slots_lock);
3251 spin_lock(&kvm->mmu_lock);
3252
3253 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3254 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3255
3256 spin_unlock(&kvm->mmu_lock);
3257 mutex_unlock(&kvm->slots_lock);
3258 return 0;
3259 }
3260
3261 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3262 {
3263 return kvm->arch.n_max_mmu_pages;
3264 }
3265
3266 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3267 {
3268 int r;
3269
3270 r = 0;
3271 switch (chip->chip_id) {
3272 case KVM_IRQCHIP_PIC_MASTER:
3273 memcpy(&chip->chip.pic,
3274 &pic_irqchip(kvm)->pics[0],
3275 sizeof(struct kvm_pic_state));
3276 break;
3277 case KVM_IRQCHIP_PIC_SLAVE:
3278 memcpy(&chip->chip.pic,
3279 &pic_irqchip(kvm)->pics[1],
3280 sizeof(struct kvm_pic_state));
3281 break;
3282 case KVM_IRQCHIP_IOAPIC:
3283 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3284 break;
3285 default:
3286 r = -EINVAL;
3287 break;
3288 }
3289 return r;
3290 }
3291
3292 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3293 {
3294 int r;
3295
3296 r = 0;
3297 switch (chip->chip_id) {
3298 case KVM_IRQCHIP_PIC_MASTER:
3299 spin_lock(&pic_irqchip(kvm)->lock);
3300 memcpy(&pic_irqchip(kvm)->pics[0],
3301 &chip->chip.pic,
3302 sizeof(struct kvm_pic_state));
3303 spin_unlock(&pic_irqchip(kvm)->lock);
3304 break;
3305 case KVM_IRQCHIP_PIC_SLAVE:
3306 spin_lock(&pic_irqchip(kvm)->lock);
3307 memcpy(&pic_irqchip(kvm)->pics[1],
3308 &chip->chip.pic,
3309 sizeof(struct kvm_pic_state));
3310 spin_unlock(&pic_irqchip(kvm)->lock);
3311 break;
3312 case KVM_IRQCHIP_IOAPIC:
3313 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3314 break;
3315 default:
3316 r = -EINVAL;
3317 break;
3318 }
3319 kvm_pic_update_irq(pic_irqchip(kvm));
3320 return r;
3321 }
3322
3323 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3324 {
3325 int r = 0;
3326
3327 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3328 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3329 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3330 return r;
3331 }
3332
3333 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3334 {
3335 int r = 0;
3336
3337 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3338 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3339 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3340 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3341 return r;
3342 }
3343
3344 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3345 {
3346 int r = 0;
3347
3348 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3349 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3350 sizeof(ps->channels));
3351 ps->flags = kvm->arch.vpit->pit_state.flags;
3352 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3353 memset(&ps->reserved, 0, sizeof(ps->reserved));
3354 return r;
3355 }
3356
3357 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3358 {
3359 int r = 0, start = 0;
3360 u32 prev_legacy, cur_legacy;
3361 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3362 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3363 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3364 if (!prev_legacy && cur_legacy)
3365 start = 1;
3366 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3367 sizeof(kvm->arch.vpit->pit_state.channels));
3368 kvm->arch.vpit->pit_state.flags = ps->flags;
3369 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3370 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3371 return r;
3372 }
3373
3374 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3375 struct kvm_reinject_control *control)
3376 {
3377 if (!kvm->arch.vpit)
3378 return -ENXIO;
3379 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3380 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3381 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3382 return 0;
3383 }
3384
3385 /**
3386 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3387 * @kvm: kvm instance
3388 * @log: slot id and address to which we copy the log
3389 *
3390 * We need to keep it in mind that VCPU threads can write to the bitmap
3391 * concurrently. So, to avoid losing data, we keep the following order for
3392 * each bit:
3393 *
3394 * 1. Take a snapshot of the bit and clear it if needed.
3395 * 2. Write protect the corresponding page.
3396 * 3. Flush TLB's if needed.
3397 * 4. Copy the snapshot to the userspace.
3398 *
3399 * Between 2 and 3, the guest may write to the page using the remaining TLB
3400 * entry. This is not a problem because the page will be reported dirty at
3401 * step 4 using the snapshot taken before and step 3 ensures that successive
3402 * writes will be logged for the next call.
3403 */
3404 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3405 {
3406 int r;
3407 struct kvm_memory_slot *memslot;
3408 unsigned long n, i;
3409 unsigned long *dirty_bitmap;
3410 unsigned long *dirty_bitmap_buffer;
3411 bool is_dirty = false;
3412
3413 mutex_lock(&kvm->slots_lock);
3414
3415 r = -EINVAL;
3416 if (log->slot >= KVM_MEMORY_SLOTS)
3417 goto out;
3418
3419 memslot = id_to_memslot(kvm->memslots, log->slot);
3420
3421 dirty_bitmap = memslot->dirty_bitmap;
3422 r = -ENOENT;
3423 if (!dirty_bitmap)
3424 goto out;
3425
3426 n = kvm_dirty_bitmap_bytes(memslot);
3427
3428 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3429 memset(dirty_bitmap_buffer, 0, n);
3430
3431 spin_lock(&kvm->mmu_lock);
3432
3433 for (i = 0; i < n / sizeof(long); i++) {
3434 unsigned long mask;
3435 gfn_t offset;
3436
3437 if (!dirty_bitmap[i])
3438 continue;
3439
3440 is_dirty = true;
3441
3442 mask = xchg(&dirty_bitmap[i], 0);
3443 dirty_bitmap_buffer[i] = mask;
3444
3445 offset = i * BITS_PER_LONG;
3446 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3447 }
3448 if (is_dirty)
3449 kvm_flush_remote_tlbs(kvm);
3450
3451 spin_unlock(&kvm->mmu_lock);
3452
3453 r = -EFAULT;
3454 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3455 goto out;
3456
3457 r = 0;
3458 out:
3459 mutex_unlock(&kvm->slots_lock);
3460 return r;
3461 }
3462
3463 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3464 {
3465 if (!irqchip_in_kernel(kvm))
3466 return -ENXIO;
3467
3468 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3469 irq_event->irq, irq_event->level);
3470 return 0;
3471 }
3472
3473 long kvm_arch_vm_ioctl(struct file *filp,
3474 unsigned int ioctl, unsigned long arg)
3475 {
3476 struct kvm *kvm = filp->private_data;
3477 void __user *argp = (void __user *)arg;
3478 int r = -ENOTTY;
3479 /*
3480 * This union makes it completely explicit to gcc-3.x
3481 * that these two variables' stack usage should be
3482 * combined, not added together.
3483 */
3484 union {
3485 struct kvm_pit_state ps;
3486 struct kvm_pit_state2 ps2;
3487 struct kvm_pit_config pit_config;
3488 } u;
3489
3490 switch (ioctl) {
3491 case KVM_SET_TSS_ADDR:
3492 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3493 break;
3494 case KVM_SET_IDENTITY_MAP_ADDR: {
3495 u64 ident_addr;
3496
3497 r = -EFAULT;
3498 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3499 goto out;
3500 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3501 break;
3502 }
3503 case KVM_SET_NR_MMU_PAGES:
3504 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3505 break;
3506 case KVM_GET_NR_MMU_PAGES:
3507 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3508 break;
3509 case KVM_CREATE_IRQCHIP: {
3510 struct kvm_pic *vpic;
3511
3512 mutex_lock(&kvm->lock);
3513 r = -EEXIST;
3514 if (kvm->arch.vpic)
3515 goto create_irqchip_unlock;
3516 r = -EINVAL;
3517 if (atomic_read(&kvm->online_vcpus))
3518 goto create_irqchip_unlock;
3519 r = -ENOMEM;
3520 vpic = kvm_create_pic(kvm);
3521 if (vpic) {
3522 r = kvm_ioapic_init(kvm);
3523 if (r) {
3524 mutex_lock(&kvm->slots_lock);
3525 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3526 &vpic->dev_master);
3527 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3528 &vpic->dev_slave);
3529 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3530 &vpic->dev_eclr);
3531 mutex_unlock(&kvm->slots_lock);
3532 kfree(vpic);
3533 goto create_irqchip_unlock;
3534 }
3535 } else
3536 goto create_irqchip_unlock;
3537 smp_wmb();
3538 kvm->arch.vpic = vpic;
3539 smp_wmb();
3540 r = kvm_setup_default_irq_routing(kvm);
3541 if (r) {
3542 mutex_lock(&kvm->slots_lock);
3543 mutex_lock(&kvm->irq_lock);
3544 kvm_ioapic_destroy(kvm);
3545 kvm_destroy_pic(kvm);
3546 mutex_unlock(&kvm->irq_lock);
3547 mutex_unlock(&kvm->slots_lock);
3548 }
3549 create_irqchip_unlock:
3550 mutex_unlock(&kvm->lock);
3551 break;
3552 }
3553 case KVM_CREATE_PIT:
3554 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3555 goto create_pit;
3556 case KVM_CREATE_PIT2:
3557 r = -EFAULT;
3558 if (copy_from_user(&u.pit_config, argp,
3559 sizeof(struct kvm_pit_config)))
3560 goto out;
3561 create_pit:
3562 mutex_lock(&kvm->slots_lock);
3563 r = -EEXIST;
3564 if (kvm->arch.vpit)
3565 goto create_pit_unlock;
3566 r = -ENOMEM;
3567 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3568 if (kvm->arch.vpit)
3569 r = 0;
3570 create_pit_unlock:
3571 mutex_unlock(&kvm->slots_lock);
3572 break;
3573 case KVM_GET_IRQCHIP: {
3574 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3575 struct kvm_irqchip *chip;
3576
3577 chip = memdup_user(argp, sizeof(*chip));
3578 if (IS_ERR(chip)) {
3579 r = PTR_ERR(chip);
3580 goto out;
3581 }
3582
3583 r = -ENXIO;
3584 if (!irqchip_in_kernel(kvm))
3585 goto get_irqchip_out;
3586 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3587 if (r)
3588 goto get_irqchip_out;
3589 r = -EFAULT;
3590 if (copy_to_user(argp, chip, sizeof *chip))
3591 goto get_irqchip_out;
3592 r = 0;
3593 get_irqchip_out:
3594 kfree(chip);
3595 break;
3596 }
3597 case KVM_SET_IRQCHIP: {
3598 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3599 struct kvm_irqchip *chip;
3600
3601 chip = memdup_user(argp, sizeof(*chip));
3602 if (IS_ERR(chip)) {
3603 r = PTR_ERR(chip);
3604 goto out;
3605 }
3606
3607 r = -ENXIO;
3608 if (!irqchip_in_kernel(kvm))
3609 goto set_irqchip_out;
3610 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3611 if (r)
3612 goto set_irqchip_out;
3613 r = 0;
3614 set_irqchip_out:
3615 kfree(chip);
3616 break;
3617 }
3618 case KVM_GET_PIT: {
3619 r = -EFAULT;
3620 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3621 goto out;
3622 r = -ENXIO;
3623 if (!kvm->arch.vpit)
3624 goto out;
3625 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3626 if (r)
3627 goto out;
3628 r = -EFAULT;
3629 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3630 goto out;
3631 r = 0;
3632 break;
3633 }
3634 case KVM_SET_PIT: {
3635 r = -EFAULT;
3636 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3637 goto out;
3638 r = -ENXIO;
3639 if (!kvm->arch.vpit)
3640 goto out;
3641 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3642 break;
3643 }
3644 case KVM_GET_PIT2: {
3645 r = -ENXIO;
3646 if (!kvm->arch.vpit)
3647 goto out;
3648 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3649 if (r)
3650 goto out;
3651 r = -EFAULT;
3652 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3653 goto out;
3654 r = 0;
3655 break;
3656 }
3657 case KVM_SET_PIT2: {
3658 r = -EFAULT;
3659 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3660 goto out;
3661 r = -ENXIO;
3662 if (!kvm->arch.vpit)
3663 goto out;
3664 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3665 break;
3666 }
3667 case KVM_REINJECT_CONTROL: {
3668 struct kvm_reinject_control control;
3669 r = -EFAULT;
3670 if (copy_from_user(&control, argp, sizeof(control)))
3671 goto out;
3672 r = kvm_vm_ioctl_reinject(kvm, &control);
3673 break;
3674 }
3675 case KVM_XEN_HVM_CONFIG: {
3676 r = -EFAULT;
3677 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3678 sizeof(struct kvm_xen_hvm_config)))
3679 goto out;
3680 r = -EINVAL;
3681 if (kvm->arch.xen_hvm_config.flags)
3682 goto out;
3683 r = 0;
3684 break;
3685 }
3686 case KVM_SET_CLOCK: {
3687 struct kvm_clock_data user_ns;
3688 u64 now_ns;
3689 s64 delta;
3690
3691 r = -EFAULT;
3692 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3693 goto out;
3694
3695 r = -EINVAL;
3696 if (user_ns.flags)
3697 goto out;
3698
3699 r = 0;
3700 local_irq_disable();
3701 now_ns = get_kernel_ns();
3702 delta = user_ns.clock - now_ns;
3703 local_irq_enable();
3704 kvm->arch.kvmclock_offset = delta;
3705 break;
3706 }
3707 case KVM_GET_CLOCK: {
3708 struct kvm_clock_data user_ns;
3709 u64 now_ns;
3710
3711 local_irq_disable();
3712 now_ns = get_kernel_ns();
3713 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3714 local_irq_enable();
3715 user_ns.flags = 0;
3716 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3717
3718 r = -EFAULT;
3719 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3720 goto out;
3721 r = 0;
3722 break;
3723 }
3724
3725 default:
3726 ;
3727 }
3728 out:
3729 return r;
3730 }
3731
3732 static void kvm_init_msr_list(void)
3733 {
3734 u32 dummy[2];
3735 unsigned i, j;
3736
3737 /* skip the first msrs in the list. KVM-specific */
3738 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3739 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3740 continue;
3741 if (j < i)
3742 msrs_to_save[j] = msrs_to_save[i];
3743 j++;
3744 }
3745 num_msrs_to_save = j;
3746 }
3747
3748 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3749 const void *v)
3750 {
3751 int handled = 0;
3752 int n;
3753
3754 do {
3755 n = min(len, 8);
3756 if (!(vcpu->arch.apic &&
3757 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3758 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3759 break;
3760 handled += n;
3761 addr += n;
3762 len -= n;
3763 v += n;
3764 } while (len);
3765
3766 return handled;
3767 }
3768
3769 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3770 {
3771 int handled = 0;
3772 int n;
3773
3774 do {
3775 n = min(len, 8);
3776 if (!(vcpu->arch.apic &&
3777 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3778 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3779 break;
3780 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3781 handled += n;
3782 addr += n;
3783 len -= n;
3784 v += n;
3785 } while (len);
3786
3787 return handled;
3788 }
3789
3790 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3791 struct kvm_segment *var, int seg)
3792 {
3793 kvm_x86_ops->set_segment(vcpu, var, seg);
3794 }
3795
3796 void kvm_get_segment(struct kvm_vcpu *vcpu,
3797 struct kvm_segment *var, int seg)
3798 {
3799 kvm_x86_ops->get_segment(vcpu, var, seg);
3800 }
3801
3802 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3803 {
3804 gpa_t t_gpa;
3805 struct x86_exception exception;
3806
3807 BUG_ON(!mmu_is_nested(vcpu));
3808
3809 /* NPT walks are always user-walks */
3810 access |= PFERR_USER_MASK;
3811 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3812
3813 return t_gpa;
3814 }
3815
3816 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3817 struct x86_exception *exception)
3818 {
3819 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3820 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3821 }
3822
3823 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3824 struct x86_exception *exception)
3825 {
3826 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3827 access |= PFERR_FETCH_MASK;
3828 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3829 }
3830
3831 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3832 struct x86_exception *exception)
3833 {
3834 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3835 access |= PFERR_WRITE_MASK;
3836 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3837 }
3838
3839 /* uses this to access any guest's mapped memory without checking CPL */
3840 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3841 struct x86_exception *exception)
3842 {
3843 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3844 }
3845
3846 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3847 struct kvm_vcpu *vcpu, u32 access,
3848 struct x86_exception *exception)
3849 {
3850 void *data = val;
3851 int r = X86EMUL_CONTINUE;
3852
3853 while (bytes) {
3854 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3855 exception);
3856 unsigned offset = addr & (PAGE_SIZE-1);
3857 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3858 int ret;
3859
3860 if (gpa == UNMAPPED_GVA)
3861 return X86EMUL_PROPAGATE_FAULT;
3862 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3863 if (ret < 0) {
3864 r = X86EMUL_IO_NEEDED;
3865 goto out;
3866 }
3867
3868 bytes -= toread;
3869 data += toread;
3870 addr += toread;
3871 }
3872 out:
3873 return r;
3874 }
3875
3876 /* used for instruction fetching */
3877 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3878 gva_t addr, void *val, unsigned int bytes,
3879 struct x86_exception *exception)
3880 {
3881 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3882 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3883
3884 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3885 access | PFERR_FETCH_MASK,
3886 exception);
3887 }
3888
3889 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3890 gva_t addr, void *val, unsigned int bytes,
3891 struct x86_exception *exception)
3892 {
3893 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3894 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3895
3896 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3897 exception);
3898 }
3899 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3900
3901 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3902 gva_t addr, void *val, unsigned int bytes,
3903 struct x86_exception *exception)
3904 {
3905 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3906 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3907 }
3908
3909 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3910 gva_t addr, void *val,
3911 unsigned int bytes,
3912 struct x86_exception *exception)
3913 {
3914 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3915 void *data = val;
3916 int r = X86EMUL_CONTINUE;
3917
3918 while (bytes) {
3919 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3920 PFERR_WRITE_MASK,
3921 exception);
3922 unsigned offset = addr & (PAGE_SIZE-1);
3923 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3924 int ret;
3925
3926 if (gpa == UNMAPPED_GVA)
3927 return X86EMUL_PROPAGATE_FAULT;
3928 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3929 if (ret < 0) {
3930 r = X86EMUL_IO_NEEDED;
3931 goto out;
3932 }
3933
3934 bytes -= towrite;
3935 data += towrite;
3936 addr += towrite;
3937 }
3938 out:
3939 return r;
3940 }
3941 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3942
3943 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3944 gpa_t *gpa, struct x86_exception *exception,
3945 bool write)
3946 {
3947 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3948 | (write ? PFERR_WRITE_MASK : 0);
3949
3950 if (vcpu_match_mmio_gva(vcpu, gva)
3951 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
3952 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3953 (gva & (PAGE_SIZE - 1));
3954 trace_vcpu_match_mmio(gva, *gpa, write, false);
3955 return 1;
3956 }
3957
3958 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3959
3960 if (*gpa == UNMAPPED_GVA)
3961 return -1;
3962
3963 /* For APIC access vmexit */
3964 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3965 return 1;
3966
3967 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3968 trace_vcpu_match_mmio(gva, *gpa, write, true);
3969 return 1;
3970 }
3971
3972 return 0;
3973 }
3974
3975 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3976 const void *val, int bytes)
3977 {
3978 int ret;
3979
3980 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3981 if (ret < 0)
3982 return 0;
3983 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3984 return 1;
3985 }
3986
3987 struct read_write_emulator_ops {
3988 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3989 int bytes);
3990 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3991 void *val, int bytes);
3992 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3993 int bytes, void *val);
3994 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3995 void *val, int bytes);
3996 bool write;
3997 };
3998
3999 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4000 {
4001 if (vcpu->mmio_read_completed) {
4002 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4003 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4004 vcpu->mmio_read_completed = 0;
4005 return 1;
4006 }
4007
4008 return 0;
4009 }
4010
4011 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4012 void *val, int bytes)
4013 {
4014 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4015 }
4016
4017 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4018 void *val, int bytes)
4019 {
4020 return emulator_write_phys(vcpu, gpa, val, bytes);
4021 }
4022
4023 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4024 {
4025 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4026 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4027 }
4028
4029 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4030 void *val, int bytes)
4031 {
4032 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4033 return X86EMUL_IO_NEEDED;
4034 }
4035
4036 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4037 void *val, int bytes)
4038 {
4039 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4040
4041 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
4042 return X86EMUL_CONTINUE;
4043 }
4044
4045 static const struct read_write_emulator_ops read_emultor = {
4046 .read_write_prepare = read_prepare,
4047 .read_write_emulate = read_emulate,
4048 .read_write_mmio = vcpu_mmio_read,
4049 .read_write_exit_mmio = read_exit_mmio,
4050 };
4051
4052 static const struct read_write_emulator_ops write_emultor = {
4053 .read_write_emulate = write_emulate,
4054 .read_write_mmio = write_mmio,
4055 .read_write_exit_mmio = write_exit_mmio,
4056 .write = true,
4057 };
4058
4059 static int emulator_read_write_onepage(unsigned long addr, void *val,
4060 unsigned int bytes,
4061 struct x86_exception *exception,
4062 struct kvm_vcpu *vcpu,
4063 const struct read_write_emulator_ops *ops)
4064 {
4065 gpa_t gpa;
4066 int handled, ret;
4067 bool write = ops->write;
4068 struct kvm_mmio_fragment *frag;
4069
4070 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4071
4072 if (ret < 0)
4073 return X86EMUL_PROPAGATE_FAULT;
4074
4075 /* For APIC access vmexit */
4076 if (ret)
4077 goto mmio;
4078
4079 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4080 return X86EMUL_CONTINUE;
4081
4082 mmio:
4083 /*
4084 * Is this MMIO handled locally?
4085 */
4086 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4087 if (handled == bytes)
4088 return X86EMUL_CONTINUE;
4089
4090 gpa += handled;
4091 bytes -= handled;
4092 val += handled;
4093
4094 while (bytes) {
4095 unsigned now = min(bytes, 8U);
4096
4097 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4098 frag->gpa = gpa;
4099 frag->data = val;
4100 frag->len = now;
4101
4102 gpa += now;
4103 val += now;
4104 bytes -= now;
4105 }
4106 return X86EMUL_CONTINUE;
4107 }
4108
4109 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4110 void *val, unsigned int bytes,
4111 struct x86_exception *exception,
4112 const struct read_write_emulator_ops *ops)
4113 {
4114 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4115 gpa_t gpa;
4116 int rc;
4117
4118 if (ops->read_write_prepare &&
4119 ops->read_write_prepare(vcpu, val, bytes))
4120 return X86EMUL_CONTINUE;
4121
4122 vcpu->mmio_nr_fragments = 0;
4123
4124 /* Crossing a page boundary? */
4125 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4126 int now;
4127
4128 now = -addr & ~PAGE_MASK;
4129 rc = emulator_read_write_onepage(addr, val, now, exception,
4130 vcpu, ops);
4131
4132 if (rc != X86EMUL_CONTINUE)
4133 return rc;
4134 addr += now;
4135 val += now;
4136 bytes -= now;
4137 }
4138
4139 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4140 vcpu, ops);
4141 if (rc != X86EMUL_CONTINUE)
4142 return rc;
4143
4144 if (!vcpu->mmio_nr_fragments)
4145 return rc;
4146
4147 gpa = vcpu->mmio_fragments[0].gpa;
4148
4149 vcpu->mmio_needed = 1;
4150 vcpu->mmio_cur_fragment = 0;
4151
4152 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
4153 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4154 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4155 vcpu->run->mmio.phys_addr = gpa;
4156
4157 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4158 }
4159
4160 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4161 unsigned long addr,
4162 void *val,
4163 unsigned int bytes,
4164 struct x86_exception *exception)
4165 {
4166 return emulator_read_write(ctxt, addr, val, bytes,
4167 exception, &read_emultor);
4168 }
4169
4170 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4171 unsigned long addr,
4172 const void *val,
4173 unsigned int bytes,
4174 struct x86_exception *exception)
4175 {
4176 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4177 exception, &write_emultor);
4178 }
4179
4180 #define CMPXCHG_TYPE(t, ptr, old, new) \
4181 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4182
4183 #ifdef CONFIG_X86_64
4184 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4185 #else
4186 # define CMPXCHG64(ptr, old, new) \
4187 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4188 #endif
4189
4190 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4191 unsigned long addr,
4192 const void *old,
4193 const void *new,
4194 unsigned int bytes,
4195 struct x86_exception *exception)
4196 {
4197 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4198 gpa_t gpa;
4199 struct page *page;
4200 char *kaddr;
4201 bool exchanged;
4202
4203 /* guests cmpxchg8b have to be emulated atomically */
4204 if (bytes > 8 || (bytes & (bytes - 1)))
4205 goto emul_write;
4206
4207 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4208
4209 if (gpa == UNMAPPED_GVA ||
4210 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4211 goto emul_write;
4212
4213 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4214 goto emul_write;
4215
4216 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4217 if (is_error_page(page))
4218 goto emul_write;
4219
4220 kaddr = kmap_atomic(page);
4221 kaddr += offset_in_page(gpa);
4222 switch (bytes) {
4223 case 1:
4224 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4225 break;
4226 case 2:
4227 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4228 break;
4229 case 4:
4230 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4231 break;
4232 case 8:
4233 exchanged = CMPXCHG64(kaddr, old, new);
4234 break;
4235 default:
4236 BUG();
4237 }
4238 kunmap_atomic(kaddr);
4239 kvm_release_page_dirty(page);
4240
4241 if (!exchanged)
4242 return X86EMUL_CMPXCHG_FAILED;
4243
4244 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4245
4246 return X86EMUL_CONTINUE;
4247
4248 emul_write:
4249 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4250
4251 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4252 }
4253
4254 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4255 {
4256 /* TODO: String I/O for in kernel device */
4257 int r;
4258
4259 if (vcpu->arch.pio.in)
4260 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4261 vcpu->arch.pio.size, pd);
4262 else
4263 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4264 vcpu->arch.pio.port, vcpu->arch.pio.size,
4265 pd);
4266 return r;
4267 }
4268
4269 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4270 unsigned short port, void *val,
4271 unsigned int count, bool in)
4272 {
4273 trace_kvm_pio(!in, port, size, count);
4274
4275 vcpu->arch.pio.port = port;
4276 vcpu->arch.pio.in = in;
4277 vcpu->arch.pio.count = count;
4278 vcpu->arch.pio.size = size;
4279
4280 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4281 vcpu->arch.pio.count = 0;
4282 return 1;
4283 }
4284
4285 vcpu->run->exit_reason = KVM_EXIT_IO;
4286 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4287 vcpu->run->io.size = size;
4288 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4289 vcpu->run->io.count = count;
4290 vcpu->run->io.port = port;
4291
4292 return 0;
4293 }
4294
4295 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4296 int size, unsigned short port, void *val,
4297 unsigned int count)
4298 {
4299 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4300 int ret;
4301
4302 if (vcpu->arch.pio.count)
4303 goto data_avail;
4304
4305 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4306 if (ret) {
4307 data_avail:
4308 memcpy(val, vcpu->arch.pio_data, size * count);
4309 vcpu->arch.pio.count = 0;
4310 return 1;
4311 }
4312
4313 return 0;
4314 }
4315
4316 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4317 int size, unsigned short port,
4318 const void *val, unsigned int count)
4319 {
4320 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4321
4322 memcpy(vcpu->arch.pio_data, val, size * count);
4323 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4324 }
4325
4326 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4327 {
4328 return kvm_x86_ops->get_segment_base(vcpu, seg);
4329 }
4330
4331 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4332 {
4333 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4334 }
4335
4336 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4337 {
4338 if (!need_emulate_wbinvd(vcpu))
4339 return X86EMUL_CONTINUE;
4340
4341 if (kvm_x86_ops->has_wbinvd_exit()) {
4342 int cpu = get_cpu();
4343
4344 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4345 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4346 wbinvd_ipi, NULL, 1);
4347 put_cpu();
4348 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4349 } else
4350 wbinvd();
4351 return X86EMUL_CONTINUE;
4352 }
4353 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4354
4355 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4356 {
4357 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4358 }
4359
4360 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4361 {
4362 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4363 }
4364
4365 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4366 {
4367
4368 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4369 }
4370
4371 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4372 {
4373 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4374 }
4375
4376 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4377 {
4378 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4379 unsigned long value;
4380
4381 switch (cr) {
4382 case 0:
4383 value = kvm_read_cr0(vcpu);
4384 break;
4385 case 2:
4386 value = vcpu->arch.cr2;
4387 break;
4388 case 3:
4389 value = kvm_read_cr3(vcpu);
4390 break;
4391 case 4:
4392 value = kvm_read_cr4(vcpu);
4393 break;
4394 case 8:
4395 value = kvm_get_cr8(vcpu);
4396 break;
4397 default:
4398 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4399 return 0;
4400 }
4401
4402 return value;
4403 }
4404
4405 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4406 {
4407 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4408 int res = 0;
4409
4410 switch (cr) {
4411 case 0:
4412 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4413 break;
4414 case 2:
4415 vcpu->arch.cr2 = val;
4416 break;
4417 case 3:
4418 res = kvm_set_cr3(vcpu, val);
4419 break;
4420 case 4:
4421 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4422 break;
4423 case 8:
4424 res = kvm_set_cr8(vcpu, val);
4425 break;
4426 default:
4427 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4428 res = -1;
4429 }
4430
4431 return res;
4432 }
4433
4434 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4435 {
4436 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4437 }
4438
4439 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4440 {
4441 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4442 }
4443
4444 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4445 {
4446 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4447 }
4448
4449 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4450 {
4451 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4452 }
4453
4454 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4455 {
4456 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4457 }
4458
4459 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4460 {
4461 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4462 }
4463
4464 static unsigned long emulator_get_cached_segment_base(
4465 struct x86_emulate_ctxt *ctxt, int seg)
4466 {
4467 return get_segment_base(emul_to_vcpu(ctxt), seg);
4468 }
4469
4470 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4471 struct desc_struct *desc, u32 *base3,
4472 int seg)
4473 {
4474 struct kvm_segment var;
4475
4476 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4477 *selector = var.selector;
4478
4479 if (var.unusable)
4480 return false;
4481
4482 if (var.g)
4483 var.limit >>= 12;
4484 set_desc_limit(desc, var.limit);
4485 set_desc_base(desc, (unsigned long)var.base);
4486 #ifdef CONFIG_X86_64
4487 if (base3)
4488 *base3 = var.base >> 32;
4489 #endif
4490 desc->type = var.type;
4491 desc->s = var.s;
4492 desc->dpl = var.dpl;
4493 desc->p = var.present;
4494 desc->avl = var.avl;
4495 desc->l = var.l;
4496 desc->d = var.db;
4497 desc->g = var.g;
4498
4499 return true;
4500 }
4501
4502 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4503 struct desc_struct *desc, u32 base3,
4504 int seg)
4505 {
4506 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4507 struct kvm_segment var;
4508
4509 var.selector = selector;
4510 var.base = get_desc_base(desc);
4511 #ifdef CONFIG_X86_64
4512 var.base |= ((u64)base3) << 32;
4513 #endif
4514 var.limit = get_desc_limit(desc);
4515 if (desc->g)
4516 var.limit = (var.limit << 12) | 0xfff;
4517 var.type = desc->type;
4518 var.present = desc->p;
4519 var.dpl = desc->dpl;
4520 var.db = desc->d;
4521 var.s = desc->s;
4522 var.l = desc->l;
4523 var.g = desc->g;
4524 var.avl = desc->avl;
4525 var.present = desc->p;
4526 var.unusable = !var.present;
4527 var.padding = 0;
4528
4529 kvm_set_segment(vcpu, &var, seg);
4530 return;
4531 }
4532
4533 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4534 u32 msr_index, u64 *pdata)
4535 {
4536 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4537 }
4538
4539 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4540 u32 msr_index, u64 data)
4541 {
4542 struct msr_data msr;
4543
4544 msr.data = data;
4545 msr.index = msr_index;
4546 msr.host_initiated = false;
4547 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4548 }
4549
4550 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4551 u32 pmc, u64 *pdata)
4552 {
4553 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4554 }
4555
4556 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4557 {
4558 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4559 }
4560
4561 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4562 {
4563 preempt_disable();
4564 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4565 /*
4566 * CR0.TS may reference the host fpu state, not the guest fpu state,
4567 * so it may be clear at this point.
4568 */
4569 clts();
4570 }
4571
4572 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4573 {
4574 preempt_enable();
4575 }
4576
4577 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4578 struct x86_instruction_info *info,
4579 enum x86_intercept_stage stage)
4580 {
4581 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4582 }
4583
4584 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4585 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4586 {
4587 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4588 }
4589
4590 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4591 {
4592 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4593 }
4594
4595 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4596 {
4597 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4598 }
4599
4600 static const struct x86_emulate_ops emulate_ops = {
4601 .read_gpr = emulator_read_gpr,
4602 .write_gpr = emulator_write_gpr,
4603 .read_std = kvm_read_guest_virt_system,
4604 .write_std = kvm_write_guest_virt_system,
4605 .fetch = kvm_fetch_guest_virt,
4606 .read_emulated = emulator_read_emulated,
4607 .write_emulated = emulator_write_emulated,
4608 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4609 .invlpg = emulator_invlpg,
4610 .pio_in_emulated = emulator_pio_in_emulated,
4611 .pio_out_emulated = emulator_pio_out_emulated,
4612 .get_segment = emulator_get_segment,
4613 .set_segment = emulator_set_segment,
4614 .get_cached_segment_base = emulator_get_cached_segment_base,
4615 .get_gdt = emulator_get_gdt,
4616 .get_idt = emulator_get_idt,
4617 .set_gdt = emulator_set_gdt,
4618 .set_idt = emulator_set_idt,
4619 .get_cr = emulator_get_cr,
4620 .set_cr = emulator_set_cr,
4621 .set_rflags = emulator_set_rflags,
4622 .cpl = emulator_get_cpl,
4623 .get_dr = emulator_get_dr,
4624 .set_dr = emulator_set_dr,
4625 .set_msr = emulator_set_msr,
4626 .get_msr = emulator_get_msr,
4627 .read_pmc = emulator_read_pmc,
4628 .halt = emulator_halt,
4629 .wbinvd = emulator_wbinvd,
4630 .fix_hypercall = emulator_fix_hypercall,
4631 .get_fpu = emulator_get_fpu,
4632 .put_fpu = emulator_put_fpu,
4633 .intercept = emulator_intercept,
4634 .get_cpuid = emulator_get_cpuid,
4635 };
4636
4637 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4638 {
4639 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4640 /*
4641 * an sti; sti; sequence only disable interrupts for the first
4642 * instruction. So, if the last instruction, be it emulated or
4643 * not, left the system with the INT_STI flag enabled, it
4644 * means that the last instruction is an sti. We should not
4645 * leave the flag on in this case. The same goes for mov ss
4646 */
4647 if (!(int_shadow & mask))
4648 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4649 }
4650
4651 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4652 {
4653 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4654 if (ctxt->exception.vector == PF_VECTOR)
4655 kvm_propagate_fault(vcpu, &ctxt->exception);
4656 else if (ctxt->exception.error_code_valid)
4657 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4658 ctxt->exception.error_code);
4659 else
4660 kvm_queue_exception(vcpu, ctxt->exception.vector);
4661 }
4662
4663 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4664 {
4665 memset(&ctxt->twobyte, 0,
4666 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4667
4668 ctxt->fetch.start = 0;
4669 ctxt->fetch.end = 0;
4670 ctxt->io_read.pos = 0;
4671 ctxt->io_read.end = 0;
4672 ctxt->mem_read.pos = 0;
4673 ctxt->mem_read.end = 0;
4674 }
4675
4676 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4677 {
4678 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4679 int cs_db, cs_l;
4680
4681 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4682
4683 ctxt->eflags = kvm_get_rflags(vcpu);
4684 ctxt->eip = kvm_rip_read(vcpu);
4685 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4686 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4687 cs_l ? X86EMUL_MODE_PROT64 :
4688 cs_db ? X86EMUL_MODE_PROT32 :
4689 X86EMUL_MODE_PROT16;
4690 ctxt->guest_mode = is_guest_mode(vcpu);
4691
4692 init_decode_cache(ctxt);
4693 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4694 }
4695
4696 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4697 {
4698 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4699 int ret;
4700
4701 init_emulate_ctxt(vcpu);
4702
4703 ctxt->op_bytes = 2;
4704 ctxt->ad_bytes = 2;
4705 ctxt->_eip = ctxt->eip + inc_eip;
4706 ret = emulate_int_real(ctxt, irq);
4707
4708 if (ret != X86EMUL_CONTINUE)
4709 return EMULATE_FAIL;
4710
4711 ctxt->eip = ctxt->_eip;
4712 kvm_rip_write(vcpu, ctxt->eip);
4713 kvm_set_rflags(vcpu, ctxt->eflags);
4714
4715 if (irq == NMI_VECTOR)
4716 vcpu->arch.nmi_pending = 0;
4717 else
4718 vcpu->arch.interrupt.pending = false;
4719
4720 return EMULATE_DONE;
4721 }
4722 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4723
4724 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4725 {
4726 int r = EMULATE_DONE;
4727
4728 ++vcpu->stat.insn_emulation_fail;
4729 trace_kvm_emulate_insn_failed(vcpu);
4730 if (!is_guest_mode(vcpu)) {
4731 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4732 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4733 vcpu->run->internal.ndata = 0;
4734 r = EMULATE_FAIL;
4735 }
4736 kvm_queue_exception(vcpu, UD_VECTOR);
4737
4738 return r;
4739 }
4740
4741 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4742 {
4743 gpa_t gpa;
4744 pfn_t pfn;
4745
4746 if (tdp_enabled)
4747 return false;
4748
4749 /*
4750 * if emulation was due to access to shadowed page table
4751 * and it failed try to unshadow page and re-enter the
4752 * guest to let CPU execute the instruction.
4753 */
4754 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4755 return true;
4756
4757 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4758
4759 if (gpa == UNMAPPED_GVA)
4760 return true; /* let cpu generate fault */
4761
4762 /*
4763 * Do not retry the unhandleable instruction if it faults on the
4764 * readonly host memory, otherwise it will goto a infinite loop:
4765 * retry instruction -> write #PF -> emulation fail -> retry
4766 * instruction -> ...
4767 */
4768 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4769 if (!is_error_noslot_pfn(pfn)) {
4770 kvm_release_pfn_clean(pfn);
4771 return true;
4772 }
4773
4774 return false;
4775 }
4776
4777 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4778 unsigned long cr2, int emulation_type)
4779 {
4780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4781 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4782
4783 last_retry_eip = vcpu->arch.last_retry_eip;
4784 last_retry_addr = vcpu->arch.last_retry_addr;
4785
4786 /*
4787 * If the emulation is caused by #PF and it is non-page_table
4788 * writing instruction, it means the VM-EXIT is caused by shadow
4789 * page protected, we can zap the shadow page and retry this
4790 * instruction directly.
4791 *
4792 * Note: if the guest uses a non-page-table modifying instruction
4793 * on the PDE that points to the instruction, then we will unmap
4794 * the instruction and go to an infinite loop. So, we cache the
4795 * last retried eip and the last fault address, if we meet the eip
4796 * and the address again, we can break out of the potential infinite
4797 * loop.
4798 */
4799 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4800
4801 if (!(emulation_type & EMULTYPE_RETRY))
4802 return false;
4803
4804 if (x86_page_table_writing_insn(ctxt))
4805 return false;
4806
4807 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4808 return false;
4809
4810 vcpu->arch.last_retry_eip = ctxt->eip;
4811 vcpu->arch.last_retry_addr = cr2;
4812
4813 if (!vcpu->arch.mmu.direct_map)
4814 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4815
4816 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4817
4818 return true;
4819 }
4820
4821 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4822 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4823
4824 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4825 unsigned long cr2,
4826 int emulation_type,
4827 void *insn,
4828 int insn_len)
4829 {
4830 int r;
4831 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4832 bool writeback = true;
4833
4834 kvm_clear_exception_queue(vcpu);
4835
4836 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4837 init_emulate_ctxt(vcpu);
4838 ctxt->interruptibility = 0;
4839 ctxt->have_exception = false;
4840 ctxt->perm_ok = false;
4841
4842 ctxt->only_vendor_specific_insn
4843 = emulation_type & EMULTYPE_TRAP_UD;
4844
4845 r = x86_decode_insn(ctxt, insn, insn_len);
4846
4847 trace_kvm_emulate_insn_start(vcpu);
4848 ++vcpu->stat.insn_emulation;
4849 if (r != EMULATION_OK) {
4850 if (emulation_type & EMULTYPE_TRAP_UD)
4851 return EMULATE_FAIL;
4852 if (reexecute_instruction(vcpu, cr2))
4853 return EMULATE_DONE;
4854 if (emulation_type & EMULTYPE_SKIP)
4855 return EMULATE_FAIL;
4856 return handle_emulation_failure(vcpu);
4857 }
4858 }
4859
4860 if (emulation_type & EMULTYPE_SKIP) {
4861 kvm_rip_write(vcpu, ctxt->_eip);
4862 return EMULATE_DONE;
4863 }
4864
4865 if (retry_instruction(ctxt, cr2, emulation_type))
4866 return EMULATE_DONE;
4867
4868 /* this is needed for vmware backdoor interface to work since it
4869 changes registers values during IO operation */
4870 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4871 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4872 emulator_invalidate_register_cache(ctxt);
4873 }
4874
4875 restart:
4876 r = x86_emulate_insn(ctxt);
4877
4878 if (r == EMULATION_INTERCEPTED)
4879 return EMULATE_DONE;
4880
4881 if (r == EMULATION_FAILED) {
4882 if (reexecute_instruction(vcpu, cr2))
4883 return EMULATE_DONE;
4884
4885 return handle_emulation_failure(vcpu);
4886 }
4887
4888 if (ctxt->have_exception) {
4889 inject_emulated_exception(vcpu);
4890 r = EMULATE_DONE;
4891 } else if (vcpu->arch.pio.count) {
4892 if (!vcpu->arch.pio.in)
4893 vcpu->arch.pio.count = 0;
4894 else {
4895 writeback = false;
4896 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4897 }
4898 r = EMULATE_DO_MMIO;
4899 } else if (vcpu->mmio_needed) {
4900 if (!vcpu->mmio_is_write)
4901 writeback = false;
4902 r = EMULATE_DO_MMIO;
4903 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
4904 } else if (r == EMULATION_RESTART)
4905 goto restart;
4906 else
4907 r = EMULATE_DONE;
4908
4909 if (writeback) {
4910 toggle_interruptibility(vcpu, ctxt->interruptibility);
4911 kvm_set_rflags(vcpu, ctxt->eflags);
4912 kvm_make_request(KVM_REQ_EVENT, vcpu);
4913 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4914 kvm_rip_write(vcpu, ctxt->eip);
4915 } else
4916 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4917
4918 return r;
4919 }
4920 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4921
4922 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4923 {
4924 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4925 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4926 size, port, &val, 1);
4927 /* do not return to emulator after return from userspace */
4928 vcpu->arch.pio.count = 0;
4929 return ret;
4930 }
4931 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4932
4933 static void tsc_bad(void *info)
4934 {
4935 __this_cpu_write(cpu_tsc_khz, 0);
4936 }
4937
4938 static void tsc_khz_changed(void *data)
4939 {
4940 struct cpufreq_freqs *freq = data;
4941 unsigned long khz = 0;
4942
4943 if (data)
4944 khz = freq->new;
4945 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4946 khz = cpufreq_quick_get(raw_smp_processor_id());
4947 if (!khz)
4948 khz = tsc_khz;
4949 __this_cpu_write(cpu_tsc_khz, khz);
4950 }
4951
4952 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4953 void *data)
4954 {
4955 struct cpufreq_freqs *freq = data;
4956 struct kvm *kvm;
4957 struct kvm_vcpu *vcpu;
4958 int i, send_ipi = 0;
4959
4960 /*
4961 * We allow guests to temporarily run on slowing clocks,
4962 * provided we notify them after, or to run on accelerating
4963 * clocks, provided we notify them before. Thus time never
4964 * goes backwards.
4965 *
4966 * However, we have a problem. We can't atomically update
4967 * the frequency of a given CPU from this function; it is
4968 * merely a notifier, which can be called from any CPU.
4969 * Changing the TSC frequency at arbitrary points in time
4970 * requires a recomputation of local variables related to
4971 * the TSC for each VCPU. We must flag these local variables
4972 * to be updated and be sure the update takes place with the
4973 * new frequency before any guests proceed.
4974 *
4975 * Unfortunately, the combination of hotplug CPU and frequency
4976 * change creates an intractable locking scenario; the order
4977 * of when these callouts happen is undefined with respect to
4978 * CPU hotplug, and they can race with each other. As such,
4979 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4980 * undefined; you can actually have a CPU frequency change take
4981 * place in between the computation of X and the setting of the
4982 * variable. To protect against this problem, all updates of
4983 * the per_cpu tsc_khz variable are done in an interrupt
4984 * protected IPI, and all callers wishing to update the value
4985 * must wait for a synchronous IPI to complete (which is trivial
4986 * if the caller is on the CPU already). This establishes the
4987 * necessary total order on variable updates.
4988 *
4989 * Note that because a guest time update may take place
4990 * anytime after the setting of the VCPU's request bit, the
4991 * correct TSC value must be set before the request. However,
4992 * to ensure the update actually makes it to any guest which
4993 * starts running in hardware virtualization between the set
4994 * and the acquisition of the spinlock, we must also ping the
4995 * CPU after setting the request bit.
4996 *
4997 */
4998
4999 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5000 return 0;
5001 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5002 return 0;
5003
5004 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5005
5006 raw_spin_lock(&kvm_lock);
5007 list_for_each_entry(kvm, &vm_list, vm_list) {
5008 kvm_for_each_vcpu(i, vcpu, kvm) {
5009 if (vcpu->cpu != freq->cpu)
5010 continue;
5011 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5012 if (vcpu->cpu != smp_processor_id())
5013 send_ipi = 1;
5014 }
5015 }
5016 raw_spin_unlock(&kvm_lock);
5017
5018 if (freq->old < freq->new && send_ipi) {
5019 /*
5020 * We upscale the frequency. Must make the guest
5021 * doesn't see old kvmclock values while running with
5022 * the new frequency, otherwise we risk the guest sees
5023 * time go backwards.
5024 *
5025 * In case we update the frequency for another cpu
5026 * (which might be in guest context) send an interrupt
5027 * to kick the cpu out of guest context. Next time
5028 * guest context is entered kvmclock will be updated,
5029 * so the guest will not see stale values.
5030 */
5031 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5032 }
5033 return 0;
5034 }
5035
5036 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5037 .notifier_call = kvmclock_cpufreq_notifier
5038 };
5039
5040 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5041 unsigned long action, void *hcpu)
5042 {
5043 unsigned int cpu = (unsigned long)hcpu;
5044
5045 switch (action) {
5046 case CPU_ONLINE:
5047 case CPU_DOWN_FAILED:
5048 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5049 break;
5050 case CPU_DOWN_PREPARE:
5051 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5052 break;
5053 }
5054 return NOTIFY_OK;
5055 }
5056
5057 static struct notifier_block kvmclock_cpu_notifier_block = {
5058 .notifier_call = kvmclock_cpu_notifier,
5059 .priority = -INT_MAX
5060 };
5061
5062 static void kvm_timer_init(void)
5063 {
5064 int cpu;
5065
5066 max_tsc_khz = tsc_khz;
5067 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5068 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5069 #ifdef CONFIG_CPU_FREQ
5070 struct cpufreq_policy policy;
5071 memset(&policy, 0, sizeof(policy));
5072 cpu = get_cpu();
5073 cpufreq_get_policy(&policy, cpu);
5074 if (policy.cpuinfo.max_freq)
5075 max_tsc_khz = policy.cpuinfo.max_freq;
5076 put_cpu();
5077 #endif
5078 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5079 CPUFREQ_TRANSITION_NOTIFIER);
5080 }
5081 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5082 for_each_online_cpu(cpu)
5083 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5084 }
5085
5086 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5087
5088 int kvm_is_in_guest(void)
5089 {
5090 return __this_cpu_read(current_vcpu) != NULL;
5091 }
5092
5093 static int kvm_is_user_mode(void)
5094 {
5095 int user_mode = 3;
5096
5097 if (__this_cpu_read(current_vcpu))
5098 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5099
5100 return user_mode != 0;
5101 }
5102
5103 static unsigned long kvm_get_guest_ip(void)
5104 {
5105 unsigned long ip = 0;
5106
5107 if (__this_cpu_read(current_vcpu))
5108 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5109
5110 return ip;
5111 }
5112
5113 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5114 .is_in_guest = kvm_is_in_guest,
5115 .is_user_mode = kvm_is_user_mode,
5116 .get_guest_ip = kvm_get_guest_ip,
5117 };
5118
5119 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5120 {
5121 __this_cpu_write(current_vcpu, vcpu);
5122 }
5123 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5124
5125 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5126 {
5127 __this_cpu_write(current_vcpu, NULL);
5128 }
5129 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5130
5131 static void kvm_set_mmio_spte_mask(void)
5132 {
5133 u64 mask;
5134 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5135
5136 /*
5137 * Set the reserved bits and the present bit of an paging-structure
5138 * entry to generate page fault with PFER.RSV = 1.
5139 */
5140 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5141 mask |= 1ull;
5142
5143 #ifdef CONFIG_X86_64
5144 /*
5145 * If reserved bit is not supported, clear the present bit to disable
5146 * mmio page fault.
5147 */
5148 if (maxphyaddr == 52)
5149 mask &= ~1ull;
5150 #endif
5151
5152 kvm_mmu_set_mmio_spte_mask(mask);
5153 }
5154
5155 #ifdef CONFIG_X86_64
5156 static void pvclock_gtod_update_fn(struct work_struct *work)
5157 {
5158 struct kvm *kvm;
5159
5160 struct kvm_vcpu *vcpu;
5161 int i;
5162
5163 raw_spin_lock(&kvm_lock);
5164 list_for_each_entry(kvm, &vm_list, vm_list)
5165 kvm_for_each_vcpu(i, vcpu, kvm)
5166 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5167 atomic_set(&kvm_guest_has_master_clock, 0);
5168 raw_spin_unlock(&kvm_lock);
5169 }
5170
5171 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5172
5173 /*
5174 * Notification about pvclock gtod data update.
5175 */
5176 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5177 void *priv)
5178 {
5179 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5180 struct timekeeper *tk = priv;
5181
5182 update_pvclock_gtod(tk);
5183
5184 /* disable master clock if host does not trust, or does not
5185 * use, TSC clocksource
5186 */
5187 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5188 atomic_read(&kvm_guest_has_master_clock) != 0)
5189 queue_work(system_long_wq, &pvclock_gtod_work);
5190
5191 return 0;
5192 }
5193
5194 static struct notifier_block pvclock_gtod_notifier = {
5195 .notifier_call = pvclock_gtod_notify,
5196 };
5197 #endif
5198
5199 int kvm_arch_init(void *opaque)
5200 {
5201 int r;
5202 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5203
5204 if (kvm_x86_ops) {
5205 printk(KERN_ERR "kvm: already loaded the other module\n");
5206 r = -EEXIST;
5207 goto out;
5208 }
5209
5210 if (!ops->cpu_has_kvm_support()) {
5211 printk(KERN_ERR "kvm: no hardware support\n");
5212 r = -EOPNOTSUPP;
5213 goto out;
5214 }
5215 if (ops->disabled_by_bios()) {
5216 printk(KERN_ERR "kvm: disabled by bios\n");
5217 r = -EOPNOTSUPP;
5218 goto out;
5219 }
5220
5221 r = kvm_mmu_module_init();
5222 if (r)
5223 goto out;
5224
5225 kvm_set_mmio_spte_mask();
5226 kvm_init_msr_list();
5227
5228 kvm_x86_ops = ops;
5229 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5230 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5231
5232 kvm_timer_init();
5233
5234 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5235
5236 if (cpu_has_xsave)
5237 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5238
5239 kvm_lapic_init();
5240 #ifdef CONFIG_X86_64
5241 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5242 #endif
5243
5244 return 0;
5245
5246 out:
5247 return r;
5248 }
5249
5250 void kvm_arch_exit(void)
5251 {
5252 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5253
5254 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5255 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5256 CPUFREQ_TRANSITION_NOTIFIER);
5257 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5258 #ifdef CONFIG_X86_64
5259 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5260 #endif
5261 kvm_x86_ops = NULL;
5262 kvm_mmu_module_exit();
5263 }
5264
5265 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5266 {
5267 ++vcpu->stat.halt_exits;
5268 if (irqchip_in_kernel(vcpu->kvm)) {
5269 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5270 return 1;
5271 } else {
5272 vcpu->run->exit_reason = KVM_EXIT_HLT;
5273 return 0;
5274 }
5275 }
5276 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5277
5278 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5279 {
5280 u64 param, ingpa, outgpa, ret;
5281 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5282 bool fast, longmode;
5283 int cs_db, cs_l;
5284
5285 /*
5286 * hypercall generates UD from non zero cpl and real mode
5287 * per HYPER-V spec
5288 */
5289 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5290 kvm_queue_exception(vcpu, UD_VECTOR);
5291 return 0;
5292 }
5293
5294 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5295 longmode = is_long_mode(vcpu) && cs_l == 1;
5296
5297 if (!longmode) {
5298 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5299 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5300 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5301 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5302 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5303 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5304 }
5305 #ifdef CONFIG_X86_64
5306 else {
5307 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5308 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5309 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5310 }
5311 #endif
5312
5313 code = param & 0xffff;
5314 fast = (param >> 16) & 0x1;
5315 rep_cnt = (param >> 32) & 0xfff;
5316 rep_idx = (param >> 48) & 0xfff;
5317
5318 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5319
5320 switch (code) {
5321 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5322 kvm_vcpu_on_spin(vcpu);
5323 break;
5324 default:
5325 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5326 break;
5327 }
5328
5329 ret = res | (((u64)rep_done & 0xfff) << 32);
5330 if (longmode) {
5331 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5332 } else {
5333 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5334 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5335 }
5336
5337 return 1;
5338 }
5339
5340 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5341 {
5342 unsigned long nr, a0, a1, a2, a3, ret;
5343 int r = 1;
5344
5345 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5346 return kvm_hv_hypercall(vcpu);
5347
5348 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5349 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5350 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5351 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5352 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5353
5354 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5355
5356 if (!is_long_mode(vcpu)) {
5357 nr &= 0xFFFFFFFF;
5358 a0 &= 0xFFFFFFFF;
5359 a1 &= 0xFFFFFFFF;
5360 a2 &= 0xFFFFFFFF;
5361 a3 &= 0xFFFFFFFF;
5362 }
5363
5364 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5365 ret = -KVM_EPERM;
5366 goto out;
5367 }
5368
5369 switch (nr) {
5370 case KVM_HC_VAPIC_POLL_IRQ:
5371 ret = 0;
5372 break;
5373 default:
5374 ret = -KVM_ENOSYS;
5375 break;
5376 }
5377 out:
5378 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5379 ++vcpu->stat.hypercalls;
5380 return r;
5381 }
5382 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5383
5384 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5385 {
5386 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5387 char instruction[3];
5388 unsigned long rip = kvm_rip_read(vcpu);
5389
5390 /*
5391 * Blow out the MMU to ensure that no other VCPU has an active mapping
5392 * to ensure that the updated hypercall appears atomically across all
5393 * VCPUs.
5394 */
5395 kvm_mmu_zap_all(vcpu->kvm);
5396
5397 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5398
5399 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5400 }
5401
5402 /*
5403 * Check if userspace requested an interrupt window, and that the
5404 * interrupt window is open.
5405 *
5406 * No need to exit to userspace if we already have an interrupt queued.
5407 */
5408 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5409 {
5410 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5411 vcpu->run->request_interrupt_window &&
5412 kvm_arch_interrupt_allowed(vcpu));
5413 }
5414
5415 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5416 {
5417 struct kvm_run *kvm_run = vcpu->run;
5418
5419 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5420 kvm_run->cr8 = kvm_get_cr8(vcpu);
5421 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5422 if (irqchip_in_kernel(vcpu->kvm))
5423 kvm_run->ready_for_interrupt_injection = 1;
5424 else
5425 kvm_run->ready_for_interrupt_injection =
5426 kvm_arch_interrupt_allowed(vcpu) &&
5427 !kvm_cpu_has_interrupt(vcpu) &&
5428 !kvm_event_needs_reinjection(vcpu);
5429 }
5430
5431 static int vapic_enter(struct kvm_vcpu *vcpu)
5432 {
5433 struct kvm_lapic *apic = vcpu->arch.apic;
5434 struct page *page;
5435
5436 if (!apic || !apic->vapic_addr)
5437 return 0;
5438
5439 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5440 if (is_error_page(page))
5441 return -EFAULT;
5442
5443 vcpu->arch.apic->vapic_page = page;
5444 return 0;
5445 }
5446
5447 static void vapic_exit(struct kvm_vcpu *vcpu)
5448 {
5449 struct kvm_lapic *apic = vcpu->arch.apic;
5450 int idx;
5451
5452 if (!apic || !apic->vapic_addr)
5453 return;
5454
5455 idx = srcu_read_lock(&vcpu->kvm->srcu);
5456 kvm_release_page_dirty(apic->vapic_page);
5457 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5458 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5459 }
5460
5461 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5462 {
5463 int max_irr, tpr;
5464
5465 if (!kvm_x86_ops->update_cr8_intercept)
5466 return;
5467
5468 if (!vcpu->arch.apic)
5469 return;
5470
5471 if (!vcpu->arch.apic->vapic_addr)
5472 max_irr = kvm_lapic_find_highest_irr(vcpu);
5473 else
5474 max_irr = -1;
5475
5476 if (max_irr != -1)
5477 max_irr >>= 4;
5478
5479 tpr = kvm_lapic_get_cr8(vcpu);
5480
5481 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5482 }
5483
5484 static void inject_pending_event(struct kvm_vcpu *vcpu)
5485 {
5486 /* try to reinject previous events if any */
5487 if (vcpu->arch.exception.pending) {
5488 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5489 vcpu->arch.exception.has_error_code,
5490 vcpu->arch.exception.error_code);
5491 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5492 vcpu->arch.exception.has_error_code,
5493 vcpu->arch.exception.error_code,
5494 vcpu->arch.exception.reinject);
5495 return;
5496 }
5497
5498 if (vcpu->arch.nmi_injected) {
5499 kvm_x86_ops->set_nmi(vcpu);
5500 return;
5501 }
5502
5503 if (vcpu->arch.interrupt.pending) {
5504 kvm_x86_ops->set_irq(vcpu);
5505 return;
5506 }
5507
5508 /* try to inject new event if pending */
5509 if (vcpu->arch.nmi_pending) {
5510 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5511 --vcpu->arch.nmi_pending;
5512 vcpu->arch.nmi_injected = true;
5513 kvm_x86_ops->set_nmi(vcpu);
5514 }
5515 } else if (kvm_cpu_has_interrupt(vcpu)) {
5516 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5517 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5518 false);
5519 kvm_x86_ops->set_irq(vcpu);
5520 }
5521 }
5522 }
5523
5524 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5525 {
5526 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5527 !vcpu->guest_xcr0_loaded) {
5528 /* kvm_set_xcr() also depends on this */
5529 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5530 vcpu->guest_xcr0_loaded = 1;
5531 }
5532 }
5533
5534 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5535 {
5536 if (vcpu->guest_xcr0_loaded) {
5537 if (vcpu->arch.xcr0 != host_xcr0)
5538 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5539 vcpu->guest_xcr0_loaded = 0;
5540 }
5541 }
5542
5543 static void process_nmi(struct kvm_vcpu *vcpu)
5544 {
5545 unsigned limit = 2;
5546
5547 /*
5548 * x86 is limited to one NMI running, and one NMI pending after it.
5549 * If an NMI is already in progress, limit further NMIs to just one.
5550 * Otherwise, allow two (and we'll inject the first one immediately).
5551 */
5552 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5553 limit = 1;
5554
5555 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5556 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5557 kvm_make_request(KVM_REQ_EVENT, vcpu);
5558 }
5559
5560 static void kvm_gen_update_masterclock(struct kvm *kvm)
5561 {
5562 #ifdef CONFIG_X86_64
5563 int i;
5564 struct kvm_vcpu *vcpu;
5565 struct kvm_arch *ka = &kvm->arch;
5566
5567 spin_lock(&ka->pvclock_gtod_sync_lock);
5568 kvm_make_mclock_inprogress_request(kvm);
5569 /* no guest entries from this point */
5570 pvclock_update_vm_gtod_copy(kvm);
5571
5572 kvm_for_each_vcpu(i, vcpu, kvm)
5573 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5574
5575 /* guest entries allowed */
5576 kvm_for_each_vcpu(i, vcpu, kvm)
5577 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5578
5579 spin_unlock(&ka->pvclock_gtod_sync_lock);
5580 #endif
5581 }
5582
5583 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5584 {
5585 int r;
5586 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5587 vcpu->run->request_interrupt_window;
5588 bool req_immediate_exit = 0;
5589
5590 if (vcpu->requests) {
5591 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5592 kvm_mmu_unload(vcpu);
5593 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5594 __kvm_migrate_timers(vcpu);
5595 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5596 kvm_gen_update_masterclock(vcpu->kvm);
5597 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5598 r = kvm_guest_time_update(vcpu);
5599 if (unlikely(r))
5600 goto out;
5601 }
5602 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5603 kvm_mmu_sync_roots(vcpu);
5604 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5605 kvm_x86_ops->tlb_flush(vcpu);
5606 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5607 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5608 r = 0;
5609 goto out;
5610 }
5611 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5612 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5613 r = 0;
5614 goto out;
5615 }
5616 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5617 vcpu->fpu_active = 0;
5618 kvm_x86_ops->fpu_deactivate(vcpu);
5619 }
5620 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5621 /* Page is swapped out. Do synthetic halt */
5622 vcpu->arch.apf.halted = true;
5623 r = 1;
5624 goto out;
5625 }
5626 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5627 record_steal_time(vcpu);
5628 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5629 process_nmi(vcpu);
5630 req_immediate_exit =
5631 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5632 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5633 kvm_handle_pmu_event(vcpu);
5634 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5635 kvm_deliver_pmi(vcpu);
5636 }
5637
5638 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5639 inject_pending_event(vcpu);
5640
5641 /* enable NMI/IRQ window open exits if needed */
5642 if (vcpu->arch.nmi_pending)
5643 kvm_x86_ops->enable_nmi_window(vcpu);
5644 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5645 kvm_x86_ops->enable_irq_window(vcpu);
5646
5647 if (kvm_lapic_enabled(vcpu)) {
5648 update_cr8_intercept(vcpu);
5649 kvm_lapic_sync_to_vapic(vcpu);
5650 }
5651 }
5652
5653 r = kvm_mmu_reload(vcpu);
5654 if (unlikely(r)) {
5655 goto cancel_injection;
5656 }
5657
5658 preempt_disable();
5659
5660 kvm_x86_ops->prepare_guest_switch(vcpu);
5661 if (vcpu->fpu_active)
5662 kvm_load_guest_fpu(vcpu);
5663 kvm_load_guest_xcr0(vcpu);
5664
5665 vcpu->mode = IN_GUEST_MODE;
5666
5667 /* We should set ->mode before check ->requests,
5668 * see the comment in make_all_cpus_request.
5669 */
5670 smp_mb();
5671
5672 local_irq_disable();
5673
5674 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5675 || need_resched() || signal_pending(current)) {
5676 vcpu->mode = OUTSIDE_GUEST_MODE;
5677 smp_wmb();
5678 local_irq_enable();
5679 preempt_enable();
5680 r = 1;
5681 goto cancel_injection;
5682 }
5683
5684 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5685
5686 if (req_immediate_exit)
5687 smp_send_reschedule(vcpu->cpu);
5688
5689 kvm_guest_enter();
5690
5691 if (unlikely(vcpu->arch.switch_db_regs)) {
5692 set_debugreg(0, 7);
5693 set_debugreg(vcpu->arch.eff_db[0], 0);
5694 set_debugreg(vcpu->arch.eff_db[1], 1);
5695 set_debugreg(vcpu->arch.eff_db[2], 2);
5696 set_debugreg(vcpu->arch.eff_db[3], 3);
5697 }
5698
5699 trace_kvm_entry(vcpu->vcpu_id);
5700 kvm_x86_ops->run(vcpu);
5701
5702 /*
5703 * If the guest has used debug registers, at least dr7
5704 * will be disabled while returning to the host.
5705 * If we don't have active breakpoints in the host, we don't
5706 * care about the messed up debug address registers. But if
5707 * we have some of them active, restore the old state.
5708 */
5709 if (hw_breakpoint_active())
5710 hw_breakpoint_restore();
5711
5712 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5713 native_read_tsc());
5714
5715 vcpu->mode = OUTSIDE_GUEST_MODE;
5716 smp_wmb();
5717 local_irq_enable();
5718
5719 ++vcpu->stat.exits;
5720
5721 /*
5722 * We must have an instruction between local_irq_enable() and
5723 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5724 * the interrupt shadow. The stat.exits increment will do nicely.
5725 * But we need to prevent reordering, hence this barrier():
5726 */
5727 barrier();
5728
5729 kvm_guest_exit();
5730
5731 preempt_enable();
5732
5733 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5734
5735 /*
5736 * Profile KVM exit RIPs:
5737 */
5738 if (unlikely(prof_on == KVM_PROFILING)) {
5739 unsigned long rip = kvm_rip_read(vcpu);
5740 profile_hit(KVM_PROFILING, (void *)rip);
5741 }
5742
5743 if (unlikely(vcpu->arch.tsc_always_catchup))
5744 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5745
5746 if (vcpu->arch.apic_attention)
5747 kvm_lapic_sync_from_vapic(vcpu);
5748
5749 r = kvm_x86_ops->handle_exit(vcpu);
5750 return r;
5751
5752 cancel_injection:
5753 kvm_x86_ops->cancel_injection(vcpu);
5754 if (unlikely(vcpu->arch.apic_attention))
5755 kvm_lapic_sync_from_vapic(vcpu);
5756 out:
5757 return r;
5758 }
5759
5760
5761 static int __vcpu_run(struct kvm_vcpu *vcpu)
5762 {
5763 int r;
5764 struct kvm *kvm = vcpu->kvm;
5765
5766 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5767 pr_debug("vcpu %d received sipi with vector # %x\n",
5768 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5769 kvm_lapic_reset(vcpu);
5770 r = kvm_vcpu_reset(vcpu);
5771 if (r)
5772 return r;
5773 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5774 }
5775
5776 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5777 r = vapic_enter(vcpu);
5778 if (r) {
5779 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5780 return r;
5781 }
5782
5783 r = 1;
5784 while (r > 0) {
5785 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5786 !vcpu->arch.apf.halted)
5787 r = vcpu_enter_guest(vcpu);
5788 else {
5789 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5790 kvm_vcpu_block(vcpu);
5791 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5792 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5793 {
5794 switch(vcpu->arch.mp_state) {
5795 case KVM_MP_STATE_HALTED:
5796 vcpu->arch.mp_state =
5797 KVM_MP_STATE_RUNNABLE;
5798 case KVM_MP_STATE_RUNNABLE:
5799 vcpu->arch.apf.halted = false;
5800 break;
5801 case KVM_MP_STATE_SIPI_RECEIVED:
5802 default:
5803 r = -EINTR;
5804 break;
5805 }
5806 }
5807 }
5808
5809 if (r <= 0)
5810 break;
5811
5812 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5813 if (kvm_cpu_has_pending_timer(vcpu))
5814 kvm_inject_pending_timer_irqs(vcpu);
5815
5816 if (dm_request_for_irq_injection(vcpu)) {
5817 r = -EINTR;
5818 vcpu->run->exit_reason = KVM_EXIT_INTR;
5819 ++vcpu->stat.request_irq_exits;
5820 }
5821
5822 kvm_check_async_pf_completion(vcpu);
5823
5824 if (signal_pending(current)) {
5825 r = -EINTR;
5826 vcpu->run->exit_reason = KVM_EXIT_INTR;
5827 ++vcpu->stat.signal_exits;
5828 }
5829 if (need_resched()) {
5830 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5831 kvm_resched(vcpu);
5832 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5833 }
5834 }
5835
5836 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5837
5838 vapic_exit(vcpu);
5839
5840 return r;
5841 }
5842
5843 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5844 {
5845 int r;
5846 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5847 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5848 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5849 if (r != EMULATE_DONE)
5850 return 0;
5851 return 1;
5852 }
5853
5854 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5855 {
5856 BUG_ON(!vcpu->arch.pio.count);
5857
5858 return complete_emulated_io(vcpu);
5859 }
5860
5861 /*
5862 * Implements the following, as a state machine:
5863 *
5864 * read:
5865 * for each fragment
5866 * write gpa, len
5867 * exit
5868 * copy data
5869 * execute insn
5870 *
5871 * write:
5872 * for each fragment
5873 * write gpa, len
5874 * copy data
5875 * exit
5876 */
5877 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5878 {
5879 struct kvm_run *run = vcpu->run;
5880 struct kvm_mmio_fragment *frag;
5881
5882 BUG_ON(!vcpu->mmio_needed);
5883
5884 /* Complete previous fragment */
5885 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5886 if (!vcpu->mmio_is_write)
5887 memcpy(frag->data, run->mmio.data, frag->len);
5888 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5889 vcpu->mmio_needed = 0;
5890 if (vcpu->mmio_is_write)
5891 return 1;
5892 vcpu->mmio_read_completed = 1;
5893 return complete_emulated_io(vcpu);
5894 }
5895 /* Initiate next fragment */
5896 ++frag;
5897 run->exit_reason = KVM_EXIT_MMIO;
5898 run->mmio.phys_addr = frag->gpa;
5899 if (vcpu->mmio_is_write)
5900 memcpy(run->mmio.data, frag->data, frag->len);
5901 run->mmio.len = frag->len;
5902 run->mmio.is_write = vcpu->mmio_is_write;
5903 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5904 return 0;
5905 }
5906
5907
5908 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5909 {
5910 int r;
5911 sigset_t sigsaved;
5912
5913 if (!tsk_used_math(current) && init_fpu(current))
5914 return -ENOMEM;
5915
5916 if (vcpu->sigset_active)
5917 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5918
5919 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5920 kvm_vcpu_block(vcpu);
5921 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5922 r = -EAGAIN;
5923 goto out;
5924 }
5925
5926 /* re-sync apic's tpr */
5927 if (!irqchip_in_kernel(vcpu->kvm)) {
5928 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5929 r = -EINVAL;
5930 goto out;
5931 }
5932 }
5933
5934 if (unlikely(vcpu->arch.complete_userspace_io)) {
5935 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
5936 vcpu->arch.complete_userspace_io = NULL;
5937 r = cui(vcpu);
5938 if (r <= 0)
5939 goto out;
5940 } else
5941 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5942
5943 r = __vcpu_run(vcpu);
5944
5945 out:
5946 post_kvm_run_save(vcpu);
5947 if (vcpu->sigset_active)
5948 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5949
5950 return r;
5951 }
5952
5953 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5954 {
5955 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5956 /*
5957 * We are here if userspace calls get_regs() in the middle of
5958 * instruction emulation. Registers state needs to be copied
5959 * back from emulation context to vcpu. Userspace shouldn't do
5960 * that usually, but some bad designed PV devices (vmware
5961 * backdoor interface) need this to work
5962 */
5963 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
5964 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5965 }
5966 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5967 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5968 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5969 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5970 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5971 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5972 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5973 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5974 #ifdef CONFIG_X86_64
5975 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5976 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5977 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5978 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5979 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5980 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5981 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5982 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5983 #endif
5984
5985 regs->rip = kvm_rip_read(vcpu);
5986 regs->rflags = kvm_get_rflags(vcpu);
5987
5988 return 0;
5989 }
5990
5991 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5992 {
5993 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5994 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5995
5996 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5997 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5998 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5999 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6000 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6001 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6002 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6003 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6004 #ifdef CONFIG_X86_64
6005 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6006 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6007 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6008 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6009 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6010 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6011 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6012 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6013 #endif
6014
6015 kvm_rip_write(vcpu, regs->rip);
6016 kvm_set_rflags(vcpu, regs->rflags);
6017
6018 vcpu->arch.exception.pending = false;
6019
6020 kvm_make_request(KVM_REQ_EVENT, vcpu);
6021
6022 return 0;
6023 }
6024
6025 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6026 {
6027 struct kvm_segment cs;
6028
6029 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6030 *db = cs.db;
6031 *l = cs.l;
6032 }
6033 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6034
6035 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6036 struct kvm_sregs *sregs)
6037 {
6038 struct desc_ptr dt;
6039
6040 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6041 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6042 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6043 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6044 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6045 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6046
6047 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6048 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6049
6050 kvm_x86_ops->get_idt(vcpu, &dt);
6051 sregs->idt.limit = dt.size;
6052 sregs->idt.base = dt.address;
6053 kvm_x86_ops->get_gdt(vcpu, &dt);
6054 sregs->gdt.limit = dt.size;
6055 sregs->gdt.base = dt.address;
6056
6057 sregs->cr0 = kvm_read_cr0(vcpu);
6058 sregs->cr2 = vcpu->arch.cr2;
6059 sregs->cr3 = kvm_read_cr3(vcpu);
6060 sregs->cr4 = kvm_read_cr4(vcpu);
6061 sregs->cr8 = kvm_get_cr8(vcpu);
6062 sregs->efer = vcpu->arch.efer;
6063 sregs->apic_base = kvm_get_apic_base(vcpu);
6064
6065 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6066
6067 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6068 set_bit(vcpu->arch.interrupt.nr,
6069 (unsigned long *)sregs->interrupt_bitmap);
6070
6071 return 0;
6072 }
6073
6074 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6075 struct kvm_mp_state *mp_state)
6076 {
6077 mp_state->mp_state = vcpu->arch.mp_state;
6078 return 0;
6079 }
6080
6081 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6082 struct kvm_mp_state *mp_state)
6083 {
6084 vcpu->arch.mp_state = mp_state->mp_state;
6085 kvm_make_request(KVM_REQ_EVENT, vcpu);
6086 return 0;
6087 }
6088
6089 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6090 int reason, bool has_error_code, u32 error_code)
6091 {
6092 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6093 int ret;
6094
6095 init_emulate_ctxt(vcpu);
6096
6097 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6098 has_error_code, error_code);
6099
6100 if (ret)
6101 return EMULATE_FAIL;
6102
6103 kvm_rip_write(vcpu, ctxt->eip);
6104 kvm_set_rflags(vcpu, ctxt->eflags);
6105 kvm_make_request(KVM_REQ_EVENT, vcpu);
6106 return EMULATE_DONE;
6107 }
6108 EXPORT_SYMBOL_GPL(kvm_task_switch);
6109
6110 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6111 struct kvm_sregs *sregs)
6112 {
6113 int mmu_reset_needed = 0;
6114 int pending_vec, max_bits, idx;
6115 struct desc_ptr dt;
6116
6117 dt.size = sregs->idt.limit;
6118 dt.address = sregs->idt.base;
6119 kvm_x86_ops->set_idt(vcpu, &dt);
6120 dt.size = sregs->gdt.limit;
6121 dt.address = sregs->gdt.base;
6122 kvm_x86_ops->set_gdt(vcpu, &dt);
6123
6124 vcpu->arch.cr2 = sregs->cr2;
6125 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6126 vcpu->arch.cr3 = sregs->cr3;
6127 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6128
6129 kvm_set_cr8(vcpu, sregs->cr8);
6130
6131 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6132 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6133 kvm_set_apic_base(vcpu, sregs->apic_base);
6134
6135 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6136 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6137 vcpu->arch.cr0 = sregs->cr0;
6138
6139 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6140 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6141 if (sregs->cr4 & X86_CR4_OSXSAVE)
6142 kvm_update_cpuid(vcpu);
6143
6144 idx = srcu_read_lock(&vcpu->kvm->srcu);
6145 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6146 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6147 mmu_reset_needed = 1;
6148 }
6149 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6150
6151 if (mmu_reset_needed)
6152 kvm_mmu_reset_context(vcpu);
6153
6154 max_bits = KVM_NR_INTERRUPTS;
6155 pending_vec = find_first_bit(
6156 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6157 if (pending_vec < max_bits) {
6158 kvm_queue_interrupt(vcpu, pending_vec, false);
6159 pr_debug("Set back pending irq %d\n", pending_vec);
6160 }
6161
6162 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6163 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6164 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6165 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6166 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6167 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6168
6169 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6170 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6171
6172 update_cr8_intercept(vcpu);
6173
6174 /* Older userspace won't unhalt the vcpu on reset. */
6175 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6176 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6177 !is_protmode(vcpu))
6178 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6179
6180 kvm_make_request(KVM_REQ_EVENT, vcpu);
6181
6182 return 0;
6183 }
6184
6185 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6186 struct kvm_guest_debug *dbg)
6187 {
6188 unsigned long rflags;
6189 int i, r;
6190
6191 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6192 r = -EBUSY;
6193 if (vcpu->arch.exception.pending)
6194 goto out;
6195 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6196 kvm_queue_exception(vcpu, DB_VECTOR);
6197 else
6198 kvm_queue_exception(vcpu, BP_VECTOR);
6199 }
6200
6201 /*
6202 * Read rflags as long as potentially injected trace flags are still
6203 * filtered out.
6204 */
6205 rflags = kvm_get_rflags(vcpu);
6206
6207 vcpu->guest_debug = dbg->control;
6208 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6209 vcpu->guest_debug = 0;
6210
6211 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6212 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6213 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6214 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6215 } else {
6216 for (i = 0; i < KVM_NR_DB_REGS; i++)
6217 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6218 }
6219 kvm_update_dr7(vcpu);
6220
6221 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6222 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6223 get_segment_base(vcpu, VCPU_SREG_CS);
6224
6225 /*
6226 * Trigger an rflags update that will inject or remove the trace
6227 * flags.
6228 */
6229 kvm_set_rflags(vcpu, rflags);
6230
6231 kvm_x86_ops->update_db_bp_intercept(vcpu);
6232
6233 r = 0;
6234
6235 out:
6236
6237 return r;
6238 }
6239
6240 /*
6241 * Translate a guest virtual address to a guest physical address.
6242 */
6243 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6244 struct kvm_translation *tr)
6245 {
6246 unsigned long vaddr = tr->linear_address;
6247 gpa_t gpa;
6248 int idx;
6249
6250 idx = srcu_read_lock(&vcpu->kvm->srcu);
6251 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6252 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6253 tr->physical_address = gpa;
6254 tr->valid = gpa != UNMAPPED_GVA;
6255 tr->writeable = 1;
6256 tr->usermode = 0;
6257
6258 return 0;
6259 }
6260
6261 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6262 {
6263 struct i387_fxsave_struct *fxsave =
6264 &vcpu->arch.guest_fpu.state->fxsave;
6265
6266 memcpy(fpu->fpr, fxsave->st_space, 128);
6267 fpu->fcw = fxsave->cwd;
6268 fpu->fsw = fxsave->swd;
6269 fpu->ftwx = fxsave->twd;
6270 fpu->last_opcode = fxsave->fop;
6271 fpu->last_ip = fxsave->rip;
6272 fpu->last_dp = fxsave->rdp;
6273 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6274
6275 return 0;
6276 }
6277
6278 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6279 {
6280 struct i387_fxsave_struct *fxsave =
6281 &vcpu->arch.guest_fpu.state->fxsave;
6282
6283 memcpy(fxsave->st_space, fpu->fpr, 128);
6284 fxsave->cwd = fpu->fcw;
6285 fxsave->swd = fpu->fsw;
6286 fxsave->twd = fpu->ftwx;
6287 fxsave->fop = fpu->last_opcode;
6288 fxsave->rip = fpu->last_ip;
6289 fxsave->rdp = fpu->last_dp;
6290 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6291
6292 return 0;
6293 }
6294
6295 int fx_init(struct kvm_vcpu *vcpu)
6296 {
6297 int err;
6298
6299 err = fpu_alloc(&vcpu->arch.guest_fpu);
6300 if (err)
6301 return err;
6302
6303 fpu_finit(&vcpu->arch.guest_fpu);
6304
6305 /*
6306 * Ensure guest xcr0 is valid for loading
6307 */
6308 vcpu->arch.xcr0 = XSTATE_FP;
6309
6310 vcpu->arch.cr0 |= X86_CR0_ET;
6311
6312 return 0;
6313 }
6314 EXPORT_SYMBOL_GPL(fx_init);
6315
6316 static void fx_free(struct kvm_vcpu *vcpu)
6317 {
6318 fpu_free(&vcpu->arch.guest_fpu);
6319 }
6320
6321 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6322 {
6323 if (vcpu->guest_fpu_loaded)
6324 return;
6325
6326 /*
6327 * Restore all possible states in the guest,
6328 * and assume host would use all available bits.
6329 * Guest xcr0 would be loaded later.
6330 */
6331 kvm_put_guest_xcr0(vcpu);
6332 vcpu->guest_fpu_loaded = 1;
6333 __kernel_fpu_begin();
6334 fpu_restore_checking(&vcpu->arch.guest_fpu);
6335 trace_kvm_fpu(1);
6336 }
6337
6338 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6339 {
6340 kvm_put_guest_xcr0(vcpu);
6341
6342 if (!vcpu->guest_fpu_loaded)
6343 return;
6344
6345 vcpu->guest_fpu_loaded = 0;
6346 fpu_save_init(&vcpu->arch.guest_fpu);
6347 __kernel_fpu_end();
6348 ++vcpu->stat.fpu_reload;
6349 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6350 trace_kvm_fpu(0);
6351 }
6352
6353 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6354 {
6355 kvmclock_reset(vcpu);
6356
6357 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6358 fx_free(vcpu);
6359 kvm_x86_ops->vcpu_free(vcpu);
6360 }
6361
6362 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6363 unsigned int id)
6364 {
6365 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6366 printk_once(KERN_WARNING
6367 "kvm: SMP vm created on host with unstable TSC; "
6368 "guest TSC will not be reliable\n");
6369 return kvm_x86_ops->vcpu_create(kvm, id);
6370 }
6371
6372 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6373 {
6374 int r;
6375
6376 vcpu->arch.mtrr_state.have_fixed = 1;
6377 r = vcpu_load(vcpu);
6378 if (r)
6379 return r;
6380 r = kvm_vcpu_reset(vcpu);
6381 if (r == 0)
6382 r = kvm_mmu_setup(vcpu);
6383 vcpu_put(vcpu);
6384
6385 return r;
6386 }
6387
6388 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6389 {
6390 int r;
6391 struct msr_data msr;
6392
6393 r = vcpu_load(vcpu);
6394 if (r)
6395 return r;
6396 msr.data = 0x0;
6397 msr.index = MSR_IA32_TSC;
6398 msr.host_initiated = true;
6399 kvm_write_tsc(vcpu, &msr);
6400 vcpu_put(vcpu);
6401
6402 return r;
6403 }
6404
6405 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6406 {
6407 int r;
6408 vcpu->arch.apf.msr_val = 0;
6409
6410 r = vcpu_load(vcpu);
6411 BUG_ON(r);
6412 kvm_mmu_unload(vcpu);
6413 vcpu_put(vcpu);
6414
6415 fx_free(vcpu);
6416 kvm_x86_ops->vcpu_free(vcpu);
6417 }
6418
6419 static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6420 {
6421 atomic_set(&vcpu->arch.nmi_queued, 0);
6422 vcpu->arch.nmi_pending = 0;
6423 vcpu->arch.nmi_injected = false;
6424
6425 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6426 vcpu->arch.dr6 = DR6_FIXED_1;
6427 vcpu->arch.dr7 = DR7_FIXED_1;
6428 kvm_update_dr7(vcpu);
6429
6430 kvm_make_request(KVM_REQ_EVENT, vcpu);
6431 vcpu->arch.apf.msr_val = 0;
6432 vcpu->arch.st.msr_val = 0;
6433
6434 kvmclock_reset(vcpu);
6435
6436 kvm_clear_async_pf_completion_queue(vcpu);
6437 kvm_async_pf_hash_reset(vcpu);
6438 vcpu->arch.apf.halted = false;
6439
6440 kvm_pmu_reset(vcpu);
6441
6442 return kvm_x86_ops->vcpu_reset(vcpu);
6443 }
6444
6445 int kvm_arch_hardware_enable(void *garbage)
6446 {
6447 struct kvm *kvm;
6448 struct kvm_vcpu *vcpu;
6449 int i;
6450 int ret;
6451 u64 local_tsc;
6452 u64 max_tsc = 0;
6453 bool stable, backwards_tsc = false;
6454
6455 kvm_shared_msr_cpu_online();
6456 ret = kvm_x86_ops->hardware_enable(garbage);
6457 if (ret != 0)
6458 return ret;
6459
6460 local_tsc = native_read_tsc();
6461 stable = !check_tsc_unstable();
6462 list_for_each_entry(kvm, &vm_list, vm_list) {
6463 kvm_for_each_vcpu(i, vcpu, kvm) {
6464 if (!stable && vcpu->cpu == smp_processor_id())
6465 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6466 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6467 backwards_tsc = true;
6468 if (vcpu->arch.last_host_tsc > max_tsc)
6469 max_tsc = vcpu->arch.last_host_tsc;
6470 }
6471 }
6472 }
6473
6474 /*
6475 * Sometimes, even reliable TSCs go backwards. This happens on
6476 * platforms that reset TSC during suspend or hibernate actions, but
6477 * maintain synchronization. We must compensate. Fortunately, we can
6478 * detect that condition here, which happens early in CPU bringup,
6479 * before any KVM threads can be running. Unfortunately, we can't
6480 * bring the TSCs fully up to date with real time, as we aren't yet far
6481 * enough into CPU bringup that we know how much real time has actually
6482 * elapsed; our helper function, get_kernel_ns() will be using boot
6483 * variables that haven't been updated yet.
6484 *
6485 * So we simply find the maximum observed TSC above, then record the
6486 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6487 * the adjustment will be applied. Note that we accumulate
6488 * adjustments, in case multiple suspend cycles happen before some VCPU
6489 * gets a chance to run again. In the event that no KVM threads get a
6490 * chance to run, we will miss the entire elapsed period, as we'll have
6491 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6492 * loose cycle time. This isn't too big a deal, since the loss will be
6493 * uniform across all VCPUs (not to mention the scenario is extremely
6494 * unlikely). It is possible that a second hibernate recovery happens
6495 * much faster than a first, causing the observed TSC here to be
6496 * smaller; this would require additional padding adjustment, which is
6497 * why we set last_host_tsc to the local tsc observed here.
6498 *
6499 * N.B. - this code below runs only on platforms with reliable TSC,
6500 * as that is the only way backwards_tsc is set above. Also note
6501 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6502 * have the same delta_cyc adjustment applied if backwards_tsc
6503 * is detected. Note further, this adjustment is only done once,
6504 * as we reset last_host_tsc on all VCPUs to stop this from being
6505 * called multiple times (one for each physical CPU bringup).
6506 *
6507 * Platforms with unreliable TSCs don't have to deal with this, they
6508 * will be compensated by the logic in vcpu_load, which sets the TSC to
6509 * catchup mode. This will catchup all VCPUs to real time, but cannot
6510 * guarantee that they stay in perfect synchronization.
6511 */
6512 if (backwards_tsc) {
6513 u64 delta_cyc = max_tsc - local_tsc;
6514 list_for_each_entry(kvm, &vm_list, vm_list) {
6515 kvm_for_each_vcpu(i, vcpu, kvm) {
6516 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6517 vcpu->arch.last_host_tsc = local_tsc;
6518 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6519 &vcpu->requests);
6520 }
6521
6522 /*
6523 * We have to disable TSC offset matching.. if you were
6524 * booting a VM while issuing an S4 host suspend....
6525 * you may have some problem. Solving this issue is
6526 * left as an exercise to the reader.
6527 */
6528 kvm->arch.last_tsc_nsec = 0;
6529 kvm->arch.last_tsc_write = 0;
6530 }
6531
6532 }
6533 return 0;
6534 }
6535
6536 void kvm_arch_hardware_disable(void *garbage)
6537 {
6538 kvm_x86_ops->hardware_disable(garbage);
6539 drop_user_return_notifiers(garbage);
6540 }
6541
6542 int kvm_arch_hardware_setup(void)
6543 {
6544 return kvm_x86_ops->hardware_setup();
6545 }
6546
6547 void kvm_arch_hardware_unsetup(void)
6548 {
6549 kvm_x86_ops->hardware_unsetup();
6550 }
6551
6552 void kvm_arch_check_processor_compat(void *rtn)
6553 {
6554 kvm_x86_ops->check_processor_compatibility(rtn);
6555 }
6556
6557 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6558 {
6559 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6560 }
6561
6562 struct static_key kvm_no_apic_vcpu __read_mostly;
6563
6564 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6565 {
6566 struct page *page;
6567 struct kvm *kvm;
6568 int r;
6569
6570 BUG_ON(vcpu->kvm == NULL);
6571 kvm = vcpu->kvm;
6572
6573 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6574 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6575 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6576 else
6577 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6578
6579 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6580 if (!page) {
6581 r = -ENOMEM;
6582 goto fail;
6583 }
6584 vcpu->arch.pio_data = page_address(page);
6585
6586 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6587
6588 r = kvm_mmu_create(vcpu);
6589 if (r < 0)
6590 goto fail_free_pio_data;
6591
6592 if (irqchip_in_kernel(kvm)) {
6593 r = kvm_create_lapic(vcpu);
6594 if (r < 0)
6595 goto fail_mmu_destroy;
6596 } else
6597 static_key_slow_inc(&kvm_no_apic_vcpu);
6598
6599 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6600 GFP_KERNEL);
6601 if (!vcpu->arch.mce_banks) {
6602 r = -ENOMEM;
6603 goto fail_free_lapic;
6604 }
6605 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6606
6607 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6608 goto fail_free_mce_banks;
6609
6610 kvm_async_pf_hash_reset(vcpu);
6611 kvm_pmu_init(vcpu);
6612
6613 return 0;
6614 fail_free_mce_banks:
6615 kfree(vcpu->arch.mce_banks);
6616 fail_free_lapic:
6617 kvm_free_lapic(vcpu);
6618 fail_mmu_destroy:
6619 kvm_mmu_destroy(vcpu);
6620 fail_free_pio_data:
6621 free_page((unsigned long)vcpu->arch.pio_data);
6622 fail:
6623 return r;
6624 }
6625
6626 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6627 {
6628 int idx;
6629
6630 kvm_pmu_destroy(vcpu);
6631 kfree(vcpu->arch.mce_banks);
6632 kvm_free_lapic(vcpu);
6633 idx = srcu_read_lock(&vcpu->kvm->srcu);
6634 kvm_mmu_destroy(vcpu);
6635 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6636 free_page((unsigned long)vcpu->arch.pio_data);
6637 if (!irqchip_in_kernel(vcpu->kvm))
6638 static_key_slow_dec(&kvm_no_apic_vcpu);
6639 }
6640
6641 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6642 {
6643 if (type)
6644 return -EINVAL;
6645
6646 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6647 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6648
6649 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6650 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6651 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6652 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6653 &kvm->arch.irq_sources_bitmap);
6654
6655 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6656 mutex_init(&kvm->arch.apic_map_lock);
6657 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6658
6659 pvclock_update_vm_gtod_copy(kvm);
6660
6661 return 0;
6662 }
6663
6664 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6665 {
6666 int r;
6667 r = vcpu_load(vcpu);
6668 BUG_ON(r);
6669 kvm_mmu_unload(vcpu);
6670 vcpu_put(vcpu);
6671 }
6672
6673 static void kvm_free_vcpus(struct kvm *kvm)
6674 {
6675 unsigned int i;
6676 struct kvm_vcpu *vcpu;
6677
6678 /*
6679 * Unpin any mmu pages first.
6680 */
6681 kvm_for_each_vcpu(i, vcpu, kvm) {
6682 kvm_clear_async_pf_completion_queue(vcpu);
6683 kvm_unload_vcpu_mmu(vcpu);
6684 }
6685 kvm_for_each_vcpu(i, vcpu, kvm)
6686 kvm_arch_vcpu_free(vcpu);
6687
6688 mutex_lock(&kvm->lock);
6689 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6690 kvm->vcpus[i] = NULL;
6691
6692 atomic_set(&kvm->online_vcpus, 0);
6693 mutex_unlock(&kvm->lock);
6694 }
6695
6696 void kvm_arch_sync_events(struct kvm *kvm)
6697 {
6698 kvm_free_all_assigned_devices(kvm);
6699 kvm_free_pit(kvm);
6700 }
6701
6702 void kvm_arch_destroy_vm(struct kvm *kvm)
6703 {
6704 kvm_iommu_unmap_guest(kvm);
6705 kfree(kvm->arch.vpic);
6706 kfree(kvm->arch.vioapic);
6707 kvm_free_vcpus(kvm);
6708 if (kvm->arch.apic_access_page)
6709 put_page(kvm->arch.apic_access_page);
6710 if (kvm->arch.ept_identity_pagetable)
6711 put_page(kvm->arch.ept_identity_pagetable);
6712 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
6713 }
6714
6715 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6716 struct kvm_memory_slot *dont)
6717 {
6718 int i;
6719
6720 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6721 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6722 kvm_kvfree(free->arch.rmap[i]);
6723 free->arch.rmap[i] = NULL;
6724 }
6725 if (i == 0)
6726 continue;
6727
6728 if (!dont || free->arch.lpage_info[i - 1] !=
6729 dont->arch.lpage_info[i - 1]) {
6730 kvm_kvfree(free->arch.lpage_info[i - 1]);
6731 free->arch.lpage_info[i - 1] = NULL;
6732 }
6733 }
6734 }
6735
6736 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6737 {
6738 int i;
6739
6740 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6741 unsigned long ugfn;
6742 int lpages;
6743 int level = i + 1;
6744
6745 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6746 slot->base_gfn, level) + 1;
6747
6748 slot->arch.rmap[i] =
6749 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6750 if (!slot->arch.rmap[i])
6751 goto out_free;
6752 if (i == 0)
6753 continue;
6754
6755 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6756 sizeof(*slot->arch.lpage_info[i - 1]));
6757 if (!slot->arch.lpage_info[i - 1])
6758 goto out_free;
6759
6760 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6761 slot->arch.lpage_info[i - 1][0].write_count = 1;
6762 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6763 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
6764 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6765 /*
6766 * If the gfn and userspace address are not aligned wrt each
6767 * other, or if explicitly asked to, disable large page
6768 * support for this slot
6769 */
6770 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6771 !kvm_largepages_enabled()) {
6772 unsigned long j;
6773
6774 for (j = 0; j < lpages; ++j)
6775 slot->arch.lpage_info[i - 1][j].write_count = 1;
6776 }
6777 }
6778
6779 return 0;
6780
6781 out_free:
6782 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6783 kvm_kvfree(slot->arch.rmap[i]);
6784 slot->arch.rmap[i] = NULL;
6785 if (i == 0)
6786 continue;
6787
6788 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6789 slot->arch.lpage_info[i - 1] = NULL;
6790 }
6791 return -ENOMEM;
6792 }
6793
6794 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6795 struct kvm_memory_slot *memslot,
6796 struct kvm_memory_slot old,
6797 struct kvm_userspace_memory_region *mem,
6798 int user_alloc)
6799 {
6800 int npages = memslot->npages;
6801 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6802
6803 /* Prevent internal slot pages from being moved by fork()/COW. */
6804 if (memslot->id >= KVM_MEMORY_SLOTS)
6805 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6806
6807 /*To keep backward compatibility with older userspace,
6808 *x86 needs to handle !user_alloc case.
6809 */
6810 if (!user_alloc) {
6811 if (npages && !old.npages) {
6812 unsigned long userspace_addr;
6813
6814 userspace_addr = vm_mmap(NULL, 0,
6815 npages * PAGE_SIZE,
6816 PROT_READ | PROT_WRITE,
6817 map_flags,
6818 0);
6819
6820 if (IS_ERR((void *)userspace_addr))
6821 return PTR_ERR((void *)userspace_addr);
6822
6823 memslot->userspace_addr = userspace_addr;
6824 }
6825 }
6826
6827
6828 return 0;
6829 }
6830
6831 void kvm_arch_commit_memory_region(struct kvm *kvm,
6832 struct kvm_userspace_memory_region *mem,
6833 struct kvm_memory_slot old,
6834 int user_alloc)
6835 {
6836
6837 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6838
6839 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
6840 int ret;
6841
6842 ret = vm_munmap(old.userspace_addr,
6843 old.npages * PAGE_SIZE);
6844 if (ret < 0)
6845 printk(KERN_WARNING
6846 "kvm_vm_ioctl_set_memory_region: "
6847 "failed to munmap memory\n");
6848 }
6849
6850 if (!kvm->arch.n_requested_mmu_pages)
6851 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6852
6853 spin_lock(&kvm->mmu_lock);
6854 if (nr_mmu_pages)
6855 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6856 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6857 spin_unlock(&kvm->mmu_lock);
6858 /*
6859 * If memory slot is created, or moved, we need to clear all
6860 * mmio sptes.
6861 */
6862 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6863 kvm_mmu_zap_all(kvm);
6864 kvm_reload_remote_mmus(kvm);
6865 }
6866 }
6867
6868 void kvm_arch_flush_shadow_all(struct kvm *kvm)
6869 {
6870 kvm_mmu_zap_all(kvm);
6871 kvm_reload_remote_mmus(kvm);
6872 }
6873
6874 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6875 struct kvm_memory_slot *slot)
6876 {
6877 kvm_arch_flush_shadow_all(kvm);
6878 }
6879
6880 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6881 {
6882 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6883 !vcpu->arch.apf.halted)
6884 || !list_empty_careful(&vcpu->async_pf.done)
6885 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6886 || atomic_read(&vcpu->arch.nmi_queued) ||
6887 (kvm_arch_interrupt_allowed(vcpu) &&
6888 kvm_cpu_has_interrupt(vcpu));
6889 }
6890
6891 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
6892 {
6893 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
6894 }
6895
6896 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6897 {
6898 return kvm_x86_ops->interrupt_allowed(vcpu);
6899 }
6900
6901 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6902 {
6903 unsigned long current_rip = kvm_rip_read(vcpu) +
6904 get_segment_base(vcpu, VCPU_SREG_CS);
6905
6906 return current_rip == linear_rip;
6907 }
6908 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6909
6910 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6911 {
6912 unsigned long rflags;
6913
6914 rflags = kvm_x86_ops->get_rflags(vcpu);
6915 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6916 rflags &= ~X86_EFLAGS_TF;
6917 return rflags;
6918 }
6919 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6920
6921 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6922 {
6923 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6924 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6925 rflags |= X86_EFLAGS_TF;
6926 kvm_x86_ops->set_rflags(vcpu, rflags);
6927 kvm_make_request(KVM_REQ_EVENT, vcpu);
6928 }
6929 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6930
6931 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6932 {
6933 int r;
6934
6935 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6936 is_error_page(work->page))
6937 return;
6938
6939 r = kvm_mmu_reload(vcpu);
6940 if (unlikely(r))
6941 return;
6942
6943 if (!vcpu->arch.mmu.direct_map &&
6944 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6945 return;
6946
6947 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6948 }
6949
6950 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6951 {
6952 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6953 }
6954
6955 static inline u32 kvm_async_pf_next_probe(u32 key)
6956 {
6957 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6958 }
6959
6960 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6961 {
6962 u32 key = kvm_async_pf_hash_fn(gfn);
6963
6964 while (vcpu->arch.apf.gfns[key] != ~0)
6965 key = kvm_async_pf_next_probe(key);
6966
6967 vcpu->arch.apf.gfns[key] = gfn;
6968 }
6969
6970 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6971 {
6972 int i;
6973 u32 key = kvm_async_pf_hash_fn(gfn);
6974
6975 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6976 (vcpu->arch.apf.gfns[key] != gfn &&
6977 vcpu->arch.apf.gfns[key] != ~0); i++)
6978 key = kvm_async_pf_next_probe(key);
6979
6980 return key;
6981 }
6982
6983 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6984 {
6985 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6986 }
6987
6988 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6989 {
6990 u32 i, j, k;
6991
6992 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6993 while (true) {
6994 vcpu->arch.apf.gfns[i] = ~0;
6995 do {
6996 j = kvm_async_pf_next_probe(j);
6997 if (vcpu->arch.apf.gfns[j] == ~0)
6998 return;
6999 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7000 /*
7001 * k lies cyclically in ]i,j]
7002 * | i.k.j |
7003 * |....j i.k.| or |.k..j i...|
7004 */
7005 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7006 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7007 i = j;
7008 }
7009 }
7010
7011 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7012 {
7013
7014 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7015 sizeof(val));
7016 }
7017
7018 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7019 struct kvm_async_pf *work)
7020 {
7021 struct x86_exception fault;
7022
7023 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7024 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7025
7026 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7027 (vcpu->arch.apf.send_user_only &&
7028 kvm_x86_ops->get_cpl(vcpu) == 0))
7029 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7030 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7031 fault.vector = PF_VECTOR;
7032 fault.error_code_valid = true;
7033 fault.error_code = 0;
7034 fault.nested_page_fault = false;
7035 fault.address = work->arch.token;
7036 kvm_inject_page_fault(vcpu, &fault);
7037 }
7038 }
7039
7040 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7041 struct kvm_async_pf *work)
7042 {
7043 struct x86_exception fault;
7044
7045 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7046 if (is_error_page(work->page))
7047 work->arch.token = ~0; /* broadcast wakeup */
7048 else
7049 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7050
7051 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7052 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7053 fault.vector = PF_VECTOR;
7054 fault.error_code_valid = true;
7055 fault.error_code = 0;
7056 fault.nested_page_fault = false;
7057 fault.address = work->arch.token;
7058 kvm_inject_page_fault(vcpu, &fault);
7059 }
7060 vcpu->arch.apf.halted = false;
7061 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7062 }
7063
7064 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7065 {
7066 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7067 return true;
7068 else
7069 return !kvm_event_needs_reinjection(vcpu) &&
7070 kvm_x86_ops->interrupt_allowed(vcpu);
7071 }
7072
7073 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7074 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7075 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7076 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7077 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7078 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7079 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7080 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7081 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7082 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7083 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7084 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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