]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - arch/x86/kvm/x86.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM, pkeys: expose CPUID/CR4 to guest
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <trace/events/kvm.h>
57
58 #define CREATE_TRACE_POINTS
59 #include "trace.h"
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70
71 #define MAX_IO_MSRS 256
72 #define KVM_MAX_MCE_BANKS 32
73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
74
75 #define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
78 /* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82 #ifdef CONFIG_X86_64
83 static
84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
85 #else
86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
87 #endif
88
89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
91
92 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
93 static void process_nmi(struct kvm_vcpu *vcpu);
94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
95
96 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
97 EXPORT_SYMBOL_GPL(kvm_x86_ops);
98
99 static bool __read_mostly ignore_msrs = 0;
100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
102 unsigned int min_timer_period_us = 500;
103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
105 static bool __read_mostly kvmclock_periodic_sync = true;
106 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
108 bool __read_mostly kvm_has_tsc_control;
109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
110 u32 __read_mostly kvm_max_guest_tsc_khz;
111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114 u64 __read_mostly kvm_max_tsc_scaling_ratio;
115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
116 static u64 __read_mostly kvm_default_tsc_scaling_ratio;
117
118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
119 static u32 __read_mostly tsc_tolerance_ppm = 250;
120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
123 unsigned int __read_mostly lapic_timer_advance_ns = 0;
124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
126 static bool __read_mostly vector_hashing = true;
127 module_param(vector_hashing, bool, S_IRUGO);
128
129 static bool __read_mostly backwards_tsc_observed = false;
130
131 #define KVM_NR_SHARED_MSRS 16
132
133 struct kvm_shared_msrs_global {
134 int nr;
135 u32 msrs[KVM_NR_SHARED_MSRS];
136 };
137
138 struct kvm_shared_msrs {
139 struct user_return_notifier urn;
140 bool registered;
141 struct kvm_shared_msr_values {
142 u64 host;
143 u64 curr;
144 } values[KVM_NR_SHARED_MSRS];
145 };
146
147 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
148 static struct kvm_shared_msrs __percpu *shared_msrs;
149
150 struct kvm_stats_debugfs_item debugfs_entries[] = {
151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
161 { "halt_exits", VCPU_STAT(halt_exits) },
162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
164 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
165 { "hypercalls", VCPU_STAT(hypercalls) },
166 { "request_irq", VCPU_STAT(request_irq_exits) },
167 { "irq_exits", VCPU_STAT(irq_exits) },
168 { "host_state_reload", VCPU_STAT(host_state_reload) },
169 { "efer_reload", VCPU_STAT(efer_reload) },
170 { "fpu_reload", VCPU_STAT(fpu_reload) },
171 { "insn_emulation", VCPU_STAT(insn_emulation) },
172 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
173 { "irq_injections", VCPU_STAT(irq_injections) },
174 { "nmi_injections", VCPU_STAT(nmi_injections) },
175 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
176 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
177 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
178 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
179 { "mmu_flooded", VM_STAT(mmu_flooded) },
180 { "mmu_recycled", VM_STAT(mmu_recycled) },
181 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
182 { "mmu_unsync", VM_STAT(mmu_unsync) },
183 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
184 { "largepages", VM_STAT(lpages) },
185 { NULL }
186 };
187
188 u64 __read_mostly host_xcr0;
189
190 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
191
192 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
193 {
194 int i;
195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
196 vcpu->arch.apf.gfns[i] = ~0;
197 }
198
199 static void kvm_on_user_return(struct user_return_notifier *urn)
200 {
201 unsigned slot;
202 struct kvm_shared_msrs *locals
203 = container_of(urn, struct kvm_shared_msrs, urn);
204 struct kvm_shared_msr_values *values;
205
206 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
207 values = &locals->values[slot];
208 if (values->host != values->curr) {
209 wrmsrl(shared_msrs_global.msrs[slot], values->host);
210 values->curr = values->host;
211 }
212 }
213 locals->registered = false;
214 user_return_notifier_unregister(urn);
215 }
216
217 static void shared_msr_update(unsigned slot, u32 msr)
218 {
219 u64 value;
220 unsigned int cpu = smp_processor_id();
221 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
222
223 /* only read, and nobody should modify it at this time,
224 * so don't need lock */
225 if (slot >= shared_msrs_global.nr) {
226 printk(KERN_ERR "kvm: invalid MSR slot!");
227 return;
228 }
229 rdmsrl_safe(msr, &value);
230 smsr->values[slot].host = value;
231 smsr->values[slot].curr = value;
232 }
233
234 void kvm_define_shared_msr(unsigned slot, u32 msr)
235 {
236 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
237 shared_msrs_global.msrs[slot] = msr;
238 if (slot >= shared_msrs_global.nr)
239 shared_msrs_global.nr = slot + 1;
240 }
241 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
242
243 static void kvm_shared_msr_cpu_online(void)
244 {
245 unsigned i;
246
247 for (i = 0; i < shared_msrs_global.nr; ++i)
248 shared_msr_update(i, shared_msrs_global.msrs[i]);
249 }
250
251 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
252 {
253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
255 int err;
256
257 if (((value ^ smsr->values[slot].curr) & mask) == 0)
258 return 0;
259 smsr->values[slot].curr = value;
260 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
261 if (err)
262 return 1;
263
264 if (!smsr->registered) {
265 smsr->urn.on_user_return = kvm_on_user_return;
266 user_return_notifier_register(&smsr->urn);
267 smsr->registered = true;
268 }
269 return 0;
270 }
271 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
272
273 static void drop_user_return_notifiers(void)
274 {
275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
277
278 if (smsr->registered)
279 kvm_on_user_return(&smsr->urn);
280 }
281
282 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
283 {
284 return vcpu->arch.apic_base;
285 }
286 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
287
288 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
289 {
290 u64 old_state = vcpu->arch.apic_base &
291 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
292 u64 new_state = msr_info->data &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
295 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
296
297 if (!msr_info->host_initiated &&
298 ((msr_info->data & reserved_bits) != 0 ||
299 new_state == X2APIC_ENABLE ||
300 (new_state == MSR_IA32_APICBASE_ENABLE &&
301 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
302 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
303 old_state == 0)))
304 return 1;
305
306 kvm_lapic_set_base(vcpu, msr_info->data);
307 return 0;
308 }
309 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
310
311 asmlinkage __visible void kvm_spurious_fault(void)
312 {
313 /* Fault while not rebooting. We want the trace. */
314 BUG();
315 }
316 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
317
318 #define EXCPT_BENIGN 0
319 #define EXCPT_CONTRIBUTORY 1
320 #define EXCPT_PF 2
321
322 static int exception_class(int vector)
323 {
324 switch (vector) {
325 case PF_VECTOR:
326 return EXCPT_PF;
327 case DE_VECTOR:
328 case TS_VECTOR:
329 case NP_VECTOR:
330 case SS_VECTOR:
331 case GP_VECTOR:
332 return EXCPT_CONTRIBUTORY;
333 default:
334 break;
335 }
336 return EXCPT_BENIGN;
337 }
338
339 #define EXCPT_FAULT 0
340 #define EXCPT_TRAP 1
341 #define EXCPT_ABORT 2
342 #define EXCPT_INTERRUPT 3
343
344 static int exception_type(int vector)
345 {
346 unsigned int mask;
347
348 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
349 return EXCPT_INTERRUPT;
350
351 mask = 1 << vector;
352
353 /* #DB is trap, as instruction watchpoints are handled elsewhere */
354 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
355 return EXCPT_TRAP;
356
357 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
358 return EXCPT_ABORT;
359
360 /* Reserved exceptions will result in fault */
361 return EXCPT_FAULT;
362 }
363
364 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
365 unsigned nr, bool has_error, u32 error_code,
366 bool reinject)
367 {
368 u32 prev_nr;
369 int class1, class2;
370
371 kvm_make_request(KVM_REQ_EVENT, vcpu);
372
373 if (!vcpu->arch.exception.pending) {
374 queue:
375 if (has_error && !is_protmode(vcpu))
376 has_error = false;
377 vcpu->arch.exception.pending = true;
378 vcpu->arch.exception.has_error_code = has_error;
379 vcpu->arch.exception.nr = nr;
380 vcpu->arch.exception.error_code = error_code;
381 vcpu->arch.exception.reinject = reinject;
382 return;
383 }
384
385 /* to check exception */
386 prev_nr = vcpu->arch.exception.nr;
387 if (prev_nr == DF_VECTOR) {
388 /* triple fault -> shutdown */
389 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
390 return;
391 }
392 class1 = exception_class(prev_nr);
393 class2 = exception_class(nr);
394 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
395 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
396 /* generate double fault per SDM Table 5-5 */
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = true;
399 vcpu->arch.exception.nr = DF_VECTOR;
400 vcpu->arch.exception.error_code = 0;
401 } else
402 /* replace previous exception with a new one in a hope
403 that instruction re-execution will regenerate lost
404 exception */
405 goto queue;
406 }
407
408 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
409 {
410 kvm_multiple_exception(vcpu, nr, false, 0, false);
411 }
412 EXPORT_SYMBOL_GPL(kvm_queue_exception);
413
414 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
415 {
416 kvm_multiple_exception(vcpu, nr, false, 0, true);
417 }
418 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
419
420 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
421 {
422 if (err)
423 kvm_inject_gp(vcpu, 0);
424 else
425 kvm_x86_ops->skip_emulated_instruction(vcpu);
426 }
427 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
428
429 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
430 {
431 ++vcpu->stat.pf_guest;
432 vcpu->arch.cr2 = fault->address;
433 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
434 }
435 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
436
437 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
438 {
439 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
440 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
441 else
442 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
443
444 return fault->nested_page_fault;
445 }
446
447 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
448 {
449 atomic_inc(&vcpu->arch.nmi_queued);
450 kvm_make_request(KVM_REQ_NMI, vcpu);
451 }
452 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
453
454 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
455 {
456 kvm_multiple_exception(vcpu, nr, true, error_code, false);
457 }
458 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
459
460 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
461 {
462 kvm_multiple_exception(vcpu, nr, true, error_code, true);
463 }
464 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
465
466 /*
467 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
468 * a #GP and return false.
469 */
470 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
471 {
472 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
473 return true;
474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
475 return false;
476 }
477 EXPORT_SYMBOL_GPL(kvm_require_cpl);
478
479 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
480 {
481 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
482 return true;
483
484 kvm_queue_exception(vcpu, UD_VECTOR);
485 return false;
486 }
487 EXPORT_SYMBOL_GPL(kvm_require_dr);
488
489 /*
490 * This function will be used to read from the physical memory of the currently
491 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
492 * can read from guest physical or from the guest's guest physical memory.
493 */
494 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
495 gfn_t ngfn, void *data, int offset, int len,
496 u32 access)
497 {
498 struct x86_exception exception;
499 gfn_t real_gfn;
500 gpa_t ngpa;
501
502 ngpa = gfn_to_gpa(ngfn);
503 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
504 if (real_gfn == UNMAPPED_GVA)
505 return -EFAULT;
506
507 real_gfn = gpa_to_gfn(real_gfn);
508
509 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
510 }
511 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
512
513 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
514 void *data, int offset, int len, u32 access)
515 {
516 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
517 data, offset, len, access);
518 }
519
520 /*
521 * Load the pae pdptrs. Return true is they are all valid.
522 */
523 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
524 {
525 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
526 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
527 int i;
528 int ret;
529 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
530
531 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
532 offset * sizeof(u64), sizeof(pdpte),
533 PFERR_USER_MASK|PFERR_WRITE_MASK);
534 if (ret < 0) {
535 ret = 0;
536 goto out;
537 }
538 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
539 if (is_present_gpte(pdpte[i]) &&
540 (pdpte[i] &
541 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
542 ret = 0;
543 goto out;
544 }
545 }
546 ret = 1;
547
548 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
549 __set_bit(VCPU_EXREG_PDPTR,
550 (unsigned long *)&vcpu->arch.regs_avail);
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_dirty);
553 out:
554
555 return ret;
556 }
557 EXPORT_SYMBOL_GPL(load_pdptrs);
558
559 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
560 {
561 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
562 bool changed = true;
563 int offset;
564 gfn_t gfn;
565 int r;
566
567 if (is_long_mode(vcpu) || !is_pae(vcpu))
568 return false;
569
570 if (!test_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail))
572 return true;
573
574 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
575 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
576 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
577 PFERR_USER_MASK | PFERR_WRITE_MASK);
578 if (r < 0)
579 goto out;
580 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
581 out:
582
583 return changed;
584 }
585
586 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
587 {
588 unsigned long old_cr0 = kvm_read_cr0(vcpu);
589 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
590
591 cr0 |= X86_CR0_ET;
592
593 #ifdef CONFIG_X86_64
594 if (cr0 & 0xffffffff00000000UL)
595 return 1;
596 #endif
597
598 cr0 &= ~CR0_RESERVED_BITS;
599
600 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
601 return 1;
602
603 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
604 return 1;
605
606 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
607 #ifdef CONFIG_X86_64
608 if ((vcpu->arch.efer & EFER_LME)) {
609 int cs_db, cs_l;
610
611 if (!is_pae(vcpu))
612 return 1;
613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
614 if (cs_l)
615 return 1;
616 } else
617 #endif
618 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
619 kvm_read_cr3(vcpu)))
620 return 1;
621 }
622
623 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
624 return 1;
625
626 kvm_x86_ops->set_cr0(vcpu, cr0);
627
628 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
629 kvm_clear_async_pf_completion_queue(vcpu);
630 kvm_async_pf_hash_reset(vcpu);
631 }
632
633 if ((cr0 ^ old_cr0) & update_bits)
634 kvm_mmu_reset_context(vcpu);
635
636 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
637 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
638 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
639 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
640
641 return 0;
642 }
643 EXPORT_SYMBOL_GPL(kvm_set_cr0);
644
645 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
646 {
647 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
648 }
649 EXPORT_SYMBOL_GPL(kvm_lmsw);
650
651 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
652 {
653 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
654 !vcpu->guest_xcr0_loaded) {
655 /* kvm_set_xcr() also depends on this */
656 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
657 vcpu->guest_xcr0_loaded = 1;
658 }
659 }
660
661 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
662 {
663 if (vcpu->guest_xcr0_loaded) {
664 if (vcpu->arch.xcr0 != host_xcr0)
665 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
666 vcpu->guest_xcr0_loaded = 0;
667 }
668 }
669
670 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
671 {
672 u64 xcr0 = xcr;
673 u64 old_xcr0 = vcpu->arch.xcr0;
674 u64 valid_bits;
675
676 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
677 if (index != XCR_XFEATURE_ENABLED_MASK)
678 return 1;
679 if (!(xcr0 & XFEATURE_MASK_FP))
680 return 1;
681 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
682 return 1;
683
684 /*
685 * Do not allow the guest to set bits that we do not support
686 * saving. However, xcr0 bit 0 is always set, even if the
687 * emulated CPU does not support XSAVE (see fx_init).
688 */
689 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
690 if (xcr0 & ~valid_bits)
691 return 1;
692
693 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
694 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
695 return 1;
696
697 if (xcr0 & XFEATURE_MASK_AVX512) {
698 if (!(xcr0 & XFEATURE_MASK_YMM))
699 return 1;
700 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
701 return 1;
702 }
703 kvm_put_guest_xcr0(vcpu);
704 vcpu->arch.xcr0 = xcr0;
705
706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
707 kvm_update_cpuid(vcpu);
708 return 0;
709 }
710
711 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
712 {
713 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
714 __kvm_set_xcr(vcpu, index, xcr)) {
715 kvm_inject_gp(vcpu, 0);
716 return 1;
717 }
718 return 0;
719 }
720 EXPORT_SYMBOL_GPL(kvm_set_xcr);
721
722 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
723 {
724 unsigned long old_cr4 = kvm_read_cr4(vcpu);
725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
726 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
727
728 if (cr4 & CR4_RESERVED_BITS)
729 return 1;
730
731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
732 return 1;
733
734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
735 return 1;
736
737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
738 return 1;
739
740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
741 return 1;
742
743 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
744 return 1;
745
746 if (is_long_mode(vcpu)) {
747 if (!(cr4 & X86_CR4_PAE))
748 return 1;
749 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
750 && ((cr4 ^ old_cr4) & pdptr_bits)
751 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
752 kvm_read_cr3(vcpu)))
753 return 1;
754
755 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
756 if (!guest_cpuid_has_pcid(vcpu))
757 return 1;
758
759 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
760 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
761 return 1;
762 }
763
764 if (kvm_x86_ops->set_cr4(vcpu, cr4))
765 return 1;
766
767 if (((cr4 ^ old_cr4) & pdptr_bits) ||
768 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
769 kvm_mmu_reset_context(vcpu);
770
771 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
772 kvm_update_cpuid(vcpu);
773
774 return 0;
775 }
776 EXPORT_SYMBOL_GPL(kvm_set_cr4);
777
778 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
779 {
780 #ifdef CONFIG_X86_64
781 cr3 &= ~CR3_PCID_INVD;
782 #endif
783
784 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
785 kvm_mmu_sync_roots(vcpu);
786 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
787 return 0;
788 }
789
790 if (is_long_mode(vcpu)) {
791 if (cr3 & CR3_L_MODE_RESERVED_BITS)
792 return 1;
793 } else if (is_pae(vcpu) && is_paging(vcpu) &&
794 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
795 return 1;
796
797 vcpu->arch.cr3 = cr3;
798 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
799 kvm_mmu_new_cr3(vcpu);
800 return 0;
801 }
802 EXPORT_SYMBOL_GPL(kvm_set_cr3);
803
804 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
805 {
806 if (cr8 & CR8_RESERVED_BITS)
807 return 1;
808 if (lapic_in_kernel(vcpu))
809 kvm_lapic_set_tpr(vcpu, cr8);
810 else
811 vcpu->arch.cr8 = cr8;
812 return 0;
813 }
814 EXPORT_SYMBOL_GPL(kvm_set_cr8);
815
816 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
817 {
818 if (lapic_in_kernel(vcpu))
819 return kvm_lapic_get_cr8(vcpu);
820 else
821 return vcpu->arch.cr8;
822 }
823 EXPORT_SYMBOL_GPL(kvm_get_cr8);
824
825 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
826 {
827 int i;
828
829 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
830 for (i = 0; i < KVM_NR_DB_REGS; i++)
831 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
833 }
834 }
835
836 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
837 {
838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
839 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
840 }
841
842 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
843 {
844 unsigned long dr7;
845
846 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
847 dr7 = vcpu->arch.guest_debug_dr7;
848 else
849 dr7 = vcpu->arch.dr7;
850 kvm_x86_ops->set_dr7(vcpu, dr7);
851 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
852 if (dr7 & DR7_BP_EN_MASK)
853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
854 }
855
856 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
857 {
858 u64 fixed = DR6_FIXED_1;
859
860 if (!guest_cpuid_has_rtm(vcpu))
861 fixed |= DR6_RTM;
862 return fixed;
863 }
864
865 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
866 {
867 switch (dr) {
868 case 0 ... 3:
869 vcpu->arch.db[dr] = val;
870 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
871 vcpu->arch.eff_db[dr] = val;
872 break;
873 case 4:
874 /* fall through */
875 case 6:
876 if (val & 0xffffffff00000000ULL)
877 return -1; /* #GP */
878 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
879 kvm_update_dr6(vcpu);
880 break;
881 case 5:
882 /* fall through */
883 default: /* 7 */
884 if (val & 0xffffffff00000000ULL)
885 return -1; /* #GP */
886 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
887 kvm_update_dr7(vcpu);
888 break;
889 }
890
891 return 0;
892 }
893
894 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
895 {
896 if (__kvm_set_dr(vcpu, dr, val)) {
897 kvm_inject_gp(vcpu, 0);
898 return 1;
899 }
900 return 0;
901 }
902 EXPORT_SYMBOL_GPL(kvm_set_dr);
903
904 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
905 {
906 switch (dr) {
907 case 0 ... 3:
908 *val = vcpu->arch.db[dr];
909 break;
910 case 4:
911 /* fall through */
912 case 6:
913 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
914 *val = vcpu->arch.dr6;
915 else
916 *val = kvm_x86_ops->get_dr6(vcpu);
917 break;
918 case 5:
919 /* fall through */
920 default: /* 7 */
921 *val = vcpu->arch.dr7;
922 break;
923 }
924 return 0;
925 }
926 EXPORT_SYMBOL_GPL(kvm_get_dr);
927
928 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
929 {
930 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
931 u64 data;
932 int err;
933
934 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
935 if (err)
936 return err;
937 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
938 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
939 return err;
940 }
941 EXPORT_SYMBOL_GPL(kvm_rdpmc);
942
943 /*
944 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
945 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
946 *
947 * This list is modified at module load time to reflect the
948 * capabilities of the host cpu. This capabilities test skips MSRs that are
949 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
950 * may depend on host virtualization features rather than host cpu features.
951 */
952
953 static u32 msrs_to_save[] = {
954 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
955 MSR_STAR,
956 #ifdef CONFIG_X86_64
957 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
958 #endif
959 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
960 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
961 };
962
963 static unsigned num_msrs_to_save;
964
965 static u32 emulated_msrs[] = {
966 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
967 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
968 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
969 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
970 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
971 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
972 HV_X64_MSR_RESET,
973 HV_X64_MSR_VP_INDEX,
974 HV_X64_MSR_VP_RUNTIME,
975 HV_X64_MSR_SCONTROL,
976 HV_X64_MSR_STIMER0_CONFIG,
977 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
978 MSR_KVM_PV_EOI_EN,
979
980 MSR_IA32_TSC_ADJUST,
981 MSR_IA32_TSCDEADLINE,
982 MSR_IA32_MISC_ENABLE,
983 MSR_IA32_MCG_STATUS,
984 MSR_IA32_MCG_CTL,
985 MSR_IA32_SMBASE,
986 };
987
988 static unsigned num_emulated_msrs;
989
990 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
991 {
992 if (efer & efer_reserved_bits)
993 return false;
994
995 if (efer & EFER_FFXSR) {
996 struct kvm_cpuid_entry2 *feat;
997
998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
999 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1000 return false;
1001 }
1002
1003 if (efer & EFER_SVME) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1007 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1008 return false;
1009 }
1010
1011 return true;
1012 }
1013 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1014
1015 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1016 {
1017 u64 old_efer = vcpu->arch.efer;
1018
1019 if (!kvm_valid_efer(vcpu, efer))
1020 return 1;
1021
1022 if (is_paging(vcpu)
1023 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1024 return 1;
1025
1026 efer &= ~EFER_LMA;
1027 efer |= vcpu->arch.efer & EFER_LMA;
1028
1029 kvm_x86_ops->set_efer(vcpu, efer);
1030
1031 /* Update reserved bits */
1032 if ((efer ^ old_efer) & EFER_NX)
1033 kvm_mmu_reset_context(vcpu);
1034
1035 return 0;
1036 }
1037
1038 void kvm_enable_efer_bits(u64 mask)
1039 {
1040 efer_reserved_bits &= ~mask;
1041 }
1042 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1043
1044 /*
1045 * Writes msr value into into the appropriate "register".
1046 * Returns 0 on success, non-0 otherwise.
1047 * Assumes vcpu_load() was already called.
1048 */
1049 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1050 {
1051 switch (msr->index) {
1052 case MSR_FS_BASE:
1053 case MSR_GS_BASE:
1054 case MSR_KERNEL_GS_BASE:
1055 case MSR_CSTAR:
1056 case MSR_LSTAR:
1057 if (is_noncanonical_address(msr->data))
1058 return 1;
1059 break;
1060 case MSR_IA32_SYSENTER_EIP:
1061 case MSR_IA32_SYSENTER_ESP:
1062 /*
1063 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1064 * non-canonical address is written on Intel but not on
1065 * AMD (which ignores the top 32-bits, because it does
1066 * not implement 64-bit SYSENTER).
1067 *
1068 * 64-bit code should hence be able to write a non-canonical
1069 * value on AMD. Making the address canonical ensures that
1070 * vmentry does not fail on Intel after writing a non-canonical
1071 * value, and that something deterministic happens if the guest
1072 * invokes 64-bit SYSENTER.
1073 */
1074 msr->data = get_canonical(msr->data);
1075 }
1076 return kvm_x86_ops->set_msr(vcpu, msr);
1077 }
1078 EXPORT_SYMBOL_GPL(kvm_set_msr);
1079
1080 /*
1081 * Adapt set_msr() to msr_io()'s calling convention
1082 */
1083 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1084 {
1085 struct msr_data msr;
1086 int r;
1087
1088 msr.index = index;
1089 msr.host_initiated = true;
1090 r = kvm_get_msr(vcpu, &msr);
1091 if (r)
1092 return r;
1093
1094 *data = msr.data;
1095 return 0;
1096 }
1097
1098 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1099 {
1100 struct msr_data msr;
1101
1102 msr.data = *data;
1103 msr.index = index;
1104 msr.host_initiated = true;
1105 return kvm_set_msr(vcpu, &msr);
1106 }
1107
1108 #ifdef CONFIG_X86_64
1109 struct pvclock_gtod_data {
1110 seqcount_t seq;
1111
1112 struct { /* extract of a clocksource struct */
1113 int vclock_mode;
1114 cycle_t cycle_last;
1115 cycle_t mask;
1116 u32 mult;
1117 u32 shift;
1118 } clock;
1119
1120 u64 boot_ns;
1121 u64 nsec_base;
1122 };
1123
1124 static struct pvclock_gtod_data pvclock_gtod_data;
1125
1126 static void update_pvclock_gtod(struct timekeeper *tk)
1127 {
1128 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1129 u64 boot_ns;
1130
1131 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1132
1133 write_seqcount_begin(&vdata->seq);
1134
1135 /* copy pvclock gtod data */
1136 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1137 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1138 vdata->clock.mask = tk->tkr_mono.mask;
1139 vdata->clock.mult = tk->tkr_mono.mult;
1140 vdata->clock.shift = tk->tkr_mono.shift;
1141
1142 vdata->boot_ns = boot_ns;
1143 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1144
1145 write_seqcount_end(&vdata->seq);
1146 }
1147 #endif
1148
1149 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1150 {
1151 /*
1152 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1153 * vcpu_enter_guest. This function is only called from
1154 * the physical CPU that is running vcpu.
1155 */
1156 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1157 }
1158
1159 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1160 {
1161 int version;
1162 int r;
1163 struct pvclock_wall_clock wc;
1164 struct timespec boot;
1165
1166 if (!wall_clock)
1167 return;
1168
1169 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1170 if (r)
1171 return;
1172
1173 if (version & 1)
1174 ++version; /* first time write, random junk */
1175
1176 ++version;
1177
1178 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1179 return;
1180
1181 /*
1182 * The guest calculates current wall clock time by adding
1183 * system time (updated by kvm_guest_time_update below) to the
1184 * wall clock specified here. guest system time equals host
1185 * system time for us, thus we must fill in host boot time here.
1186 */
1187 getboottime(&boot);
1188
1189 if (kvm->arch.kvmclock_offset) {
1190 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1191 boot = timespec_sub(boot, ts);
1192 }
1193 wc.sec = boot.tv_sec;
1194 wc.nsec = boot.tv_nsec;
1195 wc.version = version;
1196
1197 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1198
1199 version++;
1200 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1201 }
1202
1203 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1204 {
1205 do_shl32_div32(dividend, divisor);
1206 return dividend;
1207 }
1208
1209 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1210 s8 *pshift, u32 *pmultiplier)
1211 {
1212 uint64_t scaled64;
1213 int32_t shift = 0;
1214 uint64_t tps64;
1215 uint32_t tps32;
1216
1217 tps64 = base_hz;
1218 scaled64 = scaled_hz;
1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1220 tps64 >>= 1;
1221 shift--;
1222 }
1223
1224 tps32 = (uint32_t)tps64;
1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1227 scaled64 >>= 1;
1228 else
1229 tps32 <<= 1;
1230 shift++;
1231 }
1232
1233 *pshift = shift;
1234 *pmultiplier = div_frac(scaled64, tps32);
1235
1236 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1237 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1238 }
1239
1240 #ifdef CONFIG_X86_64
1241 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1242 #endif
1243
1244 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1245 static unsigned long max_tsc_khz;
1246
1247 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1248 {
1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
1251 }
1252
1253 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1254 {
1255 u64 v = (u64)khz * (1000000 + ppm);
1256 do_div(v, 1000000);
1257 return v;
1258 }
1259
1260 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1261 {
1262 u64 ratio;
1263
1264 /* Guest TSC same frequency as host TSC? */
1265 if (!scale) {
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1267 return 0;
1268 }
1269
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1275 return 0;
1276 } else {
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1278 return -1;
1279 }
1280 }
1281
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1285
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1288 user_tsc_khz);
1289 return -1;
1290 }
1291
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1293 return 0;
1294 }
1295
1296 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1297 {
1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
1300
1301 /* tsc_khz can be zero if TSC calibration fails */
1302 if (user_tsc_khz == 0) {
1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1305 return -1;
1306 }
1307
1308 /* Compute a scale to convert nanoseconds in TSC cycles */
1309 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
1312 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1313
1314 /*
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1319 */
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1322 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1324 use_scaling = 1;
1325 }
1326 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1327 }
1328
1329 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1330 {
1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
1334 tsc += vcpu->arch.this_tsc_write;
1335 return tsc;
1336 }
1337
1338 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1339 {
1340 #ifdef CONFIG_X86_64
1341 bool vcpus_matched;
1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1347
1348 /*
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1351 *
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1355 */
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1359
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1363 #endif
1364 }
1365
1366 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1367 {
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1370 }
1371
1372 /*
1373 * Multiply tsc by a fixed point number represented by ratio.
1374 *
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1379 *
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1381 */
1382 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1383 {
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1385 }
1386
1387 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1388 {
1389 u64 _tsc = tsc;
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1391
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1394
1395 return _tsc;
1396 }
1397 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1398
1399 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1400 {
1401 u64 tsc;
1402
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1404
1405 return target_tsc - tsc;
1406 }
1407
1408 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1409 {
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1411 }
1412 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1413
1414 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1415 {
1416 struct kvm *kvm = vcpu->kvm;
1417 u64 offset, ns, elapsed;
1418 unsigned long flags;
1419 s64 usdiff;
1420 bool matched;
1421 bool already_matched;
1422 u64 data = msr->data;
1423
1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1425 offset = kvm_compute_tsc_offset(vcpu, data);
1426 ns = get_kernel_ns();
1427 elapsed = ns - kvm->arch.last_tsc_nsec;
1428
1429 if (vcpu->arch.virtual_tsc_khz) {
1430 int faulted = 0;
1431
1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
1434 #ifdef CONFIG_X86_64
1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1436 #else
1437 /* do_div() only does unsigned */
1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1441 "3:\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1444 " jmp 3b\n"
1445 ".previous\n"
1446
1447 _ASM_EXTABLE(1b, 4b)
1448
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1451
1452 #endif
1453 do_div(elapsed, 1000);
1454 usdiff -= elapsed;
1455 if (usdiff < 0)
1456 usdiff = -usdiff;
1457
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1459 if (faulted)
1460 usdiff = USEC_PER_SEC;
1461 } else
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1463
1464 /*
1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1468 *
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1473 */
1474 if (usdiff < USEC_PER_SEC &&
1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1476 if (!check_tsc_unstable()) {
1477 offset = kvm->arch.cur_tsc_offset;
1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1479 } else {
1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
1481 data += delta;
1482 offset = kvm_compute_tsc_offset(vcpu, data);
1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1484 }
1485 matched = true;
1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1487 } else {
1488 /*
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
1493 * exact software computation in compute_guest_tsc()
1494 *
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1496 */
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
1501 matched = false;
1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1503 kvm->arch.cur_tsc_generation, data);
1504 }
1505
1506 /*
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1509 */
1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1513
1514 vcpu->arch.last_guest_tsc = data;
1515
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1520
1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1525
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1527 if (!matched) {
1528 kvm->arch.nr_vcpus_matched_tsc = 0;
1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1531 }
1532
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1535 }
1536
1537 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1538
1539 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1540 s64 adjustment)
1541 {
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1543 }
1544
1545 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1546 {
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551 }
1552
1553 #ifdef CONFIG_X86_64
1554
1555 static cycle_t read_tsc(void)
1556 {
1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
1559
1560 if (likely(ret >= last))
1561 return ret;
1562
1563 /*
1564 * GCC likes to generate cmov here, but this branch is extremely
1565 * predictable (it's just a funciton of time and the likely is
1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1570 */
1571 asm volatile ("");
1572 return last;
1573 }
1574
1575 static inline u64 vgettsc(cycle_t *cycle_now)
1576 {
1577 long v;
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1579
1580 *cycle_now = read_tsc();
1581
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1584 }
1585
1586 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1587 {
1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1589 unsigned long seq;
1590 int mode;
1591 u64 ns;
1592
1593 do {
1594 seq = read_seqcount_begin(&gtod->seq);
1595 mode = gtod->clock.vclock_mode;
1596 ns = gtod->nsec_base;
1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
1599 ns += gtod->boot_ns;
1600 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1601 *t = ns;
1602
1603 return mode;
1604 }
1605
1606 /* returns true if host is using tsc clocksource */
1607 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1608 {
1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1611 return false;
1612
1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1614 }
1615 #endif
1616
1617 /*
1618 *
1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
1622 * CPUs at the next numbered event.
1623 *
1624 * "timespecX" represents host monotonic time. "tscX" represents
1625 * RDTSC value.
1626 *
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1628 *
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1631 * | tsc1 = tsc0 + M
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1636 *
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1638 *
1639 * - ret0 < ret1
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1641 * ...
1642 * - 0 < N - M => M < N
1643 *
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1648 *
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1652 * in lockstep.
1653 *
1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1655 *
1656 */
1657
1658 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1659 {
1660 #ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1662 int vclock_mode;
1663 bool host_tsc_clocksource, vcpus_matched;
1664
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
1667
1668 /*
1669 * If the host uses TSC clock, then passthrough TSC as stable
1670 * to the guest.
1671 */
1672 host_tsc_clocksource = kvm_get_time_and_clockread(
1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1675
1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
1679
1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1682
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1685 vcpus_matched);
1686 #endif
1687 }
1688
1689 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1690 {
1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1692 }
1693
1694 static void kvm_gen_update_masterclock(struct kvm *kvm)
1695 {
1696 #ifdef CONFIG_X86_64
1697 int i;
1698 struct kvm_vcpu *vcpu;
1699 struct kvm_arch *ka = &kvm->arch;
1700
1701 spin_lock(&ka->pvclock_gtod_sync_lock);
1702 kvm_make_mclock_inprogress_request(kvm);
1703 /* no guest entries from this point */
1704 pvclock_update_vm_gtod_copy(kvm);
1705
1706 kvm_for_each_vcpu(i, vcpu, kvm)
1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1708
1709 /* guest entries allowed */
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1712
1713 spin_unlock(&ka->pvclock_gtod_sync_lock);
1714 #endif
1715 }
1716
1717 static int kvm_guest_time_update(struct kvm_vcpu *v)
1718 {
1719 unsigned long flags, tgt_tsc_khz;
1720 struct kvm_vcpu_arch *vcpu = &v->arch;
1721 struct kvm_arch *ka = &v->kvm->arch;
1722 s64 kernel_ns;
1723 u64 tsc_timestamp, host_tsc;
1724 struct pvclock_vcpu_time_info guest_hv_clock;
1725 u8 pvclock_flags;
1726 bool use_master_clock;
1727
1728 kernel_ns = 0;
1729 host_tsc = 0;
1730
1731 /*
1732 * If the host uses TSC clock, then passthrough TSC as stable
1733 * to the guest.
1734 */
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 use_master_clock = ka->use_master_clock;
1737 if (use_master_clock) {
1738 host_tsc = ka->master_cycle_now;
1739 kernel_ns = ka->master_kernel_ns;
1740 }
1741 spin_unlock(&ka->pvclock_gtod_sync_lock);
1742
1743 /* Keep irq disabled to prevent changes to the clock */
1744 local_irq_save(flags);
1745 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1746 if (unlikely(tgt_tsc_khz == 0)) {
1747 local_irq_restore(flags);
1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1749 return 1;
1750 }
1751 if (!use_master_clock) {
1752 host_tsc = rdtsc();
1753 kernel_ns = get_kernel_ns();
1754 }
1755
1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1757
1758 /*
1759 * We may have to catch up the TSC to match elapsed wall clock
1760 * time for two reasons, even if kvmclock is used.
1761 * 1) CPU could have been running below the maximum TSC rate
1762 * 2) Broken TSC compensation resets the base at each VCPU
1763 * entry to avoid unknown leaps of TSC even when running
1764 * again on the same CPU. This may cause apparent elapsed
1765 * time to disappear, and the guest to stand still or run
1766 * very slowly.
1767 */
1768 if (vcpu->tsc_catchup) {
1769 u64 tsc = compute_guest_tsc(v, kernel_ns);
1770 if (tsc > tsc_timestamp) {
1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1772 tsc_timestamp = tsc;
1773 }
1774 }
1775
1776 local_irq_restore(flags);
1777
1778 if (!vcpu->pv_time_enabled)
1779 return 0;
1780
1781 if (kvm_has_tsc_control)
1782 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1783
1784 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1785 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1786 &vcpu->hv_clock.tsc_shift,
1787 &vcpu->hv_clock.tsc_to_system_mul);
1788 vcpu->hw_tsc_khz = tgt_tsc_khz;
1789 }
1790
1791 /* With all the info we got, fill in the values */
1792 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1793 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1794 vcpu->last_guest_tsc = tsc_timestamp;
1795
1796 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1797 &guest_hv_clock, sizeof(guest_hv_clock))))
1798 return 0;
1799
1800 /* This VCPU is paused, but it's legal for a guest to read another
1801 * VCPU's kvmclock, so we really have to follow the specification where
1802 * it says that version is odd if data is being modified, and even after
1803 * it is consistent.
1804 *
1805 * Version field updates must be kept separate. This is because
1806 * kvm_write_guest_cached might use a "rep movs" instruction, and
1807 * writes within a string instruction are weakly ordered. So there
1808 * are three writes overall.
1809 *
1810 * As a small optimization, only write the version field in the first
1811 * and third write. The vcpu->pv_time cache is still valid, because the
1812 * version field is the first in the struct.
1813 */
1814 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1815
1816 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1817 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1818 &vcpu->hv_clock,
1819 sizeof(vcpu->hv_clock.version));
1820
1821 smp_wmb();
1822
1823 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1824 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1825
1826 if (vcpu->pvclock_set_guest_stopped_request) {
1827 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1828 vcpu->pvclock_set_guest_stopped_request = false;
1829 }
1830
1831 /* If the host uses TSC clocksource, then it is stable */
1832 if (use_master_clock)
1833 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1834
1835 vcpu->hv_clock.flags = pvclock_flags;
1836
1837 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1838
1839 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1840 &vcpu->hv_clock,
1841 sizeof(vcpu->hv_clock));
1842
1843 smp_wmb();
1844
1845 vcpu->hv_clock.version++;
1846 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1847 &vcpu->hv_clock,
1848 sizeof(vcpu->hv_clock.version));
1849 return 0;
1850 }
1851
1852 /*
1853 * kvmclock updates which are isolated to a given vcpu, such as
1854 * vcpu->cpu migration, should not allow system_timestamp from
1855 * the rest of the vcpus to remain static. Otherwise ntp frequency
1856 * correction applies to one vcpu's system_timestamp but not
1857 * the others.
1858 *
1859 * So in those cases, request a kvmclock update for all vcpus.
1860 * We need to rate-limit these requests though, as they can
1861 * considerably slow guests that have a large number of vcpus.
1862 * The time for a remote vcpu to update its kvmclock is bound
1863 * by the delay we use to rate-limit the updates.
1864 */
1865
1866 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1867
1868 static void kvmclock_update_fn(struct work_struct *work)
1869 {
1870 int i;
1871 struct delayed_work *dwork = to_delayed_work(work);
1872 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1873 kvmclock_update_work);
1874 struct kvm *kvm = container_of(ka, struct kvm, arch);
1875 struct kvm_vcpu *vcpu;
1876
1877 kvm_for_each_vcpu(i, vcpu, kvm) {
1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1879 kvm_vcpu_kick(vcpu);
1880 }
1881 }
1882
1883 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1884 {
1885 struct kvm *kvm = v->kvm;
1886
1887 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1888 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1889 KVMCLOCK_UPDATE_DELAY);
1890 }
1891
1892 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1893
1894 static void kvmclock_sync_fn(struct work_struct *work)
1895 {
1896 struct delayed_work *dwork = to_delayed_work(work);
1897 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1898 kvmclock_sync_work);
1899 struct kvm *kvm = container_of(ka, struct kvm, arch);
1900
1901 if (!kvmclock_periodic_sync)
1902 return;
1903
1904 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1905 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1906 KVMCLOCK_SYNC_PERIOD);
1907 }
1908
1909 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1910 {
1911 u64 mcg_cap = vcpu->arch.mcg_cap;
1912 unsigned bank_num = mcg_cap & 0xff;
1913
1914 switch (msr) {
1915 case MSR_IA32_MCG_STATUS:
1916 vcpu->arch.mcg_status = data;
1917 break;
1918 case MSR_IA32_MCG_CTL:
1919 if (!(mcg_cap & MCG_CTL_P))
1920 return 1;
1921 if (data != 0 && data != ~(u64)0)
1922 return -1;
1923 vcpu->arch.mcg_ctl = data;
1924 break;
1925 default:
1926 if (msr >= MSR_IA32_MC0_CTL &&
1927 msr < MSR_IA32_MCx_CTL(bank_num)) {
1928 u32 offset = msr - MSR_IA32_MC0_CTL;
1929 /* only 0 or all 1s can be written to IA32_MCi_CTL
1930 * some Linux kernels though clear bit 10 in bank 4 to
1931 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1932 * this to avoid an uncatched #GP in the guest
1933 */
1934 if ((offset & 0x3) == 0 &&
1935 data != 0 && (data | (1 << 10)) != ~(u64)0)
1936 return -1;
1937 vcpu->arch.mce_banks[offset] = data;
1938 break;
1939 }
1940 return 1;
1941 }
1942 return 0;
1943 }
1944
1945 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1946 {
1947 struct kvm *kvm = vcpu->kvm;
1948 int lm = is_long_mode(vcpu);
1949 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1950 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1951 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1952 : kvm->arch.xen_hvm_config.blob_size_32;
1953 u32 page_num = data & ~PAGE_MASK;
1954 u64 page_addr = data & PAGE_MASK;
1955 u8 *page;
1956 int r;
1957
1958 r = -E2BIG;
1959 if (page_num >= blob_size)
1960 goto out;
1961 r = -ENOMEM;
1962 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1963 if (IS_ERR(page)) {
1964 r = PTR_ERR(page);
1965 goto out;
1966 }
1967 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1968 goto out_free;
1969 r = 0;
1970 out_free:
1971 kfree(page);
1972 out:
1973 return r;
1974 }
1975
1976 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1977 {
1978 gpa_t gpa = data & ~0x3f;
1979
1980 /* Bits 2:5 are reserved, Should be zero */
1981 if (data & 0x3c)
1982 return 1;
1983
1984 vcpu->arch.apf.msr_val = data;
1985
1986 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1987 kvm_clear_async_pf_completion_queue(vcpu);
1988 kvm_async_pf_hash_reset(vcpu);
1989 return 0;
1990 }
1991
1992 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1993 sizeof(u32)))
1994 return 1;
1995
1996 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1997 kvm_async_pf_wakeup_all(vcpu);
1998 return 0;
1999 }
2000
2001 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2002 {
2003 vcpu->arch.pv_time_enabled = false;
2004 }
2005
2006 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2007 {
2008 u64 delta;
2009
2010 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2011 return;
2012
2013 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2014 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2015 vcpu->arch.st.accum_steal = delta;
2016 }
2017
2018 static void record_steal_time(struct kvm_vcpu *vcpu)
2019 {
2020 accumulate_steal_time(vcpu);
2021
2022 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2023 return;
2024
2025 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2026 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2027 return;
2028
2029 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2030 vcpu->arch.st.steal.version += 2;
2031 vcpu->arch.st.accum_steal = 0;
2032
2033 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2034 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2035 }
2036
2037 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2038 {
2039 bool pr = false;
2040 u32 msr = msr_info->index;
2041 u64 data = msr_info->data;
2042
2043 switch (msr) {
2044 case MSR_AMD64_NB_CFG:
2045 case MSR_IA32_UCODE_REV:
2046 case MSR_IA32_UCODE_WRITE:
2047 case MSR_VM_HSAVE_PA:
2048 case MSR_AMD64_PATCH_LOADER:
2049 case MSR_AMD64_BU_CFG2:
2050 break;
2051
2052 case MSR_EFER:
2053 return set_efer(vcpu, data);
2054 case MSR_K7_HWCR:
2055 data &= ~(u64)0x40; /* ignore flush filter disable */
2056 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2057 data &= ~(u64)0x8; /* ignore TLB cache disable */
2058 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2059 if (data != 0) {
2060 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2061 data);
2062 return 1;
2063 }
2064 break;
2065 case MSR_FAM10H_MMIO_CONF_BASE:
2066 if (data != 0) {
2067 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2068 "0x%llx\n", data);
2069 return 1;
2070 }
2071 break;
2072 case MSR_IA32_DEBUGCTLMSR:
2073 if (!data) {
2074 /* We support the non-activated case already */
2075 break;
2076 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2077 /* Values other than LBR and BTF are vendor-specific,
2078 thus reserved and should throw a #GP */
2079 return 1;
2080 }
2081 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2082 __func__, data);
2083 break;
2084 case 0x200 ... 0x2ff:
2085 return kvm_mtrr_set_msr(vcpu, msr, data);
2086 case MSR_IA32_APICBASE:
2087 return kvm_set_apic_base(vcpu, msr_info);
2088 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2089 return kvm_x2apic_msr_write(vcpu, msr, data);
2090 case MSR_IA32_TSCDEADLINE:
2091 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2092 break;
2093 case MSR_IA32_TSC_ADJUST:
2094 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2095 if (!msr_info->host_initiated) {
2096 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2097 adjust_tsc_offset_guest(vcpu, adj);
2098 }
2099 vcpu->arch.ia32_tsc_adjust_msr = data;
2100 }
2101 break;
2102 case MSR_IA32_MISC_ENABLE:
2103 vcpu->arch.ia32_misc_enable_msr = data;
2104 break;
2105 case MSR_IA32_SMBASE:
2106 if (!msr_info->host_initiated)
2107 return 1;
2108 vcpu->arch.smbase = data;
2109 break;
2110 case MSR_KVM_WALL_CLOCK_NEW:
2111 case MSR_KVM_WALL_CLOCK:
2112 vcpu->kvm->arch.wall_clock = data;
2113 kvm_write_wall_clock(vcpu->kvm, data);
2114 break;
2115 case MSR_KVM_SYSTEM_TIME_NEW:
2116 case MSR_KVM_SYSTEM_TIME: {
2117 u64 gpa_offset;
2118 struct kvm_arch *ka = &vcpu->kvm->arch;
2119
2120 kvmclock_reset(vcpu);
2121
2122 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2123 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2124
2125 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2126 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2127 &vcpu->requests);
2128
2129 ka->boot_vcpu_runs_old_kvmclock = tmp;
2130 }
2131
2132 vcpu->arch.time = data;
2133 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2134
2135 /* we verify if the enable bit is set... */
2136 if (!(data & 1))
2137 break;
2138
2139 gpa_offset = data & ~(PAGE_MASK | 1);
2140
2141 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2142 &vcpu->arch.pv_time, data & ~1ULL,
2143 sizeof(struct pvclock_vcpu_time_info)))
2144 vcpu->arch.pv_time_enabled = false;
2145 else
2146 vcpu->arch.pv_time_enabled = true;
2147
2148 break;
2149 }
2150 case MSR_KVM_ASYNC_PF_EN:
2151 if (kvm_pv_enable_async_pf(vcpu, data))
2152 return 1;
2153 break;
2154 case MSR_KVM_STEAL_TIME:
2155
2156 if (unlikely(!sched_info_on()))
2157 return 1;
2158
2159 if (data & KVM_STEAL_RESERVED_MASK)
2160 return 1;
2161
2162 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2163 data & KVM_STEAL_VALID_BITS,
2164 sizeof(struct kvm_steal_time)))
2165 return 1;
2166
2167 vcpu->arch.st.msr_val = data;
2168
2169 if (!(data & KVM_MSR_ENABLED))
2170 break;
2171
2172 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2173
2174 break;
2175 case MSR_KVM_PV_EOI_EN:
2176 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2177 return 1;
2178 break;
2179
2180 case MSR_IA32_MCG_CTL:
2181 case MSR_IA32_MCG_STATUS:
2182 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2183 return set_msr_mce(vcpu, msr, data);
2184
2185 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2186 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2187 pr = true; /* fall through */
2188 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2189 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2190 if (kvm_pmu_is_valid_msr(vcpu, msr))
2191 return kvm_pmu_set_msr(vcpu, msr_info);
2192
2193 if (pr || data != 0)
2194 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2195 "0x%x data 0x%llx\n", msr, data);
2196 break;
2197 case MSR_K7_CLK_CTL:
2198 /*
2199 * Ignore all writes to this no longer documented MSR.
2200 * Writes are only relevant for old K7 processors,
2201 * all pre-dating SVM, but a recommended workaround from
2202 * AMD for these chips. It is possible to specify the
2203 * affected processor models on the command line, hence
2204 * the need to ignore the workaround.
2205 */
2206 break;
2207 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2208 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2209 case HV_X64_MSR_CRASH_CTL:
2210 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2211 return kvm_hv_set_msr_common(vcpu, msr, data,
2212 msr_info->host_initiated);
2213 case MSR_IA32_BBL_CR_CTL3:
2214 /* Drop writes to this legacy MSR -- see rdmsr
2215 * counterpart for further detail.
2216 */
2217 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2218 break;
2219 case MSR_AMD64_OSVW_ID_LENGTH:
2220 if (!guest_cpuid_has_osvw(vcpu))
2221 return 1;
2222 vcpu->arch.osvw.length = data;
2223 break;
2224 case MSR_AMD64_OSVW_STATUS:
2225 if (!guest_cpuid_has_osvw(vcpu))
2226 return 1;
2227 vcpu->arch.osvw.status = data;
2228 break;
2229 default:
2230 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2231 return xen_hvm_config(vcpu, data);
2232 if (kvm_pmu_is_valid_msr(vcpu, msr))
2233 return kvm_pmu_set_msr(vcpu, msr_info);
2234 if (!ignore_msrs) {
2235 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2236 msr, data);
2237 return 1;
2238 } else {
2239 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2240 msr, data);
2241 break;
2242 }
2243 }
2244 return 0;
2245 }
2246 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2247
2248
2249 /*
2250 * Reads an msr value (of 'msr_index') into 'pdata'.
2251 * Returns 0 on success, non-0 otherwise.
2252 * Assumes vcpu_load() was already called.
2253 */
2254 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2255 {
2256 return kvm_x86_ops->get_msr(vcpu, msr);
2257 }
2258 EXPORT_SYMBOL_GPL(kvm_get_msr);
2259
2260 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2261 {
2262 u64 data;
2263 u64 mcg_cap = vcpu->arch.mcg_cap;
2264 unsigned bank_num = mcg_cap & 0xff;
2265
2266 switch (msr) {
2267 case MSR_IA32_P5_MC_ADDR:
2268 case MSR_IA32_P5_MC_TYPE:
2269 data = 0;
2270 break;
2271 case MSR_IA32_MCG_CAP:
2272 data = vcpu->arch.mcg_cap;
2273 break;
2274 case MSR_IA32_MCG_CTL:
2275 if (!(mcg_cap & MCG_CTL_P))
2276 return 1;
2277 data = vcpu->arch.mcg_ctl;
2278 break;
2279 case MSR_IA32_MCG_STATUS:
2280 data = vcpu->arch.mcg_status;
2281 break;
2282 default:
2283 if (msr >= MSR_IA32_MC0_CTL &&
2284 msr < MSR_IA32_MCx_CTL(bank_num)) {
2285 u32 offset = msr - MSR_IA32_MC0_CTL;
2286 data = vcpu->arch.mce_banks[offset];
2287 break;
2288 }
2289 return 1;
2290 }
2291 *pdata = data;
2292 return 0;
2293 }
2294
2295 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2296 {
2297 switch (msr_info->index) {
2298 case MSR_IA32_PLATFORM_ID:
2299 case MSR_IA32_EBL_CR_POWERON:
2300 case MSR_IA32_DEBUGCTLMSR:
2301 case MSR_IA32_LASTBRANCHFROMIP:
2302 case MSR_IA32_LASTBRANCHTOIP:
2303 case MSR_IA32_LASTINTFROMIP:
2304 case MSR_IA32_LASTINTTOIP:
2305 case MSR_K8_SYSCFG:
2306 case MSR_K8_TSEG_ADDR:
2307 case MSR_K8_TSEG_MASK:
2308 case MSR_K7_HWCR:
2309 case MSR_VM_HSAVE_PA:
2310 case MSR_K8_INT_PENDING_MSG:
2311 case MSR_AMD64_NB_CFG:
2312 case MSR_FAM10H_MMIO_CONF_BASE:
2313 case MSR_AMD64_BU_CFG2:
2314 msr_info->data = 0;
2315 break;
2316 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2317 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2318 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2319 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2320 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2321 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2322 msr_info->data = 0;
2323 break;
2324 case MSR_IA32_UCODE_REV:
2325 msr_info->data = 0x100000000ULL;
2326 break;
2327 case MSR_MTRRcap:
2328 case 0x200 ... 0x2ff:
2329 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2330 case 0xcd: /* fsb frequency */
2331 msr_info->data = 3;
2332 break;
2333 /*
2334 * MSR_EBC_FREQUENCY_ID
2335 * Conservative value valid for even the basic CPU models.
2336 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2337 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2338 * and 266MHz for model 3, or 4. Set Core Clock
2339 * Frequency to System Bus Frequency Ratio to 1 (bits
2340 * 31:24) even though these are only valid for CPU
2341 * models > 2, however guests may end up dividing or
2342 * multiplying by zero otherwise.
2343 */
2344 case MSR_EBC_FREQUENCY_ID:
2345 msr_info->data = 1 << 24;
2346 break;
2347 case MSR_IA32_APICBASE:
2348 msr_info->data = kvm_get_apic_base(vcpu);
2349 break;
2350 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2351 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2352 break;
2353 case MSR_IA32_TSCDEADLINE:
2354 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2355 break;
2356 case MSR_IA32_TSC_ADJUST:
2357 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2358 break;
2359 case MSR_IA32_MISC_ENABLE:
2360 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2361 break;
2362 case MSR_IA32_SMBASE:
2363 if (!msr_info->host_initiated)
2364 return 1;
2365 msr_info->data = vcpu->arch.smbase;
2366 break;
2367 case MSR_IA32_PERF_STATUS:
2368 /* TSC increment by tick */
2369 msr_info->data = 1000ULL;
2370 /* CPU multiplier */
2371 msr_info->data |= (((uint64_t)4ULL) << 40);
2372 break;
2373 case MSR_EFER:
2374 msr_info->data = vcpu->arch.efer;
2375 break;
2376 case MSR_KVM_WALL_CLOCK:
2377 case MSR_KVM_WALL_CLOCK_NEW:
2378 msr_info->data = vcpu->kvm->arch.wall_clock;
2379 break;
2380 case MSR_KVM_SYSTEM_TIME:
2381 case MSR_KVM_SYSTEM_TIME_NEW:
2382 msr_info->data = vcpu->arch.time;
2383 break;
2384 case MSR_KVM_ASYNC_PF_EN:
2385 msr_info->data = vcpu->arch.apf.msr_val;
2386 break;
2387 case MSR_KVM_STEAL_TIME:
2388 msr_info->data = vcpu->arch.st.msr_val;
2389 break;
2390 case MSR_KVM_PV_EOI_EN:
2391 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2392 break;
2393 case MSR_IA32_P5_MC_ADDR:
2394 case MSR_IA32_P5_MC_TYPE:
2395 case MSR_IA32_MCG_CAP:
2396 case MSR_IA32_MCG_CTL:
2397 case MSR_IA32_MCG_STATUS:
2398 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2399 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2400 case MSR_K7_CLK_CTL:
2401 /*
2402 * Provide expected ramp-up count for K7. All other
2403 * are set to zero, indicating minimum divisors for
2404 * every field.
2405 *
2406 * This prevents guest kernels on AMD host with CPU
2407 * type 6, model 8 and higher from exploding due to
2408 * the rdmsr failing.
2409 */
2410 msr_info->data = 0x20000000;
2411 break;
2412 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2413 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2414 case HV_X64_MSR_CRASH_CTL:
2415 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2416 return kvm_hv_get_msr_common(vcpu,
2417 msr_info->index, &msr_info->data);
2418 break;
2419 case MSR_IA32_BBL_CR_CTL3:
2420 /* This legacy MSR exists but isn't fully documented in current
2421 * silicon. It is however accessed by winxp in very narrow
2422 * scenarios where it sets bit #19, itself documented as
2423 * a "reserved" bit. Best effort attempt to source coherent
2424 * read data here should the balance of the register be
2425 * interpreted by the guest:
2426 *
2427 * L2 cache control register 3: 64GB range, 256KB size,
2428 * enabled, latency 0x1, configured
2429 */
2430 msr_info->data = 0xbe702111;
2431 break;
2432 case MSR_AMD64_OSVW_ID_LENGTH:
2433 if (!guest_cpuid_has_osvw(vcpu))
2434 return 1;
2435 msr_info->data = vcpu->arch.osvw.length;
2436 break;
2437 case MSR_AMD64_OSVW_STATUS:
2438 if (!guest_cpuid_has_osvw(vcpu))
2439 return 1;
2440 msr_info->data = vcpu->arch.osvw.status;
2441 break;
2442 default:
2443 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2444 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2445 if (!ignore_msrs) {
2446 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2447 return 1;
2448 } else {
2449 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2450 msr_info->data = 0;
2451 }
2452 break;
2453 }
2454 return 0;
2455 }
2456 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2457
2458 /*
2459 * Read or write a bunch of msrs. All parameters are kernel addresses.
2460 *
2461 * @return number of msrs set successfully.
2462 */
2463 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2464 struct kvm_msr_entry *entries,
2465 int (*do_msr)(struct kvm_vcpu *vcpu,
2466 unsigned index, u64 *data))
2467 {
2468 int i, idx;
2469
2470 idx = srcu_read_lock(&vcpu->kvm->srcu);
2471 for (i = 0; i < msrs->nmsrs; ++i)
2472 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2473 break;
2474 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2475
2476 return i;
2477 }
2478
2479 /*
2480 * Read or write a bunch of msrs. Parameters are user addresses.
2481 *
2482 * @return number of msrs set successfully.
2483 */
2484 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2485 int (*do_msr)(struct kvm_vcpu *vcpu,
2486 unsigned index, u64 *data),
2487 int writeback)
2488 {
2489 struct kvm_msrs msrs;
2490 struct kvm_msr_entry *entries;
2491 int r, n;
2492 unsigned size;
2493
2494 r = -EFAULT;
2495 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2496 goto out;
2497
2498 r = -E2BIG;
2499 if (msrs.nmsrs >= MAX_IO_MSRS)
2500 goto out;
2501
2502 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2503 entries = memdup_user(user_msrs->entries, size);
2504 if (IS_ERR(entries)) {
2505 r = PTR_ERR(entries);
2506 goto out;
2507 }
2508
2509 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2510 if (r < 0)
2511 goto out_free;
2512
2513 r = -EFAULT;
2514 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2515 goto out_free;
2516
2517 r = n;
2518
2519 out_free:
2520 kfree(entries);
2521 out:
2522 return r;
2523 }
2524
2525 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2526 {
2527 int r;
2528
2529 switch (ext) {
2530 case KVM_CAP_IRQCHIP:
2531 case KVM_CAP_HLT:
2532 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2533 case KVM_CAP_SET_TSS_ADDR:
2534 case KVM_CAP_EXT_CPUID:
2535 case KVM_CAP_EXT_EMUL_CPUID:
2536 case KVM_CAP_CLOCKSOURCE:
2537 case KVM_CAP_PIT:
2538 case KVM_CAP_NOP_IO_DELAY:
2539 case KVM_CAP_MP_STATE:
2540 case KVM_CAP_SYNC_MMU:
2541 case KVM_CAP_USER_NMI:
2542 case KVM_CAP_REINJECT_CONTROL:
2543 case KVM_CAP_IRQ_INJECT_STATUS:
2544 case KVM_CAP_IOEVENTFD:
2545 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2546 case KVM_CAP_PIT2:
2547 case KVM_CAP_PIT_STATE2:
2548 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2549 case KVM_CAP_XEN_HVM:
2550 case KVM_CAP_ADJUST_CLOCK:
2551 case KVM_CAP_VCPU_EVENTS:
2552 case KVM_CAP_HYPERV:
2553 case KVM_CAP_HYPERV_VAPIC:
2554 case KVM_CAP_HYPERV_SPIN:
2555 case KVM_CAP_HYPERV_SYNIC:
2556 case KVM_CAP_PCI_SEGMENT:
2557 case KVM_CAP_DEBUGREGS:
2558 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2559 case KVM_CAP_XSAVE:
2560 case KVM_CAP_ASYNC_PF:
2561 case KVM_CAP_GET_TSC_KHZ:
2562 case KVM_CAP_KVMCLOCK_CTRL:
2563 case KVM_CAP_READONLY_MEM:
2564 case KVM_CAP_HYPERV_TIME:
2565 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2566 case KVM_CAP_TSC_DEADLINE_TIMER:
2567 case KVM_CAP_ENABLE_CAP_VM:
2568 case KVM_CAP_DISABLE_QUIRKS:
2569 case KVM_CAP_SET_BOOT_CPU_ID:
2570 case KVM_CAP_SPLIT_IRQCHIP:
2571 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2572 case KVM_CAP_ASSIGN_DEV_IRQ:
2573 case KVM_CAP_PCI_2_3:
2574 #endif
2575 r = 1;
2576 break;
2577 case KVM_CAP_X86_SMM:
2578 /* SMBASE is usually relocated above 1M on modern chipsets,
2579 * and SMM handlers might indeed rely on 4G segment limits,
2580 * so do not report SMM to be available if real mode is
2581 * emulated via vm86 mode. Still, do not go to great lengths
2582 * to avoid userspace's usage of the feature, because it is a
2583 * fringe case that is not enabled except via specific settings
2584 * of the module parameters.
2585 */
2586 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2587 break;
2588 case KVM_CAP_COALESCED_MMIO:
2589 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2590 break;
2591 case KVM_CAP_VAPIC:
2592 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2593 break;
2594 case KVM_CAP_NR_VCPUS:
2595 r = KVM_SOFT_MAX_VCPUS;
2596 break;
2597 case KVM_CAP_MAX_VCPUS:
2598 r = KVM_MAX_VCPUS;
2599 break;
2600 case KVM_CAP_NR_MEMSLOTS:
2601 r = KVM_USER_MEM_SLOTS;
2602 break;
2603 case KVM_CAP_PV_MMU: /* obsolete */
2604 r = 0;
2605 break;
2606 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2607 case KVM_CAP_IOMMU:
2608 r = iommu_present(&pci_bus_type);
2609 break;
2610 #endif
2611 case KVM_CAP_MCE:
2612 r = KVM_MAX_MCE_BANKS;
2613 break;
2614 case KVM_CAP_XCRS:
2615 r = cpu_has_xsave;
2616 break;
2617 case KVM_CAP_TSC_CONTROL:
2618 r = kvm_has_tsc_control;
2619 break;
2620 default:
2621 r = 0;
2622 break;
2623 }
2624 return r;
2625
2626 }
2627
2628 long kvm_arch_dev_ioctl(struct file *filp,
2629 unsigned int ioctl, unsigned long arg)
2630 {
2631 void __user *argp = (void __user *)arg;
2632 long r;
2633
2634 switch (ioctl) {
2635 case KVM_GET_MSR_INDEX_LIST: {
2636 struct kvm_msr_list __user *user_msr_list = argp;
2637 struct kvm_msr_list msr_list;
2638 unsigned n;
2639
2640 r = -EFAULT;
2641 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2642 goto out;
2643 n = msr_list.nmsrs;
2644 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2645 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2646 goto out;
2647 r = -E2BIG;
2648 if (n < msr_list.nmsrs)
2649 goto out;
2650 r = -EFAULT;
2651 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2652 num_msrs_to_save * sizeof(u32)))
2653 goto out;
2654 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2655 &emulated_msrs,
2656 num_emulated_msrs * sizeof(u32)))
2657 goto out;
2658 r = 0;
2659 break;
2660 }
2661 case KVM_GET_SUPPORTED_CPUID:
2662 case KVM_GET_EMULATED_CPUID: {
2663 struct kvm_cpuid2 __user *cpuid_arg = argp;
2664 struct kvm_cpuid2 cpuid;
2665
2666 r = -EFAULT;
2667 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2668 goto out;
2669
2670 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2671 ioctl);
2672 if (r)
2673 goto out;
2674
2675 r = -EFAULT;
2676 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2677 goto out;
2678 r = 0;
2679 break;
2680 }
2681 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2682 u64 mce_cap;
2683
2684 mce_cap = KVM_MCE_CAP_SUPPORTED;
2685 r = -EFAULT;
2686 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2687 goto out;
2688 r = 0;
2689 break;
2690 }
2691 default:
2692 r = -EINVAL;
2693 }
2694 out:
2695 return r;
2696 }
2697
2698 static void wbinvd_ipi(void *garbage)
2699 {
2700 wbinvd();
2701 }
2702
2703 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2704 {
2705 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2706 }
2707
2708 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2709 {
2710 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2711 }
2712
2713 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2714 {
2715 /* Address WBINVD may be executed by guest */
2716 if (need_emulate_wbinvd(vcpu)) {
2717 if (kvm_x86_ops->has_wbinvd_exit())
2718 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2719 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2720 smp_call_function_single(vcpu->cpu,
2721 wbinvd_ipi, NULL, 1);
2722 }
2723
2724 kvm_x86_ops->vcpu_load(vcpu, cpu);
2725
2726 /* Apply any externally detected TSC adjustments (due to suspend) */
2727 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2728 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2729 vcpu->arch.tsc_offset_adjustment = 0;
2730 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2731 }
2732
2733 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2734 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2735 rdtsc() - vcpu->arch.last_host_tsc;
2736 if (tsc_delta < 0)
2737 mark_tsc_unstable("KVM discovered backwards TSC");
2738 if (check_tsc_unstable()) {
2739 u64 offset = kvm_compute_tsc_offset(vcpu,
2740 vcpu->arch.last_guest_tsc);
2741 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2742 vcpu->arch.tsc_catchup = 1;
2743 }
2744 /*
2745 * On a host with synchronized TSC, there is no need to update
2746 * kvmclock on vcpu->cpu migration
2747 */
2748 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2749 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2750 if (vcpu->cpu != cpu)
2751 kvm_migrate_timers(vcpu);
2752 vcpu->cpu = cpu;
2753 }
2754
2755 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2756 }
2757
2758 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2759 {
2760 kvm_x86_ops->vcpu_put(vcpu);
2761 kvm_put_guest_fpu(vcpu);
2762 vcpu->arch.last_host_tsc = rdtsc();
2763 }
2764
2765 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2766 struct kvm_lapic_state *s)
2767 {
2768 if (vcpu->arch.apicv_active)
2769 kvm_x86_ops->sync_pir_to_irr(vcpu);
2770
2771 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2772
2773 return 0;
2774 }
2775
2776 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2777 struct kvm_lapic_state *s)
2778 {
2779 kvm_apic_post_state_restore(vcpu, s);
2780 update_cr8_intercept(vcpu);
2781
2782 return 0;
2783 }
2784
2785 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2786 {
2787 return (!lapic_in_kernel(vcpu) ||
2788 kvm_apic_accept_pic_intr(vcpu));
2789 }
2790
2791 /*
2792 * if userspace requested an interrupt window, check that the
2793 * interrupt window is open.
2794 *
2795 * No need to exit to userspace if we already have an interrupt queued.
2796 */
2797 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2798 {
2799 return kvm_arch_interrupt_allowed(vcpu) &&
2800 !kvm_cpu_has_interrupt(vcpu) &&
2801 !kvm_event_needs_reinjection(vcpu) &&
2802 kvm_cpu_accept_dm_intr(vcpu);
2803 }
2804
2805 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2806 struct kvm_interrupt *irq)
2807 {
2808 if (irq->irq >= KVM_NR_INTERRUPTS)
2809 return -EINVAL;
2810
2811 if (!irqchip_in_kernel(vcpu->kvm)) {
2812 kvm_queue_interrupt(vcpu, irq->irq, false);
2813 kvm_make_request(KVM_REQ_EVENT, vcpu);
2814 return 0;
2815 }
2816
2817 /*
2818 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2819 * fail for in-kernel 8259.
2820 */
2821 if (pic_in_kernel(vcpu->kvm))
2822 return -ENXIO;
2823
2824 if (vcpu->arch.pending_external_vector != -1)
2825 return -EEXIST;
2826
2827 vcpu->arch.pending_external_vector = irq->irq;
2828 kvm_make_request(KVM_REQ_EVENT, vcpu);
2829 return 0;
2830 }
2831
2832 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2833 {
2834 kvm_inject_nmi(vcpu);
2835
2836 return 0;
2837 }
2838
2839 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2840 {
2841 kvm_make_request(KVM_REQ_SMI, vcpu);
2842
2843 return 0;
2844 }
2845
2846 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2847 struct kvm_tpr_access_ctl *tac)
2848 {
2849 if (tac->flags)
2850 return -EINVAL;
2851 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2852 return 0;
2853 }
2854
2855 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2856 u64 mcg_cap)
2857 {
2858 int r;
2859 unsigned bank_num = mcg_cap & 0xff, bank;
2860
2861 r = -EINVAL;
2862 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2863 goto out;
2864 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2865 goto out;
2866 r = 0;
2867 vcpu->arch.mcg_cap = mcg_cap;
2868 /* Init IA32_MCG_CTL to all 1s */
2869 if (mcg_cap & MCG_CTL_P)
2870 vcpu->arch.mcg_ctl = ~(u64)0;
2871 /* Init IA32_MCi_CTL to all 1s */
2872 for (bank = 0; bank < bank_num; bank++)
2873 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2874 out:
2875 return r;
2876 }
2877
2878 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2879 struct kvm_x86_mce *mce)
2880 {
2881 u64 mcg_cap = vcpu->arch.mcg_cap;
2882 unsigned bank_num = mcg_cap & 0xff;
2883 u64 *banks = vcpu->arch.mce_banks;
2884
2885 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2886 return -EINVAL;
2887 /*
2888 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2889 * reporting is disabled
2890 */
2891 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2892 vcpu->arch.mcg_ctl != ~(u64)0)
2893 return 0;
2894 banks += 4 * mce->bank;
2895 /*
2896 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2897 * reporting is disabled for the bank
2898 */
2899 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2900 return 0;
2901 if (mce->status & MCI_STATUS_UC) {
2902 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2903 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2904 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2905 return 0;
2906 }
2907 if (banks[1] & MCI_STATUS_VAL)
2908 mce->status |= MCI_STATUS_OVER;
2909 banks[2] = mce->addr;
2910 banks[3] = mce->misc;
2911 vcpu->arch.mcg_status = mce->mcg_status;
2912 banks[1] = mce->status;
2913 kvm_queue_exception(vcpu, MC_VECTOR);
2914 } else if (!(banks[1] & MCI_STATUS_VAL)
2915 || !(banks[1] & MCI_STATUS_UC)) {
2916 if (banks[1] & MCI_STATUS_VAL)
2917 mce->status |= MCI_STATUS_OVER;
2918 banks[2] = mce->addr;
2919 banks[3] = mce->misc;
2920 banks[1] = mce->status;
2921 } else
2922 banks[1] |= MCI_STATUS_OVER;
2923 return 0;
2924 }
2925
2926 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2927 struct kvm_vcpu_events *events)
2928 {
2929 process_nmi(vcpu);
2930 events->exception.injected =
2931 vcpu->arch.exception.pending &&
2932 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2933 events->exception.nr = vcpu->arch.exception.nr;
2934 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2935 events->exception.pad = 0;
2936 events->exception.error_code = vcpu->arch.exception.error_code;
2937
2938 events->interrupt.injected =
2939 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2940 events->interrupt.nr = vcpu->arch.interrupt.nr;
2941 events->interrupt.soft = 0;
2942 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2943
2944 events->nmi.injected = vcpu->arch.nmi_injected;
2945 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2946 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2947 events->nmi.pad = 0;
2948
2949 events->sipi_vector = 0; /* never valid when reporting to user space */
2950
2951 events->smi.smm = is_smm(vcpu);
2952 events->smi.pending = vcpu->arch.smi_pending;
2953 events->smi.smm_inside_nmi =
2954 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2955 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2956
2957 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2958 | KVM_VCPUEVENT_VALID_SHADOW
2959 | KVM_VCPUEVENT_VALID_SMM);
2960 memset(&events->reserved, 0, sizeof(events->reserved));
2961 }
2962
2963 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2964 struct kvm_vcpu_events *events)
2965 {
2966 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2967 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2968 | KVM_VCPUEVENT_VALID_SHADOW
2969 | KVM_VCPUEVENT_VALID_SMM))
2970 return -EINVAL;
2971
2972 process_nmi(vcpu);
2973 vcpu->arch.exception.pending = events->exception.injected;
2974 vcpu->arch.exception.nr = events->exception.nr;
2975 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2976 vcpu->arch.exception.error_code = events->exception.error_code;
2977
2978 vcpu->arch.interrupt.pending = events->interrupt.injected;
2979 vcpu->arch.interrupt.nr = events->interrupt.nr;
2980 vcpu->arch.interrupt.soft = events->interrupt.soft;
2981 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2982 kvm_x86_ops->set_interrupt_shadow(vcpu,
2983 events->interrupt.shadow);
2984
2985 vcpu->arch.nmi_injected = events->nmi.injected;
2986 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2987 vcpu->arch.nmi_pending = events->nmi.pending;
2988 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2989
2990 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2991 lapic_in_kernel(vcpu))
2992 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2993
2994 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2995 if (events->smi.smm)
2996 vcpu->arch.hflags |= HF_SMM_MASK;
2997 else
2998 vcpu->arch.hflags &= ~HF_SMM_MASK;
2999 vcpu->arch.smi_pending = events->smi.pending;
3000 if (events->smi.smm_inside_nmi)
3001 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3002 else
3003 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3004 if (lapic_in_kernel(vcpu)) {
3005 if (events->smi.latched_init)
3006 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3007 else
3008 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3009 }
3010 }
3011
3012 kvm_make_request(KVM_REQ_EVENT, vcpu);
3013
3014 return 0;
3015 }
3016
3017 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3018 struct kvm_debugregs *dbgregs)
3019 {
3020 unsigned long val;
3021
3022 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3023 kvm_get_dr(vcpu, 6, &val);
3024 dbgregs->dr6 = val;
3025 dbgregs->dr7 = vcpu->arch.dr7;
3026 dbgregs->flags = 0;
3027 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3028 }
3029
3030 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3031 struct kvm_debugregs *dbgregs)
3032 {
3033 if (dbgregs->flags)
3034 return -EINVAL;
3035
3036 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3037 kvm_update_dr0123(vcpu);
3038 vcpu->arch.dr6 = dbgregs->dr6;
3039 kvm_update_dr6(vcpu);
3040 vcpu->arch.dr7 = dbgregs->dr7;
3041 kvm_update_dr7(vcpu);
3042
3043 return 0;
3044 }
3045
3046 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3047
3048 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3049 {
3050 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3051 u64 xstate_bv = xsave->header.xfeatures;
3052 u64 valid;
3053
3054 /*
3055 * Copy legacy XSAVE area, to avoid complications with CPUID
3056 * leaves 0 and 1 in the loop below.
3057 */
3058 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3059
3060 /* Set XSTATE_BV */
3061 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3062
3063 /*
3064 * Copy each region from the possibly compacted offset to the
3065 * non-compacted offset.
3066 */
3067 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3068 while (valid) {
3069 u64 feature = valid & -valid;
3070 int index = fls64(feature) - 1;
3071 void *src = get_xsave_addr(xsave, feature);
3072
3073 if (src) {
3074 u32 size, offset, ecx, edx;
3075 cpuid_count(XSTATE_CPUID, index,
3076 &size, &offset, &ecx, &edx);
3077 memcpy(dest + offset, src, size);
3078 }
3079
3080 valid -= feature;
3081 }
3082 }
3083
3084 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3085 {
3086 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3087 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3088 u64 valid;
3089
3090 /*
3091 * Copy legacy XSAVE area, to avoid complications with CPUID
3092 * leaves 0 and 1 in the loop below.
3093 */
3094 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3095
3096 /* Set XSTATE_BV and possibly XCOMP_BV. */
3097 xsave->header.xfeatures = xstate_bv;
3098 if (cpu_has_xsaves)
3099 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3100
3101 /*
3102 * Copy each region from the non-compacted offset to the
3103 * possibly compacted offset.
3104 */
3105 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3106 while (valid) {
3107 u64 feature = valid & -valid;
3108 int index = fls64(feature) - 1;
3109 void *dest = get_xsave_addr(xsave, feature);
3110
3111 if (dest) {
3112 u32 size, offset, ecx, edx;
3113 cpuid_count(XSTATE_CPUID, index,
3114 &size, &offset, &ecx, &edx);
3115 memcpy(dest, src + offset, size);
3116 }
3117
3118 valid -= feature;
3119 }
3120 }
3121
3122 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3123 struct kvm_xsave *guest_xsave)
3124 {
3125 if (cpu_has_xsave) {
3126 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3127 fill_xsave((u8 *) guest_xsave->region, vcpu);
3128 } else {
3129 memcpy(guest_xsave->region,
3130 &vcpu->arch.guest_fpu.state.fxsave,
3131 sizeof(struct fxregs_state));
3132 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3133 XFEATURE_MASK_FPSSE;
3134 }
3135 }
3136
3137 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3138 struct kvm_xsave *guest_xsave)
3139 {
3140 u64 xstate_bv =
3141 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3142
3143 if (cpu_has_xsave) {
3144 /*
3145 * Here we allow setting states that are not present in
3146 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3147 * with old userspace.
3148 */
3149 if (xstate_bv & ~kvm_supported_xcr0())
3150 return -EINVAL;
3151 load_xsave(vcpu, (u8 *)guest_xsave->region);
3152 } else {
3153 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3154 return -EINVAL;
3155 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3156 guest_xsave->region, sizeof(struct fxregs_state));
3157 }
3158 return 0;
3159 }
3160
3161 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3162 struct kvm_xcrs *guest_xcrs)
3163 {
3164 if (!cpu_has_xsave) {
3165 guest_xcrs->nr_xcrs = 0;
3166 return;
3167 }
3168
3169 guest_xcrs->nr_xcrs = 1;
3170 guest_xcrs->flags = 0;
3171 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3172 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3173 }
3174
3175 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3176 struct kvm_xcrs *guest_xcrs)
3177 {
3178 int i, r = 0;
3179
3180 if (!cpu_has_xsave)
3181 return -EINVAL;
3182
3183 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3184 return -EINVAL;
3185
3186 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3187 /* Only support XCR0 currently */
3188 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3189 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3190 guest_xcrs->xcrs[i].value);
3191 break;
3192 }
3193 if (r)
3194 r = -EINVAL;
3195 return r;
3196 }
3197
3198 /*
3199 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3200 * stopped by the hypervisor. This function will be called from the host only.
3201 * EINVAL is returned when the host attempts to set the flag for a guest that
3202 * does not support pv clocks.
3203 */
3204 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3205 {
3206 if (!vcpu->arch.pv_time_enabled)
3207 return -EINVAL;
3208 vcpu->arch.pvclock_set_guest_stopped_request = true;
3209 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3210 return 0;
3211 }
3212
3213 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3214 struct kvm_enable_cap *cap)
3215 {
3216 if (cap->flags)
3217 return -EINVAL;
3218
3219 switch (cap->cap) {
3220 case KVM_CAP_HYPERV_SYNIC:
3221 return kvm_hv_activate_synic(vcpu);
3222 default:
3223 return -EINVAL;
3224 }
3225 }
3226
3227 long kvm_arch_vcpu_ioctl(struct file *filp,
3228 unsigned int ioctl, unsigned long arg)
3229 {
3230 struct kvm_vcpu *vcpu = filp->private_data;
3231 void __user *argp = (void __user *)arg;
3232 int r;
3233 union {
3234 struct kvm_lapic_state *lapic;
3235 struct kvm_xsave *xsave;
3236 struct kvm_xcrs *xcrs;
3237 void *buffer;
3238 } u;
3239
3240 u.buffer = NULL;
3241 switch (ioctl) {
3242 case KVM_GET_LAPIC: {
3243 r = -EINVAL;
3244 if (!lapic_in_kernel(vcpu))
3245 goto out;
3246 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3247
3248 r = -ENOMEM;
3249 if (!u.lapic)
3250 goto out;
3251 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3252 if (r)
3253 goto out;
3254 r = -EFAULT;
3255 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3256 goto out;
3257 r = 0;
3258 break;
3259 }
3260 case KVM_SET_LAPIC: {
3261 r = -EINVAL;
3262 if (!lapic_in_kernel(vcpu))
3263 goto out;
3264 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3265 if (IS_ERR(u.lapic))
3266 return PTR_ERR(u.lapic);
3267
3268 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3269 break;
3270 }
3271 case KVM_INTERRUPT: {
3272 struct kvm_interrupt irq;
3273
3274 r = -EFAULT;
3275 if (copy_from_user(&irq, argp, sizeof irq))
3276 goto out;
3277 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3278 break;
3279 }
3280 case KVM_NMI: {
3281 r = kvm_vcpu_ioctl_nmi(vcpu);
3282 break;
3283 }
3284 case KVM_SMI: {
3285 r = kvm_vcpu_ioctl_smi(vcpu);
3286 break;
3287 }
3288 case KVM_SET_CPUID: {
3289 struct kvm_cpuid __user *cpuid_arg = argp;
3290 struct kvm_cpuid cpuid;
3291
3292 r = -EFAULT;
3293 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3294 goto out;
3295 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3296 break;
3297 }
3298 case KVM_SET_CPUID2: {
3299 struct kvm_cpuid2 __user *cpuid_arg = argp;
3300 struct kvm_cpuid2 cpuid;
3301
3302 r = -EFAULT;
3303 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3304 goto out;
3305 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3306 cpuid_arg->entries);
3307 break;
3308 }
3309 case KVM_GET_CPUID2: {
3310 struct kvm_cpuid2 __user *cpuid_arg = argp;
3311 struct kvm_cpuid2 cpuid;
3312
3313 r = -EFAULT;
3314 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3315 goto out;
3316 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3317 cpuid_arg->entries);
3318 if (r)
3319 goto out;
3320 r = -EFAULT;
3321 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3322 goto out;
3323 r = 0;
3324 break;
3325 }
3326 case KVM_GET_MSRS:
3327 r = msr_io(vcpu, argp, do_get_msr, 1);
3328 break;
3329 case KVM_SET_MSRS:
3330 r = msr_io(vcpu, argp, do_set_msr, 0);
3331 break;
3332 case KVM_TPR_ACCESS_REPORTING: {
3333 struct kvm_tpr_access_ctl tac;
3334
3335 r = -EFAULT;
3336 if (copy_from_user(&tac, argp, sizeof tac))
3337 goto out;
3338 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3339 if (r)
3340 goto out;
3341 r = -EFAULT;
3342 if (copy_to_user(argp, &tac, sizeof tac))
3343 goto out;
3344 r = 0;
3345 break;
3346 };
3347 case KVM_SET_VAPIC_ADDR: {
3348 struct kvm_vapic_addr va;
3349
3350 r = -EINVAL;
3351 if (!lapic_in_kernel(vcpu))
3352 goto out;
3353 r = -EFAULT;
3354 if (copy_from_user(&va, argp, sizeof va))
3355 goto out;
3356 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3357 break;
3358 }
3359 case KVM_X86_SETUP_MCE: {
3360 u64 mcg_cap;
3361
3362 r = -EFAULT;
3363 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3364 goto out;
3365 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3366 break;
3367 }
3368 case KVM_X86_SET_MCE: {
3369 struct kvm_x86_mce mce;
3370
3371 r = -EFAULT;
3372 if (copy_from_user(&mce, argp, sizeof mce))
3373 goto out;
3374 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3375 break;
3376 }
3377 case KVM_GET_VCPU_EVENTS: {
3378 struct kvm_vcpu_events events;
3379
3380 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3381
3382 r = -EFAULT;
3383 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3384 break;
3385 r = 0;
3386 break;
3387 }
3388 case KVM_SET_VCPU_EVENTS: {
3389 struct kvm_vcpu_events events;
3390
3391 r = -EFAULT;
3392 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3393 break;
3394
3395 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3396 break;
3397 }
3398 case KVM_GET_DEBUGREGS: {
3399 struct kvm_debugregs dbgregs;
3400
3401 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3402
3403 r = -EFAULT;
3404 if (copy_to_user(argp, &dbgregs,
3405 sizeof(struct kvm_debugregs)))
3406 break;
3407 r = 0;
3408 break;
3409 }
3410 case KVM_SET_DEBUGREGS: {
3411 struct kvm_debugregs dbgregs;
3412
3413 r = -EFAULT;
3414 if (copy_from_user(&dbgregs, argp,
3415 sizeof(struct kvm_debugregs)))
3416 break;
3417
3418 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3419 break;
3420 }
3421 case KVM_GET_XSAVE: {
3422 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3423 r = -ENOMEM;
3424 if (!u.xsave)
3425 break;
3426
3427 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3428
3429 r = -EFAULT;
3430 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3431 break;
3432 r = 0;
3433 break;
3434 }
3435 case KVM_SET_XSAVE: {
3436 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3437 if (IS_ERR(u.xsave))
3438 return PTR_ERR(u.xsave);
3439
3440 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3441 break;
3442 }
3443 case KVM_GET_XCRS: {
3444 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3445 r = -ENOMEM;
3446 if (!u.xcrs)
3447 break;
3448
3449 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3450
3451 r = -EFAULT;
3452 if (copy_to_user(argp, u.xcrs,
3453 sizeof(struct kvm_xcrs)))
3454 break;
3455 r = 0;
3456 break;
3457 }
3458 case KVM_SET_XCRS: {
3459 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3460 if (IS_ERR(u.xcrs))
3461 return PTR_ERR(u.xcrs);
3462
3463 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3464 break;
3465 }
3466 case KVM_SET_TSC_KHZ: {
3467 u32 user_tsc_khz;
3468
3469 r = -EINVAL;
3470 user_tsc_khz = (u32)arg;
3471
3472 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3473 goto out;
3474
3475 if (user_tsc_khz == 0)
3476 user_tsc_khz = tsc_khz;
3477
3478 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3479 r = 0;
3480
3481 goto out;
3482 }
3483 case KVM_GET_TSC_KHZ: {
3484 r = vcpu->arch.virtual_tsc_khz;
3485 goto out;
3486 }
3487 case KVM_KVMCLOCK_CTRL: {
3488 r = kvm_set_guest_paused(vcpu);
3489 goto out;
3490 }
3491 case KVM_ENABLE_CAP: {
3492 struct kvm_enable_cap cap;
3493
3494 r = -EFAULT;
3495 if (copy_from_user(&cap, argp, sizeof(cap)))
3496 goto out;
3497 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3498 break;
3499 }
3500 default:
3501 r = -EINVAL;
3502 }
3503 out:
3504 kfree(u.buffer);
3505 return r;
3506 }
3507
3508 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3509 {
3510 return VM_FAULT_SIGBUS;
3511 }
3512
3513 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3514 {
3515 int ret;
3516
3517 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3518 return -EINVAL;
3519 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3520 return ret;
3521 }
3522
3523 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3524 u64 ident_addr)
3525 {
3526 kvm->arch.ept_identity_map_addr = ident_addr;
3527 return 0;
3528 }
3529
3530 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3531 u32 kvm_nr_mmu_pages)
3532 {
3533 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3534 return -EINVAL;
3535
3536 mutex_lock(&kvm->slots_lock);
3537
3538 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3539 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3540
3541 mutex_unlock(&kvm->slots_lock);
3542 return 0;
3543 }
3544
3545 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3546 {
3547 return kvm->arch.n_max_mmu_pages;
3548 }
3549
3550 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3551 {
3552 int r;
3553
3554 r = 0;
3555 switch (chip->chip_id) {
3556 case KVM_IRQCHIP_PIC_MASTER:
3557 memcpy(&chip->chip.pic,
3558 &pic_irqchip(kvm)->pics[0],
3559 sizeof(struct kvm_pic_state));
3560 break;
3561 case KVM_IRQCHIP_PIC_SLAVE:
3562 memcpy(&chip->chip.pic,
3563 &pic_irqchip(kvm)->pics[1],
3564 sizeof(struct kvm_pic_state));
3565 break;
3566 case KVM_IRQCHIP_IOAPIC:
3567 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3568 break;
3569 default:
3570 r = -EINVAL;
3571 break;
3572 }
3573 return r;
3574 }
3575
3576 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3577 {
3578 int r;
3579
3580 r = 0;
3581 switch (chip->chip_id) {
3582 case KVM_IRQCHIP_PIC_MASTER:
3583 spin_lock(&pic_irqchip(kvm)->lock);
3584 memcpy(&pic_irqchip(kvm)->pics[0],
3585 &chip->chip.pic,
3586 sizeof(struct kvm_pic_state));
3587 spin_unlock(&pic_irqchip(kvm)->lock);
3588 break;
3589 case KVM_IRQCHIP_PIC_SLAVE:
3590 spin_lock(&pic_irqchip(kvm)->lock);
3591 memcpy(&pic_irqchip(kvm)->pics[1],
3592 &chip->chip.pic,
3593 sizeof(struct kvm_pic_state));
3594 spin_unlock(&pic_irqchip(kvm)->lock);
3595 break;
3596 case KVM_IRQCHIP_IOAPIC:
3597 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3598 break;
3599 default:
3600 r = -EINVAL;
3601 break;
3602 }
3603 kvm_pic_update_irq(pic_irqchip(kvm));
3604 return r;
3605 }
3606
3607 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3608 {
3609 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3610
3611 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3612
3613 mutex_lock(&kps->lock);
3614 memcpy(ps, &kps->channels, sizeof(*ps));
3615 mutex_unlock(&kps->lock);
3616 return 0;
3617 }
3618
3619 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3620 {
3621 int i;
3622 struct kvm_pit *pit = kvm->arch.vpit;
3623
3624 mutex_lock(&pit->pit_state.lock);
3625 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3626 for (i = 0; i < 3; i++)
3627 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3628 mutex_unlock(&pit->pit_state.lock);
3629 return 0;
3630 }
3631
3632 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3633 {
3634 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3635 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3636 sizeof(ps->channels));
3637 ps->flags = kvm->arch.vpit->pit_state.flags;
3638 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3639 memset(&ps->reserved, 0, sizeof(ps->reserved));
3640 return 0;
3641 }
3642
3643 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3644 {
3645 int start = 0;
3646 int i;
3647 u32 prev_legacy, cur_legacy;
3648 struct kvm_pit *pit = kvm->arch.vpit;
3649
3650 mutex_lock(&pit->pit_state.lock);
3651 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3652 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3653 if (!prev_legacy && cur_legacy)
3654 start = 1;
3655 memcpy(&pit->pit_state.channels, &ps->channels,
3656 sizeof(pit->pit_state.channels));
3657 pit->pit_state.flags = ps->flags;
3658 for (i = 0; i < 3; i++)
3659 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3660 start && i == 0);
3661 mutex_unlock(&pit->pit_state.lock);
3662 return 0;
3663 }
3664
3665 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3666 struct kvm_reinject_control *control)
3667 {
3668 struct kvm_pit *pit = kvm->arch.vpit;
3669
3670 if (!pit)
3671 return -ENXIO;
3672
3673 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3674 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3675 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3676 */
3677 mutex_lock(&pit->pit_state.lock);
3678 kvm_pit_set_reinject(pit, control->pit_reinject);
3679 mutex_unlock(&pit->pit_state.lock);
3680
3681 return 0;
3682 }
3683
3684 /**
3685 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3686 * @kvm: kvm instance
3687 * @log: slot id and address to which we copy the log
3688 *
3689 * Steps 1-4 below provide general overview of dirty page logging. See
3690 * kvm_get_dirty_log_protect() function description for additional details.
3691 *
3692 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3693 * always flush the TLB (step 4) even if previous step failed and the dirty
3694 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3695 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3696 * writes will be marked dirty for next log read.
3697 *
3698 * 1. Take a snapshot of the bit and clear it if needed.
3699 * 2. Write protect the corresponding page.
3700 * 3. Copy the snapshot to the userspace.
3701 * 4. Flush TLB's if needed.
3702 */
3703 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3704 {
3705 bool is_dirty = false;
3706 int r;
3707
3708 mutex_lock(&kvm->slots_lock);
3709
3710 /*
3711 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3712 */
3713 if (kvm_x86_ops->flush_log_dirty)
3714 kvm_x86_ops->flush_log_dirty(kvm);
3715
3716 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3717
3718 /*
3719 * All the TLBs can be flushed out of mmu lock, see the comments in
3720 * kvm_mmu_slot_remove_write_access().
3721 */
3722 lockdep_assert_held(&kvm->slots_lock);
3723 if (is_dirty)
3724 kvm_flush_remote_tlbs(kvm);
3725
3726 mutex_unlock(&kvm->slots_lock);
3727 return r;
3728 }
3729
3730 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3731 bool line_status)
3732 {
3733 if (!irqchip_in_kernel(kvm))
3734 return -ENXIO;
3735
3736 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3737 irq_event->irq, irq_event->level,
3738 line_status);
3739 return 0;
3740 }
3741
3742 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3743 struct kvm_enable_cap *cap)
3744 {
3745 int r;
3746
3747 if (cap->flags)
3748 return -EINVAL;
3749
3750 switch (cap->cap) {
3751 case KVM_CAP_DISABLE_QUIRKS:
3752 kvm->arch.disabled_quirks = cap->args[0];
3753 r = 0;
3754 break;
3755 case KVM_CAP_SPLIT_IRQCHIP: {
3756 mutex_lock(&kvm->lock);
3757 r = -EINVAL;
3758 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3759 goto split_irqchip_unlock;
3760 r = -EEXIST;
3761 if (irqchip_in_kernel(kvm))
3762 goto split_irqchip_unlock;
3763 if (atomic_read(&kvm->online_vcpus))
3764 goto split_irqchip_unlock;
3765 r = kvm_setup_empty_irq_routing(kvm);
3766 if (r)
3767 goto split_irqchip_unlock;
3768 /* Pairs with irqchip_in_kernel. */
3769 smp_wmb();
3770 kvm->arch.irqchip_split = true;
3771 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3772 r = 0;
3773 split_irqchip_unlock:
3774 mutex_unlock(&kvm->lock);
3775 break;
3776 }
3777 default:
3778 r = -EINVAL;
3779 break;
3780 }
3781 return r;
3782 }
3783
3784 long kvm_arch_vm_ioctl(struct file *filp,
3785 unsigned int ioctl, unsigned long arg)
3786 {
3787 struct kvm *kvm = filp->private_data;
3788 void __user *argp = (void __user *)arg;
3789 int r = -ENOTTY;
3790 /*
3791 * This union makes it completely explicit to gcc-3.x
3792 * that these two variables' stack usage should be
3793 * combined, not added together.
3794 */
3795 union {
3796 struct kvm_pit_state ps;
3797 struct kvm_pit_state2 ps2;
3798 struct kvm_pit_config pit_config;
3799 } u;
3800
3801 switch (ioctl) {
3802 case KVM_SET_TSS_ADDR:
3803 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3804 break;
3805 case KVM_SET_IDENTITY_MAP_ADDR: {
3806 u64 ident_addr;
3807
3808 r = -EFAULT;
3809 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3810 goto out;
3811 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3812 break;
3813 }
3814 case KVM_SET_NR_MMU_PAGES:
3815 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3816 break;
3817 case KVM_GET_NR_MMU_PAGES:
3818 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3819 break;
3820 case KVM_CREATE_IRQCHIP: {
3821 struct kvm_pic *vpic;
3822
3823 mutex_lock(&kvm->lock);
3824 r = -EEXIST;
3825 if (kvm->arch.vpic)
3826 goto create_irqchip_unlock;
3827 r = -EINVAL;
3828 if (atomic_read(&kvm->online_vcpus))
3829 goto create_irqchip_unlock;
3830 r = -ENOMEM;
3831 vpic = kvm_create_pic(kvm);
3832 if (vpic) {
3833 r = kvm_ioapic_init(kvm);
3834 if (r) {
3835 mutex_lock(&kvm->slots_lock);
3836 kvm_destroy_pic(vpic);
3837 mutex_unlock(&kvm->slots_lock);
3838 goto create_irqchip_unlock;
3839 }
3840 } else
3841 goto create_irqchip_unlock;
3842 r = kvm_setup_default_irq_routing(kvm);
3843 if (r) {
3844 mutex_lock(&kvm->slots_lock);
3845 mutex_lock(&kvm->irq_lock);
3846 kvm_ioapic_destroy(kvm);
3847 kvm_destroy_pic(vpic);
3848 mutex_unlock(&kvm->irq_lock);
3849 mutex_unlock(&kvm->slots_lock);
3850 goto create_irqchip_unlock;
3851 }
3852 /* Write kvm->irq_routing before kvm->arch.vpic. */
3853 smp_wmb();
3854 kvm->arch.vpic = vpic;
3855 create_irqchip_unlock:
3856 mutex_unlock(&kvm->lock);
3857 break;
3858 }
3859 case KVM_CREATE_PIT:
3860 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3861 goto create_pit;
3862 case KVM_CREATE_PIT2:
3863 r = -EFAULT;
3864 if (copy_from_user(&u.pit_config, argp,
3865 sizeof(struct kvm_pit_config)))
3866 goto out;
3867 create_pit:
3868 mutex_lock(&kvm->slots_lock);
3869 r = -EEXIST;
3870 if (kvm->arch.vpit)
3871 goto create_pit_unlock;
3872 r = -ENOMEM;
3873 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3874 if (kvm->arch.vpit)
3875 r = 0;
3876 create_pit_unlock:
3877 mutex_unlock(&kvm->slots_lock);
3878 break;
3879 case KVM_GET_IRQCHIP: {
3880 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3881 struct kvm_irqchip *chip;
3882
3883 chip = memdup_user(argp, sizeof(*chip));
3884 if (IS_ERR(chip)) {
3885 r = PTR_ERR(chip);
3886 goto out;
3887 }
3888
3889 r = -ENXIO;
3890 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3891 goto get_irqchip_out;
3892 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3893 if (r)
3894 goto get_irqchip_out;
3895 r = -EFAULT;
3896 if (copy_to_user(argp, chip, sizeof *chip))
3897 goto get_irqchip_out;
3898 r = 0;
3899 get_irqchip_out:
3900 kfree(chip);
3901 break;
3902 }
3903 case KVM_SET_IRQCHIP: {
3904 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3905 struct kvm_irqchip *chip;
3906
3907 chip = memdup_user(argp, sizeof(*chip));
3908 if (IS_ERR(chip)) {
3909 r = PTR_ERR(chip);
3910 goto out;
3911 }
3912
3913 r = -ENXIO;
3914 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3915 goto set_irqchip_out;
3916 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3917 if (r)
3918 goto set_irqchip_out;
3919 r = 0;
3920 set_irqchip_out:
3921 kfree(chip);
3922 break;
3923 }
3924 case KVM_GET_PIT: {
3925 r = -EFAULT;
3926 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3927 goto out;
3928 r = -ENXIO;
3929 if (!kvm->arch.vpit)
3930 goto out;
3931 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3932 if (r)
3933 goto out;
3934 r = -EFAULT;
3935 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3936 goto out;
3937 r = 0;
3938 break;
3939 }
3940 case KVM_SET_PIT: {
3941 r = -EFAULT;
3942 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3943 goto out;
3944 r = -ENXIO;
3945 if (!kvm->arch.vpit)
3946 goto out;
3947 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3948 break;
3949 }
3950 case KVM_GET_PIT2: {
3951 r = -ENXIO;
3952 if (!kvm->arch.vpit)
3953 goto out;
3954 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3955 if (r)
3956 goto out;
3957 r = -EFAULT;
3958 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3959 goto out;
3960 r = 0;
3961 break;
3962 }
3963 case KVM_SET_PIT2: {
3964 r = -EFAULT;
3965 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3966 goto out;
3967 r = -ENXIO;
3968 if (!kvm->arch.vpit)
3969 goto out;
3970 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3971 break;
3972 }
3973 case KVM_REINJECT_CONTROL: {
3974 struct kvm_reinject_control control;
3975 r = -EFAULT;
3976 if (copy_from_user(&control, argp, sizeof(control)))
3977 goto out;
3978 r = kvm_vm_ioctl_reinject(kvm, &control);
3979 break;
3980 }
3981 case KVM_SET_BOOT_CPU_ID:
3982 r = 0;
3983 mutex_lock(&kvm->lock);
3984 if (atomic_read(&kvm->online_vcpus) != 0)
3985 r = -EBUSY;
3986 else
3987 kvm->arch.bsp_vcpu_id = arg;
3988 mutex_unlock(&kvm->lock);
3989 break;
3990 case KVM_XEN_HVM_CONFIG: {
3991 r = -EFAULT;
3992 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3993 sizeof(struct kvm_xen_hvm_config)))
3994 goto out;
3995 r = -EINVAL;
3996 if (kvm->arch.xen_hvm_config.flags)
3997 goto out;
3998 r = 0;
3999 break;
4000 }
4001 case KVM_SET_CLOCK: {
4002 struct kvm_clock_data user_ns;
4003 u64 now_ns;
4004 s64 delta;
4005
4006 r = -EFAULT;
4007 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4008 goto out;
4009
4010 r = -EINVAL;
4011 if (user_ns.flags)
4012 goto out;
4013
4014 r = 0;
4015 local_irq_disable();
4016 now_ns = get_kernel_ns();
4017 delta = user_ns.clock - now_ns;
4018 local_irq_enable();
4019 kvm->arch.kvmclock_offset = delta;
4020 kvm_gen_update_masterclock(kvm);
4021 break;
4022 }
4023 case KVM_GET_CLOCK: {
4024 struct kvm_clock_data user_ns;
4025 u64 now_ns;
4026
4027 local_irq_disable();
4028 now_ns = get_kernel_ns();
4029 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4030 local_irq_enable();
4031 user_ns.flags = 0;
4032 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4033
4034 r = -EFAULT;
4035 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4036 goto out;
4037 r = 0;
4038 break;
4039 }
4040 case KVM_ENABLE_CAP: {
4041 struct kvm_enable_cap cap;
4042
4043 r = -EFAULT;
4044 if (copy_from_user(&cap, argp, sizeof(cap)))
4045 goto out;
4046 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4047 break;
4048 }
4049 default:
4050 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4051 }
4052 out:
4053 return r;
4054 }
4055
4056 static void kvm_init_msr_list(void)
4057 {
4058 u32 dummy[2];
4059 unsigned i, j;
4060
4061 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4062 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4063 continue;
4064
4065 /*
4066 * Even MSRs that are valid in the host may not be exposed
4067 * to the guests in some cases.
4068 */
4069 switch (msrs_to_save[i]) {
4070 case MSR_IA32_BNDCFGS:
4071 if (!kvm_x86_ops->mpx_supported())
4072 continue;
4073 break;
4074 case MSR_TSC_AUX:
4075 if (!kvm_x86_ops->rdtscp_supported())
4076 continue;
4077 break;
4078 default:
4079 break;
4080 }
4081
4082 if (j < i)
4083 msrs_to_save[j] = msrs_to_save[i];
4084 j++;
4085 }
4086 num_msrs_to_save = j;
4087
4088 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4089 switch (emulated_msrs[i]) {
4090 case MSR_IA32_SMBASE:
4091 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4092 continue;
4093 break;
4094 default:
4095 break;
4096 }
4097
4098 if (j < i)
4099 emulated_msrs[j] = emulated_msrs[i];
4100 j++;
4101 }
4102 num_emulated_msrs = j;
4103 }
4104
4105 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4106 const void *v)
4107 {
4108 int handled = 0;
4109 int n;
4110
4111 do {
4112 n = min(len, 8);
4113 if (!(lapic_in_kernel(vcpu) &&
4114 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4115 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4116 break;
4117 handled += n;
4118 addr += n;
4119 len -= n;
4120 v += n;
4121 } while (len);
4122
4123 return handled;
4124 }
4125
4126 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4127 {
4128 int handled = 0;
4129 int n;
4130
4131 do {
4132 n = min(len, 8);
4133 if (!(lapic_in_kernel(vcpu) &&
4134 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4135 addr, n, v))
4136 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4137 break;
4138 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4139 handled += n;
4140 addr += n;
4141 len -= n;
4142 v += n;
4143 } while (len);
4144
4145 return handled;
4146 }
4147
4148 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4149 struct kvm_segment *var, int seg)
4150 {
4151 kvm_x86_ops->set_segment(vcpu, var, seg);
4152 }
4153
4154 void kvm_get_segment(struct kvm_vcpu *vcpu,
4155 struct kvm_segment *var, int seg)
4156 {
4157 kvm_x86_ops->get_segment(vcpu, var, seg);
4158 }
4159
4160 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4161 struct x86_exception *exception)
4162 {
4163 gpa_t t_gpa;
4164
4165 BUG_ON(!mmu_is_nested(vcpu));
4166
4167 /* NPT walks are always user-walks */
4168 access |= PFERR_USER_MASK;
4169 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4170
4171 return t_gpa;
4172 }
4173
4174 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4175 struct x86_exception *exception)
4176 {
4177 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4178 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4179 }
4180
4181 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4182 struct x86_exception *exception)
4183 {
4184 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4185 access |= PFERR_FETCH_MASK;
4186 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4187 }
4188
4189 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4190 struct x86_exception *exception)
4191 {
4192 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4193 access |= PFERR_WRITE_MASK;
4194 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4195 }
4196
4197 /* uses this to access any guest's mapped memory without checking CPL */
4198 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4199 struct x86_exception *exception)
4200 {
4201 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4202 }
4203
4204 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4205 struct kvm_vcpu *vcpu, u32 access,
4206 struct x86_exception *exception)
4207 {
4208 void *data = val;
4209 int r = X86EMUL_CONTINUE;
4210
4211 while (bytes) {
4212 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4213 exception);
4214 unsigned offset = addr & (PAGE_SIZE-1);
4215 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4216 int ret;
4217
4218 if (gpa == UNMAPPED_GVA)
4219 return X86EMUL_PROPAGATE_FAULT;
4220 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4221 offset, toread);
4222 if (ret < 0) {
4223 r = X86EMUL_IO_NEEDED;
4224 goto out;
4225 }
4226
4227 bytes -= toread;
4228 data += toread;
4229 addr += toread;
4230 }
4231 out:
4232 return r;
4233 }
4234
4235 /* used for instruction fetching */
4236 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4237 gva_t addr, void *val, unsigned int bytes,
4238 struct x86_exception *exception)
4239 {
4240 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4241 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4242 unsigned offset;
4243 int ret;
4244
4245 /* Inline kvm_read_guest_virt_helper for speed. */
4246 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4247 exception);
4248 if (unlikely(gpa == UNMAPPED_GVA))
4249 return X86EMUL_PROPAGATE_FAULT;
4250
4251 offset = addr & (PAGE_SIZE-1);
4252 if (WARN_ON(offset + bytes > PAGE_SIZE))
4253 bytes = (unsigned)PAGE_SIZE - offset;
4254 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4255 offset, bytes);
4256 if (unlikely(ret < 0))
4257 return X86EMUL_IO_NEEDED;
4258
4259 return X86EMUL_CONTINUE;
4260 }
4261
4262 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4263 gva_t addr, void *val, unsigned int bytes,
4264 struct x86_exception *exception)
4265 {
4266 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4267 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4268
4269 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4270 exception);
4271 }
4272 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4273
4274 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4275 gva_t addr, void *val, unsigned int bytes,
4276 struct x86_exception *exception)
4277 {
4278 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4279 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4280 }
4281
4282 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4283 unsigned long addr, void *val, unsigned int bytes)
4284 {
4285 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4286 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4287
4288 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4289 }
4290
4291 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4292 gva_t addr, void *val,
4293 unsigned int bytes,
4294 struct x86_exception *exception)
4295 {
4296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4297 void *data = val;
4298 int r = X86EMUL_CONTINUE;
4299
4300 while (bytes) {
4301 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4302 PFERR_WRITE_MASK,
4303 exception);
4304 unsigned offset = addr & (PAGE_SIZE-1);
4305 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4306 int ret;
4307
4308 if (gpa == UNMAPPED_GVA)
4309 return X86EMUL_PROPAGATE_FAULT;
4310 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4311 if (ret < 0) {
4312 r = X86EMUL_IO_NEEDED;
4313 goto out;
4314 }
4315
4316 bytes -= towrite;
4317 data += towrite;
4318 addr += towrite;
4319 }
4320 out:
4321 return r;
4322 }
4323 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4324
4325 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4326 gpa_t *gpa, struct x86_exception *exception,
4327 bool write)
4328 {
4329 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4330 | (write ? PFERR_WRITE_MASK : 0);
4331
4332 /*
4333 * currently PKRU is only applied to ept enabled guest so
4334 * there is no pkey in EPT page table for L1 guest or EPT
4335 * shadow page table for L2 guest.
4336 */
4337 if (vcpu_match_mmio_gva(vcpu, gva)
4338 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4339 vcpu->arch.access, 0, access)) {
4340 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4341 (gva & (PAGE_SIZE - 1));
4342 trace_vcpu_match_mmio(gva, *gpa, write, false);
4343 return 1;
4344 }
4345
4346 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4347
4348 if (*gpa == UNMAPPED_GVA)
4349 return -1;
4350
4351 /* For APIC access vmexit */
4352 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4353 return 1;
4354
4355 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4356 trace_vcpu_match_mmio(gva, *gpa, write, true);
4357 return 1;
4358 }
4359
4360 return 0;
4361 }
4362
4363 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4364 const void *val, int bytes)
4365 {
4366 int ret;
4367
4368 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4369 if (ret < 0)
4370 return 0;
4371 kvm_page_track_write(vcpu, gpa, val, bytes);
4372 return 1;
4373 }
4374
4375 struct read_write_emulator_ops {
4376 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4377 int bytes);
4378 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4379 void *val, int bytes);
4380 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4381 int bytes, void *val);
4382 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4383 void *val, int bytes);
4384 bool write;
4385 };
4386
4387 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4388 {
4389 if (vcpu->mmio_read_completed) {
4390 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4391 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4392 vcpu->mmio_read_completed = 0;
4393 return 1;
4394 }
4395
4396 return 0;
4397 }
4398
4399 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4400 void *val, int bytes)
4401 {
4402 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4403 }
4404
4405 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4406 void *val, int bytes)
4407 {
4408 return emulator_write_phys(vcpu, gpa, val, bytes);
4409 }
4410
4411 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4412 {
4413 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4414 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4415 }
4416
4417 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4418 void *val, int bytes)
4419 {
4420 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4421 return X86EMUL_IO_NEEDED;
4422 }
4423
4424 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4425 void *val, int bytes)
4426 {
4427 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4428
4429 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4430 return X86EMUL_CONTINUE;
4431 }
4432
4433 static const struct read_write_emulator_ops read_emultor = {
4434 .read_write_prepare = read_prepare,
4435 .read_write_emulate = read_emulate,
4436 .read_write_mmio = vcpu_mmio_read,
4437 .read_write_exit_mmio = read_exit_mmio,
4438 };
4439
4440 static const struct read_write_emulator_ops write_emultor = {
4441 .read_write_emulate = write_emulate,
4442 .read_write_mmio = write_mmio,
4443 .read_write_exit_mmio = write_exit_mmio,
4444 .write = true,
4445 };
4446
4447 static int emulator_read_write_onepage(unsigned long addr, void *val,
4448 unsigned int bytes,
4449 struct x86_exception *exception,
4450 struct kvm_vcpu *vcpu,
4451 const struct read_write_emulator_ops *ops)
4452 {
4453 gpa_t gpa;
4454 int handled, ret;
4455 bool write = ops->write;
4456 struct kvm_mmio_fragment *frag;
4457
4458 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4459
4460 if (ret < 0)
4461 return X86EMUL_PROPAGATE_FAULT;
4462
4463 /* For APIC access vmexit */
4464 if (ret)
4465 goto mmio;
4466
4467 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4468 return X86EMUL_CONTINUE;
4469
4470 mmio:
4471 /*
4472 * Is this MMIO handled locally?
4473 */
4474 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4475 if (handled == bytes)
4476 return X86EMUL_CONTINUE;
4477
4478 gpa += handled;
4479 bytes -= handled;
4480 val += handled;
4481
4482 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4483 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4484 frag->gpa = gpa;
4485 frag->data = val;
4486 frag->len = bytes;
4487 return X86EMUL_CONTINUE;
4488 }
4489
4490 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4491 unsigned long addr,
4492 void *val, unsigned int bytes,
4493 struct x86_exception *exception,
4494 const struct read_write_emulator_ops *ops)
4495 {
4496 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4497 gpa_t gpa;
4498 int rc;
4499
4500 if (ops->read_write_prepare &&
4501 ops->read_write_prepare(vcpu, val, bytes))
4502 return X86EMUL_CONTINUE;
4503
4504 vcpu->mmio_nr_fragments = 0;
4505
4506 /* Crossing a page boundary? */
4507 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4508 int now;
4509
4510 now = -addr & ~PAGE_MASK;
4511 rc = emulator_read_write_onepage(addr, val, now, exception,
4512 vcpu, ops);
4513
4514 if (rc != X86EMUL_CONTINUE)
4515 return rc;
4516 addr += now;
4517 if (ctxt->mode != X86EMUL_MODE_PROT64)
4518 addr = (u32)addr;
4519 val += now;
4520 bytes -= now;
4521 }
4522
4523 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4524 vcpu, ops);
4525 if (rc != X86EMUL_CONTINUE)
4526 return rc;
4527
4528 if (!vcpu->mmio_nr_fragments)
4529 return rc;
4530
4531 gpa = vcpu->mmio_fragments[0].gpa;
4532
4533 vcpu->mmio_needed = 1;
4534 vcpu->mmio_cur_fragment = 0;
4535
4536 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4537 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4538 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4539 vcpu->run->mmio.phys_addr = gpa;
4540
4541 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4542 }
4543
4544 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4545 unsigned long addr,
4546 void *val,
4547 unsigned int bytes,
4548 struct x86_exception *exception)
4549 {
4550 return emulator_read_write(ctxt, addr, val, bytes,
4551 exception, &read_emultor);
4552 }
4553
4554 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4555 unsigned long addr,
4556 const void *val,
4557 unsigned int bytes,
4558 struct x86_exception *exception)
4559 {
4560 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4561 exception, &write_emultor);
4562 }
4563
4564 #define CMPXCHG_TYPE(t, ptr, old, new) \
4565 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4566
4567 #ifdef CONFIG_X86_64
4568 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4569 #else
4570 # define CMPXCHG64(ptr, old, new) \
4571 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4572 #endif
4573
4574 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4575 unsigned long addr,
4576 const void *old,
4577 const void *new,
4578 unsigned int bytes,
4579 struct x86_exception *exception)
4580 {
4581 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4582 gpa_t gpa;
4583 struct page *page;
4584 char *kaddr;
4585 bool exchanged;
4586
4587 /* guests cmpxchg8b have to be emulated atomically */
4588 if (bytes > 8 || (bytes & (bytes - 1)))
4589 goto emul_write;
4590
4591 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4592
4593 if (gpa == UNMAPPED_GVA ||
4594 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4595 goto emul_write;
4596
4597 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4598 goto emul_write;
4599
4600 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4601 if (is_error_page(page))
4602 goto emul_write;
4603
4604 kaddr = kmap_atomic(page);
4605 kaddr += offset_in_page(gpa);
4606 switch (bytes) {
4607 case 1:
4608 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4609 break;
4610 case 2:
4611 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4612 break;
4613 case 4:
4614 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4615 break;
4616 case 8:
4617 exchanged = CMPXCHG64(kaddr, old, new);
4618 break;
4619 default:
4620 BUG();
4621 }
4622 kunmap_atomic(kaddr);
4623 kvm_release_page_dirty(page);
4624
4625 if (!exchanged)
4626 return X86EMUL_CMPXCHG_FAILED;
4627
4628 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4629 kvm_page_track_write(vcpu, gpa, new, bytes);
4630
4631 return X86EMUL_CONTINUE;
4632
4633 emul_write:
4634 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4635
4636 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4637 }
4638
4639 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4640 {
4641 /* TODO: String I/O for in kernel device */
4642 int r;
4643
4644 if (vcpu->arch.pio.in)
4645 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4646 vcpu->arch.pio.size, pd);
4647 else
4648 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4649 vcpu->arch.pio.port, vcpu->arch.pio.size,
4650 pd);
4651 return r;
4652 }
4653
4654 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4655 unsigned short port, void *val,
4656 unsigned int count, bool in)
4657 {
4658 vcpu->arch.pio.port = port;
4659 vcpu->arch.pio.in = in;
4660 vcpu->arch.pio.count = count;
4661 vcpu->arch.pio.size = size;
4662
4663 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4664 vcpu->arch.pio.count = 0;
4665 return 1;
4666 }
4667
4668 vcpu->run->exit_reason = KVM_EXIT_IO;
4669 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4670 vcpu->run->io.size = size;
4671 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4672 vcpu->run->io.count = count;
4673 vcpu->run->io.port = port;
4674
4675 return 0;
4676 }
4677
4678 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4679 int size, unsigned short port, void *val,
4680 unsigned int count)
4681 {
4682 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4683 int ret;
4684
4685 if (vcpu->arch.pio.count)
4686 goto data_avail;
4687
4688 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4689 if (ret) {
4690 data_avail:
4691 memcpy(val, vcpu->arch.pio_data, size * count);
4692 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4693 vcpu->arch.pio.count = 0;
4694 return 1;
4695 }
4696
4697 return 0;
4698 }
4699
4700 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4701 int size, unsigned short port,
4702 const void *val, unsigned int count)
4703 {
4704 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4705
4706 memcpy(vcpu->arch.pio_data, val, size * count);
4707 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4708 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4709 }
4710
4711 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4712 {
4713 return kvm_x86_ops->get_segment_base(vcpu, seg);
4714 }
4715
4716 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4717 {
4718 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4719 }
4720
4721 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4722 {
4723 if (!need_emulate_wbinvd(vcpu))
4724 return X86EMUL_CONTINUE;
4725
4726 if (kvm_x86_ops->has_wbinvd_exit()) {
4727 int cpu = get_cpu();
4728
4729 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4730 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4731 wbinvd_ipi, NULL, 1);
4732 put_cpu();
4733 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4734 } else
4735 wbinvd();
4736 return X86EMUL_CONTINUE;
4737 }
4738
4739 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4740 {
4741 kvm_x86_ops->skip_emulated_instruction(vcpu);
4742 return kvm_emulate_wbinvd_noskip(vcpu);
4743 }
4744 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4745
4746
4747
4748 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4749 {
4750 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4751 }
4752
4753 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4754 unsigned long *dest)
4755 {
4756 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4757 }
4758
4759 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4760 unsigned long value)
4761 {
4762
4763 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4764 }
4765
4766 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4767 {
4768 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4769 }
4770
4771 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4772 {
4773 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4774 unsigned long value;
4775
4776 switch (cr) {
4777 case 0:
4778 value = kvm_read_cr0(vcpu);
4779 break;
4780 case 2:
4781 value = vcpu->arch.cr2;
4782 break;
4783 case 3:
4784 value = kvm_read_cr3(vcpu);
4785 break;
4786 case 4:
4787 value = kvm_read_cr4(vcpu);
4788 break;
4789 case 8:
4790 value = kvm_get_cr8(vcpu);
4791 break;
4792 default:
4793 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4794 return 0;
4795 }
4796
4797 return value;
4798 }
4799
4800 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4801 {
4802 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4803 int res = 0;
4804
4805 switch (cr) {
4806 case 0:
4807 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4808 break;
4809 case 2:
4810 vcpu->arch.cr2 = val;
4811 break;
4812 case 3:
4813 res = kvm_set_cr3(vcpu, val);
4814 break;
4815 case 4:
4816 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4817 break;
4818 case 8:
4819 res = kvm_set_cr8(vcpu, val);
4820 break;
4821 default:
4822 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4823 res = -1;
4824 }
4825
4826 return res;
4827 }
4828
4829 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4830 {
4831 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4832 }
4833
4834 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4835 {
4836 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4837 }
4838
4839 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4840 {
4841 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4842 }
4843
4844 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4845 {
4846 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4847 }
4848
4849 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4850 {
4851 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4852 }
4853
4854 static unsigned long emulator_get_cached_segment_base(
4855 struct x86_emulate_ctxt *ctxt, int seg)
4856 {
4857 return get_segment_base(emul_to_vcpu(ctxt), seg);
4858 }
4859
4860 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4861 struct desc_struct *desc, u32 *base3,
4862 int seg)
4863 {
4864 struct kvm_segment var;
4865
4866 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4867 *selector = var.selector;
4868
4869 if (var.unusable) {
4870 memset(desc, 0, sizeof(*desc));
4871 return false;
4872 }
4873
4874 if (var.g)
4875 var.limit >>= 12;
4876 set_desc_limit(desc, var.limit);
4877 set_desc_base(desc, (unsigned long)var.base);
4878 #ifdef CONFIG_X86_64
4879 if (base3)
4880 *base3 = var.base >> 32;
4881 #endif
4882 desc->type = var.type;
4883 desc->s = var.s;
4884 desc->dpl = var.dpl;
4885 desc->p = var.present;
4886 desc->avl = var.avl;
4887 desc->l = var.l;
4888 desc->d = var.db;
4889 desc->g = var.g;
4890
4891 return true;
4892 }
4893
4894 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4895 struct desc_struct *desc, u32 base3,
4896 int seg)
4897 {
4898 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4899 struct kvm_segment var;
4900
4901 var.selector = selector;
4902 var.base = get_desc_base(desc);
4903 #ifdef CONFIG_X86_64
4904 var.base |= ((u64)base3) << 32;
4905 #endif
4906 var.limit = get_desc_limit(desc);
4907 if (desc->g)
4908 var.limit = (var.limit << 12) | 0xfff;
4909 var.type = desc->type;
4910 var.dpl = desc->dpl;
4911 var.db = desc->d;
4912 var.s = desc->s;
4913 var.l = desc->l;
4914 var.g = desc->g;
4915 var.avl = desc->avl;
4916 var.present = desc->p;
4917 var.unusable = !var.present;
4918 var.padding = 0;
4919
4920 kvm_set_segment(vcpu, &var, seg);
4921 return;
4922 }
4923
4924 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4925 u32 msr_index, u64 *pdata)
4926 {
4927 struct msr_data msr;
4928 int r;
4929
4930 msr.index = msr_index;
4931 msr.host_initiated = false;
4932 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4933 if (r)
4934 return r;
4935
4936 *pdata = msr.data;
4937 return 0;
4938 }
4939
4940 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4941 u32 msr_index, u64 data)
4942 {
4943 struct msr_data msr;
4944
4945 msr.data = data;
4946 msr.index = msr_index;
4947 msr.host_initiated = false;
4948 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4949 }
4950
4951 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4952 {
4953 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4954
4955 return vcpu->arch.smbase;
4956 }
4957
4958 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4959 {
4960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4961
4962 vcpu->arch.smbase = smbase;
4963 }
4964
4965 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4966 u32 pmc)
4967 {
4968 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4969 }
4970
4971 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4972 u32 pmc, u64 *pdata)
4973 {
4974 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4975 }
4976
4977 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4978 {
4979 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4980 }
4981
4982 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4983 {
4984 preempt_disable();
4985 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4986 /*
4987 * CR0.TS may reference the host fpu state, not the guest fpu state,
4988 * so it may be clear at this point.
4989 */
4990 clts();
4991 }
4992
4993 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4994 {
4995 preempt_enable();
4996 }
4997
4998 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4999 struct x86_instruction_info *info,
5000 enum x86_intercept_stage stage)
5001 {
5002 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5003 }
5004
5005 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5006 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5007 {
5008 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5009 }
5010
5011 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5012 {
5013 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5014 }
5015
5016 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5017 {
5018 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5019 }
5020
5021 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5022 {
5023 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5024 }
5025
5026 static const struct x86_emulate_ops emulate_ops = {
5027 .read_gpr = emulator_read_gpr,
5028 .write_gpr = emulator_write_gpr,
5029 .read_std = kvm_read_guest_virt_system,
5030 .write_std = kvm_write_guest_virt_system,
5031 .read_phys = kvm_read_guest_phys_system,
5032 .fetch = kvm_fetch_guest_virt,
5033 .read_emulated = emulator_read_emulated,
5034 .write_emulated = emulator_write_emulated,
5035 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5036 .invlpg = emulator_invlpg,
5037 .pio_in_emulated = emulator_pio_in_emulated,
5038 .pio_out_emulated = emulator_pio_out_emulated,
5039 .get_segment = emulator_get_segment,
5040 .set_segment = emulator_set_segment,
5041 .get_cached_segment_base = emulator_get_cached_segment_base,
5042 .get_gdt = emulator_get_gdt,
5043 .get_idt = emulator_get_idt,
5044 .set_gdt = emulator_set_gdt,
5045 .set_idt = emulator_set_idt,
5046 .get_cr = emulator_get_cr,
5047 .set_cr = emulator_set_cr,
5048 .cpl = emulator_get_cpl,
5049 .get_dr = emulator_get_dr,
5050 .set_dr = emulator_set_dr,
5051 .get_smbase = emulator_get_smbase,
5052 .set_smbase = emulator_set_smbase,
5053 .set_msr = emulator_set_msr,
5054 .get_msr = emulator_get_msr,
5055 .check_pmc = emulator_check_pmc,
5056 .read_pmc = emulator_read_pmc,
5057 .halt = emulator_halt,
5058 .wbinvd = emulator_wbinvd,
5059 .fix_hypercall = emulator_fix_hypercall,
5060 .get_fpu = emulator_get_fpu,
5061 .put_fpu = emulator_put_fpu,
5062 .intercept = emulator_intercept,
5063 .get_cpuid = emulator_get_cpuid,
5064 .set_nmi_mask = emulator_set_nmi_mask,
5065 };
5066
5067 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5068 {
5069 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5070 /*
5071 * an sti; sti; sequence only disable interrupts for the first
5072 * instruction. So, if the last instruction, be it emulated or
5073 * not, left the system with the INT_STI flag enabled, it
5074 * means that the last instruction is an sti. We should not
5075 * leave the flag on in this case. The same goes for mov ss
5076 */
5077 if (int_shadow & mask)
5078 mask = 0;
5079 if (unlikely(int_shadow || mask)) {
5080 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5081 if (!mask)
5082 kvm_make_request(KVM_REQ_EVENT, vcpu);
5083 }
5084 }
5085
5086 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5087 {
5088 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5089 if (ctxt->exception.vector == PF_VECTOR)
5090 return kvm_propagate_fault(vcpu, &ctxt->exception);
5091
5092 if (ctxt->exception.error_code_valid)
5093 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5094 ctxt->exception.error_code);
5095 else
5096 kvm_queue_exception(vcpu, ctxt->exception.vector);
5097 return false;
5098 }
5099
5100 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5101 {
5102 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5103 int cs_db, cs_l;
5104
5105 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5106
5107 ctxt->eflags = kvm_get_rflags(vcpu);
5108 ctxt->eip = kvm_rip_read(vcpu);
5109 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5110 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5111 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5112 cs_db ? X86EMUL_MODE_PROT32 :
5113 X86EMUL_MODE_PROT16;
5114 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5115 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5116 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5117 ctxt->emul_flags = vcpu->arch.hflags;
5118
5119 init_decode_cache(ctxt);
5120 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5121 }
5122
5123 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5124 {
5125 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5126 int ret;
5127
5128 init_emulate_ctxt(vcpu);
5129
5130 ctxt->op_bytes = 2;
5131 ctxt->ad_bytes = 2;
5132 ctxt->_eip = ctxt->eip + inc_eip;
5133 ret = emulate_int_real(ctxt, irq);
5134
5135 if (ret != X86EMUL_CONTINUE)
5136 return EMULATE_FAIL;
5137
5138 ctxt->eip = ctxt->_eip;
5139 kvm_rip_write(vcpu, ctxt->eip);
5140 kvm_set_rflags(vcpu, ctxt->eflags);
5141
5142 if (irq == NMI_VECTOR)
5143 vcpu->arch.nmi_pending = 0;
5144 else
5145 vcpu->arch.interrupt.pending = false;
5146
5147 return EMULATE_DONE;
5148 }
5149 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5150
5151 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5152 {
5153 int r = EMULATE_DONE;
5154
5155 ++vcpu->stat.insn_emulation_fail;
5156 trace_kvm_emulate_insn_failed(vcpu);
5157 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5158 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5159 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5160 vcpu->run->internal.ndata = 0;
5161 r = EMULATE_FAIL;
5162 }
5163 kvm_queue_exception(vcpu, UD_VECTOR);
5164
5165 return r;
5166 }
5167
5168 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5169 bool write_fault_to_shadow_pgtable,
5170 int emulation_type)
5171 {
5172 gpa_t gpa = cr2;
5173 kvm_pfn_t pfn;
5174
5175 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5176 return false;
5177
5178 if (!vcpu->arch.mmu.direct_map) {
5179 /*
5180 * Write permission should be allowed since only
5181 * write access need to be emulated.
5182 */
5183 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5184
5185 /*
5186 * If the mapping is invalid in guest, let cpu retry
5187 * it to generate fault.
5188 */
5189 if (gpa == UNMAPPED_GVA)
5190 return true;
5191 }
5192
5193 /*
5194 * Do not retry the unhandleable instruction if it faults on the
5195 * readonly host memory, otherwise it will goto a infinite loop:
5196 * retry instruction -> write #PF -> emulation fail -> retry
5197 * instruction -> ...
5198 */
5199 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5200
5201 /*
5202 * If the instruction failed on the error pfn, it can not be fixed,
5203 * report the error to userspace.
5204 */
5205 if (is_error_noslot_pfn(pfn))
5206 return false;
5207
5208 kvm_release_pfn_clean(pfn);
5209
5210 /* The instructions are well-emulated on direct mmu. */
5211 if (vcpu->arch.mmu.direct_map) {
5212 unsigned int indirect_shadow_pages;
5213
5214 spin_lock(&vcpu->kvm->mmu_lock);
5215 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5216 spin_unlock(&vcpu->kvm->mmu_lock);
5217
5218 if (indirect_shadow_pages)
5219 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5220
5221 return true;
5222 }
5223
5224 /*
5225 * if emulation was due to access to shadowed page table
5226 * and it failed try to unshadow page and re-enter the
5227 * guest to let CPU execute the instruction.
5228 */
5229 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5230
5231 /*
5232 * If the access faults on its page table, it can not
5233 * be fixed by unprotecting shadow page and it should
5234 * be reported to userspace.
5235 */
5236 return !write_fault_to_shadow_pgtable;
5237 }
5238
5239 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5240 unsigned long cr2, int emulation_type)
5241 {
5242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5243 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5244
5245 last_retry_eip = vcpu->arch.last_retry_eip;
5246 last_retry_addr = vcpu->arch.last_retry_addr;
5247
5248 /*
5249 * If the emulation is caused by #PF and it is non-page_table
5250 * writing instruction, it means the VM-EXIT is caused by shadow
5251 * page protected, we can zap the shadow page and retry this
5252 * instruction directly.
5253 *
5254 * Note: if the guest uses a non-page-table modifying instruction
5255 * on the PDE that points to the instruction, then we will unmap
5256 * the instruction and go to an infinite loop. So, we cache the
5257 * last retried eip and the last fault address, if we meet the eip
5258 * and the address again, we can break out of the potential infinite
5259 * loop.
5260 */
5261 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5262
5263 if (!(emulation_type & EMULTYPE_RETRY))
5264 return false;
5265
5266 if (x86_page_table_writing_insn(ctxt))
5267 return false;
5268
5269 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5270 return false;
5271
5272 vcpu->arch.last_retry_eip = ctxt->eip;
5273 vcpu->arch.last_retry_addr = cr2;
5274
5275 if (!vcpu->arch.mmu.direct_map)
5276 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5277
5278 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5279
5280 return true;
5281 }
5282
5283 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5284 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5285
5286 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5287 {
5288 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5289 /* This is a good place to trace that we are exiting SMM. */
5290 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5291
5292 if (unlikely(vcpu->arch.smi_pending)) {
5293 kvm_make_request(KVM_REQ_SMI, vcpu);
5294 vcpu->arch.smi_pending = 0;
5295 } else {
5296 /* Process a latched INIT, if any. */
5297 kvm_make_request(KVM_REQ_EVENT, vcpu);
5298 }
5299 }
5300
5301 kvm_mmu_reset_context(vcpu);
5302 }
5303
5304 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5305 {
5306 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5307
5308 vcpu->arch.hflags = emul_flags;
5309
5310 if (changed & HF_SMM_MASK)
5311 kvm_smm_changed(vcpu);
5312 }
5313
5314 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5315 unsigned long *db)
5316 {
5317 u32 dr6 = 0;
5318 int i;
5319 u32 enable, rwlen;
5320
5321 enable = dr7;
5322 rwlen = dr7 >> 16;
5323 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5324 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5325 dr6 |= (1 << i);
5326 return dr6;
5327 }
5328
5329 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5330 {
5331 struct kvm_run *kvm_run = vcpu->run;
5332
5333 /*
5334 * rflags is the old, "raw" value of the flags. The new value has
5335 * not been saved yet.
5336 *
5337 * This is correct even for TF set by the guest, because "the
5338 * processor will not generate this exception after the instruction
5339 * that sets the TF flag".
5340 */
5341 if (unlikely(rflags & X86_EFLAGS_TF)) {
5342 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5343 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5344 DR6_RTM;
5345 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5346 kvm_run->debug.arch.exception = DB_VECTOR;
5347 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5348 *r = EMULATE_USER_EXIT;
5349 } else {
5350 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5351 /*
5352 * "Certain debug exceptions may clear bit 0-3. The
5353 * remaining contents of the DR6 register are never
5354 * cleared by the processor".
5355 */
5356 vcpu->arch.dr6 &= ~15;
5357 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5358 kvm_queue_exception(vcpu, DB_VECTOR);
5359 }
5360 }
5361 }
5362
5363 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5364 {
5365 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5366 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5367 struct kvm_run *kvm_run = vcpu->run;
5368 unsigned long eip = kvm_get_linear_rip(vcpu);
5369 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5370 vcpu->arch.guest_debug_dr7,
5371 vcpu->arch.eff_db);
5372
5373 if (dr6 != 0) {
5374 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5375 kvm_run->debug.arch.pc = eip;
5376 kvm_run->debug.arch.exception = DB_VECTOR;
5377 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5378 *r = EMULATE_USER_EXIT;
5379 return true;
5380 }
5381 }
5382
5383 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5384 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5385 unsigned long eip = kvm_get_linear_rip(vcpu);
5386 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5387 vcpu->arch.dr7,
5388 vcpu->arch.db);
5389
5390 if (dr6 != 0) {
5391 vcpu->arch.dr6 &= ~15;
5392 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5393 kvm_queue_exception(vcpu, DB_VECTOR);
5394 *r = EMULATE_DONE;
5395 return true;
5396 }
5397 }
5398
5399 return false;
5400 }
5401
5402 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5403 unsigned long cr2,
5404 int emulation_type,
5405 void *insn,
5406 int insn_len)
5407 {
5408 int r;
5409 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5410 bool writeback = true;
5411 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5412
5413 /*
5414 * Clear write_fault_to_shadow_pgtable here to ensure it is
5415 * never reused.
5416 */
5417 vcpu->arch.write_fault_to_shadow_pgtable = false;
5418 kvm_clear_exception_queue(vcpu);
5419
5420 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5421 init_emulate_ctxt(vcpu);
5422
5423 /*
5424 * We will reenter on the same instruction since
5425 * we do not set complete_userspace_io. This does not
5426 * handle watchpoints yet, those would be handled in
5427 * the emulate_ops.
5428 */
5429 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5430 return r;
5431
5432 ctxt->interruptibility = 0;
5433 ctxt->have_exception = false;
5434 ctxt->exception.vector = -1;
5435 ctxt->perm_ok = false;
5436
5437 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5438
5439 r = x86_decode_insn(ctxt, insn, insn_len);
5440
5441 trace_kvm_emulate_insn_start(vcpu);
5442 ++vcpu->stat.insn_emulation;
5443 if (r != EMULATION_OK) {
5444 if (emulation_type & EMULTYPE_TRAP_UD)
5445 return EMULATE_FAIL;
5446 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5447 emulation_type))
5448 return EMULATE_DONE;
5449 if (emulation_type & EMULTYPE_SKIP)
5450 return EMULATE_FAIL;
5451 return handle_emulation_failure(vcpu);
5452 }
5453 }
5454
5455 if (emulation_type & EMULTYPE_SKIP) {
5456 kvm_rip_write(vcpu, ctxt->_eip);
5457 if (ctxt->eflags & X86_EFLAGS_RF)
5458 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5459 return EMULATE_DONE;
5460 }
5461
5462 if (retry_instruction(ctxt, cr2, emulation_type))
5463 return EMULATE_DONE;
5464
5465 /* this is needed for vmware backdoor interface to work since it
5466 changes registers values during IO operation */
5467 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5468 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5469 emulator_invalidate_register_cache(ctxt);
5470 }
5471
5472 restart:
5473 r = x86_emulate_insn(ctxt);
5474
5475 if (r == EMULATION_INTERCEPTED)
5476 return EMULATE_DONE;
5477
5478 if (r == EMULATION_FAILED) {
5479 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5480 emulation_type))
5481 return EMULATE_DONE;
5482
5483 return handle_emulation_failure(vcpu);
5484 }
5485
5486 if (ctxt->have_exception) {
5487 r = EMULATE_DONE;
5488 if (inject_emulated_exception(vcpu))
5489 return r;
5490 } else if (vcpu->arch.pio.count) {
5491 if (!vcpu->arch.pio.in) {
5492 /* FIXME: return into emulator if single-stepping. */
5493 vcpu->arch.pio.count = 0;
5494 } else {
5495 writeback = false;
5496 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5497 }
5498 r = EMULATE_USER_EXIT;
5499 } else if (vcpu->mmio_needed) {
5500 if (!vcpu->mmio_is_write)
5501 writeback = false;
5502 r = EMULATE_USER_EXIT;
5503 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5504 } else if (r == EMULATION_RESTART)
5505 goto restart;
5506 else
5507 r = EMULATE_DONE;
5508
5509 if (writeback) {
5510 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5511 toggle_interruptibility(vcpu, ctxt->interruptibility);
5512 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5513 if (vcpu->arch.hflags != ctxt->emul_flags)
5514 kvm_set_hflags(vcpu, ctxt->emul_flags);
5515 kvm_rip_write(vcpu, ctxt->eip);
5516 if (r == EMULATE_DONE)
5517 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5518 if (!ctxt->have_exception ||
5519 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5520 __kvm_set_rflags(vcpu, ctxt->eflags);
5521
5522 /*
5523 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5524 * do nothing, and it will be requested again as soon as
5525 * the shadow expires. But we still need to check here,
5526 * because POPF has no interrupt shadow.
5527 */
5528 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5529 kvm_make_request(KVM_REQ_EVENT, vcpu);
5530 } else
5531 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5532
5533 return r;
5534 }
5535 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5536
5537 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5538 {
5539 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5540 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5541 size, port, &val, 1);
5542 /* do not return to emulator after return from userspace */
5543 vcpu->arch.pio.count = 0;
5544 return ret;
5545 }
5546 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5547
5548 static void tsc_bad(void *info)
5549 {
5550 __this_cpu_write(cpu_tsc_khz, 0);
5551 }
5552
5553 static void tsc_khz_changed(void *data)
5554 {
5555 struct cpufreq_freqs *freq = data;
5556 unsigned long khz = 0;
5557
5558 if (data)
5559 khz = freq->new;
5560 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5561 khz = cpufreq_quick_get(raw_smp_processor_id());
5562 if (!khz)
5563 khz = tsc_khz;
5564 __this_cpu_write(cpu_tsc_khz, khz);
5565 }
5566
5567 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5568 void *data)
5569 {
5570 struct cpufreq_freqs *freq = data;
5571 struct kvm *kvm;
5572 struct kvm_vcpu *vcpu;
5573 int i, send_ipi = 0;
5574
5575 /*
5576 * We allow guests to temporarily run on slowing clocks,
5577 * provided we notify them after, or to run on accelerating
5578 * clocks, provided we notify them before. Thus time never
5579 * goes backwards.
5580 *
5581 * However, we have a problem. We can't atomically update
5582 * the frequency of a given CPU from this function; it is
5583 * merely a notifier, which can be called from any CPU.
5584 * Changing the TSC frequency at arbitrary points in time
5585 * requires a recomputation of local variables related to
5586 * the TSC for each VCPU. We must flag these local variables
5587 * to be updated and be sure the update takes place with the
5588 * new frequency before any guests proceed.
5589 *
5590 * Unfortunately, the combination of hotplug CPU and frequency
5591 * change creates an intractable locking scenario; the order
5592 * of when these callouts happen is undefined with respect to
5593 * CPU hotplug, and they can race with each other. As such,
5594 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5595 * undefined; you can actually have a CPU frequency change take
5596 * place in between the computation of X and the setting of the
5597 * variable. To protect against this problem, all updates of
5598 * the per_cpu tsc_khz variable are done in an interrupt
5599 * protected IPI, and all callers wishing to update the value
5600 * must wait for a synchronous IPI to complete (which is trivial
5601 * if the caller is on the CPU already). This establishes the
5602 * necessary total order on variable updates.
5603 *
5604 * Note that because a guest time update may take place
5605 * anytime after the setting of the VCPU's request bit, the
5606 * correct TSC value must be set before the request. However,
5607 * to ensure the update actually makes it to any guest which
5608 * starts running in hardware virtualization between the set
5609 * and the acquisition of the spinlock, we must also ping the
5610 * CPU after setting the request bit.
5611 *
5612 */
5613
5614 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5615 return 0;
5616 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5617 return 0;
5618
5619 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5620
5621 spin_lock(&kvm_lock);
5622 list_for_each_entry(kvm, &vm_list, vm_list) {
5623 kvm_for_each_vcpu(i, vcpu, kvm) {
5624 if (vcpu->cpu != freq->cpu)
5625 continue;
5626 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5627 if (vcpu->cpu != smp_processor_id())
5628 send_ipi = 1;
5629 }
5630 }
5631 spin_unlock(&kvm_lock);
5632
5633 if (freq->old < freq->new && send_ipi) {
5634 /*
5635 * We upscale the frequency. Must make the guest
5636 * doesn't see old kvmclock values while running with
5637 * the new frequency, otherwise we risk the guest sees
5638 * time go backwards.
5639 *
5640 * In case we update the frequency for another cpu
5641 * (which might be in guest context) send an interrupt
5642 * to kick the cpu out of guest context. Next time
5643 * guest context is entered kvmclock will be updated,
5644 * so the guest will not see stale values.
5645 */
5646 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5647 }
5648 return 0;
5649 }
5650
5651 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5652 .notifier_call = kvmclock_cpufreq_notifier
5653 };
5654
5655 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5656 unsigned long action, void *hcpu)
5657 {
5658 unsigned int cpu = (unsigned long)hcpu;
5659
5660 switch (action) {
5661 case CPU_ONLINE:
5662 case CPU_DOWN_FAILED:
5663 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5664 break;
5665 case CPU_DOWN_PREPARE:
5666 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5667 break;
5668 }
5669 return NOTIFY_OK;
5670 }
5671
5672 static struct notifier_block kvmclock_cpu_notifier_block = {
5673 .notifier_call = kvmclock_cpu_notifier,
5674 .priority = -INT_MAX
5675 };
5676
5677 static void kvm_timer_init(void)
5678 {
5679 int cpu;
5680
5681 max_tsc_khz = tsc_khz;
5682
5683 cpu_notifier_register_begin();
5684 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5685 #ifdef CONFIG_CPU_FREQ
5686 struct cpufreq_policy policy;
5687 memset(&policy, 0, sizeof(policy));
5688 cpu = get_cpu();
5689 cpufreq_get_policy(&policy, cpu);
5690 if (policy.cpuinfo.max_freq)
5691 max_tsc_khz = policy.cpuinfo.max_freq;
5692 put_cpu();
5693 #endif
5694 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5695 CPUFREQ_TRANSITION_NOTIFIER);
5696 }
5697 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5698 for_each_online_cpu(cpu)
5699 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5700
5701 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5702 cpu_notifier_register_done();
5703
5704 }
5705
5706 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5707
5708 int kvm_is_in_guest(void)
5709 {
5710 return __this_cpu_read(current_vcpu) != NULL;
5711 }
5712
5713 static int kvm_is_user_mode(void)
5714 {
5715 int user_mode = 3;
5716
5717 if (__this_cpu_read(current_vcpu))
5718 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5719
5720 return user_mode != 0;
5721 }
5722
5723 static unsigned long kvm_get_guest_ip(void)
5724 {
5725 unsigned long ip = 0;
5726
5727 if (__this_cpu_read(current_vcpu))
5728 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5729
5730 return ip;
5731 }
5732
5733 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5734 .is_in_guest = kvm_is_in_guest,
5735 .is_user_mode = kvm_is_user_mode,
5736 .get_guest_ip = kvm_get_guest_ip,
5737 };
5738
5739 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5740 {
5741 __this_cpu_write(current_vcpu, vcpu);
5742 }
5743 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5744
5745 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5746 {
5747 __this_cpu_write(current_vcpu, NULL);
5748 }
5749 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5750
5751 static void kvm_set_mmio_spte_mask(void)
5752 {
5753 u64 mask;
5754 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5755
5756 /*
5757 * Set the reserved bits and the present bit of an paging-structure
5758 * entry to generate page fault with PFER.RSV = 1.
5759 */
5760 /* Mask the reserved physical address bits. */
5761 mask = rsvd_bits(maxphyaddr, 51);
5762
5763 /* Bit 62 is always reserved for 32bit host. */
5764 mask |= 0x3ull << 62;
5765
5766 /* Set the present bit. */
5767 mask |= 1ull;
5768
5769 #ifdef CONFIG_X86_64
5770 /*
5771 * If reserved bit is not supported, clear the present bit to disable
5772 * mmio page fault.
5773 */
5774 if (maxphyaddr == 52)
5775 mask &= ~1ull;
5776 #endif
5777
5778 kvm_mmu_set_mmio_spte_mask(mask);
5779 }
5780
5781 #ifdef CONFIG_X86_64
5782 static void pvclock_gtod_update_fn(struct work_struct *work)
5783 {
5784 struct kvm *kvm;
5785
5786 struct kvm_vcpu *vcpu;
5787 int i;
5788
5789 spin_lock(&kvm_lock);
5790 list_for_each_entry(kvm, &vm_list, vm_list)
5791 kvm_for_each_vcpu(i, vcpu, kvm)
5792 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5793 atomic_set(&kvm_guest_has_master_clock, 0);
5794 spin_unlock(&kvm_lock);
5795 }
5796
5797 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5798
5799 /*
5800 * Notification about pvclock gtod data update.
5801 */
5802 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5803 void *priv)
5804 {
5805 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5806 struct timekeeper *tk = priv;
5807
5808 update_pvclock_gtod(tk);
5809
5810 /* disable master clock if host does not trust, or does not
5811 * use, TSC clocksource
5812 */
5813 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5814 atomic_read(&kvm_guest_has_master_clock) != 0)
5815 queue_work(system_long_wq, &pvclock_gtod_work);
5816
5817 return 0;
5818 }
5819
5820 static struct notifier_block pvclock_gtod_notifier = {
5821 .notifier_call = pvclock_gtod_notify,
5822 };
5823 #endif
5824
5825 int kvm_arch_init(void *opaque)
5826 {
5827 int r;
5828 struct kvm_x86_ops *ops = opaque;
5829
5830 if (kvm_x86_ops) {
5831 printk(KERN_ERR "kvm: already loaded the other module\n");
5832 r = -EEXIST;
5833 goto out;
5834 }
5835
5836 if (!ops->cpu_has_kvm_support()) {
5837 printk(KERN_ERR "kvm: no hardware support\n");
5838 r = -EOPNOTSUPP;
5839 goto out;
5840 }
5841 if (ops->disabled_by_bios()) {
5842 printk(KERN_ERR "kvm: disabled by bios\n");
5843 r = -EOPNOTSUPP;
5844 goto out;
5845 }
5846
5847 r = -ENOMEM;
5848 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5849 if (!shared_msrs) {
5850 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5851 goto out;
5852 }
5853
5854 r = kvm_mmu_module_init();
5855 if (r)
5856 goto out_free_percpu;
5857
5858 kvm_set_mmio_spte_mask();
5859
5860 kvm_x86_ops = ops;
5861
5862 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5863 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5864
5865 kvm_timer_init();
5866
5867 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5868
5869 if (cpu_has_xsave)
5870 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5871
5872 kvm_lapic_init();
5873 #ifdef CONFIG_X86_64
5874 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5875 #endif
5876
5877 return 0;
5878
5879 out_free_percpu:
5880 free_percpu(shared_msrs);
5881 out:
5882 return r;
5883 }
5884
5885 void kvm_arch_exit(void)
5886 {
5887 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5888
5889 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5890 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5891 CPUFREQ_TRANSITION_NOTIFIER);
5892 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5893 #ifdef CONFIG_X86_64
5894 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5895 #endif
5896 kvm_x86_ops = NULL;
5897 kvm_mmu_module_exit();
5898 free_percpu(shared_msrs);
5899 }
5900
5901 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5902 {
5903 ++vcpu->stat.halt_exits;
5904 if (lapic_in_kernel(vcpu)) {
5905 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5906 return 1;
5907 } else {
5908 vcpu->run->exit_reason = KVM_EXIT_HLT;
5909 return 0;
5910 }
5911 }
5912 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5913
5914 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5915 {
5916 kvm_x86_ops->skip_emulated_instruction(vcpu);
5917 return kvm_vcpu_halt(vcpu);
5918 }
5919 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5920
5921 /*
5922 * kvm_pv_kick_cpu_op: Kick a vcpu.
5923 *
5924 * @apicid - apicid of vcpu to be kicked.
5925 */
5926 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5927 {
5928 struct kvm_lapic_irq lapic_irq;
5929
5930 lapic_irq.shorthand = 0;
5931 lapic_irq.dest_mode = 0;
5932 lapic_irq.dest_id = apicid;
5933 lapic_irq.msi_redir_hint = false;
5934
5935 lapic_irq.delivery_mode = APIC_DM_REMRD;
5936 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5937 }
5938
5939 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5940 {
5941 vcpu->arch.apicv_active = false;
5942 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5943 }
5944
5945 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5946 {
5947 unsigned long nr, a0, a1, a2, a3, ret;
5948 int op_64_bit, r = 1;
5949
5950 kvm_x86_ops->skip_emulated_instruction(vcpu);
5951
5952 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5953 return kvm_hv_hypercall(vcpu);
5954
5955 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5956 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5957 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5958 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5959 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5960
5961 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5962
5963 op_64_bit = is_64_bit_mode(vcpu);
5964 if (!op_64_bit) {
5965 nr &= 0xFFFFFFFF;
5966 a0 &= 0xFFFFFFFF;
5967 a1 &= 0xFFFFFFFF;
5968 a2 &= 0xFFFFFFFF;
5969 a3 &= 0xFFFFFFFF;
5970 }
5971
5972 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5973 ret = -KVM_EPERM;
5974 goto out;
5975 }
5976
5977 switch (nr) {
5978 case KVM_HC_VAPIC_POLL_IRQ:
5979 ret = 0;
5980 break;
5981 case KVM_HC_KICK_CPU:
5982 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5983 ret = 0;
5984 break;
5985 default:
5986 ret = -KVM_ENOSYS;
5987 break;
5988 }
5989 out:
5990 if (!op_64_bit)
5991 ret = (u32)ret;
5992 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5993 ++vcpu->stat.hypercalls;
5994 return r;
5995 }
5996 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5997
5998 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5999 {
6000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6001 char instruction[3];
6002 unsigned long rip = kvm_rip_read(vcpu);
6003
6004 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6005
6006 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
6007 }
6008
6009 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6010 {
6011 return vcpu->run->request_interrupt_window &&
6012 likely(!pic_in_kernel(vcpu->kvm));
6013 }
6014
6015 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6016 {
6017 struct kvm_run *kvm_run = vcpu->run;
6018
6019 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6020 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6021 kvm_run->cr8 = kvm_get_cr8(vcpu);
6022 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6023 kvm_run->ready_for_interrupt_injection =
6024 pic_in_kernel(vcpu->kvm) ||
6025 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6026 }
6027
6028 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6029 {
6030 int max_irr, tpr;
6031
6032 if (!kvm_x86_ops->update_cr8_intercept)
6033 return;
6034
6035 if (!lapic_in_kernel(vcpu))
6036 return;
6037
6038 if (vcpu->arch.apicv_active)
6039 return;
6040
6041 if (!vcpu->arch.apic->vapic_addr)
6042 max_irr = kvm_lapic_find_highest_irr(vcpu);
6043 else
6044 max_irr = -1;
6045
6046 if (max_irr != -1)
6047 max_irr >>= 4;
6048
6049 tpr = kvm_lapic_get_cr8(vcpu);
6050
6051 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6052 }
6053
6054 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6055 {
6056 int r;
6057
6058 /* try to reinject previous events if any */
6059 if (vcpu->arch.exception.pending) {
6060 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6061 vcpu->arch.exception.has_error_code,
6062 vcpu->arch.exception.error_code);
6063
6064 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6065 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6066 X86_EFLAGS_RF);
6067
6068 if (vcpu->arch.exception.nr == DB_VECTOR &&
6069 (vcpu->arch.dr7 & DR7_GD)) {
6070 vcpu->arch.dr7 &= ~DR7_GD;
6071 kvm_update_dr7(vcpu);
6072 }
6073
6074 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6075 vcpu->arch.exception.has_error_code,
6076 vcpu->arch.exception.error_code,
6077 vcpu->arch.exception.reinject);
6078 return 0;
6079 }
6080
6081 if (vcpu->arch.nmi_injected) {
6082 kvm_x86_ops->set_nmi(vcpu);
6083 return 0;
6084 }
6085
6086 if (vcpu->arch.interrupt.pending) {
6087 kvm_x86_ops->set_irq(vcpu);
6088 return 0;
6089 }
6090
6091 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6092 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6093 if (r != 0)
6094 return r;
6095 }
6096
6097 /* try to inject new event if pending */
6098 if (vcpu->arch.nmi_pending) {
6099 if (kvm_x86_ops->nmi_allowed(vcpu)) {
6100 --vcpu->arch.nmi_pending;
6101 vcpu->arch.nmi_injected = true;
6102 kvm_x86_ops->set_nmi(vcpu);
6103 }
6104 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6105 /*
6106 * Because interrupts can be injected asynchronously, we are
6107 * calling check_nested_events again here to avoid a race condition.
6108 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6109 * proposal and current concerns. Perhaps we should be setting
6110 * KVM_REQ_EVENT only on certain events and not unconditionally?
6111 */
6112 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6113 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6114 if (r != 0)
6115 return r;
6116 }
6117 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6118 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6119 false);
6120 kvm_x86_ops->set_irq(vcpu);
6121 }
6122 }
6123 return 0;
6124 }
6125
6126 static void process_nmi(struct kvm_vcpu *vcpu)
6127 {
6128 unsigned limit = 2;
6129
6130 /*
6131 * x86 is limited to one NMI running, and one NMI pending after it.
6132 * If an NMI is already in progress, limit further NMIs to just one.
6133 * Otherwise, allow two (and we'll inject the first one immediately).
6134 */
6135 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6136 limit = 1;
6137
6138 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6139 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6140 kvm_make_request(KVM_REQ_EVENT, vcpu);
6141 }
6142
6143 #define put_smstate(type, buf, offset, val) \
6144 *(type *)((buf) + (offset) - 0x7e00) = val
6145
6146 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6147 {
6148 u32 flags = 0;
6149 flags |= seg->g << 23;
6150 flags |= seg->db << 22;
6151 flags |= seg->l << 21;
6152 flags |= seg->avl << 20;
6153 flags |= seg->present << 15;
6154 flags |= seg->dpl << 13;
6155 flags |= seg->s << 12;
6156 flags |= seg->type << 8;
6157 return flags;
6158 }
6159
6160 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6161 {
6162 struct kvm_segment seg;
6163 int offset;
6164
6165 kvm_get_segment(vcpu, &seg, n);
6166 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6167
6168 if (n < 3)
6169 offset = 0x7f84 + n * 12;
6170 else
6171 offset = 0x7f2c + (n - 3) * 12;
6172
6173 put_smstate(u32, buf, offset + 8, seg.base);
6174 put_smstate(u32, buf, offset + 4, seg.limit);
6175 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6176 }
6177
6178 #ifdef CONFIG_X86_64
6179 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6180 {
6181 struct kvm_segment seg;
6182 int offset;
6183 u16 flags;
6184
6185 kvm_get_segment(vcpu, &seg, n);
6186 offset = 0x7e00 + n * 16;
6187
6188 flags = process_smi_get_segment_flags(&seg) >> 8;
6189 put_smstate(u16, buf, offset, seg.selector);
6190 put_smstate(u16, buf, offset + 2, flags);
6191 put_smstate(u32, buf, offset + 4, seg.limit);
6192 put_smstate(u64, buf, offset + 8, seg.base);
6193 }
6194 #endif
6195
6196 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6197 {
6198 struct desc_ptr dt;
6199 struct kvm_segment seg;
6200 unsigned long val;
6201 int i;
6202
6203 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6204 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6205 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6206 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6207
6208 for (i = 0; i < 8; i++)
6209 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6210
6211 kvm_get_dr(vcpu, 6, &val);
6212 put_smstate(u32, buf, 0x7fcc, (u32)val);
6213 kvm_get_dr(vcpu, 7, &val);
6214 put_smstate(u32, buf, 0x7fc8, (u32)val);
6215
6216 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6217 put_smstate(u32, buf, 0x7fc4, seg.selector);
6218 put_smstate(u32, buf, 0x7f64, seg.base);
6219 put_smstate(u32, buf, 0x7f60, seg.limit);
6220 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6221
6222 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6223 put_smstate(u32, buf, 0x7fc0, seg.selector);
6224 put_smstate(u32, buf, 0x7f80, seg.base);
6225 put_smstate(u32, buf, 0x7f7c, seg.limit);
6226 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6227
6228 kvm_x86_ops->get_gdt(vcpu, &dt);
6229 put_smstate(u32, buf, 0x7f74, dt.address);
6230 put_smstate(u32, buf, 0x7f70, dt.size);
6231
6232 kvm_x86_ops->get_idt(vcpu, &dt);
6233 put_smstate(u32, buf, 0x7f58, dt.address);
6234 put_smstate(u32, buf, 0x7f54, dt.size);
6235
6236 for (i = 0; i < 6; i++)
6237 process_smi_save_seg_32(vcpu, buf, i);
6238
6239 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6240
6241 /* revision id */
6242 put_smstate(u32, buf, 0x7efc, 0x00020000);
6243 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6244 }
6245
6246 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6247 {
6248 #ifdef CONFIG_X86_64
6249 struct desc_ptr dt;
6250 struct kvm_segment seg;
6251 unsigned long val;
6252 int i;
6253
6254 for (i = 0; i < 16; i++)
6255 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6256
6257 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6258 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6259
6260 kvm_get_dr(vcpu, 6, &val);
6261 put_smstate(u64, buf, 0x7f68, val);
6262 kvm_get_dr(vcpu, 7, &val);
6263 put_smstate(u64, buf, 0x7f60, val);
6264
6265 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6266 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6267 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6268
6269 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6270
6271 /* revision id */
6272 put_smstate(u32, buf, 0x7efc, 0x00020064);
6273
6274 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6275
6276 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6277 put_smstate(u16, buf, 0x7e90, seg.selector);
6278 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6279 put_smstate(u32, buf, 0x7e94, seg.limit);
6280 put_smstate(u64, buf, 0x7e98, seg.base);
6281
6282 kvm_x86_ops->get_idt(vcpu, &dt);
6283 put_smstate(u32, buf, 0x7e84, dt.size);
6284 put_smstate(u64, buf, 0x7e88, dt.address);
6285
6286 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6287 put_smstate(u16, buf, 0x7e70, seg.selector);
6288 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6289 put_smstate(u32, buf, 0x7e74, seg.limit);
6290 put_smstate(u64, buf, 0x7e78, seg.base);
6291
6292 kvm_x86_ops->get_gdt(vcpu, &dt);
6293 put_smstate(u32, buf, 0x7e64, dt.size);
6294 put_smstate(u64, buf, 0x7e68, dt.address);
6295
6296 for (i = 0; i < 6; i++)
6297 process_smi_save_seg_64(vcpu, buf, i);
6298 #else
6299 WARN_ON_ONCE(1);
6300 #endif
6301 }
6302
6303 static void process_smi(struct kvm_vcpu *vcpu)
6304 {
6305 struct kvm_segment cs, ds;
6306 struct desc_ptr dt;
6307 char buf[512];
6308 u32 cr0;
6309
6310 if (is_smm(vcpu)) {
6311 vcpu->arch.smi_pending = true;
6312 return;
6313 }
6314
6315 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6316 vcpu->arch.hflags |= HF_SMM_MASK;
6317 memset(buf, 0, 512);
6318 if (guest_cpuid_has_longmode(vcpu))
6319 process_smi_save_state_64(vcpu, buf);
6320 else
6321 process_smi_save_state_32(vcpu, buf);
6322
6323 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6324
6325 if (kvm_x86_ops->get_nmi_mask(vcpu))
6326 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6327 else
6328 kvm_x86_ops->set_nmi_mask(vcpu, true);
6329
6330 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6331 kvm_rip_write(vcpu, 0x8000);
6332
6333 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6334 kvm_x86_ops->set_cr0(vcpu, cr0);
6335 vcpu->arch.cr0 = cr0;
6336
6337 kvm_x86_ops->set_cr4(vcpu, 0);
6338
6339 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6340 dt.address = dt.size = 0;
6341 kvm_x86_ops->set_idt(vcpu, &dt);
6342
6343 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6344
6345 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6346 cs.base = vcpu->arch.smbase;
6347
6348 ds.selector = 0;
6349 ds.base = 0;
6350
6351 cs.limit = ds.limit = 0xffffffff;
6352 cs.type = ds.type = 0x3;
6353 cs.dpl = ds.dpl = 0;
6354 cs.db = ds.db = 0;
6355 cs.s = ds.s = 1;
6356 cs.l = ds.l = 0;
6357 cs.g = ds.g = 1;
6358 cs.avl = ds.avl = 0;
6359 cs.present = ds.present = 1;
6360 cs.unusable = ds.unusable = 0;
6361 cs.padding = ds.padding = 0;
6362
6363 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6364 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6365 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6366 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6367 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6368 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6369
6370 if (guest_cpuid_has_longmode(vcpu))
6371 kvm_x86_ops->set_efer(vcpu, 0);
6372
6373 kvm_update_cpuid(vcpu);
6374 kvm_mmu_reset_context(vcpu);
6375 }
6376
6377 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6378 {
6379 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6380 }
6381
6382 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6383 {
6384 u64 eoi_exit_bitmap[4];
6385
6386 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6387 return;
6388
6389 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6390
6391 if (irqchip_split(vcpu->kvm))
6392 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6393 else {
6394 if (vcpu->arch.apicv_active)
6395 kvm_x86_ops->sync_pir_to_irr(vcpu);
6396 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6397 }
6398 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6399 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6400 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6401 }
6402
6403 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6404 {
6405 ++vcpu->stat.tlb_flush;
6406 kvm_x86_ops->tlb_flush(vcpu);
6407 }
6408
6409 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6410 {
6411 struct page *page = NULL;
6412
6413 if (!lapic_in_kernel(vcpu))
6414 return;
6415
6416 if (!kvm_x86_ops->set_apic_access_page_addr)
6417 return;
6418
6419 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6420 if (is_error_page(page))
6421 return;
6422 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6423
6424 /*
6425 * Do not pin apic access page in memory, the MMU notifier
6426 * will call us again if it is migrated or swapped out.
6427 */
6428 put_page(page);
6429 }
6430 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6431
6432 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6433 unsigned long address)
6434 {
6435 /*
6436 * The physical address of apic access page is stored in the VMCS.
6437 * Update it when it becomes invalid.
6438 */
6439 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6440 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6441 }
6442
6443 /*
6444 * Returns 1 to let vcpu_run() continue the guest execution loop without
6445 * exiting to the userspace. Otherwise, the value will be returned to the
6446 * userspace.
6447 */
6448 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6449 {
6450 int r;
6451 bool req_int_win =
6452 dm_request_for_irq_injection(vcpu) &&
6453 kvm_cpu_accept_dm_intr(vcpu);
6454
6455 bool req_immediate_exit = false;
6456
6457 if (vcpu->requests) {
6458 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6459 kvm_mmu_unload(vcpu);
6460 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6461 __kvm_migrate_timers(vcpu);
6462 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6463 kvm_gen_update_masterclock(vcpu->kvm);
6464 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6465 kvm_gen_kvmclock_update(vcpu);
6466 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6467 r = kvm_guest_time_update(vcpu);
6468 if (unlikely(r))
6469 goto out;
6470 }
6471 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6472 kvm_mmu_sync_roots(vcpu);
6473 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6474 kvm_vcpu_flush_tlb(vcpu);
6475 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6476 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6477 r = 0;
6478 goto out;
6479 }
6480 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6481 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6482 r = 0;
6483 goto out;
6484 }
6485 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6486 vcpu->fpu_active = 0;
6487 kvm_x86_ops->fpu_deactivate(vcpu);
6488 }
6489 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6490 /* Page is swapped out. Do synthetic halt */
6491 vcpu->arch.apf.halted = true;
6492 r = 1;
6493 goto out;
6494 }
6495 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6496 record_steal_time(vcpu);
6497 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6498 process_smi(vcpu);
6499 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6500 process_nmi(vcpu);
6501 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6502 kvm_pmu_handle_event(vcpu);
6503 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6504 kvm_pmu_deliver_pmi(vcpu);
6505 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6506 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6507 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6508 vcpu->arch.ioapic_handled_vectors)) {
6509 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6510 vcpu->run->eoi.vector =
6511 vcpu->arch.pending_ioapic_eoi;
6512 r = 0;
6513 goto out;
6514 }
6515 }
6516 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6517 vcpu_scan_ioapic(vcpu);
6518 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6519 kvm_vcpu_reload_apic_access_page(vcpu);
6520 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6521 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6522 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6523 r = 0;
6524 goto out;
6525 }
6526 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6527 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6528 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6529 r = 0;
6530 goto out;
6531 }
6532 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6533 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6534 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6535 r = 0;
6536 goto out;
6537 }
6538
6539 /*
6540 * KVM_REQ_HV_STIMER has to be processed after
6541 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6542 * depend on the guest clock being up-to-date
6543 */
6544 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6545 kvm_hv_process_stimers(vcpu);
6546 }
6547
6548 /*
6549 * KVM_REQ_EVENT is not set when posted interrupts are set by
6550 * VT-d hardware, so we have to update RVI unconditionally.
6551 */
6552 if (kvm_lapic_enabled(vcpu)) {
6553 /*
6554 * Update architecture specific hints for APIC
6555 * virtual interrupt delivery.
6556 */
6557 if (vcpu->arch.apicv_active)
6558 kvm_x86_ops->hwapic_irr_update(vcpu,
6559 kvm_lapic_find_highest_irr(vcpu));
6560 }
6561
6562 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6563 kvm_apic_accept_events(vcpu);
6564 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6565 r = 1;
6566 goto out;
6567 }
6568
6569 if (inject_pending_event(vcpu, req_int_win) != 0)
6570 req_immediate_exit = true;
6571 /* enable NMI/IRQ window open exits if needed */
6572 else if (vcpu->arch.nmi_pending)
6573 kvm_x86_ops->enable_nmi_window(vcpu);
6574 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6575 kvm_x86_ops->enable_irq_window(vcpu);
6576
6577 if (kvm_lapic_enabled(vcpu)) {
6578 update_cr8_intercept(vcpu);
6579 kvm_lapic_sync_to_vapic(vcpu);
6580 }
6581 }
6582
6583 r = kvm_mmu_reload(vcpu);
6584 if (unlikely(r)) {
6585 goto cancel_injection;
6586 }
6587
6588 preempt_disable();
6589
6590 kvm_x86_ops->prepare_guest_switch(vcpu);
6591 if (vcpu->fpu_active)
6592 kvm_load_guest_fpu(vcpu);
6593 kvm_load_guest_xcr0(vcpu);
6594
6595 vcpu->mode = IN_GUEST_MODE;
6596
6597 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6598
6599 /* We should set ->mode before check ->requests,
6600 * see the comment in make_all_cpus_request.
6601 */
6602 smp_mb__after_srcu_read_unlock();
6603
6604 local_irq_disable();
6605
6606 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6607 || need_resched() || signal_pending(current)) {
6608 vcpu->mode = OUTSIDE_GUEST_MODE;
6609 smp_wmb();
6610 local_irq_enable();
6611 preempt_enable();
6612 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6613 r = 1;
6614 goto cancel_injection;
6615 }
6616
6617 if (req_immediate_exit)
6618 smp_send_reschedule(vcpu->cpu);
6619
6620 trace_kvm_entry(vcpu->vcpu_id);
6621 wait_lapic_expire(vcpu);
6622 __kvm_guest_enter();
6623
6624 if (unlikely(vcpu->arch.switch_db_regs)) {
6625 set_debugreg(0, 7);
6626 set_debugreg(vcpu->arch.eff_db[0], 0);
6627 set_debugreg(vcpu->arch.eff_db[1], 1);
6628 set_debugreg(vcpu->arch.eff_db[2], 2);
6629 set_debugreg(vcpu->arch.eff_db[3], 3);
6630 set_debugreg(vcpu->arch.dr6, 6);
6631 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6632 }
6633
6634 kvm_x86_ops->run(vcpu);
6635
6636 /*
6637 * Do this here before restoring debug registers on the host. And
6638 * since we do this before handling the vmexit, a DR access vmexit
6639 * can (a) read the correct value of the debug registers, (b) set
6640 * KVM_DEBUGREG_WONT_EXIT again.
6641 */
6642 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6643 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6644 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6645 kvm_update_dr0123(vcpu);
6646 kvm_update_dr6(vcpu);
6647 kvm_update_dr7(vcpu);
6648 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6649 }
6650
6651 /*
6652 * If the guest has used debug registers, at least dr7
6653 * will be disabled while returning to the host.
6654 * If we don't have active breakpoints in the host, we don't
6655 * care about the messed up debug address registers. But if
6656 * we have some of them active, restore the old state.
6657 */
6658 if (hw_breakpoint_active())
6659 hw_breakpoint_restore();
6660
6661 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6662
6663 vcpu->mode = OUTSIDE_GUEST_MODE;
6664 smp_wmb();
6665
6666 /* Interrupt is enabled by handle_external_intr() */
6667 kvm_x86_ops->handle_external_intr(vcpu);
6668
6669 ++vcpu->stat.exits;
6670
6671 /*
6672 * We must have an instruction between local_irq_enable() and
6673 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6674 * the interrupt shadow. The stat.exits increment will do nicely.
6675 * But we need to prevent reordering, hence this barrier():
6676 */
6677 barrier();
6678
6679 kvm_guest_exit();
6680
6681 preempt_enable();
6682
6683 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6684
6685 /*
6686 * Profile KVM exit RIPs:
6687 */
6688 if (unlikely(prof_on == KVM_PROFILING)) {
6689 unsigned long rip = kvm_rip_read(vcpu);
6690 profile_hit(KVM_PROFILING, (void *)rip);
6691 }
6692
6693 if (unlikely(vcpu->arch.tsc_always_catchup))
6694 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6695
6696 if (vcpu->arch.apic_attention)
6697 kvm_lapic_sync_from_vapic(vcpu);
6698
6699 r = kvm_x86_ops->handle_exit(vcpu);
6700 return r;
6701
6702 cancel_injection:
6703 kvm_x86_ops->cancel_injection(vcpu);
6704 if (unlikely(vcpu->arch.apic_attention))
6705 kvm_lapic_sync_from_vapic(vcpu);
6706 out:
6707 return r;
6708 }
6709
6710 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6711 {
6712 if (!kvm_arch_vcpu_runnable(vcpu) &&
6713 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6714 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6715 kvm_vcpu_block(vcpu);
6716 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6717
6718 if (kvm_x86_ops->post_block)
6719 kvm_x86_ops->post_block(vcpu);
6720
6721 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6722 return 1;
6723 }
6724
6725 kvm_apic_accept_events(vcpu);
6726 switch(vcpu->arch.mp_state) {
6727 case KVM_MP_STATE_HALTED:
6728 vcpu->arch.pv.pv_unhalted = false;
6729 vcpu->arch.mp_state =
6730 KVM_MP_STATE_RUNNABLE;
6731 case KVM_MP_STATE_RUNNABLE:
6732 vcpu->arch.apf.halted = false;
6733 break;
6734 case KVM_MP_STATE_INIT_RECEIVED:
6735 break;
6736 default:
6737 return -EINTR;
6738 break;
6739 }
6740 return 1;
6741 }
6742
6743 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6744 {
6745 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6746 !vcpu->arch.apf.halted);
6747 }
6748
6749 static int vcpu_run(struct kvm_vcpu *vcpu)
6750 {
6751 int r;
6752 struct kvm *kvm = vcpu->kvm;
6753
6754 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6755
6756 for (;;) {
6757 if (kvm_vcpu_running(vcpu)) {
6758 r = vcpu_enter_guest(vcpu);
6759 } else {
6760 r = vcpu_block(kvm, vcpu);
6761 }
6762
6763 if (r <= 0)
6764 break;
6765
6766 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6767 if (kvm_cpu_has_pending_timer(vcpu))
6768 kvm_inject_pending_timer_irqs(vcpu);
6769
6770 if (dm_request_for_irq_injection(vcpu) &&
6771 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6772 r = 0;
6773 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6774 ++vcpu->stat.request_irq_exits;
6775 break;
6776 }
6777
6778 kvm_check_async_pf_completion(vcpu);
6779
6780 if (signal_pending(current)) {
6781 r = -EINTR;
6782 vcpu->run->exit_reason = KVM_EXIT_INTR;
6783 ++vcpu->stat.signal_exits;
6784 break;
6785 }
6786 if (need_resched()) {
6787 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6788 cond_resched();
6789 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6790 }
6791 }
6792
6793 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6794
6795 return r;
6796 }
6797
6798 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6799 {
6800 int r;
6801 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6802 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6803 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6804 if (r != EMULATE_DONE)
6805 return 0;
6806 return 1;
6807 }
6808
6809 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6810 {
6811 BUG_ON(!vcpu->arch.pio.count);
6812
6813 return complete_emulated_io(vcpu);
6814 }
6815
6816 /*
6817 * Implements the following, as a state machine:
6818 *
6819 * read:
6820 * for each fragment
6821 * for each mmio piece in the fragment
6822 * write gpa, len
6823 * exit
6824 * copy data
6825 * execute insn
6826 *
6827 * write:
6828 * for each fragment
6829 * for each mmio piece in the fragment
6830 * write gpa, len
6831 * copy data
6832 * exit
6833 */
6834 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6835 {
6836 struct kvm_run *run = vcpu->run;
6837 struct kvm_mmio_fragment *frag;
6838 unsigned len;
6839
6840 BUG_ON(!vcpu->mmio_needed);
6841
6842 /* Complete previous fragment */
6843 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6844 len = min(8u, frag->len);
6845 if (!vcpu->mmio_is_write)
6846 memcpy(frag->data, run->mmio.data, len);
6847
6848 if (frag->len <= 8) {
6849 /* Switch to the next fragment. */
6850 frag++;
6851 vcpu->mmio_cur_fragment++;
6852 } else {
6853 /* Go forward to the next mmio piece. */
6854 frag->data += len;
6855 frag->gpa += len;
6856 frag->len -= len;
6857 }
6858
6859 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6860 vcpu->mmio_needed = 0;
6861
6862 /* FIXME: return into emulator if single-stepping. */
6863 if (vcpu->mmio_is_write)
6864 return 1;
6865 vcpu->mmio_read_completed = 1;
6866 return complete_emulated_io(vcpu);
6867 }
6868
6869 run->exit_reason = KVM_EXIT_MMIO;
6870 run->mmio.phys_addr = frag->gpa;
6871 if (vcpu->mmio_is_write)
6872 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6873 run->mmio.len = min(8u, frag->len);
6874 run->mmio.is_write = vcpu->mmio_is_write;
6875 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6876 return 0;
6877 }
6878
6879
6880 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6881 {
6882 struct fpu *fpu = &current->thread.fpu;
6883 int r;
6884 sigset_t sigsaved;
6885
6886 fpu__activate_curr(fpu);
6887
6888 if (vcpu->sigset_active)
6889 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6890
6891 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6892 kvm_vcpu_block(vcpu);
6893 kvm_apic_accept_events(vcpu);
6894 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6895 r = -EAGAIN;
6896 goto out;
6897 }
6898
6899 /* re-sync apic's tpr */
6900 if (!lapic_in_kernel(vcpu)) {
6901 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6902 r = -EINVAL;
6903 goto out;
6904 }
6905 }
6906
6907 if (unlikely(vcpu->arch.complete_userspace_io)) {
6908 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6909 vcpu->arch.complete_userspace_io = NULL;
6910 r = cui(vcpu);
6911 if (r <= 0)
6912 goto out;
6913 } else
6914 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6915
6916 r = vcpu_run(vcpu);
6917
6918 out:
6919 post_kvm_run_save(vcpu);
6920 if (vcpu->sigset_active)
6921 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6922
6923 return r;
6924 }
6925
6926 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6927 {
6928 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6929 /*
6930 * We are here if userspace calls get_regs() in the middle of
6931 * instruction emulation. Registers state needs to be copied
6932 * back from emulation context to vcpu. Userspace shouldn't do
6933 * that usually, but some bad designed PV devices (vmware
6934 * backdoor interface) need this to work
6935 */
6936 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6937 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6938 }
6939 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6940 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6941 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6942 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6943 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6944 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6945 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6946 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6947 #ifdef CONFIG_X86_64
6948 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6949 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6950 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6951 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6952 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6953 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6954 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6955 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6956 #endif
6957
6958 regs->rip = kvm_rip_read(vcpu);
6959 regs->rflags = kvm_get_rflags(vcpu);
6960
6961 return 0;
6962 }
6963
6964 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6965 {
6966 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6967 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6968
6969 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6970 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6971 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6972 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6973 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6974 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6975 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6976 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6977 #ifdef CONFIG_X86_64
6978 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6979 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6980 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6981 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6982 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6983 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6984 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6985 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6986 #endif
6987
6988 kvm_rip_write(vcpu, regs->rip);
6989 kvm_set_rflags(vcpu, regs->rflags);
6990
6991 vcpu->arch.exception.pending = false;
6992
6993 kvm_make_request(KVM_REQ_EVENT, vcpu);
6994
6995 return 0;
6996 }
6997
6998 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6999 {
7000 struct kvm_segment cs;
7001
7002 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7003 *db = cs.db;
7004 *l = cs.l;
7005 }
7006 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7007
7008 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7009 struct kvm_sregs *sregs)
7010 {
7011 struct desc_ptr dt;
7012
7013 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7014 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7015 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7016 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7017 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7018 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7019
7020 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7021 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7022
7023 kvm_x86_ops->get_idt(vcpu, &dt);
7024 sregs->idt.limit = dt.size;
7025 sregs->idt.base = dt.address;
7026 kvm_x86_ops->get_gdt(vcpu, &dt);
7027 sregs->gdt.limit = dt.size;
7028 sregs->gdt.base = dt.address;
7029
7030 sregs->cr0 = kvm_read_cr0(vcpu);
7031 sregs->cr2 = vcpu->arch.cr2;
7032 sregs->cr3 = kvm_read_cr3(vcpu);
7033 sregs->cr4 = kvm_read_cr4(vcpu);
7034 sregs->cr8 = kvm_get_cr8(vcpu);
7035 sregs->efer = vcpu->arch.efer;
7036 sregs->apic_base = kvm_get_apic_base(vcpu);
7037
7038 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7039
7040 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7041 set_bit(vcpu->arch.interrupt.nr,
7042 (unsigned long *)sregs->interrupt_bitmap);
7043
7044 return 0;
7045 }
7046
7047 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7048 struct kvm_mp_state *mp_state)
7049 {
7050 kvm_apic_accept_events(vcpu);
7051 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7052 vcpu->arch.pv.pv_unhalted)
7053 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7054 else
7055 mp_state->mp_state = vcpu->arch.mp_state;
7056
7057 return 0;
7058 }
7059
7060 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7061 struct kvm_mp_state *mp_state)
7062 {
7063 if (!lapic_in_kernel(vcpu) &&
7064 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7065 return -EINVAL;
7066
7067 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7068 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7069 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7070 } else
7071 vcpu->arch.mp_state = mp_state->mp_state;
7072 kvm_make_request(KVM_REQ_EVENT, vcpu);
7073 return 0;
7074 }
7075
7076 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7077 int reason, bool has_error_code, u32 error_code)
7078 {
7079 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7080 int ret;
7081
7082 init_emulate_ctxt(vcpu);
7083
7084 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7085 has_error_code, error_code);
7086
7087 if (ret)
7088 return EMULATE_FAIL;
7089
7090 kvm_rip_write(vcpu, ctxt->eip);
7091 kvm_set_rflags(vcpu, ctxt->eflags);
7092 kvm_make_request(KVM_REQ_EVENT, vcpu);
7093 return EMULATE_DONE;
7094 }
7095 EXPORT_SYMBOL_GPL(kvm_task_switch);
7096
7097 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7098 struct kvm_sregs *sregs)
7099 {
7100 struct msr_data apic_base_msr;
7101 int mmu_reset_needed = 0;
7102 int pending_vec, max_bits, idx;
7103 struct desc_ptr dt;
7104
7105 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7106 return -EINVAL;
7107
7108 dt.size = sregs->idt.limit;
7109 dt.address = sregs->idt.base;
7110 kvm_x86_ops->set_idt(vcpu, &dt);
7111 dt.size = sregs->gdt.limit;
7112 dt.address = sregs->gdt.base;
7113 kvm_x86_ops->set_gdt(vcpu, &dt);
7114
7115 vcpu->arch.cr2 = sregs->cr2;
7116 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7117 vcpu->arch.cr3 = sregs->cr3;
7118 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7119
7120 kvm_set_cr8(vcpu, sregs->cr8);
7121
7122 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7123 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7124 apic_base_msr.data = sregs->apic_base;
7125 apic_base_msr.host_initiated = true;
7126 kvm_set_apic_base(vcpu, &apic_base_msr);
7127
7128 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7129 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7130 vcpu->arch.cr0 = sregs->cr0;
7131
7132 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7133 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7134 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7135 kvm_update_cpuid(vcpu);
7136
7137 idx = srcu_read_lock(&vcpu->kvm->srcu);
7138 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7139 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7140 mmu_reset_needed = 1;
7141 }
7142 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7143
7144 if (mmu_reset_needed)
7145 kvm_mmu_reset_context(vcpu);
7146
7147 max_bits = KVM_NR_INTERRUPTS;
7148 pending_vec = find_first_bit(
7149 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7150 if (pending_vec < max_bits) {
7151 kvm_queue_interrupt(vcpu, pending_vec, false);
7152 pr_debug("Set back pending irq %d\n", pending_vec);
7153 }
7154
7155 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7156 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7157 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7158 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7159 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7160 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7161
7162 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7163 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7164
7165 update_cr8_intercept(vcpu);
7166
7167 /* Older userspace won't unhalt the vcpu on reset. */
7168 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7169 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7170 !is_protmode(vcpu))
7171 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7172
7173 kvm_make_request(KVM_REQ_EVENT, vcpu);
7174
7175 return 0;
7176 }
7177
7178 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7179 struct kvm_guest_debug *dbg)
7180 {
7181 unsigned long rflags;
7182 int i, r;
7183
7184 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7185 r = -EBUSY;
7186 if (vcpu->arch.exception.pending)
7187 goto out;
7188 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7189 kvm_queue_exception(vcpu, DB_VECTOR);
7190 else
7191 kvm_queue_exception(vcpu, BP_VECTOR);
7192 }
7193
7194 /*
7195 * Read rflags as long as potentially injected trace flags are still
7196 * filtered out.
7197 */
7198 rflags = kvm_get_rflags(vcpu);
7199
7200 vcpu->guest_debug = dbg->control;
7201 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7202 vcpu->guest_debug = 0;
7203
7204 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7205 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7206 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7207 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7208 } else {
7209 for (i = 0; i < KVM_NR_DB_REGS; i++)
7210 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7211 }
7212 kvm_update_dr7(vcpu);
7213
7214 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7215 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7216 get_segment_base(vcpu, VCPU_SREG_CS);
7217
7218 /*
7219 * Trigger an rflags update that will inject or remove the trace
7220 * flags.
7221 */
7222 kvm_set_rflags(vcpu, rflags);
7223
7224 kvm_x86_ops->update_bp_intercept(vcpu);
7225
7226 r = 0;
7227
7228 out:
7229
7230 return r;
7231 }
7232
7233 /*
7234 * Translate a guest virtual address to a guest physical address.
7235 */
7236 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7237 struct kvm_translation *tr)
7238 {
7239 unsigned long vaddr = tr->linear_address;
7240 gpa_t gpa;
7241 int idx;
7242
7243 idx = srcu_read_lock(&vcpu->kvm->srcu);
7244 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7245 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7246 tr->physical_address = gpa;
7247 tr->valid = gpa != UNMAPPED_GVA;
7248 tr->writeable = 1;
7249 tr->usermode = 0;
7250
7251 return 0;
7252 }
7253
7254 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7255 {
7256 struct fxregs_state *fxsave =
7257 &vcpu->arch.guest_fpu.state.fxsave;
7258
7259 memcpy(fpu->fpr, fxsave->st_space, 128);
7260 fpu->fcw = fxsave->cwd;
7261 fpu->fsw = fxsave->swd;
7262 fpu->ftwx = fxsave->twd;
7263 fpu->last_opcode = fxsave->fop;
7264 fpu->last_ip = fxsave->rip;
7265 fpu->last_dp = fxsave->rdp;
7266 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7267
7268 return 0;
7269 }
7270
7271 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7272 {
7273 struct fxregs_state *fxsave =
7274 &vcpu->arch.guest_fpu.state.fxsave;
7275
7276 memcpy(fxsave->st_space, fpu->fpr, 128);
7277 fxsave->cwd = fpu->fcw;
7278 fxsave->swd = fpu->fsw;
7279 fxsave->twd = fpu->ftwx;
7280 fxsave->fop = fpu->last_opcode;
7281 fxsave->rip = fpu->last_ip;
7282 fxsave->rdp = fpu->last_dp;
7283 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7284
7285 return 0;
7286 }
7287
7288 static void fx_init(struct kvm_vcpu *vcpu)
7289 {
7290 fpstate_init(&vcpu->arch.guest_fpu.state);
7291 if (cpu_has_xsaves)
7292 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7293 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7294
7295 /*
7296 * Ensure guest xcr0 is valid for loading
7297 */
7298 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7299
7300 vcpu->arch.cr0 |= X86_CR0_ET;
7301 }
7302
7303 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7304 {
7305 if (vcpu->guest_fpu_loaded)
7306 return;
7307
7308 /*
7309 * Restore all possible states in the guest,
7310 * and assume host would use all available bits.
7311 * Guest xcr0 would be loaded later.
7312 */
7313 kvm_put_guest_xcr0(vcpu);
7314 vcpu->guest_fpu_loaded = 1;
7315 __kernel_fpu_begin();
7316 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7317 trace_kvm_fpu(1);
7318 }
7319
7320 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7321 {
7322 kvm_put_guest_xcr0(vcpu);
7323
7324 if (!vcpu->guest_fpu_loaded) {
7325 vcpu->fpu_counter = 0;
7326 return;
7327 }
7328
7329 vcpu->guest_fpu_loaded = 0;
7330 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7331 __kernel_fpu_end();
7332 ++vcpu->stat.fpu_reload;
7333 /*
7334 * If using eager FPU mode, or if the guest is a frequent user
7335 * of the FPU, just leave the FPU active for next time.
7336 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7337 * the FPU in bursts will revert to loading it on demand.
7338 */
7339 if (!use_eager_fpu()) {
7340 if (++vcpu->fpu_counter < 5)
7341 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7342 }
7343 trace_kvm_fpu(0);
7344 }
7345
7346 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7347 {
7348 kvmclock_reset(vcpu);
7349
7350 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7351 kvm_x86_ops->vcpu_free(vcpu);
7352 }
7353
7354 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7355 unsigned int id)
7356 {
7357 struct kvm_vcpu *vcpu;
7358
7359 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7360 printk_once(KERN_WARNING
7361 "kvm: SMP vm created on host with unstable TSC; "
7362 "guest TSC will not be reliable\n");
7363
7364 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7365
7366 return vcpu;
7367 }
7368
7369 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7370 {
7371 int r;
7372
7373 kvm_vcpu_mtrr_init(vcpu);
7374 r = vcpu_load(vcpu);
7375 if (r)
7376 return r;
7377 kvm_vcpu_reset(vcpu, false);
7378 kvm_mmu_setup(vcpu);
7379 vcpu_put(vcpu);
7380 return r;
7381 }
7382
7383 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7384 {
7385 struct msr_data msr;
7386 struct kvm *kvm = vcpu->kvm;
7387
7388 if (vcpu_load(vcpu))
7389 return;
7390 msr.data = 0x0;
7391 msr.index = MSR_IA32_TSC;
7392 msr.host_initiated = true;
7393 kvm_write_tsc(vcpu, &msr);
7394 vcpu_put(vcpu);
7395
7396 if (!kvmclock_periodic_sync)
7397 return;
7398
7399 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7400 KVMCLOCK_SYNC_PERIOD);
7401 }
7402
7403 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7404 {
7405 int r;
7406 vcpu->arch.apf.msr_val = 0;
7407
7408 r = vcpu_load(vcpu);
7409 BUG_ON(r);
7410 kvm_mmu_unload(vcpu);
7411 vcpu_put(vcpu);
7412
7413 kvm_x86_ops->vcpu_free(vcpu);
7414 }
7415
7416 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7417 {
7418 vcpu->arch.hflags = 0;
7419
7420 atomic_set(&vcpu->arch.nmi_queued, 0);
7421 vcpu->arch.nmi_pending = 0;
7422 vcpu->arch.nmi_injected = false;
7423 kvm_clear_interrupt_queue(vcpu);
7424 kvm_clear_exception_queue(vcpu);
7425
7426 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7427 kvm_update_dr0123(vcpu);
7428 vcpu->arch.dr6 = DR6_INIT;
7429 kvm_update_dr6(vcpu);
7430 vcpu->arch.dr7 = DR7_FIXED_1;
7431 kvm_update_dr7(vcpu);
7432
7433 vcpu->arch.cr2 = 0;
7434
7435 kvm_make_request(KVM_REQ_EVENT, vcpu);
7436 vcpu->arch.apf.msr_val = 0;
7437 vcpu->arch.st.msr_val = 0;
7438
7439 kvmclock_reset(vcpu);
7440
7441 kvm_clear_async_pf_completion_queue(vcpu);
7442 kvm_async_pf_hash_reset(vcpu);
7443 vcpu->arch.apf.halted = false;
7444
7445 if (!init_event) {
7446 kvm_pmu_reset(vcpu);
7447 vcpu->arch.smbase = 0x30000;
7448 }
7449
7450 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7451 vcpu->arch.regs_avail = ~0;
7452 vcpu->arch.regs_dirty = ~0;
7453
7454 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7455 }
7456
7457 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7458 {
7459 struct kvm_segment cs;
7460
7461 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7462 cs.selector = vector << 8;
7463 cs.base = vector << 12;
7464 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7465 kvm_rip_write(vcpu, 0);
7466 }
7467
7468 int kvm_arch_hardware_enable(void)
7469 {
7470 struct kvm *kvm;
7471 struct kvm_vcpu *vcpu;
7472 int i;
7473 int ret;
7474 u64 local_tsc;
7475 u64 max_tsc = 0;
7476 bool stable, backwards_tsc = false;
7477
7478 kvm_shared_msr_cpu_online();
7479 ret = kvm_x86_ops->hardware_enable();
7480 if (ret != 0)
7481 return ret;
7482
7483 local_tsc = rdtsc();
7484 stable = !check_tsc_unstable();
7485 list_for_each_entry(kvm, &vm_list, vm_list) {
7486 kvm_for_each_vcpu(i, vcpu, kvm) {
7487 if (!stable && vcpu->cpu == smp_processor_id())
7488 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7489 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7490 backwards_tsc = true;
7491 if (vcpu->arch.last_host_tsc > max_tsc)
7492 max_tsc = vcpu->arch.last_host_tsc;
7493 }
7494 }
7495 }
7496
7497 /*
7498 * Sometimes, even reliable TSCs go backwards. This happens on
7499 * platforms that reset TSC during suspend or hibernate actions, but
7500 * maintain synchronization. We must compensate. Fortunately, we can
7501 * detect that condition here, which happens early in CPU bringup,
7502 * before any KVM threads can be running. Unfortunately, we can't
7503 * bring the TSCs fully up to date with real time, as we aren't yet far
7504 * enough into CPU bringup that we know how much real time has actually
7505 * elapsed; our helper function, get_kernel_ns() will be using boot
7506 * variables that haven't been updated yet.
7507 *
7508 * So we simply find the maximum observed TSC above, then record the
7509 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7510 * the adjustment will be applied. Note that we accumulate
7511 * adjustments, in case multiple suspend cycles happen before some VCPU
7512 * gets a chance to run again. In the event that no KVM threads get a
7513 * chance to run, we will miss the entire elapsed period, as we'll have
7514 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7515 * loose cycle time. This isn't too big a deal, since the loss will be
7516 * uniform across all VCPUs (not to mention the scenario is extremely
7517 * unlikely). It is possible that a second hibernate recovery happens
7518 * much faster than a first, causing the observed TSC here to be
7519 * smaller; this would require additional padding adjustment, which is
7520 * why we set last_host_tsc to the local tsc observed here.
7521 *
7522 * N.B. - this code below runs only on platforms with reliable TSC,
7523 * as that is the only way backwards_tsc is set above. Also note
7524 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7525 * have the same delta_cyc adjustment applied if backwards_tsc
7526 * is detected. Note further, this adjustment is only done once,
7527 * as we reset last_host_tsc on all VCPUs to stop this from being
7528 * called multiple times (one for each physical CPU bringup).
7529 *
7530 * Platforms with unreliable TSCs don't have to deal with this, they
7531 * will be compensated by the logic in vcpu_load, which sets the TSC to
7532 * catchup mode. This will catchup all VCPUs to real time, but cannot
7533 * guarantee that they stay in perfect synchronization.
7534 */
7535 if (backwards_tsc) {
7536 u64 delta_cyc = max_tsc - local_tsc;
7537 backwards_tsc_observed = true;
7538 list_for_each_entry(kvm, &vm_list, vm_list) {
7539 kvm_for_each_vcpu(i, vcpu, kvm) {
7540 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7541 vcpu->arch.last_host_tsc = local_tsc;
7542 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7543 }
7544
7545 /*
7546 * We have to disable TSC offset matching.. if you were
7547 * booting a VM while issuing an S4 host suspend....
7548 * you may have some problem. Solving this issue is
7549 * left as an exercise to the reader.
7550 */
7551 kvm->arch.last_tsc_nsec = 0;
7552 kvm->arch.last_tsc_write = 0;
7553 }
7554
7555 }
7556 return 0;
7557 }
7558
7559 void kvm_arch_hardware_disable(void)
7560 {
7561 kvm_x86_ops->hardware_disable();
7562 drop_user_return_notifiers();
7563 }
7564
7565 int kvm_arch_hardware_setup(void)
7566 {
7567 int r;
7568
7569 r = kvm_x86_ops->hardware_setup();
7570 if (r != 0)
7571 return r;
7572
7573 if (kvm_has_tsc_control) {
7574 /*
7575 * Make sure the user can only configure tsc_khz values that
7576 * fit into a signed integer.
7577 * A min value is not calculated needed because it will always
7578 * be 1 on all machines.
7579 */
7580 u64 max = min(0x7fffffffULL,
7581 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7582 kvm_max_guest_tsc_khz = max;
7583
7584 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7585 }
7586
7587 kvm_init_msr_list();
7588 return 0;
7589 }
7590
7591 void kvm_arch_hardware_unsetup(void)
7592 {
7593 kvm_x86_ops->hardware_unsetup();
7594 }
7595
7596 void kvm_arch_check_processor_compat(void *rtn)
7597 {
7598 kvm_x86_ops->check_processor_compatibility(rtn);
7599 }
7600
7601 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7602 {
7603 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7604 }
7605 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7606
7607 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7608 {
7609 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7610 }
7611
7612 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7613 {
7614 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7615 }
7616
7617 struct static_key kvm_no_apic_vcpu __read_mostly;
7618 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7619
7620 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7621 {
7622 struct page *page;
7623 struct kvm *kvm;
7624 int r;
7625
7626 BUG_ON(vcpu->kvm == NULL);
7627 kvm = vcpu->kvm;
7628
7629 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7630 vcpu->arch.pv.pv_unhalted = false;
7631 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7632 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7633 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7634 else
7635 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7636
7637 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7638 if (!page) {
7639 r = -ENOMEM;
7640 goto fail;
7641 }
7642 vcpu->arch.pio_data = page_address(page);
7643
7644 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7645
7646 r = kvm_mmu_create(vcpu);
7647 if (r < 0)
7648 goto fail_free_pio_data;
7649
7650 if (irqchip_in_kernel(kvm)) {
7651 r = kvm_create_lapic(vcpu);
7652 if (r < 0)
7653 goto fail_mmu_destroy;
7654 } else
7655 static_key_slow_inc(&kvm_no_apic_vcpu);
7656
7657 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7658 GFP_KERNEL);
7659 if (!vcpu->arch.mce_banks) {
7660 r = -ENOMEM;
7661 goto fail_free_lapic;
7662 }
7663 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7664
7665 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7666 r = -ENOMEM;
7667 goto fail_free_mce_banks;
7668 }
7669
7670 fx_init(vcpu);
7671
7672 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7673 vcpu->arch.pv_time_enabled = false;
7674
7675 vcpu->arch.guest_supported_xcr0 = 0;
7676 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7677
7678 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7679
7680 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7681
7682 kvm_async_pf_hash_reset(vcpu);
7683 kvm_pmu_init(vcpu);
7684
7685 vcpu->arch.pending_external_vector = -1;
7686
7687 kvm_hv_vcpu_init(vcpu);
7688
7689 return 0;
7690
7691 fail_free_mce_banks:
7692 kfree(vcpu->arch.mce_banks);
7693 fail_free_lapic:
7694 kvm_free_lapic(vcpu);
7695 fail_mmu_destroy:
7696 kvm_mmu_destroy(vcpu);
7697 fail_free_pio_data:
7698 free_page((unsigned long)vcpu->arch.pio_data);
7699 fail:
7700 return r;
7701 }
7702
7703 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7704 {
7705 int idx;
7706
7707 kvm_hv_vcpu_uninit(vcpu);
7708 kvm_pmu_destroy(vcpu);
7709 kfree(vcpu->arch.mce_banks);
7710 kvm_free_lapic(vcpu);
7711 idx = srcu_read_lock(&vcpu->kvm->srcu);
7712 kvm_mmu_destroy(vcpu);
7713 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7714 free_page((unsigned long)vcpu->arch.pio_data);
7715 if (!lapic_in_kernel(vcpu))
7716 static_key_slow_dec(&kvm_no_apic_vcpu);
7717 }
7718
7719 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7720 {
7721 kvm_x86_ops->sched_in(vcpu, cpu);
7722 }
7723
7724 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7725 {
7726 if (type)
7727 return -EINVAL;
7728
7729 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7730 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7731 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7732 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7733 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7734
7735 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7736 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7737 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7738 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7739 &kvm->arch.irq_sources_bitmap);
7740
7741 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7742 mutex_init(&kvm->arch.apic_map_lock);
7743 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7744
7745 pvclock_update_vm_gtod_copy(kvm);
7746
7747 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7748 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7749
7750 kvm_page_track_init(kvm);
7751 kvm_mmu_init_vm(kvm);
7752
7753 return 0;
7754 }
7755
7756 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7757 {
7758 int r;
7759 r = vcpu_load(vcpu);
7760 BUG_ON(r);
7761 kvm_mmu_unload(vcpu);
7762 vcpu_put(vcpu);
7763 }
7764
7765 static void kvm_free_vcpus(struct kvm *kvm)
7766 {
7767 unsigned int i;
7768 struct kvm_vcpu *vcpu;
7769
7770 /*
7771 * Unpin any mmu pages first.
7772 */
7773 kvm_for_each_vcpu(i, vcpu, kvm) {
7774 kvm_clear_async_pf_completion_queue(vcpu);
7775 kvm_unload_vcpu_mmu(vcpu);
7776 }
7777 kvm_for_each_vcpu(i, vcpu, kvm)
7778 kvm_arch_vcpu_free(vcpu);
7779
7780 mutex_lock(&kvm->lock);
7781 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7782 kvm->vcpus[i] = NULL;
7783
7784 atomic_set(&kvm->online_vcpus, 0);
7785 mutex_unlock(&kvm->lock);
7786 }
7787
7788 void kvm_arch_sync_events(struct kvm *kvm)
7789 {
7790 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7791 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7792 kvm_free_all_assigned_devices(kvm);
7793 kvm_free_pit(kvm);
7794 }
7795
7796 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7797 {
7798 int i, r;
7799 unsigned long hva;
7800 struct kvm_memslots *slots = kvm_memslots(kvm);
7801 struct kvm_memory_slot *slot, old;
7802
7803 /* Called with kvm->slots_lock held. */
7804 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7805 return -EINVAL;
7806
7807 slot = id_to_memslot(slots, id);
7808 if (size) {
7809 if (WARN_ON(slot->npages))
7810 return -EEXIST;
7811
7812 /*
7813 * MAP_SHARED to prevent internal slot pages from being moved
7814 * by fork()/COW.
7815 */
7816 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7817 MAP_SHARED | MAP_ANONYMOUS, 0);
7818 if (IS_ERR((void *)hva))
7819 return PTR_ERR((void *)hva);
7820 } else {
7821 if (!slot->npages)
7822 return 0;
7823
7824 hva = 0;
7825 }
7826
7827 old = *slot;
7828 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7829 struct kvm_userspace_memory_region m;
7830
7831 m.slot = id | (i << 16);
7832 m.flags = 0;
7833 m.guest_phys_addr = gpa;
7834 m.userspace_addr = hva;
7835 m.memory_size = size;
7836 r = __kvm_set_memory_region(kvm, &m);
7837 if (r < 0)
7838 return r;
7839 }
7840
7841 if (!size) {
7842 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7843 WARN_ON(r < 0);
7844 }
7845
7846 return 0;
7847 }
7848 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7849
7850 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7851 {
7852 int r;
7853
7854 mutex_lock(&kvm->slots_lock);
7855 r = __x86_set_memory_region(kvm, id, gpa, size);
7856 mutex_unlock(&kvm->slots_lock);
7857
7858 return r;
7859 }
7860 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7861
7862 void kvm_arch_destroy_vm(struct kvm *kvm)
7863 {
7864 if (current->mm == kvm->mm) {
7865 /*
7866 * Free memory regions allocated on behalf of userspace,
7867 * unless the the memory map has changed due to process exit
7868 * or fd copying.
7869 */
7870 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7871 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7872 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7873 }
7874 kvm_iommu_unmap_guest(kvm);
7875 kfree(kvm->arch.vpic);
7876 kfree(kvm->arch.vioapic);
7877 kvm_free_vcpus(kvm);
7878 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7879 kvm_mmu_uninit_vm(kvm);
7880 }
7881
7882 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7883 struct kvm_memory_slot *dont)
7884 {
7885 int i;
7886
7887 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7888 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7889 kvfree(free->arch.rmap[i]);
7890 free->arch.rmap[i] = NULL;
7891 }
7892 if (i == 0)
7893 continue;
7894
7895 if (!dont || free->arch.lpage_info[i - 1] !=
7896 dont->arch.lpage_info[i - 1]) {
7897 kvfree(free->arch.lpage_info[i - 1]);
7898 free->arch.lpage_info[i - 1] = NULL;
7899 }
7900 }
7901
7902 kvm_page_track_free_memslot(free, dont);
7903 }
7904
7905 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7906 unsigned long npages)
7907 {
7908 int i;
7909
7910 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7911 struct kvm_lpage_info *linfo;
7912 unsigned long ugfn;
7913 int lpages;
7914 int level = i + 1;
7915
7916 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7917 slot->base_gfn, level) + 1;
7918
7919 slot->arch.rmap[i] =
7920 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7921 if (!slot->arch.rmap[i])
7922 goto out_free;
7923 if (i == 0)
7924 continue;
7925
7926 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7927 if (!linfo)
7928 goto out_free;
7929
7930 slot->arch.lpage_info[i - 1] = linfo;
7931
7932 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7933 linfo[0].disallow_lpage = 1;
7934 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7935 linfo[lpages - 1].disallow_lpage = 1;
7936 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7937 /*
7938 * If the gfn and userspace address are not aligned wrt each
7939 * other, or if explicitly asked to, disable large page
7940 * support for this slot
7941 */
7942 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7943 !kvm_largepages_enabled()) {
7944 unsigned long j;
7945
7946 for (j = 0; j < lpages; ++j)
7947 linfo[j].disallow_lpage = 1;
7948 }
7949 }
7950
7951 if (kvm_page_track_create_memslot(slot, npages))
7952 goto out_free;
7953
7954 return 0;
7955
7956 out_free:
7957 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7958 kvfree(slot->arch.rmap[i]);
7959 slot->arch.rmap[i] = NULL;
7960 if (i == 0)
7961 continue;
7962
7963 kvfree(slot->arch.lpage_info[i - 1]);
7964 slot->arch.lpage_info[i - 1] = NULL;
7965 }
7966 return -ENOMEM;
7967 }
7968
7969 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7970 {
7971 /*
7972 * memslots->generation has been incremented.
7973 * mmio generation may have reached its maximum value.
7974 */
7975 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7976 }
7977
7978 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7979 struct kvm_memory_slot *memslot,
7980 const struct kvm_userspace_memory_region *mem,
7981 enum kvm_mr_change change)
7982 {
7983 return 0;
7984 }
7985
7986 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7987 struct kvm_memory_slot *new)
7988 {
7989 /* Still write protect RO slot */
7990 if (new->flags & KVM_MEM_READONLY) {
7991 kvm_mmu_slot_remove_write_access(kvm, new);
7992 return;
7993 }
7994
7995 /*
7996 * Call kvm_x86_ops dirty logging hooks when they are valid.
7997 *
7998 * kvm_x86_ops->slot_disable_log_dirty is called when:
7999 *
8000 * - KVM_MR_CREATE with dirty logging is disabled
8001 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8002 *
8003 * The reason is, in case of PML, we need to set D-bit for any slots
8004 * with dirty logging disabled in order to eliminate unnecessary GPA
8005 * logging in PML buffer (and potential PML buffer full VMEXT). This
8006 * guarantees leaving PML enabled during guest's lifetime won't have
8007 * any additonal overhead from PML when guest is running with dirty
8008 * logging disabled for memory slots.
8009 *
8010 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8011 * to dirty logging mode.
8012 *
8013 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8014 *
8015 * In case of write protect:
8016 *
8017 * Write protect all pages for dirty logging.
8018 *
8019 * All the sptes including the large sptes which point to this
8020 * slot are set to readonly. We can not create any new large
8021 * spte on this slot until the end of the logging.
8022 *
8023 * See the comments in fast_page_fault().
8024 */
8025 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8026 if (kvm_x86_ops->slot_enable_log_dirty)
8027 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8028 else
8029 kvm_mmu_slot_remove_write_access(kvm, new);
8030 } else {
8031 if (kvm_x86_ops->slot_disable_log_dirty)
8032 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8033 }
8034 }
8035
8036 void kvm_arch_commit_memory_region(struct kvm *kvm,
8037 const struct kvm_userspace_memory_region *mem,
8038 const struct kvm_memory_slot *old,
8039 const struct kvm_memory_slot *new,
8040 enum kvm_mr_change change)
8041 {
8042 int nr_mmu_pages = 0;
8043
8044 if (!kvm->arch.n_requested_mmu_pages)
8045 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8046
8047 if (nr_mmu_pages)
8048 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8049
8050 /*
8051 * Dirty logging tracks sptes in 4k granularity, meaning that large
8052 * sptes have to be split. If live migration is successful, the guest
8053 * in the source machine will be destroyed and large sptes will be
8054 * created in the destination. However, if the guest continues to run
8055 * in the source machine (for example if live migration fails), small
8056 * sptes will remain around and cause bad performance.
8057 *
8058 * Scan sptes if dirty logging has been stopped, dropping those
8059 * which can be collapsed into a single large-page spte. Later
8060 * page faults will create the large-page sptes.
8061 */
8062 if ((change != KVM_MR_DELETE) &&
8063 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8064 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8065 kvm_mmu_zap_collapsible_sptes(kvm, new);
8066
8067 /*
8068 * Set up write protection and/or dirty logging for the new slot.
8069 *
8070 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8071 * been zapped so no dirty logging staff is needed for old slot. For
8072 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8073 * new and it's also covered when dealing with the new slot.
8074 *
8075 * FIXME: const-ify all uses of struct kvm_memory_slot.
8076 */
8077 if (change != KVM_MR_DELETE)
8078 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8079 }
8080
8081 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8082 {
8083 kvm_mmu_invalidate_zap_all_pages(kvm);
8084 }
8085
8086 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8087 struct kvm_memory_slot *slot)
8088 {
8089 kvm_mmu_invalidate_zap_all_pages(kvm);
8090 }
8091
8092 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8093 {
8094 if (!list_empty_careful(&vcpu->async_pf.done))
8095 return true;
8096
8097 if (kvm_apic_has_events(vcpu))
8098 return true;
8099
8100 if (vcpu->arch.pv.pv_unhalted)
8101 return true;
8102
8103 if (atomic_read(&vcpu->arch.nmi_queued))
8104 return true;
8105
8106 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8107 return true;
8108
8109 if (kvm_arch_interrupt_allowed(vcpu) &&
8110 kvm_cpu_has_interrupt(vcpu))
8111 return true;
8112
8113 if (kvm_hv_has_stimer_pending(vcpu))
8114 return true;
8115
8116 return false;
8117 }
8118
8119 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8120 {
8121 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8122 kvm_x86_ops->check_nested_events(vcpu, false);
8123
8124 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8125 }
8126
8127 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8128 {
8129 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8130 }
8131
8132 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8133 {
8134 return kvm_x86_ops->interrupt_allowed(vcpu);
8135 }
8136
8137 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8138 {
8139 if (is_64_bit_mode(vcpu))
8140 return kvm_rip_read(vcpu);
8141 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8142 kvm_rip_read(vcpu));
8143 }
8144 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8145
8146 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8147 {
8148 return kvm_get_linear_rip(vcpu) == linear_rip;
8149 }
8150 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8151
8152 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8153 {
8154 unsigned long rflags;
8155
8156 rflags = kvm_x86_ops->get_rflags(vcpu);
8157 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8158 rflags &= ~X86_EFLAGS_TF;
8159 return rflags;
8160 }
8161 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8162
8163 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8164 {
8165 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8166 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8167 rflags |= X86_EFLAGS_TF;
8168 kvm_x86_ops->set_rflags(vcpu, rflags);
8169 }
8170
8171 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8172 {
8173 __kvm_set_rflags(vcpu, rflags);
8174 kvm_make_request(KVM_REQ_EVENT, vcpu);
8175 }
8176 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8177
8178 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8179 {
8180 int r;
8181
8182 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8183 work->wakeup_all)
8184 return;
8185
8186 r = kvm_mmu_reload(vcpu);
8187 if (unlikely(r))
8188 return;
8189
8190 if (!vcpu->arch.mmu.direct_map &&
8191 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8192 return;
8193
8194 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8195 }
8196
8197 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8198 {
8199 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8200 }
8201
8202 static inline u32 kvm_async_pf_next_probe(u32 key)
8203 {
8204 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8205 }
8206
8207 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8208 {
8209 u32 key = kvm_async_pf_hash_fn(gfn);
8210
8211 while (vcpu->arch.apf.gfns[key] != ~0)
8212 key = kvm_async_pf_next_probe(key);
8213
8214 vcpu->arch.apf.gfns[key] = gfn;
8215 }
8216
8217 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8218 {
8219 int i;
8220 u32 key = kvm_async_pf_hash_fn(gfn);
8221
8222 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8223 (vcpu->arch.apf.gfns[key] != gfn &&
8224 vcpu->arch.apf.gfns[key] != ~0); i++)
8225 key = kvm_async_pf_next_probe(key);
8226
8227 return key;
8228 }
8229
8230 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8231 {
8232 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8233 }
8234
8235 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8236 {
8237 u32 i, j, k;
8238
8239 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8240 while (true) {
8241 vcpu->arch.apf.gfns[i] = ~0;
8242 do {
8243 j = kvm_async_pf_next_probe(j);
8244 if (vcpu->arch.apf.gfns[j] == ~0)
8245 return;
8246 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8247 /*
8248 * k lies cyclically in ]i,j]
8249 * | i.k.j |
8250 * |....j i.k.| or |.k..j i...|
8251 */
8252 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8253 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8254 i = j;
8255 }
8256 }
8257
8258 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8259 {
8260
8261 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8262 sizeof(val));
8263 }
8264
8265 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8266 struct kvm_async_pf *work)
8267 {
8268 struct x86_exception fault;
8269
8270 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8271 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8272
8273 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8274 (vcpu->arch.apf.send_user_only &&
8275 kvm_x86_ops->get_cpl(vcpu) == 0))
8276 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8277 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8278 fault.vector = PF_VECTOR;
8279 fault.error_code_valid = true;
8280 fault.error_code = 0;
8281 fault.nested_page_fault = false;
8282 fault.address = work->arch.token;
8283 kvm_inject_page_fault(vcpu, &fault);
8284 }
8285 }
8286
8287 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8288 struct kvm_async_pf *work)
8289 {
8290 struct x86_exception fault;
8291
8292 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8293 if (work->wakeup_all)
8294 work->arch.token = ~0; /* broadcast wakeup */
8295 else
8296 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8297
8298 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8299 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8300 fault.vector = PF_VECTOR;
8301 fault.error_code_valid = true;
8302 fault.error_code = 0;
8303 fault.nested_page_fault = false;
8304 fault.address = work->arch.token;
8305 kvm_inject_page_fault(vcpu, &fault);
8306 }
8307 vcpu->arch.apf.halted = false;
8308 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8309 }
8310
8311 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8312 {
8313 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8314 return true;
8315 else
8316 return !kvm_event_needs_reinjection(vcpu) &&
8317 kvm_x86_ops->interrupt_allowed(vcpu);
8318 }
8319
8320 void kvm_arch_start_assignment(struct kvm *kvm)
8321 {
8322 atomic_inc(&kvm->arch.assigned_device_count);
8323 }
8324 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8325
8326 void kvm_arch_end_assignment(struct kvm *kvm)
8327 {
8328 atomic_dec(&kvm->arch.assigned_device_count);
8329 }
8330 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8331
8332 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8333 {
8334 return atomic_read(&kvm->arch.assigned_device_count);
8335 }
8336 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8337
8338 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8339 {
8340 atomic_inc(&kvm->arch.noncoherent_dma_count);
8341 }
8342 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8343
8344 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8345 {
8346 atomic_dec(&kvm->arch.noncoherent_dma_count);
8347 }
8348 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8349
8350 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8351 {
8352 return atomic_read(&kvm->arch.noncoherent_dma_count);
8353 }
8354 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8355
8356 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8357 struct irq_bypass_producer *prod)
8358 {
8359 struct kvm_kernel_irqfd *irqfd =
8360 container_of(cons, struct kvm_kernel_irqfd, consumer);
8361
8362 if (kvm_x86_ops->update_pi_irte) {
8363 irqfd->producer = prod;
8364 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8365 prod->irq, irqfd->gsi, 1);
8366 }
8367
8368 return -EINVAL;
8369 }
8370
8371 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8372 struct irq_bypass_producer *prod)
8373 {
8374 int ret;
8375 struct kvm_kernel_irqfd *irqfd =
8376 container_of(cons, struct kvm_kernel_irqfd, consumer);
8377
8378 if (!kvm_x86_ops->update_pi_irte) {
8379 WARN_ON(irqfd->producer != NULL);
8380 return;
8381 }
8382
8383 WARN_ON(irqfd->producer != prod);
8384 irqfd->producer = NULL;
8385
8386 /*
8387 * When producer of consumer is unregistered, we change back to
8388 * remapped mode, so we can re-use the current implementation
8389 * when the irq is masked/disabed or the consumer side (KVM
8390 * int this case doesn't want to receive the interrupts.
8391 */
8392 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8393 if (ret)
8394 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8395 " fails: %d\n", irqfd->consumer.token, ret);
8396 }
8397
8398 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8399 uint32_t guest_irq, bool set)
8400 {
8401 if (!kvm_x86_ops->update_pi_irte)
8402 return -EINVAL;
8403
8404 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8405 }
8406
8407 bool kvm_vector_hashing_enabled(void)
8408 {
8409 return vector_hashing;
8410 }
8411 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8412
8413 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8414 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8415 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8416 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8417 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8418 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8419 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8420 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8421 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8422 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8423 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8424 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8425 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8426 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8427 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8428 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8429 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
ubuntu-bionic-kernel mirror