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KVM: Drop "const" attribute from old memslot in commit_memory_region()
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19 #include <linux/kvm_host.h>
20 #include "irq.h"
21 #include "mmu.h"
22 #include "i8254.h"
23 #include "tss.h"
24 #include "kvm_cache_regs.h"
25 #include "x86.h"
26 #include "cpuid.h"
27 #include "pmu.h"
28 #include "hyperv.h"
29 #include "lapic.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/export.h>
37 #include <linux/moduleparam.h>
38 #include <linux/mman.h>
39 #include <linux/highmem.h>
40 #include <linux/iommu.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/cpufreq.h>
43 #include <linux/user-return-notifier.h>
44 #include <linux/srcu.h>
45 #include <linux/slab.h>
46 #include <linux/perf_event.h>
47 #include <linux/uaccess.h>
48 #include <linux/hash.h>
49 #include <linux/pci.h>
50 #include <linux/timekeeper_internal.h>
51 #include <linux/pvclock_gtod.h>
52 #include <linux/kvm_irqfd.h>
53 #include <linux/irqbypass.h>
54 #include <linux/sched/stat.h>
55 #include <linux/sched/isolation.h>
56 #include <linux/mem_encrypt.h>
57
58 #include <trace/events/kvm.h>
59
60 #include <asm/debugreg.h>
61 #include <asm/msr.h>
62 #include <asm/desc.h>
63 #include <asm/mce.h>
64 #include <linux/kernel_stat.h>
65 #include <asm/fpu/internal.h> /* Ugh! */
66 #include <asm/pvclock.h>
67 #include <asm/div64.h>
68 #include <asm/irq_remapping.h>
69 #include <asm/mshyperv.h>
70 #include <asm/hypervisor.h>
71 #include <asm/intel_pt.h>
72 #include <asm/emulate_prefix.h>
73 #include <clocksource/hyperv_timer.h>
74
75 #define CREATE_TRACE_POINTS
76 #include "trace.h"
77
78 #define MAX_IO_MSRS 256
79 #define KVM_MAX_MCE_BANKS 32
80 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
81 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
82
83 #define emul_to_vcpu(ctxt) \
84 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
85
86 /* EFER defaults:
87 * - enable syscall per default because its emulated by KVM
88 * - enable LME and LMA per default on 64 bit KVM
89 */
90 #ifdef CONFIG_X86_64
91 static
92 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
93 #else
94 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
95 #endif
96
97 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
98
99 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
100 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
101
102 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
103 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
104
105 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
106 static void process_nmi(struct kvm_vcpu *vcpu);
107 static void enter_smm(struct kvm_vcpu *vcpu);
108 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
109 static void store_regs(struct kvm_vcpu *vcpu);
110 static int sync_regs(struct kvm_vcpu *vcpu);
111
112 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
113 EXPORT_SYMBOL_GPL(kvm_x86_ops);
114
115 static bool __read_mostly ignore_msrs = 0;
116 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
117
118 static bool __read_mostly report_ignored_msrs = true;
119 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
120
121 unsigned int min_timer_period_us = 200;
122 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
123
124 static bool __read_mostly kvmclock_periodic_sync = true;
125 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
126
127 bool __read_mostly kvm_has_tsc_control;
128 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
129 u32 __read_mostly kvm_max_guest_tsc_khz;
130 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
131 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
132 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
133 u64 __read_mostly kvm_max_tsc_scaling_ratio;
134 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
135 u64 __read_mostly kvm_default_tsc_scaling_ratio;
136 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
137
138 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
139 static u32 __read_mostly tsc_tolerance_ppm = 250;
140 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
141
142 /*
143 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
144 * adaptive tuning starting from default advancment of 1000ns. '0' disables
145 * advancement entirely. Any other value is used as-is and disables adaptive
146 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
147 */
148 static int __read_mostly lapic_timer_advance_ns = -1;
149 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
150
151 static bool __read_mostly vector_hashing = true;
152 module_param(vector_hashing, bool, S_IRUGO);
153
154 bool __read_mostly enable_vmware_backdoor = false;
155 module_param(enable_vmware_backdoor, bool, S_IRUGO);
156 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
157
158 static bool __read_mostly force_emulation_prefix = false;
159 module_param(force_emulation_prefix, bool, S_IRUGO);
160
161 int __read_mostly pi_inject_timer = -1;
162 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
163
164 #define KVM_NR_SHARED_MSRS 16
165
166 struct kvm_shared_msrs_global {
167 int nr;
168 u32 msrs[KVM_NR_SHARED_MSRS];
169 };
170
171 struct kvm_shared_msrs {
172 struct user_return_notifier urn;
173 bool registered;
174 struct kvm_shared_msr_values {
175 u64 host;
176 u64 curr;
177 } values[KVM_NR_SHARED_MSRS];
178 };
179
180 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
181 static struct kvm_shared_msrs __percpu *shared_msrs;
182
183 static u64 __read_mostly host_xss;
184
185 struct kvm_stats_debugfs_item debugfs_entries[] = {
186 { "pf_fixed", VCPU_STAT(pf_fixed) },
187 { "pf_guest", VCPU_STAT(pf_guest) },
188 { "tlb_flush", VCPU_STAT(tlb_flush) },
189 { "invlpg", VCPU_STAT(invlpg) },
190 { "exits", VCPU_STAT(exits) },
191 { "io_exits", VCPU_STAT(io_exits) },
192 { "mmio_exits", VCPU_STAT(mmio_exits) },
193 { "signal_exits", VCPU_STAT(signal_exits) },
194 { "irq_window", VCPU_STAT(irq_window_exits) },
195 { "nmi_window", VCPU_STAT(nmi_window_exits) },
196 { "halt_exits", VCPU_STAT(halt_exits) },
197 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
198 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
199 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
200 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
201 { "hypercalls", VCPU_STAT(hypercalls) },
202 { "request_irq", VCPU_STAT(request_irq_exits) },
203 { "irq_exits", VCPU_STAT(irq_exits) },
204 { "host_state_reload", VCPU_STAT(host_state_reload) },
205 { "fpu_reload", VCPU_STAT(fpu_reload) },
206 { "insn_emulation", VCPU_STAT(insn_emulation) },
207 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
208 { "irq_injections", VCPU_STAT(irq_injections) },
209 { "nmi_injections", VCPU_STAT(nmi_injections) },
210 { "req_event", VCPU_STAT(req_event) },
211 { "l1d_flush", VCPU_STAT(l1d_flush) },
212 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
213 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
214 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
215 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
216 { "mmu_flooded", VM_STAT(mmu_flooded) },
217 { "mmu_recycled", VM_STAT(mmu_recycled) },
218 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
219 { "mmu_unsync", VM_STAT(mmu_unsync) },
220 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
221 { "largepages", VM_STAT(lpages, .mode = 0444) },
222 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
223 { "max_mmu_page_hash_collisions",
224 VM_STAT(max_mmu_page_hash_collisions) },
225 { NULL }
226 };
227
228 u64 __read_mostly host_xcr0;
229
230 struct kmem_cache *x86_fpu_cache;
231 EXPORT_SYMBOL_GPL(x86_fpu_cache);
232
233 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
234
235 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
236 {
237 int i;
238 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
239 vcpu->arch.apf.gfns[i] = ~0;
240 }
241
242 static void kvm_on_user_return(struct user_return_notifier *urn)
243 {
244 unsigned slot;
245 struct kvm_shared_msrs *locals
246 = container_of(urn, struct kvm_shared_msrs, urn);
247 struct kvm_shared_msr_values *values;
248 unsigned long flags;
249
250 /*
251 * Disabling irqs at this point since the following code could be
252 * interrupted and executed through kvm_arch_hardware_disable()
253 */
254 local_irq_save(flags);
255 if (locals->registered) {
256 locals->registered = false;
257 user_return_notifier_unregister(urn);
258 }
259 local_irq_restore(flags);
260 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
261 values = &locals->values[slot];
262 if (values->host != values->curr) {
263 wrmsrl(shared_msrs_global.msrs[slot], values->host);
264 values->curr = values->host;
265 }
266 }
267 }
268
269 void kvm_define_shared_msr(unsigned slot, u32 msr)
270 {
271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
272 shared_msrs_global.msrs[slot] = msr;
273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
275 }
276 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277
278 static void kvm_shared_msr_cpu_online(void)
279 {
280 unsigned int cpu = smp_processor_id();
281 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
282 u64 value;
283 int i;
284
285 for (i = 0; i < shared_msrs_global.nr; ++i) {
286 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
287 smsr->values[i].host = value;
288 smsr->values[i].curr = value;
289 }
290 }
291
292 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
293 {
294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
296 int err;
297
298 value = (value & mask) | (smsr->values[slot].host & ~mask);
299 if (value == smsr->values[slot].curr)
300 return 0;
301 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
302 if (err)
303 return 1;
304
305 smsr->values[slot].curr = value;
306 if (!smsr->registered) {
307 smsr->urn.on_user_return = kvm_on_user_return;
308 user_return_notifier_register(&smsr->urn);
309 smsr->registered = true;
310 }
311 return 0;
312 }
313 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
314
315 static void drop_user_return_notifiers(void)
316 {
317 unsigned int cpu = smp_processor_id();
318 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
319
320 if (smsr->registered)
321 kvm_on_user_return(&smsr->urn);
322 }
323
324 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
325 {
326 return vcpu->arch.apic_base;
327 }
328 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
329
330 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
331 {
332 return kvm_apic_mode(kvm_get_apic_base(vcpu));
333 }
334 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
335
336 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
337 {
338 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
339 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
340 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
341 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
342
343 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
344 return 1;
345 if (!msr_info->host_initiated) {
346 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
347 return 1;
348 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
349 return 1;
350 }
351
352 kvm_lapic_set_base(vcpu, msr_info->data);
353 return 0;
354 }
355 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
356
357 asmlinkage __visible void kvm_spurious_fault(void)
358 {
359 /* Fault while not rebooting. We want the trace. */
360 BUG_ON(!kvm_rebooting);
361 }
362 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
363
364 #define EXCPT_BENIGN 0
365 #define EXCPT_CONTRIBUTORY 1
366 #define EXCPT_PF 2
367
368 static int exception_class(int vector)
369 {
370 switch (vector) {
371 case PF_VECTOR:
372 return EXCPT_PF;
373 case DE_VECTOR:
374 case TS_VECTOR:
375 case NP_VECTOR:
376 case SS_VECTOR:
377 case GP_VECTOR:
378 return EXCPT_CONTRIBUTORY;
379 default:
380 break;
381 }
382 return EXCPT_BENIGN;
383 }
384
385 #define EXCPT_FAULT 0
386 #define EXCPT_TRAP 1
387 #define EXCPT_ABORT 2
388 #define EXCPT_INTERRUPT 3
389
390 static int exception_type(int vector)
391 {
392 unsigned int mask;
393
394 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
395 return EXCPT_INTERRUPT;
396
397 mask = 1 << vector;
398
399 /* #DB is trap, as instruction watchpoints are handled elsewhere */
400 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
401 return EXCPT_TRAP;
402
403 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
404 return EXCPT_ABORT;
405
406 /* Reserved exceptions will result in fault */
407 return EXCPT_FAULT;
408 }
409
410 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
411 {
412 unsigned nr = vcpu->arch.exception.nr;
413 bool has_payload = vcpu->arch.exception.has_payload;
414 unsigned long payload = vcpu->arch.exception.payload;
415
416 if (!has_payload)
417 return;
418
419 switch (nr) {
420 case DB_VECTOR:
421 /*
422 * "Certain debug exceptions may clear bit 0-3. The
423 * remaining contents of the DR6 register are never
424 * cleared by the processor".
425 */
426 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
427 /*
428 * DR6.RTM is set by all #DB exceptions that don't clear it.
429 */
430 vcpu->arch.dr6 |= DR6_RTM;
431 vcpu->arch.dr6 |= payload;
432 /*
433 * Bit 16 should be set in the payload whenever the #DB
434 * exception should clear DR6.RTM. This makes the payload
435 * compatible with the pending debug exceptions under VMX.
436 * Though not currently documented in the SDM, this also
437 * makes the payload compatible with the exit qualification
438 * for #DB exceptions under VMX.
439 */
440 vcpu->arch.dr6 ^= payload & DR6_RTM;
441
442 /*
443 * The #DB payload is defined as compatible with the 'pending
444 * debug exceptions' field under VMX, not DR6. While bit 12 is
445 * defined in the 'pending debug exceptions' field (enabled
446 * breakpoint), it is reserved and must be zero in DR6.
447 */
448 vcpu->arch.dr6 &= ~BIT(12);
449 break;
450 case PF_VECTOR:
451 vcpu->arch.cr2 = payload;
452 break;
453 }
454
455 vcpu->arch.exception.has_payload = false;
456 vcpu->arch.exception.payload = 0;
457 }
458 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
459
460 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
461 unsigned nr, bool has_error, u32 error_code,
462 bool has_payload, unsigned long payload, bool reinject)
463 {
464 u32 prev_nr;
465 int class1, class2;
466
467 kvm_make_request(KVM_REQ_EVENT, vcpu);
468
469 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
470 queue:
471 if (has_error && !is_protmode(vcpu))
472 has_error = false;
473 if (reinject) {
474 /*
475 * On vmentry, vcpu->arch.exception.pending is only
476 * true if an event injection was blocked by
477 * nested_run_pending. In that case, however,
478 * vcpu_enter_guest requests an immediate exit,
479 * and the guest shouldn't proceed far enough to
480 * need reinjection.
481 */
482 WARN_ON_ONCE(vcpu->arch.exception.pending);
483 vcpu->arch.exception.injected = true;
484 if (WARN_ON_ONCE(has_payload)) {
485 /*
486 * A reinjected event has already
487 * delivered its payload.
488 */
489 has_payload = false;
490 payload = 0;
491 }
492 } else {
493 vcpu->arch.exception.pending = true;
494 vcpu->arch.exception.injected = false;
495 }
496 vcpu->arch.exception.has_error_code = has_error;
497 vcpu->arch.exception.nr = nr;
498 vcpu->arch.exception.error_code = error_code;
499 vcpu->arch.exception.has_payload = has_payload;
500 vcpu->arch.exception.payload = payload;
501 if (!is_guest_mode(vcpu))
502 kvm_deliver_exception_payload(vcpu);
503 return;
504 }
505
506 /* to check exception */
507 prev_nr = vcpu->arch.exception.nr;
508 if (prev_nr == DF_VECTOR) {
509 /* triple fault -> shutdown */
510 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
511 return;
512 }
513 class1 = exception_class(prev_nr);
514 class2 = exception_class(nr);
515 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
516 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
517 /*
518 * Generate double fault per SDM Table 5-5. Set
519 * exception.pending = true so that the double fault
520 * can trigger a nested vmexit.
521 */
522 vcpu->arch.exception.pending = true;
523 vcpu->arch.exception.injected = false;
524 vcpu->arch.exception.has_error_code = true;
525 vcpu->arch.exception.nr = DF_VECTOR;
526 vcpu->arch.exception.error_code = 0;
527 vcpu->arch.exception.has_payload = false;
528 vcpu->arch.exception.payload = 0;
529 } else
530 /* replace previous exception with a new one in a hope
531 that instruction re-execution will regenerate lost
532 exception */
533 goto queue;
534 }
535
536 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
537 {
538 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
539 }
540 EXPORT_SYMBOL_GPL(kvm_queue_exception);
541
542 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
543 {
544 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
545 }
546 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
547
548 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
549 unsigned long payload)
550 {
551 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
552 }
553
554 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
555 u32 error_code, unsigned long payload)
556 {
557 kvm_multiple_exception(vcpu, nr, true, error_code,
558 true, payload, false);
559 }
560
561 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
562 {
563 if (err)
564 kvm_inject_gp(vcpu, 0);
565 else
566 return kvm_skip_emulated_instruction(vcpu);
567
568 return 1;
569 }
570 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
571
572 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
573 {
574 ++vcpu->stat.pf_guest;
575 vcpu->arch.exception.nested_apf =
576 is_guest_mode(vcpu) && fault->async_page_fault;
577 if (vcpu->arch.exception.nested_apf) {
578 vcpu->arch.apf.nested_apf_token = fault->address;
579 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
580 } else {
581 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
582 fault->address);
583 }
584 }
585 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
586
587 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
588 {
589 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
590 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
591 else
592 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
593
594 return fault->nested_page_fault;
595 }
596
597 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
598 {
599 atomic_inc(&vcpu->arch.nmi_queued);
600 kvm_make_request(KVM_REQ_NMI, vcpu);
601 }
602 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
603
604 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
605 {
606 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
607 }
608 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
609
610 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
611 {
612 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
613 }
614 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
615
616 /*
617 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
618 * a #GP and return false.
619 */
620 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
621 {
622 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
623 return true;
624 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
625 return false;
626 }
627 EXPORT_SYMBOL_GPL(kvm_require_cpl);
628
629 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
630 {
631 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
632 return true;
633
634 kvm_queue_exception(vcpu, UD_VECTOR);
635 return false;
636 }
637 EXPORT_SYMBOL_GPL(kvm_require_dr);
638
639 /*
640 * This function will be used to read from the physical memory of the currently
641 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
642 * can read from guest physical or from the guest's guest physical memory.
643 */
644 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
645 gfn_t ngfn, void *data, int offset, int len,
646 u32 access)
647 {
648 struct x86_exception exception;
649 gfn_t real_gfn;
650 gpa_t ngpa;
651
652 ngpa = gfn_to_gpa(ngfn);
653 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
654 if (real_gfn == UNMAPPED_GVA)
655 return -EFAULT;
656
657 real_gfn = gpa_to_gfn(real_gfn);
658
659 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
660 }
661 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
662
663 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
664 void *data, int offset, int len, u32 access)
665 {
666 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
667 data, offset, len, access);
668 }
669
670 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
671 {
672 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
673 rsvd_bits(1, 2);
674 }
675
676 /*
677 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
678 */
679 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
680 {
681 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
682 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
683 int i;
684 int ret;
685 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
686
687 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
688 offset * sizeof(u64), sizeof(pdpte),
689 PFERR_USER_MASK|PFERR_WRITE_MASK);
690 if (ret < 0) {
691 ret = 0;
692 goto out;
693 }
694 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
695 if ((pdpte[i] & PT_PRESENT_MASK) &&
696 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
697 ret = 0;
698 goto out;
699 }
700 }
701 ret = 1;
702
703 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
704 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
705
706 out:
707
708 return ret;
709 }
710 EXPORT_SYMBOL_GPL(load_pdptrs);
711
712 bool pdptrs_changed(struct kvm_vcpu *vcpu)
713 {
714 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
715 int offset;
716 gfn_t gfn;
717 int r;
718
719 if (!is_pae_paging(vcpu))
720 return false;
721
722 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
723 return true;
724
725 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
726 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
727 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
728 PFERR_USER_MASK | PFERR_WRITE_MASK);
729 if (r < 0)
730 return true;
731
732 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
733 }
734 EXPORT_SYMBOL_GPL(pdptrs_changed);
735
736 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
737 {
738 unsigned long old_cr0 = kvm_read_cr0(vcpu);
739 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
740
741 cr0 |= X86_CR0_ET;
742
743 #ifdef CONFIG_X86_64
744 if (cr0 & 0xffffffff00000000UL)
745 return 1;
746 #endif
747
748 cr0 &= ~CR0_RESERVED_BITS;
749
750 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
751 return 1;
752
753 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
754 return 1;
755
756 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
757 #ifdef CONFIG_X86_64
758 if ((vcpu->arch.efer & EFER_LME)) {
759 int cs_db, cs_l;
760
761 if (!is_pae(vcpu))
762 return 1;
763 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
764 if (cs_l)
765 return 1;
766 } else
767 #endif
768 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
769 kvm_read_cr3(vcpu)))
770 return 1;
771 }
772
773 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
774 return 1;
775
776 kvm_x86_ops->set_cr0(vcpu, cr0);
777
778 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
779 kvm_clear_async_pf_completion_queue(vcpu);
780 kvm_async_pf_hash_reset(vcpu);
781 }
782
783 if ((cr0 ^ old_cr0) & update_bits)
784 kvm_mmu_reset_context(vcpu);
785
786 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
787 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
788 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
789 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
790
791 return 0;
792 }
793 EXPORT_SYMBOL_GPL(kvm_set_cr0);
794
795 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
796 {
797 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
798 }
799 EXPORT_SYMBOL_GPL(kvm_lmsw);
800
801 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
802 {
803 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
804
805 if (vcpu->arch.xcr0 != host_xcr0)
806 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
807
808 if (vcpu->arch.xsaves_enabled &&
809 vcpu->arch.ia32_xss != host_xss)
810 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
811 }
812 }
813 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
814
815 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
816 {
817 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
818
819 if (vcpu->arch.xcr0 != host_xcr0)
820 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
821
822 if (vcpu->arch.xsaves_enabled &&
823 vcpu->arch.ia32_xss != host_xss)
824 wrmsrl(MSR_IA32_XSS, host_xss);
825 }
826
827 }
828 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
829
830 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
831 {
832 u64 xcr0 = xcr;
833 u64 old_xcr0 = vcpu->arch.xcr0;
834 u64 valid_bits;
835
836 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
837 if (index != XCR_XFEATURE_ENABLED_MASK)
838 return 1;
839 if (!(xcr0 & XFEATURE_MASK_FP))
840 return 1;
841 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
842 return 1;
843
844 /*
845 * Do not allow the guest to set bits that we do not support
846 * saving. However, xcr0 bit 0 is always set, even if the
847 * emulated CPU does not support XSAVE (see fx_init).
848 */
849 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
850 if (xcr0 & ~valid_bits)
851 return 1;
852
853 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
854 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
855 return 1;
856
857 if (xcr0 & XFEATURE_MASK_AVX512) {
858 if (!(xcr0 & XFEATURE_MASK_YMM))
859 return 1;
860 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
861 return 1;
862 }
863 vcpu->arch.xcr0 = xcr0;
864
865 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
866 kvm_update_cpuid(vcpu);
867 return 0;
868 }
869
870 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
871 {
872 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
873 __kvm_set_xcr(vcpu, index, xcr)) {
874 kvm_inject_gp(vcpu, 0);
875 return 1;
876 }
877 return 0;
878 }
879 EXPORT_SYMBOL_GPL(kvm_set_xcr);
880
881 #define __cr4_reserved_bits(__cpu_has, __c) \
882 ({ \
883 u64 __reserved_bits = CR4_RESERVED_BITS; \
884 \
885 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
886 __reserved_bits |= X86_CR4_OSXSAVE; \
887 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
888 __reserved_bits |= X86_CR4_SMEP; \
889 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
890 __reserved_bits |= X86_CR4_SMAP; \
891 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
892 __reserved_bits |= X86_CR4_FSGSBASE; \
893 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
894 __reserved_bits |= X86_CR4_PKE; \
895 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
896 __reserved_bits |= X86_CR4_LA57; \
897 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
898 __reserved_bits |= X86_CR4_UMIP; \
899 __reserved_bits; \
900 })
901
902 static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
903 {
904 u64 reserved_bits = __cr4_reserved_bits(cpu_has, c);
905
906 if (cpuid_ecx(0x7) & feature_bit(LA57))
907 reserved_bits &= ~X86_CR4_LA57;
908
909 if (kvm_x86_ops->umip_emulated())
910 reserved_bits &= ~X86_CR4_UMIP;
911
912 return reserved_bits;
913 }
914
915 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
916 {
917 if (cr4 & cr4_reserved_bits)
918 return -EINVAL;
919
920 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
921 return -EINVAL;
922
923 return 0;
924 }
925
926 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
927 {
928 unsigned long old_cr4 = kvm_read_cr4(vcpu);
929 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
930 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
931
932 if (kvm_valid_cr4(vcpu, cr4))
933 return 1;
934
935 if (is_long_mode(vcpu)) {
936 if (!(cr4 & X86_CR4_PAE))
937 return 1;
938 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
939 && ((cr4 ^ old_cr4) & pdptr_bits)
940 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
941 kvm_read_cr3(vcpu)))
942 return 1;
943
944 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
945 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
946 return 1;
947
948 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
949 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
950 return 1;
951 }
952
953 if (kvm_x86_ops->set_cr4(vcpu, cr4))
954 return 1;
955
956 if (((cr4 ^ old_cr4) & pdptr_bits) ||
957 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
958 kvm_mmu_reset_context(vcpu);
959
960 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
961 kvm_update_cpuid(vcpu);
962
963 return 0;
964 }
965 EXPORT_SYMBOL_GPL(kvm_set_cr4);
966
967 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
968 {
969 bool skip_tlb_flush = false;
970 #ifdef CONFIG_X86_64
971 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
972
973 if (pcid_enabled) {
974 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
975 cr3 &= ~X86_CR3_PCID_NOFLUSH;
976 }
977 #endif
978
979 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
980 if (!skip_tlb_flush) {
981 kvm_mmu_sync_roots(vcpu);
982 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
983 }
984 return 0;
985 }
986
987 if (is_long_mode(vcpu) &&
988 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
989 return 1;
990 else if (is_pae_paging(vcpu) &&
991 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
992 return 1;
993
994 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
995 vcpu->arch.cr3 = cr3;
996 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
997
998 return 0;
999 }
1000 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1001
1002 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1003 {
1004 if (cr8 & CR8_RESERVED_BITS)
1005 return 1;
1006 if (lapic_in_kernel(vcpu))
1007 kvm_lapic_set_tpr(vcpu, cr8);
1008 else
1009 vcpu->arch.cr8 = cr8;
1010 return 0;
1011 }
1012 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1013
1014 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1015 {
1016 if (lapic_in_kernel(vcpu))
1017 return kvm_lapic_get_cr8(vcpu);
1018 else
1019 return vcpu->arch.cr8;
1020 }
1021 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1022
1023 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1024 {
1025 int i;
1026
1027 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1028 for (i = 0; i < KVM_NR_DB_REGS; i++)
1029 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1030 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1031 }
1032 }
1033
1034 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1035 {
1036 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1037 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1038 }
1039
1040 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1041 {
1042 unsigned long dr7;
1043
1044 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1045 dr7 = vcpu->arch.guest_debug_dr7;
1046 else
1047 dr7 = vcpu->arch.dr7;
1048 kvm_x86_ops->set_dr7(vcpu, dr7);
1049 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1050 if (dr7 & DR7_BP_EN_MASK)
1051 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1052 }
1053
1054 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1055 {
1056 u64 fixed = DR6_FIXED_1;
1057
1058 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1059 fixed |= DR6_RTM;
1060 return fixed;
1061 }
1062
1063 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1064 {
1065 size_t size = ARRAY_SIZE(vcpu->arch.db);
1066
1067 switch (dr) {
1068 case 0 ... 3:
1069 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1070 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1071 vcpu->arch.eff_db[dr] = val;
1072 break;
1073 case 4:
1074 /* fall through */
1075 case 6:
1076 if (val & 0xffffffff00000000ULL)
1077 return -1; /* #GP */
1078 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1079 kvm_update_dr6(vcpu);
1080 break;
1081 case 5:
1082 /* fall through */
1083 default: /* 7 */
1084 if (!kvm_dr7_valid(val))
1085 return -1; /* #GP */
1086 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1087 kvm_update_dr7(vcpu);
1088 break;
1089 }
1090
1091 return 0;
1092 }
1093
1094 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1095 {
1096 if (__kvm_set_dr(vcpu, dr, val)) {
1097 kvm_inject_gp(vcpu, 0);
1098 return 1;
1099 }
1100 return 0;
1101 }
1102 EXPORT_SYMBOL_GPL(kvm_set_dr);
1103
1104 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1105 {
1106 size_t size = ARRAY_SIZE(vcpu->arch.db);
1107
1108 switch (dr) {
1109 case 0 ... 3:
1110 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1111 break;
1112 case 4:
1113 /* fall through */
1114 case 6:
1115 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1116 *val = vcpu->arch.dr6;
1117 else
1118 *val = kvm_x86_ops->get_dr6(vcpu);
1119 break;
1120 case 5:
1121 /* fall through */
1122 default: /* 7 */
1123 *val = vcpu->arch.dr7;
1124 break;
1125 }
1126 return 0;
1127 }
1128 EXPORT_SYMBOL_GPL(kvm_get_dr);
1129
1130 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1131 {
1132 u32 ecx = kvm_rcx_read(vcpu);
1133 u64 data;
1134 int err;
1135
1136 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1137 if (err)
1138 return err;
1139 kvm_rax_write(vcpu, (u32)data);
1140 kvm_rdx_write(vcpu, data >> 32);
1141 return err;
1142 }
1143 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1144
1145 /*
1146 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1147 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1148 *
1149 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1150 * extract the supported MSRs from the related const lists.
1151 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1152 * capabilities of the host cpu. This capabilities test skips MSRs that are
1153 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1154 * may depend on host virtualization features rather than host cpu features.
1155 */
1156
1157 static const u32 msrs_to_save_all[] = {
1158 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1159 MSR_STAR,
1160 #ifdef CONFIG_X86_64
1161 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1162 #endif
1163 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1164 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1165 MSR_IA32_SPEC_CTRL,
1166 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1167 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1168 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1169 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1170 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1171 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1172 MSR_IA32_UMWAIT_CONTROL,
1173
1174 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1175 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1176 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1177 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1178 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1179 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1180 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1181 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1182 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1183 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1184 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1185 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1186 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1187 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1188 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1189 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1190 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1191 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1192 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1193 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1194 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1195 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1196 };
1197
1198 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1199 static unsigned num_msrs_to_save;
1200
1201 static const u32 emulated_msrs_all[] = {
1202 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1203 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1204 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1205 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1206 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1207 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1208 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1209 HV_X64_MSR_RESET,
1210 HV_X64_MSR_VP_INDEX,
1211 HV_X64_MSR_VP_RUNTIME,
1212 HV_X64_MSR_SCONTROL,
1213 HV_X64_MSR_STIMER0_CONFIG,
1214 HV_X64_MSR_VP_ASSIST_PAGE,
1215 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1216 HV_X64_MSR_TSC_EMULATION_STATUS,
1217
1218 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1219 MSR_KVM_PV_EOI_EN,
1220
1221 MSR_IA32_TSC_ADJUST,
1222 MSR_IA32_TSCDEADLINE,
1223 MSR_IA32_ARCH_CAPABILITIES,
1224 MSR_IA32_MISC_ENABLE,
1225 MSR_IA32_MCG_STATUS,
1226 MSR_IA32_MCG_CTL,
1227 MSR_IA32_MCG_EXT_CTL,
1228 MSR_IA32_SMBASE,
1229 MSR_SMI_COUNT,
1230 MSR_PLATFORM_INFO,
1231 MSR_MISC_FEATURES_ENABLES,
1232 MSR_AMD64_VIRT_SPEC_CTRL,
1233 MSR_IA32_POWER_CTL,
1234 MSR_IA32_UCODE_REV,
1235
1236 /*
1237 * The following list leaves out MSRs whose values are determined
1238 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1239 * We always support the "true" VMX control MSRs, even if the host
1240 * processor does not, so I am putting these registers here rather
1241 * than in msrs_to_save_all.
1242 */
1243 MSR_IA32_VMX_BASIC,
1244 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1245 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1246 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1247 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1248 MSR_IA32_VMX_MISC,
1249 MSR_IA32_VMX_CR0_FIXED0,
1250 MSR_IA32_VMX_CR4_FIXED0,
1251 MSR_IA32_VMX_VMCS_ENUM,
1252 MSR_IA32_VMX_PROCBASED_CTLS2,
1253 MSR_IA32_VMX_EPT_VPID_CAP,
1254 MSR_IA32_VMX_VMFUNC,
1255
1256 MSR_K7_HWCR,
1257 MSR_KVM_POLL_CONTROL,
1258 };
1259
1260 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1261 static unsigned num_emulated_msrs;
1262
1263 /*
1264 * List of msr numbers which are used to expose MSR-based features that
1265 * can be used by a hypervisor to validate requested CPU features.
1266 */
1267 static const u32 msr_based_features_all[] = {
1268 MSR_IA32_VMX_BASIC,
1269 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1270 MSR_IA32_VMX_PINBASED_CTLS,
1271 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1272 MSR_IA32_VMX_PROCBASED_CTLS,
1273 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1274 MSR_IA32_VMX_EXIT_CTLS,
1275 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1276 MSR_IA32_VMX_ENTRY_CTLS,
1277 MSR_IA32_VMX_MISC,
1278 MSR_IA32_VMX_CR0_FIXED0,
1279 MSR_IA32_VMX_CR0_FIXED1,
1280 MSR_IA32_VMX_CR4_FIXED0,
1281 MSR_IA32_VMX_CR4_FIXED1,
1282 MSR_IA32_VMX_VMCS_ENUM,
1283 MSR_IA32_VMX_PROCBASED_CTLS2,
1284 MSR_IA32_VMX_EPT_VPID_CAP,
1285 MSR_IA32_VMX_VMFUNC,
1286
1287 MSR_F10H_DECFG,
1288 MSR_IA32_UCODE_REV,
1289 MSR_IA32_ARCH_CAPABILITIES,
1290 };
1291
1292 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1293 static unsigned int num_msr_based_features;
1294
1295 static u64 kvm_get_arch_capabilities(void)
1296 {
1297 u64 data = 0;
1298
1299 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1300 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1301
1302 /*
1303 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1304 * the nested hypervisor runs with NX huge pages. If it is not,
1305 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1306 * L1 guests, so it need not worry about its own (L2) guests.
1307 */
1308 data |= ARCH_CAP_PSCHANGE_MC_NO;
1309
1310 /*
1311 * If we're doing cache flushes (either "always" or "cond")
1312 * we will do one whenever the guest does a vmlaunch/vmresume.
1313 * If an outer hypervisor is doing the cache flush for us
1314 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1315 * capability to the guest too, and if EPT is disabled we're not
1316 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1317 * require a nested hypervisor to do a flush of its own.
1318 */
1319 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1320 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1321
1322 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1323 data |= ARCH_CAP_RDCL_NO;
1324 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1325 data |= ARCH_CAP_SSB_NO;
1326 if (!boot_cpu_has_bug(X86_BUG_MDS))
1327 data |= ARCH_CAP_MDS_NO;
1328
1329 /*
1330 * On TAA affected systems:
1331 * - nothing to do if TSX is disabled on the host.
1332 * - we emulate TSX_CTRL if present on the host.
1333 * This lets the guest use VERW to clear CPU buffers.
1334 */
1335 if (!boot_cpu_has(X86_FEATURE_RTM))
1336 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1337 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1338 data |= ARCH_CAP_TAA_NO;
1339
1340 return data;
1341 }
1342
1343 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1344 {
1345 switch (msr->index) {
1346 case MSR_IA32_ARCH_CAPABILITIES:
1347 msr->data = kvm_get_arch_capabilities();
1348 break;
1349 case MSR_IA32_UCODE_REV:
1350 rdmsrl_safe(msr->index, &msr->data);
1351 break;
1352 default:
1353 if (kvm_x86_ops->get_msr_feature(msr))
1354 return 1;
1355 }
1356 return 0;
1357 }
1358
1359 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1360 {
1361 struct kvm_msr_entry msr;
1362 int r;
1363
1364 msr.index = index;
1365 r = kvm_get_msr_feature(&msr);
1366 if (r)
1367 return r;
1368
1369 *data = msr.data;
1370
1371 return 0;
1372 }
1373
1374 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1375 {
1376 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1377 return false;
1378
1379 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1380 return false;
1381
1382 if (efer & (EFER_LME | EFER_LMA) &&
1383 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1384 return false;
1385
1386 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1387 return false;
1388
1389 return true;
1390
1391 }
1392 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1393 {
1394 if (efer & efer_reserved_bits)
1395 return false;
1396
1397 return __kvm_valid_efer(vcpu, efer);
1398 }
1399 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1400
1401 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1402 {
1403 u64 old_efer = vcpu->arch.efer;
1404 u64 efer = msr_info->data;
1405
1406 if (efer & efer_reserved_bits)
1407 return 1;
1408
1409 if (!msr_info->host_initiated) {
1410 if (!__kvm_valid_efer(vcpu, efer))
1411 return 1;
1412
1413 if (is_paging(vcpu) &&
1414 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1415 return 1;
1416 }
1417
1418 efer &= ~EFER_LMA;
1419 efer |= vcpu->arch.efer & EFER_LMA;
1420
1421 kvm_x86_ops->set_efer(vcpu, efer);
1422
1423 /* Update reserved bits */
1424 if ((efer ^ old_efer) & EFER_NX)
1425 kvm_mmu_reset_context(vcpu);
1426
1427 return 0;
1428 }
1429
1430 void kvm_enable_efer_bits(u64 mask)
1431 {
1432 efer_reserved_bits &= ~mask;
1433 }
1434 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1435
1436 /*
1437 * Write @data into the MSR specified by @index. Select MSR specific fault
1438 * checks are bypassed if @host_initiated is %true.
1439 * Returns 0 on success, non-0 otherwise.
1440 * Assumes vcpu_load() was already called.
1441 */
1442 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1443 bool host_initiated)
1444 {
1445 struct msr_data msr;
1446
1447 switch (index) {
1448 case MSR_FS_BASE:
1449 case MSR_GS_BASE:
1450 case MSR_KERNEL_GS_BASE:
1451 case MSR_CSTAR:
1452 case MSR_LSTAR:
1453 if (is_noncanonical_address(data, vcpu))
1454 return 1;
1455 break;
1456 case MSR_IA32_SYSENTER_EIP:
1457 case MSR_IA32_SYSENTER_ESP:
1458 /*
1459 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1460 * non-canonical address is written on Intel but not on
1461 * AMD (which ignores the top 32-bits, because it does
1462 * not implement 64-bit SYSENTER).
1463 *
1464 * 64-bit code should hence be able to write a non-canonical
1465 * value on AMD. Making the address canonical ensures that
1466 * vmentry does not fail on Intel after writing a non-canonical
1467 * value, and that something deterministic happens if the guest
1468 * invokes 64-bit SYSENTER.
1469 */
1470 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1471 }
1472
1473 msr.data = data;
1474 msr.index = index;
1475 msr.host_initiated = host_initiated;
1476
1477 return kvm_x86_ops->set_msr(vcpu, &msr);
1478 }
1479
1480 /*
1481 * Read the MSR specified by @index into @data. Select MSR specific fault
1482 * checks are bypassed if @host_initiated is %true.
1483 * Returns 0 on success, non-0 otherwise.
1484 * Assumes vcpu_load() was already called.
1485 */
1486 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1487 bool host_initiated)
1488 {
1489 struct msr_data msr;
1490 int ret;
1491
1492 msr.index = index;
1493 msr.host_initiated = host_initiated;
1494
1495 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1496 if (!ret)
1497 *data = msr.data;
1498 return ret;
1499 }
1500
1501 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1502 {
1503 return __kvm_get_msr(vcpu, index, data, false);
1504 }
1505 EXPORT_SYMBOL_GPL(kvm_get_msr);
1506
1507 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1508 {
1509 return __kvm_set_msr(vcpu, index, data, false);
1510 }
1511 EXPORT_SYMBOL_GPL(kvm_set_msr);
1512
1513 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1514 {
1515 u32 ecx = kvm_rcx_read(vcpu);
1516 u64 data;
1517
1518 if (kvm_get_msr(vcpu, ecx, &data)) {
1519 trace_kvm_msr_read_ex(ecx);
1520 kvm_inject_gp(vcpu, 0);
1521 return 1;
1522 }
1523
1524 trace_kvm_msr_read(ecx, data);
1525
1526 kvm_rax_write(vcpu, data & -1u);
1527 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1528 return kvm_skip_emulated_instruction(vcpu);
1529 }
1530 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1531
1532 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1533 {
1534 u32 ecx = kvm_rcx_read(vcpu);
1535 u64 data = kvm_read_edx_eax(vcpu);
1536
1537 if (kvm_set_msr(vcpu, ecx, data)) {
1538 trace_kvm_msr_write_ex(ecx, data);
1539 kvm_inject_gp(vcpu, 0);
1540 return 1;
1541 }
1542
1543 trace_kvm_msr_write(ecx, data);
1544 return kvm_skip_emulated_instruction(vcpu);
1545 }
1546 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1547
1548 /*
1549 * The fast path for frequent and performance sensitive wrmsr emulation,
1550 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1551 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1552 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1553 * other cases which must be called after interrupts are enabled on the host.
1554 */
1555 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1556 {
1557 if (lapic_in_kernel(vcpu) && apic_x2apic_mode(vcpu->arch.apic) &&
1558 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1559 ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) {
1560
1561 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1562 return kvm_lapic_reg_write(vcpu->arch.apic, APIC_ICR, (u32)data);
1563 }
1564
1565 return 1;
1566 }
1567
1568 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1569 {
1570 u32 msr = kvm_rcx_read(vcpu);
1571 u64 data = kvm_read_edx_eax(vcpu);
1572 int ret = 0;
1573
1574 switch (msr) {
1575 case APIC_BASE_MSR + (APIC_ICR >> 4):
1576 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1577 break;
1578 default:
1579 return EXIT_FASTPATH_NONE;
1580 }
1581
1582 if (!ret) {
1583 trace_kvm_msr_write(msr, data);
1584 return EXIT_FASTPATH_SKIP_EMUL_INS;
1585 }
1586
1587 return EXIT_FASTPATH_NONE;
1588 }
1589 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1590
1591 /*
1592 * Adapt set_msr() to msr_io()'s calling convention
1593 */
1594 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1595 {
1596 return __kvm_get_msr(vcpu, index, data, true);
1597 }
1598
1599 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1600 {
1601 return __kvm_set_msr(vcpu, index, *data, true);
1602 }
1603
1604 #ifdef CONFIG_X86_64
1605 struct pvclock_clock {
1606 int vclock_mode;
1607 u64 cycle_last;
1608 u64 mask;
1609 u32 mult;
1610 u32 shift;
1611 u64 base_cycles;
1612 u64 offset;
1613 };
1614
1615 struct pvclock_gtod_data {
1616 seqcount_t seq;
1617
1618 struct pvclock_clock clock; /* extract of a clocksource struct */
1619 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1620
1621 ktime_t offs_boot;
1622 u64 wall_time_sec;
1623 };
1624
1625 static struct pvclock_gtod_data pvclock_gtod_data;
1626
1627 static void update_pvclock_gtod(struct timekeeper *tk)
1628 {
1629 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1630
1631 write_seqcount_begin(&vdata->seq);
1632
1633 /* copy pvclock gtod data */
1634 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1635 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1636 vdata->clock.mask = tk->tkr_mono.mask;
1637 vdata->clock.mult = tk->tkr_mono.mult;
1638 vdata->clock.shift = tk->tkr_mono.shift;
1639 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1640 vdata->clock.offset = tk->tkr_mono.base;
1641
1642 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->archdata.vclock_mode;
1643 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1644 vdata->raw_clock.mask = tk->tkr_raw.mask;
1645 vdata->raw_clock.mult = tk->tkr_raw.mult;
1646 vdata->raw_clock.shift = tk->tkr_raw.shift;
1647 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1648 vdata->raw_clock.offset = tk->tkr_raw.base;
1649
1650 vdata->wall_time_sec = tk->xtime_sec;
1651
1652 vdata->offs_boot = tk->offs_boot;
1653
1654 write_seqcount_end(&vdata->seq);
1655 }
1656
1657 static s64 get_kvmclock_base_ns(void)
1658 {
1659 /* Count up from boot time, but with the frequency of the raw clock. */
1660 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1661 }
1662 #else
1663 static s64 get_kvmclock_base_ns(void)
1664 {
1665 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1666 return ktime_get_boottime_ns();
1667 }
1668 #endif
1669
1670 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1671 {
1672 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1673 kvm_vcpu_kick(vcpu);
1674 }
1675
1676 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1677 {
1678 int version;
1679 int r;
1680 struct pvclock_wall_clock wc;
1681 u64 wall_nsec;
1682
1683 if (!wall_clock)
1684 return;
1685
1686 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1687 if (r)
1688 return;
1689
1690 if (version & 1)
1691 ++version; /* first time write, random junk */
1692
1693 ++version;
1694
1695 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1696 return;
1697
1698 /*
1699 * The guest calculates current wall clock time by adding
1700 * system time (updated by kvm_guest_time_update below) to the
1701 * wall clock specified here. We do the reverse here.
1702 */
1703 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1704
1705 wc.nsec = do_div(wall_nsec, 1000000000);
1706 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1707 wc.version = version;
1708
1709 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1710
1711 version++;
1712 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1713 }
1714
1715 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1716 {
1717 do_shl32_div32(dividend, divisor);
1718 return dividend;
1719 }
1720
1721 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1722 s8 *pshift, u32 *pmultiplier)
1723 {
1724 uint64_t scaled64;
1725 int32_t shift = 0;
1726 uint64_t tps64;
1727 uint32_t tps32;
1728
1729 tps64 = base_hz;
1730 scaled64 = scaled_hz;
1731 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1732 tps64 >>= 1;
1733 shift--;
1734 }
1735
1736 tps32 = (uint32_t)tps64;
1737 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1738 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1739 scaled64 >>= 1;
1740 else
1741 tps32 <<= 1;
1742 shift++;
1743 }
1744
1745 *pshift = shift;
1746 *pmultiplier = div_frac(scaled64, tps32);
1747 }
1748
1749 #ifdef CONFIG_X86_64
1750 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1751 #endif
1752
1753 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1754 static unsigned long max_tsc_khz;
1755
1756 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1757 {
1758 u64 v = (u64)khz * (1000000 + ppm);
1759 do_div(v, 1000000);
1760 return v;
1761 }
1762
1763 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1764 {
1765 u64 ratio;
1766
1767 /* Guest TSC same frequency as host TSC? */
1768 if (!scale) {
1769 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1770 return 0;
1771 }
1772
1773 /* TSC scaling supported? */
1774 if (!kvm_has_tsc_control) {
1775 if (user_tsc_khz > tsc_khz) {
1776 vcpu->arch.tsc_catchup = 1;
1777 vcpu->arch.tsc_always_catchup = 1;
1778 return 0;
1779 } else {
1780 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1781 return -1;
1782 }
1783 }
1784
1785 /* TSC scaling required - calculate ratio */
1786 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1787 user_tsc_khz, tsc_khz);
1788
1789 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1790 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1791 user_tsc_khz);
1792 return -1;
1793 }
1794
1795 vcpu->arch.tsc_scaling_ratio = ratio;
1796 return 0;
1797 }
1798
1799 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1800 {
1801 u32 thresh_lo, thresh_hi;
1802 int use_scaling = 0;
1803
1804 /* tsc_khz can be zero if TSC calibration fails */
1805 if (user_tsc_khz == 0) {
1806 /* set tsc_scaling_ratio to a safe value */
1807 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1808 return -1;
1809 }
1810
1811 /* Compute a scale to convert nanoseconds in TSC cycles */
1812 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1813 &vcpu->arch.virtual_tsc_shift,
1814 &vcpu->arch.virtual_tsc_mult);
1815 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1816
1817 /*
1818 * Compute the variation in TSC rate which is acceptable
1819 * within the range of tolerance and decide if the
1820 * rate being applied is within that bounds of the hardware
1821 * rate. If so, no scaling or compensation need be done.
1822 */
1823 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1824 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1825 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1826 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1827 use_scaling = 1;
1828 }
1829 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1830 }
1831
1832 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1833 {
1834 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1835 vcpu->arch.virtual_tsc_mult,
1836 vcpu->arch.virtual_tsc_shift);
1837 tsc += vcpu->arch.this_tsc_write;
1838 return tsc;
1839 }
1840
1841 static inline int gtod_is_based_on_tsc(int mode)
1842 {
1843 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1844 }
1845
1846 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1847 {
1848 #ifdef CONFIG_X86_64
1849 bool vcpus_matched;
1850 struct kvm_arch *ka = &vcpu->kvm->arch;
1851 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1852
1853 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1854 atomic_read(&vcpu->kvm->online_vcpus));
1855
1856 /*
1857 * Once the masterclock is enabled, always perform request in
1858 * order to update it.
1859 *
1860 * In order to enable masterclock, the host clocksource must be TSC
1861 * and the vcpus need to have matched TSCs. When that happens,
1862 * perform request to enable masterclock.
1863 */
1864 if (ka->use_master_clock ||
1865 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1866 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1867
1868 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1869 atomic_read(&vcpu->kvm->online_vcpus),
1870 ka->use_master_clock, gtod->clock.vclock_mode);
1871 #endif
1872 }
1873
1874 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1875 {
1876 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1877 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1878 }
1879
1880 /*
1881 * Multiply tsc by a fixed point number represented by ratio.
1882 *
1883 * The most significant 64-N bits (mult) of ratio represent the
1884 * integral part of the fixed point number; the remaining N bits
1885 * (frac) represent the fractional part, ie. ratio represents a fixed
1886 * point number (mult + frac * 2^(-N)).
1887 *
1888 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1889 */
1890 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1891 {
1892 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1893 }
1894
1895 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1896 {
1897 u64 _tsc = tsc;
1898 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1899
1900 if (ratio != kvm_default_tsc_scaling_ratio)
1901 _tsc = __scale_tsc(ratio, tsc);
1902
1903 return _tsc;
1904 }
1905 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1906
1907 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1908 {
1909 u64 tsc;
1910
1911 tsc = kvm_scale_tsc(vcpu, rdtsc());
1912
1913 return target_tsc - tsc;
1914 }
1915
1916 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1917 {
1918 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1919
1920 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1921 }
1922 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1923
1924 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1925 {
1926 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1927 }
1928
1929 static inline bool kvm_check_tsc_unstable(void)
1930 {
1931 #ifdef CONFIG_X86_64
1932 /*
1933 * TSC is marked unstable when we're running on Hyper-V,
1934 * 'TSC page' clocksource is good.
1935 */
1936 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1937 return false;
1938 #endif
1939 return check_tsc_unstable();
1940 }
1941
1942 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1943 {
1944 struct kvm *kvm = vcpu->kvm;
1945 u64 offset, ns, elapsed;
1946 unsigned long flags;
1947 bool matched;
1948 bool already_matched;
1949 u64 data = msr->data;
1950 bool synchronizing = false;
1951
1952 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1953 offset = kvm_compute_tsc_offset(vcpu, data);
1954 ns = get_kvmclock_base_ns();
1955 elapsed = ns - kvm->arch.last_tsc_nsec;
1956
1957 if (vcpu->arch.virtual_tsc_khz) {
1958 if (data == 0 && msr->host_initiated) {
1959 /*
1960 * detection of vcpu initialization -- need to sync
1961 * with other vCPUs. This particularly helps to keep
1962 * kvm_clock stable after CPU hotplug
1963 */
1964 synchronizing = true;
1965 } else {
1966 u64 tsc_exp = kvm->arch.last_tsc_write +
1967 nsec_to_cycles(vcpu, elapsed);
1968 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1969 /*
1970 * Special case: TSC write with a small delta (1 second)
1971 * of virtual cycle time against real time is
1972 * interpreted as an attempt to synchronize the CPU.
1973 */
1974 synchronizing = data < tsc_exp + tsc_hz &&
1975 data + tsc_hz > tsc_exp;
1976 }
1977 }
1978
1979 /*
1980 * For a reliable TSC, we can match TSC offsets, and for an unstable
1981 * TSC, we add elapsed time in this computation. We could let the
1982 * compensation code attempt to catch up if we fall behind, but
1983 * it's better to try to match offsets from the beginning.
1984 */
1985 if (synchronizing &&
1986 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1987 if (!kvm_check_tsc_unstable()) {
1988 offset = kvm->arch.cur_tsc_offset;
1989 } else {
1990 u64 delta = nsec_to_cycles(vcpu, elapsed);
1991 data += delta;
1992 offset = kvm_compute_tsc_offset(vcpu, data);
1993 }
1994 matched = true;
1995 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1996 } else {
1997 /*
1998 * We split periods of matched TSC writes into generations.
1999 * For each generation, we track the original measured
2000 * nanosecond time, offset, and write, so if TSCs are in
2001 * sync, we can match exact offset, and if not, we can match
2002 * exact software computation in compute_guest_tsc()
2003 *
2004 * These values are tracked in kvm->arch.cur_xxx variables.
2005 */
2006 kvm->arch.cur_tsc_generation++;
2007 kvm->arch.cur_tsc_nsec = ns;
2008 kvm->arch.cur_tsc_write = data;
2009 kvm->arch.cur_tsc_offset = offset;
2010 matched = false;
2011 }
2012
2013 /*
2014 * We also track th most recent recorded KHZ, write and time to
2015 * allow the matching interval to be extended at each write.
2016 */
2017 kvm->arch.last_tsc_nsec = ns;
2018 kvm->arch.last_tsc_write = data;
2019 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2020
2021 vcpu->arch.last_guest_tsc = data;
2022
2023 /* Keep track of which generation this VCPU has synchronized to */
2024 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2025 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2026 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2027
2028 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2029 update_ia32_tsc_adjust_msr(vcpu, offset);
2030
2031 kvm_vcpu_write_tsc_offset(vcpu, offset);
2032 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2033
2034 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2035 if (!matched) {
2036 kvm->arch.nr_vcpus_matched_tsc = 0;
2037 } else if (!already_matched) {
2038 kvm->arch.nr_vcpus_matched_tsc++;
2039 }
2040
2041 kvm_track_tsc_matching(vcpu);
2042 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2043 }
2044
2045 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2046
2047 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2048 s64 adjustment)
2049 {
2050 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
2051 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2052 }
2053
2054 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2055 {
2056 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2057 WARN_ON(adjustment < 0);
2058 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2059 adjust_tsc_offset_guest(vcpu, adjustment);
2060 }
2061
2062 #ifdef CONFIG_X86_64
2063
2064 static u64 read_tsc(void)
2065 {
2066 u64 ret = (u64)rdtsc_ordered();
2067 u64 last = pvclock_gtod_data.clock.cycle_last;
2068
2069 if (likely(ret >= last))
2070 return ret;
2071
2072 /*
2073 * GCC likes to generate cmov here, but this branch is extremely
2074 * predictable (it's just a function of time and the likely is
2075 * very likely) and there's a data dependence, so force GCC
2076 * to generate a branch instead. I don't barrier() because
2077 * we don't actually need a barrier, and if this function
2078 * ever gets inlined it will generate worse code.
2079 */
2080 asm volatile ("");
2081 return last;
2082 }
2083
2084 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2085 int *mode)
2086 {
2087 long v;
2088 u64 tsc_pg_val;
2089
2090 switch (clock->vclock_mode) {
2091 case VCLOCK_HVCLOCK:
2092 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2093 tsc_timestamp);
2094 if (tsc_pg_val != U64_MAX) {
2095 /* TSC page valid */
2096 *mode = VCLOCK_HVCLOCK;
2097 v = (tsc_pg_val - clock->cycle_last) &
2098 clock->mask;
2099 } else {
2100 /* TSC page invalid */
2101 *mode = VCLOCK_NONE;
2102 }
2103 break;
2104 case VCLOCK_TSC:
2105 *mode = VCLOCK_TSC;
2106 *tsc_timestamp = read_tsc();
2107 v = (*tsc_timestamp - clock->cycle_last) &
2108 clock->mask;
2109 break;
2110 default:
2111 *mode = VCLOCK_NONE;
2112 }
2113
2114 if (*mode == VCLOCK_NONE)
2115 *tsc_timestamp = v = 0;
2116
2117 return v * clock->mult;
2118 }
2119
2120 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2121 {
2122 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2123 unsigned long seq;
2124 int mode;
2125 u64 ns;
2126
2127 do {
2128 seq = read_seqcount_begin(&gtod->seq);
2129 ns = gtod->raw_clock.base_cycles;
2130 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2131 ns >>= gtod->raw_clock.shift;
2132 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2133 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2134 *t = ns;
2135
2136 return mode;
2137 }
2138
2139 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2140 {
2141 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2142 unsigned long seq;
2143 int mode;
2144 u64 ns;
2145
2146 do {
2147 seq = read_seqcount_begin(&gtod->seq);
2148 ts->tv_sec = gtod->wall_time_sec;
2149 ns = gtod->clock.base_cycles;
2150 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2151 ns >>= gtod->clock.shift;
2152 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2153
2154 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2155 ts->tv_nsec = ns;
2156
2157 return mode;
2158 }
2159
2160 /* returns true if host is using TSC based clocksource */
2161 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2162 {
2163 /* checked again under seqlock below */
2164 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2165 return false;
2166
2167 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2168 tsc_timestamp));
2169 }
2170
2171 /* returns true if host is using TSC based clocksource */
2172 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2173 u64 *tsc_timestamp)
2174 {
2175 /* checked again under seqlock below */
2176 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2177 return false;
2178
2179 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2180 }
2181 #endif
2182
2183 /*
2184 *
2185 * Assuming a stable TSC across physical CPUS, and a stable TSC
2186 * across virtual CPUs, the following condition is possible.
2187 * Each numbered line represents an event visible to both
2188 * CPUs at the next numbered event.
2189 *
2190 * "timespecX" represents host monotonic time. "tscX" represents
2191 * RDTSC value.
2192 *
2193 * VCPU0 on CPU0 | VCPU1 on CPU1
2194 *
2195 * 1. read timespec0,tsc0
2196 * 2. | timespec1 = timespec0 + N
2197 * | tsc1 = tsc0 + M
2198 * 3. transition to guest | transition to guest
2199 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2200 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2201 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2202 *
2203 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2204 *
2205 * - ret0 < ret1
2206 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2207 * ...
2208 * - 0 < N - M => M < N
2209 *
2210 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2211 * always the case (the difference between two distinct xtime instances
2212 * might be smaller then the difference between corresponding TSC reads,
2213 * when updating guest vcpus pvclock areas).
2214 *
2215 * To avoid that problem, do not allow visibility of distinct
2216 * system_timestamp/tsc_timestamp values simultaneously: use a master
2217 * copy of host monotonic time values. Update that master copy
2218 * in lockstep.
2219 *
2220 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2221 *
2222 */
2223
2224 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2225 {
2226 #ifdef CONFIG_X86_64
2227 struct kvm_arch *ka = &kvm->arch;
2228 int vclock_mode;
2229 bool host_tsc_clocksource, vcpus_matched;
2230
2231 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2232 atomic_read(&kvm->online_vcpus));
2233
2234 /*
2235 * If the host uses TSC clock, then passthrough TSC as stable
2236 * to the guest.
2237 */
2238 host_tsc_clocksource = kvm_get_time_and_clockread(
2239 &ka->master_kernel_ns,
2240 &ka->master_cycle_now);
2241
2242 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2243 && !ka->backwards_tsc_observed
2244 && !ka->boot_vcpu_runs_old_kvmclock;
2245
2246 if (ka->use_master_clock)
2247 atomic_set(&kvm_guest_has_master_clock, 1);
2248
2249 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2250 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2251 vcpus_matched);
2252 #endif
2253 }
2254
2255 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2256 {
2257 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2258 }
2259
2260 static void kvm_gen_update_masterclock(struct kvm *kvm)
2261 {
2262 #ifdef CONFIG_X86_64
2263 int i;
2264 struct kvm_vcpu *vcpu;
2265 struct kvm_arch *ka = &kvm->arch;
2266
2267 spin_lock(&ka->pvclock_gtod_sync_lock);
2268 kvm_make_mclock_inprogress_request(kvm);
2269 /* no guest entries from this point */
2270 pvclock_update_vm_gtod_copy(kvm);
2271
2272 kvm_for_each_vcpu(i, vcpu, kvm)
2273 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2274
2275 /* guest entries allowed */
2276 kvm_for_each_vcpu(i, vcpu, kvm)
2277 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2278
2279 spin_unlock(&ka->pvclock_gtod_sync_lock);
2280 #endif
2281 }
2282
2283 u64 get_kvmclock_ns(struct kvm *kvm)
2284 {
2285 struct kvm_arch *ka = &kvm->arch;
2286 struct pvclock_vcpu_time_info hv_clock;
2287 u64 ret;
2288
2289 spin_lock(&ka->pvclock_gtod_sync_lock);
2290 if (!ka->use_master_clock) {
2291 spin_unlock(&ka->pvclock_gtod_sync_lock);
2292 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2293 }
2294
2295 hv_clock.tsc_timestamp = ka->master_cycle_now;
2296 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2297 spin_unlock(&ka->pvclock_gtod_sync_lock);
2298
2299 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2300 get_cpu();
2301
2302 if (__this_cpu_read(cpu_tsc_khz)) {
2303 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2304 &hv_clock.tsc_shift,
2305 &hv_clock.tsc_to_system_mul);
2306 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2307 } else
2308 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2309
2310 put_cpu();
2311
2312 return ret;
2313 }
2314
2315 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2316 {
2317 struct kvm_vcpu_arch *vcpu = &v->arch;
2318 struct pvclock_vcpu_time_info guest_hv_clock;
2319
2320 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2321 &guest_hv_clock, sizeof(guest_hv_clock))))
2322 return;
2323
2324 /* This VCPU is paused, but it's legal for a guest to read another
2325 * VCPU's kvmclock, so we really have to follow the specification where
2326 * it says that version is odd if data is being modified, and even after
2327 * it is consistent.
2328 *
2329 * Version field updates must be kept separate. This is because
2330 * kvm_write_guest_cached might use a "rep movs" instruction, and
2331 * writes within a string instruction are weakly ordered. So there
2332 * are three writes overall.
2333 *
2334 * As a small optimization, only write the version field in the first
2335 * and third write. The vcpu->pv_time cache is still valid, because the
2336 * version field is the first in the struct.
2337 */
2338 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2339
2340 if (guest_hv_clock.version & 1)
2341 ++guest_hv_clock.version; /* first time write, random junk */
2342
2343 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2344 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2345 &vcpu->hv_clock,
2346 sizeof(vcpu->hv_clock.version));
2347
2348 smp_wmb();
2349
2350 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2351 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2352
2353 if (vcpu->pvclock_set_guest_stopped_request) {
2354 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2355 vcpu->pvclock_set_guest_stopped_request = false;
2356 }
2357
2358 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2359
2360 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2361 &vcpu->hv_clock,
2362 sizeof(vcpu->hv_clock));
2363
2364 smp_wmb();
2365
2366 vcpu->hv_clock.version++;
2367 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2368 &vcpu->hv_clock,
2369 sizeof(vcpu->hv_clock.version));
2370 }
2371
2372 static int kvm_guest_time_update(struct kvm_vcpu *v)
2373 {
2374 unsigned long flags, tgt_tsc_khz;
2375 struct kvm_vcpu_arch *vcpu = &v->arch;
2376 struct kvm_arch *ka = &v->kvm->arch;
2377 s64 kernel_ns;
2378 u64 tsc_timestamp, host_tsc;
2379 u8 pvclock_flags;
2380 bool use_master_clock;
2381
2382 kernel_ns = 0;
2383 host_tsc = 0;
2384
2385 /*
2386 * If the host uses TSC clock, then passthrough TSC as stable
2387 * to the guest.
2388 */
2389 spin_lock(&ka->pvclock_gtod_sync_lock);
2390 use_master_clock = ka->use_master_clock;
2391 if (use_master_clock) {
2392 host_tsc = ka->master_cycle_now;
2393 kernel_ns = ka->master_kernel_ns;
2394 }
2395 spin_unlock(&ka->pvclock_gtod_sync_lock);
2396
2397 /* Keep irq disabled to prevent changes to the clock */
2398 local_irq_save(flags);
2399 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2400 if (unlikely(tgt_tsc_khz == 0)) {
2401 local_irq_restore(flags);
2402 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2403 return 1;
2404 }
2405 if (!use_master_clock) {
2406 host_tsc = rdtsc();
2407 kernel_ns = get_kvmclock_base_ns();
2408 }
2409
2410 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2411
2412 /*
2413 * We may have to catch up the TSC to match elapsed wall clock
2414 * time for two reasons, even if kvmclock is used.
2415 * 1) CPU could have been running below the maximum TSC rate
2416 * 2) Broken TSC compensation resets the base at each VCPU
2417 * entry to avoid unknown leaps of TSC even when running
2418 * again on the same CPU. This may cause apparent elapsed
2419 * time to disappear, and the guest to stand still or run
2420 * very slowly.
2421 */
2422 if (vcpu->tsc_catchup) {
2423 u64 tsc = compute_guest_tsc(v, kernel_ns);
2424 if (tsc > tsc_timestamp) {
2425 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2426 tsc_timestamp = tsc;
2427 }
2428 }
2429
2430 local_irq_restore(flags);
2431
2432 /* With all the info we got, fill in the values */
2433
2434 if (kvm_has_tsc_control)
2435 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2436
2437 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2438 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2439 &vcpu->hv_clock.tsc_shift,
2440 &vcpu->hv_clock.tsc_to_system_mul);
2441 vcpu->hw_tsc_khz = tgt_tsc_khz;
2442 }
2443
2444 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2445 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2446 vcpu->last_guest_tsc = tsc_timestamp;
2447 WARN_ON((s64)vcpu->hv_clock.system_time < 0);
2448
2449 /* If the host uses TSC clocksource, then it is stable */
2450 pvclock_flags = 0;
2451 if (use_master_clock)
2452 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2453
2454 vcpu->hv_clock.flags = pvclock_flags;
2455
2456 if (vcpu->pv_time_enabled)
2457 kvm_setup_pvclock_page(v);
2458 if (v == kvm_get_vcpu(v->kvm, 0))
2459 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2460 return 0;
2461 }
2462
2463 /*
2464 * kvmclock updates which are isolated to a given vcpu, such as
2465 * vcpu->cpu migration, should not allow system_timestamp from
2466 * the rest of the vcpus to remain static. Otherwise ntp frequency
2467 * correction applies to one vcpu's system_timestamp but not
2468 * the others.
2469 *
2470 * So in those cases, request a kvmclock update for all vcpus.
2471 * We need to rate-limit these requests though, as they can
2472 * considerably slow guests that have a large number of vcpus.
2473 * The time for a remote vcpu to update its kvmclock is bound
2474 * by the delay we use to rate-limit the updates.
2475 */
2476
2477 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2478
2479 static void kvmclock_update_fn(struct work_struct *work)
2480 {
2481 int i;
2482 struct delayed_work *dwork = to_delayed_work(work);
2483 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2484 kvmclock_update_work);
2485 struct kvm *kvm = container_of(ka, struct kvm, arch);
2486 struct kvm_vcpu *vcpu;
2487
2488 kvm_for_each_vcpu(i, vcpu, kvm) {
2489 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2490 kvm_vcpu_kick(vcpu);
2491 }
2492 }
2493
2494 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2495 {
2496 struct kvm *kvm = v->kvm;
2497
2498 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2499 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2500 KVMCLOCK_UPDATE_DELAY);
2501 }
2502
2503 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2504
2505 static void kvmclock_sync_fn(struct work_struct *work)
2506 {
2507 struct delayed_work *dwork = to_delayed_work(work);
2508 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2509 kvmclock_sync_work);
2510 struct kvm *kvm = container_of(ka, struct kvm, arch);
2511
2512 if (!kvmclock_periodic_sync)
2513 return;
2514
2515 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2516 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2517 KVMCLOCK_SYNC_PERIOD);
2518 }
2519
2520 /*
2521 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2522 */
2523 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2524 {
2525 /* McStatusWrEn enabled? */
2526 if (guest_cpuid_is_amd(vcpu))
2527 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2528
2529 return false;
2530 }
2531
2532 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2533 {
2534 u64 mcg_cap = vcpu->arch.mcg_cap;
2535 unsigned bank_num = mcg_cap & 0xff;
2536 u32 msr = msr_info->index;
2537 u64 data = msr_info->data;
2538
2539 switch (msr) {
2540 case MSR_IA32_MCG_STATUS:
2541 vcpu->arch.mcg_status = data;
2542 break;
2543 case MSR_IA32_MCG_CTL:
2544 if (!(mcg_cap & MCG_CTL_P) &&
2545 (data || !msr_info->host_initiated))
2546 return 1;
2547 if (data != 0 && data != ~(u64)0)
2548 return 1;
2549 vcpu->arch.mcg_ctl = data;
2550 break;
2551 default:
2552 if (msr >= MSR_IA32_MC0_CTL &&
2553 msr < MSR_IA32_MCx_CTL(bank_num)) {
2554 u32 offset = array_index_nospec(
2555 msr - MSR_IA32_MC0_CTL,
2556 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2557
2558 /* only 0 or all 1s can be written to IA32_MCi_CTL
2559 * some Linux kernels though clear bit 10 in bank 4 to
2560 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2561 * this to avoid an uncatched #GP in the guest
2562 */
2563 if ((offset & 0x3) == 0 &&
2564 data != 0 && (data | (1 << 10)) != ~(u64)0)
2565 return -1;
2566
2567 /* MCi_STATUS */
2568 if (!msr_info->host_initiated &&
2569 (offset & 0x3) == 1 && data != 0) {
2570 if (!can_set_mci_status(vcpu))
2571 return -1;
2572 }
2573
2574 vcpu->arch.mce_banks[offset] = data;
2575 break;
2576 }
2577 return 1;
2578 }
2579 return 0;
2580 }
2581
2582 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2583 {
2584 struct kvm *kvm = vcpu->kvm;
2585 int lm = is_long_mode(vcpu);
2586 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2587 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2588 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2589 : kvm->arch.xen_hvm_config.blob_size_32;
2590 u32 page_num = data & ~PAGE_MASK;
2591 u64 page_addr = data & PAGE_MASK;
2592 u8 *page;
2593 int r;
2594
2595 r = -E2BIG;
2596 if (page_num >= blob_size)
2597 goto out;
2598 r = -ENOMEM;
2599 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2600 if (IS_ERR(page)) {
2601 r = PTR_ERR(page);
2602 goto out;
2603 }
2604 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2605 goto out_free;
2606 r = 0;
2607 out_free:
2608 kfree(page);
2609 out:
2610 return r;
2611 }
2612
2613 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2614 {
2615 gpa_t gpa = data & ~0x3f;
2616
2617 /* Bits 3:5 are reserved, Should be zero */
2618 if (data & 0x38)
2619 return 1;
2620
2621 vcpu->arch.apf.msr_val = data;
2622
2623 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2624 kvm_clear_async_pf_completion_queue(vcpu);
2625 kvm_async_pf_hash_reset(vcpu);
2626 return 0;
2627 }
2628
2629 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2630 sizeof(u32)))
2631 return 1;
2632
2633 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2634 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2635 kvm_async_pf_wakeup_all(vcpu);
2636 return 0;
2637 }
2638
2639 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2640 {
2641 vcpu->arch.pv_time_enabled = false;
2642 vcpu->arch.time = 0;
2643 }
2644
2645 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2646 {
2647 ++vcpu->stat.tlb_flush;
2648 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2649 }
2650
2651 static void record_steal_time(struct kvm_vcpu *vcpu)
2652 {
2653 struct kvm_host_map map;
2654 struct kvm_steal_time *st;
2655
2656 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2657 return;
2658
2659 /* -EAGAIN is returned in atomic context so we can just return. */
2660 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2661 &map, &vcpu->arch.st.cache, false))
2662 return;
2663
2664 st = map.hva +
2665 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2666
2667 /*
2668 * Doing a TLB flush here, on the guest's behalf, can avoid
2669 * expensive IPIs.
2670 */
2671 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2672 st->preempted & KVM_VCPU_FLUSH_TLB);
2673 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2674 kvm_vcpu_flush_tlb(vcpu, false);
2675
2676 vcpu->arch.st.preempted = 0;
2677
2678 if (st->version & 1)
2679 st->version += 1; /* first time write, random junk */
2680
2681 st->version += 1;
2682
2683 smp_wmb();
2684
2685 st->steal += current->sched_info.run_delay -
2686 vcpu->arch.st.last_steal;
2687 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2688
2689 smp_wmb();
2690
2691 st->version += 1;
2692
2693 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2694 }
2695
2696 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2697 {
2698 bool pr = false;
2699 u32 msr = msr_info->index;
2700 u64 data = msr_info->data;
2701
2702 switch (msr) {
2703 case MSR_AMD64_NB_CFG:
2704 case MSR_IA32_UCODE_WRITE:
2705 case MSR_VM_HSAVE_PA:
2706 case MSR_AMD64_PATCH_LOADER:
2707 case MSR_AMD64_BU_CFG2:
2708 case MSR_AMD64_DC_CFG:
2709 case MSR_F15H_EX_CFG:
2710 break;
2711
2712 case MSR_IA32_UCODE_REV:
2713 if (msr_info->host_initiated)
2714 vcpu->arch.microcode_version = data;
2715 break;
2716 case MSR_IA32_ARCH_CAPABILITIES:
2717 if (!msr_info->host_initiated)
2718 return 1;
2719 vcpu->arch.arch_capabilities = data;
2720 break;
2721 case MSR_EFER:
2722 return set_efer(vcpu, msr_info);
2723 case MSR_K7_HWCR:
2724 data &= ~(u64)0x40; /* ignore flush filter disable */
2725 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2726 data &= ~(u64)0x8; /* ignore TLB cache disable */
2727
2728 /* Handle McStatusWrEn */
2729 if (data == BIT_ULL(18)) {
2730 vcpu->arch.msr_hwcr = data;
2731 } else if (data != 0) {
2732 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2733 data);
2734 return 1;
2735 }
2736 break;
2737 case MSR_FAM10H_MMIO_CONF_BASE:
2738 if (data != 0) {
2739 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2740 "0x%llx\n", data);
2741 return 1;
2742 }
2743 break;
2744 case MSR_IA32_DEBUGCTLMSR:
2745 if (!data) {
2746 /* We support the non-activated case already */
2747 break;
2748 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2749 /* Values other than LBR and BTF are vendor-specific,
2750 thus reserved and should throw a #GP */
2751 return 1;
2752 }
2753 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2754 __func__, data);
2755 break;
2756 case 0x200 ... 0x2ff:
2757 return kvm_mtrr_set_msr(vcpu, msr, data);
2758 case MSR_IA32_APICBASE:
2759 return kvm_set_apic_base(vcpu, msr_info);
2760 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2761 return kvm_x2apic_msr_write(vcpu, msr, data);
2762 case MSR_IA32_TSCDEADLINE:
2763 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2764 break;
2765 case MSR_IA32_TSC_ADJUST:
2766 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2767 if (!msr_info->host_initiated) {
2768 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2769 adjust_tsc_offset_guest(vcpu, adj);
2770 }
2771 vcpu->arch.ia32_tsc_adjust_msr = data;
2772 }
2773 break;
2774 case MSR_IA32_MISC_ENABLE:
2775 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2776 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2777 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2778 return 1;
2779 vcpu->arch.ia32_misc_enable_msr = data;
2780 kvm_update_cpuid(vcpu);
2781 } else {
2782 vcpu->arch.ia32_misc_enable_msr = data;
2783 }
2784 break;
2785 case MSR_IA32_SMBASE:
2786 if (!msr_info->host_initiated)
2787 return 1;
2788 vcpu->arch.smbase = data;
2789 break;
2790 case MSR_IA32_POWER_CTL:
2791 vcpu->arch.msr_ia32_power_ctl = data;
2792 break;
2793 case MSR_IA32_TSC:
2794 kvm_write_tsc(vcpu, msr_info);
2795 break;
2796 case MSR_IA32_XSS:
2797 if (!msr_info->host_initiated &&
2798 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2799 return 1;
2800 /*
2801 * We do support PT if kvm_x86_ops->pt_supported(), but we do
2802 * not support IA32_XSS[bit 8]. Guests will have to use
2803 * RDMSR/WRMSR rather than XSAVES/XRSTORS to save/restore PT
2804 * MSRs.
2805 */
2806 if (data != 0)
2807 return 1;
2808 vcpu->arch.ia32_xss = data;
2809 break;
2810 case MSR_SMI_COUNT:
2811 if (!msr_info->host_initiated)
2812 return 1;
2813 vcpu->arch.smi_count = data;
2814 break;
2815 case MSR_KVM_WALL_CLOCK_NEW:
2816 case MSR_KVM_WALL_CLOCK:
2817 vcpu->kvm->arch.wall_clock = data;
2818 kvm_write_wall_clock(vcpu->kvm, data);
2819 break;
2820 case MSR_KVM_SYSTEM_TIME_NEW:
2821 case MSR_KVM_SYSTEM_TIME: {
2822 struct kvm_arch *ka = &vcpu->kvm->arch;
2823
2824 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2825 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2826
2827 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2828 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2829
2830 ka->boot_vcpu_runs_old_kvmclock = tmp;
2831 }
2832
2833 vcpu->arch.time = data;
2834 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2835
2836 /* we verify if the enable bit is set... */
2837 vcpu->arch.pv_time_enabled = false;
2838 if (!(data & 1))
2839 break;
2840
2841 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2842 &vcpu->arch.pv_time, data & ~1ULL,
2843 sizeof(struct pvclock_vcpu_time_info)))
2844 vcpu->arch.pv_time_enabled = true;
2845
2846 break;
2847 }
2848 case MSR_KVM_ASYNC_PF_EN:
2849 if (kvm_pv_enable_async_pf(vcpu, data))
2850 return 1;
2851 break;
2852 case MSR_KVM_STEAL_TIME:
2853
2854 if (unlikely(!sched_info_on()))
2855 return 1;
2856
2857 if (data & KVM_STEAL_RESERVED_MASK)
2858 return 1;
2859
2860 vcpu->arch.st.msr_val = data;
2861
2862 if (!(data & KVM_MSR_ENABLED))
2863 break;
2864
2865 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2866
2867 break;
2868 case MSR_KVM_PV_EOI_EN:
2869 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2870 return 1;
2871 break;
2872
2873 case MSR_KVM_POLL_CONTROL:
2874 /* only enable bit supported */
2875 if (data & (-1ULL << 1))
2876 return 1;
2877
2878 vcpu->arch.msr_kvm_poll_control = data;
2879 break;
2880
2881 case MSR_IA32_MCG_CTL:
2882 case MSR_IA32_MCG_STATUS:
2883 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2884 return set_msr_mce(vcpu, msr_info);
2885
2886 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2887 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2888 pr = true; /* fall through */
2889 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2890 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2891 if (kvm_pmu_is_valid_msr(vcpu, msr))
2892 return kvm_pmu_set_msr(vcpu, msr_info);
2893
2894 if (pr || data != 0)
2895 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2896 "0x%x data 0x%llx\n", msr, data);
2897 break;
2898 case MSR_K7_CLK_CTL:
2899 /*
2900 * Ignore all writes to this no longer documented MSR.
2901 * Writes are only relevant for old K7 processors,
2902 * all pre-dating SVM, but a recommended workaround from
2903 * AMD for these chips. It is possible to specify the
2904 * affected processor models on the command line, hence
2905 * the need to ignore the workaround.
2906 */
2907 break;
2908 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2909 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2910 case HV_X64_MSR_CRASH_CTL:
2911 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2912 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2913 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2914 case HV_X64_MSR_TSC_EMULATION_STATUS:
2915 return kvm_hv_set_msr_common(vcpu, msr, data,
2916 msr_info->host_initiated);
2917 case MSR_IA32_BBL_CR_CTL3:
2918 /* Drop writes to this legacy MSR -- see rdmsr
2919 * counterpart for further detail.
2920 */
2921 if (report_ignored_msrs)
2922 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2923 msr, data);
2924 break;
2925 case MSR_AMD64_OSVW_ID_LENGTH:
2926 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2927 return 1;
2928 vcpu->arch.osvw.length = data;
2929 break;
2930 case MSR_AMD64_OSVW_STATUS:
2931 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2932 return 1;
2933 vcpu->arch.osvw.status = data;
2934 break;
2935 case MSR_PLATFORM_INFO:
2936 if (!msr_info->host_initiated ||
2937 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2938 cpuid_fault_enabled(vcpu)))
2939 return 1;
2940 vcpu->arch.msr_platform_info = data;
2941 break;
2942 case MSR_MISC_FEATURES_ENABLES:
2943 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2944 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2945 !supports_cpuid_fault(vcpu)))
2946 return 1;
2947 vcpu->arch.msr_misc_features_enables = data;
2948 break;
2949 default:
2950 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2951 return xen_hvm_config(vcpu, data);
2952 if (kvm_pmu_is_valid_msr(vcpu, msr))
2953 return kvm_pmu_set_msr(vcpu, msr_info);
2954 if (!ignore_msrs) {
2955 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2956 msr, data);
2957 return 1;
2958 } else {
2959 if (report_ignored_msrs)
2960 vcpu_unimpl(vcpu,
2961 "ignored wrmsr: 0x%x data 0x%llx\n",
2962 msr, data);
2963 break;
2964 }
2965 }
2966 return 0;
2967 }
2968 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2969
2970 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2971 {
2972 u64 data;
2973 u64 mcg_cap = vcpu->arch.mcg_cap;
2974 unsigned bank_num = mcg_cap & 0xff;
2975
2976 switch (msr) {
2977 case MSR_IA32_P5_MC_ADDR:
2978 case MSR_IA32_P5_MC_TYPE:
2979 data = 0;
2980 break;
2981 case MSR_IA32_MCG_CAP:
2982 data = vcpu->arch.mcg_cap;
2983 break;
2984 case MSR_IA32_MCG_CTL:
2985 if (!(mcg_cap & MCG_CTL_P) && !host)
2986 return 1;
2987 data = vcpu->arch.mcg_ctl;
2988 break;
2989 case MSR_IA32_MCG_STATUS:
2990 data = vcpu->arch.mcg_status;
2991 break;
2992 default:
2993 if (msr >= MSR_IA32_MC0_CTL &&
2994 msr < MSR_IA32_MCx_CTL(bank_num)) {
2995 u32 offset = array_index_nospec(
2996 msr - MSR_IA32_MC0_CTL,
2997 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2998
2999 data = vcpu->arch.mce_banks[offset];
3000 break;
3001 }
3002 return 1;
3003 }
3004 *pdata = data;
3005 return 0;
3006 }
3007
3008 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3009 {
3010 switch (msr_info->index) {
3011 case MSR_IA32_PLATFORM_ID:
3012 case MSR_IA32_EBL_CR_POWERON:
3013 case MSR_IA32_DEBUGCTLMSR:
3014 case MSR_IA32_LASTBRANCHFROMIP:
3015 case MSR_IA32_LASTBRANCHTOIP:
3016 case MSR_IA32_LASTINTFROMIP:
3017 case MSR_IA32_LASTINTTOIP:
3018 case MSR_K8_SYSCFG:
3019 case MSR_K8_TSEG_ADDR:
3020 case MSR_K8_TSEG_MASK:
3021 case MSR_VM_HSAVE_PA:
3022 case MSR_K8_INT_PENDING_MSG:
3023 case MSR_AMD64_NB_CFG:
3024 case MSR_FAM10H_MMIO_CONF_BASE:
3025 case MSR_AMD64_BU_CFG2:
3026 case MSR_IA32_PERF_CTL:
3027 case MSR_AMD64_DC_CFG:
3028 case MSR_F15H_EX_CFG:
3029 msr_info->data = 0;
3030 break;
3031 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3032 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3033 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3034 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3035 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3036 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3037 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3038 msr_info->data = 0;
3039 break;
3040 case MSR_IA32_UCODE_REV:
3041 msr_info->data = vcpu->arch.microcode_version;
3042 break;
3043 case MSR_IA32_ARCH_CAPABILITIES:
3044 if (!msr_info->host_initiated &&
3045 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3046 return 1;
3047 msr_info->data = vcpu->arch.arch_capabilities;
3048 break;
3049 case MSR_IA32_POWER_CTL:
3050 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3051 break;
3052 case MSR_IA32_TSC:
3053 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3054 break;
3055 case MSR_MTRRcap:
3056 case 0x200 ... 0x2ff:
3057 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3058 case 0xcd: /* fsb frequency */
3059 msr_info->data = 3;
3060 break;
3061 /*
3062 * MSR_EBC_FREQUENCY_ID
3063 * Conservative value valid for even the basic CPU models.
3064 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3065 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3066 * and 266MHz for model 3, or 4. Set Core Clock
3067 * Frequency to System Bus Frequency Ratio to 1 (bits
3068 * 31:24) even though these are only valid for CPU
3069 * models > 2, however guests may end up dividing or
3070 * multiplying by zero otherwise.
3071 */
3072 case MSR_EBC_FREQUENCY_ID:
3073 msr_info->data = 1 << 24;
3074 break;
3075 case MSR_IA32_APICBASE:
3076 msr_info->data = kvm_get_apic_base(vcpu);
3077 break;
3078 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3079 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3080 case MSR_IA32_TSCDEADLINE:
3081 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3082 break;
3083 case MSR_IA32_TSC_ADJUST:
3084 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3085 break;
3086 case MSR_IA32_MISC_ENABLE:
3087 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3088 break;
3089 case MSR_IA32_SMBASE:
3090 if (!msr_info->host_initiated)
3091 return 1;
3092 msr_info->data = vcpu->arch.smbase;
3093 break;
3094 case MSR_SMI_COUNT:
3095 msr_info->data = vcpu->arch.smi_count;
3096 break;
3097 case MSR_IA32_PERF_STATUS:
3098 /* TSC increment by tick */
3099 msr_info->data = 1000ULL;
3100 /* CPU multiplier */
3101 msr_info->data |= (((uint64_t)4ULL) << 40);
3102 break;
3103 case MSR_EFER:
3104 msr_info->data = vcpu->arch.efer;
3105 break;
3106 case MSR_KVM_WALL_CLOCK:
3107 case MSR_KVM_WALL_CLOCK_NEW:
3108 msr_info->data = vcpu->kvm->arch.wall_clock;
3109 break;
3110 case MSR_KVM_SYSTEM_TIME:
3111 case MSR_KVM_SYSTEM_TIME_NEW:
3112 msr_info->data = vcpu->arch.time;
3113 break;
3114 case MSR_KVM_ASYNC_PF_EN:
3115 msr_info->data = vcpu->arch.apf.msr_val;
3116 break;
3117 case MSR_KVM_STEAL_TIME:
3118 msr_info->data = vcpu->arch.st.msr_val;
3119 break;
3120 case MSR_KVM_PV_EOI_EN:
3121 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3122 break;
3123 case MSR_KVM_POLL_CONTROL:
3124 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3125 break;
3126 case MSR_IA32_P5_MC_ADDR:
3127 case MSR_IA32_P5_MC_TYPE:
3128 case MSR_IA32_MCG_CAP:
3129 case MSR_IA32_MCG_CTL:
3130 case MSR_IA32_MCG_STATUS:
3131 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3132 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3133 msr_info->host_initiated);
3134 case MSR_IA32_XSS:
3135 if (!msr_info->host_initiated &&
3136 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3137 return 1;
3138 msr_info->data = vcpu->arch.ia32_xss;
3139 break;
3140 case MSR_K7_CLK_CTL:
3141 /*
3142 * Provide expected ramp-up count for K7. All other
3143 * are set to zero, indicating minimum divisors for
3144 * every field.
3145 *
3146 * This prevents guest kernels on AMD host with CPU
3147 * type 6, model 8 and higher from exploding due to
3148 * the rdmsr failing.
3149 */
3150 msr_info->data = 0x20000000;
3151 break;
3152 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3153 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3154 case HV_X64_MSR_CRASH_CTL:
3155 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3156 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3157 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3158 case HV_X64_MSR_TSC_EMULATION_STATUS:
3159 return kvm_hv_get_msr_common(vcpu,
3160 msr_info->index, &msr_info->data,
3161 msr_info->host_initiated);
3162 case MSR_IA32_BBL_CR_CTL3:
3163 /* This legacy MSR exists but isn't fully documented in current
3164 * silicon. It is however accessed by winxp in very narrow
3165 * scenarios where it sets bit #19, itself documented as
3166 * a "reserved" bit. Best effort attempt to source coherent
3167 * read data here should the balance of the register be
3168 * interpreted by the guest:
3169 *
3170 * L2 cache control register 3: 64GB range, 256KB size,
3171 * enabled, latency 0x1, configured
3172 */
3173 msr_info->data = 0xbe702111;
3174 break;
3175 case MSR_AMD64_OSVW_ID_LENGTH:
3176 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3177 return 1;
3178 msr_info->data = vcpu->arch.osvw.length;
3179 break;
3180 case MSR_AMD64_OSVW_STATUS:
3181 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3182 return 1;
3183 msr_info->data = vcpu->arch.osvw.status;
3184 break;
3185 case MSR_PLATFORM_INFO:
3186 if (!msr_info->host_initiated &&
3187 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3188 return 1;
3189 msr_info->data = vcpu->arch.msr_platform_info;
3190 break;
3191 case MSR_MISC_FEATURES_ENABLES:
3192 msr_info->data = vcpu->arch.msr_misc_features_enables;
3193 break;
3194 case MSR_K7_HWCR:
3195 msr_info->data = vcpu->arch.msr_hwcr;
3196 break;
3197 default:
3198 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3199 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3200 if (!ignore_msrs) {
3201 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3202 msr_info->index);
3203 return 1;
3204 } else {
3205 if (report_ignored_msrs)
3206 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3207 msr_info->index);
3208 msr_info->data = 0;
3209 }
3210 break;
3211 }
3212 return 0;
3213 }
3214 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3215
3216 /*
3217 * Read or write a bunch of msrs. All parameters are kernel addresses.
3218 *
3219 * @return number of msrs set successfully.
3220 */
3221 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3222 struct kvm_msr_entry *entries,
3223 int (*do_msr)(struct kvm_vcpu *vcpu,
3224 unsigned index, u64 *data))
3225 {
3226 int i;
3227
3228 for (i = 0; i < msrs->nmsrs; ++i)
3229 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3230 break;
3231
3232 return i;
3233 }
3234
3235 /*
3236 * Read or write a bunch of msrs. Parameters are user addresses.
3237 *
3238 * @return number of msrs set successfully.
3239 */
3240 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3241 int (*do_msr)(struct kvm_vcpu *vcpu,
3242 unsigned index, u64 *data),
3243 int writeback)
3244 {
3245 struct kvm_msrs msrs;
3246 struct kvm_msr_entry *entries;
3247 int r, n;
3248 unsigned size;
3249
3250 r = -EFAULT;
3251 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3252 goto out;
3253
3254 r = -E2BIG;
3255 if (msrs.nmsrs >= MAX_IO_MSRS)
3256 goto out;
3257
3258 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3259 entries = memdup_user(user_msrs->entries, size);
3260 if (IS_ERR(entries)) {
3261 r = PTR_ERR(entries);
3262 goto out;
3263 }
3264
3265 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3266 if (r < 0)
3267 goto out_free;
3268
3269 r = -EFAULT;
3270 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3271 goto out_free;
3272
3273 r = n;
3274
3275 out_free:
3276 kfree(entries);
3277 out:
3278 return r;
3279 }
3280
3281 static inline bool kvm_can_mwait_in_guest(void)
3282 {
3283 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3284 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3285 boot_cpu_has(X86_FEATURE_ARAT);
3286 }
3287
3288 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3289 {
3290 int r = 0;
3291
3292 switch (ext) {
3293 case KVM_CAP_IRQCHIP:
3294 case KVM_CAP_HLT:
3295 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3296 case KVM_CAP_SET_TSS_ADDR:
3297 case KVM_CAP_EXT_CPUID:
3298 case KVM_CAP_EXT_EMUL_CPUID:
3299 case KVM_CAP_CLOCKSOURCE:
3300 case KVM_CAP_PIT:
3301 case KVM_CAP_NOP_IO_DELAY:
3302 case KVM_CAP_MP_STATE:
3303 case KVM_CAP_SYNC_MMU:
3304 case KVM_CAP_USER_NMI:
3305 case KVM_CAP_REINJECT_CONTROL:
3306 case KVM_CAP_IRQ_INJECT_STATUS:
3307 case KVM_CAP_IOEVENTFD:
3308 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3309 case KVM_CAP_PIT2:
3310 case KVM_CAP_PIT_STATE2:
3311 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3312 case KVM_CAP_XEN_HVM:
3313 case KVM_CAP_VCPU_EVENTS:
3314 case KVM_CAP_HYPERV:
3315 case KVM_CAP_HYPERV_VAPIC:
3316 case KVM_CAP_HYPERV_SPIN:
3317 case KVM_CAP_HYPERV_SYNIC:
3318 case KVM_CAP_HYPERV_SYNIC2:
3319 case KVM_CAP_HYPERV_VP_INDEX:
3320 case KVM_CAP_HYPERV_EVENTFD:
3321 case KVM_CAP_HYPERV_TLBFLUSH:
3322 case KVM_CAP_HYPERV_SEND_IPI:
3323 case KVM_CAP_HYPERV_CPUID:
3324 case KVM_CAP_PCI_SEGMENT:
3325 case KVM_CAP_DEBUGREGS:
3326 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3327 case KVM_CAP_XSAVE:
3328 case KVM_CAP_ASYNC_PF:
3329 case KVM_CAP_GET_TSC_KHZ:
3330 case KVM_CAP_KVMCLOCK_CTRL:
3331 case KVM_CAP_READONLY_MEM:
3332 case KVM_CAP_HYPERV_TIME:
3333 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3334 case KVM_CAP_TSC_DEADLINE_TIMER:
3335 case KVM_CAP_DISABLE_QUIRKS:
3336 case KVM_CAP_SET_BOOT_CPU_ID:
3337 case KVM_CAP_SPLIT_IRQCHIP:
3338 case KVM_CAP_IMMEDIATE_EXIT:
3339 case KVM_CAP_PMU_EVENT_FILTER:
3340 case KVM_CAP_GET_MSR_FEATURES:
3341 case KVM_CAP_MSR_PLATFORM_INFO:
3342 case KVM_CAP_EXCEPTION_PAYLOAD:
3343 r = 1;
3344 break;
3345 case KVM_CAP_SYNC_REGS:
3346 r = KVM_SYNC_X86_VALID_FIELDS;
3347 break;
3348 case KVM_CAP_ADJUST_CLOCK:
3349 r = KVM_CLOCK_TSC_STABLE;
3350 break;
3351 case KVM_CAP_X86_DISABLE_EXITS:
3352 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3353 KVM_X86_DISABLE_EXITS_CSTATE;
3354 if(kvm_can_mwait_in_guest())
3355 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3356 break;
3357 case KVM_CAP_X86_SMM:
3358 /* SMBASE is usually relocated above 1M on modern chipsets,
3359 * and SMM handlers might indeed rely on 4G segment limits,
3360 * so do not report SMM to be available if real mode is
3361 * emulated via vm86 mode. Still, do not go to great lengths
3362 * to avoid userspace's usage of the feature, because it is a
3363 * fringe case that is not enabled except via specific settings
3364 * of the module parameters.
3365 */
3366 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3367 break;
3368 case KVM_CAP_VAPIC:
3369 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3370 break;
3371 case KVM_CAP_NR_VCPUS:
3372 r = KVM_SOFT_MAX_VCPUS;
3373 break;
3374 case KVM_CAP_MAX_VCPUS:
3375 r = KVM_MAX_VCPUS;
3376 break;
3377 case KVM_CAP_MAX_VCPU_ID:
3378 r = KVM_MAX_VCPU_ID;
3379 break;
3380 case KVM_CAP_PV_MMU: /* obsolete */
3381 r = 0;
3382 break;
3383 case KVM_CAP_MCE:
3384 r = KVM_MAX_MCE_BANKS;
3385 break;
3386 case KVM_CAP_XCRS:
3387 r = boot_cpu_has(X86_FEATURE_XSAVE);
3388 break;
3389 case KVM_CAP_TSC_CONTROL:
3390 r = kvm_has_tsc_control;
3391 break;
3392 case KVM_CAP_X2APIC_API:
3393 r = KVM_X2APIC_API_VALID_FLAGS;
3394 break;
3395 case KVM_CAP_NESTED_STATE:
3396 r = kvm_x86_ops->get_nested_state ?
3397 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3398 break;
3399 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3400 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3401 break;
3402 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3403 r = kvm_x86_ops->nested_enable_evmcs != NULL;
3404 break;
3405 default:
3406 break;
3407 }
3408 return r;
3409
3410 }
3411
3412 long kvm_arch_dev_ioctl(struct file *filp,
3413 unsigned int ioctl, unsigned long arg)
3414 {
3415 void __user *argp = (void __user *)arg;
3416 long r;
3417
3418 switch (ioctl) {
3419 case KVM_GET_MSR_INDEX_LIST: {
3420 struct kvm_msr_list __user *user_msr_list = argp;
3421 struct kvm_msr_list msr_list;
3422 unsigned n;
3423
3424 r = -EFAULT;
3425 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3426 goto out;
3427 n = msr_list.nmsrs;
3428 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3429 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3430 goto out;
3431 r = -E2BIG;
3432 if (n < msr_list.nmsrs)
3433 goto out;
3434 r = -EFAULT;
3435 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3436 num_msrs_to_save * sizeof(u32)))
3437 goto out;
3438 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3439 &emulated_msrs,
3440 num_emulated_msrs * sizeof(u32)))
3441 goto out;
3442 r = 0;
3443 break;
3444 }
3445 case KVM_GET_SUPPORTED_CPUID:
3446 case KVM_GET_EMULATED_CPUID: {
3447 struct kvm_cpuid2 __user *cpuid_arg = argp;
3448 struct kvm_cpuid2 cpuid;
3449
3450 r = -EFAULT;
3451 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3452 goto out;
3453
3454 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3455 ioctl);
3456 if (r)
3457 goto out;
3458
3459 r = -EFAULT;
3460 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3461 goto out;
3462 r = 0;
3463 break;
3464 }
3465 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3466 r = -EFAULT;
3467 if (copy_to_user(argp, &kvm_mce_cap_supported,
3468 sizeof(kvm_mce_cap_supported)))
3469 goto out;
3470 r = 0;
3471 break;
3472 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3473 struct kvm_msr_list __user *user_msr_list = argp;
3474 struct kvm_msr_list msr_list;
3475 unsigned int n;
3476
3477 r = -EFAULT;
3478 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3479 goto out;
3480 n = msr_list.nmsrs;
3481 msr_list.nmsrs = num_msr_based_features;
3482 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3483 goto out;
3484 r = -E2BIG;
3485 if (n < msr_list.nmsrs)
3486 goto out;
3487 r = -EFAULT;
3488 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3489 num_msr_based_features * sizeof(u32)))
3490 goto out;
3491 r = 0;
3492 break;
3493 }
3494 case KVM_GET_MSRS:
3495 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3496 break;
3497 }
3498 default:
3499 r = -EINVAL;
3500 }
3501 out:
3502 return r;
3503 }
3504
3505 static void wbinvd_ipi(void *garbage)
3506 {
3507 wbinvd();
3508 }
3509
3510 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3511 {
3512 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3513 }
3514
3515 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3516 {
3517 /* Address WBINVD may be executed by guest */
3518 if (need_emulate_wbinvd(vcpu)) {
3519 if (kvm_x86_ops->has_wbinvd_exit())
3520 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3521 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3522 smp_call_function_single(vcpu->cpu,
3523 wbinvd_ipi, NULL, 1);
3524 }
3525
3526 kvm_x86_ops->vcpu_load(vcpu, cpu);
3527
3528 /* Apply any externally detected TSC adjustments (due to suspend) */
3529 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3530 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3531 vcpu->arch.tsc_offset_adjustment = 0;
3532 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3533 }
3534
3535 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3536 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3537 rdtsc() - vcpu->arch.last_host_tsc;
3538 if (tsc_delta < 0)
3539 mark_tsc_unstable("KVM discovered backwards TSC");
3540
3541 if (kvm_check_tsc_unstable()) {
3542 u64 offset = kvm_compute_tsc_offset(vcpu,
3543 vcpu->arch.last_guest_tsc);
3544 kvm_vcpu_write_tsc_offset(vcpu, offset);
3545 vcpu->arch.tsc_catchup = 1;
3546 }
3547
3548 if (kvm_lapic_hv_timer_in_use(vcpu))
3549 kvm_lapic_restart_hv_timer(vcpu);
3550
3551 /*
3552 * On a host with synchronized TSC, there is no need to update
3553 * kvmclock on vcpu->cpu migration
3554 */
3555 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3556 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3557 if (vcpu->cpu != cpu)
3558 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3559 vcpu->cpu = cpu;
3560 }
3561
3562 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3563 }
3564
3565 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3566 {
3567 struct kvm_host_map map;
3568 struct kvm_steal_time *st;
3569
3570 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3571 return;
3572
3573 if (vcpu->arch.st.preempted)
3574 return;
3575
3576 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3577 &vcpu->arch.st.cache, true))
3578 return;
3579
3580 st = map.hva +
3581 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3582
3583 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3584
3585 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3586 }
3587
3588 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3589 {
3590 int idx;
3591
3592 if (vcpu->preempted)
3593 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3594
3595 /*
3596 * Disable page faults because we're in atomic context here.
3597 * kvm_write_guest_offset_cached() would call might_fault()
3598 * that relies on pagefault_disable() to tell if there's a
3599 * bug. NOTE: the write to guest memory may not go through if
3600 * during postcopy live migration or if there's heavy guest
3601 * paging.
3602 */
3603 pagefault_disable();
3604 /*
3605 * kvm_memslots() will be called by
3606 * kvm_write_guest_offset_cached() so take the srcu lock.
3607 */
3608 idx = srcu_read_lock(&vcpu->kvm->srcu);
3609 kvm_steal_time_set_preempted(vcpu);
3610 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3611 pagefault_enable();
3612 kvm_x86_ops->vcpu_put(vcpu);
3613 vcpu->arch.last_host_tsc = rdtsc();
3614 /*
3615 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3616 * on every vmexit, but if not, we might have a stale dr6 from the
3617 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3618 */
3619 set_debugreg(0, 6);
3620 }
3621
3622 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3623 struct kvm_lapic_state *s)
3624 {
3625 if (vcpu->arch.apicv_active)
3626 kvm_x86_ops->sync_pir_to_irr(vcpu);
3627
3628 return kvm_apic_get_state(vcpu, s);
3629 }
3630
3631 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3632 struct kvm_lapic_state *s)
3633 {
3634 int r;
3635
3636 r = kvm_apic_set_state(vcpu, s);
3637 if (r)
3638 return r;
3639 update_cr8_intercept(vcpu);
3640
3641 return 0;
3642 }
3643
3644 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3645 {
3646 return (!lapic_in_kernel(vcpu) ||
3647 kvm_apic_accept_pic_intr(vcpu));
3648 }
3649
3650 /*
3651 * if userspace requested an interrupt window, check that the
3652 * interrupt window is open.
3653 *
3654 * No need to exit to userspace if we already have an interrupt queued.
3655 */
3656 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3657 {
3658 return kvm_arch_interrupt_allowed(vcpu) &&
3659 !kvm_cpu_has_interrupt(vcpu) &&
3660 !kvm_event_needs_reinjection(vcpu) &&
3661 kvm_cpu_accept_dm_intr(vcpu);
3662 }
3663
3664 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3665 struct kvm_interrupt *irq)
3666 {
3667 if (irq->irq >= KVM_NR_INTERRUPTS)
3668 return -EINVAL;
3669
3670 if (!irqchip_in_kernel(vcpu->kvm)) {
3671 kvm_queue_interrupt(vcpu, irq->irq, false);
3672 kvm_make_request(KVM_REQ_EVENT, vcpu);
3673 return 0;
3674 }
3675
3676 /*
3677 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3678 * fail for in-kernel 8259.
3679 */
3680 if (pic_in_kernel(vcpu->kvm))
3681 return -ENXIO;
3682
3683 if (vcpu->arch.pending_external_vector != -1)
3684 return -EEXIST;
3685
3686 vcpu->arch.pending_external_vector = irq->irq;
3687 kvm_make_request(KVM_REQ_EVENT, vcpu);
3688 return 0;
3689 }
3690
3691 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3692 {
3693 kvm_inject_nmi(vcpu);
3694
3695 return 0;
3696 }
3697
3698 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3699 {
3700 kvm_make_request(KVM_REQ_SMI, vcpu);
3701
3702 return 0;
3703 }
3704
3705 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3706 struct kvm_tpr_access_ctl *tac)
3707 {
3708 if (tac->flags)
3709 return -EINVAL;
3710 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3711 return 0;
3712 }
3713
3714 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3715 u64 mcg_cap)
3716 {
3717 int r;
3718 unsigned bank_num = mcg_cap & 0xff, bank;
3719
3720 r = -EINVAL;
3721 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3722 goto out;
3723 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3724 goto out;
3725 r = 0;
3726 vcpu->arch.mcg_cap = mcg_cap;
3727 /* Init IA32_MCG_CTL to all 1s */
3728 if (mcg_cap & MCG_CTL_P)
3729 vcpu->arch.mcg_ctl = ~(u64)0;
3730 /* Init IA32_MCi_CTL to all 1s */
3731 for (bank = 0; bank < bank_num; bank++)
3732 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3733
3734 kvm_x86_ops->setup_mce(vcpu);
3735 out:
3736 return r;
3737 }
3738
3739 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3740 struct kvm_x86_mce *mce)
3741 {
3742 u64 mcg_cap = vcpu->arch.mcg_cap;
3743 unsigned bank_num = mcg_cap & 0xff;
3744 u64 *banks = vcpu->arch.mce_banks;
3745
3746 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3747 return -EINVAL;
3748 /*
3749 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3750 * reporting is disabled
3751 */
3752 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3753 vcpu->arch.mcg_ctl != ~(u64)0)
3754 return 0;
3755 banks += 4 * mce->bank;
3756 /*
3757 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3758 * reporting is disabled for the bank
3759 */
3760 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3761 return 0;
3762 if (mce->status & MCI_STATUS_UC) {
3763 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3764 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3765 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3766 return 0;
3767 }
3768 if (banks[1] & MCI_STATUS_VAL)
3769 mce->status |= MCI_STATUS_OVER;
3770 banks[2] = mce->addr;
3771 banks[3] = mce->misc;
3772 vcpu->arch.mcg_status = mce->mcg_status;
3773 banks[1] = mce->status;
3774 kvm_queue_exception(vcpu, MC_VECTOR);
3775 } else if (!(banks[1] & MCI_STATUS_VAL)
3776 || !(banks[1] & MCI_STATUS_UC)) {
3777 if (banks[1] & MCI_STATUS_VAL)
3778 mce->status |= MCI_STATUS_OVER;
3779 banks[2] = mce->addr;
3780 banks[3] = mce->misc;
3781 banks[1] = mce->status;
3782 } else
3783 banks[1] |= MCI_STATUS_OVER;
3784 return 0;
3785 }
3786
3787 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3788 struct kvm_vcpu_events *events)
3789 {
3790 process_nmi(vcpu);
3791
3792 /*
3793 * In guest mode, payload delivery should be deferred,
3794 * so that the L1 hypervisor can intercept #PF before
3795 * CR2 is modified (or intercept #DB before DR6 is
3796 * modified under nVMX). Unless the per-VM capability,
3797 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3798 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3799 * opportunistically defer the exception payload, deliver it if the
3800 * capability hasn't been requested before processing a
3801 * KVM_GET_VCPU_EVENTS.
3802 */
3803 if (!vcpu->kvm->arch.exception_payload_enabled &&
3804 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3805 kvm_deliver_exception_payload(vcpu);
3806
3807 /*
3808 * The API doesn't provide the instruction length for software
3809 * exceptions, so don't report them. As long as the guest RIP
3810 * isn't advanced, we should expect to encounter the exception
3811 * again.
3812 */
3813 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3814 events->exception.injected = 0;
3815 events->exception.pending = 0;
3816 } else {
3817 events->exception.injected = vcpu->arch.exception.injected;
3818 events->exception.pending = vcpu->arch.exception.pending;
3819 /*
3820 * For ABI compatibility, deliberately conflate
3821 * pending and injected exceptions when
3822 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3823 */
3824 if (!vcpu->kvm->arch.exception_payload_enabled)
3825 events->exception.injected |=
3826 vcpu->arch.exception.pending;
3827 }
3828 events->exception.nr = vcpu->arch.exception.nr;
3829 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3830 events->exception.error_code = vcpu->arch.exception.error_code;
3831 events->exception_has_payload = vcpu->arch.exception.has_payload;
3832 events->exception_payload = vcpu->arch.exception.payload;
3833
3834 events->interrupt.injected =
3835 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3836 events->interrupt.nr = vcpu->arch.interrupt.nr;
3837 events->interrupt.soft = 0;
3838 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3839
3840 events->nmi.injected = vcpu->arch.nmi_injected;
3841 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3842 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3843 events->nmi.pad = 0;
3844
3845 events->sipi_vector = 0; /* never valid when reporting to user space */
3846
3847 events->smi.smm = is_smm(vcpu);
3848 events->smi.pending = vcpu->arch.smi_pending;
3849 events->smi.smm_inside_nmi =
3850 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3851 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3852
3853 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3854 | KVM_VCPUEVENT_VALID_SHADOW
3855 | KVM_VCPUEVENT_VALID_SMM);
3856 if (vcpu->kvm->arch.exception_payload_enabled)
3857 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3858
3859 memset(&events->reserved, 0, sizeof(events->reserved));
3860 }
3861
3862 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3863
3864 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3865 struct kvm_vcpu_events *events)
3866 {
3867 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3868 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3869 | KVM_VCPUEVENT_VALID_SHADOW
3870 | KVM_VCPUEVENT_VALID_SMM
3871 | KVM_VCPUEVENT_VALID_PAYLOAD))
3872 return -EINVAL;
3873
3874 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3875 if (!vcpu->kvm->arch.exception_payload_enabled)
3876 return -EINVAL;
3877 if (events->exception.pending)
3878 events->exception.injected = 0;
3879 else
3880 events->exception_has_payload = 0;
3881 } else {
3882 events->exception.pending = 0;
3883 events->exception_has_payload = 0;
3884 }
3885
3886 if ((events->exception.injected || events->exception.pending) &&
3887 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3888 return -EINVAL;
3889
3890 /* INITs are latched while in SMM */
3891 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3892 (events->smi.smm || events->smi.pending) &&
3893 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3894 return -EINVAL;
3895
3896 process_nmi(vcpu);
3897 vcpu->arch.exception.injected = events->exception.injected;
3898 vcpu->arch.exception.pending = events->exception.pending;
3899 vcpu->arch.exception.nr = events->exception.nr;
3900 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3901 vcpu->arch.exception.error_code = events->exception.error_code;
3902 vcpu->arch.exception.has_payload = events->exception_has_payload;
3903 vcpu->arch.exception.payload = events->exception_payload;
3904
3905 vcpu->arch.interrupt.injected = events->interrupt.injected;
3906 vcpu->arch.interrupt.nr = events->interrupt.nr;
3907 vcpu->arch.interrupt.soft = events->interrupt.soft;
3908 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3909 kvm_x86_ops->set_interrupt_shadow(vcpu,
3910 events->interrupt.shadow);
3911
3912 vcpu->arch.nmi_injected = events->nmi.injected;
3913 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3914 vcpu->arch.nmi_pending = events->nmi.pending;
3915 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3916
3917 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3918 lapic_in_kernel(vcpu))
3919 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3920
3921 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3922 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3923 if (events->smi.smm)
3924 vcpu->arch.hflags |= HF_SMM_MASK;
3925 else
3926 vcpu->arch.hflags &= ~HF_SMM_MASK;
3927 kvm_smm_changed(vcpu);
3928 }
3929
3930 vcpu->arch.smi_pending = events->smi.pending;
3931
3932 if (events->smi.smm) {
3933 if (events->smi.smm_inside_nmi)
3934 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3935 else
3936 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3937 }
3938
3939 if (lapic_in_kernel(vcpu)) {
3940 if (events->smi.latched_init)
3941 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3942 else
3943 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3944 }
3945 }
3946
3947 kvm_make_request(KVM_REQ_EVENT, vcpu);
3948
3949 return 0;
3950 }
3951
3952 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3953 struct kvm_debugregs *dbgregs)
3954 {
3955 unsigned long val;
3956
3957 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3958 kvm_get_dr(vcpu, 6, &val);
3959 dbgregs->dr6 = val;
3960 dbgregs->dr7 = vcpu->arch.dr7;
3961 dbgregs->flags = 0;
3962 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3963 }
3964
3965 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3966 struct kvm_debugregs *dbgregs)
3967 {
3968 if (dbgregs->flags)
3969 return -EINVAL;
3970
3971 if (dbgregs->dr6 & ~0xffffffffull)
3972 return -EINVAL;
3973 if (dbgregs->dr7 & ~0xffffffffull)
3974 return -EINVAL;
3975
3976 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3977 kvm_update_dr0123(vcpu);
3978 vcpu->arch.dr6 = dbgregs->dr6;
3979 kvm_update_dr6(vcpu);
3980 vcpu->arch.dr7 = dbgregs->dr7;
3981 kvm_update_dr7(vcpu);
3982
3983 return 0;
3984 }
3985
3986 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3987
3988 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3989 {
3990 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3991 u64 xstate_bv = xsave->header.xfeatures;
3992 u64 valid;
3993
3994 /*
3995 * Copy legacy XSAVE area, to avoid complications with CPUID
3996 * leaves 0 and 1 in the loop below.
3997 */
3998 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3999
4000 /* Set XSTATE_BV */
4001 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4002 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4003
4004 /*
4005 * Copy each region from the possibly compacted offset to the
4006 * non-compacted offset.
4007 */
4008 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4009 while (valid) {
4010 u64 xfeature_mask = valid & -valid;
4011 int xfeature_nr = fls64(xfeature_mask) - 1;
4012 void *src = get_xsave_addr(xsave, xfeature_nr);
4013
4014 if (src) {
4015 u32 size, offset, ecx, edx;
4016 cpuid_count(XSTATE_CPUID, xfeature_nr,
4017 &size, &offset, &ecx, &edx);
4018 if (xfeature_nr == XFEATURE_PKRU)
4019 memcpy(dest + offset, &vcpu->arch.pkru,
4020 sizeof(vcpu->arch.pkru));
4021 else
4022 memcpy(dest + offset, src, size);
4023
4024 }
4025
4026 valid -= xfeature_mask;
4027 }
4028 }
4029
4030 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4031 {
4032 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4033 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4034 u64 valid;
4035
4036 /*
4037 * Copy legacy XSAVE area, to avoid complications with CPUID
4038 * leaves 0 and 1 in the loop below.
4039 */
4040 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4041
4042 /* Set XSTATE_BV and possibly XCOMP_BV. */
4043 xsave->header.xfeatures = xstate_bv;
4044 if (boot_cpu_has(X86_FEATURE_XSAVES))
4045 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4046
4047 /*
4048 * Copy each region from the non-compacted offset to the
4049 * possibly compacted offset.
4050 */
4051 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4052 while (valid) {
4053 u64 xfeature_mask = valid & -valid;
4054 int xfeature_nr = fls64(xfeature_mask) - 1;
4055 void *dest = get_xsave_addr(xsave, xfeature_nr);
4056
4057 if (dest) {
4058 u32 size, offset, ecx, edx;
4059 cpuid_count(XSTATE_CPUID, xfeature_nr,
4060 &size, &offset, &ecx, &edx);
4061 if (xfeature_nr == XFEATURE_PKRU)
4062 memcpy(&vcpu->arch.pkru, src + offset,
4063 sizeof(vcpu->arch.pkru));
4064 else
4065 memcpy(dest, src + offset, size);
4066 }
4067
4068 valid -= xfeature_mask;
4069 }
4070 }
4071
4072 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4073 struct kvm_xsave *guest_xsave)
4074 {
4075 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4076 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4077 fill_xsave((u8 *) guest_xsave->region, vcpu);
4078 } else {
4079 memcpy(guest_xsave->region,
4080 &vcpu->arch.guest_fpu->state.fxsave,
4081 sizeof(struct fxregs_state));
4082 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4083 XFEATURE_MASK_FPSSE;
4084 }
4085 }
4086
4087 #define XSAVE_MXCSR_OFFSET 24
4088
4089 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4090 struct kvm_xsave *guest_xsave)
4091 {
4092 u64 xstate_bv =
4093 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4094 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4095
4096 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4097 /*
4098 * Here we allow setting states that are not present in
4099 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4100 * with old userspace.
4101 */
4102 if (xstate_bv & ~kvm_supported_xcr0() ||
4103 mxcsr & ~mxcsr_feature_mask)
4104 return -EINVAL;
4105 load_xsave(vcpu, (u8 *)guest_xsave->region);
4106 } else {
4107 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4108 mxcsr & ~mxcsr_feature_mask)
4109 return -EINVAL;
4110 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4111 guest_xsave->region, sizeof(struct fxregs_state));
4112 }
4113 return 0;
4114 }
4115
4116 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4117 struct kvm_xcrs *guest_xcrs)
4118 {
4119 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4120 guest_xcrs->nr_xcrs = 0;
4121 return;
4122 }
4123
4124 guest_xcrs->nr_xcrs = 1;
4125 guest_xcrs->flags = 0;
4126 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4127 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4128 }
4129
4130 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4131 struct kvm_xcrs *guest_xcrs)
4132 {
4133 int i, r = 0;
4134
4135 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4136 return -EINVAL;
4137
4138 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4139 return -EINVAL;
4140
4141 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4142 /* Only support XCR0 currently */
4143 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4144 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4145 guest_xcrs->xcrs[i].value);
4146 break;
4147 }
4148 if (r)
4149 r = -EINVAL;
4150 return r;
4151 }
4152
4153 /*
4154 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4155 * stopped by the hypervisor. This function will be called from the host only.
4156 * EINVAL is returned when the host attempts to set the flag for a guest that
4157 * does not support pv clocks.
4158 */
4159 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4160 {
4161 if (!vcpu->arch.pv_time_enabled)
4162 return -EINVAL;
4163 vcpu->arch.pvclock_set_guest_stopped_request = true;
4164 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4165 return 0;
4166 }
4167
4168 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4169 struct kvm_enable_cap *cap)
4170 {
4171 int r;
4172 uint16_t vmcs_version;
4173 void __user *user_ptr;
4174
4175 if (cap->flags)
4176 return -EINVAL;
4177
4178 switch (cap->cap) {
4179 case KVM_CAP_HYPERV_SYNIC2:
4180 if (cap->args[0])
4181 return -EINVAL;
4182 /* fall through */
4183
4184 case KVM_CAP_HYPERV_SYNIC:
4185 if (!irqchip_in_kernel(vcpu->kvm))
4186 return -EINVAL;
4187 return kvm_hv_activate_synic(vcpu, cap->cap ==
4188 KVM_CAP_HYPERV_SYNIC2);
4189 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4190 if (!kvm_x86_ops->nested_enable_evmcs)
4191 return -ENOTTY;
4192 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4193 if (!r) {
4194 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4195 if (copy_to_user(user_ptr, &vmcs_version,
4196 sizeof(vmcs_version)))
4197 r = -EFAULT;
4198 }
4199 return r;
4200 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4201 if (!kvm_x86_ops->enable_direct_tlbflush)
4202 return -ENOTTY;
4203
4204 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
4205
4206 default:
4207 return -EINVAL;
4208 }
4209 }
4210
4211 long kvm_arch_vcpu_ioctl(struct file *filp,
4212 unsigned int ioctl, unsigned long arg)
4213 {
4214 struct kvm_vcpu *vcpu = filp->private_data;
4215 void __user *argp = (void __user *)arg;
4216 int r;
4217 union {
4218 struct kvm_lapic_state *lapic;
4219 struct kvm_xsave *xsave;
4220 struct kvm_xcrs *xcrs;
4221 void *buffer;
4222 } u;
4223
4224 vcpu_load(vcpu);
4225
4226 u.buffer = NULL;
4227 switch (ioctl) {
4228 case KVM_GET_LAPIC: {
4229 r = -EINVAL;
4230 if (!lapic_in_kernel(vcpu))
4231 goto out;
4232 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4233 GFP_KERNEL_ACCOUNT);
4234
4235 r = -ENOMEM;
4236 if (!u.lapic)
4237 goto out;
4238 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4239 if (r)
4240 goto out;
4241 r = -EFAULT;
4242 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4243 goto out;
4244 r = 0;
4245 break;
4246 }
4247 case KVM_SET_LAPIC: {
4248 r = -EINVAL;
4249 if (!lapic_in_kernel(vcpu))
4250 goto out;
4251 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4252 if (IS_ERR(u.lapic)) {
4253 r = PTR_ERR(u.lapic);
4254 goto out_nofree;
4255 }
4256
4257 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4258 break;
4259 }
4260 case KVM_INTERRUPT: {
4261 struct kvm_interrupt irq;
4262
4263 r = -EFAULT;
4264 if (copy_from_user(&irq, argp, sizeof(irq)))
4265 goto out;
4266 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4267 break;
4268 }
4269 case KVM_NMI: {
4270 r = kvm_vcpu_ioctl_nmi(vcpu);
4271 break;
4272 }
4273 case KVM_SMI: {
4274 r = kvm_vcpu_ioctl_smi(vcpu);
4275 break;
4276 }
4277 case KVM_SET_CPUID: {
4278 struct kvm_cpuid __user *cpuid_arg = argp;
4279 struct kvm_cpuid cpuid;
4280
4281 r = -EFAULT;
4282 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4283 goto out;
4284 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4285 break;
4286 }
4287 case KVM_SET_CPUID2: {
4288 struct kvm_cpuid2 __user *cpuid_arg = argp;
4289 struct kvm_cpuid2 cpuid;
4290
4291 r = -EFAULT;
4292 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4293 goto out;
4294 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4295 cpuid_arg->entries);
4296 break;
4297 }
4298 case KVM_GET_CPUID2: {
4299 struct kvm_cpuid2 __user *cpuid_arg = argp;
4300 struct kvm_cpuid2 cpuid;
4301
4302 r = -EFAULT;
4303 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4304 goto out;
4305 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4306 cpuid_arg->entries);
4307 if (r)
4308 goto out;
4309 r = -EFAULT;
4310 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4311 goto out;
4312 r = 0;
4313 break;
4314 }
4315 case KVM_GET_MSRS: {
4316 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4317 r = msr_io(vcpu, argp, do_get_msr, 1);
4318 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4319 break;
4320 }
4321 case KVM_SET_MSRS: {
4322 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4323 r = msr_io(vcpu, argp, do_set_msr, 0);
4324 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4325 break;
4326 }
4327 case KVM_TPR_ACCESS_REPORTING: {
4328 struct kvm_tpr_access_ctl tac;
4329
4330 r = -EFAULT;
4331 if (copy_from_user(&tac, argp, sizeof(tac)))
4332 goto out;
4333 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4334 if (r)
4335 goto out;
4336 r = -EFAULT;
4337 if (copy_to_user(argp, &tac, sizeof(tac)))
4338 goto out;
4339 r = 0;
4340 break;
4341 };
4342 case KVM_SET_VAPIC_ADDR: {
4343 struct kvm_vapic_addr va;
4344 int idx;
4345
4346 r = -EINVAL;
4347 if (!lapic_in_kernel(vcpu))
4348 goto out;
4349 r = -EFAULT;
4350 if (copy_from_user(&va, argp, sizeof(va)))
4351 goto out;
4352 idx = srcu_read_lock(&vcpu->kvm->srcu);
4353 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4354 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4355 break;
4356 }
4357 case KVM_X86_SETUP_MCE: {
4358 u64 mcg_cap;
4359
4360 r = -EFAULT;
4361 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4362 goto out;
4363 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4364 break;
4365 }
4366 case KVM_X86_SET_MCE: {
4367 struct kvm_x86_mce mce;
4368
4369 r = -EFAULT;
4370 if (copy_from_user(&mce, argp, sizeof(mce)))
4371 goto out;
4372 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4373 break;
4374 }
4375 case KVM_GET_VCPU_EVENTS: {
4376 struct kvm_vcpu_events events;
4377
4378 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4379
4380 r = -EFAULT;
4381 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4382 break;
4383 r = 0;
4384 break;
4385 }
4386 case KVM_SET_VCPU_EVENTS: {
4387 struct kvm_vcpu_events events;
4388
4389 r = -EFAULT;
4390 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4391 break;
4392
4393 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4394 break;
4395 }
4396 case KVM_GET_DEBUGREGS: {
4397 struct kvm_debugregs dbgregs;
4398
4399 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4400
4401 r = -EFAULT;
4402 if (copy_to_user(argp, &dbgregs,
4403 sizeof(struct kvm_debugregs)))
4404 break;
4405 r = 0;
4406 break;
4407 }
4408 case KVM_SET_DEBUGREGS: {
4409 struct kvm_debugregs dbgregs;
4410
4411 r = -EFAULT;
4412 if (copy_from_user(&dbgregs, argp,
4413 sizeof(struct kvm_debugregs)))
4414 break;
4415
4416 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4417 break;
4418 }
4419 case KVM_GET_XSAVE: {
4420 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4421 r = -ENOMEM;
4422 if (!u.xsave)
4423 break;
4424
4425 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4426
4427 r = -EFAULT;
4428 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4429 break;
4430 r = 0;
4431 break;
4432 }
4433 case KVM_SET_XSAVE: {
4434 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4435 if (IS_ERR(u.xsave)) {
4436 r = PTR_ERR(u.xsave);
4437 goto out_nofree;
4438 }
4439
4440 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4441 break;
4442 }
4443 case KVM_GET_XCRS: {
4444 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4445 r = -ENOMEM;
4446 if (!u.xcrs)
4447 break;
4448
4449 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4450
4451 r = -EFAULT;
4452 if (copy_to_user(argp, u.xcrs,
4453 sizeof(struct kvm_xcrs)))
4454 break;
4455 r = 0;
4456 break;
4457 }
4458 case KVM_SET_XCRS: {
4459 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4460 if (IS_ERR(u.xcrs)) {
4461 r = PTR_ERR(u.xcrs);
4462 goto out_nofree;
4463 }
4464
4465 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4466 break;
4467 }
4468 case KVM_SET_TSC_KHZ: {
4469 u32 user_tsc_khz;
4470
4471 r = -EINVAL;
4472 user_tsc_khz = (u32)arg;
4473
4474 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4475 goto out;
4476
4477 if (user_tsc_khz == 0)
4478 user_tsc_khz = tsc_khz;
4479
4480 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4481 r = 0;
4482
4483 goto out;
4484 }
4485 case KVM_GET_TSC_KHZ: {
4486 r = vcpu->arch.virtual_tsc_khz;
4487 goto out;
4488 }
4489 case KVM_KVMCLOCK_CTRL: {
4490 r = kvm_set_guest_paused(vcpu);
4491 goto out;
4492 }
4493 case KVM_ENABLE_CAP: {
4494 struct kvm_enable_cap cap;
4495
4496 r = -EFAULT;
4497 if (copy_from_user(&cap, argp, sizeof(cap)))
4498 goto out;
4499 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4500 break;
4501 }
4502 case KVM_GET_NESTED_STATE: {
4503 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4504 u32 user_data_size;
4505
4506 r = -EINVAL;
4507 if (!kvm_x86_ops->get_nested_state)
4508 break;
4509
4510 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4511 r = -EFAULT;
4512 if (get_user(user_data_size, &user_kvm_nested_state->size))
4513 break;
4514
4515 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4516 user_data_size);
4517 if (r < 0)
4518 break;
4519
4520 if (r > user_data_size) {
4521 if (put_user(r, &user_kvm_nested_state->size))
4522 r = -EFAULT;
4523 else
4524 r = -E2BIG;
4525 break;
4526 }
4527
4528 r = 0;
4529 break;
4530 }
4531 case KVM_SET_NESTED_STATE: {
4532 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4533 struct kvm_nested_state kvm_state;
4534 int idx;
4535
4536 r = -EINVAL;
4537 if (!kvm_x86_ops->set_nested_state)
4538 break;
4539
4540 r = -EFAULT;
4541 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4542 break;
4543
4544 r = -EINVAL;
4545 if (kvm_state.size < sizeof(kvm_state))
4546 break;
4547
4548 if (kvm_state.flags &
4549 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4550 | KVM_STATE_NESTED_EVMCS))
4551 break;
4552
4553 /* nested_run_pending implies guest_mode. */
4554 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4555 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4556 break;
4557
4558 idx = srcu_read_lock(&vcpu->kvm->srcu);
4559 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4561 break;
4562 }
4563 case KVM_GET_SUPPORTED_HV_CPUID: {
4564 struct kvm_cpuid2 __user *cpuid_arg = argp;
4565 struct kvm_cpuid2 cpuid;
4566
4567 r = -EFAULT;
4568 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4569 goto out;
4570
4571 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4572 cpuid_arg->entries);
4573 if (r)
4574 goto out;
4575
4576 r = -EFAULT;
4577 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4578 goto out;
4579 r = 0;
4580 break;
4581 }
4582 default:
4583 r = -EINVAL;
4584 }
4585 out:
4586 kfree(u.buffer);
4587 out_nofree:
4588 vcpu_put(vcpu);
4589 return r;
4590 }
4591
4592 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4593 {
4594 return VM_FAULT_SIGBUS;
4595 }
4596
4597 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4598 {
4599 int ret;
4600
4601 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4602 return -EINVAL;
4603 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4604 return ret;
4605 }
4606
4607 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4608 u64 ident_addr)
4609 {
4610 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4611 }
4612
4613 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4614 unsigned long kvm_nr_mmu_pages)
4615 {
4616 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4617 return -EINVAL;
4618
4619 mutex_lock(&kvm->slots_lock);
4620
4621 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4622 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4623
4624 mutex_unlock(&kvm->slots_lock);
4625 return 0;
4626 }
4627
4628 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4629 {
4630 return kvm->arch.n_max_mmu_pages;
4631 }
4632
4633 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4634 {
4635 struct kvm_pic *pic = kvm->arch.vpic;
4636 int r;
4637
4638 r = 0;
4639 switch (chip->chip_id) {
4640 case KVM_IRQCHIP_PIC_MASTER:
4641 memcpy(&chip->chip.pic, &pic->pics[0],
4642 sizeof(struct kvm_pic_state));
4643 break;
4644 case KVM_IRQCHIP_PIC_SLAVE:
4645 memcpy(&chip->chip.pic, &pic->pics[1],
4646 sizeof(struct kvm_pic_state));
4647 break;
4648 case KVM_IRQCHIP_IOAPIC:
4649 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4650 break;
4651 default:
4652 r = -EINVAL;
4653 break;
4654 }
4655 return r;
4656 }
4657
4658 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4659 {
4660 struct kvm_pic *pic = kvm->arch.vpic;
4661 int r;
4662
4663 r = 0;
4664 switch (chip->chip_id) {
4665 case KVM_IRQCHIP_PIC_MASTER:
4666 spin_lock(&pic->lock);
4667 memcpy(&pic->pics[0], &chip->chip.pic,
4668 sizeof(struct kvm_pic_state));
4669 spin_unlock(&pic->lock);
4670 break;
4671 case KVM_IRQCHIP_PIC_SLAVE:
4672 spin_lock(&pic->lock);
4673 memcpy(&pic->pics[1], &chip->chip.pic,
4674 sizeof(struct kvm_pic_state));
4675 spin_unlock(&pic->lock);
4676 break;
4677 case KVM_IRQCHIP_IOAPIC:
4678 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4679 break;
4680 default:
4681 r = -EINVAL;
4682 break;
4683 }
4684 kvm_pic_update_irq(pic);
4685 return r;
4686 }
4687
4688 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4689 {
4690 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4691
4692 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4693
4694 mutex_lock(&kps->lock);
4695 memcpy(ps, &kps->channels, sizeof(*ps));
4696 mutex_unlock(&kps->lock);
4697 return 0;
4698 }
4699
4700 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4701 {
4702 int i;
4703 struct kvm_pit *pit = kvm->arch.vpit;
4704
4705 mutex_lock(&pit->pit_state.lock);
4706 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4707 for (i = 0; i < 3; i++)
4708 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4709 mutex_unlock(&pit->pit_state.lock);
4710 return 0;
4711 }
4712
4713 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4714 {
4715 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4716 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4717 sizeof(ps->channels));
4718 ps->flags = kvm->arch.vpit->pit_state.flags;
4719 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4720 memset(&ps->reserved, 0, sizeof(ps->reserved));
4721 return 0;
4722 }
4723
4724 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4725 {
4726 int start = 0;
4727 int i;
4728 u32 prev_legacy, cur_legacy;
4729 struct kvm_pit *pit = kvm->arch.vpit;
4730
4731 mutex_lock(&pit->pit_state.lock);
4732 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4733 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4734 if (!prev_legacy && cur_legacy)
4735 start = 1;
4736 memcpy(&pit->pit_state.channels, &ps->channels,
4737 sizeof(pit->pit_state.channels));
4738 pit->pit_state.flags = ps->flags;
4739 for (i = 0; i < 3; i++)
4740 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4741 start && i == 0);
4742 mutex_unlock(&pit->pit_state.lock);
4743 return 0;
4744 }
4745
4746 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4747 struct kvm_reinject_control *control)
4748 {
4749 struct kvm_pit *pit = kvm->arch.vpit;
4750
4751 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4752 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4753 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4754 */
4755 mutex_lock(&pit->pit_state.lock);
4756 kvm_pit_set_reinject(pit, control->pit_reinject);
4757 mutex_unlock(&pit->pit_state.lock);
4758
4759 return 0;
4760 }
4761
4762 /**
4763 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4764 * @kvm: kvm instance
4765 * @log: slot id and address to which we copy the log
4766 *
4767 * Steps 1-4 below provide general overview of dirty page logging. See
4768 * kvm_get_dirty_log_protect() function description for additional details.
4769 *
4770 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4771 * always flush the TLB (step 4) even if previous step failed and the dirty
4772 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4773 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4774 * writes will be marked dirty for next log read.
4775 *
4776 * 1. Take a snapshot of the bit and clear it if needed.
4777 * 2. Write protect the corresponding page.
4778 * 3. Copy the snapshot to the userspace.
4779 * 4. Flush TLB's if needed.
4780 */
4781 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4782 {
4783 bool flush = false;
4784 int r;
4785
4786 mutex_lock(&kvm->slots_lock);
4787
4788 /*
4789 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4790 */
4791 if (kvm_x86_ops->flush_log_dirty)
4792 kvm_x86_ops->flush_log_dirty(kvm);
4793
4794 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4795
4796 /*
4797 * All the TLBs can be flushed out of mmu lock, see the comments in
4798 * kvm_mmu_slot_remove_write_access().
4799 */
4800 lockdep_assert_held(&kvm->slots_lock);
4801 if (flush)
4802 kvm_flush_remote_tlbs(kvm);
4803
4804 mutex_unlock(&kvm->slots_lock);
4805 return r;
4806 }
4807
4808 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4809 {
4810 bool flush = false;
4811 int r;
4812
4813 mutex_lock(&kvm->slots_lock);
4814
4815 /*
4816 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4817 */
4818 if (kvm_x86_ops->flush_log_dirty)
4819 kvm_x86_ops->flush_log_dirty(kvm);
4820
4821 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4822
4823 /*
4824 * All the TLBs can be flushed out of mmu lock, see the comments in
4825 * kvm_mmu_slot_remove_write_access().
4826 */
4827 lockdep_assert_held(&kvm->slots_lock);
4828 if (flush)
4829 kvm_flush_remote_tlbs(kvm);
4830
4831 mutex_unlock(&kvm->slots_lock);
4832 return r;
4833 }
4834
4835 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4836 bool line_status)
4837 {
4838 if (!irqchip_in_kernel(kvm))
4839 return -ENXIO;
4840
4841 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4842 irq_event->irq, irq_event->level,
4843 line_status);
4844 return 0;
4845 }
4846
4847 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4848 struct kvm_enable_cap *cap)
4849 {
4850 int r;
4851
4852 if (cap->flags)
4853 return -EINVAL;
4854
4855 switch (cap->cap) {
4856 case KVM_CAP_DISABLE_QUIRKS:
4857 kvm->arch.disabled_quirks = cap->args[0];
4858 r = 0;
4859 break;
4860 case KVM_CAP_SPLIT_IRQCHIP: {
4861 mutex_lock(&kvm->lock);
4862 r = -EINVAL;
4863 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4864 goto split_irqchip_unlock;
4865 r = -EEXIST;
4866 if (irqchip_in_kernel(kvm))
4867 goto split_irqchip_unlock;
4868 if (kvm->created_vcpus)
4869 goto split_irqchip_unlock;
4870 r = kvm_setup_empty_irq_routing(kvm);
4871 if (r)
4872 goto split_irqchip_unlock;
4873 /* Pairs with irqchip_in_kernel. */
4874 smp_wmb();
4875 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4876 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4877 r = 0;
4878 split_irqchip_unlock:
4879 mutex_unlock(&kvm->lock);
4880 break;
4881 }
4882 case KVM_CAP_X2APIC_API:
4883 r = -EINVAL;
4884 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4885 break;
4886
4887 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4888 kvm->arch.x2apic_format = true;
4889 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4890 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4891
4892 r = 0;
4893 break;
4894 case KVM_CAP_X86_DISABLE_EXITS:
4895 r = -EINVAL;
4896 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4897 break;
4898
4899 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4900 kvm_can_mwait_in_guest())
4901 kvm->arch.mwait_in_guest = true;
4902 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4903 kvm->arch.hlt_in_guest = true;
4904 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4905 kvm->arch.pause_in_guest = true;
4906 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4907 kvm->arch.cstate_in_guest = true;
4908 r = 0;
4909 break;
4910 case KVM_CAP_MSR_PLATFORM_INFO:
4911 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4912 r = 0;
4913 break;
4914 case KVM_CAP_EXCEPTION_PAYLOAD:
4915 kvm->arch.exception_payload_enabled = cap->args[0];
4916 r = 0;
4917 break;
4918 default:
4919 r = -EINVAL;
4920 break;
4921 }
4922 return r;
4923 }
4924
4925 long kvm_arch_vm_ioctl(struct file *filp,
4926 unsigned int ioctl, unsigned long arg)
4927 {
4928 struct kvm *kvm = filp->private_data;
4929 void __user *argp = (void __user *)arg;
4930 int r = -ENOTTY;
4931 /*
4932 * This union makes it completely explicit to gcc-3.x
4933 * that these two variables' stack usage should be
4934 * combined, not added together.
4935 */
4936 union {
4937 struct kvm_pit_state ps;
4938 struct kvm_pit_state2 ps2;
4939 struct kvm_pit_config pit_config;
4940 } u;
4941
4942 switch (ioctl) {
4943 case KVM_SET_TSS_ADDR:
4944 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4945 break;
4946 case KVM_SET_IDENTITY_MAP_ADDR: {
4947 u64 ident_addr;
4948
4949 mutex_lock(&kvm->lock);
4950 r = -EINVAL;
4951 if (kvm->created_vcpus)
4952 goto set_identity_unlock;
4953 r = -EFAULT;
4954 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4955 goto set_identity_unlock;
4956 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4957 set_identity_unlock:
4958 mutex_unlock(&kvm->lock);
4959 break;
4960 }
4961 case KVM_SET_NR_MMU_PAGES:
4962 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4963 break;
4964 case KVM_GET_NR_MMU_PAGES:
4965 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4966 break;
4967 case KVM_CREATE_IRQCHIP: {
4968 mutex_lock(&kvm->lock);
4969
4970 r = -EEXIST;
4971 if (irqchip_in_kernel(kvm))
4972 goto create_irqchip_unlock;
4973
4974 r = -EINVAL;
4975 if (kvm->created_vcpus)
4976 goto create_irqchip_unlock;
4977
4978 r = kvm_pic_init(kvm);
4979 if (r)
4980 goto create_irqchip_unlock;
4981
4982 r = kvm_ioapic_init(kvm);
4983 if (r) {
4984 kvm_pic_destroy(kvm);
4985 goto create_irqchip_unlock;
4986 }
4987
4988 r = kvm_setup_default_irq_routing(kvm);
4989 if (r) {
4990 kvm_ioapic_destroy(kvm);
4991 kvm_pic_destroy(kvm);
4992 goto create_irqchip_unlock;
4993 }
4994 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4995 smp_wmb();
4996 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4997 create_irqchip_unlock:
4998 mutex_unlock(&kvm->lock);
4999 break;
5000 }
5001 case KVM_CREATE_PIT:
5002 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5003 goto create_pit;
5004 case KVM_CREATE_PIT2:
5005 r = -EFAULT;
5006 if (copy_from_user(&u.pit_config, argp,
5007 sizeof(struct kvm_pit_config)))
5008 goto out;
5009 create_pit:
5010 mutex_lock(&kvm->lock);
5011 r = -EEXIST;
5012 if (kvm->arch.vpit)
5013 goto create_pit_unlock;
5014 r = -ENOMEM;
5015 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5016 if (kvm->arch.vpit)
5017 r = 0;
5018 create_pit_unlock:
5019 mutex_unlock(&kvm->lock);
5020 break;
5021 case KVM_GET_IRQCHIP: {
5022 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5023 struct kvm_irqchip *chip;
5024
5025 chip = memdup_user(argp, sizeof(*chip));
5026 if (IS_ERR(chip)) {
5027 r = PTR_ERR(chip);
5028 goto out;
5029 }
5030
5031 r = -ENXIO;
5032 if (!irqchip_kernel(kvm))
5033 goto get_irqchip_out;
5034 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5035 if (r)
5036 goto get_irqchip_out;
5037 r = -EFAULT;
5038 if (copy_to_user(argp, chip, sizeof(*chip)))
5039 goto get_irqchip_out;
5040 r = 0;
5041 get_irqchip_out:
5042 kfree(chip);
5043 break;
5044 }
5045 case KVM_SET_IRQCHIP: {
5046 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5047 struct kvm_irqchip *chip;
5048
5049 chip = memdup_user(argp, sizeof(*chip));
5050 if (IS_ERR(chip)) {
5051 r = PTR_ERR(chip);
5052 goto out;
5053 }
5054
5055 r = -ENXIO;
5056 if (!irqchip_kernel(kvm))
5057 goto set_irqchip_out;
5058 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5059 set_irqchip_out:
5060 kfree(chip);
5061 break;
5062 }
5063 case KVM_GET_PIT: {
5064 r = -EFAULT;
5065 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5066 goto out;
5067 r = -ENXIO;
5068 if (!kvm->arch.vpit)
5069 goto out;
5070 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5071 if (r)
5072 goto out;
5073 r = -EFAULT;
5074 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5075 goto out;
5076 r = 0;
5077 break;
5078 }
5079 case KVM_SET_PIT: {
5080 r = -EFAULT;
5081 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5082 goto out;
5083 r = -ENXIO;
5084 if (!kvm->arch.vpit)
5085 goto out;
5086 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5087 break;
5088 }
5089 case KVM_GET_PIT2: {
5090 r = -ENXIO;
5091 if (!kvm->arch.vpit)
5092 goto out;
5093 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5094 if (r)
5095 goto out;
5096 r = -EFAULT;
5097 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5098 goto out;
5099 r = 0;
5100 break;
5101 }
5102 case KVM_SET_PIT2: {
5103 r = -EFAULT;
5104 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5105 goto out;
5106 r = -ENXIO;
5107 if (!kvm->arch.vpit)
5108 goto out;
5109 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5110 break;
5111 }
5112 case KVM_REINJECT_CONTROL: {
5113 struct kvm_reinject_control control;
5114 r = -EFAULT;
5115 if (copy_from_user(&control, argp, sizeof(control)))
5116 goto out;
5117 r = -ENXIO;
5118 if (!kvm->arch.vpit)
5119 goto out;
5120 r = kvm_vm_ioctl_reinject(kvm, &control);
5121 break;
5122 }
5123 case KVM_SET_BOOT_CPU_ID:
5124 r = 0;
5125 mutex_lock(&kvm->lock);
5126 if (kvm->created_vcpus)
5127 r = -EBUSY;
5128 else
5129 kvm->arch.bsp_vcpu_id = arg;
5130 mutex_unlock(&kvm->lock);
5131 break;
5132 case KVM_XEN_HVM_CONFIG: {
5133 struct kvm_xen_hvm_config xhc;
5134 r = -EFAULT;
5135 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5136 goto out;
5137 r = -EINVAL;
5138 if (xhc.flags)
5139 goto out;
5140 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5141 r = 0;
5142 break;
5143 }
5144 case KVM_SET_CLOCK: {
5145 struct kvm_clock_data user_ns;
5146 u64 now_ns;
5147
5148 r = -EFAULT;
5149 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5150 goto out;
5151
5152 r = -EINVAL;
5153 if (user_ns.flags)
5154 goto out;
5155
5156 r = 0;
5157 /*
5158 * TODO: userspace has to take care of races with VCPU_RUN, so
5159 * kvm_gen_update_masterclock() can be cut down to locked
5160 * pvclock_update_vm_gtod_copy().
5161 */
5162 kvm_gen_update_masterclock(kvm);
5163 now_ns = get_kvmclock_ns(kvm);
5164 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5165 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5166 break;
5167 }
5168 case KVM_GET_CLOCK: {
5169 struct kvm_clock_data user_ns;
5170 u64 now_ns;
5171
5172 now_ns = get_kvmclock_ns(kvm);
5173 user_ns.clock = now_ns;
5174 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5175 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5176
5177 r = -EFAULT;
5178 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5179 goto out;
5180 r = 0;
5181 break;
5182 }
5183 case KVM_MEMORY_ENCRYPT_OP: {
5184 r = -ENOTTY;
5185 if (kvm_x86_ops->mem_enc_op)
5186 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5187 break;
5188 }
5189 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5190 struct kvm_enc_region region;
5191
5192 r = -EFAULT;
5193 if (copy_from_user(&region, argp, sizeof(region)))
5194 goto out;
5195
5196 r = -ENOTTY;
5197 if (kvm_x86_ops->mem_enc_reg_region)
5198 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5199 break;
5200 }
5201 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5202 struct kvm_enc_region region;
5203
5204 r = -EFAULT;
5205 if (copy_from_user(&region, argp, sizeof(region)))
5206 goto out;
5207
5208 r = -ENOTTY;
5209 if (kvm_x86_ops->mem_enc_unreg_region)
5210 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5211 break;
5212 }
5213 case KVM_HYPERV_EVENTFD: {
5214 struct kvm_hyperv_eventfd hvevfd;
5215
5216 r = -EFAULT;
5217 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5218 goto out;
5219 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5220 break;
5221 }
5222 case KVM_SET_PMU_EVENT_FILTER:
5223 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5224 break;
5225 default:
5226 r = -ENOTTY;
5227 }
5228 out:
5229 return r;
5230 }
5231
5232 static void kvm_init_msr_list(void)
5233 {
5234 struct x86_pmu_capability x86_pmu;
5235 u32 dummy[2];
5236 unsigned i;
5237
5238 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5239 "Please update the fixed PMCs in msrs_to_saved_all[]");
5240
5241 perf_get_x86_pmu_capability(&x86_pmu);
5242
5243 num_msrs_to_save = 0;
5244 num_emulated_msrs = 0;
5245 num_msr_based_features = 0;
5246
5247 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5248 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5249 continue;
5250
5251 /*
5252 * Even MSRs that are valid in the host may not be exposed
5253 * to the guests in some cases.
5254 */
5255 switch (msrs_to_save_all[i]) {
5256 case MSR_IA32_BNDCFGS:
5257 if (!kvm_mpx_supported())
5258 continue;
5259 break;
5260 case MSR_TSC_AUX:
5261 if (!kvm_x86_ops->rdtscp_supported())
5262 continue;
5263 break;
5264 case MSR_IA32_RTIT_CTL:
5265 case MSR_IA32_RTIT_STATUS:
5266 if (!kvm_x86_ops->pt_supported())
5267 continue;
5268 break;
5269 case MSR_IA32_RTIT_CR3_MATCH:
5270 if (!kvm_x86_ops->pt_supported() ||
5271 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5272 continue;
5273 break;
5274 case MSR_IA32_RTIT_OUTPUT_BASE:
5275 case MSR_IA32_RTIT_OUTPUT_MASK:
5276 if (!kvm_x86_ops->pt_supported() ||
5277 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5278 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5279 continue;
5280 break;
5281 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5282 if (!kvm_x86_ops->pt_supported() ||
5283 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5284 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5285 continue;
5286 break;
5287 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5288 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5289 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5290 continue;
5291 break;
5292 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5293 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5294 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5295 continue;
5296 }
5297 default:
5298 break;
5299 }
5300
5301 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5302 }
5303
5304 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5305 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs_all[i]))
5306 continue;
5307
5308 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5309 }
5310
5311 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5312 struct kvm_msr_entry msr;
5313
5314 msr.index = msr_based_features_all[i];
5315 if (kvm_get_msr_feature(&msr))
5316 continue;
5317
5318 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5319 }
5320 }
5321
5322 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5323 const void *v)
5324 {
5325 int handled = 0;
5326 int n;
5327
5328 do {
5329 n = min(len, 8);
5330 if (!(lapic_in_kernel(vcpu) &&
5331 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5332 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5333 break;
5334 handled += n;
5335 addr += n;
5336 len -= n;
5337 v += n;
5338 } while (len);
5339
5340 return handled;
5341 }
5342
5343 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5344 {
5345 int handled = 0;
5346 int n;
5347
5348 do {
5349 n = min(len, 8);
5350 if (!(lapic_in_kernel(vcpu) &&
5351 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5352 addr, n, v))
5353 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5354 break;
5355 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5356 handled += n;
5357 addr += n;
5358 len -= n;
5359 v += n;
5360 } while (len);
5361
5362 return handled;
5363 }
5364
5365 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5366 struct kvm_segment *var, int seg)
5367 {
5368 kvm_x86_ops->set_segment(vcpu, var, seg);
5369 }
5370
5371 void kvm_get_segment(struct kvm_vcpu *vcpu,
5372 struct kvm_segment *var, int seg)
5373 {
5374 kvm_x86_ops->get_segment(vcpu, var, seg);
5375 }
5376
5377 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5378 struct x86_exception *exception)
5379 {
5380 gpa_t t_gpa;
5381
5382 BUG_ON(!mmu_is_nested(vcpu));
5383
5384 /* NPT walks are always user-walks */
5385 access |= PFERR_USER_MASK;
5386 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5387
5388 return t_gpa;
5389 }
5390
5391 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5392 struct x86_exception *exception)
5393 {
5394 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5395 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5396 }
5397
5398 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5399 struct x86_exception *exception)
5400 {
5401 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5402 access |= PFERR_FETCH_MASK;
5403 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5404 }
5405
5406 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5407 struct x86_exception *exception)
5408 {
5409 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5410 access |= PFERR_WRITE_MASK;
5411 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5412 }
5413
5414 /* uses this to access any guest's mapped memory without checking CPL */
5415 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5416 struct x86_exception *exception)
5417 {
5418 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5419 }
5420
5421 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5422 struct kvm_vcpu *vcpu, u32 access,
5423 struct x86_exception *exception)
5424 {
5425 void *data = val;
5426 int r = X86EMUL_CONTINUE;
5427
5428 while (bytes) {
5429 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5430 exception);
5431 unsigned offset = addr & (PAGE_SIZE-1);
5432 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5433 int ret;
5434
5435 if (gpa == UNMAPPED_GVA)
5436 return X86EMUL_PROPAGATE_FAULT;
5437 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5438 offset, toread);
5439 if (ret < 0) {
5440 r = X86EMUL_IO_NEEDED;
5441 goto out;
5442 }
5443
5444 bytes -= toread;
5445 data += toread;
5446 addr += toread;
5447 }
5448 out:
5449 return r;
5450 }
5451
5452 /* used for instruction fetching */
5453 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5454 gva_t addr, void *val, unsigned int bytes,
5455 struct x86_exception *exception)
5456 {
5457 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5458 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5459 unsigned offset;
5460 int ret;
5461
5462 /* Inline kvm_read_guest_virt_helper for speed. */
5463 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5464 exception);
5465 if (unlikely(gpa == UNMAPPED_GVA))
5466 return X86EMUL_PROPAGATE_FAULT;
5467
5468 offset = addr & (PAGE_SIZE-1);
5469 if (WARN_ON(offset + bytes > PAGE_SIZE))
5470 bytes = (unsigned)PAGE_SIZE - offset;
5471 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5472 offset, bytes);
5473 if (unlikely(ret < 0))
5474 return X86EMUL_IO_NEEDED;
5475
5476 return X86EMUL_CONTINUE;
5477 }
5478
5479 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5480 gva_t addr, void *val, unsigned int bytes,
5481 struct x86_exception *exception)
5482 {
5483 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5484
5485 /*
5486 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5487 * is returned, but our callers are not ready for that and they blindly
5488 * call kvm_inject_page_fault. Ensure that they at least do not leak
5489 * uninitialized kernel stack memory into cr2 and error code.
5490 */
5491 memset(exception, 0, sizeof(*exception));
5492 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5493 exception);
5494 }
5495 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5496
5497 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5498 gva_t addr, void *val, unsigned int bytes,
5499 struct x86_exception *exception, bool system)
5500 {
5501 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5502 u32 access = 0;
5503
5504 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5505 access |= PFERR_USER_MASK;
5506
5507 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5508 }
5509
5510 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5511 unsigned long addr, void *val, unsigned int bytes)
5512 {
5513 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5514 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5515
5516 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5517 }
5518
5519 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5520 struct kvm_vcpu *vcpu, u32 access,
5521 struct x86_exception *exception)
5522 {
5523 void *data = val;
5524 int r = X86EMUL_CONTINUE;
5525
5526 while (bytes) {
5527 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5528 access,
5529 exception);
5530 unsigned offset = addr & (PAGE_SIZE-1);
5531 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5532 int ret;
5533
5534 if (gpa == UNMAPPED_GVA)
5535 return X86EMUL_PROPAGATE_FAULT;
5536 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5537 if (ret < 0) {
5538 r = X86EMUL_IO_NEEDED;
5539 goto out;
5540 }
5541
5542 bytes -= towrite;
5543 data += towrite;
5544 addr += towrite;
5545 }
5546 out:
5547 return r;
5548 }
5549
5550 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5551 unsigned int bytes, struct x86_exception *exception,
5552 bool system)
5553 {
5554 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5555 u32 access = PFERR_WRITE_MASK;
5556
5557 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5558 access |= PFERR_USER_MASK;
5559
5560 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5561 access, exception);
5562 }
5563
5564 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5565 unsigned int bytes, struct x86_exception *exception)
5566 {
5567 /* kvm_write_guest_virt_system can pull in tons of pages. */
5568 vcpu->arch.l1tf_flush_l1d = true;
5569
5570 /*
5571 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5572 * is returned, but our callers are not ready for that and they blindly
5573 * call kvm_inject_page_fault. Ensure that they at least do not leak
5574 * uninitialized kernel stack memory into cr2 and error code.
5575 */
5576 memset(exception, 0, sizeof(*exception));
5577 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5578 PFERR_WRITE_MASK, exception);
5579 }
5580 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5581
5582 int handle_ud(struct kvm_vcpu *vcpu)
5583 {
5584 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5585 int emul_type = EMULTYPE_TRAP_UD;
5586 char sig[5]; /* ud2; .ascii "kvm" */
5587 struct x86_exception e;
5588
5589 if (force_emulation_prefix &&
5590 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5591 sig, sizeof(sig), &e) == 0 &&
5592 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5593 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5594 emul_type = EMULTYPE_TRAP_UD_FORCED;
5595 }
5596
5597 return kvm_emulate_instruction(vcpu, emul_type);
5598 }
5599 EXPORT_SYMBOL_GPL(handle_ud);
5600
5601 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5602 gpa_t gpa, bool write)
5603 {
5604 /* For APIC access vmexit */
5605 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5606 return 1;
5607
5608 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5609 trace_vcpu_match_mmio(gva, gpa, write, true);
5610 return 1;
5611 }
5612
5613 return 0;
5614 }
5615
5616 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5617 gpa_t *gpa, struct x86_exception *exception,
5618 bool write)
5619 {
5620 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5621 | (write ? PFERR_WRITE_MASK : 0);
5622
5623 /*
5624 * currently PKRU is only applied to ept enabled guest so
5625 * there is no pkey in EPT page table for L1 guest or EPT
5626 * shadow page table for L2 guest.
5627 */
5628 if (vcpu_match_mmio_gva(vcpu, gva)
5629 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5630 vcpu->arch.mmio_access, 0, access)) {
5631 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5632 (gva & (PAGE_SIZE - 1));
5633 trace_vcpu_match_mmio(gva, *gpa, write, false);
5634 return 1;
5635 }
5636
5637 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5638
5639 if (*gpa == UNMAPPED_GVA)
5640 return -1;
5641
5642 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5643 }
5644
5645 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5646 const void *val, int bytes)
5647 {
5648 int ret;
5649
5650 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5651 if (ret < 0)
5652 return 0;
5653 kvm_page_track_write(vcpu, gpa, val, bytes);
5654 return 1;
5655 }
5656
5657 struct read_write_emulator_ops {
5658 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5659 int bytes);
5660 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5661 void *val, int bytes);
5662 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5663 int bytes, void *val);
5664 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5665 void *val, int bytes);
5666 bool write;
5667 };
5668
5669 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5670 {
5671 if (vcpu->mmio_read_completed) {
5672 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5673 vcpu->mmio_fragments[0].gpa, val);
5674 vcpu->mmio_read_completed = 0;
5675 return 1;
5676 }
5677
5678 return 0;
5679 }
5680
5681 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5682 void *val, int bytes)
5683 {
5684 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5685 }
5686
5687 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5688 void *val, int bytes)
5689 {
5690 return emulator_write_phys(vcpu, gpa, val, bytes);
5691 }
5692
5693 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5694 {
5695 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5696 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5697 }
5698
5699 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5700 void *val, int bytes)
5701 {
5702 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5703 return X86EMUL_IO_NEEDED;
5704 }
5705
5706 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5707 void *val, int bytes)
5708 {
5709 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5710
5711 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5712 return X86EMUL_CONTINUE;
5713 }
5714
5715 static const struct read_write_emulator_ops read_emultor = {
5716 .read_write_prepare = read_prepare,
5717 .read_write_emulate = read_emulate,
5718 .read_write_mmio = vcpu_mmio_read,
5719 .read_write_exit_mmio = read_exit_mmio,
5720 };
5721
5722 static const struct read_write_emulator_ops write_emultor = {
5723 .read_write_emulate = write_emulate,
5724 .read_write_mmio = write_mmio,
5725 .read_write_exit_mmio = write_exit_mmio,
5726 .write = true,
5727 };
5728
5729 static int emulator_read_write_onepage(unsigned long addr, void *val,
5730 unsigned int bytes,
5731 struct x86_exception *exception,
5732 struct kvm_vcpu *vcpu,
5733 const struct read_write_emulator_ops *ops)
5734 {
5735 gpa_t gpa;
5736 int handled, ret;
5737 bool write = ops->write;
5738 struct kvm_mmio_fragment *frag;
5739 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5740
5741 /*
5742 * If the exit was due to a NPF we may already have a GPA.
5743 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5744 * Note, this cannot be used on string operations since string
5745 * operation using rep will only have the initial GPA from the NPF
5746 * occurred.
5747 */
5748 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5749 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5750 gpa = ctxt->gpa_val;
5751 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5752 } else {
5753 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5754 if (ret < 0)
5755 return X86EMUL_PROPAGATE_FAULT;
5756 }
5757
5758 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5759 return X86EMUL_CONTINUE;
5760
5761 /*
5762 * Is this MMIO handled locally?
5763 */
5764 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5765 if (handled == bytes)
5766 return X86EMUL_CONTINUE;
5767
5768 gpa += handled;
5769 bytes -= handled;
5770 val += handled;
5771
5772 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5773 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5774 frag->gpa = gpa;
5775 frag->data = val;
5776 frag->len = bytes;
5777 return X86EMUL_CONTINUE;
5778 }
5779
5780 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5781 unsigned long addr,
5782 void *val, unsigned int bytes,
5783 struct x86_exception *exception,
5784 const struct read_write_emulator_ops *ops)
5785 {
5786 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5787 gpa_t gpa;
5788 int rc;
5789
5790 if (ops->read_write_prepare &&
5791 ops->read_write_prepare(vcpu, val, bytes))
5792 return X86EMUL_CONTINUE;
5793
5794 vcpu->mmio_nr_fragments = 0;
5795
5796 /* Crossing a page boundary? */
5797 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5798 int now;
5799
5800 now = -addr & ~PAGE_MASK;
5801 rc = emulator_read_write_onepage(addr, val, now, exception,
5802 vcpu, ops);
5803
5804 if (rc != X86EMUL_CONTINUE)
5805 return rc;
5806 addr += now;
5807 if (ctxt->mode != X86EMUL_MODE_PROT64)
5808 addr = (u32)addr;
5809 val += now;
5810 bytes -= now;
5811 }
5812
5813 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5814 vcpu, ops);
5815 if (rc != X86EMUL_CONTINUE)
5816 return rc;
5817
5818 if (!vcpu->mmio_nr_fragments)
5819 return rc;
5820
5821 gpa = vcpu->mmio_fragments[0].gpa;
5822
5823 vcpu->mmio_needed = 1;
5824 vcpu->mmio_cur_fragment = 0;
5825
5826 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5827 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5828 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5829 vcpu->run->mmio.phys_addr = gpa;
5830
5831 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5832 }
5833
5834 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5835 unsigned long addr,
5836 void *val,
5837 unsigned int bytes,
5838 struct x86_exception *exception)
5839 {
5840 return emulator_read_write(ctxt, addr, val, bytes,
5841 exception, &read_emultor);
5842 }
5843
5844 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5845 unsigned long addr,
5846 const void *val,
5847 unsigned int bytes,
5848 struct x86_exception *exception)
5849 {
5850 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5851 exception, &write_emultor);
5852 }
5853
5854 #define CMPXCHG_TYPE(t, ptr, old, new) \
5855 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5856
5857 #ifdef CONFIG_X86_64
5858 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5859 #else
5860 # define CMPXCHG64(ptr, old, new) \
5861 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5862 #endif
5863
5864 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5865 unsigned long addr,
5866 const void *old,
5867 const void *new,
5868 unsigned int bytes,
5869 struct x86_exception *exception)
5870 {
5871 struct kvm_host_map map;
5872 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5873 gpa_t gpa;
5874 char *kaddr;
5875 bool exchanged;
5876
5877 /* guests cmpxchg8b have to be emulated atomically */
5878 if (bytes > 8 || (bytes & (bytes - 1)))
5879 goto emul_write;
5880
5881 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5882
5883 if (gpa == UNMAPPED_GVA ||
5884 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5885 goto emul_write;
5886
5887 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5888 goto emul_write;
5889
5890 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5891 goto emul_write;
5892
5893 kaddr = map.hva + offset_in_page(gpa);
5894
5895 switch (bytes) {
5896 case 1:
5897 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5898 break;
5899 case 2:
5900 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5901 break;
5902 case 4:
5903 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5904 break;
5905 case 8:
5906 exchanged = CMPXCHG64(kaddr, old, new);
5907 break;
5908 default:
5909 BUG();
5910 }
5911
5912 kvm_vcpu_unmap(vcpu, &map, true);
5913
5914 if (!exchanged)
5915 return X86EMUL_CMPXCHG_FAILED;
5916
5917 kvm_page_track_write(vcpu, gpa, new, bytes);
5918
5919 return X86EMUL_CONTINUE;
5920
5921 emul_write:
5922 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5923
5924 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5925 }
5926
5927 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5928 {
5929 int r = 0, i;
5930
5931 for (i = 0; i < vcpu->arch.pio.count; i++) {
5932 if (vcpu->arch.pio.in)
5933 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5934 vcpu->arch.pio.size, pd);
5935 else
5936 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5937 vcpu->arch.pio.port, vcpu->arch.pio.size,
5938 pd);
5939 if (r)
5940 break;
5941 pd += vcpu->arch.pio.size;
5942 }
5943 return r;
5944 }
5945
5946 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5947 unsigned short port, void *val,
5948 unsigned int count, bool in)
5949 {
5950 vcpu->arch.pio.port = port;
5951 vcpu->arch.pio.in = in;
5952 vcpu->arch.pio.count = count;
5953 vcpu->arch.pio.size = size;
5954
5955 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5956 vcpu->arch.pio.count = 0;
5957 return 1;
5958 }
5959
5960 vcpu->run->exit_reason = KVM_EXIT_IO;
5961 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5962 vcpu->run->io.size = size;
5963 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5964 vcpu->run->io.count = count;
5965 vcpu->run->io.port = port;
5966
5967 return 0;
5968 }
5969
5970 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5971 int size, unsigned short port, void *val,
5972 unsigned int count)
5973 {
5974 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5975 int ret;
5976
5977 if (vcpu->arch.pio.count)
5978 goto data_avail;
5979
5980 memset(vcpu->arch.pio_data, 0, size * count);
5981
5982 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5983 if (ret) {
5984 data_avail:
5985 memcpy(val, vcpu->arch.pio_data, size * count);
5986 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5987 vcpu->arch.pio.count = 0;
5988 return 1;
5989 }
5990
5991 return 0;
5992 }
5993
5994 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5995 int size, unsigned short port,
5996 const void *val, unsigned int count)
5997 {
5998 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5999
6000 memcpy(vcpu->arch.pio_data, val, size * count);
6001 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6002 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6003 }
6004
6005 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6006 {
6007 return kvm_x86_ops->get_segment_base(vcpu, seg);
6008 }
6009
6010 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6011 {
6012 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6013 }
6014
6015 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6016 {
6017 if (!need_emulate_wbinvd(vcpu))
6018 return X86EMUL_CONTINUE;
6019
6020 if (kvm_x86_ops->has_wbinvd_exit()) {
6021 int cpu = get_cpu();
6022
6023 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6024 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6025 wbinvd_ipi, NULL, 1);
6026 put_cpu();
6027 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6028 } else
6029 wbinvd();
6030 return X86EMUL_CONTINUE;
6031 }
6032
6033 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6034 {
6035 kvm_emulate_wbinvd_noskip(vcpu);
6036 return kvm_skip_emulated_instruction(vcpu);
6037 }
6038 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6039
6040
6041
6042 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6043 {
6044 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6045 }
6046
6047 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6048 unsigned long *dest)
6049 {
6050 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6051 }
6052
6053 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6054 unsigned long value)
6055 {
6056
6057 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6058 }
6059
6060 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6061 {
6062 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6063 }
6064
6065 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6066 {
6067 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6068 unsigned long value;
6069
6070 switch (cr) {
6071 case 0:
6072 value = kvm_read_cr0(vcpu);
6073 break;
6074 case 2:
6075 value = vcpu->arch.cr2;
6076 break;
6077 case 3:
6078 value = kvm_read_cr3(vcpu);
6079 break;
6080 case 4:
6081 value = kvm_read_cr4(vcpu);
6082 break;
6083 case 8:
6084 value = kvm_get_cr8(vcpu);
6085 break;
6086 default:
6087 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6088 return 0;
6089 }
6090
6091 return value;
6092 }
6093
6094 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6095 {
6096 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6097 int res = 0;
6098
6099 switch (cr) {
6100 case 0:
6101 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6102 break;
6103 case 2:
6104 vcpu->arch.cr2 = val;
6105 break;
6106 case 3:
6107 res = kvm_set_cr3(vcpu, val);
6108 break;
6109 case 4:
6110 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6111 break;
6112 case 8:
6113 res = kvm_set_cr8(vcpu, val);
6114 break;
6115 default:
6116 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6117 res = -1;
6118 }
6119
6120 return res;
6121 }
6122
6123 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6124 {
6125 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
6126 }
6127
6128 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6129 {
6130 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
6131 }
6132
6133 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6134 {
6135 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
6136 }
6137
6138 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6139 {
6140 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6141 }
6142
6143 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6144 {
6145 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6146 }
6147
6148 static unsigned long emulator_get_cached_segment_base(
6149 struct x86_emulate_ctxt *ctxt, int seg)
6150 {
6151 return get_segment_base(emul_to_vcpu(ctxt), seg);
6152 }
6153
6154 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6155 struct desc_struct *desc, u32 *base3,
6156 int seg)
6157 {
6158 struct kvm_segment var;
6159
6160 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6161 *selector = var.selector;
6162
6163 if (var.unusable) {
6164 memset(desc, 0, sizeof(*desc));
6165 if (base3)
6166 *base3 = 0;
6167 return false;
6168 }
6169
6170 if (var.g)
6171 var.limit >>= 12;
6172 set_desc_limit(desc, var.limit);
6173 set_desc_base(desc, (unsigned long)var.base);
6174 #ifdef CONFIG_X86_64
6175 if (base3)
6176 *base3 = var.base >> 32;
6177 #endif
6178 desc->type = var.type;
6179 desc->s = var.s;
6180 desc->dpl = var.dpl;
6181 desc->p = var.present;
6182 desc->avl = var.avl;
6183 desc->l = var.l;
6184 desc->d = var.db;
6185 desc->g = var.g;
6186
6187 return true;
6188 }
6189
6190 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6191 struct desc_struct *desc, u32 base3,
6192 int seg)
6193 {
6194 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6195 struct kvm_segment var;
6196
6197 var.selector = selector;
6198 var.base = get_desc_base(desc);
6199 #ifdef CONFIG_X86_64
6200 var.base |= ((u64)base3) << 32;
6201 #endif
6202 var.limit = get_desc_limit(desc);
6203 if (desc->g)
6204 var.limit = (var.limit << 12) | 0xfff;
6205 var.type = desc->type;
6206 var.dpl = desc->dpl;
6207 var.db = desc->d;
6208 var.s = desc->s;
6209 var.l = desc->l;
6210 var.g = desc->g;
6211 var.avl = desc->avl;
6212 var.present = desc->p;
6213 var.unusable = !var.present;
6214 var.padding = 0;
6215
6216 kvm_set_segment(vcpu, &var, seg);
6217 return;
6218 }
6219
6220 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6221 u32 msr_index, u64 *pdata)
6222 {
6223 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6224 }
6225
6226 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6227 u32 msr_index, u64 data)
6228 {
6229 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6230 }
6231
6232 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6233 {
6234 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6235
6236 return vcpu->arch.smbase;
6237 }
6238
6239 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6240 {
6241 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6242
6243 vcpu->arch.smbase = smbase;
6244 }
6245
6246 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6247 u32 pmc)
6248 {
6249 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6250 }
6251
6252 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6253 u32 pmc, u64 *pdata)
6254 {
6255 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6256 }
6257
6258 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6259 {
6260 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6261 }
6262
6263 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6264 struct x86_instruction_info *info,
6265 enum x86_intercept_stage stage)
6266 {
6267 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6268 }
6269
6270 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6271 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6272 {
6273 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6274 }
6275
6276 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6277 {
6278 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6279 }
6280
6281 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6282 {
6283 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6284 }
6285
6286 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6287 {
6288 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6289 }
6290
6291 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6292 {
6293 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6294 }
6295
6296 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6297 {
6298 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6299 }
6300
6301 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6302 {
6303 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6304 }
6305
6306 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6307 {
6308 return emul_to_vcpu(ctxt)->arch.hflags;
6309 }
6310
6311 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6312 {
6313 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6314 }
6315
6316 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6317 const char *smstate)
6318 {
6319 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6320 }
6321
6322 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6323 {
6324 kvm_smm_changed(emul_to_vcpu(ctxt));
6325 }
6326
6327 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6328 {
6329 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6330 }
6331
6332 static const struct x86_emulate_ops emulate_ops = {
6333 .read_gpr = emulator_read_gpr,
6334 .write_gpr = emulator_write_gpr,
6335 .read_std = emulator_read_std,
6336 .write_std = emulator_write_std,
6337 .read_phys = kvm_read_guest_phys_system,
6338 .fetch = kvm_fetch_guest_virt,
6339 .read_emulated = emulator_read_emulated,
6340 .write_emulated = emulator_write_emulated,
6341 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6342 .invlpg = emulator_invlpg,
6343 .pio_in_emulated = emulator_pio_in_emulated,
6344 .pio_out_emulated = emulator_pio_out_emulated,
6345 .get_segment = emulator_get_segment,
6346 .set_segment = emulator_set_segment,
6347 .get_cached_segment_base = emulator_get_cached_segment_base,
6348 .get_gdt = emulator_get_gdt,
6349 .get_idt = emulator_get_idt,
6350 .set_gdt = emulator_set_gdt,
6351 .set_idt = emulator_set_idt,
6352 .get_cr = emulator_get_cr,
6353 .set_cr = emulator_set_cr,
6354 .cpl = emulator_get_cpl,
6355 .get_dr = emulator_get_dr,
6356 .set_dr = emulator_set_dr,
6357 .get_smbase = emulator_get_smbase,
6358 .set_smbase = emulator_set_smbase,
6359 .set_msr = emulator_set_msr,
6360 .get_msr = emulator_get_msr,
6361 .check_pmc = emulator_check_pmc,
6362 .read_pmc = emulator_read_pmc,
6363 .halt = emulator_halt,
6364 .wbinvd = emulator_wbinvd,
6365 .fix_hypercall = emulator_fix_hypercall,
6366 .intercept = emulator_intercept,
6367 .get_cpuid = emulator_get_cpuid,
6368 .guest_has_long_mode = emulator_guest_has_long_mode,
6369 .guest_has_movbe = emulator_guest_has_movbe,
6370 .guest_has_fxsr = emulator_guest_has_fxsr,
6371 .set_nmi_mask = emulator_set_nmi_mask,
6372 .get_hflags = emulator_get_hflags,
6373 .set_hflags = emulator_set_hflags,
6374 .pre_leave_smm = emulator_pre_leave_smm,
6375 .post_leave_smm = emulator_post_leave_smm,
6376 .set_xcr = emulator_set_xcr,
6377 };
6378
6379 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6380 {
6381 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6382 /*
6383 * an sti; sti; sequence only disable interrupts for the first
6384 * instruction. So, if the last instruction, be it emulated or
6385 * not, left the system with the INT_STI flag enabled, it
6386 * means that the last instruction is an sti. We should not
6387 * leave the flag on in this case. The same goes for mov ss
6388 */
6389 if (int_shadow & mask)
6390 mask = 0;
6391 if (unlikely(int_shadow || mask)) {
6392 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6393 if (!mask)
6394 kvm_make_request(KVM_REQ_EVENT, vcpu);
6395 }
6396 }
6397
6398 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6399 {
6400 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6401 if (ctxt->exception.vector == PF_VECTOR)
6402 return kvm_propagate_fault(vcpu, &ctxt->exception);
6403
6404 if (ctxt->exception.error_code_valid)
6405 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6406 ctxt->exception.error_code);
6407 else
6408 kvm_queue_exception(vcpu, ctxt->exception.vector);
6409 return false;
6410 }
6411
6412 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6413 {
6414 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6415 int cs_db, cs_l;
6416
6417 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6418
6419 ctxt->gpa_available = false;
6420 ctxt->eflags = kvm_get_rflags(vcpu);
6421 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6422
6423 ctxt->eip = kvm_rip_read(vcpu);
6424 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6425 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6426 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6427 cs_db ? X86EMUL_MODE_PROT32 :
6428 X86EMUL_MODE_PROT16;
6429 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6430 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6431 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6432
6433 init_decode_cache(ctxt);
6434 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6435 }
6436
6437 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6438 {
6439 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6440 int ret;
6441
6442 init_emulate_ctxt(vcpu);
6443
6444 ctxt->op_bytes = 2;
6445 ctxt->ad_bytes = 2;
6446 ctxt->_eip = ctxt->eip + inc_eip;
6447 ret = emulate_int_real(ctxt, irq);
6448
6449 if (ret != X86EMUL_CONTINUE) {
6450 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6451 } else {
6452 ctxt->eip = ctxt->_eip;
6453 kvm_rip_write(vcpu, ctxt->eip);
6454 kvm_set_rflags(vcpu, ctxt->eflags);
6455 }
6456 }
6457 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6458
6459 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6460 {
6461 ++vcpu->stat.insn_emulation_fail;
6462 trace_kvm_emulate_insn_failed(vcpu);
6463
6464 if (emulation_type & EMULTYPE_VMWARE_GP) {
6465 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6466 return 1;
6467 }
6468
6469 if (emulation_type & EMULTYPE_SKIP) {
6470 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6471 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6472 vcpu->run->internal.ndata = 0;
6473 return 0;
6474 }
6475
6476 kvm_queue_exception(vcpu, UD_VECTOR);
6477
6478 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6479 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6480 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6481 vcpu->run->internal.ndata = 0;
6482 return 0;
6483 }
6484
6485 return 1;
6486 }
6487
6488 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6489 bool write_fault_to_shadow_pgtable,
6490 int emulation_type)
6491 {
6492 gpa_t gpa = cr2_or_gpa;
6493 kvm_pfn_t pfn;
6494
6495 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6496 return false;
6497
6498 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6499 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6500 return false;
6501
6502 if (!vcpu->arch.mmu->direct_map) {
6503 /*
6504 * Write permission should be allowed since only
6505 * write access need to be emulated.
6506 */
6507 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6508
6509 /*
6510 * If the mapping is invalid in guest, let cpu retry
6511 * it to generate fault.
6512 */
6513 if (gpa == UNMAPPED_GVA)
6514 return true;
6515 }
6516
6517 /*
6518 * Do not retry the unhandleable instruction if it faults on the
6519 * readonly host memory, otherwise it will goto a infinite loop:
6520 * retry instruction -> write #PF -> emulation fail -> retry
6521 * instruction -> ...
6522 */
6523 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6524
6525 /*
6526 * If the instruction failed on the error pfn, it can not be fixed,
6527 * report the error to userspace.
6528 */
6529 if (is_error_noslot_pfn(pfn))
6530 return false;
6531
6532 kvm_release_pfn_clean(pfn);
6533
6534 /* The instructions are well-emulated on direct mmu. */
6535 if (vcpu->arch.mmu->direct_map) {
6536 unsigned int indirect_shadow_pages;
6537
6538 spin_lock(&vcpu->kvm->mmu_lock);
6539 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6540 spin_unlock(&vcpu->kvm->mmu_lock);
6541
6542 if (indirect_shadow_pages)
6543 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6544
6545 return true;
6546 }
6547
6548 /*
6549 * if emulation was due to access to shadowed page table
6550 * and it failed try to unshadow page and re-enter the
6551 * guest to let CPU execute the instruction.
6552 */
6553 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6554
6555 /*
6556 * If the access faults on its page table, it can not
6557 * be fixed by unprotecting shadow page and it should
6558 * be reported to userspace.
6559 */
6560 return !write_fault_to_shadow_pgtable;
6561 }
6562
6563 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6564 gpa_t cr2_or_gpa, int emulation_type)
6565 {
6566 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6567 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6568
6569 last_retry_eip = vcpu->arch.last_retry_eip;
6570 last_retry_addr = vcpu->arch.last_retry_addr;
6571
6572 /*
6573 * If the emulation is caused by #PF and it is non-page_table
6574 * writing instruction, it means the VM-EXIT is caused by shadow
6575 * page protected, we can zap the shadow page and retry this
6576 * instruction directly.
6577 *
6578 * Note: if the guest uses a non-page-table modifying instruction
6579 * on the PDE that points to the instruction, then we will unmap
6580 * the instruction and go to an infinite loop. So, we cache the
6581 * last retried eip and the last fault address, if we meet the eip
6582 * and the address again, we can break out of the potential infinite
6583 * loop.
6584 */
6585 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6586
6587 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6588 return false;
6589
6590 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6591 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6592 return false;
6593
6594 if (x86_page_table_writing_insn(ctxt))
6595 return false;
6596
6597 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6598 return false;
6599
6600 vcpu->arch.last_retry_eip = ctxt->eip;
6601 vcpu->arch.last_retry_addr = cr2_or_gpa;
6602
6603 if (!vcpu->arch.mmu->direct_map)
6604 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6605
6606 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6607
6608 return true;
6609 }
6610
6611 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6612 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6613
6614 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6615 {
6616 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6617 /* This is a good place to trace that we are exiting SMM. */
6618 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6619
6620 /* Process a latched INIT or SMI, if any. */
6621 kvm_make_request(KVM_REQ_EVENT, vcpu);
6622 }
6623
6624 kvm_mmu_reset_context(vcpu);
6625 }
6626
6627 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6628 unsigned long *db)
6629 {
6630 u32 dr6 = 0;
6631 int i;
6632 u32 enable, rwlen;
6633
6634 enable = dr7;
6635 rwlen = dr7 >> 16;
6636 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6637 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6638 dr6 |= (1 << i);
6639 return dr6;
6640 }
6641
6642 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6643 {
6644 struct kvm_run *kvm_run = vcpu->run;
6645
6646 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6647 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6648 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6649 kvm_run->debug.arch.exception = DB_VECTOR;
6650 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6651 return 0;
6652 }
6653 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6654 return 1;
6655 }
6656
6657 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6658 {
6659 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6660 int r;
6661
6662 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6663 if (unlikely(!r))
6664 return 0;
6665
6666 /*
6667 * rflags is the old, "raw" value of the flags. The new value has
6668 * not been saved yet.
6669 *
6670 * This is correct even for TF set by the guest, because "the
6671 * processor will not generate this exception after the instruction
6672 * that sets the TF flag".
6673 */
6674 if (unlikely(rflags & X86_EFLAGS_TF))
6675 r = kvm_vcpu_do_singlestep(vcpu);
6676 return r;
6677 }
6678 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6679
6680 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6681 {
6682 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6683 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6684 struct kvm_run *kvm_run = vcpu->run;
6685 unsigned long eip = kvm_get_linear_rip(vcpu);
6686 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6687 vcpu->arch.guest_debug_dr7,
6688 vcpu->arch.eff_db);
6689
6690 if (dr6 != 0) {
6691 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6692 kvm_run->debug.arch.pc = eip;
6693 kvm_run->debug.arch.exception = DB_VECTOR;
6694 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6695 *r = 0;
6696 return true;
6697 }
6698 }
6699
6700 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6701 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6702 unsigned long eip = kvm_get_linear_rip(vcpu);
6703 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6704 vcpu->arch.dr7,
6705 vcpu->arch.db);
6706
6707 if (dr6 != 0) {
6708 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6709 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6710 kvm_queue_exception(vcpu, DB_VECTOR);
6711 *r = 1;
6712 return true;
6713 }
6714 }
6715
6716 return false;
6717 }
6718
6719 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6720 {
6721 switch (ctxt->opcode_len) {
6722 case 1:
6723 switch (ctxt->b) {
6724 case 0xe4: /* IN */
6725 case 0xe5:
6726 case 0xec:
6727 case 0xed:
6728 case 0xe6: /* OUT */
6729 case 0xe7:
6730 case 0xee:
6731 case 0xef:
6732 case 0x6c: /* INS */
6733 case 0x6d:
6734 case 0x6e: /* OUTS */
6735 case 0x6f:
6736 return true;
6737 }
6738 break;
6739 case 2:
6740 switch (ctxt->b) {
6741 case 0x33: /* RDPMC */
6742 return true;
6743 }
6744 break;
6745 }
6746
6747 return false;
6748 }
6749
6750 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6751 int emulation_type, void *insn, int insn_len)
6752 {
6753 int r;
6754 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6755 bool writeback = true;
6756 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6757
6758 vcpu->arch.l1tf_flush_l1d = true;
6759
6760 /*
6761 * Clear write_fault_to_shadow_pgtable here to ensure it is
6762 * never reused.
6763 */
6764 vcpu->arch.write_fault_to_shadow_pgtable = false;
6765 kvm_clear_exception_queue(vcpu);
6766
6767 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6768 init_emulate_ctxt(vcpu);
6769
6770 /*
6771 * We will reenter on the same instruction since
6772 * we do not set complete_userspace_io. This does not
6773 * handle watchpoints yet, those would be handled in
6774 * the emulate_ops.
6775 */
6776 if (!(emulation_type & EMULTYPE_SKIP) &&
6777 kvm_vcpu_check_breakpoint(vcpu, &r))
6778 return r;
6779
6780 ctxt->interruptibility = 0;
6781 ctxt->have_exception = false;
6782 ctxt->exception.vector = -1;
6783 ctxt->perm_ok = false;
6784
6785 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6786
6787 r = x86_decode_insn(ctxt, insn, insn_len);
6788
6789 trace_kvm_emulate_insn_start(vcpu);
6790 ++vcpu->stat.insn_emulation;
6791 if (r != EMULATION_OK) {
6792 if ((emulation_type & EMULTYPE_TRAP_UD) ||
6793 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6794 kvm_queue_exception(vcpu, UD_VECTOR);
6795 return 1;
6796 }
6797 if (reexecute_instruction(vcpu, cr2_or_gpa,
6798 write_fault_to_spt,
6799 emulation_type))
6800 return 1;
6801 if (ctxt->have_exception) {
6802 /*
6803 * #UD should result in just EMULATION_FAILED, and trap-like
6804 * exception should not be encountered during decode.
6805 */
6806 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6807 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6808 inject_emulated_exception(vcpu);
6809 return 1;
6810 }
6811 return handle_emulation_failure(vcpu, emulation_type);
6812 }
6813 }
6814
6815 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6816 !is_vmware_backdoor_opcode(ctxt)) {
6817 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6818 return 1;
6819 }
6820
6821 /*
6822 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6823 * for kvm_skip_emulated_instruction(). The caller is responsible for
6824 * updating interruptibility state and injecting single-step #DBs.
6825 */
6826 if (emulation_type & EMULTYPE_SKIP) {
6827 kvm_rip_write(vcpu, ctxt->_eip);
6828 if (ctxt->eflags & X86_EFLAGS_RF)
6829 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6830 return 1;
6831 }
6832
6833 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6834 return 1;
6835
6836 /* this is needed for vmware backdoor interface to work since it
6837 changes registers values during IO operation */
6838 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6839 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6840 emulator_invalidate_register_cache(ctxt);
6841 }
6842
6843 restart:
6844 if (emulation_type & EMULTYPE_PF) {
6845 /* Save the faulting GPA (cr2) in the address field */
6846 ctxt->exception.address = cr2_or_gpa;
6847
6848 /* With shadow page tables, cr2 contains a GVA or nGPA. */
6849 if (vcpu->arch.mmu->direct_map) {
6850 ctxt->gpa_available = true;
6851 ctxt->gpa_val = cr2_or_gpa;
6852 }
6853 } else {
6854 /* Sanitize the address out of an abundance of paranoia. */
6855 ctxt->exception.address = 0;
6856 }
6857
6858 r = x86_emulate_insn(ctxt);
6859
6860 if (r == EMULATION_INTERCEPTED)
6861 return 1;
6862
6863 if (r == EMULATION_FAILED) {
6864 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6865 emulation_type))
6866 return 1;
6867
6868 return handle_emulation_failure(vcpu, emulation_type);
6869 }
6870
6871 if (ctxt->have_exception) {
6872 r = 1;
6873 if (inject_emulated_exception(vcpu))
6874 return r;
6875 } else if (vcpu->arch.pio.count) {
6876 if (!vcpu->arch.pio.in) {
6877 /* FIXME: return into emulator if single-stepping. */
6878 vcpu->arch.pio.count = 0;
6879 } else {
6880 writeback = false;
6881 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6882 }
6883 r = 0;
6884 } else if (vcpu->mmio_needed) {
6885 ++vcpu->stat.mmio_exits;
6886
6887 if (!vcpu->mmio_is_write)
6888 writeback = false;
6889 r = 0;
6890 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6891 } else if (r == EMULATION_RESTART)
6892 goto restart;
6893 else
6894 r = 1;
6895
6896 if (writeback) {
6897 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6898 toggle_interruptibility(vcpu, ctxt->interruptibility);
6899 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6900 if (!ctxt->have_exception ||
6901 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6902 kvm_rip_write(vcpu, ctxt->eip);
6903 if (r && ctxt->tf)
6904 r = kvm_vcpu_do_singlestep(vcpu);
6905 if (kvm_x86_ops->update_emulated_instruction)
6906 kvm_x86_ops->update_emulated_instruction(vcpu);
6907 __kvm_set_rflags(vcpu, ctxt->eflags);
6908 }
6909
6910 /*
6911 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6912 * do nothing, and it will be requested again as soon as
6913 * the shadow expires. But we still need to check here,
6914 * because POPF has no interrupt shadow.
6915 */
6916 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6917 kvm_make_request(KVM_REQ_EVENT, vcpu);
6918 } else
6919 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6920
6921 return r;
6922 }
6923
6924 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6925 {
6926 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6927 }
6928 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6929
6930 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6931 void *insn, int insn_len)
6932 {
6933 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6934 }
6935 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6936
6937 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6938 {
6939 vcpu->arch.pio.count = 0;
6940 return 1;
6941 }
6942
6943 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6944 {
6945 vcpu->arch.pio.count = 0;
6946
6947 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6948 return 1;
6949
6950 return kvm_skip_emulated_instruction(vcpu);
6951 }
6952
6953 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6954 unsigned short port)
6955 {
6956 unsigned long val = kvm_rax_read(vcpu);
6957 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6958 size, port, &val, 1);
6959 if (ret)
6960 return ret;
6961
6962 /*
6963 * Workaround userspace that relies on old KVM behavior of %rip being
6964 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6965 */
6966 if (port == 0x7e &&
6967 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6968 vcpu->arch.complete_userspace_io =
6969 complete_fast_pio_out_port_0x7e;
6970 kvm_skip_emulated_instruction(vcpu);
6971 } else {
6972 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6973 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6974 }
6975 return 0;
6976 }
6977
6978 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6979 {
6980 unsigned long val;
6981
6982 /* We should only ever be called with arch.pio.count equal to 1 */
6983 BUG_ON(vcpu->arch.pio.count != 1);
6984
6985 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6986 vcpu->arch.pio.count = 0;
6987 return 1;
6988 }
6989
6990 /* For size less than 4 we merge, else we zero extend */
6991 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6992
6993 /*
6994 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6995 * the copy and tracing
6996 */
6997 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6998 vcpu->arch.pio.port, &val, 1);
6999 kvm_rax_write(vcpu, val);
7000
7001 return kvm_skip_emulated_instruction(vcpu);
7002 }
7003
7004 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7005 unsigned short port)
7006 {
7007 unsigned long val;
7008 int ret;
7009
7010 /* For size less than 4 we merge, else we zero extend */
7011 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7012
7013 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
7014 &val, 1);
7015 if (ret) {
7016 kvm_rax_write(vcpu, val);
7017 return ret;
7018 }
7019
7020 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7021 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7022
7023 return 0;
7024 }
7025
7026 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7027 {
7028 int ret;
7029
7030 if (in)
7031 ret = kvm_fast_pio_in(vcpu, size, port);
7032 else
7033 ret = kvm_fast_pio_out(vcpu, size, port);
7034 return ret && kvm_skip_emulated_instruction(vcpu);
7035 }
7036 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7037
7038 static int kvmclock_cpu_down_prep(unsigned int cpu)
7039 {
7040 __this_cpu_write(cpu_tsc_khz, 0);
7041 return 0;
7042 }
7043
7044 static void tsc_khz_changed(void *data)
7045 {
7046 struct cpufreq_freqs *freq = data;
7047 unsigned long khz = 0;
7048
7049 if (data)
7050 khz = freq->new;
7051 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7052 khz = cpufreq_quick_get(raw_smp_processor_id());
7053 if (!khz)
7054 khz = tsc_khz;
7055 __this_cpu_write(cpu_tsc_khz, khz);
7056 }
7057
7058 #ifdef CONFIG_X86_64
7059 static void kvm_hyperv_tsc_notifier(void)
7060 {
7061 struct kvm *kvm;
7062 struct kvm_vcpu *vcpu;
7063 int cpu;
7064
7065 mutex_lock(&kvm_lock);
7066 list_for_each_entry(kvm, &vm_list, vm_list)
7067 kvm_make_mclock_inprogress_request(kvm);
7068
7069 hyperv_stop_tsc_emulation();
7070
7071 /* TSC frequency always matches when on Hyper-V */
7072 for_each_present_cpu(cpu)
7073 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7074 kvm_max_guest_tsc_khz = tsc_khz;
7075
7076 list_for_each_entry(kvm, &vm_list, vm_list) {
7077 struct kvm_arch *ka = &kvm->arch;
7078
7079 spin_lock(&ka->pvclock_gtod_sync_lock);
7080
7081 pvclock_update_vm_gtod_copy(kvm);
7082
7083 kvm_for_each_vcpu(cpu, vcpu, kvm)
7084 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7085
7086 kvm_for_each_vcpu(cpu, vcpu, kvm)
7087 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7088
7089 spin_unlock(&ka->pvclock_gtod_sync_lock);
7090 }
7091 mutex_unlock(&kvm_lock);
7092 }
7093 #endif
7094
7095 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7096 {
7097 struct kvm *kvm;
7098 struct kvm_vcpu *vcpu;
7099 int i, send_ipi = 0;
7100
7101 /*
7102 * We allow guests to temporarily run on slowing clocks,
7103 * provided we notify them after, or to run on accelerating
7104 * clocks, provided we notify them before. Thus time never
7105 * goes backwards.
7106 *
7107 * However, we have a problem. We can't atomically update
7108 * the frequency of a given CPU from this function; it is
7109 * merely a notifier, which can be called from any CPU.
7110 * Changing the TSC frequency at arbitrary points in time
7111 * requires a recomputation of local variables related to
7112 * the TSC for each VCPU. We must flag these local variables
7113 * to be updated and be sure the update takes place with the
7114 * new frequency before any guests proceed.
7115 *
7116 * Unfortunately, the combination of hotplug CPU and frequency
7117 * change creates an intractable locking scenario; the order
7118 * of when these callouts happen is undefined with respect to
7119 * CPU hotplug, and they can race with each other. As such,
7120 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7121 * undefined; you can actually have a CPU frequency change take
7122 * place in between the computation of X and the setting of the
7123 * variable. To protect against this problem, all updates of
7124 * the per_cpu tsc_khz variable are done in an interrupt
7125 * protected IPI, and all callers wishing to update the value
7126 * must wait for a synchronous IPI to complete (which is trivial
7127 * if the caller is on the CPU already). This establishes the
7128 * necessary total order on variable updates.
7129 *
7130 * Note that because a guest time update may take place
7131 * anytime after the setting of the VCPU's request bit, the
7132 * correct TSC value must be set before the request. However,
7133 * to ensure the update actually makes it to any guest which
7134 * starts running in hardware virtualization between the set
7135 * and the acquisition of the spinlock, we must also ping the
7136 * CPU after setting the request bit.
7137 *
7138 */
7139
7140 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7141
7142 mutex_lock(&kvm_lock);
7143 list_for_each_entry(kvm, &vm_list, vm_list) {
7144 kvm_for_each_vcpu(i, vcpu, kvm) {
7145 if (vcpu->cpu != cpu)
7146 continue;
7147 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7148 if (vcpu->cpu != raw_smp_processor_id())
7149 send_ipi = 1;
7150 }
7151 }
7152 mutex_unlock(&kvm_lock);
7153
7154 if (freq->old < freq->new && send_ipi) {
7155 /*
7156 * We upscale the frequency. Must make the guest
7157 * doesn't see old kvmclock values while running with
7158 * the new frequency, otherwise we risk the guest sees
7159 * time go backwards.
7160 *
7161 * In case we update the frequency for another cpu
7162 * (which might be in guest context) send an interrupt
7163 * to kick the cpu out of guest context. Next time
7164 * guest context is entered kvmclock will be updated,
7165 * so the guest will not see stale values.
7166 */
7167 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7168 }
7169 }
7170
7171 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7172 void *data)
7173 {
7174 struct cpufreq_freqs *freq = data;
7175 int cpu;
7176
7177 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7178 return 0;
7179 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7180 return 0;
7181
7182 for_each_cpu(cpu, freq->policy->cpus)
7183 __kvmclock_cpufreq_notifier(freq, cpu);
7184
7185 return 0;
7186 }
7187
7188 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7189 .notifier_call = kvmclock_cpufreq_notifier
7190 };
7191
7192 static int kvmclock_cpu_online(unsigned int cpu)
7193 {
7194 tsc_khz_changed(NULL);
7195 return 0;
7196 }
7197
7198 static void kvm_timer_init(void)
7199 {
7200 max_tsc_khz = tsc_khz;
7201
7202 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7203 #ifdef CONFIG_CPU_FREQ
7204 struct cpufreq_policy policy;
7205 int cpu;
7206
7207 memset(&policy, 0, sizeof(policy));
7208 cpu = get_cpu();
7209 cpufreq_get_policy(&policy, cpu);
7210 if (policy.cpuinfo.max_freq)
7211 max_tsc_khz = policy.cpuinfo.max_freq;
7212 put_cpu();
7213 #endif
7214 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7215 CPUFREQ_TRANSITION_NOTIFIER);
7216 }
7217
7218 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7219 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7220 }
7221
7222 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7223 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7224
7225 int kvm_is_in_guest(void)
7226 {
7227 return __this_cpu_read(current_vcpu) != NULL;
7228 }
7229
7230 static int kvm_is_user_mode(void)
7231 {
7232 int user_mode = 3;
7233
7234 if (__this_cpu_read(current_vcpu))
7235 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
7236
7237 return user_mode != 0;
7238 }
7239
7240 static unsigned long kvm_get_guest_ip(void)
7241 {
7242 unsigned long ip = 0;
7243
7244 if (__this_cpu_read(current_vcpu))
7245 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7246
7247 return ip;
7248 }
7249
7250 static void kvm_handle_intel_pt_intr(void)
7251 {
7252 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7253
7254 kvm_make_request(KVM_REQ_PMI, vcpu);
7255 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7256 (unsigned long *)&vcpu->arch.pmu.global_status);
7257 }
7258
7259 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7260 .is_in_guest = kvm_is_in_guest,
7261 .is_user_mode = kvm_is_user_mode,
7262 .get_guest_ip = kvm_get_guest_ip,
7263 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7264 };
7265
7266 #ifdef CONFIG_X86_64
7267 static void pvclock_gtod_update_fn(struct work_struct *work)
7268 {
7269 struct kvm *kvm;
7270
7271 struct kvm_vcpu *vcpu;
7272 int i;
7273
7274 mutex_lock(&kvm_lock);
7275 list_for_each_entry(kvm, &vm_list, vm_list)
7276 kvm_for_each_vcpu(i, vcpu, kvm)
7277 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7278 atomic_set(&kvm_guest_has_master_clock, 0);
7279 mutex_unlock(&kvm_lock);
7280 }
7281
7282 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7283
7284 /*
7285 * Notification about pvclock gtod data update.
7286 */
7287 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7288 void *priv)
7289 {
7290 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7291 struct timekeeper *tk = priv;
7292
7293 update_pvclock_gtod(tk);
7294
7295 /* disable master clock if host does not trust, or does not
7296 * use, TSC based clocksource.
7297 */
7298 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7299 atomic_read(&kvm_guest_has_master_clock) != 0)
7300 queue_work(system_long_wq, &pvclock_gtod_work);
7301
7302 return 0;
7303 }
7304
7305 static struct notifier_block pvclock_gtod_notifier = {
7306 .notifier_call = pvclock_gtod_notify,
7307 };
7308 #endif
7309
7310 int kvm_arch_init(void *opaque)
7311 {
7312 int r;
7313 struct kvm_x86_ops *ops = opaque;
7314
7315 if (kvm_x86_ops) {
7316 printk(KERN_ERR "kvm: already loaded the other module\n");
7317 r = -EEXIST;
7318 goto out;
7319 }
7320
7321 if (!ops->cpu_has_kvm_support()) {
7322 printk(KERN_ERR "kvm: no hardware support\n");
7323 r = -EOPNOTSUPP;
7324 goto out;
7325 }
7326 if (ops->disabled_by_bios()) {
7327 printk(KERN_ERR "kvm: disabled by bios\n");
7328 r = -EOPNOTSUPP;
7329 goto out;
7330 }
7331
7332 /*
7333 * KVM explicitly assumes that the guest has an FPU and
7334 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7335 * vCPU's FPU state as a fxregs_state struct.
7336 */
7337 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7338 printk(KERN_ERR "kvm: inadequate fpu\n");
7339 r = -EOPNOTSUPP;
7340 goto out;
7341 }
7342
7343 r = -ENOMEM;
7344 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7345 __alignof__(struct fpu), SLAB_ACCOUNT,
7346 NULL);
7347 if (!x86_fpu_cache) {
7348 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7349 goto out;
7350 }
7351
7352 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7353 if (!shared_msrs) {
7354 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7355 goto out_free_x86_fpu_cache;
7356 }
7357
7358 r = kvm_mmu_module_init();
7359 if (r)
7360 goto out_free_percpu;
7361
7362 kvm_x86_ops = ops;
7363
7364 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7365 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7366 PT_PRESENT_MASK, 0, sme_me_mask);
7367 kvm_timer_init();
7368
7369 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7370
7371 if (boot_cpu_has(X86_FEATURE_XSAVE))
7372 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7373
7374 kvm_lapic_init();
7375 if (pi_inject_timer == -1)
7376 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7377 #ifdef CONFIG_X86_64
7378 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7379
7380 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7381 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7382 #endif
7383
7384 return 0;
7385
7386 out_free_percpu:
7387 free_percpu(shared_msrs);
7388 out_free_x86_fpu_cache:
7389 kmem_cache_destroy(x86_fpu_cache);
7390 out:
7391 return r;
7392 }
7393
7394 void kvm_arch_exit(void)
7395 {
7396 #ifdef CONFIG_X86_64
7397 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7398 clear_hv_tscchange_cb();
7399 #endif
7400 kvm_lapic_exit();
7401 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7402
7403 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7404 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7405 CPUFREQ_TRANSITION_NOTIFIER);
7406 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7407 #ifdef CONFIG_X86_64
7408 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7409 #endif
7410 kvm_x86_ops = NULL;
7411 kvm_mmu_module_exit();
7412 free_percpu(shared_msrs);
7413 kmem_cache_destroy(x86_fpu_cache);
7414 }
7415
7416 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7417 {
7418 ++vcpu->stat.halt_exits;
7419 if (lapic_in_kernel(vcpu)) {
7420 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7421 return 1;
7422 } else {
7423 vcpu->run->exit_reason = KVM_EXIT_HLT;
7424 return 0;
7425 }
7426 }
7427 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7428
7429 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7430 {
7431 int ret = kvm_skip_emulated_instruction(vcpu);
7432 /*
7433 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7434 * KVM_EXIT_DEBUG here.
7435 */
7436 return kvm_vcpu_halt(vcpu) && ret;
7437 }
7438 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7439
7440 #ifdef CONFIG_X86_64
7441 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7442 unsigned long clock_type)
7443 {
7444 struct kvm_clock_pairing clock_pairing;
7445 struct timespec64 ts;
7446 u64 cycle;
7447 int ret;
7448
7449 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7450 return -KVM_EOPNOTSUPP;
7451
7452 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7453 return -KVM_EOPNOTSUPP;
7454
7455 clock_pairing.sec = ts.tv_sec;
7456 clock_pairing.nsec = ts.tv_nsec;
7457 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7458 clock_pairing.flags = 0;
7459 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7460
7461 ret = 0;
7462 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7463 sizeof(struct kvm_clock_pairing)))
7464 ret = -KVM_EFAULT;
7465
7466 return ret;
7467 }
7468 #endif
7469
7470 /*
7471 * kvm_pv_kick_cpu_op: Kick a vcpu.
7472 *
7473 * @apicid - apicid of vcpu to be kicked.
7474 */
7475 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7476 {
7477 struct kvm_lapic_irq lapic_irq;
7478
7479 lapic_irq.shorthand = APIC_DEST_NOSHORT;
7480 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7481 lapic_irq.level = 0;
7482 lapic_irq.dest_id = apicid;
7483 lapic_irq.msi_redir_hint = false;
7484
7485 lapic_irq.delivery_mode = APIC_DM_REMRD;
7486 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7487 }
7488
7489 bool kvm_apicv_activated(struct kvm *kvm)
7490 {
7491 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7492 }
7493 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7494
7495 void kvm_apicv_init(struct kvm *kvm, bool enable)
7496 {
7497 if (enable)
7498 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7499 &kvm->arch.apicv_inhibit_reasons);
7500 else
7501 set_bit(APICV_INHIBIT_REASON_DISABLE,
7502 &kvm->arch.apicv_inhibit_reasons);
7503 }
7504 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7505
7506 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7507 {
7508 struct kvm_vcpu *target = NULL;
7509 struct kvm_apic_map *map;
7510
7511 rcu_read_lock();
7512 map = rcu_dereference(kvm->arch.apic_map);
7513
7514 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7515 target = map->phys_map[dest_id]->vcpu;
7516
7517 rcu_read_unlock();
7518
7519 if (target && READ_ONCE(target->ready))
7520 kvm_vcpu_yield_to(target);
7521 }
7522
7523 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7524 {
7525 unsigned long nr, a0, a1, a2, a3, ret;
7526 int op_64_bit;
7527
7528 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7529 return kvm_hv_hypercall(vcpu);
7530
7531 nr = kvm_rax_read(vcpu);
7532 a0 = kvm_rbx_read(vcpu);
7533 a1 = kvm_rcx_read(vcpu);
7534 a2 = kvm_rdx_read(vcpu);
7535 a3 = kvm_rsi_read(vcpu);
7536
7537 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7538
7539 op_64_bit = is_64_bit_mode(vcpu);
7540 if (!op_64_bit) {
7541 nr &= 0xFFFFFFFF;
7542 a0 &= 0xFFFFFFFF;
7543 a1 &= 0xFFFFFFFF;
7544 a2 &= 0xFFFFFFFF;
7545 a3 &= 0xFFFFFFFF;
7546 }
7547
7548 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7549 ret = -KVM_EPERM;
7550 goto out;
7551 }
7552
7553 switch (nr) {
7554 case KVM_HC_VAPIC_POLL_IRQ:
7555 ret = 0;
7556 break;
7557 case KVM_HC_KICK_CPU:
7558 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7559 kvm_sched_yield(vcpu->kvm, a1);
7560 ret = 0;
7561 break;
7562 #ifdef CONFIG_X86_64
7563 case KVM_HC_CLOCK_PAIRING:
7564 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7565 break;
7566 #endif
7567 case KVM_HC_SEND_IPI:
7568 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7569 break;
7570 case KVM_HC_SCHED_YIELD:
7571 kvm_sched_yield(vcpu->kvm, a0);
7572 ret = 0;
7573 break;
7574 default:
7575 ret = -KVM_ENOSYS;
7576 break;
7577 }
7578 out:
7579 if (!op_64_bit)
7580 ret = (u32)ret;
7581 kvm_rax_write(vcpu, ret);
7582
7583 ++vcpu->stat.hypercalls;
7584 return kvm_skip_emulated_instruction(vcpu);
7585 }
7586 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7587
7588 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7589 {
7590 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7591 char instruction[3];
7592 unsigned long rip = kvm_rip_read(vcpu);
7593
7594 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7595
7596 return emulator_write_emulated(ctxt, rip, instruction, 3,
7597 &ctxt->exception);
7598 }
7599
7600 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7601 {
7602 return vcpu->run->request_interrupt_window &&
7603 likely(!pic_in_kernel(vcpu->kvm));
7604 }
7605
7606 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7607 {
7608 struct kvm_run *kvm_run = vcpu->run;
7609
7610 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7611 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7612 kvm_run->cr8 = kvm_get_cr8(vcpu);
7613 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7614 kvm_run->ready_for_interrupt_injection =
7615 pic_in_kernel(vcpu->kvm) ||
7616 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7617 }
7618
7619 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7620 {
7621 int max_irr, tpr;
7622
7623 if (!kvm_x86_ops->update_cr8_intercept)
7624 return;
7625
7626 if (!lapic_in_kernel(vcpu))
7627 return;
7628
7629 if (vcpu->arch.apicv_active)
7630 return;
7631
7632 if (!vcpu->arch.apic->vapic_addr)
7633 max_irr = kvm_lapic_find_highest_irr(vcpu);
7634 else
7635 max_irr = -1;
7636
7637 if (max_irr != -1)
7638 max_irr >>= 4;
7639
7640 tpr = kvm_lapic_get_cr8(vcpu);
7641
7642 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7643 }
7644
7645 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7646 {
7647 int r;
7648
7649 /* try to reinject previous events if any */
7650
7651 if (vcpu->arch.exception.injected)
7652 kvm_x86_ops->queue_exception(vcpu);
7653 /*
7654 * Do not inject an NMI or interrupt if there is a pending
7655 * exception. Exceptions and interrupts are recognized at
7656 * instruction boundaries, i.e. the start of an instruction.
7657 * Trap-like exceptions, e.g. #DB, have higher priority than
7658 * NMIs and interrupts, i.e. traps are recognized before an
7659 * NMI/interrupt that's pending on the same instruction.
7660 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7661 * priority, but are only generated (pended) during instruction
7662 * execution, i.e. a pending fault-like exception means the
7663 * fault occurred on the *previous* instruction and must be
7664 * serviced prior to recognizing any new events in order to
7665 * fully complete the previous instruction.
7666 */
7667 else if (!vcpu->arch.exception.pending) {
7668 if (vcpu->arch.nmi_injected)
7669 kvm_x86_ops->set_nmi(vcpu);
7670 else if (vcpu->arch.interrupt.injected)
7671 kvm_x86_ops->set_irq(vcpu);
7672 }
7673
7674 /*
7675 * Call check_nested_events() even if we reinjected a previous event
7676 * in order for caller to determine if it should require immediate-exit
7677 * from L2 to L1 due to pending L1 events which require exit
7678 * from L2 to L1.
7679 */
7680 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7681 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7682 if (r != 0)
7683 return r;
7684 }
7685
7686 /* try to inject new event if pending */
7687 if (vcpu->arch.exception.pending) {
7688 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7689 vcpu->arch.exception.has_error_code,
7690 vcpu->arch.exception.error_code);
7691
7692 WARN_ON_ONCE(vcpu->arch.exception.injected);
7693 vcpu->arch.exception.pending = false;
7694 vcpu->arch.exception.injected = true;
7695
7696 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7697 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7698 X86_EFLAGS_RF);
7699
7700 if (vcpu->arch.exception.nr == DB_VECTOR) {
7701 /*
7702 * This code assumes that nSVM doesn't use
7703 * check_nested_events(). If it does, the
7704 * DR6/DR7 changes should happen before L1
7705 * gets a #VMEXIT for an intercepted #DB in
7706 * L2. (Under VMX, on the other hand, the
7707 * DR6/DR7 changes should not happen in the
7708 * event of a VM-exit to L1 for an intercepted
7709 * #DB in L2.)
7710 */
7711 kvm_deliver_exception_payload(vcpu);
7712 if (vcpu->arch.dr7 & DR7_GD) {
7713 vcpu->arch.dr7 &= ~DR7_GD;
7714 kvm_update_dr7(vcpu);
7715 }
7716 }
7717
7718 kvm_x86_ops->queue_exception(vcpu);
7719 }
7720
7721 /* Don't consider new event if we re-injected an event */
7722 if (kvm_event_needs_reinjection(vcpu))
7723 return 0;
7724
7725 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7726 kvm_x86_ops->smi_allowed(vcpu)) {
7727 vcpu->arch.smi_pending = false;
7728 ++vcpu->arch.smi_count;
7729 enter_smm(vcpu);
7730 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7731 --vcpu->arch.nmi_pending;
7732 vcpu->arch.nmi_injected = true;
7733 kvm_x86_ops->set_nmi(vcpu);
7734 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7735 /*
7736 * Because interrupts can be injected asynchronously, we are
7737 * calling check_nested_events again here to avoid a race condition.
7738 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7739 * proposal and current concerns. Perhaps we should be setting
7740 * KVM_REQ_EVENT only on certain events and not unconditionally?
7741 */
7742 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7743 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7744 if (r != 0)
7745 return r;
7746 }
7747 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7748 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7749 false);
7750 kvm_x86_ops->set_irq(vcpu);
7751 }
7752 }
7753
7754 return 0;
7755 }
7756
7757 static void process_nmi(struct kvm_vcpu *vcpu)
7758 {
7759 unsigned limit = 2;
7760
7761 /*
7762 * x86 is limited to one NMI running, and one NMI pending after it.
7763 * If an NMI is already in progress, limit further NMIs to just one.
7764 * Otherwise, allow two (and we'll inject the first one immediately).
7765 */
7766 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7767 limit = 1;
7768
7769 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7770 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7771 kvm_make_request(KVM_REQ_EVENT, vcpu);
7772 }
7773
7774 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7775 {
7776 u32 flags = 0;
7777 flags |= seg->g << 23;
7778 flags |= seg->db << 22;
7779 flags |= seg->l << 21;
7780 flags |= seg->avl << 20;
7781 flags |= seg->present << 15;
7782 flags |= seg->dpl << 13;
7783 flags |= seg->s << 12;
7784 flags |= seg->type << 8;
7785 return flags;
7786 }
7787
7788 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7789 {
7790 struct kvm_segment seg;
7791 int offset;
7792
7793 kvm_get_segment(vcpu, &seg, n);
7794 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7795
7796 if (n < 3)
7797 offset = 0x7f84 + n * 12;
7798 else
7799 offset = 0x7f2c + (n - 3) * 12;
7800
7801 put_smstate(u32, buf, offset + 8, seg.base);
7802 put_smstate(u32, buf, offset + 4, seg.limit);
7803 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7804 }
7805
7806 #ifdef CONFIG_X86_64
7807 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7808 {
7809 struct kvm_segment seg;
7810 int offset;
7811 u16 flags;
7812
7813 kvm_get_segment(vcpu, &seg, n);
7814 offset = 0x7e00 + n * 16;
7815
7816 flags = enter_smm_get_segment_flags(&seg) >> 8;
7817 put_smstate(u16, buf, offset, seg.selector);
7818 put_smstate(u16, buf, offset + 2, flags);
7819 put_smstate(u32, buf, offset + 4, seg.limit);
7820 put_smstate(u64, buf, offset + 8, seg.base);
7821 }
7822 #endif
7823
7824 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7825 {
7826 struct desc_ptr dt;
7827 struct kvm_segment seg;
7828 unsigned long val;
7829 int i;
7830
7831 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7832 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7833 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7834 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7835
7836 for (i = 0; i < 8; i++)
7837 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7838
7839 kvm_get_dr(vcpu, 6, &val);
7840 put_smstate(u32, buf, 0x7fcc, (u32)val);
7841 kvm_get_dr(vcpu, 7, &val);
7842 put_smstate(u32, buf, 0x7fc8, (u32)val);
7843
7844 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7845 put_smstate(u32, buf, 0x7fc4, seg.selector);
7846 put_smstate(u32, buf, 0x7f64, seg.base);
7847 put_smstate(u32, buf, 0x7f60, seg.limit);
7848 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7849
7850 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7851 put_smstate(u32, buf, 0x7fc0, seg.selector);
7852 put_smstate(u32, buf, 0x7f80, seg.base);
7853 put_smstate(u32, buf, 0x7f7c, seg.limit);
7854 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7855
7856 kvm_x86_ops->get_gdt(vcpu, &dt);
7857 put_smstate(u32, buf, 0x7f74, dt.address);
7858 put_smstate(u32, buf, 0x7f70, dt.size);
7859
7860 kvm_x86_ops->get_idt(vcpu, &dt);
7861 put_smstate(u32, buf, 0x7f58, dt.address);
7862 put_smstate(u32, buf, 0x7f54, dt.size);
7863
7864 for (i = 0; i < 6; i++)
7865 enter_smm_save_seg_32(vcpu, buf, i);
7866
7867 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7868
7869 /* revision id */
7870 put_smstate(u32, buf, 0x7efc, 0x00020000);
7871 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7872 }
7873
7874 #ifdef CONFIG_X86_64
7875 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7876 {
7877 struct desc_ptr dt;
7878 struct kvm_segment seg;
7879 unsigned long val;
7880 int i;
7881
7882 for (i = 0; i < 16; i++)
7883 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7884
7885 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7886 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7887
7888 kvm_get_dr(vcpu, 6, &val);
7889 put_smstate(u64, buf, 0x7f68, val);
7890 kvm_get_dr(vcpu, 7, &val);
7891 put_smstate(u64, buf, 0x7f60, val);
7892
7893 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7894 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7895 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7896
7897 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7898
7899 /* revision id */
7900 put_smstate(u32, buf, 0x7efc, 0x00020064);
7901
7902 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7903
7904 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7905 put_smstate(u16, buf, 0x7e90, seg.selector);
7906 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7907 put_smstate(u32, buf, 0x7e94, seg.limit);
7908 put_smstate(u64, buf, 0x7e98, seg.base);
7909
7910 kvm_x86_ops->get_idt(vcpu, &dt);
7911 put_smstate(u32, buf, 0x7e84, dt.size);
7912 put_smstate(u64, buf, 0x7e88, dt.address);
7913
7914 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7915 put_smstate(u16, buf, 0x7e70, seg.selector);
7916 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7917 put_smstate(u32, buf, 0x7e74, seg.limit);
7918 put_smstate(u64, buf, 0x7e78, seg.base);
7919
7920 kvm_x86_ops->get_gdt(vcpu, &dt);
7921 put_smstate(u32, buf, 0x7e64, dt.size);
7922 put_smstate(u64, buf, 0x7e68, dt.address);
7923
7924 for (i = 0; i < 6; i++)
7925 enter_smm_save_seg_64(vcpu, buf, i);
7926 }
7927 #endif
7928
7929 static void enter_smm(struct kvm_vcpu *vcpu)
7930 {
7931 struct kvm_segment cs, ds;
7932 struct desc_ptr dt;
7933 char buf[512];
7934 u32 cr0;
7935
7936 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7937 memset(buf, 0, 512);
7938 #ifdef CONFIG_X86_64
7939 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7940 enter_smm_save_state_64(vcpu, buf);
7941 else
7942 #endif
7943 enter_smm_save_state_32(vcpu, buf);
7944
7945 /*
7946 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7947 * vCPU state (e.g. leave guest mode) after we've saved the state into
7948 * the SMM state-save area.
7949 */
7950 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7951
7952 vcpu->arch.hflags |= HF_SMM_MASK;
7953 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7954
7955 if (kvm_x86_ops->get_nmi_mask(vcpu))
7956 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7957 else
7958 kvm_x86_ops->set_nmi_mask(vcpu, true);
7959
7960 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7961 kvm_rip_write(vcpu, 0x8000);
7962
7963 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7964 kvm_x86_ops->set_cr0(vcpu, cr0);
7965 vcpu->arch.cr0 = cr0;
7966
7967 kvm_x86_ops->set_cr4(vcpu, 0);
7968
7969 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7970 dt.address = dt.size = 0;
7971 kvm_x86_ops->set_idt(vcpu, &dt);
7972
7973 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7974
7975 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7976 cs.base = vcpu->arch.smbase;
7977
7978 ds.selector = 0;
7979 ds.base = 0;
7980
7981 cs.limit = ds.limit = 0xffffffff;
7982 cs.type = ds.type = 0x3;
7983 cs.dpl = ds.dpl = 0;
7984 cs.db = ds.db = 0;
7985 cs.s = ds.s = 1;
7986 cs.l = ds.l = 0;
7987 cs.g = ds.g = 1;
7988 cs.avl = ds.avl = 0;
7989 cs.present = ds.present = 1;
7990 cs.unusable = ds.unusable = 0;
7991 cs.padding = ds.padding = 0;
7992
7993 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7994 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7995 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7996 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7997 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7998 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7999
8000 #ifdef CONFIG_X86_64
8001 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8002 kvm_x86_ops->set_efer(vcpu, 0);
8003 #endif
8004
8005 kvm_update_cpuid(vcpu);
8006 kvm_mmu_reset_context(vcpu);
8007 }
8008
8009 static void process_smi(struct kvm_vcpu *vcpu)
8010 {
8011 vcpu->arch.smi_pending = true;
8012 kvm_make_request(KVM_REQ_EVENT, vcpu);
8013 }
8014
8015 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8016 unsigned long *vcpu_bitmap)
8017 {
8018 cpumask_var_t cpus;
8019
8020 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8021
8022 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8023 vcpu_bitmap, cpus);
8024
8025 free_cpumask_var(cpus);
8026 }
8027
8028 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8029 {
8030 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8031 }
8032
8033 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8034 {
8035 if (!lapic_in_kernel(vcpu))
8036 return;
8037
8038 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8039 kvm_apic_update_apicv(vcpu);
8040 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
8041 }
8042 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8043
8044 /*
8045 * NOTE: Do not hold any lock prior to calling this.
8046 *
8047 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8048 * locked, because it calls __x86_set_memory_region() which does
8049 * synchronize_srcu(&kvm->srcu).
8050 */
8051 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8052 {
8053 if (!kvm_x86_ops->check_apicv_inhibit_reasons ||
8054 !kvm_x86_ops->check_apicv_inhibit_reasons(bit))
8055 return;
8056
8057 if (activate) {
8058 if (!test_and_clear_bit(bit, &kvm->arch.apicv_inhibit_reasons) ||
8059 !kvm_apicv_activated(kvm))
8060 return;
8061 } else {
8062 if (test_and_set_bit(bit, &kvm->arch.apicv_inhibit_reasons) ||
8063 kvm_apicv_activated(kvm))
8064 return;
8065 }
8066
8067 trace_kvm_apicv_update_request(activate, bit);
8068 if (kvm_x86_ops->pre_update_apicv_exec_ctrl)
8069 kvm_x86_ops->pre_update_apicv_exec_ctrl(kvm, activate);
8070 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
8071 }
8072 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8073
8074 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8075 {
8076 if (!kvm_apic_present(vcpu))
8077 return;
8078
8079 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8080
8081 if (irqchip_split(vcpu->kvm))
8082 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8083 else {
8084 if (vcpu->arch.apicv_active)
8085 kvm_x86_ops->sync_pir_to_irr(vcpu);
8086 if (ioapic_in_kernel(vcpu->kvm))
8087 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8088 }
8089
8090 if (is_guest_mode(vcpu))
8091 vcpu->arch.load_eoi_exitmap_pending = true;
8092 else
8093 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8094 }
8095
8096 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8097 {
8098 u64 eoi_exit_bitmap[4];
8099
8100 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8101 return;
8102
8103 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8104 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8105 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8106 }
8107
8108 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8109 unsigned long start, unsigned long end,
8110 bool blockable)
8111 {
8112 unsigned long apic_address;
8113
8114 /*
8115 * The physical address of apic access page is stored in the VMCS.
8116 * Update it when it becomes invalid.
8117 */
8118 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8119 if (start <= apic_address && apic_address < end)
8120 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8121
8122 return 0;
8123 }
8124
8125 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8126 {
8127 struct page *page = NULL;
8128
8129 if (!lapic_in_kernel(vcpu))
8130 return;
8131
8132 if (!kvm_x86_ops->set_apic_access_page_addr)
8133 return;
8134
8135 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8136 if (is_error_page(page))
8137 return;
8138 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
8139
8140 /*
8141 * Do not pin apic access page in memory, the MMU notifier
8142 * will call us again if it is migrated or swapped out.
8143 */
8144 put_page(page);
8145 }
8146
8147 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8148 {
8149 smp_send_reschedule(vcpu->cpu);
8150 }
8151 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8152
8153 /*
8154 * Returns 1 to let vcpu_run() continue the guest execution loop without
8155 * exiting to the userspace. Otherwise, the value will be returned to the
8156 * userspace.
8157 */
8158 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8159 {
8160 int r;
8161 bool req_int_win =
8162 dm_request_for_irq_injection(vcpu) &&
8163 kvm_cpu_accept_dm_intr(vcpu);
8164 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
8165
8166 bool req_immediate_exit = false;
8167
8168 if (kvm_request_pending(vcpu)) {
8169 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8170 if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) {
8171 r = 0;
8172 goto out;
8173 }
8174 }
8175 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8176 kvm_mmu_unload(vcpu);
8177 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8178 __kvm_migrate_timers(vcpu);
8179 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8180 kvm_gen_update_masterclock(vcpu->kvm);
8181 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8182 kvm_gen_kvmclock_update(vcpu);
8183 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8184 r = kvm_guest_time_update(vcpu);
8185 if (unlikely(r))
8186 goto out;
8187 }
8188 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8189 kvm_mmu_sync_roots(vcpu);
8190 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
8191 kvm_mmu_load_cr3(vcpu);
8192 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
8193 kvm_vcpu_flush_tlb(vcpu, true);
8194 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8195 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8196 r = 0;
8197 goto out;
8198 }
8199 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8200 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8201 vcpu->mmio_needed = 0;
8202 r = 0;
8203 goto out;
8204 }
8205 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8206 /* Page is swapped out. Do synthetic halt */
8207 vcpu->arch.apf.halted = true;
8208 r = 1;
8209 goto out;
8210 }
8211 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8212 record_steal_time(vcpu);
8213 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8214 process_smi(vcpu);
8215 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8216 process_nmi(vcpu);
8217 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8218 kvm_pmu_handle_event(vcpu);
8219 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8220 kvm_pmu_deliver_pmi(vcpu);
8221 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8222 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8223 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8224 vcpu->arch.ioapic_handled_vectors)) {
8225 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8226 vcpu->run->eoi.vector =
8227 vcpu->arch.pending_ioapic_eoi;
8228 r = 0;
8229 goto out;
8230 }
8231 }
8232 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8233 vcpu_scan_ioapic(vcpu);
8234 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8235 vcpu_load_eoi_exitmap(vcpu);
8236 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8237 kvm_vcpu_reload_apic_access_page(vcpu);
8238 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8239 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8240 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8241 r = 0;
8242 goto out;
8243 }
8244 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8245 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8246 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8247 r = 0;
8248 goto out;
8249 }
8250 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8251 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8252 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8253 r = 0;
8254 goto out;
8255 }
8256
8257 /*
8258 * KVM_REQ_HV_STIMER has to be processed after
8259 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8260 * depend on the guest clock being up-to-date
8261 */
8262 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8263 kvm_hv_process_stimers(vcpu);
8264 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8265 kvm_vcpu_update_apicv(vcpu);
8266 }
8267
8268 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8269 ++vcpu->stat.req_event;
8270 kvm_apic_accept_events(vcpu);
8271 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8272 r = 1;
8273 goto out;
8274 }
8275
8276 if (inject_pending_event(vcpu, req_int_win) != 0)
8277 req_immediate_exit = true;
8278 else {
8279 /* Enable SMI/NMI/IRQ window open exits if needed.
8280 *
8281 * SMIs have three cases:
8282 * 1) They can be nested, and then there is nothing to
8283 * do here because RSM will cause a vmexit anyway.
8284 * 2) There is an ISA-specific reason why SMI cannot be
8285 * injected, and the moment when this changes can be
8286 * intercepted.
8287 * 3) Or the SMI can be pending because
8288 * inject_pending_event has completed the injection
8289 * of an IRQ or NMI from the previous vmexit, and
8290 * then we request an immediate exit to inject the
8291 * SMI.
8292 */
8293 if (vcpu->arch.smi_pending && !is_smm(vcpu))
8294 if (!kvm_x86_ops->enable_smi_window(vcpu))
8295 req_immediate_exit = true;
8296 if (vcpu->arch.nmi_pending)
8297 kvm_x86_ops->enable_nmi_window(vcpu);
8298 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8299 kvm_x86_ops->enable_irq_window(vcpu);
8300 WARN_ON(vcpu->arch.exception.pending);
8301 }
8302
8303 if (kvm_lapic_enabled(vcpu)) {
8304 update_cr8_intercept(vcpu);
8305 kvm_lapic_sync_to_vapic(vcpu);
8306 }
8307 }
8308
8309 r = kvm_mmu_reload(vcpu);
8310 if (unlikely(r)) {
8311 goto cancel_injection;
8312 }
8313
8314 preempt_disable();
8315
8316 kvm_x86_ops->prepare_guest_switch(vcpu);
8317
8318 /*
8319 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8320 * IPI are then delayed after guest entry, which ensures that they
8321 * result in virtual interrupt delivery.
8322 */
8323 local_irq_disable();
8324 vcpu->mode = IN_GUEST_MODE;
8325
8326 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8327
8328 /*
8329 * 1) We should set ->mode before checking ->requests. Please see
8330 * the comment in kvm_vcpu_exiting_guest_mode().
8331 *
8332 * 2) For APICv, we should set ->mode before checking PID.ON. This
8333 * pairs with the memory barrier implicit in pi_test_and_set_on
8334 * (see vmx_deliver_posted_interrupt).
8335 *
8336 * 3) This also orders the write to mode from any reads to the page
8337 * tables done while the VCPU is running. Please see the comment
8338 * in kvm_flush_remote_tlbs.
8339 */
8340 smp_mb__after_srcu_read_unlock();
8341
8342 /*
8343 * This handles the case where a posted interrupt was
8344 * notified with kvm_vcpu_kick.
8345 */
8346 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8347 kvm_x86_ops->sync_pir_to_irr(vcpu);
8348
8349 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8350 || need_resched() || signal_pending(current)) {
8351 vcpu->mode = OUTSIDE_GUEST_MODE;
8352 smp_wmb();
8353 local_irq_enable();
8354 preempt_enable();
8355 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8356 r = 1;
8357 goto cancel_injection;
8358 }
8359
8360 if (req_immediate_exit) {
8361 kvm_make_request(KVM_REQ_EVENT, vcpu);
8362 kvm_x86_ops->request_immediate_exit(vcpu);
8363 }
8364
8365 trace_kvm_entry(vcpu->vcpu_id);
8366 guest_enter_irqoff();
8367
8368 fpregs_assert_state_consistent();
8369 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8370 switch_fpu_return();
8371
8372 if (unlikely(vcpu->arch.switch_db_regs)) {
8373 set_debugreg(0, 7);
8374 set_debugreg(vcpu->arch.eff_db[0], 0);
8375 set_debugreg(vcpu->arch.eff_db[1], 1);
8376 set_debugreg(vcpu->arch.eff_db[2], 2);
8377 set_debugreg(vcpu->arch.eff_db[3], 3);
8378 set_debugreg(vcpu->arch.dr6, 6);
8379 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8380 }
8381
8382 kvm_x86_ops->run(vcpu);
8383
8384 /*
8385 * Do this here before restoring debug registers on the host. And
8386 * since we do this before handling the vmexit, a DR access vmexit
8387 * can (a) read the correct value of the debug registers, (b) set
8388 * KVM_DEBUGREG_WONT_EXIT again.
8389 */
8390 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8391 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8392 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8393 kvm_update_dr0123(vcpu);
8394 kvm_update_dr6(vcpu);
8395 kvm_update_dr7(vcpu);
8396 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8397 }
8398
8399 /*
8400 * If the guest has used debug registers, at least dr7
8401 * will be disabled while returning to the host.
8402 * If we don't have active breakpoints in the host, we don't
8403 * care about the messed up debug address registers. But if
8404 * we have some of them active, restore the old state.
8405 */
8406 if (hw_breakpoint_active())
8407 hw_breakpoint_restore();
8408
8409 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8410
8411 vcpu->mode = OUTSIDE_GUEST_MODE;
8412 smp_wmb();
8413
8414 kvm_x86_ops->handle_exit_irqoff(vcpu, &exit_fastpath);
8415
8416 /*
8417 * Consume any pending interrupts, including the possible source of
8418 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8419 * An instruction is required after local_irq_enable() to fully unblock
8420 * interrupts on processors that implement an interrupt shadow, the
8421 * stat.exits increment will do nicely.
8422 */
8423 kvm_before_interrupt(vcpu);
8424 local_irq_enable();
8425 ++vcpu->stat.exits;
8426 local_irq_disable();
8427 kvm_after_interrupt(vcpu);
8428
8429 guest_exit_irqoff();
8430 if (lapic_in_kernel(vcpu)) {
8431 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8432 if (delta != S64_MIN) {
8433 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8434 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8435 }
8436 }
8437
8438 local_irq_enable();
8439 preempt_enable();
8440
8441 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8442
8443 /*
8444 * Profile KVM exit RIPs:
8445 */
8446 if (unlikely(prof_on == KVM_PROFILING)) {
8447 unsigned long rip = kvm_rip_read(vcpu);
8448 profile_hit(KVM_PROFILING, (void *)rip);
8449 }
8450
8451 if (unlikely(vcpu->arch.tsc_always_catchup))
8452 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8453
8454 if (vcpu->arch.apic_attention)
8455 kvm_lapic_sync_from_vapic(vcpu);
8456
8457 r = kvm_x86_ops->handle_exit(vcpu, exit_fastpath);
8458 return r;
8459
8460 cancel_injection:
8461 kvm_x86_ops->cancel_injection(vcpu);
8462 if (unlikely(vcpu->arch.apic_attention))
8463 kvm_lapic_sync_from_vapic(vcpu);
8464 out:
8465 return r;
8466 }
8467
8468 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8469 {
8470 if (!kvm_arch_vcpu_runnable(vcpu) &&
8471 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8472 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8473 kvm_vcpu_block(vcpu);
8474 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8475
8476 if (kvm_x86_ops->post_block)
8477 kvm_x86_ops->post_block(vcpu);
8478
8479 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8480 return 1;
8481 }
8482
8483 kvm_apic_accept_events(vcpu);
8484 switch(vcpu->arch.mp_state) {
8485 case KVM_MP_STATE_HALTED:
8486 vcpu->arch.pv.pv_unhalted = false;
8487 vcpu->arch.mp_state =
8488 KVM_MP_STATE_RUNNABLE;
8489 /* fall through */
8490 case KVM_MP_STATE_RUNNABLE:
8491 vcpu->arch.apf.halted = false;
8492 break;
8493 case KVM_MP_STATE_INIT_RECEIVED:
8494 break;
8495 default:
8496 return -EINTR;
8497 }
8498 return 1;
8499 }
8500
8501 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8502 {
8503 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8504 kvm_x86_ops->check_nested_events(vcpu, false);
8505
8506 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8507 !vcpu->arch.apf.halted);
8508 }
8509
8510 static int vcpu_run(struct kvm_vcpu *vcpu)
8511 {
8512 int r;
8513 struct kvm *kvm = vcpu->kvm;
8514
8515 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8516 vcpu->arch.l1tf_flush_l1d = true;
8517
8518 for (;;) {
8519 if (kvm_vcpu_running(vcpu)) {
8520 r = vcpu_enter_guest(vcpu);
8521 } else {
8522 r = vcpu_block(kvm, vcpu);
8523 }
8524
8525 if (r <= 0)
8526 break;
8527
8528 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8529 if (kvm_cpu_has_pending_timer(vcpu))
8530 kvm_inject_pending_timer_irqs(vcpu);
8531
8532 if (dm_request_for_irq_injection(vcpu) &&
8533 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8534 r = 0;
8535 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8536 ++vcpu->stat.request_irq_exits;
8537 break;
8538 }
8539
8540 kvm_check_async_pf_completion(vcpu);
8541
8542 if (signal_pending(current)) {
8543 r = -EINTR;
8544 vcpu->run->exit_reason = KVM_EXIT_INTR;
8545 ++vcpu->stat.signal_exits;
8546 break;
8547 }
8548 if (need_resched()) {
8549 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8550 cond_resched();
8551 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8552 }
8553 }
8554
8555 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8556
8557 return r;
8558 }
8559
8560 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8561 {
8562 int r;
8563
8564 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8565 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8566 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8567 return r;
8568 }
8569
8570 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8571 {
8572 BUG_ON(!vcpu->arch.pio.count);
8573
8574 return complete_emulated_io(vcpu);
8575 }
8576
8577 /*
8578 * Implements the following, as a state machine:
8579 *
8580 * read:
8581 * for each fragment
8582 * for each mmio piece in the fragment
8583 * write gpa, len
8584 * exit
8585 * copy data
8586 * execute insn
8587 *
8588 * write:
8589 * for each fragment
8590 * for each mmio piece in the fragment
8591 * write gpa, len
8592 * copy data
8593 * exit
8594 */
8595 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8596 {
8597 struct kvm_run *run = vcpu->run;
8598 struct kvm_mmio_fragment *frag;
8599 unsigned len;
8600
8601 BUG_ON(!vcpu->mmio_needed);
8602
8603 /* Complete previous fragment */
8604 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8605 len = min(8u, frag->len);
8606 if (!vcpu->mmio_is_write)
8607 memcpy(frag->data, run->mmio.data, len);
8608
8609 if (frag->len <= 8) {
8610 /* Switch to the next fragment. */
8611 frag++;
8612 vcpu->mmio_cur_fragment++;
8613 } else {
8614 /* Go forward to the next mmio piece. */
8615 frag->data += len;
8616 frag->gpa += len;
8617 frag->len -= len;
8618 }
8619
8620 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8621 vcpu->mmio_needed = 0;
8622
8623 /* FIXME: return into emulator if single-stepping. */
8624 if (vcpu->mmio_is_write)
8625 return 1;
8626 vcpu->mmio_read_completed = 1;
8627 return complete_emulated_io(vcpu);
8628 }
8629
8630 run->exit_reason = KVM_EXIT_MMIO;
8631 run->mmio.phys_addr = frag->gpa;
8632 if (vcpu->mmio_is_write)
8633 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8634 run->mmio.len = min(8u, frag->len);
8635 run->mmio.is_write = vcpu->mmio_is_write;
8636 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8637 return 0;
8638 }
8639
8640 static void kvm_save_current_fpu(struct fpu *fpu)
8641 {
8642 /*
8643 * If the target FPU state is not resident in the CPU registers, just
8644 * memcpy() from current, else save CPU state directly to the target.
8645 */
8646 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8647 memcpy(&fpu->state, &current->thread.fpu.state,
8648 fpu_kernel_xstate_size);
8649 else
8650 copy_fpregs_to_fpstate(fpu);
8651 }
8652
8653 /* Swap (qemu) user FPU context for the guest FPU context. */
8654 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8655 {
8656 fpregs_lock();
8657
8658 kvm_save_current_fpu(vcpu->arch.user_fpu);
8659
8660 /* PKRU is separately restored in kvm_x86_ops->run. */
8661 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8662 ~XFEATURE_MASK_PKRU);
8663
8664 fpregs_mark_activate();
8665 fpregs_unlock();
8666
8667 trace_kvm_fpu(1);
8668 }
8669
8670 /* When vcpu_run ends, restore user space FPU context. */
8671 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8672 {
8673 fpregs_lock();
8674
8675 kvm_save_current_fpu(vcpu->arch.guest_fpu);
8676
8677 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8678
8679 fpregs_mark_activate();
8680 fpregs_unlock();
8681
8682 ++vcpu->stat.fpu_reload;
8683 trace_kvm_fpu(0);
8684 }
8685
8686 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8687 {
8688 int r;
8689
8690 vcpu_load(vcpu);
8691 kvm_sigset_activate(vcpu);
8692 kvm_load_guest_fpu(vcpu);
8693
8694 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8695 if (kvm_run->immediate_exit) {
8696 r = -EINTR;
8697 goto out;
8698 }
8699 kvm_vcpu_block(vcpu);
8700 kvm_apic_accept_events(vcpu);
8701 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8702 r = -EAGAIN;
8703 if (signal_pending(current)) {
8704 r = -EINTR;
8705 vcpu->run->exit_reason = KVM_EXIT_INTR;
8706 ++vcpu->stat.signal_exits;
8707 }
8708 goto out;
8709 }
8710
8711 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8712 r = -EINVAL;
8713 goto out;
8714 }
8715
8716 if (vcpu->run->kvm_dirty_regs) {
8717 r = sync_regs(vcpu);
8718 if (r != 0)
8719 goto out;
8720 }
8721
8722 /* re-sync apic's tpr */
8723 if (!lapic_in_kernel(vcpu)) {
8724 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8725 r = -EINVAL;
8726 goto out;
8727 }
8728 }
8729
8730 if (unlikely(vcpu->arch.complete_userspace_io)) {
8731 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8732 vcpu->arch.complete_userspace_io = NULL;
8733 r = cui(vcpu);
8734 if (r <= 0)
8735 goto out;
8736 } else
8737 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8738
8739 if (kvm_run->immediate_exit)
8740 r = -EINTR;
8741 else
8742 r = vcpu_run(vcpu);
8743
8744 out:
8745 kvm_put_guest_fpu(vcpu);
8746 if (vcpu->run->kvm_valid_regs)
8747 store_regs(vcpu);
8748 post_kvm_run_save(vcpu);
8749 kvm_sigset_deactivate(vcpu);
8750
8751 vcpu_put(vcpu);
8752 return r;
8753 }
8754
8755 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8756 {
8757 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8758 /*
8759 * We are here if userspace calls get_regs() in the middle of
8760 * instruction emulation. Registers state needs to be copied
8761 * back from emulation context to vcpu. Userspace shouldn't do
8762 * that usually, but some bad designed PV devices (vmware
8763 * backdoor interface) need this to work
8764 */
8765 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8766 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8767 }
8768 regs->rax = kvm_rax_read(vcpu);
8769 regs->rbx = kvm_rbx_read(vcpu);
8770 regs->rcx = kvm_rcx_read(vcpu);
8771 regs->rdx = kvm_rdx_read(vcpu);
8772 regs->rsi = kvm_rsi_read(vcpu);
8773 regs->rdi = kvm_rdi_read(vcpu);
8774 regs->rsp = kvm_rsp_read(vcpu);
8775 regs->rbp = kvm_rbp_read(vcpu);
8776 #ifdef CONFIG_X86_64
8777 regs->r8 = kvm_r8_read(vcpu);
8778 regs->r9 = kvm_r9_read(vcpu);
8779 regs->r10 = kvm_r10_read(vcpu);
8780 regs->r11 = kvm_r11_read(vcpu);
8781 regs->r12 = kvm_r12_read(vcpu);
8782 regs->r13 = kvm_r13_read(vcpu);
8783 regs->r14 = kvm_r14_read(vcpu);
8784 regs->r15 = kvm_r15_read(vcpu);
8785 #endif
8786
8787 regs->rip = kvm_rip_read(vcpu);
8788 regs->rflags = kvm_get_rflags(vcpu);
8789 }
8790
8791 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8792 {
8793 vcpu_load(vcpu);
8794 __get_regs(vcpu, regs);
8795 vcpu_put(vcpu);
8796 return 0;
8797 }
8798
8799 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8800 {
8801 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8802 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8803
8804 kvm_rax_write(vcpu, regs->rax);
8805 kvm_rbx_write(vcpu, regs->rbx);
8806 kvm_rcx_write(vcpu, regs->rcx);
8807 kvm_rdx_write(vcpu, regs->rdx);
8808 kvm_rsi_write(vcpu, regs->rsi);
8809 kvm_rdi_write(vcpu, regs->rdi);
8810 kvm_rsp_write(vcpu, regs->rsp);
8811 kvm_rbp_write(vcpu, regs->rbp);
8812 #ifdef CONFIG_X86_64
8813 kvm_r8_write(vcpu, regs->r8);
8814 kvm_r9_write(vcpu, regs->r9);
8815 kvm_r10_write(vcpu, regs->r10);
8816 kvm_r11_write(vcpu, regs->r11);
8817 kvm_r12_write(vcpu, regs->r12);
8818 kvm_r13_write(vcpu, regs->r13);
8819 kvm_r14_write(vcpu, regs->r14);
8820 kvm_r15_write(vcpu, regs->r15);
8821 #endif
8822
8823 kvm_rip_write(vcpu, regs->rip);
8824 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8825
8826 vcpu->arch.exception.pending = false;
8827
8828 kvm_make_request(KVM_REQ_EVENT, vcpu);
8829 }
8830
8831 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8832 {
8833 vcpu_load(vcpu);
8834 __set_regs(vcpu, regs);
8835 vcpu_put(vcpu);
8836 return 0;
8837 }
8838
8839 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8840 {
8841 struct kvm_segment cs;
8842
8843 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8844 *db = cs.db;
8845 *l = cs.l;
8846 }
8847 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8848
8849 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8850 {
8851 struct desc_ptr dt;
8852
8853 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8854 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8855 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8856 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8857 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8858 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8859
8860 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8861 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8862
8863 kvm_x86_ops->get_idt(vcpu, &dt);
8864 sregs->idt.limit = dt.size;
8865 sregs->idt.base = dt.address;
8866 kvm_x86_ops->get_gdt(vcpu, &dt);
8867 sregs->gdt.limit = dt.size;
8868 sregs->gdt.base = dt.address;
8869
8870 sregs->cr0 = kvm_read_cr0(vcpu);
8871 sregs->cr2 = vcpu->arch.cr2;
8872 sregs->cr3 = kvm_read_cr3(vcpu);
8873 sregs->cr4 = kvm_read_cr4(vcpu);
8874 sregs->cr8 = kvm_get_cr8(vcpu);
8875 sregs->efer = vcpu->arch.efer;
8876 sregs->apic_base = kvm_get_apic_base(vcpu);
8877
8878 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8879
8880 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8881 set_bit(vcpu->arch.interrupt.nr,
8882 (unsigned long *)sregs->interrupt_bitmap);
8883 }
8884
8885 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8886 struct kvm_sregs *sregs)
8887 {
8888 vcpu_load(vcpu);
8889 __get_sregs(vcpu, sregs);
8890 vcpu_put(vcpu);
8891 return 0;
8892 }
8893
8894 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8895 struct kvm_mp_state *mp_state)
8896 {
8897 vcpu_load(vcpu);
8898 if (kvm_mpx_supported())
8899 kvm_load_guest_fpu(vcpu);
8900
8901 kvm_apic_accept_events(vcpu);
8902 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8903 vcpu->arch.pv.pv_unhalted)
8904 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8905 else
8906 mp_state->mp_state = vcpu->arch.mp_state;
8907
8908 if (kvm_mpx_supported())
8909 kvm_put_guest_fpu(vcpu);
8910 vcpu_put(vcpu);
8911 return 0;
8912 }
8913
8914 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8915 struct kvm_mp_state *mp_state)
8916 {
8917 int ret = -EINVAL;
8918
8919 vcpu_load(vcpu);
8920
8921 if (!lapic_in_kernel(vcpu) &&
8922 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8923 goto out;
8924
8925 /*
8926 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8927 * INIT state; latched init should be reported using
8928 * KVM_SET_VCPU_EVENTS, so reject it here.
8929 */
8930 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8931 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8932 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8933 goto out;
8934
8935 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8936 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8937 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8938 } else
8939 vcpu->arch.mp_state = mp_state->mp_state;
8940 kvm_make_request(KVM_REQ_EVENT, vcpu);
8941
8942 ret = 0;
8943 out:
8944 vcpu_put(vcpu);
8945 return ret;
8946 }
8947
8948 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8949 int reason, bool has_error_code, u32 error_code)
8950 {
8951 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8952 int ret;
8953
8954 init_emulate_ctxt(vcpu);
8955
8956 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8957 has_error_code, error_code);
8958 if (ret) {
8959 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8960 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8961 vcpu->run->internal.ndata = 0;
8962 return 0;
8963 }
8964
8965 kvm_rip_write(vcpu, ctxt->eip);
8966 kvm_set_rflags(vcpu, ctxt->eflags);
8967 return 1;
8968 }
8969 EXPORT_SYMBOL_GPL(kvm_task_switch);
8970
8971 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8972 {
8973 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8974 /*
8975 * When EFER.LME and CR0.PG are set, the processor is in
8976 * 64-bit mode (though maybe in a 32-bit code segment).
8977 * CR4.PAE and EFER.LMA must be set.
8978 */
8979 if (!(sregs->cr4 & X86_CR4_PAE)
8980 || !(sregs->efer & EFER_LMA))
8981 return -EINVAL;
8982 } else {
8983 /*
8984 * Not in 64-bit mode: EFER.LMA is clear and the code
8985 * segment cannot be 64-bit.
8986 */
8987 if (sregs->efer & EFER_LMA || sregs->cs.l)
8988 return -EINVAL;
8989 }
8990
8991 return kvm_valid_cr4(vcpu, sregs->cr4);
8992 }
8993
8994 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8995 {
8996 struct msr_data apic_base_msr;
8997 int mmu_reset_needed = 0;
8998 int cpuid_update_needed = 0;
8999 int pending_vec, max_bits, idx;
9000 struct desc_ptr dt;
9001 int ret = -EINVAL;
9002
9003 if (kvm_valid_sregs(vcpu, sregs))
9004 goto out;
9005
9006 apic_base_msr.data = sregs->apic_base;
9007 apic_base_msr.host_initiated = true;
9008 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9009 goto out;
9010
9011 dt.size = sregs->idt.limit;
9012 dt.address = sregs->idt.base;
9013 kvm_x86_ops->set_idt(vcpu, &dt);
9014 dt.size = sregs->gdt.limit;
9015 dt.address = sregs->gdt.base;
9016 kvm_x86_ops->set_gdt(vcpu, &dt);
9017
9018 vcpu->arch.cr2 = sregs->cr2;
9019 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9020 vcpu->arch.cr3 = sregs->cr3;
9021 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9022
9023 kvm_set_cr8(vcpu, sregs->cr8);
9024
9025 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9026 kvm_x86_ops->set_efer(vcpu, sregs->efer);
9027
9028 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9029 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
9030 vcpu->arch.cr0 = sregs->cr0;
9031
9032 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9033 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9034 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9035 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
9036 if (cpuid_update_needed)
9037 kvm_update_cpuid(vcpu);
9038
9039 idx = srcu_read_lock(&vcpu->kvm->srcu);
9040 if (is_pae_paging(vcpu)) {
9041 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9042 mmu_reset_needed = 1;
9043 }
9044 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9045
9046 if (mmu_reset_needed)
9047 kvm_mmu_reset_context(vcpu);
9048
9049 max_bits = KVM_NR_INTERRUPTS;
9050 pending_vec = find_first_bit(
9051 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9052 if (pending_vec < max_bits) {
9053 kvm_queue_interrupt(vcpu, pending_vec, false);
9054 pr_debug("Set back pending irq %d\n", pending_vec);
9055 }
9056
9057 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9058 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9059 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9060 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9061 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9062 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9063
9064 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9065 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9066
9067 update_cr8_intercept(vcpu);
9068
9069 /* Older userspace won't unhalt the vcpu on reset. */
9070 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9071 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9072 !is_protmode(vcpu))
9073 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9074
9075 kvm_make_request(KVM_REQ_EVENT, vcpu);
9076
9077 ret = 0;
9078 out:
9079 return ret;
9080 }
9081
9082 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9083 struct kvm_sregs *sregs)
9084 {
9085 int ret;
9086
9087 vcpu_load(vcpu);
9088 ret = __set_sregs(vcpu, sregs);
9089 vcpu_put(vcpu);
9090 return ret;
9091 }
9092
9093 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9094 struct kvm_guest_debug *dbg)
9095 {
9096 unsigned long rflags;
9097 int i, r;
9098
9099 vcpu_load(vcpu);
9100
9101 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9102 r = -EBUSY;
9103 if (vcpu->arch.exception.pending)
9104 goto out;
9105 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9106 kvm_queue_exception(vcpu, DB_VECTOR);
9107 else
9108 kvm_queue_exception(vcpu, BP_VECTOR);
9109 }
9110
9111 /*
9112 * Read rflags as long as potentially injected trace flags are still
9113 * filtered out.
9114 */
9115 rflags = kvm_get_rflags(vcpu);
9116
9117 vcpu->guest_debug = dbg->control;
9118 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9119 vcpu->guest_debug = 0;
9120
9121 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9122 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9123 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9124 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9125 } else {
9126 for (i = 0; i < KVM_NR_DB_REGS; i++)
9127 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9128 }
9129 kvm_update_dr7(vcpu);
9130
9131 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9132 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9133 get_segment_base(vcpu, VCPU_SREG_CS);
9134
9135 /*
9136 * Trigger an rflags update that will inject or remove the trace
9137 * flags.
9138 */
9139 kvm_set_rflags(vcpu, rflags);
9140
9141 kvm_x86_ops->update_bp_intercept(vcpu);
9142
9143 r = 0;
9144
9145 out:
9146 vcpu_put(vcpu);
9147 return r;
9148 }
9149
9150 /*
9151 * Translate a guest virtual address to a guest physical address.
9152 */
9153 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9154 struct kvm_translation *tr)
9155 {
9156 unsigned long vaddr = tr->linear_address;
9157 gpa_t gpa;
9158 int idx;
9159
9160 vcpu_load(vcpu);
9161
9162 idx = srcu_read_lock(&vcpu->kvm->srcu);
9163 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9164 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9165 tr->physical_address = gpa;
9166 tr->valid = gpa != UNMAPPED_GVA;
9167 tr->writeable = 1;
9168 tr->usermode = 0;
9169
9170 vcpu_put(vcpu);
9171 return 0;
9172 }
9173
9174 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9175 {
9176 struct fxregs_state *fxsave;
9177
9178 vcpu_load(vcpu);
9179
9180 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9181 memcpy(fpu->fpr, fxsave->st_space, 128);
9182 fpu->fcw = fxsave->cwd;
9183 fpu->fsw = fxsave->swd;
9184 fpu->ftwx = fxsave->twd;
9185 fpu->last_opcode = fxsave->fop;
9186 fpu->last_ip = fxsave->rip;
9187 fpu->last_dp = fxsave->rdp;
9188 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9189
9190 vcpu_put(vcpu);
9191 return 0;
9192 }
9193
9194 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9195 {
9196 struct fxregs_state *fxsave;
9197
9198 vcpu_load(vcpu);
9199
9200 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9201
9202 memcpy(fxsave->st_space, fpu->fpr, 128);
9203 fxsave->cwd = fpu->fcw;
9204 fxsave->swd = fpu->fsw;
9205 fxsave->twd = fpu->ftwx;
9206 fxsave->fop = fpu->last_opcode;
9207 fxsave->rip = fpu->last_ip;
9208 fxsave->rdp = fpu->last_dp;
9209 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9210
9211 vcpu_put(vcpu);
9212 return 0;
9213 }
9214
9215 static void store_regs(struct kvm_vcpu *vcpu)
9216 {
9217 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9218
9219 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9220 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9221
9222 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9223 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9224
9225 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9226 kvm_vcpu_ioctl_x86_get_vcpu_events(
9227 vcpu, &vcpu->run->s.regs.events);
9228 }
9229
9230 static int sync_regs(struct kvm_vcpu *vcpu)
9231 {
9232 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9233 return -EINVAL;
9234
9235 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9236 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9237 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9238 }
9239 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9240 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9241 return -EINVAL;
9242 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9243 }
9244 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9245 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9246 vcpu, &vcpu->run->s.regs.events))
9247 return -EINVAL;
9248 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9249 }
9250
9251 return 0;
9252 }
9253
9254 static void fx_init(struct kvm_vcpu *vcpu)
9255 {
9256 fpstate_init(&vcpu->arch.guest_fpu->state);
9257 if (boot_cpu_has(X86_FEATURE_XSAVES))
9258 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9259 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9260
9261 /*
9262 * Ensure guest xcr0 is valid for loading
9263 */
9264 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9265
9266 vcpu->arch.cr0 |= X86_CR0_ET;
9267 }
9268
9269 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9270 {
9271 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9272 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9273 "guest TSC will not be reliable\n");
9274
9275 return 0;
9276 }
9277
9278 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9279 {
9280 struct page *page;
9281 int r;
9282
9283 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9284 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9285 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9286 else
9287 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9288
9289 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9290
9291 r = kvm_mmu_create(vcpu);
9292 if (r < 0)
9293 return r;
9294
9295 if (irqchip_in_kernel(vcpu->kvm)) {
9296 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9297 if (r < 0)
9298 goto fail_mmu_destroy;
9299 if (kvm_apicv_activated(vcpu->kvm))
9300 vcpu->arch.apicv_active = true;
9301 } else
9302 static_key_slow_inc(&kvm_no_apic_vcpu);
9303
9304 r = -ENOMEM;
9305
9306 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9307 if (!page)
9308 goto fail_free_lapic;
9309 vcpu->arch.pio_data = page_address(page);
9310
9311 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9312 GFP_KERNEL_ACCOUNT);
9313 if (!vcpu->arch.mce_banks)
9314 goto fail_free_pio_data;
9315 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9316
9317 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9318 GFP_KERNEL_ACCOUNT))
9319 goto fail_free_mce_banks;
9320
9321 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9322 GFP_KERNEL_ACCOUNT);
9323 if (!vcpu->arch.user_fpu) {
9324 pr_err("kvm: failed to allocate userspace's fpu\n");
9325 goto free_wbinvd_dirty_mask;
9326 }
9327
9328 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9329 GFP_KERNEL_ACCOUNT);
9330 if (!vcpu->arch.guest_fpu) {
9331 pr_err("kvm: failed to allocate vcpu's fpu\n");
9332 goto free_user_fpu;
9333 }
9334 fx_init(vcpu);
9335
9336 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9337
9338 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9339
9340 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9341
9342 kvm_async_pf_hash_reset(vcpu);
9343 kvm_pmu_init(vcpu);
9344
9345 vcpu->arch.pending_external_vector = -1;
9346 vcpu->arch.preempted_in_kernel = false;
9347
9348 kvm_hv_vcpu_init(vcpu);
9349
9350 r = kvm_x86_ops->vcpu_create(vcpu);
9351 if (r)
9352 goto free_guest_fpu;
9353
9354 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9355 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9356 kvm_vcpu_mtrr_init(vcpu);
9357 vcpu_load(vcpu);
9358 kvm_vcpu_reset(vcpu, false);
9359 kvm_init_mmu(vcpu, false);
9360 vcpu_put(vcpu);
9361 return 0;
9362
9363 free_guest_fpu:
9364 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9365 free_user_fpu:
9366 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9367 free_wbinvd_dirty_mask:
9368 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9369 fail_free_mce_banks:
9370 kfree(vcpu->arch.mce_banks);
9371 fail_free_pio_data:
9372 free_page((unsigned long)vcpu->arch.pio_data);
9373 fail_free_lapic:
9374 kvm_free_lapic(vcpu);
9375 fail_mmu_destroy:
9376 kvm_mmu_destroy(vcpu);
9377 return r;
9378 }
9379
9380 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9381 {
9382 struct msr_data msr;
9383 struct kvm *kvm = vcpu->kvm;
9384
9385 kvm_hv_vcpu_postcreate(vcpu);
9386
9387 if (mutex_lock_killable(&vcpu->mutex))
9388 return;
9389 vcpu_load(vcpu);
9390 msr.data = 0x0;
9391 msr.index = MSR_IA32_TSC;
9392 msr.host_initiated = true;
9393 kvm_write_tsc(vcpu, &msr);
9394 vcpu_put(vcpu);
9395
9396 /* poll control enabled by default */
9397 vcpu->arch.msr_kvm_poll_control = 1;
9398
9399 mutex_unlock(&vcpu->mutex);
9400
9401 if (!kvmclock_periodic_sync)
9402 return;
9403
9404 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9405 KVMCLOCK_SYNC_PERIOD);
9406 }
9407
9408 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9409 {
9410 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9411 int idx;
9412
9413 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9414
9415 kvmclock_reset(vcpu);
9416
9417 kvm_x86_ops->vcpu_free(vcpu);
9418
9419 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9420 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9421 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9422
9423 kvm_hv_vcpu_uninit(vcpu);
9424 kvm_pmu_destroy(vcpu);
9425 kfree(vcpu->arch.mce_banks);
9426 kvm_free_lapic(vcpu);
9427 idx = srcu_read_lock(&vcpu->kvm->srcu);
9428 kvm_mmu_destroy(vcpu);
9429 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9430 free_page((unsigned long)vcpu->arch.pio_data);
9431 if (!lapic_in_kernel(vcpu))
9432 static_key_slow_dec(&kvm_no_apic_vcpu);
9433 }
9434
9435 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9436 {
9437 kvm_lapic_reset(vcpu, init_event);
9438
9439 vcpu->arch.hflags = 0;
9440
9441 vcpu->arch.smi_pending = 0;
9442 vcpu->arch.smi_count = 0;
9443 atomic_set(&vcpu->arch.nmi_queued, 0);
9444 vcpu->arch.nmi_pending = 0;
9445 vcpu->arch.nmi_injected = false;
9446 kvm_clear_interrupt_queue(vcpu);
9447 kvm_clear_exception_queue(vcpu);
9448
9449 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9450 kvm_update_dr0123(vcpu);
9451 vcpu->arch.dr6 = DR6_INIT;
9452 kvm_update_dr6(vcpu);
9453 vcpu->arch.dr7 = DR7_FIXED_1;
9454 kvm_update_dr7(vcpu);
9455
9456 vcpu->arch.cr2 = 0;
9457
9458 kvm_make_request(KVM_REQ_EVENT, vcpu);
9459 vcpu->arch.apf.msr_val = 0;
9460 vcpu->arch.st.msr_val = 0;
9461
9462 kvmclock_reset(vcpu);
9463
9464 kvm_clear_async_pf_completion_queue(vcpu);
9465 kvm_async_pf_hash_reset(vcpu);
9466 vcpu->arch.apf.halted = false;
9467
9468 if (kvm_mpx_supported()) {
9469 void *mpx_state_buffer;
9470
9471 /*
9472 * To avoid have the INIT path from kvm_apic_has_events() that be
9473 * called with loaded FPU and does not let userspace fix the state.
9474 */
9475 if (init_event)
9476 kvm_put_guest_fpu(vcpu);
9477 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9478 XFEATURE_BNDREGS);
9479 if (mpx_state_buffer)
9480 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9481 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9482 XFEATURE_BNDCSR);
9483 if (mpx_state_buffer)
9484 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9485 if (init_event)
9486 kvm_load_guest_fpu(vcpu);
9487 }
9488
9489 if (!init_event) {
9490 kvm_pmu_reset(vcpu);
9491 vcpu->arch.smbase = 0x30000;
9492
9493 vcpu->arch.msr_misc_features_enables = 0;
9494
9495 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9496 }
9497
9498 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9499 vcpu->arch.regs_avail = ~0;
9500 vcpu->arch.regs_dirty = ~0;
9501
9502 vcpu->arch.ia32_xss = 0;
9503
9504 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9505 }
9506
9507 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9508 {
9509 struct kvm_segment cs;
9510
9511 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9512 cs.selector = vector << 8;
9513 cs.base = vector << 12;
9514 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9515 kvm_rip_write(vcpu, 0);
9516 }
9517
9518 int kvm_arch_hardware_enable(void)
9519 {
9520 struct kvm *kvm;
9521 struct kvm_vcpu *vcpu;
9522 int i;
9523 int ret;
9524 u64 local_tsc;
9525 u64 max_tsc = 0;
9526 bool stable, backwards_tsc = false;
9527
9528 kvm_shared_msr_cpu_online();
9529 ret = kvm_x86_ops->hardware_enable();
9530 if (ret != 0)
9531 return ret;
9532
9533 local_tsc = rdtsc();
9534 stable = !kvm_check_tsc_unstable();
9535 list_for_each_entry(kvm, &vm_list, vm_list) {
9536 kvm_for_each_vcpu(i, vcpu, kvm) {
9537 if (!stable && vcpu->cpu == smp_processor_id())
9538 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9539 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9540 backwards_tsc = true;
9541 if (vcpu->arch.last_host_tsc > max_tsc)
9542 max_tsc = vcpu->arch.last_host_tsc;
9543 }
9544 }
9545 }
9546
9547 /*
9548 * Sometimes, even reliable TSCs go backwards. This happens on
9549 * platforms that reset TSC during suspend or hibernate actions, but
9550 * maintain synchronization. We must compensate. Fortunately, we can
9551 * detect that condition here, which happens early in CPU bringup,
9552 * before any KVM threads can be running. Unfortunately, we can't
9553 * bring the TSCs fully up to date with real time, as we aren't yet far
9554 * enough into CPU bringup that we know how much real time has actually
9555 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9556 * variables that haven't been updated yet.
9557 *
9558 * So we simply find the maximum observed TSC above, then record the
9559 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9560 * the adjustment will be applied. Note that we accumulate
9561 * adjustments, in case multiple suspend cycles happen before some VCPU
9562 * gets a chance to run again. In the event that no KVM threads get a
9563 * chance to run, we will miss the entire elapsed period, as we'll have
9564 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9565 * loose cycle time. This isn't too big a deal, since the loss will be
9566 * uniform across all VCPUs (not to mention the scenario is extremely
9567 * unlikely). It is possible that a second hibernate recovery happens
9568 * much faster than a first, causing the observed TSC here to be
9569 * smaller; this would require additional padding adjustment, which is
9570 * why we set last_host_tsc to the local tsc observed here.
9571 *
9572 * N.B. - this code below runs only on platforms with reliable TSC,
9573 * as that is the only way backwards_tsc is set above. Also note
9574 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9575 * have the same delta_cyc adjustment applied if backwards_tsc
9576 * is detected. Note further, this adjustment is only done once,
9577 * as we reset last_host_tsc on all VCPUs to stop this from being
9578 * called multiple times (one for each physical CPU bringup).
9579 *
9580 * Platforms with unreliable TSCs don't have to deal with this, they
9581 * will be compensated by the logic in vcpu_load, which sets the TSC to
9582 * catchup mode. This will catchup all VCPUs to real time, but cannot
9583 * guarantee that they stay in perfect synchronization.
9584 */
9585 if (backwards_tsc) {
9586 u64 delta_cyc = max_tsc - local_tsc;
9587 list_for_each_entry(kvm, &vm_list, vm_list) {
9588 kvm->arch.backwards_tsc_observed = true;
9589 kvm_for_each_vcpu(i, vcpu, kvm) {
9590 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9591 vcpu->arch.last_host_tsc = local_tsc;
9592 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9593 }
9594
9595 /*
9596 * We have to disable TSC offset matching.. if you were
9597 * booting a VM while issuing an S4 host suspend....
9598 * you may have some problem. Solving this issue is
9599 * left as an exercise to the reader.
9600 */
9601 kvm->arch.last_tsc_nsec = 0;
9602 kvm->arch.last_tsc_write = 0;
9603 }
9604
9605 }
9606 return 0;
9607 }
9608
9609 void kvm_arch_hardware_disable(void)
9610 {
9611 kvm_x86_ops->hardware_disable();
9612 drop_user_return_notifiers();
9613 }
9614
9615 int kvm_arch_hardware_setup(void)
9616 {
9617 int r;
9618
9619 r = kvm_x86_ops->hardware_setup();
9620 if (r != 0)
9621 return r;
9622
9623 cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
9624
9625 if (kvm_has_tsc_control) {
9626 /*
9627 * Make sure the user can only configure tsc_khz values that
9628 * fit into a signed integer.
9629 * A min value is not calculated because it will always
9630 * be 1 on all machines.
9631 */
9632 u64 max = min(0x7fffffffULL,
9633 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9634 kvm_max_guest_tsc_khz = max;
9635
9636 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9637 }
9638
9639 if (boot_cpu_has(X86_FEATURE_XSAVES))
9640 rdmsrl(MSR_IA32_XSS, host_xss);
9641
9642 kvm_init_msr_list();
9643 return 0;
9644 }
9645
9646 void kvm_arch_hardware_unsetup(void)
9647 {
9648 kvm_x86_ops->hardware_unsetup();
9649 }
9650
9651 int kvm_arch_check_processor_compat(void)
9652 {
9653 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9654
9655 WARN_ON(!irqs_disabled());
9656
9657 if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits)
9658 return -EIO;
9659
9660 return kvm_x86_ops->check_processor_compatibility();
9661 }
9662
9663 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9664 {
9665 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9666 }
9667 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9668
9669 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9670 {
9671 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9672 }
9673
9674 struct static_key kvm_no_apic_vcpu __read_mostly;
9675 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9676
9677 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9678 {
9679 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9680
9681 vcpu->arch.l1tf_flush_l1d = true;
9682 if (pmu->version && unlikely(pmu->event_count)) {
9683 pmu->need_cleanup = true;
9684 kvm_make_request(KVM_REQ_PMU, vcpu);
9685 }
9686 kvm_x86_ops->sched_in(vcpu, cpu);
9687 }
9688
9689 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9690 {
9691 if (type)
9692 return -EINVAL;
9693
9694 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9695 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9696 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9697 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9698 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9699 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9700
9701 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9702 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9703 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9704 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9705 &kvm->arch.irq_sources_bitmap);
9706
9707 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9708 mutex_init(&kvm->arch.apic_map_lock);
9709 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9710
9711 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9712 pvclock_update_vm_gtod_copy(kvm);
9713
9714 kvm->arch.guest_can_read_msr_platform_info = true;
9715
9716 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9717 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9718
9719 kvm_hv_init_vm(kvm);
9720 kvm_page_track_init(kvm);
9721 kvm_mmu_init_vm(kvm);
9722
9723 return kvm_x86_ops->vm_init(kvm);
9724 }
9725
9726 int kvm_arch_post_init_vm(struct kvm *kvm)
9727 {
9728 return kvm_mmu_post_init_vm(kvm);
9729 }
9730
9731 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9732 {
9733 vcpu_load(vcpu);
9734 kvm_mmu_unload(vcpu);
9735 vcpu_put(vcpu);
9736 }
9737
9738 static void kvm_free_vcpus(struct kvm *kvm)
9739 {
9740 unsigned int i;
9741 struct kvm_vcpu *vcpu;
9742
9743 /*
9744 * Unpin any mmu pages first.
9745 */
9746 kvm_for_each_vcpu(i, vcpu, kvm) {
9747 kvm_clear_async_pf_completion_queue(vcpu);
9748 kvm_unload_vcpu_mmu(vcpu);
9749 }
9750 kvm_for_each_vcpu(i, vcpu, kvm)
9751 kvm_vcpu_destroy(vcpu);
9752
9753 mutex_lock(&kvm->lock);
9754 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9755 kvm->vcpus[i] = NULL;
9756
9757 atomic_set(&kvm->online_vcpus, 0);
9758 mutex_unlock(&kvm->lock);
9759 }
9760
9761 void kvm_arch_sync_events(struct kvm *kvm)
9762 {
9763 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9764 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9765 kvm_free_pit(kvm);
9766 }
9767
9768 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9769 {
9770 int i, r;
9771 unsigned long hva;
9772 struct kvm_memslots *slots = kvm_memslots(kvm);
9773 struct kvm_memory_slot *slot, old;
9774
9775 /* Called with kvm->slots_lock held. */
9776 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9777 return -EINVAL;
9778
9779 slot = id_to_memslot(slots, id);
9780 if (size) {
9781 if (slot->npages)
9782 return -EEXIST;
9783
9784 /*
9785 * MAP_SHARED to prevent internal slot pages from being moved
9786 * by fork()/COW.
9787 */
9788 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9789 MAP_SHARED | MAP_ANONYMOUS, 0);
9790 if (IS_ERR((void *)hva))
9791 return PTR_ERR((void *)hva);
9792 } else {
9793 if (!slot->npages)
9794 return 0;
9795
9796 hva = 0;
9797 }
9798
9799 old = *slot;
9800 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9801 struct kvm_userspace_memory_region m;
9802
9803 m.slot = id | (i << 16);
9804 m.flags = 0;
9805 m.guest_phys_addr = gpa;
9806 m.userspace_addr = hva;
9807 m.memory_size = size;
9808 r = __kvm_set_memory_region(kvm, &m);
9809 if (r < 0)
9810 return r;
9811 }
9812
9813 if (!size)
9814 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9815
9816 return 0;
9817 }
9818 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9819
9820 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9821 {
9822 kvm_mmu_pre_destroy_vm(kvm);
9823 }
9824
9825 void kvm_arch_destroy_vm(struct kvm *kvm)
9826 {
9827 if (current->mm == kvm->mm) {
9828 /*
9829 * Free memory regions allocated on behalf of userspace,
9830 * unless the the memory map has changed due to process exit
9831 * or fd copying.
9832 */
9833 mutex_lock(&kvm->slots_lock);
9834 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9835 0, 0);
9836 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9837 0, 0);
9838 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9839 mutex_unlock(&kvm->slots_lock);
9840 }
9841 if (kvm_x86_ops->vm_destroy)
9842 kvm_x86_ops->vm_destroy(kvm);
9843 kvm_pic_destroy(kvm);
9844 kvm_ioapic_destroy(kvm);
9845 kvm_free_vcpus(kvm);
9846 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9847 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9848 kvm_mmu_uninit_vm(kvm);
9849 kvm_page_track_cleanup(kvm);
9850 kvm_hv_destroy_vm(kvm);
9851 }
9852
9853 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9854 struct kvm_memory_slot *dont)
9855 {
9856 int i;
9857
9858 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9859 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9860 kvfree(free->arch.rmap[i]);
9861 free->arch.rmap[i] = NULL;
9862 }
9863 if (i == 0)
9864 continue;
9865
9866 if (!dont || free->arch.lpage_info[i - 1] !=
9867 dont->arch.lpage_info[i - 1]) {
9868 kvfree(free->arch.lpage_info[i - 1]);
9869 free->arch.lpage_info[i - 1] = NULL;
9870 }
9871 }
9872
9873 kvm_page_track_free_memslot(free, dont);
9874 }
9875
9876 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
9877 unsigned long npages)
9878 {
9879 int i;
9880
9881 /*
9882 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
9883 * old arrays will be freed by __kvm_set_memory_region() if installing
9884 * the new memslot is successful.
9885 */
9886 memset(&slot->arch, 0, sizeof(slot->arch));
9887
9888 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9889 struct kvm_lpage_info *linfo;
9890 unsigned long ugfn;
9891 int lpages;
9892 int level = i + 1;
9893
9894 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9895 slot->base_gfn, level) + 1;
9896
9897 slot->arch.rmap[i] =
9898 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9899 GFP_KERNEL_ACCOUNT);
9900 if (!slot->arch.rmap[i])
9901 goto out_free;
9902 if (i == 0)
9903 continue;
9904
9905 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9906 if (!linfo)
9907 goto out_free;
9908
9909 slot->arch.lpage_info[i - 1] = linfo;
9910
9911 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9912 linfo[0].disallow_lpage = 1;
9913 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9914 linfo[lpages - 1].disallow_lpage = 1;
9915 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9916 /*
9917 * If the gfn and userspace address are not aligned wrt each
9918 * other, or if explicitly asked to, disable large page
9919 * support for this slot
9920 */
9921 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9922 !kvm_largepages_enabled()) {
9923 unsigned long j;
9924
9925 for (j = 0; j < lpages; ++j)
9926 linfo[j].disallow_lpage = 1;
9927 }
9928 }
9929
9930 if (kvm_page_track_create_memslot(slot, npages))
9931 goto out_free;
9932
9933 return 0;
9934
9935 out_free:
9936 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9937 kvfree(slot->arch.rmap[i]);
9938 slot->arch.rmap[i] = NULL;
9939 if (i == 0)
9940 continue;
9941
9942 kvfree(slot->arch.lpage_info[i - 1]);
9943 slot->arch.lpage_info[i - 1] = NULL;
9944 }
9945 return -ENOMEM;
9946 }
9947
9948 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9949 {
9950 struct kvm_vcpu *vcpu;
9951 int i;
9952
9953 /*
9954 * memslots->generation has been incremented.
9955 * mmio generation may have reached its maximum value.
9956 */
9957 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9958
9959 /* Force re-initialization of steal_time cache */
9960 kvm_for_each_vcpu(i, vcpu, kvm)
9961 kvm_vcpu_kick(vcpu);
9962 }
9963
9964 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9965 struct kvm_memory_slot *memslot,
9966 const struct kvm_userspace_memory_region *mem,
9967 enum kvm_mr_change change)
9968 {
9969 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
9970 return kvm_alloc_memslot_metadata(memslot,
9971 mem->memory_size >> PAGE_SHIFT);
9972 return 0;
9973 }
9974
9975 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9976 struct kvm_memory_slot *new)
9977 {
9978 /* Still write protect RO slot */
9979 if (new->flags & KVM_MEM_READONLY) {
9980 kvm_mmu_slot_remove_write_access(kvm, new);
9981 return;
9982 }
9983
9984 /*
9985 * Call kvm_x86_ops dirty logging hooks when they are valid.
9986 *
9987 * kvm_x86_ops->slot_disable_log_dirty is called when:
9988 *
9989 * - KVM_MR_CREATE with dirty logging is disabled
9990 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9991 *
9992 * The reason is, in case of PML, we need to set D-bit for any slots
9993 * with dirty logging disabled in order to eliminate unnecessary GPA
9994 * logging in PML buffer (and potential PML buffer full VMEXIT). This
9995 * guarantees leaving PML enabled during guest's lifetime won't have
9996 * any additional overhead from PML when guest is running with dirty
9997 * logging disabled for memory slots.
9998 *
9999 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
10000 * to dirty logging mode.
10001 *
10002 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
10003 *
10004 * In case of write protect:
10005 *
10006 * Write protect all pages for dirty logging.
10007 *
10008 * All the sptes including the large sptes which point to this
10009 * slot are set to readonly. We can not create any new large
10010 * spte on this slot until the end of the logging.
10011 *
10012 * See the comments in fast_page_fault().
10013 */
10014 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10015 if (kvm_x86_ops->slot_enable_log_dirty)
10016 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
10017 else
10018 kvm_mmu_slot_remove_write_access(kvm, new);
10019 } else {
10020 if (kvm_x86_ops->slot_disable_log_dirty)
10021 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
10022 }
10023 }
10024
10025 void kvm_arch_commit_memory_region(struct kvm *kvm,
10026 const struct kvm_userspace_memory_region *mem,
10027 struct kvm_memory_slot *old,
10028 const struct kvm_memory_slot *new,
10029 enum kvm_mr_change change)
10030 {
10031 if (!kvm->arch.n_requested_mmu_pages)
10032 kvm_mmu_change_mmu_pages(kvm,
10033 kvm_mmu_calculate_default_mmu_pages(kvm));
10034
10035 /*
10036 * Dirty logging tracks sptes in 4k granularity, meaning that large
10037 * sptes have to be split. If live migration is successful, the guest
10038 * in the source machine will be destroyed and large sptes will be
10039 * created in the destination. However, if the guest continues to run
10040 * in the source machine (for example if live migration fails), small
10041 * sptes will remain around and cause bad performance.
10042 *
10043 * Scan sptes if dirty logging has been stopped, dropping those
10044 * which can be collapsed into a single large-page spte. Later
10045 * page faults will create the large-page sptes.
10046 *
10047 * There is no need to do this in any of the following cases:
10048 * CREATE: No dirty mappings will already exist.
10049 * MOVE/DELETE: The old mappings will already have been cleaned up by
10050 * kvm_arch_flush_shadow_memslot()
10051 */
10052 if (change == KVM_MR_FLAGS_ONLY &&
10053 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10054 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10055 kvm_mmu_zap_collapsible_sptes(kvm, new);
10056
10057 /*
10058 * Set up write protection and/or dirty logging for the new slot.
10059 *
10060 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
10061 * been zapped so no dirty logging staff is needed for old slot. For
10062 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
10063 * new and it's also covered when dealing with the new slot.
10064 *
10065 * FIXME: const-ify all uses of struct kvm_memory_slot.
10066 */
10067 if (change != KVM_MR_DELETE)
10068 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
10069 }
10070
10071 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10072 {
10073 kvm_mmu_zap_all(kvm);
10074 }
10075
10076 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10077 struct kvm_memory_slot *slot)
10078 {
10079 kvm_page_track_flush_slot(kvm, slot);
10080 }
10081
10082 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10083 {
10084 return (is_guest_mode(vcpu) &&
10085 kvm_x86_ops->guest_apic_has_interrupt &&
10086 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
10087 }
10088
10089 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10090 {
10091 if (!list_empty_careful(&vcpu->async_pf.done))
10092 return true;
10093
10094 if (kvm_apic_has_events(vcpu))
10095 return true;
10096
10097 if (vcpu->arch.pv.pv_unhalted)
10098 return true;
10099
10100 if (vcpu->arch.exception.pending)
10101 return true;
10102
10103 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10104 (vcpu->arch.nmi_pending &&
10105 kvm_x86_ops->nmi_allowed(vcpu)))
10106 return true;
10107
10108 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10109 (vcpu->arch.smi_pending && !is_smm(vcpu)))
10110 return true;
10111
10112 if (kvm_arch_interrupt_allowed(vcpu) &&
10113 (kvm_cpu_has_interrupt(vcpu) ||
10114 kvm_guest_apic_has_interrupt(vcpu)))
10115 return true;
10116
10117 if (kvm_hv_has_stimer_pending(vcpu))
10118 return true;
10119
10120 return false;
10121 }
10122
10123 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10124 {
10125 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10126 }
10127
10128 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10129 {
10130 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10131 return true;
10132
10133 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10134 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10135 kvm_test_request(KVM_REQ_EVENT, vcpu))
10136 return true;
10137
10138 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
10139 return true;
10140
10141 return false;
10142 }
10143
10144 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10145 {
10146 return vcpu->arch.preempted_in_kernel;
10147 }
10148
10149 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10150 {
10151 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10152 }
10153
10154 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10155 {
10156 return kvm_x86_ops->interrupt_allowed(vcpu);
10157 }
10158
10159 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10160 {
10161 if (is_64_bit_mode(vcpu))
10162 return kvm_rip_read(vcpu);
10163 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10164 kvm_rip_read(vcpu));
10165 }
10166 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10167
10168 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10169 {
10170 return kvm_get_linear_rip(vcpu) == linear_rip;
10171 }
10172 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10173
10174 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10175 {
10176 unsigned long rflags;
10177
10178 rflags = kvm_x86_ops->get_rflags(vcpu);
10179 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10180 rflags &= ~X86_EFLAGS_TF;
10181 return rflags;
10182 }
10183 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10184
10185 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10186 {
10187 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10188 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10189 rflags |= X86_EFLAGS_TF;
10190 kvm_x86_ops->set_rflags(vcpu, rflags);
10191 }
10192
10193 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10194 {
10195 __kvm_set_rflags(vcpu, rflags);
10196 kvm_make_request(KVM_REQ_EVENT, vcpu);
10197 }
10198 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10199
10200 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10201 {
10202 int r;
10203
10204 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10205 work->wakeup_all)
10206 return;
10207
10208 r = kvm_mmu_reload(vcpu);
10209 if (unlikely(r))
10210 return;
10211
10212 if (!vcpu->arch.mmu->direct_map &&
10213 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
10214 return;
10215
10216 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10217 }
10218
10219 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10220 {
10221 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10222 }
10223
10224 static inline u32 kvm_async_pf_next_probe(u32 key)
10225 {
10226 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10227 }
10228
10229 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10230 {
10231 u32 key = kvm_async_pf_hash_fn(gfn);
10232
10233 while (vcpu->arch.apf.gfns[key] != ~0)
10234 key = kvm_async_pf_next_probe(key);
10235
10236 vcpu->arch.apf.gfns[key] = gfn;
10237 }
10238
10239 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10240 {
10241 int i;
10242 u32 key = kvm_async_pf_hash_fn(gfn);
10243
10244 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10245 (vcpu->arch.apf.gfns[key] != gfn &&
10246 vcpu->arch.apf.gfns[key] != ~0); i++)
10247 key = kvm_async_pf_next_probe(key);
10248
10249 return key;
10250 }
10251
10252 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10253 {
10254 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10255 }
10256
10257 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10258 {
10259 u32 i, j, k;
10260
10261 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10262 while (true) {
10263 vcpu->arch.apf.gfns[i] = ~0;
10264 do {
10265 j = kvm_async_pf_next_probe(j);
10266 if (vcpu->arch.apf.gfns[j] == ~0)
10267 return;
10268 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10269 /*
10270 * k lies cyclically in ]i,j]
10271 * | i.k.j |
10272 * |....j i.k.| or |.k..j i...|
10273 */
10274 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10275 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10276 i = j;
10277 }
10278 }
10279
10280 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10281 {
10282
10283 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10284 sizeof(val));
10285 }
10286
10287 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10288 {
10289
10290 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10291 sizeof(u32));
10292 }
10293
10294 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10295 {
10296 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10297 return false;
10298
10299 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10300 (vcpu->arch.apf.send_user_only &&
10301 kvm_x86_ops->get_cpl(vcpu) == 0))
10302 return false;
10303
10304 return true;
10305 }
10306
10307 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10308 {
10309 if (unlikely(!lapic_in_kernel(vcpu) ||
10310 kvm_event_needs_reinjection(vcpu) ||
10311 vcpu->arch.exception.pending))
10312 return false;
10313
10314 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10315 return false;
10316
10317 /*
10318 * If interrupts are off we cannot even use an artificial
10319 * halt state.
10320 */
10321 return kvm_x86_ops->interrupt_allowed(vcpu);
10322 }
10323
10324 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10325 struct kvm_async_pf *work)
10326 {
10327 struct x86_exception fault;
10328
10329 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10330 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10331
10332 if (kvm_can_deliver_async_pf(vcpu) &&
10333 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10334 fault.vector = PF_VECTOR;
10335 fault.error_code_valid = true;
10336 fault.error_code = 0;
10337 fault.nested_page_fault = false;
10338 fault.address = work->arch.token;
10339 fault.async_page_fault = true;
10340 kvm_inject_page_fault(vcpu, &fault);
10341 } else {
10342 /*
10343 * It is not possible to deliver a paravirtualized asynchronous
10344 * page fault, but putting the guest in an artificial halt state
10345 * can be beneficial nevertheless: if an interrupt arrives, we
10346 * can deliver it timely and perhaps the guest will schedule
10347 * another process. When the instruction that triggered a page
10348 * fault is retried, hopefully the page will be ready in the host.
10349 */
10350 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10351 }
10352 }
10353
10354 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10355 struct kvm_async_pf *work)
10356 {
10357 struct x86_exception fault;
10358 u32 val;
10359
10360 if (work->wakeup_all)
10361 work->arch.token = ~0; /* broadcast wakeup */
10362 else
10363 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10364 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10365
10366 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10367 !apf_get_user(vcpu, &val)) {
10368 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10369 vcpu->arch.exception.pending &&
10370 vcpu->arch.exception.nr == PF_VECTOR &&
10371 !apf_put_user(vcpu, 0)) {
10372 vcpu->arch.exception.injected = false;
10373 vcpu->arch.exception.pending = false;
10374 vcpu->arch.exception.nr = 0;
10375 vcpu->arch.exception.has_error_code = false;
10376 vcpu->arch.exception.error_code = 0;
10377 vcpu->arch.exception.has_payload = false;
10378 vcpu->arch.exception.payload = 0;
10379 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10380 fault.vector = PF_VECTOR;
10381 fault.error_code_valid = true;
10382 fault.error_code = 0;
10383 fault.nested_page_fault = false;
10384 fault.address = work->arch.token;
10385 fault.async_page_fault = true;
10386 kvm_inject_page_fault(vcpu, &fault);
10387 }
10388 }
10389 vcpu->arch.apf.halted = false;
10390 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10391 }
10392
10393 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10394 {
10395 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10396 return true;
10397 else
10398 return kvm_can_do_async_pf(vcpu);
10399 }
10400
10401 void kvm_arch_start_assignment(struct kvm *kvm)
10402 {
10403 atomic_inc(&kvm->arch.assigned_device_count);
10404 }
10405 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10406
10407 void kvm_arch_end_assignment(struct kvm *kvm)
10408 {
10409 atomic_dec(&kvm->arch.assigned_device_count);
10410 }
10411 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10412
10413 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10414 {
10415 return atomic_read(&kvm->arch.assigned_device_count);
10416 }
10417 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10418
10419 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10420 {
10421 atomic_inc(&kvm->arch.noncoherent_dma_count);
10422 }
10423 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10424
10425 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10426 {
10427 atomic_dec(&kvm->arch.noncoherent_dma_count);
10428 }
10429 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10430
10431 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10432 {
10433 return atomic_read(&kvm->arch.noncoherent_dma_count);
10434 }
10435 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10436
10437 bool kvm_arch_has_irq_bypass(void)
10438 {
10439 return true;
10440 }
10441
10442 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10443 struct irq_bypass_producer *prod)
10444 {
10445 struct kvm_kernel_irqfd *irqfd =
10446 container_of(cons, struct kvm_kernel_irqfd, consumer);
10447
10448 irqfd->producer = prod;
10449
10450 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10451 prod->irq, irqfd->gsi, 1);
10452 }
10453
10454 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10455 struct irq_bypass_producer *prod)
10456 {
10457 int ret;
10458 struct kvm_kernel_irqfd *irqfd =
10459 container_of(cons, struct kvm_kernel_irqfd, consumer);
10460
10461 WARN_ON(irqfd->producer != prod);
10462 irqfd->producer = NULL;
10463
10464 /*
10465 * When producer of consumer is unregistered, we change back to
10466 * remapped mode, so we can re-use the current implementation
10467 * when the irq is masked/disabled or the consumer side (KVM
10468 * int this case doesn't want to receive the interrupts.
10469 */
10470 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10471 if (ret)
10472 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10473 " fails: %d\n", irqfd->consumer.token, ret);
10474 }
10475
10476 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10477 uint32_t guest_irq, bool set)
10478 {
10479 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10480 }
10481
10482 bool kvm_vector_hashing_enabled(void)
10483 {
10484 return vector_hashing;
10485 }
10486
10487 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10488 {
10489 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10490 }
10491 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10492
10493 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10494 {
10495 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10496
10497 /* The STIBP bit doesn't fault even if it's not advertised */
10498 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10499 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10500 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10501 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10502 !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10503 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10504
10505 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10506 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10507 bits &= ~SPEC_CTRL_SSBD;
10508 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10509 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10510 bits &= ~SPEC_CTRL_SSBD;
10511
10512 return bits;
10513 }
10514 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10515
10516 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10517 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10518 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10519 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10520 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10521 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10522 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10523 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10524 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10525 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10526 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10527 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10528 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10529 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10530 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10531 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10532 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10533 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10534 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10535 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10536 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
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