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KVM: x86: Emulate IA32_TSC_ADJUST MSR
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 bool kvm_has_tsc_control;
98 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99 u32 kvm_max_guest_tsc_khz;
100 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
102 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103 static u32 tsc_tolerance_ppm = 250;
104 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
106 #define KVM_NR_SHARED_MSRS 16
107
108 struct kvm_shared_msrs_global {
109 int nr;
110 u32 msrs[KVM_NR_SHARED_MSRS];
111 };
112
113 struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
120 };
121
122 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
124
125 struct kvm_stats_debugfs_item debugfs_entries[] = {
126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
138 { "hypercalls", VCPU_STAT(hypercalls) },
139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
146 { "irq_injections", VCPU_STAT(irq_injections) },
147 { "nmi_injections", VCPU_STAT(nmi_injections) },
148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
155 { "mmu_unsync", VM_STAT(mmu_unsync) },
156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
157 { "largepages", VM_STAT(lpages) },
158 { NULL }
159 };
160
161 u64 __read_mostly host_xcr0;
162
163 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
164
165 static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
166
167 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
168 {
169 int i;
170 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
171 vcpu->arch.apf.gfns[i] = ~0;
172 }
173
174 static void kvm_on_user_return(struct user_return_notifier *urn)
175 {
176 unsigned slot;
177 struct kvm_shared_msrs *locals
178 = container_of(urn, struct kvm_shared_msrs, urn);
179 struct kvm_shared_msr_values *values;
180
181 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
182 values = &locals->values[slot];
183 if (values->host != values->curr) {
184 wrmsrl(shared_msrs_global.msrs[slot], values->host);
185 values->curr = values->host;
186 }
187 }
188 locals->registered = false;
189 user_return_notifier_unregister(urn);
190 }
191
192 static void shared_msr_update(unsigned slot, u32 msr)
193 {
194 struct kvm_shared_msrs *smsr;
195 u64 value;
196
197 smsr = &__get_cpu_var(shared_msrs);
198 /* only read, and nobody should modify it at this time,
199 * so don't need lock */
200 if (slot >= shared_msrs_global.nr) {
201 printk(KERN_ERR "kvm: invalid MSR slot!");
202 return;
203 }
204 rdmsrl_safe(msr, &value);
205 smsr->values[slot].host = value;
206 smsr->values[slot].curr = value;
207 }
208
209 void kvm_define_shared_msr(unsigned slot, u32 msr)
210 {
211 if (slot >= shared_msrs_global.nr)
212 shared_msrs_global.nr = slot + 1;
213 shared_msrs_global.msrs[slot] = msr;
214 /* we need ensured the shared_msr_global have been updated */
215 smp_wmb();
216 }
217 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
218
219 static void kvm_shared_msr_cpu_online(void)
220 {
221 unsigned i;
222
223 for (i = 0; i < shared_msrs_global.nr; ++i)
224 shared_msr_update(i, shared_msrs_global.msrs[i]);
225 }
226
227 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
228 {
229 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
230
231 if (((value ^ smsr->values[slot].curr) & mask) == 0)
232 return;
233 smsr->values[slot].curr = value;
234 wrmsrl(shared_msrs_global.msrs[slot], value);
235 if (!smsr->registered) {
236 smsr->urn.on_user_return = kvm_on_user_return;
237 user_return_notifier_register(&smsr->urn);
238 smsr->registered = true;
239 }
240 }
241 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
242
243 static void drop_user_return_notifiers(void *ignore)
244 {
245 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249 }
250
251 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252 {
253 return vcpu->arch.apic_base;
254 }
255 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258 {
259 /* TODO: reserve bits check */
260 kvm_lapic_set_base(vcpu, data);
261 }
262 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
264 #define EXCPT_BENIGN 0
265 #define EXCPT_CONTRIBUTORY 1
266 #define EXCPT_PF 2
267
268 static int exception_class(int vector)
269 {
270 switch (vector) {
271 case PF_VECTOR:
272 return EXCPT_PF;
273 case DE_VECTOR:
274 case TS_VECTOR:
275 case NP_VECTOR:
276 case SS_VECTOR:
277 case GP_VECTOR:
278 return EXCPT_CONTRIBUTORY;
279 default:
280 break;
281 }
282 return EXCPT_BENIGN;
283 }
284
285 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
286 unsigned nr, bool has_error, u32 error_code,
287 bool reinject)
288 {
289 u32 prev_nr;
290 int class1, class2;
291
292 kvm_make_request(KVM_REQ_EVENT, vcpu);
293
294 if (!vcpu->arch.exception.pending) {
295 queue:
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = has_error;
298 vcpu->arch.exception.nr = nr;
299 vcpu->arch.exception.error_code = error_code;
300 vcpu->arch.exception.reinject = reinject;
301 return;
302 }
303
304 /* to check exception */
305 prev_nr = vcpu->arch.exception.nr;
306 if (prev_nr == DF_VECTOR) {
307 /* triple fault -> shutdown */
308 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
309 return;
310 }
311 class1 = exception_class(prev_nr);
312 class2 = exception_class(nr);
313 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
314 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
315 /* generate double fault per SDM Table 5-5 */
316 vcpu->arch.exception.pending = true;
317 vcpu->arch.exception.has_error_code = true;
318 vcpu->arch.exception.nr = DF_VECTOR;
319 vcpu->arch.exception.error_code = 0;
320 } else
321 /* replace previous exception with a new one in a hope
322 that instruction re-execution will regenerate lost
323 exception */
324 goto queue;
325 }
326
327 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
328 {
329 kvm_multiple_exception(vcpu, nr, false, 0, false);
330 }
331 EXPORT_SYMBOL_GPL(kvm_queue_exception);
332
333 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
334 {
335 kvm_multiple_exception(vcpu, nr, false, 0, true);
336 }
337 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
338
339 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
340 {
341 if (err)
342 kvm_inject_gp(vcpu, 0);
343 else
344 kvm_x86_ops->skip_emulated_instruction(vcpu);
345 }
346 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
347
348 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
349 {
350 ++vcpu->stat.pf_guest;
351 vcpu->arch.cr2 = fault->address;
352 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
353 }
354 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
355
356 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
357 {
358 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
359 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
360 else
361 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
362 }
363
364 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
365 {
366 atomic_inc(&vcpu->arch.nmi_queued);
367 kvm_make_request(KVM_REQ_NMI, vcpu);
368 }
369 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
370
371 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
372 {
373 kvm_multiple_exception(vcpu, nr, true, error_code, false);
374 }
375 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
376
377 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
378 {
379 kvm_multiple_exception(vcpu, nr, true, error_code, true);
380 }
381 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
382
383 /*
384 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
385 * a #GP and return false.
386 */
387 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
388 {
389 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
390 return true;
391 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
392 return false;
393 }
394 EXPORT_SYMBOL_GPL(kvm_require_cpl);
395
396 /*
397 * This function will be used to read from the physical memory of the currently
398 * running guest. The difference to kvm_read_guest_page is that this function
399 * can read from guest physical or from the guest's guest physical memory.
400 */
401 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
402 gfn_t ngfn, void *data, int offset, int len,
403 u32 access)
404 {
405 gfn_t real_gfn;
406 gpa_t ngpa;
407
408 ngpa = gfn_to_gpa(ngfn);
409 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
410 if (real_gfn == UNMAPPED_GVA)
411 return -EFAULT;
412
413 real_gfn = gpa_to_gfn(real_gfn);
414
415 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
416 }
417 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
418
419 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
420 void *data, int offset, int len, u32 access)
421 {
422 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
423 data, offset, len, access);
424 }
425
426 /*
427 * Load the pae pdptrs. Return true is they are all valid.
428 */
429 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
430 {
431 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
432 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
433 int i;
434 int ret;
435 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
436
437 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
438 offset * sizeof(u64), sizeof(pdpte),
439 PFERR_USER_MASK|PFERR_WRITE_MASK);
440 if (ret < 0) {
441 ret = 0;
442 goto out;
443 }
444 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
445 if (is_present_gpte(pdpte[i]) &&
446 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
447 ret = 0;
448 goto out;
449 }
450 }
451 ret = 1;
452
453 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
454 __set_bit(VCPU_EXREG_PDPTR,
455 (unsigned long *)&vcpu->arch.regs_avail);
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_dirty);
458 out:
459
460 return ret;
461 }
462 EXPORT_SYMBOL_GPL(load_pdptrs);
463
464 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
465 {
466 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
467 bool changed = true;
468 int offset;
469 gfn_t gfn;
470 int r;
471
472 if (is_long_mode(vcpu) || !is_pae(vcpu))
473 return false;
474
475 if (!test_bit(VCPU_EXREG_PDPTR,
476 (unsigned long *)&vcpu->arch.regs_avail))
477 return true;
478
479 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
480 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
481 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
482 PFERR_USER_MASK | PFERR_WRITE_MASK);
483 if (r < 0)
484 goto out;
485 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
486 out:
487
488 return changed;
489 }
490
491 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
492 {
493 unsigned long old_cr0 = kvm_read_cr0(vcpu);
494 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
495 X86_CR0_CD | X86_CR0_NW;
496
497 cr0 |= X86_CR0_ET;
498
499 #ifdef CONFIG_X86_64
500 if (cr0 & 0xffffffff00000000UL)
501 return 1;
502 #endif
503
504 cr0 &= ~CR0_RESERVED_BITS;
505
506 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
507 return 1;
508
509 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
510 return 1;
511
512 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
513 #ifdef CONFIG_X86_64
514 if ((vcpu->arch.efer & EFER_LME)) {
515 int cs_db, cs_l;
516
517 if (!is_pae(vcpu))
518 return 1;
519 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
520 if (cs_l)
521 return 1;
522 } else
523 #endif
524 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
525 kvm_read_cr3(vcpu)))
526 return 1;
527 }
528
529 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
530 return 1;
531
532 kvm_x86_ops->set_cr0(vcpu, cr0);
533
534 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
535 kvm_clear_async_pf_completion_queue(vcpu);
536 kvm_async_pf_hash_reset(vcpu);
537 }
538
539 if ((cr0 ^ old_cr0) & update_bits)
540 kvm_mmu_reset_context(vcpu);
541 return 0;
542 }
543 EXPORT_SYMBOL_GPL(kvm_set_cr0);
544
545 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
546 {
547 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
548 }
549 EXPORT_SYMBOL_GPL(kvm_lmsw);
550
551 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
552 {
553 u64 xcr0;
554
555 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
556 if (index != XCR_XFEATURE_ENABLED_MASK)
557 return 1;
558 xcr0 = xcr;
559 if (kvm_x86_ops->get_cpl(vcpu) != 0)
560 return 1;
561 if (!(xcr0 & XSTATE_FP))
562 return 1;
563 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
564 return 1;
565 if (xcr0 & ~host_xcr0)
566 return 1;
567 vcpu->arch.xcr0 = xcr0;
568 vcpu->guest_xcr0_loaded = 0;
569 return 0;
570 }
571
572 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
573 {
574 if (__kvm_set_xcr(vcpu, index, xcr)) {
575 kvm_inject_gp(vcpu, 0);
576 return 1;
577 }
578 return 0;
579 }
580 EXPORT_SYMBOL_GPL(kvm_set_xcr);
581
582 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
583 {
584 unsigned long old_cr4 = kvm_read_cr4(vcpu);
585 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
586 X86_CR4_PAE | X86_CR4_SMEP;
587 if (cr4 & CR4_RESERVED_BITS)
588 return 1;
589
590 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
591 return 1;
592
593 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
594 return 1;
595
596 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
597 return 1;
598
599 if (is_long_mode(vcpu)) {
600 if (!(cr4 & X86_CR4_PAE))
601 return 1;
602 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
603 && ((cr4 ^ old_cr4) & pdptr_bits)
604 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
605 kvm_read_cr3(vcpu)))
606 return 1;
607
608 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
609 if (!guest_cpuid_has_pcid(vcpu))
610 return 1;
611
612 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
613 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
614 return 1;
615 }
616
617 if (kvm_x86_ops->set_cr4(vcpu, cr4))
618 return 1;
619
620 if (((cr4 ^ old_cr4) & pdptr_bits) ||
621 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
622 kvm_mmu_reset_context(vcpu);
623
624 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
625 kvm_update_cpuid(vcpu);
626
627 return 0;
628 }
629 EXPORT_SYMBOL_GPL(kvm_set_cr4);
630
631 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
632 {
633 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
634 kvm_mmu_sync_roots(vcpu);
635 kvm_mmu_flush_tlb(vcpu);
636 return 0;
637 }
638
639 if (is_long_mode(vcpu)) {
640 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
641 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
642 return 1;
643 } else
644 if (cr3 & CR3_L_MODE_RESERVED_BITS)
645 return 1;
646 } else {
647 if (is_pae(vcpu)) {
648 if (cr3 & CR3_PAE_RESERVED_BITS)
649 return 1;
650 if (is_paging(vcpu) &&
651 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
652 return 1;
653 }
654 /*
655 * We don't check reserved bits in nonpae mode, because
656 * this isn't enforced, and VMware depends on this.
657 */
658 }
659
660 /*
661 * Does the new cr3 value map to physical memory? (Note, we
662 * catch an invalid cr3 even in real-mode, because it would
663 * cause trouble later on when we turn on paging anyway.)
664 *
665 * A real CPU would silently accept an invalid cr3 and would
666 * attempt to use it - with largely undefined (and often hard
667 * to debug) behavior on the guest side.
668 */
669 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
670 return 1;
671 vcpu->arch.cr3 = cr3;
672 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
673 vcpu->arch.mmu.new_cr3(vcpu);
674 return 0;
675 }
676 EXPORT_SYMBOL_GPL(kvm_set_cr3);
677
678 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
679 {
680 if (cr8 & CR8_RESERVED_BITS)
681 return 1;
682 if (irqchip_in_kernel(vcpu->kvm))
683 kvm_lapic_set_tpr(vcpu, cr8);
684 else
685 vcpu->arch.cr8 = cr8;
686 return 0;
687 }
688 EXPORT_SYMBOL_GPL(kvm_set_cr8);
689
690 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
691 {
692 if (irqchip_in_kernel(vcpu->kvm))
693 return kvm_lapic_get_cr8(vcpu);
694 else
695 return vcpu->arch.cr8;
696 }
697 EXPORT_SYMBOL_GPL(kvm_get_cr8);
698
699 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
700 {
701 unsigned long dr7;
702
703 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
704 dr7 = vcpu->arch.guest_debug_dr7;
705 else
706 dr7 = vcpu->arch.dr7;
707 kvm_x86_ops->set_dr7(vcpu, dr7);
708 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
709 }
710
711 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
712 {
713 switch (dr) {
714 case 0 ... 3:
715 vcpu->arch.db[dr] = val;
716 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
717 vcpu->arch.eff_db[dr] = val;
718 break;
719 case 4:
720 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
721 return 1; /* #UD */
722 /* fall through */
723 case 6:
724 if (val & 0xffffffff00000000ULL)
725 return -1; /* #GP */
726 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
727 break;
728 case 5:
729 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
730 return 1; /* #UD */
731 /* fall through */
732 default: /* 7 */
733 if (val & 0xffffffff00000000ULL)
734 return -1; /* #GP */
735 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
736 kvm_update_dr7(vcpu);
737 break;
738 }
739
740 return 0;
741 }
742
743 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
744 {
745 int res;
746
747 res = __kvm_set_dr(vcpu, dr, val);
748 if (res > 0)
749 kvm_queue_exception(vcpu, UD_VECTOR);
750 else if (res < 0)
751 kvm_inject_gp(vcpu, 0);
752
753 return res;
754 }
755 EXPORT_SYMBOL_GPL(kvm_set_dr);
756
757 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
758 {
759 switch (dr) {
760 case 0 ... 3:
761 *val = vcpu->arch.db[dr];
762 break;
763 case 4:
764 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
765 return 1;
766 /* fall through */
767 case 6:
768 *val = vcpu->arch.dr6;
769 break;
770 case 5:
771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
772 return 1;
773 /* fall through */
774 default: /* 7 */
775 *val = vcpu->arch.dr7;
776 break;
777 }
778
779 return 0;
780 }
781
782 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
783 {
784 if (_kvm_get_dr(vcpu, dr, val)) {
785 kvm_queue_exception(vcpu, UD_VECTOR);
786 return 1;
787 }
788 return 0;
789 }
790 EXPORT_SYMBOL_GPL(kvm_get_dr);
791
792 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
793 {
794 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
795 u64 data;
796 int err;
797
798 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
799 if (err)
800 return err;
801 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
802 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
803 return err;
804 }
805 EXPORT_SYMBOL_GPL(kvm_rdpmc);
806
807 /*
808 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
809 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
810 *
811 * This list is modified at module load time to reflect the
812 * capabilities of the host cpu. This capabilities test skips MSRs that are
813 * kvm-specific. Those are put in the beginning of the list.
814 */
815
816 #define KVM_SAVE_MSRS_BEGIN 10
817 static u32 msrs_to_save[] = {
818 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
819 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
820 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
821 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
822 MSR_KVM_PV_EOI_EN,
823 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
824 MSR_STAR,
825 #ifdef CONFIG_X86_64
826 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
827 #endif
828 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
829 };
830
831 static unsigned num_msrs_to_save;
832
833 static const u32 emulated_msrs[] = {
834 MSR_IA32_TSC_ADJUST,
835 MSR_IA32_TSCDEADLINE,
836 MSR_IA32_MISC_ENABLE,
837 MSR_IA32_MCG_STATUS,
838 MSR_IA32_MCG_CTL,
839 };
840
841 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
842 {
843 u64 old_efer = vcpu->arch.efer;
844
845 if (efer & efer_reserved_bits)
846 return 1;
847
848 if (is_paging(vcpu)
849 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
850 return 1;
851
852 if (efer & EFER_FFXSR) {
853 struct kvm_cpuid_entry2 *feat;
854
855 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
856 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
857 return 1;
858 }
859
860 if (efer & EFER_SVME) {
861 struct kvm_cpuid_entry2 *feat;
862
863 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
864 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
865 return 1;
866 }
867
868 efer &= ~EFER_LMA;
869 efer |= vcpu->arch.efer & EFER_LMA;
870
871 kvm_x86_ops->set_efer(vcpu, efer);
872
873 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
874
875 /* Update reserved bits */
876 if ((efer ^ old_efer) & EFER_NX)
877 kvm_mmu_reset_context(vcpu);
878
879 return 0;
880 }
881
882 void kvm_enable_efer_bits(u64 mask)
883 {
884 efer_reserved_bits &= ~mask;
885 }
886 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
887
888
889 /*
890 * Writes msr value into into the appropriate "register".
891 * Returns 0 on success, non-0 otherwise.
892 * Assumes vcpu_load() was already called.
893 */
894 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
895 {
896 return kvm_x86_ops->set_msr(vcpu, msr);
897 }
898
899 /*
900 * Adapt set_msr() to msr_io()'s calling convention
901 */
902 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
903 {
904 struct msr_data msr;
905
906 msr.data = *data;
907 msr.index = index;
908 msr.host_initiated = true;
909 return kvm_set_msr(vcpu, &msr);
910 }
911
912 #ifdef CONFIG_X86_64
913 struct pvclock_gtod_data {
914 seqcount_t seq;
915
916 struct { /* extract of a clocksource struct */
917 int vclock_mode;
918 cycle_t cycle_last;
919 cycle_t mask;
920 u32 mult;
921 u32 shift;
922 } clock;
923
924 /* open coded 'struct timespec' */
925 u64 monotonic_time_snsec;
926 time_t monotonic_time_sec;
927 };
928
929 static struct pvclock_gtod_data pvclock_gtod_data;
930
931 static void update_pvclock_gtod(struct timekeeper *tk)
932 {
933 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
934
935 write_seqcount_begin(&vdata->seq);
936
937 /* copy pvclock gtod data */
938 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
939 vdata->clock.cycle_last = tk->clock->cycle_last;
940 vdata->clock.mask = tk->clock->mask;
941 vdata->clock.mult = tk->mult;
942 vdata->clock.shift = tk->shift;
943
944 vdata->monotonic_time_sec = tk->xtime_sec
945 + tk->wall_to_monotonic.tv_sec;
946 vdata->monotonic_time_snsec = tk->xtime_nsec
947 + (tk->wall_to_monotonic.tv_nsec
948 << tk->shift);
949 while (vdata->monotonic_time_snsec >=
950 (((u64)NSEC_PER_SEC) << tk->shift)) {
951 vdata->monotonic_time_snsec -=
952 ((u64)NSEC_PER_SEC) << tk->shift;
953 vdata->monotonic_time_sec++;
954 }
955
956 write_seqcount_end(&vdata->seq);
957 }
958 #endif
959
960
961 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
962 {
963 int version;
964 int r;
965 struct pvclock_wall_clock wc;
966 struct timespec boot;
967
968 if (!wall_clock)
969 return;
970
971 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
972 if (r)
973 return;
974
975 if (version & 1)
976 ++version; /* first time write, random junk */
977
978 ++version;
979
980 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
981
982 /*
983 * The guest calculates current wall clock time by adding
984 * system time (updated by kvm_guest_time_update below) to the
985 * wall clock specified here. guest system time equals host
986 * system time for us, thus we must fill in host boot time here.
987 */
988 getboottime(&boot);
989
990 if (kvm->arch.kvmclock_offset) {
991 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
992 boot = timespec_sub(boot, ts);
993 }
994 wc.sec = boot.tv_sec;
995 wc.nsec = boot.tv_nsec;
996 wc.version = version;
997
998 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
999
1000 version++;
1001 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1002 }
1003
1004 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1005 {
1006 uint32_t quotient, remainder;
1007
1008 /* Don't try to replace with do_div(), this one calculates
1009 * "(dividend << 32) / divisor" */
1010 __asm__ ( "divl %4"
1011 : "=a" (quotient), "=d" (remainder)
1012 : "0" (0), "1" (dividend), "r" (divisor) );
1013 return quotient;
1014 }
1015
1016 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1017 s8 *pshift, u32 *pmultiplier)
1018 {
1019 uint64_t scaled64;
1020 int32_t shift = 0;
1021 uint64_t tps64;
1022 uint32_t tps32;
1023
1024 tps64 = base_khz * 1000LL;
1025 scaled64 = scaled_khz * 1000LL;
1026 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1027 tps64 >>= 1;
1028 shift--;
1029 }
1030
1031 tps32 = (uint32_t)tps64;
1032 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1033 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1034 scaled64 >>= 1;
1035 else
1036 tps32 <<= 1;
1037 shift++;
1038 }
1039
1040 *pshift = shift;
1041 *pmultiplier = div_frac(scaled64, tps32);
1042
1043 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1044 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1045 }
1046
1047 static inline u64 get_kernel_ns(void)
1048 {
1049 struct timespec ts;
1050
1051 WARN_ON(preemptible());
1052 ktime_get_ts(&ts);
1053 monotonic_to_bootbased(&ts);
1054 return timespec_to_ns(&ts);
1055 }
1056
1057 #ifdef CONFIG_X86_64
1058 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1059 #endif
1060
1061 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1062 unsigned long max_tsc_khz;
1063
1064 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1065 {
1066 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1067 vcpu->arch.virtual_tsc_shift);
1068 }
1069
1070 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1071 {
1072 u64 v = (u64)khz * (1000000 + ppm);
1073 do_div(v, 1000000);
1074 return v;
1075 }
1076
1077 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1078 {
1079 u32 thresh_lo, thresh_hi;
1080 int use_scaling = 0;
1081
1082 /* Compute a scale to convert nanoseconds in TSC cycles */
1083 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1084 &vcpu->arch.virtual_tsc_shift,
1085 &vcpu->arch.virtual_tsc_mult);
1086 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1087
1088 /*
1089 * Compute the variation in TSC rate which is acceptable
1090 * within the range of tolerance and decide if the
1091 * rate being applied is within that bounds of the hardware
1092 * rate. If so, no scaling or compensation need be done.
1093 */
1094 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1095 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1096 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1097 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1098 use_scaling = 1;
1099 }
1100 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1101 }
1102
1103 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1104 {
1105 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1106 vcpu->arch.virtual_tsc_mult,
1107 vcpu->arch.virtual_tsc_shift);
1108 tsc += vcpu->arch.this_tsc_write;
1109 return tsc;
1110 }
1111
1112 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1113 {
1114 #ifdef CONFIG_X86_64
1115 bool vcpus_matched;
1116 bool do_request = false;
1117 struct kvm_arch *ka = &vcpu->kvm->arch;
1118 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1119
1120 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1121 atomic_read(&vcpu->kvm->online_vcpus));
1122
1123 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1124 if (!ka->use_master_clock)
1125 do_request = 1;
1126
1127 if (!vcpus_matched && ka->use_master_clock)
1128 do_request = 1;
1129
1130 if (do_request)
1131 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1132
1133 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1134 atomic_read(&vcpu->kvm->online_vcpus),
1135 ka->use_master_clock, gtod->clock.vclock_mode);
1136 #endif
1137 }
1138
1139 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1140 {
1141 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1142 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1143 }
1144
1145 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1146 {
1147 struct kvm *kvm = vcpu->kvm;
1148 u64 offset, ns, elapsed;
1149 unsigned long flags;
1150 s64 usdiff;
1151 bool matched;
1152 u64 data = msr->data;
1153
1154 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1155 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1156 ns = get_kernel_ns();
1157 elapsed = ns - kvm->arch.last_tsc_nsec;
1158
1159 /* n.b - signed multiplication and division required */
1160 usdiff = data - kvm->arch.last_tsc_write;
1161 #ifdef CONFIG_X86_64
1162 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1163 #else
1164 /* do_div() only does unsigned */
1165 asm("idivl %2; xor %%edx, %%edx"
1166 : "=A"(usdiff)
1167 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1168 #endif
1169 do_div(elapsed, 1000);
1170 usdiff -= elapsed;
1171 if (usdiff < 0)
1172 usdiff = -usdiff;
1173
1174 /*
1175 * Special case: TSC write with a small delta (1 second) of virtual
1176 * cycle time against real time is interpreted as an attempt to
1177 * synchronize the CPU.
1178 *
1179 * For a reliable TSC, we can match TSC offsets, and for an unstable
1180 * TSC, we add elapsed time in this computation. We could let the
1181 * compensation code attempt to catch up if we fall behind, but
1182 * it's better to try to match offsets from the beginning.
1183 */
1184 if (usdiff < USEC_PER_SEC &&
1185 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1186 if (!check_tsc_unstable()) {
1187 offset = kvm->arch.cur_tsc_offset;
1188 pr_debug("kvm: matched tsc offset for %llu\n", data);
1189 } else {
1190 u64 delta = nsec_to_cycles(vcpu, elapsed);
1191 data += delta;
1192 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1193 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1194 }
1195 matched = true;
1196 } else {
1197 /*
1198 * We split periods of matched TSC writes into generations.
1199 * For each generation, we track the original measured
1200 * nanosecond time, offset, and write, so if TSCs are in
1201 * sync, we can match exact offset, and if not, we can match
1202 * exact software computation in compute_guest_tsc()
1203 *
1204 * These values are tracked in kvm->arch.cur_xxx variables.
1205 */
1206 kvm->arch.cur_tsc_generation++;
1207 kvm->arch.cur_tsc_nsec = ns;
1208 kvm->arch.cur_tsc_write = data;
1209 kvm->arch.cur_tsc_offset = offset;
1210 matched = false;
1211 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1212 kvm->arch.cur_tsc_generation, data);
1213 }
1214
1215 /*
1216 * We also track th most recent recorded KHZ, write and time to
1217 * allow the matching interval to be extended at each write.
1218 */
1219 kvm->arch.last_tsc_nsec = ns;
1220 kvm->arch.last_tsc_write = data;
1221 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1222
1223 /* Reset of TSC must disable overshoot protection below */
1224 vcpu->arch.hv_clock.tsc_timestamp = 0;
1225 vcpu->arch.last_guest_tsc = data;
1226
1227 /* Keep track of which generation this VCPU has synchronized to */
1228 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1229 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1230 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1231
1232 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1233 update_ia32_tsc_adjust_msr(vcpu, offset);
1234 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1235 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1236
1237 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1238 if (matched)
1239 kvm->arch.nr_vcpus_matched_tsc++;
1240 else
1241 kvm->arch.nr_vcpus_matched_tsc = 0;
1242
1243 kvm_track_tsc_matching(vcpu);
1244 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1245 }
1246
1247 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1248
1249 #ifdef CONFIG_X86_64
1250
1251 static cycle_t read_tsc(void)
1252 {
1253 cycle_t ret;
1254 u64 last;
1255
1256 /*
1257 * Empirically, a fence (of type that depends on the CPU)
1258 * before rdtsc is enough to ensure that rdtsc is ordered
1259 * with respect to loads. The various CPU manuals are unclear
1260 * as to whether rdtsc can be reordered with later loads,
1261 * but no one has ever seen it happen.
1262 */
1263 rdtsc_barrier();
1264 ret = (cycle_t)vget_cycles();
1265
1266 last = pvclock_gtod_data.clock.cycle_last;
1267
1268 if (likely(ret >= last))
1269 return ret;
1270
1271 /*
1272 * GCC likes to generate cmov here, but this branch is extremely
1273 * predictable (it's just a funciton of time and the likely is
1274 * very likely) and there's a data dependence, so force GCC
1275 * to generate a branch instead. I don't barrier() because
1276 * we don't actually need a barrier, and if this function
1277 * ever gets inlined it will generate worse code.
1278 */
1279 asm volatile ("");
1280 return last;
1281 }
1282
1283 static inline u64 vgettsc(cycle_t *cycle_now)
1284 {
1285 long v;
1286 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1287
1288 *cycle_now = read_tsc();
1289
1290 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1291 return v * gtod->clock.mult;
1292 }
1293
1294 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1295 {
1296 unsigned long seq;
1297 u64 ns;
1298 int mode;
1299 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1300
1301 ts->tv_nsec = 0;
1302 do {
1303 seq = read_seqcount_begin(&gtod->seq);
1304 mode = gtod->clock.vclock_mode;
1305 ts->tv_sec = gtod->monotonic_time_sec;
1306 ns = gtod->monotonic_time_snsec;
1307 ns += vgettsc(cycle_now);
1308 ns >>= gtod->clock.shift;
1309 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1310 timespec_add_ns(ts, ns);
1311
1312 return mode;
1313 }
1314
1315 /* returns true if host is using tsc clocksource */
1316 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1317 {
1318 struct timespec ts;
1319
1320 /* checked again under seqlock below */
1321 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1322 return false;
1323
1324 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1325 return false;
1326
1327 monotonic_to_bootbased(&ts);
1328 *kernel_ns = timespec_to_ns(&ts);
1329
1330 return true;
1331 }
1332 #endif
1333
1334 /*
1335 *
1336 * Assuming a stable TSC across physical CPUS, and a stable TSC
1337 * across virtual CPUs, the following condition is possible.
1338 * Each numbered line represents an event visible to both
1339 * CPUs at the next numbered event.
1340 *
1341 * "timespecX" represents host monotonic time. "tscX" represents
1342 * RDTSC value.
1343 *
1344 * VCPU0 on CPU0 | VCPU1 on CPU1
1345 *
1346 * 1. read timespec0,tsc0
1347 * 2. | timespec1 = timespec0 + N
1348 * | tsc1 = tsc0 + M
1349 * 3. transition to guest | transition to guest
1350 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1351 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1352 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1353 *
1354 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1355 *
1356 * - ret0 < ret1
1357 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1358 * ...
1359 * - 0 < N - M => M < N
1360 *
1361 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1362 * always the case (the difference between two distinct xtime instances
1363 * might be smaller then the difference between corresponding TSC reads,
1364 * when updating guest vcpus pvclock areas).
1365 *
1366 * To avoid that problem, do not allow visibility of distinct
1367 * system_timestamp/tsc_timestamp values simultaneously: use a master
1368 * copy of host monotonic time values. Update that master copy
1369 * in lockstep.
1370 *
1371 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1372 *
1373 */
1374
1375 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1376 {
1377 #ifdef CONFIG_X86_64
1378 struct kvm_arch *ka = &kvm->arch;
1379 int vclock_mode;
1380 bool host_tsc_clocksource, vcpus_matched;
1381
1382 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1383 atomic_read(&kvm->online_vcpus));
1384
1385 /*
1386 * If the host uses TSC clock, then passthrough TSC as stable
1387 * to the guest.
1388 */
1389 host_tsc_clocksource = kvm_get_time_and_clockread(
1390 &ka->master_kernel_ns,
1391 &ka->master_cycle_now);
1392
1393 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1394
1395 if (ka->use_master_clock)
1396 atomic_set(&kvm_guest_has_master_clock, 1);
1397
1398 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1399 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1400 vcpus_matched);
1401 #endif
1402 }
1403
1404 static int kvm_guest_time_update(struct kvm_vcpu *v)
1405 {
1406 unsigned long flags, this_tsc_khz;
1407 struct kvm_vcpu_arch *vcpu = &v->arch;
1408 struct kvm_arch *ka = &v->kvm->arch;
1409 void *shared_kaddr;
1410 s64 kernel_ns, max_kernel_ns;
1411 u64 tsc_timestamp, host_tsc;
1412 struct pvclock_vcpu_time_info *guest_hv_clock;
1413 u8 pvclock_flags;
1414 bool use_master_clock;
1415
1416 kernel_ns = 0;
1417 host_tsc = 0;
1418
1419 /* Keep irq disabled to prevent changes to the clock */
1420 local_irq_save(flags);
1421 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1422 if (unlikely(this_tsc_khz == 0)) {
1423 local_irq_restore(flags);
1424 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1425 return 1;
1426 }
1427
1428 /*
1429 * If the host uses TSC clock, then passthrough TSC as stable
1430 * to the guest.
1431 */
1432 spin_lock(&ka->pvclock_gtod_sync_lock);
1433 use_master_clock = ka->use_master_clock;
1434 if (use_master_clock) {
1435 host_tsc = ka->master_cycle_now;
1436 kernel_ns = ka->master_kernel_ns;
1437 }
1438 spin_unlock(&ka->pvclock_gtod_sync_lock);
1439 if (!use_master_clock) {
1440 host_tsc = native_read_tsc();
1441 kernel_ns = get_kernel_ns();
1442 }
1443
1444 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1445
1446 /*
1447 * We may have to catch up the TSC to match elapsed wall clock
1448 * time for two reasons, even if kvmclock is used.
1449 * 1) CPU could have been running below the maximum TSC rate
1450 * 2) Broken TSC compensation resets the base at each VCPU
1451 * entry to avoid unknown leaps of TSC even when running
1452 * again on the same CPU. This may cause apparent elapsed
1453 * time to disappear, and the guest to stand still or run
1454 * very slowly.
1455 */
1456 if (vcpu->tsc_catchup) {
1457 u64 tsc = compute_guest_tsc(v, kernel_ns);
1458 if (tsc > tsc_timestamp) {
1459 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1460 tsc_timestamp = tsc;
1461 }
1462 }
1463
1464 local_irq_restore(flags);
1465
1466 if (!vcpu->time_page)
1467 return 0;
1468
1469 /*
1470 * Time as measured by the TSC may go backwards when resetting the base
1471 * tsc_timestamp. The reason for this is that the TSC resolution is
1472 * higher than the resolution of the other clock scales. Thus, many
1473 * possible measurments of the TSC correspond to one measurement of any
1474 * other clock, and so a spread of values is possible. This is not a
1475 * problem for the computation of the nanosecond clock; with TSC rates
1476 * around 1GHZ, there can only be a few cycles which correspond to one
1477 * nanosecond value, and any path through this code will inevitably
1478 * take longer than that. However, with the kernel_ns value itself,
1479 * the precision may be much lower, down to HZ granularity. If the
1480 * first sampling of TSC against kernel_ns ends in the low part of the
1481 * range, and the second in the high end of the range, we can get:
1482 *
1483 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1484 *
1485 * As the sampling errors potentially range in the thousands of cycles,
1486 * it is possible such a time value has already been observed by the
1487 * guest. To protect against this, we must compute the system time as
1488 * observed by the guest and ensure the new system time is greater.
1489 */
1490 max_kernel_ns = 0;
1491 if (vcpu->hv_clock.tsc_timestamp) {
1492 max_kernel_ns = vcpu->last_guest_tsc -
1493 vcpu->hv_clock.tsc_timestamp;
1494 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1495 vcpu->hv_clock.tsc_to_system_mul,
1496 vcpu->hv_clock.tsc_shift);
1497 max_kernel_ns += vcpu->last_kernel_ns;
1498 }
1499
1500 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1501 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1502 &vcpu->hv_clock.tsc_shift,
1503 &vcpu->hv_clock.tsc_to_system_mul);
1504 vcpu->hw_tsc_khz = this_tsc_khz;
1505 }
1506
1507 /* with a master <monotonic time, tsc value> tuple,
1508 * pvclock clock reads always increase at the (scaled) rate
1509 * of guest TSC - no need to deal with sampling errors.
1510 */
1511 if (!use_master_clock) {
1512 if (max_kernel_ns > kernel_ns)
1513 kernel_ns = max_kernel_ns;
1514 }
1515 /* With all the info we got, fill in the values */
1516 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1517 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1518 vcpu->last_kernel_ns = kernel_ns;
1519 vcpu->last_guest_tsc = tsc_timestamp;
1520
1521 /*
1522 * The interface expects us to write an even number signaling that the
1523 * update is finished. Since the guest won't see the intermediate
1524 * state, we just increase by 2 at the end.
1525 */
1526 vcpu->hv_clock.version += 2;
1527
1528 shared_kaddr = kmap_atomic(vcpu->time_page);
1529
1530 guest_hv_clock = shared_kaddr + vcpu->time_offset;
1531
1532 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1533 pvclock_flags = (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
1534
1535 if (vcpu->pvclock_set_guest_stopped_request) {
1536 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1537 vcpu->pvclock_set_guest_stopped_request = false;
1538 }
1539
1540 /* If the host uses TSC clocksource, then it is stable */
1541 if (use_master_clock)
1542 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1543
1544 vcpu->hv_clock.flags = pvclock_flags;
1545
1546 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1547 sizeof(vcpu->hv_clock));
1548
1549 kunmap_atomic(shared_kaddr);
1550
1551 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1552 return 0;
1553 }
1554
1555 static bool msr_mtrr_valid(unsigned msr)
1556 {
1557 switch (msr) {
1558 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1559 case MSR_MTRRfix64K_00000:
1560 case MSR_MTRRfix16K_80000:
1561 case MSR_MTRRfix16K_A0000:
1562 case MSR_MTRRfix4K_C0000:
1563 case MSR_MTRRfix4K_C8000:
1564 case MSR_MTRRfix4K_D0000:
1565 case MSR_MTRRfix4K_D8000:
1566 case MSR_MTRRfix4K_E0000:
1567 case MSR_MTRRfix4K_E8000:
1568 case MSR_MTRRfix4K_F0000:
1569 case MSR_MTRRfix4K_F8000:
1570 case MSR_MTRRdefType:
1571 case MSR_IA32_CR_PAT:
1572 return true;
1573 case 0x2f8:
1574 return true;
1575 }
1576 return false;
1577 }
1578
1579 static bool valid_pat_type(unsigned t)
1580 {
1581 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1582 }
1583
1584 static bool valid_mtrr_type(unsigned t)
1585 {
1586 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1587 }
1588
1589 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1590 {
1591 int i;
1592
1593 if (!msr_mtrr_valid(msr))
1594 return false;
1595
1596 if (msr == MSR_IA32_CR_PAT) {
1597 for (i = 0; i < 8; i++)
1598 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1599 return false;
1600 return true;
1601 } else if (msr == MSR_MTRRdefType) {
1602 if (data & ~0xcff)
1603 return false;
1604 return valid_mtrr_type(data & 0xff);
1605 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1606 for (i = 0; i < 8 ; i++)
1607 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1608 return false;
1609 return true;
1610 }
1611
1612 /* variable MTRRs */
1613 return valid_mtrr_type(data & 0xff);
1614 }
1615
1616 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1617 {
1618 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1619
1620 if (!mtrr_valid(vcpu, msr, data))
1621 return 1;
1622
1623 if (msr == MSR_MTRRdefType) {
1624 vcpu->arch.mtrr_state.def_type = data;
1625 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1626 } else if (msr == MSR_MTRRfix64K_00000)
1627 p[0] = data;
1628 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1629 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1630 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1631 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1632 else if (msr == MSR_IA32_CR_PAT)
1633 vcpu->arch.pat = data;
1634 else { /* Variable MTRRs */
1635 int idx, is_mtrr_mask;
1636 u64 *pt;
1637
1638 idx = (msr - 0x200) / 2;
1639 is_mtrr_mask = msr - 0x200 - 2 * idx;
1640 if (!is_mtrr_mask)
1641 pt =
1642 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1643 else
1644 pt =
1645 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1646 *pt = data;
1647 }
1648
1649 kvm_mmu_reset_context(vcpu);
1650 return 0;
1651 }
1652
1653 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1654 {
1655 u64 mcg_cap = vcpu->arch.mcg_cap;
1656 unsigned bank_num = mcg_cap & 0xff;
1657
1658 switch (msr) {
1659 case MSR_IA32_MCG_STATUS:
1660 vcpu->arch.mcg_status = data;
1661 break;
1662 case MSR_IA32_MCG_CTL:
1663 if (!(mcg_cap & MCG_CTL_P))
1664 return 1;
1665 if (data != 0 && data != ~(u64)0)
1666 return -1;
1667 vcpu->arch.mcg_ctl = data;
1668 break;
1669 default:
1670 if (msr >= MSR_IA32_MC0_CTL &&
1671 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1672 u32 offset = msr - MSR_IA32_MC0_CTL;
1673 /* only 0 or all 1s can be written to IA32_MCi_CTL
1674 * some Linux kernels though clear bit 10 in bank 4 to
1675 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1676 * this to avoid an uncatched #GP in the guest
1677 */
1678 if ((offset & 0x3) == 0 &&
1679 data != 0 && (data | (1 << 10)) != ~(u64)0)
1680 return -1;
1681 vcpu->arch.mce_banks[offset] = data;
1682 break;
1683 }
1684 return 1;
1685 }
1686 return 0;
1687 }
1688
1689 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1690 {
1691 struct kvm *kvm = vcpu->kvm;
1692 int lm = is_long_mode(vcpu);
1693 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1694 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1695 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1696 : kvm->arch.xen_hvm_config.blob_size_32;
1697 u32 page_num = data & ~PAGE_MASK;
1698 u64 page_addr = data & PAGE_MASK;
1699 u8 *page;
1700 int r;
1701
1702 r = -E2BIG;
1703 if (page_num >= blob_size)
1704 goto out;
1705 r = -ENOMEM;
1706 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1707 if (IS_ERR(page)) {
1708 r = PTR_ERR(page);
1709 goto out;
1710 }
1711 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1712 goto out_free;
1713 r = 0;
1714 out_free:
1715 kfree(page);
1716 out:
1717 return r;
1718 }
1719
1720 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1721 {
1722 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1723 }
1724
1725 static bool kvm_hv_msr_partition_wide(u32 msr)
1726 {
1727 bool r = false;
1728 switch (msr) {
1729 case HV_X64_MSR_GUEST_OS_ID:
1730 case HV_X64_MSR_HYPERCALL:
1731 r = true;
1732 break;
1733 }
1734
1735 return r;
1736 }
1737
1738 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1739 {
1740 struct kvm *kvm = vcpu->kvm;
1741
1742 switch (msr) {
1743 case HV_X64_MSR_GUEST_OS_ID:
1744 kvm->arch.hv_guest_os_id = data;
1745 /* setting guest os id to zero disables hypercall page */
1746 if (!kvm->arch.hv_guest_os_id)
1747 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1748 break;
1749 case HV_X64_MSR_HYPERCALL: {
1750 u64 gfn;
1751 unsigned long addr;
1752 u8 instructions[4];
1753
1754 /* if guest os id is not set hypercall should remain disabled */
1755 if (!kvm->arch.hv_guest_os_id)
1756 break;
1757 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1758 kvm->arch.hv_hypercall = data;
1759 break;
1760 }
1761 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1762 addr = gfn_to_hva(kvm, gfn);
1763 if (kvm_is_error_hva(addr))
1764 return 1;
1765 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1766 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1767 if (__copy_to_user((void __user *)addr, instructions, 4))
1768 return 1;
1769 kvm->arch.hv_hypercall = data;
1770 break;
1771 }
1772 default:
1773 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1774 "data 0x%llx\n", msr, data);
1775 return 1;
1776 }
1777 return 0;
1778 }
1779
1780 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1781 {
1782 switch (msr) {
1783 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1784 unsigned long addr;
1785
1786 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1787 vcpu->arch.hv_vapic = data;
1788 break;
1789 }
1790 addr = gfn_to_hva(vcpu->kvm, data >>
1791 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1792 if (kvm_is_error_hva(addr))
1793 return 1;
1794 if (__clear_user((void __user *)addr, PAGE_SIZE))
1795 return 1;
1796 vcpu->arch.hv_vapic = data;
1797 break;
1798 }
1799 case HV_X64_MSR_EOI:
1800 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1801 case HV_X64_MSR_ICR:
1802 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1803 case HV_X64_MSR_TPR:
1804 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1805 default:
1806 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1807 "data 0x%llx\n", msr, data);
1808 return 1;
1809 }
1810
1811 return 0;
1812 }
1813
1814 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1815 {
1816 gpa_t gpa = data & ~0x3f;
1817
1818 /* Bits 2:5 are reserved, Should be zero */
1819 if (data & 0x3c)
1820 return 1;
1821
1822 vcpu->arch.apf.msr_val = data;
1823
1824 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1825 kvm_clear_async_pf_completion_queue(vcpu);
1826 kvm_async_pf_hash_reset(vcpu);
1827 return 0;
1828 }
1829
1830 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1831 return 1;
1832
1833 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1834 kvm_async_pf_wakeup_all(vcpu);
1835 return 0;
1836 }
1837
1838 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1839 {
1840 if (vcpu->arch.time_page) {
1841 kvm_release_page_dirty(vcpu->arch.time_page);
1842 vcpu->arch.time_page = NULL;
1843 }
1844 }
1845
1846 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1847 {
1848 u64 delta;
1849
1850 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1851 return;
1852
1853 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1854 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1855 vcpu->arch.st.accum_steal = delta;
1856 }
1857
1858 static void record_steal_time(struct kvm_vcpu *vcpu)
1859 {
1860 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1861 return;
1862
1863 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1864 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1865 return;
1866
1867 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1868 vcpu->arch.st.steal.version += 2;
1869 vcpu->arch.st.accum_steal = 0;
1870
1871 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1872 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1873 }
1874
1875 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1876 {
1877 bool pr = false;
1878 u32 msr = msr_info->index;
1879 u64 data = msr_info->data;
1880
1881 switch (msr) {
1882 case MSR_EFER:
1883 return set_efer(vcpu, data);
1884 case MSR_K7_HWCR:
1885 data &= ~(u64)0x40; /* ignore flush filter disable */
1886 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1887 data &= ~(u64)0x8; /* ignore TLB cache disable */
1888 if (data != 0) {
1889 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1890 data);
1891 return 1;
1892 }
1893 break;
1894 case MSR_FAM10H_MMIO_CONF_BASE:
1895 if (data != 0) {
1896 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1897 "0x%llx\n", data);
1898 return 1;
1899 }
1900 break;
1901 case MSR_AMD64_NB_CFG:
1902 break;
1903 case MSR_IA32_DEBUGCTLMSR:
1904 if (!data) {
1905 /* We support the non-activated case already */
1906 break;
1907 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1908 /* Values other than LBR and BTF are vendor-specific,
1909 thus reserved and should throw a #GP */
1910 return 1;
1911 }
1912 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1913 __func__, data);
1914 break;
1915 case MSR_IA32_UCODE_REV:
1916 case MSR_IA32_UCODE_WRITE:
1917 case MSR_VM_HSAVE_PA:
1918 case MSR_AMD64_PATCH_LOADER:
1919 break;
1920 case 0x200 ... 0x2ff:
1921 return set_msr_mtrr(vcpu, msr, data);
1922 case MSR_IA32_APICBASE:
1923 kvm_set_apic_base(vcpu, data);
1924 break;
1925 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1926 return kvm_x2apic_msr_write(vcpu, msr, data);
1927 case MSR_IA32_TSCDEADLINE:
1928 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1929 break;
1930 case MSR_IA32_TSC_ADJUST:
1931 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1932 if (!msr_info->host_initiated) {
1933 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1934 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1935 }
1936 vcpu->arch.ia32_tsc_adjust_msr = data;
1937 }
1938 break;
1939 case MSR_IA32_MISC_ENABLE:
1940 vcpu->arch.ia32_misc_enable_msr = data;
1941 break;
1942 case MSR_KVM_WALL_CLOCK_NEW:
1943 case MSR_KVM_WALL_CLOCK:
1944 vcpu->kvm->arch.wall_clock = data;
1945 kvm_write_wall_clock(vcpu->kvm, data);
1946 break;
1947 case MSR_KVM_SYSTEM_TIME_NEW:
1948 case MSR_KVM_SYSTEM_TIME: {
1949 kvmclock_reset(vcpu);
1950
1951 vcpu->arch.time = data;
1952 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1953
1954 /* we verify if the enable bit is set... */
1955 if (!(data & 1))
1956 break;
1957
1958 /* ...but clean it before doing the actual write */
1959 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1960
1961 vcpu->arch.time_page =
1962 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1963
1964 if (is_error_page(vcpu->arch.time_page))
1965 vcpu->arch.time_page = NULL;
1966
1967 break;
1968 }
1969 case MSR_KVM_ASYNC_PF_EN:
1970 if (kvm_pv_enable_async_pf(vcpu, data))
1971 return 1;
1972 break;
1973 case MSR_KVM_STEAL_TIME:
1974
1975 if (unlikely(!sched_info_on()))
1976 return 1;
1977
1978 if (data & KVM_STEAL_RESERVED_MASK)
1979 return 1;
1980
1981 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1982 data & KVM_STEAL_VALID_BITS))
1983 return 1;
1984
1985 vcpu->arch.st.msr_val = data;
1986
1987 if (!(data & KVM_MSR_ENABLED))
1988 break;
1989
1990 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1991
1992 preempt_disable();
1993 accumulate_steal_time(vcpu);
1994 preempt_enable();
1995
1996 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1997
1998 break;
1999 case MSR_KVM_PV_EOI_EN:
2000 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2001 return 1;
2002 break;
2003
2004 case MSR_IA32_MCG_CTL:
2005 case MSR_IA32_MCG_STATUS:
2006 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2007 return set_msr_mce(vcpu, msr, data);
2008
2009 /* Performance counters are not protected by a CPUID bit,
2010 * so we should check all of them in the generic path for the sake of
2011 * cross vendor migration.
2012 * Writing a zero into the event select MSRs disables them,
2013 * which we perfectly emulate ;-). Any other value should be at least
2014 * reported, some guests depend on them.
2015 */
2016 case MSR_K7_EVNTSEL0:
2017 case MSR_K7_EVNTSEL1:
2018 case MSR_K7_EVNTSEL2:
2019 case MSR_K7_EVNTSEL3:
2020 if (data != 0)
2021 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2022 "0x%x data 0x%llx\n", msr, data);
2023 break;
2024 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2025 * so we ignore writes to make it happy.
2026 */
2027 case MSR_K7_PERFCTR0:
2028 case MSR_K7_PERFCTR1:
2029 case MSR_K7_PERFCTR2:
2030 case MSR_K7_PERFCTR3:
2031 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2032 "0x%x data 0x%llx\n", msr, data);
2033 break;
2034 case MSR_P6_PERFCTR0:
2035 case MSR_P6_PERFCTR1:
2036 pr = true;
2037 case MSR_P6_EVNTSEL0:
2038 case MSR_P6_EVNTSEL1:
2039 if (kvm_pmu_msr(vcpu, msr))
2040 return kvm_pmu_set_msr(vcpu, msr, data);
2041
2042 if (pr || data != 0)
2043 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2044 "0x%x data 0x%llx\n", msr, data);
2045 break;
2046 case MSR_K7_CLK_CTL:
2047 /*
2048 * Ignore all writes to this no longer documented MSR.
2049 * Writes are only relevant for old K7 processors,
2050 * all pre-dating SVM, but a recommended workaround from
2051 * AMD for these chips. It is possible to specify the
2052 * affected processor models on the command line, hence
2053 * the need to ignore the workaround.
2054 */
2055 break;
2056 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2057 if (kvm_hv_msr_partition_wide(msr)) {
2058 int r;
2059 mutex_lock(&vcpu->kvm->lock);
2060 r = set_msr_hyperv_pw(vcpu, msr, data);
2061 mutex_unlock(&vcpu->kvm->lock);
2062 return r;
2063 } else
2064 return set_msr_hyperv(vcpu, msr, data);
2065 break;
2066 case MSR_IA32_BBL_CR_CTL3:
2067 /* Drop writes to this legacy MSR -- see rdmsr
2068 * counterpart for further detail.
2069 */
2070 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2071 break;
2072 case MSR_AMD64_OSVW_ID_LENGTH:
2073 if (!guest_cpuid_has_osvw(vcpu))
2074 return 1;
2075 vcpu->arch.osvw.length = data;
2076 break;
2077 case MSR_AMD64_OSVW_STATUS:
2078 if (!guest_cpuid_has_osvw(vcpu))
2079 return 1;
2080 vcpu->arch.osvw.status = data;
2081 break;
2082 default:
2083 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2084 return xen_hvm_config(vcpu, data);
2085 if (kvm_pmu_msr(vcpu, msr))
2086 return kvm_pmu_set_msr(vcpu, msr, data);
2087 if (!ignore_msrs) {
2088 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2089 msr, data);
2090 return 1;
2091 } else {
2092 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2093 msr, data);
2094 break;
2095 }
2096 }
2097 return 0;
2098 }
2099 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2100
2101
2102 /*
2103 * Reads an msr value (of 'msr_index') into 'pdata'.
2104 * Returns 0 on success, non-0 otherwise.
2105 * Assumes vcpu_load() was already called.
2106 */
2107 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2108 {
2109 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2110 }
2111
2112 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2113 {
2114 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2115
2116 if (!msr_mtrr_valid(msr))
2117 return 1;
2118
2119 if (msr == MSR_MTRRdefType)
2120 *pdata = vcpu->arch.mtrr_state.def_type +
2121 (vcpu->arch.mtrr_state.enabled << 10);
2122 else if (msr == MSR_MTRRfix64K_00000)
2123 *pdata = p[0];
2124 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2125 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2126 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2127 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2128 else if (msr == MSR_IA32_CR_PAT)
2129 *pdata = vcpu->arch.pat;
2130 else { /* Variable MTRRs */
2131 int idx, is_mtrr_mask;
2132 u64 *pt;
2133
2134 idx = (msr - 0x200) / 2;
2135 is_mtrr_mask = msr - 0x200 - 2 * idx;
2136 if (!is_mtrr_mask)
2137 pt =
2138 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2139 else
2140 pt =
2141 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2142 *pdata = *pt;
2143 }
2144
2145 return 0;
2146 }
2147
2148 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2149 {
2150 u64 data;
2151 u64 mcg_cap = vcpu->arch.mcg_cap;
2152 unsigned bank_num = mcg_cap & 0xff;
2153
2154 switch (msr) {
2155 case MSR_IA32_P5_MC_ADDR:
2156 case MSR_IA32_P5_MC_TYPE:
2157 data = 0;
2158 break;
2159 case MSR_IA32_MCG_CAP:
2160 data = vcpu->arch.mcg_cap;
2161 break;
2162 case MSR_IA32_MCG_CTL:
2163 if (!(mcg_cap & MCG_CTL_P))
2164 return 1;
2165 data = vcpu->arch.mcg_ctl;
2166 break;
2167 case MSR_IA32_MCG_STATUS:
2168 data = vcpu->arch.mcg_status;
2169 break;
2170 default:
2171 if (msr >= MSR_IA32_MC0_CTL &&
2172 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2173 u32 offset = msr - MSR_IA32_MC0_CTL;
2174 data = vcpu->arch.mce_banks[offset];
2175 break;
2176 }
2177 return 1;
2178 }
2179 *pdata = data;
2180 return 0;
2181 }
2182
2183 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2184 {
2185 u64 data = 0;
2186 struct kvm *kvm = vcpu->kvm;
2187
2188 switch (msr) {
2189 case HV_X64_MSR_GUEST_OS_ID:
2190 data = kvm->arch.hv_guest_os_id;
2191 break;
2192 case HV_X64_MSR_HYPERCALL:
2193 data = kvm->arch.hv_hypercall;
2194 break;
2195 default:
2196 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2197 return 1;
2198 }
2199
2200 *pdata = data;
2201 return 0;
2202 }
2203
2204 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2205 {
2206 u64 data = 0;
2207
2208 switch (msr) {
2209 case HV_X64_MSR_VP_INDEX: {
2210 int r;
2211 struct kvm_vcpu *v;
2212 kvm_for_each_vcpu(r, v, vcpu->kvm)
2213 if (v == vcpu)
2214 data = r;
2215 break;
2216 }
2217 case HV_X64_MSR_EOI:
2218 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2219 case HV_X64_MSR_ICR:
2220 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2221 case HV_X64_MSR_TPR:
2222 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2223 case HV_X64_MSR_APIC_ASSIST_PAGE:
2224 data = vcpu->arch.hv_vapic;
2225 break;
2226 default:
2227 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2228 return 1;
2229 }
2230 *pdata = data;
2231 return 0;
2232 }
2233
2234 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2235 {
2236 u64 data;
2237
2238 switch (msr) {
2239 case MSR_IA32_PLATFORM_ID:
2240 case MSR_IA32_EBL_CR_POWERON:
2241 case MSR_IA32_DEBUGCTLMSR:
2242 case MSR_IA32_LASTBRANCHFROMIP:
2243 case MSR_IA32_LASTBRANCHTOIP:
2244 case MSR_IA32_LASTINTFROMIP:
2245 case MSR_IA32_LASTINTTOIP:
2246 case MSR_K8_SYSCFG:
2247 case MSR_K7_HWCR:
2248 case MSR_VM_HSAVE_PA:
2249 case MSR_K7_EVNTSEL0:
2250 case MSR_K7_PERFCTR0:
2251 case MSR_K8_INT_PENDING_MSG:
2252 case MSR_AMD64_NB_CFG:
2253 case MSR_FAM10H_MMIO_CONF_BASE:
2254 data = 0;
2255 break;
2256 case MSR_P6_PERFCTR0:
2257 case MSR_P6_PERFCTR1:
2258 case MSR_P6_EVNTSEL0:
2259 case MSR_P6_EVNTSEL1:
2260 if (kvm_pmu_msr(vcpu, msr))
2261 return kvm_pmu_get_msr(vcpu, msr, pdata);
2262 data = 0;
2263 break;
2264 case MSR_IA32_UCODE_REV:
2265 data = 0x100000000ULL;
2266 break;
2267 case MSR_MTRRcap:
2268 data = 0x500 | KVM_NR_VAR_MTRR;
2269 break;
2270 case 0x200 ... 0x2ff:
2271 return get_msr_mtrr(vcpu, msr, pdata);
2272 case 0xcd: /* fsb frequency */
2273 data = 3;
2274 break;
2275 /*
2276 * MSR_EBC_FREQUENCY_ID
2277 * Conservative value valid for even the basic CPU models.
2278 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2279 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2280 * and 266MHz for model 3, or 4. Set Core Clock
2281 * Frequency to System Bus Frequency Ratio to 1 (bits
2282 * 31:24) even though these are only valid for CPU
2283 * models > 2, however guests may end up dividing or
2284 * multiplying by zero otherwise.
2285 */
2286 case MSR_EBC_FREQUENCY_ID:
2287 data = 1 << 24;
2288 break;
2289 case MSR_IA32_APICBASE:
2290 data = kvm_get_apic_base(vcpu);
2291 break;
2292 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2293 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2294 break;
2295 case MSR_IA32_TSCDEADLINE:
2296 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2297 break;
2298 case MSR_IA32_TSC_ADJUST:
2299 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2300 break;
2301 case MSR_IA32_MISC_ENABLE:
2302 data = vcpu->arch.ia32_misc_enable_msr;
2303 break;
2304 case MSR_IA32_PERF_STATUS:
2305 /* TSC increment by tick */
2306 data = 1000ULL;
2307 /* CPU multiplier */
2308 data |= (((uint64_t)4ULL) << 40);
2309 break;
2310 case MSR_EFER:
2311 data = vcpu->arch.efer;
2312 break;
2313 case MSR_KVM_WALL_CLOCK:
2314 case MSR_KVM_WALL_CLOCK_NEW:
2315 data = vcpu->kvm->arch.wall_clock;
2316 break;
2317 case MSR_KVM_SYSTEM_TIME:
2318 case MSR_KVM_SYSTEM_TIME_NEW:
2319 data = vcpu->arch.time;
2320 break;
2321 case MSR_KVM_ASYNC_PF_EN:
2322 data = vcpu->arch.apf.msr_val;
2323 break;
2324 case MSR_KVM_STEAL_TIME:
2325 data = vcpu->arch.st.msr_val;
2326 break;
2327 case MSR_KVM_PV_EOI_EN:
2328 data = vcpu->arch.pv_eoi.msr_val;
2329 break;
2330 case MSR_IA32_P5_MC_ADDR:
2331 case MSR_IA32_P5_MC_TYPE:
2332 case MSR_IA32_MCG_CAP:
2333 case MSR_IA32_MCG_CTL:
2334 case MSR_IA32_MCG_STATUS:
2335 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2336 return get_msr_mce(vcpu, msr, pdata);
2337 case MSR_K7_CLK_CTL:
2338 /*
2339 * Provide expected ramp-up count for K7. All other
2340 * are set to zero, indicating minimum divisors for
2341 * every field.
2342 *
2343 * This prevents guest kernels on AMD host with CPU
2344 * type 6, model 8 and higher from exploding due to
2345 * the rdmsr failing.
2346 */
2347 data = 0x20000000;
2348 break;
2349 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2350 if (kvm_hv_msr_partition_wide(msr)) {
2351 int r;
2352 mutex_lock(&vcpu->kvm->lock);
2353 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2354 mutex_unlock(&vcpu->kvm->lock);
2355 return r;
2356 } else
2357 return get_msr_hyperv(vcpu, msr, pdata);
2358 break;
2359 case MSR_IA32_BBL_CR_CTL3:
2360 /* This legacy MSR exists but isn't fully documented in current
2361 * silicon. It is however accessed by winxp in very narrow
2362 * scenarios where it sets bit #19, itself documented as
2363 * a "reserved" bit. Best effort attempt to source coherent
2364 * read data here should the balance of the register be
2365 * interpreted by the guest:
2366 *
2367 * L2 cache control register 3: 64GB range, 256KB size,
2368 * enabled, latency 0x1, configured
2369 */
2370 data = 0xbe702111;
2371 break;
2372 case MSR_AMD64_OSVW_ID_LENGTH:
2373 if (!guest_cpuid_has_osvw(vcpu))
2374 return 1;
2375 data = vcpu->arch.osvw.length;
2376 break;
2377 case MSR_AMD64_OSVW_STATUS:
2378 if (!guest_cpuid_has_osvw(vcpu))
2379 return 1;
2380 data = vcpu->arch.osvw.status;
2381 break;
2382 default:
2383 if (kvm_pmu_msr(vcpu, msr))
2384 return kvm_pmu_get_msr(vcpu, msr, pdata);
2385 if (!ignore_msrs) {
2386 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2387 return 1;
2388 } else {
2389 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2390 data = 0;
2391 }
2392 break;
2393 }
2394 *pdata = data;
2395 return 0;
2396 }
2397 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2398
2399 /*
2400 * Read or write a bunch of msrs. All parameters are kernel addresses.
2401 *
2402 * @return number of msrs set successfully.
2403 */
2404 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2405 struct kvm_msr_entry *entries,
2406 int (*do_msr)(struct kvm_vcpu *vcpu,
2407 unsigned index, u64 *data))
2408 {
2409 int i, idx;
2410
2411 idx = srcu_read_lock(&vcpu->kvm->srcu);
2412 for (i = 0; i < msrs->nmsrs; ++i)
2413 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2414 break;
2415 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2416
2417 return i;
2418 }
2419
2420 /*
2421 * Read or write a bunch of msrs. Parameters are user addresses.
2422 *
2423 * @return number of msrs set successfully.
2424 */
2425 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2426 int (*do_msr)(struct kvm_vcpu *vcpu,
2427 unsigned index, u64 *data),
2428 int writeback)
2429 {
2430 struct kvm_msrs msrs;
2431 struct kvm_msr_entry *entries;
2432 int r, n;
2433 unsigned size;
2434
2435 r = -EFAULT;
2436 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2437 goto out;
2438
2439 r = -E2BIG;
2440 if (msrs.nmsrs >= MAX_IO_MSRS)
2441 goto out;
2442
2443 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2444 entries = memdup_user(user_msrs->entries, size);
2445 if (IS_ERR(entries)) {
2446 r = PTR_ERR(entries);
2447 goto out;
2448 }
2449
2450 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2451 if (r < 0)
2452 goto out_free;
2453
2454 r = -EFAULT;
2455 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2456 goto out_free;
2457
2458 r = n;
2459
2460 out_free:
2461 kfree(entries);
2462 out:
2463 return r;
2464 }
2465
2466 int kvm_dev_ioctl_check_extension(long ext)
2467 {
2468 int r;
2469
2470 switch (ext) {
2471 case KVM_CAP_IRQCHIP:
2472 case KVM_CAP_HLT:
2473 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2474 case KVM_CAP_SET_TSS_ADDR:
2475 case KVM_CAP_EXT_CPUID:
2476 case KVM_CAP_CLOCKSOURCE:
2477 case KVM_CAP_PIT:
2478 case KVM_CAP_NOP_IO_DELAY:
2479 case KVM_CAP_MP_STATE:
2480 case KVM_CAP_SYNC_MMU:
2481 case KVM_CAP_USER_NMI:
2482 case KVM_CAP_REINJECT_CONTROL:
2483 case KVM_CAP_IRQ_INJECT_STATUS:
2484 case KVM_CAP_ASSIGN_DEV_IRQ:
2485 case KVM_CAP_IRQFD:
2486 case KVM_CAP_IOEVENTFD:
2487 case KVM_CAP_PIT2:
2488 case KVM_CAP_PIT_STATE2:
2489 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2490 case KVM_CAP_XEN_HVM:
2491 case KVM_CAP_ADJUST_CLOCK:
2492 case KVM_CAP_VCPU_EVENTS:
2493 case KVM_CAP_HYPERV:
2494 case KVM_CAP_HYPERV_VAPIC:
2495 case KVM_CAP_HYPERV_SPIN:
2496 case KVM_CAP_PCI_SEGMENT:
2497 case KVM_CAP_DEBUGREGS:
2498 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2499 case KVM_CAP_XSAVE:
2500 case KVM_CAP_ASYNC_PF:
2501 case KVM_CAP_GET_TSC_KHZ:
2502 case KVM_CAP_PCI_2_3:
2503 case KVM_CAP_KVMCLOCK_CTRL:
2504 case KVM_CAP_READONLY_MEM:
2505 case KVM_CAP_IRQFD_RESAMPLE:
2506 r = 1;
2507 break;
2508 case KVM_CAP_COALESCED_MMIO:
2509 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2510 break;
2511 case KVM_CAP_VAPIC:
2512 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2513 break;
2514 case KVM_CAP_NR_VCPUS:
2515 r = KVM_SOFT_MAX_VCPUS;
2516 break;
2517 case KVM_CAP_MAX_VCPUS:
2518 r = KVM_MAX_VCPUS;
2519 break;
2520 case KVM_CAP_NR_MEMSLOTS:
2521 r = KVM_MEMORY_SLOTS;
2522 break;
2523 case KVM_CAP_PV_MMU: /* obsolete */
2524 r = 0;
2525 break;
2526 case KVM_CAP_IOMMU:
2527 r = iommu_present(&pci_bus_type);
2528 break;
2529 case KVM_CAP_MCE:
2530 r = KVM_MAX_MCE_BANKS;
2531 break;
2532 case KVM_CAP_XCRS:
2533 r = cpu_has_xsave;
2534 break;
2535 case KVM_CAP_TSC_CONTROL:
2536 r = kvm_has_tsc_control;
2537 break;
2538 case KVM_CAP_TSC_DEADLINE_TIMER:
2539 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2540 break;
2541 default:
2542 r = 0;
2543 break;
2544 }
2545 return r;
2546
2547 }
2548
2549 long kvm_arch_dev_ioctl(struct file *filp,
2550 unsigned int ioctl, unsigned long arg)
2551 {
2552 void __user *argp = (void __user *)arg;
2553 long r;
2554
2555 switch (ioctl) {
2556 case KVM_GET_MSR_INDEX_LIST: {
2557 struct kvm_msr_list __user *user_msr_list = argp;
2558 struct kvm_msr_list msr_list;
2559 unsigned n;
2560
2561 r = -EFAULT;
2562 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2563 goto out;
2564 n = msr_list.nmsrs;
2565 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2566 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2567 goto out;
2568 r = -E2BIG;
2569 if (n < msr_list.nmsrs)
2570 goto out;
2571 r = -EFAULT;
2572 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2573 num_msrs_to_save * sizeof(u32)))
2574 goto out;
2575 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2576 &emulated_msrs,
2577 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2578 goto out;
2579 r = 0;
2580 break;
2581 }
2582 case KVM_GET_SUPPORTED_CPUID: {
2583 struct kvm_cpuid2 __user *cpuid_arg = argp;
2584 struct kvm_cpuid2 cpuid;
2585
2586 r = -EFAULT;
2587 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2588 goto out;
2589 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2590 cpuid_arg->entries);
2591 if (r)
2592 goto out;
2593
2594 r = -EFAULT;
2595 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2596 goto out;
2597 r = 0;
2598 break;
2599 }
2600 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2601 u64 mce_cap;
2602
2603 mce_cap = KVM_MCE_CAP_SUPPORTED;
2604 r = -EFAULT;
2605 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2606 goto out;
2607 r = 0;
2608 break;
2609 }
2610 default:
2611 r = -EINVAL;
2612 }
2613 out:
2614 return r;
2615 }
2616
2617 static void wbinvd_ipi(void *garbage)
2618 {
2619 wbinvd();
2620 }
2621
2622 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2623 {
2624 return vcpu->kvm->arch.iommu_domain &&
2625 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2626 }
2627
2628 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2629 {
2630 /* Address WBINVD may be executed by guest */
2631 if (need_emulate_wbinvd(vcpu)) {
2632 if (kvm_x86_ops->has_wbinvd_exit())
2633 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2634 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2635 smp_call_function_single(vcpu->cpu,
2636 wbinvd_ipi, NULL, 1);
2637 }
2638
2639 kvm_x86_ops->vcpu_load(vcpu, cpu);
2640
2641 /* Apply any externally detected TSC adjustments (due to suspend) */
2642 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2643 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2644 vcpu->arch.tsc_offset_adjustment = 0;
2645 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2646 }
2647
2648 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2649 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2650 native_read_tsc() - vcpu->arch.last_host_tsc;
2651 if (tsc_delta < 0)
2652 mark_tsc_unstable("KVM discovered backwards TSC");
2653 if (check_tsc_unstable()) {
2654 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2655 vcpu->arch.last_guest_tsc);
2656 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2657 vcpu->arch.tsc_catchup = 1;
2658 }
2659 /*
2660 * On a host with synchronized TSC, there is no need to update
2661 * kvmclock on vcpu->cpu migration
2662 */
2663 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2664 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2665 if (vcpu->cpu != cpu)
2666 kvm_migrate_timers(vcpu);
2667 vcpu->cpu = cpu;
2668 }
2669
2670 accumulate_steal_time(vcpu);
2671 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2672 }
2673
2674 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2675 {
2676 kvm_x86_ops->vcpu_put(vcpu);
2677 kvm_put_guest_fpu(vcpu);
2678 vcpu->arch.last_host_tsc = native_read_tsc();
2679 }
2680
2681 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2682 struct kvm_lapic_state *s)
2683 {
2684 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2685
2686 return 0;
2687 }
2688
2689 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2690 struct kvm_lapic_state *s)
2691 {
2692 kvm_apic_post_state_restore(vcpu, s);
2693 update_cr8_intercept(vcpu);
2694
2695 return 0;
2696 }
2697
2698 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2699 struct kvm_interrupt *irq)
2700 {
2701 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
2702 return -EINVAL;
2703 if (irqchip_in_kernel(vcpu->kvm))
2704 return -ENXIO;
2705
2706 kvm_queue_interrupt(vcpu, irq->irq, false);
2707 kvm_make_request(KVM_REQ_EVENT, vcpu);
2708
2709 return 0;
2710 }
2711
2712 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2713 {
2714 kvm_inject_nmi(vcpu);
2715
2716 return 0;
2717 }
2718
2719 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2720 struct kvm_tpr_access_ctl *tac)
2721 {
2722 if (tac->flags)
2723 return -EINVAL;
2724 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2725 return 0;
2726 }
2727
2728 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2729 u64 mcg_cap)
2730 {
2731 int r;
2732 unsigned bank_num = mcg_cap & 0xff, bank;
2733
2734 r = -EINVAL;
2735 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2736 goto out;
2737 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2738 goto out;
2739 r = 0;
2740 vcpu->arch.mcg_cap = mcg_cap;
2741 /* Init IA32_MCG_CTL to all 1s */
2742 if (mcg_cap & MCG_CTL_P)
2743 vcpu->arch.mcg_ctl = ~(u64)0;
2744 /* Init IA32_MCi_CTL to all 1s */
2745 for (bank = 0; bank < bank_num; bank++)
2746 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2747 out:
2748 return r;
2749 }
2750
2751 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2752 struct kvm_x86_mce *mce)
2753 {
2754 u64 mcg_cap = vcpu->arch.mcg_cap;
2755 unsigned bank_num = mcg_cap & 0xff;
2756 u64 *banks = vcpu->arch.mce_banks;
2757
2758 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2759 return -EINVAL;
2760 /*
2761 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2762 * reporting is disabled
2763 */
2764 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2765 vcpu->arch.mcg_ctl != ~(u64)0)
2766 return 0;
2767 banks += 4 * mce->bank;
2768 /*
2769 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2770 * reporting is disabled for the bank
2771 */
2772 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2773 return 0;
2774 if (mce->status & MCI_STATUS_UC) {
2775 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2776 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2777 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2778 return 0;
2779 }
2780 if (banks[1] & MCI_STATUS_VAL)
2781 mce->status |= MCI_STATUS_OVER;
2782 banks[2] = mce->addr;
2783 banks[3] = mce->misc;
2784 vcpu->arch.mcg_status = mce->mcg_status;
2785 banks[1] = mce->status;
2786 kvm_queue_exception(vcpu, MC_VECTOR);
2787 } else if (!(banks[1] & MCI_STATUS_VAL)
2788 || !(banks[1] & MCI_STATUS_UC)) {
2789 if (banks[1] & MCI_STATUS_VAL)
2790 mce->status |= MCI_STATUS_OVER;
2791 banks[2] = mce->addr;
2792 banks[3] = mce->misc;
2793 banks[1] = mce->status;
2794 } else
2795 banks[1] |= MCI_STATUS_OVER;
2796 return 0;
2797 }
2798
2799 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2800 struct kvm_vcpu_events *events)
2801 {
2802 process_nmi(vcpu);
2803 events->exception.injected =
2804 vcpu->arch.exception.pending &&
2805 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2806 events->exception.nr = vcpu->arch.exception.nr;
2807 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2808 events->exception.pad = 0;
2809 events->exception.error_code = vcpu->arch.exception.error_code;
2810
2811 events->interrupt.injected =
2812 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2813 events->interrupt.nr = vcpu->arch.interrupt.nr;
2814 events->interrupt.soft = 0;
2815 events->interrupt.shadow =
2816 kvm_x86_ops->get_interrupt_shadow(vcpu,
2817 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2818
2819 events->nmi.injected = vcpu->arch.nmi_injected;
2820 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2821 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2822 events->nmi.pad = 0;
2823
2824 events->sipi_vector = vcpu->arch.sipi_vector;
2825
2826 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2827 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2828 | KVM_VCPUEVENT_VALID_SHADOW);
2829 memset(&events->reserved, 0, sizeof(events->reserved));
2830 }
2831
2832 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2833 struct kvm_vcpu_events *events)
2834 {
2835 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2836 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2837 | KVM_VCPUEVENT_VALID_SHADOW))
2838 return -EINVAL;
2839
2840 process_nmi(vcpu);
2841 vcpu->arch.exception.pending = events->exception.injected;
2842 vcpu->arch.exception.nr = events->exception.nr;
2843 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2844 vcpu->arch.exception.error_code = events->exception.error_code;
2845
2846 vcpu->arch.interrupt.pending = events->interrupt.injected;
2847 vcpu->arch.interrupt.nr = events->interrupt.nr;
2848 vcpu->arch.interrupt.soft = events->interrupt.soft;
2849 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2850 kvm_x86_ops->set_interrupt_shadow(vcpu,
2851 events->interrupt.shadow);
2852
2853 vcpu->arch.nmi_injected = events->nmi.injected;
2854 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2855 vcpu->arch.nmi_pending = events->nmi.pending;
2856 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2857
2858 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2859 vcpu->arch.sipi_vector = events->sipi_vector;
2860
2861 kvm_make_request(KVM_REQ_EVENT, vcpu);
2862
2863 return 0;
2864 }
2865
2866 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2867 struct kvm_debugregs *dbgregs)
2868 {
2869 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2870 dbgregs->dr6 = vcpu->arch.dr6;
2871 dbgregs->dr7 = vcpu->arch.dr7;
2872 dbgregs->flags = 0;
2873 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2874 }
2875
2876 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2877 struct kvm_debugregs *dbgregs)
2878 {
2879 if (dbgregs->flags)
2880 return -EINVAL;
2881
2882 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2883 vcpu->arch.dr6 = dbgregs->dr6;
2884 vcpu->arch.dr7 = dbgregs->dr7;
2885
2886 return 0;
2887 }
2888
2889 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2890 struct kvm_xsave *guest_xsave)
2891 {
2892 if (cpu_has_xsave)
2893 memcpy(guest_xsave->region,
2894 &vcpu->arch.guest_fpu.state->xsave,
2895 xstate_size);
2896 else {
2897 memcpy(guest_xsave->region,
2898 &vcpu->arch.guest_fpu.state->fxsave,
2899 sizeof(struct i387_fxsave_struct));
2900 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2901 XSTATE_FPSSE;
2902 }
2903 }
2904
2905 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2906 struct kvm_xsave *guest_xsave)
2907 {
2908 u64 xstate_bv =
2909 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2910
2911 if (cpu_has_xsave)
2912 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2913 guest_xsave->region, xstate_size);
2914 else {
2915 if (xstate_bv & ~XSTATE_FPSSE)
2916 return -EINVAL;
2917 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2918 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2919 }
2920 return 0;
2921 }
2922
2923 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2924 struct kvm_xcrs *guest_xcrs)
2925 {
2926 if (!cpu_has_xsave) {
2927 guest_xcrs->nr_xcrs = 0;
2928 return;
2929 }
2930
2931 guest_xcrs->nr_xcrs = 1;
2932 guest_xcrs->flags = 0;
2933 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2934 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2935 }
2936
2937 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2938 struct kvm_xcrs *guest_xcrs)
2939 {
2940 int i, r = 0;
2941
2942 if (!cpu_has_xsave)
2943 return -EINVAL;
2944
2945 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2946 return -EINVAL;
2947
2948 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2949 /* Only support XCR0 currently */
2950 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2951 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2952 guest_xcrs->xcrs[0].value);
2953 break;
2954 }
2955 if (r)
2956 r = -EINVAL;
2957 return r;
2958 }
2959
2960 /*
2961 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2962 * stopped by the hypervisor. This function will be called from the host only.
2963 * EINVAL is returned when the host attempts to set the flag for a guest that
2964 * does not support pv clocks.
2965 */
2966 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2967 {
2968 if (!vcpu->arch.time_page)
2969 return -EINVAL;
2970 vcpu->arch.pvclock_set_guest_stopped_request = true;
2971 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2972 return 0;
2973 }
2974
2975 long kvm_arch_vcpu_ioctl(struct file *filp,
2976 unsigned int ioctl, unsigned long arg)
2977 {
2978 struct kvm_vcpu *vcpu = filp->private_data;
2979 void __user *argp = (void __user *)arg;
2980 int r;
2981 union {
2982 struct kvm_lapic_state *lapic;
2983 struct kvm_xsave *xsave;
2984 struct kvm_xcrs *xcrs;
2985 void *buffer;
2986 } u;
2987
2988 u.buffer = NULL;
2989 switch (ioctl) {
2990 case KVM_GET_LAPIC: {
2991 r = -EINVAL;
2992 if (!vcpu->arch.apic)
2993 goto out;
2994 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2995
2996 r = -ENOMEM;
2997 if (!u.lapic)
2998 goto out;
2999 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3000 if (r)
3001 goto out;
3002 r = -EFAULT;
3003 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3004 goto out;
3005 r = 0;
3006 break;
3007 }
3008 case KVM_SET_LAPIC: {
3009 if (!vcpu->arch.apic)
3010 goto out;
3011 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3012 if (IS_ERR(u.lapic))
3013 return PTR_ERR(u.lapic);
3014
3015 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3016 break;
3017 }
3018 case KVM_INTERRUPT: {
3019 struct kvm_interrupt irq;
3020
3021 r = -EFAULT;
3022 if (copy_from_user(&irq, argp, sizeof irq))
3023 goto out;
3024 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3025 break;
3026 }
3027 case KVM_NMI: {
3028 r = kvm_vcpu_ioctl_nmi(vcpu);
3029 break;
3030 }
3031 case KVM_SET_CPUID: {
3032 struct kvm_cpuid __user *cpuid_arg = argp;
3033 struct kvm_cpuid cpuid;
3034
3035 r = -EFAULT;
3036 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3037 goto out;
3038 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3039 break;
3040 }
3041 case KVM_SET_CPUID2: {
3042 struct kvm_cpuid2 __user *cpuid_arg = argp;
3043 struct kvm_cpuid2 cpuid;
3044
3045 r = -EFAULT;
3046 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3047 goto out;
3048 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3049 cpuid_arg->entries);
3050 break;
3051 }
3052 case KVM_GET_CPUID2: {
3053 struct kvm_cpuid2 __user *cpuid_arg = argp;
3054 struct kvm_cpuid2 cpuid;
3055
3056 r = -EFAULT;
3057 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3058 goto out;
3059 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3060 cpuid_arg->entries);
3061 if (r)
3062 goto out;
3063 r = -EFAULT;
3064 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3065 goto out;
3066 r = 0;
3067 break;
3068 }
3069 case KVM_GET_MSRS:
3070 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3071 break;
3072 case KVM_SET_MSRS:
3073 r = msr_io(vcpu, argp, do_set_msr, 0);
3074 break;
3075 case KVM_TPR_ACCESS_REPORTING: {
3076 struct kvm_tpr_access_ctl tac;
3077
3078 r = -EFAULT;
3079 if (copy_from_user(&tac, argp, sizeof tac))
3080 goto out;
3081 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3082 if (r)
3083 goto out;
3084 r = -EFAULT;
3085 if (copy_to_user(argp, &tac, sizeof tac))
3086 goto out;
3087 r = 0;
3088 break;
3089 };
3090 case KVM_SET_VAPIC_ADDR: {
3091 struct kvm_vapic_addr va;
3092
3093 r = -EINVAL;
3094 if (!irqchip_in_kernel(vcpu->kvm))
3095 goto out;
3096 r = -EFAULT;
3097 if (copy_from_user(&va, argp, sizeof va))
3098 goto out;
3099 r = 0;
3100 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3101 break;
3102 }
3103 case KVM_X86_SETUP_MCE: {
3104 u64 mcg_cap;
3105
3106 r = -EFAULT;
3107 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3108 goto out;
3109 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3110 break;
3111 }
3112 case KVM_X86_SET_MCE: {
3113 struct kvm_x86_mce mce;
3114
3115 r = -EFAULT;
3116 if (copy_from_user(&mce, argp, sizeof mce))
3117 goto out;
3118 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3119 break;
3120 }
3121 case KVM_GET_VCPU_EVENTS: {
3122 struct kvm_vcpu_events events;
3123
3124 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3125
3126 r = -EFAULT;
3127 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3128 break;
3129 r = 0;
3130 break;
3131 }
3132 case KVM_SET_VCPU_EVENTS: {
3133 struct kvm_vcpu_events events;
3134
3135 r = -EFAULT;
3136 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3137 break;
3138
3139 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3140 break;
3141 }
3142 case KVM_GET_DEBUGREGS: {
3143 struct kvm_debugregs dbgregs;
3144
3145 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3146
3147 r = -EFAULT;
3148 if (copy_to_user(argp, &dbgregs,
3149 sizeof(struct kvm_debugregs)))
3150 break;
3151 r = 0;
3152 break;
3153 }
3154 case KVM_SET_DEBUGREGS: {
3155 struct kvm_debugregs dbgregs;
3156
3157 r = -EFAULT;
3158 if (copy_from_user(&dbgregs, argp,
3159 sizeof(struct kvm_debugregs)))
3160 break;
3161
3162 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3163 break;
3164 }
3165 case KVM_GET_XSAVE: {
3166 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3167 r = -ENOMEM;
3168 if (!u.xsave)
3169 break;
3170
3171 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3172
3173 r = -EFAULT;
3174 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3175 break;
3176 r = 0;
3177 break;
3178 }
3179 case KVM_SET_XSAVE: {
3180 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3181 if (IS_ERR(u.xsave))
3182 return PTR_ERR(u.xsave);
3183
3184 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3185 break;
3186 }
3187 case KVM_GET_XCRS: {
3188 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3189 r = -ENOMEM;
3190 if (!u.xcrs)
3191 break;
3192
3193 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3194
3195 r = -EFAULT;
3196 if (copy_to_user(argp, u.xcrs,
3197 sizeof(struct kvm_xcrs)))
3198 break;
3199 r = 0;
3200 break;
3201 }
3202 case KVM_SET_XCRS: {
3203 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3204 if (IS_ERR(u.xcrs))
3205 return PTR_ERR(u.xcrs);
3206
3207 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3208 break;
3209 }
3210 case KVM_SET_TSC_KHZ: {
3211 u32 user_tsc_khz;
3212
3213 r = -EINVAL;
3214 user_tsc_khz = (u32)arg;
3215
3216 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3217 goto out;
3218
3219 if (user_tsc_khz == 0)
3220 user_tsc_khz = tsc_khz;
3221
3222 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3223
3224 r = 0;
3225 goto out;
3226 }
3227 case KVM_GET_TSC_KHZ: {
3228 r = vcpu->arch.virtual_tsc_khz;
3229 goto out;
3230 }
3231 case KVM_KVMCLOCK_CTRL: {
3232 r = kvm_set_guest_paused(vcpu);
3233 goto out;
3234 }
3235 default:
3236 r = -EINVAL;
3237 }
3238 out:
3239 kfree(u.buffer);
3240 return r;
3241 }
3242
3243 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3244 {
3245 return VM_FAULT_SIGBUS;
3246 }
3247
3248 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3249 {
3250 int ret;
3251
3252 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3253 return -EINVAL;
3254 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3255 return ret;
3256 }
3257
3258 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3259 u64 ident_addr)
3260 {
3261 kvm->arch.ept_identity_map_addr = ident_addr;
3262 return 0;
3263 }
3264
3265 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3266 u32 kvm_nr_mmu_pages)
3267 {
3268 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3269 return -EINVAL;
3270
3271 mutex_lock(&kvm->slots_lock);
3272 spin_lock(&kvm->mmu_lock);
3273
3274 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3275 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3276
3277 spin_unlock(&kvm->mmu_lock);
3278 mutex_unlock(&kvm->slots_lock);
3279 return 0;
3280 }
3281
3282 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3283 {
3284 return kvm->arch.n_max_mmu_pages;
3285 }
3286
3287 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3288 {
3289 int r;
3290
3291 r = 0;
3292 switch (chip->chip_id) {
3293 case KVM_IRQCHIP_PIC_MASTER:
3294 memcpy(&chip->chip.pic,
3295 &pic_irqchip(kvm)->pics[0],
3296 sizeof(struct kvm_pic_state));
3297 break;
3298 case KVM_IRQCHIP_PIC_SLAVE:
3299 memcpy(&chip->chip.pic,
3300 &pic_irqchip(kvm)->pics[1],
3301 sizeof(struct kvm_pic_state));
3302 break;
3303 case KVM_IRQCHIP_IOAPIC:
3304 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3305 break;
3306 default:
3307 r = -EINVAL;
3308 break;
3309 }
3310 return r;
3311 }
3312
3313 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3314 {
3315 int r;
3316
3317 r = 0;
3318 switch (chip->chip_id) {
3319 case KVM_IRQCHIP_PIC_MASTER:
3320 spin_lock(&pic_irqchip(kvm)->lock);
3321 memcpy(&pic_irqchip(kvm)->pics[0],
3322 &chip->chip.pic,
3323 sizeof(struct kvm_pic_state));
3324 spin_unlock(&pic_irqchip(kvm)->lock);
3325 break;
3326 case KVM_IRQCHIP_PIC_SLAVE:
3327 spin_lock(&pic_irqchip(kvm)->lock);
3328 memcpy(&pic_irqchip(kvm)->pics[1],
3329 &chip->chip.pic,
3330 sizeof(struct kvm_pic_state));
3331 spin_unlock(&pic_irqchip(kvm)->lock);
3332 break;
3333 case KVM_IRQCHIP_IOAPIC:
3334 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3335 break;
3336 default:
3337 r = -EINVAL;
3338 break;
3339 }
3340 kvm_pic_update_irq(pic_irqchip(kvm));
3341 return r;
3342 }
3343
3344 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3345 {
3346 int r = 0;
3347
3348 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3349 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3350 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3351 return r;
3352 }
3353
3354 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3355 {
3356 int r = 0;
3357
3358 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3359 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3360 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3361 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3362 return r;
3363 }
3364
3365 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3366 {
3367 int r = 0;
3368
3369 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3370 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3371 sizeof(ps->channels));
3372 ps->flags = kvm->arch.vpit->pit_state.flags;
3373 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3374 memset(&ps->reserved, 0, sizeof(ps->reserved));
3375 return r;
3376 }
3377
3378 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3379 {
3380 int r = 0, start = 0;
3381 u32 prev_legacy, cur_legacy;
3382 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3383 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3384 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3385 if (!prev_legacy && cur_legacy)
3386 start = 1;
3387 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3388 sizeof(kvm->arch.vpit->pit_state.channels));
3389 kvm->arch.vpit->pit_state.flags = ps->flags;
3390 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3391 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3392 return r;
3393 }
3394
3395 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3396 struct kvm_reinject_control *control)
3397 {
3398 if (!kvm->arch.vpit)
3399 return -ENXIO;
3400 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3401 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3402 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3403 return 0;
3404 }
3405
3406 /**
3407 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3408 * @kvm: kvm instance
3409 * @log: slot id and address to which we copy the log
3410 *
3411 * We need to keep it in mind that VCPU threads can write to the bitmap
3412 * concurrently. So, to avoid losing data, we keep the following order for
3413 * each bit:
3414 *
3415 * 1. Take a snapshot of the bit and clear it if needed.
3416 * 2. Write protect the corresponding page.
3417 * 3. Flush TLB's if needed.
3418 * 4. Copy the snapshot to the userspace.
3419 *
3420 * Between 2 and 3, the guest may write to the page using the remaining TLB
3421 * entry. This is not a problem because the page will be reported dirty at
3422 * step 4 using the snapshot taken before and step 3 ensures that successive
3423 * writes will be logged for the next call.
3424 */
3425 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3426 {
3427 int r;
3428 struct kvm_memory_slot *memslot;
3429 unsigned long n, i;
3430 unsigned long *dirty_bitmap;
3431 unsigned long *dirty_bitmap_buffer;
3432 bool is_dirty = false;
3433
3434 mutex_lock(&kvm->slots_lock);
3435
3436 r = -EINVAL;
3437 if (log->slot >= KVM_MEMORY_SLOTS)
3438 goto out;
3439
3440 memslot = id_to_memslot(kvm->memslots, log->slot);
3441
3442 dirty_bitmap = memslot->dirty_bitmap;
3443 r = -ENOENT;
3444 if (!dirty_bitmap)
3445 goto out;
3446
3447 n = kvm_dirty_bitmap_bytes(memslot);
3448
3449 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3450 memset(dirty_bitmap_buffer, 0, n);
3451
3452 spin_lock(&kvm->mmu_lock);
3453
3454 for (i = 0; i < n / sizeof(long); i++) {
3455 unsigned long mask;
3456 gfn_t offset;
3457
3458 if (!dirty_bitmap[i])
3459 continue;
3460
3461 is_dirty = true;
3462
3463 mask = xchg(&dirty_bitmap[i], 0);
3464 dirty_bitmap_buffer[i] = mask;
3465
3466 offset = i * BITS_PER_LONG;
3467 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3468 }
3469 if (is_dirty)
3470 kvm_flush_remote_tlbs(kvm);
3471
3472 spin_unlock(&kvm->mmu_lock);
3473
3474 r = -EFAULT;
3475 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3476 goto out;
3477
3478 r = 0;
3479 out:
3480 mutex_unlock(&kvm->slots_lock);
3481 return r;
3482 }
3483
3484 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3485 {
3486 if (!irqchip_in_kernel(kvm))
3487 return -ENXIO;
3488
3489 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3490 irq_event->irq, irq_event->level);
3491 return 0;
3492 }
3493
3494 long kvm_arch_vm_ioctl(struct file *filp,
3495 unsigned int ioctl, unsigned long arg)
3496 {
3497 struct kvm *kvm = filp->private_data;
3498 void __user *argp = (void __user *)arg;
3499 int r = -ENOTTY;
3500 /*
3501 * This union makes it completely explicit to gcc-3.x
3502 * that these two variables' stack usage should be
3503 * combined, not added together.
3504 */
3505 union {
3506 struct kvm_pit_state ps;
3507 struct kvm_pit_state2 ps2;
3508 struct kvm_pit_config pit_config;
3509 } u;
3510
3511 switch (ioctl) {
3512 case KVM_SET_TSS_ADDR:
3513 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3514 break;
3515 case KVM_SET_IDENTITY_MAP_ADDR: {
3516 u64 ident_addr;
3517
3518 r = -EFAULT;
3519 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3520 goto out;
3521 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3522 break;
3523 }
3524 case KVM_SET_NR_MMU_PAGES:
3525 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3526 break;
3527 case KVM_GET_NR_MMU_PAGES:
3528 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3529 break;
3530 case KVM_CREATE_IRQCHIP: {
3531 struct kvm_pic *vpic;
3532
3533 mutex_lock(&kvm->lock);
3534 r = -EEXIST;
3535 if (kvm->arch.vpic)
3536 goto create_irqchip_unlock;
3537 r = -EINVAL;
3538 if (atomic_read(&kvm->online_vcpus))
3539 goto create_irqchip_unlock;
3540 r = -ENOMEM;
3541 vpic = kvm_create_pic(kvm);
3542 if (vpic) {
3543 r = kvm_ioapic_init(kvm);
3544 if (r) {
3545 mutex_lock(&kvm->slots_lock);
3546 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3547 &vpic->dev_master);
3548 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3549 &vpic->dev_slave);
3550 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3551 &vpic->dev_eclr);
3552 mutex_unlock(&kvm->slots_lock);
3553 kfree(vpic);
3554 goto create_irqchip_unlock;
3555 }
3556 } else
3557 goto create_irqchip_unlock;
3558 smp_wmb();
3559 kvm->arch.vpic = vpic;
3560 smp_wmb();
3561 r = kvm_setup_default_irq_routing(kvm);
3562 if (r) {
3563 mutex_lock(&kvm->slots_lock);
3564 mutex_lock(&kvm->irq_lock);
3565 kvm_ioapic_destroy(kvm);
3566 kvm_destroy_pic(kvm);
3567 mutex_unlock(&kvm->irq_lock);
3568 mutex_unlock(&kvm->slots_lock);
3569 }
3570 create_irqchip_unlock:
3571 mutex_unlock(&kvm->lock);
3572 break;
3573 }
3574 case KVM_CREATE_PIT:
3575 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3576 goto create_pit;
3577 case KVM_CREATE_PIT2:
3578 r = -EFAULT;
3579 if (copy_from_user(&u.pit_config, argp,
3580 sizeof(struct kvm_pit_config)))
3581 goto out;
3582 create_pit:
3583 mutex_lock(&kvm->slots_lock);
3584 r = -EEXIST;
3585 if (kvm->arch.vpit)
3586 goto create_pit_unlock;
3587 r = -ENOMEM;
3588 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3589 if (kvm->arch.vpit)
3590 r = 0;
3591 create_pit_unlock:
3592 mutex_unlock(&kvm->slots_lock);
3593 break;
3594 case KVM_GET_IRQCHIP: {
3595 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3596 struct kvm_irqchip *chip;
3597
3598 chip = memdup_user(argp, sizeof(*chip));
3599 if (IS_ERR(chip)) {
3600 r = PTR_ERR(chip);
3601 goto out;
3602 }
3603
3604 r = -ENXIO;
3605 if (!irqchip_in_kernel(kvm))
3606 goto get_irqchip_out;
3607 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3608 if (r)
3609 goto get_irqchip_out;
3610 r = -EFAULT;
3611 if (copy_to_user(argp, chip, sizeof *chip))
3612 goto get_irqchip_out;
3613 r = 0;
3614 get_irqchip_out:
3615 kfree(chip);
3616 break;
3617 }
3618 case KVM_SET_IRQCHIP: {
3619 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3620 struct kvm_irqchip *chip;
3621
3622 chip = memdup_user(argp, sizeof(*chip));
3623 if (IS_ERR(chip)) {
3624 r = PTR_ERR(chip);
3625 goto out;
3626 }
3627
3628 r = -ENXIO;
3629 if (!irqchip_in_kernel(kvm))
3630 goto set_irqchip_out;
3631 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3632 if (r)
3633 goto set_irqchip_out;
3634 r = 0;
3635 set_irqchip_out:
3636 kfree(chip);
3637 break;
3638 }
3639 case KVM_GET_PIT: {
3640 r = -EFAULT;
3641 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3642 goto out;
3643 r = -ENXIO;
3644 if (!kvm->arch.vpit)
3645 goto out;
3646 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3647 if (r)
3648 goto out;
3649 r = -EFAULT;
3650 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3651 goto out;
3652 r = 0;
3653 break;
3654 }
3655 case KVM_SET_PIT: {
3656 r = -EFAULT;
3657 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3658 goto out;
3659 r = -ENXIO;
3660 if (!kvm->arch.vpit)
3661 goto out;
3662 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3663 break;
3664 }
3665 case KVM_GET_PIT2: {
3666 r = -ENXIO;
3667 if (!kvm->arch.vpit)
3668 goto out;
3669 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3670 if (r)
3671 goto out;
3672 r = -EFAULT;
3673 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3674 goto out;
3675 r = 0;
3676 break;
3677 }
3678 case KVM_SET_PIT2: {
3679 r = -EFAULT;
3680 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3681 goto out;
3682 r = -ENXIO;
3683 if (!kvm->arch.vpit)
3684 goto out;
3685 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3686 break;
3687 }
3688 case KVM_REINJECT_CONTROL: {
3689 struct kvm_reinject_control control;
3690 r = -EFAULT;
3691 if (copy_from_user(&control, argp, sizeof(control)))
3692 goto out;
3693 r = kvm_vm_ioctl_reinject(kvm, &control);
3694 break;
3695 }
3696 case KVM_XEN_HVM_CONFIG: {
3697 r = -EFAULT;
3698 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3699 sizeof(struct kvm_xen_hvm_config)))
3700 goto out;
3701 r = -EINVAL;
3702 if (kvm->arch.xen_hvm_config.flags)
3703 goto out;
3704 r = 0;
3705 break;
3706 }
3707 case KVM_SET_CLOCK: {
3708 struct kvm_clock_data user_ns;
3709 u64 now_ns;
3710 s64 delta;
3711
3712 r = -EFAULT;
3713 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3714 goto out;
3715
3716 r = -EINVAL;
3717 if (user_ns.flags)
3718 goto out;
3719
3720 r = 0;
3721 local_irq_disable();
3722 now_ns = get_kernel_ns();
3723 delta = user_ns.clock - now_ns;
3724 local_irq_enable();
3725 kvm->arch.kvmclock_offset = delta;
3726 break;
3727 }
3728 case KVM_GET_CLOCK: {
3729 struct kvm_clock_data user_ns;
3730 u64 now_ns;
3731
3732 local_irq_disable();
3733 now_ns = get_kernel_ns();
3734 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3735 local_irq_enable();
3736 user_ns.flags = 0;
3737 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3738
3739 r = -EFAULT;
3740 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3741 goto out;
3742 r = 0;
3743 break;
3744 }
3745
3746 default:
3747 ;
3748 }
3749 out:
3750 return r;
3751 }
3752
3753 static void kvm_init_msr_list(void)
3754 {
3755 u32 dummy[2];
3756 unsigned i, j;
3757
3758 /* skip the first msrs in the list. KVM-specific */
3759 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3760 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3761 continue;
3762 if (j < i)
3763 msrs_to_save[j] = msrs_to_save[i];
3764 j++;
3765 }
3766 num_msrs_to_save = j;
3767 }
3768
3769 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3770 const void *v)
3771 {
3772 int handled = 0;
3773 int n;
3774
3775 do {
3776 n = min(len, 8);
3777 if (!(vcpu->arch.apic &&
3778 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3779 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3780 break;
3781 handled += n;
3782 addr += n;
3783 len -= n;
3784 v += n;
3785 } while (len);
3786
3787 return handled;
3788 }
3789
3790 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3791 {
3792 int handled = 0;
3793 int n;
3794
3795 do {
3796 n = min(len, 8);
3797 if (!(vcpu->arch.apic &&
3798 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3799 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3800 break;
3801 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3802 handled += n;
3803 addr += n;
3804 len -= n;
3805 v += n;
3806 } while (len);
3807
3808 return handled;
3809 }
3810
3811 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3812 struct kvm_segment *var, int seg)
3813 {
3814 kvm_x86_ops->set_segment(vcpu, var, seg);
3815 }
3816
3817 void kvm_get_segment(struct kvm_vcpu *vcpu,
3818 struct kvm_segment *var, int seg)
3819 {
3820 kvm_x86_ops->get_segment(vcpu, var, seg);
3821 }
3822
3823 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3824 {
3825 gpa_t t_gpa;
3826 struct x86_exception exception;
3827
3828 BUG_ON(!mmu_is_nested(vcpu));
3829
3830 /* NPT walks are always user-walks */
3831 access |= PFERR_USER_MASK;
3832 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3833
3834 return t_gpa;
3835 }
3836
3837 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3838 struct x86_exception *exception)
3839 {
3840 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3841 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3842 }
3843
3844 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3845 struct x86_exception *exception)
3846 {
3847 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3848 access |= PFERR_FETCH_MASK;
3849 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3850 }
3851
3852 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3853 struct x86_exception *exception)
3854 {
3855 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3856 access |= PFERR_WRITE_MASK;
3857 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3858 }
3859
3860 /* uses this to access any guest's mapped memory without checking CPL */
3861 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3862 struct x86_exception *exception)
3863 {
3864 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3865 }
3866
3867 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3868 struct kvm_vcpu *vcpu, u32 access,
3869 struct x86_exception *exception)
3870 {
3871 void *data = val;
3872 int r = X86EMUL_CONTINUE;
3873
3874 while (bytes) {
3875 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3876 exception);
3877 unsigned offset = addr & (PAGE_SIZE-1);
3878 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3879 int ret;
3880
3881 if (gpa == UNMAPPED_GVA)
3882 return X86EMUL_PROPAGATE_FAULT;
3883 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3884 if (ret < 0) {
3885 r = X86EMUL_IO_NEEDED;
3886 goto out;
3887 }
3888
3889 bytes -= toread;
3890 data += toread;
3891 addr += toread;
3892 }
3893 out:
3894 return r;
3895 }
3896
3897 /* used for instruction fetching */
3898 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3899 gva_t addr, void *val, unsigned int bytes,
3900 struct x86_exception *exception)
3901 {
3902 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3903 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3904
3905 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3906 access | PFERR_FETCH_MASK,
3907 exception);
3908 }
3909
3910 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3911 gva_t addr, void *val, unsigned int bytes,
3912 struct x86_exception *exception)
3913 {
3914 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3915 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3916
3917 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3918 exception);
3919 }
3920 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3921
3922 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3923 gva_t addr, void *val, unsigned int bytes,
3924 struct x86_exception *exception)
3925 {
3926 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3927 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3928 }
3929
3930 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3931 gva_t addr, void *val,
3932 unsigned int bytes,
3933 struct x86_exception *exception)
3934 {
3935 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3936 void *data = val;
3937 int r = X86EMUL_CONTINUE;
3938
3939 while (bytes) {
3940 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3941 PFERR_WRITE_MASK,
3942 exception);
3943 unsigned offset = addr & (PAGE_SIZE-1);
3944 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3945 int ret;
3946
3947 if (gpa == UNMAPPED_GVA)
3948 return X86EMUL_PROPAGATE_FAULT;
3949 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3950 if (ret < 0) {
3951 r = X86EMUL_IO_NEEDED;
3952 goto out;
3953 }
3954
3955 bytes -= towrite;
3956 data += towrite;
3957 addr += towrite;
3958 }
3959 out:
3960 return r;
3961 }
3962 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3963
3964 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3965 gpa_t *gpa, struct x86_exception *exception,
3966 bool write)
3967 {
3968 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3969 | (write ? PFERR_WRITE_MASK : 0);
3970
3971 if (vcpu_match_mmio_gva(vcpu, gva)
3972 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
3973 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3974 (gva & (PAGE_SIZE - 1));
3975 trace_vcpu_match_mmio(gva, *gpa, write, false);
3976 return 1;
3977 }
3978
3979 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3980
3981 if (*gpa == UNMAPPED_GVA)
3982 return -1;
3983
3984 /* For APIC access vmexit */
3985 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3986 return 1;
3987
3988 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3989 trace_vcpu_match_mmio(gva, *gpa, write, true);
3990 return 1;
3991 }
3992
3993 return 0;
3994 }
3995
3996 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3997 const void *val, int bytes)
3998 {
3999 int ret;
4000
4001 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4002 if (ret < 0)
4003 return 0;
4004 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4005 return 1;
4006 }
4007
4008 struct read_write_emulator_ops {
4009 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4010 int bytes);
4011 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4012 void *val, int bytes);
4013 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4014 int bytes, void *val);
4015 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4016 void *val, int bytes);
4017 bool write;
4018 };
4019
4020 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4021 {
4022 if (vcpu->mmio_read_completed) {
4023 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4024 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4025 vcpu->mmio_read_completed = 0;
4026 return 1;
4027 }
4028
4029 return 0;
4030 }
4031
4032 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4033 void *val, int bytes)
4034 {
4035 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4036 }
4037
4038 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4039 void *val, int bytes)
4040 {
4041 return emulator_write_phys(vcpu, gpa, val, bytes);
4042 }
4043
4044 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4045 {
4046 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4047 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4048 }
4049
4050 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4051 void *val, int bytes)
4052 {
4053 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4054 return X86EMUL_IO_NEEDED;
4055 }
4056
4057 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4058 void *val, int bytes)
4059 {
4060 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4061
4062 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
4063 return X86EMUL_CONTINUE;
4064 }
4065
4066 static const struct read_write_emulator_ops read_emultor = {
4067 .read_write_prepare = read_prepare,
4068 .read_write_emulate = read_emulate,
4069 .read_write_mmio = vcpu_mmio_read,
4070 .read_write_exit_mmio = read_exit_mmio,
4071 };
4072
4073 static const struct read_write_emulator_ops write_emultor = {
4074 .read_write_emulate = write_emulate,
4075 .read_write_mmio = write_mmio,
4076 .read_write_exit_mmio = write_exit_mmio,
4077 .write = true,
4078 };
4079
4080 static int emulator_read_write_onepage(unsigned long addr, void *val,
4081 unsigned int bytes,
4082 struct x86_exception *exception,
4083 struct kvm_vcpu *vcpu,
4084 const struct read_write_emulator_ops *ops)
4085 {
4086 gpa_t gpa;
4087 int handled, ret;
4088 bool write = ops->write;
4089 struct kvm_mmio_fragment *frag;
4090
4091 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4092
4093 if (ret < 0)
4094 return X86EMUL_PROPAGATE_FAULT;
4095
4096 /* For APIC access vmexit */
4097 if (ret)
4098 goto mmio;
4099
4100 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4101 return X86EMUL_CONTINUE;
4102
4103 mmio:
4104 /*
4105 * Is this MMIO handled locally?
4106 */
4107 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4108 if (handled == bytes)
4109 return X86EMUL_CONTINUE;
4110
4111 gpa += handled;
4112 bytes -= handled;
4113 val += handled;
4114
4115 while (bytes) {
4116 unsigned now = min(bytes, 8U);
4117
4118 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4119 frag->gpa = gpa;
4120 frag->data = val;
4121 frag->len = now;
4122
4123 gpa += now;
4124 val += now;
4125 bytes -= now;
4126 }
4127 return X86EMUL_CONTINUE;
4128 }
4129
4130 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4131 void *val, unsigned int bytes,
4132 struct x86_exception *exception,
4133 const struct read_write_emulator_ops *ops)
4134 {
4135 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4136 gpa_t gpa;
4137 int rc;
4138
4139 if (ops->read_write_prepare &&
4140 ops->read_write_prepare(vcpu, val, bytes))
4141 return X86EMUL_CONTINUE;
4142
4143 vcpu->mmio_nr_fragments = 0;
4144
4145 /* Crossing a page boundary? */
4146 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4147 int now;
4148
4149 now = -addr & ~PAGE_MASK;
4150 rc = emulator_read_write_onepage(addr, val, now, exception,
4151 vcpu, ops);
4152
4153 if (rc != X86EMUL_CONTINUE)
4154 return rc;
4155 addr += now;
4156 val += now;
4157 bytes -= now;
4158 }
4159
4160 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4161 vcpu, ops);
4162 if (rc != X86EMUL_CONTINUE)
4163 return rc;
4164
4165 if (!vcpu->mmio_nr_fragments)
4166 return rc;
4167
4168 gpa = vcpu->mmio_fragments[0].gpa;
4169
4170 vcpu->mmio_needed = 1;
4171 vcpu->mmio_cur_fragment = 0;
4172
4173 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
4174 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4175 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4176 vcpu->run->mmio.phys_addr = gpa;
4177
4178 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4179 }
4180
4181 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4182 unsigned long addr,
4183 void *val,
4184 unsigned int bytes,
4185 struct x86_exception *exception)
4186 {
4187 return emulator_read_write(ctxt, addr, val, bytes,
4188 exception, &read_emultor);
4189 }
4190
4191 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4192 unsigned long addr,
4193 const void *val,
4194 unsigned int bytes,
4195 struct x86_exception *exception)
4196 {
4197 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4198 exception, &write_emultor);
4199 }
4200
4201 #define CMPXCHG_TYPE(t, ptr, old, new) \
4202 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4203
4204 #ifdef CONFIG_X86_64
4205 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4206 #else
4207 # define CMPXCHG64(ptr, old, new) \
4208 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4209 #endif
4210
4211 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4212 unsigned long addr,
4213 const void *old,
4214 const void *new,
4215 unsigned int bytes,
4216 struct x86_exception *exception)
4217 {
4218 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4219 gpa_t gpa;
4220 struct page *page;
4221 char *kaddr;
4222 bool exchanged;
4223
4224 /* guests cmpxchg8b have to be emulated atomically */
4225 if (bytes > 8 || (bytes & (bytes - 1)))
4226 goto emul_write;
4227
4228 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4229
4230 if (gpa == UNMAPPED_GVA ||
4231 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4232 goto emul_write;
4233
4234 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4235 goto emul_write;
4236
4237 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4238 if (is_error_page(page))
4239 goto emul_write;
4240
4241 kaddr = kmap_atomic(page);
4242 kaddr += offset_in_page(gpa);
4243 switch (bytes) {
4244 case 1:
4245 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4246 break;
4247 case 2:
4248 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4249 break;
4250 case 4:
4251 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4252 break;
4253 case 8:
4254 exchanged = CMPXCHG64(kaddr, old, new);
4255 break;
4256 default:
4257 BUG();
4258 }
4259 kunmap_atomic(kaddr);
4260 kvm_release_page_dirty(page);
4261
4262 if (!exchanged)
4263 return X86EMUL_CMPXCHG_FAILED;
4264
4265 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4266
4267 return X86EMUL_CONTINUE;
4268
4269 emul_write:
4270 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4271
4272 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4273 }
4274
4275 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4276 {
4277 /* TODO: String I/O for in kernel device */
4278 int r;
4279
4280 if (vcpu->arch.pio.in)
4281 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4282 vcpu->arch.pio.size, pd);
4283 else
4284 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4285 vcpu->arch.pio.port, vcpu->arch.pio.size,
4286 pd);
4287 return r;
4288 }
4289
4290 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4291 unsigned short port, void *val,
4292 unsigned int count, bool in)
4293 {
4294 trace_kvm_pio(!in, port, size, count);
4295
4296 vcpu->arch.pio.port = port;
4297 vcpu->arch.pio.in = in;
4298 vcpu->arch.pio.count = count;
4299 vcpu->arch.pio.size = size;
4300
4301 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4302 vcpu->arch.pio.count = 0;
4303 return 1;
4304 }
4305
4306 vcpu->run->exit_reason = KVM_EXIT_IO;
4307 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4308 vcpu->run->io.size = size;
4309 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4310 vcpu->run->io.count = count;
4311 vcpu->run->io.port = port;
4312
4313 return 0;
4314 }
4315
4316 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4317 int size, unsigned short port, void *val,
4318 unsigned int count)
4319 {
4320 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4321 int ret;
4322
4323 if (vcpu->arch.pio.count)
4324 goto data_avail;
4325
4326 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4327 if (ret) {
4328 data_avail:
4329 memcpy(val, vcpu->arch.pio_data, size * count);
4330 vcpu->arch.pio.count = 0;
4331 return 1;
4332 }
4333
4334 return 0;
4335 }
4336
4337 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4338 int size, unsigned short port,
4339 const void *val, unsigned int count)
4340 {
4341 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4342
4343 memcpy(vcpu->arch.pio_data, val, size * count);
4344 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4345 }
4346
4347 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4348 {
4349 return kvm_x86_ops->get_segment_base(vcpu, seg);
4350 }
4351
4352 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4353 {
4354 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4355 }
4356
4357 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4358 {
4359 if (!need_emulate_wbinvd(vcpu))
4360 return X86EMUL_CONTINUE;
4361
4362 if (kvm_x86_ops->has_wbinvd_exit()) {
4363 int cpu = get_cpu();
4364
4365 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4366 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4367 wbinvd_ipi, NULL, 1);
4368 put_cpu();
4369 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4370 } else
4371 wbinvd();
4372 return X86EMUL_CONTINUE;
4373 }
4374 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4375
4376 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4377 {
4378 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4379 }
4380
4381 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4382 {
4383 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4384 }
4385
4386 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4387 {
4388
4389 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4390 }
4391
4392 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4393 {
4394 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4395 }
4396
4397 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4398 {
4399 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4400 unsigned long value;
4401
4402 switch (cr) {
4403 case 0:
4404 value = kvm_read_cr0(vcpu);
4405 break;
4406 case 2:
4407 value = vcpu->arch.cr2;
4408 break;
4409 case 3:
4410 value = kvm_read_cr3(vcpu);
4411 break;
4412 case 4:
4413 value = kvm_read_cr4(vcpu);
4414 break;
4415 case 8:
4416 value = kvm_get_cr8(vcpu);
4417 break;
4418 default:
4419 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4420 return 0;
4421 }
4422
4423 return value;
4424 }
4425
4426 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4427 {
4428 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4429 int res = 0;
4430
4431 switch (cr) {
4432 case 0:
4433 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4434 break;
4435 case 2:
4436 vcpu->arch.cr2 = val;
4437 break;
4438 case 3:
4439 res = kvm_set_cr3(vcpu, val);
4440 break;
4441 case 4:
4442 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4443 break;
4444 case 8:
4445 res = kvm_set_cr8(vcpu, val);
4446 break;
4447 default:
4448 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4449 res = -1;
4450 }
4451
4452 return res;
4453 }
4454
4455 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4456 {
4457 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4458 }
4459
4460 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4461 {
4462 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4463 }
4464
4465 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4466 {
4467 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4468 }
4469
4470 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4471 {
4472 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4473 }
4474
4475 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4476 {
4477 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4478 }
4479
4480 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4481 {
4482 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4483 }
4484
4485 static unsigned long emulator_get_cached_segment_base(
4486 struct x86_emulate_ctxt *ctxt, int seg)
4487 {
4488 return get_segment_base(emul_to_vcpu(ctxt), seg);
4489 }
4490
4491 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4492 struct desc_struct *desc, u32 *base3,
4493 int seg)
4494 {
4495 struct kvm_segment var;
4496
4497 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4498 *selector = var.selector;
4499
4500 if (var.unusable)
4501 return false;
4502
4503 if (var.g)
4504 var.limit >>= 12;
4505 set_desc_limit(desc, var.limit);
4506 set_desc_base(desc, (unsigned long)var.base);
4507 #ifdef CONFIG_X86_64
4508 if (base3)
4509 *base3 = var.base >> 32;
4510 #endif
4511 desc->type = var.type;
4512 desc->s = var.s;
4513 desc->dpl = var.dpl;
4514 desc->p = var.present;
4515 desc->avl = var.avl;
4516 desc->l = var.l;
4517 desc->d = var.db;
4518 desc->g = var.g;
4519
4520 return true;
4521 }
4522
4523 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4524 struct desc_struct *desc, u32 base3,
4525 int seg)
4526 {
4527 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4528 struct kvm_segment var;
4529
4530 var.selector = selector;
4531 var.base = get_desc_base(desc);
4532 #ifdef CONFIG_X86_64
4533 var.base |= ((u64)base3) << 32;
4534 #endif
4535 var.limit = get_desc_limit(desc);
4536 if (desc->g)
4537 var.limit = (var.limit << 12) | 0xfff;
4538 var.type = desc->type;
4539 var.present = desc->p;
4540 var.dpl = desc->dpl;
4541 var.db = desc->d;
4542 var.s = desc->s;
4543 var.l = desc->l;
4544 var.g = desc->g;
4545 var.avl = desc->avl;
4546 var.present = desc->p;
4547 var.unusable = !var.present;
4548 var.padding = 0;
4549
4550 kvm_set_segment(vcpu, &var, seg);
4551 return;
4552 }
4553
4554 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4555 u32 msr_index, u64 *pdata)
4556 {
4557 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4558 }
4559
4560 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4561 u32 msr_index, u64 data)
4562 {
4563 struct msr_data msr;
4564
4565 msr.data = data;
4566 msr.index = msr_index;
4567 msr.host_initiated = false;
4568 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4569 }
4570
4571 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4572 u32 pmc, u64 *pdata)
4573 {
4574 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4575 }
4576
4577 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4578 {
4579 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4580 }
4581
4582 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4583 {
4584 preempt_disable();
4585 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4586 /*
4587 * CR0.TS may reference the host fpu state, not the guest fpu state,
4588 * so it may be clear at this point.
4589 */
4590 clts();
4591 }
4592
4593 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4594 {
4595 preempt_enable();
4596 }
4597
4598 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4599 struct x86_instruction_info *info,
4600 enum x86_intercept_stage stage)
4601 {
4602 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4603 }
4604
4605 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4606 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4607 {
4608 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4609 }
4610
4611 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4612 {
4613 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4614 }
4615
4616 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4617 {
4618 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4619 }
4620
4621 static const struct x86_emulate_ops emulate_ops = {
4622 .read_gpr = emulator_read_gpr,
4623 .write_gpr = emulator_write_gpr,
4624 .read_std = kvm_read_guest_virt_system,
4625 .write_std = kvm_write_guest_virt_system,
4626 .fetch = kvm_fetch_guest_virt,
4627 .read_emulated = emulator_read_emulated,
4628 .write_emulated = emulator_write_emulated,
4629 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4630 .invlpg = emulator_invlpg,
4631 .pio_in_emulated = emulator_pio_in_emulated,
4632 .pio_out_emulated = emulator_pio_out_emulated,
4633 .get_segment = emulator_get_segment,
4634 .set_segment = emulator_set_segment,
4635 .get_cached_segment_base = emulator_get_cached_segment_base,
4636 .get_gdt = emulator_get_gdt,
4637 .get_idt = emulator_get_idt,
4638 .set_gdt = emulator_set_gdt,
4639 .set_idt = emulator_set_idt,
4640 .get_cr = emulator_get_cr,
4641 .set_cr = emulator_set_cr,
4642 .set_rflags = emulator_set_rflags,
4643 .cpl = emulator_get_cpl,
4644 .get_dr = emulator_get_dr,
4645 .set_dr = emulator_set_dr,
4646 .set_msr = emulator_set_msr,
4647 .get_msr = emulator_get_msr,
4648 .read_pmc = emulator_read_pmc,
4649 .halt = emulator_halt,
4650 .wbinvd = emulator_wbinvd,
4651 .fix_hypercall = emulator_fix_hypercall,
4652 .get_fpu = emulator_get_fpu,
4653 .put_fpu = emulator_put_fpu,
4654 .intercept = emulator_intercept,
4655 .get_cpuid = emulator_get_cpuid,
4656 };
4657
4658 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4659 {
4660 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4661 /*
4662 * an sti; sti; sequence only disable interrupts for the first
4663 * instruction. So, if the last instruction, be it emulated or
4664 * not, left the system with the INT_STI flag enabled, it
4665 * means that the last instruction is an sti. We should not
4666 * leave the flag on in this case. The same goes for mov ss
4667 */
4668 if (!(int_shadow & mask))
4669 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4670 }
4671
4672 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4673 {
4674 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4675 if (ctxt->exception.vector == PF_VECTOR)
4676 kvm_propagate_fault(vcpu, &ctxt->exception);
4677 else if (ctxt->exception.error_code_valid)
4678 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4679 ctxt->exception.error_code);
4680 else
4681 kvm_queue_exception(vcpu, ctxt->exception.vector);
4682 }
4683
4684 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4685 {
4686 memset(&ctxt->twobyte, 0,
4687 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4688
4689 ctxt->fetch.start = 0;
4690 ctxt->fetch.end = 0;
4691 ctxt->io_read.pos = 0;
4692 ctxt->io_read.end = 0;
4693 ctxt->mem_read.pos = 0;
4694 ctxt->mem_read.end = 0;
4695 }
4696
4697 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4698 {
4699 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4700 int cs_db, cs_l;
4701
4702 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4703
4704 ctxt->eflags = kvm_get_rflags(vcpu);
4705 ctxt->eip = kvm_rip_read(vcpu);
4706 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4707 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4708 cs_l ? X86EMUL_MODE_PROT64 :
4709 cs_db ? X86EMUL_MODE_PROT32 :
4710 X86EMUL_MODE_PROT16;
4711 ctxt->guest_mode = is_guest_mode(vcpu);
4712
4713 init_decode_cache(ctxt);
4714 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4715 }
4716
4717 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4718 {
4719 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4720 int ret;
4721
4722 init_emulate_ctxt(vcpu);
4723
4724 ctxt->op_bytes = 2;
4725 ctxt->ad_bytes = 2;
4726 ctxt->_eip = ctxt->eip + inc_eip;
4727 ret = emulate_int_real(ctxt, irq);
4728
4729 if (ret != X86EMUL_CONTINUE)
4730 return EMULATE_FAIL;
4731
4732 ctxt->eip = ctxt->_eip;
4733 kvm_rip_write(vcpu, ctxt->eip);
4734 kvm_set_rflags(vcpu, ctxt->eflags);
4735
4736 if (irq == NMI_VECTOR)
4737 vcpu->arch.nmi_pending = 0;
4738 else
4739 vcpu->arch.interrupt.pending = false;
4740
4741 return EMULATE_DONE;
4742 }
4743 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4744
4745 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4746 {
4747 int r = EMULATE_DONE;
4748
4749 ++vcpu->stat.insn_emulation_fail;
4750 trace_kvm_emulate_insn_failed(vcpu);
4751 if (!is_guest_mode(vcpu)) {
4752 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4753 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4754 vcpu->run->internal.ndata = 0;
4755 r = EMULATE_FAIL;
4756 }
4757 kvm_queue_exception(vcpu, UD_VECTOR);
4758
4759 return r;
4760 }
4761
4762 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4763 {
4764 gpa_t gpa;
4765 pfn_t pfn;
4766
4767 if (tdp_enabled)
4768 return false;
4769
4770 /*
4771 * if emulation was due to access to shadowed page table
4772 * and it failed try to unshadow page and re-enter the
4773 * guest to let CPU execute the instruction.
4774 */
4775 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4776 return true;
4777
4778 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4779
4780 if (gpa == UNMAPPED_GVA)
4781 return true; /* let cpu generate fault */
4782
4783 /*
4784 * Do not retry the unhandleable instruction if it faults on the
4785 * readonly host memory, otherwise it will goto a infinite loop:
4786 * retry instruction -> write #PF -> emulation fail -> retry
4787 * instruction -> ...
4788 */
4789 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4790 if (!is_error_noslot_pfn(pfn)) {
4791 kvm_release_pfn_clean(pfn);
4792 return true;
4793 }
4794
4795 return false;
4796 }
4797
4798 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4799 unsigned long cr2, int emulation_type)
4800 {
4801 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4802 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4803
4804 last_retry_eip = vcpu->arch.last_retry_eip;
4805 last_retry_addr = vcpu->arch.last_retry_addr;
4806
4807 /*
4808 * If the emulation is caused by #PF and it is non-page_table
4809 * writing instruction, it means the VM-EXIT is caused by shadow
4810 * page protected, we can zap the shadow page and retry this
4811 * instruction directly.
4812 *
4813 * Note: if the guest uses a non-page-table modifying instruction
4814 * on the PDE that points to the instruction, then we will unmap
4815 * the instruction and go to an infinite loop. So, we cache the
4816 * last retried eip and the last fault address, if we meet the eip
4817 * and the address again, we can break out of the potential infinite
4818 * loop.
4819 */
4820 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4821
4822 if (!(emulation_type & EMULTYPE_RETRY))
4823 return false;
4824
4825 if (x86_page_table_writing_insn(ctxt))
4826 return false;
4827
4828 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4829 return false;
4830
4831 vcpu->arch.last_retry_eip = ctxt->eip;
4832 vcpu->arch.last_retry_addr = cr2;
4833
4834 if (!vcpu->arch.mmu.direct_map)
4835 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4836
4837 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4838
4839 return true;
4840 }
4841
4842 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4843 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4844
4845 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4846 unsigned long cr2,
4847 int emulation_type,
4848 void *insn,
4849 int insn_len)
4850 {
4851 int r;
4852 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4853 bool writeback = true;
4854
4855 kvm_clear_exception_queue(vcpu);
4856
4857 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4858 init_emulate_ctxt(vcpu);
4859 ctxt->interruptibility = 0;
4860 ctxt->have_exception = false;
4861 ctxt->perm_ok = false;
4862
4863 ctxt->only_vendor_specific_insn
4864 = emulation_type & EMULTYPE_TRAP_UD;
4865
4866 r = x86_decode_insn(ctxt, insn, insn_len);
4867
4868 trace_kvm_emulate_insn_start(vcpu);
4869 ++vcpu->stat.insn_emulation;
4870 if (r != EMULATION_OK) {
4871 if (emulation_type & EMULTYPE_TRAP_UD)
4872 return EMULATE_FAIL;
4873 if (reexecute_instruction(vcpu, cr2))
4874 return EMULATE_DONE;
4875 if (emulation_type & EMULTYPE_SKIP)
4876 return EMULATE_FAIL;
4877 return handle_emulation_failure(vcpu);
4878 }
4879 }
4880
4881 if (emulation_type & EMULTYPE_SKIP) {
4882 kvm_rip_write(vcpu, ctxt->_eip);
4883 return EMULATE_DONE;
4884 }
4885
4886 if (retry_instruction(ctxt, cr2, emulation_type))
4887 return EMULATE_DONE;
4888
4889 /* this is needed for vmware backdoor interface to work since it
4890 changes registers values during IO operation */
4891 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4892 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4893 emulator_invalidate_register_cache(ctxt);
4894 }
4895
4896 restart:
4897 r = x86_emulate_insn(ctxt);
4898
4899 if (r == EMULATION_INTERCEPTED)
4900 return EMULATE_DONE;
4901
4902 if (r == EMULATION_FAILED) {
4903 if (reexecute_instruction(vcpu, cr2))
4904 return EMULATE_DONE;
4905
4906 return handle_emulation_failure(vcpu);
4907 }
4908
4909 if (ctxt->have_exception) {
4910 inject_emulated_exception(vcpu);
4911 r = EMULATE_DONE;
4912 } else if (vcpu->arch.pio.count) {
4913 if (!vcpu->arch.pio.in)
4914 vcpu->arch.pio.count = 0;
4915 else {
4916 writeback = false;
4917 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4918 }
4919 r = EMULATE_DO_MMIO;
4920 } else if (vcpu->mmio_needed) {
4921 if (!vcpu->mmio_is_write)
4922 writeback = false;
4923 r = EMULATE_DO_MMIO;
4924 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
4925 } else if (r == EMULATION_RESTART)
4926 goto restart;
4927 else
4928 r = EMULATE_DONE;
4929
4930 if (writeback) {
4931 toggle_interruptibility(vcpu, ctxt->interruptibility);
4932 kvm_set_rflags(vcpu, ctxt->eflags);
4933 kvm_make_request(KVM_REQ_EVENT, vcpu);
4934 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4935 kvm_rip_write(vcpu, ctxt->eip);
4936 } else
4937 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4938
4939 return r;
4940 }
4941 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4942
4943 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4944 {
4945 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4946 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4947 size, port, &val, 1);
4948 /* do not return to emulator after return from userspace */
4949 vcpu->arch.pio.count = 0;
4950 return ret;
4951 }
4952 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4953
4954 static void tsc_bad(void *info)
4955 {
4956 __this_cpu_write(cpu_tsc_khz, 0);
4957 }
4958
4959 static void tsc_khz_changed(void *data)
4960 {
4961 struct cpufreq_freqs *freq = data;
4962 unsigned long khz = 0;
4963
4964 if (data)
4965 khz = freq->new;
4966 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4967 khz = cpufreq_quick_get(raw_smp_processor_id());
4968 if (!khz)
4969 khz = tsc_khz;
4970 __this_cpu_write(cpu_tsc_khz, khz);
4971 }
4972
4973 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4974 void *data)
4975 {
4976 struct cpufreq_freqs *freq = data;
4977 struct kvm *kvm;
4978 struct kvm_vcpu *vcpu;
4979 int i, send_ipi = 0;
4980
4981 /*
4982 * We allow guests to temporarily run on slowing clocks,
4983 * provided we notify them after, or to run on accelerating
4984 * clocks, provided we notify them before. Thus time never
4985 * goes backwards.
4986 *
4987 * However, we have a problem. We can't atomically update
4988 * the frequency of a given CPU from this function; it is
4989 * merely a notifier, which can be called from any CPU.
4990 * Changing the TSC frequency at arbitrary points in time
4991 * requires a recomputation of local variables related to
4992 * the TSC for each VCPU. We must flag these local variables
4993 * to be updated and be sure the update takes place with the
4994 * new frequency before any guests proceed.
4995 *
4996 * Unfortunately, the combination of hotplug CPU and frequency
4997 * change creates an intractable locking scenario; the order
4998 * of when these callouts happen is undefined with respect to
4999 * CPU hotplug, and they can race with each other. As such,
5000 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5001 * undefined; you can actually have a CPU frequency change take
5002 * place in between the computation of X and the setting of the
5003 * variable. To protect against this problem, all updates of
5004 * the per_cpu tsc_khz variable are done in an interrupt
5005 * protected IPI, and all callers wishing to update the value
5006 * must wait for a synchronous IPI to complete (which is trivial
5007 * if the caller is on the CPU already). This establishes the
5008 * necessary total order on variable updates.
5009 *
5010 * Note that because a guest time update may take place
5011 * anytime after the setting of the VCPU's request bit, the
5012 * correct TSC value must be set before the request. However,
5013 * to ensure the update actually makes it to any guest which
5014 * starts running in hardware virtualization between the set
5015 * and the acquisition of the spinlock, we must also ping the
5016 * CPU after setting the request bit.
5017 *
5018 */
5019
5020 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5021 return 0;
5022 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5023 return 0;
5024
5025 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5026
5027 raw_spin_lock(&kvm_lock);
5028 list_for_each_entry(kvm, &vm_list, vm_list) {
5029 kvm_for_each_vcpu(i, vcpu, kvm) {
5030 if (vcpu->cpu != freq->cpu)
5031 continue;
5032 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5033 if (vcpu->cpu != smp_processor_id())
5034 send_ipi = 1;
5035 }
5036 }
5037 raw_spin_unlock(&kvm_lock);
5038
5039 if (freq->old < freq->new && send_ipi) {
5040 /*
5041 * We upscale the frequency. Must make the guest
5042 * doesn't see old kvmclock values while running with
5043 * the new frequency, otherwise we risk the guest sees
5044 * time go backwards.
5045 *
5046 * In case we update the frequency for another cpu
5047 * (which might be in guest context) send an interrupt
5048 * to kick the cpu out of guest context. Next time
5049 * guest context is entered kvmclock will be updated,
5050 * so the guest will not see stale values.
5051 */
5052 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5053 }
5054 return 0;
5055 }
5056
5057 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5058 .notifier_call = kvmclock_cpufreq_notifier
5059 };
5060
5061 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5062 unsigned long action, void *hcpu)
5063 {
5064 unsigned int cpu = (unsigned long)hcpu;
5065
5066 switch (action) {
5067 case CPU_ONLINE:
5068 case CPU_DOWN_FAILED:
5069 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5070 break;
5071 case CPU_DOWN_PREPARE:
5072 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5073 break;
5074 }
5075 return NOTIFY_OK;
5076 }
5077
5078 static struct notifier_block kvmclock_cpu_notifier_block = {
5079 .notifier_call = kvmclock_cpu_notifier,
5080 .priority = -INT_MAX
5081 };
5082
5083 static void kvm_timer_init(void)
5084 {
5085 int cpu;
5086
5087 max_tsc_khz = tsc_khz;
5088 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5089 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5090 #ifdef CONFIG_CPU_FREQ
5091 struct cpufreq_policy policy;
5092 memset(&policy, 0, sizeof(policy));
5093 cpu = get_cpu();
5094 cpufreq_get_policy(&policy, cpu);
5095 if (policy.cpuinfo.max_freq)
5096 max_tsc_khz = policy.cpuinfo.max_freq;
5097 put_cpu();
5098 #endif
5099 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5100 CPUFREQ_TRANSITION_NOTIFIER);
5101 }
5102 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5103 for_each_online_cpu(cpu)
5104 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5105 }
5106
5107 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5108
5109 int kvm_is_in_guest(void)
5110 {
5111 return __this_cpu_read(current_vcpu) != NULL;
5112 }
5113
5114 static int kvm_is_user_mode(void)
5115 {
5116 int user_mode = 3;
5117
5118 if (__this_cpu_read(current_vcpu))
5119 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5120
5121 return user_mode != 0;
5122 }
5123
5124 static unsigned long kvm_get_guest_ip(void)
5125 {
5126 unsigned long ip = 0;
5127
5128 if (__this_cpu_read(current_vcpu))
5129 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5130
5131 return ip;
5132 }
5133
5134 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5135 .is_in_guest = kvm_is_in_guest,
5136 .is_user_mode = kvm_is_user_mode,
5137 .get_guest_ip = kvm_get_guest_ip,
5138 };
5139
5140 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5141 {
5142 __this_cpu_write(current_vcpu, vcpu);
5143 }
5144 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5145
5146 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5147 {
5148 __this_cpu_write(current_vcpu, NULL);
5149 }
5150 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5151
5152 static void kvm_set_mmio_spte_mask(void)
5153 {
5154 u64 mask;
5155 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5156
5157 /*
5158 * Set the reserved bits and the present bit of an paging-structure
5159 * entry to generate page fault with PFER.RSV = 1.
5160 */
5161 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5162 mask |= 1ull;
5163
5164 #ifdef CONFIG_X86_64
5165 /*
5166 * If reserved bit is not supported, clear the present bit to disable
5167 * mmio page fault.
5168 */
5169 if (maxphyaddr == 52)
5170 mask &= ~1ull;
5171 #endif
5172
5173 kvm_mmu_set_mmio_spte_mask(mask);
5174 }
5175
5176 #ifdef CONFIG_X86_64
5177 static void pvclock_gtod_update_fn(struct work_struct *work)
5178 {
5179 struct kvm *kvm;
5180
5181 struct kvm_vcpu *vcpu;
5182 int i;
5183
5184 raw_spin_lock(&kvm_lock);
5185 list_for_each_entry(kvm, &vm_list, vm_list)
5186 kvm_for_each_vcpu(i, vcpu, kvm)
5187 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5188 atomic_set(&kvm_guest_has_master_clock, 0);
5189 raw_spin_unlock(&kvm_lock);
5190 }
5191
5192 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5193
5194 /*
5195 * Notification about pvclock gtod data update.
5196 */
5197 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5198 void *priv)
5199 {
5200 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5201 struct timekeeper *tk = priv;
5202
5203 update_pvclock_gtod(tk);
5204
5205 /* disable master clock if host does not trust, or does not
5206 * use, TSC clocksource
5207 */
5208 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5209 atomic_read(&kvm_guest_has_master_clock) != 0)
5210 queue_work(system_long_wq, &pvclock_gtod_work);
5211
5212 return 0;
5213 }
5214
5215 static struct notifier_block pvclock_gtod_notifier = {
5216 .notifier_call = pvclock_gtod_notify,
5217 };
5218 #endif
5219
5220 int kvm_arch_init(void *opaque)
5221 {
5222 int r;
5223 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5224
5225 if (kvm_x86_ops) {
5226 printk(KERN_ERR "kvm: already loaded the other module\n");
5227 r = -EEXIST;
5228 goto out;
5229 }
5230
5231 if (!ops->cpu_has_kvm_support()) {
5232 printk(KERN_ERR "kvm: no hardware support\n");
5233 r = -EOPNOTSUPP;
5234 goto out;
5235 }
5236 if (ops->disabled_by_bios()) {
5237 printk(KERN_ERR "kvm: disabled by bios\n");
5238 r = -EOPNOTSUPP;
5239 goto out;
5240 }
5241
5242 r = kvm_mmu_module_init();
5243 if (r)
5244 goto out;
5245
5246 kvm_set_mmio_spte_mask();
5247 kvm_init_msr_list();
5248
5249 kvm_x86_ops = ops;
5250 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5251 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5252
5253 kvm_timer_init();
5254
5255 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5256
5257 if (cpu_has_xsave)
5258 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5259
5260 kvm_lapic_init();
5261 #ifdef CONFIG_X86_64
5262 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5263 #endif
5264
5265 return 0;
5266
5267 out:
5268 return r;
5269 }
5270
5271 void kvm_arch_exit(void)
5272 {
5273 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5274
5275 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5276 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5277 CPUFREQ_TRANSITION_NOTIFIER);
5278 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5279 #ifdef CONFIG_X86_64
5280 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5281 #endif
5282 kvm_x86_ops = NULL;
5283 kvm_mmu_module_exit();
5284 }
5285
5286 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5287 {
5288 ++vcpu->stat.halt_exits;
5289 if (irqchip_in_kernel(vcpu->kvm)) {
5290 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5291 return 1;
5292 } else {
5293 vcpu->run->exit_reason = KVM_EXIT_HLT;
5294 return 0;
5295 }
5296 }
5297 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5298
5299 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5300 {
5301 u64 param, ingpa, outgpa, ret;
5302 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5303 bool fast, longmode;
5304 int cs_db, cs_l;
5305
5306 /*
5307 * hypercall generates UD from non zero cpl and real mode
5308 * per HYPER-V spec
5309 */
5310 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5311 kvm_queue_exception(vcpu, UD_VECTOR);
5312 return 0;
5313 }
5314
5315 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5316 longmode = is_long_mode(vcpu) && cs_l == 1;
5317
5318 if (!longmode) {
5319 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5320 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5321 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5322 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5323 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5324 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5325 }
5326 #ifdef CONFIG_X86_64
5327 else {
5328 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5329 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5330 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5331 }
5332 #endif
5333
5334 code = param & 0xffff;
5335 fast = (param >> 16) & 0x1;
5336 rep_cnt = (param >> 32) & 0xfff;
5337 rep_idx = (param >> 48) & 0xfff;
5338
5339 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5340
5341 switch (code) {
5342 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5343 kvm_vcpu_on_spin(vcpu);
5344 break;
5345 default:
5346 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5347 break;
5348 }
5349
5350 ret = res | (((u64)rep_done & 0xfff) << 32);
5351 if (longmode) {
5352 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5353 } else {
5354 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5355 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5356 }
5357
5358 return 1;
5359 }
5360
5361 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5362 {
5363 unsigned long nr, a0, a1, a2, a3, ret;
5364 int r = 1;
5365
5366 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5367 return kvm_hv_hypercall(vcpu);
5368
5369 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5370 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5371 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5372 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5373 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5374
5375 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5376
5377 if (!is_long_mode(vcpu)) {
5378 nr &= 0xFFFFFFFF;
5379 a0 &= 0xFFFFFFFF;
5380 a1 &= 0xFFFFFFFF;
5381 a2 &= 0xFFFFFFFF;
5382 a3 &= 0xFFFFFFFF;
5383 }
5384
5385 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5386 ret = -KVM_EPERM;
5387 goto out;
5388 }
5389
5390 switch (nr) {
5391 case KVM_HC_VAPIC_POLL_IRQ:
5392 ret = 0;
5393 break;
5394 default:
5395 ret = -KVM_ENOSYS;
5396 break;
5397 }
5398 out:
5399 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5400 ++vcpu->stat.hypercalls;
5401 return r;
5402 }
5403 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5404
5405 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5406 {
5407 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5408 char instruction[3];
5409 unsigned long rip = kvm_rip_read(vcpu);
5410
5411 /*
5412 * Blow out the MMU to ensure that no other VCPU has an active mapping
5413 * to ensure that the updated hypercall appears atomically across all
5414 * VCPUs.
5415 */
5416 kvm_mmu_zap_all(vcpu->kvm);
5417
5418 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5419
5420 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5421 }
5422
5423 /*
5424 * Check if userspace requested an interrupt window, and that the
5425 * interrupt window is open.
5426 *
5427 * No need to exit to userspace if we already have an interrupt queued.
5428 */
5429 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5430 {
5431 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5432 vcpu->run->request_interrupt_window &&
5433 kvm_arch_interrupt_allowed(vcpu));
5434 }
5435
5436 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5437 {
5438 struct kvm_run *kvm_run = vcpu->run;
5439
5440 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5441 kvm_run->cr8 = kvm_get_cr8(vcpu);
5442 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5443 if (irqchip_in_kernel(vcpu->kvm))
5444 kvm_run->ready_for_interrupt_injection = 1;
5445 else
5446 kvm_run->ready_for_interrupt_injection =
5447 kvm_arch_interrupt_allowed(vcpu) &&
5448 !kvm_cpu_has_interrupt(vcpu) &&
5449 !kvm_event_needs_reinjection(vcpu);
5450 }
5451
5452 static int vapic_enter(struct kvm_vcpu *vcpu)
5453 {
5454 struct kvm_lapic *apic = vcpu->arch.apic;
5455 struct page *page;
5456
5457 if (!apic || !apic->vapic_addr)
5458 return 0;
5459
5460 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5461 if (is_error_page(page))
5462 return -EFAULT;
5463
5464 vcpu->arch.apic->vapic_page = page;
5465 return 0;
5466 }
5467
5468 static void vapic_exit(struct kvm_vcpu *vcpu)
5469 {
5470 struct kvm_lapic *apic = vcpu->arch.apic;
5471 int idx;
5472
5473 if (!apic || !apic->vapic_addr)
5474 return;
5475
5476 idx = srcu_read_lock(&vcpu->kvm->srcu);
5477 kvm_release_page_dirty(apic->vapic_page);
5478 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5479 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5480 }
5481
5482 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5483 {
5484 int max_irr, tpr;
5485
5486 if (!kvm_x86_ops->update_cr8_intercept)
5487 return;
5488
5489 if (!vcpu->arch.apic)
5490 return;
5491
5492 if (!vcpu->arch.apic->vapic_addr)
5493 max_irr = kvm_lapic_find_highest_irr(vcpu);
5494 else
5495 max_irr = -1;
5496
5497 if (max_irr != -1)
5498 max_irr >>= 4;
5499
5500 tpr = kvm_lapic_get_cr8(vcpu);
5501
5502 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5503 }
5504
5505 static void inject_pending_event(struct kvm_vcpu *vcpu)
5506 {
5507 /* try to reinject previous events if any */
5508 if (vcpu->arch.exception.pending) {
5509 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5510 vcpu->arch.exception.has_error_code,
5511 vcpu->arch.exception.error_code);
5512 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5513 vcpu->arch.exception.has_error_code,
5514 vcpu->arch.exception.error_code,
5515 vcpu->arch.exception.reinject);
5516 return;
5517 }
5518
5519 if (vcpu->arch.nmi_injected) {
5520 kvm_x86_ops->set_nmi(vcpu);
5521 return;
5522 }
5523
5524 if (vcpu->arch.interrupt.pending) {
5525 kvm_x86_ops->set_irq(vcpu);
5526 return;
5527 }
5528
5529 /* try to inject new event if pending */
5530 if (vcpu->arch.nmi_pending) {
5531 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5532 --vcpu->arch.nmi_pending;
5533 vcpu->arch.nmi_injected = true;
5534 kvm_x86_ops->set_nmi(vcpu);
5535 }
5536 } else if (kvm_cpu_has_interrupt(vcpu)) {
5537 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5538 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5539 false);
5540 kvm_x86_ops->set_irq(vcpu);
5541 }
5542 }
5543 }
5544
5545 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5546 {
5547 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5548 !vcpu->guest_xcr0_loaded) {
5549 /* kvm_set_xcr() also depends on this */
5550 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5551 vcpu->guest_xcr0_loaded = 1;
5552 }
5553 }
5554
5555 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5556 {
5557 if (vcpu->guest_xcr0_loaded) {
5558 if (vcpu->arch.xcr0 != host_xcr0)
5559 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5560 vcpu->guest_xcr0_loaded = 0;
5561 }
5562 }
5563
5564 static void process_nmi(struct kvm_vcpu *vcpu)
5565 {
5566 unsigned limit = 2;
5567
5568 /*
5569 * x86 is limited to one NMI running, and one NMI pending after it.
5570 * If an NMI is already in progress, limit further NMIs to just one.
5571 * Otherwise, allow two (and we'll inject the first one immediately).
5572 */
5573 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5574 limit = 1;
5575
5576 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5577 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5578 kvm_make_request(KVM_REQ_EVENT, vcpu);
5579 }
5580
5581 static void kvm_gen_update_masterclock(struct kvm *kvm)
5582 {
5583 #ifdef CONFIG_X86_64
5584 int i;
5585 struct kvm_vcpu *vcpu;
5586 struct kvm_arch *ka = &kvm->arch;
5587
5588 spin_lock(&ka->pvclock_gtod_sync_lock);
5589 kvm_make_mclock_inprogress_request(kvm);
5590 /* no guest entries from this point */
5591 pvclock_update_vm_gtod_copy(kvm);
5592
5593 kvm_for_each_vcpu(i, vcpu, kvm)
5594 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5595
5596 /* guest entries allowed */
5597 kvm_for_each_vcpu(i, vcpu, kvm)
5598 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5599
5600 spin_unlock(&ka->pvclock_gtod_sync_lock);
5601 #endif
5602 }
5603
5604 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5605 {
5606 int r;
5607 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5608 vcpu->run->request_interrupt_window;
5609 bool req_immediate_exit = 0;
5610
5611 if (vcpu->requests) {
5612 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5613 kvm_mmu_unload(vcpu);
5614 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5615 __kvm_migrate_timers(vcpu);
5616 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5617 kvm_gen_update_masterclock(vcpu->kvm);
5618 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5619 r = kvm_guest_time_update(vcpu);
5620 if (unlikely(r))
5621 goto out;
5622 }
5623 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5624 kvm_mmu_sync_roots(vcpu);
5625 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5626 kvm_x86_ops->tlb_flush(vcpu);
5627 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5628 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5629 r = 0;
5630 goto out;
5631 }
5632 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5633 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5634 r = 0;
5635 goto out;
5636 }
5637 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5638 vcpu->fpu_active = 0;
5639 kvm_x86_ops->fpu_deactivate(vcpu);
5640 }
5641 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5642 /* Page is swapped out. Do synthetic halt */
5643 vcpu->arch.apf.halted = true;
5644 r = 1;
5645 goto out;
5646 }
5647 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5648 record_steal_time(vcpu);
5649 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5650 process_nmi(vcpu);
5651 req_immediate_exit =
5652 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5653 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5654 kvm_handle_pmu_event(vcpu);
5655 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5656 kvm_deliver_pmi(vcpu);
5657 }
5658
5659 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5660 inject_pending_event(vcpu);
5661
5662 /* enable NMI/IRQ window open exits if needed */
5663 if (vcpu->arch.nmi_pending)
5664 kvm_x86_ops->enable_nmi_window(vcpu);
5665 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5666 kvm_x86_ops->enable_irq_window(vcpu);
5667
5668 if (kvm_lapic_enabled(vcpu)) {
5669 update_cr8_intercept(vcpu);
5670 kvm_lapic_sync_to_vapic(vcpu);
5671 }
5672 }
5673
5674 r = kvm_mmu_reload(vcpu);
5675 if (unlikely(r)) {
5676 goto cancel_injection;
5677 }
5678
5679 preempt_disable();
5680
5681 kvm_x86_ops->prepare_guest_switch(vcpu);
5682 if (vcpu->fpu_active)
5683 kvm_load_guest_fpu(vcpu);
5684 kvm_load_guest_xcr0(vcpu);
5685
5686 vcpu->mode = IN_GUEST_MODE;
5687
5688 /* We should set ->mode before check ->requests,
5689 * see the comment in make_all_cpus_request.
5690 */
5691 smp_mb();
5692
5693 local_irq_disable();
5694
5695 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5696 || need_resched() || signal_pending(current)) {
5697 vcpu->mode = OUTSIDE_GUEST_MODE;
5698 smp_wmb();
5699 local_irq_enable();
5700 preempt_enable();
5701 r = 1;
5702 goto cancel_injection;
5703 }
5704
5705 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5706
5707 if (req_immediate_exit)
5708 smp_send_reschedule(vcpu->cpu);
5709
5710 kvm_guest_enter();
5711
5712 if (unlikely(vcpu->arch.switch_db_regs)) {
5713 set_debugreg(0, 7);
5714 set_debugreg(vcpu->arch.eff_db[0], 0);
5715 set_debugreg(vcpu->arch.eff_db[1], 1);
5716 set_debugreg(vcpu->arch.eff_db[2], 2);
5717 set_debugreg(vcpu->arch.eff_db[3], 3);
5718 }
5719
5720 trace_kvm_entry(vcpu->vcpu_id);
5721 kvm_x86_ops->run(vcpu);
5722
5723 /*
5724 * If the guest has used debug registers, at least dr7
5725 * will be disabled while returning to the host.
5726 * If we don't have active breakpoints in the host, we don't
5727 * care about the messed up debug address registers. But if
5728 * we have some of them active, restore the old state.
5729 */
5730 if (hw_breakpoint_active())
5731 hw_breakpoint_restore();
5732
5733 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5734 native_read_tsc());
5735
5736 vcpu->mode = OUTSIDE_GUEST_MODE;
5737 smp_wmb();
5738 local_irq_enable();
5739
5740 ++vcpu->stat.exits;
5741
5742 /*
5743 * We must have an instruction between local_irq_enable() and
5744 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5745 * the interrupt shadow. The stat.exits increment will do nicely.
5746 * But we need to prevent reordering, hence this barrier():
5747 */
5748 barrier();
5749
5750 kvm_guest_exit();
5751
5752 preempt_enable();
5753
5754 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5755
5756 /*
5757 * Profile KVM exit RIPs:
5758 */
5759 if (unlikely(prof_on == KVM_PROFILING)) {
5760 unsigned long rip = kvm_rip_read(vcpu);
5761 profile_hit(KVM_PROFILING, (void *)rip);
5762 }
5763
5764 if (unlikely(vcpu->arch.tsc_always_catchup))
5765 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5766
5767 if (vcpu->arch.apic_attention)
5768 kvm_lapic_sync_from_vapic(vcpu);
5769
5770 r = kvm_x86_ops->handle_exit(vcpu);
5771 return r;
5772
5773 cancel_injection:
5774 kvm_x86_ops->cancel_injection(vcpu);
5775 if (unlikely(vcpu->arch.apic_attention))
5776 kvm_lapic_sync_from_vapic(vcpu);
5777 out:
5778 return r;
5779 }
5780
5781
5782 static int __vcpu_run(struct kvm_vcpu *vcpu)
5783 {
5784 int r;
5785 struct kvm *kvm = vcpu->kvm;
5786
5787 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5788 pr_debug("vcpu %d received sipi with vector # %x\n",
5789 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5790 kvm_lapic_reset(vcpu);
5791 r = kvm_vcpu_reset(vcpu);
5792 if (r)
5793 return r;
5794 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5795 }
5796
5797 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5798 r = vapic_enter(vcpu);
5799 if (r) {
5800 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5801 return r;
5802 }
5803
5804 r = 1;
5805 while (r > 0) {
5806 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5807 !vcpu->arch.apf.halted)
5808 r = vcpu_enter_guest(vcpu);
5809 else {
5810 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5811 kvm_vcpu_block(vcpu);
5812 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5813 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5814 {
5815 switch(vcpu->arch.mp_state) {
5816 case KVM_MP_STATE_HALTED:
5817 vcpu->arch.mp_state =
5818 KVM_MP_STATE_RUNNABLE;
5819 case KVM_MP_STATE_RUNNABLE:
5820 vcpu->arch.apf.halted = false;
5821 break;
5822 case KVM_MP_STATE_SIPI_RECEIVED:
5823 default:
5824 r = -EINTR;
5825 break;
5826 }
5827 }
5828 }
5829
5830 if (r <= 0)
5831 break;
5832
5833 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5834 if (kvm_cpu_has_pending_timer(vcpu))
5835 kvm_inject_pending_timer_irqs(vcpu);
5836
5837 if (dm_request_for_irq_injection(vcpu)) {
5838 r = -EINTR;
5839 vcpu->run->exit_reason = KVM_EXIT_INTR;
5840 ++vcpu->stat.request_irq_exits;
5841 }
5842
5843 kvm_check_async_pf_completion(vcpu);
5844
5845 if (signal_pending(current)) {
5846 r = -EINTR;
5847 vcpu->run->exit_reason = KVM_EXIT_INTR;
5848 ++vcpu->stat.signal_exits;
5849 }
5850 if (need_resched()) {
5851 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5852 kvm_resched(vcpu);
5853 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5854 }
5855 }
5856
5857 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5858
5859 vapic_exit(vcpu);
5860
5861 return r;
5862 }
5863
5864 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5865 {
5866 int r;
5867 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5868 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5869 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5870 if (r != EMULATE_DONE)
5871 return 0;
5872 return 1;
5873 }
5874
5875 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5876 {
5877 BUG_ON(!vcpu->arch.pio.count);
5878
5879 return complete_emulated_io(vcpu);
5880 }
5881
5882 /*
5883 * Implements the following, as a state machine:
5884 *
5885 * read:
5886 * for each fragment
5887 * write gpa, len
5888 * exit
5889 * copy data
5890 * execute insn
5891 *
5892 * write:
5893 * for each fragment
5894 * write gpa, len
5895 * copy data
5896 * exit
5897 */
5898 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5899 {
5900 struct kvm_run *run = vcpu->run;
5901 struct kvm_mmio_fragment *frag;
5902
5903 BUG_ON(!vcpu->mmio_needed);
5904
5905 /* Complete previous fragment */
5906 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5907 if (!vcpu->mmio_is_write)
5908 memcpy(frag->data, run->mmio.data, frag->len);
5909 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5910 vcpu->mmio_needed = 0;
5911 if (vcpu->mmio_is_write)
5912 return 1;
5913 vcpu->mmio_read_completed = 1;
5914 return complete_emulated_io(vcpu);
5915 }
5916 /* Initiate next fragment */
5917 ++frag;
5918 run->exit_reason = KVM_EXIT_MMIO;
5919 run->mmio.phys_addr = frag->gpa;
5920 if (vcpu->mmio_is_write)
5921 memcpy(run->mmio.data, frag->data, frag->len);
5922 run->mmio.len = frag->len;
5923 run->mmio.is_write = vcpu->mmio_is_write;
5924 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5925 return 0;
5926 }
5927
5928
5929 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5930 {
5931 int r;
5932 sigset_t sigsaved;
5933
5934 if (!tsk_used_math(current) && init_fpu(current))
5935 return -ENOMEM;
5936
5937 if (vcpu->sigset_active)
5938 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5939
5940 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5941 kvm_vcpu_block(vcpu);
5942 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5943 r = -EAGAIN;
5944 goto out;
5945 }
5946
5947 /* re-sync apic's tpr */
5948 if (!irqchip_in_kernel(vcpu->kvm)) {
5949 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5950 r = -EINVAL;
5951 goto out;
5952 }
5953 }
5954
5955 if (unlikely(vcpu->arch.complete_userspace_io)) {
5956 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
5957 vcpu->arch.complete_userspace_io = NULL;
5958 r = cui(vcpu);
5959 if (r <= 0)
5960 goto out;
5961 } else
5962 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5963
5964 r = __vcpu_run(vcpu);
5965
5966 out:
5967 post_kvm_run_save(vcpu);
5968 if (vcpu->sigset_active)
5969 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5970
5971 return r;
5972 }
5973
5974 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5975 {
5976 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5977 /*
5978 * We are here if userspace calls get_regs() in the middle of
5979 * instruction emulation. Registers state needs to be copied
5980 * back from emulation context to vcpu. Userspace shouldn't do
5981 * that usually, but some bad designed PV devices (vmware
5982 * backdoor interface) need this to work
5983 */
5984 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
5985 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5986 }
5987 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5988 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5989 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5990 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5991 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5992 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5993 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5994 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5995 #ifdef CONFIG_X86_64
5996 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5997 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5998 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5999 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6000 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6001 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6002 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6003 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6004 #endif
6005
6006 regs->rip = kvm_rip_read(vcpu);
6007 regs->rflags = kvm_get_rflags(vcpu);
6008
6009 return 0;
6010 }
6011
6012 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6013 {
6014 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6015 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6016
6017 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6018 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6019 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6020 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6021 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6022 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6023 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6024 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6025 #ifdef CONFIG_X86_64
6026 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6027 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6028 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6029 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6030 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6031 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6032 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6033 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6034 #endif
6035
6036 kvm_rip_write(vcpu, regs->rip);
6037 kvm_set_rflags(vcpu, regs->rflags);
6038
6039 vcpu->arch.exception.pending = false;
6040
6041 kvm_make_request(KVM_REQ_EVENT, vcpu);
6042
6043 return 0;
6044 }
6045
6046 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6047 {
6048 struct kvm_segment cs;
6049
6050 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6051 *db = cs.db;
6052 *l = cs.l;
6053 }
6054 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6055
6056 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6057 struct kvm_sregs *sregs)
6058 {
6059 struct desc_ptr dt;
6060
6061 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6062 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6063 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6064 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6065 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6066 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6067
6068 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6069 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6070
6071 kvm_x86_ops->get_idt(vcpu, &dt);
6072 sregs->idt.limit = dt.size;
6073 sregs->idt.base = dt.address;
6074 kvm_x86_ops->get_gdt(vcpu, &dt);
6075 sregs->gdt.limit = dt.size;
6076 sregs->gdt.base = dt.address;
6077
6078 sregs->cr0 = kvm_read_cr0(vcpu);
6079 sregs->cr2 = vcpu->arch.cr2;
6080 sregs->cr3 = kvm_read_cr3(vcpu);
6081 sregs->cr4 = kvm_read_cr4(vcpu);
6082 sregs->cr8 = kvm_get_cr8(vcpu);
6083 sregs->efer = vcpu->arch.efer;
6084 sregs->apic_base = kvm_get_apic_base(vcpu);
6085
6086 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6087
6088 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6089 set_bit(vcpu->arch.interrupt.nr,
6090 (unsigned long *)sregs->interrupt_bitmap);
6091
6092 return 0;
6093 }
6094
6095 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6096 struct kvm_mp_state *mp_state)
6097 {
6098 mp_state->mp_state = vcpu->arch.mp_state;
6099 return 0;
6100 }
6101
6102 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6103 struct kvm_mp_state *mp_state)
6104 {
6105 vcpu->arch.mp_state = mp_state->mp_state;
6106 kvm_make_request(KVM_REQ_EVENT, vcpu);
6107 return 0;
6108 }
6109
6110 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6111 int reason, bool has_error_code, u32 error_code)
6112 {
6113 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6114 int ret;
6115
6116 init_emulate_ctxt(vcpu);
6117
6118 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6119 has_error_code, error_code);
6120
6121 if (ret)
6122 return EMULATE_FAIL;
6123
6124 kvm_rip_write(vcpu, ctxt->eip);
6125 kvm_set_rflags(vcpu, ctxt->eflags);
6126 kvm_make_request(KVM_REQ_EVENT, vcpu);
6127 return EMULATE_DONE;
6128 }
6129 EXPORT_SYMBOL_GPL(kvm_task_switch);
6130
6131 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6132 struct kvm_sregs *sregs)
6133 {
6134 int mmu_reset_needed = 0;
6135 int pending_vec, max_bits, idx;
6136 struct desc_ptr dt;
6137
6138 dt.size = sregs->idt.limit;
6139 dt.address = sregs->idt.base;
6140 kvm_x86_ops->set_idt(vcpu, &dt);
6141 dt.size = sregs->gdt.limit;
6142 dt.address = sregs->gdt.base;
6143 kvm_x86_ops->set_gdt(vcpu, &dt);
6144
6145 vcpu->arch.cr2 = sregs->cr2;
6146 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6147 vcpu->arch.cr3 = sregs->cr3;
6148 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6149
6150 kvm_set_cr8(vcpu, sregs->cr8);
6151
6152 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6153 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6154 kvm_set_apic_base(vcpu, sregs->apic_base);
6155
6156 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6157 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6158 vcpu->arch.cr0 = sregs->cr0;
6159
6160 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6161 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6162 if (sregs->cr4 & X86_CR4_OSXSAVE)
6163 kvm_update_cpuid(vcpu);
6164
6165 idx = srcu_read_lock(&vcpu->kvm->srcu);
6166 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6167 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6168 mmu_reset_needed = 1;
6169 }
6170 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6171
6172 if (mmu_reset_needed)
6173 kvm_mmu_reset_context(vcpu);
6174
6175 max_bits = KVM_NR_INTERRUPTS;
6176 pending_vec = find_first_bit(
6177 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6178 if (pending_vec < max_bits) {
6179 kvm_queue_interrupt(vcpu, pending_vec, false);
6180 pr_debug("Set back pending irq %d\n", pending_vec);
6181 }
6182
6183 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6184 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6185 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6186 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6187 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6188 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6189
6190 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6191 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6192
6193 update_cr8_intercept(vcpu);
6194
6195 /* Older userspace won't unhalt the vcpu on reset. */
6196 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6197 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6198 !is_protmode(vcpu))
6199 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6200
6201 kvm_make_request(KVM_REQ_EVENT, vcpu);
6202
6203 return 0;
6204 }
6205
6206 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6207 struct kvm_guest_debug *dbg)
6208 {
6209 unsigned long rflags;
6210 int i, r;
6211
6212 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6213 r = -EBUSY;
6214 if (vcpu->arch.exception.pending)
6215 goto out;
6216 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6217 kvm_queue_exception(vcpu, DB_VECTOR);
6218 else
6219 kvm_queue_exception(vcpu, BP_VECTOR);
6220 }
6221
6222 /*
6223 * Read rflags as long as potentially injected trace flags are still
6224 * filtered out.
6225 */
6226 rflags = kvm_get_rflags(vcpu);
6227
6228 vcpu->guest_debug = dbg->control;
6229 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6230 vcpu->guest_debug = 0;
6231
6232 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6233 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6234 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6235 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6236 } else {
6237 for (i = 0; i < KVM_NR_DB_REGS; i++)
6238 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6239 }
6240 kvm_update_dr7(vcpu);
6241
6242 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6243 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6244 get_segment_base(vcpu, VCPU_SREG_CS);
6245
6246 /*
6247 * Trigger an rflags update that will inject or remove the trace
6248 * flags.
6249 */
6250 kvm_set_rflags(vcpu, rflags);
6251
6252 kvm_x86_ops->update_db_bp_intercept(vcpu);
6253
6254 r = 0;
6255
6256 out:
6257
6258 return r;
6259 }
6260
6261 /*
6262 * Translate a guest virtual address to a guest physical address.
6263 */
6264 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6265 struct kvm_translation *tr)
6266 {
6267 unsigned long vaddr = tr->linear_address;
6268 gpa_t gpa;
6269 int idx;
6270
6271 idx = srcu_read_lock(&vcpu->kvm->srcu);
6272 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6273 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6274 tr->physical_address = gpa;
6275 tr->valid = gpa != UNMAPPED_GVA;
6276 tr->writeable = 1;
6277 tr->usermode = 0;
6278
6279 return 0;
6280 }
6281
6282 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6283 {
6284 struct i387_fxsave_struct *fxsave =
6285 &vcpu->arch.guest_fpu.state->fxsave;
6286
6287 memcpy(fpu->fpr, fxsave->st_space, 128);
6288 fpu->fcw = fxsave->cwd;
6289 fpu->fsw = fxsave->swd;
6290 fpu->ftwx = fxsave->twd;
6291 fpu->last_opcode = fxsave->fop;
6292 fpu->last_ip = fxsave->rip;
6293 fpu->last_dp = fxsave->rdp;
6294 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6295
6296 return 0;
6297 }
6298
6299 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6300 {
6301 struct i387_fxsave_struct *fxsave =
6302 &vcpu->arch.guest_fpu.state->fxsave;
6303
6304 memcpy(fxsave->st_space, fpu->fpr, 128);
6305 fxsave->cwd = fpu->fcw;
6306 fxsave->swd = fpu->fsw;
6307 fxsave->twd = fpu->ftwx;
6308 fxsave->fop = fpu->last_opcode;
6309 fxsave->rip = fpu->last_ip;
6310 fxsave->rdp = fpu->last_dp;
6311 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6312
6313 return 0;
6314 }
6315
6316 int fx_init(struct kvm_vcpu *vcpu)
6317 {
6318 int err;
6319
6320 err = fpu_alloc(&vcpu->arch.guest_fpu);
6321 if (err)
6322 return err;
6323
6324 fpu_finit(&vcpu->arch.guest_fpu);
6325
6326 /*
6327 * Ensure guest xcr0 is valid for loading
6328 */
6329 vcpu->arch.xcr0 = XSTATE_FP;
6330
6331 vcpu->arch.cr0 |= X86_CR0_ET;
6332
6333 return 0;
6334 }
6335 EXPORT_SYMBOL_GPL(fx_init);
6336
6337 static void fx_free(struct kvm_vcpu *vcpu)
6338 {
6339 fpu_free(&vcpu->arch.guest_fpu);
6340 }
6341
6342 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6343 {
6344 if (vcpu->guest_fpu_loaded)
6345 return;
6346
6347 /*
6348 * Restore all possible states in the guest,
6349 * and assume host would use all available bits.
6350 * Guest xcr0 would be loaded later.
6351 */
6352 kvm_put_guest_xcr0(vcpu);
6353 vcpu->guest_fpu_loaded = 1;
6354 __kernel_fpu_begin();
6355 fpu_restore_checking(&vcpu->arch.guest_fpu);
6356 trace_kvm_fpu(1);
6357 }
6358
6359 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6360 {
6361 kvm_put_guest_xcr0(vcpu);
6362
6363 if (!vcpu->guest_fpu_loaded)
6364 return;
6365
6366 vcpu->guest_fpu_loaded = 0;
6367 fpu_save_init(&vcpu->arch.guest_fpu);
6368 __kernel_fpu_end();
6369 ++vcpu->stat.fpu_reload;
6370 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6371 trace_kvm_fpu(0);
6372 }
6373
6374 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6375 {
6376 kvmclock_reset(vcpu);
6377
6378 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6379 fx_free(vcpu);
6380 kvm_x86_ops->vcpu_free(vcpu);
6381 }
6382
6383 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6384 unsigned int id)
6385 {
6386 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6387 printk_once(KERN_WARNING
6388 "kvm: SMP vm created on host with unstable TSC; "
6389 "guest TSC will not be reliable\n");
6390 return kvm_x86_ops->vcpu_create(kvm, id);
6391 }
6392
6393 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6394 {
6395 int r;
6396
6397 vcpu->arch.mtrr_state.have_fixed = 1;
6398 r = vcpu_load(vcpu);
6399 if (r)
6400 return r;
6401 r = kvm_vcpu_reset(vcpu);
6402 if (r == 0)
6403 r = kvm_mmu_setup(vcpu);
6404 vcpu_put(vcpu);
6405
6406 return r;
6407 }
6408
6409 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6410 {
6411 int r;
6412 struct msr_data msr;
6413
6414 r = vcpu_load(vcpu);
6415 if (r)
6416 return r;
6417 msr.data = 0x0;
6418 msr.index = MSR_IA32_TSC;
6419 msr.host_initiated = true;
6420 kvm_write_tsc(vcpu, &msr);
6421 vcpu_put(vcpu);
6422
6423 return r;
6424 }
6425
6426 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6427 {
6428 int r;
6429 vcpu->arch.apf.msr_val = 0;
6430
6431 r = vcpu_load(vcpu);
6432 BUG_ON(r);
6433 kvm_mmu_unload(vcpu);
6434 vcpu_put(vcpu);
6435
6436 fx_free(vcpu);
6437 kvm_x86_ops->vcpu_free(vcpu);
6438 }
6439
6440 static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6441 {
6442 atomic_set(&vcpu->arch.nmi_queued, 0);
6443 vcpu->arch.nmi_pending = 0;
6444 vcpu->arch.nmi_injected = false;
6445
6446 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6447 vcpu->arch.dr6 = DR6_FIXED_1;
6448 vcpu->arch.dr7 = DR7_FIXED_1;
6449 kvm_update_dr7(vcpu);
6450
6451 kvm_make_request(KVM_REQ_EVENT, vcpu);
6452 vcpu->arch.apf.msr_val = 0;
6453 vcpu->arch.st.msr_val = 0;
6454
6455 kvmclock_reset(vcpu);
6456
6457 kvm_clear_async_pf_completion_queue(vcpu);
6458 kvm_async_pf_hash_reset(vcpu);
6459 vcpu->arch.apf.halted = false;
6460
6461 kvm_pmu_reset(vcpu);
6462
6463 return kvm_x86_ops->vcpu_reset(vcpu);
6464 }
6465
6466 int kvm_arch_hardware_enable(void *garbage)
6467 {
6468 struct kvm *kvm;
6469 struct kvm_vcpu *vcpu;
6470 int i;
6471 int ret;
6472 u64 local_tsc;
6473 u64 max_tsc = 0;
6474 bool stable, backwards_tsc = false;
6475
6476 kvm_shared_msr_cpu_online();
6477 ret = kvm_x86_ops->hardware_enable(garbage);
6478 if (ret != 0)
6479 return ret;
6480
6481 local_tsc = native_read_tsc();
6482 stable = !check_tsc_unstable();
6483 list_for_each_entry(kvm, &vm_list, vm_list) {
6484 kvm_for_each_vcpu(i, vcpu, kvm) {
6485 if (!stable && vcpu->cpu == smp_processor_id())
6486 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6487 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6488 backwards_tsc = true;
6489 if (vcpu->arch.last_host_tsc > max_tsc)
6490 max_tsc = vcpu->arch.last_host_tsc;
6491 }
6492 }
6493 }
6494
6495 /*
6496 * Sometimes, even reliable TSCs go backwards. This happens on
6497 * platforms that reset TSC during suspend or hibernate actions, but
6498 * maintain synchronization. We must compensate. Fortunately, we can
6499 * detect that condition here, which happens early in CPU bringup,
6500 * before any KVM threads can be running. Unfortunately, we can't
6501 * bring the TSCs fully up to date with real time, as we aren't yet far
6502 * enough into CPU bringup that we know how much real time has actually
6503 * elapsed; our helper function, get_kernel_ns() will be using boot
6504 * variables that haven't been updated yet.
6505 *
6506 * So we simply find the maximum observed TSC above, then record the
6507 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6508 * the adjustment will be applied. Note that we accumulate
6509 * adjustments, in case multiple suspend cycles happen before some VCPU
6510 * gets a chance to run again. In the event that no KVM threads get a
6511 * chance to run, we will miss the entire elapsed period, as we'll have
6512 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6513 * loose cycle time. This isn't too big a deal, since the loss will be
6514 * uniform across all VCPUs (not to mention the scenario is extremely
6515 * unlikely). It is possible that a second hibernate recovery happens
6516 * much faster than a first, causing the observed TSC here to be
6517 * smaller; this would require additional padding adjustment, which is
6518 * why we set last_host_tsc to the local tsc observed here.
6519 *
6520 * N.B. - this code below runs only on platforms with reliable TSC,
6521 * as that is the only way backwards_tsc is set above. Also note
6522 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6523 * have the same delta_cyc adjustment applied if backwards_tsc
6524 * is detected. Note further, this adjustment is only done once,
6525 * as we reset last_host_tsc on all VCPUs to stop this from being
6526 * called multiple times (one for each physical CPU bringup).
6527 *
6528 * Platforms with unreliable TSCs don't have to deal with this, they
6529 * will be compensated by the logic in vcpu_load, which sets the TSC to
6530 * catchup mode. This will catchup all VCPUs to real time, but cannot
6531 * guarantee that they stay in perfect synchronization.
6532 */
6533 if (backwards_tsc) {
6534 u64 delta_cyc = max_tsc - local_tsc;
6535 list_for_each_entry(kvm, &vm_list, vm_list) {
6536 kvm_for_each_vcpu(i, vcpu, kvm) {
6537 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6538 vcpu->arch.last_host_tsc = local_tsc;
6539 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6540 &vcpu->requests);
6541 }
6542
6543 /*
6544 * We have to disable TSC offset matching.. if you were
6545 * booting a VM while issuing an S4 host suspend....
6546 * you may have some problem. Solving this issue is
6547 * left as an exercise to the reader.
6548 */
6549 kvm->arch.last_tsc_nsec = 0;
6550 kvm->arch.last_tsc_write = 0;
6551 }
6552
6553 }
6554 return 0;
6555 }
6556
6557 void kvm_arch_hardware_disable(void *garbage)
6558 {
6559 kvm_x86_ops->hardware_disable(garbage);
6560 drop_user_return_notifiers(garbage);
6561 }
6562
6563 int kvm_arch_hardware_setup(void)
6564 {
6565 return kvm_x86_ops->hardware_setup();
6566 }
6567
6568 void kvm_arch_hardware_unsetup(void)
6569 {
6570 kvm_x86_ops->hardware_unsetup();
6571 }
6572
6573 void kvm_arch_check_processor_compat(void *rtn)
6574 {
6575 kvm_x86_ops->check_processor_compatibility(rtn);
6576 }
6577
6578 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6579 {
6580 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6581 }
6582
6583 struct static_key kvm_no_apic_vcpu __read_mostly;
6584
6585 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6586 {
6587 struct page *page;
6588 struct kvm *kvm;
6589 int r;
6590
6591 BUG_ON(vcpu->kvm == NULL);
6592 kvm = vcpu->kvm;
6593
6594 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6595 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6596 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6597 else
6598 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6599
6600 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6601 if (!page) {
6602 r = -ENOMEM;
6603 goto fail;
6604 }
6605 vcpu->arch.pio_data = page_address(page);
6606
6607 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6608
6609 r = kvm_mmu_create(vcpu);
6610 if (r < 0)
6611 goto fail_free_pio_data;
6612
6613 if (irqchip_in_kernel(kvm)) {
6614 r = kvm_create_lapic(vcpu);
6615 if (r < 0)
6616 goto fail_mmu_destroy;
6617 } else
6618 static_key_slow_inc(&kvm_no_apic_vcpu);
6619
6620 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6621 GFP_KERNEL);
6622 if (!vcpu->arch.mce_banks) {
6623 r = -ENOMEM;
6624 goto fail_free_lapic;
6625 }
6626 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6627
6628 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6629 goto fail_free_mce_banks;
6630
6631 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6632 kvm_async_pf_hash_reset(vcpu);
6633 kvm_pmu_init(vcpu);
6634
6635 return 0;
6636 fail_free_mce_banks:
6637 kfree(vcpu->arch.mce_banks);
6638 fail_free_lapic:
6639 kvm_free_lapic(vcpu);
6640 fail_mmu_destroy:
6641 kvm_mmu_destroy(vcpu);
6642 fail_free_pio_data:
6643 free_page((unsigned long)vcpu->arch.pio_data);
6644 fail:
6645 return r;
6646 }
6647
6648 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6649 {
6650 int idx;
6651
6652 kvm_pmu_destroy(vcpu);
6653 kfree(vcpu->arch.mce_banks);
6654 kvm_free_lapic(vcpu);
6655 idx = srcu_read_lock(&vcpu->kvm->srcu);
6656 kvm_mmu_destroy(vcpu);
6657 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6658 free_page((unsigned long)vcpu->arch.pio_data);
6659 if (!irqchip_in_kernel(vcpu->kvm))
6660 static_key_slow_dec(&kvm_no_apic_vcpu);
6661 }
6662
6663 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6664 {
6665 if (type)
6666 return -EINVAL;
6667
6668 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6669 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6670
6671 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6672 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6673 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6674 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6675 &kvm->arch.irq_sources_bitmap);
6676
6677 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6678 mutex_init(&kvm->arch.apic_map_lock);
6679 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6680
6681 pvclock_update_vm_gtod_copy(kvm);
6682
6683 return 0;
6684 }
6685
6686 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6687 {
6688 int r;
6689 r = vcpu_load(vcpu);
6690 BUG_ON(r);
6691 kvm_mmu_unload(vcpu);
6692 vcpu_put(vcpu);
6693 }
6694
6695 static void kvm_free_vcpus(struct kvm *kvm)
6696 {
6697 unsigned int i;
6698 struct kvm_vcpu *vcpu;
6699
6700 /*
6701 * Unpin any mmu pages first.
6702 */
6703 kvm_for_each_vcpu(i, vcpu, kvm) {
6704 kvm_clear_async_pf_completion_queue(vcpu);
6705 kvm_unload_vcpu_mmu(vcpu);
6706 }
6707 kvm_for_each_vcpu(i, vcpu, kvm)
6708 kvm_arch_vcpu_free(vcpu);
6709
6710 mutex_lock(&kvm->lock);
6711 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6712 kvm->vcpus[i] = NULL;
6713
6714 atomic_set(&kvm->online_vcpus, 0);
6715 mutex_unlock(&kvm->lock);
6716 }
6717
6718 void kvm_arch_sync_events(struct kvm *kvm)
6719 {
6720 kvm_free_all_assigned_devices(kvm);
6721 kvm_free_pit(kvm);
6722 }
6723
6724 void kvm_arch_destroy_vm(struct kvm *kvm)
6725 {
6726 kvm_iommu_unmap_guest(kvm);
6727 kfree(kvm->arch.vpic);
6728 kfree(kvm->arch.vioapic);
6729 kvm_free_vcpus(kvm);
6730 if (kvm->arch.apic_access_page)
6731 put_page(kvm->arch.apic_access_page);
6732 if (kvm->arch.ept_identity_pagetable)
6733 put_page(kvm->arch.ept_identity_pagetable);
6734 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
6735 }
6736
6737 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6738 struct kvm_memory_slot *dont)
6739 {
6740 int i;
6741
6742 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6743 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6744 kvm_kvfree(free->arch.rmap[i]);
6745 free->arch.rmap[i] = NULL;
6746 }
6747 if (i == 0)
6748 continue;
6749
6750 if (!dont || free->arch.lpage_info[i - 1] !=
6751 dont->arch.lpage_info[i - 1]) {
6752 kvm_kvfree(free->arch.lpage_info[i - 1]);
6753 free->arch.lpage_info[i - 1] = NULL;
6754 }
6755 }
6756 }
6757
6758 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6759 {
6760 int i;
6761
6762 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6763 unsigned long ugfn;
6764 int lpages;
6765 int level = i + 1;
6766
6767 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6768 slot->base_gfn, level) + 1;
6769
6770 slot->arch.rmap[i] =
6771 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6772 if (!slot->arch.rmap[i])
6773 goto out_free;
6774 if (i == 0)
6775 continue;
6776
6777 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6778 sizeof(*slot->arch.lpage_info[i - 1]));
6779 if (!slot->arch.lpage_info[i - 1])
6780 goto out_free;
6781
6782 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6783 slot->arch.lpage_info[i - 1][0].write_count = 1;
6784 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6785 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
6786 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6787 /*
6788 * If the gfn and userspace address are not aligned wrt each
6789 * other, or if explicitly asked to, disable large page
6790 * support for this slot
6791 */
6792 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6793 !kvm_largepages_enabled()) {
6794 unsigned long j;
6795
6796 for (j = 0; j < lpages; ++j)
6797 slot->arch.lpage_info[i - 1][j].write_count = 1;
6798 }
6799 }
6800
6801 return 0;
6802
6803 out_free:
6804 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6805 kvm_kvfree(slot->arch.rmap[i]);
6806 slot->arch.rmap[i] = NULL;
6807 if (i == 0)
6808 continue;
6809
6810 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6811 slot->arch.lpage_info[i - 1] = NULL;
6812 }
6813 return -ENOMEM;
6814 }
6815
6816 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6817 struct kvm_memory_slot *memslot,
6818 struct kvm_memory_slot old,
6819 struct kvm_userspace_memory_region *mem,
6820 int user_alloc)
6821 {
6822 int npages = memslot->npages;
6823 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6824
6825 /* Prevent internal slot pages from being moved by fork()/COW. */
6826 if (memslot->id >= KVM_MEMORY_SLOTS)
6827 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6828
6829 /*To keep backward compatibility with older userspace,
6830 *x86 needs to handle !user_alloc case.
6831 */
6832 if (!user_alloc) {
6833 if (npages && !old.npages) {
6834 unsigned long userspace_addr;
6835
6836 userspace_addr = vm_mmap(NULL, 0,
6837 npages * PAGE_SIZE,
6838 PROT_READ | PROT_WRITE,
6839 map_flags,
6840 0);
6841
6842 if (IS_ERR((void *)userspace_addr))
6843 return PTR_ERR((void *)userspace_addr);
6844
6845 memslot->userspace_addr = userspace_addr;
6846 }
6847 }
6848
6849
6850 return 0;
6851 }
6852
6853 void kvm_arch_commit_memory_region(struct kvm *kvm,
6854 struct kvm_userspace_memory_region *mem,
6855 struct kvm_memory_slot old,
6856 int user_alloc)
6857 {
6858
6859 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6860
6861 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
6862 int ret;
6863
6864 ret = vm_munmap(old.userspace_addr,
6865 old.npages * PAGE_SIZE);
6866 if (ret < 0)
6867 printk(KERN_WARNING
6868 "kvm_vm_ioctl_set_memory_region: "
6869 "failed to munmap memory\n");
6870 }
6871
6872 if (!kvm->arch.n_requested_mmu_pages)
6873 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6874
6875 spin_lock(&kvm->mmu_lock);
6876 if (nr_mmu_pages)
6877 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6878 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6879 spin_unlock(&kvm->mmu_lock);
6880 /*
6881 * If memory slot is created, or moved, we need to clear all
6882 * mmio sptes.
6883 */
6884 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6885 kvm_mmu_zap_all(kvm);
6886 kvm_reload_remote_mmus(kvm);
6887 }
6888 }
6889
6890 void kvm_arch_flush_shadow_all(struct kvm *kvm)
6891 {
6892 kvm_mmu_zap_all(kvm);
6893 kvm_reload_remote_mmus(kvm);
6894 }
6895
6896 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6897 struct kvm_memory_slot *slot)
6898 {
6899 kvm_arch_flush_shadow_all(kvm);
6900 }
6901
6902 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6903 {
6904 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6905 !vcpu->arch.apf.halted)
6906 || !list_empty_careful(&vcpu->async_pf.done)
6907 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6908 || atomic_read(&vcpu->arch.nmi_queued) ||
6909 (kvm_arch_interrupt_allowed(vcpu) &&
6910 kvm_cpu_has_interrupt(vcpu));
6911 }
6912
6913 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
6914 {
6915 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
6916 }
6917
6918 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6919 {
6920 return kvm_x86_ops->interrupt_allowed(vcpu);
6921 }
6922
6923 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6924 {
6925 unsigned long current_rip = kvm_rip_read(vcpu) +
6926 get_segment_base(vcpu, VCPU_SREG_CS);
6927
6928 return current_rip == linear_rip;
6929 }
6930 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6931
6932 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6933 {
6934 unsigned long rflags;
6935
6936 rflags = kvm_x86_ops->get_rflags(vcpu);
6937 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6938 rflags &= ~X86_EFLAGS_TF;
6939 return rflags;
6940 }
6941 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6942
6943 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6944 {
6945 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6946 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6947 rflags |= X86_EFLAGS_TF;
6948 kvm_x86_ops->set_rflags(vcpu, rflags);
6949 kvm_make_request(KVM_REQ_EVENT, vcpu);
6950 }
6951 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6952
6953 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6954 {
6955 int r;
6956
6957 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6958 is_error_page(work->page))
6959 return;
6960
6961 r = kvm_mmu_reload(vcpu);
6962 if (unlikely(r))
6963 return;
6964
6965 if (!vcpu->arch.mmu.direct_map &&
6966 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6967 return;
6968
6969 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6970 }
6971
6972 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6973 {
6974 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6975 }
6976
6977 static inline u32 kvm_async_pf_next_probe(u32 key)
6978 {
6979 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6980 }
6981
6982 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6983 {
6984 u32 key = kvm_async_pf_hash_fn(gfn);
6985
6986 while (vcpu->arch.apf.gfns[key] != ~0)
6987 key = kvm_async_pf_next_probe(key);
6988
6989 vcpu->arch.apf.gfns[key] = gfn;
6990 }
6991
6992 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6993 {
6994 int i;
6995 u32 key = kvm_async_pf_hash_fn(gfn);
6996
6997 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6998 (vcpu->arch.apf.gfns[key] != gfn &&
6999 vcpu->arch.apf.gfns[key] != ~0); i++)
7000 key = kvm_async_pf_next_probe(key);
7001
7002 return key;
7003 }
7004
7005 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7006 {
7007 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7008 }
7009
7010 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7011 {
7012 u32 i, j, k;
7013
7014 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7015 while (true) {
7016 vcpu->arch.apf.gfns[i] = ~0;
7017 do {
7018 j = kvm_async_pf_next_probe(j);
7019 if (vcpu->arch.apf.gfns[j] == ~0)
7020 return;
7021 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7022 /*
7023 * k lies cyclically in ]i,j]
7024 * | i.k.j |
7025 * |....j i.k.| or |.k..j i...|
7026 */
7027 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7028 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7029 i = j;
7030 }
7031 }
7032
7033 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7034 {
7035
7036 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7037 sizeof(val));
7038 }
7039
7040 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7041 struct kvm_async_pf *work)
7042 {
7043 struct x86_exception fault;
7044
7045 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7046 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7047
7048 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7049 (vcpu->arch.apf.send_user_only &&
7050 kvm_x86_ops->get_cpl(vcpu) == 0))
7051 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7052 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7053 fault.vector = PF_VECTOR;
7054 fault.error_code_valid = true;
7055 fault.error_code = 0;
7056 fault.nested_page_fault = false;
7057 fault.address = work->arch.token;
7058 kvm_inject_page_fault(vcpu, &fault);
7059 }
7060 }
7061
7062 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7063 struct kvm_async_pf *work)
7064 {
7065 struct x86_exception fault;
7066
7067 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7068 if (is_error_page(work->page))
7069 work->arch.token = ~0; /* broadcast wakeup */
7070 else
7071 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7072
7073 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7074 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7075 fault.vector = PF_VECTOR;
7076 fault.error_code_valid = true;
7077 fault.error_code = 0;
7078 fault.nested_page_fault = false;
7079 fault.address = work->arch.token;
7080 kvm_inject_page_fault(vcpu, &fault);
7081 }
7082 vcpu->arch.apf.halted = false;
7083 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7084 }
7085
7086 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7087 {
7088 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7089 return true;
7090 else
7091 return !kvm_event_needs_reinjection(vcpu) &&
7092 kvm_x86_ops->interrupt_allowed(vcpu);
7093 }
7094
7095 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7096 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7097 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7098 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7099 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7100 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7101 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7102 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7103 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7104 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7105 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7106 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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