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[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / x86.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19 #include <linux/kvm_host.h>
20 #include "irq.h"
21 #include "ioapic.h"
22 #include "mmu.h"
23 #include "i8254.h"
24 #include "tss.h"
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
27 #include "x86.h"
28 #include "cpuid.h"
29 #include "pmu.h"
30 #include "hyperv.h"
31 #include "lapic.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
60
61 #include <trace/events/kvm.h>
62
63 #include <asm/debugreg.h>
64 #include <asm/msr.h>
65 #include <asm/desc.h>
66 #include <asm/mce.h>
67 #include <linux/kernel_stat.h>
68 #include <asm/fpu/internal.h> /* Ugh! */
69 #include <asm/pvclock.h>
70 #include <asm/div64.h>
71 #include <asm/irq_remapping.h>
72 #include <asm/mshyperv.h>
73 #include <asm/hypervisor.h>
74 #include <asm/tlbflush.h>
75 #include <asm/intel_pt.h>
76 #include <asm/emulate_prefix.h>
77 #include <clocksource/hyperv_timer.h>
78
79 #define CREATE_TRACE_POINTS
80 #include "trace.h"
81
82 #define MAX_IO_MSRS 256
83 #define KVM_MAX_MCE_BANKS 32
84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
86
87 #define emul_to_vcpu(ctxt) \
88 ((struct kvm_vcpu *)(ctxt)->vcpu)
89
90 /* EFER defaults:
91 * - enable syscall per default because its emulated by KVM
92 * - enable LME and LMA per default on 64 bit KVM
93 */
94 #ifdef CONFIG_X86_64
95 static
96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
97 #else
98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
99 #endif
100
101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
102
103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
105
106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
107 static void process_nmi(struct kvm_vcpu *vcpu);
108 static void process_smi(struct kvm_vcpu *vcpu);
109 static void enter_smm(struct kvm_vcpu *vcpu);
110 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
111 static void store_regs(struct kvm_vcpu *vcpu);
112 static int sync_regs(struct kvm_vcpu *vcpu);
113
114 struct kvm_x86_ops kvm_x86_ops __read_mostly;
115 EXPORT_SYMBOL_GPL(kvm_x86_ops);
116
117 static bool __read_mostly ignore_msrs = 0;
118 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
119
120 static bool __read_mostly report_ignored_msrs = true;
121 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
122
123 unsigned int min_timer_period_us = 200;
124 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
125
126 static bool __read_mostly kvmclock_periodic_sync = true;
127 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
128
129 bool __read_mostly kvm_has_tsc_control;
130 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
131 u32 __read_mostly kvm_max_guest_tsc_khz;
132 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
133 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
134 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
135 u64 __read_mostly kvm_max_tsc_scaling_ratio;
136 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
137 u64 __read_mostly kvm_default_tsc_scaling_ratio;
138 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
139
140 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
141 static u32 __read_mostly tsc_tolerance_ppm = 250;
142 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
143
144 /*
145 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
146 * adaptive tuning starting from default advancment of 1000ns. '0' disables
147 * advancement entirely. Any other value is used as-is and disables adaptive
148 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
149 */
150 static int __read_mostly lapic_timer_advance_ns = -1;
151 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
152
153 static bool __read_mostly vector_hashing = true;
154 module_param(vector_hashing, bool, S_IRUGO);
155
156 bool __read_mostly enable_vmware_backdoor = false;
157 module_param(enable_vmware_backdoor, bool, S_IRUGO);
158 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
159
160 static bool __read_mostly force_emulation_prefix = false;
161 module_param(force_emulation_prefix, bool, S_IRUGO);
162
163 int __read_mostly pi_inject_timer = -1;
164 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
165
166 /*
167 * Restoring the host value for MSRs that are only consumed when running in
168 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
169 * returns to userspace, i.e. the kernel can run with the guest's value.
170 */
171 #define KVM_MAX_NR_USER_RETURN_MSRS 16
172
173 struct kvm_user_return_msrs_global {
174 int nr;
175 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
176 };
177
178 struct kvm_user_return_msrs {
179 struct user_return_notifier urn;
180 bool registered;
181 struct kvm_user_return_msr_values {
182 u64 host;
183 u64 curr;
184 } values[KVM_MAX_NR_USER_RETURN_MSRS];
185 };
186
187 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
188 static struct kvm_user_return_msrs __percpu *user_return_msrs;
189
190 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
191 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
192 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
193 | XFEATURE_MASK_PKRU)
194
195 u64 __read_mostly host_efer;
196 EXPORT_SYMBOL_GPL(host_efer);
197
198 bool __read_mostly allow_smaller_maxphyaddr = 0;
199 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
200
201 u64 __read_mostly host_xss;
202 EXPORT_SYMBOL_GPL(host_xss);
203 u64 __read_mostly supported_xss;
204 EXPORT_SYMBOL_GPL(supported_xss);
205
206 struct kvm_stats_debugfs_item debugfs_entries[] = {
207 VCPU_STAT("pf_fixed", pf_fixed),
208 VCPU_STAT("pf_guest", pf_guest),
209 VCPU_STAT("tlb_flush", tlb_flush),
210 VCPU_STAT("invlpg", invlpg),
211 VCPU_STAT("exits", exits),
212 VCPU_STAT("io_exits", io_exits),
213 VCPU_STAT("mmio_exits", mmio_exits),
214 VCPU_STAT("signal_exits", signal_exits),
215 VCPU_STAT("irq_window", irq_window_exits),
216 VCPU_STAT("nmi_window", nmi_window_exits),
217 VCPU_STAT("halt_exits", halt_exits),
218 VCPU_STAT("halt_successful_poll", halt_successful_poll),
219 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
220 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
221 VCPU_STAT("halt_wakeup", halt_wakeup),
222 VCPU_STAT("hypercalls", hypercalls),
223 VCPU_STAT("request_irq", request_irq_exits),
224 VCPU_STAT("irq_exits", irq_exits),
225 VCPU_STAT("host_state_reload", host_state_reload),
226 VCPU_STAT("fpu_reload", fpu_reload),
227 VCPU_STAT("insn_emulation", insn_emulation),
228 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
229 VCPU_STAT("irq_injections", irq_injections),
230 VCPU_STAT("nmi_injections", nmi_injections),
231 VCPU_STAT("req_event", req_event),
232 VCPU_STAT("l1d_flush", l1d_flush),
233 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
234 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
235 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
236 VM_STAT("mmu_pte_write", mmu_pte_write),
237 VM_STAT("mmu_pte_updated", mmu_pte_updated),
238 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
239 VM_STAT("mmu_flooded", mmu_flooded),
240 VM_STAT("mmu_recycled", mmu_recycled),
241 VM_STAT("mmu_cache_miss", mmu_cache_miss),
242 VM_STAT("mmu_unsync", mmu_unsync),
243 VM_STAT("remote_tlb_flush", remote_tlb_flush),
244 VM_STAT("largepages", lpages, .mode = 0444),
245 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
246 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
247 { NULL }
248 };
249
250 u64 __read_mostly host_xcr0;
251 u64 __read_mostly supported_xcr0;
252 EXPORT_SYMBOL_GPL(supported_xcr0);
253
254 static struct kmem_cache *x86_fpu_cache;
255
256 static struct kmem_cache *x86_emulator_cache;
257
258 /*
259 * When called, it means the previous get/set msr reached an invalid msr.
260 * Return true if we want to ignore/silent this failed msr access.
261 */
262 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
263 u64 data, bool write)
264 {
265 const char *op = write ? "wrmsr" : "rdmsr";
266
267 if (ignore_msrs) {
268 if (report_ignored_msrs)
269 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
270 op, msr, data);
271 /* Mask the error */
272 return true;
273 } else {
274 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
275 op, msr, data);
276 return false;
277 }
278 }
279
280 static struct kmem_cache *kvm_alloc_emulator_cache(void)
281 {
282 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
283 unsigned int size = sizeof(struct x86_emulate_ctxt);
284
285 return kmem_cache_create_usercopy("x86_emulator", size,
286 __alignof__(struct x86_emulate_ctxt),
287 SLAB_ACCOUNT, useroffset,
288 size - useroffset, NULL);
289 }
290
291 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
292
293 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
294 {
295 int i;
296 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
297 vcpu->arch.apf.gfns[i] = ~0;
298 }
299
300 static void kvm_on_user_return(struct user_return_notifier *urn)
301 {
302 unsigned slot;
303 struct kvm_user_return_msrs *msrs
304 = container_of(urn, struct kvm_user_return_msrs, urn);
305 struct kvm_user_return_msr_values *values;
306 unsigned long flags;
307
308 /*
309 * Disabling irqs at this point since the following code could be
310 * interrupted and executed through kvm_arch_hardware_disable()
311 */
312 local_irq_save(flags);
313 if (msrs->registered) {
314 msrs->registered = false;
315 user_return_notifier_unregister(urn);
316 }
317 local_irq_restore(flags);
318 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
319 values = &msrs->values[slot];
320 if (values->host != values->curr) {
321 wrmsrl(user_return_msrs_global.msrs[slot], values->host);
322 values->curr = values->host;
323 }
324 }
325 }
326
327 void kvm_define_user_return_msr(unsigned slot, u32 msr)
328 {
329 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
330 user_return_msrs_global.msrs[slot] = msr;
331 if (slot >= user_return_msrs_global.nr)
332 user_return_msrs_global.nr = slot + 1;
333 }
334 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
335
336 static void kvm_user_return_msr_cpu_online(void)
337 {
338 unsigned int cpu = smp_processor_id();
339 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
340 u64 value;
341 int i;
342
343 for (i = 0; i < user_return_msrs_global.nr; ++i) {
344 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
345 msrs->values[i].host = value;
346 msrs->values[i].curr = value;
347 }
348 }
349
350 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
351 {
352 unsigned int cpu = smp_processor_id();
353 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
354 int err;
355
356 value = (value & mask) | (msrs->values[slot].host & ~mask);
357 if (value == msrs->values[slot].curr)
358 return 0;
359 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
360 if (err)
361 return 1;
362
363 msrs->values[slot].curr = value;
364 if (!msrs->registered) {
365 msrs->urn.on_user_return = kvm_on_user_return;
366 user_return_notifier_register(&msrs->urn);
367 msrs->registered = true;
368 }
369 return 0;
370 }
371 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
372
373 static void drop_user_return_notifiers(void)
374 {
375 unsigned int cpu = smp_processor_id();
376 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
377
378 if (msrs->registered)
379 kvm_on_user_return(&msrs->urn);
380 }
381
382 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
383 {
384 return vcpu->arch.apic_base;
385 }
386 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
387
388 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
389 {
390 return kvm_apic_mode(kvm_get_apic_base(vcpu));
391 }
392 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
393
394 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
395 {
396 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
397 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
398 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
399 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
400
401 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
402 return 1;
403 if (!msr_info->host_initiated) {
404 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
405 return 1;
406 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
407 return 1;
408 }
409
410 kvm_lapic_set_base(vcpu, msr_info->data);
411 kvm_recalculate_apic_map(vcpu->kvm);
412 return 0;
413 }
414 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
415
416 asmlinkage __visible noinstr void kvm_spurious_fault(void)
417 {
418 /* Fault while not rebooting. We want the trace. */
419 BUG_ON(!kvm_rebooting);
420 }
421 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
422
423 #define EXCPT_BENIGN 0
424 #define EXCPT_CONTRIBUTORY 1
425 #define EXCPT_PF 2
426
427 static int exception_class(int vector)
428 {
429 switch (vector) {
430 case PF_VECTOR:
431 return EXCPT_PF;
432 case DE_VECTOR:
433 case TS_VECTOR:
434 case NP_VECTOR:
435 case SS_VECTOR:
436 case GP_VECTOR:
437 return EXCPT_CONTRIBUTORY;
438 default:
439 break;
440 }
441 return EXCPT_BENIGN;
442 }
443
444 #define EXCPT_FAULT 0
445 #define EXCPT_TRAP 1
446 #define EXCPT_ABORT 2
447 #define EXCPT_INTERRUPT 3
448
449 static int exception_type(int vector)
450 {
451 unsigned int mask;
452
453 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
454 return EXCPT_INTERRUPT;
455
456 mask = 1 << vector;
457
458 /* #DB is trap, as instruction watchpoints are handled elsewhere */
459 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
460 return EXCPT_TRAP;
461
462 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
463 return EXCPT_ABORT;
464
465 /* Reserved exceptions will result in fault */
466 return EXCPT_FAULT;
467 }
468
469 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
470 {
471 unsigned nr = vcpu->arch.exception.nr;
472 bool has_payload = vcpu->arch.exception.has_payload;
473 unsigned long payload = vcpu->arch.exception.payload;
474
475 if (!has_payload)
476 return;
477
478 switch (nr) {
479 case DB_VECTOR:
480 /*
481 * "Certain debug exceptions may clear bit 0-3. The
482 * remaining contents of the DR6 register are never
483 * cleared by the processor".
484 */
485 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
486 /*
487 * DR6.RTM is set by all #DB exceptions that don't clear it.
488 */
489 vcpu->arch.dr6 |= DR6_RTM;
490 vcpu->arch.dr6 |= payload;
491 /*
492 * Bit 16 should be set in the payload whenever the #DB
493 * exception should clear DR6.RTM. This makes the payload
494 * compatible with the pending debug exceptions under VMX.
495 * Though not currently documented in the SDM, this also
496 * makes the payload compatible with the exit qualification
497 * for #DB exceptions under VMX.
498 */
499 vcpu->arch.dr6 ^= payload & DR6_RTM;
500
501 /*
502 * The #DB payload is defined as compatible with the 'pending
503 * debug exceptions' field under VMX, not DR6. While bit 12 is
504 * defined in the 'pending debug exceptions' field (enabled
505 * breakpoint), it is reserved and must be zero in DR6.
506 */
507 vcpu->arch.dr6 &= ~BIT(12);
508 break;
509 case PF_VECTOR:
510 vcpu->arch.cr2 = payload;
511 break;
512 }
513
514 vcpu->arch.exception.has_payload = false;
515 vcpu->arch.exception.payload = 0;
516 }
517 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
518
519 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
520 unsigned nr, bool has_error, u32 error_code,
521 bool has_payload, unsigned long payload, bool reinject)
522 {
523 u32 prev_nr;
524 int class1, class2;
525
526 kvm_make_request(KVM_REQ_EVENT, vcpu);
527
528 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
529 queue:
530 if (has_error && !is_protmode(vcpu))
531 has_error = false;
532 if (reinject) {
533 /*
534 * On vmentry, vcpu->arch.exception.pending is only
535 * true if an event injection was blocked by
536 * nested_run_pending. In that case, however,
537 * vcpu_enter_guest requests an immediate exit,
538 * and the guest shouldn't proceed far enough to
539 * need reinjection.
540 */
541 WARN_ON_ONCE(vcpu->arch.exception.pending);
542 vcpu->arch.exception.injected = true;
543 if (WARN_ON_ONCE(has_payload)) {
544 /*
545 * A reinjected event has already
546 * delivered its payload.
547 */
548 has_payload = false;
549 payload = 0;
550 }
551 } else {
552 vcpu->arch.exception.pending = true;
553 vcpu->arch.exception.injected = false;
554 }
555 vcpu->arch.exception.has_error_code = has_error;
556 vcpu->arch.exception.nr = nr;
557 vcpu->arch.exception.error_code = error_code;
558 vcpu->arch.exception.has_payload = has_payload;
559 vcpu->arch.exception.payload = payload;
560 if (!is_guest_mode(vcpu))
561 kvm_deliver_exception_payload(vcpu);
562 return;
563 }
564
565 /* to check exception */
566 prev_nr = vcpu->arch.exception.nr;
567 if (prev_nr == DF_VECTOR) {
568 /* triple fault -> shutdown */
569 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
570 return;
571 }
572 class1 = exception_class(prev_nr);
573 class2 = exception_class(nr);
574 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
575 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
576 /*
577 * Generate double fault per SDM Table 5-5. Set
578 * exception.pending = true so that the double fault
579 * can trigger a nested vmexit.
580 */
581 vcpu->arch.exception.pending = true;
582 vcpu->arch.exception.injected = false;
583 vcpu->arch.exception.has_error_code = true;
584 vcpu->arch.exception.nr = DF_VECTOR;
585 vcpu->arch.exception.error_code = 0;
586 vcpu->arch.exception.has_payload = false;
587 vcpu->arch.exception.payload = 0;
588 } else
589 /* replace previous exception with a new one in a hope
590 that instruction re-execution will regenerate lost
591 exception */
592 goto queue;
593 }
594
595 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
596 {
597 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
598 }
599 EXPORT_SYMBOL_GPL(kvm_queue_exception);
600
601 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
602 {
603 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
604 }
605 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
606
607 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
608 unsigned long payload)
609 {
610 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
611 }
612 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
613
614 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
615 u32 error_code, unsigned long payload)
616 {
617 kvm_multiple_exception(vcpu, nr, true, error_code,
618 true, payload, false);
619 }
620
621 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
622 {
623 if (err)
624 kvm_inject_gp(vcpu, 0);
625 else
626 return kvm_skip_emulated_instruction(vcpu);
627
628 return 1;
629 }
630 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
631
632 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
633 {
634 ++vcpu->stat.pf_guest;
635 vcpu->arch.exception.nested_apf =
636 is_guest_mode(vcpu) && fault->async_page_fault;
637 if (vcpu->arch.exception.nested_apf) {
638 vcpu->arch.apf.nested_apf_token = fault->address;
639 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
640 } else {
641 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
642 fault->address);
643 }
644 }
645 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
646
647 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
648 struct x86_exception *fault)
649 {
650 struct kvm_mmu *fault_mmu;
651 WARN_ON_ONCE(fault->vector != PF_VECTOR);
652
653 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
654 vcpu->arch.walk_mmu;
655
656 /*
657 * Invalidate the TLB entry for the faulting address, if it exists,
658 * else the access will fault indefinitely (and to emulate hardware).
659 */
660 if ((fault->error_code & PFERR_PRESENT_MASK) &&
661 !(fault->error_code & PFERR_RSVD_MASK))
662 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
663 fault_mmu->root_hpa);
664
665 fault_mmu->inject_page_fault(vcpu, fault);
666 return fault->nested_page_fault;
667 }
668 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
669
670 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
671 {
672 atomic_inc(&vcpu->arch.nmi_queued);
673 kvm_make_request(KVM_REQ_NMI, vcpu);
674 }
675 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
676
677 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
678 {
679 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
680 }
681 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
682
683 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
684 {
685 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
686 }
687 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
688
689 /*
690 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
691 * a #GP and return false.
692 */
693 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
694 {
695 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
696 return true;
697 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
698 return false;
699 }
700 EXPORT_SYMBOL_GPL(kvm_require_cpl);
701
702 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
703 {
704 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return true;
706
707 kvm_queue_exception(vcpu, UD_VECTOR);
708 return false;
709 }
710 EXPORT_SYMBOL_GPL(kvm_require_dr);
711
712 /*
713 * This function will be used to read from the physical memory of the currently
714 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
715 * can read from guest physical or from the guest's guest physical memory.
716 */
717 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
718 gfn_t ngfn, void *data, int offset, int len,
719 u32 access)
720 {
721 struct x86_exception exception;
722 gfn_t real_gfn;
723 gpa_t ngpa;
724
725 ngpa = gfn_to_gpa(ngfn);
726 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
727 if (real_gfn == UNMAPPED_GVA)
728 return -EFAULT;
729
730 real_gfn = gpa_to_gfn(real_gfn);
731
732 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
733 }
734 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
735
736 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
737 void *data, int offset, int len, u32 access)
738 {
739 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
740 data, offset, len, access);
741 }
742
743 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
744 {
745 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
746 rsvd_bits(1, 2);
747 }
748
749 /*
750 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
751 */
752 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
753 {
754 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
755 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
756 int i;
757 int ret;
758 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
759
760 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
761 offset * sizeof(u64), sizeof(pdpte),
762 PFERR_USER_MASK|PFERR_WRITE_MASK);
763 if (ret < 0) {
764 ret = 0;
765 goto out;
766 }
767 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
768 if ((pdpte[i] & PT_PRESENT_MASK) &&
769 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
770 ret = 0;
771 goto out;
772 }
773 }
774 ret = 1;
775
776 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
777 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
778
779 out:
780
781 return ret;
782 }
783 EXPORT_SYMBOL_GPL(load_pdptrs);
784
785 bool pdptrs_changed(struct kvm_vcpu *vcpu)
786 {
787 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
788 int offset;
789 gfn_t gfn;
790 int r;
791
792 if (!is_pae_paging(vcpu))
793 return false;
794
795 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
796 return true;
797
798 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
799 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
800 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
801 PFERR_USER_MASK | PFERR_WRITE_MASK);
802 if (r < 0)
803 return true;
804
805 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
806 }
807 EXPORT_SYMBOL_GPL(pdptrs_changed);
808
809 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
810 {
811 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
812
813 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
814 kvm_clear_async_pf_completion_queue(vcpu);
815 kvm_async_pf_hash_reset(vcpu);
816 }
817
818 if ((cr0 ^ old_cr0) & update_bits)
819 kvm_mmu_reset_context(vcpu);
820
821 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
822 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
823 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
824 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
825 }
826 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
827
828 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
829 {
830 unsigned long old_cr0 = kvm_read_cr0(vcpu);
831 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
832
833 cr0 |= X86_CR0_ET;
834
835 #ifdef CONFIG_X86_64
836 if (cr0 & 0xffffffff00000000UL)
837 return 1;
838 #endif
839
840 cr0 &= ~CR0_RESERVED_BITS;
841
842 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
843 return 1;
844
845 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
846 return 1;
847
848 #ifdef CONFIG_X86_64
849 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
850 (cr0 & X86_CR0_PG)) {
851 int cs_db, cs_l;
852
853 if (!is_pae(vcpu))
854 return 1;
855 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
856 if (cs_l)
857 return 1;
858 }
859 #endif
860 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
861 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
862 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
863 return 1;
864
865 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
866 return 1;
867
868 kvm_x86_ops.set_cr0(vcpu, cr0);
869
870 kvm_post_set_cr0(vcpu, old_cr0, cr0);
871
872 return 0;
873 }
874 EXPORT_SYMBOL_GPL(kvm_set_cr0);
875
876 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
877 {
878 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
879 }
880 EXPORT_SYMBOL_GPL(kvm_lmsw);
881
882 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
883 {
884 if (vcpu->arch.guest_state_protected)
885 return;
886
887 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
888
889 if (vcpu->arch.xcr0 != host_xcr0)
890 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
891
892 if (vcpu->arch.xsaves_enabled &&
893 vcpu->arch.ia32_xss != host_xss)
894 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
895 }
896
897 if (static_cpu_has(X86_FEATURE_PKU) &&
898 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
899 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
900 vcpu->arch.pkru != vcpu->arch.host_pkru)
901 __write_pkru(vcpu->arch.pkru);
902 }
903 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
904
905 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
906 {
907 if (vcpu->arch.guest_state_protected)
908 return;
909
910 if (static_cpu_has(X86_FEATURE_PKU) &&
911 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
912 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
913 vcpu->arch.pkru = rdpkru();
914 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
915 __write_pkru(vcpu->arch.host_pkru);
916 }
917
918 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
919
920 if (vcpu->arch.xcr0 != host_xcr0)
921 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
922
923 if (vcpu->arch.xsaves_enabled &&
924 vcpu->arch.ia32_xss != host_xss)
925 wrmsrl(MSR_IA32_XSS, host_xss);
926 }
927
928 }
929 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
930
931 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
932 {
933 u64 xcr0 = xcr;
934 u64 old_xcr0 = vcpu->arch.xcr0;
935 u64 valid_bits;
936
937 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
938 if (index != XCR_XFEATURE_ENABLED_MASK)
939 return 1;
940 if (!(xcr0 & XFEATURE_MASK_FP))
941 return 1;
942 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
943 return 1;
944
945 /*
946 * Do not allow the guest to set bits that we do not support
947 * saving. However, xcr0 bit 0 is always set, even if the
948 * emulated CPU does not support XSAVE (see fx_init).
949 */
950 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
951 if (xcr0 & ~valid_bits)
952 return 1;
953
954 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
955 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
956 return 1;
957
958 if (xcr0 & XFEATURE_MASK_AVX512) {
959 if (!(xcr0 & XFEATURE_MASK_YMM))
960 return 1;
961 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
962 return 1;
963 }
964 vcpu->arch.xcr0 = xcr0;
965
966 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
967 kvm_update_cpuid_runtime(vcpu);
968 return 0;
969 }
970
971 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
972 {
973 if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
974 __kvm_set_xcr(vcpu, index, xcr)) {
975 kvm_inject_gp(vcpu, 0);
976 return 1;
977 }
978 return 0;
979 }
980 EXPORT_SYMBOL_GPL(kvm_set_xcr);
981
982 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
983 {
984 if (cr4 & cr4_reserved_bits)
985 return false;
986
987 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
988 return false;
989
990 return kvm_x86_ops.is_valid_cr4(vcpu, cr4);
991 }
992 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
993
994 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
995 {
996 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
997 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
998
999 if (((cr4 ^ old_cr4) & mmu_role_bits) ||
1000 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1001 kvm_mmu_reset_context(vcpu);
1002 }
1003 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1004
1005 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1006 {
1007 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1008 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
1009 X86_CR4_SMEP;
1010
1011 if (!kvm_is_valid_cr4(vcpu, cr4))
1012 return 1;
1013
1014 if (is_long_mode(vcpu)) {
1015 if (!(cr4 & X86_CR4_PAE))
1016 return 1;
1017 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1018 return 1;
1019 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1020 && ((cr4 ^ old_cr4) & pdptr_bits)
1021 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
1022 kvm_read_cr3(vcpu)))
1023 return 1;
1024
1025 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1026 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1027 return 1;
1028
1029 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1030 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1031 return 1;
1032 }
1033
1034 kvm_x86_ops.set_cr4(vcpu, cr4);
1035
1036 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1037
1038 return 0;
1039 }
1040 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1041
1042 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1043 {
1044 bool skip_tlb_flush = false;
1045 #ifdef CONFIG_X86_64
1046 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1047
1048 if (pcid_enabled) {
1049 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1050 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1051 }
1052 #endif
1053
1054 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1055 if (!skip_tlb_flush) {
1056 kvm_mmu_sync_roots(vcpu);
1057 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1058 }
1059 return 0;
1060 }
1061
1062 if (is_long_mode(vcpu) &&
1063 (cr3 & vcpu->arch.cr3_lm_rsvd_bits))
1064 return 1;
1065 else if (is_pae_paging(vcpu) &&
1066 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1067 return 1;
1068
1069 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1070 vcpu->arch.cr3 = cr3;
1071 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1072
1073 return 0;
1074 }
1075 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1076
1077 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1078 {
1079 if (cr8 & CR8_RESERVED_BITS)
1080 return 1;
1081 if (lapic_in_kernel(vcpu))
1082 kvm_lapic_set_tpr(vcpu, cr8);
1083 else
1084 vcpu->arch.cr8 = cr8;
1085 return 0;
1086 }
1087 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1088
1089 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1090 {
1091 if (lapic_in_kernel(vcpu))
1092 return kvm_lapic_get_cr8(vcpu);
1093 else
1094 return vcpu->arch.cr8;
1095 }
1096 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1097
1098 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1099 {
1100 int i;
1101
1102 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1103 for (i = 0; i < KVM_NR_DB_REGS; i++)
1104 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1105 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1106 }
1107 }
1108
1109 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1110 {
1111 unsigned long dr7;
1112
1113 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1114 dr7 = vcpu->arch.guest_debug_dr7;
1115 else
1116 dr7 = vcpu->arch.dr7;
1117 kvm_x86_ops.set_dr7(vcpu, dr7);
1118 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1119 if (dr7 & DR7_BP_EN_MASK)
1120 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1121 }
1122 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1123
1124 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1125 {
1126 u64 fixed = DR6_FIXED_1;
1127
1128 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1129 fixed |= DR6_RTM;
1130 return fixed;
1131 }
1132
1133 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1134 {
1135 size_t size = ARRAY_SIZE(vcpu->arch.db);
1136
1137 switch (dr) {
1138 case 0 ... 3:
1139 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1140 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1141 vcpu->arch.eff_db[dr] = val;
1142 break;
1143 case 4:
1144 case 6:
1145 if (!kvm_dr6_valid(val))
1146 return -1; /* #GP */
1147 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1148 break;
1149 case 5:
1150 default: /* 7 */
1151 if (!kvm_dr7_valid(val))
1152 return -1; /* #GP */
1153 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1154 kvm_update_dr7(vcpu);
1155 break;
1156 }
1157
1158 return 0;
1159 }
1160
1161 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1162 {
1163 if (__kvm_set_dr(vcpu, dr, val)) {
1164 kvm_inject_gp(vcpu, 0);
1165 return 1;
1166 }
1167 return 0;
1168 }
1169 EXPORT_SYMBOL_GPL(kvm_set_dr);
1170
1171 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1172 {
1173 size_t size = ARRAY_SIZE(vcpu->arch.db);
1174
1175 switch (dr) {
1176 case 0 ... 3:
1177 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1178 break;
1179 case 4:
1180 case 6:
1181 *val = vcpu->arch.dr6;
1182 break;
1183 case 5:
1184 default: /* 7 */
1185 *val = vcpu->arch.dr7;
1186 break;
1187 }
1188 return 0;
1189 }
1190 EXPORT_SYMBOL_GPL(kvm_get_dr);
1191
1192 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1193 {
1194 u32 ecx = kvm_rcx_read(vcpu);
1195 u64 data;
1196 int err;
1197
1198 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1199 if (err)
1200 return err;
1201 kvm_rax_write(vcpu, (u32)data);
1202 kvm_rdx_write(vcpu, data >> 32);
1203 return err;
1204 }
1205 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1206
1207 /*
1208 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1209 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1210 *
1211 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1212 * extract the supported MSRs from the related const lists.
1213 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1214 * capabilities of the host cpu. This capabilities test skips MSRs that are
1215 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1216 * may depend on host virtualization features rather than host cpu features.
1217 */
1218
1219 static const u32 msrs_to_save_all[] = {
1220 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1221 MSR_STAR,
1222 #ifdef CONFIG_X86_64
1223 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1224 #endif
1225 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1226 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1227 MSR_IA32_SPEC_CTRL,
1228 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1229 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1230 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1231 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1232 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1233 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1234 MSR_IA32_UMWAIT_CONTROL,
1235
1236 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1237 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1238 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1239 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1240 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1241 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1242 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1243 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1244 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1245 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1246 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1247 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1248 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1249 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1250 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1251 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1252 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1253 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1254 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1255 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1256 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1257 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1258 };
1259
1260 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1261 static unsigned num_msrs_to_save;
1262
1263 static const u32 emulated_msrs_all[] = {
1264 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1265 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1266 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1267 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1268 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1269 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1270 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1271 HV_X64_MSR_RESET,
1272 HV_X64_MSR_VP_INDEX,
1273 HV_X64_MSR_VP_RUNTIME,
1274 HV_X64_MSR_SCONTROL,
1275 HV_X64_MSR_STIMER0_CONFIG,
1276 HV_X64_MSR_VP_ASSIST_PAGE,
1277 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1278 HV_X64_MSR_TSC_EMULATION_STATUS,
1279 HV_X64_MSR_SYNDBG_OPTIONS,
1280 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1281 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1282 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1283
1284 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1285 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1286
1287 MSR_IA32_TSC_ADJUST,
1288 MSR_IA32_TSCDEADLINE,
1289 MSR_IA32_ARCH_CAPABILITIES,
1290 MSR_IA32_PERF_CAPABILITIES,
1291 MSR_IA32_MISC_ENABLE,
1292 MSR_IA32_MCG_STATUS,
1293 MSR_IA32_MCG_CTL,
1294 MSR_IA32_MCG_EXT_CTL,
1295 MSR_IA32_SMBASE,
1296 MSR_SMI_COUNT,
1297 MSR_PLATFORM_INFO,
1298 MSR_MISC_FEATURES_ENABLES,
1299 MSR_AMD64_VIRT_SPEC_CTRL,
1300 MSR_IA32_POWER_CTL,
1301 MSR_IA32_UCODE_REV,
1302
1303 /*
1304 * The following list leaves out MSRs whose values are determined
1305 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1306 * We always support the "true" VMX control MSRs, even if the host
1307 * processor does not, so I am putting these registers here rather
1308 * than in msrs_to_save_all.
1309 */
1310 MSR_IA32_VMX_BASIC,
1311 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1312 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1313 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1314 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1315 MSR_IA32_VMX_MISC,
1316 MSR_IA32_VMX_CR0_FIXED0,
1317 MSR_IA32_VMX_CR4_FIXED0,
1318 MSR_IA32_VMX_VMCS_ENUM,
1319 MSR_IA32_VMX_PROCBASED_CTLS2,
1320 MSR_IA32_VMX_EPT_VPID_CAP,
1321 MSR_IA32_VMX_VMFUNC,
1322
1323 MSR_K7_HWCR,
1324 MSR_KVM_POLL_CONTROL,
1325 };
1326
1327 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1328 static unsigned num_emulated_msrs;
1329
1330 /*
1331 * List of msr numbers which are used to expose MSR-based features that
1332 * can be used by a hypervisor to validate requested CPU features.
1333 */
1334 static const u32 msr_based_features_all[] = {
1335 MSR_IA32_VMX_BASIC,
1336 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1337 MSR_IA32_VMX_PINBASED_CTLS,
1338 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1339 MSR_IA32_VMX_PROCBASED_CTLS,
1340 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1341 MSR_IA32_VMX_EXIT_CTLS,
1342 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1343 MSR_IA32_VMX_ENTRY_CTLS,
1344 MSR_IA32_VMX_MISC,
1345 MSR_IA32_VMX_CR0_FIXED0,
1346 MSR_IA32_VMX_CR0_FIXED1,
1347 MSR_IA32_VMX_CR4_FIXED0,
1348 MSR_IA32_VMX_CR4_FIXED1,
1349 MSR_IA32_VMX_VMCS_ENUM,
1350 MSR_IA32_VMX_PROCBASED_CTLS2,
1351 MSR_IA32_VMX_EPT_VPID_CAP,
1352 MSR_IA32_VMX_VMFUNC,
1353
1354 MSR_F10H_DECFG,
1355 MSR_IA32_UCODE_REV,
1356 MSR_IA32_ARCH_CAPABILITIES,
1357 MSR_IA32_PERF_CAPABILITIES,
1358 };
1359
1360 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1361 static unsigned int num_msr_based_features;
1362
1363 static u64 kvm_get_arch_capabilities(void)
1364 {
1365 u64 data = 0;
1366
1367 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1368 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1369
1370 /*
1371 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1372 * the nested hypervisor runs with NX huge pages. If it is not,
1373 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1374 * L1 guests, so it need not worry about its own (L2) guests.
1375 */
1376 data |= ARCH_CAP_PSCHANGE_MC_NO;
1377
1378 /*
1379 * If we're doing cache flushes (either "always" or "cond")
1380 * we will do one whenever the guest does a vmlaunch/vmresume.
1381 * If an outer hypervisor is doing the cache flush for us
1382 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1383 * capability to the guest too, and if EPT is disabled we're not
1384 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1385 * require a nested hypervisor to do a flush of its own.
1386 */
1387 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1388 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1389
1390 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1391 data |= ARCH_CAP_RDCL_NO;
1392 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1393 data |= ARCH_CAP_SSB_NO;
1394 if (!boot_cpu_has_bug(X86_BUG_MDS))
1395 data |= ARCH_CAP_MDS_NO;
1396
1397 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1398 /*
1399 * If RTM=0 because the kernel has disabled TSX, the host might
1400 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1401 * and therefore knows that there cannot be TAA) but keep
1402 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1403 * and we want to allow migrating those guests to tsx=off hosts.
1404 */
1405 data &= ~ARCH_CAP_TAA_NO;
1406 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1407 data |= ARCH_CAP_TAA_NO;
1408 } else {
1409 /*
1410 * Nothing to do here; we emulate TSX_CTRL if present on the
1411 * host so the guest can choose between disabling TSX or
1412 * using VERW to clear CPU buffers.
1413 */
1414 }
1415
1416 return data;
1417 }
1418
1419 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1420 {
1421 switch (msr->index) {
1422 case MSR_IA32_ARCH_CAPABILITIES:
1423 msr->data = kvm_get_arch_capabilities();
1424 break;
1425 case MSR_IA32_UCODE_REV:
1426 rdmsrl_safe(msr->index, &msr->data);
1427 break;
1428 default:
1429 return kvm_x86_ops.get_msr_feature(msr);
1430 }
1431 return 0;
1432 }
1433
1434 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1435 {
1436 struct kvm_msr_entry msr;
1437 int r;
1438
1439 msr.index = index;
1440 r = kvm_get_msr_feature(&msr);
1441
1442 if (r == KVM_MSR_RET_INVALID) {
1443 /* Unconditionally clear the output for simplicity */
1444 *data = 0;
1445 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1446 r = 0;
1447 }
1448
1449 if (r)
1450 return r;
1451
1452 *data = msr.data;
1453
1454 return 0;
1455 }
1456
1457 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1458 {
1459 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1460 return false;
1461
1462 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1463 return false;
1464
1465 if (efer & (EFER_LME | EFER_LMA) &&
1466 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1467 return false;
1468
1469 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1470 return false;
1471
1472 return true;
1473
1474 }
1475 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1476 {
1477 if (efer & efer_reserved_bits)
1478 return false;
1479
1480 return __kvm_valid_efer(vcpu, efer);
1481 }
1482 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1483
1484 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1485 {
1486 u64 old_efer = vcpu->arch.efer;
1487 u64 efer = msr_info->data;
1488 int r;
1489
1490 if (efer & efer_reserved_bits)
1491 return 1;
1492
1493 if (!msr_info->host_initiated) {
1494 if (!__kvm_valid_efer(vcpu, efer))
1495 return 1;
1496
1497 if (is_paging(vcpu) &&
1498 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1499 return 1;
1500 }
1501
1502 efer &= ~EFER_LMA;
1503 efer |= vcpu->arch.efer & EFER_LMA;
1504
1505 r = kvm_x86_ops.set_efer(vcpu, efer);
1506 if (r) {
1507 WARN_ON(r > 0);
1508 return r;
1509 }
1510
1511 /* Update reserved bits */
1512 if ((efer ^ old_efer) & EFER_NX)
1513 kvm_mmu_reset_context(vcpu);
1514
1515 return 0;
1516 }
1517
1518 void kvm_enable_efer_bits(u64 mask)
1519 {
1520 efer_reserved_bits &= ~mask;
1521 }
1522 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1523
1524 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1525 {
1526 struct kvm_x86_msr_filter *msr_filter;
1527 struct msr_bitmap_range *ranges;
1528 struct kvm *kvm = vcpu->kvm;
1529 bool allowed;
1530 int idx;
1531 u32 i;
1532
1533 /* x2APIC MSRs do not support filtering. */
1534 if (index >= 0x800 && index <= 0x8ff)
1535 return true;
1536
1537 idx = srcu_read_lock(&kvm->srcu);
1538
1539 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1540 if (!msr_filter) {
1541 allowed = true;
1542 goto out;
1543 }
1544
1545 allowed = msr_filter->default_allow;
1546 ranges = msr_filter->ranges;
1547
1548 for (i = 0; i < msr_filter->count; i++) {
1549 u32 start = ranges[i].base;
1550 u32 end = start + ranges[i].nmsrs;
1551 u32 flags = ranges[i].flags;
1552 unsigned long *bitmap = ranges[i].bitmap;
1553
1554 if ((index >= start) && (index < end) && (flags & type)) {
1555 allowed = !!test_bit(index - start, bitmap);
1556 break;
1557 }
1558 }
1559
1560 out:
1561 srcu_read_unlock(&kvm->srcu, idx);
1562
1563 return allowed;
1564 }
1565 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1566
1567 /*
1568 * Write @data into the MSR specified by @index. Select MSR specific fault
1569 * checks are bypassed if @host_initiated is %true.
1570 * Returns 0 on success, non-0 otherwise.
1571 * Assumes vcpu_load() was already called.
1572 */
1573 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1574 bool host_initiated)
1575 {
1576 struct msr_data msr;
1577
1578 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1579 return KVM_MSR_RET_FILTERED;
1580
1581 switch (index) {
1582 case MSR_FS_BASE:
1583 case MSR_GS_BASE:
1584 case MSR_KERNEL_GS_BASE:
1585 case MSR_CSTAR:
1586 case MSR_LSTAR:
1587 if (is_noncanonical_address(data, vcpu))
1588 return 1;
1589 break;
1590 case MSR_IA32_SYSENTER_EIP:
1591 case MSR_IA32_SYSENTER_ESP:
1592 /*
1593 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1594 * non-canonical address is written on Intel but not on
1595 * AMD (which ignores the top 32-bits, because it does
1596 * not implement 64-bit SYSENTER).
1597 *
1598 * 64-bit code should hence be able to write a non-canonical
1599 * value on AMD. Making the address canonical ensures that
1600 * vmentry does not fail on Intel after writing a non-canonical
1601 * value, and that something deterministic happens if the guest
1602 * invokes 64-bit SYSENTER.
1603 */
1604 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1605 }
1606
1607 msr.data = data;
1608 msr.index = index;
1609 msr.host_initiated = host_initiated;
1610
1611 return kvm_x86_ops.set_msr(vcpu, &msr);
1612 }
1613
1614 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1615 u32 index, u64 data, bool host_initiated)
1616 {
1617 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1618
1619 if (ret == KVM_MSR_RET_INVALID)
1620 if (kvm_msr_ignored_check(vcpu, index, data, true))
1621 ret = 0;
1622
1623 return ret;
1624 }
1625
1626 /*
1627 * Read the MSR specified by @index into @data. Select MSR specific fault
1628 * checks are bypassed if @host_initiated is %true.
1629 * Returns 0 on success, non-0 otherwise.
1630 * Assumes vcpu_load() was already called.
1631 */
1632 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1633 bool host_initiated)
1634 {
1635 struct msr_data msr;
1636 int ret;
1637
1638 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1639 return KVM_MSR_RET_FILTERED;
1640
1641 msr.index = index;
1642 msr.host_initiated = host_initiated;
1643
1644 ret = kvm_x86_ops.get_msr(vcpu, &msr);
1645 if (!ret)
1646 *data = msr.data;
1647 return ret;
1648 }
1649
1650 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1651 u32 index, u64 *data, bool host_initiated)
1652 {
1653 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1654
1655 if (ret == KVM_MSR_RET_INVALID) {
1656 /* Unconditionally clear *data for simplicity */
1657 *data = 0;
1658 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1659 ret = 0;
1660 }
1661
1662 return ret;
1663 }
1664
1665 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1666 {
1667 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1668 }
1669 EXPORT_SYMBOL_GPL(kvm_get_msr);
1670
1671 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1672 {
1673 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1674 }
1675 EXPORT_SYMBOL_GPL(kvm_set_msr);
1676
1677 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1678 {
1679 int err = vcpu->run->msr.error;
1680 if (!err) {
1681 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1682 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1683 }
1684
1685 return kvm_x86_ops.complete_emulated_msr(vcpu, err);
1686 }
1687
1688 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1689 {
1690 return kvm_x86_ops.complete_emulated_msr(vcpu, vcpu->run->msr.error);
1691 }
1692
1693 static u64 kvm_msr_reason(int r)
1694 {
1695 switch (r) {
1696 case KVM_MSR_RET_INVALID:
1697 return KVM_MSR_EXIT_REASON_UNKNOWN;
1698 case KVM_MSR_RET_FILTERED:
1699 return KVM_MSR_EXIT_REASON_FILTER;
1700 default:
1701 return KVM_MSR_EXIT_REASON_INVAL;
1702 }
1703 }
1704
1705 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1706 u32 exit_reason, u64 data,
1707 int (*completion)(struct kvm_vcpu *vcpu),
1708 int r)
1709 {
1710 u64 msr_reason = kvm_msr_reason(r);
1711
1712 /* Check if the user wanted to know about this MSR fault */
1713 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1714 return 0;
1715
1716 vcpu->run->exit_reason = exit_reason;
1717 vcpu->run->msr.error = 0;
1718 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1719 vcpu->run->msr.reason = msr_reason;
1720 vcpu->run->msr.index = index;
1721 vcpu->run->msr.data = data;
1722 vcpu->arch.complete_userspace_io = completion;
1723
1724 return 1;
1725 }
1726
1727 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1728 {
1729 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1730 complete_emulated_rdmsr, r);
1731 }
1732
1733 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1734 {
1735 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1736 complete_emulated_wrmsr, r);
1737 }
1738
1739 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1740 {
1741 u32 ecx = kvm_rcx_read(vcpu);
1742 u64 data;
1743 int r;
1744
1745 r = kvm_get_msr(vcpu, ecx, &data);
1746
1747 /* MSR read failed? See if we should ask user space */
1748 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1749 /* Bounce to user space */
1750 return 0;
1751 }
1752
1753 if (!r) {
1754 trace_kvm_msr_read(ecx, data);
1755
1756 kvm_rax_write(vcpu, data & -1u);
1757 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1758 } else {
1759 trace_kvm_msr_read_ex(ecx);
1760 }
1761
1762 return kvm_x86_ops.complete_emulated_msr(vcpu, r);
1763 }
1764 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1765
1766 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1767 {
1768 u32 ecx = kvm_rcx_read(vcpu);
1769 u64 data = kvm_read_edx_eax(vcpu);
1770 int r;
1771
1772 r = kvm_set_msr(vcpu, ecx, data);
1773
1774 /* MSR write failed? See if we should ask user space */
1775 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r))
1776 /* Bounce to user space */
1777 return 0;
1778
1779 /* Signal all other negative errors to userspace */
1780 if (r < 0)
1781 return r;
1782
1783 if (!r)
1784 trace_kvm_msr_write(ecx, data);
1785 else
1786 trace_kvm_msr_write_ex(ecx, data);
1787
1788 return kvm_x86_ops.complete_emulated_msr(vcpu, r);
1789 }
1790 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1791
1792 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1793 {
1794 xfer_to_guest_mode_prepare();
1795 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1796 xfer_to_guest_mode_work_pending();
1797 }
1798 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1799
1800 /*
1801 * The fast path for frequent and performance sensitive wrmsr emulation,
1802 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1803 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1804 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1805 * other cases which must be called after interrupts are enabled on the host.
1806 */
1807 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1808 {
1809 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1810 return 1;
1811
1812 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1813 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1814 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1815 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1816
1817 data &= ~(1 << 12);
1818 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1819 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1820 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1821 trace_kvm_apic_write(APIC_ICR, (u32)data);
1822 return 0;
1823 }
1824
1825 return 1;
1826 }
1827
1828 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1829 {
1830 if (!kvm_can_use_hv_timer(vcpu))
1831 return 1;
1832
1833 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1834 return 0;
1835 }
1836
1837 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1838 {
1839 u32 msr = kvm_rcx_read(vcpu);
1840 u64 data;
1841 fastpath_t ret = EXIT_FASTPATH_NONE;
1842
1843 switch (msr) {
1844 case APIC_BASE_MSR + (APIC_ICR >> 4):
1845 data = kvm_read_edx_eax(vcpu);
1846 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1847 kvm_skip_emulated_instruction(vcpu);
1848 ret = EXIT_FASTPATH_EXIT_HANDLED;
1849 }
1850 break;
1851 case MSR_IA32_TSCDEADLINE:
1852 data = kvm_read_edx_eax(vcpu);
1853 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1854 kvm_skip_emulated_instruction(vcpu);
1855 ret = EXIT_FASTPATH_REENTER_GUEST;
1856 }
1857 break;
1858 default:
1859 break;
1860 }
1861
1862 if (ret != EXIT_FASTPATH_NONE)
1863 trace_kvm_msr_write(msr, data);
1864
1865 return ret;
1866 }
1867 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1868
1869 /*
1870 * Adapt set_msr() to msr_io()'s calling convention
1871 */
1872 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1873 {
1874 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1875 }
1876
1877 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1878 {
1879 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1880 }
1881
1882 #ifdef CONFIG_X86_64
1883 struct pvclock_clock {
1884 int vclock_mode;
1885 u64 cycle_last;
1886 u64 mask;
1887 u32 mult;
1888 u32 shift;
1889 u64 base_cycles;
1890 u64 offset;
1891 };
1892
1893 struct pvclock_gtod_data {
1894 seqcount_t seq;
1895
1896 struct pvclock_clock clock; /* extract of a clocksource struct */
1897 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1898
1899 ktime_t offs_boot;
1900 u64 wall_time_sec;
1901 };
1902
1903 static struct pvclock_gtod_data pvclock_gtod_data;
1904
1905 static void update_pvclock_gtod(struct timekeeper *tk)
1906 {
1907 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1908
1909 write_seqcount_begin(&vdata->seq);
1910
1911 /* copy pvclock gtod data */
1912 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1913 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1914 vdata->clock.mask = tk->tkr_mono.mask;
1915 vdata->clock.mult = tk->tkr_mono.mult;
1916 vdata->clock.shift = tk->tkr_mono.shift;
1917 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1918 vdata->clock.offset = tk->tkr_mono.base;
1919
1920 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1921 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1922 vdata->raw_clock.mask = tk->tkr_raw.mask;
1923 vdata->raw_clock.mult = tk->tkr_raw.mult;
1924 vdata->raw_clock.shift = tk->tkr_raw.shift;
1925 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1926 vdata->raw_clock.offset = tk->tkr_raw.base;
1927
1928 vdata->wall_time_sec = tk->xtime_sec;
1929
1930 vdata->offs_boot = tk->offs_boot;
1931
1932 write_seqcount_end(&vdata->seq);
1933 }
1934
1935 static s64 get_kvmclock_base_ns(void)
1936 {
1937 /* Count up from boot time, but with the frequency of the raw clock. */
1938 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1939 }
1940 #else
1941 static s64 get_kvmclock_base_ns(void)
1942 {
1943 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1944 return ktime_get_boottime_ns();
1945 }
1946 #endif
1947
1948 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1949 {
1950 int version;
1951 int r;
1952 struct pvclock_wall_clock wc;
1953 u64 wall_nsec;
1954
1955 kvm->arch.wall_clock = wall_clock;
1956
1957 if (!wall_clock)
1958 return;
1959
1960 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1961 if (r)
1962 return;
1963
1964 if (version & 1)
1965 ++version; /* first time write, random junk */
1966
1967 ++version;
1968
1969 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1970 return;
1971
1972 /*
1973 * The guest calculates current wall clock time by adding
1974 * system time (updated by kvm_guest_time_update below) to the
1975 * wall clock specified here. We do the reverse here.
1976 */
1977 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1978
1979 wc.nsec = do_div(wall_nsec, 1000000000);
1980 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1981 wc.version = version;
1982
1983 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1984
1985 version++;
1986 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1987 }
1988
1989 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1990 bool old_msr, bool host_initiated)
1991 {
1992 struct kvm_arch *ka = &vcpu->kvm->arch;
1993
1994 if (vcpu->vcpu_id == 0 && !host_initiated) {
1995 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
1996 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1997
1998 ka->boot_vcpu_runs_old_kvmclock = old_msr;
1999 }
2000
2001 vcpu->arch.time = system_time;
2002 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2003
2004 /* we verify if the enable bit is set... */
2005 vcpu->arch.pv_time_enabled = false;
2006 if (!(system_time & 1))
2007 return;
2008
2009 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2010 &vcpu->arch.pv_time, system_time & ~1ULL,
2011 sizeof(struct pvclock_vcpu_time_info)))
2012 vcpu->arch.pv_time_enabled = true;
2013
2014 return;
2015 }
2016
2017 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2018 {
2019 do_shl32_div32(dividend, divisor);
2020 return dividend;
2021 }
2022
2023 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2024 s8 *pshift, u32 *pmultiplier)
2025 {
2026 uint64_t scaled64;
2027 int32_t shift = 0;
2028 uint64_t tps64;
2029 uint32_t tps32;
2030
2031 tps64 = base_hz;
2032 scaled64 = scaled_hz;
2033 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2034 tps64 >>= 1;
2035 shift--;
2036 }
2037
2038 tps32 = (uint32_t)tps64;
2039 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2040 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2041 scaled64 >>= 1;
2042 else
2043 tps32 <<= 1;
2044 shift++;
2045 }
2046
2047 *pshift = shift;
2048 *pmultiplier = div_frac(scaled64, tps32);
2049 }
2050
2051 #ifdef CONFIG_X86_64
2052 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2053 #endif
2054
2055 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2056 static unsigned long max_tsc_khz;
2057
2058 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2059 {
2060 u64 v = (u64)khz * (1000000 + ppm);
2061 do_div(v, 1000000);
2062 return v;
2063 }
2064
2065 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2066 {
2067 u64 ratio;
2068
2069 /* Guest TSC same frequency as host TSC? */
2070 if (!scale) {
2071 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2072 return 0;
2073 }
2074
2075 /* TSC scaling supported? */
2076 if (!kvm_has_tsc_control) {
2077 if (user_tsc_khz > tsc_khz) {
2078 vcpu->arch.tsc_catchup = 1;
2079 vcpu->arch.tsc_always_catchup = 1;
2080 return 0;
2081 } else {
2082 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2083 return -1;
2084 }
2085 }
2086
2087 /* TSC scaling required - calculate ratio */
2088 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2089 user_tsc_khz, tsc_khz);
2090
2091 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2092 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2093 user_tsc_khz);
2094 return -1;
2095 }
2096
2097 vcpu->arch.tsc_scaling_ratio = ratio;
2098 return 0;
2099 }
2100
2101 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2102 {
2103 u32 thresh_lo, thresh_hi;
2104 int use_scaling = 0;
2105
2106 /* tsc_khz can be zero if TSC calibration fails */
2107 if (user_tsc_khz == 0) {
2108 /* set tsc_scaling_ratio to a safe value */
2109 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2110 return -1;
2111 }
2112
2113 /* Compute a scale to convert nanoseconds in TSC cycles */
2114 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2115 &vcpu->arch.virtual_tsc_shift,
2116 &vcpu->arch.virtual_tsc_mult);
2117 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2118
2119 /*
2120 * Compute the variation in TSC rate which is acceptable
2121 * within the range of tolerance and decide if the
2122 * rate being applied is within that bounds of the hardware
2123 * rate. If so, no scaling or compensation need be done.
2124 */
2125 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2126 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2127 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2128 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2129 use_scaling = 1;
2130 }
2131 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2132 }
2133
2134 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2135 {
2136 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2137 vcpu->arch.virtual_tsc_mult,
2138 vcpu->arch.virtual_tsc_shift);
2139 tsc += vcpu->arch.this_tsc_write;
2140 return tsc;
2141 }
2142
2143 static inline int gtod_is_based_on_tsc(int mode)
2144 {
2145 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2146 }
2147
2148 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2149 {
2150 #ifdef CONFIG_X86_64
2151 bool vcpus_matched;
2152 struct kvm_arch *ka = &vcpu->kvm->arch;
2153 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2154
2155 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2156 atomic_read(&vcpu->kvm->online_vcpus));
2157
2158 /*
2159 * Once the masterclock is enabled, always perform request in
2160 * order to update it.
2161 *
2162 * In order to enable masterclock, the host clocksource must be TSC
2163 * and the vcpus need to have matched TSCs. When that happens,
2164 * perform request to enable masterclock.
2165 */
2166 if (ka->use_master_clock ||
2167 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2168 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2169
2170 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2171 atomic_read(&vcpu->kvm->online_vcpus),
2172 ka->use_master_clock, gtod->clock.vclock_mode);
2173 #endif
2174 }
2175
2176 /*
2177 * Multiply tsc by a fixed point number represented by ratio.
2178 *
2179 * The most significant 64-N bits (mult) of ratio represent the
2180 * integral part of the fixed point number; the remaining N bits
2181 * (frac) represent the fractional part, ie. ratio represents a fixed
2182 * point number (mult + frac * 2^(-N)).
2183 *
2184 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2185 */
2186 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2187 {
2188 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2189 }
2190
2191 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2192 {
2193 u64 _tsc = tsc;
2194 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2195
2196 if (ratio != kvm_default_tsc_scaling_ratio)
2197 _tsc = __scale_tsc(ratio, tsc);
2198
2199 return _tsc;
2200 }
2201 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2202
2203 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2204 {
2205 u64 tsc;
2206
2207 tsc = kvm_scale_tsc(vcpu, rdtsc());
2208
2209 return target_tsc - tsc;
2210 }
2211
2212 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2213 {
2214 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2215 }
2216 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2217
2218 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2219 {
2220 vcpu->arch.l1_tsc_offset = offset;
2221 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2222 }
2223
2224 static inline bool kvm_check_tsc_unstable(void)
2225 {
2226 #ifdef CONFIG_X86_64
2227 /*
2228 * TSC is marked unstable when we're running on Hyper-V,
2229 * 'TSC page' clocksource is good.
2230 */
2231 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2232 return false;
2233 #endif
2234 return check_tsc_unstable();
2235 }
2236
2237 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2238 {
2239 struct kvm *kvm = vcpu->kvm;
2240 u64 offset, ns, elapsed;
2241 unsigned long flags;
2242 bool matched;
2243 bool already_matched;
2244 bool synchronizing = false;
2245
2246 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2247 offset = kvm_compute_tsc_offset(vcpu, data);
2248 ns = get_kvmclock_base_ns();
2249 elapsed = ns - kvm->arch.last_tsc_nsec;
2250
2251 if (vcpu->arch.virtual_tsc_khz) {
2252 if (data == 0) {
2253 /*
2254 * detection of vcpu initialization -- need to sync
2255 * with other vCPUs. This particularly helps to keep
2256 * kvm_clock stable after CPU hotplug
2257 */
2258 synchronizing = true;
2259 } else {
2260 u64 tsc_exp = kvm->arch.last_tsc_write +
2261 nsec_to_cycles(vcpu, elapsed);
2262 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2263 /*
2264 * Special case: TSC write with a small delta (1 second)
2265 * of virtual cycle time against real time is
2266 * interpreted as an attempt to synchronize the CPU.
2267 */
2268 synchronizing = data < tsc_exp + tsc_hz &&
2269 data + tsc_hz > tsc_exp;
2270 }
2271 }
2272
2273 /*
2274 * For a reliable TSC, we can match TSC offsets, and for an unstable
2275 * TSC, we add elapsed time in this computation. We could let the
2276 * compensation code attempt to catch up if we fall behind, but
2277 * it's better to try to match offsets from the beginning.
2278 */
2279 if (synchronizing &&
2280 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2281 if (!kvm_check_tsc_unstable()) {
2282 offset = kvm->arch.cur_tsc_offset;
2283 } else {
2284 u64 delta = nsec_to_cycles(vcpu, elapsed);
2285 data += delta;
2286 offset = kvm_compute_tsc_offset(vcpu, data);
2287 }
2288 matched = true;
2289 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2290 } else {
2291 /*
2292 * We split periods of matched TSC writes into generations.
2293 * For each generation, we track the original measured
2294 * nanosecond time, offset, and write, so if TSCs are in
2295 * sync, we can match exact offset, and if not, we can match
2296 * exact software computation in compute_guest_tsc()
2297 *
2298 * These values are tracked in kvm->arch.cur_xxx variables.
2299 */
2300 kvm->arch.cur_tsc_generation++;
2301 kvm->arch.cur_tsc_nsec = ns;
2302 kvm->arch.cur_tsc_write = data;
2303 kvm->arch.cur_tsc_offset = offset;
2304 matched = false;
2305 }
2306
2307 /*
2308 * We also track th most recent recorded KHZ, write and time to
2309 * allow the matching interval to be extended at each write.
2310 */
2311 kvm->arch.last_tsc_nsec = ns;
2312 kvm->arch.last_tsc_write = data;
2313 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2314
2315 vcpu->arch.last_guest_tsc = data;
2316
2317 /* Keep track of which generation this VCPU has synchronized to */
2318 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2319 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2320 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2321
2322 kvm_vcpu_write_tsc_offset(vcpu, offset);
2323 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2324
2325 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2326 if (!matched) {
2327 kvm->arch.nr_vcpus_matched_tsc = 0;
2328 } else if (!already_matched) {
2329 kvm->arch.nr_vcpus_matched_tsc++;
2330 }
2331
2332 kvm_track_tsc_matching(vcpu);
2333 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2334 }
2335
2336 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2337 s64 adjustment)
2338 {
2339 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2340 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2341 }
2342
2343 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2344 {
2345 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2346 WARN_ON(adjustment < 0);
2347 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2348 adjust_tsc_offset_guest(vcpu, adjustment);
2349 }
2350
2351 #ifdef CONFIG_X86_64
2352
2353 static u64 read_tsc(void)
2354 {
2355 u64 ret = (u64)rdtsc_ordered();
2356 u64 last = pvclock_gtod_data.clock.cycle_last;
2357
2358 if (likely(ret >= last))
2359 return ret;
2360
2361 /*
2362 * GCC likes to generate cmov here, but this branch is extremely
2363 * predictable (it's just a function of time and the likely is
2364 * very likely) and there's a data dependence, so force GCC
2365 * to generate a branch instead. I don't barrier() because
2366 * we don't actually need a barrier, and if this function
2367 * ever gets inlined it will generate worse code.
2368 */
2369 asm volatile ("");
2370 return last;
2371 }
2372
2373 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2374 int *mode)
2375 {
2376 long v;
2377 u64 tsc_pg_val;
2378
2379 switch (clock->vclock_mode) {
2380 case VDSO_CLOCKMODE_HVCLOCK:
2381 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2382 tsc_timestamp);
2383 if (tsc_pg_val != U64_MAX) {
2384 /* TSC page valid */
2385 *mode = VDSO_CLOCKMODE_HVCLOCK;
2386 v = (tsc_pg_val - clock->cycle_last) &
2387 clock->mask;
2388 } else {
2389 /* TSC page invalid */
2390 *mode = VDSO_CLOCKMODE_NONE;
2391 }
2392 break;
2393 case VDSO_CLOCKMODE_TSC:
2394 *mode = VDSO_CLOCKMODE_TSC;
2395 *tsc_timestamp = read_tsc();
2396 v = (*tsc_timestamp - clock->cycle_last) &
2397 clock->mask;
2398 break;
2399 default:
2400 *mode = VDSO_CLOCKMODE_NONE;
2401 }
2402
2403 if (*mode == VDSO_CLOCKMODE_NONE)
2404 *tsc_timestamp = v = 0;
2405
2406 return v * clock->mult;
2407 }
2408
2409 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2410 {
2411 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2412 unsigned long seq;
2413 int mode;
2414 u64 ns;
2415
2416 do {
2417 seq = read_seqcount_begin(&gtod->seq);
2418 ns = gtod->raw_clock.base_cycles;
2419 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2420 ns >>= gtod->raw_clock.shift;
2421 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2422 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2423 *t = ns;
2424
2425 return mode;
2426 }
2427
2428 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2429 {
2430 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2431 unsigned long seq;
2432 int mode;
2433 u64 ns;
2434
2435 do {
2436 seq = read_seqcount_begin(&gtod->seq);
2437 ts->tv_sec = gtod->wall_time_sec;
2438 ns = gtod->clock.base_cycles;
2439 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2440 ns >>= gtod->clock.shift;
2441 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2442
2443 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2444 ts->tv_nsec = ns;
2445
2446 return mode;
2447 }
2448
2449 /* returns true if host is using TSC based clocksource */
2450 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2451 {
2452 /* checked again under seqlock below */
2453 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2454 return false;
2455
2456 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2457 tsc_timestamp));
2458 }
2459
2460 /* returns true if host is using TSC based clocksource */
2461 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2462 u64 *tsc_timestamp)
2463 {
2464 /* checked again under seqlock below */
2465 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2466 return false;
2467
2468 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2469 }
2470 #endif
2471
2472 /*
2473 *
2474 * Assuming a stable TSC across physical CPUS, and a stable TSC
2475 * across virtual CPUs, the following condition is possible.
2476 * Each numbered line represents an event visible to both
2477 * CPUs at the next numbered event.
2478 *
2479 * "timespecX" represents host monotonic time. "tscX" represents
2480 * RDTSC value.
2481 *
2482 * VCPU0 on CPU0 | VCPU1 on CPU1
2483 *
2484 * 1. read timespec0,tsc0
2485 * 2. | timespec1 = timespec0 + N
2486 * | tsc1 = tsc0 + M
2487 * 3. transition to guest | transition to guest
2488 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2489 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2490 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2491 *
2492 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2493 *
2494 * - ret0 < ret1
2495 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2496 * ...
2497 * - 0 < N - M => M < N
2498 *
2499 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2500 * always the case (the difference between two distinct xtime instances
2501 * might be smaller then the difference between corresponding TSC reads,
2502 * when updating guest vcpus pvclock areas).
2503 *
2504 * To avoid that problem, do not allow visibility of distinct
2505 * system_timestamp/tsc_timestamp values simultaneously: use a master
2506 * copy of host monotonic time values. Update that master copy
2507 * in lockstep.
2508 *
2509 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2510 *
2511 */
2512
2513 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2514 {
2515 #ifdef CONFIG_X86_64
2516 struct kvm_arch *ka = &kvm->arch;
2517 int vclock_mode;
2518 bool host_tsc_clocksource, vcpus_matched;
2519
2520 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2521 atomic_read(&kvm->online_vcpus));
2522
2523 /*
2524 * If the host uses TSC clock, then passthrough TSC as stable
2525 * to the guest.
2526 */
2527 host_tsc_clocksource = kvm_get_time_and_clockread(
2528 &ka->master_kernel_ns,
2529 &ka->master_cycle_now);
2530
2531 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2532 && !ka->backwards_tsc_observed
2533 && !ka->boot_vcpu_runs_old_kvmclock;
2534
2535 if (ka->use_master_clock)
2536 atomic_set(&kvm_guest_has_master_clock, 1);
2537
2538 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2539 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2540 vcpus_matched);
2541 #endif
2542 }
2543
2544 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2545 {
2546 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2547 }
2548
2549 static void kvm_gen_update_masterclock(struct kvm *kvm)
2550 {
2551 #ifdef CONFIG_X86_64
2552 int i;
2553 struct kvm_vcpu *vcpu;
2554 struct kvm_arch *ka = &kvm->arch;
2555
2556 spin_lock(&ka->pvclock_gtod_sync_lock);
2557 kvm_make_mclock_inprogress_request(kvm);
2558 /* no guest entries from this point */
2559 pvclock_update_vm_gtod_copy(kvm);
2560
2561 kvm_for_each_vcpu(i, vcpu, kvm)
2562 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2563
2564 /* guest entries allowed */
2565 kvm_for_each_vcpu(i, vcpu, kvm)
2566 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2567
2568 spin_unlock(&ka->pvclock_gtod_sync_lock);
2569 #endif
2570 }
2571
2572 u64 get_kvmclock_ns(struct kvm *kvm)
2573 {
2574 struct kvm_arch *ka = &kvm->arch;
2575 struct pvclock_vcpu_time_info hv_clock;
2576 u64 ret;
2577
2578 spin_lock(&ka->pvclock_gtod_sync_lock);
2579 if (!ka->use_master_clock) {
2580 spin_unlock(&ka->pvclock_gtod_sync_lock);
2581 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2582 }
2583
2584 hv_clock.tsc_timestamp = ka->master_cycle_now;
2585 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2586 spin_unlock(&ka->pvclock_gtod_sync_lock);
2587
2588 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2589 get_cpu();
2590
2591 if (__this_cpu_read(cpu_tsc_khz)) {
2592 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2593 &hv_clock.tsc_shift,
2594 &hv_clock.tsc_to_system_mul);
2595 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2596 } else
2597 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2598
2599 put_cpu();
2600
2601 return ret;
2602 }
2603
2604 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2605 {
2606 struct kvm_vcpu_arch *vcpu = &v->arch;
2607 struct pvclock_vcpu_time_info guest_hv_clock;
2608
2609 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2610 &guest_hv_clock, sizeof(guest_hv_clock))))
2611 return;
2612
2613 /* This VCPU is paused, but it's legal for a guest to read another
2614 * VCPU's kvmclock, so we really have to follow the specification where
2615 * it says that version is odd if data is being modified, and even after
2616 * it is consistent.
2617 *
2618 * Version field updates must be kept separate. This is because
2619 * kvm_write_guest_cached might use a "rep movs" instruction, and
2620 * writes within a string instruction are weakly ordered. So there
2621 * are three writes overall.
2622 *
2623 * As a small optimization, only write the version field in the first
2624 * and third write. The vcpu->pv_time cache is still valid, because the
2625 * version field is the first in the struct.
2626 */
2627 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2628
2629 if (guest_hv_clock.version & 1)
2630 ++guest_hv_clock.version; /* first time write, random junk */
2631
2632 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2633 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2634 &vcpu->hv_clock,
2635 sizeof(vcpu->hv_clock.version));
2636
2637 smp_wmb();
2638
2639 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2640 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2641
2642 if (vcpu->pvclock_set_guest_stopped_request) {
2643 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2644 vcpu->pvclock_set_guest_stopped_request = false;
2645 }
2646
2647 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2648
2649 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2650 &vcpu->hv_clock,
2651 sizeof(vcpu->hv_clock));
2652
2653 smp_wmb();
2654
2655 vcpu->hv_clock.version++;
2656 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2657 &vcpu->hv_clock,
2658 sizeof(vcpu->hv_clock.version));
2659 }
2660
2661 static int kvm_guest_time_update(struct kvm_vcpu *v)
2662 {
2663 unsigned long flags, tgt_tsc_khz;
2664 struct kvm_vcpu_arch *vcpu = &v->arch;
2665 struct kvm_arch *ka = &v->kvm->arch;
2666 s64 kernel_ns;
2667 u64 tsc_timestamp, host_tsc;
2668 u8 pvclock_flags;
2669 bool use_master_clock;
2670
2671 kernel_ns = 0;
2672 host_tsc = 0;
2673
2674 /*
2675 * If the host uses TSC clock, then passthrough TSC as stable
2676 * to the guest.
2677 */
2678 spin_lock(&ka->pvclock_gtod_sync_lock);
2679 use_master_clock = ka->use_master_clock;
2680 if (use_master_clock) {
2681 host_tsc = ka->master_cycle_now;
2682 kernel_ns = ka->master_kernel_ns;
2683 }
2684 spin_unlock(&ka->pvclock_gtod_sync_lock);
2685
2686 /* Keep irq disabled to prevent changes to the clock */
2687 local_irq_save(flags);
2688 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2689 if (unlikely(tgt_tsc_khz == 0)) {
2690 local_irq_restore(flags);
2691 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2692 return 1;
2693 }
2694 if (!use_master_clock) {
2695 host_tsc = rdtsc();
2696 kernel_ns = get_kvmclock_base_ns();
2697 }
2698
2699 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2700
2701 /*
2702 * We may have to catch up the TSC to match elapsed wall clock
2703 * time for two reasons, even if kvmclock is used.
2704 * 1) CPU could have been running below the maximum TSC rate
2705 * 2) Broken TSC compensation resets the base at each VCPU
2706 * entry to avoid unknown leaps of TSC even when running
2707 * again on the same CPU. This may cause apparent elapsed
2708 * time to disappear, and the guest to stand still or run
2709 * very slowly.
2710 */
2711 if (vcpu->tsc_catchup) {
2712 u64 tsc = compute_guest_tsc(v, kernel_ns);
2713 if (tsc > tsc_timestamp) {
2714 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2715 tsc_timestamp = tsc;
2716 }
2717 }
2718
2719 local_irq_restore(flags);
2720
2721 /* With all the info we got, fill in the values */
2722
2723 if (kvm_has_tsc_control)
2724 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2725
2726 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2727 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2728 &vcpu->hv_clock.tsc_shift,
2729 &vcpu->hv_clock.tsc_to_system_mul);
2730 vcpu->hw_tsc_khz = tgt_tsc_khz;
2731 }
2732
2733 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2734 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2735 vcpu->last_guest_tsc = tsc_timestamp;
2736
2737 /* If the host uses TSC clocksource, then it is stable */
2738 pvclock_flags = 0;
2739 if (use_master_clock)
2740 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2741
2742 vcpu->hv_clock.flags = pvclock_flags;
2743
2744 if (vcpu->pv_time_enabled)
2745 kvm_setup_pvclock_page(v);
2746 if (v == kvm_get_vcpu(v->kvm, 0))
2747 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2748 return 0;
2749 }
2750
2751 /*
2752 * kvmclock updates which are isolated to a given vcpu, such as
2753 * vcpu->cpu migration, should not allow system_timestamp from
2754 * the rest of the vcpus to remain static. Otherwise ntp frequency
2755 * correction applies to one vcpu's system_timestamp but not
2756 * the others.
2757 *
2758 * So in those cases, request a kvmclock update for all vcpus.
2759 * We need to rate-limit these requests though, as they can
2760 * considerably slow guests that have a large number of vcpus.
2761 * The time for a remote vcpu to update its kvmclock is bound
2762 * by the delay we use to rate-limit the updates.
2763 */
2764
2765 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2766
2767 static void kvmclock_update_fn(struct work_struct *work)
2768 {
2769 int i;
2770 struct delayed_work *dwork = to_delayed_work(work);
2771 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2772 kvmclock_update_work);
2773 struct kvm *kvm = container_of(ka, struct kvm, arch);
2774 struct kvm_vcpu *vcpu;
2775
2776 kvm_for_each_vcpu(i, vcpu, kvm) {
2777 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2778 kvm_vcpu_kick(vcpu);
2779 }
2780 }
2781
2782 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2783 {
2784 struct kvm *kvm = v->kvm;
2785
2786 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2787 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2788 KVMCLOCK_UPDATE_DELAY);
2789 }
2790
2791 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2792
2793 static void kvmclock_sync_fn(struct work_struct *work)
2794 {
2795 struct delayed_work *dwork = to_delayed_work(work);
2796 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2797 kvmclock_sync_work);
2798 struct kvm *kvm = container_of(ka, struct kvm, arch);
2799
2800 if (!kvmclock_periodic_sync)
2801 return;
2802
2803 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2804 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2805 KVMCLOCK_SYNC_PERIOD);
2806 }
2807
2808 /*
2809 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2810 */
2811 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2812 {
2813 /* McStatusWrEn enabled? */
2814 if (guest_cpuid_is_amd_or_hygon(vcpu))
2815 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2816
2817 return false;
2818 }
2819
2820 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2821 {
2822 u64 mcg_cap = vcpu->arch.mcg_cap;
2823 unsigned bank_num = mcg_cap & 0xff;
2824 u32 msr = msr_info->index;
2825 u64 data = msr_info->data;
2826
2827 switch (msr) {
2828 case MSR_IA32_MCG_STATUS:
2829 vcpu->arch.mcg_status = data;
2830 break;
2831 case MSR_IA32_MCG_CTL:
2832 if (!(mcg_cap & MCG_CTL_P) &&
2833 (data || !msr_info->host_initiated))
2834 return 1;
2835 if (data != 0 && data != ~(u64)0)
2836 return 1;
2837 vcpu->arch.mcg_ctl = data;
2838 break;
2839 default:
2840 if (msr >= MSR_IA32_MC0_CTL &&
2841 msr < MSR_IA32_MCx_CTL(bank_num)) {
2842 u32 offset = array_index_nospec(
2843 msr - MSR_IA32_MC0_CTL,
2844 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2845
2846 /* only 0 or all 1s can be written to IA32_MCi_CTL
2847 * some Linux kernels though clear bit 10 in bank 4 to
2848 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2849 * this to avoid an uncatched #GP in the guest
2850 */
2851 if ((offset & 0x3) == 0 &&
2852 data != 0 && (data | (1 << 10)) != ~(u64)0)
2853 return -1;
2854
2855 /* MCi_STATUS */
2856 if (!msr_info->host_initiated &&
2857 (offset & 0x3) == 1 && data != 0) {
2858 if (!can_set_mci_status(vcpu))
2859 return -1;
2860 }
2861
2862 vcpu->arch.mce_banks[offset] = data;
2863 break;
2864 }
2865 return 1;
2866 }
2867 return 0;
2868 }
2869
2870 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2871 {
2872 struct kvm *kvm = vcpu->kvm;
2873 int lm = is_long_mode(vcpu);
2874 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2875 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2876 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2877 : kvm->arch.xen_hvm_config.blob_size_32;
2878 u32 page_num = data & ~PAGE_MASK;
2879 u64 page_addr = data & PAGE_MASK;
2880 u8 *page;
2881
2882 if (page_num >= blob_size)
2883 return 1;
2884
2885 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2886 if (IS_ERR(page))
2887 return PTR_ERR(page);
2888
2889 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) {
2890 kfree(page);
2891 return 1;
2892 }
2893 return 0;
2894 }
2895
2896 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2897 {
2898 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2899
2900 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2901 }
2902
2903 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2904 {
2905 gpa_t gpa = data & ~0x3f;
2906
2907 /* Bits 4:5 are reserved, Should be zero */
2908 if (data & 0x30)
2909 return 1;
2910
2911 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
2912 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
2913 return 1;
2914
2915 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
2916 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
2917 return 1;
2918
2919 if (!lapic_in_kernel(vcpu))
2920 return data ? 1 : 0;
2921
2922 vcpu->arch.apf.msr_en_val = data;
2923
2924 if (!kvm_pv_async_pf_enabled(vcpu)) {
2925 kvm_clear_async_pf_completion_queue(vcpu);
2926 kvm_async_pf_hash_reset(vcpu);
2927 return 0;
2928 }
2929
2930 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2931 sizeof(u64)))
2932 return 1;
2933
2934 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2935 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2936
2937 kvm_async_pf_wakeup_all(vcpu);
2938
2939 return 0;
2940 }
2941
2942 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2943 {
2944 /* Bits 8-63 are reserved */
2945 if (data >> 8)
2946 return 1;
2947
2948 if (!lapic_in_kernel(vcpu))
2949 return 1;
2950
2951 vcpu->arch.apf.msr_int_val = data;
2952
2953 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2954
2955 return 0;
2956 }
2957
2958 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2959 {
2960 vcpu->arch.pv_time_enabled = false;
2961 vcpu->arch.time = 0;
2962 }
2963
2964 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2965 {
2966 ++vcpu->stat.tlb_flush;
2967 kvm_x86_ops.tlb_flush_all(vcpu);
2968 }
2969
2970 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2971 {
2972 ++vcpu->stat.tlb_flush;
2973 kvm_x86_ops.tlb_flush_guest(vcpu);
2974 }
2975
2976 static void record_steal_time(struct kvm_vcpu *vcpu)
2977 {
2978 struct kvm_host_map map;
2979 struct kvm_steal_time *st;
2980
2981 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2982 return;
2983
2984 /* -EAGAIN is returned in atomic context so we can just return. */
2985 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2986 &map, &vcpu->arch.st.cache, false))
2987 return;
2988
2989 st = map.hva +
2990 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2991
2992 /*
2993 * Doing a TLB flush here, on the guest's behalf, can avoid
2994 * expensive IPIs.
2995 */
2996 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
2997 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2998 st->preempted & KVM_VCPU_FLUSH_TLB);
2999 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
3000 kvm_vcpu_flush_tlb_guest(vcpu);
3001 }
3002
3003 vcpu->arch.st.preempted = 0;
3004
3005 if (st->version & 1)
3006 st->version += 1; /* first time write, random junk */
3007
3008 st->version += 1;
3009
3010 smp_wmb();
3011
3012 st->steal += current->sched_info.run_delay -
3013 vcpu->arch.st.last_steal;
3014 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3015
3016 smp_wmb();
3017
3018 st->version += 1;
3019
3020 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
3021 }
3022
3023 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3024 {
3025 bool pr = false;
3026 u32 msr = msr_info->index;
3027 u64 data = msr_info->data;
3028
3029 switch (msr) {
3030 case MSR_AMD64_NB_CFG:
3031 case MSR_IA32_UCODE_WRITE:
3032 case MSR_VM_HSAVE_PA:
3033 case MSR_AMD64_PATCH_LOADER:
3034 case MSR_AMD64_BU_CFG2:
3035 case MSR_AMD64_DC_CFG:
3036 case MSR_F15H_EX_CFG:
3037 break;
3038
3039 case MSR_IA32_UCODE_REV:
3040 if (msr_info->host_initiated)
3041 vcpu->arch.microcode_version = data;
3042 break;
3043 case MSR_IA32_ARCH_CAPABILITIES:
3044 if (!msr_info->host_initiated)
3045 return 1;
3046 vcpu->arch.arch_capabilities = data;
3047 break;
3048 case MSR_IA32_PERF_CAPABILITIES: {
3049 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3050
3051 if (!msr_info->host_initiated)
3052 return 1;
3053 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3054 return 1;
3055 if (data & ~msr_ent.data)
3056 return 1;
3057
3058 vcpu->arch.perf_capabilities = data;
3059
3060 return 0;
3061 }
3062 case MSR_EFER:
3063 return set_efer(vcpu, msr_info);
3064 case MSR_K7_HWCR:
3065 data &= ~(u64)0x40; /* ignore flush filter disable */
3066 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3067 data &= ~(u64)0x8; /* ignore TLB cache disable */
3068
3069 /* Handle McStatusWrEn */
3070 if (data == BIT_ULL(18)) {
3071 vcpu->arch.msr_hwcr = data;
3072 } else if (data != 0) {
3073 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3074 data);
3075 return 1;
3076 }
3077 break;
3078 case MSR_FAM10H_MMIO_CONF_BASE:
3079 if (data != 0) {
3080 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3081 "0x%llx\n", data);
3082 return 1;
3083 }
3084 break;
3085 case MSR_IA32_DEBUGCTLMSR:
3086 if (!data) {
3087 /* We support the non-activated case already */
3088 break;
3089 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
3090 /* Values other than LBR and BTF are vendor-specific,
3091 thus reserved and should throw a #GP */
3092 return 1;
3093 } else if (report_ignored_msrs)
3094 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
3095 __func__, data);
3096 break;
3097 case 0x200 ... 0x2ff:
3098 return kvm_mtrr_set_msr(vcpu, msr, data);
3099 case MSR_IA32_APICBASE:
3100 return kvm_set_apic_base(vcpu, msr_info);
3101 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3102 return kvm_x2apic_msr_write(vcpu, msr, data);
3103 case MSR_IA32_TSCDEADLINE:
3104 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3105 break;
3106 case MSR_IA32_TSC_ADJUST:
3107 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3108 if (!msr_info->host_initiated) {
3109 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3110 adjust_tsc_offset_guest(vcpu, adj);
3111 }
3112 vcpu->arch.ia32_tsc_adjust_msr = data;
3113 }
3114 break;
3115 case MSR_IA32_MISC_ENABLE:
3116 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3117 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3118 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3119 return 1;
3120 vcpu->arch.ia32_misc_enable_msr = data;
3121 kvm_update_cpuid_runtime(vcpu);
3122 } else {
3123 vcpu->arch.ia32_misc_enable_msr = data;
3124 }
3125 break;
3126 case MSR_IA32_SMBASE:
3127 if (!msr_info->host_initiated)
3128 return 1;
3129 vcpu->arch.smbase = data;
3130 break;
3131 case MSR_IA32_POWER_CTL:
3132 vcpu->arch.msr_ia32_power_ctl = data;
3133 break;
3134 case MSR_IA32_TSC:
3135 if (msr_info->host_initiated) {
3136 kvm_synchronize_tsc(vcpu, data);
3137 } else {
3138 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3139 adjust_tsc_offset_guest(vcpu, adj);
3140 vcpu->arch.ia32_tsc_adjust_msr += adj;
3141 }
3142 break;
3143 case MSR_IA32_XSS:
3144 if (!msr_info->host_initiated &&
3145 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3146 return 1;
3147 /*
3148 * KVM supports exposing PT to the guest, but does not support
3149 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3150 * XSAVES/XRSTORS to save/restore PT MSRs.
3151 */
3152 if (data & ~supported_xss)
3153 return 1;
3154 vcpu->arch.ia32_xss = data;
3155 break;
3156 case MSR_SMI_COUNT:
3157 if (!msr_info->host_initiated)
3158 return 1;
3159 vcpu->arch.smi_count = data;
3160 break;
3161 case MSR_KVM_WALL_CLOCK_NEW:
3162 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3163 return 1;
3164
3165 kvm_write_wall_clock(vcpu->kvm, data);
3166 break;
3167 case MSR_KVM_WALL_CLOCK:
3168 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3169 return 1;
3170
3171 kvm_write_wall_clock(vcpu->kvm, data);
3172 break;
3173 case MSR_KVM_SYSTEM_TIME_NEW:
3174 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3175 return 1;
3176
3177 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3178 break;
3179 case MSR_KVM_SYSTEM_TIME:
3180 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3181 return 1;
3182
3183 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3184 break;
3185 case MSR_KVM_ASYNC_PF_EN:
3186 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3187 return 1;
3188
3189 if (kvm_pv_enable_async_pf(vcpu, data))
3190 return 1;
3191 break;
3192 case MSR_KVM_ASYNC_PF_INT:
3193 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3194 return 1;
3195
3196 if (kvm_pv_enable_async_pf_int(vcpu, data))
3197 return 1;
3198 break;
3199 case MSR_KVM_ASYNC_PF_ACK:
3200 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3201 return 1;
3202 if (data & 0x1) {
3203 vcpu->arch.apf.pageready_pending = false;
3204 kvm_check_async_pf_completion(vcpu);
3205 }
3206 break;
3207 case MSR_KVM_STEAL_TIME:
3208 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3209 return 1;
3210
3211 if (unlikely(!sched_info_on()))
3212 return 1;
3213
3214 if (data & KVM_STEAL_RESERVED_MASK)
3215 return 1;
3216
3217 vcpu->arch.st.msr_val = data;
3218
3219 if (!(data & KVM_MSR_ENABLED))
3220 break;
3221
3222 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3223
3224 break;
3225 case MSR_KVM_PV_EOI_EN:
3226 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3227 return 1;
3228
3229 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3230 return 1;
3231 break;
3232
3233 case MSR_KVM_POLL_CONTROL:
3234 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3235 return 1;
3236
3237 /* only enable bit supported */
3238 if (data & (-1ULL << 1))
3239 return 1;
3240
3241 vcpu->arch.msr_kvm_poll_control = data;
3242 break;
3243
3244 case MSR_IA32_MCG_CTL:
3245 case MSR_IA32_MCG_STATUS:
3246 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3247 return set_msr_mce(vcpu, msr_info);
3248
3249 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3250 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3251 pr = true;
3252 fallthrough;
3253 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3254 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3255 if (kvm_pmu_is_valid_msr(vcpu, msr))
3256 return kvm_pmu_set_msr(vcpu, msr_info);
3257
3258 if (pr || data != 0)
3259 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3260 "0x%x data 0x%llx\n", msr, data);
3261 break;
3262 case MSR_K7_CLK_CTL:
3263 /*
3264 * Ignore all writes to this no longer documented MSR.
3265 * Writes are only relevant for old K7 processors,
3266 * all pre-dating SVM, but a recommended workaround from
3267 * AMD for these chips. It is possible to specify the
3268 * affected processor models on the command line, hence
3269 * the need to ignore the workaround.
3270 */
3271 break;
3272 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3273 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3274 case HV_X64_MSR_SYNDBG_OPTIONS:
3275 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3276 case HV_X64_MSR_CRASH_CTL:
3277 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3278 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3279 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3280 case HV_X64_MSR_TSC_EMULATION_STATUS:
3281 return kvm_hv_set_msr_common(vcpu, msr, data,
3282 msr_info->host_initiated);
3283 case MSR_IA32_BBL_CR_CTL3:
3284 /* Drop writes to this legacy MSR -- see rdmsr
3285 * counterpart for further detail.
3286 */
3287 if (report_ignored_msrs)
3288 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3289 msr, data);
3290 break;
3291 case MSR_AMD64_OSVW_ID_LENGTH:
3292 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3293 return 1;
3294 vcpu->arch.osvw.length = data;
3295 break;
3296 case MSR_AMD64_OSVW_STATUS:
3297 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3298 return 1;
3299 vcpu->arch.osvw.status = data;
3300 break;
3301 case MSR_PLATFORM_INFO:
3302 if (!msr_info->host_initiated ||
3303 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3304 cpuid_fault_enabled(vcpu)))
3305 return 1;
3306 vcpu->arch.msr_platform_info = data;
3307 break;
3308 case MSR_MISC_FEATURES_ENABLES:
3309 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3310 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3311 !supports_cpuid_fault(vcpu)))
3312 return 1;
3313 vcpu->arch.msr_misc_features_enables = data;
3314 break;
3315 default:
3316 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3317 return xen_hvm_config(vcpu, data);
3318 if (kvm_pmu_is_valid_msr(vcpu, msr))
3319 return kvm_pmu_set_msr(vcpu, msr_info);
3320 return KVM_MSR_RET_INVALID;
3321 }
3322 return 0;
3323 }
3324 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3325
3326 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3327 {
3328 u64 data;
3329 u64 mcg_cap = vcpu->arch.mcg_cap;
3330 unsigned bank_num = mcg_cap & 0xff;
3331
3332 switch (msr) {
3333 case MSR_IA32_P5_MC_ADDR:
3334 case MSR_IA32_P5_MC_TYPE:
3335 data = 0;
3336 break;
3337 case MSR_IA32_MCG_CAP:
3338 data = vcpu->arch.mcg_cap;
3339 break;
3340 case MSR_IA32_MCG_CTL:
3341 if (!(mcg_cap & MCG_CTL_P) && !host)
3342 return 1;
3343 data = vcpu->arch.mcg_ctl;
3344 break;
3345 case MSR_IA32_MCG_STATUS:
3346 data = vcpu->arch.mcg_status;
3347 break;
3348 default:
3349 if (msr >= MSR_IA32_MC0_CTL &&
3350 msr < MSR_IA32_MCx_CTL(bank_num)) {
3351 u32 offset = array_index_nospec(
3352 msr - MSR_IA32_MC0_CTL,
3353 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3354
3355 data = vcpu->arch.mce_banks[offset];
3356 break;
3357 }
3358 return 1;
3359 }
3360 *pdata = data;
3361 return 0;
3362 }
3363
3364 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3365 {
3366 switch (msr_info->index) {
3367 case MSR_IA32_PLATFORM_ID:
3368 case MSR_IA32_EBL_CR_POWERON:
3369 case MSR_IA32_DEBUGCTLMSR:
3370 case MSR_IA32_LASTBRANCHFROMIP:
3371 case MSR_IA32_LASTBRANCHTOIP:
3372 case MSR_IA32_LASTINTFROMIP:
3373 case MSR_IA32_LASTINTTOIP:
3374 case MSR_K8_SYSCFG:
3375 case MSR_K8_TSEG_ADDR:
3376 case MSR_K8_TSEG_MASK:
3377 case MSR_VM_HSAVE_PA:
3378 case MSR_K8_INT_PENDING_MSG:
3379 case MSR_AMD64_NB_CFG:
3380 case MSR_FAM10H_MMIO_CONF_BASE:
3381 case MSR_AMD64_BU_CFG2:
3382 case MSR_IA32_PERF_CTL:
3383 case MSR_AMD64_DC_CFG:
3384 case MSR_F15H_EX_CFG:
3385 /*
3386 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3387 * limit) MSRs. Just return 0, as we do not want to expose the host
3388 * data here. Do not conditionalize this on CPUID, as KVM does not do
3389 * so for existing CPU-specific MSRs.
3390 */
3391 case MSR_RAPL_POWER_UNIT:
3392 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3393 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3394 case MSR_PKG_ENERGY_STATUS: /* Total package */
3395 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3396 msr_info->data = 0;
3397 break;
3398 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3399 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3400 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3401 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3402 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3403 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3404 return kvm_pmu_get_msr(vcpu, msr_info);
3405 msr_info->data = 0;
3406 break;
3407 case MSR_IA32_UCODE_REV:
3408 msr_info->data = vcpu->arch.microcode_version;
3409 break;
3410 case MSR_IA32_ARCH_CAPABILITIES:
3411 if (!msr_info->host_initiated &&
3412 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3413 return 1;
3414 msr_info->data = vcpu->arch.arch_capabilities;
3415 break;
3416 case MSR_IA32_PERF_CAPABILITIES:
3417 if (!msr_info->host_initiated &&
3418 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3419 return 1;
3420 msr_info->data = vcpu->arch.perf_capabilities;
3421 break;
3422 case MSR_IA32_POWER_CTL:
3423 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3424 break;
3425 case MSR_IA32_TSC: {
3426 /*
3427 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3428 * even when not intercepted. AMD manual doesn't explicitly
3429 * state this but appears to behave the same.
3430 *
3431 * On userspace reads and writes, however, we unconditionally
3432 * return L1's TSC value to ensure backwards-compatible
3433 * behavior for migration.
3434 */
3435 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3436 vcpu->arch.tsc_offset;
3437
3438 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3439 break;
3440 }
3441 case MSR_MTRRcap:
3442 case 0x200 ... 0x2ff:
3443 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3444 case 0xcd: /* fsb frequency */
3445 msr_info->data = 3;
3446 break;
3447 /*
3448 * MSR_EBC_FREQUENCY_ID
3449 * Conservative value valid for even the basic CPU models.
3450 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3451 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3452 * and 266MHz for model 3, or 4. Set Core Clock
3453 * Frequency to System Bus Frequency Ratio to 1 (bits
3454 * 31:24) even though these are only valid for CPU
3455 * models > 2, however guests may end up dividing or
3456 * multiplying by zero otherwise.
3457 */
3458 case MSR_EBC_FREQUENCY_ID:
3459 msr_info->data = 1 << 24;
3460 break;
3461 case MSR_IA32_APICBASE:
3462 msr_info->data = kvm_get_apic_base(vcpu);
3463 break;
3464 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3465 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3466 case MSR_IA32_TSCDEADLINE:
3467 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3468 break;
3469 case MSR_IA32_TSC_ADJUST:
3470 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3471 break;
3472 case MSR_IA32_MISC_ENABLE:
3473 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3474 break;
3475 case MSR_IA32_SMBASE:
3476 if (!msr_info->host_initiated)
3477 return 1;
3478 msr_info->data = vcpu->arch.smbase;
3479 break;
3480 case MSR_SMI_COUNT:
3481 msr_info->data = vcpu->arch.smi_count;
3482 break;
3483 case MSR_IA32_PERF_STATUS:
3484 /* TSC increment by tick */
3485 msr_info->data = 1000ULL;
3486 /* CPU multiplier */
3487 msr_info->data |= (((uint64_t)4ULL) << 40);
3488 break;
3489 case MSR_EFER:
3490 msr_info->data = vcpu->arch.efer;
3491 break;
3492 case MSR_KVM_WALL_CLOCK:
3493 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3494 return 1;
3495
3496 msr_info->data = vcpu->kvm->arch.wall_clock;
3497 break;
3498 case MSR_KVM_WALL_CLOCK_NEW:
3499 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3500 return 1;
3501
3502 msr_info->data = vcpu->kvm->arch.wall_clock;
3503 break;
3504 case MSR_KVM_SYSTEM_TIME:
3505 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3506 return 1;
3507
3508 msr_info->data = vcpu->arch.time;
3509 break;
3510 case MSR_KVM_SYSTEM_TIME_NEW:
3511 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3512 return 1;
3513
3514 msr_info->data = vcpu->arch.time;
3515 break;
3516 case MSR_KVM_ASYNC_PF_EN:
3517 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3518 return 1;
3519
3520 msr_info->data = vcpu->arch.apf.msr_en_val;
3521 break;
3522 case MSR_KVM_ASYNC_PF_INT:
3523 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3524 return 1;
3525
3526 msr_info->data = vcpu->arch.apf.msr_int_val;
3527 break;
3528 case MSR_KVM_ASYNC_PF_ACK:
3529 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3530 return 1;
3531
3532 msr_info->data = 0;
3533 break;
3534 case MSR_KVM_STEAL_TIME:
3535 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3536 return 1;
3537
3538 msr_info->data = vcpu->arch.st.msr_val;
3539 break;
3540 case MSR_KVM_PV_EOI_EN:
3541 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3542 return 1;
3543
3544 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3545 break;
3546 case MSR_KVM_POLL_CONTROL:
3547 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3548 return 1;
3549
3550 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3551 break;
3552 case MSR_IA32_P5_MC_ADDR:
3553 case MSR_IA32_P5_MC_TYPE:
3554 case MSR_IA32_MCG_CAP:
3555 case MSR_IA32_MCG_CTL:
3556 case MSR_IA32_MCG_STATUS:
3557 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3558 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3559 msr_info->host_initiated);
3560 case MSR_IA32_XSS:
3561 if (!msr_info->host_initiated &&
3562 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3563 return 1;
3564 msr_info->data = vcpu->arch.ia32_xss;
3565 break;
3566 case MSR_K7_CLK_CTL:
3567 /*
3568 * Provide expected ramp-up count for K7. All other
3569 * are set to zero, indicating minimum divisors for
3570 * every field.
3571 *
3572 * This prevents guest kernels on AMD host with CPU
3573 * type 6, model 8 and higher from exploding due to
3574 * the rdmsr failing.
3575 */
3576 msr_info->data = 0x20000000;
3577 break;
3578 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3579 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3580 case HV_X64_MSR_SYNDBG_OPTIONS:
3581 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3582 case HV_X64_MSR_CRASH_CTL:
3583 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3584 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3585 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3586 case HV_X64_MSR_TSC_EMULATION_STATUS:
3587 return kvm_hv_get_msr_common(vcpu,
3588 msr_info->index, &msr_info->data,
3589 msr_info->host_initiated);
3590 case MSR_IA32_BBL_CR_CTL3:
3591 /* This legacy MSR exists but isn't fully documented in current
3592 * silicon. It is however accessed by winxp in very narrow
3593 * scenarios where it sets bit #19, itself documented as
3594 * a "reserved" bit. Best effort attempt to source coherent
3595 * read data here should the balance of the register be
3596 * interpreted by the guest:
3597 *
3598 * L2 cache control register 3: 64GB range, 256KB size,
3599 * enabled, latency 0x1, configured
3600 */
3601 msr_info->data = 0xbe702111;
3602 break;
3603 case MSR_AMD64_OSVW_ID_LENGTH:
3604 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3605 return 1;
3606 msr_info->data = vcpu->arch.osvw.length;
3607 break;
3608 case MSR_AMD64_OSVW_STATUS:
3609 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3610 return 1;
3611 msr_info->data = vcpu->arch.osvw.status;
3612 break;
3613 case MSR_PLATFORM_INFO:
3614 if (!msr_info->host_initiated &&
3615 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3616 return 1;
3617 msr_info->data = vcpu->arch.msr_platform_info;
3618 break;
3619 case MSR_MISC_FEATURES_ENABLES:
3620 msr_info->data = vcpu->arch.msr_misc_features_enables;
3621 break;
3622 case MSR_K7_HWCR:
3623 msr_info->data = vcpu->arch.msr_hwcr;
3624 break;
3625 default:
3626 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3627 return kvm_pmu_get_msr(vcpu, msr_info);
3628 return KVM_MSR_RET_INVALID;
3629 }
3630 return 0;
3631 }
3632 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3633
3634 /*
3635 * Read or write a bunch of msrs. All parameters are kernel addresses.
3636 *
3637 * @return number of msrs set successfully.
3638 */
3639 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3640 struct kvm_msr_entry *entries,
3641 int (*do_msr)(struct kvm_vcpu *vcpu,
3642 unsigned index, u64 *data))
3643 {
3644 int i;
3645
3646 for (i = 0; i < msrs->nmsrs; ++i)
3647 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3648 break;
3649
3650 return i;
3651 }
3652
3653 /*
3654 * Read or write a bunch of msrs. Parameters are user addresses.
3655 *
3656 * @return number of msrs set successfully.
3657 */
3658 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3659 int (*do_msr)(struct kvm_vcpu *vcpu,
3660 unsigned index, u64 *data),
3661 int writeback)
3662 {
3663 struct kvm_msrs msrs;
3664 struct kvm_msr_entry *entries;
3665 int r, n;
3666 unsigned size;
3667
3668 r = -EFAULT;
3669 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3670 goto out;
3671
3672 r = -E2BIG;
3673 if (msrs.nmsrs >= MAX_IO_MSRS)
3674 goto out;
3675
3676 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3677 entries = memdup_user(user_msrs->entries, size);
3678 if (IS_ERR(entries)) {
3679 r = PTR_ERR(entries);
3680 goto out;
3681 }
3682
3683 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3684 if (r < 0)
3685 goto out_free;
3686
3687 r = -EFAULT;
3688 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3689 goto out_free;
3690
3691 r = n;
3692
3693 out_free:
3694 kfree(entries);
3695 out:
3696 return r;
3697 }
3698
3699 static inline bool kvm_can_mwait_in_guest(void)
3700 {
3701 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3702 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3703 boot_cpu_has(X86_FEATURE_ARAT);
3704 }
3705
3706 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
3707 struct kvm_cpuid2 __user *cpuid_arg)
3708 {
3709 struct kvm_cpuid2 cpuid;
3710 int r;
3711
3712 r = -EFAULT;
3713 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3714 return r;
3715
3716 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3717 if (r)
3718 return r;
3719
3720 r = -EFAULT;
3721 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3722 return r;
3723
3724 return 0;
3725 }
3726
3727 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3728 {
3729 int r = 0;
3730
3731 switch (ext) {
3732 case KVM_CAP_IRQCHIP:
3733 case KVM_CAP_HLT:
3734 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3735 case KVM_CAP_SET_TSS_ADDR:
3736 case KVM_CAP_EXT_CPUID:
3737 case KVM_CAP_EXT_EMUL_CPUID:
3738 case KVM_CAP_CLOCKSOURCE:
3739 case KVM_CAP_PIT:
3740 case KVM_CAP_NOP_IO_DELAY:
3741 case KVM_CAP_MP_STATE:
3742 case KVM_CAP_SYNC_MMU:
3743 case KVM_CAP_USER_NMI:
3744 case KVM_CAP_REINJECT_CONTROL:
3745 case KVM_CAP_IRQ_INJECT_STATUS:
3746 case KVM_CAP_IOEVENTFD:
3747 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3748 case KVM_CAP_PIT2:
3749 case KVM_CAP_PIT_STATE2:
3750 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3751 case KVM_CAP_XEN_HVM:
3752 case KVM_CAP_VCPU_EVENTS:
3753 case KVM_CAP_HYPERV:
3754 case KVM_CAP_HYPERV_VAPIC:
3755 case KVM_CAP_HYPERV_SPIN:
3756 case KVM_CAP_HYPERV_SYNIC:
3757 case KVM_CAP_HYPERV_SYNIC2:
3758 case KVM_CAP_HYPERV_VP_INDEX:
3759 case KVM_CAP_HYPERV_EVENTFD:
3760 case KVM_CAP_HYPERV_TLBFLUSH:
3761 case KVM_CAP_HYPERV_SEND_IPI:
3762 case KVM_CAP_HYPERV_CPUID:
3763 case KVM_CAP_SYS_HYPERV_CPUID:
3764 case KVM_CAP_PCI_SEGMENT:
3765 case KVM_CAP_DEBUGREGS:
3766 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3767 case KVM_CAP_XSAVE:
3768 case KVM_CAP_ASYNC_PF:
3769 case KVM_CAP_ASYNC_PF_INT:
3770 case KVM_CAP_GET_TSC_KHZ:
3771 case KVM_CAP_KVMCLOCK_CTRL:
3772 case KVM_CAP_READONLY_MEM:
3773 case KVM_CAP_HYPERV_TIME:
3774 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3775 case KVM_CAP_TSC_DEADLINE_TIMER:
3776 case KVM_CAP_DISABLE_QUIRKS:
3777 case KVM_CAP_SET_BOOT_CPU_ID:
3778 case KVM_CAP_SPLIT_IRQCHIP:
3779 case KVM_CAP_IMMEDIATE_EXIT:
3780 case KVM_CAP_PMU_EVENT_FILTER:
3781 case KVM_CAP_GET_MSR_FEATURES:
3782 case KVM_CAP_MSR_PLATFORM_INFO:
3783 case KVM_CAP_EXCEPTION_PAYLOAD:
3784 case KVM_CAP_SET_GUEST_DEBUG:
3785 case KVM_CAP_LAST_CPU:
3786 case KVM_CAP_X86_USER_SPACE_MSR:
3787 case KVM_CAP_X86_MSR_FILTER:
3788 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
3789 r = 1;
3790 break;
3791 case KVM_CAP_SYNC_REGS:
3792 r = KVM_SYNC_X86_VALID_FIELDS;
3793 break;
3794 case KVM_CAP_ADJUST_CLOCK:
3795 r = KVM_CLOCK_TSC_STABLE;
3796 break;
3797 case KVM_CAP_X86_DISABLE_EXITS:
3798 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3799 KVM_X86_DISABLE_EXITS_CSTATE;
3800 if(kvm_can_mwait_in_guest())
3801 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3802 break;
3803 case KVM_CAP_X86_SMM:
3804 /* SMBASE is usually relocated above 1M on modern chipsets,
3805 * and SMM handlers might indeed rely on 4G segment limits,
3806 * so do not report SMM to be available if real mode is
3807 * emulated via vm86 mode. Still, do not go to great lengths
3808 * to avoid userspace's usage of the feature, because it is a
3809 * fringe case that is not enabled except via specific settings
3810 * of the module parameters.
3811 */
3812 r = kvm_x86_ops.has_emulated_msr(kvm, MSR_IA32_SMBASE);
3813 break;
3814 case KVM_CAP_VAPIC:
3815 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3816 break;
3817 case KVM_CAP_NR_VCPUS:
3818 r = KVM_SOFT_MAX_VCPUS;
3819 break;
3820 case KVM_CAP_MAX_VCPUS:
3821 r = KVM_MAX_VCPUS;
3822 break;
3823 case KVM_CAP_MAX_VCPU_ID:
3824 r = KVM_MAX_VCPU_ID;
3825 break;
3826 case KVM_CAP_PV_MMU: /* obsolete */
3827 r = 0;
3828 break;
3829 case KVM_CAP_MCE:
3830 r = KVM_MAX_MCE_BANKS;
3831 break;
3832 case KVM_CAP_XCRS:
3833 r = boot_cpu_has(X86_FEATURE_XSAVE);
3834 break;
3835 case KVM_CAP_TSC_CONTROL:
3836 r = kvm_has_tsc_control;
3837 break;
3838 case KVM_CAP_X2APIC_API:
3839 r = KVM_X2APIC_API_VALID_FLAGS;
3840 break;
3841 case KVM_CAP_NESTED_STATE:
3842 r = kvm_x86_ops.nested_ops->get_state ?
3843 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3844 break;
3845 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3846 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3847 break;
3848 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3849 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3850 break;
3851 case KVM_CAP_SMALLER_MAXPHYADDR:
3852 r = (int) allow_smaller_maxphyaddr;
3853 break;
3854 case KVM_CAP_STEAL_TIME:
3855 r = sched_info_on();
3856 break;
3857 default:
3858 break;
3859 }
3860 return r;
3861
3862 }
3863
3864 long kvm_arch_dev_ioctl(struct file *filp,
3865 unsigned int ioctl, unsigned long arg)
3866 {
3867 void __user *argp = (void __user *)arg;
3868 long r;
3869
3870 switch (ioctl) {
3871 case KVM_GET_MSR_INDEX_LIST: {
3872 struct kvm_msr_list __user *user_msr_list = argp;
3873 struct kvm_msr_list msr_list;
3874 unsigned n;
3875
3876 r = -EFAULT;
3877 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3878 goto out;
3879 n = msr_list.nmsrs;
3880 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3881 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3882 goto out;
3883 r = -E2BIG;
3884 if (n < msr_list.nmsrs)
3885 goto out;
3886 r = -EFAULT;
3887 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3888 num_msrs_to_save * sizeof(u32)))
3889 goto out;
3890 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3891 &emulated_msrs,
3892 num_emulated_msrs * sizeof(u32)))
3893 goto out;
3894 r = 0;
3895 break;
3896 }
3897 case KVM_GET_SUPPORTED_CPUID:
3898 case KVM_GET_EMULATED_CPUID: {
3899 struct kvm_cpuid2 __user *cpuid_arg = argp;
3900 struct kvm_cpuid2 cpuid;
3901
3902 r = -EFAULT;
3903 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3904 goto out;
3905
3906 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3907 ioctl);
3908 if (r)
3909 goto out;
3910
3911 r = -EFAULT;
3912 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3913 goto out;
3914 r = 0;
3915 break;
3916 }
3917 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3918 r = -EFAULT;
3919 if (copy_to_user(argp, &kvm_mce_cap_supported,
3920 sizeof(kvm_mce_cap_supported)))
3921 goto out;
3922 r = 0;
3923 break;
3924 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3925 struct kvm_msr_list __user *user_msr_list = argp;
3926 struct kvm_msr_list msr_list;
3927 unsigned int n;
3928
3929 r = -EFAULT;
3930 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3931 goto out;
3932 n = msr_list.nmsrs;
3933 msr_list.nmsrs = num_msr_based_features;
3934 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3935 goto out;
3936 r = -E2BIG;
3937 if (n < msr_list.nmsrs)
3938 goto out;
3939 r = -EFAULT;
3940 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3941 num_msr_based_features * sizeof(u32)))
3942 goto out;
3943 r = 0;
3944 break;
3945 }
3946 case KVM_GET_MSRS:
3947 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3948 break;
3949 case KVM_GET_SUPPORTED_HV_CPUID:
3950 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
3951 break;
3952 default:
3953 r = -EINVAL;
3954 break;
3955 }
3956 out:
3957 return r;
3958 }
3959
3960 static void wbinvd_ipi(void *garbage)
3961 {
3962 wbinvd();
3963 }
3964
3965 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3966 {
3967 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3968 }
3969
3970 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3971 {
3972 /* Address WBINVD may be executed by guest */
3973 if (need_emulate_wbinvd(vcpu)) {
3974 if (kvm_x86_ops.has_wbinvd_exit())
3975 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3976 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3977 smp_call_function_single(vcpu->cpu,
3978 wbinvd_ipi, NULL, 1);
3979 }
3980
3981 kvm_x86_ops.vcpu_load(vcpu, cpu);
3982
3983 /* Save host pkru register if supported */
3984 vcpu->arch.host_pkru = read_pkru();
3985
3986 /* Apply any externally detected TSC adjustments (due to suspend) */
3987 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3988 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3989 vcpu->arch.tsc_offset_adjustment = 0;
3990 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3991 }
3992
3993 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3994 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3995 rdtsc() - vcpu->arch.last_host_tsc;
3996 if (tsc_delta < 0)
3997 mark_tsc_unstable("KVM discovered backwards TSC");
3998
3999 if (kvm_check_tsc_unstable()) {
4000 u64 offset = kvm_compute_tsc_offset(vcpu,
4001 vcpu->arch.last_guest_tsc);
4002 kvm_vcpu_write_tsc_offset(vcpu, offset);
4003 vcpu->arch.tsc_catchup = 1;
4004 }
4005
4006 if (kvm_lapic_hv_timer_in_use(vcpu))
4007 kvm_lapic_restart_hv_timer(vcpu);
4008
4009 /*
4010 * On a host with synchronized TSC, there is no need to update
4011 * kvmclock on vcpu->cpu migration
4012 */
4013 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4014 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4015 if (vcpu->cpu != cpu)
4016 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4017 vcpu->cpu = cpu;
4018 }
4019
4020 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4021 }
4022
4023 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4024 {
4025 struct kvm_host_map map;
4026 struct kvm_steal_time *st;
4027
4028 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4029 return;
4030
4031 if (vcpu->arch.st.preempted)
4032 return;
4033
4034 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
4035 &vcpu->arch.st.cache, true))
4036 return;
4037
4038 st = map.hva +
4039 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
4040
4041 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4042
4043 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
4044 }
4045
4046 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4047 {
4048 int idx;
4049
4050 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4051 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
4052
4053 /*
4054 * Disable page faults because we're in atomic context here.
4055 * kvm_write_guest_offset_cached() would call might_fault()
4056 * that relies on pagefault_disable() to tell if there's a
4057 * bug. NOTE: the write to guest memory may not go through if
4058 * during postcopy live migration or if there's heavy guest
4059 * paging.
4060 */
4061 pagefault_disable();
4062 /*
4063 * kvm_memslots() will be called by
4064 * kvm_write_guest_offset_cached() so take the srcu lock.
4065 */
4066 idx = srcu_read_lock(&vcpu->kvm->srcu);
4067 kvm_steal_time_set_preempted(vcpu);
4068 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4069 pagefault_enable();
4070 kvm_x86_ops.vcpu_put(vcpu);
4071 vcpu->arch.last_host_tsc = rdtsc();
4072 /*
4073 * If userspace has set any breakpoints or watchpoints, dr6 is restored
4074 * on every vmexit, but if not, we might have a stale dr6 from the
4075 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
4076 */
4077 set_debugreg(0, 6);
4078 }
4079
4080 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4081 struct kvm_lapic_state *s)
4082 {
4083 if (vcpu->arch.apicv_active)
4084 kvm_x86_ops.sync_pir_to_irr(vcpu);
4085
4086 return kvm_apic_get_state(vcpu, s);
4087 }
4088
4089 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4090 struct kvm_lapic_state *s)
4091 {
4092 int r;
4093
4094 r = kvm_apic_set_state(vcpu, s);
4095 if (r)
4096 return r;
4097 update_cr8_intercept(vcpu);
4098
4099 return 0;
4100 }
4101
4102 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4103 {
4104 /*
4105 * We can accept userspace's request for interrupt injection
4106 * as long as we have a place to store the interrupt number.
4107 * The actual injection will happen when the CPU is able to
4108 * deliver the interrupt.
4109 */
4110 if (kvm_cpu_has_extint(vcpu))
4111 return false;
4112
4113 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4114 return (!lapic_in_kernel(vcpu) ||
4115 kvm_apic_accept_pic_intr(vcpu));
4116 }
4117
4118 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4119 {
4120 return kvm_arch_interrupt_allowed(vcpu) &&
4121 kvm_cpu_accept_dm_intr(vcpu);
4122 }
4123
4124 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4125 struct kvm_interrupt *irq)
4126 {
4127 if (irq->irq >= KVM_NR_INTERRUPTS)
4128 return -EINVAL;
4129
4130 if (!irqchip_in_kernel(vcpu->kvm)) {
4131 kvm_queue_interrupt(vcpu, irq->irq, false);
4132 kvm_make_request(KVM_REQ_EVENT, vcpu);
4133 return 0;
4134 }
4135
4136 /*
4137 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4138 * fail for in-kernel 8259.
4139 */
4140 if (pic_in_kernel(vcpu->kvm))
4141 return -ENXIO;
4142
4143 if (vcpu->arch.pending_external_vector != -1)
4144 return -EEXIST;
4145
4146 vcpu->arch.pending_external_vector = irq->irq;
4147 kvm_make_request(KVM_REQ_EVENT, vcpu);
4148 return 0;
4149 }
4150
4151 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4152 {
4153 kvm_inject_nmi(vcpu);
4154
4155 return 0;
4156 }
4157
4158 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4159 {
4160 kvm_make_request(KVM_REQ_SMI, vcpu);
4161
4162 return 0;
4163 }
4164
4165 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4166 struct kvm_tpr_access_ctl *tac)
4167 {
4168 if (tac->flags)
4169 return -EINVAL;
4170 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4171 return 0;
4172 }
4173
4174 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4175 u64 mcg_cap)
4176 {
4177 int r;
4178 unsigned bank_num = mcg_cap & 0xff, bank;
4179
4180 r = -EINVAL;
4181 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4182 goto out;
4183 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4184 goto out;
4185 r = 0;
4186 vcpu->arch.mcg_cap = mcg_cap;
4187 /* Init IA32_MCG_CTL to all 1s */
4188 if (mcg_cap & MCG_CTL_P)
4189 vcpu->arch.mcg_ctl = ~(u64)0;
4190 /* Init IA32_MCi_CTL to all 1s */
4191 for (bank = 0; bank < bank_num; bank++)
4192 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4193
4194 kvm_x86_ops.setup_mce(vcpu);
4195 out:
4196 return r;
4197 }
4198
4199 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4200 struct kvm_x86_mce *mce)
4201 {
4202 u64 mcg_cap = vcpu->arch.mcg_cap;
4203 unsigned bank_num = mcg_cap & 0xff;
4204 u64 *banks = vcpu->arch.mce_banks;
4205
4206 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4207 return -EINVAL;
4208 /*
4209 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4210 * reporting is disabled
4211 */
4212 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4213 vcpu->arch.mcg_ctl != ~(u64)0)
4214 return 0;
4215 banks += 4 * mce->bank;
4216 /*
4217 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4218 * reporting is disabled for the bank
4219 */
4220 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4221 return 0;
4222 if (mce->status & MCI_STATUS_UC) {
4223 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4224 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4225 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4226 return 0;
4227 }
4228 if (banks[1] & MCI_STATUS_VAL)
4229 mce->status |= MCI_STATUS_OVER;
4230 banks[2] = mce->addr;
4231 banks[3] = mce->misc;
4232 vcpu->arch.mcg_status = mce->mcg_status;
4233 banks[1] = mce->status;
4234 kvm_queue_exception(vcpu, MC_VECTOR);
4235 } else if (!(banks[1] & MCI_STATUS_VAL)
4236 || !(banks[1] & MCI_STATUS_UC)) {
4237 if (banks[1] & MCI_STATUS_VAL)
4238 mce->status |= MCI_STATUS_OVER;
4239 banks[2] = mce->addr;
4240 banks[3] = mce->misc;
4241 banks[1] = mce->status;
4242 } else
4243 banks[1] |= MCI_STATUS_OVER;
4244 return 0;
4245 }
4246
4247 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4248 struct kvm_vcpu_events *events)
4249 {
4250 process_nmi(vcpu);
4251
4252 if (kvm_check_request(KVM_REQ_SMI, vcpu))
4253 process_smi(vcpu);
4254
4255 /*
4256 * In guest mode, payload delivery should be deferred,
4257 * so that the L1 hypervisor can intercept #PF before
4258 * CR2 is modified (or intercept #DB before DR6 is
4259 * modified under nVMX). Unless the per-VM capability,
4260 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4261 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4262 * opportunistically defer the exception payload, deliver it if the
4263 * capability hasn't been requested before processing a
4264 * KVM_GET_VCPU_EVENTS.
4265 */
4266 if (!vcpu->kvm->arch.exception_payload_enabled &&
4267 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4268 kvm_deliver_exception_payload(vcpu);
4269
4270 /*
4271 * The API doesn't provide the instruction length for software
4272 * exceptions, so don't report them. As long as the guest RIP
4273 * isn't advanced, we should expect to encounter the exception
4274 * again.
4275 */
4276 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4277 events->exception.injected = 0;
4278 events->exception.pending = 0;
4279 } else {
4280 events->exception.injected = vcpu->arch.exception.injected;
4281 events->exception.pending = vcpu->arch.exception.pending;
4282 /*
4283 * For ABI compatibility, deliberately conflate
4284 * pending and injected exceptions when
4285 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4286 */
4287 if (!vcpu->kvm->arch.exception_payload_enabled)
4288 events->exception.injected |=
4289 vcpu->arch.exception.pending;
4290 }
4291 events->exception.nr = vcpu->arch.exception.nr;
4292 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4293 events->exception.error_code = vcpu->arch.exception.error_code;
4294 events->exception_has_payload = vcpu->arch.exception.has_payload;
4295 events->exception_payload = vcpu->arch.exception.payload;
4296
4297 events->interrupt.injected =
4298 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4299 events->interrupt.nr = vcpu->arch.interrupt.nr;
4300 events->interrupt.soft = 0;
4301 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4302
4303 events->nmi.injected = vcpu->arch.nmi_injected;
4304 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4305 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4306 events->nmi.pad = 0;
4307
4308 events->sipi_vector = 0; /* never valid when reporting to user space */
4309
4310 events->smi.smm = is_smm(vcpu);
4311 events->smi.pending = vcpu->arch.smi_pending;
4312 events->smi.smm_inside_nmi =
4313 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4314 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4315
4316 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4317 | KVM_VCPUEVENT_VALID_SHADOW
4318 | KVM_VCPUEVENT_VALID_SMM);
4319 if (vcpu->kvm->arch.exception_payload_enabled)
4320 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4321
4322 memset(&events->reserved, 0, sizeof(events->reserved));
4323 }
4324
4325 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4326
4327 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4328 struct kvm_vcpu_events *events)
4329 {
4330 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4331 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4332 | KVM_VCPUEVENT_VALID_SHADOW
4333 | KVM_VCPUEVENT_VALID_SMM
4334 | KVM_VCPUEVENT_VALID_PAYLOAD))
4335 return -EINVAL;
4336
4337 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4338 if (!vcpu->kvm->arch.exception_payload_enabled)
4339 return -EINVAL;
4340 if (events->exception.pending)
4341 events->exception.injected = 0;
4342 else
4343 events->exception_has_payload = 0;
4344 } else {
4345 events->exception.pending = 0;
4346 events->exception_has_payload = 0;
4347 }
4348
4349 if ((events->exception.injected || events->exception.pending) &&
4350 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4351 return -EINVAL;
4352
4353 /* INITs are latched while in SMM */
4354 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4355 (events->smi.smm || events->smi.pending) &&
4356 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4357 return -EINVAL;
4358
4359 process_nmi(vcpu);
4360 vcpu->arch.exception.injected = events->exception.injected;
4361 vcpu->arch.exception.pending = events->exception.pending;
4362 vcpu->arch.exception.nr = events->exception.nr;
4363 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4364 vcpu->arch.exception.error_code = events->exception.error_code;
4365 vcpu->arch.exception.has_payload = events->exception_has_payload;
4366 vcpu->arch.exception.payload = events->exception_payload;
4367
4368 vcpu->arch.interrupt.injected = events->interrupt.injected;
4369 vcpu->arch.interrupt.nr = events->interrupt.nr;
4370 vcpu->arch.interrupt.soft = events->interrupt.soft;
4371 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4372 kvm_x86_ops.set_interrupt_shadow(vcpu,
4373 events->interrupt.shadow);
4374
4375 vcpu->arch.nmi_injected = events->nmi.injected;
4376 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4377 vcpu->arch.nmi_pending = events->nmi.pending;
4378 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4379
4380 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4381 lapic_in_kernel(vcpu))
4382 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4383
4384 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4385 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4386 if (events->smi.smm)
4387 vcpu->arch.hflags |= HF_SMM_MASK;
4388 else
4389 vcpu->arch.hflags &= ~HF_SMM_MASK;
4390 kvm_smm_changed(vcpu);
4391 }
4392
4393 vcpu->arch.smi_pending = events->smi.pending;
4394
4395 if (events->smi.smm) {
4396 if (events->smi.smm_inside_nmi)
4397 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4398 else
4399 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4400 }
4401
4402 if (lapic_in_kernel(vcpu)) {
4403 if (events->smi.latched_init)
4404 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4405 else
4406 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4407 }
4408 }
4409
4410 kvm_make_request(KVM_REQ_EVENT, vcpu);
4411
4412 return 0;
4413 }
4414
4415 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4416 struct kvm_debugregs *dbgregs)
4417 {
4418 unsigned long val;
4419
4420 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4421 kvm_get_dr(vcpu, 6, &val);
4422 dbgregs->dr6 = val;
4423 dbgregs->dr7 = vcpu->arch.dr7;
4424 dbgregs->flags = 0;
4425 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4426 }
4427
4428 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4429 struct kvm_debugregs *dbgregs)
4430 {
4431 if (dbgregs->flags)
4432 return -EINVAL;
4433
4434 if (dbgregs->dr6 & ~0xffffffffull)
4435 return -EINVAL;
4436 if (dbgregs->dr7 & ~0xffffffffull)
4437 return -EINVAL;
4438
4439 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4440 kvm_update_dr0123(vcpu);
4441 vcpu->arch.dr6 = dbgregs->dr6;
4442 vcpu->arch.dr7 = dbgregs->dr7;
4443 kvm_update_dr7(vcpu);
4444
4445 return 0;
4446 }
4447
4448 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4449
4450 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4451 {
4452 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4453 u64 xstate_bv = xsave->header.xfeatures;
4454 u64 valid;
4455
4456 /*
4457 * Copy legacy XSAVE area, to avoid complications with CPUID
4458 * leaves 0 and 1 in the loop below.
4459 */
4460 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4461
4462 /* Set XSTATE_BV */
4463 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4464 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4465
4466 /*
4467 * Copy each region from the possibly compacted offset to the
4468 * non-compacted offset.
4469 */
4470 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4471 while (valid) {
4472 u64 xfeature_mask = valid & -valid;
4473 int xfeature_nr = fls64(xfeature_mask) - 1;
4474 void *src = get_xsave_addr(xsave, xfeature_nr);
4475
4476 if (src) {
4477 u32 size, offset, ecx, edx;
4478 cpuid_count(XSTATE_CPUID, xfeature_nr,
4479 &size, &offset, &ecx, &edx);
4480 if (xfeature_nr == XFEATURE_PKRU)
4481 memcpy(dest + offset, &vcpu->arch.pkru,
4482 sizeof(vcpu->arch.pkru));
4483 else
4484 memcpy(dest + offset, src, size);
4485
4486 }
4487
4488 valid -= xfeature_mask;
4489 }
4490 }
4491
4492 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4493 {
4494 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4495 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4496 u64 valid;
4497
4498 /*
4499 * Copy legacy XSAVE area, to avoid complications with CPUID
4500 * leaves 0 and 1 in the loop below.
4501 */
4502 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4503
4504 /* Set XSTATE_BV and possibly XCOMP_BV. */
4505 xsave->header.xfeatures = xstate_bv;
4506 if (boot_cpu_has(X86_FEATURE_XSAVES))
4507 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4508
4509 /*
4510 * Copy each region from the non-compacted offset to the
4511 * possibly compacted offset.
4512 */
4513 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4514 while (valid) {
4515 u64 xfeature_mask = valid & -valid;
4516 int xfeature_nr = fls64(xfeature_mask) - 1;
4517 void *dest = get_xsave_addr(xsave, xfeature_nr);
4518
4519 if (dest) {
4520 u32 size, offset, ecx, edx;
4521 cpuid_count(XSTATE_CPUID, xfeature_nr,
4522 &size, &offset, &ecx, &edx);
4523 if (xfeature_nr == XFEATURE_PKRU)
4524 memcpy(&vcpu->arch.pkru, src + offset,
4525 sizeof(vcpu->arch.pkru));
4526 else
4527 memcpy(dest, src + offset, size);
4528 }
4529
4530 valid -= xfeature_mask;
4531 }
4532 }
4533
4534 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4535 struct kvm_xsave *guest_xsave)
4536 {
4537 if (!vcpu->arch.guest_fpu)
4538 return;
4539
4540 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4541 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4542 fill_xsave((u8 *) guest_xsave->region, vcpu);
4543 } else {
4544 memcpy(guest_xsave->region,
4545 &vcpu->arch.guest_fpu->state.fxsave,
4546 sizeof(struct fxregs_state));
4547 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4548 XFEATURE_MASK_FPSSE;
4549 }
4550 }
4551
4552 #define XSAVE_MXCSR_OFFSET 24
4553
4554 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4555 struct kvm_xsave *guest_xsave)
4556 {
4557 u64 xstate_bv;
4558 u32 mxcsr;
4559
4560 if (!vcpu->arch.guest_fpu)
4561 return 0;
4562
4563 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4564 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4565
4566 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4567 /*
4568 * Here we allow setting states that are not present in
4569 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4570 * with old userspace.
4571 */
4572 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4573 return -EINVAL;
4574 load_xsave(vcpu, (u8 *)guest_xsave->region);
4575 } else {
4576 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4577 mxcsr & ~mxcsr_feature_mask)
4578 return -EINVAL;
4579 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4580 guest_xsave->region, sizeof(struct fxregs_state));
4581 }
4582 return 0;
4583 }
4584
4585 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4586 struct kvm_xcrs *guest_xcrs)
4587 {
4588 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4589 guest_xcrs->nr_xcrs = 0;
4590 return;
4591 }
4592
4593 guest_xcrs->nr_xcrs = 1;
4594 guest_xcrs->flags = 0;
4595 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4596 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4597 }
4598
4599 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4600 struct kvm_xcrs *guest_xcrs)
4601 {
4602 int i, r = 0;
4603
4604 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4605 return -EINVAL;
4606
4607 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4608 return -EINVAL;
4609
4610 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4611 /* Only support XCR0 currently */
4612 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4613 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4614 guest_xcrs->xcrs[i].value);
4615 break;
4616 }
4617 if (r)
4618 r = -EINVAL;
4619 return r;
4620 }
4621
4622 /*
4623 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4624 * stopped by the hypervisor. This function will be called from the host only.
4625 * EINVAL is returned when the host attempts to set the flag for a guest that
4626 * does not support pv clocks.
4627 */
4628 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4629 {
4630 if (!vcpu->arch.pv_time_enabled)
4631 return -EINVAL;
4632 vcpu->arch.pvclock_set_guest_stopped_request = true;
4633 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4634 return 0;
4635 }
4636
4637 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4638 struct kvm_enable_cap *cap)
4639 {
4640 int r;
4641 uint16_t vmcs_version;
4642 void __user *user_ptr;
4643
4644 if (cap->flags)
4645 return -EINVAL;
4646
4647 switch (cap->cap) {
4648 case KVM_CAP_HYPERV_SYNIC2:
4649 if (cap->args[0])
4650 return -EINVAL;
4651 fallthrough;
4652
4653 case KVM_CAP_HYPERV_SYNIC:
4654 if (!irqchip_in_kernel(vcpu->kvm))
4655 return -EINVAL;
4656 return kvm_hv_activate_synic(vcpu, cap->cap ==
4657 KVM_CAP_HYPERV_SYNIC2);
4658 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4659 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4660 return -ENOTTY;
4661 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4662 if (!r) {
4663 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4664 if (copy_to_user(user_ptr, &vmcs_version,
4665 sizeof(vmcs_version)))
4666 r = -EFAULT;
4667 }
4668 return r;
4669 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4670 if (!kvm_x86_ops.enable_direct_tlbflush)
4671 return -ENOTTY;
4672
4673 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4674
4675 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4676 vcpu->arch.pv_cpuid.enforce = cap->args[0];
4677 if (vcpu->arch.pv_cpuid.enforce)
4678 kvm_update_pv_runtime(vcpu);
4679
4680 return 0;
4681
4682 default:
4683 return -EINVAL;
4684 }
4685 }
4686
4687 long kvm_arch_vcpu_ioctl(struct file *filp,
4688 unsigned int ioctl, unsigned long arg)
4689 {
4690 struct kvm_vcpu *vcpu = filp->private_data;
4691 void __user *argp = (void __user *)arg;
4692 int r;
4693 union {
4694 struct kvm_lapic_state *lapic;
4695 struct kvm_xsave *xsave;
4696 struct kvm_xcrs *xcrs;
4697 void *buffer;
4698 } u;
4699
4700 vcpu_load(vcpu);
4701
4702 u.buffer = NULL;
4703 switch (ioctl) {
4704 case KVM_GET_LAPIC: {
4705 r = -EINVAL;
4706 if (!lapic_in_kernel(vcpu))
4707 goto out;
4708 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4709 GFP_KERNEL_ACCOUNT);
4710
4711 r = -ENOMEM;
4712 if (!u.lapic)
4713 goto out;
4714 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4715 if (r)
4716 goto out;
4717 r = -EFAULT;
4718 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4719 goto out;
4720 r = 0;
4721 break;
4722 }
4723 case KVM_SET_LAPIC: {
4724 r = -EINVAL;
4725 if (!lapic_in_kernel(vcpu))
4726 goto out;
4727 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4728 if (IS_ERR(u.lapic)) {
4729 r = PTR_ERR(u.lapic);
4730 goto out_nofree;
4731 }
4732
4733 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4734 break;
4735 }
4736 case KVM_INTERRUPT: {
4737 struct kvm_interrupt irq;
4738
4739 r = -EFAULT;
4740 if (copy_from_user(&irq, argp, sizeof(irq)))
4741 goto out;
4742 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4743 break;
4744 }
4745 case KVM_NMI: {
4746 r = kvm_vcpu_ioctl_nmi(vcpu);
4747 break;
4748 }
4749 case KVM_SMI: {
4750 r = kvm_vcpu_ioctl_smi(vcpu);
4751 break;
4752 }
4753 case KVM_SET_CPUID: {
4754 struct kvm_cpuid __user *cpuid_arg = argp;
4755 struct kvm_cpuid cpuid;
4756
4757 r = -EFAULT;
4758 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4759 goto out;
4760 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4761 break;
4762 }
4763 case KVM_SET_CPUID2: {
4764 struct kvm_cpuid2 __user *cpuid_arg = argp;
4765 struct kvm_cpuid2 cpuid;
4766
4767 r = -EFAULT;
4768 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4769 goto out;
4770 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4771 cpuid_arg->entries);
4772 break;
4773 }
4774 case KVM_GET_CPUID2: {
4775 struct kvm_cpuid2 __user *cpuid_arg = argp;
4776 struct kvm_cpuid2 cpuid;
4777
4778 r = -EFAULT;
4779 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4780 goto out;
4781 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4782 cpuid_arg->entries);
4783 if (r)
4784 goto out;
4785 r = -EFAULT;
4786 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4787 goto out;
4788 r = 0;
4789 break;
4790 }
4791 case KVM_GET_MSRS: {
4792 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4793 r = msr_io(vcpu, argp, do_get_msr, 1);
4794 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4795 break;
4796 }
4797 case KVM_SET_MSRS: {
4798 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4799 r = msr_io(vcpu, argp, do_set_msr, 0);
4800 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4801 break;
4802 }
4803 case KVM_TPR_ACCESS_REPORTING: {
4804 struct kvm_tpr_access_ctl tac;
4805
4806 r = -EFAULT;
4807 if (copy_from_user(&tac, argp, sizeof(tac)))
4808 goto out;
4809 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4810 if (r)
4811 goto out;
4812 r = -EFAULT;
4813 if (copy_to_user(argp, &tac, sizeof(tac)))
4814 goto out;
4815 r = 0;
4816 break;
4817 };
4818 case KVM_SET_VAPIC_ADDR: {
4819 struct kvm_vapic_addr va;
4820 int idx;
4821
4822 r = -EINVAL;
4823 if (!lapic_in_kernel(vcpu))
4824 goto out;
4825 r = -EFAULT;
4826 if (copy_from_user(&va, argp, sizeof(va)))
4827 goto out;
4828 idx = srcu_read_lock(&vcpu->kvm->srcu);
4829 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4830 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4831 break;
4832 }
4833 case KVM_X86_SETUP_MCE: {
4834 u64 mcg_cap;
4835
4836 r = -EFAULT;
4837 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4838 goto out;
4839 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4840 break;
4841 }
4842 case KVM_X86_SET_MCE: {
4843 struct kvm_x86_mce mce;
4844
4845 r = -EFAULT;
4846 if (copy_from_user(&mce, argp, sizeof(mce)))
4847 goto out;
4848 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4849 break;
4850 }
4851 case KVM_GET_VCPU_EVENTS: {
4852 struct kvm_vcpu_events events;
4853
4854 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4855
4856 r = -EFAULT;
4857 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4858 break;
4859 r = 0;
4860 break;
4861 }
4862 case KVM_SET_VCPU_EVENTS: {
4863 struct kvm_vcpu_events events;
4864
4865 r = -EFAULT;
4866 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4867 break;
4868
4869 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4870 break;
4871 }
4872 case KVM_GET_DEBUGREGS: {
4873 struct kvm_debugregs dbgregs;
4874
4875 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4876
4877 r = -EFAULT;
4878 if (copy_to_user(argp, &dbgregs,
4879 sizeof(struct kvm_debugregs)))
4880 break;
4881 r = 0;
4882 break;
4883 }
4884 case KVM_SET_DEBUGREGS: {
4885 struct kvm_debugregs dbgregs;
4886
4887 r = -EFAULT;
4888 if (copy_from_user(&dbgregs, argp,
4889 sizeof(struct kvm_debugregs)))
4890 break;
4891
4892 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4893 break;
4894 }
4895 case KVM_GET_XSAVE: {
4896 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4897 r = -ENOMEM;
4898 if (!u.xsave)
4899 break;
4900
4901 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4902
4903 r = -EFAULT;
4904 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4905 break;
4906 r = 0;
4907 break;
4908 }
4909 case KVM_SET_XSAVE: {
4910 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4911 if (IS_ERR(u.xsave)) {
4912 r = PTR_ERR(u.xsave);
4913 goto out_nofree;
4914 }
4915
4916 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4917 break;
4918 }
4919 case KVM_GET_XCRS: {
4920 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4921 r = -ENOMEM;
4922 if (!u.xcrs)
4923 break;
4924
4925 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4926
4927 r = -EFAULT;
4928 if (copy_to_user(argp, u.xcrs,
4929 sizeof(struct kvm_xcrs)))
4930 break;
4931 r = 0;
4932 break;
4933 }
4934 case KVM_SET_XCRS: {
4935 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4936 if (IS_ERR(u.xcrs)) {
4937 r = PTR_ERR(u.xcrs);
4938 goto out_nofree;
4939 }
4940
4941 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4942 break;
4943 }
4944 case KVM_SET_TSC_KHZ: {
4945 u32 user_tsc_khz;
4946
4947 r = -EINVAL;
4948 user_tsc_khz = (u32)arg;
4949
4950 if (kvm_has_tsc_control &&
4951 user_tsc_khz >= kvm_max_guest_tsc_khz)
4952 goto out;
4953
4954 if (user_tsc_khz == 0)
4955 user_tsc_khz = tsc_khz;
4956
4957 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4958 r = 0;
4959
4960 goto out;
4961 }
4962 case KVM_GET_TSC_KHZ: {
4963 r = vcpu->arch.virtual_tsc_khz;
4964 goto out;
4965 }
4966 case KVM_KVMCLOCK_CTRL: {
4967 r = kvm_set_guest_paused(vcpu);
4968 goto out;
4969 }
4970 case KVM_ENABLE_CAP: {
4971 struct kvm_enable_cap cap;
4972
4973 r = -EFAULT;
4974 if (copy_from_user(&cap, argp, sizeof(cap)))
4975 goto out;
4976 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4977 break;
4978 }
4979 case KVM_GET_NESTED_STATE: {
4980 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4981 u32 user_data_size;
4982
4983 r = -EINVAL;
4984 if (!kvm_x86_ops.nested_ops->get_state)
4985 break;
4986
4987 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4988 r = -EFAULT;
4989 if (get_user(user_data_size, &user_kvm_nested_state->size))
4990 break;
4991
4992 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4993 user_data_size);
4994 if (r < 0)
4995 break;
4996
4997 if (r > user_data_size) {
4998 if (put_user(r, &user_kvm_nested_state->size))
4999 r = -EFAULT;
5000 else
5001 r = -E2BIG;
5002 break;
5003 }
5004
5005 r = 0;
5006 break;
5007 }
5008 case KVM_SET_NESTED_STATE: {
5009 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5010 struct kvm_nested_state kvm_state;
5011 int idx;
5012
5013 r = -EINVAL;
5014 if (!kvm_x86_ops.nested_ops->set_state)
5015 break;
5016
5017 r = -EFAULT;
5018 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5019 break;
5020
5021 r = -EINVAL;
5022 if (kvm_state.size < sizeof(kvm_state))
5023 break;
5024
5025 if (kvm_state.flags &
5026 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5027 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5028 | KVM_STATE_NESTED_GIF_SET))
5029 break;
5030
5031 /* nested_run_pending implies guest_mode. */
5032 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5033 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5034 break;
5035
5036 idx = srcu_read_lock(&vcpu->kvm->srcu);
5037 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5038 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5039 break;
5040 }
5041 case KVM_GET_SUPPORTED_HV_CPUID:
5042 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5043 break;
5044 default:
5045 r = -EINVAL;
5046 }
5047 out:
5048 kfree(u.buffer);
5049 out_nofree:
5050 vcpu_put(vcpu);
5051 return r;
5052 }
5053
5054 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5055 {
5056 return VM_FAULT_SIGBUS;
5057 }
5058
5059 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5060 {
5061 int ret;
5062
5063 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5064 return -EINVAL;
5065 ret = kvm_x86_ops.set_tss_addr(kvm, addr);
5066 return ret;
5067 }
5068
5069 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5070 u64 ident_addr)
5071 {
5072 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
5073 }
5074
5075 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5076 unsigned long kvm_nr_mmu_pages)
5077 {
5078 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5079 return -EINVAL;
5080
5081 mutex_lock(&kvm->slots_lock);
5082
5083 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5084 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5085
5086 mutex_unlock(&kvm->slots_lock);
5087 return 0;
5088 }
5089
5090 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5091 {
5092 return kvm->arch.n_max_mmu_pages;
5093 }
5094
5095 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5096 {
5097 struct kvm_pic *pic = kvm->arch.vpic;
5098 int r;
5099
5100 r = 0;
5101 switch (chip->chip_id) {
5102 case KVM_IRQCHIP_PIC_MASTER:
5103 memcpy(&chip->chip.pic, &pic->pics[0],
5104 sizeof(struct kvm_pic_state));
5105 break;
5106 case KVM_IRQCHIP_PIC_SLAVE:
5107 memcpy(&chip->chip.pic, &pic->pics[1],
5108 sizeof(struct kvm_pic_state));
5109 break;
5110 case KVM_IRQCHIP_IOAPIC:
5111 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5112 break;
5113 default:
5114 r = -EINVAL;
5115 break;
5116 }
5117 return r;
5118 }
5119
5120 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5121 {
5122 struct kvm_pic *pic = kvm->arch.vpic;
5123 int r;
5124
5125 r = 0;
5126 switch (chip->chip_id) {
5127 case KVM_IRQCHIP_PIC_MASTER:
5128 spin_lock(&pic->lock);
5129 memcpy(&pic->pics[0], &chip->chip.pic,
5130 sizeof(struct kvm_pic_state));
5131 spin_unlock(&pic->lock);
5132 break;
5133 case KVM_IRQCHIP_PIC_SLAVE:
5134 spin_lock(&pic->lock);
5135 memcpy(&pic->pics[1], &chip->chip.pic,
5136 sizeof(struct kvm_pic_state));
5137 spin_unlock(&pic->lock);
5138 break;
5139 case KVM_IRQCHIP_IOAPIC:
5140 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5141 break;
5142 default:
5143 r = -EINVAL;
5144 break;
5145 }
5146 kvm_pic_update_irq(pic);
5147 return r;
5148 }
5149
5150 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5151 {
5152 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5153
5154 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5155
5156 mutex_lock(&kps->lock);
5157 memcpy(ps, &kps->channels, sizeof(*ps));
5158 mutex_unlock(&kps->lock);
5159 return 0;
5160 }
5161
5162 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5163 {
5164 int i;
5165 struct kvm_pit *pit = kvm->arch.vpit;
5166
5167 mutex_lock(&pit->pit_state.lock);
5168 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5169 for (i = 0; i < 3; i++)
5170 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5171 mutex_unlock(&pit->pit_state.lock);
5172 return 0;
5173 }
5174
5175 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5176 {
5177 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5178 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5179 sizeof(ps->channels));
5180 ps->flags = kvm->arch.vpit->pit_state.flags;
5181 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5182 memset(&ps->reserved, 0, sizeof(ps->reserved));
5183 return 0;
5184 }
5185
5186 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5187 {
5188 int start = 0;
5189 int i;
5190 u32 prev_legacy, cur_legacy;
5191 struct kvm_pit *pit = kvm->arch.vpit;
5192
5193 mutex_lock(&pit->pit_state.lock);
5194 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5195 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5196 if (!prev_legacy && cur_legacy)
5197 start = 1;
5198 memcpy(&pit->pit_state.channels, &ps->channels,
5199 sizeof(pit->pit_state.channels));
5200 pit->pit_state.flags = ps->flags;
5201 for (i = 0; i < 3; i++)
5202 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5203 start && i == 0);
5204 mutex_unlock(&pit->pit_state.lock);
5205 return 0;
5206 }
5207
5208 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5209 struct kvm_reinject_control *control)
5210 {
5211 struct kvm_pit *pit = kvm->arch.vpit;
5212
5213 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5214 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5215 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5216 */
5217 mutex_lock(&pit->pit_state.lock);
5218 kvm_pit_set_reinject(pit, control->pit_reinject);
5219 mutex_unlock(&pit->pit_state.lock);
5220
5221 return 0;
5222 }
5223
5224 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5225 {
5226 /*
5227 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
5228 */
5229 if (kvm_x86_ops.flush_log_dirty)
5230 kvm_x86_ops.flush_log_dirty(kvm);
5231 }
5232
5233 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5234 bool line_status)
5235 {
5236 if (!irqchip_in_kernel(kvm))
5237 return -ENXIO;
5238
5239 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5240 irq_event->irq, irq_event->level,
5241 line_status);
5242 return 0;
5243 }
5244
5245 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5246 struct kvm_enable_cap *cap)
5247 {
5248 int r;
5249
5250 if (cap->flags)
5251 return -EINVAL;
5252
5253 switch (cap->cap) {
5254 case KVM_CAP_DISABLE_QUIRKS:
5255 kvm->arch.disabled_quirks = cap->args[0];
5256 r = 0;
5257 break;
5258 case KVM_CAP_SPLIT_IRQCHIP: {
5259 mutex_lock(&kvm->lock);
5260 r = -EINVAL;
5261 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5262 goto split_irqchip_unlock;
5263 r = -EEXIST;
5264 if (irqchip_in_kernel(kvm))
5265 goto split_irqchip_unlock;
5266 if (kvm->created_vcpus)
5267 goto split_irqchip_unlock;
5268 r = kvm_setup_empty_irq_routing(kvm);
5269 if (r)
5270 goto split_irqchip_unlock;
5271 /* Pairs with irqchip_in_kernel. */
5272 smp_wmb();
5273 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5274 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5275 r = 0;
5276 split_irqchip_unlock:
5277 mutex_unlock(&kvm->lock);
5278 break;
5279 }
5280 case KVM_CAP_X2APIC_API:
5281 r = -EINVAL;
5282 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5283 break;
5284
5285 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5286 kvm->arch.x2apic_format = true;
5287 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5288 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5289
5290 r = 0;
5291 break;
5292 case KVM_CAP_X86_DISABLE_EXITS:
5293 r = -EINVAL;
5294 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5295 break;
5296
5297 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5298 kvm_can_mwait_in_guest())
5299 kvm->arch.mwait_in_guest = true;
5300 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5301 kvm->arch.hlt_in_guest = true;
5302 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5303 kvm->arch.pause_in_guest = true;
5304 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5305 kvm->arch.cstate_in_guest = true;
5306 r = 0;
5307 break;
5308 case KVM_CAP_MSR_PLATFORM_INFO:
5309 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5310 r = 0;
5311 break;
5312 case KVM_CAP_EXCEPTION_PAYLOAD:
5313 kvm->arch.exception_payload_enabled = cap->args[0];
5314 r = 0;
5315 break;
5316 case KVM_CAP_X86_USER_SPACE_MSR:
5317 kvm->arch.user_space_msr_mask = cap->args[0];
5318 r = 0;
5319 break;
5320 default:
5321 r = -EINVAL;
5322 break;
5323 }
5324 return r;
5325 }
5326
5327 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
5328 {
5329 struct kvm_x86_msr_filter *msr_filter;
5330
5331 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
5332 if (!msr_filter)
5333 return NULL;
5334
5335 msr_filter->default_allow = default_allow;
5336 return msr_filter;
5337 }
5338
5339 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
5340 {
5341 u32 i;
5342
5343 if (!msr_filter)
5344 return;
5345
5346 for (i = 0; i < msr_filter->count; i++)
5347 kfree(msr_filter->ranges[i].bitmap);
5348
5349 kfree(msr_filter);
5350 }
5351
5352 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
5353 struct kvm_msr_filter_range *user_range)
5354 {
5355 struct msr_bitmap_range range;
5356 unsigned long *bitmap = NULL;
5357 size_t bitmap_size;
5358 int r;
5359
5360 if (!user_range->nmsrs)
5361 return 0;
5362
5363 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5364 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5365 return -EINVAL;
5366
5367 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5368 if (IS_ERR(bitmap))
5369 return PTR_ERR(bitmap);
5370
5371 range = (struct msr_bitmap_range) {
5372 .flags = user_range->flags,
5373 .base = user_range->base,
5374 .nmsrs = user_range->nmsrs,
5375 .bitmap = bitmap,
5376 };
5377
5378 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5379 r = -EINVAL;
5380 goto err;
5381 }
5382
5383 if (!range.flags) {
5384 r = -EINVAL;
5385 goto err;
5386 }
5387
5388 /* Everything ok, add this range identifier. */
5389 msr_filter->ranges[msr_filter->count] = range;
5390 msr_filter->count++;
5391
5392 return 0;
5393 err:
5394 kfree(bitmap);
5395 return r;
5396 }
5397
5398 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5399 {
5400 struct kvm_msr_filter __user *user_msr_filter = argp;
5401 struct kvm_x86_msr_filter *new_filter, *old_filter;
5402 struct kvm_msr_filter filter;
5403 bool default_allow;
5404 bool empty = true;
5405 int r = 0;
5406 u32 i;
5407
5408 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5409 return -EFAULT;
5410
5411 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5412 empty &= !filter.ranges[i].nmsrs;
5413
5414 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5415 if (empty && !default_allow)
5416 return -EINVAL;
5417
5418 new_filter = kvm_alloc_msr_filter(default_allow);
5419 if (!new_filter)
5420 return -ENOMEM;
5421
5422 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5423 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]);
5424 if (r) {
5425 kvm_free_msr_filter(new_filter);
5426 return r;
5427 }
5428 }
5429
5430 mutex_lock(&kvm->lock);
5431
5432 /* The per-VM filter is protected by kvm->lock... */
5433 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1);
5434
5435 rcu_assign_pointer(kvm->arch.msr_filter, new_filter);
5436 synchronize_srcu(&kvm->srcu);
5437
5438 kvm_free_msr_filter(old_filter);
5439
5440 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5441 mutex_unlock(&kvm->lock);
5442
5443 return 0;
5444 }
5445
5446 long kvm_arch_vm_ioctl(struct file *filp,
5447 unsigned int ioctl, unsigned long arg)
5448 {
5449 struct kvm *kvm = filp->private_data;
5450 void __user *argp = (void __user *)arg;
5451 int r = -ENOTTY;
5452 /*
5453 * This union makes it completely explicit to gcc-3.x
5454 * that these two variables' stack usage should be
5455 * combined, not added together.
5456 */
5457 union {
5458 struct kvm_pit_state ps;
5459 struct kvm_pit_state2 ps2;
5460 struct kvm_pit_config pit_config;
5461 } u;
5462
5463 switch (ioctl) {
5464 case KVM_SET_TSS_ADDR:
5465 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5466 break;
5467 case KVM_SET_IDENTITY_MAP_ADDR: {
5468 u64 ident_addr;
5469
5470 mutex_lock(&kvm->lock);
5471 r = -EINVAL;
5472 if (kvm->created_vcpus)
5473 goto set_identity_unlock;
5474 r = -EFAULT;
5475 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5476 goto set_identity_unlock;
5477 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5478 set_identity_unlock:
5479 mutex_unlock(&kvm->lock);
5480 break;
5481 }
5482 case KVM_SET_NR_MMU_PAGES:
5483 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5484 break;
5485 case KVM_GET_NR_MMU_PAGES:
5486 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5487 break;
5488 case KVM_CREATE_IRQCHIP: {
5489 mutex_lock(&kvm->lock);
5490
5491 r = -EEXIST;
5492 if (irqchip_in_kernel(kvm))
5493 goto create_irqchip_unlock;
5494
5495 r = -EINVAL;
5496 if (kvm->created_vcpus)
5497 goto create_irqchip_unlock;
5498
5499 r = kvm_pic_init(kvm);
5500 if (r)
5501 goto create_irqchip_unlock;
5502
5503 r = kvm_ioapic_init(kvm);
5504 if (r) {
5505 kvm_pic_destroy(kvm);
5506 goto create_irqchip_unlock;
5507 }
5508
5509 r = kvm_setup_default_irq_routing(kvm);
5510 if (r) {
5511 kvm_ioapic_destroy(kvm);
5512 kvm_pic_destroy(kvm);
5513 goto create_irqchip_unlock;
5514 }
5515 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5516 smp_wmb();
5517 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5518 create_irqchip_unlock:
5519 mutex_unlock(&kvm->lock);
5520 break;
5521 }
5522 case KVM_CREATE_PIT:
5523 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5524 goto create_pit;
5525 case KVM_CREATE_PIT2:
5526 r = -EFAULT;
5527 if (copy_from_user(&u.pit_config, argp,
5528 sizeof(struct kvm_pit_config)))
5529 goto out;
5530 create_pit:
5531 mutex_lock(&kvm->lock);
5532 r = -EEXIST;
5533 if (kvm->arch.vpit)
5534 goto create_pit_unlock;
5535 r = -ENOMEM;
5536 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5537 if (kvm->arch.vpit)
5538 r = 0;
5539 create_pit_unlock:
5540 mutex_unlock(&kvm->lock);
5541 break;
5542 case KVM_GET_IRQCHIP: {
5543 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5544 struct kvm_irqchip *chip;
5545
5546 chip = memdup_user(argp, sizeof(*chip));
5547 if (IS_ERR(chip)) {
5548 r = PTR_ERR(chip);
5549 goto out;
5550 }
5551
5552 r = -ENXIO;
5553 if (!irqchip_kernel(kvm))
5554 goto get_irqchip_out;
5555 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5556 if (r)
5557 goto get_irqchip_out;
5558 r = -EFAULT;
5559 if (copy_to_user(argp, chip, sizeof(*chip)))
5560 goto get_irqchip_out;
5561 r = 0;
5562 get_irqchip_out:
5563 kfree(chip);
5564 break;
5565 }
5566 case KVM_SET_IRQCHIP: {
5567 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5568 struct kvm_irqchip *chip;
5569
5570 chip = memdup_user(argp, sizeof(*chip));
5571 if (IS_ERR(chip)) {
5572 r = PTR_ERR(chip);
5573 goto out;
5574 }
5575
5576 r = -ENXIO;
5577 if (!irqchip_kernel(kvm))
5578 goto set_irqchip_out;
5579 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5580 set_irqchip_out:
5581 kfree(chip);
5582 break;
5583 }
5584 case KVM_GET_PIT: {
5585 r = -EFAULT;
5586 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5587 goto out;
5588 r = -ENXIO;
5589 if (!kvm->arch.vpit)
5590 goto out;
5591 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5592 if (r)
5593 goto out;
5594 r = -EFAULT;
5595 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5596 goto out;
5597 r = 0;
5598 break;
5599 }
5600 case KVM_SET_PIT: {
5601 r = -EFAULT;
5602 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5603 goto out;
5604 mutex_lock(&kvm->lock);
5605 r = -ENXIO;
5606 if (!kvm->arch.vpit)
5607 goto set_pit_out;
5608 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5609 set_pit_out:
5610 mutex_unlock(&kvm->lock);
5611 break;
5612 }
5613 case KVM_GET_PIT2: {
5614 r = -ENXIO;
5615 if (!kvm->arch.vpit)
5616 goto out;
5617 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5618 if (r)
5619 goto out;
5620 r = -EFAULT;
5621 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5622 goto out;
5623 r = 0;
5624 break;
5625 }
5626 case KVM_SET_PIT2: {
5627 r = -EFAULT;
5628 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5629 goto out;
5630 mutex_lock(&kvm->lock);
5631 r = -ENXIO;
5632 if (!kvm->arch.vpit)
5633 goto set_pit2_out;
5634 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5635 set_pit2_out:
5636 mutex_unlock(&kvm->lock);
5637 break;
5638 }
5639 case KVM_REINJECT_CONTROL: {
5640 struct kvm_reinject_control control;
5641 r = -EFAULT;
5642 if (copy_from_user(&control, argp, sizeof(control)))
5643 goto out;
5644 r = -ENXIO;
5645 if (!kvm->arch.vpit)
5646 goto out;
5647 r = kvm_vm_ioctl_reinject(kvm, &control);
5648 break;
5649 }
5650 case KVM_SET_BOOT_CPU_ID:
5651 r = 0;
5652 mutex_lock(&kvm->lock);
5653 if (kvm->created_vcpus)
5654 r = -EBUSY;
5655 else
5656 kvm->arch.bsp_vcpu_id = arg;
5657 mutex_unlock(&kvm->lock);
5658 break;
5659 case KVM_XEN_HVM_CONFIG: {
5660 struct kvm_xen_hvm_config xhc;
5661 r = -EFAULT;
5662 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5663 goto out;
5664 r = -EINVAL;
5665 if (xhc.flags)
5666 goto out;
5667 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5668 r = 0;
5669 break;
5670 }
5671 case KVM_SET_CLOCK: {
5672 struct kvm_clock_data user_ns;
5673 u64 now_ns;
5674
5675 r = -EFAULT;
5676 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5677 goto out;
5678
5679 r = -EINVAL;
5680 if (user_ns.flags)
5681 goto out;
5682
5683 r = 0;
5684 /*
5685 * TODO: userspace has to take care of races with VCPU_RUN, so
5686 * kvm_gen_update_masterclock() can be cut down to locked
5687 * pvclock_update_vm_gtod_copy().
5688 */
5689 kvm_gen_update_masterclock(kvm);
5690 now_ns = get_kvmclock_ns(kvm);
5691 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5692 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5693 break;
5694 }
5695 case KVM_GET_CLOCK: {
5696 struct kvm_clock_data user_ns;
5697 u64 now_ns;
5698
5699 now_ns = get_kvmclock_ns(kvm);
5700 user_ns.clock = now_ns;
5701 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5702 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5703
5704 r = -EFAULT;
5705 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5706 goto out;
5707 r = 0;
5708 break;
5709 }
5710 case KVM_MEMORY_ENCRYPT_OP: {
5711 r = -ENOTTY;
5712 if (kvm_x86_ops.mem_enc_op)
5713 r = kvm_x86_ops.mem_enc_op(kvm, argp);
5714 break;
5715 }
5716 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5717 struct kvm_enc_region region;
5718
5719 r = -EFAULT;
5720 if (copy_from_user(&region, argp, sizeof(region)))
5721 goto out;
5722
5723 r = -ENOTTY;
5724 if (kvm_x86_ops.mem_enc_reg_region)
5725 r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5726 break;
5727 }
5728 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5729 struct kvm_enc_region region;
5730
5731 r = -EFAULT;
5732 if (copy_from_user(&region, argp, sizeof(region)))
5733 goto out;
5734
5735 r = -ENOTTY;
5736 if (kvm_x86_ops.mem_enc_unreg_region)
5737 r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5738 break;
5739 }
5740 case KVM_HYPERV_EVENTFD: {
5741 struct kvm_hyperv_eventfd hvevfd;
5742
5743 r = -EFAULT;
5744 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5745 goto out;
5746 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5747 break;
5748 }
5749 case KVM_SET_PMU_EVENT_FILTER:
5750 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5751 break;
5752 case KVM_X86_SET_MSR_FILTER:
5753 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5754 break;
5755 default:
5756 r = -ENOTTY;
5757 }
5758 out:
5759 return r;
5760 }
5761
5762 static void kvm_init_msr_list(void)
5763 {
5764 struct x86_pmu_capability x86_pmu;
5765 u32 dummy[2];
5766 unsigned i;
5767
5768 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5769 "Please update the fixed PMCs in msrs_to_saved_all[]");
5770
5771 perf_get_x86_pmu_capability(&x86_pmu);
5772
5773 num_msrs_to_save = 0;
5774 num_emulated_msrs = 0;
5775 num_msr_based_features = 0;
5776
5777 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5778 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5779 continue;
5780
5781 /*
5782 * Even MSRs that are valid in the host may not be exposed
5783 * to the guests in some cases.
5784 */
5785 switch (msrs_to_save_all[i]) {
5786 case MSR_IA32_BNDCFGS:
5787 if (!kvm_mpx_supported())
5788 continue;
5789 break;
5790 case MSR_TSC_AUX:
5791 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5792 continue;
5793 break;
5794 case MSR_IA32_UMWAIT_CONTROL:
5795 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5796 continue;
5797 break;
5798 case MSR_IA32_RTIT_CTL:
5799 case MSR_IA32_RTIT_STATUS:
5800 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5801 continue;
5802 break;
5803 case MSR_IA32_RTIT_CR3_MATCH:
5804 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5805 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5806 continue;
5807 break;
5808 case MSR_IA32_RTIT_OUTPUT_BASE:
5809 case MSR_IA32_RTIT_OUTPUT_MASK:
5810 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5811 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5812 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5813 continue;
5814 break;
5815 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5816 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5817 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5818 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5819 continue;
5820 break;
5821 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5822 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5823 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5824 continue;
5825 break;
5826 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5827 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5828 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5829 continue;
5830 break;
5831 default:
5832 break;
5833 }
5834
5835 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5836 }
5837
5838 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5839 if (!kvm_x86_ops.has_emulated_msr(NULL, emulated_msrs_all[i]))
5840 continue;
5841
5842 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5843 }
5844
5845 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5846 struct kvm_msr_entry msr;
5847
5848 msr.index = msr_based_features_all[i];
5849 if (kvm_get_msr_feature(&msr))
5850 continue;
5851
5852 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5853 }
5854 }
5855
5856 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5857 const void *v)
5858 {
5859 int handled = 0;
5860 int n;
5861
5862 do {
5863 n = min(len, 8);
5864 if (!(lapic_in_kernel(vcpu) &&
5865 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5866 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5867 break;
5868 handled += n;
5869 addr += n;
5870 len -= n;
5871 v += n;
5872 } while (len);
5873
5874 return handled;
5875 }
5876
5877 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5878 {
5879 int handled = 0;
5880 int n;
5881
5882 do {
5883 n = min(len, 8);
5884 if (!(lapic_in_kernel(vcpu) &&
5885 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5886 addr, n, v))
5887 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5888 break;
5889 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5890 handled += n;
5891 addr += n;
5892 len -= n;
5893 v += n;
5894 } while (len);
5895
5896 return handled;
5897 }
5898
5899 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5900 struct kvm_segment *var, int seg)
5901 {
5902 kvm_x86_ops.set_segment(vcpu, var, seg);
5903 }
5904
5905 void kvm_get_segment(struct kvm_vcpu *vcpu,
5906 struct kvm_segment *var, int seg)
5907 {
5908 kvm_x86_ops.get_segment(vcpu, var, seg);
5909 }
5910
5911 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5912 struct x86_exception *exception)
5913 {
5914 gpa_t t_gpa;
5915
5916 BUG_ON(!mmu_is_nested(vcpu));
5917
5918 /* NPT walks are always user-walks */
5919 access |= PFERR_USER_MASK;
5920 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5921
5922 return t_gpa;
5923 }
5924
5925 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5926 struct x86_exception *exception)
5927 {
5928 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5929 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5930 }
5931
5932 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5933 struct x86_exception *exception)
5934 {
5935 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5936 access |= PFERR_FETCH_MASK;
5937 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5938 }
5939
5940 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5941 struct x86_exception *exception)
5942 {
5943 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5944 access |= PFERR_WRITE_MASK;
5945 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5946 }
5947
5948 /* uses this to access any guest's mapped memory without checking CPL */
5949 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5950 struct x86_exception *exception)
5951 {
5952 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5953 }
5954
5955 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5956 struct kvm_vcpu *vcpu, u32 access,
5957 struct x86_exception *exception)
5958 {
5959 void *data = val;
5960 int r = X86EMUL_CONTINUE;
5961
5962 while (bytes) {
5963 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5964 exception);
5965 unsigned offset = addr & (PAGE_SIZE-1);
5966 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5967 int ret;
5968
5969 if (gpa == UNMAPPED_GVA)
5970 return X86EMUL_PROPAGATE_FAULT;
5971 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5972 offset, toread);
5973 if (ret < 0) {
5974 r = X86EMUL_IO_NEEDED;
5975 goto out;
5976 }
5977
5978 bytes -= toread;
5979 data += toread;
5980 addr += toread;
5981 }
5982 out:
5983 return r;
5984 }
5985
5986 /* used for instruction fetching */
5987 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5988 gva_t addr, void *val, unsigned int bytes,
5989 struct x86_exception *exception)
5990 {
5991 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5992 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5993 unsigned offset;
5994 int ret;
5995
5996 /* Inline kvm_read_guest_virt_helper for speed. */
5997 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5998 exception);
5999 if (unlikely(gpa == UNMAPPED_GVA))
6000 return X86EMUL_PROPAGATE_FAULT;
6001
6002 offset = addr & (PAGE_SIZE-1);
6003 if (WARN_ON(offset + bytes > PAGE_SIZE))
6004 bytes = (unsigned)PAGE_SIZE - offset;
6005 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
6006 offset, bytes);
6007 if (unlikely(ret < 0))
6008 return X86EMUL_IO_NEEDED;
6009
6010 return X86EMUL_CONTINUE;
6011 }
6012
6013 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
6014 gva_t addr, void *val, unsigned int bytes,
6015 struct x86_exception *exception)
6016 {
6017 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
6018
6019 /*
6020 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
6021 * is returned, but our callers are not ready for that and they blindly
6022 * call kvm_inject_page_fault. Ensure that they at least do not leak
6023 * uninitialized kernel stack memory into cr2 and error code.
6024 */
6025 memset(exception, 0, sizeof(*exception));
6026 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
6027 exception);
6028 }
6029 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
6030
6031 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
6032 gva_t addr, void *val, unsigned int bytes,
6033 struct x86_exception *exception, bool system)
6034 {
6035 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6036 u32 access = 0;
6037
6038 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6039 access |= PFERR_USER_MASK;
6040
6041 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
6042 }
6043
6044 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
6045 unsigned long addr, void *val, unsigned int bytes)
6046 {
6047 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6048 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
6049
6050 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
6051 }
6052
6053 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6054 struct kvm_vcpu *vcpu, u32 access,
6055 struct x86_exception *exception)
6056 {
6057 void *data = val;
6058 int r = X86EMUL_CONTINUE;
6059
6060 while (bytes) {
6061 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
6062 access,
6063 exception);
6064 unsigned offset = addr & (PAGE_SIZE-1);
6065 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6066 int ret;
6067
6068 if (gpa == UNMAPPED_GVA)
6069 return X86EMUL_PROPAGATE_FAULT;
6070 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6071 if (ret < 0) {
6072 r = X86EMUL_IO_NEEDED;
6073 goto out;
6074 }
6075
6076 bytes -= towrite;
6077 data += towrite;
6078 addr += towrite;
6079 }
6080 out:
6081 return r;
6082 }
6083
6084 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6085 unsigned int bytes, struct x86_exception *exception,
6086 bool system)
6087 {
6088 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6089 u32 access = PFERR_WRITE_MASK;
6090
6091 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6092 access |= PFERR_USER_MASK;
6093
6094 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6095 access, exception);
6096 }
6097
6098 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6099 unsigned int bytes, struct x86_exception *exception)
6100 {
6101 /* kvm_write_guest_virt_system can pull in tons of pages. */
6102 vcpu->arch.l1tf_flush_l1d = true;
6103
6104 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6105 PFERR_WRITE_MASK, exception);
6106 }
6107 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6108
6109 int handle_ud(struct kvm_vcpu *vcpu)
6110 {
6111 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6112 int emul_type = EMULTYPE_TRAP_UD;
6113 char sig[5]; /* ud2; .ascii "kvm" */
6114 struct x86_exception e;
6115
6116 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0)))
6117 return 1;
6118
6119 if (force_emulation_prefix &&
6120 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6121 sig, sizeof(sig), &e) == 0 &&
6122 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6123 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6124 emul_type = EMULTYPE_TRAP_UD_FORCED;
6125 }
6126
6127 return kvm_emulate_instruction(vcpu, emul_type);
6128 }
6129 EXPORT_SYMBOL_GPL(handle_ud);
6130
6131 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6132 gpa_t gpa, bool write)
6133 {
6134 /* For APIC access vmexit */
6135 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6136 return 1;
6137
6138 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6139 trace_vcpu_match_mmio(gva, gpa, write, true);
6140 return 1;
6141 }
6142
6143 return 0;
6144 }
6145
6146 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6147 gpa_t *gpa, struct x86_exception *exception,
6148 bool write)
6149 {
6150 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
6151 | (write ? PFERR_WRITE_MASK : 0);
6152
6153 /*
6154 * currently PKRU is only applied to ept enabled guest so
6155 * there is no pkey in EPT page table for L1 guest or EPT
6156 * shadow page table for L2 guest.
6157 */
6158 if (vcpu_match_mmio_gva(vcpu, gva)
6159 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6160 vcpu->arch.mmio_access, 0, access)) {
6161 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6162 (gva & (PAGE_SIZE - 1));
6163 trace_vcpu_match_mmio(gva, *gpa, write, false);
6164 return 1;
6165 }
6166
6167 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6168
6169 if (*gpa == UNMAPPED_GVA)
6170 return -1;
6171
6172 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6173 }
6174
6175 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6176 const void *val, int bytes)
6177 {
6178 int ret;
6179
6180 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6181 if (ret < 0)
6182 return 0;
6183 kvm_page_track_write(vcpu, gpa, val, bytes);
6184 return 1;
6185 }
6186
6187 struct read_write_emulator_ops {
6188 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6189 int bytes);
6190 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6191 void *val, int bytes);
6192 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6193 int bytes, void *val);
6194 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6195 void *val, int bytes);
6196 bool write;
6197 };
6198
6199 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6200 {
6201 if (vcpu->mmio_read_completed) {
6202 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6203 vcpu->mmio_fragments[0].gpa, val);
6204 vcpu->mmio_read_completed = 0;
6205 return 1;
6206 }
6207
6208 return 0;
6209 }
6210
6211 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6212 void *val, int bytes)
6213 {
6214 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6215 }
6216
6217 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6218 void *val, int bytes)
6219 {
6220 return emulator_write_phys(vcpu, gpa, val, bytes);
6221 }
6222
6223 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6224 {
6225 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6226 return vcpu_mmio_write(vcpu, gpa, bytes, val);
6227 }
6228
6229 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6230 void *val, int bytes)
6231 {
6232 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6233 return X86EMUL_IO_NEEDED;
6234 }
6235
6236 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6237 void *val, int bytes)
6238 {
6239 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6240
6241 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6242 return X86EMUL_CONTINUE;
6243 }
6244
6245 static const struct read_write_emulator_ops read_emultor = {
6246 .read_write_prepare = read_prepare,
6247 .read_write_emulate = read_emulate,
6248 .read_write_mmio = vcpu_mmio_read,
6249 .read_write_exit_mmio = read_exit_mmio,
6250 };
6251
6252 static const struct read_write_emulator_ops write_emultor = {
6253 .read_write_emulate = write_emulate,
6254 .read_write_mmio = write_mmio,
6255 .read_write_exit_mmio = write_exit_mmio,
6256 .write = true,
6257 };
6258
6259 static int emulator_read_write_onepage(unsigned long addr, void *val,
6260 unsigned int bytes,
6261 struct x86_exception *exception,
6262 struct kvm_vcpu *vcpu,
6263 const struct read_write_emulator_ops *ops)
6264 {
6265 gpa_t gpa;
6266 int handled, ret;
6267 bool write = ops->write;
6268 struct kvm_mmio_fragment *frag;
6269 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6270
6271 /*
6272 * If the exit was due to a NPF we may already have a GPA.
6273 * If the GPA is present, use it to avoid the GVA to GPA table walk.
6274 * Note, this cannot be used on string operations since string
6275 * operation using rep will only have the initial GPA from the NPF
6276 * occurred.
6277 */
6278 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6279 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6280 gpa = ctxt->gpa_val;
6281 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6282 } else {
6283 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6284 if (ret < 0)
6285 return X86EMUL_PROPAGATE_FAULT;
6286 }
6287
6288 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6289 return X86EMUL_CONTINUE;
6290
6291 /*
6292 * Is this MMIO handled locally?
6293 */
6294 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6295 if (handled == bytes)
6296 return X86EMUL_CONTINUE;
6297
6298 gpa += handled;
6299 bytes -= handled;
6300 val += handled;
6301
6302 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6303 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6304 frag->gpa = gpa;
6305 frag->data = val;
6306 frag->len = bytes;
6307 return X86EMUL_CONTINUE;
6308 }
6309
6310 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6311 unsigned long addr,
6312 void *val, unsigned int bytes,
6313 struct x86_exception *exception,
6314 const struct read_write_emulator_ops *ops)
6315 {
6316 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6317 gpa_t gpa;
6318 int rc;
6319
6320 if (ops->read_write_prepare &&
6321 ops->read_write_prepare(vcpu, val, bytes))
6322 return X86EMUL_CONTINUE;
6323
6324 vcpu->mmio_nr_fragments = 0;
6325
6326 /* Crossing a page boundary? */
6327 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6328 int now;
6329
6330 now = -addr & ~PAGE_MASK;
6331 rc = emulator_read_write_onepage(addr, val, now, exception,
6332 vcpu, ops);
6333
6334 if (rc != X86EMUL_CONTINUE)
6335 return rc;
6336 addr += now;
6337 if (ctxt->mode != X86EMUL_MODE_PROT64)
6338 addr = (u32)addr;
6339 val += now;
6340 bytes -= now;
6341 }
6342
6343 rc = emulator_read_write_onepage(addr, val, bytes, exception,
6344 vcpu, ops);
6345 if (rc != X86EMUL_CONTINUE)
6346 return rc;
6347
6348 if (!vcpu->mmio_nr_fragments)
6349 return rc;
6350
6351 gpa = vcpu->mmio_fragments[0].gpa;
6352
6353 vcpu->mmio_needed = 1;
6354 vcpu->mmio_cur_fragment = 0;
6355
6356 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6357 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6358 vcpu->run->exit_reason = KVM_EXIT_MMIO;
6359 vcpu->run->mmio.phys_addr = gpa;
6360
6361 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6362 }
6363
6364 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6365 unsigned long addr,
6366 void *val,
6367 unsigned int bytes,
6368 struct x86_exception *exception)
6369 {
6370 return emulator_read_write(ctxt, addr, val, bytes,
6371 exception, &read_emultor);
6372 }
6373
6374 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6375 unsigned long addr,
6376 const void *val,
6377 unsigned int bytes,
6378 struct x86_exception *exception)
6379 {
6380 return emulator_read_write(ctxt, addr, (void *)val, bytes,
6381 exception, &write_emultor);
6382 }
6383
6384 #define CMPXCHG_TYPE(t, ptr, old, new) \
6385 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6386
6387 #ifdef CONFIG_X86_64
6388 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6389 #else
6390 # define CMPXCHG64(ptr, old, new) \
6391 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6392 #endif
6393
6394 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6395 unsigned long addr,
6396 const void *old,
6397 const void *new,
6398 unsigned int bytes,
6399 struct x86_exception *exception)
6400 {
6401 struct kvm_host_map map;
6402 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6403 u64 page_line_mask;
6404 gpa_t gpa;
6405 char *kaddr;
6406 bool exchanged;
6407
6408 /* guests cmpxchg8b have to be emulated atomically */
6409 if (bytes > 8 || (bytes & (bytes - 1)))
6410 goto emul_write;
6411
6412 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6413
6414 if (gpa == UNMAPPED_GVA ||
6415 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6416 goto emul_write;
6417
6418 /*
6419 * Emulate the atomic as a straight write to avoid #AC if SLD is
6420 * enabled in the host and the access splits a cache line.
6421 */
6422 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6423 page_line_mask = ~(cache_line_size() - 1);
6424 else
6425 page_line_mask = PAGE_MASK;
6426
6427 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6428 goto emul_write;
6429
6430 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6431 goto emul_write;
6432
6433 kaddr = map.hva + offset_in_page(gpa);
6434
6435 switch (bytes) {
6436 case 1:
6437 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6438 break;
6439 case 2:
6440 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6441 break;
6442 case 4:
6443 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6444 break;
6445 case 8:
6446 exchanged = CMPXCHG64(kaddr, old, new);
6447 break;
6448 default:
6449 BUG();
6450 }
6451
6452 kvm_vcpu_unmap(vcpu, &map, true);
6453
6454 if (!exchanged)
6455 return X86EMUL_CMPXCHG_FAILED;
6456
6457 kvm_page_track_write(vcpu, gpa, new, bytes);
6458
6459 return X86EMUL_CONTINUE;
6460
6461 emul_write:
6462 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6463
6464 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6465 }
6466
6467 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6468 {
6469 int r = 0, i;
6470
6471 for (i = 0; i < vcpu->arch.pio.count; i++) {
6472 if (vcpu->arch.pio.in)
6473 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6474 vcpu->arch.pio.size, pd);
6475 else
6476 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6477 vcpu->arch.pio.port, vcpu->arch.pio.size,
6478 pd);
6479 if (r)
6480 break;
6481 pd += vcpu->arch.pio.size;
6482 }
6483 return r;
6484 }
6485
6486 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6487 unsigned short port, void *val,
6488 unsigned int count, bool in)
6489 {
6490 vcpu->arch.pio.port = port;
6491 vcpu->arch.pio.in = in;
6492 vcpu->arch.pio.count = count;
6493 vcpu->arch.pio.size = size;
6494
6495 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6496 vcpu->arch.pio.count = 0;
6497 return 1;
6498 }
6499
6500 vcpu->run->exit_reason = KVM_EXIT_IO;
6501 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6502 vcpu->run->io.size = size;
6503 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6504 vcpu->run->io.count = count;
6505 vcpu->run->io.port = port;
6506
6507 return 0;
6508 }
6509
6510 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6511 unsigned short port, void *val, unsigned int count)
6512 {
6513 int ret;
6514
6515 if (vcpu->arch.pio.count)
6516 goto data_avail;
6517
6518 memset(vcpu->arch.pio_data, 0, size * count);
6519
6520 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6521 if (ret) {
6522 data_avail:
6523 memcpy(val, vcpu->arch.pio_data, size * count);
6524 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6525 vcpu->arch.pio.count = 0;
6526 return 1;
6527 }
6528
6529 return 0;
6530 }
6531
6532 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6533 int size, unsigned short port, void *val,
6534 unsigned int count)
6535 {
6536 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6537
6538 }
6539
6540 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6541 unsigned short port, const void *val,
6542 unsigned int count)
6543 {
6544 memcpy(vcpu->arch.pio_data, val, size * count);
6545 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6546 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6547 }
6548
6549 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6550 int size, unsigned short port,
6551 const void *val, unsigned int count)
6552 {
6553 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6554 }
6555
6556 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6557 {
6558 return kvm_x86_ops.get_segment_base(vcpu, seg);
6559 }
6560
6561 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6562 {
6563 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6564 }
6565
6566 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6567 {
6568 if (!need_emulate_wbinvd(vcpu))
6569 return X86EMUL_CONTINUE;
6570
6571 if (kvm_x86_ops.has_wbinvd_exit()) {
6572 int cpu = get_cpu();
6573
6574 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6575 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6576 wbinvd_ipi, NULL, 1);
6577 put_cpu();
6578 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6579 } else
6580 wbinvd();
6581 return X86EMUL_CONTINUE;
6582 }
6583
6584 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6585 {
6586 kvm_emulate_wbinvd_noskip(vcpu);
6587 return kvm_skip_emulated_instruction(vcpu);
6588 }
6589 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6590
6591
6592
6593 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6594 {
6595 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6596 }
6597
6598 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6599 unsigned long *dest)
6600 {
6601 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6602 }
6603
6604 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6605 unsigned long value)
6606 {
6607
6608 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6609 }
6610
6611 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6612 {
6613 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6614 }
6615
6616 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6617 {
6618 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6619 unsigned long value;
6620
6621 switch (cr) {
6622 case 0:
6623 value = kvm_read_cr0(vcpu);
6624 break;
6625 case 2:
6626 value = vcpu->arch.cr2;
6627 break;
6628 case 3:
6629 value = kvm_read_cr3(vcpu);
6630 break;
6631 case 4:
6632 value = kvm_read_cr4(vcpu);
6633 break;
6634 case 8:
6635 value = kvm_get_cr8(vcpu);
6636 break;
6637 default:
6638 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6639 return 0;
6640 }
6641
6642 return value;
6643 }
6644
6645 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6646 {
6647 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6648 int res = 0;
6649
6650 switch (cr) {
6651 case 0:
6652 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6653 break;
6654 case 2:
6655 vcpu->arch.cr2 = val;
6656 break;
6657 case 3:
6658 res = kvm_set_cr3(vcpu, val);
6659 break;
6660 case 4:
6661 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6662 break;
6663 case 8:
6664 res = kvm_set_cr8(vcpu, val);
6665 break;
6666 default:
6667 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6668 res = -1;
6669 }
6670
6671 return res;
6672 }
6673
6674 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6675 {
6676 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6677 }
6678
6679 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6680 {
6681 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6682 }
6683
6684 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6685 {
6686 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6687 }
6688
6689 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6690 {
6691 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6692 }
6693
6694 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6695 {
6696 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6697 }
6698
6699 static unsigned long emulator_get_cached_segment_base(
6700 struct x86_emulate_ctxt *ctxt, int seg)
6701 {
6702 return get_segment_base(emul_to_vcpu(ctxt), seg);
6703 }
6704
6705 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6706 struct desc_struct *desc, u32 *base3,
6707 int seg)
6708 {
6709 struct kvm_segment var;
6710
6711 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6712 *selector = var.selector;
6713
6714 if (var.unusable) {
6715 memset(desc, 0, sizeof(*desc));
6716 if (base3)
6717 *base3 = 0;
6718 return false;
6719 }
6720
6721 if (var.g)
6722 var.limit >>= 12;
6723 set_desc_limit(desc, var.limit);
6724 set_desc_base(desc, (unsigned long)var.base);
6725 #ifdef CONFIG_X86_64
6726 if (base3)
6727 *base3 = var.base >> 32;
6728 #endif
6729 desc->type = var.type;
6730 desc->s = var.s;
6731 desc->dpl = var.dpl;
6732 desc->p = var.present;
6733 desc->avl = var.avl;
6734 desc->l = var.l;
6735 desc->d = var.db;
6736 desc->g = var.g;
6737
6738 return true;
6739 }
6740
6741 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6742 struct desc_struct *desc, u32 base3,
6743 int seg)
6744 {
6745 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6746 struct kvm_segment var;
6747
6748 var.selector = selector;
6749 var.base = get_desc_base(desc);
6750 #ifdef CONFIG_X86_64
6751 var.base |= ((u64)base3) << 32;
6752 #endif
6753 var.limit = get_desc_limit(desc);
6754 if (desc->g)
6755 var.limit = (var.limit << 12) | 0xfff;
6756 var.type = desc->type;
6757 var.dpl = desc->dpl;
6758 var.db = desc->d;
6759 var.s = desc->s;
6760 var.l = desc->l;
6761 var.g = desc->g;
6762 var.avl = desc->avl;
6763 var.present = desc->p;
6764 var.unusable = !var.present;
6765 var.padding = 0;
6766
6767 kvm_set_segment(vcpu, &var, seg);
6768 return;
6769 }
6770
6771 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6772 u32 msr_index, u64 *pdata)
6773 {
6774 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6775 int r;
6776
6777 r = kvm_get_msr(vcpu, msr_index, pdata);
6778
6779 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6780 /* Bounce to user space */
6781 return X86EMUL_IO_NEEDED;
6782 }
6783
6784 return r;
6785 }
6786
6787 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6788 u32 msr_index, u64 data)
6789 {
6790 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6791 int r;
6792
6793 r = kvm_set_msr(vcpu, msr_index, data);
6794
6795 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6796 /* Bounce to user space */
6797 return X86EMUL_IO_NEEDED;
6798 }
6799
6800 return r;
6801 }
6802
6803 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6804 {
6805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6806
6807 return vcpu->arch.smbase;
6808 }
6809
6810 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6811 {
6812 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6813
6814 vcpu->arch.smbase = smbase;
6815 }
6816
6817 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6818 u32 pmc)
6819 {
6820 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6821 }
6822
6823 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6824 u32 pmc, u64 *pdata)
6825 {
6826 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6827 }
6828
6829 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6830 {
6831 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6832 }
6833
6834 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6835 struct x86_instruction_info *info,
6836 enum x86_intercept_stage stage)
6837 {
6838 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6839 &ctxt->exception);
6840 }
6841
6842 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6843 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6844 bool exact_only)
6845 {
6846 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6847 }
6848
6849 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6850 {
6851 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6852 }
6853
6854 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6855 {
6856 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6857 }
6858
6859 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6860 {
6861 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6862 }
6863
6864 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6865 {
6866 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6867 }
6868
6869 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6870 {
6871 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6872 }
6873
6874 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6875 {
6876 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6877 }
6878
6879 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6880 {
6881 return emul_to_vcpu(ctxt)->arch.hflags;
6882 }
6883
6884 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6885 {
6886 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6887 }
6888
6889 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6890 const char *smstate)
6891 {
6892 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6893 }
6894
6895 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6896 {
6897 kvm_smm_changed(emul_to_vcpu(ctxt));
6898 }
6899
6900 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6901 {
6902 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6903 }
6904
6905 static const struct x86_emulate_ops emulate_ops = {
6906 .read_gpr = emulator_read_gpr,
6907 .write_gpr = emulator_write_gpr,
6908 .read_std = emulator_read_std,
6909 .write_std = emulator_write_std,
6910 .read_phys = kvm_read_guest_phys_system,
6911 .fetch = kvm_fetch_guest_virt,
6912 .read_emulated = emulator_read_emulated,
6913 .write_emulated = emulator_write_emulated,
6914 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6915 .invlpg = emulator_invlpg,
6916 .pio_in_emulated = emulator_pio_in_emulated,
6917 .pio_out_emulated = emulator_pio_out_emulated,
6918 .get_segment = emulator_get_segment,
6919 .set_segment = emulator_set_segment,
6920 .get_cached_segment_base = emulator_get_cached_segment_base,
6921 .get_gdt = emulator_get_gdt,
6922 .get_idt = emulator_get_idt,
6923 .set_gdt = emulator_set_gdt,
6924 .set_idt = emulator_set_idt,
6925 .get_cr = emulator_get_cr,
6926 .set_cr = emulator_set_cr,
6927 .cpl = emulator_get_cpl,
6928 .get_dr = emulator_get_dr,
6929 .set_dr = emulator_set_dr,
6930 .get_smbase = emulator_get_smbase,
6931 .set_smbase = emulator_set_smbase,
6932 .set_msr = emulator_set_msr,
6933 .get_msr = emulator_get_msr,
6934 .check_pmc = emulator_check_pmc,
6935 .read_pmc = emulator_read_pmc,
6936 .halt = emulator_halt,
6937 .wbinvd = emulator_wbinvd,
6938 .fix_hypercall = emulator_fix_hypercall,
6939 .intercept = emulator_intercept,
6940 .get_cpuid = emulator_get_cpuid,
6941 .guest_has_long_mode = emulator_guest_has_long_mode,
6942 .guest_has_movbe = emulator_guest_has_movbe,
6943 .guest_has_fxsr = emulator_guest_has_fxsr,
6944 .set_nmi_mask = emulator_set_nmi_mask,
6945 .get_hflags = emulator_get_hflags,
6946 .set_hflags = emulator_set_hflags,
6947 .pre_leave_smm = emulator_pre_leave_smm,
6948 .post_leave_smm = emulator_post_leave_smm,
6949 .set_xcr = emulator_set_xcr,
6950 };
6951
6952 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6953 {
6954 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6955 /*
6956 * an sti; sti; sequence only disable interrupts for the first
6957 * instruction. So, if the last instruction, be it emulated or
6958 * not, left the system with the INT_STI flag enabled, it
6959 * means that the last instruction is an sti. We should not
6960 * leave the flag on in this case. The same goes for mov ss
6961 */
6962 if (int_shadow & mask)
6963 mask = 0;
6964 if (unlikely(int_shadow || mask)) {
6965 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6966 if (!mask)
6967 kvm_make_request(KVM_REQ_EVENT, vcpu);
6968 }
6969 }
6970
6971 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6972 {
6973 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6974 if (ctxt->exception.vector == PF_VECTOR)
6975 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6976
6977 if (ctxt->exception.error_code_valid)
6978 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6979 ctxt->exception.error_code);
6980 else
6981 kvm_queue_exception(vcpu, ctxt->exception.vector);
6982 return false;
6983 }
6984
6985 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6986 {
6987 struct x86_emulate_ctxt *ctxt;
6988
6989 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6990 if (!ctxt) {
6991 pr_err("kvm: failed to allocate vcpu's emulator\n");
6992 return NULL;
6993 }
6994
6995 ctxt->vcpu = vcpu;
6996 ctxt->ops = &emulate_ops;
6997 vcpu->arch.emulate_ctxt = ctxt;
6998
6999 return ctxt;
7000 }
7001
7002 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
7003 {
7004 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7005 int cs_db, cs_l;
7006
7007 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
7008
7009 ctxt->gpa_available = false;
7010 ctxt->eflags = kvm_get_rflags(vcpu);
7011 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
7012
7013 ctxt->eip = kvm_rip_read(vcpu);
7014 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
7015 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
7016 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
7017 cs_db ? X86EMUL_MODE_PROT32 :
7018 X86EMUL_MODE_PROT16;
7019 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
7020 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
7021 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
7022
7023 init_decode_cache(ctxt);
7024 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7025 }
7026
7027 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
7028 {
7029 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7030 int ret;
7031
7032 init_emulate_ctxt(vcpu);
7033
7034 ctxt->op_bytes = 2;
7035 ctxt->ad_bytes = 2;
7036 ctxt->_eip = ctxt->eip + inc_eip;
7037 ret = emulate_int_real(ctxt, irq);
7038
7039 if (ret != X86EMUL_CONTINUE) {
7040 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7041 } else {
7042 ctxt->eip = ctxt->_eip;
7043 kvm_rip_write(vcpu, ctxt->eip);
7044 kvm_set_rflags(vcpu, ctxt->eflags);
7045 }
7046 }
7047 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
7048
7049 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
7050 {
7051 ++vcpu->stat.insn_emulation_fail;
7052 trace_kvm_emulate_insn_failed(vcpu);
7053
7054 if (emulation_type & EMULTYPE_VMWARE_GP) {
7055 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7056 return 1;
7057 }
7058
7059 if (emulation_type & EMULTYPE_SKIP) {
7060 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7061 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7062 vcpu->run->internal.ndata = 0;
7063 return 0;
7064 }
7065
7066 kvm_queue_exception(vcpu, UD_VECTOR);
7067
7068 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
7069 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7070 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7071 vcpu->run->internal.ndata = 0;
7072 return 0;
7073 }
7074
7075 return 1;
7076 }
7077
7078 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7079 bool write_fault_to_shadow_pgtable,
7080 int emulation_type)
7081 {
7082 gpa_t gpa = cr2_or_gpa;
7083 kvm_pfn_t pfn;
7084
7085 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7086 return false;
7087
7088 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7089 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7090 return false;
7091
7092 if (!vcpu->arch.mmu->direct_map) {
7093 /*
7094 * Write permission should be allowed since only
7095 * write access need to be emulated.
7096 */
7097 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7098
7099 /*
7100 * If the mapping is invalid in guest, let cpu retry
7101 * it to generate fault.
7102 */
7103 if (gpa == UNMAPPED_GVA)
7104 return true;
7105 }
7106
7107 /*
7108 * Do not retry the unhandleable instruction if it faults on the
7109 * readonly host memory, otherwise it will goto a infinite loop:
7110 * retry instruction -> write #PF -> emulation fail -> retry
7111 * instruction -> ...
7112 */
7113 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
7114
7115 /*
7116 * If the instruction failed on the error pfn, it can not be fixed,
7117 * report the error to userspace.
7118 */
7119 if (is_error_noslot_pfn(pfn))
7120 return false;
7121
7122 kvm_release_pfn_clean(pfn);
7123
7124 /* The instructions are well-emulated on direct mmu. */
7125 if (vcpu->arch.mmu->direct_map) {
7126 unsigned int indirect_shadow_pages;
7127
7128 spin_lock(&vcpu->kvm->mmu_lock);
7129 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
7130 spin_unlock(&vcpu->kvm->mmu_lock);
7131
7132 if (indirect_shadow_pages)
7133 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7134
7135 return true;
7136 }
7137
7138 /*
7139 * if emulation was due to access to shadowed page table
7140 * and it failed try to unshadow page and re-enter the
7141 * guest to let CPU execute the instruction.
7142 */
7143 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7144
7145 /*
7146 * If the access faults on its page table, it can not
7147 * be fixed by unprotecting shadow page and it should
7148 * be reported to userspace.
7149 */
7150 return !write_fault_to_shadow_pgtable;
7151 }
7152
7153 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7154 gpa_t cr2_or_gpa, int emulation_type)
7155 {
7156 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7157 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7158
7159 last_retry_eip = vcpu->arch.last_retry_eip;
7160 last_retry_addr = vcpu->arch.last_retry_addr;
7161
7162 /*
7163 * If the emulation is caused by #PF and it is non-page_table
7164 * writing instruction, it means the VM-EXIT is caused by shadow
7165 * page protected, we can zap the shadow page and retry this
7166 * instruction directly.
7167 *
7168 * Note: if the guest uses a non-page-table modifying instruction
7169 * on the PDE that points to the instruction, then we will unmap
7170 * the instruction and go to an infinite loop. So, we cache the
7171 * last retried eip and the last fault address, if we meet the eip
7172 * and the address again, we can break out of the potential infinite
7173 * loop.
7174 */
7175 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7176
7177 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7178 return false;
7179
7180 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7181 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7182 return false;
7183
7184 if (x86_page_table_writing_insn(ctxt))
7185 return false;
7186
7187 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7188 return false;
7189
7190 vcpu->arch.last_retry_eip = ctxt->eip;
7191 vcpu->arch.last_retry_addr = cr2_or_gpa;
7192
7193 if (!vcpu->arch.mmu->direct_map)
7194 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7195
7196 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7197
7198 return true;
7199 }
7200
7201 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7202 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7203
7204 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7205 {
7206 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7207 /* This is a good place to trace that we are exiting SMM. */
7208 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7209
7210 /* Process a latched INIT or SMI, if any. */
7211 kvm_make_request(KVM_REQ_EVENT, vcpu);
7212 }
7213
7214 kvm_mmu_reset_context(vcpu);
7215 }
7216
7217 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7218 unsigned long *db)
7219 {
7220 u32 dr6 = 0;
7221 int i;
7222 u32 enable, rwlen;
7223
7224 enable = dr7;
7225 rwlen = dr7 >> 16;
7226 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7227 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7228 dr6 |= (1 << i);
7229 return dr6;
7230 }
7231
7232 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7233 {
7234 struct kvm_run *kvm_run = vcpu->run;
7235
7236 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7237 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
7238 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7239 kvm_run->debug.arch.exception = DB_VECTOR;
7240 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7241 return 0;
7242 }
7243 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7244 return 1;
7245 }
7246
7247 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7248 {
7249 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7250 int r;
7251
7252 r = kvm_x86_ops.skip_emulated_instruction(vcpu);
7253 if (unlikely(!r))
7254 return 0;
7255
7256 /*
7257 * rflags is the old, "raw" value of the flags. The new value has
7258 * not been saved yet.
7259 *
7260 * This is correct even for TF set by the guest, because "the
7261 * processor will not generate this exception after the instruction
7262 * that sets the TF flag".
7263 */
7264 if (unlikely(rflags & X86_EFLAGS_TF))
7265 r = kvm_vcpu_do_singlestep(vcpu);
7266 return r;
7267 }
7268 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7269
7270 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7271 {
7272 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7273 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7274 struct kvm_run *kvm_run = vcpu->run;
7275 unsigned long eip = kvm_get_linear_rip(vcpu);
7276 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7277 vcpu->arch.guest_debug_dr7,
7278 vcpu->arch.eff_db);
7279
7280 if (dr6 != 0) {
7281 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
7282 kvm_run->debug.arch.pc = eip;
7283 kvm_run->debug.arch.exception = DB_VECTOR;
7284 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7285 *r = 0;
7286 return true;
7287 }
7288 }
7289
7290 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7291 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7292 unsigned long eip = kvm_get_linear_rip(vcpu);
7293 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7294 vcpu->arch.dr7,
7295 vcpu->arch.db);
7296
7297 if (dr6 != 0) {
7298 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7299 *r = 1;
7300 return true;
7301 }
7302 }
7303
7304 return false;
7305 }
7306
7307 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7308 {
7309 switch (ctxt->opcode_len) {
7310 case 1:
7311 switch (ctxt->b) {
7312 case 0xe4: /* IN */
7313 case 0xe5:
7314 case 0xec:
7315 case 0xed:
7316 case 0xe6: /* OUT */
7317 case 0xe7:
7318 case 0xee:
7319 case 0xef:
7320 case 0x6c: /* INS */
7321 case 0x6d:
7322 case 0x6e: /* OUTS */
7323 case 0x6f:
7324 return true;
7325 }
7326 break;
7327 case 2:
7328 switch (ctxt->b) {
7329 case 0x33: /* RDPMC */
7330 return true;
7331 }
7332 break;
7333 }
7334
7335 return false;
7336 }
7337
7338 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7339 int emulation_type, void *insn, int insn_len)
7340 {
7341 int r;
7342 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7343 bool writeback = true;
7344 bool write_fault_to_spt;
7345
7346 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len)))
7347 return 1;
7348
7349 vcpu->arch.l1tf_flush_l1d = true;
7350
7351 /*
7352 * Clear write_fault_to_shadow_pgtable here to ensure it is
7353 * never reused.
7354 */
7355 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7356 vcpu->arch.write_fault_to_shadow_pgtable = false;
7357 kvm_clear_exception_queue(vcpu);
7358
7359 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7360 init_emulate_ctxt(vcpu);
7361
7362 /*
7363 * We will reenter on the same instruction since
7364 * we do not set complete_userspace_io. This does not
7365 * handle watchpoints yet, those would be handled in
7366 * the emulate_ops.
7367 */
7368 if (!(emulation_type & EMULTYPE_SKIP) &&
7369 kvm_vcpu_check_breakpoint(vcpu, &r))
7370 return r;
7371
7372 ctxt->interruptibility = 0;
7373 ctxt->have_exception = false;
7374 ctxt->exception.vector = -1;
7375 ctxt->perm_ok = false;
7376
7377 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7378
7379 r = x86_decode_insn(ctxt, insn, insn_len);
7380
7381 trace_kvm_emulate_insn_start(vcpu);
7382 ++vcpu->stat.insn_emulation;
7383 if (r != EMULATION_OK) {
7384 if ((emulation_type & EMULTYPE_TRAP_UD) ||
7385 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7386 kvm_queue_exception(vcpu, UD_VECTOR);
7387 return 1;
7388 }
7389 if (reexecute_instruction(vcpu, cr2_or_gpa,
7390 write_fault_to_spt,
7391 emulation_type))
7392 return 1;
7393 if (ctxt->have_exception) {
7394 /*
7395 * #UD should result in just EMULATION_FAILED, and trap-like
7396 * exception should not be encountered during decode.
7397 */
7398 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7399 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7400 inject_emulated_exception(vcpu);
7401 return 1;
7402 }
7403 return handle_emulation_failure(vcpu, emulation_type);
7404 }
7405 }
7406
7407 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7408 !is_vmware_backdoor_opcode(ctxt)) {
7409 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7410 return 1;
7411 }
7412
7413 /*
7414 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7415 * for kvm_skip_emulated_instruction(). The caller is responsible for
7416 * updating interruptibility state and injecting single-step #DBs.
7417 */
7418 if (emulation_type & EMULTYPE_SKIP) {
7419 kvm_rip_write(vcpu, ctxt->_eip);
7420 if (ctxt->eflags & X86_EFLAGS_RF)
7421 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7422 return 1;
7423 }
7424
7425 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7426 return 1;
7427
7428 /* this is needed for vmware backdoor interface to work since it
7429 changes registers values during IO operation */
7430 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7431 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7432 emulator_invalidate_register_cache(ctxt);
7433 }
7434
7435 restart:
7436 if (emulation_type & EMULTYPE_PF) {
7437 /* Save the faulting GPA (cr2) in the address field */
7438 ctxt->exception.address = cr2_or_gpa;
7439
7440 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7441 if (vcpu->arch.mmu->direct_map) {
7442 ctxt->gpa_available = true;
7443 ctxt->gpa_val = cr2_or_gpa;
7444 }
7445 } else {
7446 /* Sanitize the address out of an abundance of paranoia. */
7447 ctxt->exception.address = 0;
7448 }
7449
7450 r = x86_emulate_insn(ctxt);
7451
7452 if (r == EMULATION_INTERCEPTED)
7453 return 1;
7454
7455 if (r == EMULATION_FAILED) {
7456 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7457 emulation_type))
7458 return 1;
7459
7460 return handle_emulation_failure(vcpu, emulation_type);
7461 }
7462
7463 if (ctxt->have_exception) {
7464 r = 1;
7465 if (inject_emulated_exception(vcpu))
7466 return r;
7467 } else if (vcpu->arch.pio.count) {
7468 if (!vcpu->arch.pio.in) {
7469 /* FIXME: return into emulator if single-stepping. */
7470 vcpu->arch.pio.count = 0;
7471 } else {
7472 writeback = false;
7473 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7474 }
7475 r = 0;
7476 } else if (vcpu->mmio_needed) {
7477 ++vcpu->stat.mmio_exits;
7478
7479 if (!vcpu->mmio_is_write)
7480 writeback = false;
7481 r = 0;
7482 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7483 } else if (r == EMULATION_RESTART)
7484 goto restart;
7485 else
7486 r = 1;
7487
7488 if (writeback) {
7489 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7490 toggle_interruptibility(vcpu, ctxt->interruptibility);
7491 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7492 if (!ctxt->have_exception ||
7493 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7494 kvm_rip_write(vcpu, ctxt->eip);
7495 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7496 r = kvm_vcpu_do_singlestep(vcpu);
7497 if (kvm_x86_ops.update_emulated_instruction)
7498 kvm_x86_ops.update_emulated_instruction(vcpu);
7499 __kvm_set_rflags(vcpu, ctxt->eflags);
7500 }
7501
7502 /*
7503 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7504 * do nothing, and it will be requested again as soon as
7505 * the shadow expires. But we still need to check here,
7506 * because POPF has no interrupt shadow.
7507 */
7508 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7509 kvm_make_request(KVM_REQ_EVENT, vcpu);
7510 } else
7511 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7512
7513 return r;
7514 }
7515
7516 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7517 {
7518 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7519 }
7520 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7521
7522 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7523 void *insn, int insn_len)
7524 {
7525 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7526 }
7527 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7528
7529 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7530 {
7531 vcpu->arch.pio.count = 0;
7532 return 1;
7533 }
7534
7535 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7536 {
7537 vcpu->arch.pio.count = 0;
7538
7539 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7540 return 1;
7541
7542 return kvm_skip_emulated_instruction(vcpu);
7543 }
7544
7545 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7546 unsigned short port)
7547 {
7548 unsigned long val = kvm_rax_read(vcpu);
7549 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7550
7551 if (ret)
7552 return ret;
7553
7554 /*
7555 * Workaround userspace that relies on old KVM behavior of %rip being
7556 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7557 */
7558 if (port == 0x7e &&
7559 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7560 vcpu->arch.complete_userspace_io =
7561 complete_fast_pio_out_port_0x7e;
7562 kvm_skip_emulated_instruction(vcpu);
7563 } else {
7564 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7565 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7566 }
7567 return 0;
7568 }
7569
7570 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7571 {
7572 unsigned long val;
7573
7574 /* We should only ever be called with arch.pio.count equal to 1 */
7575 BUG_ON(vcpu->arch.pio.count != 1);
7576
7577 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7578 vcpu->arch.pio.count = 0;
7579 return 1;
7580 }
7581
7582 /* For size less than 4 we merge, else we zero extend */
7583 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7584
7585 /*
7586 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7587 * the copy and tracing
7588 */
7589 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7590 kvm_rax_write(vcpu, val);
7591
7592 return kvm_skip_emulated_instruction(vcpu);
7593 }
7594
7595 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7596 unsigned short port)
7597 {
7598 unsigned long val;
7599 int ret;
7600
7601 /* For size less than 4 we merge, else we zero extend */
7602 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7603
7604 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7605 if (ret) {
7606 kvm_rax_write(vcpu, val);
7607 return ret;
7608 }
7609
7610 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7611 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7612
7613 return 0;
7614 }
7615
7616 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7617 {
7618 int ret;
7619
7620 if (in)
7621 ret = kvm_fast_pio_in(vcpu, size, port);
7622 else
7623 ret = kvm_fast_pio_out(vcpu, size, port);
7624 return ret && kvm_skip_emulated_instruction(vcpu);
7625 }
7626 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7627
7628 static int kvmclock_cpu_down_prep(unsigned int cpu)
7629 {
7630 __this_cpu_write(cpu_tsc_khz, 0);
7631 return 0;
7632 }
7633
7634 static void tsc_khz_changed(void *data)
7635 {
7636 struct cpufreq_freqs *freq = data;
7637 unsigned long khz = 0;
7638
7639 if (data)
7640 khz = freq->new;
7641 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7642 khz = cpufreq_quick_get(raw_smp_processor_id());
7643 if (!khz)
7644 khz = tsc_khz;
7645 __this_cpu_write(cpu_tsc_khz, khz);
7646 }
7647
7648 #ifdef CONFIG_X86_64
7649 static void kvm_hyperv_tsc_notifier(void)
7650 {
7651 struct kvm *kvm;
7652 struct kvm_vcpu *vcpu;
7653 int cpu;
7654
7655 mutex_lock(&kvm_lock);
7656 list_for_each_entry(kvm, &vm_list, vm_list)
7657 kvm_make_mclock_inprogress_request(kvm);
7658
7659 hyperv_stop_tsc_emulation();
7660
7661 /* TSC frequency always matches when on Hyper-V */
7662 for_each_present_cpu(cpu)
7663 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7664 kvm_max_guest_tsc_khz = tsc_khz;
7665
7666 list_for_each_entry(kvm, &vm_list, vm_list) {
7667 struct kvm_arch *ka = &kvm->arch;
7668
7669 spin_lock(&ka->pvclock_gtod_sync_lock);
7670
7671 pvclock_update_vm_gtod_copy(kvm);
7672
7673 kvm_for_each_vcpu(cpu, vcpu, kvm)
7674 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7675
7676 kvm_for_each_vcpu(cpu, vcpu, kvm)
7677 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7678
7679 spin_unlock(&ka->pvclock_gtod_sync_lock);
7680 }
7681 mutex_unlock(&kvm_lock);
7682 }
7683 #endif
7684
7685 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7686 {
7687 struct kvm *kvm;
7688 struct kvm_vcpu *vcpu;
7689 int i, send_ipi = 0;
7690
7691 /*
7692 * We allow guests to temporarily run on slowing clocks,
7693 * provided we notify them after, or to run on accelerating
7694 * clocks, provided we notify them before. Thus time never
7695 * goes backwards.
7696 *
7697 * However, we have a problem. We can't atomically update
7698 * the frequency of a given CPU from this function; it is
7699 * merely a notifier, which can be called from any CPU.
7700 * Changing the TSC frequency at arbitrary points in time
7701 * requires a recomputation of local variables related to
7702 * the TSC for each VCPU. We must flag these local variables
7703 * to be updated and be sure the update takes place with the
7704 * new frequency before any guests proceed.
7705 *
7706 * Unfortunately, the combination of hotplug CPU and frequency
7707 * change creates an intractable locking scenario; the order
7708 * of when these callouts happen is undefined with respect to
7709 * CPU hotplug, and they can race with each other. As such,
7710 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7711 * undefined; you can actually have a CPU frequency change take
7712 * place in between the computation of X and the setting of the
7713 * variable. To protect against this problem, all updates of
7714 * the per_cpu tsc_khz variable are done in an interrupt
7715 * protected IPI, and all callers wishing to update the value
7716 * must wait for a synchronous IPI to complete (which is trivial
7717 * if the caller is on the CPU already). This establishes the
7718 * necessary total order on variable updates.
7719 *
7720 * Note that because a guest time update may take place
7721 * anytime after the setting of the VCPU's request bit, the
7722 * correct TSC value must be set before the request. However,
7723 * to ensure the update actually makes it to any guest which
7724 * starts running in hardware virtualization between the set
7725 * and the acquisition of the spinlock, we must also ping the
7726 * CPU after setting the request bit.
7727 *
7728 */
7729
7730 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7731
7732 mutex_lock(&kvm_lock);
7733 list_for_each_entry(kvm, &vm_list, vm_list) {
7734 kvm_for_each_vcpu(i, vcpu, kvm) {
7735 if (vcpu->cpu != cpu)
7736 continue;
7737 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7738 if (vcpu->cpu != raw_smp_processor_id())
7739 send_ipi = 1;
7740 }
7741 }
7742 mutex_unlock(&kvm_lock);
7743
7744 if (freq->old < freq->new && send_ipi) {
7745 /*
7746 * We upscale the frequency. Must make the guest
7747 * doesn't see old kvmclock values while running with
7748 * the new frequency, otherwise we risk the guest sees
7749 * time go backwards.
7750 *
7751 * In case we update the frequency for another cpu
7752 * (which might be in guest context) send an interrupt
7753 * to kick the cpu out of guest context. Next time
7754 * guest context is entered kvmclock will be updated,
7755 * so the guest will not see stale values.
7756 */
7757 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7758 }
7759 }
7760
7761 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7762 void *data)
7763 {
7764 struct cpufreq_freqs *freq = data;
7765 int cpu;
7766
7767 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7768 return 0;
7769 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7770 return 0;
7771
7772 for_each_cpu(cpu, freq->policy->cpus)
7773 __kvmclock_cpufreq_notifier(freq, cpu);
7774
7775 return 0;
7776 }
7777
7778 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7779 .notifier_call = kvmclock_cpufreq_notifier
7780 };
7781
7782 static int kvmclock_cpu_online(unsigned int cpu)
7783 {
7784 tsc_khz_changed(NULL);
7785 return 0;
7786 }
7787
7788 static void kvm_timer_init(void)
7789 {
7790 max_tsc_khz = tsc_khz;
7791
7792 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7793 #ifdef CONFIG_CPU_FREQ
7794 struct cpufreq_policy *policy;
7795 int cpu;
7796
7797 cpu = get_cpu();
7798 policy = cpufreq_cpu_get(cpu);
7799 if (policy) {
7800 if (policy->cpuinfo.max_freq)
7801 max_tsc_khz = policy->cpuinfo.max_freq;
7802 cpufreq_cpu_put(policy);
7803 }
7804 put_cpu();
7805 #endif
7806 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7807 CPUFREQ_TRANSITION_NOTIFIER);
7808 }
7809
7810 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7811 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7812 }
7813
7814 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7815 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7816
7817 int kvm_is_in_guest(void)
7818 {
7819 return __this_cpu_read(current_vcpu) != NULL;
7820 }
7821
7822 static int kvm_is_user_mode(void)
7823 {
7824 int user_mode = 3;
7825
7826 if (__this_cpu_read(current_vcpu))
7827 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7828
7829 return user_mode != 0;
7830 }
7831
7832 static unsigned long kvm_get_guest_ip(void)
7833 {
7834 unsigned long ip = 0;
7835
7836 if (__this_cpu_read(current_vcpu))
7837 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7838
7839 return ip;
7840 }
7841
7842 static void kvm_handle_intel_pt_intr(void)
7843 {
7844 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7845
7846 kvm_make_request(KVM_REQ_PMI, vcpu);
7847 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7848 (unsigned long *)&vcpu->arch.pmu.global_status);
7849 }
7850
7851 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7852 .is_in_guest = kvm_is_in_guest,
7853 .is_user_mode = kvm_is_user_mode,
7854 .get_guest_ip = kvm_get_guest_ip,
7855 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7856 };
7857
7858 #ifdef CONFIG_X86_64
7859 static void pvclock_gtod_update_fn(struct work_struct *work)
7860 {
7861 struct kvm *kvm;
7862
7863 struct kvm_vcpu *vcpu;
7864 int i;
7865
7866 mutex_lock(&kvm_lock);
7867 list_for_each_entry(kvm, &vm_list, vm_list)
7868 kvm_for_each_vcpu(i, vcpu, kvm)
7869 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7870 atomic_set(&kvm_guest_has_master_clock, 0);
7871 mutex_unlock(&kvm_lock);
7872 }
7873
7874 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7875
7876 /*
7877 * Notification about pvclock gtod data update.
7878 */
7879 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7880 void *priv)
7881 {
7882 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7883 struct timekeeper *tk = priv;
7884
7885 update_pvclock_gtod(tk);
7886
7887 /* disable master clock if host does not trust, or does not
7888 * use, TSC based clocksource.
7889 */
7890 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7891 atomic_read(&kvm_guest_has_master_clock) != 0)
7892 queue_work(system_long_wq, &pvclock_gtod_work);
7893
7894 return 0;
7895 }
7896
7897 static struct notifier_block pvclock_gtod_notifier = {
7898 .notifier_call = pvclock_gtod_notify,
7899 };
7900 #endif
7901
7902 int kvm_arch_init(void *opaque)
7903 {
7904 struct kvm_x86_init_ops *ops = opaque;
7905 int r;
7906
7907 if (kvm_x86_ops.hardware_enable) {
7908 printk(KERN_ERR "kvm: already loaded the other module\n");
7909 r = -EEXIST;
7910 goto out;
7911 }
7912
7913 if (!ops->cpu_has_kvm_support()) {
7914 pr_err_ratelimited("kvm: no hardware support\n");
7915 r = -EOPNOTSUPP;
7916 goto out;
7917 }
7918 if (ops->disabled_by_bios()) {
7919 pr_warn_ratelimited("kvm: disabled by bios\n");
7920 r = -EOPNOTSUPP;
7921 goto out;
7922 }
7923
7924 /*
7925 * KVM explicitly assumes that the guest has an FPU and
7926 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7927 * vCPU's FPU state as a fxregs_state struct.
7928 */
7929 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7930 printk(KERN_ERR "kvm: inadequate fpu\n");
7931 r = -EOPNOTSUPP;
7932 goto out;
7933 }
7934
7935 r = -ENOMEM;
7936 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7937 __alignof__(struct fpu), SLAB_ACCOUNT,
7938 NULL);
7939 if (!x86_fpu_cache) {
7940 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7941 goto out;
7942 }
7943
7944 x86_emulator_cache = kvm_alloc_emulator_cache();
7945 if (!x86_emulator_cache) {
7946 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7947 goto out_free_x86_fpu_cache;
7948 }
7949
7950 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7951 if (!user_return_msrs) {
7952 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7953 goto out_free_x86_emulator_cache;
7954 }
7955
7956 r = kvm_mmu_module_init();
7957 if (r)
7958 goto out_free_percpu;
7959
7960 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7961 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7962 PT_PRESENT_MASK, 0, sme_me_mask);
7963 kvm_timer_init();
7964
7965 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7966
7967 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7968 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7969 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7970 }
7971
7972 kvm_lapic_init();
7973 if (pi_inject_timer == -1)
7974 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7975 #ifdef CONFIG_X86_64
7976 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7977
7978 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7979 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7980 #endif
7981
7982 return 0;
7983
7984 out_free_percpu:
7985 free_percpu(user_return_msrs);
7986 out_free_x86_emulator_cache:
7987 kmem_cache_destroy(x86_emulator_cache);
7988 out_free_x86_fpu_cache:
7989 kmem_cache_destroy(x86_fpu_cache);
7990 out:
7991 return r;
7992 }
7993
7994 void kvm_arch_exit(void)
7995 {
7996 #ifdef CONFIG_X86_64
7997 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7998 clear_hv_tscchange_cb();
7999 #endif
8000 kvm_lapic_exit();
8001 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
8002
8003 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8004 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
8005 CPUFREQ_TRANSITION_NOTIFIER);
8006 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
8007 #ifdef CONFIG_X86_64
8008 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
8009 #endif
8010 kvm_x86_ops.hardware_enable = NULL;
8011 kvm_mmu_module_exit();
8012 free_percpu(user_return_msrs);
8013 kmem_cache_destroy(x86_fpu_cache);
8014 }
8015
8016 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason)
8017 {
8018 ++vcpu->stat.halt_exits;
8019 if (lapic_in_kernel(vcpu)) {
8020 vcpu->arch.mp_state = state;
8021 return 1;
8022 } else {
8023 vcpu->run->exit_reason = reason;
8024 return 0;
8025 }
8026 }
8027
8028 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8029 {
8030 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
8031 }
8032 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
8033
8034 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
8035 {
8036 int ret = kvm_skip_emulated_instruction(vcpu);
8037 /*
8038 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
8039 * KVM_EXIT_DEBUG here.
8040 */
8041 return kvm_vcpu_halt(vcpu) && ret;
8042 }
8043 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
8044
8045 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
8046 {
8047 int ret = kvm_skip_emulated_instruction(vcpu);
8048
8049 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret;
8050 }
8051 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
8052
8053 #ifdef CONFIG_X86_64
8054 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
8055 unsigned long clock_type)
8056 {
8057 struct kvm_clock_pairing clock_pairing;
8058 struct timespec64 ts;
8059 u64 cycle;
8060 int ret;
8061
8062 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
8063 return -KVM_EOPNOTSUPP;
8064
8065 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
8066 return -KVM_EOPNOTSUPP;
8067
8068 clock_pairing.sec = ts.tv_sec;
8069 clock_pairing.nsec = ts.tv_nsec;
8070 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
8071 clock_pairing.flags = 0;
8072 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
8073
8074 ret = 0;
8075 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
8076 sizeof(struct kvm_clock_pairing)))
8077 ret = -KVM_EFAULT;
8078
8079 return ret;
8080 }
8081 #endif
8082
8083 /*
8084 * kvm_pv_kick_cpu_op: Kick a vcpu.
8085 *
8086 * @apicid - apicid of vcpu to be kicked.
8087 */
8088 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
8089 {
8090 struct kvm_lapic_irq lapic_irq;
8091
8092 lapic_irq.shorthand = APIC_DEST_NOSHORT;
8093 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
8094 lapic_irq.level = 0;
8095 lapic_irq.dest_id = apicid;
8096 lapic_irq.msi_redir_hint = false;
8097
8098 lapic_irq.delivery_mode = APIC_DM_REMRD;
8099 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
8100 }
8101
8102 bool kvm_apicv_activated(struct kvm *kvm)
8103 {
8104 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
8105 }
8106 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
8107
8108 void kvm_apicv_init(struct kvm *kvm, bool enable)
8109 {
8110 if (enable)
8111 clear_bit(APICV_INHIBIT_REASON_DISABLE,
8112 &kvm->arch.apicv_inhibit_reasons);
8113 else
8114 set_bit(APICV_INHIBIT_REASON_DISABLE,
8115 &kvm->arch.apicv_inhibit_reasons);
8116 }
8117 EXPORT_SYMBOL_GPL(kvm_apicv_init);
8118
8119 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
8120 {
8121 struct kvm_vcpu *target = NULL;
8122 struct kvm_apic_map *map;
8123
8124 rcu_read_lock();
8125 map = rcu_dereference(kvm->arch.apic_map);
8126
8127 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
8128 target = map->phys_map[dest_id]->vcpu;
8129
8130 rcu_read_unlock();
8131
8132 if (target && READ_ONCE(target->ready))
8133 kvm_vcpu_yield_to(target);
8134 }
8135
8136 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
8137 {
8138 unsigned long nr, a0, a1, a2, a3, ret;
8139 int op_64_bit;
8140
8141 if (kvm_hv_hypercall_enabled(vcpu->kvm))
8142 return kvm_hv_hypercall(vcpu);
8143
8144 nr = kvm_rax_read(vcpu);
8145 a0 = kvm_rbx_read(vcpu);
8146 a1 = kvm_rcx_read(vcpu);
8147 a2 = kvm_rdx_read(vcpu);
8148 a3 = kvm_rsi_read(vcpu);
8149
8150 trace_kvm_hypercall(nr, a0, a1, a2, a3);
8151
8152 op_64_bit = is_64_bit_mode(vcpu);
8153 if (!op_64_bit) {
8154 nr &= 0xFFFFFFFF;
8155 a0 &= 0xFFFFFFFF;
8156 a1 &= 0xFFFFFFFF;
8157 a2 &= 0xFFFFFFFF;
8158 a3 &= 0xFFFFFFFF;
8159 }
8160
8161 if (kvm_x86_ops.get_cpl(vcpu) != 0) {
8162 ret = -KVM_EPERM;
8163 goto out;
8164 }
8165
8166 ret = -KVM_ENOSYS;
8167
8168 switch (nr) {
8169 case KVM_HC_VAPIC_POLL_IRQ:
8170 ret = 0;
8171 break;
8172 case KVM_HC_KICK_CPU:
8173 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
8174 break;
8175
8176 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8177 kvm_sched_yield(vcpu->kvm, a1);
8178 ret = 0;
8179 break;
8180 #ifdef CONFIG_X86_64
8181 case KVM_HC_CLOCK_PAIRING:
8182 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8183 break;
8184 #endif
8185 case KVM_HC_SEND_IPI:
8186 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
8187 break;
8188
8189 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8190 break;
8191 case KVM_HC_SCHED_YIELD:
8192 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
8193 break;
8194
8195 kvm_sched_yield(vcpu->kvm, a0);
8196 ret = 0;
8197 break;
8198 default:
8199 ret = -KVM_ENOSYS;
8200 break;
8201 }
8202 out:
8203 if (!op_64_bit)
8204 ret = (u32)ret;
8205 kvm_rax_write(vcpu, ret);
8206
8207 ++vcpu->stat.hypercalls;
8208 return kvm_skip_emulated_instruction(vcpu);
8209 }
8210 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8211
8212 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8213 {
8214 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8215 char instruction[3];
8216 unsigned long rip = kvm_rip_read(vcpu);
8217
8218 kvm_x86_ops.patch_hypercall(vcpu, instruction);
8219
8220 return emulator_write_emulated(ctxt, rip, instruction, 3,
8221 &ctxt->exception);
8222 }
8223
8224 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8225 {
8226 return vcpu->run->request_interrupt_window &&
8227 likely(!pic_in_kernel(vcpu->kvm));
8228 }
8229
8230 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8231 {
8232 struct kvm_run *kvm_run = vcpu->run;
8233
8234 /*
8235 * if_flag is obsolete and useless, so do not bother
8236 * setting it for SEV-ES guests. Userspace can just
8237 * use kvm_run->ready_for_interrupt_injection.
8238 */
8239 kvm_run->if_flag = !vcpu->arch.guest_state_protected
8240 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8241
8242 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
8243 kvm_run->cr8 = kvm_get_cr8(vcpu);
8244 kvm_run->apic_base = kvm_get_apic_base(vcpu);
8245 kvm_run->ready_for_interrupt_injection =
8246 pic_in_kernel(vcpu->kvm) ||
8247 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8248 }
8249
8250 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8251 {
8252 int max_irr, tpr;
8253
8254 if (!kvm_x86_ops.update_cr8_intercept)
8255 return;
8256
8257 if (!lapic_in_kernel(vcpu))
8258 return;
8259
8260 if (vcpu->arch.apicv_active)
8261 return;
8262
8263 if (!vcpu->arch.apic->vapic_addr)
8264 max_irr = kvm_lapic_find_highest_irr(vcpu);
8265 else
8266 max_irr = -1;
8267
8268 if (max_irr != -1)
8269 max_irr >>= 4;
8270
8271 tpr = kvm_lapic_get_cr8(vcpu);
8272
8273 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
8274 }
8275
8276 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8277 {
8278 int r;
8279 bool can_inject = true;
8280
8281 /* try to reinject previous events if any */
8282
8283 if (vcpu->arch.exception.injected) {
8284 kvm_x86_ops.queue_exception(vcpu);
8285 can_inject = false;
8286 }
8287 /*
8288 * Do not inject an NMI or interrupt if there is a pending
8289 * exception. Exceptions and interrupts are recognized at
8290 * instruction boundaries, i.e. the start of an instruction.
8291 * Trap-like exceptions, e.g. #DB, have higher priority than
8292 * NMIs and interrupts, i.e. traps are recognized before an
8293 * NMI/interrupt that's pending on the same instruction.
8294 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8295 * priority, but are only generated (pended) during instruction
8296 * execution, i.e. a pending fault-like exception means the
8297 * fault occurred on the *previous* instruction and must be
8298 * serviced prior to recognizing any new events in order to
8299 * fully complete the previous instruction.
8300 */
8301 else if (!vcpu->arch.exception.pending) {
8302 if (vcpu->arch.nmi_injected) {
8303 kvm_x86_ops.set_nmi(vcpu);
8304 can_inject = false;
8305 } else if (vcpu->arch.interrupt.injected) {
8306 kvm_x86_ops.set_irq(vcpu);
8307 can_inject = false;
8308 }
8309 }
8310
8311 WARN_ON_ONCE(vcpu->arch.exception.injected &&
8312 vcpu->arch.exception.pending);
8313
8314 /*
8315 * Call check_nested_events() even if we reinjected a previous event
8316 * in order for caller to determine if it should require immediate-exit
8317 * from L2 to L1 due to pending L1 events which require exit
8318 * from L2 to L1.
8319 */
8320 if (is_guest_mode(vcpu)) {
8321 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8322 if (r < 0)
8323 goto busy;
8324 }
8325
8326 /* try to inject new event if pending */
8327 if (vcpu->arch.exception.pending) {
8328 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8329 vcpu->arch.exception.has_error_code,
8330 vcpu->arch.exception.error_code);
8331
8332 vcpu->arch.exception.pending = false;
8333 vcpu->arch.exception.injected = true;
8334
8335 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8336 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8337 X86_EFLAGS_RF);
8338
8339 if (vcpu->arch.exception.nr == DB_VECTOR) {
8340 kvm_deliver_exception_payload(vcpu);
8341 if (vcpu->arch.dr7 & DR7_GD) {
8342 vcpu->arch.dr7 &= ~DR7_GD;
8343 kvm_update_dr7(vcpu);
8344 }
8345 }
8346
8347 kvm_x86_ops.queue_exception(vcpu);
8348 can_inject = false;
8349 }
8350
8351 /*
8352 * Finally, inject interrupt events. If an event cannot be injected
8353 * due to architectural conditions (e.g. IF=0) a window-open exit
8354 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
8355 * and can architecturally be injected, but we cannot do it right now:
8356 * an interrupt could have arrived just now and we have to inject it
8357 * as a vmexit, or there could already an event in the queue, which is
8358 * indicated by can_inject. In that case we request an immediate exit
8359 * in order to make progress and get back here for another iteration.
8360 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8361 */
8362 if (vcpu->arch.smi_pending) {
8363 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
8364 if (r < 0)
8365 goto busy;
8366 if (r) {
8367 vcpu->arch.smi_pending = false;
8368 ++vcpu->arch.smi_count;
8369 enter_smm(vcpu);
8370 can_inject = false;
8371 } else
8372 kvm_x86_ops.enable_smi_window(vcpu);
8373 }
8374
8375 if (vcpu->arch.nmi_pending) {
8376 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
8377 if (r < 0)
8378 goto busy;
8379 if (r) {
8380 --vcpu->arch.nmi_pending;
8381 vcpu->arch.nmi_injected = true;
8382 kvm_x86_ops.set_nmi(vcpu);
8383 can_inject = false;
8384 WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
8385 }
8386 if (vcpu->arch.nmi_pending)
8387 kvm_x86_ops.enable_nmi_window(vcpu);
8388 }
8389
8390 if (kvm_cpu_has_injectable_intr(vcpu)) {
8391 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
8392 if (r < 0)
8393 goto busy;
8394 if (r) {
8395 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8396 kvm_x86_ops.set_irq(vcpu);
8397 WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
8398 }
8399 if (kvm_cpu_has_injectable_intr(vcpu))
8400 kvm_x86_ops.enable_irq_window(vcpu);
8401 }
8402
8403 if (is_guest_mode(vcpu) &&
8404 kvm_x86_ops.nested_ops->hv_timer_pending &&
8405 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8406 *req_immediate_exit = true;
8407
8408 WARN_ON(vcpu->arch.exception.pending);
8409 return;
8410
8411 busy:
8412 *req_immediate_exit = true;
8413 return;
8414 }
8415
8416 static void process_nmi(struct kvm_vcpu *vcpu)
8417 {
8418 unsigned limit = 2;
8419
8420 /*
8421 * x86 is limited to one NMI running, and one NMI pending after it.
8422 * If an NMI is already in progress, limit further NMIs to just one.
8423 * Otherwise, allow two (and we'll inject the first one immediately).
8424 */
8425 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
8426 limit = 1;
8427
8428 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8429 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8430 kvm_make_request(KVM_REQ_EVENT, vcpu);
8431 }
8432
8433 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8434 {
8435 u32 flags = 0;
8436 flags |= seg->g << 23;
8437 flags |= seg->db << 22;
8438 flags |= seg->l << 21;
8439 flags |= seg->avl << 20;
8440 flags |= seg->present << 15;
8441 flags |= seg->dpl << 13;
8442 flags |= seg->s << 12;
8443 flags |= seg->type << 8;
8444 return flags;
8445 }
8446
8447 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8448 {
8449 struct kvm_segment seg;
8450 int offset;
8451
8452 kvm_get_segment(vcpu, &seg, n);
8453 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8454
8455 if (n < 3)
8456 offset = 0x7f84 + n * 12;
8457 else
8458 offset = 0x7f2c + (n - 3) * 12;
8459
8460 put_smstate(u32, buf, offset + 8, seg.base);
8461 put_smstate(u32, buf, offset + 4, seg.limit);
8462 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8463 }
8464
8465 #ifdef CONFIG_X86_64
8466 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8467 {
8468 struct kvm_segment seg;
8469 int offset;
8470 u16 flags;
8471
8472 kvm_get_segment(vcpu, &seg, n);
8473 offset = 0x7e00 + n * 16;
8474
8475 flags = enter_smm_get_segment_flags(&seg) >> 8;
8476 put_smstate(u16, buf, offset, seg.selector);
8477 put_smstate(u16, buf, offset + 2, flags);
8478 put_smstate(u32, buf, offset + 4, seg.limit);
8479 put_smstate(u64, buf, offset + 8, seg.base);
8480 }
8481 #endif
8482
8483 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8484 {
8485 struct desc_ptr dt;
8486 struct kvm_segment seg;
8487 unsigned long val;
8488 int i;
8489
8490 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8491 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8492 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8493 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8494
8495 for (i = 0; i < 8; i++)
8496 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8497
8498 kvm_get_dr(vcpu, 6, &val);
8499 put_smstate(u32, buf, 0x7fcc, (u32)val);
8500 kvm_get_dr(vcpu, 7, &val);
8501 put_smstate(u32, buf, 0x7fc8, (u32)val);
8502
8503 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8504 put_smstate(u32, buf, 0x7fc4, seg.selector);
8505 put_smstate(u32, buf, 0x7f64, seg.base);
8506 put_smstate(u32, buf, 0x7f60, seg.limit);
8507 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8508
8509 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8510 put_smstate(u32, buf, 0x7fc0, seg.selector);
8511 put_smstate(u32, buf, 0x7f80, seg.base);
8512 put_smstate(u32, buf, 0x7f7c, seg.limit);
8513 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8514
8515 kvm_x86_ops.get_gdt(vcpu, &dt);
8516 put_smstate(u32, buf, 0x7f74, dt.address);
8517 put_smstate(u32, buf, 0x7f70, dt.size);
8518
8519 kvm_x86_ops.get_idt(vcpu, &dt);
8520 put_smstate(u32, buf, 0x7f58, dt.address);
8521 put_smstate(u32, buf, 0x7f54, dt.size);
8522
8523 for (i = 0; i < 6; i++)
8524 enter_smm_save_seg_32(vcpu, buf, i);
8525
8526 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8527
8528 /* revision id */
8529 put_smstate(u32, buf, 0x7efc, 0x00020000);
8530 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8531 }
8532
8533 #ifdef CONFIG_X86_64
8534 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8535 {
8536 struct desc_ptr dt;
8537 struct kvm_segment seg;
8538 unsigned long val;
8539 int i;
8540
8541 for (i = 0; i < 16; i++)
8542 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8543
8544 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8545 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8546
8547 kvm_get_dr(vcpu, 6, &val);
8548 put_smstate(u64, buf, 0x7f68, val);
8549 kvm_get_dr(vcpu, 7, &val);
8550 put_smstate(u64, buf, 0x7f60, val);
8551
8552 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8553 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8554 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8555
8556 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8557
8558 /* revision id */
8559 put_smstate(u32, buf, 0x7efc, 0x00020064);
8560
8561 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8562
8563 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8564 put_smstate(u16, buf, 0x7e90, seg.selector);
8565 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8566 put_smstate(u32, buf, 0x7e94, seg.limit);
8567 put_smstate(u64, buf, 0x7e98, seg.base);
8568
8569 kvm_x86_ops.get_idt(vcpu, &dt);
8570 put_smstate(u32, buf, 0x7e84, dt.size);
8571 put_smstate(u64, buf, 0x7e88, dt.address);
8572
8573 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8574 put_smstate(u16, buf, 0x7e70, seg.selector);
8575 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8576 put_smstate(u32, buf, 0x7e74, seg.limit);
8577 put_smstate(u64, buf, 0x7e78, seg.base);
8578
8579 kvm_x86_ops.get_gdt(vcpu, &dt);
8580 put_smstate(u32, buf, 0x7e64, dt.size);
8581 put_smstate(u64, buf, 0x7e68, dt.address);
8582
8583 for (i = 0; i < 6; i++)
8584 enter_smm_save_seg_64(vcpu, buf, i);
8585 }
8586 #endif
8587
8588 static void enter_smm(struct kvm_vcpu *vcpu)
8589 {
8590 struct kvm_segment cs, ds;
8591 struct desc_ptr dt;
8592 char buf[512];
8593 u32 cr0;
8594
8595 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8596 memset(buf, 0, 512);
8597 #ifdef CONFIG_X86_64
8598 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8599 enter_smm_save_state_64(vcpu, buf);
8600 else
8601 #endif
8602 enter_smm_save_state_32(vcpu, buf);
8603
8604 /*
8605 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8606 * vCPU state (e.g. leave guest mode) after we've saved the state into
8607 * the SMM state-save area.
8608 */
8609 kvm_x86_ops.pre_enter_smm(vcpu, buf);
8610
8611 vcpu->arch.hflags |= HF_SMM_MASK;
8612 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8613
8614 if (kvm_x86_ops.get_nmi_mask(vcpu))
8615 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8616 else
8617 kvm_x86_ops.set_nmi_mask(vcpu, true);
8618
8619 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8620 kvm_rip_write(vcpu, 0x8000);
8621
8622 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8623 kvm_x86_ops.set_cr0(vcpu, cr0);
8624 vcpu->arch.cr0 = cr0;
8625
8626 kvm_x86_ops.set_cr4(vcpu, 0);
8627
8628 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8629 dt.address = dt.size = 0;
8630 kvm_x86_ops.set_idt(vcpu, &dt);
8631
8632 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8633
8634 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8635 cs.base = vcpu->arch.smbase;
8636
8637 ds.selector = 0;
8638 ds.base = 0;
8639
8640 cs.limit = ds.limit = 0xffffffff;
8641 cs.type = ds.type = 0x3;
8642 cs.dpl = ds.dpl = 0;
8643 cs.db = ds.db = 0;
8644 cs.s = ds.s = 1;
8645 cs.l = ds.l = 0;
8646 cs.g = ds.g = 1;
8647 cs.avl = ds.avl = 0;
8648 cs.present = ds.present = 1;
8649 cs.unusable = ds.unusable = 0;
8650 cs.padding = ds.padding = 0;
8651
8652 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8653 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8654 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8655 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8656 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8657 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8658
8659 #ifdef CONFIG_X86_64
8660 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8661 kvm_x86_ops.set_efer(vcpu, 0);
8662 #endif
8663
8664 kvm_update_cpuid_runtime(vcpu);
8665 kvm_mmu_reset_context(vcpu);
8666 }
8667
8668 static void process_smi(struct kvm_vcpu *vcpu)
8669 {
8670 vcpu->arch.smi_pending = true;
8671 kvm_make_request(KVM_REQ_EVENT, vcpu);
8672 }
8673
8674 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8675 unsigned long *vcpu_bitmap)
8676 {
8677 cpumask_var_t cpus;
8678
8679 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8680
8681 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8682 NULL, vcpu_bitmap, cpus);
8683
8684 free_cpumask_var(cpus);
8685 }
8686
8687 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8688 {
8689 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8690 }
8691
8692 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8693 {
8694 if (!lapic_in_kernel(vcpu))
8695 return;
8696
8697 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8698 kvm_apic_update_apicv(vcpu);
8699 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8700 }
8701 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8702
8703 /*
8704 * NOTE: Do not hold any lock prior to calling this.
8705 *
8706 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8707 * locked, because it calls __x86_set_memory_region() which does
8708 * synchronize_srcu(&kvm->srcu).
8709 */
8710 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8711 {
8712 struct kvm_vcpu *except;
8713 unsigned long old, new, expected;
8714
8715 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8716 !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8717 return;
8718
8719 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8720 do {
8721 expected = new = old;
8722 if (activate)
8723 __clear_bit(bit, &new);
8724 else
8725 __set_bit(bit, &new);
8726 if (new == old)
8727 break;
8728 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8729 } while (old != expected);
8730
8731 if (!!old == !!new)
8732 return;
8733
8734 trace_kvm_apicv_update_request(activate, bit);
8735 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8736 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8737
8738 /*
8739 * Sending request to update APICV for all other vcpus,
8740 * while update the calling vcpu immediately instead of
8741 * waiting for another #VMEXIT to handle the request.
8742 */
8743 except = kvm_get_running_vcpu();
8744 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8745 except);
8746 if (except)
8747 kvm_vcpu_update_apicv(except);
8748 }
8749 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8750
8751 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8752 {
8753 if (!kvm_apic_present(vcpu))
8754 return;
8755
8756 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8757
8758 if (irqchip_split(vcpu->kvm))
8759 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8760 else {
8761 if (vcpu->arch.apicv_active)
8762 kvm_x86_ops.sync_pir_to_irr(vcpu);
8763 if (ioapic_in_kernel(vcpu->kvm))
8764 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8765 }
8766
8767 if (is_guest_mode(vcpu))
8768 vcpu->arch.load_eoi_exitmap_pending = true;
8769 else
8770 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8771 }
8772
8773 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8774 {
8775 u64 eoi_exit_bitmap[4];
8776
8777 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8778 return;
8779
8780 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8781 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8782 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8783 }
8784
8785 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8786 unsigned long start, unsigned long end)
8787 {
8788 unsigned long apic_address;
8789
8790 /*
8791 * The physical address of apic access page is stored in the VMCS.
8792 * Update it when it becomes invalid.
8793 */
8794 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8795 if (start <= apic_address && apic_address < end)
8796 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8797 }
8798
8799 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8800 {
8801 if (!lapic_in_kernel(vcpu))
8802 return;
8803
8804 if (!kvm_x86_ops.set_apic_access_page_addr)
8805 return;
8806
8807 kvm_x86_ops.set_apic_access_page_addr(vcpu);
8808 }
8809
8810 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8811 {
8812 smp_send_reschedule(vcpu->cpu);
8813 }
8814 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8815
8816 /*
8817 * Returns 1 to let vcpu_run() continue the guest execution loop without
8818 * exiting to the userspace. Otherwise, the value will be returned to the
8819 * userspace.
8820 */
8821 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8822 {
8823 int r;
8824 bool req_int_win =
8825 dm_request_for_irq_injection(vcpu) &&
8826 kvm_cpu_accept_dm_intr(vcpu);
8827 fastpath_t exit_fastpath;
8828
8829 bool req_immediate_exit = false;
8830
8831 /* Forbid vmenter if vcpu dirty ring is soft-full */
8832 if (unlikely(vcpu->kvm->dirty_ring_size &&
8833 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
8834 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
8835 trace_kvm_dirty_ring_exit(vcpu);
8836 r = 0;
8837 goto out;
8838 }
8839
8840 if (kvm_request_pending(vcpu)) {
8841 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8842 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8843 r = 0;
8844 goto out;
8845 }
8846 }
8847 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8848 kvm_mmu_unload(vcpu);
8849 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8850 __kvm_migrate_timers(vcpu);
8851 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8852 kvm_gen_update_masterclock(vcpu->kvm);
8853 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8854 kvm_gen_kvmclock_update(vcpu);
8855 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8856 r = kvm_guest_time_update(vcpu);
8857 if (unlikely(r))
8858 goto out;
8859 }
8860 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8861 kvm_mmu_sync_roots(vcpu);
8862 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8863 kvm_mmu_load_pgd(vcpu);
8864 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8865 kvm_vcpu_flush_tlb_all(vcpu);
8866
8867 /* Flushing all ASIDs flushes the current ASID... */
8868 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8869 }
8870 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8871 kvm_vcpu_flush_tlb_current(vcpu);
8872 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8873 kvm_vcpu_flush_tlb_guest(vcpu);
8874
8875 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8876 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8877 r = 0;
8878 goto out;
8879 }
8880 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8881 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8882 vcpu->mmio_needed = 0;
8883 r = 0;
8884 goto out;
8885 }
8886 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8887 /* Page is swapped out. Do synthetic halt */
8888 vcpu->arch.apf.halted = true;
8889 r = 1;
8890 goto out;
8891 }
8892 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8893 record_steal_time(vcpu);
8894 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8895 process_smi(vcpu);
8896 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8897 process_nmi(vcpu);
8898 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8899 kvm_pmu_handle_event(vcpu);
8900 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8901 kvm_pmu_deliver_pmi(vcpu);
8902 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8903 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8904 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8905 vcpu->arch.ioapic_handled_vectors)) {
8906 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8907 vcpu->run->eoi.vector =
8908 vcpu->arch.pending_ioapic_eoi;
8909 r = 0;
8910 goto out;
8911 }
8912 }
8913 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8914 vcpu_scan_ioapic(vcpu);
8915 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8916 vcpu_load_eoi_exitmap(vcpu);
8917 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8918 kvm_vcpu_reload_apic_access_page(vcpu);
8919 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8920 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8921 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8922 r = 0;
8923 goto out;
8924 }
8925 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8926 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8927 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8928 r = 0;
8929 goto out;
8930 }
8931 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8932 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8933 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8934 r = 0;
8935 goto out;
8936 }
8937
8938 /*
8939 * KVM_REQ_HV_STIMER has to be processed after
8940 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8941 * depend on the guest clock being up-to-date
8942 */
8943 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8944 kvm_hv_process_stimers(vcpu);
8945 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8946 kvm_vcpu_update_apicv(vcpu);
8947 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8948 kvm_check_async_pf_completion(vcpu);
8949 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8950 kvm_x86_ops.msr_filter_changed(vcpu);
8951 }
8952
8953 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8954 ++vcpu->stat.req_event;
8955 kvm_apic_accept_events(vcpu);
8956 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8957 r = 1;
8958 goto out;
8959 }
8960
8961 inject_pending_event(vcpu, &req_immediate_exit);
8962 if (req_int_win)
8963 kvm_x86_ops.enable_irq_window(vcpu);
8964
8965 if (kvm_lapic_enabled(vcpu)) {
8966 update_cr8_intercept(vcpu);
8967 kvm_lapic_sync_to_vapic(vcpu);
8968 }
8969 }
8970
8971 r = kvm_mmu_reload(vcpu);
8972 if (unlikely(r)) {
8973 goto cancel_injection;
8974 }
8975
8976 preempt_disable();
8977
8978 kvm_x86_ops.prepare_guest_switch(vcpu);
8979
8980 /*
8981 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8982 * IPI are then delayed after guest entry, which ensures that they
8983 * result in virtual interrupt delivery.
8984 */
8985 local_irq_disable();
8986 vcpu->mode = IN_GUEST_MODE;
8987
8988 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8989
8990 /*
8991 * 1) We should set ->mode before checking ->requests. Please see
8992 * the comment in kvm_vcpu_exiting_guest_mode().
8993 *
8994 * 2) For APICv, we should set ->mode before checking PID.ON. This
8995 * pairs with the memory barrier implicit in pi_test_and_set_on
8996 * (see vmx_deliver_posted_interrupt).
8997 *
8998 * 3) This also orders the write to mode from any reads to the page
8999 * tables done while the VCPU is running. Please see the comment
9000 * in kvm_flush_remote_tlbs.
9001 */
9002 smp_mb__after_srcu_read_unlock();
9003
9004 /*
9005 * This handles the case where a posted interrupt was
9006 * notified with kvm_vcpu_kick.
9007 */
9008 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
9009 kvm_x86_ops.sync_pir_to_irr(vcpu);
9010
9011 if (kvm_vcpu_exit_request(vcpu)) {
9012 vcpu->mode = OUTSIDE_GUEST_MODE;
9013 smp_wmb();
9014 local_irq_enable();
9015 preempt_enable();
9016 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9017 r = 1;
9018 goto cancel_injection;
9019 }
9020
9021 if (req_immediate_exit) {
9022 kvm_make_request(KVM_REQ_EVENT, vcpu);
9023 kvm_x86_ops.request_immediate_exit(vcpu);
9024 }
9025
9026 fpregs_assert_state_consistent();
9027 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9028 switch_fpu_return();
9029
9030 if (unlikely(vcpu->arch.switch_db_regs)) {
9031 set_debugreg(0, 7);
9032 set_debugreg(vcpu->arch.eff_db[0], 0);
9033 set_debugreg(vcpu->arch.eff_db[1], 1);
9034 set_debugreg(vcpu->arch.eff_db[2], 2);
9035 set_debugreg(vcpu->arch.eff_db[3], 3);
9036 set_debugreg(vcpu->arch.dr6, 6);
9037 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9038 }
9039
9040 exit_fastpath = kvm_x86_ops.run(vcpu);
9041
9042 /*
9043 * Do this here before restoring debug registers on the host. And
9044 * since we do this before handling the vmexit, a DR access vmexit
9045 * can (a) read the correct value of the debug registers, (b) set
9046 * KVM_DEBUGREG_WONT_EXIT again.
9047 */
9048 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
9049 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
9050 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
9051 kvm_update_dr0123(vcpu);
9052 kvm_update_dr7(vcpu);
9053 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9054 }
9055
9056 /*
9057 * If the guest has used debug registers, at least dr7
9058 * will be disabled while returning to the host.
9059 * If we don't have active breakpoints in the host, we don't
9060 * care about the messed up debug address registers. But if
9061 * we have some of them active, restore the old state.
9062 */
9063 if (hw_breakpoint_active())
9064 hw_breakpoint_restore();
9065
9066 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
9067 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
9068
9069 vcpu->mode = OUTSIDE_GUEST_MODE;
9070 smp_wmb();
9071
9072 kvm_x86_ops.handle_exit_irqoff(vcpu);
9073
9074 /*
9075 * Consume any pending interrupts, including the possible source of
9076 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
9077 * An instruction is required after local_irq_enable() to fully unblock
9078 * interrupts on processors that implement an interrupt shadow, the
9079 * stat.exits increment will do nicely.
9080 */
9081 kvm_before_interrupt(vcpu);
9082 local_irq_enable();
9083 ++vcpu->stat.exits;
9084 local_irq_disable();
9085 kvm_after_interrupt(vcpu);
9086
9087 if (lapic_in_kernel(vcpu)) {
9088 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
9089 if (delta != S64_MIN) {
9090 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
9091 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
9092 }
9093 }
9094
9095 local_irq_enable();
9096 preempt_enable();
9097
9098 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9099
9100 /*
9101 * Profile KVM exit RIPs:
9102 */
9103 if (unlikely(prof_on == KVM_PROFILING)) {
9104 unsigned long rip = kvm_rip_read(vcpu);
9105 profile_hit(KVM_PROFILING, (void *)rip);
9106 }
9107
9108 if (unlikely(vcpu->arch.tsc_always_catchup))
9109 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9110
9111 if (vcpu->arch.apic_attention)
9112 kvm_lapic_sync_from_vapic(vcpu);
9113
9114 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
9115 return r;
9116
9117 cancel_injection:
9118 if (req_immediate_exit)
9119 kvm_make_request(KVM_REQ_EVENT, vcpu);
9120 kvm_x86_ops.cancel_injection(vcpu);
9121 if (unlikely(vcpu->arch.apic_attention))
9122 kvm_lapic_sync_from_vapic(vcpu);
9123 out:
9124 return r;
9125 }
9126
9127 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
9128 {
9129 if (!kvm_arch_vcpu_runnable(vcpu) &&
9130 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
9131 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9132 kvm_vcpu_block(vcpu);
9133 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9134
9135 if (kvm_x86_ops.post_block)
9136 kvm_x86_ops.post_block(vcpu);
9137
9138 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
9139 return 1;
9140 }
9141
9142 kvm_apic_accept_events(vcpu);
9143 switch(vcpu->arch.mp_state) {
9144 case KVM_MP_STATE_HALTED:
9145 case KVM_MP_STATE_AP_RESET_HOLD:
9146 vcpu->arch.pv.pv_unhalted = false;
9147 vcpu->arch.mp_state =
9148 KVM_MP_STATE_RUNNABLE;
9149 fallthrough;
9150 case KVM_MP_STATE_RUNNABLE:
9151 vcpu->arch.apf.halted = false;
9152 break;
9153 case KVM_MP_STATE_INIT_RECEIVED:
9154 break;
9155 default:
9156 return -EINTR;
9157 }
9158 return 1;
9159 }
9160
9161 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
9162 {
9163 if (is_guest_mode(vcpu))
9164 kvm_x86_ops.nested_ops->check_events(vcpu);
9165
9166 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
9167 !vcpu->arch.apf.halted);
9168 }
9169
9170 static int vcpu_run(struct kvm_vcpu *vcpu)
9171 {
9172 int r;
9173 struct kvm *kvm = vcpu->kvm;
9174
9175 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9176 vcpu->arch.l1tf_flush_l1d = true;
9177
9178 for (;;) {
9179 if (kvm_vcpu_running(vcpu)) {
9180 r = vcpu_enter_guest(vcpu);
9181 } else {
9182 r = vcpu_block(kvm, vcpu);
9183 }
9184
9185 if (r <= 0)
9186 break;
9187
9188 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
9189 if (kvm_cpu_has_pending_timer(vcpu))
9190 kvm_inject_pending_timer_irqs(vcpu);
9191
9192 if (dm_request_for_irq_injection(vcpu) &&
9193 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9194 r = 0;
9195 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9196 ++vcpu->stat.request_irq_exits;
9197 break;
9198 }
9199
9200 if (__xfer_to_guest_mode_work_pending()) {
9201 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9202 r = xfer_to_guest_mode_handle_work(vcpu);
9203 if (r)
9204 return r;
9205 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9206 }
9207 }
9208
9209 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9210
9211 return r;
9212 }
9213
9214 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9215 {
9216 int r;
9217
9218 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9219 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9220 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9221 return r;
9222 }
9223
9224 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9225 {
9226 BUG_ON(!vcpu->arch.pio.count);
9227
9228 return complete_emulated_io(vcpu);
9229 }
9230
9231 /*
9232 * Implements the following, as a state machine:
9233 *
9234 * read:
9235 * for each fragment
9236 * for each mmio piece in the fragment
9237 * write gpa, len
9238 * exit
9239 * copy data
9240 * execute insn
9241 *
9242 * write:
9243 * for each fragment
9244 * for each mmio piece in the fragment
9245 * write gpa, len
9246 * copy data
9247 * exit
9248 */
9249 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9250 {
9251 struct kvm_run *run = vcpu->run;
9252 struct kvm_mmio_fragment *frag;
9253 unsigned len;
9254
9255 BUG_ON(!vcpu->mmio_needed);
9256
9257 /* Complete previous fragment */
9258 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9259 len = min(8u, frag->len);
9260 if (!vcpu->mmio_is_write)
9261 memcpy(frag->data, run->mmio.data, len);
9262
9263 if (frag->len <= 8) {
9264 /* Switch to the next fragment. */
9265 frag++;
9266 vcpu->mmio_cur_fragment++;
9267 } else {
9268 /* Go forward to the next mmio piece. */
9269 frag->data += len;
9270 frag->gpa += len;
9271 frag->len -= len;
9272 }
9273
9274 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9275 vcpu->mmio_needed = 0;
9276
9277 /* FIXME: return into emulator if single-stepping. */
9278 if (vcpu->mmio_is_write)
9279 return 1;
9280 vcpu->mmio_read_completed = 1;
9281 return complete_emulated_io(vcpu);
9282 }
9283
9284 run->exit_reason = KVM_EXIT_MMIO;
9285 run->mmio.phys_addr = frag->gpa;
9286 if (vcpu->mmio_is_write)
9287 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9288 run->mmio.len = min(8u, frag->len);
9289 run->mmio.is_write = vcpu->mmio_is_write;
9290 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9291 return 0;
9292 }
9293
9294 static void kvm_save_current_fpu(struct fpu *fpu)
9295 {
9296 /*
9297 * If the target FPU state is not resident in the CPU registers, just
9298 * memcpy() from current, else save CPU state directly to the target.
9299 */
9300 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9301 memcpy(&fpu->state, &current->thread.fpu.state,
9302 fpu_kernel_xstate_size);
9303 else
9304 copy_fpregs_to_fpstate(fpu);
9305 }
9306
9307 /* Swap (qemu) user FPU context for the guest FPU context. */
9308 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9309 {
9310 fpregs_lock();
9311
9312 kvm_save_current_fpu(vcpu->arch.user_fpu);
9313
9314 /*
9315 * Guests with protected state can't have it set by the hypervisor,
9316 * so skip trying to set it.
9317 */
9318 if (vcpu->arch.guest_fpu)
9319 /* PKRU is separately restored in kvm_x86_ops.run. */
9320 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9321 ~XFEATURE_MASK_PKRU);
9322
9323 fpregs_mark_activate();
9324 fpregs_unlock();
9325
9326 trace_kvm_fpu(1);
9327 }
9328
9329 /* When vcpu_run ends, restore user space FPU context. */
9330 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9331 {
9332 fpregs_lock();
9333
9334 /*
9335 * Guests with protected state can't have it read by the hypervisor,
9336 * so skip trying to save it.
9337 */
9338 if (vcpu->arch.guest_fpu)
9339 kvm_save_current_fpu(vcpu->arch.guest_fpu);
9340
9341 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9342
9343 fpregs_mark_activate();
9344 fpregs_unlock();
9345
9346 ++vcpu->stat.fpu_reload;
9347 trace_kvm_fpu(0);
9348 }
9349
9350 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9351 {
9352 struct kvm_run *kvm_run = vcpu->run;
9353 int r;
9354
9355 vcpu_load(vcpu);
9356 kvm_sigset_activate(vcpu);
9357 kvm_load_guest_fpu(vcpu);
9358
9359 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9360 if (kvm_run->immediate_exit) {
9361 r = -EINTR;
9362 goto out;
9363 }
9364 kvm_vcpu_block(vcpu);
9365 kvm_apic_accept_events(vcpu);
9366 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9367 r = -EAGAIN;
9368 if (signal_pending(current)) {
9369 r = -EINTR;
9370 kvm_run->exit_reason = KVM_EXIT_INTR;
9371 ++vcpu->stat.signal_exits;
9372 }
9373 goto out;
9374 }
9375
9376 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9377 r = -EINVAL;
9378 goto out;
9379 }
9380
9381 if (kvm_run->kvm_dirty_regs) {
9382 r = sync_regs(vcpu);
9383 if (r != 0)
9384 goto out;
9385 }
9386
9387 /* re-sync apic's tpr */
9388 if (!lapic_in_kernel(vcpu)) {
9389 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9390 r = -EINVAL;
9391 goto out;
9392 }
9393 }
9394
9395 if (unlikely(vcpu->arch.complete_userspace_io)) {
9396 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9397 vcpu->arch.complete_userspace_io = NULL;
9398 r = cui(vcpu);
9399 if (r <= 0)
9400 goto out;
9401 } else
9402 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9403
9404 if (kvm_run->immediate_exit)
9405 r = -EINTR;
9406 else
9407 r = vcpu_run(vcpu);
9408
9409 out:
9410 kvm_put_guest_fpu(vcpu);
9411 if (kvm_run->kvm_valid_regs)
9412 store_regs(vcpu);
9413 post_kvm_run_save(vcpu);
9414 kvm_sigset_deactivate(vcpu);
9415
9416 vcpu_put(vcpu);
9417 return r;
9418 }
9419
9420 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9421 {
9422 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9423 /*
9424 * We are here if userspace calls get_regs() in the middle of
9425 * instruction emulation. Registers state needs to be copied
9426 * back from emulation context to vcpu. Userspace shouldn't do
9427 * that usually, but some bad designed PV devices (vmware
9428 * backdoor interface) need this to work
9429 */
9430 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9431 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9432 }
9433 regs->rax = kvm_rax_read(vcpu);
9434 regs->rbx = kvm_rbx_read(vcpu);
9435 regs->rcx = kvm_rcx_read(vcpu);
9436 regs->rdx = kvm_rdx_read(vcpu);
9437 regs->rsi = kvm_rsi_read(vcpu);
9438 regs->rdi = kvm_rdi_read(vcpu);
9439 regs->rsp = kvm_rsp_read(vcpu);
9440 regs->rbp = kvm_rbp_read(vcpu);
9441 #ifdef CONFIG_X86_64
9442 regs->r8 = kvm_r8_read(vcpu);
9443 regs->r9 = kvm_r9_read(vcpu);
9444 regs->r10 = kvm_r10_read(vcpu);
9445 regs->r11 = kvm_r11_read(vcpu);
9446 regs->r12 = kvm_r12_read(vcpu);
9447 regs->r13 = kvm_r13_read(vcpu);
9448 regs->r14 = kvm_r14_read(vcpu);
9449 regs->r15 = kvm_r15_read(vcpu);
9450 #endif
9451
9452 regs->rip = kvm_rip_read(vcpu);
9453 regs->rflags = kvm_get_rflags(vcpu);
9454 }
9455
9456 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9457 {
9458 vcpu_load(vcpu);
9459 __get_regs(vcpu, regs);
9460 vcpu_put(vcpu);
9461 return 0;
9462 }
9463
9464 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9465 {
9466 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9467 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9468
9469 kvm_rax_write(vcpu, regs->rax);
9470 kvm_rbx_write(vcpu, regs->rbx);
9471 kvm_rcx_write(vcpu, regs->rcx);
9472 kvm_rdx_write(vcpu, regs->rdx);
9473 kvm_rsi_write(vcpu, regs->rsi);
9474 kvm_rdi_write(vcpu, regs->rdi);
9475 kvm_rsp_write(vcpu, regs->rsp);
9476 kvm_rbp_write(vcpu, regs->rbp);
9477 #ifdef CONFIG_X86_64
9478 kvm_r8_write(vcpu, regs->r8);
9479 kvm_r9_write(vcpu, regs->r9);
9480 kvm_r10_write(vcpu, regs->r10);
9481 kvm_r11_write(vcpu, regs->r11);
9482 kvm_r12_write(vcpu, regs->r12);
9483 kvm_r13_write(vcpu, regs->r13);
9484 kvm_r14_write(vcpu, regs->r14);
9485 kvm_r15_write(vcpu, regs->r15);
9486 #endif
9487
9488 kvm_rip_write(vcpu, regs->rip);
9489 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9490
9491 vcpu->arch.exception.pending = false;
9492
9493 kvm_make_request(KVM_REQ_EVENT, vcpu);
9494 }
9495
9496 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9497 {
9498 vcpu_load(vcpu);
9499 __set_regs(vcpu, regs);
9500 vcpu_put(vcpu);
9501 return 0;
9502 }
9503
9504 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9505 {
9506 struct kvm_segment cs;
9507
9508 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9509 *db = cs.db;
9510 *l = cs.l;
9511 }
9512 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9513
9514 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9515 {
9516 struct desc_ptr dt;
9517
9518 if (vcpu->arch.guest_state_protected)
9519 goto skip_protected_regs;
9520
9521 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9522 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9523 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9524 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9525 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9526 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9527
9528 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9529 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9530
9531 kvm_x86_ops.get_idt(vcpu, &dt);
9532 sregs->idt.limit = dt.size;
9533 sregs->idt.base = dt.address;
9534 kvm_x86_ops.get_gdt(vcpu, &dt);
9535 sregs->gdt.limit = dt.size;
9536 sregs->gdt.base = dt.address;
9537
9538 sregs->cr2 = vcpu->arch.cr2;
9539 sregs->cr3 = kvm_read_cr3(vcpu);
9540
9541 skip_protected_regs:
9542 sregs->cr0 = kvm_read_cr0(vcpu);
9543 sregs->cr4 = kvm_read_cr4(vcpu);
9544 sregs->cr8 = kvm_get_cr8(vcpu);
9545 sregs->efer = vcpu->arch.efer;
9546 sregs->apic_base = kvm_get_apic_base(vcpu);
9547
9548 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9549
9550 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9551 set_bit(vcpu->arch.interrupt.nr,
9552 (unsigned long *)sregs->interrupt_bitmap);
9553 }
9554
9555 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9556 struct kvm_sregs *sregs)
9557 {
9558 vcpu_load(vcpu);
9559 __get_sregs(vcpu, sregs);
9560 vcpu_put(vcpu);
9561 return 0;
9562 }
9563
9564 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9565 struct kvm_mp_state *mp_state)
9566 {
9567 vcpu_load(vcpu);
9568 if (kvm_mpx_supported())
9569 kvm_load_guest_fpu(vcpu);
9570
9571 kvm_apic_accept_events(vcpu);
9572 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
9573 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
9574 vcpu->arch.pv.pv_unhalted)
9575 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9576 else
9577 mp_state->mp_state = vcpu->arch.mp_state;
9578
9579 if (kvm_mpx_supported())
9580 kvm_put_guest_fpu(vcpu);
9581 vcpu_put(vcpu);
9582 return 0;
9583 }
9584
9585 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9586 struct kvm_mp_state *mp_state)
9587 {
9588 int ret = -EINVAL;
9589
9590 vcpu_load(vcpu);
9591
9592 if (!lapic_in_kernel(vcpu) &&
9593 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9594 goto out;
9595
9596 /*
9597 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9598 * INIT state; latched init should be reported using
9599 * KVM_SET_VCPU_EVENTS, so reject it here.
9600 */
9601 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9602 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9603 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9604 goto out;
9605
9606 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9607 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9608 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9609 } else
9610 vcpu->arch.mp_state = mp_state->mp_state;
9611 kvm_make_request(KVM_REQ_EVENT, vcpu);
9612
9613 ret = 0;
9614 out:
9615 vcpu_put(vcpu);
9616 return ret;
9617 }
9618
9619 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9620 int reason, bool has_error_code, u32 error_code)
9621 {
9622 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9623 int ret;
9624
9625 init_emulate_ctxt(vcpu);
9626
9627 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9628 has_error_code, error_code);
9629 if (ret) {
9630 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9631 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9632 vcpu->run->internal.ndata = 0;
9633 return 0;
9634 }
9635
9636 kvm_rip_write(vcpu, ctxt->eip);
9637 kvm_set_rflags(vcpu, ctxt->eflags);
9638 return 1;
9639 }
9640 EXPORT_SYMBOL_GPL(kvm_task_switch);
9641
9642 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9643 {
9644 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9645 /*
9646 * When EFER.LME and CR0.PG are set, the processor is in
9647 * 64-bit mode (though maybe in a 32-bit code segment).
9648 * CR4.PAE and EFER.LMA must be set.
9649 */
9650 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
9651 return false;
9652 if (sregs->cr3 & vcpu->arch.cr3_lm_rsvd_bits)
9653 return false;
9654 } else {
9655 /*
9656 * Not in 64-bit mode: EFER.LMA is clear and the code
9657 * segment cannot be 64-bit.
9658 */
9659 if (sregs->efer & EFER_LMA || sregs->cs.l)
9660 return false;
9661 }
9662
9663 return kvm_is_valid_cr4(vcpu, sregs->cr4);
9664 }
9665
9666 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9667 {
9668 struct msr_data apic_base_msr;
9669 int mmu_reset_needed = 0;
9670 int pending_vec, max_bits, idx;
9671 struct desc_ptr dt;
9672 int ret = -EINVAL;
9673
9674 if (!kvm_is_valid_sregs(vcpu, sregs))
9675 goto out;
9676
9677 apic_base_msr.data = sregs->apic_base;
9678 apic_base_msr.host_initiated = true;
9679 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9680 goto out;
9681
9682 if (vcpu->arch.guest_state_protected)
9683 goto skip_protected_regs;
9684
9685 dt.size = sregs->idt.limit;
9686 dt.address = sregs->idt.base;
9687 kvm_x86_ops.set_idt(vcpu, &dt);
9688 dt.size = sregs->gdt.limit;
9689 dt.address = sregs->gdt.base;
9690 kvm_x86_ops.set_gdt(vcpu, &dt);
9691
9692 vcpu->arch.cr2 = sregs->cr2;
9693 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9694 vcpu->arch.cr3 = sregs->cr3;
9695 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9696
9697 kvm_set_cr8(vcpu, sregs->cr8);
9698
9699 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9700 kvm_x86_ops.set_efer(vcpu, sregs->efer);
9701
9702 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9703 kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9704 vcpu->arch.cr0 = sregs->cr0;
9705
9706 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9707 kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9708
9709 idx = srcu_read_lock(&vcpu->kvm->srcu);
9710 if (is_pae_paging(vcpu)) {
9711 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9712 mmu_reset_needed = 1;
9713 }
9714 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9715
9716 if (mmu_reset_needed)
9717 kvm_mmu_reset_context(vcpu);
9718
9719 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9720 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9721 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9722 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9723 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9724 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9725
9726 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9727 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9728
9729 update_cr8_intercept(vcpu);
9730
9731 /* Older userspace won't unhalt the vcpu on reset. */
9732 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9733 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9734 !is_protmode(vcpu))
9735 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9736
9737 skip_protected_regs:
9738 max_bits = KVM_NR_INTERRUPTS;
9739 pending_vec = find_first_bit(
9740 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9741 if (pending_vec < max_bits) {
9742 kvm_queue_interrupt(vcpu, pending_vec, false);
9743 pr_debug("Set back pending irq %d\n", pending_vec);
9744 }
9745
9746 kvm_make_request(KVM_REQ_EVENT, vcpu);
9747
9748 ret = 0;
9749 out:
9750 return ret;
9751 }
9752
9753 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9754 struct kvm_sregs *sregs)
9755 {
9756 int ret;
9757
9758 vcpu_load(vcpu);
9759 ret = __set_sregs(vcpu, sregs);
9760 vcpu_put(vcpu);
9761 return ret;
9762 }
9763
9764 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9765 struct kvm_guest_debug *dbg)
9766 {
9767 unsigned long rflags;
9768 int i, r;
9769
9770 if (vcpu->arch.guest_state_protected)
9771 return -EINVAL;
9772
9773 vcpu_load(vcpu);
9774
9775 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9776 r = -EBUSY;
9777 if (vcpu->arch.exception.pending)
9778 goto out;
9779 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9780 kvm_queue_exception(vcpu, DB_VECTOR);
9781 else
9782 kvm_queue_exception(vcpu, BP_VECTOR);
9783 }
9784
9785 /*
9786 * Read rflags as long as potentially injected trace flags are still
9787 * filtered out.
9788 */
9789 rflags = kvm_get_rflags(vcpu);
9790
9791 vcpu->guest_debug = dbg->control;
9792 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9793 vcpu->guest_debug = 0;
9794
9795 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9796 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9797 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9798 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9799 } else {
9800 for (i = 0; i < KVM_NR_DB_REGS; i++)
9801 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9802 }
9803 kvm_update_dr7(vcpu);
9804
9805 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9806 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9807 get_segment_base(vcpu, VCPU_SREG_CS);
9808
9809 /*
9810 * Trigger an rflags update that will inject or remove the trace
9811 * flags.
9812 */
9813 kvm_set_rflags(vcpu, rflags);
9814
9815 kvm_x86_ops.update_exception_bitmap(vcpu);
9816
9817 r = 0;
9818
9819 out:
9820 vcpu_put(vcpu);
9821 return r;
9822 }
9823
9824 /*
9825 * Translate a guest virtual address to a guest physical address.
9826 */
9827 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9828 struct kvm_translation *tr)
9829 {
9830 unsigned long vaddr = tr->linear_address;
9831 gpa_t gpa;
9832 int idx;
9833
9834 vcpu_load(vcpu);
9835
9836 idx = srcu_read_lock(&vcpu->kvm->srcu);
9837 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9838 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9839 tr->physical_address = gpa;
9840 tr->valid = gpa != UNMAPPED_GVA;
9841 tr->writeable = 1;
9842 tr->usermode = 0;
9843
9844 vcpu_put(vcpu);
9845 return 0;
9846 }
9847
9848 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9849 {
9850 struct fxregs_state *fxsave;
9851
9852 if (!vcpu->arch.guest_fpu)
9853 return 0;
9854
9855 vcpu_load(vcpu);
9856
9857 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9858 memcpy(fpu->fpr, fxsave->st_space, 128);
9859 fpu->fcw = fxsave->cwd;
9860 fpu->fsw = fxsave->swd;
9861 fpu->ftwx = fxsave->twd;
9862 fpu->last_opcode = fxsave->fop;
9863 fpu->last_ip = fxsave->rip;
9864 fpu->last_dp = fxsave->rdp;
9865 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9866
9867 vcpu_put(vcpu);
9868 return 0;
9869 }
9870
9871 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9872 {
9873 struct fxregs_state *fxsave;
9874
9875 if (!vcpu->arch.guest_fpu)
9876 return 0;
9877
9878 vcpu_load(vcpu);
9879
9880 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9881
9882 memcpy(fxsave->st_space, fpu->fpr, 128);
9883 fxsave->cwd = fpu->fcw;
9884 fxsave->swd = fpu->fsw;
9885 fxsave->twd = fpu->ftwx;
9886 fxsave->fop = fpu->last_opcode;
9887 fxsave->rip = fpu->last_ip;
9888 fxsave->rdp = fpu->last_dp;
9889 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9890
9891 vcpu_put(vcpu);
9892 return 0;
9893 }
9894
9895 static void store_regs(struct kvm_vcpu *vcpu)
9896 {
9897 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9898
9899 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9900 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9901
9902 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9903 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9904
9905 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9906 kvm_vcpu_ioctl_x86_get_vcpu_events(
9907 vcpu, &vcpu->run->s.regs.events);
9908 }
9909
9910 static int sync_regs(struct kvm_vcpu *vcpu)
9911 {
9912 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9913 return -EINVAL;
9914
9915 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9916 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9917 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9918 }
9919 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9920 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9921 return -EINVAL;
9922 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9923 }
9924 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9925 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9926 vcpu, &vcpu->run->s.regs.events))
9927 return -EINVAL;
9928 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9929 }
9930
9931 return 0;
9932 }
9933
9934 static void fx_init(struct kvm_vcpu *vcpu)
9935 {
9936 if (!vcpu->arch.guest_fpu)
9937 return;
9938
9939 fpstate_init(&vcpu->arch.guest_fpu->state);
9940 if (boot_cpu_has(X86_FEATURE_XSAVES))
9941 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9942 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9943
9944 /*
9945 * Ensure guest xcr0 is valid for loading
9946 */
9947 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9948
9949 vcpu->arch.cr0 |= X86_CR0_ET;
9950 }
9951
9952 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu)
9953 {
9954 if (vcpu->arch.guest_fpu) {
9955 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9956 vcpu->arch.guest_fpu = NULL;
9957 }
9958 }
9959 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu);
9960
9961 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9962 {
9963 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9964 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9965 "guest TSC will not be reliable\n");
9966
9967 return 0;
9968 }
9969
9970 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9971 {
9972 struct page *page;
9973 int r;
9974
9975 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9976 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9977 else
9978 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9979
9980 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9981
9982 r = kvm_mmu_create(vcpu);
9983 if (r < 0)
9984 return r;
9985
9986 if (irqchip_in_kernel(vcpu->kvm)) {
9987 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9988 if (r < 0)
9989 goto fail_mmu_destroy;
9990 if (kvm_apicv_activated(vcpu->kvm))
9991 vcpu->arch.apicv_active = true;
9992 } else
9993 static_key_slow_inc(&kvm_no_apic_vcpu);
9994
9995 r = -ENOMEM;
9996
9997 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
9998 if (!page)
9999 goto fail_free_lapic;
10000 vcpu->arch.pio_data = page_address(page);
10001
10002 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
10003 GFP_KERNEL_ACCOUNT);
10004 if (!vcpu->arch.mce_banks)
10005 goto fail_free_pio_data;
10006 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
10007
10008 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
10009 GFP_KERNEL_ACCOUNT))
10010 goto fail_free_mce_banks;
10011
10012 if (!alloc_emulate_ctxt(vcpu))
10013 goto free_wbinvd_dirty_mask;
10014
10015 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
10016 GFP_KERNEL_ACCOUNT);
10017 if (!vcpu->arch.user_fpu) {
10018 pr_err("kvm: failed to allocate userspace's fpu\n");
10019 goto free_emulate_ctxt;
10020 }
10021
10022 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
10023 GFP_KERNEL_ACCOUNT);
10024 if (!vcpu->arch.guest_fpu) {
10025 pr_err("kvm: failed to allocate vcpu's fpu\n");
10026 goto free_user_fpu;
10027 }
10028 fx_init(vcpu);
10029
10030 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
10031 vcpu->arch.cr3_lm_rsvd_bits = rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
10032
10033 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
10034
10035 kvm_async_pf_hash_reset(vcpu);
10036 kvm_pmu_init(vcpu);
10037
10038 vcpu->arch.pending_external_vector = -1;
10039 vcpu->arch.preempted_in_kernel = false;
10040
10041 kvm_hv_vcpu_init(vcpu);
10042
10043 r = kvm_x86_ops.vcpu_create(vcpu);
10044 if (r)
10045 goto free_guest_fpu;
10046
10047 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
10048 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
10049 kvm_vcpu_mtrr_init(vcpu);
10050 vcpu_load(vcpu);
10051 kvm_vcpu_reset(vcpu, false);
10052 kvm_init_mmu(vcpu, false);
10053 vcpu_put(vcpu);
10054 return 0;
10055
10056 free_guest_fpu:
10057 kvm_free_guest_fpu(vcpu);
10058 free_user_fpu:
10059 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10060 free_emulate_ctxt:
10061 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10062 free_wbinvd_dirty_mask:
10063 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10064 fail_free_mce_banks:
10065 kfree(vcpu->arch.mce_banks);
10066 fail_free_pio_data:
10067 free_page((unsigned long)vcpu->arch.pio_data);
10068 fail_free_lapic:
10069 kvm_free_lapic(vcpu);
10070 fail_mmu_destroy:
10071 kvm_mmu_destroy(vcpu);
10072 return r;
10073 }
10074
10075 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
10076 {
10077 struct kvm *kvm = vcpu->kvm;
10078
10079 kvm_hv_vcpu_postcreate(vcpu);
10080
10081 if (mutex_lock_killable(&vcpu->mutex))
10082 return;
10083 vcpu_load(vcpu);
10084 kvm_synchronize_tsc(vcpu, 0);
10085 vcpu_put(vcpu);
10086
10087 /* poll control enabled by default */
10088 vcpu->arch.msr_kvm_poll_control = 1;
10089
10090 mutex_unlock(&vcpu->mutex);
10091
10092 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
10093 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
10094 KVMCLOCK_SYNC_PERIOD);
10095 }
10096
10097 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
10098 {
10099 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
10100 int idx;
10101
10102 kvm_release_pfn(cache->pfn, cache->dirty, cache);
10103
10104 kvmclock_reset(vcpu);
10105
10106 kvm_x86_ops.vcpu_free(vcpu);
10107
10108 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10109 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10110 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10111 kvm_free_guest_fpu(vcpu);
10112
10113 kvm_hv_vcpu_uninit(vcpu);
10114 kvm_pmu_destroy(vcpu);
10115 kfree(vcpu->arch.mce_banks);
10116 kvm_free_lapic(vcpu);
10117 idx = srcu_read_lock(&vcpu->kvm->srcu);
10118 kvm_mmu_destroy(vcpu);
10119 srcu_read_unlock(&vcpu->kvm->srcu, idx);
10120 free_page((unsigned long)vcpu->arch.pio_data);
10121 kvfree(vcpu->arch.cpuid_entries);
10122 if (!lapic_in_kernel(vcpu))
10123 static_key_slow_dec(&kvm_no_apic_vcpu);
10124 }
10125
10126 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
10127 {
10128 kvm_lapic_reset(vcpu, init_event);
10129
10130 vcpu->arch.hflags = 0;
10131
10132 vcpu->arch.smi_pending = 0;
10133 vcpu->arch.smi_count = 0;
10134 atomic_set(&vcpu->arch.nmi_queued, 0);
10135 vcpu->arch.nmi_pending = 0;
10136 vcpu->arch.nmi_injected = false;
10137 kvm_clear_interrupt_queue(vcpu);
10138 kvm_clear_exception_queue(vcpu);
10139
10140 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
10141 kvm_update_dr0123(vcpu);
10142 vcpu->arch.dr6 = DR6_INIT;
10143 vcpu->arch.dr7 = DR7_FIXED_1;
10144 kvm_update_dr7(vcpu);
10145
10146 vcpu->arch.cr2 = 0;
10147
10148 kvm_make_request(KVM_REQ_EVENT, vcpu);
10149 vcpu->arch.apf.msr_en_val = 0;
10150 vcpu->arch.apf.msr_int_val = 0;
10151 vcpu->arch.st.msr_val = 0;
10152
10153 kvmclock_reset(vcpu);
10154
10155 kvm_clear_async_pf_completion_queue(vcpu);
10156 kvm_async_pf_hash_reset(vcpu);
10157 vcpu->arch.apf.halted = false;
10158
10159 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) {
10160 void *mpx_state_buffer;
10161
10162 /*
10163 * To avoid have the INIT path from kvm_apic_has_events() that be
10164 * called with loaded FPU and does not let userspace fix the state.
10165 */
10166 if (init_event)
10167 kvm_put_guest_fpu(vcpu);
10168 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10169 XFEATURE_BNDREGS);
10170 if (mpx_state_buffer)
10171 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
10172 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10173 XFEATURE_BNDCSR);
10174 if (mpx_state_buffer)
10175 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
10176 if (init_event)
10177 kvm_load_guest_fpu(vcpu);
10178 }
10179
10180 if (!init_event) {
10181 kvm_pmu_reset(vcpu);
10182 vcpu->arch.smbase = 0x30000;
10183
10184 vcpu->arch.msr_misc_features_enables = 0;
10185
10186 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
10187 }
10188
10189 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
10190 vcpu->arch.regs_avail = ~0;
10191 vcpu->arch.regs_dirty = ~0;
10192
10193 vcpu->arch.ia32_xss = 0;
10194
10195 kvm_x86_ops.vcpu_reset(vcpu, init_event);
10196 }
10197
10198 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
10199 {
10200 struct kvm_segment cs;
10201
10202 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
10203 cs.selector = vector << 8;
10204 cs.base = vector << 12;
10205 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10206 kvm_rip_write(vcpu, 0);
10207 }
10208 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
10209
10210 int kvm_arch_hardware_enable(void)
10211 {
10212 struct kvm *kvm;
10213 struct kvm_vcpu *vcpu;
10214 int i;
10215 int ret;
10216 u64 local_tsc;
10217 u64 max_tsc = 0;
10218 bool stable, backwards_tsc = false;
10219
10220 kvm_user_return_msr_cpu_online();
10221 ret = kvm_x86_ops.hardware_enable();
10222 if (ret != 0)
10223 return ret;
10224
10225 local_tsc = rdtsc();
10226 stable = !kvm_check_tsc_unstable();
10227 list_for_each_entry(kvm, &vm_list, vm_list) {
10228 kvm_for_each_vcpu(i, vcpu, kvm) {
10229 if (!stable && vcpu->cpu == smp_processor_id())
10230 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10231 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10232 backwards_tsc = true;
10233 if (vcpu->arch.last_host_tsc > max_tsc)
10234 max_tsc = vcpu->arch.last_host_tsc;
10235 }
10236 }
10237 }
10238
10239 /*
10240 * Sometimes, even reliable TSCs go backwards. This happens on
10241 * platforms that reset TSC during suspend or hibernate actions, but
10242 * maintain synchronization. We must compensate. Fortunately, we can
10243 * detect that condition here, which happens early in CPU bringup,
10244 * before any KVM threads can be running. Unfortunately, we can't
10245 * bring the TSCs fully up to date with real time, as we aren't yet far
10246 * enough into CPU bringup that we know how much real time has actually
10247 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10248 * variables that haven't been updated yet.
10249 *
10250 * So we simply find the maximum observed TSC above, then record the
10251 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
10252 * the adjustment will be applied. Note that we accumulate
10253 * adjustments, in case multiple suspend cycles happen before some VCPU
10254 * gets a chance to run again. In the event that no KVM threads get a
10255 * chance to run, we will miss the entire elapsed period, as we'll have
10256 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10257 * loose cycle time. This isn't too big a deal, since the loss will be
10258 * uniform across all VCPUs (not to mention the scenario is extremely
10259 * unlikely). It is possible that a second hibernate recovery happens
10260 * much faster than a first, causing the observed TSC here to be
10261 * smaller; this would require additional padding adjustment, which is
10262 * why we set last_host_tsc to the local tsc observed here.
10263 *
10264 * N.B. - this code below runs only on platforms with reliable TSC,
10265 * as that is the only way backwards_tsc is set above. Also note
10266 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10267 * have the same delta_cyc adjustment applied if backwards_tsc
10268 * is detected. Note further, this adjustment is only done once,
10269 * as we reset last_host_tsc on all VCPUs to stop this from being
10270 * called multiple times (one for each physical CPU bringup).
10271 *
10272 * Platforms with unreliable TSCs don't have to deal with this, they
10273 * will be compensated by the logic in vcpu_load, which sets the TSC to
10274 * catchup mode. This will catchup all VCPUs to real time, but cannot
10275 * guarantee that they stay in perfect synchronization.
10276 */
10277 if (backwards_tsc) {
10278 u64 delta_cyc = max_tsc - local_tsc;
10279 list_for_each_entry(kvm, &vm_list, vm_list) {
10280 kvm->arch.backwards_tsc_observed = true;
10281 kvm_for_each_vcpu(i, vcpu, kvm) {
10282 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10283 vcpu->arch.last_host_tsc = local_tsc;
10284 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10285 }
10286
10287 /*
10288 * We have to disable TSC offset matching.. if you were
10289 * booting a VM while issuing an S4 host suspend....
10290 * you may have some problem. Solving this issue is
10291 * left as an exercise to the reader.
10292 */
10293 kvm->arch.last_tsc_nsec = 0;
10294 kvm->arch.last_tsc_write = 0;
10295 }
10296
10297 }
10298 return 0;
10299 }
10300
10301 void kvm_arch_hardware_disable(void)
10302 {
10303 kvm_x86_ops.hardware_disable();
10304 drop_user_return_notifiers();
10305 }
10306
10307 int kvm_arch_hardware_setup(void *opaque)
10308 {
10309 struct kvm_x86_init_ops *ops = opaque;
10310 int r;
10311
10312 rdmsrl_safe(MSR_EFER, &host_efer);
10313
10314 if (boot_cpu_has(X86_FEATURE_XSAVES))
10315 rdmsrl(MSR_IA32_XSS, host_xss);
10316
10317 r = ops->hardware_setup();
10318 if (r != 0)
10319 return r;
10320
10321 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10322
10323 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10324 supported_xss = 0;
10325
10326 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10327 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10328 #undef __kvm_cpu_cap_has
10329
10330 if (kvm_has_tsc_control) {
10331 /*
10332 * Make sure the user can only configure tsc_khz values that
10333 * fit into a signed integer.
10334 * A min value is not calculated because it will always
10335 * be 1 on all machines.
10336 */
10337 u64 max = min(0x7fffffffULL,
10338 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10339 kvm_max_guest_tsc_khz = max;
10340
10341 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10342 }
10343
10344 kvm_init_msr_list();
10345 return 0;
10346 }
10347
10348 void kvm_arch_hardware_unsetup(void)
10349 {
10350 kvm_x86_ops.hardware_unsetup();
10351 }
10352
10353 int kvm_arch_check_processor_compat(void *opaque)
10354 {
10355 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10356 struct kvm_x86_init_ops *ops = opaque;
10357
10358 WARN_ON(!irqs_disabled());
10359
10360 if (__cr4_reserved_bits(cpu_has, c) !=
10361 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10362 return -EIO;
10363
10364 return ops->check_processor_compatibility();
10365 }
10366
10367 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10368 {
10369 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10370 }
10371 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10372
10373 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10374 {
10375 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10376 }
10377
10378 struct static_key kvm_no_apic_vcpu __read_mostly;
10379 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
10380
10381 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10382 {
10383 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10384
10385 vcpu->arch.l1tf_flush_l1d = true;
10386 if (pmu->version && unlikely(pmu->event_count)) {
10387 pmu->need_cleanup = true;
10388 kvm_make_request(KVM_REQ_PMU, vcpu);
10389 }
10390 kvm_x86_ops.sched_in(vcpu, cpu);
10391 }
10392
10393 void kvm_arch_free_vm(struct kvm *kvm)
10394 {
10395 kfree(kvm->arch.hyperv.hv_pa_pg);
10396 vfree(kvm);
10397 }
10398
10399
10400 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10401 {
10402 if (type)
10403 return -EINVAL;
10404
10405 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10406 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10407 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10408 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10409 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10410 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10411
10412 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10413 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10414 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10415 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10416 &kvm->arch.irq_sources_bitmap);
10417
10418 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10419 mutex_init(&kvm->arch.apic_map_lock);
10420 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10421
10422 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10423 pvclock_update_vm_gtod_copy(kvm);
10424
10425 kvm->arch.guest_can_read_msr_platform_info = true;
10426
10427 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10428 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10429
10430 kvm_hv_init_vm(kvm);
10431 kvm_page_track_init(kvm);
10432 kvm_mmu_init_vm(kvm);
10433
10434 return kvm_x86_ops.vm_init(kvm);
10435 }
10436
10437 int kvm_arch_post_init_vm(struct kvm *kvm)
10438 {
10439 return kvm_mmu_post_init_vm(kvm);
10440 }
10441
10442 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10443 {
10444 vcpu_load(vcpu);
10445 kvm_mmu_unload(vcpu);
10446 vcpu_put(vcpu);
10447 }
10448
10449 static void kvm_free_vcpus(struct kvm *kvm)
10450 {
10451 unsigned int i;
10452 struct kvm_vcpu *vcpu;
10453
10454 /*
10455 * Unpin any mmu pages first.
10456 */
10457 kvm_for_each_vcpu(i, vcpu, kvm) {
10458 kvm_clear_async_pf_completion_queue(vcpu);
10459 kvm_unload_vcpu_mmu(vcpu);
10460 }
10461 kvm_for_each_vcpu(i, vcpu, kvm)
10462 kvm_vcpu_destroy(vcpu);
10463
10464 mutex_lock(&kvm->lock);
10465 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10466 kvm->vcpus[i] = NULL;
10467
10468 atomic_set(&kvm->online_vcpus, 0);
10469 mutex_unlock(&kvm->lock);
10470 }
10471
10472 void kvm_arch_sync_events(struct kvm *kvm)
10473 {
10474 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10475 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10476 kvm_free_pit(kvm);
10477 }
10478
10479 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
10480
10481 /**
10482 * __x86_set_memory_region: Setup KVM internal memory slot
10483 *
10484 * @kvm: the kvm pointer to the VM.
10485 * @id: the slot ID to setup.
10486 * @gpa: the GPA to install the slot (unused when @size == 0).
10487 * @size: the size of the slot. Set to zero to uninstall a slot.
10488 *
10489 * This function helps to setup a KVM internal memory slot. Specify
10490 * @size > 0 to install a new slot, while @size == 0 to uninstall a
10491 * slot. The return code can be one of the following:
10492 *
10493 * HVA: on success (uninstall will return a bogus HVA)
10494 * -errno: on error
10495 *
10496 * The caller should always use IS_ERR() to check the return value
10497 * before use. Note, the KVM internal memory slots are guaranteed to
10498 * remain valid and unchanged until the VM is destroyed, i.e., the
10499 * GPA->HVA translation will not change. However, the HVA is a user
10500 * address, i.e. its accessibility is not guaranteed, and must be
10501 * accessed via __copy_{to,from}_user().
10502 */
10503 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
10504 u32 size)
10505 {
10506 int i, r;
10507 unsigned long hva, old_npages;
10508 struct kvm_memslots *slots = kvm_memslots(kvm);
10509 struct kvm_memory_slot *slot;
10510
10511 /* Called with kvm->slots_lock held. */
10512 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10513 return ERR_PTR_USR(-EINVAL);
10514
10515 slot = id_to_memslot(slots, id);
10516 if (size) {
10517 if (slot && slot->npages)
10518 return ERR_PTR_USR(-EEXIST);
10519
10520 /*
10521 * MAP_SHARED to prevent internal slot pages from being moved
10522 * by fork()/COW.
10523 */
10524 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10525 MAP_SHARED | MAP_ANONYMOUS, 0);
10526 if (IS_ERR((void *)hva))
10527 return (void __user *)hva;
10528 } else {
10529 if (!slot || !slot->npages)
10530 return 0;
10531
10532 old_npages = slot->npages;
10533 hva = slot->userspace_addr;
10534 }
10535
10536 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10537 struct kvm_userspace_memory_region m;
10538
10539 m.slot = id | (i << 16);
10540 m.flags = 0;
10541 m.guest_phys_addr = gpa;
10542 m.userspace_addr = hva;
10543 m.memory_size = size;
10544 r = __kvm_set_memory_region(kvm, &m);
10545 if (r < 0)
10546 return ERR_PTR_USR(r);
10547 }
10548
10549 if (!size)
10550 vm_munmap(hva, old_npages * PAGE_SIZE);
10551
10552 return (void __user *)hva;
10553 }
10554 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10555
10556 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10557 {
10558 kvm_mmu_pre_destroy_vm(kvm);
10559 }
10560
10561 void kvm_arch_destroy_vm(struct kvm *kvm)
10562 {
10563 if (current->mm == kvm->mm) {
10564 /*
10565 * Free memory regions allocated on behalf of userspace,
10566 * unless the the memory map has changed due to process exit
10567 * or fd copying.
10568 */
10569 mutex_lock(&kvm->slots_lock);
10570 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10571 0, 0);
10572 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10573 0, 0);
10574 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10575 mutex_unlock(&kvm->slots_lock);
10576 }
10577 if (kvm_x86_ops.vm_destroy)
10578 kvm_x86_ops.vm_destroy(kvm);
10579 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
10580 kvm_pic_destroy(kvm);
10581 kvm_ioapic_destroy(kvm);
10582 kvm_free_vcpus(kvm);
10583 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10584 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10585 kvm_mmu_uninit_vm(kvm);
10586 kvm_page_track_cleanup(kvm);
10587 kvm_hv_destroy_vm(kvm);
10588 }
10589
10590 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10591 {
10592 int i;
10593
10594 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10595 kvfree(slot->arch.rmap[i]);
10596 slot->arch.rmap[i] = NULL;
10597
10598 if (i == 0)
10599 continue;
10600
10601 kvfree(slot->arch.lpage_info[i - 1]);
10602 slot->arch.lpage_info[i - 1] = NULL;
10603 }
10604
10605 kvm_page_track_free_memslot(slot);
10606 }
10607
10608 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10609 unsigned long npages)
10610 {
10611 int i;
10612
10613 /*
10614 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10615 * old arrays will be freed by __kvm_set_memory_region() if installing
10616 * the new memslot is successful.
10617 */
10618 memset(&slot->arch, 0, sizeof(slot->arch));
10619
10620 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10621 struct kvm_lpage_info *linfo;
10622 unsigned long ugfn;
10623 int lpages;
10624 int level = i + 1;
10625
10626 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10627 slot->base_gfn, level) + 1;
10628
10629 slot->arch.rmap[i] =
10630 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10631 GFP_KERNEL_ACCOUNT);
10632 if (!slot->arch.rmap[i])
10633 goto out_free;
10634 if (i == 0)
10635 continue;
10636
10637 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10638 if (!linfo)
10639 goto out_free;
10640
10641 slot->arch.lpage_info[i - 1] = linfo;
10642
10643 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10644 linfo[0].disallow_lpage = 1;
10645 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10646 linfo[lpages - 1].disallow_lpage = 1;
10647 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10648 /*
10649 * If the gfn and userspace address are not aligned wrt each
10650 * other, disable large page support for this slot.
10651 */
10652 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10653 unsigned long j;
10654
10655 for (j = 0; j < lpages; ++j)
10656 linfo[j].disallow_lpage = 1;
10657 }
10658 }
10659
10660 if (kvm_page_track_create_memslot(slot, npages))
10661 goto out_free;
10662
10663 return 0;
10664
10665 out_free:
10666 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10667 kvfree(slot->arch.rmap[i]);
10668 slot->arch.rmap[i] = NULL;
10669 if (i == 0)
10670 continue;
10671
10672 kvfree(slot->arch.lpage_info[i - 1]);
10673 slot->arch.lpage_info[i - 1] = NULL;
10674 }
10675 return -ENOMEM;
10676 }
10677
10678 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10679 {
10680 struct kvm_vcpu *vcpu;
10681 int i;
10682
10683 /*
10684 * memslots->generation has been incremented.
10685 * mmio generation may have reached its maximum value.
10686 */
10687 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10688
10689 /* Force re-initialization of steal_time cache */
10690 kvm_for_each_vcpu(i, vcpu, kvm)
10691 kvm_vcpu_kick(vcpu);
10692 }
10693
10694 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10695 struct kvm_memory_slot *memslot,
10696 const struct kvm_userspace_memory_region *mem,
10697 enum kvm_mr_change change)
10698 {
10699 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10700 return kvm_alloc_memslot_metadata(memslot,
10701 mem->memory_size >> PAGE_SHIFT);
10702 return 0;
10703 }
10704
10705 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10706 struct kvm_memory_slot *old,
10707 struct kvm_memory_slot *new,
10708 enum kvm_mr_change change)
10709 {
10710 /*
10711 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10712 * See comments below.
10713 */
10714 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10715 return;
10716
10717 /*
10718 * Dirty logging tracks sptes in 4k granularity, meaning that large
10719 * sptes have to be split. If live migration is successful, the guest
10720 * in the source machine will be destroyed and large sptes will be
10721 * created in the destination. However, if the guest continues to run
10722 * in the source machine (for example if live migration fails), small
10723 * sptes will remain around and cause bad performance.
10724 *
10725 * Scan sptes if dirty logging has been stopped, dropping those
10726 * which can be collapsed into a single large-page spte. Later
10727 * page faults will create the large-page sptes.
10728 *
10729 * There is no need to do this in any of the following cases:
10730 * CREATE: No dirty mappings will already exist.
10731 * MOVE/DELETE: The old mappings will already have been cleaned up by
10732 * kvm_arch_flush_shadow_memslot()
10733 */
10734 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10735 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10736 kvm_mmu_zap_collapsible_sptes(kvm, new);
10737
10738 /*
10739 * Enable or disable dirty logging for the slot.
10740 *
10741 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10742 * slot have been zapped so no dirty logging updates are needed for
10743 * the old slot.
10744 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10745 * any mappings that might be created in it will consume the
10746 * properties of the new slot and do not need to be updated here.
10747 *
10748 * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10749 * called to enable/disable dirty logging.
10750 *
10751 * When disabling dirty logging with PML enabled, the D-bit is set
10752 * for sptes in the slot in order to prevent unnecessary GPA
10753 * logging in the PML buffer (and potential PML buffer full VMEXIT).
10754 * This guarantees leaving PML enabled for the guest's lifetime
10755 * won't have any additional overhead from PML when the guest is
10756 * running with dirty logging disabled.
10757 *
10758 * When enabling dirty logging, large sptes are write-protected
10759 * so they can be split on first write. New large sptes cannot
10760 * be created for this slot until the end of the logging.
10761 * See the comments in fast_page_fault().
10762 * For small sptes, nothing is done if the dirty log is in the
10763 * initial-all-set state. Otherwise, depending on whether pml
10764 * is enabled the D-bit or the W-bit will be cleared.
10765 */
10766 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10767 if (kvm_x86_ops.slot_enable_log_dirty) {
10768 kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10769 } else {
10770 int level =
10771 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10772 PG_LEVEL_2M : PG_LEVEL_4K;
10773
10774 /*
10775 * If we're with initial-all-set, we don't need
10776 * to write protect any small page because
10777 * they're reported as dirty already. However
10778 * we still need to write-protect huge pages
10779 * so that the page split can happen lazily on
10780 * the first write to the huge page.
10781 */
10782 kvm_mmu_slot_remove_write_access(kvm, new, level);
10783 }
10784 } else {
10785 if (kvm_x86_ops.slot_disable_log_dirty)
10786 kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10787 }
10788 }
10789
10790 void kvm_arch_commit_memory_region(struct kvm *kvm,
10791 const struct kvm_userspace_memory_region *mem,
10792 struct kvm_memory_slot *old,
10793 const struct kvm_memory_slot *new,
10794 enum kvm_mr_change change)
10795 {
10796 if (!kvm->arch.n_requested_mmu_pages)
10797 kvm_mmu_change_mmu_pages(kvm,
10798 kvm_mmu_calculate_default_mmu_pages(kvm));
10799
10800 /*
10801 * FIXME: const-ify all uses of struct kvm_memory_slot.
10802 */
10803 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10804
10805 /* Free the arrays associated with the old memslot. */
10806 if (change == KVM_MR_MOVE)
10807 kvm_arch_free_memslot(kvm, old);
10808 }
10809
10810 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10811 {
10812 kvm_mmu_zap_all(kvm);
10813 }
10814
10815 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10816 struct kvm_memory_slot *slot)
10817 {
10818 kvm_page_track_flush_slot(kvm, slot);
10819 }
10820
10821 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10822 {
10823 return (is_guest_mode(vcpu) &&
10824 kvm_x86_ops.guest_apic_has_interrupt &&
10825 kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10826 }
10827
10828 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10829 {
10830 if (!list_empty_careful(&vcpu->async_pf.done))
10831 return true;
10832
10833 if (kvm_apic_has_events(vcpu))
10834 return true;
10835
10836 if (vcpu->arch.pv.pv_unhalted)
10837 return true;
10838
10839 if (vcpu->arch.exception.pending)
10840 return true;
10841
10842 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10843 (vcpu->arch.nmi_pending &&
10844 kvm_x86_ops.nmi_allowed(vcpu, false)))
10845 return true;
10846
10847 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10848 (vcpu->arch.smi_pending &&
10849 kvm_x86_ops.smi_allowed(vcpu, false)))
10850 return true;
10851
10852 if (kvm_arch_interrupt_allowed(vcpu) &&
10853 (kvm_cpu_has_interrupt(vcpu) ||
10854 kvm_guest_apic_has_interrupt(vcpu)))
10855 return true;
10856
10857 if (kvm_hv_has_stimer_pending(vcpu))
10858 return true;
10859
10860 if (is_guest_mode(vcpu) &&
10861 kvm_x86_ops.nested_ops->hv_timer_pending &&
10862 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10863 return true;
10864
10865 return false;
10866 }
10867
10868 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10869 {
10870 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10871 }
10872
10873 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10874 {
10875 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10876 return true;
10877
10878 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10879 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10880 kvm_test_request(KVM_REQ_EVENT, vcpu))
10881 return true;
10882
10883 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10884 return true;
10885
10886 return false;
10887 }
10888
10889 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10890 {
10891 return vcpu->arch.preempted_in_kernel;
10892 }
10893
10894 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10895 {
10896 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10897 }
10898
10899 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10900 {
10901 return kvm_x86_ops.interrupt_allowed(vcpu, false);
10902 }
10903
10904 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10905 {
10906 /* Can't read the RIP when guest state is protected, just return 0 */
10907 if (vcpu->arch.guest_state_protected)
10908 return 0;
10909
10910 if (is_64_bit_mode(vcpu))
10911 return kvm_rip_read(vcpu);
10912 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10913 kvm_rip_read(vcpu));
10914 }
10915 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10916
10917 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10918 {
10919 return kvm_get_linear_rip(vcpu) == linear_rip;
10920 }
10921 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10922
10923 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10924 {
10925 unsigned long rflags;
10926
10927 rflags = kvm_x86_ops.get_rflags(vcpu);
10928 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10929 rflags &= ~X86_EFLAGS_TF;
10930 return rflags;
10931 }
10932 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10933
10934 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10935 {
10936 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10937 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10938 rflags |= X86_EFLAGS_TF;
10939 kvm_x86_ops.set_rflags(vcpu, rflags);
10940 }
10941
10942 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10943 {
10944 __kvm_set_rflags(vcpu, rflags);
10945 kvm_make_request(KVM_REQ_EVENT, vcpu);
10946 }
10947 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10948
10949 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10950 {
10951 int r;
10952
10953 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10954 work->wakeup_all)
10955 return;
10956
10957 r = kvm_mmu_reload(vcpu);
10958 if (unlikely(r))
10959 return;
10960
10961 if (!vcpu->arch.mmu->direct_map &&
10962 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10963 return;
10964
10965 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10966 }
10967
10968 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10969 {
10970 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10971
10972 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10973 }
10974
10975 static inline u32 kvm_async_pf_next_probe(u32 key)
10976 {
10977 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10978 }
10979
10980 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10981 {
10982 u32 key = kvm_async_pf_hash_fn(gfn);
10983
10984 while (vcpu->arch.apf.gfns[key] != ~0)
10985 key = kvm_async_pf_next_probe(key);
10986
10987 vcpu->arch.apf.gfns[key] = gfn;
10988 }
10989
10990 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10991 {
10992 int i;
10993 u32 key = kvm_async_pf_hash_fn(gfn);
10994
10995 for (i = 0; i < ASYNC_PF_PER_VCPU &&
10996 (vcpu->arch.apf.gfns[key] != gfn &&
10997 vcpu->arch.apf.gfns[key] != ~0); i++)
10998 key = kvm_async_pf_next_probe(key);
10999
11000 return key;
11001 }
11002
11003 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
11004 {
11005 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
11006 }
11007
11008 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
11009 {
11010 u32 i, j, k;
11011
11012 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
11013
11014 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
11015 return;
11016
11017 while (true) {
11018 vcpu->arch.apf.gfns[i] = ~0;
11019 do {
11020 j = kvm_async_pf_next_probe(j);
11021 if (vcpu->arch.apf.gfns[j] == ~0)
11022 return;
11023 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
11024 /*
11025 * k lies cyclically in ]i,j]
11026 * | i.k.j |
11027 * |....j i.k.| or |.k..j i...|
11028 */
11029 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
11030 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
11031 i = j;
11032 }
11033 }
11034
11035 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
11036 {
11037 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
11038
11039 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
11040 sizeof(reason));
11041 }
11042
11043 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
11044 {
11045 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11046
11047 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11048 &token, offset, sizeof(token));
11049 }
11050
11051 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
11052 {
11053 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11054 u32 val;
11055
11056 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11057 &val, offset, sizeof(val)))
11058 return false;
11059
11060 return !val;
11061 }
11062
11063 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
11064 {
11065 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
11066 return false;
11067
11068 if (!kvm_pv_async_pf_enabled(vcpu) ||
11069 (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
11070 return false;
11071
11072 return true;
11073 }
11074
11075 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
11076 {
11077 if (unlikely(!lapic_in_kernel(vcpu) ||
11078 kvm_event_needs_reinjection(vcpu) ||
11079 vcpu->arch.exception.pending))
11080 return false;
11081
11082 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
11083 return false;
11084
11085 /*
11086 * If interrupts are off we cannot even use an artificial
11087 * halt state.
11088 */
11089 return kvm_arch_interrupt_allowed(vcpu);
11090 }
11091
11092 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
11093 struct kvm_async_pf *work)
11094 {
11095 struct x86_exception fault;
11096
11097 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
11098 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
11099
11100 if (kvm_can_deliver_async_pf(vcpu) &&
11101 !apf_put_user_notpresent(vcpu)) {
11102 fault.vector = PF_VECTOR;
11103 fault.error_code_valid = true;
11104 fault.error_code = 0;
11105 fault.nested_page_fault = false;
11106 fault.address = work->arch.token;
11107 fault.async_page_fault = true;
11108 kvm_inject_page_fault(vcpu, &fault);
11109 return true;
11110 } else {
11111 /*
11112 * It is not possible to deliver a paravirtualized asynchronous
11113 * page fault, but putting the guest in an artificial halt state
11114 * can be beneficial nevertheless: if an interrupt arrives, we
11115 * can deliver it timely and perhaps the guest will schedule
11116 * another process. When the instruction that triggered a page
11117 * fault is retried, hopefully the page will be ready in the host.
11118 */
11119 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
11120 return false;
11121 }
11122 }
11123
11124 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
11125 struct kvm_async_pf *work)
11126 {
11127 struct kvm_lapic_irq irq = {
11128 .delivery_mode = APIC_DM_FIXED,
11129 .vector = vcpu->arch.apf.vec
11130 };
11131
11132 if (work->wakeup_all)
11133 work->arch.token = ~0; /* broadcast wakeup */
11134 else
11135 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
11136 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
11137
11138 if ((work->wakeup_all || work->notpresent_injected) &&
11139 kvm_pv_async_pf_enabled(vcpu) &&
11140 !apf_put_user_ready(vcpu, work->arch.token)) {
11141 vcpu->arch.apf.pageready_pending = true;
11142 kvm_apic_set_irq(vcpu, &irq, NULL);
11143 }
11144
11145 vcpu->arch.apf.halted = false;
11146 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11147 }
11148
11149 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
11150 {
11151 kvm_make_request(KVM_REQ_APF_READY, vcpu);
11152 if (!vcpu->arch.apf.pageready_pending)
11153 kvm_vcpu_kick(vcpu);
11154 }
11155
11156 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
11157 {
11158 if (!kvm_pv_async_pf_enabled(vcpu))
11159 return true;
11160 else
11161 return apf_pageready_slot_free(vcpu);
11162 }
11163
11164 void kvm_arch_start_assignment(struct kvm *kvm)
11165 {
11166 atomic_inc(&kvm->arch.assigned_device_count);
11167 }
11168 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
11169
11170 void kvm_arch_end_assignment(struct kvm *kvm)
11171 {
11172 atomic_dec(&kvm->arch.assigned_device_count);
11173 }
11174 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
11175
11176 bool kvm_arch_has_assigned_device(struct kvm *kvm)
11177 {
11178 return atomic_read(&kvm->arch.assigned_device_count);
11179 }
11180 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
11181
11182 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
11183 {
11184 atomic_inc(&kvm->arch.noncoherent_dma_count);
11185 }
11186 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
11187
11188 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
11189 {
11190 atomic_dec(&kvm->arch.noncoherent_dma_count);
11191 }
11192 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
11193
11194 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
11195 {
11196 return atomic_read(&kvm->arch.noncoherent_dma_count);
11197 }
11198 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
11199
11200 bool kvm_arch_has_irq_bypass(void)
11201 {
11202 return true;
11203 }
11204
11205 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
11206 struct irq_bypass_producer *prod)
11207 {
11208 struct kvm_kernel_irqfd *irqfd =
11209 container_of(cons, struct kvm_kernel_irqfd, consumer);
11210 int ret;
11211
11212 irqfd->producer = prod;
11213 kvm_arch_start_assignment(irqfd->kvm);
11214 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
11215 prod->irq, irqfd->gsi, 1);
11216
11217 if (ret)
11218 kvm_arch_end_assignment(irqfd->kvm);
11219
11220 return ret;
11221 }
11222
11223 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
11224 struct irq_bypass_producer *prod)
11225 {
11226 int ret;
11227 struct kvm_kernel_irqfd *irqfd =
11228 container_of(cons, struct kvm_kernel_irqfd, consumer);
11229
11230 WARN_ON(irqfd->producer != prod);
11231 irqfd->producer = NULL;
11232
11233 /*
11234 * When producer of consumer is unregistered, we change back to
11235 * remapped mode, so we can re-use the current implementation
11236 * when the irq is masked/disabled or the consumer side (KVM
11237 * int this case doesn't want to receive the interrupts.
11238 */
11239 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
11240 if (ret)
11241 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
11242 " fails: %d\n", irqfd->consumer.token, ret);
11243
11244 kvm_arch_end_assignment(irqfd->kvm);
11245 }
11246
11247 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
11248 uint32_t guest_irq, bool set)
11249 {
11250 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
11251 }
11252
11253 bool kvm_vector_hashing_enabled(void)
11254 {
11255 return vector_hashing;
11256 }
11257
11258 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11259 {
11260 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11261 }
11262 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11263
11264
11265 int kvm_spec_ctrl_test_value(u64 value)
11266 {
11267 /*
11268 * test that setting IA32_SPEC_CTRL to given value
11269 * is allowed by the host processor
11270 */
11271
11272 u64 saved_value;
11273 unsigned long flags;
11274 int ret = 0;
11275
11276 local_irq_save(flags);
11277
11278 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11279 ret = 1;
11280 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11281 ret = 1;
11282 else
11283 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11284
11285 local_irq_restore(flags);
11286
11287 return ret;
11288 }
11289 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11290
11291 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11292 {
11293 struct x86_exception fault;
11294 u32 access = error_code &
11295 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11296
11297 if (!(error_code & PFERR_PRESENT_MASK) ||
11298 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11299 /*
11300 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11301 * tables probably do not match the TLB. Just proceed
11302 * with the error code that the processor gave.
11303 */
11304 fault.vector = PF_VECTOR;
11305 fault.error_code_valid = true;
11306 fault.error_code = error_code;
11307 fault.nested_page_fault = false;
11308 fault.address = gva;
11309 }
11310 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11311 }
11312 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11313
11314 /*
11315 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11316 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11317 * indicates whether exit to userspace is needed.
11318 */
11319 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11320 struct x86_exception *e)
11321 {
11322 if (r == X86EMUL_PROPAGATE_FAULT) {
11323 kvm_inject_emulated_page_fault(vcpu, e);
11324 return 1;
11325 }
11326
11327 /*
11328 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11329 * while handling a VMX instruction KVM could've handled the request
11330 * correctly by exiting to userspace and performing I/O but there
11331 * doesn't seem to be a real use-case behind such requests, just return
11332 * KVM_EXIT_INTERNAL_ERROR for now.
11333 */
11334 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11335 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11336 vcpu->run->internal.ndata = 0;
11337
11338 return 0;
11339 }
11340 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11341
11342 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11343 {
11344 bool pcid_enabled;
11345 struct x86_exception e;
11346 unsigned i;
11347 unsigned long roots_to_free = 0;
11348 struct {
11349 u64 pcid;
11350 u64 gla;
11351 } operand;
11352 int r;
11353
11354 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11355 if (r != X86EMUL_CONTINUE)
11356 return kvm_handle_memory_failure(vcpu, r, &e);
11357
11358 if (operand.pcid >> 12 != 0) {
11359 kvm_inject_gp(vcpu, 0);
11360 return 1;
11361 }
11362
11363 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11364
11365 switch (type) {
11366 case INVPCID_TYPE_INDIV_ADDR:
11367 if ((!pcid_enabled && (operand.pcid != 0)) ||
11368 is_noncanonical_address(operand.gla, vcpu)) {
11369 kvm_inject_gp(vcpu, 0);
11370 return 1;
11371 }
11372 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11373 return kvm_skip_emulated_instruction(vcpu);
11374
11375 case INVPCID_TYPE_SINGLE_CTXT:
11376 if (!pcid_enabled && (operand.pcid != 0)) {
11377 kvm_inject_gp(vcpu, 0);
11378 return 1;
11379 }
11380
11381 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11382 kvm_mmu_sync_roots(vcpu);
11383 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11384 }
11385
11386 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11387 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11388 == operand.pcid)
11389 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11390
11391 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11392 /*
11393 * If neither the current cr3 nor any of the prev_roots use the
11394 * given PCID, then nothing needs to be done here because a
11395 * resync will happen anyway before switching to any other CR3.
11396 */
11397
11398 return kvm_skip_emulated_instruction(vcpu);
11399
11400 case INVPCID_TYPE_ALL_NON_GLOBAL:
11401 /*
11402 * Currently, KVM doesn't mark global entries in the shadow
11403 * page tables, so a non-global flush just degenerates to a
11404 * global flush. If needed, we could optimize this later by
11405 * keeping track of global entries in shadow page tables.
11406 */
11407
11408 fallthrough;
11409 case INVPCID_TYPE_ALL_INCL_GLOBAL:
11410 kvm_mmu_unload(vcpu);
11411 return kvm_skip_emulated_instruction(vcpu);
11412
11413 default:
11414 BUG(); /* We have already checked above that type <= 3 */
11415 }
11416 }
11417 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11418
11419 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
11420 {
11421 struct kvm_run *run = vcpu->run;
11422 struct kvm_mmio_fragment *frag;
11423 unsigned int len;
11424
11425 BUG_ON(!vcpu->mmio_needed);
11426
11427 /* Complete previous fragment */
11428 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11429 len = min(8u, frag->len);
11430 if (!vcpu->mmio_is_write)
11431 memcpy(frag->data, run->mmio.data, len);
11432
11433 if (frag->len <= 8) {
11434 /* Switch to the next fragment. */
11435 frag++;
11436 vcpu->mmio_cur_fragment++;
11437 } else {
11438 /* Go forward to the next mmio piece. */
11439 frag->data += len;
11440 frag->gpa += len;
11441 frag->len -= len;
11442 }
11443
11444 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11445 vcpu->mmio_needed = 0;
11446
11447 // VMG change, at this point, we're always done
11448 // RIP has already been advanced
11449 return 1;
11450 }
11451
11452 // More MMIO is needed
11453 run->mmio.phys_addr = frag->gpa;
11454 run->mmio.len = min(8u, frag->len);
11455 run->mmio.is_write = vcpu->mmio_is_write;
11456 if (run->mmio.is_write)
11457 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11458 run->exit_reason = KVM_EXIT_MMIO;
11459
11460 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11461
11462 return 0;
11463 }
11464
11465 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11466 void *data)
11467 {
11468 int handled;
11469 struct kvm_mmio_fragment *frag;
11470
11471 if (!data)
11472 return -EINVAL;
11473
11474 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11475 if (handled == bytes)
11476 return 1;
11477
11478 bytes -= handled;
11479 gpa += handled;
11480 data += handled;
11481
11482 /*TODO: Check if need to increment number of frags */
11483 frag = vcpu->mmio_fragments;
11484 vcpu->mmio_nr_fragments = 1;
11485 frag->len = bytes;
11486 frag->gpa = gpa;
11487 frag->data = data;
11488
11489 vcpu->mmio_needed = 1;
11490 vcpu->mmio_cur_fragment = 0;
11491
11492 vcpu->run->mmio.phys_addr = gpa;
11493 vcpu->run->mmio.len = min(8u, frag->len);
11494 vcpu->run->mmio.is_write = 1;
11495 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
11496 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11497
11498 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11499
11500 return 0;
11501 }
11502 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
11503
11504 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11505 void *data)
11506 {
11507 int handled;
11508 struct kvm_mmio_fragment *frag;
11509
11510 if (!data)
11511 return -EINVAL;
11512
11513 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11514 if (handled == bytes)
11515 return 1;
11516
11517 bytes -= handled;
11518 gpa += handled;
11519 data += handled;
11520
11521 /*TODO: Check if need to increment number of frags */
11522 frag = vcpu->mmio_fragments;
11523 vcpu->mmio_nr_fragments = 1;
11524 frag->len = bytes;
11525 frag->gpa = gpa;
11526 frag->data = data;
11527
11528 vcpu->mmio_needed = 1;
11529 vcpu->mmio_cur_fragment = 0;
11530
11531 vcpu->run->mmio.phys_addr = gpa;
11532 vcpu->run->mmio.len = min(8u, frag->len);
11533 vcpu->run->mmio.is_write = 0;
11534 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11535
11536 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11537
11538 return 0;
11539 }
11540 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
11541
11542 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
11543 {
11544 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data,
11545 vcpu->arch.pio.count * vcpu->arch.pio.size);
11546 vcpu->arch.pio.count = 0;
11547
11548 return 1;
11549 }
11550
11551 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
11552 unsigned int port, void *data, unsigned int count)
11553 {
11554 int ret;
11555
11556 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port,
11557 data, count);
11558 if (ret)
11559 return ret;
11560
11561 vcpu->arch.pio.count = 0;
11562
11563 return 0;
11564 }
11565
11566 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
11567 unsigned int port, void *data, unsigned int count)
11568 {
11569 int ret;
11570
11571 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port,
11572 data, count);
11573 if (ret) {
11574 vcpu->arch.pio.count = 0;
11575 } else {
11576 vcpu->arch.guest_ins_data = data;
11577 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
11578 }
11579
11580 return 0;
11581 }
11582
11583 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
11584 unsigned int port, void *data, unsigned int count,
11585 int in)
11586 {
11587 return in ? kvm_sev_es_ins(vcpu, size, port, data, count)
11588 : kvm_sev_es_outs(vcpu, size, port, data, count);
11589 }
11590 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
11591
11592 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
11593 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11594 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11595 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11596 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11597 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11598 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11599 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11600 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11601 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11602 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11603 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11604 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11605 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11606 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11607 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11608 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11609 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11610 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11611 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11612 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11613 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11614 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
11615 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
11616 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
11617 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
11618 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
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