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KVM: x86: use hardware-compatible format for APIC ID register
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <trace/events/kvm.h>
57
58 #define CREATE_TRACE_POINTS
59 #include "trace.h"
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70
71 #define MAX_IO_MSRS 256
72 #define KVM_MAX_MCE_BANKS 32
73 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
74 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
75
76 #define emul_to_vcpu(ctxt) \
77 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
78
79 /* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83 #ifdef CONFIG_X86_64
84 static
85 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
86 #else
87 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
88 #endif
89
90 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
91 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
92
93 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
94 static void process_nmi(struct kvm_vcpu *vcpu);
95 static void enter_smm(struct kvm_vcpu *vcpu);
96 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
97
98 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
99 EXPORT_SYMBOL_GPL(kvm_x86_ops);
100
101 static bool __read_mostly ignore_msrs = 0;
102 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
103
104 unsigned int min_timer_period_us = 500;
105 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
106
107 static bool __read_mostly kvmclock_periodic_sync = true;
108 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
109
110 bool __read_mostly kvm_has_tsc_control;
111 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
112 u32 __read_mostly kvm_max_guest_tsc_khz;
113 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
114 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
115 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
116 u64 __read_mostly kvm_max_tsc_scaling_ratio;
117 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
118 u64 __read_mostly kvm_default_tsc_scaling_ratio;
119 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
120
121 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
122 static u32 __read_mostly tsc_tolerance_ppm = 250;
123 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
124
125 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
126 unsigned int __read_mostly lapic_timer_advance_ns = 0;
127 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
128
129 static bool __read_mostly vector_hashing = true;
130 module_param(vector_hashing, bool, S_IRUGO);
131
132 static bool __read_mostly backwards_tsc_observed = false;
133
134 #define KVM_NR_SHARED_MSRS 16
135
136 struct kvm_shared_msrs_global {
137 int nr;
138 u32 msrs[KVM_NR_SHARED_MSRS];
139 };
140
141 struct kvm_shared_msrs {
142 struct user_return_notifier urn;
143 bool registered;
144 struct kvm_shared_msr_values {
145 u64 host;
146 u64 curr;
147 } values[KVM_NR_SHARED_MSRS];
148 };
149
150 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
151 static struct kvm_shared_msrs __percpu *shared_msrs;
152
153 struct kvm_stats_debugfs_item debugfs_entries[] = {
154 { "pf_fixed", VCPU_STAT(pf_fixed) },
155 { "pf_guest", VCPU_STAT(pf_guest) },
156 { "tlb_flush", VCPU_STAT(tlb_flush) },
157 { "invlpg", VCPU_STAT(invlpg) },
158 { "exits", VCPU_STAT(exits) },
159 { "io_exits", VCPU_STAT(io_exits) },
160 { "mmio_exits", VCPU_STAT(mmio_exits) },
161 { "signal_exits", VCPU_STAT(signal_exits) },
162 { "irq_window", VCPU_STAT(irq_window_exits) },
163 { "nmi_window", VCPU_STAT(nmi_window_exits) },
164 { "halt_exits", VCPU_STAT(halt_exits) },
165 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
166 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
167 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
168 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
169 { "hypercalls", VCPU_STAT(hypercalls) },
170 { "request_irq", VCPU_STAT(request_irq_exits) },
171 { "irq_exits", VCPU_STAT(irq_exits) },
172 { "host_state_reload", VCPU_STAT(host_state_reload) },
173 { "efer_reload", VCPU_STAT(efer_reload) },
174 { "fpu_reload", VCPU_STAT(fpu_reload) },
175 { "insn_emulation", VCPU_STAT(insn_emulation) },
176 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
177 { "irq_injections", VCPU_STAT(irq_injections) },
178 { "nmi_injections", VCPU_STAT(nmi_injections) },
179 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
180 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
181 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
182 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
183 { "mmu_flooded", VM_STAT(mmu_flooded) },
184 { "mmu_recycled", VM_STAT(mmu_recycled) },
185 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
186 { "mmu_unsync", VM_STAT(mmu_unsync) },
187 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
188 { "largepages", VM_STAT(lpages) },
189 { NULL }
190 };
191
192 u64 __read_mostly host_xcr0;
193
194 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
195
196 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
197 {
198 int i;
199 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
200 vcpu->arch.apf.gfns[i] = ~0;
201 }
202
203 static void kvm_on_user_return(struct user_return_notifier *urn)
204 {
205 unsigned slot;
206 struct kvm_shared_msrs *locals
207 = container_of(urn, struct kvm_shared_msrs, urn);
208 struct kvm_shared_msr_values *values;
209
210 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
211 values = &locals->values[slot];
212 if (values->host != values->curr) {
213 wrmsrl(shared_msrs_global.msrs[slot], values->host);
214 values->curr = values->host;
215 }
216 }
217 locals->registered = false;
218 user_return_notifier_unregister(urn);
219 }
220
221 static void shared_msr_update(unsigned slot, u32 msr)
222 {
223 u64 value;
224 unsigned int cpu = smp_processor_id();
225 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
226
227 /* only read, and nobody should modify it at this time,
228 * so don't need lock */
229 if (slot >= shared_msrs_global.nr) {
230 printk(KERN_ERR "kvm: invalid MSR slot!");
231 return;
232 }
233 rdmsrl_safe(msr, &value);
234 smsr->values[slot].host = value;
235 smsr->values[slot].curr = value;
236 }
237
238 void kvm_define_shared_msr(unsigned slot, u32 msr)
239 {
240 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
241 shared_msrs_global.msrs[slot] = msr;
242 if (slot >= shared_msrs_global.nr)
243 shared_msrs_global.nr = slot + 1;
244 }
245 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
246
247 static void kvm_shared_msr_cpu_online(void)
248 {
249 unsigned i;
250
251 for (i = 0; i < shared_msrs_global.nr; ++i)
252 shared_msr_update(i, shared_msrs_global.msrs[i]);
253 }
254
255 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
256 {
257 unsigned int cpu = smp_processor_id();
258 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
259 int err;
260
261 if (((value ^ smsr->values[slot].curr) & mask) == 0)
262 return 0;
263 smsr->values[slot].curr = value;
264 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
265 if (err)
266 return 1;
267
268 if (!smsr->registered) {
269 smsr->urn.on_user_return = kvm_on_user_return;
270 user_return_notifier_register(&smsr->urn);
271 smsr->registered = true;
272 }
273 return 0;
274 }
275 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
276
277 static void drop_user_return_notifiers(void)
278 {
279 unsigned int cpu = smp_processor_id();
280 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
281
282 if (smsr->registered)
283 kvm_on_user_return(&smsr->urn);
284 }
285
286 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
287 {
288 return vcpu->arch.apic_base;
289 }
290 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
291
292 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
293 {
294 u64 old_state = vcpu->arch.apic_base &
295 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
296 u64 new_state = msr_info->data &
297 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
298 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
299 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
300
301 if (!msr_info->host_initiated &&
302 ((msr_info->data & reserved_bits) != 0 ||
303 new_state == X2APIC_ENABLE ||
304 (new_state == MSR_IA32_APICBASE_ENABLE &&
305 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
306 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
307 old_state == 0)))
308 return 1;
309
310 kvm_lapic_set_base(vcpu, msr_info->data);
311 return 0;
312 }
313 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
314
315 asmlinkage __visible void kvm_spurious_fault(void)
316 {
317 /* Fault while not rebooting. We want the trace. */
318 BUG();
319 }
320 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
321
322 #define EXCPT_BENIGN 0
323 #define EXCPT_CONTRIBUTORY 1
324 #define EXCPT_PF 2
325
326 static int exception_class(int vector)
327 {
328 switch (vector) {
329 case PF_VECTOR:
330 return EXCPT_PF;
331 case DE_VECTOR:
332 case TS_VECTOR:
333 case NP_VECTOR:
334 case SS_VECTOR:
335 case GP_VECTOR:
336 return EXCPT_CONTRIBUTORY;
337 default:
338 break;
339 }
340 return EXCPT_BENIGN;
341 }
342
343 #define EXCPT_FAULT 0
344 #define EXCPT_TRAP 1
345 #define EXCPT_ABORT 2
346 #define EXCPT_INTERRUPT 3
347
348 static int exception_type(int vector)
349 {
350 unsigned int mask;
351
352 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
353 return EXCPT_INTERRUPT;
354
355 mask = 1 << vector;
356
357 /* #DB is trap, as instruction watchpoints are handled elsewhere */
358 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
359 return EXCPT_TRAP;
360
361 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
362 return EXCPT_ABORT;
363
364 /* Reserved exceptions will result in fault */
365 return EXCPT_FAULT;
366 }
367
368 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
369 unsigned nr, bool has_error, u32 error_code,
370 bool reinject)
371 {
372 u32 prev_nr;
373 int class1, class2;
374
375 kvm_make_request(KVM_REQ_EVENT, vcpu);
376
377 if (!vcpu->arch.exception.pending) {
378 queue:
379 if (has_error && !is_protmode(vcpu))
380 has_error = false;
381 vcpu->arch.exception.pending = true;
382 vcpu->arch.exception.has_error_code = has_error;
383 vcpu->arch.exception.nr = nr;
384 vcpu->arch.exception.error_code = error_code;
385 vcpu->arch.exception.reinject = reinject;
386 return;
387 }
388
389 /* to check exception */
390 prev_nr = vcpu->arch.exception.nr;
391 if (prev_nr == DF_VECTOR) {
392 /* triple fault -> shutdown */
393 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
394 return;
395 }
396 class1 = exception_class(prev_nr);
397 class2 = exception_class(nr);
398 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
399 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
400 /* generate double fault per SDM Table 5-5 */
401 vcpu->arch.exception.pending = true;
402 vcpu->arch.exception.has_error_code = true;
403 vcpu->arch.exception.nr = DF_VECTOR;
404 vcpu->arch.exception.error_code = 0;
405 } else
406 /* replace previous exception with a new one in a hope
407 that instruction re-execution will regenerate lost
408 exception */
409 goto queue;
410 }
411
412 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
413 {
414 kvm_multiple_exception(vcpu, nr, false, 0, false);
415 }
416 EXPORT_SYMBOL_GPL(kvm_queue_exception);
417
418 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
419 {
420 kvm_multiple_exception(vcpu, nr, false, 0, true);
421 }
422 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
423
424 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
425 {
426 if (err)
427 kvm_inject_gp(vcpu, 0);
428 else
429 kvm_x86_ops->skip_emulated_instruction(vcpu);
430 }
431 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
432
433 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
434 {
435 ++vcpu->stat.pf_guest;
436 vcpu->arch.cr2 = fault->address;
437 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
438 }
439 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
440
441 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
442 {
443 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
444 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
445 else
446 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
447
448 return fault->nested_page_fault;
449 }
450
451 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
452 {
453 atomic_inc(&vcpu->arch.nmi_queued);
454 kvm_make_request(KVM_REQ_NMI, vcpu);
455 }
456 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
457
458 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
459 {
460 kvm_multiple_exception(vcpu, nr, true, error_code, false);
461 }
462 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
463
464 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
465 {
466 kvm_multiple_exception(vcpu, nr, true, error_code, true);
467 }
468 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
469
470 /*
471 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
472 * a #GP and return false.
473 */
474 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
475 {
476 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
477 return true;
478 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
479 return false;
480 }
481 EXPORT_SYMBOL_GPL(kvm_require_cpl);
482
483 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
484 {
485 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
486 return true;
487
488 kvm_queue_exception(vcpu, UD_VECTOR);
489 return false;
490 }
491 EXPORT_SYMBOL_GPL(kvm_require_dr);
492
493 /*
494 * This function will be used to read from the physical memory of the currently
495 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
496 * can read from guest physical or from the guest's guest physical memory.
497 */
498 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
499 gfn_t ngfn, void *data, int offset, int len,
500 u32 access)
501 {
502 struct x86_exception exception;
503 gfn_t real_gfn;
504 gpa_t ngpa;
505
506 ngpa = gfn_to_gpa(ngfn);
507 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
508 if (real_gfn == UNMAPPED_GVA)
509 return -EFAULT;
510
511 real_gfn = gpa_to_gfn(real_gfn);
512
513 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
514 }
515 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
516
517 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
518 void *data, int offset, int len, u32 access)
519 {
520 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
521 data, offset, len, access);
522 }
523
524 /*
525 * Load the pae pdptrs. Return true is they are all valid.
526 */
527 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
528 {
529 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
530 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
531 int i;
532 int ret;
533 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
534
535 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
536 offset * sizeof(u64), sizeof(pdpte),
537 PFERR_USER_MASK|PFERR_WRITE_MASK);
538 if (ret < 0) {
539 ret = 0;
540 goto out;
541 }
542 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
543 if ((pdpte[i] & PT_PRESENT_MASK) &&
544 (pdpte[i] &
545 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
546 ret = 0;
547 goto out;
548 }
549 }
550 ret = 1;
551
552 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
553 __set_bit(VCPU_EXREG_PDPTR,
554 (unsigned long *)&vcpu->arch.regs_avail);
555 __set_bit(VCPU_EXREG_PDPTR,
556 (unsigned long *)&vcpu->arch.regs_dirty);
557 out:
558
559 return ret;
560 }
561 EXPORT_SYMBOL_GPL(load_pdptrs);
562
563 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
564 {
565 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
566 bool changed = true;
567 int offset;
568 gfn_t gfn;
569 int r;
570
571 if (is_long_mode(vcpu) || !is_pae(vcpu))
572 return false;
573
574 if (!test_bit(VCPU_EXREG_PDPTR,
575 (unsigned long *)&vcpu->arch.regs_avail))
576 return true;
577
578 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
579 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
580 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
581 PFERR_USER_MASK | PFERR_WRITE_MASK);
582 if (r < 0)
583 goto out;
584 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
585 out:
586
587 return changed;
588 }
589
590 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
591 {
592 unsigned long old_cr0 = kvm_read_cr0(vcpu);
593 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
594
595 cr0 |= X86_CR0_ET;
596
597 #ifdef CONFIG_X86_64
598 if (cr0 & 0xffffffff00000000UL)
599 return 1;
600 #endif
601
602 cr0 &= ~CR0_RESERVED_BITS;
603
604 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
605 return 1;
606
607 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
608 return 1;
609
610 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
611 #ifdef CONFIG_X86_64
612 if ((vcpu->arch.efer & EFER_LME)) {
613 int cs_db, cs_l;
614
615 if (!is_pae(vcpu))
616 return 1;
617 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
618 if (cs_l)
619 return 1;
620 } else
621 #endif
622 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
623 kvm_read_cr3(vcpu)))
624 return 1;
625 }
626
627 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
628 return 1;
629
630 kvm_x86_ops->set_cr0(vcpu, cr0);
631
632 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
633 kvm_clear_async_pf_completion_queue(vcpu);
634 kvm_async_pf_hash_reset(vcpu);
635 }
636
637 if ((cr0 ^ old_cr0) & update_bits)
638 kvm_mmu_reset_context(vcpu);
639
640 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
641 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
642 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
643 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
644
645 return 0;
646 }
647 EXPORT_SYMBOL_GPL(kvm_set_cr0);
648
649 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
650 {
651 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
652 }
653 EXPORT_SYMBOL_GPL(kvm_lmsw);
654
655 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
656 {
657 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
658 !vcpu->guest_xcr0_loaded) {
659 /* kvm_set_xcr() also depends on this */
660 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
661 vcpu->guest_xcr0_loaded = 1;
662 }
663 }
664
665 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
666 {
667 if (vcpu->guest_xcr0_loaded) {
668 if (vcpu->arch.xcr0 != host_xcr0)
669 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
670 vcpu->guest_xcr0_loaded = 0;
671 }
672 }
673
674 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
675 {
676 u64 xcr0 = xcr;
677 u64 old_xcr0 = vcpu->arch.xcr0;
678 u64 valid_bits;
679
680 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
681 if (index != XCR_XFEATURE_ENABLED_MASK)
682 return 1;
683 if (!(xcr0 & XFEATURE_MASK_FP))
684 return 1;
685 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
686 return 1;
687
688 /*
689 * Do not allow the guest to set bits that we do not support
690 * saving. However, xcr0 bit 0 is always set, even if the
691 * emulated CPU does not support XSAVE (see fx_init).
692 */
693 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
694 if (xcr0 & ~valid_bits)
695 return 1;
696
697 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
698 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
699 return 1;
700
701 if (xcr0 & XFEATURE_MASK_AVX512) {
702 if (!(xcr0 & XFEATURE_MASK_YMM))
703 return 1;
704 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
705 return 1;
706 }
707 vcpu->arch.xcr0 = xcr0;
708
709 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
710 kvm_update_cpuid(vcpu);
711 return 0;
712 }
713
714 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
715 {
716 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
717 __kvm_set_xcr(vcpu, index, xcr)) {
718 kvm_inject_gp(vcpu, 0);
719 return 1;
720 }
721 return 0;
722 }
723 EXPORT_SYMBOL_GPL(kvm_set_xcr);
724
725 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
726 {
727 unsigned long old_cr4 = kvm_read_cr4(vcpu);
728 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
729 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
730
731 if (cr4 & CR4_RESERVED_BITS)
732 return 1;
733
734 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
735 return 1;
736
737 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
738 return 1;
739
740 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
741 return 1;
742
743 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
744 return 1;
745
746 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
747 return 1;
748
749 if (is_long_mode(vcpu)) {
750 if (!(cr4 & X86_CR4_PAE))
751 return 1;
752 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
753 && ((cr4 ^ old_cr4) & pdptr_bits)
754 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
755 kvm_read_cr3(vcpu)))
756 return 1;
757
758 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
759 if (!guest_cpuid_has_pcid(vcpu))
760 return 1;
761
762 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
763 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
764 return 1;
765 }
766
767 if (kvm_x86_ops->set_cr4(vcpu, cr4))
768 return 1;
769
770 if (((cr4 ^ old_cr4) & pdptr_bits) ||
771 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
772 kvm_mmu_reset_context(vcpu);
773
774 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
775 kvm_update_cpuid(vcpu);
776
777 return 0;
778 }
779 EXPORT_SYMBOL_GPL(kvm_set_cr4);
780
781 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
782 {
783 #ifdef CONFIG_X86_64
784 cr3 &= ~CR3_PCID_INVD;
785 #endif
786
787 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
788 kvm_mmu_sync_roots(vcpu);
789 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
790 return 0;
791 }
792
793 if (is_long_mode(vcpu)) {
794 if (cr3 & CR3_L_MODE_RESERVED_BITS)
795 return 1;
796 } else if (is_pae(vcpu) && is_paging(vcpu) &&
797 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
798 return 1;
799
800 vcpu->arch.cr3 = cr3;
801 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
802 kvm_mmu_new_cr3(vcpu);
803 return 0;
804 }
805 EXPORT_SYMBOL_GPL(kvm_set_cr3);
806
807 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
808 {
809 if (cr8 & CR8_RESERVED_BITS)
810 return 1;
811 if (lapic_in_kernel(vcpu))
812 kvm_lapic_set_tpr(vcpu, cr8);
813 else
814 vcpu->arch.cr8 = cr8;
815 return 0;
816 }
817 EXPORT_SYMBOL_GPL(kvm_set_cr8);
818
819 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
820 {
821 if (lapic_in_kernel(vcpu))
822 return kvm_lapic_get_cr8(vcpu);
823 else
824 return vcpu->arch.cr8;
825 }
826 EXPORT_SYMBOL_GPL(kvm_get_cr8);
827
828 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
829 {
830 int i;
831
832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
833 for (i = 0; i < KVM_NR_DB_REGS; i++)
834 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
835 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
836 }
837 }
838
839 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
840 {
841 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
842 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
843 }
844
845 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
846 {
847 unsigned long dr7;
848
849 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
850 dr7 = vcpu->arch.guest_debug_dr7;
851 else
852 dr7 = vcpu->arch.dr7;
853 kvm_x86_ops->set_dr7(vcpu, dr7);
854 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
855 if (dr7 & DR7_BP_EN_MASK)
856 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
857 }
858
859 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
860 {
861 u64 fixed = DR6_FIXED_1;
862
863 if (!guest_cpuid_has_rtm(vcpu))
864 fixed |= DR6_RTM;
865 return fixed;
866 }
867
868 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
869 {
870 switch (dr) {
871 case 0 ... 3:
872 vcpu->arch.db[dr] = val;
873 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
874 vcpu->arch.eff_db[dr] = val;
875 break;
876 case 4:
877 /* fall through */
878 case 6:
879 if (val & 0xffffffff00000000ULL)
880 return -1; /* #GP */
881 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
882 kvm_update_dr6(vcpu);
883 break;
884 case 5:
885 /* fall through */
886 default: /* 7 */
887 if (val & 0xffffffff00000000ULL)
888 return -1; /* #GP */
889 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
890 kvm_update_dr7(vcpu);
891 break;
892 }
893
894 return 0;
895 }
896
897 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
898 {
899 if (__kvm_set_dr(vcpu, dr, val)) {
900 kvm_inject_gp(vcpu, 0);
901 return 1;
902 }
903 return 0;
904 }
905 EXPORT_SYMBOL_GPL(kvm_set_dr);
906
907 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
908 {
909 switch (dr) {
910 case 0 ... 3:
911 *val = vcpu->arch.db[dr];
912 break;
913 case 4:
914 /* fall through */
915 case 6:
916 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
917 *val = vcpu->arch.dr6;
918 else
919 *val = kvm_x86_ops->get_dr6(vcpu);
920 break;
921 case 5:
922 /* fall through */
923 default: /* 7 */
924 *val = vcpu->arch.dr7;
925 break;
926 }
927 return 0;
928 }
929 EXPORT_SYMBOL_GPL(kvm_get_dr);
930
931 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
932 {
933 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
934 u64 data;
935 int err;
936
937 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
938 if (err)
939 return err;
940 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
941 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
942 return err;
943 }
944 EXPORT_SYMBOL_GPL(kvm_rdpmc);
945
946 /*
947 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
948 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
949 *
950 * This list is modified at module load time to reflect the
951 * capabilities of the host cpu. This capabilities test skips MSRs that are
952 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
953 * may depend on host virtualization features rather than host cpu features.
954 */
955
956 static u32 msrs_to_save[] = {
957 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
958 MSR_STAR,
959 #ifdef CONFIG_X86_64
960 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
961 #endif
962 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
963 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
964 };
965
966 static unsigned num_msrs_to_save;
967
968 static u32 emulated_msrs[] = {
969 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
970 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
971 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
972 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
973 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
974 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
975 HV_X64_MSR_RESET,
976 HV_X64_MSR_VP_INDEX,
977 HV_X64_MSR_VP_RUNTIME,
978 HV_X64_MSR_SCONTROL,
979 HV_X64_MSR_STIMER0_CONFIG,
980 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
981 MSR_KVM_PV_EOI_EN,
982
983 MSR_IA32_TSC_ADJUST,
984 MSR_IA32_TSCDEADLINE,
985 MSR_IA32_MISC_ENABLE,
986 MSR_IA32_MCG_STATUS,
987 MSR_IA32_MCG_CTL,
988 MSR_IA32_MCG_EXT_CTL,
989 MSR_IA32_SMBASE,
990 };
991
992 static unsigned num_emulated_msrs;
993
994 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
995 {
996 if (efer & efer_reserved_bits)
997 return false;
998
999 if (efer & EFER_FFXSR) {
1000 struct kvm_cpuid_entry2 *feat;
1001
1002 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1003 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1004 return false;
1005 }
1006
1007 if (efer & EFER_SVME) {
1008 struct kvm_cpuid_entry2 *feat;
1009
1010 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1011 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1012 return false;
1013 }
1014
1015 return true;
1016 }
1017 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1018
1019 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1020 {
1021 u64 old_efer = vcpu->arch.efer;
1022
1023 if (!kvm_valid_efer(vcpu, efer))
1024 return 1;
1025
1026 if (is_paging(vcpu)
1027 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1028 return 1;
1029
1030 efer &= ~EFER_LMA;
1031 efer |= vcpu->arch.efer & EFER_LMA;
1032
1033 kvm_x86_ops->set_efer(vcpu, efer);
1034
1035 /* Update reserved bits */
1036 if ((efer ^ old_efer) & EFER_NX)
1037 kvm_mmu_reset_context(vcpu);
1038
1039 return 0;
1040 }
1041
1042 void kvm_enable_efer_bits(u64 mask)
1043 {
1044 efer_reserved_bits &= ~mask;
1045 }
1046 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1047
1048 /*
1049 * Writes msr value into into the appropriate "register".
1050 * Returns 0 on success, non-0 otherwise.
1051 * Assumes vcpu_load() was already called.
1052 */
1053 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1054 {
1055 switch (msr->index) {
1056 case MSR_FS_BASE:
1057 case MSR_GS_BASE:
1058 case MSR_KERNEL_GS_BASE:
1059 case MSR_CSTAR:
1060 case MSR_LSTAR:
1061 if (is_noncanonical_address(msr->data))
1062 return 1;
1063 break;
1064 case MSR_IA32_SYSENTER_EIP:
1065 case MSR_IA32_SYSENTER_ESP:
1066 /*
1067 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1068 * non-canonical address is written on Intel but not on
1069 * AMD (which ignores the top 32-bits, because it does
1070 * not implement 64-bit SYSENTER).
1071 *
1072 * 64-bit code should hence be able to write a non-canonical
1073 * value on AMD. Making the address canonical ensures that
1074 * vmentry does not fail on Intel after writing a non-canonical
1075 * value, and that something deterministic happens if the guest
1076 * invokes 64-bit SYSENTER.
1077 */
1078 msr->data = get_canonical(msr->data);
1079 }
1080 return kvm_x86_ops->set_msr(vcpu, msr);
1081 }
1082 EXPORT_SYMBOL_GPL(kvm_set_msr);
1083
1084 /*
1085 * Adapt set_msr() to msr_io()'s calling convention
1086 */
1087 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1088 {
1089 struct msr_data msr;
1090 int r;
1091
1092 msr.index = index;
1093 msr.host_initiated = true;
1094 r = kvm_get_msr(vcpu, &msr);
1095 if (r)
1096 return r;
1097
1098 *data = msr.data;
1099 return 0;
1100 }
1101
1102 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1103 {
1104 struct msr_data msr;
1105
1106 msr.data = *data;
1107 msr.index = index;
1108 msr.host_initiated = true;
1109 return kvm_set_msr(vcpu, &msr);
1110 }
1111
1112 #ifdef CONFIG_X86_64
1113 struct pvclock_gtod_data {
1114 seqcount_t seq;
1115
1116 struct { /* extract of a clocksource struct */
1117 int vclock_mode;
1118 cycle_t cycle_last;
1119 cycle_t mask;
1120 u32 mult;
1121 u32 shift;
1122 } clock;
1123
1124 u64 boot_ns;
1125 u64 nsec_base;
1126 };
1127
1128 static struct pvclock_gtod_data pvclock_gtod_data;
1129
1130 static void update_pvclock_gtod(struct timekeeper *tk)
1131 {
1132 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1133 u64 boot_ns;
1134
1135 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1136
1137 write_seqcount_begin(&vdata->seq);
1138
1139 /* copy pvclock gtod data */
1140 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1141 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1142 vdata->clock.mask = tk->tkr_mono.mask;
1143 vdata->clock.mult = tk->tkr_mono.mult;
1144 vdata->clock.shift = tk->tkr_mono.shift;
1145
1146 vdata->boot_ns = boot_ns;
1147 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1148
1149 write_seqcount_end(&vdata->seq);
1150 }
1151 #endif
1152
1153 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1154 {
1155 /*
1156 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1157 * vcpu_enter_guest. This function is only called from
1158 * the physical CPU that is running vcpu.
1159 */
1160 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1161 }
1162
1163 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1164 {
1165 int version;
1166 int r;
1167 struct pvclock_wall_clock wc;
1168 struct timespec64 boot;
1169
1170 if (!wall_clock)
1171 return;
1172
1173 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1174 if (r)
1175 return;
1176
1177 if (version & 1)
1178 ++version; /* first time write, random junk */
1179
1180 ++version;
1181
1182 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1183 return;
1184
1185 /*
1186 * The guest calculates current wall clock time by adding
1187 * system time (updated by kvm_guest_time_update below) to the
1188 * wall clock specified here. guest system time equals host
1189 * system time for us, thus we must fill in host boot time here.
1190 */
1191 getboottime64(&boot);
1192
1193 if (kvm->arch.kvmclock_offset) {
1194 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1195 boot = timespec64_sub(boot, ts);
1196 }
1197 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1198 wc.nsec = boot.tv_nsec;
1199 wc.version = version;
1200
1201 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1202
1203 version++;
1204 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1205 }
1206
1207 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1208 {
1209 do_shl32_div32(dividend, divisor);
1210 return dividend;
1211 }
1212
1213 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1214 s8 *pshift, u32 *pmultiplier)
1215 {
1216 uint64_t scaled64;
1217 int32_t shift = 0;
1218 uint64_t tps64;
1219 uint32_t tps32;
1220
1221 tps64 = base_hz;
1222 scaled64 = scaled_hz;
1223 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1224 tps64 >>= 1;
1225 shift--;
1226 }
1227
1228 tps32 = (uint32_t)tps64;
1229 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1230 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1231 scaled64 >>= 1;
1232 else
1233 tps32 <<= 1;
1234 shift++;
1235 }
1236
1237 *pshift = shift;
1238 *pmultiplier = div_frac(scaled64, tps32);
1239
1240 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1241 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1242 }
1243
1244 #ifdef CONFIG_X86_64
1245 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1246 #endif
1247
1248 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1249 static unsigned long max_tsc_khz;
1250
1251 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1252 {
1253 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1254 vcpu->arch.virtual_tsc_shift);
1255 }
1256
1257 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1258 {
1259 u64 v = (u64)khz * (1000000 + ppm);
1260 do_div(v, 1000000);
1261 return v;
1262 }
1263
1264 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1265 {
1266 u64 ratio;
1267
1268 /* Guest TSC same frequency as host TSC? */
1269 if (!scale) {
1270 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1271 return 0;
1272 }
1273
1274 /* TSC scaling supported? */
1275 if (!kvm_has_tsc_control) {
1276 if (user_tsc_khz > tsc_khz) {
1277 vcpu->arch.tsc_catchup = 1;
1278 vcpu->arch.tsc_always_catchup = 1;
1279 return 0;
1280 } else {
1281 WARN(1, "user requested TSC rate below hardware speed\n");
1282 return -1;
1283 }
1284 }
1285
1286 /* TSC scaling required - calculate ratio */
1287 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1288 user_tsc_khz, tsc_khz);
1289
1290 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1291 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1292 user_tsc_khz);
1293 return -1;
1294 }
1295
1296 vcpu->arch.tsc_scaling_ratio = ratio;
1297 return 0;
1298 }
1299
1300 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1301 {
1302 u32 thresh_lo, thresh_hi;
1303 int use_scaling = 0;
1304
1305 /* tsc_khz can be zero if TSC calibration fails */
1306 if (user_tsc_khz == 0) {
1307 /* set tsc_scaling_ratio to a safe value */
1308 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1309 return -1;
1310 }
1311
1312 /* Compute a scale to convert nanoseconds in TSC cycles */
1313 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1314 &vcpu->arch.virtual_tsc_shift,
1315 &vcpu->arch.virtual_tsc_mult);
1316 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1317
1318 /*
1319 * Compute the variation in TSC rate which is acceptable
1320 * within the range of tolerance and decide if the
1321 * rate being applied is within that bounds of the hardware
1322 * rate. If so, no scaling or compensation need be done.
1323 */
1324 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1325 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1326 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1327 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1328 use_scaling = 1;
1329 }
1330 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1331 }
1332
1333 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1334 {
1335 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1336 vcpu->arch.virtual_tsc_mult,
1337 vcpu->arch.virtual_tsc_shift);
1338 tsc += vcpu->arch.this_tsc_write;
1339 return tsc;
1340 }
1341
1342 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1343 {
1344 #ifdef CONFIG_X86_64
1345 bool vcpus_matched;
1346 struct kvm_arch *ka = &vcpu->kvm->arch;
1347 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1348
1349 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1350 atomic_read(&vcpu->kvm->online_vcpus));
1351
1352 /*
1353 * Once the masterclock is enabled, always perform request in
1354 * order to update it.
1355 *
1356 * In order to enable masterclock, the host clocksource must be TSC
1357 * and the vcpus need to have matched TSCs. When that happens,
1358 * perform request to enable masterclock.
1359 */
1360 if (ka->use_master_clock ||
1361 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1362 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1363
1364 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1365 atomic_read(&vcpu->kvm->online_vcpus),
1366 ka->use_master_clock, gtod->clock.vclock_mode);
1367 #endif
1368 }
1369
1370 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1371 {
1372 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1373 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1374 }
1375
1376 /*
1377 * Multiply tsc by a fixed point number represented by ratio.
1378 *
1379 * The most significant 64-N bits (mult) of ratio represent the
1380 * integral part of the fixed point number; the remaining N bits
1381 * (frac) represent the fractional part, ie. ratio represents a fixed
1382 * point number (mult + frac * 2^(-N)).
1383 *
1384 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1385 */
1386 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1387 {
1388 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1389 }
1390
1391 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1392 {
1393 u64 _tsc = tsc;
1394 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1395
1396 if (ratio != kvm_default_tsc_scaling_ratio)
1397 _tsc = __scale_tsc(ratio, tsc);
1398
1399 return _tsc;
1400 }
1401 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1402
1403 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1404 {
1405 u64 tsc;
1406
1407 tsc = kvm_scale_tsc(vcpu, rdtsc());
1408
1409 return target_tsc - tsc;
1410 }
1411
1412 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1413 {
1414 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1415 }
1416 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1417
1418 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1419 {
1420 struct kvm *kvm = vcpu->kvm;
1421 u64 offset, ns, elapsed;
1422 unsigned long flags;
1423 s64 usdiff;
1424 bool matched;
1425 bool already_matched;
1426 u64 data = msr->data;
1427
1428 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1429 offset = kvm_compute_tsc_offset(vcpu, data);
1430 ns = get_kernel_ns();
1431 elapsed = ns - kvm->arch.last_tsc_nsec;
1432
1433 if (vcpu->arch.virtual_tsc_khz) {
1434 int faulted = 0;
1435
1436 /* n.b - signed multiplication and division required */
1437 usdiff = data - kvm->arch.last_tsc_write;
1438 #ifdef CONFIG_X86_64
1439 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1440 #else
1441 /* do_div() only does unsigned */
1442 asm("1: idivl %[divisor]\n"
1443 "2: xor %%edx, %%edx\n"
1444 " movl $0, %[faulted]\n"
1445 "3:\n"
1446 ".section .fixup,\"ax\"\n"
1447 "4: movl $1, %[faulted]\n"
1448 " jmp 3b\n"
1449 ".previous\n"
1450
1451 _ASM_EXTABLE(1b, 4b)
1452
1453 : "=A"(usdiff), [faulted] "=r" (faulted)
1454 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1455
1456 #endif
1457 do_div(elapsed, 1000);
1458 usdiff -= elapsed;
1459 if (usdiff < 0)
1460 usdiff = -usdiff;
1461
1462 /* idivl overflow => difference is larger than USEC_PER_SEC */
1463 if (faulted)
1464 usdiff = USEC_PER_SEC;
1465 } else
1466 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1467
1468 /*
1469 * Special case: TSC write with a small delta (1 second) of virtual
1470 * cycle time against real time is interpreted as an attempt to
1471 * synchronize the CPU.
1472 *
1473 * For a reliable TSC, we can match TSC offsets, and for an unstable
1474 * TSC, we add elapsed time in this computation. We could let the
1475 * compensation code attempt to catch up if we fall behind, but
1476 * it's better to try to match offsets from the beginning.
1477 */
1478 if (usdiff < USEC_PER_SEC &&
1479 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1480 if (!check_tsc_unstable()) {
1481 offset = kvm->arch.cur_tsc_offset;
1482 pr_debug("kvm: matched tsc offset for %llu\n", data);
1483 } else {
1484 u64 delta = nsec_to_cycles(vcpu, elapsed);
1485 data += delta;
1486 offset = kvm_compute_tsc_offset(vcpu, data);
1487 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1488 }
1489 matched = true;
1490 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1491 } else {
1492 /*
1493 * We split periods of matched TSC writes into generations.
1494 * For each generation, we track the original measured
1495 * nanosecond time, offset, and write, so if TSCs are in
1496 * sync, we can match exact offset, and if not, we can match
1497 * exact software computation in compute_guest_tsc()
1498 *
1499 * These values are tracked in kvm->arch.cur_xxx variables.
1500 */
1501 kvm->arch.cur_tsc_generation++;
1502 kvm->arch.cur_tsc_nsec = ns;
1503 kvm->arch.cur_tsc_write = data;
1504 kvm->arch.cur_tsc_offset = offset;
1505 matched = false;
1506 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1507 kvm->arch.cur_tsc_generation, data);
1508 }
1509
1510 /*
1511 * We also track th most recent recorded KHZ, write and time to
1512 * allow the matching interval to be extended at each write.
1513 */
1514 kvm->arch.last_tsc_nsec = ns;
1515 kvm->arch.last_tsc_write = data;
1516 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1517
1518 vcpu->arch.last_guest_tsc = data;
1519
1520 /* Keep track of which generation this VCPU has synchronized to */
1521 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1522 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1523 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1524
1525 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1526 update_ia32_tsc_adjust_msr(vcpu, offset);
1527 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1528 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1529
1530 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1531 if (!matched) {
1532 kvm->arch.nr_vcpus_matched_tsc = 0;
1533 } else if (!already_matched) {
1534 kvm->arch.nr_vcpus_matched_tsc++;
1535 }
1536
1537 kvm_track_tsc_matching(vcpu);
1538 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1539 }
1540
1541 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1542
1543 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1544 s64 adjustment)
1545 {
1546 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1547 }
1548
1549 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1550 {
1551 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1552 WARN_ON(adjustment < 0);
1553 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1554 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1555 }
1556
1557 #ifdef CONFIG_X86_64
1558
1559 static cycle_t read_tsc(void)
1560 {
1561 cycle_t ret = (cycle_t)rdtsc_ordered();
1562 u64 last = pvclock_gtod_data.clock.cycle_last;
1563
1564 if (likely(ret >= last))
1565 return ret;
1566
1567 /*
1568 * GCC likes to generate cmov here, but this branch is extremely
1569 * predictable (it's just a function of time and the likely is
1570 * very likely) and there's a data dependence, so force GCC
1571 * to generate a branch instead. I don't barrier() because
1572 * we don't actually need a barrier, and if this function
1573 * ever gets inlined it will generate worse code.
1574 */
1575 asm volatile ("");
1576 return last;
1577 }
1578
1579 static inline u64 vgettsc(cycle_t *cycle_now)
1580 {
1581 long v;
1582 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1583
1584 *cycle_now = read_tsc();
1585
1586 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1587 return v * gtod->clock.mult;
1588 }
1589
1590 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1591 {
1592 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1593 unsigned long seq;
1594 int mode;
1595 u64 ns;
1596
1597 do {
1598 seq = read_seqcount_begin(&gtod->seq);
1599 mode = gtod->clock.vclock_mode;
1600 ns = gtod->nsec_base;
1601 ns += vgettsc(cycle_now);
1602 ns >>= gtod->clock.shift;
1603 ns += gtod->boot_ns;
1604 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1605 *t = ns;
1606
1607 return mode;
1608 }
1609
1610 /* returns true if host is using tsc clocksource */
1611 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1612 {
1613 /* checked again under seqlock below */
1614 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1615 return false;
1616
1617 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1618 }
1619 #endif
1620
1621 /*
1622 *
1623 * Assuming a stable TSC across physical CPUS, and a stable TSC
1624 * across virtual CPUs, the following condition is possible.
1625 * Each numbered line represents an event visible to both
1626 * CPUs at the next numbered event.
1627 *
1628 * "timespecX" represents host monotonic time. "tscX" represents
1629 * RDTSC value.
1630 *
1631 * VCPU0 on CPU0 | VCPU1 on CPU1
1632 *
1633 * 1. read timespec0,tsc0
1634 * 2. | timespec1 = timespec0 + N
1635 * | tsc1 = tsc0 + M
1636 * 3. transition to guest | transition to guest
1637 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1638 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1639 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1640 *
1641 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1642 *
1643 * - ret0 < ret1
1644 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1645 * ...
1646 * - 0 < N - M => M < N
1647 *
1648 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1649 * always the case (the difference between two distinct xtime instances
1650 * might be smaller then the difference between corresponding TSC reads,
1651 * when updating guest vcpus pvclock areas).
1652 *
1653 * To avoid that problem, do not allow visibility of distinct
1654 * system_timestamp/tsc_timestamp values simultaneously: use a master
1655 * copy of host monotonic time values. Update that master copy
1656 * in lockstep.
1657 *
1658 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1659 *
1660 */
1661
1662 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1663 {
1664 #ifdef CONFIG_X86_64
1665 struct kvm_arch *ka = &kvm->arch;
1666 int vclock_mode;
1667 bool host_tsc_clocksource, vcpus_matched;
1668
1669 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1670 atomic_read(&kvm->online_vcpus));
1671
1672 /*
1673 * If the host uses TSC clock, then passthrough TSC as stable
1674 * to the guest.
1675 */
1676 host_tsc_clocksource = kvm_get_time_and_clockread(
1677 &ka->master_kernel_ns,
1678 &ka->master_cycle_now);
1679
1680 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1681 && !backwards_tsc_observed
1682 && !ka->boot_vcpu_runs_old_kvmclock;
1683
1684 if (ka->use_master_clock)
1685 atomic_set(&kvm_guest_has_master_clock, 1);
1686
1687 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1688 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1689 vcpus_matched);
1690 #endif
1691 }
1692
1693 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1694 {
1695 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1696 }
1697
1698 static void kvm_gen_update_masterclock(struct kvm *kvm)
1699 {
1700 #ifdef CONFIG_X86_64
1701 int i;
1702 struct kvm_vcpu *vcpu;
1703 struct kvm_arch *ka = &kvm->arch;
1704
1705 spin_lock(&ka->pvclock_gtod_sync_lock);
1706 kvm_make_mclock_inprogress_request(kvm);
1707 /* no guest entries from this point */
1708 pvclock_update_vm_gtod_copy(kvm);
1709
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1712
1713 /* guest entries allowed */
1714 kvm_for_each_vcpu(i, vcpu, kvm)
1715 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1716
1717 spin_unlock(&ka->pvclock_gtod_sync_lock);
1718 #endif
1719 }
1720
1721 static int kvm_guest_time_update(struct kvm_vcpu *v)
1722 {
1723 unsigned long flags, tgt_tsc_khz;
1724 struct kvm_vcpu_arch *vcpu = &v->arch;
1725 struct kvm_arch *ka = &v->kvm->arch;
1726 s64 kernel_ns;
1727 u64 tsc_timestamp, host_tsc;
1728 struct pvclock_vcpu_time_info guest_hv_clock;
1729 u8 pvclock_flags;
1730 bool use_master_clock;
1731
1732 kernel_ns = 0;
1733 host_tsc = 0;
1734
1735 /*
1736 * If the host uses TSC clock, then passthrough TSC as stable
1737 * to the guest.
1738 */
1739 spin_lock(&ka->pvclock_gtod_sync_lock);
1740 use_master_clock = ka->use_master_clock;
1741 if (use_master_clock) {
1742 host_tsc = ka->master_cycle_now;
1743 kernel_ns = ka->master_kernel_ns;
1744 }
1745 spin_unlock(&ka->pvclock_gtod_sync_lock);
1746
1747 /* Keep irq disabled to prevent changes to the clock */
1748 local_irq_save(flags);
1749 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1750 if (unlikely(tgt_tsc_khz == 0)) {
1751 local_irq_restore(flags);
1752 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1753 return 1;
1754 }
1755 if (!use_master_clock) {
1756 host_tsc = rdtsc();
1757 kernel_ns = get_kernel_ns();
1758 }
1759
1760 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1761
1762 /*
1763 * We may have to catch up the TSC to match elapsed wall clock
1764 * time for two reasons, even if kvmclock is used.
1765 * 1) CPU could have been running below the maximum TSC rate
1766 * 2) Broken TSC compensation resets the base at each VCPU
1767 * entry to avoid unknown leaps of TSC even when running
1768 * again on the same CPU. This may cause apparent elapsed
1769 * time to disappear, and the guest to stand still or run
1770 * very slowly.
1771 */
1772 if (vcpu->tsc_catchup) {
1773 u64 tsc = compute_guest_tsc(v, kernel_ns);
1774 if (tsc > tsc_timestamp) {
1775 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1776 tsc_timestamp = tsc;
1777 }
1778 }
1779
1780 local_irq_restore(flags);
1781
1782 if (!vcpu->pv_time_enabled)
1783 return 0;
1784
1785 if (kvm_has_tsc_control)
1786 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1787
1788 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1789 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1790 &vcpu->hv_clock.tsc_shift,
1791 &vcpu->hv_clock.tsc_to_system_mul);
1792 vcpu->hw_tsc_khz = tgt_tsc_khz;
1793 }
1794
1795 /* With all the info we got, fill in the values */
1796 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1797 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1798 vcpu->last_guest_tsc = tsc_timestamp;
1799
1800 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1801 &guest_hv_clock, sizeof(guest_hv_clock))))
1802 return 0;
1803
1804 /* This VCPU is paused, but it's legal for a guest to read another
1805 * VCPU's kvmclock, so we really have to follow the specification where
1806 * it says that version is odd if data is being modified, and even after
1807 * it is consistent.
1808 *
1809 * Version field updates must be kept separate. This is because
1810 * kvm_write_guest_cached might use a "rep movs" instruction, and
1811 * writes within a string instruction are weakly ordered. So there
1812 * are three writes overall.
1813 *
1814 * As a small optimization, only write the version field in the first
1815 * and third write. The vcpu->pv_time cache is still valid, because the
1816 * version field is the first in the struct.
1817 */
1818 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1819
1820 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1821 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1822 &vcpu->hv_clock,
1823 sizeof(vcpu->hv_clock.version));
1824
1825 smp_wmb();
1826
1827 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1828 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1829
1830 if (vcpu->pvclock_set_guest_stopped_request) {
1831 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1832 vcpu->pvclock_set_guest_stopped_request = false;
1833 }
1834
1835 /* If the host uses TSC clocksource, then it is stable */
1836 if (use_master_clock)
1837 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1838
1839 vcpu->hv_clock.flags = pvclock_flags;
1840
1841 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1842
1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1844 &vcpu->hv_clock,
1845 sizeof(vcpu->hv_clock));
1846
1847 smp_wmb();
1848
1849 vcpu->hv_clock.version++;
1850 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1851 &vcpu->hv_clock,
1852 sizeof(vcpu->hv_clock.version));
1853 return 0;
1854 }
1855
1856 /*
1857 * kvmclock updates which are isolated to a given vcpu, such as
1858 * vcpu->cpu migration, should not allow system_timestamp from
1859 * the rest of the vcpus to remain static. Otherwise ntp frequency
1860 * correction applies to one vcpu's system_timestamp but not
1861 * the others.
1862 *
1863 * So in those cases, request a kvmclock update for all vcpus.
1864 * We need to rate-limit these requests though, as they can
1865 * considerably slow guests that have a large number of vcpus.
1866 * The time for a remote vcpu to update its kvmclock is bound
1867 * by the delay we use to rate-limit the updates.
1868 */
1869
1870 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1871
1872 static void kvmclock_update_fn(struct work_struct *work)
1873 {
1874 int i;
1875 struct delayed_work *dwork = to_delayed_work(work);
1876 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1877 kvmclock_update_work);
1878 struct kvm *kvm = container_of(ka, struct kvm, arch);
1879 struct kvm_vcpu *vcpu;
1880
1881 kvm_for_each_vcpu(i, vcpu, kvm) {
1882 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1883 kvm_vcpu_kick(vcpu);
1884 }
1885 }
1886
1887 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1888 {
1889 struct kvm *kvm = v->kvm;
1890
1891 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1892 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1893 KVMCLOCK_UPDATE_DELAY);
1894 }
1895
1896 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1897
1898 static void kvmclock_sync_fn(struct work_struct *work)
1899 {
1900 struct delayed_work *dwork = to_delayed_work(work);
1901 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1902 kvmclock_sync_work);
1903 struct kvm *kvm = container_of(ka, struct kvm, arch);
1904
1905 if (!kvmclock_periodic_sync)
1906 return;
1907
1908 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1909 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1910 KVMCLOCK_SYNC_PERIOD);
1911 }
1912
1913 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1914 {
1915 u64 mcg_cap = vcpu->arch.mcg_cap;
1916 unsigned bank_num = mcg_cap & 0xff;
1917
1918 switch (msr) {
1919 case MSR_IA32_MCG_STATUS:
1920 vcpu->arch.mcg_status = data;
1921 break;
1922 case MSR_IA32_MCG_CTL:
1923 if (!(mcg_cap & MCG_CTL_P))
1924 return 1;
1925 if (data != 0 && data != ~(u64)0)
1926 return -1;
1927 vcpu->arch.mcg_ctl = data;
1928 break;
1929 default:
1930 if (msr >= MSR_IA32_MC0_CTL &&
1931 msr < MSR_IA32_MCx_CTL(bank_num)) {
1932 u32 offset = msr - MSR_IA32_MC0_CTL;
1933 /* only 0 or all 1s can be written to IA32_MCi_CTL
1934 * some Linux kernels though clear bit 10 in bank 4 to
1935 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1936 * this to avoid an uncatched #GP in the guest
1937 */
1938 if ((offset & 0x3) == 0 &&
1939 data != 0 && (data | (1 << 10)) != ~(u64)0)
1940 return -1;
1941 vcpu->arch.mce_banks[offset] = data;
1942 break;
1943 }
1944 return 1;
1945 }
1946 return 0;
1947 }
1948
1949 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1950 {
1951 struct kvm *kvm = vcpu->kvm;
1952 int lm = is_long_mode(vcpu);
1953 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1954 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1955 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1956 : kvm->arch.xen_hvm_config.blob_size_32;
1957 u32 page_num = data & ~PAGE_MASK;
1958 u64 page_addr = data & PAGE_MASK;
1959 u8 *page;
1960 int r;
1961
1962 r = -E2BIG;
1963 if (page_num >= blob_size)
1964 goto out;
1965 r = -ENOMEM;
1966 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1967 if (IS_ERR(page)) {
1968 r = PTR_ERR(page);
1969 goto out;
1970 }
1971 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1972 goto out_free;
1973 r = 0;
1974 out_free:
1975 kfree(page);
1976 out:
1977 return r;
1978 }
1979
1980 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1981 {
1982 gpa_t gpa = data & ~0x3f;
1983
1984 /* Bits 2:5 are reserved, Should be zero */
1985 if (data & 0x3c)
1986 return 1;
1987
1988 vcpu->arch.apf.msr_val = data;
1989
1990 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1991 kvm_clear_async_pf_completion_queue(vcpu);
1992 kvm_async_pf_hash_reset(vcpu);
1993 return 0;
1994 }
1995
1996 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1997 sizeof(u32)))
1998 return 1;
1999
2000 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2001 kvm_async_pf_wakeup_all(vcpu);
2002 return 0;
2003 }
2004
2005 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2006 {
2007 vcpu->arch.pv_time_enabled = false;
2008 }
2009
2010 static void record_steal_time(struct kvm_vcpu *vcpu)
2011 {
2012 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2013 return;
2014
2015 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2016 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2017 return;
2018
2019 if (vcpu->arch.st.steal.version & 1)
2020 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2021
2022 vcpu->arch.st.steal.version += 1;
2023
2024 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2026
2027 smp_wmb();
2028
2029 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2030 vcpu->arch.st.last_steal;
2031 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2032
2033 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2034 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2035
2036 smp_wmb();
2037
2038 vcpu->arch.st.steal.version += 1;
2039
2040 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2041 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2042 }
2043
2044 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2045 {
2046 bool pr = false;
2047 u32 msr = msr_info->index;
2048 u64 data = msr_info->data;
2049
2050 switch (msr) {
2051 case MSR_AMD64_NB_CFG:
2052 case MSR_IA32_UCODE_REV:
2053 case MSR_IA32_UCODE_WRITE:
2054 case MSR_VM_HSAVE_PA:
2055 case MSR_AMD64_PATCH_LOADER:
2056 case MSR_AMD64_BU_CFG2:
2057 break;
2058
2059 case MSR_EFER:
2060 return set_efer(vcpu, data);
2061 case MSR_K7_HWCR:
2062 data &= ~(u64)0x40; /* ignore flush filter disable */
2063 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2064 data &= ~(u64)0x8; /* ignore TLB cache disable */
2065 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2066 if (data != 0) {
2067 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2068 data);
2069 return 1;
2070 }
2071 break;
2072 case MSR_FAM10H_MMIO_CONF_BASE:
2073 if (data != 0) {
2074 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2075 "0x%llx\n", data);
2076 return 1;
2077 }
2078 break;
2079 case MSR_IA32_DEBUGCTLMSR:
2080 if (!data) {
2081 /* We support the non-activated case already */
2082 break;
2083 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2084 /* Values other than LBR and BTF are vendor-specific,
2085 thus reserved and should throw a #GP */
2086 return 1;
2087 }
2088 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2089 __func__, data);
2090 break;
2091 case 0x200 ... 0x2ff:
2092 return kvm_mtrr_set_msr(vcpu, msr, data);
2093 case MSR_IA32_APICBASE:
2094 return kvm_set_apic_base(vcpu, msr_info);
2095 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2096 return kvm_x2apic_msr_write(vcpu, msr, data);
2097 case MSR_IA32_TSCDEADLINE:
2098 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2099 break;
2100 case MSR_IA32_TSC_ADJUST:
2101 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2102 if (!msr_info->host_initiated) {
2103 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2104 adjust_tsc_offset_guest(vcpu, adj);
2105 }
2106 vcpu->arch.ia32_tsc_adjust_msr = data;
2107 }
2108 break;
2109 case MSR_IA32_MISC_ENABLE:
2110 vcpu->arch.ia32_misc_enable_msr = data;
2111 break;
2112 case MSR_IA32_SMBASE:
2113 if (!msr_info->host_initiated)
2114 return 1;
2115 vcpu->arch.smbase = data;
2116 break;
2117 case MSR_KVM_WALL_CLOCK_NEW:
2118 case MSR_KVM_WALL_CLOCK:
2119 vcpu->kvm->arch.wall_clock = data;
2120 kvm_write_wall_clock(vcpu->kvm, data);
2121 break;
2122 case MSR_KVM_SYSTEM_TIME_NEW:
2123 case MSR_KVM_SYSTEM_TIME: {
2124 u64 gpa_offset;
2125 struct kvm_arch *ka = &vcpu->kvm->arch;
2126
2127 kvmclock_reset(vcpu);
2128
2129 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2130 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2131
2132 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2133 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2134 &vcpu->requests);
2135
2136 ka->boot_vcpu_runs_old_kvmclock = tmp;
2137 }
2138
2139 vcpu->arch.time = data;
2140 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2141
2142 /* we verify if the enable bit is set... */
2143 if (!(data & 1))
2144 break;
2145
2146 gpa_offset = data & ~(PAGE_MASK | 1);
2147
2148 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2149 &vcpu->arch.pv_time, data & ~1ULL,
2150 sizeof(struct pvclock_vcpu_time_info)))
2151 vcpu->arch.pv_time_enabled = false;
2152 else
2153 vcpu->arch.pv_time_enabled = true;
2154
2155 break;
2156 }
2157 case MSR_KVM_ASYNC_PF_EN:
2158 if (kvm_pv_enable_async_pf(vcpu, data))
2159 return 1;
2160 break;
2161 case MSR_KVM_STEAL_TIME:
2162
2163 if (unlikely(!sched_info_on()))
2164 return 1;
2165
2166 if (data & KVM_STEAL_RESERVED_MASK)
2167 return 1;
2168
2169 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2170 data & KVM_STEAL_VALID_BITS,
2171 sizeof(struct kvm_steal_time)))
2172 return 1;
2173
2174 vcpu->arch.st.msr_val = data;
2175
2176 if (!(data & KVM_MSR_ENABLED))
2177 break;
2178
2179 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2180
2181 break;
2182 case MSR_KVM_PV_EOI_EN:
2183 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2184 return 1;
2185 break;
2186
2187 case MSR_IA32_MCG_CTL:
2188 case MSR_IA32_MCG_STATUS:
2189 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2190 return set_msr_mce(vcpu, msr, data);
2191
2192 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2193 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2194 pr = true; /* fall through */
2195 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2196 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2197 if (kvm_pmu_is_valid_msr(vcpu, msr))
2198 return kvm_pmu_set_msr(vcpu, msr_info);
2199
2200 if (pr || data != 0)
2201 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2202 "0x%x data 0x%llx\n", msr, data);
2203 break;
2204 case MSR_K7_CLK_CTL:
2205 /*
2206 * Ignore all writes to this no longer documented MSR.
2207 * Writes are only relevant for old K7 processors,
2208 * all pre-dating SVM, but a recommended workaround from
2209 * AMD for these chips. It is possible to specify the
2210 * affected processor models on the command line, hence
2211 * the need to ignore the workaround.
2212 */
2213 break;
2214 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2215 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2216 case HV_X64_MSR_CRASH_CTL:
2217 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2218 return kvm_hv_set_msr_common(vcpu, msr, data,
2219 msr_info->host_initiated);
2220 case MSR_IA32_BBL_CR_CTL3:
2221 /* Drop writes to this legacy MSR -- see rdmsr
2222 * counterpart for further detail.
2223 */
2224 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2225 break;
2226 case MSR_AMD64_OSVW_ID_LENGTH:
2227 if (!guest_cpuid_has_osvw(vcpu))
2228 return 1;
2229 vcpu->arch.osvw.length = data;
2230 break;
2231 case MSR_AMD64_OSVW_STATUS:
2232 if (!guest_cpuid_has_osvw(vcpu))
2233 return 1;
2234 vcpu->arch.osvw.status = data;
2235 break;
2236 default:
2237 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2238 return xen_hvm_config(vcpu, data);
2239 if (kvm_pmu_is_valid_msr(vcpu, msr))
2240 return kvm_pmu_set_msr(vcpu, msr_info);
2241 if (!ignore_msrs) {
2242 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2243 msr, data);
2244 return 1;
2245 } else {
2246 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2247 msr, data);
2248 break;
2249 }
2250 }
2251 return 0;
2252 }
2253 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2254
2255
2256 /*
2257 * Reads an msr value (of 'msr_index') into 'pdata'.
2258 * Returns 0 on success, non-0 otherwise.
2259 * Assumes vcpu_load() was already called.
2260 */
2261 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2262 {
2263 return kvm_x86_ops->get_msr(vcpu, msr);
2264 }
2265 EXPORT_SYMBOL_GPL(kvm_get_msr);
2266
2267 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2268 {
2269 u64 data;
2270 u64 mcg_cap = vcpu->arch.mcg_cap;
2271 unsigned bank_num = mcg_cap & 0xff;
2272
2273 switch (msr) {
2274 case MSR_IA32_P5_MC_ADDR:
2275 case MSR_IA32_P5_MC_TYPE:
2276 data = 0;
2277 break;
2278 case MSR_IA32_MCG_CAP:
2279 data = vcpu->arch.mcg_cap;
2280 break;
2281 case MSR_IA32_MCG_CTL:
2282 if (!(mcg_cap & MCG_CTL_P))
2283 return 1;
2284 data = vcpu->arch.mcg_ctl;
2285 break;
2286 case MSR_IA32_MCG_STATUS:
2287 data = vcpu->arch.mcg_status;
2288 break;
2289 default:
2290 if (msr >= MSR_IA32_MC0_CTL &&
2291 msr < MSR_IA32_MCx_CTL(bank_num)) {
2292 u32 offset = msr - MSR_IA32_MC0_CTL;
2293 data = vcpu->arch.mce_banks[offset];
2294 break;
2295 }
2296 return 1;
2297 }
2298 *pdata = data;
2299 return 0;
2300 }
2301
2302 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2303 {
2304 switch (msr_info->index) {
2305 case MSR_IA32_PLATFORM_ID:
2306 case MSR_IA32_EBL_CR_POWERON:
2307 case MSR_IA32_DEBUGCTLMSR:
2308 case MSR_IA32_LASTBRANCHFROMIP:
2309 case MSR_IA32_LASTBRANCHTOIP:
2310 case MSR_IA32_LASTINTFROMIP:
2311 case MSR_IA32_LASTINTTOIP:
2312 case MSR_K8_SYSCFG:
2313 case MSR_K8_TSEG_ADDR:
2314 case MSR_K8_TSEG_MASK:
2315 case MSR_K7_HWCR:
2316 case MSR_VM_HSAVE_PA:
2317 case MSR_K8_INT_PENDING_MSG:
2318 case MSR_AMD64_NB_CFG:
2319 case MSR_FAM10H_MMIO_CONF_BASE:
2320 case MSR_AMD64_BU_CFG2:
2321 case MSR_IA32_PERF_CTL:
2322 msr_info->data = 0;
2323 break;
2324 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2325 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2326 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2327 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2328 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2329 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2330 msr_info->data = 0;
2331 break;
2332 case MSR_IA32_UCODE_REV:
2333 msr_info->data = 0x100000000ULL;
2334 break;
2335 case MSR_MTRRcap:
2336 case 0x200 ... 0x2ff:
2337 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2338 case 0xcd: /* fsb frequency */
2339 msr_info->data = 3;
2340 break;
2341 /*
2342 * MSR_EBC_FREQUENCY_ID
2343 * Conservative value valid for even the basic CPU models.
2344 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2345 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2346 * and 266MHz for model 3, or 4. Set Core Clock
2347 * Frequency to System Bus Frequency Ratio to 1 (bits
2348 * 31:24) even though these are only valid for CPU
2349 * models > 2, however guests may end up dividing or
2350 * multiplying by zero otherwise.
2351 */
2352 case MSR_EBC_FREQUENCY_ID:
2353 msr_info->data = 1 << 24;
2354 break;
2355 case MSR_IA32_APICBASE:
2356 msr_info->data = kvm_get_apic_base(vcpu);
2357 break;
2358 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2359 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2360 break;
2361 case MSR_IA32_TSCDEADLINE:
2362 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2363 break;
2364 case MSR_IA32_TSC_ADJUST:
2365 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2366 break;
2367 case MSR_IA32_MISC_ENABLE:
2368 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2369 break;
2370 case MSR_IA32_SMBASE:
2371 if (!msr_info->host_initiated)
2372 return 1;
2373 msr_info->data = vcpu->arch.smbase;
2374 break;
2375 case MSR_IA32_PERF_STATUS:
2376 /* TSC increment by tick */
2377 msr_info->data = 1000ULL;
2378 /* CPU multiplier */
2379 msr_info->data |= (((uint64_t)4ULL) << 40);
2380 break;
2381 case MSR_EFER:
2382 msr_info->data = vcpu->arch.efer;
2383 break;
2384 case MSR_KVM_WALL_CLOCK:
2385 case MSR_KVM_WALL_CLOCK_NEW:
2386 msr_info->data = vcpu->kvm->arch.wall_clock;
2387 break;
2388 case MSR_KVM_SYSTEM_TIME:
2389 case MSR_KVM_SYSTEM_TIME_NEW:
2390 msr_info->data = vcpu->arch.time;
2391 break;
2392 case MSR_KVM_ASYNC_PF_EN:
2393 msr_info->data = vcpu->arch.apf.msr_val;
2394 break;
2395 case MSR_KVM_STEAL_TIME:
2396 msr_info->data = vcpu->arch.st.msr_val;
2397 break;
2398 case MSR_KVM_PV_EOI_EN:
2399 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2400 break;
2401 case MSR_IA32_P5_MC_ADDR:
2402 case MSR_IA32_P5_MC_TYPE:
2403 case MSR_IA32_MCG_CAP:
2404 case MSR_IA32_MCG_CTL:
2405 case MSR_IA32_MCG_STATUS:
2406 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2407 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2408 case MSR_K7_CLK_CTL:
2409 /*
2410 * Provide expected ramp-up count for K7. All other
2411 * are set to zero, indicating minimum divisors for
2412 * every field.
2413 *
2414 * This prevents guest kernels on AMD host with CPU
2415 * type 6, model 8 and higher from exploding due to
2416 * the rdmsr failing.
2417 */
2418 msr_info->data = 0x20000000;
2419 break;
2420 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2421 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2422 case HV_X64_MSR_CRASH_CTL:
2423 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2424 return kvm_hv_get_msr_common(vcpu,
2425 msr_info->index, &msr_info->data);
2426 break;
2427 case MSR_IA32_BBL_CR_CTL3:
2428 /* This legacy MSR exists but isn't fully documented in current
2429 * silicon. It is however accessed by winxp in very narrow
2430 * scenarios where it sets bit #19, itself documented as
2431 * a "reserved" bit. Best effort attempt to source coherent
2432 * read data here should the balance of the register be
2433 * interpreted by the guest:
2434 *
2435 * L2 cache control register 3: 64GB range, 256KB size,
2436 * enabled, latency 0x1, configured
2437 */
2438 msr_info->data = 0xbe702111;
2439 break;
2440 case MSR_AMD64_OSVW_ID_LENGTH:
2441 if (!guest_cpuid_has_osvw(vcpu))
2442 return 1;
2443 msr_info->data = vcpu->arch.osvw.length;
2444 break;
2445 case MSR_AMD64_OSVW_STATUS:
2446 if (!guest_cpuid_has_osvw(vcpu))
2447 return 1;
2448 msr_info->data = vcpu->arch.osvw.status;
2449 break;
2450 default:
2451 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2452 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2453 if (!ignore_msrs) {
2454 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2455 return 1;
2456 } else {
2457 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2458 msr_info->data = 0;
2459 }
2460 break;
2461 }
2462 return 0;
2463 }
2464 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2465
2466 /*
2467 * Read or write a bunch of msrs. All parameters are kernel addresses.
2468 *
2469 * @return number of msrs set successfully.
2470 */
2471 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2472 struct kvm_msr_entry *entries,
2473 int (*do_msr)(struct kvm_vcpu *vcpu,
2474 unsigned index, u64 *data))
2475 {
2476 int i, idx;
2477
2478 idx = srcu_read_lock(&vcpu->kvm->srcu);
2479 for (i = 0; i < msrs->nmsrs; ++i)
2480 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2481 break;
2482 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2483
2484 return i;
2485 }
2486
2487 /*
2488 * Read or write a bunch of msrs. Parameters are user addresses.
2489 *
2490 * @return number of msrs set successfully.
2491 */
2492 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2493 int (*do_msr)(struct kvm_vcpu *vcpu,
2494 unsigned index, u64 *data),
2495 int writeback)
2496 {
2497 struct kvm_msrs msrs;
2498 struct kvm_msr_entry *entries;
2499 int r, n;
2500 unsigned size;
2501
2502 r = -EFAULT;
2503 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2504 goto out;
2505
2506 r = -E2BIG;
2507 if (msrs.nmsrs >= MAX_IO_MSRS)
2508 goto out;
2509
2510 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2511 entries = memdup_user(user_msrs->entries, size);
2512 if (IS_ERR(entries)) {
2513 r = PTR_ERR(entries);
2514 goto out;
2515 }
2516
2517 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2518 if (r < 0)
2519 goto out_free;
2520
2521 r = -EFAULT;
2522 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2523 goto out_free;
2524
2525 r = n;
2526
2527 out_free:
2528 kfree(entries);
2529 out:
2530 return r;
2531 }
2532
2533 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2534 {
2535 int r;
2536
2537 switch (ext) {
2538 case KVM_CAP_IRQCHIP:
2539 case KVM_CAP_HLT:
2540 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2541 case KVM_CAP_SET_TSS_ADDR:
2542 case KVM_CAP_EXT_CPUID:
2543 case KVM_CAP_EXT_EMUL_CPUID:
2544 case KVM_CAP_CLOCKSOURCE:
2545 case KVM_CAP_PIT:
2546 case KVM_CAP_NOP_IO_DELAY:
2547 case KVM_CAP_MP_STATE:
2548 case KVM_CAP_SYNC_MMU:
2549 case KVM_CAP_USER_NMI:
2550 case KVM_CAP_REINJECT_CONTROL:
2551 case KVM_CAP_IRQ_INJECT_STATUS:
2552 case KVM_CAP_IOEVENTFD:
2553 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2554 case KVM_CAP_PIT2:
2555 case KVM_CAP_PIT_STATE2:
2556 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2557 case KVM_CAP_XEN_HVM:
2558 case KVM_CAP_ADJUST_CLOCK:
2559 case KVM_CAP_VCPU_EVENTS:
2560 case KVM_CAP_HYPERV:
2561 case KVM_CAP_HYPERV_VAPIC:
2562 case KVM_CAP_HYPERV_SPIN:
2563 case KVM_CAP_HYPERV_SYNIC:
2564 case KVM_CAP_PCI_SEGMENT:
2565 case KVM_CAP_DEBUGREGS:
2566 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2567 case KVM_CAP_XSAVE:
2568 case KVM_CAP_ASYNC_PF:
2569 case KVM_CAP_GET_TSC_KHZ:
2570 case KVM_CAP_KVMCLOCK_CTRL:
2571 case KVM_CAP_READONLY_MEM:
2572 case KVM_CAP_HYPERV_TIME:
2573 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2574 case KVM_CAP_TSC_DEADLINE_TIMER:
2575 case KVM_CAP_ENABLE_CAP_VM:
2576 case KVM_CAP_DISABLE_QUIRKS:
2577 case KVM_CAP_SET_BOOT_CPU_ID:
2578 case KVM_CAP_SPLIT_IRQCHIP:
2579 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2580 case KVM_CAP_ASSIGN_DEV_IRQ:
2581 case KVM_CAP_PCI_2_3:
2582 #endif
2583 r = 1;
2584 break;
2585 case KVM_CAP_X86_SMM:
2586 /* SMBASE is usually relocated above 1M on modern chipsets,
2587 * and SMM handlers might indeed rely on 4G segment limits,
2588 * so do not report SMM to be available if real mode is
2589 * emulated via vm86 mode. Still, do not go to great lengths
2590 * to avoid userspace's usage of the feature, because it is a
2591 * fringe case that is not enabled except via specific settings
2592 * of the module parameters.
2593 */
2594 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2595 break;
2596 case KVM_CAP_COALESCED_MMIO:
2597 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2598 break;
2599 case KVM_CAP_VAPIC:
2600 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2601 break;
2602 case KVM_CAP_NR_VCPUS:
2603 r = KVM_SOFT_MAX_VCPUS;
2604 break;
2605 case KVM_CAP_MAX_VCPUS:
2606 r = KVM_MAX_VCPUS;
2607 break;
2608 case KVM_CAP_NR_MEMSLOTS:
2609 r = KVM_USER_MEM_SLOTS;
2610 break;
2611 case KVM_CAP_PV_MMU: /* obsolete */
2612 r = 0;
2613 break;
2614 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2615 case KVM_CAP_IOMMU:
2616 r = iommu_present(&pci_bus_type);
2617 break;
2618 #endif
2619 case KVM_CAP_MCE:
2620 r = KVM_MAX_MCE_BANKS;
2621 break;
2622 case KVM_CAP_XCRS:
2623 r = boot_cpu_has(X86_FEATURE_XSAVE);
2624 break;
2625 case KVM_CAP_TSC_CONTROL:
2626 r = kvm_has_tsc_control;
2627 break;
2628 default:
2629 r = 0;
2630 break;
2631 }
2632 return r;
2633
2634 }
2635
2636 long kvm_arch_dev_ioctl(struct file *filp,
2637 unsigned int ioctl, unsigned long arg)
2638 {
2639 void __user *argp = (void __user *)arg;
2640 long r;
2641
2642 switch (ioctl) {
2643 case KVM_GET_MSR_INDEX_LIST: {
2644 struct kvm_msr_list __user *user_msr_list = argp;
2645 struct kvm_msr_list msr_list;
2646 unsigned n;
2647
2648 r = -EFAULT;
2649 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2650 goto out;
2651 n = msr_list.nmsrs;
2652 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2653 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2654 goto out;
2655 r = -E2BIG;
2656 if (n < msr_list.nmsrs)
2657 goto out;
2658 r = -EFAULT;
2659 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2660 num_msrs_to_save * sizeof(u32)))
2661 goto out;
2662 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2663 &emulated_msrs,
2664 num_emulated_msrs * sizeof(u32)))
2665 goto out;
2666 r = 0;
2667 break;
2668 }
2669 case KVM_GET_SUPPORTED_CPUID:
2670 case KVM_GET_EMULATED_CPUID: {
2671 struct kvm_cpuid2 __user *cpuid_arg = argp;
2672 struct kvm_cpuid2 cpuid;
2673
2674 r = -EFAULT;
2675 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2676 goto out;
2677
2678 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2679 ioctl);
2680 if (r)
2681 goto out;
2682
2683 r = -EFAULT;
2684 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2685 goto out;
2686 r = 0;
2687 break;
2688 }
2689 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2690 r = -EFAULT;
2691 if (copy_to_user(argp, &kvm_mce_cap_supported,
2692 sizeof(kvm_mce_cap_supported)))
2693 goto out;
2694 r = 0;
2695 break;
2696 }
2697 default:
2698 r = -EINVAL;
2699 }
2700 out:
2701 return r;
2702 }
2703
2704 static void wbinvd_ipi(void *garbage)
2705 {
2706 wbinvd();
2707 }
2708
2709 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2710 {
2711 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2712 }
2713
2714 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2715 {
2716 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2717 }
2718
2719 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2720 {
2721 /* Address WBINVD may be executed by guest */
2722 if (need_emulate_wbinvd(vcpu)) {
2723 if (kvm_x86_ops->has_wbinvd_exit())
2724 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2725 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2726 smp_call_function_single(vcpu->cpu,
2727 wbinvd_ipi, NULL, 1);
2728 }
2729
2730 kvm_x86_ops->vcpu_load(vcpu, cpu);
2731
2732 /* Apply any externally detected TSC adjustments (due to suspend) */
2733 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2734 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2735 vcpu->arch.tsc_offset_adjustment = 0;
2736 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2737 }
2738
2739 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2740 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2741 rdtsc() - vcpu->arch.last_host_tsc;
2742 if (tsc_delta < 0)
2743 mark_tsc_unstable("KVM discovered backwards TSC");
2744
2745 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2746 kvm_x86_ops->set_hv_timer(vcpu,
2747 kvm_get_lapic_tscdeadline_msr(vcpu)))
2748 kvm_lapic_switch_to_sw_timer(vcpu);
2749 if (check_tsc_unstable()) {
2750 u64 offset = kvm_compute_tsc_offset(vcpu,
2751 vcpu->arch.last_guest_tsc);
2752 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2753 vcpu->arch.tsc_catchup = 1;
2754 }
2755 /*
2756 * On a host with synchronized TSC, there is no need to update
2757 * kvmclock on vcpu->cpu migration
2758 */
2759 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2760 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2761 if (vcpu->cpu != cpu)
2762 kvm_migrate_timers(vcpu);
2763 vcpu->cpu = cpu;
2764 }
2765
2766 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2767 }
2768
2769 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2770 {
2771 kvm_x86_ops->vcpu_put(vcpu);
2772 kvm_put_guest_fpu(vcpu);
2773 vcpu->arch.last_host_tsc = rdtsc();
2774 }
2775
2776 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2777 struct kvm_lapic_state *s)
2778 {
2779 if (vcpu->arch.apicv_active)
2780 kvm_x86_ops->sync_pir_to_irr(vcpu);
2781
2782 return kvm_apic_get_state(vcpu, s);
2783 }
2784
2785 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2786 struct kvm_lapic_state *s)
2787 {
2788 int r;
2789
2790 r = kvm_apic_set_state(vcpu, s);
2791 if (r)
2792 return r;
2793 update_cr8_intercept(vcpu);
2794
2795 return 0;
2796 }
2797
2798 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2799 {
2800 return (!lapic_in_kernel(vcpu) ||
2801 kvm_apic_accept_pic_intr(vcpu));
2802 }
2803
2804 /*
2805 * if userspace requested an interrupt window, check that the
2806 * interrupt window is open.
2807 *
2808 * No need to exit to userspace if we already have an interrupt queued.
2809 */
2810 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2811 {
2812 return kvm_arch_interrupt_allowed(vcpu) &&
2813 !kvm_cpu_has_interrupt(vcpu) &&
2814 !kvm_event_needs_reinjection(vcpu) &&
2815 kvm_cpu_accept_dm_intr(vcpu);
2816 }
2817
2818 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2819 struct kvm_interrupt *irq)
2820 {
2821 if (irq->irq >= KVM_NR_INTERRUPTS)
2822 return -EINVAL;
2823
2824 if (!irqchip_in_kernel(vcpu->kvm)) {
2825 kvm_queue_interrupt(vcpu, irq->irq, false);
2826 kvm_make_request(KVM_REQ_EVENT, vcpu);
2827 return 0;
2828 }
2829
2830 /*
2831 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2832 * fail for in-kernel 8259.
2833 */
2834 if (pic_in_kernel(vcpu->kvm))
2835 return -ENXIO;
2836
2837 if (vcpu->arch.pending_external_vector != -1)
2838 return -EEXIST;
2839
2840 vcpu->arch.pending_external_vector = irq->irq;
2841 kvm_make_request(KVM_REQ_EVENT, vcpu);
2842 return 0;
2843 }
2844
2845 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2846 {
2847 kvm_inject_nmi(vcpu);
2848
2849 return 0;
2850 }
2851
2852 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2853 {
2854 kvm_make_request(KVM_REQ_SMI, vcpu);
2855
2856 return 0;
2857 }
2858
2859 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2860 struct kvm_tpr_access_ctl *tac)
2861 {
2862 if (tac->flags)
2863 return -EINVAL;
2864 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2865 return 0;
2866 }
2867
2868 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2869 u64 mcg_cap)
2870 {
2871 int r;
2872 unsigned bank_num = mcg_cap & 0xff, bank;
2873
2874 r = -EINVAL;
2875 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2876 goto out;
2877 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
2878 goto out;
2879 r = 0;
2880 vcpu->arch.mcg_cap = mcg_cap;
2881 /* Init IA32_MCG_CTL to all 1s */
2882 if (mcg_cap & MCG_CTL_P)
2883 vcpu->arch.mcg_ctl = ~(u64)0;
2884 /* Init IA32_MCi_CTL to all 1s */
2885 for (bank = 0; bank < bank_num; bank++)
2886 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2887
2888 if (kvm_x86_ops->setup_mce)
2889 kvm_x86_ops->setup_mce(vcpu);
2890 out:
2891 return r;
2892 }
2893
2894 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2895 struct kvm_x86_mce *mce)
2896 {
2897 u64 mcg_cap = vcpu->arch.mcg_cap;
2898 unsigned bank_num = mcg_cap & 0xff;
2899 u64 *banks = vcpu->arch.mce_banks;
2900
2901 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2902 return -EINVAL;
2903 /*
2904 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2905 * reporting is disabled
2906 */
2907 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2908 vcpu->arch.mcg_ctl != ~(u64)0)
2909 return 0;
2910 banks += 4 * mce->bank;
2911 /*
2912 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2913 * reporting is disabled for the bank
2914 */
2915 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2916 return 0;
2917 if (mce->status & MCI_STATUS_UC) {
2918 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2919 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2920 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2921 return 0;
2922 }
2923 if (banks[1] & MCI_STATUS_VAL)
2924 mce->status |= MCI_STATUS_OVER;
2925 banks[2] = mce->addr;
2926 banks[3] = mce->misc;
2927 vcpu->arch.mcg_status = mce->mcg_status;
2928 banks[1] = mce->status;
2929 kvm_queue_exception(vcpu, MC_VECTOR);
2930 } else if (!(banks[1] & MCI_STATUS_VAL)
2931 || !(banks[1] & MCI_STATUS_UC)) {
2932 if (banks[1] & MCI_STATUS_VAL)
2933 mce->status |= MCI_STATUS_OVER;
2934 banks[2] = mce->addr;
2935 banks[3] = mce->misc;
2936 banks[1] = mce->status;
2937 } else
2938 banks[1] |= MCI_STATUS_OVER;
2939 return 0;
2940 }
2941
2942 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2943 struct kvm_vcpu_events *events)
2944 {
2945 process_nmi(vcpu);
2946 events->exception.injected =
2947 vcpu->arch.exception.pending &&
2948 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2949 events->exception.nr = vcpu->arch.exception.nr;
2950 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2951 events->exception.pad = 0;
2952 events->exception.error_code = vcpu->arch.exception.error_code;
2953
2954 events->interrupt.injected =
2955 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2956 events->interrupt.nr = vcpu->arch.interrupt.nr;
2957 events->interrupt.soft = 0;
2958 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2959
2960 events->nmi.injected = vcpu->arch.nmi_injected;
2961 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2962 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2963 events->nmi.pad = 0;
2964
2965 events->sipi_vector = 0; /* never valid when reporting to user space */
2966
2967 events->smi.smm = is_smm(vcpu);
2968 events->smi.pending = vcpu->arch.smi_pending;
2969 events->smi.smm_inside_nmi =
2970 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2971 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2972
2973 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2974 | KVM_VCPUEVENT_VALID_SHADOW
2975 | KVM_VCPUEVENT_VALID_SMM);
2976 memset(&events->reserved, 0, sizeof(events->reserved));
2977 }
2978
2979 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2980 struct kvm_vcpu_events *events)
2981 {
2982 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2983 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2984 | KVM_VCPUEVENT_VALID_SHADOW
2985 | KVM_VCPUEVENT_VALID_SMM))
2986 return -EINVAL;
2987
2988 if (events->exception.injected &&
2989 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
2990 return -EINVAL;
2991
2992 process_nmi(vcpu);
2993 vcpu->arch.exception.pending = events->exception.injected;
2994 vcpu->arch.exception.nr = events->exception.nr;
2995 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2996 vcpu->arch.exception.error_code = events->exception.error_code;
2997
2998 vcpu->arch.interrupt.pending = events->interrupt.injected;
2999 vcpu->arch.interrupt.nr = events->interrupt.nr;
3000 vcpu->arch.interrupt.soft = events->interrupt.soft;
3001 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3002 kvm_x86_ops->set_interrupt_shadow(vcpu,
3003 events->interrupt.shadow);
3004
3005 vcpu->arch.nmi_injected = events->nmi.injected;
3006 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3007 vcpu->arch.nmi_pending = events->nmi.pending;
3008 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3009
3010 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3011 lapic_in_kernel(vcpu))
3012 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3013
3014 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3015 if (events->smi.smm)
3016 vcpu->arch.hflags |= HF_SMM_MASK;
3017 else
3018 vcpu->arch.hflags &= ~HF_SMM_MASK;
3019 vcpu->arch.smi_pending = events->smi.pending;
3020 if (events->smi.smm_inside_nmi)
3021 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3022 else
3023 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3024 if (lapic_in_kernel(vcpu)) {
3025 if (events->smi.latched_init)
3026 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3027 else
3028 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3029 }
3030 }
3031
3032 kvm_make_request(KVM_REQ_EVENT, vcpu);
3033
3034 return 0;
3035 }
3036
3037 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3038 struct kvm_debugregs *dbgregs)
3039 {
3040 unsigned long val;
3041
3042 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3043 kvm_get_dr(vcpu, 6, &val);
3044 dbgregs->dr6 = val;
3045 dbgregs->dr7 = vcpu->arch.dr7;
3046 dbgregs->flags = 0;
3047 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3048 }
3049
3050 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3051 struct kvm_debugregs *dbgregs)
3052 {
3053 if (dbgregs->flags)
3054 return -EINVAL;
3055
3056 if (dbgregs->dr6 & ~0xffffffffull)
3057 return -EINVAL;
3058 if (dbgregs->dr7 & ~0xffffffffull)
3059 return -EINVAL;
3060
3061 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3062 kvm_update_dr0123(vcpu);
3063 vcpu->arch.dr6 = dbgregs->dr6;
3064 kvm_update_dr6(vcpu);
3065 vcpu->arch.dr7 = dbgregs->dr7;
3066 kvm_update_dr7(vcpu);
3067
3068 return 0;
3069 }
3070
3071 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3072
3073 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3074 {
3075 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3076 u64 xstate_bv = xsave->header.xfeatures;
3077 u64 valid;
3078
3079 /*
3080 * Copy legacy XSAVE area, to avoid complications with CPUID
3081 * leaves 0 and 1 in the loop below.
3082 */
3083 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3084
3085 /* Set XSTATE_BV */
3086 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3087
3088 /*
3089 * Copy each region from the possibly compacted offset to the
3090 * non-compacted offset.
3091 */
3092 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3093 while (valid) {
3094 u64 feature = valid & -valid;
3095 int index = fls64(feature) - 1;
3096 void *src = get_xsave_addr(xsave, feature);
3097
3098 if (src) {
3099 u32 size, offset, ecx, edx;
3100 cpuid_count(XSTATE_CPUID, index,
3101 &size, &offset, &ecx, &edx);
3102 memcpy(dest + offset, src, size);
3103 }
3104
3105 valid -= feature;
3106 }
3107 }
3108
3109 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3110 {
3111 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3112 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3113 u64 valid;
3114
3115 /*
3116 * Copy legacy XSAVE area, to avoid complications with CPUID
3117 * leaves 0 and 1 in the loop below.
3118 */
3119 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3120
3121 /* Set XSTATE_BV and possibly XCOMP_BV. */
3122 xsave->header.xfeatures = xstate_bv;
3123 if (boot_cpu_has(X86_FEATURE_XSAVES))
3124 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3125
3126 /*
3127 * Copy each region from the non-compacted offset to the
3128 * possibly compacted offset.
3129 */
3130 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3131 while (valid) {
3132 u64 feature = valid & -valid;
3133 int index = fls64(feature) - 1;
3134 void *dest = get_xsave_addr(xsave, feature);
3135
3136 if (dest) {
3137 u32 size, offset, ecx, edx;
3138 cpuid_count(XSTATE_CPUID, index,
3139 &size, &offset, &ecx, &edx);
3140 memcpy(dest, src + offset, size);
3141 }
3142
3143 valid -= feature;
3144 }
3145 }
3146
3147 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3148 struct kvm_xsave *guest_xsave)
3149 {
3150 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3151 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3152 fill_xsave((u8 *) guest_xsave->region, vcpu);
3153 } else {
3154 memcpy(guest_xsave->region,
3155 &vcpu->arch.guest_fpu.state.fxsave,
3156 sizeof(struct fxregs_state));
3157 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3158 XFEATURE_MASK_FPSSE;
3159 }
3160 }
3161
3162 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3163 struct kvm_xsave *guest_xsave)
3164 {
3165 u64 xstate_bv =
3166 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3167
3168 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3169 /*
3170 * Here we allow setting states that are not present in
3171 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3172 * with old userspace.
3173 */
3174 if (xstate_bv & ~kvm_supported_xcr0())
3175 return -EINVAL;
3176 load_xsave(vcpu, (u8 *)guest_xsave->region);
3177 } else {
3178 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3179 return -EINVAL;
3180 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3181 guest_xsave->region, sizeof(struct fxregs_state));
3182 }
3183 return 0;
3184 }
3185
3186 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3187 struct kvm_xcrs *guest_xcrs)
3188 {
3189 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3190 guest_xcrs->nr_xcrs = 0;
3191 return;
3192 }
3193
3194 guest_xcrs->nr_xcrs = 1;
3195 guest_xcrs->flags = 0;
3196 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3197 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3198 }
3199
3200 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3201 struct kvm_xcrs *guest_xcrs)
3202 {
3203 int i, r = 0;
3204
3205 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3206 return -EINVAL;
3207
3208 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3209 return -EINVAL;
3210
3211 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3212 /* Only support XCR0 currently */
3213 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3214 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3215 guest_xcrs->xcrs[i].value);
3216 break;
3217 }
3218 if (r)
3219 r = -EINVAL;
3220 return r;
3221 }
3222
3223 /*
3224 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3225 * stopped by the hypervisor. This function will be called from the host only.
3226 * EINVAL is returned when the host attempts to set the flag for a guest that
3227 * does not support pv clocks.
3228 */
3229 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3230 {
3231 if (!vcpu->arch.pv_time_enabled)
3232 return -EINVAL;
3233 vcpu->arch.pvclock_set_guest_stopped_request = true;
3234 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3235 return 0;
3236 }
3237
3238 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3239 struct kvm_enable_cap *cap)
3240 {
3241 if (cap->flags)
3242 return -EINVAL;
3243
3244 switch (cap->cap) {
3245 case KVM_CAP_HYPERV_SYNIC:
3246 return kvm_hv_activate_synic(vcpu);
3247 default:
3248 return -EINVAL;
3249 }
3250 }
3251
3252 long kvm_arch_vcpu_ioctl(struct file *filp,
3253 unsigned int ioctl, unsigned long arg)
3254 {
3255 struct kvm_vcpu *vcpu = filp->private_data;
3256 void __user *argp = (void __user *)arg;
3257 int r;
3258 union {
3259 struct kvm_lapic_state *lapic;
3260 struct kvm_xsave *xsave;
3261 struct kvm_xcrs *xcrs;
3262 void *buffer;
3263 } u;
3264
3265 u.buffer = NULL;
3266 switch (ioctl) {
3267 case KVM_GET_LAPIC: {
3268 r = -EINVAL;
3269 if (!lapic_in_kernel(vcpu))
3270 goto out;
3271 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3272
3273 r = -ENOMEM;
3274 if (!u.lapic)
3275 goto out;
3276 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3277 if (r)
3278 goto out;
3279 r = -EFAULT;
3280 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3281 goto out;
3282 r = 0;
3283 break;
3284 }
3285 case KVM_SET_LAPIC: {
3286 r = -EINVAL;
3287 if (!lapic_in_kernel(vcpu))
3288 goto out;
3289 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3290 if (IS_ERR(u.lapic))
3291 return PTR_ERR(u.lapic);
3292
3293 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3294 break;
3295 }
3296 case KVM_INTERRUPT: {
3297 struct kvm_interrupt irq;
3298
3299 r = -EFAULT;
3300 if (copy_from_user(&irq, argp, sizeof irq))
3301 goto out;
3302 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3303 break;
3304 }
3305 case KVM_NMI: {
3306 r = kvm_vcpu_ioctl_nmi(vcpu);
3307 break;
3308 }
3309 case KVM_SMI: {
3310 r = kvm_vcpu_ioctl_smi(vcpu);
3311 break;
3312 }
3313 case KVM_SET_CPUID: {
3314 struct kvm_cpuid __user *cpuid_arg = argp;
3315 struct kvm_cpuid cpuid;
3316
3317 r = -EFAULT;
3318 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3319 goto out;
3320 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3321 break;
3322 }
3323 case KVM_SET_CPUID2: {
3324 struct kvm_cpuid2 __user *cpuid_arg = argp;
3325 struct kvm_cpuid2 cpuid;
3326
3327 r = -EFAULT;
3328 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3329 goto out;
3330 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3331 cpuid_arg->entries);
3332 break;
3333 }
3334 case KVM_GET_CPUID2: {
3335 struct kvm_cpuid2 __user *cpuid_arg = argp;
3336 struct kvm_cpuid2 cpuid;
3337
3338 r = -EFAULT;
3339 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3340 goto out;
3341 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3342 cpuid_arg->entries);
3343 if (r)
3344 goto out;
3345 r = -EFAULT;
3346 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3347 goto out;
3348 r = 0;
3349 break;
3350 }
3351 case KVM_GET_MSRS:
3352 r = msr_io(vcpu, argp, do_get_msr, 1);
3353 break;
3354 case KVM_SET_MSRS:
3355 r = msr_io(vcpu, argp, do_set_msr, 0);
3356 break;
3357 case KVM_TPR_ACCESS_REPORTING: {
3358 struct kvm_tpr_access_ctl tac;
3359
3360 r = -EFAULT;
3361 if (copy_from_user(&tac, argp, sizeof tac))
3362 goto out;
3363 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3364 if (r)
3365 goto out;
3366 r = -EFAULT;
3367 if (copy_to_user(argp, &tac, sizeof tac))
3368 goto out;
3369 r = 0;
3370 break;
3371 };
3372 case KVM_SET_VAPIC_ADDR: {
3373 struct kvm_vapic_addr va;
3374
3375 r = -EINVAL;
3376 if (!lapic_in_kernel(vcpu))
3377 goto out;
3378 r = -EFAULT;
3379 if (copy_from_user(&va, argp, sizeof va))
3380 goto out;
3381 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3382 break;
3383 }
3384 case KVM_X86_SETUP_MCE: {
3385 u64 mcg_cap;
3386
3387 r = -EFAULT;
3388 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3389 goto out;
3390 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3391 break;
3392 }
3393 case KVM_X86_SET_MCE: {
3394 struct kvm_x86_mce mce;
3395
3396 r = -EFAULT;
3397 if (copy_from_user(&mce, argp, sizeof mce))
3398 goto out;
3399 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3400 break;
3401 }
3402 case KVM_GET_VCPU_EVENTS: {
3403 struct kvm_vcpu_events events;
3404
3405 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3406
3407 r = -EFAULT;
3408 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3409 break;
3410 r = 0;
3411 break;
3412 }
3413 case KVM_SET_VCPU_EVENTS: {
3414 struct kvm_vcpu_events events;
3415
3416 r = -EFAULT;
3417 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3418 break;
3419
3420 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3421 break;
3422 }
3423 case KVM_GET_DEBUGREGS: {
3424 struct kvm_debugregs dbgregs;
3425
3426 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3427
3428 r = -EFAULT;
3429 if (copy_to_user(argp, &dbgregs,
3430 sizeof(struct kvm_debugregs)))
3431 break;
3432 r = 0;
3433 break;
3434 }
3435 case KVM_SET_DEBUGREGS: {
3436 struct kvm_debugregs dbgregs;
3437
3438 r = -EFAULT;
3439 if (copy_from_user(&dbgregs, argp,
3440 sizeof(struct kvm_debugregs)))
3441 break;
3442
3443 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3444 break;
3445 }
3446 case KVM_GET_XSAVE: {
3447 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3448 r = -ENOMEM;
3449 if (!u.xsave)
3450 break;
3451
3452 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3453
3454 r = -EFAULT;
3455 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3456 break;
3457 r = 0;
3458 break;
3459 }
3460 case KVM_SET_XSAVE: {
3461 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3462 if (IS_ERR(u.xsave))
3463 return PTR_ERR(u.xsave);
3464
3465 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3466 break;
3467 }
3468 case KVM_GET_XCRS: {
3469 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3470 r = -ENOMEM;
3471 if (!u.xcrs)
3472 break;
3473
3474 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3475
3476 r = -EFAULT;
3477 if (copy_to_user(argp, u.xcrs,
3478 sizeof(struct kvm_xcrs)))
3479 break;
3480 r = 0;
3481 break;
3482 }
3483 case KVM_SET_XCRS: {
3484 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3485 if (IS_ERR(u.xcrs))
3486 return PTR_ERR(u.xcrs);
3487
3488 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3489 break;
3490 }
3491 case KVM_SET_TSC_KHZ: {
3492 u32 user_tsc_khz;
3493
3494 r = -EINVAL;
3495 user_tsc_khz = (u32)arg;
3496
3497 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3498 goto out;
3499
3500 if (user_tsc_khz == 0)
3501 user_tsc_khz = tsc_khz;
3502
3503 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3504 r = 0;
3505
3506 goto out;
3507 }
3508 case KVM_GET_TSC_KHZ: {
3509 r = vcpu->arch.virtual_tsc_khz;
3510 goto out;
3511 }
3512 case KVM_KVMCLOCK_CTRL: {
3513 r = kvm_set_guest_paused(vcpu);
3514 goto out;
3515 }
3516 case KVM_ENABLE_CAP: {
3517 struct kvm_enable_cap cap;
3518
3519 r = -EFAULT;
3520 if (copy_from_user(&cap, argp, sizeof(cap)))
3521 goto out;
3522 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3523 break;
3524 }
3525 default:
3526 r = -EINVAL;
3527 }
3528 out:
3529 kfree(u.buffer);
3530 return r;
3531 }
3532
3533 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3534 {
3535 return VM_FAULT_SIGBUS;
3536 }
3537
3538 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3539 {
3540 int ret;
3541
3542 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3543 return -EINVAL;
3544 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3545 return ret;
3546 }
3547
3548 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3549 u64 ident_addr)
3550 {
3551 kvm->arch.ept_identity_map_addr = ident_addr;
3552 return 0;
3553 }
3554
3555 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3556 u32 kvm_nr_mmu_pages)
3557 {
3558 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3559 return -EINVAL;
3560
3561 mutex_lock(&kvm->slots_lock);
3562
3563 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3564 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3565
3566 mutex_unlock(&kvm->slots_lock);
3567 return 0;
3568 }
3569
3570 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3571 {
3572 return kvm->arch.n_max_mmu_pages;
3573 }
3574
3575 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3576 {
3577 int r;
3578
3579 r = 0;
3580 switch (chip->chip_id) {
3581 case KVM_IRQCHIP_PIC_MASTER:
3582 memcpy(&chip->chip.pic,
3583 &pic_irqchip(kvm)->pics[0],
3584 sizeof(struct kvm_pic_state));
3585 break;
3586 case KVM_IRQCHIP_PIC_SLAVE:
3587 memcpy(&chip->chip.pic,
3588 &pic_irqchip(kvm)->pics[1],
3589 sizeof(struct kvm_pic_state));
3590 break;
3591 case KVM_IRQCHIP_IOAPIC:
3592 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3593 break;
3594 default:
3595 r = -EINVAL;
3596 break;
3597 }
3598 return r;
3599 }
3600
3601 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3602 {
3603 int r;
3604
3605 r = 0;
3606 switch (chip->chip_id) {
3607 case KVM_IRQCHIP_PIC_MASTER:
3608 spin_lock(&pic_irqchip(kvm)->lock);
3609 memcpy(&pic_irqchip(kvm)->pics[0],
3610 &chip->chip.pic,
3611 sizeof(struct kvm_pic_state));
3612 spin_unlock(&pic_irqchip(kvm)->lock);
3613 break;
3614 case KVM_IRQCHIP_PIC_SLAVE:
3615 spin_lock(&pic_irqchip(kvm)->lock);
3616 memcpy(&pic_irqchip(kvm)->pics[1],
3617 &chip->chip.pic,
3618 sizeof(struct kvm_pic_state));
3619 spin_unlock(&pic_irqchip(kvm)->lock);
3620 break;
3621 case KVM_IRQCHIP_IOAPIC:
3622 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3623 break;
3624 default:
3625 r = -EINVAL;
3626 break;
3627 }
3628 kvm_pic_update_irq(pic_irqchip(kvm));
3629 return r;
3630 }
3631
3632 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3633 {
3634 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3635
3636 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3637
3638 mutex_lock(&kps->lock);
3639 memcpy(ps, &kps->channels, sizeof(*ps));
3640 mutex_unlock(&kps->lock);
3641 return 0;
3642 }
3643
3644 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3645 {
3646 int i;
3647 struct kvm_pit *pit = kvm->arch.vpit;
3648
3649 mutex_lock(&pit->pit_state.lock);
3650 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3651 for (i = 0; i < 3; i++)
3652 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3653 mutex_unlock(&pit->pit_state.lock);
3654 return 0;
3655 }
3656
3657 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3658 {
3659 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3660 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3661 sizeof(ps->channels));
3662 ps->flags = kvm->arch.vpit->pit_state.flags;
3663 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3664 memset(&ps->reserved, 0, sizeof(ps->reserved));
3665 return 0;
3666 }
3667
3668 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3669 {
3670 int start = 0;
3671 int i;
3672 u32 prev_legacy, cur_legacy;
3673 struct kvm_pit *pit = kvm->arch.vpit;
3674
3675 mutex_lock(&pit->pit_state.lock);
3676 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3677 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3678 if (!prev_legacy && cur_legacy)
3679 start = 1;
3680 memcpy(&pit->pit_state.channels, &ps->channels,
3681 sizeof(pit->pit_state.channels));
3682 pit->pit_state.flags = ps->flags;
3683 for (i = 0; i < 3; i++)
3684 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3685 start && i == 0);
3686 mutex_unlock(&pit->pit_state.lock);
3687 return 0;
3688 }
3689
3690 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3691 struct kvm_reinject_control *control)
3692 {
3693 struct kvm_pit *pit = kvm->arch.vpit;
3694
3695 if (!pit)
3696 return -ENXIO;
3697
3698 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3699 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3700 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3701 */
3702 mutex_lock(&pit->pit_state.lock);
3703 kvm_pit_set_reinject(pit, control->pit_reinject);
3704 mutex_unlock(&pit->pit_state.lock);
3705
3706 return 0;
3707 }
3708
3709 /**
3710 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3711 * @kvm: kvm instance
3712 * @log: slot id and address to which we copy the log
3713 *
3714 * Steps 1-4 below provide general overview of dirty page logging. See
3715 * kvm_get_dirty_log_protect() function description for additional details.
3716 *
3717 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3718 * always flush the TLB (step 4) even if previous step failed and the dirty
3719 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3720 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3721 * writes will be marked dirty for next log read.
3722 *
3723 * 1. Take a snapshot of the bit and clear it if needed.
3724 * 2. Write protect the corresponding page.
3725 * 3. Copy the snapshot to the userspace.
3726 * 4. Flush TLB's if needed.
3727 */
3728 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3729 {
3730 bool is_dirty = false;
3731 int r;
3732
3733 mutex_lock(&kvm->slots_lock);
3734
3735 /*
3736 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3737 */
3738 if (kvm_x86_ops->flush_log_dirty)
3739 kvm_x86_ops->flush_log_dirty(kvm);
3740
3741 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3742
3743 /*
3744 * All the TLBs can be flushed out of mmu lock, see the comments in
3745 * kvm_mmu_slot_remove_write_access().
3746 */
3747 lockdep_assert_held(&kvm->slots_lock);
3748 if (is_dirty)
3749 kvm_flush_remote_tlbs(kvm);
3750
3751 mutex_unlock(&kvm->slots_lock);
3752 return r;
3753 }
3754
3755 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3756 bool line_status)
3757 {
3758 if (!irqchip_in_kernel(kvm))
3759 return -ENXIO;
3760
3761 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3762 irq_event->irq, irq_event->level,
3763 line_status);
3764 return 0;
3765 }
3766
3767 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3768 struct kvm_enable_cap *cap)
3769 {
3770 int r;
3771
3772 if (cap->flags)
3773 return -EINVAL;
3774
3775 switch (cap->cap) {
3776 case KVM_CAP_DISABLE_QUIRKS:
3777 kvm->arch.disabled_quirks = cap->args[0];
3778 r = 0;
3779 break;
3780 case KVM_CAP_SPLIT_IRQCHIP: {
3781 mutex_lock(&kvm->lock);
3782 r = -EINVAL;
3783 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3784 goto split_irqchip_unlock;
3785 r = -EEXIST;
3786 if (irqchip_in_kernel(kvm))
3787 goto split_irqchip_unlock;
3788 if (kvm->created_vcpus)
3789 goto split_irqchip_unlock;
3790 r = kvm_setup_empty_irq_routing(kvm);
3791 if (r)
3792 goto split_irqchip_unlock;
3793 /* Pairs with irqchip_in_kernel. */
3794 smp_wmb();
3795 kvm->arch.irqchip_split = true;
3796 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3797 r = 0;
3798 split_irqchip_unlock:
3799 mutex_unlock(&kvm->lock);
3800 break;
3801 }
3802 default:
3803 r = -EINVAL;
3804 break;
3805 }
3806 return r;
3807 }
3808
3809 long kvm_arch_vm_ioctl(struct file *filp,
3810 unsigned int ioctl, unsigned long arg)
3811 {
3812 struct kvm *kvm = filp->private_data;
3813 void __user *argp = (void __user *)arg;
3814 int r = -ENOTTY;
3815 /*
3816 * This union makes it completely explicit to gcc-3.x
3817 * that these two variables' stack usage should be
3818 * combined, not added together.
3819 */
3820 union {
3821 struct kvm_pit_state ps;
3822 struct kvm_pit_state2 ps2;
3823 struct kvm_pit_config pit_config;
3824 } u;
3825
3826 switch (ioctl) {
3827 case KVM_SET_TSS_ADDR:
3828 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3829 break;
3830 case KVM_SET_IDENTITY_MAP_ADDR: {
3831 u64 ident_addr;
3832
3833 r = -EFAULT;
3834 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3835 goto out;
3836 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3837 break;
3838 }
3839 case KVM_SET_NR_MMU_PAGES:
3840 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3841 break;
3842 case KVM_GET_NR_MMU_PAGES:
3843 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3844 break;
3845 case KVM_CREATE_IRQCHIP: {
3846 struct kvm_pic *vpic;
3847
3848 mutex_lock(&kvm->lock);
3849 r = -EEXIST;
3850 if (kvm->arch.vpic)
3851 goto create_irqchip_unlock;
3852 r = -EINVAL;
3853 if (kvm->created_vcpus)
3854 goto create_irqchip_unlock;
3855 r = -ENOMEM;
3856 vpic = kvm_create_pic(kvm);
3857 if (vpic) {
3858 r = kvm_ioapic_init(kvm);
3859 if (r) {
3860 mutex_lock(&kvm->slots_lock);
3861 kvm_destroy_pic(vpic);
3862 mutex_unlock(&kvm->slots_lock);
3863 goto create_irqchip_unlock;
3864 }
3865 } else
3866 goto create_irqchip_unlock;
3867 r = kvm_setup_default_irq_routing(kvm);
3868 if (r) {
3869 mutex_lock(&kvm->slots_lock);
3870 mutex_lock(&kvm->irq_lock);
3871 kvm_ioapic_destroy(kvm);
3872 kvm_destroy_pic(vpic);
3873 mutex_unlock(&kvm->irq_lock);
3874 mutex_unlock(&kvm->slots_lock);
3875 goto create_irqchip_unlock;
3876 }
3877 /* Write kvm->irq_routing before kvm->arch.vpic. */
3878 smp_wmb();
3879 kvm->arch.vpic = vpic;
3880 create_irqchip_unlock:
3881 mutex_unlock(&kvm->lock);
3882 break;
3883 }
3884 case KVM_CREATE_PIT:
3885 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3886 goto create_pit;
3887 case KVM_CREATE_PIT2:
3888 r = -EFAULT;
3889 if (copy_from_user(&u.pit_config, argp,
3890 sizeof(struct kvm_pit_config)))
3891 goto out;
3892 create_pit:
3893 mutex_lock(&kvm->lock);
3894 r = -EEXIST;
3895 if (kvm->arch.vpit)
3896 goto create_pit_unlock;
3897 r = -ENOMEM;
3898 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3899 if (kvm->arch.vpit)
3900 r = 0;
3901 create_pit_unlock:
3902 mutex_unlock(&kvm->lock);
3903 break;
3904 case KVM_GET_IRQCHIP: {
3905 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3906 struct kvm_irqchip *chip;
3907
3908 chip = memdup_user(argp, sizeof(*chip));
3909 if (IS_ERR(chip)) {
3910 r = PTR_ERR(chip);
3911 goto out;
3912 }
3913
3914 r = -ENXIO;
3915 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3916 goto get_irqchip_out;
3917 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3918 if (r)
3919 goto get_irqchip_out;
3920 r = -EFAULT;
3921 if (copy_to_user(argp, chip, sizeof *chip))
3922 goto get_irqchip_out;
3923 r = 0;
3924 get_irqchip_out:
3925 kfree(chip);
3926 break;
3927 }
3928 case KVM_SET_IRQCHIP: {
3929 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3930 struct kvm_irqchip *chip;
3931
3932 chip = memdup_user(argp, sizeof(*chip));
3933 if (IS_ERR(chip)) {
3934 r = PTR_ERR(chip);
3935 goto out;
3936 }
3937
3938 r = -ENXIO;
3939 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3940 goto set_irqchip_out;
3941 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3942 if (r)
3943 goto set_irqchip_out;
3944 r = 0;
3945 set_irqchip_out:
3946 kfree(chip);
3947 break;
3948 }
3949 case KVM_GET_PIT: {
3950 r = -EFAULT;
3951 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3952 goto out;
3953 r = -ENXIO;
3954 if (!kvm->arch.vpit)
3955 goto out;
3956 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3957 if (r)
3958 goto out;
3959 r = -EFAULT;
3960 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3961 goto out;
3962 r = 0;
3963 break;
3964 }
3965 case KVM_SET_PIT: {
3966 r = -EFAULT;
3967 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3968 goto out;
3969 r = -ENXIO;
3970 if (!kvm->arch.vpit)
3971 goto out;
3972 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3973 break;
3974 }
3975 case KVM_GET_PIT2: {
3976 r = -ENXIO;
3977 if (!kvm->arch.vpit)
3978 goto out;
3979 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3980 if (r)
3981 goto out;
3982 r = -EFAULT;
3983 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3984 goto out;
3985 r = 0;
3986 break;
3987 }
3988 case KVM_SET_PIT2: {
3989 r = -EFAULT;
3990 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3991 goto out;
3992 r = -ENXIO;
3993 if (!kvm->arch.vpit)
3994 goto out;
3995 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3996 break;
3997 }
3998 case KVM_REINJECT_CONTROL: {
3999 struct kvm_reinject_control control;
4000 r = -EFAULT;
4001 if (copy_from_user(&control, argp, sizeof(control)))
4002 goto out;
4003 r = kvm_vm_ioctl_reinject(kvm, &control);
4004 break;
4005 }
4006 case KVM_SET_BOOT_CPU_ID:
4007 r = 0;
4008 mutex_lock(&kvm->lock);
4009 if (kvm->created_vcpus)
4010 r = -EBUSY;
4011 else
4012 kvm->arch.bsp_vcpu_id = arg;
4013 mutex_unlock(&kvm->lock);
4014 break;
4015 case KVM_XEN_HVM_CONFIG: {
4016 r = -EFAULT;
4017 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4018 sizeof(struct kvm_xen_hvm_config)))
4019 goto out;
4020 r = -EINVAL;
4021 if (kvm->arch.xen_hvm_config.flags)
4022 goto out;
4023 r = 0;
4024 break;
4025 }
4026 case KVM_SET_CLOCK: {
4027 struct kvm_clock_data user_ns;
4028 u64 now_ns;
4029 s64 delta;
4030
4031 r = -EFAULT;
4032 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4033 goto out;
4034
4035 r = -EINVAL;
4036 if (user_ns.flags)
4037 goto out;
4038
4039 r = 0;
4040 local_irq_disable();
4041 now_ns = get_kernel_ns();
4042 delta = user_ns.clock - now_ns;
4043 local_irq_enable();
4044 kvm->arch.kvmclock_offset = delta;
4045 kvm_gen_update_masterclock(kvm);
4046 break;
4047 }
4048 case KVM_GET_CLOCK: {
4049 struct kvm_clock_data user_ns;
4050 u64 now_ns;
4051
4052 local_irq_disable();
4053 now_ns = get_kernel_ns();
4054 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4055 local_irq_enable();
4056 user_ns.flags = 0;
4057 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4058
4059 r = -EFAULT;
4060 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4061 goto out;
4062 r = 0;
4063 break;
4064 }
4065 case KVM_ENABLE_CAP: {
4066 struct kvm_enable_cap cap;
4067
4068 r = -EFAULT;
4069 if (copy_from_user(&cap, argp, sizeof(cap)))
4070 goto out;
4071 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4072 break;
4073 }
4074 default:
4075 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4076 }
4077 out:
4078 return r;
4079 }
4080
4081 static void kvm_init_msr_list(void)
4082 {
4083 u32 dummy[2];
4084 unsigned i, j;
4085
4086 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4087 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4088 continue;
4089
4090 /*
4091 * Even MSRs that are valid in the host may not be exposed
4092 * to the guests in some cases.
4093 */
4094 switch (msrs_to_save[i]) {
4095 case MSR_IA32_BNDCFGS:
4096 if (!kvm_x86_ops->mpx_supported())
4097 continue;
4098 break;
4099 case MSR_TSC_AUX:
4100 if (!kvm_x86_ops->rdtscp_supported())
4101 continue;
4102 break;
4103 default:
4104 break;
4105 }
4106
4107 if (j < i)
4108 msrs_to_save[j] = msrs_to_save[i];
4109 j++;
4110 }
4111 num_msrs_to_save = j;
4112
4113 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4114 switch (emulated_msrs[i]) {
4115 case MSR_IA32_SMBASE:
4116 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4117 continue;
4118 break;
4119 default:
4120 break;
4121 }
4122
4123 if (j < i)
4124 emulated_msrs[j] = emulated_msrs[i];
4125 j++;
4126 }
4127 num_emulated_msrs = j;
4128 }
4129
4130 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4131 const void *v)
4132 {
4133 int handled = 0;
4134 int n;
4135
4136 do {
4137 n = min(len, 8);
4138 if (!(lapic_in_kernel(vcpu) &&
4139 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4140 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4141 break;
4142 handled += n;
4143 addr += n;
4144 len -= n;
4145 v += n;
4146 } while (len);
4147
4148 return handled;
4149 }
4150
4151 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4152 {
4153 int handled = 0;
4154 int n;
4155
4156 do {
4157 n = min(len, 8);
4158 if (!(lapic_in_kernel(vcpu) &&
4159 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4160 addr, n, v))
4161 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4162 break;
4163 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4164 handled += n;
4165 addr += n;
4166 len -= n;
4167 v += n;
4168 } while (len);
4169
4170 return handled;
4171 }
4172
4173 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4174 struct kvm_segment *var, int seg)
4175 {
4176 kvm_x86_ops->set_segment(vcpu, var, seg);
4177 }
4178
4179 void kvm_get_segment(struct kvm_vcpu *vcpu,
4180 struct kvm_segment *var, int seg)
4181 {
4182 kvm_x86_ops->get_segment(vcpu, var, seg);
4183 }
4184
4185 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4186 struct x86_exception *exception)
4187 {
4188 gpa_t t_gpa;
4189
4190 BUG_ON(!mmu_is_nested(vcpu));
4191
4192 /* NPT walks are always user-walks */
4193 access |= PFERR_USER_MASK;
4194 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4195
4196 return t_gpa;
4197 }
4198
4199 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4200 struct x86_exception *exception)
4201 {
4202 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4203 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4204 }
4205
4206 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4207 struct x86_exception *exception)
4208 {
4209 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4210 access |= PFERR_FETCH_MASK;
4211 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4212 }
4213
4214 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4215 struct x86_exception *exception)
4216 {
4217 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4218 access |= PFERR_WRITE_MASK;
4219 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4220 }
4221
4222 /* uses this to access any guest's mapped memory without checking CPL */
4223 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4224 struct x86_exception *exception)
4225 {
4226 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4227 }
4228
4229 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4230 struct kvm_vcpu *vcpu, u32 access,
4231 struct x86_exception *exception)
4232 {
4233 void *data = val;
4234 int r = X86EMUL_CONTINUE;
4235
4236 while (bytes) {
4237 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4238 exception);
4239 unsigned offset = addr & (PAGE_SIZE-1);
4240 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4241 int ret;
4242
4243 if (gpa == UNMAPPED_GVA)
4244 return X86EMUL_PROPAGATE_FAULT;
4245 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4246 offset, toread);
4247 if (ret < 0) {
4248 r = X86EMUL_IO_NEEDED;
4249 goto out;
4250 }
4251
4252 bytes -= toread;
4253 data += toread;
4254 addr += toread;
4255 }
4256 out:
4257 return r;
4258 }
4259
4260 /* used for instruction fetching */
4261 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4262 gva_t addr, void *val, unsigned int bytes,
4263 struct x86_exception *exception)
4264 {
4265 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4266 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4267 unsigned offset;
4268 int ret;
4269
4270 /* Inline kvm_read_guest_virt_helper for speed. */
4271 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4272 exception);
4273 if (unlikely(gpa == UNMAPPED_GVA))
4274 return X86EMUL_PROPAGATE_FAULT;
4275
4276 offset = addr & (PAGE_SIZE-1);
4277 if (WARN_ON(offset + bytes > PAGE_SIZE))
4278 bytes = (unsigned)PAGE_SIZE - offset;
4279 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4280 offset, bytes);
4281 if (unlikely(ret < 0))
4282 return X86EMUL_IO_NEEDED;
4283
4284 return X86EMUL_CONTINUE;
4285 }
4286
4287 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4288 gva_t addr, void *val, unsigned int bytes,
4289 struct x86_exception *exception)
4290 {
4291 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4292 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4293
4294 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4295 exception);
4296 }
4297 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4298
4299 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4300 gva_t addr, void *val, unsigned int bytes,
4301 struct x86_exception *exception)
4302 {
4303 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4304 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4305 }
4306
4307 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4308 unsigned long addr, void *val, unsigned int bytes)
4309 {
4310 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4311 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4312
4313 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4314 }
4315
4316 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4317 gva_t addr, void *val,
4318 unsigned int bytes,
4319 struct x86_exception *exception)
4320 {
4321 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4322 void *data = val;
4323 int r = X86EMUL_CONTINUE;
4324
4325 while (bytes) {
4326 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4327 PFERR_WRITE_MASK,
4328 exception);
4329 unsigned offset = addr & (PAGE_SIZE-1);
4330 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4331 int ret;
4332
4333 if (gpa == UNMAPPED_GVA)
4334 return X86EMUL_PROPAGATE_FAULT;
4335 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4336 if (ret < 0) {
4337 r = X86EMUL_IO_NEEDED;
4338 goto out;
4339 }
4340
4341 bytes -= towrite;
4342 data += towrite;
4343 addr += towrite;
4344 }
4345 out:
4346 return r;
4347 }
4348 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4349
4350 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4351 gpa_t *gpa, struct x86_exception *exception,
4352 bool write)
4353 {
4354 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4355 | (write ? PFERR_WRITE_MASK : 0);
4356
4357 /*
4358 * currently PKRU is only applied to ept enabled guest so
4359 * there is no pkey in EPT page table for L1 guest or EPT
4360 * shadow page table for L2 guest.
4361 */
4362 if (vcpu_match_mmio_gva(vcpu, gva)
4363 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4364 vcpu->arch.access, 0, access)) {
4365 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4366 (gva & (PAGE_SIZE - 1));
4367 trace_vcpu_match_mmio(gva, *gpa, write, false);
4368 return 1;
4369 }
4370
4371 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4372
4373 if (*gpa == UNMAPPED_GVA)
4374 return -1;
4375
4376 /* For APIC access vmexit */
4377 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4378 return 1;
4379
4380 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4381 trace_vcpu_match_mmio(gva, *gpa, write, true);
4382 return 1;
4383 }
4384
4385 return 0;
4386 }
4387
4388 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4389 const void *val, int bytes)
4390 {
4391 int ret;
4392
4393 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4394 if (ret < 0)
4395 return 0;
4396 kvm_page_track_write(vcpu, gpa, val, bytes);
4397 return 1;
4398 }
4399
4400 struct read_write_emulator_ops {
4401 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4402 int bytes);
4403 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4404 void *val, int bytes);
4405 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4406 int bytes, void *val);
4407 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4408 void *val, int bytes);
4409 bool write;
4410 };
4411
4412 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4413 {
4414 if (vcpu->mmio_read_completed) {
4415 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4416 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4417 vcpu->mmio_read_completed = 0;
4418 return 1;
4419 }
4420
4421 return 0;
4422 }
4423
4424 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4425 void *val, int bytes)
4426 {
4427 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4428 }
4429
4430 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4431 void *val, int bytes)
4432 {
4433 return emulator_write_phys(vcpu, gpa, val, bytes);
4434 }
4435
4436 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4437 {
4438 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4439 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4440 }
4441
4442 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4443 void *val, int bytes)
4444 {
4445 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4446 return X86EMUL_IO_NEEDED;
4447 }
4448
4449 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4450 void *val, int bytes)
4451 {
4452 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4453
4454 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4455 return X86EMUL_CONTINUE;
4456 }
4457
4458 static const struct read_write_emulator_ops read_emultor = {
4459 .read_write_prepare = read_prepare,
4460 .read_write_emulate = read_emulate,
4461 .read_write_mmio = vcpu_mmio_read,
4462 .read_write_exit_mmio = read_exit_mmio,
4463 };
4464
4465 static const struct read_write_emulator_ops write_emultor = {
4466 .read_write_emulate = write_emulate,
4467 .read_write_mmio = write_mmio,
4468 .read_write_exit_mmio = write_exit_mmio,
4469 .write = true,
4470 };
4471
4472 static int emulator_read_write_onepage(unsigned long addr, void *val,
4473 unsigned int bytes,
4474 struct x86_exception *exception,
4475 struct kvm_vcpu *vcpu,
4476 const struct read_write_emulator_ops *ops)
4477 {
4478 gpa_t gpa;
4479 int handled, ret;
4480 bool write = ops->write;
4481 struct kvm_mmio_fragment *frag;
4482
4483 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4484
4485 if (ret < 0)
4486 return X86EMUL_PROPAGATE_FAULT;
4487
4488 /* For APIC access vmexit */
4489 if (ret)
4490 goto mmio;
4491
4492 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4493 return X86EMUL_CONTINUE;
4494
4495 mmio:
4496 /*
4497 * Is this MMIO handled locally?
4498 */
4499 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4500 if (handled == bytes)
4501 return X86EMUL_CONTINUE;
4502
4503 gpa += handled;
4504 bytes -= handled;
4505 val += handled;
4506
4507 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4508 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4509 frag->gpa = gpa;
4510 frag->data = val;
4511 frag->len = bytes;
4512 return X86EMUL_CONTINUE;
4513 }
4514
4515 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4516 unsigned long addr,
4517 void *val, unsigned int bytes,
4518 struct x86_exception *exception,
4519 const struct read_write_emulator_ops *ops)
4520 {
4521 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4522 gpa_t gpa;
4523 int rc;
4524
4525 if (ops->read_write_prepare &&
4526 ops->read_write_prepare(vcpu, val, bytes))
4527 return X86EMUL_CONTINUE;
4528
4529 vcpu->mmio_nr_fragments = 0;
4530
4531 /* Crossing a page boundary? */
4532 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4533 int now;
4534
4535 now = -addr & ~PAGE_MASK;
4536 rc = emulator_read_write_onepage(addr, val, now, exception,
4537 vcpu, ops);
4538
4539 if (rc != X86EMUL_CONTINUE)
4540 return rc;
4541 addr += now;
4542 if (ctxt->mode != X86EMUL_MODE_PROT64)
4543 addr = (u32)addr;
4544 val += now;
4545 bytes -= now;
4546 }
4547
4548 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4549 vcpu, ops);
4550 if (rc != X86EMUL_CONTINUE)
4551 return rc;
4552
4553 if (!vcpu->mmio_nr_fragments)
4554 return rc;
4555
4556 gpa = vcpu->mmio_fragments[0].gpa;
4557
4558 vcpu->mmio_needed = 1;
4559 vcpu->mmio_cur_fragment = 0;
4560
4561 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4562 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4563 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4564 vcpu->run->mmio.phys_addr = gpa;
4565
4566 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4567 }
4568
4569 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4570 unsigned long addr,
4571 void *val,
4572 unsigned int bytes,
4573 struct x86_exception *exception)
4574 {
4575 return emulator_read_write(ctxt, addr, val, bytes,
4576 exception, &read_emultor);
4577 }
4578
4579 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4580 unsigned long addr,
4581 const void *val,
4582 unsigned int bytes,
4583 struct x86_exception *exception)
4584 {
4585 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4586 exception, &write_emultor);
4587 }
4588
4589 #define CMPXCHG_TYPE(t, ptr, old, new) \
4590 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4591
4592 #ifdef CONFIG_X86_64
4593 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4594 #else
4595 # define CMPXCHG64(ptr, old, new) \
4596 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4597 #endif
4598
4599 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4600 unsigned long addr,
4601 const void *old,
4602 const void *new,
4603 unsigned int bytes,
4604 struct x86_exception *exception)
4605 {
4606 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4607 gpa_t gpa;
4608 struct page *page;
4609 char *kaddr;
4610 bool exchanged;
4611
4612 /* guests cmpxchg8b have to be emulated atomically */
4613 if (bytes > 8 || (bytes & (bytes - 1)))
4614 goto emul_write;
4615
4616 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4617
4618 if (gpa == UNMAPPED_GVA ||
4619 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4620 goto emul_write;
4621
4622 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4623 goto emul_write;
4624
4625 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4626 if (is_error_page(page))
4627 goto emul_write;
4628
4629 kaddr = kmap_atomic(page);
4630 kaddr += offset_in_page(gpa);
4631 switch (bytes) {
4632 case 1:
4633 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4634 break;
4635 case 2:
4636 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4637 break;
4638 case 4:
4639 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4640 break;
4641 case 8:
4642 exchanged = CMPXCHG64(kaddr, old, new);
4643 break;
4644 default:
4645 BUG();
4646 }
4647 kunmap_atomic(kaddr);
4648 kvm_release_page_dirty(page);
4649
4650 if (!exchanged)
4651 return X86EMUL_CMPXCHG_FAILED;
4652
4653 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4654 kvm_page_track_write(vcpu, gpa, new, bytes);
4655
4656 return X86EMUL_CONTINUE;
4657
4658 emul_write:
4659 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4660
4661 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4662 }
4663
4664 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4665 {
4666 /* TODO: String I/O for in kernel device */
4667 int r;
4668
4669 if (vcpu->arch.pio.in)
4670 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4671 vcpu->arch.pio.size, pd);
4672 else
4673 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4674 vcpu->arch.pio.port, vcpu->arch.pio.size,
4675 pd);
4676 return r;
4677 }
4678
4679 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4680 unsigned short port, void *val,
4681 unsigned int count, bool in)
4682 {
4683 vcpu->arch.pio.port = port;
4684 vcpu->arch.pio.in = in;
4685 vcpu->arch.pio.count = count;
4686 vcpu->arch.pio.size = size;
4687
4688 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4689 vcpu->arch.pio.count = 0;
4690 return 1;
4691 }
4692
4693 vcpu->run->exit_reason = KVM_EXIT_IO;
4694 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4695 vcpu->run->io.size = size;
4696 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4697 vcpu->run->io.count = count;
4698 vcpu->run->io.port = port;
4699
4700 return 0;
4701 }
4702
4703 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4704 int size, unsigned short port, void *val,
4705 unsigned int count)
4706 {
4707 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4708 int ret;
4709
4710 if (vcpu->arch.pio.count)
4711 goto data_avail;
4712
4713 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4714 if (ret) {
4715 data_avail:
4716 memcpy(val, vcpu->arch.pio_data, size * count);
4717 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4718 vcpu->arch.pio.count = 0;
4719 return 1;
4720 }
4721
4722 return 0;
4723 }
4724
4725 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4726 int size, unsigned short port,
4727 const void *val, unsigned int count)
4728 {
4729 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4730
4731 memcpy(vcpu->arch.pio_data, val, size * count);
4732 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4733 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4734 }
4735
4736 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4737 {
4738 return kvm_x86_ops->get_segment_base(vcpu, seg);
4739 }
4740
4741 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4742 {
4743 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4744 }
4745
4746 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4747 {
4748 if (!need_emulate_wbinvd(vcpu))
4749 return X86EMUL_CONTINUE;
4750
4751 if (kvm_x86_ops->has_wbinvd_exit()) {
4752 int cpu = get_cpu();
4753
4754 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4755 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4756 wbinvd_ipi, NULL, 1);
4757 put_cpu();
4758 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4759 } else
4760 wbinvd();
4761 return X86EMUL_CONTINUE;
4762 }
4763
4764 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4765 {
4766 kvm_x86_ops->skip_emulated_instruction(vcpu);
4767 return kvm_emulate_wbinvd_noskip(vcpu);
4768 }
4769 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4770
4771
4772
4773 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4774 {
4775 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4776 }
4777
4778 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4779 unsigned long *dest)
4780 {
4781 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4782 }
4783
4784 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4785 unsigned long value)
4786 {
4787
4788 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4789 }
4790
4791 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4792 {
4793 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4794 }
4795
4796 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4797 {
4798 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4799 unsigned long value;
4800
4801 switch (cr) {
4802 case 0:
4803 value = kvm_read_cr0(vcpu);
4804 break;
4805 case 2:
4806 value = vcpu->arch.cr2;
4807 break;
4808 case 3:
4809 value = kvm_read_cr3(vcpu);
4810 break;
4811 case 4:
4812 value = kvm_read_cr4(vcpu);
4813 break;
4814 case 8:
4815 value = kvm_get_cr8(vcpu);
4816 break;
4817 default:
4818 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4819 return 0;
4820 }
4821
4822 return value;
4823 }
4824
4825 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4826 {
4827 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4828 int res = 0;
4829
4830 switch (cr) {
4831 case 0:
4832 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4833 break;
4834 case 2:
4835 vcpu->arch.cr2 = val;
4836 break;
4837 case 3:
4838 res = kvm_set_cr3(vcpu, val);
4839 break;
4840 case 4:
4841 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4842 break;
4843 case 8:
4844 res = kvm_set_cr8(vcpu, val);
4845 break;
4846 default:
4847 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4848 res = -1;
4849 }
4850
4851 return res;
4852 }
4853
4854 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4855 {
4856 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4857 }
4858
4859 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4860 {
4861 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4862 }
4863
4864 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4865 {
4866 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4867 }
4868
4869 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4870 {
4871 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4872 }
4873
4874 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4875 {
4876 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4877 }
4878
4879 static unsigned long emulator_get_cached_segment_base(
4880 struct x86_emulate_ctxt *ctxt, int seg)
4881 {
4882 return get_segment_base(emul_to_vcpu(ctxt), seg);
4883 }
4884
4885 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4886 struct desc_struct *desc, u32 *base3,
4887 int seg)
4888 {
4889 struct kvm_segment var;
4890
4891 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4892 *selector = var.selector;
4893
4894 if (var.unusable) {
4895 memset(desc, 0, sizeof(*desc));
4896 return false;
4897 }
4898
4899 if (var.g)
4900 var.limit >>= 12;
4901 set_desc_limit(desc, var.limit);
4902 set_desc_base(desc, (unsigned long)var.base);
4903 #ifdef CONFIG_X86_64
4904 if (base3)
4905 *base3 = var.base >> 32;
4906 #endif
4907 desc->type = var.type;
4908 desc->s = var.s;
4909 desc->dpl = var.dpl;
4910 desc->p = var.present;
4911 desc->avl = var.avl;
4912 desc->l = var.l;
4913 desc->d = var.db;
4914 desc->g = var.g;
4915
4916 return true;
4917 }
4918
4919 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4920 struct desc_struct *desc, u32 base3,
4921 int seg)
4922 {
4923 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4924 struct kvm_segment var;
4925
4926 var.selector = selector;
4927 var.base = get_desc_base(desc);
4928 #ifdef CONFIG_X86_64
4929 var.base |= ((u64)base3) << 32;
4930 #endif
4931 var.limit = get_desc_limit(desc);
4932 if (desc->g)
4933 var.limit = (var.limit << 12) | 0xfff;
4934 var.type = desc->type;
4935 var.dpl = desc->dpl;
4936 var.db = desc->d;
4937 var.s = desc->s;
4938 var.l = desc->l;
4939 var.g = desc->g;
4940 var.avl = desc->avl;
4941 var.present = desc->p;
4942 var.unusable = !var.present;
4943 var.padding = 0;
4944
4945 kvm_set_segment(vcpu, &var, seg);
4946 return;
4947 }
4948
4949 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4950 u32 msr_index, u64 *pdata)
4951 {
4952 struct msr_data msr;
4953 int r;
4954
4955 msr.index = msr_index;
4956 msr.host_initiated = false;
4957 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4958 if (r)
4959 return r;
4960
4961 *pdata = msr.data;
4962 return 0;
4963 }
4964
4965 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4966 u32 msr_index, u64 data)
4967 {
4968 struct msr_data msr;
4969
4970 msr.data = data;
4971 msr.index = msr_index;
4972 msr.host_initiated = false;
4973 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4974 }
4975
4976 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4977 {
4978 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4979
4980 return vcpu->arch.smbase;
4981 }
4982
4983 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4984 {
4985 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4986
4987 vcpu->arch.smbase = smbase;
4988 }
4989
4990 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4991 u32 pmc)
4992 {
4993 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4994 }
4995
4996 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4997 u32 pmc, u64 *pdata)
4998 {
4999 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5000 }
5001
5002 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5003 {
5004 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5005 }
5006
5007 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5008 {
5009 preempt_disable();
5010 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5011 /*
5012 * CR0.TS may reference the host fpu state, not the guest fpu state,
5013 * so it may be clear at this point.
5014 */
5015 clts();
5016 }
5017
5018 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5019 {
5020 preempt_enable();
5021 }
5022
5023 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5024 struct x86_instruction_info *info,
5025 enum x86_intercept_stage stage)
5026 {
5027 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5028 }
5029
5030 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5031 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5032 {
5033 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5034 }
5035
5036 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5037 {
5038 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5039 }
5040
5041 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5042 {
5043 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5044 }
5045
5046 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5047 {
5048 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5049 }
5050
5051 static const struct x86_emulate_ops emulate_ops = {
5052 .read_gpr = emulator_read_gpr,
5053 .write_gpr = emulator_write_gpr,
5054 .read_std = kvm_read_guest_virt_system,
5055 .write_std = kvm_write_guest_virt_system,
5056 .read_phys = kvm_read_guest_phys_system,
5057 .fetch = kvm_fetch_guest_virt,
5058 .read_emulated = emulator_read_emulated,
5059 .write_emulated = emulator_write_emulated,
5060 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5061 .invlpg = emulator_invlpg,
5062 .pio_in_emulated = emulator_pio_in_emulated,
5063 .pio_out_emulated = emulator_pio_out_emulated,
5064 .get_segment = emulator_get_segment,
5065 .set_segment = emulator_set_segment,
5066 .get_cached_segment_base = emulator_get_cached_segment_base,
5067 .get_gdt = emulator_get_gdt,
5068 .get_idt = emulator_get_idt,
5069 .set_gdt = emulator_set_gdt,
5070 .set_idt = emulator_set_idt,
5071 .get_cr = emulator_get_cr,
5072 .set_cr = emulator_set_cr,
5073 .cpl = emulator_get_cpl,
5074 .get_dr = emulator_get_dr,
5075 .set_dr = emulator_set_dr,
5076 .get_smbase = emulator_get_smbase,
5077 .set_smbase = emulator_set_smbase,
5078 .set_msr = emulator_set_msr,
5079 .get_msr = emulator_get_msr,
5080 .check_pmc = emulator_check_pmc,
5081 .read_pmc = emulator_read_pmc,
5082 .halt = emulator_halt,
5083 .wbinvd = emulator_wbinvd,
5084 .fix_hypercall = emulator_fix_hypercall,
5085 .get_fpu = emulator_get_fpu,
5086 .put_fpu = emulator_put_fpu,
5087 .intercept = emulator_intercept,
5088 .get_cpuid = emulator_get_cpuid,
5089 .set_nmi_mask = emulator_set_nmi_mask,
5090 };
5091
5092 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5093 {
5094 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5095 /*
5096 * an sti; sti; sequence only disable interrupts for the first
5097 * instruction. So, if the last instruction, be it emulated or
5098 * not, left the system with the INT_STI flag enabled, it
5099 * means that the last instruction is an sti. We should not
5100 * leave the flag on in this case. The same goes for mov ss
5101 */
5102 if (int_shadow & mask)
5103 mask = 0;
5104 if (unlikely(int_shadow || mask)) {
5105 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5106 if (!mask)
5107 kvm_make_request(KVM_REQ_EVENT, vcpu);
5108 }
5109 }
5110
5111 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5112 {
5113 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5114 if (ctxt->exception.vector == PF_VECTOR)
5115 return kvm_propagate_fault(vcpu, &ctxt->exception);
5116
5117 if (ctxt->exception.error_code_valid)
5118 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5119 ctxt->exception.error_code);
5120 else
5121 kvm_queue_exception(vcpu, ctxt->exception.vector);
5122 return false;
5123 }
5124
5125 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5126 {
5127 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5128 int cs_db, cs_l;
5129
5130 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5131
5132 ctxt->eflags = kvm_get_rflags(vcpu);
5133 ctxt->eip = kvm_rip_read(vcpu);
5134 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5135 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5136 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5137 cs_db ? X86EMUL_MODE_PROT32 :
5138 X86EMUL_MODE_PROT16;
5139 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5140 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5141 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5142 ctxt->emul_flags = vcpu->arch.hflags;
5143
5144 init_decode_cache(ctxt);
5145 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5146 }
5147
5148 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5149 {
5150 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5151 int ret;
5152
5153 init_emulate_ctxt(vcpu);
5154
5155 ctxt->op_bytes = 2;
5156 ctxt->ad_bytes = 2;
5157 ctxt->_eip = ctxt->eip + inc_eip;
5158 ret = emulate_int_real(ctxt, irq);
5159
5160 if (ret != X86EMUL_CONTINUE)
5161 return EMULATE_FAIL;
5162
5163 ctxt->eip = ctxt->_eip;
5164 kvm_rip_write(vcpu, ctxt->eip);
5165 kvm_set_rflags(vcpu, ctxt->eflags);
5166
5167 if (irq == NMI_VECTOR)
5168 vcpu->arch.nmi_pending = 0;
5169 else
5170 vcpu->arch.interrupt.pending = false;
5171
5172 return EMULATE_DONE;
5173 }
5174 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5175
5176 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5177 {
5178 int r = EMULATE_DONE;
5179
5180 ++vcpu->stat.insn_emulation_fail;
5181 trace_kvm_emulate_insn_failed(vcpu);
5182 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5183 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5184 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5185 vcpu->run->internal.ndata = 0;
5186 r = EMULATE_FAIL;
5187 }
5188 kvm_queue_exception(vcpu, UD_VECTOR);
5189
5190 return r;
5191 }
5192
5193 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5194 bool write_fault_to_shadow_pgtable,
5195 int emulation_type)
5196 {
5197 gpa_t gpa = cr2;
5198 kvm_pfn_t pfn;
5199
5200 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5201 return false;
5202
5203 if (!vcpu->arch.mmu.direct_map) {
5204 /*
5205 * Write permission should be allowed since only
5206 * write access need to be emulated.
5207 */
5208 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5209
5210 /*
5211 * If the mapping is invalid in guest, let cpu retry
5212 * it to generate fault.
5213 */
5214 if (gpa == UNMAPPED_GVA)
5215 return true;
5216 }
5217
5218 /*
5219 * Do not retry the unhandleable instruction if it faults on the
5220 * readonly host memory, otherwise it will goto a infinite loop:
5221 * retry instruction -> write #PF -> emulation fail -> retry
5222 * instruction -> ...
5223 */
5224 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5225
5226 /*
5227 * If the instruction failed on the error pfn, it can not be fixed,
5228 * report the error to userspace.
5229 */
5230 if (is_error_noslot_pfn(pfn))
5231 return false;
5232
5233 kvm_release_pfn_clean(pfn);
5234
5235 /* The instructions are well-emulated on direct mmu. */
5236 if (vcpu->arch.mmu.direct_map) {
5237 unsigned int indirect_shadow_pages;
5238
5239 spin_lock(&vcpu->kvm->mmu_lock);
5240 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5241 spin_unlock(&vcpu->kvm->mmu_lock);
5242
5243 if (indirect_shadow_pages)
5244 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5245
5246 return true;
5247 }
5248
5249 /*
5250 * if emulation was due to access to shadowed page table
5251 * and it failed try to unshadow page and re-enter the
5252 * guest to let CPU execute the instruction.
5253 */
5254 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5255
5256 /*
5257 * If the access faults on its page table, it can not
5258 * be fixed by unprotecting shadow page and it should
5259 * be reported to userspace.
5260 */
5261 return !write_fault_to_shadow_pgtable;
5262 }
5263
5264 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5265 unsigned long cr2, int emulation_type)
5266 {
5267 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5268 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5269
5270 last_retry_eip = vcpu->arch.last_retry_eip;
5271 last_retry_addr = vcpu->arch.last_retry_addr;
5272
5273 /*
5274 * If the emulation is caused by #PF and it is non-page_table
5275 * writing instruction, it means the VM-EXIT is caused by shadow
5276 * page protected, we can zap the shadow page and retry this
5277 * instruction directly.
5278 *
5279 * Note: if the guest uses a non-page-table modifying instruction
5280 * on the PDE that points to the instruction, then we will unmap
5281 * the instruction and go to an infinite loop. So, we cache the
5282 * last retried eip and the last fault address, if we meet the eip
5283 * and the address again, we can break out of the potential infinite
5284 * loop.
5285 */
5286 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5287
5288 if (!(emulation_type & EMULTYPE_RETRY))
5289 return false;
5290
5291 if (x86_page_table_writing_insn(ctxt))
5292 return false;
5293
5294 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5295 return false;
5296
5297 vcpu->arch.last_retry_eip = ctxt->eip;
5298 vcpu->arch.last_retry_addr = cr2;
5299
5300 if (!vcpu->arch.mmu.direct_map)
5301 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5302
5303 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5304
5305 return true;
5306 }
5307
5308 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5309 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5310
5311 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5312 {
5313 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5314 /* This is a good place to trace that we are exiting SMM. */
5315 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5316
5317 /* Process a latched INIT or SMI, if any. */
5318 kvm_make_request(KVM_REQ_EVENT, vcpu);
5319 }
5320
5321 kvm_mmu_reset_context(vcpu);
5322 }
5323
5324 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5325 {
5326 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5327
5328 vcpu->arch.hflags = emul_flags;
5329
5330 if (changed & HF_SMM_MASK)
5331 kvm_smm_changed(vcpu);
5332 }
5333
5334 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5335 unsigned long *db)
5336 {
5337 u32 dr6 = 0;
5338 int i;
5339 u32 enable, rwlen;
5340
5341 enable = dr7;
5342 rwlen = dr7 >> 16;
5343 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5344 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5345 dr6 |= (1 << i);
5346 return dr6;
5347 }
5348
5349 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5350 {
5351 struct kvm_run *kvm_run = vcpu->run;
5352
5353 /*
5354 * rflags is the old, "raw" value of the flags. The new value has
5355 * not been saved yet.
5356 *
5357 * This is correct even for TF set by the guest, because "the
5358 * processor will not generate this exception after the instruction
5359 * that sets the TF flag".
5360 */
5361 if (unlikely(rflags & X86_EFLAGS_TF)) {
5362 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5363 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5364 DR6_RTM;
5365 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5366 kvm_run->debug.arch.exception = DB_VECTOR;
5367 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5368 *r = EMULATE_USER_EXIT;
5369 } else {
5370 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5371 /*
5372 * "Certain debug exceptions may clear bit 0-3. The
5373 * remaining contents of the DR6 register are never
5374 * cleared by the processor".
5375 */
5376 vcpu->arch.dr6 &= ~15;
5377 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5378 kvm_queue_exception(vcpu, DB_VECTOR);
5379 }
5380 }
5381 }
5382
5383 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5384 {
5385 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5386 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5387 struct kvm_run *kvm_run = vcpu->run;
5388 unsigned long eip = kvm_get_linear_rip(vcpu);
5389 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5390 vcpu->arch.guest_debug_dr7,
5391 vcpu->arch.eff_db);
5392
5393 if (dr6 != 0) {
5394 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5395 kvm_run->debug.arch.pc = eip;
5396 kvm_run->debug.arch.exception = DB_VECTOR;
5397 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5398 *r = EMULATE_USER_EXIT;
5399 return true;
5400 }
5401 }
5402
5403 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5404 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5405 unsigned long eip = kvm_get_linear_rip(vcpu);
5406 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5407 vcpu->arch.dr7,
5408 vcpu->arch.db);
5409
5410 if (dr6 != 0) {
5411 vcpu->arch.dr6 &= ~15;
5412 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5413 kvm_queue_exception(vcpu, DB_VECTOR);
5414 *r = EMULATE_DONE;
5415 return true;
5416 }
5417 }
5418
5419 return false;
5420 }
5421
5422 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5423 unsigned long cr2,
5424 int emulation_type,
5425 void *insn,
5426 int insn_len)
5427 {
5428 int r;
5429 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5430 bool writeback = true;
5431 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5432
5433 /*
5434 * Clear write_fault_to_shadow_pgtable here to ensure it is
5435 * never reused.
5436 */
5437 vcpu->arch.write_fault_to_shadow_pgtable = false;
5438 kvm_clear_exception_queue(vcpu);
5439
5440 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5441 init_emulate_ctxt(vcpu);
5442
5443 /*
5444 * We will reenter on the same instruction since
5445 * we do not set complete_userspace_io. This does not
5446 * handle watchpoints yet, those would be handled in
5447 * the emulate_ops.
5448 */
5449 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5450 return r;
5451
5452 ctxt->interruptibility = 0;
5453 ctxt->have_exception = false;
5454 ctxt->exception.vector = -1;
5455 ctxt->perm_ok = false;
5456
5457 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5458
5459 r = x86_decode_insn(ctxt, insn, insn_len);
5460
5461 trace_kvm_emulate_insn_start(vcpu);
5462 ++vcpu->stat.insn_emulation;
5463 if (r != EMULATION_OK) {
5464 if (emulation_type & EMULTYPE_TRAP_UD)
5465 return EMULATE_FAIL;
5466 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5467 emulation_type))
5468 return EMULATE_DONE;
5469 if (emulation_type & EMULTYPE_SKIP)
5470 return EMULATE_FAIL;
5471 return handle_emulation_failure(vcpu);
5472 }
5473 }
5474
5475 if (emulation_type & EMULTYPE_SKIP) {
5476 kvm_rip_write(vcpu, ctxt->_eip);
5477 if (ctxt->eflags & X86_EFLAGS_RF)
5478 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5479 return EMULATE_DONE;
5480 }
5481
5482 if (retry_instruction(ctxt, cr2, emulation_type))
5483 return EMULATE_DONE;
5484
5485 /* this is needed for vmware backdoor interface to work since it
5486 changes registers values during IO operation */
5487 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5488 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5489 emulator_invalidate_register_cache(ctxt);
5490 }
5491
5492 restart:
5493 r = x86_emulate_insn(ctxt);
5494
5495 if (r == EMULATION_INTERCEPTED)
5496 return EMULATE_DONE;
5497
5498 if (r == EMULATION_FAILED) {
5499 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5500 emulation_type))
5501 return EMULATE_DONE;
5502
5503 return handle_emulation_failure(vcpu);
5504 }
5505
5506 if (ctxt->have_exception) {
5507 r = EMULATE_DONE;
5508 if (inject_emulated_exception(vcpu))
5509 return r;
5510 } else if (vcpu->arch.pio.count) {
5511 if (!vcpu->arch.pio.in) {
5512 /* FIXME: return into emulator if single-stepping. */
5513 vcpu->arch.pio.count = 0;
5514 } else {
5515 writeback = false;
5516 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5517 }
5518 r = EMULATE_USER_EXIT;
5519 } else if (vcpu->mmio_needed) {
5520 if (!vcpu->mmio_is_write)
5521 writeback = false;
5522 r = EMULATE_USER_EXIT;
5523 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5524 } else if (r == EMULATION_RESTART)
5525 goto restart;
5526 else
5527 r = EMULATE_DONE;
5528
5529 if (writeback) {
5530 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5531 toggle_interruptibility(vcpu, ctxt->interruptibility);
5532 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5533 if (vcpu->arch.hflags != ctxt->emul_flags)
5534 kvm_set_hflags(vcpu, ctxt->emul_flags);
5535 kvm_rip_write(vcpu, ctxt->eip);
5536 if (r == EMULATE_DONE)
5537 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5538 if (!ctxt->have_exception ||
5539 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5540 __kvm_set_rflags(vcpu, ctxt->eflags);
5541
5542 /*
5543 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5544 * do nothing, and it will be requested again as soon as
5545 * the shadow expires. But we still need to check here,
5546 * because POPF has no interrupt shadow.
5547 */
5548 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5549 kvm_make_request(KVM_REQ_EVENT, vcpu);
5550 } else
5551 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5552
5553 return r;
5554 }
5555 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5556
5557 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5558 {
5559 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5560 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5561 size, port, &val, 1);
5562 /* do not return to emulator after return from userspace */
5563 vcpu->arch.pio.count = 0;
5564 return ret;
5565 }
5566 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5567
5568 static void tsc_bad(void *info)
5569 {
5570 __this_cpu_write(cpu_tsc_khz, 0);
5571 }
5572
5573 static void tsc_khz_changed(void *data)
5574 {
5575 struct cpufreq_freqs *freq = data;
5576 unsigned long khz = 0;
5577
5578 if (data)
5579 khz = freq->new;
5580 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5581 khz = cpufreq_quick_get(raw_smp_processor_id());
5582 if (!khz)
5583 khz = tsc_khz;
5584 __this_cpu_write(cpu_tsc_khz, khz);
5585 }
5586
5587 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5588 void *data)
5589 {
5590 struct cpufreq_freqs *freq = data;
5591 struct kvm *kvm;
5592 struct kvm_vcpu *vcpu;
5593 int i, send_ipi = 0;
5594
5595 /*
5596 * We allow guests to temporarily run on slowing clocks,
5597 * provided we notify them after, or to run on accelerating
5598 * clocks, provided we notify them before. Thus time never
5599 * goes backwards.
5600 *
5601 * However, we have a problem. We can't atomically update
5602 * the frequency of a given CPU from this function; it is
5603 * merely a notifier, which can be called from any CPU.
5604 * Changing the TSC frequency at arbitrary points in time
5605 * requires a recomputation of local variables related to
5606 * the TSC for each VCPU. We must flag these local variables
5607 * to be updated and be sure the update takes place with the
5608 * new frequency before any guests proceed.
5609 *
5610 * Unfortunately, the combination of hotplug CPU and frequency
5611 * change creates an intractable locking scenario; the order
5612 * of when these callouts happen is undefined with respect to
5613 * CPU hotplug, and they can race with each other. As such,
5614 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5615 * undefined; you can actually have a CPU frequency change take
5616 * place in between the computation of X and the setting of the
5617 * variable. To protect against this problem, all updates of
5618 * the per_cpu tsc_khz variable are done in an interrupt
5619 * protected IPI, and all callers wishing to update the value
5620 * must wait for a synchronous IPI to complete (which is trivial
5621 * if the caller is on the CPU already). This establishes the
5622 * necessary total order on variable updates.
5623 *
5624 * Note that because a guest time update may take place
5625 * anytime after the setting of the VCPU's request bit, the
5626 * correct TSC value must be set before the request. However,
5627 * to ensure the update actually makes it to any guest which
5628 * starts running in hardware virtualization between the set
5629 * and the acquisition of the spinlock, we must also ping the
5630 * CPU after setting the request bit.
5631 *
5632 */
5633
5634 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5635 return 0;
5636 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5637 return 0;
5638
5639 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5640
5641 spin_lock(&kvm_lock);
5642 list_for_each_entry(kvm, &vm_list, vm_list) {
5643 kvm_for_each_vcpu(i, vcpu, kvm) {
5644 if (vcpu->cpu != freq->cpu)
5645 continue;
5646 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5647 if (vcpu->cpu != smp_processor_id())
5648 send_ipi = 1;
5649 }
5650 }
5651 spin_unlock(&kvm_lock);
5652
5653 if (freq->old < freq->new && send_ipi) {
5654 /*
5655 * We upscale the frequency. Must make the guest
5656 * doesn't see old kvmclock values while running with
5657 * the new frequency, otherwise we risk the guest sees
5658 * time go backwards.
5659 *
5660 * In case we update the frequency for another cpu
5661 * (which might be in guest context) send an interrupt
5662 * to kick the cpu out of guest context. Next time
5663 * guest context is entered kvmclock will be updated,
5664 * so the guest will not see stale values.
5665 */
5666 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5667 }
5668 return 0;
5669 }
5670
5671 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5672 .notifier_call = kvmclock_cpufreq_notifier
5673 };
5674
5675 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5676 unsigned long action, void *hcpu)
5677 {
5678 unsigned int cpu = (unsigned long)hcpu;
5679
5680 switch (action) {
5681 case CPU_ONLINE:
5682 case CPU_DOWN_FAILED:
5683 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5684 break;
5685 case CPU_DOWN_PREPARE:
5686 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5687 break;
5688 }
5689 return NOTIFY_OK;
5690 }
5691
5692 static struct notifier_block kvmclock_cpu_notifier_block = {
5693 .notifier_call = kvmclock_cpu_notifier,
5694 .priority = -INT_MAX
5695 };
5696
5697 static void kvm_timer_init(void)
5698 {
5699 int cpu;
5700
5701 max_tsc_khz = tsc_khz;
5702
5703 cpu_notifier_register_begin();
5704 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5705 #ifdef CONFIG_CPU_FREQ
5706 struct cpufreq_policy policy;
5707 memset(&policy, 0, sizeof(policy));
5708 cpu = get_cpu();
5709 cpufreq_get_policy(&policy, cpu);
5710 if (policy.cpuinfo.max_freq)
5711 max_tsc_khz = policy.cpuinfo.max_freq;
5712 put_cpu();
5713 #endif
5714 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5715 CPUFREQ_TRANSITION_NOTIFIER);
5716 }
5717 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5718 for_each_online_cpu(cpu)
5719 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5720
5721 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5722 cpu_notifier_register_done();
5723
5724 }
5725
5726 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5727
5728 int kvm_is_in_guest(void)
5729 {
5730 return __this_cpu_read(current_vcpu) != NULL;
5731 }
5732
5733 static int kvm_is_user_mode(void)
5734 {
5735 int user_mode = 3;
5736
5737 if (__this_cpu_read(current_vcpu))
5738 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5739
5740 return user_mode != 0;
5741 }
5742
5743 static unsigned long kvm_get_guest_ip(void)
5744 {
5745 unsigned long ip = 0;
5746
5747 if (__this_cpu_read(current_vcpu))
5748 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5749
5750 return ip;
5751 }
5752
5753 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5754 .is_in_guest = kvm_is_in_guest,
5755 .is_user_mode = kvm_is_user_mode,
5756 .get_guest_ip = kvm_get_guest_ip,
5757 };
5758
5759 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5760 {
5761 __this_cpu_write(current_vcpu, vcpu);
5762 }
5763 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5764
5765 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5766 {
5767 __this_cpu_write(current_vcpu, NULL);
5768 }
5769 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5770
5771 static void kvm_set_mmio_spte_mask(void)
5772 {
5773 u64 mask;
5774 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5775
5776 /*
5777 * Set the reserved bits and the present bit of an paging-structure
5778 * entry to generate page fault with PFER.RSV = 1.
5779 */
5780 /* Mask the reserved physical address bits. */
5781 mask = rsvd_bits(maxphyaddr, 51);
5782
5783 /* Bit 62 is always reserved for 32bit host. */
5784 mask |= 0x3ull << 62;
5785
5786 /* Set the present bit. */
5787 mask |= 1ull;
5788
5789 #ifdef CONFIG_X86_64
5790 /*
5791 * If reserved bit is not supported, clear the present bit to disable
5792 * mmio page fault.
5793 */
5794 if (maxphyaddr == 52)
5795 mask &= ~1ull;
5796 #endif
5797
5798 kvm_mmu_set_mmio_spte_mask(mask);
5799 }
5800
5801 #ifdef CONFIG_X86_64
5802 static void pvclock_gtod_update_fn(struct work_struct *work)
5803 {
5804 struct kvm *kvm;
5805
5806 struct kvm_vcpu *vcpu;
5807 int i;
5808
5809 spin_lock(&kvm_lock);
5810 list_for_each_entry(kvm, &vm_list, vm_list)
5811 kvm_for_each_vcpu(i, vcpu, kvm)
5812 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5813 atomic_set(&kvm_guest_has_master_clock, 0);
5814 spin_unlock(&kvm_lock);
5815 }
5816
5817 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5818
5819 /*
5820 * Notification about pvclock gtod data update.
5821 */
5822 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5823 void *priv)
5824 {
5825 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5826 struct timekeeper *tk = priv;
5827
5828 update_pvclock_gtod(tk);
5829
5830 /* disable master clock if host does not trust, or does not
5831 * use, TSC clocksource
5832 */
5833 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5834 atomic_read(&kvm_guest_has_master_clock) != 0)
5835 queue_work(system_long_wq, &pvclock_gtod_work);
5836
5837 return 0;
5838 }
5839
5840 static struct notifier_block pvclock_gtod_notifier = {
5841 .notifier_call = pvclock_gtod_notify,
5842 };
5843 #endif
5844
5845 int kvm_arch_init(void *opaque)
5846 {
5847 int r;
5848 struct kvm_x86_ops *ops = opaque;
5849
5850 if (kvm_x86_ops) {
5851 printk(KERN_ERR "kvm: already loaded the other module\n");
5852 r = -EEXIST;
5853 goto out;
5854 }
5855
5856 if (!ops->cpu_has_kvm_support()) {
5857 printk(KERN_ERR "kvm: no hardware support\n");
5858 r = -EOPNOTSUPP;
5859 goto out;
5860 }
5861 if (ops->disabled_by_bios()) {
5862 printk(KERN_ERR "kvm: disabled by bios\n");
5863 r = -EOPNOTSUPP;
5864 goto out;
5865 }
5866
5867 r = -ENOMEM;
5868 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5869 if (!shared_msrs) {
5870 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5871 goto out;
5872 }
5873
5874 r = kvm_mmu_module_init();
5875 if (r)
5876 goto out_free_percpu;
5877
5878 kvm_set_mmio_spte_mask();
5879
5880 kvm_x86_ops = ops;
5881
5882 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5883 PT_DIRTY_MASK, PT64_NX_MASK, 0,
5884 PT_PRESENT_MASK);
5885 kvm_timer_init();
5886
5887 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5888
5889 if (boot_cpu_has(X86_FEATURE_XSAVE))
5890 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5891
5892 kvm_lapic_init();
5893 #ifdef CONFIG_X86_64
5894 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5895 #endif
5896
5897 return 0;
5898
5899 out_free_percpu:
5900 free_percpu(shared_msrs);
5901 out:
5902 return r;
5903 }
5904
5905 void kvm_arch_exit(void)
5906 {
5907 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5908
5909 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5910 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5911 CPUFREQ_TRANSITION_NOTIFIER);
5912 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5913 #ifdef CONFIG_X86_64
5914 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5915 #endif
5916 kvm_x86_ops = NULL;
5917 kvm_mmu_module_exit();
5918 free_percpu(shared_msrs);
5919 }
5920
5921 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5922 {
5923 ++vcpu->stat.halt_exits;
5924 if (lapic_in_kernel(vcpu)) {
5925 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5926 return 1;
5927 } else {
5928 vcpu->run->exit_reason = KVM_EXIT_HLT;
5929 return 0;
5930 }
5931 }
5932 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5933
5934 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5935 {
5936 kvm_x86_ops->skip_emulated_instruction(vcpu);
5937 return kvm_vcpu_halt(vcpu);
5938 }
5939 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5940
5941 /*
5942 * kvm_pv_kick_cpu_op: Kick a vcpu.
5943 *
5944 * @apicid - apicid of vcpu to be kicked.
5945 */
5946 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5947 {
5948 struct kvm_lapic_irq lapic_irq;
5949
5950 lapic_irq.shorthand = 0;
5951 lapic_irq.dest_mode = 0;
5952 lapic_irq.dest_id = apicid;
5953 lapic_irq.msi_redir_hint = false;
5954
5955 lapic_irq.delivery_mode = APIC_DM_REMRD;
5956 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5957 }
5958
5959 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5960 {
5961 vcpu->arch.apicv_active = false;
5962 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5963 }
5964
5965 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5966 {
5967 unsigned long nr, a0, a1, a2, a3, ret;
5968 int op_64_bit, r = 1;
5969
5970 kvm_x86_ops->skip_emulated_instruction(vcpu);
5971
5972 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5973 return kvm_hv_hypercall(vcpu);
5974
5975 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5976 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5977 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5978 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5979 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5980
5981 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5982
5983 op_64_bit = is_64_bit_mode(vcpu);
5984 if (!op_64_bit) {
5985 nr &= 0xFFFFFFFF;
5986 a0 &= 0xFFFFFFFF;
5987 a1 &= 0xFFFFFFFF;
5988 a2 &= 0xFFFFFFFF;
5989 a3 &= 0xFFFFFFFF;
5990 }
5991
5992 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5993 ret = -KVM_EPERM;
5994 goto out;
5995 }
5996
5997 switch (nr) {
5998 case KVM_HC_VAPIC_POLL_IRQ:
5999 ret = 0;
6000 break;
6001 case KVM_HC_KICK_CPU:
6002 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6003 ret = 0;
6004 break;
6005 default:
6006 ret = -KVM_ENOSYS;
6007 break;
6008 }
6009 out:
6010 if (!op_64_bit)
6011 ret = (u32)ret;
6012 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6013 ++vcpu->stat.hypercalls;
6014 return r;
6015 }
6016 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6017
6018 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6019 {
6020 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6021 char instruction[3];
6022 unsigned long rip = kvm_rip_read(vcpu);
6023
6024 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6025
6026 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
6027 }
6028
6029 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6030 {
6031 return vcpu->run->request_interrupt_window &&
6032 likely(!pic_in_kernel(vcpu->kvm));
6033 }
6034
6035 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6036 {
6037 struct kvm_run *kvm_run = vcpu->run;
6038
6039 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6040 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6041 kvm_run->cr8 = kvm_get_cr8(vcpu);
6042 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6043 kvm_run->ready_for_interrupt_injection =
6044 pic_in_kernel(vcpu->kvm) ||
6045 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6046 }
6047
6048 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6049 {
6050 int max_irr, tpr;
6051
6052 if (!kvm_x86_ops->update_cr8_intercept)
6053 return;
6054
6055 if (!lapic_in_kernel(vcpu))
6056 return;
6057
6058 if (vcpu->arch.apicv_active)
6059 return;
6060
6061 if (!vcpu->arch.apic->vapic_addr)
6062 max_irr = kvm_lapic_find_highest_irr(vcpu);
6063 else
6064 max_irr = -1;
6065
6066 if (max_irr != -1)
6067 max_irr >>= 4;
6068
6069 tpr = kvm_lapic_get_cr8(vcpu);
6070
6071 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6072 }
6073
6074 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6075 {
6076 int r;
6077
6078 /* try to reinject previous events if any */
6079 if (vcpu->arch.exception.pending) {
6080 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6081 vcpu->arch.exception.has_error_code,
6082 vcpu->arch.exception.error_code);
6083
6084 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6085 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6086 X86_EFLAGS_RF);
6087
6088 if (vcpu->arch.exception.nr == DB_VECTOR &&
6089 (vcpu->arch.dr7 & DR7_GD)) {
6090 vcpu->arch.dr7 &= ~DR7_GD;
6091 kvm_update_dr7(vcpu);
6092 }
6093
6094 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6095 vcpu->arch.exception.has_error_code,
6096 vcpu->arch.exception.error_code,
6097 vcpu->arch.exception.reinject);
6098 return 0;
6099 }
6100
6101 if (vcpu->arch.nmi_injected) {
6102 kvm_x86_ops->set_nmi(vcpu);
6103 return 0;
6104 }
6105
6106 if (vcpu->arch.interrupt.pending) {
6107 kvm_x86_ops->set_irq(vcpu);
6108 return 0;
6109 }
6110
6111 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6112 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6113 if (r != 0)
6114 return r;
6115 }
6116
6117 /* try to inject new event if pending */
6118 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6119 vcpu->arch.smi_pending = false;
6120 enter_smm(vcpu);
6121 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6122 --vcpu->arch.nmi_pending;
6123 vcpu->arch.nmi_injected = true;
6124 kvm_x86_ops->set_nmi(vcpu);
6125 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6126 /*
6127 * Because interrupts can be injected asynchronously, we are
6128 * calling check_nested_events again here to avoid a race condition.
6129 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6130 * proposal and current concerns. Perhaps we should be setting
6131 * KVM_REQ_EVENT only on certain events and not unconditionally?
6132 */
6133 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6134 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6135 if (r != 0)
6136 return r;
6137 }
6138 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6139 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6140 false);
6141 kvm_x86_ops->set_irq(vcpu);
6142 }
6143 }
6144
6145 return 0;
6146 }
6147
6148 static void process_nmi(struct kvm_vcpu *vcpu)
6149 {
6150 unsigned limit = 2;
6151
6152 /*
6153 * x86 is limited to one NMI running, and one NMI pending after it.
6154 * If an NMI is already in progress, limit further NMIs to just one.
6155 * Otherwise, allow two (and we'll inject the first one immediately).
6156 */
6157 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6158 limit = 1;
6159
6160 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6161 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6162 kvm_make_request(KVM_REQ_EVENT, vcpu);
6163 }
6164
6165 #define put_smstate(type, buf, offset, val) \
6166 *(type *)((buf) + (offset) - 0x7e00) = val
6167
6168 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6169 {
6170 u32 flags = 0;
6171 flags |= seg->g << 23;
6172 flags |= seg->db << 22;
6173 flags |= seg->l << 21;
6174 flags |= seg->avl << 20;
6175 flags |= seg->present << 15;
6176 flags |= seg->dpl << 13;
6177 flags |= seg->s << 12;
6178 flags |= seg->type << 8;
6179 return flags;
6180 }
6181
6182 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6183 {
6184 struct kvm_segment seg;
6185 int offset;
6186
6187 kvm_get_segment(vcpu, &seg, n);
6188 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6189
6190 if (n < 3)
6191 offset = 0x7f84 + n * 12;
6192 else
6193 offset = 0x7f2c + (n - 3) * 12;
6194
6195 put_smstate(u32, buf, offset + 8, seg.base);
6196 put_smstate(u32, buf, offset + 4, seg.limit);
6197 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6198 }
6199
6200 #ifdef CONFIG_X86_64
6201 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6202 {
6203 struct kvm_segment seg;
6204 int offset;
6205 u16 flags;
6206
6207 kvm_get_segment(vcpu, &seg, n);
6208 offset = 0x7e00 + n * 16;
6209
6210 flags = enter_smm_get_segment_flags(&seg) >> 8;
6211 put_smstate(u16, buf, offset, seg.selector);
6212 put_smstate(u16, buf, offset + 2, flags);
6213 put_smstate(u32, buf, offset + 4, seg.limit);
6214 put_smstate(u64, buf, offset + 8, seg.base);
6215 }
6216 #endif
6217
6218 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6219 {
6220 struct desc_ptr dt;
6221 struct kvm_segment seg;
6222 unsigned long val;
6223 int i;
6224
6225 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6226 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6227 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6228 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6229
6230 for (i = 0; i < 8; i++)
6231 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6232
6233 kvm_get_dr(vcpu, 6, &val);
6234 put_smstate(u32, buf, 0x7fcc, (u32)val);
6235 kvm_get_dr(vcpu, 7, &val);
6236 put_smstate(u32, buf, 0x7fc8, (u32)val);
6237
6238 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6239 put_smstate(u32, buf, 0x7fc4, seg.selector);
6240 put_smstate(u32, buf, 0x7f64, seg.base);
6241 put_smstate(u32, buf, 0x7f60, seg.limit);
6242 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6243
6244 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6245 put_smstate(u32, buf, 0x7fc0, seg.selector);
6246 put_smstate(u32, buf, 0x7f80, seg.base);
6247 put_smstate(u32, buf, 0x7f7c, seg.limit);
6248 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6249
6250 kvm_x86_ops->get_gdt(vcpu, &dt);
6251 put_smstate(u32, buf, 0x7f74, dt.address);
6252 put_smstate(u32, buf, 0x7f70, dt.size);
6253
6254 kvm_x86_ops->get_idt(vcpu, &dt);
6255 put_smstate(u32, buf, 0x7f58, dt.address);
6256 put_smstate(u32, buf, 0x7f54, dt.size);
6257
6258 for (i = 0; i < 6; i++)
6259 enter_smm_save_seg_32(vcpu, buf, i);
6260
6261 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6262
6263 /* revision id */
6264 put_smstate(u32, buf, 0x7efc, 0x00020000);
6265 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6266 }
6267
6268 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6269 {
6270 #ifdef CONFIG_X86_64
6271 struct desc_ptr dt;
6272 struct kvm_segment seg;
6273 unsigned long val;
6274 int i;
6275
6276 for (i = 0; i < 16; i++)
6277 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6278
6279 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6280 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6281
6282 kvm_get_dr(vcpu, 6, &val);
6283 put_smstate(u64, buf, 0x7f68, val);
6284 kvm_get_dr(vcpu, 7, &val);
6285 put_smstate(u64, buf, 0x7f60, val);
6286
6287 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6288 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6289 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6290
6291 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6292
6293 /* revision id */
6294 put_smstate(u32, buf, 0x7efc, 0x00020064);
6295
6296 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6297
6298 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6299 put_smstate(u16, buf, 0x7e90, seg.selector);
6300 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6301 put_smstate(u32, buf, 0x7e94, seg.limit);
6302 put_smstate(u64, buf, 0x7e98, seg.base);
6303
6304 kvm_x86_ops->get_idt(vcpu, &dt);
6305 put_smstate(u32, buf, 0x7e84, dt.size);
6306 put_smstate(u64, buf, 0x7e88, dt.address);
6307
6308 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6309 put_smstate(u16, buf, 0x7e70, seg.selector);
6310 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6311 put_smstate(u32, buf, 0x7e74, seg.limit);
6312 put_smstate(u64, buf, 0x7e78, seg.base);
6313
6314 kvm_x86_ops->get_gdt(vcpu, &dt);
6315 put_smstate(u32, buf, 0x7e64, dt.size);
6316 put_smstate(u64, buf, 0x7e68, dt.address);
6317
6318 for (i = 0; i < 6; i++)
6319 enter_smm_save_seg_64(vcpu, buf, i);
6320 #else
6321 WARN_ON_ONCE(1);
6322 #endif
6323 }
6324
6325 static void enter_smm(struct kvm_vcpu *vcpu)
6326 {
6327 struct kvm_segment cs, ds;
6328 struct desc_ptr dt;
6329 char buf[512];
6330 u32 cr0;
6331
6332 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6333 vcpu->arch.hflags |= HF_SMM_MASK;
6334 memset(buf, 0, 512);
6335 if (guest_cpuid_has_longmode(vcpu))
6336 enter_smm_save_state_64(vcpu, buf);
6337 else
6338 enter_smm_save_state_32(vcpu, buf);
6339
6340 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6341
6342 if (kvm_x86_ops->get_nmi_mask(vcpu))
6343 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6344 else
6345 kvm_x86_ops->set_nmi_mask(vcpu, true);
6346
6347 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6348 kvm_rip_write(vcpu, 0x8000);
6349
6350 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6351 kvm_x86_ops->set_cr0(vcpu, cr0);
6352 vcpu->arch.cr0 = cr0;
6353
6354 kvm_x86_ops->set_cr4(vcpu, 0);
6355
6356 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6357 dt.address = dt.size = 0;
6358 kvm_x86_ops->set_idt(vcpu, &dt);
6359
6360 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6361
6362 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6363 cs.base = vcpu->arch.smbase;
6364
6365 ds.selector = 0;
6366 ds.base = 0;
6367
6368 cs.limit = ds.limit = 0xffffffff;
6369 cs.type = ds.type = 0x3;
6370 cs.dpl = ds.dpl = 0;
6371 cs.db = ds.db = 0;
6372 cs.s = ds.s = 1;
6373 cs.l = ds.l = 0;
6374 cs.g = ds.g = 1;
6375 cs.avl = ds.avl = 0;
6376 cs.present = ds.present = 1;
6377 cs.unusable = ds.unusable = 0;
6378 cs.padding = ds.padding = 0;
6379
6380 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6381 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6382 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6383 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6384 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6385 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6386
6387 if (guest_cpuid_has_longmode(vcpu))
6388 kvm_x86_ops->set_efer(vcpu, 0);
6389
6390 kvm_update_cpuid(vcpu);
6391 kvm_mmu_reset_context(vcpu);
6392 }
6393
6394 static void process_smi(struct kvm_vcpu *vcpu)
6395 {
6396 vcpu->arch.smi_pending = true;
6397 kvm_make_request(KVM_REQ_EVENT, vcpu);
6398 }
6399
6400 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6401 {
6402 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6403 }
6404
6405 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6406 {
6407 u64 eoi_exit_bitmap[4];
6408
6409 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6410 return;
6411
6412 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6413
6414 if (irqchip_split(vcpu->kvm))
6415 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6416 else {
6417 if (vcpu->arch.apicv_active)
6418 kvm_x86_ops->sync_pir_to_irr(vcpu);
6419 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6420 }
6421 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6422 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6423 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6424 }
6425
6426 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6427 {
6428 ++vcpu->stat.tlb_flush;
6429 kvm_x86_ops->tlb_flush(vcpu);
6430 }
6431
6432 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6433 {
6434 struct page *page = NULL;
6435
6436 if (!lapic_in_kernel(vcpu))
6437 return;
6438
6439 if (!kvm_x86_ops->set_apic_access_page_addr)
6440 return;
6441
6442 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6443 if (is_error_page(page))
6444 return;
6445 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6446
6447 /*
6448 * Do not pin apic access page in memory, the MMU notifier
6449 * will call us again if it is migrated or swapped out.
6450 */
6451 put_page(page);
6452 }
6453 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6454
6455 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6456 unsigned long address)
6457 {
6458 /*
6459 * The physical address of apic access page is stored in the VMCS.
6460 * Update it when it becomes invalid.
6461 */
6462 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6463 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6464 }
6465
6466 /*
6467 * Returns 1 to let vcpu_run() continue the guest execution loop without
6468 * exiting to the userspace. Otherwise, the value will be returned to the
6469 * userspace.
6470 */
6471 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6472 {
6473 int r;
6474 bool req_int_win =
6475 dm_request_for_irq_injection(vcpu) &&
6476 kvm_cpu_accept_dm_intr(vcpu);
6477
6478 bool req_immediate_exit = false;
6479
6480 if (vcpu->requests) {
6481 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6482 kvm_mmu_unload(vcpu);
6483 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6484 __kvm_migrate_timers(vcpu);
6485 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6486 kvm_gen_update_masterclock(vcpu->kvm);
6487 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6488 kvm_gen_kvmclock_update(vcpu);
6489 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6490 r = kvm_guest_time_update(vcpu);
6491 if (unlikely(r))
6492 goto out;
6493 }
6494 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6495 kvm_mmu_sync_roots(vcpu);
6496 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6497 kvm_vcpu_flush_tlb(vcpu);
6498 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6499 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6500 r = 0;
6501 goto out;
6502 }
6503 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6504 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6505 r = 0;
6506 goto out;
6507 }
6508 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6509 vcpu->fpu_active = 0;
6510 kvm_x86_ops->fpu_deactivate(vcpu);
6511 }
6512 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6513 /* Page is swapped out. Do synthetic halt */
6514 vcpu->arch.apf.halted = true;
6515 r = 1;
6516 goto out;
6517 }
6518 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6519 record_steal_time(vcpu);
6520 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6521 process_smi(vcpu);
6522 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6523 process_nmi(vcpu);
6524 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6525 kvm_pmu_handle_event(vcpu);
6526 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6527 kvm_pmu_deliver_pmi(vcpu);
6528 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6529 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6530 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6531 vcpu->arch.ioapic_handled_vectors)) {
6532 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6533 vcpu->run->eoi.vector =
6534 vcpu->arch.pending_ioapic_eoi;
6535 r = 0;
6536 goto out;
6537 }
6538 }
6539 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6540 vcpu_scan_ioapic(vcpu);
6541 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6542 kvm_vcpu_reload_apic_access_page(vcpu);
6543 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6544 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6545 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6546 r = 0;
6547 goto out;
6548 }
6549 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6550 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6551 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6552 r = 0;
6553 goto out;
6554 }
6555 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6556 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6557 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6558 r = 0;
6559 goto out;
6560 }
6561
6562 /*
6563 * KVM_REQ_HV_STIMER has to be processed after
6564 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6565 * depend on the guest clock being up-to-date
6566 */
6567 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6568 kvm_hv_process_stimers(vcpu);
6569 }
6570
6571 /*
6572 * KVM_REQ_EVENT is not set when posted interrupts are set by
6573 * VT-d hardware, so we have to update RVI unconditionally.
6574 */
6575 if (kvm_lapic_enabled(vcpu)) {
6576 /*
6577 * Update architecture specific hints for APIC
6578 * virtual interrupt delivery.
6579 */
6580 if (vcpu->arch.apicv_active)
6581 kvm_x86_ops->hwapic_irr_update(vcpu,
6582 kvm_lapic_find_highest_irr(vcpu));
6583 }
6584
6585 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6586 kvm_apic_accept_events(vcpu);
6587 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6588 r = 1;
6589 goto out;
6590 }
6591
6592 if (inject_pending_event(vcpu, req_int_win) != 0)
6593 req_immediate_exit = true;
6594 else {
6595 /* Enable NMI/IRQ window open exits if needed.
6596 *
6597 * SMIs have two cases: 1) they can be nested, and
6598 * then there is nothing to do here because RSM will
6599 * cause a vmexit anyway; 2) or the SMI can be pending
6600 * because inject_pending_event has completed the
6601 * injection of an IRQ or NMI from the previous vmexit,
6602 * and then we request an immediate exit to inject the SMI.
6603 */
6604 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6605 req_immediate_exit = true;
6606 if (vcpu->arch.nmi_pending)
6607 kvm_x86_ops->enable_nmi_window(vcpu);
6608 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6609 kvm_x86_ops->enable_irq_window(vcpu);
6610 }
6611
6612 if (kvm_lapic_enabled(vcpu)) {
6613 update_cr8_intercept(vcpu);
6614 kvm_lapic_sync_to_vapic(vcpu);
6615 }
6616 }
6617
6618 r = kvm_mmu_reload(vcpu);
6619 if (unlikely(r)) {
6620 goto cancel_injection;
6621 }
6622
6623 preempt_disable();
6624
6625 kvm_x86_ops->prepare_guest_switch(vcpu);
6626 if (vcpu->fpu_active)
6627 kvm_load_guest_fpu(vcpu);
6628 vcpu->mode = IN_GUEST_MODE;
6629
6630 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6631
6632 /*
6633 * We should set ->mode before check ->requests,
6634 * Please see the comment in kvm_make_all_cpus_request.
6635 * This also orders the write to mode from any reads
6636 * to the page tables done while the VCPU is running.
6637 * Please see the comment in kvm_flush_remote_tlbs.
6638 */
6639 smp_mb__after_srcu_read_unlock();
6640
6641 local_irq_disable();
6642
6643 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6644 || need_resched() || signal_pending(current)) {
6645 vcpu->mode = OUTSIDE_GUEST_MODE;
6646 smp_wmb();
6647 local_irq_enable();
6648 preempt_enable();
6649 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6650 r = 1;
6651 goto cancel_injection;
6652 }
6653
6654 kvm_load_guest_xcr0(vcpu);
6655
6656 if (req_immediate_exit) {
6657 kvm_make_request(KVM_REQ_EVENT, vcpu);
6658 smp_send_reschedule(vcpu->cpu);
6659 }
6660
6661 trace_kvm_entry(vcpu->vcpu_id);
6662 wait_lapic_expire(vcpu);
6663 guest_enter_irqoff();
6664
6665 if (unlikely(vcpu->arch.switch_db_regs)) {
6666 set_debugreg(0, 7);
6667 set_debugreg(vcpu->arch.eff_db[0], 0);
6668 set_debugreg(vcpu->arch.eff_db[1], 1);
6669 set_debugreg(vcpu->arch.eff_db[2], 2);
6670 set_debugreg(vcpu->arch.eff_db[3], 3);
6671 set_debugreg(vcpu->arch.dr6, 6);
6672 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6673 }
6674
6675 kvm_x86_ops->run(vcpu);
6676
6677 /*
6678 * Do this here before restoring debug registers on the host. And
6679 * since we do this before handling the vmexit, a DR access vmexit
6680 * can (a) read the correct value of the debug registers, (b) set
6681 * KVM_DEBUGREG_WONT_EXIT again.
6682 */
6683 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6684 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6685 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6686 kvm_update_dr0123(vcpu);
6687 kvm_update_dr6(vcpu);
6688 kvm_update_dr7(vcpu);
6689 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6690 }
6691
6692 /*
6693 * If the guest has used debug registers, at least dr7
6694 * will be disabled while returning to the host.
6695 * If we don't have active breakpoints in the host, we don't
6696 * care about the messed up debug address registers. But if
6697 * we have some of them active, restore the old state.
6698 */
6699 if (hw_breakpoint_active())
6700 hw_breakpoint_restore();
6701
6702 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6703
6704 vcpu->mode = OUTSIDE_GUEST_MODE;
6705 smp_wmb();
6706
6707 kvm_put_guest_xcr0(vcpu);
6708
6709 /* Interrupt is enabled by handle_external_intr() */
6710 kvm_x86_ops->handle_external_intr(vcpu);
6711
6712 ++vcpu->stat.exits;
6713
6714 guest_exit_irqoff();
6715
6716 local_irq_enable();
6717 preempt_enable();
6718
6719 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6720
6721 /*
6722 * Profile KVM exit RIPs:
6723 */
6724 if (unlikely(prof_on == KVM_PROFILING)) {
6725 unsigned long rip = kvm_rip_read(vcpu);
6726 profile_hit(KVM_PROFILING, (void *)rip);
6727 }
6728
6729 if (unlikely(vcpu->arch.tsc_always_catchup))
6730 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6731
6732 if (vcpu->arch.apic_attention)
6733 kvm_lapic_sync_from_vapic(vcpu);
6734
6735 r = kvm_x86_ops->handle_exit(vcpu);
6736 return r;
6737
6738 cancel_injection:
6739 kvm_x86_ops->cancel_injection(vcpu);
6740 if (unlikely(vcpu->arch.apic_attention))
6741 kvm_lapic_sync_from_vapic(vcpu);
6742 out:
6743 return r;
6744 }
6745
6746 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6747 {
6748 if (!kvm_arch_vcpu_runnable(vcpu) &&
6749 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6750 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6751 kvm_vcpu_block(vcpu);
6752 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6753
6754 if (kvm_x86_ops->post_block)
6755 kvm_x86_ops->post_block(vcpu);
6756
6757 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6758 return 1;
6759 }
6760
6761 kvm_apic_accept_events(vcpu);
6762 switch(vcpu->arch.mp_state) {
6763 case KVM_MP_STATE_HALTED:
6764 vcpu->arch.pv.pv_unhalted = false;
6765 vcpu->arch.mp_state =
6766 KVM_MP_STATE_RUNNABLE;
6767 case KVM_MP_STATE_RUNNABLE:
6768 vcpu->arch.apf.halted = false;
6769 break;
6770 case KVM_MP_STATE_INIT_RECEIVED:
6771 break;
6772 default:
6773 return -EINTR;
6774 break;
6775 }
6776 return 1;
6777 }
6778
6779 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6780 {
6781 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6782 !vcpu->arch.apf.halted);
6783 }
6784
6785 static int vcpu_run(struct kvm_vcpu *vcpu)
6786 {
6787 int r;
6788 struct kvm *kvm = vcpu->kvm;
6789
6790 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6791
6792 for (;;) {
6793 if (kvm_vcpu_running(vcpu)) {
6794 r = vcpu_enter_guest(vcpu);
6795 } else {
6796 r = vcpu_block(kvm, vcpu);
6797 }
6798
6799 if (r <= 0)
6800 break;
6801
6802 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6803 if (kvm_cpu_has_pending_timer(vcpu))
6804 kvm_inject_pending_timer_irqs(vcpu);
6805
6806 if (dm_request_for_irq_injection(vcpu) &&
6807 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6808 r = 0;
6809 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6810 ++vcpu->stat.request_irq_exits;
6811 break;
6812 }
6813
6814 kvm_check_async_pf_completion(vcpu);
6815
6816 if (signal_pending(current)) {
6817 r = -EINTR;
6818 vcpu->run->exit_reason = KVM_EXIT_INTR;
6819 ++vcpu->stat.signal_exits;
6820 break;
6821 }
6822 if (need_resched()) {
6823 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6824 cond_resched();
6825 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6826 }
6827 }
6828
6829 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6830
6831 return r;
6832 }
6833
6834 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6835 {
6836 int r;
6837 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6838 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6839 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6840 if (r != EMULATE_DONE)
6841 return 0;
6842 return 1;
6843 }
6844
6845 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6846 {
6847 BUG_ON(!vcpu->arch.pio.count);
6848
6849 return complete_emulated_io(vcpu);
6850 }
6851
6852 /*
6853 * Implements the following, as a state machine:
6854 *
6855 * read:
6856 * for each fragment
6857 * for each mmio piece in the fragment
6858 * write gpa, len
6859 * exit
6860 * copy data
6861 * execute insn
6862 *
6863 * write:
6864 * for each fragment
6865 * for each mmio piece in the fragment
6866 * write gpa, len
6867 * copy data
6868 * exit
6869 */
6870 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6871 {
6872 struct kvm_run *run = vcpu->run;
6873 struct kvm_mmio_fragment *frag;
6874 unsigned len;
6875
6876 BUG_ON(!vcpu->mmio_needed);
6877
6878 /* Complete previous fragment */
6879 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6880 len = min(8u, frag->len);
6881 if (!vcpu->mmio_is_write)
6882 memcpy(frag->data, run->mmio.data, len);
6883
6884 if (frag->len <= 8) {
6885 /* Switch to the next fragment. */
6886 frag++;
6887 vcpu->mmio_cur_fragment++;
6888 } else {
6889 /* Go forward to the next mmio piece. */
6890 frag->data += len;
6891 frag->gpa += len;
6892 frag->len -= len;
6893 }
6894
6895 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6896 vcpu->mmio_needed = 0;
6897
6898 /* FIXME: return into emulator if single-stepping. */
6899 if (vcpu->mmio_is_write)
6900 return 1;
6901 vcpu->mmio_read_completed = 1;
6902 return complete_emulated_io(vcpu);
6903 }
6904
6905 run->exit_reason = KVM_EXIT_MMIO;
6906 run->mmio.phys_addr = frag->gpa;
6907 if (vcpu->mmio_is_write)
6908 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6909 run->mmio.len = min(8u, frag->len);
6910 run->mmio.is_write = vcpu->mmio_is_write;
6911 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6912 return 0;
6913 }
6914
6915
6916 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6917 {
6918 struct fpu *fpu = &current->thread.fpu;
6919 int r;
6920 sigset_t sigsaved;
6921
6922 fpu__activate_curr(fpu);
6923
6924 if (vcpu->sigset_active)
6925 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6926
6927 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6928 kvm_vcpu_block(vcpu);
6929 kvm_apic_accept_events(vcpu);
6930 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6931 r = -EAGAIN;
6932 goto out;
6933 }
6934
6935 /* re-sync apic's tpr */
6936 if (!lapic_in_kernel(vcpu)) {
6937 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6938 r = -EINVAL;
6939 goto out;
6940 }
6941 }
6942
6943 if (unlikely(vcpu->arch.complete_userspace_io)) {
6944 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6945 vcpu->arch.complete_userspace_io = NULL;
6946 r = cui(vcpu);
6947 if (r <= 0)
6948 goto out;
6949 } else
6950 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6951
6952 r = vcpu_run(vcpu);
6953
6954 out:
6955 post_kvm_run_save(vcpu);
6956 if (vcpu->sigset_active)
6957 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6958
6959 return r;
6960 }
6961
6962 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6963 {
6964 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6965 /*
6966 * We are here if userspace calls get_regs() in the middle of
6967 * instruction emulation. Registers state needs to be copied
6968 * back from emulation context to vcpu. Userspace shouldn't do
6969 * that usually, but some bad designed PV devices (vmware
6970 * backdoor interface) need this to work
6971 */
6972 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6973 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6974 }
6975 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6976 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6977 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6978 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6979 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6980 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6981 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6982 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6983 #ifdef CONFIG_X86_64
6984 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6985 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6986 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6987 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6988 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6989 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6990 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6991 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6992 #endif
6993
6994 regs->rip = kvm_rip_read(vcpu);
6995 regs->rflags = kvm_get_rflags(vcpu);
6996
6997 return 0;
6998 }
6999
7000 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7001 {
7002 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7003 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7004
7005 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7006 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7007 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7008 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7009 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7010 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7011 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7012 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7013 #ifdef CONFIG_X86_64
7014 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7015 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7016 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7017 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7018 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7019 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7020 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7021 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7022 #endif
7023
7024 kvm_rip_write(vcpu, regs->rip);
7025 kvm_set_rflags(vcpu, regs->rflags);
7026
7027 vcpu->arch.exception.pending = false;
7028
7029 kvm_make_request(KVM_REQ_EVENT, vcpu);
7030
7031 return 0;
7032 }
7033
7034 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7035 {
7036 struct kvm_segment cs;
7037
7038 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7039 *db = cs.db;
7040 *l = cs.l;
7041 }
7042 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7043
7044 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7045 struct kvm_sregs *sregs)
7046 {
7047 struct desc_ptr dt;
7048
7049 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7050 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7051 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7052 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7053 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7054 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7055
7056 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7057 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7058
7059 kvm_x86_ops->get_idt(vcpu, &dt);
7060 sregs->idt.limit = dt.size;
7061 sregs->idt.base = dt.address;
7062 kvm_x86_ops->get_gdt(vcpu, &dt);
7063 sregs->gdt.limit = dt.size;
7064 sregs->gdt.base = dt.address;
7065
7066 sregs->cr0 = kvm_read_cr0(vcpu);
7067 sregs->cr2 = vcpu->arch.cr2;
7068 sregs->cr3 = kvm_read_cr3(vcpu);
7069 sregs->cr4 = kvm_read_cr4(vcpu);
7070 sregs->cr8 = kvm_get_cr8(vcpu);
7071 sregs->efer = vcpu->arch.efer;
7072 sregs->apic_base = kvm_get_apic_base(vcpu);
7073
7074 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7075
7076 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7077 set_bit(vcpu->arch.interrupt.nr,
7078 (unsigned long *)sregs->interrupt_bitmap);
7079
7080 return 0;
7081 }
7082
7083 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7084 struct kvm_mp_state *mp_state)
7085 {
7086 kvm_apic_accept_events(vcpu);
7087 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7088 vcpu->arch.pv.pv_unhalted)
7089 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7090 else
7091 mp_state->mp_state = vcpu->arch.mp_state;
7092
7093 return 0;
7094 }
7095
7096 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7097 struct kvm_mp_state *mp_state)
7098 {
7099 if (!lapic_in_kernel(vcpu) &&
7100 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7101 return -EINVAL;
7102
7103 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7104 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7105 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7106 } else
7107 vcpu->arch.mp_state = mp_state->mp_state;
7108 kvm_make_request(KVM_REQ_EVENT, vcpu);
7109 return 0;
7110 }
7111
7112 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7113 int reason, bool has_error_code, u32 error_code)
7114 {
7115 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7116 int ret;
7117
7118 init_emulate_ctxt(vcpu);
7119
7120 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7121 has_error_code, error_code);
7122
7123 if (ret)
7124 return EMULATE_FAIL;
7125
7126 kvm_rip_write(vcpu, ctxt->eip);
7127 kvm_set_rflags(vcpu, ctxt->eflags);
7128 kvm_make_request(KVM_REQ_EVENT, vcpu);
7129 return EMULATE_DONE;
7130 }
7131 EXPORT_SYMBOL_GPL(kvm_task_switch);
7132
7133 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7134 struct kvm_sregs *sregs)
7135 {
7136 struct msr_data apic_base_msr;
7137 int mmu_reset_needed = 0;
7138 int pending_vec, max_bits, idx;
7139 struct desc_ptr dt;
7140
7141 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7142 return -EINVAL;
7143
7144 dt.size = sregs->idt.limit;
7145 dt.address = sregs->idt.base;
7146 kvm_x86_ops->set_idt(vcpu, &dt);
7147 dt.size = sregs->gdt.limit;
7148 dt.address = sregs->gdt.base;
7149 kvm_x86_ops->set_gdt(vcpu, &dt);
7150
7151 vcpu->arch.cr2 = sregs->cr2;
7152 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7153 vcpu->arch.cr3 = sregs->cr3;
7154 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7155
7156 kvm_set_cr8(vcpu, sregs->cr8);
7157
7158 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7159 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7160 apic_base_msr.data = sregs->apic_base;
7161 apic_base_msr.host_initiated = true;
7162 kvm_set_apic_base(vcpu, &apic_base_msr);
7163
7164 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7165 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7166 vcpu->arch.cr0 = sregs->cr0;
7167
7168 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7169 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7170 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7171 kvm_update_cpuid(vcpu);
7172
7173 idx = srcu_read_lock(&vcpu->kvm->srcu);
7174 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7175 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7176 mmu_reset_needed = 1;
7177 }
7178 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7179
7180 if (mmu_reset_needed)
7181 kvm_mmu_reset_context(vcpu);
7182
7183 max_bits = KVM_NR_INTERRUPTS;
7184 pending_vec = find_first_bit(
7185 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7186 if (pending_vec < max_bits) {
7187 kvm_queue_interrupt(vcpu, pending_vec, false);
7188 pr_debug("Set back pending irq %d\n", pending_vec);
7189 }
7190
7191 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7192 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7193 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7194 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7195 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7196 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7197
7198 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7199 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7200
7201 update_cr8_intercept(vcpu);
7202
7203 /* Older userspace won't unhalt the vcpu on reset. */
7204 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7205 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7206 !is_protmode(vcpu))
7207 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7208
7209 kvm_make_request(KVM_REQ_EVENT, vcpu);
7210
7211 return 0;
7212 }
7213
7214 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7215 struct kvm_guest_debug *dbg)
7216 {
7217 unsigned long rflags;
7218 int i, r;
7219
7220 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7221 r = -EBUSY;
7222 if (vcpu->arch.exception.pending)
7223 goto out;
7224 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7225 kvm_queue_exception(vcpu, DB_VECTOR);
7226 else
7227 kvm_queue_exception(vcpu, BP_VECTOR);
7228 }
7229
7230 /*
7231 * Read rflags as long as potentially injected trace flags are still
7232 * filtered out.
7233 */
7234 rflags = kvm_get_rflags(vcpu);
7235
7236 vcpu->guest_debug = dbg->control;
7237 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7238 vcpu->guest_debug = 0;
7239
7240 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7241 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7242 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7243 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7244 } else {
7245 for (i = 0; i < KVM_NR_DB_REGS; i++)
7246 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7247 }
7248 kvm_update_dr7(vcpu);
7249
7250 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7251 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7252 get_segment_base(vcpu, VCPU_SREG_CS);
7253
7254 /*
7255 * Trigger an rflags update that will inject or remove the trace
7256 * flags.
7257 */
7258 kvm_set_rflags(vcpu, rflags);
7259
7260 kvm_x86_ops->update_bp_intercept(vcpu);
7261
7262 r = 0;
7263
7264 out:
7265
7266 return r;
7267 }
7268
7269 /*
7270 * Translate a guest virtual address to a guest physical address.
7271 */
7272 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7273 struct kvm_translation *tr)
7274 {
7275 unsigned long vaddr = tr->linear_address;
7276 gpa_t gpa;
7277 int idx;
7278
7279 idx = srcu_read_lock(&vcpu->kvm->srcu);
7280 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7281 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7282 tr->physical_address = gpa;
7283 tr->valid = gpa != UNMAPPED_GVA;
7284 tr->writeable = 1;
7285 tr->usermode = 0;
7286
7287 return 0;
7288 }
7289
7290 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7291 {
7292 struct fxregs_state *fxsave =
7293 &vcpu->arch.guest_fpu.state.fxsave;
7294
7295 memcpy(fpu->fpr, fxsave->st_space, 128);
7296 fpu->fcw = fxsave->cwd;
7297 fpu->fsw = fxsave->swd;
7298 fpu->ftwx = fxsave->twd;
7299 fpu->last_opcode = fxsave->fop;
7300 fpu->last_ip = fxsave->rip;
7301 fpu->last_dp = fxsave->rdp;
7302 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7303
7304 return 0;
7305 }
7306
7307 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7308 {
7309 struct fxregs_state *fxsave =
7310 &vcpu->arch.guest_fpu.state.fxsave;
7311
7312 memcpy(fxsave->st_space, fpu->fpr, 128);
7313 fxsave->cwd = fpu->fcw;
7314 fxsave->swd = fpu->fsw;
7315 fxsave->twd = fpu->ftwx;
7316 fxsave->fop = fpu->last_opcode;
7317 fxsave->rip = fpu->last_ip;
7318 fxsave->rdp = fpu->last_dp;
7319 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7320
7321 return 0;
7322 }
7323
7324 static void fx_init(struct kvm_vcpu *vcpu)
7325 {
7326 fpstate_init(&vcpu->arch.guest_fpu.state);
7327 if (boot_cpu_has(X86_FEATURE_XSAVES))
7328 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7329 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7330
7331 /*
7332 * Ensure guest xcr0 is valid for loading
7333 */
7334 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7335
7336 vcpu->arch.cr0 |= X86_CR0_ET;
7337 }
7338
7339 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7340 {
7341 if (vcpu->guest_fpu_loaded)
7342 return;
7343
7344 /*
7345 * Restore all possible states in the guest,
7346 * and assume host would use all available bits.
7347 * Guest xcr0 would be loaded later.
7348 */
7349 vcpu->guest_fpu_loaded = 1;
7350 __kernel_fpu_begin();
7351 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7352 trace_kvm_fpu(1);
7353 }
7354
7355 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7356 {
7357 if (!vcpu->guest_fpu_loaded) {
7358 vcpu->fpu_counter = 0;
7359 return;
7360 }
7361
7362 vcpu->guest_fpu_loaded = 0;
7363 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7364 __kernel_fpu_end();
7365 ++vcpu->stat.fpu_reload;
7366 /*
7367 * If using eager FPU mode, or if the guest is a frequent user
7368 * of the FPU, just leave the FPU active for next time.
7369 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7370 * the FPU in bursts will revert to loading it on demand.
7371 */
7372 if (!use_eager_fpu()) {
7373 if (++vcpu->fpu_counter < 5)
7374 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7375 }
7376 trace_kvm_fpu(0);
7377 }
7378
7379 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7380 {
7381 kvmclock_reset(vcpu);
7382
7383 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7384 kvm_x86_ops->vcpu_free(vcpu);
7385 }
7386
7387 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7388 unsigned int id)
7389 {
7390 struct kvm_vcpu *vcpu;
7391
7392 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7393 printk_once(KERN_WARNING
7394 "kvm: SMP vm created on host with unstable TSC; "
7395 "guest TSC will not be reliable\n");
7396
7397 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7398
7399 return vcpu;
7400 }
7401
7402 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7403 {
7404 int r;
7405
7406 kvm_vcpu_mtrr_init(vcpu);
7407 r = vcpu_load(vcpu);
7408 if (r)
7409 return r;
7410 kvm_vcpu_reset(vcpu, false);
7411 kvm_mmu_setup(vcpu);
7412 vcpu_put(vcpu);
7413 return r;
7414 }
7415
7416 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7417 {
7418 struct msr_data msr;
7419 struct kvm *kvm = vcpu->kvm;
7420
7421 if (vcpu_load(vcpu))
7422 return;
7423 msr.data = 0x0;
7424 msr.index = MSR_IA32_TSC;
7425 msr.host_initiated = true;
7426 kvm_write_tsc(vcpu, &msr);
7427 vcpu_put(vcpu);
7428
7429 if (!kvmclock_periodic_sync)
7430 return;
7431
7432 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7433 KVMCLOCK_SYNC_PERIOD);
7434 }
7435
7436 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7437 {
7438 int r;
7439 vcpu->arch.apf.msr_val = 0;
7440
7441 r = vcpu_load(vcpu);
7442 BUG_ON(r);
7443 kvm_mmu_unload(vcpu);
7444 vcpu_put(vcpu);
7445
7446 kvm_x86_ops->vcpu_free(vcpu);
7447 }
7448
7449 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7450 {
7451 vcpu->arch.hflags = 0;
7452
7453 vcpu->arch.smi_pending = 0;
7454 atomic_set(&vcpu->arch.nmi_queued, 0);
7455 vcpu->arch.nmi_pending = 0;
7456 vcpu->arch.nmi_injected = false;
7457 kvm_clear_interrupt_queue(vcpu);
7458 kvm_clear_exception_queue(vcpu);
7459
7460 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7461 kvm_update_dr0123(vcpu);
7462 vcpu->arch.dr6 = DR6_INIT;
7463 kvm_update_dr6(vcpu);
7464 vcpu->arch.dr7 = DR7_FIXED_1;
7465 kvm_update_dr7(vcpu);
7466
7467 vcpu->arch.cr2 = 0;
7468
7469 kvm_make_request(KVM_REQ_EVENT, vcpu);
7470 vcpu->arch.apf.msr_val = 0;
7471 vcpu->arch.st.msr_val = 0;
7472
7473 kvmclock_reset(vcpu);
7474
7475 kvm_clear_async_pf_completion_queue(vcpu);
7476 kvm_async_pf_hash_reset(vcpu);
7477 vcpu->arch.apf.halted = false;
7478
7479 if (!init_event) {
7480 kvm_pmu_reset(vcpu);
7481 vcpu->arch.smbase = 0x30000;
7482 }
7483
7484 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7485 vcpu->arch.regs_avail = ~0;
7486 vcpu->arch.regs_dirty = ~0;
7487
7488 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7489 }
7490
7491 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7492 {
7493 struct kvm_segment cs;
7494
7495 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7496 cs.selector = vector << 8;
7497 cs.base = vector << 12;
7498 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7499 kvm_rip_write(vcpu, 0);
7500 }
7501
7502 int kvm_arch_hardware_enable(void)
7503 {
7504 struct kvm *kvm;
7505 struct kvm_vcpu *vcpu;
7506 int i;
7507 int ret;
7508 u64 local_tsc;
7509 u64 max_tsc = 0;
7510 bool stable, backwards_tsc = false;
7511
7512 kvm_shared_msr_cpu_online();
7513 ret = kvm_x86_ops->hardware_enable();
7514 if (ret != 0)
7515 return ret;
7516
7517 local_tsc = rdtsc();
7518 stable = !check_tsc_unstable();
7519 list_for_each_entry(kvm, &vm_list, vm_list) {
7520 kvm_for_each_vcpu(i, vcpu, kvm) {
7521 if (!stable && vcpu->cpu == smp_processor_id())
7522 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7523 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7524 backwards_tsc = true;
7525 if (vcpu->arch.last_host_tsc > max_tsc)
7526 max_tsc = vcpu->arch.last_host_tsc;
7527 }
7528 }
7529 }
7530
7531 /*
7532 * Sometimes, even reliable TSCs go backwards. This happens on
7533 * platforms that reset TSC during suspend or hibernate actions, but
7534 * maintain synchronization. We must compensate. Fortunately, we can
7535 * detect that condition here, which happens early in CPU bringup,
7536 * before any KVM threads can be running. Unfortunately, we can't
7537 * bring the TSCs fully up to date with real time, as we aren't yet far
7538 * enough into CPU bringup that we know how much real time has actually
7539 * elapsed; our helper function, get_kernel_ns() will be using boot
7540 * variables that haven't been updated yet.
7541 *
7542 * So we simply find the maximum observed TSC above, then record the
7543 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7544 * the adjustment will be applied. Note that we accumulate
7545 * adjustments, in case multiple suspend cycles happen before some VCPU
7546 * gets a chance to run again. In the event that no KVM threads get a
7547 * chance to run, we will miss the entire elapsed period, as we'll have
7548 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7549 * loose cycle time. This isn't too big a deal, since the loss will be
7550 * uniform across all VCPUs (not to mention the scenario is extremely
7551 * unlikely). It is possible that a second hibernate recovery happens
7552 * much faster than a first, causing the observed TSC here to be
7553 * smaller; this would require additional padding adjustment, which is
7554 * why we set last_host_tsc to the local tsc observed here.
7555 *
7556 * N.B. - this code below runs only on platforms with reliable TSC,
7557 * as that is the only way backwards_tsc is set above. Also note
7558 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7559 * have the same delta_cyc adjustment applied if backwards_tsc
7560 * is detected. Note further, this adjustment is only done once,
7561 * as we reset last_host_tsc on all VCPUs to stop this from being
7562 * called multiple times (one for each physical CPU bringup).
7563 *
7564 * Platforms with unreliable TSCs don't have to deal with this, they
7565 * will be compensated by the logic in vcpu_load, which sets the TSC to
7566 * catchup mode. This will catchup all VCPUs to real time, but cannot
7567 * guarantee that they stay in perfect synchronization.
7568 */
7569 if (backwards_tsc) {
7570 u64 delta_cyc = max_tsc - local_tsc;
7571 backwards_tsc_observed = true;
7572 list_for_each_entry(kvm, &vm_list, vm_list) {
7573 kvm_for_each_vcpu(i, vcpu, kvm) {
7574 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7575 vcpu->arch.last_host_tsc = local_tsc;
7576 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7577 }
7578
7579 /*
7580 * We have to disable TSC offset matching.. if you were
7581 * booting a VM while issuing an S4 host suspend....
7582 * you may have some problem. Solving this issue is
7583 * left as an exercise to the reader.
7584 */
7585 kvm->arch.last_tsc_nsec = 0;
7586 kvm->arch.last_tsc_write = 0;
7587 }
7588
7589 }
7590 return 0;
7591 }
7592
7593 void kvm_arch_hardware_disable(void)
7594 {
7595 kvm_x86_ops->hardware_disable();
7596 drop_user_return_notifiers();
7597 }
7598
7599 int kvm_arch_hardware_setup(void)
7600 {
7601 int r;
7602
7603 r = kvm_x86_ops->hardware_setup();
7604 if (r != 0)
7605 return r;
7606
7607 if (kvm_has_tsc_control) {
7608 /*
7609 * Make sure the user can only configure tsc_khz values that
7610 * fit into a signed integer.
7611 * A min value is not calculated needed because it will always
7612 * be 1 on all machines.
7613 */
7614 u64 max = min(0x7fffffffULL,
7615 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7616 kvm_max_guest_tsc_khz = max;
7617
7618 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7619 }
7620
7621 kvm_init_msr_list();
7622 return 0;
7623 }
7624
7625 void kvm_arch_hardware_unsetup(void)
7626 {
7627 kvm_x86_ops->hardware_unsetup();
7628 }
7629
7630 void kvm_arch_check_processor_compat(void *rtn)
7631 {
7632 kvm_x86_ops->check_processor_compatibility(rtn);
7633 }
7634
7635 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7636 {
7637 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7638 }
7639 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7640
7641 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7642 {
7643 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7644 }
7645
7646 struct static_key kvm_no_apic_vcpu __read_mostly;
7647 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7648
7649 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7650 {
7651 struct page *page;
7652 struct kvm *kvm;
7653 int r;
7654
7655 BUG_ON(vcpu->kvm == NULL);
7656 kvm = vcpu->kvm;
7657
7658 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7659 vcpu->arch.pv.pv_unhalted = false;
7660 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7661 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7662 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7663 else
7664 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7665
7666 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7667 if (!page) {
7668 r = -ENOMEM;
7669 goto fail;
7670 }
7671 vcpu->arch.pio_data = page_address(page);
7672
7673 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7674
7675 r = kvm_mmu_create(vcpu);
7676 if (r < 0)
7677 goto fail_free_pio_data;
7678
7679 if (irqchip_in_kernel(kvm)) {
7680 r = kvm_create_lapic(vcpu);
7681 if (r < 0)
7682 goto fail_mmu_destroy;
7683 } else
7684 static_key_slow_inc(&kvm_no_apic_vcpu);
7685
7686 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7687 GFP_KERNEL);
7688 if (!vcpu->arch.mce_banks) {
7689 r = -ENOMEM;
7690 goto fail_free_lapic;
7691 }
7692 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7693
7694 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7695 r = -ENOMEM;
7696 goto fail_free_mce_banks;
7697 }
7698
7699 fx_init(vcpu);
7700
7701 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7702 vcpu->arch.pv_time_enabled = false;
7703
7704 vcpu->arch.guest_supported_xcr0 = 0;
7705 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7706
7707 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7708
7709 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7710
7711 kvm_async_pf_hash_reset(vcpu);
7712 kvm_pmu_init(vcpu);
7713
7714 vcpu->arch.pending_external_vector = -1;
7715
7716 kvm_hv_vcpu_init(vcpu);
7717
7718 return 0;
7719
7720 fail_free_mce_banks:
7721 kfree(vcpu->arch.mce_banks);
7722 fail_free_lapic:
7723 kvm_free_lapic(vcpu);
7724 fail_mmu_destroy:
7725 kvm_mmu_destroy(vcpu);
7726 fail_free_pio_data:
7727 free_page((unsigned long)vcpu->arch.pio_data);
7728 fail:
7729 return r;
7730 }
7731
7732 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7733 {
7734 int idx;
7735
7736 kvm_hv_vcpu_uninit(vcpu);
7737 kvm_pmu_destroy(vcpu);
7738 kfree(vcpu->arch.mce_banks);
7739 kvm_free_lapic(vcpu);
7740 idx = srcu_read_lock(&vcpu->kvm->srcu);
7741 kvm_mmu_destroy(vcpu);
7742 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7743 free_page((unsigned long)vcpu->arch.pio_data);
7744 if (!lapic_in_kernel(vcpu))
7745 static_key_slow_dec(&kvm_no_apic_vcpu);
7746 }
7747
7748 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7749 {
7750 kvm_x86_ops->sched_in(vcpu, cpu);
7751 }
7752
7753 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7754 {
7755 if (type)
7756 return -EINVAL;
7757
7758 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7759 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7760 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7761 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7762 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7763
7764 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7765 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7766 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7767 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7768 &kvm->arch.irq_sources_bitmap);
7769
7770 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7771 mutex_init(&kvm->arch.apic_map_lock);
7772 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7773
7774 pvclock_update_vm_gtod_copy(kvm);
7775
7776 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7777 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7778
7779 kvm_page_track_init(kvm);
7780 kvm_mmu_init_vm(kvm);
7781
7782 if (kvm_x86_ops->vm_init)
7783 return kvm_x86_ops->vm_init(kvm);
7784
7785 return 0;
7786 }
7787
7788 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7789 {
7790 int r;
7791 r = vcpu_load(vcpu);
7792 BUG_ON(r);
7793 kvm_mmu_unload(vcpu);
7794 vcpu_put(vcpu);
7795 }
7796
7797 static void kvm_free_vcpus(struct kvm *kvm)
7798 {
7799 unsigned int i;
7800 struct kvm_vcpu *vcpu;
7801
7802 /*
7803 * Unpin any mmu pages first.
7804 */
7805 kvm_for_each_vcpu(i, vcpu, kvm) {
7806 kvm_clear_async_pf_completion_queue(vcpu);
7807 kvm_unload_vcpu_mmu(vcpu);
7808 }
7809 kvm_for_each_vcpu(i, vcpu, kvm)
7810 kvm_arch_vcpu_free(vcpu);
7811
7812 mutex_lock(&kvm->lock);
7813 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7814 kvm->vcpus[i] = NULL;
7815
7816 atomic_set(&kvm->online_vcpus, 0);
7817 mutex_unlock(&kvm->lock);
7818 }
7819
7820 void kvm_arch_sync_events(struct kvm *kvm)
7821 {
7822 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7823 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7824 kvm_free_all_assigned_devices(kvm);
7825 kvm_free_pit(kvm);
7826 }
7827
7828 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7829 {
7830 int i, r;
7831 unsigned long hva;
7832 struct kvm_memslots *slots = kvm_memslots(kvm);
7833 struct kvm_memory_slot *slot, old;
7834
7835 /* Called with kvm->slots_lock held. */
7836 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7837 return -EINVAL;
7838
7839 slot = id_to_memslot(slots, id);
7840 if (size) {
7841 if (slot->npages)
7842 return -EEXIST;
7843
7844 /*
7845 * MAP_SHARED to prevent internal slot pages from being moved
7846 * by fork()/COW.
7847 */
7848 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7849 MAP_SHARED | MAP_ANONYMOUS, 0);
7850 if (IS_ERR((void *)hva))
7851 return PTR_ERR((void *)hva);
7852 } else {
7853 if (!slot->npages)
7854 return 0;
7855
7856 hva = 0;
7857 }
7858
7859 old = *slot;
7860 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7861 struct kvm_userspace_memory_region m;
7862
7863 m.slot = id | (i << 16);
7864 m.flags = 0;
7865 m.guest_phys_addr = gpa;
7866 m.userspace_addr = hva;
7867 m.memory_size = size;
7868 r = __kvm_set_memory_region(kvm, &m);
7869 if (r < 0)
7870 return r;
7871 }
7872
7873 if (!size) {
7874 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7875 WARN_ON(r < 0);
7876 }
7877
7878 return 0;
7879 }
7880 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7881
7882 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7883 {
7884 int r;
7885
7886 mutex_lock(&kvm->slots_lock);
7887 r = __x86_set_memory_region(kvm, id, gpa, size);
7888 mutex_unlock(&kvm->slots_lock);
7889
7890 return r;
7891 }
7892 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7893
7894 void kvm_arch_destroy_vm(struct kvm *kvm)
7895 {
7896 if (current->mm == kvm->mm) {
7897 /*
7898 * Free memory regions allocated on behalf of userspace,
7899 * unless the the memory map has changed due to process exit
7900 * or fd copying.
7901 */
7902 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7903 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7904 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7905 }
7906 if (kvm_x86_ops->vm_destroy)
7907 kvm_x86_ops->vm_destroy(kvm);
7908 kvm_iommu_unmap_guest(kvm);
7909 kfree(kvm->arch.vpic);
7910 kfree(kvm->arch.vioapic);
7911 kvm_free_vcpus(kvm);
7912 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7913 kvm_mmu_uninit_vm(kvm);
7914 }
7915
7916 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7917 struct kvm_memory_slot *dont)
7918 {
7919 int i;
7920
7921 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7922 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7923 kvfree(free->arch.rmap[i]);
7924 free->arch.rmap[i] = NULL;
7925 }
7926 if (i == 0)
7927 continue;
7928
7929 if (!dont || free->arch.lpage_info[i - 1] !=
7930 dont->arch.lpage_info[i - 1]) {
7931 kvfree(free->arch.lpage_info[i - 1]);
7932 free->arch.lpage_info[i - 1] = NULL;
7933 }
7934 }
7935
7936 kvm_page_track_free_memslot(free, dont);
7937 }
7938
7939 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7940 unsigned long npages)
7941 {
7942 int i;
7943
7944 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7945 struct kvm_lpage_info *linfo;
7946 unsigned long ugfn;
7947 int lpages;
7948 int level = i + 1;
7949
7950 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7951 slot->base_gfn, level) + 1;
7952
7953 slot->arch.rmap[i] =
7954 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7955 if (!slot->arch.rmap[i])
7956 goto out_free;
7957 if (i == 0)
7958 continue;
7959
7960 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7961 if (!linfo)
7962 goto out_free;
7963
7964 slot->arch.lpage_info[i - 1] = linfo;
7965
7966 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7967 linfo[0].disallow_lpage = 1;
7968 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7969 linfo[lpages - 1].disallow_lpage = 1;
7970 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7971 /*
7972 * If the gfn and userspace address are not aligned wrt each
7973 * other, or if explicitly asked to, disable large page
7974 * support for this slot
7975 */
7976 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7977 !kvm_largepages_enabled()) {
7978 unsigned long j;
7979
7980 for (j = 0; j < lpages; ++j)
7981 linfo[j].disallow_lpage = 1;
7982 }
7983 }
7984
7985 if (kvm_page_track_create_memslot(slot, npages))
7986 goto out_free;
7987
7988 return 0;
7989
7990 out_free:
7991 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7992 kvfree(slot->arch.rmap[i]);
7993 slot->arch.rmap[i] = NULL;
7994 if (i == 0)
7995 continue;
7996
7997 kvfree(slot->arch.lpage_info[i - 1]);
7998 slot->arch.lpage_info[i - 1] = NULL;
7999 }
8000 return -ENOMEM;
8001 }
8002
8003 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8004 {
8005 /*
8006 * memslots->generation has been incremented.
8007 * mmio generation may have reached its maximum value.
8008 */
8009 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8010 }
8011
8012 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8013 struct kvm_memory_slot *memslot,
8014 const struct kvm_userspace_memory_region *mem,
8015 enum kvm_mr_change change)
8016 {
8017 return 0;
8018 }
8019
8020 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8021 struct kvm_memory_slot *new)
8022 {
8023 /* Still write protect RO slot */
8024 if (new->flags & KVM_MEM_READONLY) {
8025 kvm_mmu_slot_remove_write_access(kvm, new);
8026 return;
8027 }
8028
8029 /*
8030 * Call kvm_x86_ops dirty logging hooks when they are valid.
8031 *
8032 * kvm_x86_ops->slot_disable_log_dirty is called when:
8033 *
8034 * - KVM_MR_CREATE with dirty logging is disabled
8035 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8036 *
8037 * The reason is, in case of PML, we need to set D-bit for any slots
8038 * with dirty logging disabled in order to eliminate unnecessary GPA
8039 * logging in PML buffer (and potential PML buffer full VMEXT). This
8040 * guarantees leaving PML enabled during guest's lifetime won't have
8041 * any additonal overhead from PML when guest is running with dirty
8042 * logging disabled for memory slots.
8043 *
8044 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8045 * to dirty logging mode.
8046 *
8047 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8048 *
8049 * In case of write protect:
8050 *
8051 * Write protect all pages for dirty logging.
8052 *
8053 * All the sptes including the large sptes which point to this
8054 * slot are set to readonly. We can not create any new large
8055 * spte on this slot until the end of the logging.
8056 *
8057 * See the comments in fast_page_fault().
8058 */
8059 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8060 if (kvm_x86_ops->slot_enable_log_dirty)
8061 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8062 else
8063 kvm_mmu_slot_remove_write_access(kvm, new);
8064 } else {
8065 if (kvm_x86_ops->slot_disable_log_dirty)
8066 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8067 }
8068 }
8069
8070 void kvm_arch_commit_memory_region(struct kvm *kvm,
8071 const struct kvm_userspace_memory_region *mem,
8072 const struct kvm_memory_slot *old,
8073 const struct kvm_memory_slot *new,
8074 enum kvm_mr_change change)
8075 {
8076 int nr_mmu_pages = 0;
8077
8078 if (!kvm->arch.n_requested_mmu_pages)
8079 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8080
8081 if (nr_mmu_pages)
8082 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8083
8084 /*
8085 * Dirty logging tracks sptes in 4k granularity, meaning that large
8086 * sptes have to be split. If live migration is successful, the guest
8087 * in the source machine will be destroyed and large sptes will be
8088 * created in the destination. However, if the guest continues to run
8089 * in the source machine (for example if live migration fails), small
8090 * sptes will remain around and cause bad performance.
8091 *
8092 * Scan sptes if dirty logging has been stopped, dropping those
8093 * which can be collapsed into a single large-page spte. Later
8094 * page faults will create the large-page sptes.
8095 */
8096 if ((change != KVM_MR_DELETE) &&
8097 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8098 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8099 kvm_mmu_zap_collapsible_sptes(kvm, new);
8100
8101 /*
8102 * Set up write protection and/or dirty logging for the new slot.
8103 *
8104 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8105 * been zapped so no dirty logging staff is needed for old slot. For
8106 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8107 * new and it's also covered when dealing with the new slot.
8108 *
8109 * FIXME: const-ify all uses of struct kvm_memory_slot.
8110 */
8111 if (change != KVM_MR_DELETE)
8112 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8113 }
8114
8115 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8116 {
8117 kvm_mmu_invalidate_zap_all_pages(kvm);
8118 }
8119
8120 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8121 struct kvm_memory_slot *slot)
8122 {
8123 kvm_mmu_invalidate_zap_all_pages(kvm);
8124 }
8125
8126 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8127 {
8128 if (!list_empty_careful(&vcpu->async_pf.done))
8129 return true;
8130
8131 if (kvm_apic_has_events(vcpu))
8132 return true;
8133
8134 if (vcpu->arch.pv.pv_unhalted)
8135 return true;
8136
8137 if (atomic_read(&vcpu->arch.nmi_queued))
8138 return true;
8139
8140 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8141 return true;
8142
8143 if (kvm_arch_interrupt_allowed(vcpu) &&
8144 kvm_cpu_has_interrupt(vcpu))
8145 return true;
8146
8147 if (kvm_hv_has_stimer_pending(vcpu))
8148 return true;
8149
8150 return false;
8151 }
8152
8153 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8154 {
8155 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8156 kvm_x86_ops->check_nested_events(vcpu, false);
8157
8158 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8159 }
8160
8161 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8162 {
8163 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8164 }
8165
8166 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8167 {
8168 return kvm_x86_ops->interrupt_allowed(vcpu);
8169 }
8170
8171 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8172 {
8173 if (is_64_bit_mode(vcpu))
8174 return kvm_rip_read(vcpu);
8175 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8176 kvm_rip_read(vcpu));
8177 }
8178 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8179
8180 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8181 {
8182 return kvm_get_linear_rip(vcpu) == linear_rip;
8183 }
8184 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8185
8186 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8187 {
8188 unsigned long rflags;
8189
8190 rflags = kvm_x86_ops->get_rflags(vcpu);
8191 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8192 rflags &= ~X86_EFLAGS_TF;
8193 return rflags;
8194 }
8195 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8196
8197 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8198 {
8199 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8200 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8201 rflags |= X86_EFLAGS_TF;
8202 kvm_x86_ops->set_rflags(vcpu, rflags);
8203 }
8204
8205 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8206 {
8207 __kvm_set_rflags(vcpu, rflags);
8208 kvm_make_request(KVM_REQ_EVENT, vcpu);
8209 }
8210 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8211
8212 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8213 {
8214 int r;
8215
8216 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8217 work->wakeup_all)
8218 return;
8219
8220 r = kvm_mmu_reload(vcpu);
8221 if (unlikely(r))
8222 return;
8223
8224 if (!vcpu->arch.mmu.direct_map &&
8225 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8226 return;
8227
8228 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8229 }
8230
8231 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8232 {
8233 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8234 }
8235
8236 static inline u32 kvm_async_pf_next_probe(u32 key)
8237 {
8238 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8239 }
8240
8241 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8242 {
8243 u32 key = kvm_async_pf_hash_fn(gfn);
8244
8245 while (vcpu->arch.apf.gfns[key] != ~0)
8246 key = kvm_async_pf_next_probe(key);
8247
8248 vcpu->arch.apf.gfns[key] = gfn;
8249 }
8250
8251 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8252 {
8253 int i;
8254 u32 key = kvm_async_pf_hash_fn(gfn);
8255
8256 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8257 (vcpu->arch.apf.gfns[key] != gfn &&
8258 vcpu->arch.apf.gfns[key] != ~0); i++)
8259 key = kvm_async_pf_next_probe(key);
8260
8261 return key;
8262 }
8263
8264 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8265 {
8266 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8267 }
8268
8269 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8270 {
8271 u32 i, j, k;
8272
8273 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8274 while (true) {
8275 vcpu->arch.apf.gfns[i] = ~0;
8276 do {
8277 j = kvm_async_pf_next_probe(j);
8278 if (vcpu->arch.apf.gfns[j] == ~0)
8279 return;
8280 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8281 /*
8282 * k lies cyclically in ]i,j]
8283 * | i.k.j |
8284 * |....j i.k.| or |.k..j i...|
8285 */
8286 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8287 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8288 i = j;
8289 }
8290 }
8291
8292 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8293 {
8294
8295 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8296 sizeof(val));
8297 }
8298
8299 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8300 struct kvm_async_pf *work)
8301 {
8302 struct x86_exception fault;
8303
8304 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8305 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8306
8307 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8308 (vcpu->arch.apf.send_user_only &&
8309 kvm_x86_ops->get_cpl(vcpu) == 0))
8310 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8311 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8312 fault.vector = PF_VECTOR;
8313 fault.error_code_valid = true;
8314 fault.error_code = 0;
8315 fault.nested_page_fault = false;
8316 fault.address = work->arch.token;
8317 kvm_inject_page_fault(vcpu, &fault);
8318 }
8319 }
8320
8321 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8322 struct kvm_async_pf *work)
8323 {
8324 struct x86_exception fault;
8325
8326 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8327 if (work->wakeup_all)
8328 work->arch.token = ~0; /* broadcast wakeup */
8329 else
8330 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8331
8332 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8333 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8334 fault.vector = PF_VECTOR;
8335 fault.error_code_valid = true;
8336 fault.error_code = 0;
8337 fault.nested_page_fault = false;
8338 fault.address = work->arch.token;
8339 kvm_inject_page_fault(vcpu, &fault);
8340 }
8341 vcpu->arch.apf.halted = false;
8342 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8343 }
8344
8345 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8346 {
8347 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8348 return true;
8349 else
8350 return !kvm_event_needs_reinjection(vcpu) &&
8351 kvm_x86_ops->interrupt_allowed(vcpu);
8352 }
8353
8354 void kvm_arch_start_assignment(struct kvm *kvm)
8355 {
8356 atomic_inc(&kvm->arch.assigned_device_count);
8357 }
8358 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8359
8360 void kvm_arch_end_assignment(struct kvm *kvm)
8361 {
8362 atomic_dec(&kvm->arch.assigned_device_count);
8363 }
8364 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8365
8366 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8367 {
8368 return atomic_read(&kvm->arch.assigned_device_count);
8369 }
8370 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8371
8372 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8373 {
8374 atomic_inc(&kvm->arch.noncoherent_dma_count);
8375 }
8376 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8377
8378 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8379 {
8380 atomic_dec(&kvm->arch.noncoherent_dma_count);
8381 }
8382 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8383
8384 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8385 {
8386 return atomic_read(&kvm->arch.noncoherent_dma_count);
8387 }
8388 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8389
8390 bool kvm_arch_has_irq_bypass(void)
8391 {
8392 return kvm_x86_ops->update_pi_irte != NULL;
8393 }
8394
8395 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8396 struct irq_bypass_producer *prod)
8397 {
8398 struct kvm_kernel_irqfd *irqfd =
8399 container_of(cons, struct kvm_kernel_irqfd, consumer);
8400
8401 irqfd->producer = prod;
8402
8403 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8404 prod->irq, irqfd->gsi, 1);
8405 }
8406
8407 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8408 struct irq_bypass_producer *prod)
8409 {
8410 int ret;
8411 struct kvm_kernel_irqfd *irqfd =
8412 container_of(cons, struct kvm_kernel_irqfd, consumer);
8413
8414 WARN_ON(irqfd->producer != prod);
8415 irqfd->producer = NULL;
8416
8417 /*
8418 * When producer of consumer is unregistered, we change back to
8419 * remapped mode, so we can re-use the current implementation
8420 * when the irq is masked/disabled or the consumer side (KVM
8421 * int this case doesn't want to receive the interrupts.
8422 */
8423 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8424 if (ret)
8425 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8426 " fails: %d\n", irqfd->consumer.token, ret);
8427 }
8428
8429 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8430 uint32_t guest_irq, bool set)
8431 {
8432 if (!kvm_x86_ops->update_pi_irte)
8433 return -EINVAL;
8434
8435 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8436 }
8437
8438 bool kvm_vector_hashing_enabled(void)
8439 {
8440 return vector_hashing;
8441 }
8442 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8443
8444 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8445 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8446 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8447 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8448 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8449 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8450 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8451 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8452 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8453 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8454 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8455 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8456 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8457 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8458 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8459 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8460 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8461 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8462 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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