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Merge remote-tracking branches 'asoc/topic/atmel', 'asoc/topic/bcm2835' and 'asoc...
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <trace/events/kvm.h>
57
58 #define CREATE_TRACE_POINTS
59 #include "trace.h"
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70
71 #define MAX_IO_MSRS 256
72 #define KVM_MAX_MCE_BANKS 32
73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
74
75 #define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
78 /* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82 #ifdef CONFIG_X86_64
83 static
84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
85 #else
86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
87 #endif
88
89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
91
92 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
93 static void process_nmi(struct kvm_vcpu *vcpu);
94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
95
96 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
97 EXPORT_SYMBOL_GPL(kvm_x86_ops);
98
99 static bool __read_mostly ignore_msrs = 0;
100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
102 unsigned int min_timer_period_us = 500;
103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
105 static bool __read_mostly kvmclock_periodic_sync = true;
106 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
108 bool __read_mostly kvm_has_tsc_control;
109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
110 u32 __read_mostly kvm_max_guest_tsc_khz;
111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114 u64 __read_mostly kvm_max_tsc_scaling_ratio;
115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
116 static u64 __read_mostly kvm_default_tsc_scaling_ratio;
117
118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
119 static u32 __read_mostly tsc_tolerance_ppm = 250;
120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
123 unsigned int __read_mostly lapic_timer_advance_ns = 0;
124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
126 static bool __read_mostly backwards_tsc_observed = false;
127
128 #define KVM_NR_SHARED_MSRS 16
129
130 struct kvm_shared_msrs_global {
131 int nr;
132 u32 msrs[KVM_NR_SHARED_MSRS];
133 };
134
135 struct kvm_shared_msrs {
136 struct user_return_notifier urn;
137 bool registered;
138 struct kvm_shared_msr_values {
139 u64 host;
140 u64 curr;
141 } values[KVM_NR_SHARED_MSRS];
142 };
143
144 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
145 static struct kvm_shared_msrs __percpu *shared_msrs;
146
147 struct kvm_stats_debugfs_item debugfs_entries[] = {
148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
158 { "halt_exits", VCPU_STAT(halt_exits) },
159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
162 { "hypercalls", VCPU_STAT(hypercalls) },
163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
170 { "irq_injections", VCPU_STAT(irq_injections) },
171 { "nmi_injections", VCPU_STAT(nmi_injections) },
172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
179 { "mmu_unsync", VM_STAT(mmu_unsync) },
180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
181 { "largepages", VM_STAT(lpages) },
182 { NULL }
183 };
184
185 u64 __read_mostly host_xcr0;
186
187 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
188
189 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190 {
191 int i;
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
194 }
195
196 static void kvm_on_user_return(struct user_return_notifier *urn)
197 {
198 unsigned slot;
199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
201 struct kvm_shared_msr_values *values;
202
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
208 }
209 }
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
212 }
213
214 static void shared_msr_update(unsigned slot, u32 msr)
215 {
216 u64 value;
217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
219
220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
224 return;
225 }
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
229 }
230
231 void kvm_define_shared_msr(unsigned slot, u32 msr)
232 {
233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
234 shared_msrs_global.msrs[slot] = msr;
235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
237 }
238 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239
240 static void kvm_shared_msr_cpu_online(void)
241 {
242 unsigned i;
243
244 for (i = 0; i < shared_msrs_global.nr; ++i)
245 shared_msr_update(i, shared_msrs_global.msrs[i]);
246 }
247
248 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
249 {
250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
252 int err;
253
254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
255 return 0;
256 smsr->values[slot].curr = value;
257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 if (err)
259 return 1;
260
261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
265 }
266 return 0;
267 }
268 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269
270 static void drop_user_return_notifiers(void)
271 {
272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
274
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
277 }
278
279 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280 {
281 return vcpu->arch.apic_base;
282 }
283 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284
285 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286 {
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 old_state == 0)))
301 return 1;
302
303 kvm_lapic_set_base(vcpu, msr_info->data);
304 return 0;
305 }
306 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307
308 asmlinkage __visible void kvm_spurious_fault(void)
309 {
310 /* Fault while not rebooting. We want the trace. */
311 BUG();
312 }
313 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314
315 #define EXCPT_BENIGN 0
316 #define EXCPT_CONTRIBUTORY 1
317 #define EXCPT_PF 2
318
319 static int exception_class(int vector)
320 {
321 switch (vector) {
322 case PF_VECTOR:
323 return EXCPT_PF;
324 case DE_VECTOR:
325 case TS_VECTOR:
326 case NP_VECTOR:
327 case SS_VECTOR:
328 case GP_VECTOR:
329 return EXCPT_CONTRIBUTORY;
330 default:
331 break;
332 }
333 return EXCPT_BENIGN;
334 }
335
336 #define EXCPT_FAULT 0
337 #define EXCPT_TRAP 1
338 #define EXCPT_ABORT 2
339 #define EXCPT_INTERRUPT 3
340
341 static int exception_type(int vector)
342 {
343 unsigned int mask;
344
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
347
348 mask = 1 << vector;
349
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 return EXCPT_TRAP;
353
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 return EXCPT_ABORT;
356
357 /* Reserved exceptions will result in fault */
358 return EXCPT_FAULT;
359 }
360
361 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
362 unsigned nr, bool has_error, u32 error_code,
363 bool reinject)
364 {
365 u32 prev_nr;
366 int class1, class2;
367
368 kvm_make_request(KVM_REQ_EVENT, vcpu);
369
370 if (!vcpu->arch.exception.pending) {
371 queue:
372 if (has_error && !is_protmode(vcpu))
373 has_error = false;
374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
378 vcpu->arch.exception.reinject = reinject;
379 return;
380 }
381
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
387 return;
388 }
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
398 } else
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
401 exception */
402 goto queue;
403 }
404
405 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406 {
407 kvm_multiple_exception(vcpu, nr, false, 0, false);
408 }
409 EXPORT_SYMBOL_GPL(kvm_queue_exception);
410
411 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412 {
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
414 }
415 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416
417 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
418 {
419 if (err)
420 kvm_inject_gp(vcpu, 0);
421 else
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
423 }
424 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
425
426 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
427 {
428 ++vcpu->stat.pf_guest;
429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
431 }
432 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
433
434 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
435 {
436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
438 else
439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
440
441 return fault->nested_page_fault;
442 }
443
444 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445 {
446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
448 }
449 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450
451 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452 {
453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
454 }
455 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456
457 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458 {
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
460 }
461 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462
463 /*
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
466 */
467 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
468 {
469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 return true;
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 return false;
473 }
474 EXPORT_SYMBOL_GPL(kvm_require_cpl);
475
476 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477 {
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 return true;
480
481 kvm_queue_exception(vcpu, UD_VECTOR);
482 return false;
483 }
484 EXPORT_SYMBOL_GPL(kvm_require_dr);
485
486 /*
487 * This function will be used to read from the physical memory of the currently
488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
489 * can read from guest physical or from the guest's guest physical memory.
490 */
491 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
493 u32 access)
494 {
495 struct x86_exception exception;
496 gfn_t real_gfn;
497 gpa_t ngpa;
498
499 ngpa = gfn_to_gpa(ngfn);
500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
501 if (real_gfn == UNMAPPED_GVA)
502 return -EFAULT;
503
504 real_gfn = gpa_to_gfn(real_gfn);
505
506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
507 }
508 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509
510 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
511 void *data, int offset, int len, u32 access)
512 {
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
515 }
516
517 /*
518 * Load the pae pdptrs. Return true is they are all valid.
519 */
520 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
521 {
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 int i;
525 int ret;
526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
527
528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
531 if (ret < 0) {
532 ret = 0;
533 goto out;
534 }
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
536 if (is_present_gpte(pdpte[i]) &&
537 (pdpte[i] &
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
539 ret = 0;
540 goto out;
541 }
542 }
543 ret = 1;
544
545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
550 out:
551
552 return ret;
553 }
554 EXPORT_SYMBOL_GPL(load_pdptrs);
555
556 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557 {
558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
559 bool changed = true;
560 int offset;
561 gfn_t gfn;
562 int r;
563
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
565 return false;
566
567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
569 return true;
570
571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
575 if (r < 0)
576 goto out;
577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
578 out:
579
580 return changed;
581 }
582
583 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
584 {
585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
587
588 cr0 |= X86_CR0_ET;
589
590 #ifdef CONFIG_X86_64
591 if (cr0 & 0xffffffff00000000UL)
592 return 1;
593 #endif
594
595 cr0 &= ~CR0_RESERVED_BITS;
596
597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 return 1;
599
600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 return 1;
602
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604 #ifdef CONFIG_X86_64
605 if ((vcpu->arch.efer & EFER_LME)) {
606 int cs_db, cs_l;
607
608 if (!is_pae(vcpu))
609 return 1;
610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
611 if (cs_l)
612 return 1;
613 } else
614 #endif
615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
616 kvm_read_cr3(vcpu)))
617 return 1;
618 }
619
620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 return 1;
622
623 kvm_x86_ops->set_cr0(vcpu, cr0);
624
625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
626 kvm_clear_async_pf_completion_queue(vcpu);
627 kvm_async_pf_hash_reset(vcpu);
628 }
629
630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
632
633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637
638 return 0;
639 }
640 EXPORT_SYMBOL_GPL(kvm_set_cr0);
641
642 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
643 {
644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
645 }
646 EXPORT_SYMBOL_GPL(kvm_lmsw);
647
648 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649 {
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
655 }
656 }
657
658 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659 {
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
664 }
665 }
666
667 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
668 {
669 u64 xcr0 = xcr;
670 u64 old_xcr0 = vcpu->arch.xcr0;
671 u64 valid_bits;
672
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
675 return 1;
676 if (!(xcr0 & XFEATURE_MASK_FP))
677 return 1;
678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
679 return 1;
680
681 /*
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
685 */
686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
687 if (xcr0 & ~valid_bits)
688 return 1;
689
690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
691 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
692 return 1;
693
694 if (xcr0 & XFEATURE_MASK_AVX512) {
695 if (!(xcr0 & XFEATURE_MASK_YMM))
696 return 1;
697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
698 return 1;
699 }
700 kvm_put_guest_xcr0(vcpu);
701 vcpu->arch.xcr0 = xcr0;
702
703 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
704 kvm_update_cpuid(vcpu);
705 return 0;
706 }
707
708 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
709 {
710 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
711 __kvm_set_xcr(vcpu, index, xcr)) {
712 kvm_inject_gp(vcpu, 0);
713 return 1;
714 }
715 return 0;
716 }
717 EXPORT_SYMBOL_GPL(kvm_set_xcr);
718
719 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
720 {
721 unsigned long old_cr4 = kvm_read_cr4(vcpu);
722 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
723 X86_CR4_SMEP | X86_CR4_SMAP;
724
725 if (cr4 & CR4_RESERVED_BITS)
726 return 1;
727
728 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
729 return 1;
730
731 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
732 return 1;
733
734 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
735 return 1;
736
737 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
738 return 1;
739
740 if (is_long_mode(vcpu)) {
741 if (!(cr4 & X86_CR4_PAE))
742 return 1;
743 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
744 && ((cr4 ^ old_cr4) & pdptr_bits)
745 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
746 kvm_read_cr3(vcpu)))
747 return 1;
748
749 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
750 if (!guest_cpuid_has_pcid(vcpu))
751 return 1;
752
753 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
754 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
755 return 1;
756 }
757
758 if (kvm_x86_ops->set_cr4(vcpu, cr4))
759 return 1;
760
761 if (((cr4 ^ old_cr4) & pdptr_bits) ||
762 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
763 kvm_mmu_reset_context(vcpu);
764
765 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
766 kvm_update_cpuid(vcpu);
767
768 return 0;
769 }
770 EXPORT_SYMBOL_GPL(kvm_set_cr4);
771
772 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
773 {
774 #ifdef CONFIG_X86_64
775 cr3 &= ~CR3_PCID_INVD;
776 #endif
777
778 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
779 kvm_mmu_sync_roots(vcpu);
780 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
781 return 0;
782 }
783
784 if (is_long_mode(vcpu)) {
785 if (cr3 & CR3_L_MODE_RESERVED_BITS)
786 return 1;
787 } else if (is_pae(vcpu) && is_paging(vcpu) &&
788 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
789 return 1;
790
791 vcpu->arch.cr3 = cr3;
792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
793 kvm_mmu_new_cr3(vcpu);
794 return 0;
795 }
796 EXPORT_SYMBOL_GPL(kvm_set_cr3);
797
798 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
799 {
800 if (cr8 & CR8_RESERVED_BITS)
801 return 1;
802 if (lapic_in_kernel(vcpu))
803 kvm_lapic_set_tpr(vcpu, cr8);
804 else
805 vcpu->arch.cr8 = cr8;
806 return 0;
807 }
808 EXPORT_SYMBOL_GPL(kvm_set_cr8);
809
810 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
811 {
812 if (lapic_in_kernel(vcpu))
813 return kvm_lapic_get_cr8(vcpu);
814 else
815 return vcpu->arch.cr8;
816 }
817 EXPORT_SYMBOL_GPL(kvm_get_cr8);
818
819 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
820 {
821 int i;
822
823 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
824 for (i = 0; i < KVM_NR_DB_REGS; i++)
825 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
826 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
827 }
828 }
829
830 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
831 {
832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
833 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
834 }
835
836 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
837 {
838 unsigned long dr7;
839
840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
841 dr7 = vcpu->arch.guest_debug_dr7;
842 else
843 dr7 = vcpu->arch.dr7;
844 kvm_x86_ops->set_dr7(vcpu, dr7);
845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
846 if (dr7 & DR7_BP_EN_MASK)
847 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
848 }
849
850 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
851 {
852 u64 fixed = DR6_FIXED_1;
853
854 if (!guest_cpuid_has_rtm(vcpu))
855 fixed |= DR6_RTM;
856 return fixed;
857 }
858
859 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
860 {
861 switch (dr) {
862 case 0 ... 3:
863 vcpu->arch.db[dr] = val;
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 vcpu->arch.eff_db[dr] = val;
866 break;
867 case 4:
868 /* fall through */
869 case 6:
870 if (val & 0xffffffff00000000ULL)
871 return -1; /* #GP */
872 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
873 kvm_update_dr6(vcpu);
874 break;
875 case 5:
876 /* fall through */
877 default: /* 7 */
878 if (val & 0xffffffff00000000ULL)
879 return -1; /* #GP */
880 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
881 kvm_update_dr7(vcpu);
882 break;
883 }
884
885 return 0;
886 }
887
888 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
889 {
890 if (__kvm_set_dr(vcpu, dr, val)) {
891 kvm_inject_gp(vcpu, 0);
892 return 1;
893 }
894 return 0;
895 }
896 EXPORT_SYMBOL_GPL(kvm_set_dr);
897
898 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
899 {
900 switch (dr) {
901 case 0 ... 3:
902 *val = vcpu->arch.db[dr];
903 break;
904 case 4:
905 /* fall through */
906 case 6:
907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
908 *val = vcpu->arch.dr6;
909 else
910 *val = kvm_x86_ops->get_dr6(vcpu);
911 break;
912 case 5:
913 /* fall through */
914 default: /* 7 */
915 *val = vcpu->arch.dr7;
916 break;
917 }
918 return 0;
919 }
920 EXPORT_SYMBOL_GPL(kvm_get_dr);
921
922 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
923 {
924 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
925 u64 data;
926 int err;
927
928 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
929 if (err)
930 return err;
931 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
932 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
933 return err;
934 }
935 EXPORT_SYMBOL_GPL(kvm_rdpmc);
936
937 /*
938 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
939 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
940 *
941 * This list is modified at module load time to reflect the
942 * capabilities of the host cpu. This capabilities test skips MSRs that are
943 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
944 * may depend on host virtualization features rather than host cpu features.
945 */
946
947 static u32 msrs_to_save[] = {
948 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
949 MSR_STAR,
950 #ifdef CONFIG_X86_64
951 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
952 #endif
953 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
954 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
955 };
956
957 static unsigned num_msrs_to_save;
958
959 static u32 emulated_msrs[] = {
960 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
961 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
962 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
963 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
964 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
965 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
966 HV_X64_MSR_RESET,
967 HV_X64_MSR_VP_INDEX,
968 HV_X64_MSR_VP_RUNTIME,
969 HV_X64_MSR_SCONTROL,
970 HV_X64_MSR_STIMER0_CONFIG,
971 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
972 MSR_KVM_PV_EOI_EN,
973
974 MSR_IA32_TSC_ADJUST,
975 MSR_IA32_TSCDEADLINE,
976 MSR_IA32_MISC_ENABLE,
977 MSR_IA32_MCG_STATUS,
978 MSR_IA32_MCG_CTL,
979 MSR_IA32_SMBASE,
980 };
981
982 static unsigned num_emulated_msrs;
983
984 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
985 {
986 if (efer & efer_reserved_bits)
987 return false;
988
989 if (efer & EFER_FFXSR) {
990 struct kvm_cpuid_entry2 *feat;
991
992 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
993 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
994 return false;
995 }
996
997 if (efer & EFER_SVME) {
998 struct kvm_cpuid_entry2 *feat;
999
1000 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1001 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1002 return false;
1003 }
1004
1005 return true;
1006 }
1007 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1008
1009 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1010 {
1011 u64 old_efer = vcpu->arch.efer;
1012
1013 if (!kvm_valid_efer(vcpu, efer))
1014 return 1;
1015
1016 if (is_paging(vcpu)
1017 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1018 return 1;
1019
1020 efer &= ~EFER_LMA;
1021 efer |= vcpu->arch.efer & EFER_LMA;
1022
1023 kvm_x86_ops->set_efer(vcpu, efer);
1024
1025 /* Update reserved bits */
1026 if ((efer ^ old_efer) & EFER_NX)
1027 kvm_mmu_reset_context(vcpu);
1028
1029 return 0;
1030 }
1031
1032 void kvm_enable_efer_bits(u64 mask)
1033 {
1034 efer_reserved_bits &= ~mask;
1035 }
1036 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1037
1038 /*
1039 * Writes msr value into into the appropriate "register".
1040 * Returns 0 on success, non-0 otherwise.
1041 * Assumes vcpu_load() was already called.
1042 */
1043 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1044 {
1045 switch (msr->index) {
1046 case MSR_FS_BASE:
1047 case MSR_GS_BASE:
1048 case MSR_KERNEL_GS_BASE:
1049 case MSR_CSTAR:
1050 case MSR_LSTAR:
1051 if (is_noncanonical_address(msr->data))
1052 return 1;
1053 break;
1054 case MSR_IA32_SYSENTER_EIP:
1055 case MSR_IA32_SYSENTER_ESP:
1056 /*
1057 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1058 * non-canonical address is written on Intel but not on
1059 * AMD (which ignores the top 32-bits, because it does
1060 * not implement 64-bit SYSENTER).
1061 *
1062 * 64-bit code should hence be able to write a non-canonical
1063 * value on AMD. Making the address canonical ensures that
1064 * vmentry does not fail on Intel after writing a non-canonical
1065 * value, and that something deterministic happens if the guest
1066 * invokes 64-bit SYSENTER.
1067 */
1068 msr->data = get_canonical(msr->data);
1069 }
1070 return kvm_x86_ops->set_msr(vcpu, msr);
1071 }
1072 EXPORT_SYMBOL_GPL(kvm_set_msr);
1073
1074 /*
1075 * Adapt set_msr() to msr_io()'s calling convention
1076 */
1077 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1078 {
1079 struct msr_data msr;
1080 int r;
1081
1082 msr.index = index;
1083 msr.host_initiated = true;
1084 r = kvm_get_msr(vcpu, &msr);
1085 if (r)
1086 return r;
1087
1088 *data = msr.data;
1089 return 0;
1090 }
1091
1092 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1093 {
1094 struct msr_data msr;
1095
1096 msr.data = *data;
1097 msr.index = index;
1098 msr.host_initiated = true;
1099 return kvm_set_msr(vcpu, &msr);
1100 }
1101
1102 #ifdef CONFIG_X86_64
1103 struct pvclock_gtod_data {
1104 seqcount_t seq;
1105
1106 struct { /* extract of a clocksource struct */
1107 int vclock_mode;
1108 cycle_t cycle_last;
1109 cycle_t mask;
1110 u32 mult;
1111 u32 shift;
1112 } clock;
1113
1114 u64 boot_ns;
1115 u64 nsec_base;
1116 };
1117
1118 static struct pvclock_gtod_data pvclock_gtod_data;
1119
1120 static void update_pvclock_gtod(struct timekeeper *tk)
1121 {
1122 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1123 u64 boot_ns;
1124
1125 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1126
1127 write_seqcount_begin(&vdata->seq);
1128
1129 /* copy pvclock gtod data */
1130 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1131 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1132 vdata->clock.mask = tk->tkr_mono.mask;
1133 vdata->clock.mult = tk->tkr_mono.mult;
1134 vdata->clock.shift = tk->tkr_mono.shift;
1135
1136 vdata->boot_ns = boot_ns;
1137 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1138
1139 write_seqcount_end(&vdata->seq);
1140 }
1141 #endif
1142
1143 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1144 {
1145 /*
1146 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1147 * vcpu_enter_guest. This function is only called from
1148 * the physical CPU that is running vcpu.
1149 */
1150 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1151 }
1152
1153 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1154 {
1155 int version;
1156 int r;
1157 struct pvclock_wall_clock wc;
1158 struct timespec boot;
1159
1160 if (!wall_clock)
1161 return;
1162
1163 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1164 if (r)
1165 return;
1166
1167 if (version & 1)
1168 ++version; /* first time write, random junk */
1169
1170 ++version;
1171
1172 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1173 return;
1174
1175 /*
1176 * The guest calculates current wall clock time by adding
1177 * system time (updated by kvm_guest_time_update below) to the
1178 * wall clock specified here. guest system time equals host
1179 * system time for us, thus we must fill in host boot time here.
1180 */
1181 getboottime(&boot);
1182
1183 if (kvm->arch.kvmclock_offset) {
1184 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1185 boot = timespec_sub(boot, ts);
1186 }
1187 wc.sec = boot.tv_sec;
1188 wc.nsec = boot.tv_nsec;
1189 wc.version = version;
1190
1191 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1192
1193 version++;
1194 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1195 }
1196
1197 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1198 {
1199 uint32_t quotient, remainder;
1200
1201 /* Don't try to replace with do_div(), this one calculates
1202 * "(dividend << 32) / divisor" */
1203 __asm__ ( "divl %4"
1204 : "=a" (quotient), "=d" (remainder)
1205 : "0" (0), "1" (dividend), "r" (divisor) );
1206 return quotient;
1207 }
1208
1209 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1210 s8 *pshift, u32 *pmultiplier)
1211 {
1212 uint64_t scaled64;
1213 int32_t shift = 0;
1214 uint64_t tps64;
1215 uint32_t tps32;
1216
1217 tps64 = base_khz * 1000LL;
1218 scaled64 = scaled_khz * 1000LL;
1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1220 tps64 >>= 1;
1221 shift--;
1222 }
1223
1224 tps32 = (uint32_t)tps64;
1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1227 scaled64 >>= 1;
1228 else
1229 tps32 <<= 1;
1230 shift++;
1231 }
1232
1233 *pshift = shift;
1234 *pmultiplier = div_frac(scaled64, tps32);
1235
1236 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1237 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1238 }
1239
1240 #ifdef CONFIG_X86_64
1241 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1242 #endif
1243
1244 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1245 static unsigned long max_tsc_khz;
1246
1247 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1248 {
1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
1251 }
1252
1253 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1254 {
1255 u64 v = (u64)khz * (1000000 + ppm);
1256 do_div(v, 1000000);
1257 return v;
1258 }
1259
1260 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1261 {
1262 u64 ratio;
1263
1264 /* Guest TSC same frequency as host TSC? */
1265 if (!scale) {
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1267 return 0;
1268 }
1269
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1275 return 0;
1276 } else {
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1278 return -1;
1279 }
1280 }
1281
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1285
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1288 user_tsc_khz);
1289 return -1;
1290 }
1291
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1293 return 0;
1294 }
1295
1296 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1297 {
1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
1300
1301 /* tsc_khz can be zero if TSC calibration fails */
1302 if (this_tsc_khz == 0) {
1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1305 return -1;
1306 }
1307
1308 /* Compute a scale to convert nanoseconds in TSC cycles */
1309 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
1312 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1313
1314 /*
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1319 */
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1322 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1324 use_scaling = 1;
1325 }
1326 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1327 }
1328
1329 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1330 {
1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
1334 tsc += vcpu->arch.this_tsc_write;
1335 return tsc;
1336 }
1337
1338 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1339 {
1340 #ifdef CONFIG_X86_64
1341 bool vcpus_matched;
1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1347
1348 /*
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1351 *
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1355 */
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1359
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1363 #endif
1364 }
1365
1366 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1367 {
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1370 }
1371
1372 /*
1373 * Multiply tsc by a fixed point number represented by ratio.
1374 *
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1379 *
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1381 */
1382 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1383 {
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1385 }
1386
1387 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1388 {
1389 u64 _tsc = tsc;
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1391
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1394
1395 return _tsc;
1396 }
1397 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1398
1399 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1400 {
1401 u64 tsc;
1402
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1404
1405 return target_tsc - tsc;
1406 }
1407
1408 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1409 {
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1411 }
1412 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1413
1414 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1415 {
1416 struct kvm *kvm = vcpu->kvm;
1417 u64 offset, ns, elapsed;
1418 unsigned long flags;
1419 s64 usdiff;
1420 bool matched;
1421 bool already_matched;
1422 u64 data = msr->data;
1423
1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1425 offset = kvm_compute_tsc_offset(vcpu, data);
1426 ns = get_kernel_ns();
1427 elapsed = ns - kvm->arch.last_tsc_nsec;
1428
1429 if (vcpu->arch.virtual_tsc_khz) {
1430 int faulted = 0;
1431
1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
1434 #ifdef CONFIG_X86_64
1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1436 #else
1437 /* do_div() only does unsigned */
1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1441 "3:\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1444 " jmp 3b\n"
1445 ".previous\n"
1446
1447 _ASM_EXTABLE(1b, 4b)
1448
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1451
1452 #endif
1453 do_div(elapsed, 1000);
1454 usdiff -= elapsed;
1455 if (usdiff < 0)
1456 usdiff = -usdiff;
1457
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1459 if (faulted)
1460 usdiff = USEC_PER_SEC;
1461 } else
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1463
1464 /*
1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1468 *
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1473 */
1474 if (usdiff < USEC_PER_SEC &&
1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1476 if (!check_tsc_unstable()) {
1477 offset = kvm->arch.cur_tsc_offset;
1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1479 } else {
1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
1481 data += delta;
1482 offset = kvm_compute_tsc_offset(vcpu, data);
1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1484 }
1485 matched = true;
1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1487 } else {
1488 /*
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
1493 * exact software computation in compute_guest_tsc()
1494 *
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1496 */
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
1501 matched = false;
1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1503 kvm->arch.cur_tsc_generation, data);
1504 }
1505
1506 /*
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1509 */
1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1513
1514 vcpu->arch.last_guest_tsc = data;
1515
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1520
1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1525
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1527 if (!matched) {
1528 kvm->arch.nr_vcpus_matched_tsc = 0;
1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1531 }
1532
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1535 }
1536
1537 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1538
1539 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1540 s64 adjustment)
1541 {
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1543 }
1544
1545 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1546 {
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551 }
1552
1553 #ifdef CONFIG_X86_64
1554
1555 static cycle_t read_tsc(void)
1556 {
1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
1559
1560 if (likely(ret >= last))
1561 return ret;
1562
1563 /*
1564 * GCC likes to generate cmov here, but this branch is extremely
1565 * predictable (it's just a funciton of time and the likely is
1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1570 */
1571 asm volatile ("");
1572 return last;
1573 }
1574
1575 static inline u64 vgettsc(cycle_t *cycle_now)
1576 {
1577 long v;
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1579
1580 *cycle_now = read_tsc();
1581
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1584 }
1585
1586 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1587 {
1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1589 unsigned long seq;
1590 int mode;
1591 u64 ns;
1592
1593 do {
1594 seq = read_seqcount_begin(&gtod->seq);
1595 mode = gtod->clock.vclock_mode;
1596 ns = gtod->nsec_base;
1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
1599 ns += gtod->boot_ns;
1600 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1601 *t = ns;
1602
1603 return mode;
1604 }
1605
1606 /* returns true if host is using tsc clocksource */
1607 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1608 {
1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1611 return false;
1612
1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1614 }
1615 #endif
1616
1617 /*
1618 *
1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
1622 * CPUs at the next numbered event.
1623 *
1624 * "timespecX" represents host monotonic time. "tscX" represents
1625 * RDTSC value.
1626 *
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1628 *
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1631 * | tsc1 = tsc0 + M
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1636 *
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1638 *
1639 * - ret0 < ret1
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1641 * ...
1642 * - 0 < N - M => M < N
1643 *
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1648 *
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1652 * in lockstep.
1653 *
1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1655 *
1656 */
1657
1658 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1659 {
1660 #ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1662 int vclock_mode;
1663 bool host_tsc_clocksource, vcpus_matched;
1664
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
1667
1668 /*
1669 * If the host uses TSC clock, then passthrough TSC as stable
1670 * to the guest.
1671 */
1672 host_tsc_clocksource = kvm_get_time_and_clockread(
1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1675
1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
1679
1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1682
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1685 vcpus_matched);
1686 #endif
1687 }
1688
1689 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1690 {
1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1692 }
1693
1694 static void kvm_gen_update_masterclock(struct kvm *kvm)
1695 {
1696 #ifdef CONFIG_X86_64
1697 int i;
1698 struct kvm_vcpu *vcpu;
1699 struct kvm_arch *ka = &kvm->arch;
1700
1701 spin_lock(&ka->pvclock_gtod_sync_lock);
1702 kvm_make_mclock_inprogress_request(kvm);
1703 /* no guest entries from this point */
1704 pvclock_update_vm_gtod_copy(kvm);
1705
1706 kvm_for_each_vcpu(i, vcpu, kvm)
1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1708
1709 /* guest entries allowed */
1710 kvm_for_each_vcpu(i, vcpu, kvm)
1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1712
1713 spin_unlock(&ka->pvclock_gtod_sync_lock);
1714 #endif
1715 }
1716
1717 static int kvm_guest_time_update(struct kvm_vcpu *v)
1718 {
1719 unsigned long flags, this_tsc_khz, tgt_tsc_khz;
1720 struct kvm_vcpu_arch *vcpu = &v->arch;
1721 struct kvm_arch *ka = &v->kvm->arch;
1722 s64 kernel_ns;
1723 u64 tsc_timestamp, host_tsc;
1724 struct pvclock_vcpu_time_info guest_hv_clock;
1725 u8 pvclock_flags;
1726 bool use_master_clock;
1727
1728 kernel_ns = 0;
1729 host_tsc = 0;
1730
1731 /*
1732 * If the host uses TSC clock, then passthrough TSC as stable
1733 * to the guest.
1734 */
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 use_master_clock = ka->use_master_clock;
1737 if (use_master_clock) {
1738 host_tsc = ka->master_cycle_now;
1739 kernel_ns = ka->master_kernel_ns;
1740 }
1741 spin_unlock(&ka->pvclock_gtod_sync_lock);
1742
1743 /* Keep irq disabled to prevent changes to the clock */
1744 local_irq_save(flags);
1745 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1746 if (unlikely(this_tsc_khz == 0)) {
1747 local_irq_restore(flags);
1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1749 return 1;
1750 }
1751 if (!use_master_clock) {
1752 host_tsc = rdtsc();
1753 kernel_ns = get_kernel_ns();
1754 }
1755
1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1757
1758 /*
1759 * We may have to catch up the TSC to match elapsed wall clock
1760 * time for two reasons, even if kvmclock is used.
1761 * 1) CPU could have been running below the maximum TSC rate
1762 * 2) Broken TSC compensation resets the base at each VCPU
1763 * entry to avoid unknown leaps of TSC even when running
1764 * again on the same CPU. This may cause apparent elapsed
1765 * time to disappear, and the guest to stand still or run
1766 * very slowly.
1767 */
1768 if (vcpu->tsc_catchup) {
1769 u64 tsc = compute_guest_tsc(v, kernel_ns);
1770 if (tsc > tsc_timestamp) {
1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1772 tsc_timestamp = tsc;
1773 }
1774 }
1775
1776 local_irq_restore(flags);
1777
1778 if (!vcpu->pv_time_enabled)
1779 return 0;
1780
1781 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1782 tgt_tsc_khz = kvm_has_tsc_control ?
1783 vcpu->virtual_tsc_khz : this_tsc_khz;
1784 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
1785 &vcpu->hv_clock.tsc_shift,
1786 &vcpu->hv_clock.tsc_to_system_mul);
1787 vcpu->hw_tsc_khz = this_tsc_khz;
1788 }
1789
1790 /* With all the info we got, fill in the values */
1791 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1792 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1793 vcpu->last_guest_tsc = tsc_timestamp;
1794
1795 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1796 &guest_hv_clock, sizeof(guest_hv_clock))))
1797 return 0;
1798
1799 /* This VCPU is paused, but it's legal for a guest to read another
1800 * VCPU's kvmclock, so we really have to follow the specification where
1801 * it says that version is odd if data is being modified, and even after
1802 * it is consistent.
1803 *
1804 * Version field updates must be kept separate. This is because
1805 * kvm_write_guest_cached might use a "rep movs" instruction, and
1806 * writes within a string instruction are weakly ordered. So there
1807 * are three writes overall.
1808 *
1809 * As a small optimization, only write the version field in the first
1810 * and third write. The vcpu->pv_time cache is still valid, because the
1811 * version field is the first in the struct.
1812 */
1813 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1814
1815 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1816 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1817 &vcpu->hv_clock,
1818 sizeof(vcpu->hv_clock.version));
1819
1820 smp_wmb();
1821
1822 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1823 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1824
1825 if (vcpu->pvclock_set_guest_stopped_request) {
1826 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1827 vcpu->pvclock_set_guest_stopped_request = false;
1828 }
1829
1830 /* If the host uses TSC clocksource, then it is stable */
1831 if (use_master_clock)
1832 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1833
1834 vcpu->hv_clock.flags = pvclock_flags;
1835
1836 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1837
1838 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1839 &vcpu->hv_clock,
1840 sizeof(vcpu->hv_clock));
1841
1842 smp_wmb();
1843
1844 vcpu->hv_clock.version++;
1845 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1846 &vcpu->hv_clock,
1847 sizeof(vcpu->hv_clock.version));
1848 return 0;
1849 }
1850
1851 /*
1852 * kvmclock updates which are isolated to a given vcpu, such as
1853 * vcpu->cpu migration, should not allow system_timestamp from
1854 * the rest of the vcpus to remain static. Otherwise ntp frequency
1855 * correction applies to one vcpu's system_timestamp but not
1856 * the others.
1857 *
1858 * So in those cases, request a kvmclock update for all vcpus.
1859 * We need to rate-limit these requests though, as they can
1860 * considerably slow guests that have a large number of vcpus.
1861 * The time for a remote vcpu to update its kvmclock is bound
1862 * by the delay we use to rate-limit the updates.
1863 */
1864
1865 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1866
1867 static void kvmclock_update_fn(struct work_struct *work)
1868 {
1869 int i;
1870 struct delayed_work *dwork = to_delayed_work(work);
1871 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1872 kvmclock_update_work);
1873 struct kvm *kvm = container_of(ka, struct kvm, arch);
1874 struct kvm_vcpu *vcpu;
1875
1876 kvm_for_each_vcpu(i, vcpu, kvm) {
1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1878 kvm_vcpu_kick(vcpu);
1879 }
1880 }
1881
1882 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1883 {
1884 struct kvm *kvm = v->kvm;
1885
1886 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1887 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1888 KVMCLOCK_UPDATE_DELAY);
1889 }
1890
1891 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1892
1893 static void kvmclock_sync_fn(struct work_struct *work)
1894 {
1895 struct delayed_work *dwork = to_delayed_work(work);
1896 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1897 kvmclock_sync_work);
1898 struct kvm *kvm = container_of(ka, struct kvm, arch);
1899
1900 if (!kvmclock_periodic_sync)
1901 return;
1902
1903 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1904 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1905 KVMCLOCK_SYNC_PERIOD);
1906 }
1907
1908 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1909 {
1910 u64 mcg_cap = vcpu->arch.mcg_cap;
1911 unsigned bank_num = mcg_cap & 0xff;
1912
1913 switch (msr) {
1914 case MSR_IA32_MCG_STATUS:
1915 vcpu->arch.mcg_status = data;
1916 break;
1917 case MSR_IA32_MCG_CTL:
1918 if (!(mcg_cap & MCG_CTL_P))
1919 return 1;
1920 if (data != 0 && data != ~(u64)0)
1921 return -1;
1922 vcpu->arch.mcg_ctl = data;
1923 break;
1924 default:
1925 if (msr >= MSR_IA32_MC0_CTL &&
1926 msr < MSR_IA32_MCx_CTL(bank_num)) {
1927 u32 offset = msr - MSR_IA32_MC0_CTL;
1928 /* only 0 or all 1s can be written to IA32_MCi_CTL
1929 * some Linux kernels though clear bit 10 in bank 4 to
1930 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1931 * this to avoid an uncatched #GP in the guest
1932 */
1933 if ((offset & 0x3) == 0 &&
1934 data != 0 && (data | (1 << 10)) != ~(u64)0)
1935 return -1;
1936 vcpu->arch.mce_banks[offset] = data;
1937 break;
1938 }
1939 return 1;
1940 }
1941 return 0;
1942 }
1943
1944 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1945 {
1946 struct kvm *kvm = vcpu->kvm;
1947 int lm = is_long_mode(vcpu);
1948 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1949 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1950 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1951 : kvm->arch.xen_hvm_config.blob_size_32;
1952 u32 page_num = data & ~PAGE_MASK;
1953 u64 page_addr = data & PAGE_MASK;
1954 u8 *page;
1955 int r;
1956
1957 r = -E2BIG;
1958 if (page_num >= blob_size)
1959 goto out;
1960 r = -ENOMEM;
1961 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1962 if (IS_ERR(page)) {
1963 r = PTR_ERR(page);
1964 goto out;
1965 }
1966 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1967 goto out_free;
1968 r = 0;
1969 out_free:
1970 kfree(page);
1971 out:
1972 return r;
1973 }
1974
1975 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1976 {
1977 gpa_t gpa = data & ~0x3f;
1978
1979 /* Bits 2:5 are reserved, Should be zero */
1980 if (data & 0x3c)
1981 return 1;
1982
1983 vcpu->arch.apf.msr_val = data;
1984
1985 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1986 kvm_clear_async_pf_completion_queue(vcpu);
1987 kvm_async_pf_hash_reset(vcpu);
1988 return 0;
1989 }
1990
1991 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1992 sizeof(u32)))
1993 return 1;
1994
1995 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1996 kvm_async_pf_wakeup_all(vcpu);
1997 return 0;
1998 }
1999
2000 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2001 {
2002 vcpu->arch.pv_time_enabled = false;
2003 }
2004
2005 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2006 {
2007 u64 delta;
2008
2009 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2010 return;
2011
2012 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2013 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2014 vcpu->arch.st.accum_steal = delta;
2015 }
2016
2017 static void record_steal_time(struct kvm_vcpu *vcpu)
2018 {
2019 accumulate_steal_time(vcpu);
2020
2021 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2022 return;
2023
2024 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2026 return;
2027
2028 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2029 vcpu->arch.st.steal.version += 2;
2030 vcpu->arch.st.accum_steal = 0;
2031
2032 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2033 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2034 }
2035
2036 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2037 {
2038 bool pr = false;
2039 u32 msr = msr_info->index;
2040 u64 data = msr_info->data;
2041
2042 switch (msr) {
2043 case MSR_AMD64_NB_CFG:
2044 case MSR_IA32_UCODE_REV:
2045 case MSR_IA32_UCODE_WRITE:
2046 case MSR_VM_HSAVE_PA:
2047 case MSR_AMD64_PATCH_LOADER:
2048 case MSR_AMD64_BU_CFG2:
2049 break;
2050
2051 case MSR_EFER:
2052 return set_efer(vcpu, data);
2053 case MSR_K7_HWCR:
2054 data &= ~(u64)0x40; /* ignore flush filter disable */
2055 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2056 data &= ~(u64)0x8; /* ignore TLB cache disable */
2057 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2058 if (data != 0) {
2059 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2060 data);
2061 return 1;
2062 }
2063 break;
2064 case MSR_FAM10H_MMIO_CONF_BASE:
2065 if (data != 0) {
2066 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2067 "0x%llx\n", data);
2068 return 1;
2069 }
2070 break;
2071 case MSR_IA32_DEBUGCTLMSR:
2072 if (!data) {
2073 /* We support the non-activated case already */
2074 break;
2075 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2076 /* Values other than LBR and BTF are vendor-specific,
2077 thus reserved and should throw a #GP */
2078 return 1;
2079 }
2080 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2081 __func__, data);
2082 break;
2083 case 0x200 ... 0x2ff:
2084 return kvm_mtrr_set_msr(vcpu, msr, data);
2085 case MSR_IA32_APICBASE:
2086 return kvm_set_apic_base(vcpu, msr_info);
2087 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2088 return kvm_x2apic_msr_write(vcpu, msr, data);
2089 case MSR_IA32_TSCDEADLINE:
2090 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2091 break;
2092 case MSR_IA32_TSC_ADJUST:
2093 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2094 if (!msr_info->host_initiated) {
2095 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2096 adjust_tsc_offset_guest(vcpu, adj);
2097 }
2098 vcpu->arch.ia32_tsc_adjust_msr = data;
2099 }
2100 break;
2101 case MSR_IA32_MISC_ENABLE:
2102 vcpu->arch.ia32_misc_enable_msr = data;
2103 break;
2104 case MSR_IA32_SMBASE:
2105 if (!msr_info->host_initiated)
2106 return 1;
2107 vcpu->arch.smbase = data;
2108 break;
2109 case MSR_KVM_WALL_CLOCK_NEW:
2110 case MSR_KVM_WALL_CLOCK:
2111 vcpu->kvm->arch.wall_clock = data;
2112 kvm_write_wall_clock(vcpu->kvm, data);
2113 break;
2114 case MSR_KVM_SYSTEM_TIME_NEW:
2115 case MSR_KVM_SYSTEM_TIME: {
2116 u64 gpa_offset;
2117 struct kvm_arch *ka = &vcpu->kvm->arch;
2118
2119 kvmclock_reset(vcpu);
2120
2121 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2122 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2123
2124 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2125 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2126 &vcpu->requests);
2127
2128 ka->boot_vcpu_runs_old_kvmclock = tmp;
2129 }
2130
2131 vcpu->arch.time = data;
2132 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2133
2134 /* we verify if the enable bit is set... */
2135 if (!(data & 1))
2136 break;
2137
2138 gpa_offset = data & ~(PAGE_MASK | 1);
2139
2140 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2141 &vcpu->arch.pv_time, data & ~1ULL,
2142 sizeof(struct pvclock_vcpu_time_info)))
2143 vcpu->arch.pv_time_enabled = false;
2144 else
2145 vcpu->arch.pv_time_enabled = true;
2146
2147 break;
2148 }
2149 case MSR_KVM_ASYNC_PF_EN:
2150 if (kvm_pv_enable_async_pf(vcpu, data))
2151 return 1;
2152 break;
2153 case MSR_KVM_STEAL_TIME:
2154
2155 if (unlikely(!sched_info_on()))
2156 return 1;
2157
2158 if (data & KVM_STEAL_RESERVED_MASK)
2159 return 1;
2160
2161 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2162 data & KVM_STEAL_VALID_BITS,
2163 sizeof(struct kvm_steal_time)))
2164 return 1;
2165
2166 vcpu->arch.st.msr_val = data;
2167
2168 if (!(data & KVM_MSR_ENABLED))
2169 break;
2170
2171 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2172
2173 break;
2174 case MSR_KVM_PV_EOI_EN:
2175 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2176 return 1;
2177 break;
2178
2179 case MSR_IA32_MCG_CTL:
2180 case MSR_IA32_MCG_STATUS:
2181 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2182 return set_msr_mce(vcpu, msr, data);
2183
2184 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2185 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2186 pr = true; /* fall through */
2187 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2188 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2189 if (kvm_pmu_is_valid_msr(vcpu, msr))
2190 return kvm_pmu_set_msr(vcpu, msr_info);
2191
2192 if (pr || data != 0)
2193 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2194 "0x%x data 0x%llx\n", msr, data);
2195 break;
2196 case MSR_K7_CLK_CTL:
2197 /*
2198 * Ignore all writes to this no longer documented MSR.
2199 * Writes are only relevant for old K7 processors,
2200 * all pre-dating SVM, but a recommended workaround from
2201 * AMD for these chips. It is possible to specify the
2202 * affected processor models on the command line, hence
2203 * the need to ignore the workaround.
2204 */
2205 break;
2206 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2207 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2208 case HV_X64_MSR_CRASH_CTL:
2209 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2210 return kvm_hv_set_msr_common(vcpu, msr, data,
2211 msr_info->host_initiated);
2212 case MSR_IA32_BBL_CR_CTL3:
2213 /* Drop writes to this legacy MSR -- see rdmsr
2214 * counterpart for further detail.
2215 */
2216 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2217 break;
2218 case MSR_AMD64_OSVW_ID_LENGTH:
2219 if (!guest_cpuid_has_osvw(vcpu))
2220 return 1;
2221 vcpu->arch.osvw.length = data;
2222 break;
2223 case MSR_AMD64_OSVW_STATUS:
2224 if (!guest_cpuid_has_osvw(vcpu))
2225 return 1;
2226 vcpu->arch.osvw.status = data;
2227 break;
2228 default:
2229 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2230 return xen_hvm_config(vcpu, data);
2231 if (kvm_pmu_is_valid_msr(vcpu, msr))
2232 return kvm_pmu_set_msr(vcpu, msr_info);
2233 if (!ignore_msrs) {
2234 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2235 msr, data);
2236 return 1;
2237 } else {
2238 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2239 msr, data);
2240 break;
2241 }
2242 }
2243 return 0;
2244 }
2245 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2246
2247
2248 /*
2249 * Reads an msr value (of 'msr_index') into 'pdata'.
2250 * Returns 0 on success, non-0 otherwise.
2251 * Assumes vcpu_load() was already called.
2252 */
2253 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2254 {
2255 return kvm_x86_ops->get_msr(vcpu, msr);
2256 }
2257 EXPORT_SYMBOL_GPL(kvm_get_msr);
2258
2259 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2260 {
2261 u64 data;
2262 u64 mcg_cap = vcpu->arch.mcg_cap;
2263 unsigned bank_num = mcg_cap & 0xff;
2264
2265 switch (msr) {
2266 case MSR_IA32_P5_MC_ADDR:
2267 case MSR_IA32_P5_MC_TYPE:
2268 data = 0;
2269 break;
2270 case MSR_IA32_MCG_CAP:
2271 data = vcpu->arch.mcg_cap;
2272 break;
2273 case MSR_IA32_MCG_CTL:
2274 if (!(mcg_cap & MCG_CTL_P))
2275 return 1;
2276 data = vcpu->arch.mcg_ctl;
2277 break;
2278 case MSR_IA32_MCG_STATUS:
2279 data = vcpu->arch.mcg_status;
2280 break;
2281 default:
2282 if (msr >= MSR_IA32_MC0_CTL &&
2283 msr < MSR_IA32_MCx_CTL(bank_num)) {
2284 u32 offset = msr - MSR_IA32_MC0_CTL;
2285 data = vcpu->arch.mce_banks[offset];
2286 break;
2287 }
2288 return 1;
2289 }
2290 *pdata = data;
2291 return 0;
2292 }
2293
2294 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2295 {
2296 switch (msr_info->index) {
2297 case MSR_IA32_PLATFORM_ID:
2298 case MSR_IA32_EBL_CR_POWERON:
2299 case MSR_IA32_DEBUGCTLMSR:
2300 case MSR_IA32_LASTBRANCHFROMIP:
2301 case MSR_IA32_LASTBRANCHTOIP:
2302 case MSR_IA32_LASTINTFROMIP:
2303 case MSR_IA32_LASTINTTOIP:
2304 case MSR_K8_SYSCFG:
2305 case MSR_K8_TSEG_ADDR:
2306 case MSR_K8_TSEG_MASK:
2307 case MSR_K7_HWCR:
2308 case MSR_VM_HSAVE_PA:
2309 case MSR_K8_INT_PENDING_MSG:
2310 case MSR_AMD64_NB_CFG:
2311 case MSR_FAM10H_MMIO_CONF_BASE:
2312 case MSR_AMD64_BU_CFG2:
2313 msr_info->data = 0;
2314 break;
2315 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2316 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2317 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2318 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2319 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2320 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2321 msr_info->data = 0;
2322 break;
2323 case MSR_IA32_UCODE_REV:
2324 msr_info->data = 0x100000000ULL;
2325 break;
2326 case MSR_MTRRcap:
2327 case 0x200 ... 0x2ff:
2328 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2329 case 0xcd: /* fsb frequency */
2330 msr_info->data = 3;
2331 break;
2332 /*
2333 * MSR_EBC_FREQUENCY_ID
2334 * Conservative value valid for even the basic CPU models.
2335 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2336 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2337 * and 266MHz for model 3, or 4. Set Core Clock
2338 * Frequency to System Bus Frequency Ratio to 1 (bits
2339 * 31:24) even though these are only valid for CPU
2340 * models > 2, however guests may end up dividing or
2341 * multiplying by zero otherwise.
2342 */
2343 case MSR_EBC_FREQUENCY_ID:
2344 msr_info->data = 1 << 24;
2345 break;
2346 case MSR_IA32_APICBASE:
2347 msr_info->data = kvm_get_apic_base(vcpu);
2348 break;
2349 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2350 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2351 break;
2352 case MSR_IA32_TSCDEADLINE:
2353 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2354 break;
2355 case MSR_IA32_TSC_ADJUST:
2356 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2357 break;
2358 case MSR_IA32_MISC_ENABLE:
2359 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2360 break;
2361 case MSR_IA32_SMBASE:
2362 if (!msr_info->host_initiated)
2363 return 1;
2364 msr_info->data = vcpu->arch.smbase;
2365 break;
2366 case MSR_IA32_PERF_STATUS:
2367 /* TSC increment by tick */
2368 msr_info->data = 1000ULL;
2369 /* CPU multiplier */
2370 msr_info->data |= (((uint64_t)4ULL) << 40);
2371 break;
2372 case MSR_EFER:
2373 msr_info->data = vcpu->arch.efer;
2374 break;
2375 case MSR_KVM_WALL_CLOCK:
2376 case MSR_KVM_WALL_CLOCK_NEW:
2377 msr_info->data = vcpu->kvm->arch.wall_clock;
2378 break;
2379 case MSR_KVM_SYSTEM_TIME:
2380 case MSR_KVM_SYSTEM_TIME_NEW:
2381 msr_info->data = vcpu->arch.time;
2382 break;
2383 case MSR_KVM_ASYNC_PF_EN:
2384 msr_info->data = vcpu->arch.apf.msr_val;
2385 break;
2386 case MSR_KVM_STEAL_TIME:
2387 msr_info->data = vcpu->arch.st.msr_val;
2388 break;
2389 case MSR_KVM_PV_EOI_EN:
2390 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2391 break;
2392 case MSR_IA32_P5_MC_ADDR:
2393 case MSR_IA32_P5_MC_TYPE:
2394 case MSR_IA32_MCG_CAP:
2395 case MSR_IA32_MCG_CTL:
2396 case MSR_IA32_MCG_STATUS:
2397 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2398 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2399 case MSR_K7_CLK_CTL:
2400 /*
2401 * Provide expected ramp-up count for K7. All other
2402 * are set to zero, indicating minimum divisors for
2403 * every field.
2404 *
2405 * This prevents guest kernels on AMD host with CPU
2406 * type 6, model 8 and higher from exploding due to
2407 * the rdmsr failing.
2408 */
2409 msr_info->data = 0x20000000;
2410 break;
2411 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2412 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2413 case HV_X64_MSR_CRASH_CTL:
2414 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2415 return kvm_hv_get_msr_common(vcpu,
2416 msr_info->index, &msr_info->data);
2417 break;
2418 case MSR_IA32_BBL_CR_CTL3:
2419 /* This legacy MSR exists but isn't fully documented in current
2420 * silicon. It is however accessed by winxp in very narrow
2421 * scenarios where it sets bit #19, itself documented as
2422 * a "reserved" bit. Best effort attempt to source coherent
2423 * read data here should the balance of the register be
2424 * interpreted by the guest:
2425 *
2426 * L2 cache control register 3: 64GB range, 256KB size,
2427 * enabled, latency 0x1, configured
2428 */
2429 msr_info->data = 0xbe702111;
2430 break;
2431 case MSR_AMD64_OSVW_ID_LENGTH:
2432 if (!guest_cpuid_has_osvw(vcpu))
2433 return 1;
2434 msr_info->data = vcpu->arch.osvw.length;
2435 break;
2436 case MSR_AMD64_OSVW_STATUS:
2437 if (!guest_cpuid_has_osvw(vcpu))
2438 return 1;
2439 msr_info->data = vcpu->arch.osvw.status;
2440 break;
2441 default:
2442 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2443 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2444 if (!ignore_msrs) {
2445 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2446 return 1;
2447 } else {
2448 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2449 msr_info->data = 0;
2450 }
2451 break;
2452 }
2453 return 0;
2454 }
2455 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2456
2457 /*
2458 * Read or write a bunch of msrs. All parameters are kernel addresses.
2459 *
2460 * @return number of msrs set successfully.
2461 */
2462 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2463 struct kvm_msr_entry *entries,
2464 int (*do_msr)(struct kvm_vcpu *vcpu,
2465 unsigned index, u64 *data))
2466 {
2467 int i, idx;
2468
2469 idx = srcu_read_lock(&vcpu->kvm->srcu);
2470 for (i = 0; i < msrs->nmsrs; ++i)
2471 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2472 break;
2473 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2474
2475 return i;
2476 }
2477
2478 /*
2479 * Read or write a bunch of msrs. Parameters are user addresses.
2480 *
2481 * @return number of msrs set successfully.
2482 */
2483 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2484 int (*do_msr)(struct kvm_vcpu *vcpu,
2485 unsigned index, u64 *data),
2486 int writeback)
2487 {
2488 struct kvm_msrs msrs;
2489 struct kvm_msr_entry *entries;
2490 int r, n;
2491 unsigned size;
2492
2493 r = -EFAULT;
2494 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2495 goto out;
2496
2497 r = -E2BIG;
2498 if (msrs.nmsrs >= MAX_IO_MSRS)
2499 goto out;
2500
2501 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2502 entries = memdup_user(user_msrs->entries, size);
2503 if (IS_ERR(entries)) {
2504 r = PTR_ERR(entries);
2505 goto out;
2506 }
2507
2508 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2509 if (r < 0)
2510 goto out_free;
2511
2512 r = -EFAULT;
2513 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2514 goto out_free;
2515
2516 r = n;
2517
2518 out_free:
2519 kfree(entries);
2520 out:
2521 return r;
2522 }
2523
2524 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2525 {
2526 int r;
2527
2528 switch (ext) {
2529 case KVM_CAP_IRQCHIP:
2530 case KVM_CAP_HLT:
2531 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2532 case KVM_CAP_SET_TSS_ADDR:
2533 case KVM_CAP_EXT_CPUID:
2534 case KVM_CAP_EXT_EMUL_CPUID:
2535 case KVM_CAP_CLOCKSOURCE:
2536 case KVM_CAP_PIT:
2537 case KVM_CAP_NOP_IO_DELAY:
2538 case KVM_CAP_MP_STATE:
2539 case KVM_CAP_SYNC_MMU:
2540 case KVM_CAP_USER_NMI:
2541 case KVM_CAP_REINJECT_CONTROL:
2542 case KVM_CAP_IRQ_INJECT_STATUS:
2543 case KVM_CAP_IOEVENTFD:
2544 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2545 case KVM_CAP_PIT2:
2546 case KVM_CAP_PIT_STATE2:
2547 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2548 case KVM_CAP_XEN_HVM:
2549 case KVM_CAP_ADJUST_CLOCK:
2550 case KVM_CAP_VCPU_EVENTS:
2551 case KVM_CAP_HYPERV:
2552 case KVM_CAP_HYPERV_VAPIC:
2553 case KVM_CAP_HYPERV_SPIN:
2554 case KVM_CAP_HYPERV_SYNIC:
2555 case KVM_CAP_PCI_SEGMENT:
2556 case KVM_CAP_DEBUGREGS:
2557 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2558 case KVM_CAP_XSAVE:
2559 case KVM_CAP_ASYNC_PF:
2560 case KVM_CAP_GET_TSC_KHZ:
2561 case KVM_CAP_KVMCLOCK_CTRL:
2562 case KVM_CAP_READONLY_MEM:
2563 case KVM_CAP_HYPERV_TIME:
2564 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2565 case KVM_CAP_TSC_DEADLINE_TIMER:
2566 case KVM_CAP_ENABLE_CAP_VM:
2567 case KVM_CAP_DISABLE_QUIRKS:
2568 case KVM_CAP_SET_BOOT_CPU_ID:
2569 case KVM_CAP_SPLIT_IRQCHIP:
2570 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2571 case KVM_CAP_ASSIGN_DEV_IRQ:
2572 case KVM_CAP_PCI_2_3:
2573 #endif
2574 r = 1;
2575 break;
2576 case KVM_CAP_X86_SMM:
2577 /* SMBASE is usually relocated above 1M on modern chipsets,
2578 * and SMM handlers might indeed rely on 4G segment limits,
2579 * so do not report SMM to be available if real mode is
2580 * emulated via vm86 mode. Still, do not go to great lengths
2581 * to avoid userspace's usage of the feature, because it is a
2582 * fringe case that is not enabled except via specific settings
2583 * of the module parameters.
2584 */
2585 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2586 break;
2587 case KVM_CAP_COALESCED_MMIO:
2588 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2589 break;
2590 case KVM_CAP_VAPIC:
2591 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2592 break;
2593 case KVM_CAP_NR_VCPUS:
2594 r = KVM_SOFT_MAX_VCPUS;
2595 break;
2596 case KVM_CAP_MAX_VCPUS:
2597 r = KVM_MAX_VCPUS;
2598 break;
2599 case KVM_CAP_NR_MEMSLOTS:
2600 r = KVM_USER_MEM_SLOTS;
2601 break;
2602 case KVM_CAP_PV_MMU: /* obsolete */
2603 r = 0;
2604 break;
2605 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2606 case KVM_CAP_IOMMU:
2607 r = iommu_present(&pci_bus_type);
2608 break;
2609 #endif
2610 case KVM_CAP_MCE:
2611 r = KVM_MAX_MCE_BANKS;
2612 break;
2613 case KVM_CAP_XCRS:
2614 r = cpu_has_xsave;
2615 break;
2616 case KVM_CAP_TSC_CONTROL:
2617 r = kvm_has_tsc_control;
2618 break;
2619 default:
2620 r = 0;
2621 break;
2622 }
2623 return r;
2624
2625 }
2626
2627 long kvm_arch_dev_ioctl(struct file *filp,
2628 unsigned int ioctl, unsigned long arg)
2629 {
2630 void __user *argp = (void __user *)arg;
2631 long r;
2632
2633 switch (ioctl) {
2634 case KVM_GET_MSR_INDEX_LIST: {
2635 struct kvm_msr_list __user *user_msr_list = argp;
2636 struct kvm_msr_list msr_list;
2637 unsigned n;
2638
2639 r = -EFAULT;
2640 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2641 goto out;
2642 n = msr_list.nmsrs;
2643 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2644 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2645 goto out;
2646 r = -E2BIG;
2647 if (n < msr_list.nmsrs)
2648 goto out;
2649 r = -EFAULT;
2650 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2651 num_msrs_to_save * sizeof(u32)))
2652 goto out;
2653 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2654 &emulated_msrs,
2655 num_emulated_msrs * sizeof(u32)))
2656 goto out;
2657 r = 0;
2658 break;
2659 }
2660 case KVM_GET_SUPPORTED_CPUID:
2661 case KVM_GET_EMULATED_CPUID: {
2662 struct kvm_cpuid2 __user *cpuid_arg = argp;
2663 struct kvm_cpuid2 cpuid;
2664
2665 r = -EFAULT;
2666 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2667 goto out;
2668
2669 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2670 ioctl);
2671 if (r)
2672 goto out;
2673
2674 r = -EFAULT;
2675 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2676 goto out;
2677 r = 0;
2678 break;
2679 }
2680 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2681 u64 mce_cap;
2682
2683 mce_cap = KVM_MCE_CAP_SUPPORTED;
2684 r = -EFAULT;
2685 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2686 goto out;
2687 r = 0;
2688 break;
2689 }
2690 default:
2691 r = -EINVAL;
2692 }
2693 out:
2694 return r;
2695 }
2696
2697 static void wbinvd_ipi(void *garbage)
2698 {
2699 wbinvd();
2700 }
2701
2702 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2703 {
2704 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2705 }
2706
2707 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2708 {
2709 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2710 }
2711
2712 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2713 {
2714 /* Address WBINVD may be executed by guest */
2715 if (need_emulate_wbinvd(vcpu)) {
2716 if (kvm_x86_ops->has_wbinvd_exit())
2717 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2718 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2719 smp_call_function_single(vcpu->cpu,
2720 wbinvd_ipi, NULL, 1);
2721 }
2722
2723 kvm_x86_ops->vcpu_load(vcpu, cpu);
2724
2725 /* Apply any externally detected TSC adjustments (due to suspend) */
2726 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2727 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2728 vcpu->arch.tsc_offset_adjustment = 0;
2729 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2730 }
2731
2732 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2733 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2734 rdtsc() - vcpu->arch.last_host_tsc;
2735 if (tsc_delta < 0)
2736 mark_tsc_unstable("KVM discovered backwards TSC");
2737 if (check_tsc_unstable()) {
2738 u64 offset = kvm_compute_tsc_offset(vcpu,
2739 vcpu->arch.last_guest_tsc);
2740 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2741 vcpu->arch.tsc_catchup = 1;
2742 }
2743 /*
2744 * On a host with synchronized TSC, there is no need to update
2745 * kvmclock on vcpu->cpu migration
2746 */
2747 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2748 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2749 if (vcpu->cpu != cpu)
2750 kvm_migrate_timers(vcpu);
2751 vcpu->cpu = cpu;
2752 }
2753
2754 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2755 }
2756
2757 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2758 {
2759 kvm_x86_ops->vcpu_put(vcpu);
2760 kvm_put_guest_fpu(vcpu);
2761 vcpu->arch.last_host_tsc = rdtsc();
2762 }
2763
2764 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2765 struct kvm_lapic_state *s)
2766 {
2767 if (vcpu->arch.apicv_active)
2768 kvm_x86_ops->sync_pir_to_irr(vcpu);
2769
2770 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2771
2772 return 0;
2773 }
2774
2775 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2776 struct kvm_lapic_state *s)
2777 {
2778 kvm_apic_post_state_restore(vcpu, s);
2779 update_cr8_intercept(vcpu);
2780
2781 return 0;
2782 }
2783
2784 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2785 {
2786 return (!lapic_in_kernel(vcpu) ||
2787 kvm_apic_accept_pic_intr(vcpu));
2788 }
2789
2790 /*
2791 * if userspace requested an interrupt window, check that the
2792 * interrupt window is open.
2793 *
2794 * No need to exit to userspace if we already have an interrupt queued.
2795 */
2796 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2797 {
2798 return kvm_arch_interrupt_allowed(vcpu) &&
2799 !kvm_cpu_has_interrupt(vcpu) &&
2800 !kvm_event_needs_reinjection(vcpu) &&
2801 kvm_cpu_accept_dm_intr(vcpu);
2802 }
2803
2804 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2805 struct kvm_interrupt *irq)
2806 {
2807 if (irq->irq >= KVM_NR_INTERRUPTS)
2808 return -EINVAL;
2809
2810 if (!irqchip_in_kernel(vcpu->kvm)) {
2811 kvm_queue_interrupt(vcpu, irq->irq, false);
2812 kvm_make_request(KVM_REQ_EVENT, vcpu);
2813 return 0;
2814 }
2815
2816 /*
2817 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2818 * fail for in-kernel 8259.
2819 */
2820 if (pic_in_kernel(vcpu->kvm))
2821 return -ENXIO;
2822
2823 if (vcpu->arch.pending_external_vector != -1)
2824 return -EEXIST;
2825
2826 vcpu->arch.pending_external_vector = irq->irq;
2827 kvm_make_request(KVM_REQ_EVENT, vcpu);
2828 return 0;
2829 }
2830
2831 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2832 {
2833 kvm_inject_nmi(vcpu);
2834
2835 return 0;
2836 }
2837
2838 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2839 {
2840 kvm_make_request(KVM_REQ_SMI, vcpu);
2841
2842 return 0;
2843 }
2844
2845 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2846 struct kvm_tpr_access_ctl *tac)
2847 {
2848 if (tac->flags)
2849 return -EINVAL;
2850 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2851 return 0;
2852 }
2853
2854 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2855 u64 mcg_cap)
2856 {
2857 int r;
2858 unsigned bank_num = mcg_cap & 0xff, bank;
2859
2860 r = -EINVAL;
2861 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2862 goto out;
2863 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2864 goto out;
2865 r = 0;
2866 vcpu->arch.mcg_cap = mcg_cap;
2867 /* Init IA32_MCG_CTL to all 1s */
2868 if (mcg_cap & MCG_CTL_P)
2869 vcpu->arch.mcg_ctl = ~(u64)0;
2870 /* Init IA32_MCi_CTL to all 1s */
2871 for (bank = 0; bank < bank_num; bank++)
2872 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2873 out:
2874 return r;
2875 }
2876
2877 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2878 struct kvm_x86_mce *mce)
2879 {
2880 u64 mcg_cap = vcpu->arch.mcg_cap;
2881 unsigned bank_num = mcg_cap & 0xff;
2882 u64 *banks = vcpu->arch.mce_banks;
2883
2884 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2885 return -EINVAL;
2886 /*
2887 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2888 * reporting is disabled
2889 */
2890 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2891 vcpu->arch.mcg_ctl != ~(u64)0)
2892 return 0;
2893 banks += 4 * mce->bank;
2894 /*
2895 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2896 * reporting is disabled for the bank
2897 */
2898 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2899 return 0;
2900 if (mce->status & MCI_STATUS_UC) {
2901 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2902 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2903 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2904 return 0;
2905 }
2906 if (banks[1] & MCI_STATUS_VAL)
2907 mce->status |= MCI_STATUS_OVER;
2908 banks[2] = mce->addr;
2909 banks[3] = mce->misc;
2910 vcpu->arch.mcg_status = mce->mcg_status;
2911 banks[1] = mce->status;
2912 kvm_queue_exception(vcpu, MC_VECTOR);
2913 } else if (!(banks[1] & MCI_STATUS_VAL)
2914 || !(banks[1] & MCI_STATUS_UC)) {
2915 if (banks[1] & MCI_STATUS_VAL)
2916 mce->status |= MCI_STATUS_OVER;
2917 banks[2] = mce->addr;
2918 banks[3] = mce->misc;
2919 banks[1] = mce->status;
2920 } else
2921 banks[1] |= MCI_STATUS_OVER;
2922 return 0;
2923 }
2924
2925 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2926 struct kvm_vcpu_events *events)
2927 {
2928 process_nmi(vcpu);
2929 events->exception.injected =
2930 vcpu->arch.exception.pending &&
2931 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2932 events->exception.nr = vcpu->arch.exception.nr;
2933 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2934 events->exception.pad = 0;
2935 events->exception.error_code = vcpu->arch.exception.error_code;
2936
2937 events->interrupt.injected =
2938 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2939 events->interrupt.nr = vcpu->arch.interrupt.nr;
2940 events->interrupt.soft = 0;
2941 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2942
2943 events->nmi.injected = vcpu->arch.nmi_injected;
2944 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2945 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2946 events->nmi.pad = 0;
2947
2948 events->sipi_vector = 0; /* never valid when reporting to user space */
2949
2950 events->smi.smm = is_smm(vcpu);
2951 events->smi.pending = vcpu->arch.smi_pending;
2952 events->smi.smm_inside_nmi =
2953 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2954 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2955
2956 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2957 | KVM_VCPUEVENT_VALID_SHADOW
2958 | KVM_VCPUEVENT_VALID_SMM);
2959 memset(&events->reserved, 0, sizeof(events->reserved));
2960 }
2961
2962 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2963 struct kvm_vcpu_events *events)
2964 {
2965 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2966 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2967 | KVM_VCPUEVENT_VALID_SHADOW
2968 | KVM_VCPUEVENT_VALID_SMM))
2969 return -EINVAL;
2970
2971 process_nmi(vcpu);
2972 vcpu->arch.exception.pending = events->exception.injected;
2973 vcpu->arch.exception.nr = events->exception.nr;
2974 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2975 vcpu->arch.exception.error_code = events->exception.error_code;
2976
2977 vcpu->arch.interrupt.pending = events->interrupt.injected;
2978 vcpu->arch.interrupt.nr = events->interrupt.nr;
2979 vcpu->arch.interrupt.soft = events->interrupt.soft;
2980 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2981 kvm_x86_ops->set_interrupt_shadow(vcpu,
2982 events->interrupt.shadow);
2983
2984 vcpu->arch.nmi_injected = events->nmi.injected;
2985 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2986 vcpu->arch.nmi_pending = events->nmi.pending;
2987 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2988
2989 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2990 kvm_vcpu_has_lapic(vcpu))
2991 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2992
2993 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2994 if (events->smi.smm)
2995 vcpu->arch.hflags |= HF_SMM_MASK;
2996 else
2997 vcpu->arch.hflags &= ~HF_SMM_MASK;
2998 vcpu->arch.smi_pending = events->smi.pending;
2999 if (events->smi.smm_inside_nmi)
3000 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3001 else
3002 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3003 if (kvm_vcpu_has_lapic(vcpu)) {
3004 if (events->smi.latched_init)
3005 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3006 else
3007 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3008 }
3009 }
3010
3011 kvm_make_request(KVM_REQ_EVENT, vcpu);
3012
3013 return 0;
3014 }
3015
3016 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3017 struct kvm_debugregs *dbgregs)
3018 {
3019 unsigned long val;
3020
3021 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3022 kvm_get_dr(vcpu, 6, &val);
3023 dbgregs->dr6 = val;
3024 dbgregs->dr7 = vcpu->arch.dr7;
3025 dbgregs->flags = 0;
3026 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3027 }
3028
3029 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3030 struct kvm_debugregs *dbgregs)
3031 {
3032 if (dbgregs->flags)
3033 return -EINVAL;
3034
3035 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3036 kvm_update_dr0123(vcpu);
3037 vcpu->arch.dr6 = dbgregs->dr6;
3038 kvm_update_dr6(vcpu);
3039 vcpu->arch.dr7 = dbgregs->dr7;
3040 kvm_update_dr7(vcpu);
3041
3042 return 0;
3043 }
3044
3045 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3046
3047 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3048 {
3049 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3050 u64 xstate_bv = xsave->header.xfeatures;
3051 u64 valid;
3052
3053 /*
3054 * Copy legacy XSAVE area, to avoid complications with CPUID
3055 * leaves 0 and 1 in the loop below.
3056 */
3057 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3058
3059 /* Set XSTATE_BV */
3060 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3061
3062 /*
3063 * Copy each region from the possibly compacted offset to the
3064 * non-compacted offset.
3065 */
3066 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3067 while (valid) {
3068 u64 feature = valid & -valid;
3069 int index = fls64(feature) - 1;
3070 void *src = get_xsave_addr(xsave, feature);
3071
3072 if (src) {
3073 u32 size, offset, ecx, edx;
3074 cpuid_count(XSTATE_CPUID, index,
3075 &size, &offset, &ecx, &edx);
3076 memcpy(dest + offset, src, size);
3077 }
3078
3079 valid -= feature;
3080 }
3081 }
3082
3083 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3084 {
3085 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3086 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3087 u64 valid;
3088
3089 /*
3090 * Copy legacy XSAVE area, to avoid complications with CPUID
3091 * leaves 0 and 1 in the loop below.
3092 */
3093 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3094
3095 /* Set XSTATE_BV and possibly XCOMP_BV. */
3096 xsave->header.xfeatures = xstate_bv;
3097 if (cpu_has_xsaves)
3098 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3099
3100 /*
3101 * Copy each region from the non-compacted offset to the
3102 * possibly compacted offset.
3103 */
3104 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3105 while (valid) {
3106 u64 feature = valid & -valid;
3107 int index = fls64(feature) - 1;
3108 void *dest = get_xsave_addr(xsave, feature);
3109
3110 if (dest) {
3111 u32 size, offset, ecx, edx;
3112 cpuid_count(XSTATE_CPUID, index,
3113 &size, &offset, &ecx, &edx);
3114 memcpy(dest, src + offset, size);
3115 }
3116
3117 valid -= feature;
3118 }
3119 }
3120
3121 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3122 struct kvm_xsave *guest_xsave)
3123 {
3124 if (cpu_has_xsave) {
3125 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3126 fill_xsave((u8 *) guest_xsave->region, vcpu);
3127 } else {
3128 memcpy(guest_xsave->region,
3129 &vcpu->arch.guest_fpu.state.fxsave,
3130 sizeof(struct fxregs_state));
3131 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3132 XFEATURE_MASK_FPSSE;
3133 }
3134 }
3135
3136 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3137 struct kvm_xsave *guest_xsave)
3138 {
3139 u64 xstate_bv =
3140 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3141
3142 if (cpu_has_xsave) {
3143 /*
3144 * Here we allow setting states that are not present in
3145 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3146 * with old userspace.
3147 */
3148 if (xstate_bv & ~kvm_supported_xcr0())
3149 return -EINVAL;
3150 load_xsave(vcpu, (u8 *)guest_xsave->region);
3151 } else {
3152 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3153 return -EINVAL;
3154 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3155 guest_xsave->region, sizeof(struct fxregs_state));
3156 }
3157 return 0;
3158 }
3159
3160 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3161 struct kvm_xcrs *guest_xcrs)
3162 {
3163 if (!cpu_has_xsave) {
3164 guest_xcrs->nr_xcrs = 0;
3165 return;
3166 }
3167
3168 guest_xcrs->nr_xcrs = 1;
3169 guest_xcrs->flags = 0;
3170 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3171 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3172 }
3173
3174 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3175 struct kvm_xcrs *guest_xcrs)
3176 {
3177 int i, r = 0;
3178
3179 if (!cpu_has_xsave)
3180 return -EINVAL;
3181
3182 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3183 return -EINVAL;
3184
3185 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3186 /* Only support XCR0 currently */
3187 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3188 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3189 guest_xcrs->xcrs[i].value);
3190 break;
3191 }
3192 if (r)
3193 r = -EINVAL;
3194 return r;
3195 }
3196
3197 /*
3198 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3199 * stopped by the hypervisor. This function will be called from the host only.
3200 * EINVAL is returned when the host attempts to set the flag for a guest that
3201 * does not support pv clocks.
3202 */
3203 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3204 {
3205 if (!vcpu->arch.pv_time_enabled)
3206 return -EINVAL;
3207 vcpu->arch.pvclock_set_guest_stopped_request = true;
3208 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3209 return 0;
3210 }
3211
3212 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3213 struct kvm_enable_cap *cap)
3214 {
3215 if (cap->flags)
3216 return -EINVAL;
3217
3218 switch (cap->cap) {
3219 case KVM_CAP_HYPERV_SYNIC:
3220 return kvm_hv_activate_synic(vcpu);
3221 default:
3222 return -EINVAL;
3223 }
3224 }
3225
3226 long kvm_arch_vcpu_ioctl(struct file *filp,
3227 unsigned int ioctl, unsigned long arg)
3228 {
3229 struct kvm_vcpu *vcpu = filp->private_data;
3230 void __user *argp = (void __user *)arg;
3231 int r;
3232 union {
3233 struct kvm_lapic_state *lapic;
3234 struct kvm_xsave *xsave;
3235 struct kvm_xcrs *xcrs;
3236 void *buffer;
3237 } u;
3238
3239 u.buffer = NULL;
3240 switch (ioctl) {
3241 case KVM_GET_LAPIC: {
3242 r = -EINVAL;
3243 if (!vcpu->arch.apic)
3244 goto out;
3245 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3246
3247 r = -ENOMEM;
3248 if (!u.lapic)
3249 goto out;
3250 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3251 if (r)
3252 goto out;
3253 r = -EFAULT;
3254 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3255 goto out;
3256 r = 0;
3257 break;
3258 }
3259 case KVM_SET_LAPIC: {
3260 r = -EINVAL;
3261 if (!vcpu->arch.apic)
3262 goto out;
3263 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3264 if (IS_ERR(u.lapic))
3265 return PTR_ERR(u.lapic);
3266
3267 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3268 break;
3269 }
3270 case KVM_INTERRUPT: {
3271 struct kvm_interrupt irq;
3272
3273 r = -EFAULT;
3274 if (copy_from_user(&irq, argp, sizeof irq))
3275 goto out;
3276 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3277 break;
3278 }
3279 case KVM_NMI: {
3280 r = kvm_vcpu_ioctl_nmi(vcpu);
3281 break;
3282 }
3283 case KVM_SMI: {
3284 r = kvm_vcpu_ioctl_smi(vcpu);
3285 break;
3286 }
3287 case KVM_SET_CPUID: {
3288 struct kvm_cpuid __user *cpuid_arg = argp;
3289 struct kvm_cpuid cpuid;
3290
3291 r = -EFAULT;
3292 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3293 goto out;
3294 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3295 break;
3296 }
3297 case KVM_SET_CPUID2: {
3298 struct kvm_cpuid2 __user *cpuid_arg = argp;
3299 struct kvm_cpuid2 cpuid;
3300
3301 r = -EFAULT;
3302 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3303 goto out;
3304 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3305 cpuid_arg->entries);
3306 break;
3307 }
3308 case KVM_GET_CPUID2: {
3309 struct kvm_cpuid2 __user *cpuid_arg = argp;
3310 struct kvm_cpuid2 cpuid;
3311
3312 r = -EFAULT;
3313 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3314 goto out;
3315 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3316 cpuid_arg->entries);
3317 if (r)
3318 goto out;
3319 r = -EFAULT;
3320 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3321 goto out;
3322 r = 0;
3323 break;
3324 }
3325 case KVM_GET_MSRS:
3326 r = msr_io(vcpu, argp, do_get_msr, 1);
3327 break;
3328 case KVM_SET_MSRS:
3329 r = msr_io(vcpu, argp, do_set_msr, 0);
3330 break;
3331 case KVM_TPR_ACCESS_REPORTING: {
3332 struct kvm_tpr_access_ctl tac;
3333
3334 r = -EFAULT;
3335 if (copy_from_user(&tac, argp, sizeof tac))
3336 goto out;
3337 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3338 if (r)
3339 goto out;
3340 r = -EFAULT;
3341 if (copy_to_user(argp, &tac, sizeof tac))
3342 goto out;
3343 r = 0;
3344 break;
3345 };
3346 case KVM_SET_VAPIC_ADDR: {
3347 struct kvm_vapic_addr va;
3348
3349 r = -EINVAL;
3350 if (!lapic_in_kernel(vcpu))
3351 goto out;
3352 r = -EFAULT;
3353 if (copy_from_user(&va, argp, sizeof va))
3354 goto out;
3355 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3356 break;
3357 }
3358 case KVM_X86_SETUP_MCE: {
3359 u64 mcg_cap;
3360
3361 r = -EFAULT;
3362 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3363 goto out;
3364 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3365 break;
3366 }
3367 case KVM_X86_SET_MCE: {
3368 struct kvm_x86_mce mce;
3369
3370 r = -EFAULT;
3371 if (copy_from_user(&mce, argp, sizeof mce))
3372 goto out;
3373 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3374 break;
3375 }
3376 case KVM_GET_VCPU_EVENTS: {
3377 struct kvm_vcpu_events events;
3378
3379 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3380
3381 r = -EFAULT;
3382 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3383 break;
3384 r = 0;
3385 break;
3386 }
3387 case KVM_SET_VCPU_EVENTS: {
3388 struct kvm_vcpu_events events;
3389
3390 r = -EFAULT;
3391 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3392 break;
3393
3394 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3395 break;
3396 }
3397 case KVM_GET_DEBUGREGS: {
3398 struct kvm_debugregs dbgregs;
3399
3400 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3401
3402 r = -EFAULT;
3403 if (copy_to_user(argp, &dbgregs,
3404 sizeof(struct kvm_debugregs)))
3405 break;
3406 r = 0;
3407 break;
3408 }
3409 case KVM_SET_DEBUGREGS: {
3410 struct kvm_debugregs dbgregs;
3411
3412 r = -EFAULT;
3413 if (copy_from_user(&dbgregs, argp,
3414 sizeof(struct kvm_debugregs)))
3415 break;
3416
3417 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3418 break;
3419 }
3420 case KVM_GET_XSAVE: {
3421 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3422 r = -ENOMEM;
3423 if (!u.xsave)
3424 break;
3425
3426 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3427
3428 r = -EFAULT;
3429 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3430 break;
3431 r = 0;
3432 break;
3433 }
3434 case KVM_SET_XSAVE: {
3435 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3436 if (IS_ERR(u.xsave))
3437 return PTR_ERR(u.xsave);
3438
3439 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3440 break;
3441 }
3442 case KVM_GET_XCRS: {
3443 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3444 r = -ENOMEM;
3445 if (!u.xcrs)
3446 break;
3447
3448 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3449
3450 r = -EFAULT;
3451 if (copy_to_user(argp, u.xcrs,
3452 sizeof(struct kvm_xcrs)))
3453 break;
3454 r = 0;
3455 break;
3456 }
3457 case KVM_SET_XCRS: {
3458 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3459 if (IS_ERR(u.xcrs))
3460 return PTR_ERR(u.xcrs);
3461
3462 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3463 break;
3464 }
3465 case KVM_SET_TSC_KHZ: {
3466 u32 user_tsc_khz;
3467
3468 r = -EINVAL;
3469 user_tsc_khz = (u32)arg;
3470
3471 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3472 goto out;
3473
3474 if (user_tsc_khz == 0)
3475 user_tsc_khz = tsc_khz;
3476
3477 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3478 r = 0;
3479
3480 goto out;
3481 }
3482 case KVM_GET_TSC_KHZ: {
3483 r = vcpu->arch.virtual_tsc_khz;
3484 goto out;
3485 }
3486 case KVM_KVMCLOCK_CTRL: {
3487 r = kvm_set_guest_paused(vcpu);
3488 goto out;
3489 }
3490 case KVM_ENABLE_CAP: {
3491 struct kvm_enable_cap cap;
3492
3493 r = -EFAULT;
3494 if (copy_from_user(&cap, argp, sizeof(cap)))
3495 goto out;
3496 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3497 break;
3498 }
3499 default:
3500 r = -EINVAL;
3501 }
3502 out:
3503 kfree(u.buffer);
3504 return r;
3505 }
3506
3507 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3508 {
3509 return VM_FAULT_SIGBUS;
3510 }
3511
3512 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3513 {
3514 int ret;
3515
3516 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3517 return -EINVAL;
3518 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3519 return ret;
3520 }
3521
3522 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3523 u64 ident_addr)
3524 {
3525 kvm->arch.ept_identity_map_addr = ident_addr;
3526 return 0;
3527 }
3528
3529 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3530 u32 kvm_nr_mmu_pages)
3531 {
3532 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3533 return -EINVAL;
3534
3535 mutex_lock(&kvm->slots_lock);
3536
3537 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3538 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3539
3540 mutex_unlock(&kvm->slots_lock);
3541 return 0;
3542 }
3543
3544 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3545 {
3546 return kvm->arch.n_max_mmu_pages;
3547 }
3548
3549 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3550 {
3551 int r;
3552
3553 r = 0;
3554 switch (chip->chip_id) {
3555 case KVM_IRQCHIP_PIC_MASTER:
3556 memcpy(&chip->chip.pic,
3557 &pic_irqchip(kvm)->pics[0],
3558 sizeof(struct kvm_pic_state));
3559 break;
3560 case KVM_IRQCHIP_PIC_SLAVE:
3561 memcpy(&chip->chip.pic,
3562 &pic_irqchip(kvm)->pics[1],
3563 sizeof(struct kvm_pic_state));
3564 break;
3565 case KVM_IRQCHIP_IOAPIC:
3566 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3567 break;
3568 default:
3569 r = -EINVAL;
3570 break;
3571 }
3572 return r;
3573 }
3574
3575 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3576 {
3577 int r;
3578
3579 r = 0;
3580 switch (chip->chip_id) {
3581 case KVM_IRQCHIP_PIC_MASTER:
3582 spin_lock(&pic_irqchip(kvm)->lock);
3583 memcpy(&pic_irqchip(kvm)->pics[0],
3584 &chip->chip.pic,
3585 sizeof(struct kvm_pic_state));
3586 spin_unlock(&pic_irqchip(kvm)->lock);
3587 break;
3588 case KVM_IRQCHIP_PIC_SLAVE:
3589 spin_lock(&pic_irqchip(kvm)->lock);
3590 memcpy(&pic_irqchip(kvm)->pics[1],
3591 &chip->chip.pic,
3592 sizeof(struct kvm_pic_state));
3593 spin_unlock(&pic_irqchip(kvm)->lock);
3594 break;
3595 case KVM_IRQCHIP_IOAPIC:
3596 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3597 break;
3598 default:
3599 r = -EINVAL;
3600 break;
3601 }
3602 kvm_pic_update_irq(pic_irqchip(kvm));
3603 return r;
3604 }
3605
3606 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3607 {
3608 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3609 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3610 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3611 return 0;
3612 }
3613
3614 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3615 {
3616 int i;
3617 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3618 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3619 for (i = 0; i < 3; i++)
3620 kvm_pit_load_count(kvm, i, ps->channels[i].count, 0);
3621 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3622 return 0;
3623 }
3624
3625 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3626 {
3627 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3628 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3629 sizeof(ps->channels));
3630 ps->flags = kvm->arch.vpit->pit_state.flags;
3631 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3632 memset(&ps->reserved, 0, sizeof(ps->reserved));
3633 return 0;
3634 }
3635
3636 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3637 {
3638 int start = 0;
3639 int i;
3640 u32 prev_legacy, cur_legacy;
3641 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3642 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3643 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3644 if (!prev_legacy && cur_legacy)
3645 start = 1;
3646 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3647 sizeof(kvm->arch.vpit->pit_state.channels));
3648 kvm->arch.vpit->pit_state.flags = ps->flags;
3649 for (i = 0; i < 3; i++)
3650 kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count,
3651 start && i == 0);
3652 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3653 return 0;
3654 }
3655
3656 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3657 struct kvm_reinject_control *control)
3658 {
3659 if (!kvm->arch.vpit)
3660 return -ENXIO;
3661 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3662 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3663 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3664 return 0;
3665 }
3666
3667 /**
3668 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3669 * @kvm: kvm instance
3670 * @log: slot id and address to which we copy the log
3671 *
3672 * Steps 1-4 below provide general overview of dirty page logging. See
3673 * kvm_get_dirty_log_protect() function description for additional details.
3674 *
3675 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3676 * always flush the TLB (step 4) even if previous step failed and the dirty
3677 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3678 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3679 * writes will be marked dirty for next log read.
3680 *
3681 * 1. Take a snapshot of the bit and clear it if needed.
3682 * 2. Write protect the corresponding page.
3683 * 3. Copy the snapshot to the userspace.
3684 * 4. Flush TLB's if needed.
3685 */
3686 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3687 {
3688 bool is_dirty = false;
3689 int r;
3690
3691 mutex_lock(&kvm->slots_lock);
3692
3693 /*
3694 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3695 */
3696 if (kvm_x86_ops->flush_log_dirty)
3697 kvm_x86_ops->flush_log_dirty(kvm);
3698
3699 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3700
3701 /*
3702 * All the TLBs can be flushed out of mmu lock, see the comments in
3703 * kvm_mmu_slot_remove_write_access().
3704 */
3705 lockdep_assert_held(&kvm->slots_lock);
3706 if (is_dirty)
3707 kvm_flush_remote_tlbs(kvm);
3708
3709 mutex_unlock(&kvm->slots_lock);
3710 return r;
3711 }
3712
3713 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3714 bool line_status)
3715 {
3716 if (!irqchip_in_kernel(kvm))
3717 return -ENXIO;
3718
3719 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3720 irq_event->irq, irq_event->level,
3721 line_status);
3722 return 0;
3723 }
3724
3725 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3726 struct kvm_enable_cap *cap)
3727 {
3728 int r;
3729
3730 if (cap->flags)
3731 return -EINVAL;
3732
3733 switch (cap->cap) {
3734 case KVM_CAP_DISABLE_QUIRKS:
3735 kvm->arch.disabled_quirks = cap->args[0];
3736 r = 0;
3737 break;
3738 case KVM_CAP_SPLIT_IRQCHIP: {
3739 mutex_lock(&kvm->lock);
3740 r = -EINVAL;
3741 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3742 goto split_irqchip_unlock;
3743 r = -EEXIST;
3744 if (irqchip_in_kernel(kvm))
3745 goto split_irqchip_unlock;
3746 if (atomic_read(&kvm->online_vcpus))
3747 goto split_irqchip_unlock;
3748 r = kvm_setup_empty_irq_routing(kvm);
3749 if (r)
3750 goto split_irqchip_unlock;
3751 /* Pairs with irqchip_in_kernel. */
3752 smp_wmb();
3753 kvm->arch.irqchip_split = true;
3754 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3755 r = 0;
3756 split_irqchip_unlock:
3757 mutex_unlock(&kvm->lock);
3758 break;
3759 }
3760 default:
3761 r = -EINVAL;
3762 break;
3763 }
3764 return r;
3765 }
3766
3767 long kvm_arch_vm_ioctl(struct file *filp,
3768 unsigned int ioctl, unsigned long arg)
3769 {
3770 struct kvm *kvm = filp->private_data;
3771 void __user *argp = (void __user *)arg;
3772 int r = -ENOTTY;
3773 /*
3774 * This union makes it completely explicit to gcc-3.x
3775 * that these two variables' stack usage should be
3776 * combined, not added together.
3777 */
3778 union {
3779 struct kvm_pit_state ps;
3780 struct kvm_pit_state2 ps2;
3781 struct kvm_pit_config pit_config;
3782 } u;
3783
3784 switch (ioctl) {
3785 case KVM_SET_TSS_ADDR:
3786 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3787 break;
3788 case KVM_SET_IDENTITY_MAP_ADDR: {
3789 u64 ident_addr;
3790
3791 r = -EFAULT;
3792 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3793 goto out;
3794 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3795 break;
3796 }
3797 case KVM_SET_NR_MMU_PAGES:
3798 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3799 break;
3800 case KVM_GET_NR_MMU_PAGES:
3801 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3802 break;
3803 case KVM_CREATE_IRQCHIP: {
3804 struct kvm_pic *vpic;
3805
3806 mutex_lock(&kvm->lock);
3807 r = -EEXIST;
3808 if (kvm->arch.vpic)
3809 goto create_irqchip_unlock;
3810 r = -EINVAL;
3811 if (atomic_read(&kvm->online_vcpus))
3812 goto create_irqchip_unlock;
3813 r = -ENOMEM;
3814 vpic = kvm_create_pic(kvm);
3815 if (vpic) {
3816 r = kvm_ioapic_init(kvm);
3817 if (r) {
3818 mutex_lock(&kvm->slots_lock);
3819 kvm_destroy_pic(vpic);
3820 mutex_unlock(&kvm->slots_lock);
3821 goto create_irqchip_unlock;
3822 }
3823 } else
3824 goto create_irqchip_unlock;
3825 r = kvm_setup_default_irq_routing(kvm);
3826 if (r) {
3827 mutex_lock(&kvm->slots_lock);
3828 mutex_lock(&kvm->irq_lock);
3829 kvm_ioapic_destroy(kvm);
3830 kvm_destroy_pic(vpic);
3831 mutex_unlock(&kvm->irq_lock);
3832 mutex_unlock(&kvm->slots_lock);
3833 goto create_irqchip_unlock;
3834 }
3835 /* Write kvm->irq_routing before kvm->arch.vpic. */
3836 smp_wmb();
3837 kvm->arch.vpic = vpic;
3838 create_irqchip_unlock:
3839 mutex_unlock(&kvm->lock);
3840 break;
3841 }
3842 case KVM_CREATE_PIT:
3843 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3844 goto create_pit;
3845 case KVM_CREATE_PIT2:
3846 r = -EFAULT;
3847 if (copy_from_user(&u.pit_config, argp,
3848 sizeof(struct kvm_pit_config)))
3849 goto out;
3850 create_pit:
3851 mutex_lock(&kvm->slots_lock);
3852 r = -EEXIST;
3853 if (kvm->arch.vpit)
3854 goto create_pit_unlock;
3855 r = -ENOMEM;
3856 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3857 if (kvm->arch.vpit)
3858 r = 0;
3859 create_pit_unlock:
3860 mutex_unlock(&kvm->slots_lock);
3861 break;
3862 case KVM_GET_IRQCHIP: {
3863 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3864 struct kvm_irqchip *chip;
3865
3866 chip = memdup_user(argp, sizeof(*chip));
3867 if (IS_ERR(chip)) {
3868 r = PTR_ERR(chip);
3869 goto out;
3870 }
3871
3872 r = -ENXIO;
3873 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3874 goto get_irqchip_out;
3875 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3876 if (r)
3877 goto get_irqchip_out;
3878 r = -EFAULT;
3879 if (copy_to_user(argp, chip, sizeof *chip))
3880 goto get_irqchip_out;
3881 r = 0;
3882 get_irqchip_out:
3883 kfree(chip);
3884 break;
3885 }
3886 case KVM_SET_IRQCHIP: {
3887 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3888 struct kvm_irqchip *chip;
3889
3890 chip = memdup_user(argp, sizeof(*chip));
3891 if (IS_ERR(chip)) {
3892 r = PTR_ERR(chip);
3893 goto out;
3894 }
3895
3896 r = -ENXIO;
3897 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3898 goto set_irqchip_out;
3899 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3900 if (r)
3901 goto set_irqchip_out;
3902 r = 0;
3903 set_irqchip_out:
3904 kfree(chip);
3905 break;
3906 }
3907 case KVM_GET_PIT: {
3908 r = -EFAULT;
3909 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3910 goto out;
3911 r = -ENXIO;
3912 if (!kvm->arch.vpit)
3913 goto out;
3914 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3915 if (r)
3916 goto out;
3917 r = -EFAULT;
3918 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3919 goto out;
3920 r = 0;
3921 break;
3922 }
3923 case KVM_SET_PIT: {
3924 r = -EFAULT;
3925 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3926 goto out;
3927 r = -ENXIO;
3928 if (!kvm->arch.vpit)
3929 goto out;
3930 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3931 break;
3932 }
3933 case KVM_GET_PIT2: {
3934 r = -ENXIO;
3935 if (!kvm->arch.vpit)
3936 goto out;
3937 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3938 if (r)
3939 goto out;
3940 r = -EFAULT;
3941 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3942 goto out;
3943 r = 0;
3944 break;
3945 }
3946 case KVM_SET_PIT2: {
3947 r = -EFAULT;
3948 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3949 goto out;
3950 r = -ENXIO;
3951 if (!kvm->arch.vpit)
3952 goto out;
3953 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3954 break;
3955 }
3956 case KVM_REINJECT_CONTROL: {
3957 struct kvm_reinject_control control;
3958 r = -EFAULT;
3959 if (copy_from_user(&control, argp, sizeof(control)))
3960 goto out;
3961 r = kvm_vm_ioctl_reinject(kvm, &control);
3962 break;
3963 }
3964 case KVM_SET_BOOT_CPU_ID:
3965 r = 0;
3966 mutex_lock(&kvm->lock);
3967 if (atomic_read(&kvm->online_vcpus) != 0)
3968 r = -EBUSY;
3969 else
3970 kvm->arch.bsp_vcpu_id = arg;
3971 mutex_unlock(&kvm->lock);
3972 break;
3973 case KVM_XEN_HVM_CONFIG: {
3974 r = -EFAULT;
3975 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3976 sizeof(struct kvm_xen_hvm_config)))
3977 goto out;
3978 r = -EINVAL;
3979 if (kvm->arch.xen_hvm_config.flags)
3980 goto out;
3981 r = 0;
3982 break;
3983 }
3984 case KVM_SET_CLOCK: {
3985 struct kvm_clock_data user_ns;
3986 u64 now_ns;
3987 s64 delta;
3988
3989 r = -EFAULT;
3990 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3991 goto out;
3992
3993 r = -EINVAL;
3994 if (user_ns.flags)
3995 goto out;
3996
3997 r = 0;
3998 local_irq_disable();
3999 now_ns = get_kernel_ns();
4000 delta = user_ns.clock - now_ns;
4001 local_irq_enable();
4002 kvm->arch.kvmclock_offset = delta;
4003 kvm_gen_update_masterclock(kvm);
4004 break;
4005 }
4006 case KVM_GET_CLOCK: {
4007 struct kvm_clock_data user_ns;
4008 u64 now_ns;
4009
4010 local_irq_disable();
4011 now_ns = get_kernel_ns();
4012 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4013 local_irq_enable();
4014 user_ns.flags = 0;
4015 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4016
4017 r = -EFAULT;
4018 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4019 goto out;
4020 r = 0;
4021 break;
4022 }
4023 case KVM_ENABLE_CAP: {
4024 struct kvm_enable_cap cap;
4025
4026 r = -EFAULT;
4027 if (copy_from_user(&cap, argp, sizeof(cap)))
4028 goto out;
4029 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4030 break;
4031 }
4032 default:
4033 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4034 }
4035 out:
4036 return r;
4037 }
4038
4039 static void kvm_init_msr_list(void)
4040 {
4041 u32 dummy[2];
4042 unsigned i, j;
4043
4044 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4045 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4046 continue;
4047
4048 /*
4049 * Even MSRs that are valid in the host may not be exposed
4050 * to the guests in some cases.
4051 */
4052 switch (msrs_to_save[i]) {
4053 case MSR_IA32_BNDCFGS:
4054 if (!kvm_x86_ops->mpx_supported())
4055 continue;
4056 break;
4057 case MSR_TSC_AUX:
4058 if (!kvm_x86_ops->rdtscp_supported())
4059 continue;
4060 break;
4061 default:
4062 break;
4063 }
4064
4065 if (j < i)
4066 msrs_to_save[j] = msrs_to_save[i];
4067 j++;
4068 }
4069 num_msrs_to_save = j;
4070
4071 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4072 switch (emulated_msrs[i]) {
4073 case MSR_IA32_SMBASE:
4074 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4075 continue;
4076 break;
4077 default:
4078 break;
4079 }
4080
4081 if (j < i)
4082 emulated_msrs[j] = emulated_msrs[i];
4083 j++;
4084 }
4085 num_emulated_msrs = j;
4086 }
4087
4088 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4089 const void *v)
4090 {
4091 int handled = 0;
4092 int n;
4093
4094 do {
4095 n = min(len, 8);
4096 if (!(vcpu->arch.apic &&
4097 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4098 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4099 break;
4100 handled += n;
4101 addr += n;
4102 len -= n;
4103 v += n;
4104 } while (len);
4105
4106 return handled;
4107 }
4108
4109 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4110 {
4111 int handled = 0;
4112 int n;
4113
4114 do {
4115 n = min(len, 8);
4116 if (!(vcpu->arch.apic &&
4117 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4118 addr, n, v))
4119 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4120 break;
4121 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4122 handled += n;
4123 addr += n;
4124 len -= n;
4125 v += n;
4126 } while (len);
4127
4128 return handled;
4129 }
4130
4131 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4132 struct kvm_segment *var, int seg)
4133 {
4134 kvm_x86_ops->set_segment(vcpu, var, seg);
4135 }
4136
4137 void kvm_get_segment(struct kvm_vcpu *vcpu,
4138 struct kvm_segment *var, int seg)
4139 {
4140 kvm_x86_ops->get_segment(vcpu, var, seg);
4141 }
4142
4143 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4144 struct x86_exception *exception)
4145 {
4146 gpa_t t_gpa;
4147
4148 BUG_ON(!mmu_is_nested(vcpu));
4149
4150 /* NPT walks are always user-walks */
4151 access |= PFERR_USER_MASK;
4152 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4153
4154 return t_gpa;
4155 }
4156
4157 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4158 struct x86_exception *exception)
4159 {
4160 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4161 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4162 }
4163
4164 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4165 struct x86_exception *exception)
4166 {
4167 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4168 access |= PFERR_FETCH_MASK;
4169 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4170 }
4171
4172 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4173 struct x86_exception *exception)
4174 {
4175 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4176 access |= PFERR_WRITE_MASK;
4177 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4178 }
4179
4180 /* uses this to access any guest's mapped memory without checking CPL */
4181 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4182 struct x86_exception *exception)
4183 {
4184 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4185 }
4186
4187 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4188 struct kvm_vcpu *vcpu, u32 access,
4189 struct x86_exception *exception)
4190 {
4191 void *data = val;
4192 int r = X86EMUL_CONTINUE;
4193
4194 while (bytes) {
4195 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4196 exception);
4197 unsigned offset = addr & (PAGE_SIZE-1);
4198 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4199 int ret;
4200
4201 if (gpa == UNMAPPED_GVA)
4202 return X86EMUL_PROPAGATE_FAULT;
4203 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4204 offset, toread);
4205 if (ret < 0) {
4206 r = X86EMUL_IO_NEEDED;
4207 goto out;
4208 }
4209
4210 bytes -= toread;
4211 data += toread;
4212 addr += toread;
4213 }
4214 out:
4215 return r;
4216 }
4217
4218 /* used for instruction fetching */
4219 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4220 gva_t addr, void *val, unsigned int bytes,
4221 struct x86_exception *exception)
4222 {
4223 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4224 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4225 unsigned offset;
4226 int ret;
4227
4228 /* Inline kvm_read_guest_virt_helper for speed. */
4229 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4230 exception);
4231 if (unlikely(gpa == UNMAPPED_GVA))
4232 return X86EMUL_PROPAGATE_FAULT;
4233
4234 offset = addr & (PAGE_SIZE-1);
4235 if (WARN_ON(offset + bytes > PAGE_SIZE))
4236 bytes = (unsigned)PAGE_SIZE - offset;
4237 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4238 offset, bytes);
4239 if (unlikely(ret < 0))
4240 return X86EMUL_IO_NEEDED;
4241
4242 return X86EMUL_CONTINUE;
4243 }
4244
4245 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4246 gva_t addr, void *val, unsigned int bytes,
4247 struct x86_exception *exception)
4248 {
4249 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4250 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4251
4252 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4253 exception);
4254 }
4255 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4256
4257 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4258 gva_t addr, void *val, unsigned int bytes,
4259 struct x86_exception *exception)
4260 {
4261 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4262 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4263 }
4264
4265 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4266 unsigned long addr, void *val, unsigned int bytes)
4267 {
4268 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4269 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4270
4271 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4272 }
4273
4274 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4275 gva_t addr, void *val,
4276 unsigned int bytes,
4277 struct x86_exception *exception)
4278 {
4279 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4280 void *data = val;
4281 int r = X86EMUL_CONTINUE;
4282
4283 while (bytes) {
4284 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4285 PFERR_WRITE_MASK,
4286 exception);
4287 unsigned offset = addr & (PAGE_SIZE-1);
4288 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4289 int ret;
4290
4291 if (gpa == UNMAPPED_GVA)
4292 return X86EMUL_PROPAGATE_FAULT;
4293 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4294 if (ret < 0) {
4295 r = X86EMUL_IO_NEEDED;
4296 goto out;
4297 }
4298
4299 bytes -= towrite;
4300 data += towrite;
4301 addr += towrite;
4302 }
4303 out:
4304 return r;
4305 }
4306 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4307
4308 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4309 gpa_t *gpa, struct x86_exception *exception,
4310 bool write)
4311 {
4312 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4313 | (write ? PFERR_WRITE_MASK : 0);
4314
4315 if (vcpu_match_mmio_gva(vcpu, gva)
4316 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4317 vcpu->arch.access, access)) {
4318 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4319 (gva & (PAGE_SIZE - 1));
4320 trace_vcpu_match_mmio(gva, *gpa, write, false);
4321 return 1;
4322 }
4323
4324 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4325
4326 if (*gpa == UNMAPPED_GVA)
4327 return -1;
4328
4329 /* For APIC access vmexit */
4330 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4331 return 1;
4332
4333 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4334 trace_vcpu_match_mmio(gva, *gpa, write, true);
4335 return 1;
4336 }
4337
4338 return 0;
4339 }
4340
4341 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4342 const void *val, int bytes)
4343 {
4344 int ret;
4345
4346 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4347 if (ret < 0)
4348 return 0;
4349 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4350 return 1;
4351 }
4352
4353 struct read_write_emulator_ops {
4354 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4355 int bytes);
4356 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4357 void *val, int bytes);
4358 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4359 int bytes, void *val);
4360 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4361 void *val, int bytes);
4362 bool write;
4363 };
4364
4365 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4366 {
4367 if (vcpu->mmio_read_completed) {
4368 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4369 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4370 vcpu->mmio_read_completed = 0;
4371 return 1;
4372 }
4373
4374 return 0;
4375 }
4376
4377 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4378 void *val, int bytes)
4379 {
4380 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4381 }
4382
4383 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4384 void *val, int bytes)
4385 {
4386 return emulator_write_phys(vcpu, gpa, val, bytes);
4387 }
4388
4389 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4390 {
4391 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4392 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4393 }
4394
4395 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4396 void *val, int bytes)
4397 {
4398 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4399 return X86EMUL_IO_NEEDED;
4400 }
4401
4402 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4403 void *val, int bytes)
4404 {
4405 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4406
4407 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4408 return X86EMUL_CONTINUE;
4409 }
4410
4411 static const struct read_write_emulator_ops read_emultor = {
4412 .read_write_prepare = read_prepare,
4413 .read_write_emulate = read_emulate,
4414 .read_write_mmio = vcpu_mmio_read,
4415 .read_write_exit_mmio = read_exit_mmio,
4416 };
4417
4418 static const struct read_write_emulator_ops write_emultor = {
4419 .read_write_emulate = write_emulate,
4420 .read_write_mmio = write_mmio,
4421 .read_write_exit_mmio = write_exit_mmio,
4422 .write = true,
4423 };
4424
4425 static int emulator_read_write_onepage(unsigned long addr, void *val,
4426 unsigned int bytes,
4427 struct x86_exception *exception,
4428 struct kvm_vcpu *vcpu,
4429 const struct read_write_emulator_ops *ops)
4430 {
4431 gpa_t gpa;
4432 int handled, ret;
4433 bool write = ops->write;
4434 struct kvm_mmio_fragment *frag;
4435
4436 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4437
4438 if (ret < 0)
4439 return X86EMUL_PROPAGATE_FAULT;
4440
4441 /* For APIC access vmexit */
4442 if (ret)
4443 goto mmio;
4444
4445 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4446 return X86EMUL_CONTINUE;
4447
4448 mmio:
4449 /*
4450 * Is this MMIO handled locally?
4451 */
4452 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4453 if (handled == bytes)
4454 return X86EMUL_CONTINUE;
4455
4456 gpa += handled;
4457 bytes -= handled;
4458 val += handled;
4459
4460 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4461 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4462 frag->gpa = gpa;
4463 frag->data = val;
4464 frag->len = bytes;
4465 return X86EMUL_CONTINUE;
4466 }
4467
4468 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4469 unsigned long addr,
4470 void *val, unsigned int bytes,
4471 struct x86_exception *exception,
4472 const struct read_write_emulator_ops *ops)
4473 {
4474 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4475 gpa_t gpa;
4476 int rc;
4477
4478 if (ops->read_write_prepare &&
4479 ops->read_write_prepare(vcpu, val, bytes))
4480 return X86EMUL_CONTINUE;
4481
4482 vcpu->mmio_nr_fragments = 0;
4483
4484 /* Crossing a page boundary? */
4485 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4486 int now;
4487
4488 now = -addr & ~PAGE_MASK;
4489 rc = emulator_read_write_onepage(addr, val, now, exception,
4490 vcpu, ops);
4491
4492 if (rc != X86EMUL_CONTINUE)
4493 return rc;
4494 addr += now;
4495 if (ctxt->mode != X86EMUL_MODE_PROT64)
4496 addr = (u32)addr;
4497 val += now;
4498 bytes -= now;
4499 }
4500
4501 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4502 vcpu, ops);
4503 if (rc != X86EMUL_CONTINUE)
4504 return rc;
4505
4506 if (!vcpu->mmio_nr_fragments)
4507 return rc;
4508
4509 gpa = vcpu->mmio_fragments[0].gpa;
4510
4511 vcpu->mmio_needed = 1;
4512 vcpu->mmio_cur_fragment = 0;
4513
4514 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4515 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4516 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4517 vcpu->run->mmio.phys_addr = gpa;
4518
4519 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4520 }
4521
4522 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4523 unsigned long addr,
4524 void *val,
4525 unsigned int bytes,
4526 struct x86_exception *exception)
4527 {
4528 return emulator_read_write(ctxt, addr, val, bytes,
4529 exception, &read_emultor);
4530 }
4531
4532 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4533 unsigned long addr,
4534 const void *val,
4535 unsigned int bytes,
4536 struct x86_exception *exception)
4537 {
4538 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4539 exception, &write_emultor);
4540 }
4541
4542 #define CMPXCHG_TYPE(t, ptr, old, new) \
4543 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4544
4545 #ifdef CONFIG_X86_64
4546 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4547 #else
4548 # define CMPXCHG64(ptr, old, new) \
4549 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4550 #endif
4551
4552 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4553 unsigned long addr,
4554 const void *old,
4555 const void *new,
4556 unsigned int bytes,
4557 struct x86_exception *exception)
4558 {
4559 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4560 gpa_t gpa;
4561 struct page *page;
4562 char *kaddr;
4563 bool exchanged;
4564
4565 /* guests cmpxchg8b have to be emulated atomically */
4566 if (bytes > 8 || (bytes & (bytes - 1)))
4567 goto emul_write;
4568
4569 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4570
4571 if (gpa == UNMAPPED_GVA ||
4572 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4573 goto emul_write;
4574
4575 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4576 goto emul_write;
4577
4578 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4579 if (is_error_page(page))
4580 goto emul_write;
4581
4582 kaddr = kmap_atomic(page);
4583 kaddr += offset_in_page(gpa);
4584 switch (bytes) {
4585 case 1:
4586 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4587 break;
4588 case 2:
4589 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4590 break;
4591 case 4:
4592 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4593 break;
4594 case 8:
4595 exchanged = CMPXCHG64(kaddr, old, new);
4596 break;
4597 default:
4598 BUG();
4599 }
4600 kunmap_atomic(kaddr);
4601 kvm_release_page_dirty(page);
4602
4603 if (!exchanged)
4604 return X86EMUL_CMPXCHG_FAILED;
4605
4606 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4607 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4608
4609 return X86EMUL_CONTINUE;
4610
4611 emul_write:
4612 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4613
4614 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4615 }
4616
4617 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4618 {
4619 /* TODO: String I/O for in kernel device */
4620 int r;
4621
4622 if (vcpu->arch.pio.in)
4623 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4624 vcpu->arch.pio.size, pd);
4625 else
4626 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4627 vcpu->arch.pio.port, vcpu->arch.pio.size,
4628 pd);
4629 return r;
4630 }
4631
4632 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4633 unsigned short port, void *val,
4634 unsigned int count, bool in)
4635 {
4636 vcpu->arch.pio.port = port;
4637 vcpu->arch.pio.in = in;
4638 vcpu->arch.pio.count = count;
4639 vcpu->arch.pio.size = size;
4640
4641 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4642 vcpu->arch.pio.count = 0;
4643 return 1;
4644 }
4645
4646 vcpu->run->exit_reason = KVM_EXIT_IO;
4647 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4648 vcpu->run->io.size = size;
4649 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4650 vcpu->run->io.count = count;
4651 vcpu->run->io.port = port;
4652
4653 return 0;
4654 }
4655
4656 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4657 int size, unsigned short port, void *val,
4658 unsigned int count)
4659 {
4660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4661 int ret;
4662
4663 if (vcpu->arch.pio.count)
4664 goto data_avail;
4665
4666 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4667 if (ret) {
4668 data_avail:
4669 memcpy(val, vcpu->arch.pio_data, size * count);
4670 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4671 vcpu->arch.pio.count = 0;
4672 return 1;
4673 }
4674
4675 return 0;
4676 }
4677
4678 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4679 int size, unsigned short port,
4680 const void *val, unsigned int count)
4681 {
4682 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4683
4684 memcpy(vcpu->arch.pio_data, val, size * count);
4685 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4686 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4687 }
4688
4689 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4690 {
4691 return kvm_x86_ops->get_segment_base(vcpu, seg);
4692 }
4693
4694 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4695 {
4696 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4697 }
4698
4699 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4700 {
4701 if (!need_emulate_wbinvd(vcpu))
4702 return X86EMUL_CONTINUE;
4703
4704 if (kvm_x86_ops->has_wbinvd_exit()) {
4705 int cpu = get_cpu();
4706
4707 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4708 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4709 wbinvd_ipi, NULL, 1);
4710 put_cpu();
4711 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4712 } else
4713 wbinvd();
4714 return X86EMUL_CONTINUE;
4715 }
4716
4717 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4718 {
4719 kvm_x86_ops->skip_emulated_instruction(vcpu);
4720 return kvm_emulate_wbinvd_noskip(vcpu);
4721 }
4722 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4723
4724
4725
4726 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4727 {
4728 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4729 }
4730
4731 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4732 unsigned long *dest)
4733 {
4734 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4735 }
4736
4737 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4738 unsigned long value)
4739 {
4740
4741 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4742 }
4743
4744 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4745 {
4746 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4747 }
4748
4749 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4750 {
4751 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4752 unsigned long value;
4753
4754 switch (cr) {
4755 case 0:
4756 value = kvm_read_cr0(vcpu);
4757 break;
4758 case 2:
4759 value = vcpu->arch.cr2;
4760 break;
4761 case 3:
4762 value = kvm_read_cr3(vcpu);
4763 break;
4764 case 4:
4765 value = kvm_read_cr4(vcpu);
4766 break;
4767 case 8:
4768 value = kvm_get_cr8(vcpu);
4769 break;
4770 default:
4771 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4772 return 0;
4773 }
4774
4775 return value;
4776 }
4777
4778 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4779 {
4780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4781 int res = 0;
4782
4783 switch (cr) {
4784 case 0:
4785 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4786 break;
4787 case 2:
4788 vcpu->arch.cr2 = val;
4789 break;
4790 case 3:
4791 res = kvm_set_cr3(vcpu, val);
4792 break;
4793 case 4:
4794 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4795 break;
4796 case 8:
4797 res = kvm_set_cr8(vcpu, val);
4798 break;
4799 default:
4800 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4801 res = -1;
4802 }
4803
4804 return res;
4805 }
4806
4807 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4808 {
4809 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4810 }
4811
4812 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4813 {
4814 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4815 }
4816
4817 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4818 {
4819 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4820 }
4821
4822 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4823 {
4824 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4825 }
4826
4827 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4828 {
4829 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4830 }
4831
4832 static unsigned long emulator_get_cached_segment_base(
4833 struct x86_emulate_ctxt *ctxt, int seg)
4834 {
4835 return get_segment_base(emul_to_vcpu(ctxt), seg);
4836 }
4837
4838 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4839 struct desc_struct *desc, u32 *base3,
4840 int seg)
4841 {
4842 struct kvm_segment var;
4843
4844 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4845 *selector = var.selector;
4846
4847 if (var.unusable) {
4848 memset(desc, 0, sizeof(*desc));
4849 return false;
4850 }
4851
4852 if (var.g)
4853 var.limit >>= 12;
4854 set_desc_limit(desc, var.limit);
4855 set_desc_base(desc, (unsigned long)var.base);
4856 #ifdef CONFIG_X86_64
4857 if (base3)
4858 *base3 = var.base >> 32;
4859 #endif
4860 desc->type = var.type;
4861 desc->s = var.s;
4862 desc->dpl = var.dpl;
4863 desc->p = var.present;
4864 desc->avl = var.avl;
4865 desc->l = var.l;
4866 desc->d = var.db;
4867 desc->g = var.g;
4868
4869 return true;
4870 }
4871
4872 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4873 struct desc_struct *desc, u32 base3,
4874 int seg)
4875 {
4876 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4877 struct kvm_segment var;
4878
4879 var.selector = selector;
4880 var.base = get_desc_base(desc);
4881 #ifdef CONFIG_X86_64
4882 var.base |= ((u64)base3) << 32;
4883 #endif
4884 var.limit = get_desc_limit(desc);
4885 if (desc->g)
4886 var.limit = (var.limit << 12) | 0xfff;
4887 var.type = desc->type;
4888 var.dpl = desc->dpl;
4889 var.db = desc->d;
4890 var.s = desc->s;
4891 var.l = desc->l;
4892 var.g = desc->g;
4893 var.avl = desc->avl;
4894 var.present = desc->p;
4895 var.unusable = !var.present;
4896 var.padding = 0;
4897
4898 kvm_set_segment(vcpu, &var, seg);
4899 return;
4900 }
4901
4902 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4903 u32 msr_index, u64 *pdata)
4904 {
4905 struct msr_data msr;
4906 int r;
4907
4908 msr.index = msr_index;
4909 msr.host_initiated = false;
4910 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4911 if (r)
4912 return r;
4913
4914 *pdata = msr.data;
4915 return 0;
4916 }
4917
4918 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4919 u32 msr_index, u64 data)
4920 {
4921 struct msr_data msr;
4922
4923 msr.data = data;
4924 msr.index = msr_index;
4925 msr.host_initiated = false;
4926 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4927 }
4928
4929 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4930 {
4931 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4932
4933 return vcpu->arch.smbase;
4934 }
4935
4936 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4937 {
4938 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4939
4940 vcpu->arch.smbase = smbase;
4941 }
4942
4943 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4944 u32 pmc)
4945 {
4946 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4947 }
4948
4949 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4950 u32 pmc, u64 *pdata)
4951 {
4952 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4953 }
4954
4955 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4956 {
4957 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4958 }
4959
4960 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4961 {
4962 preempt_disable();
4963 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4964 /*
4965 * CR0.TS may reference the host fpu state, not the guest fpu state,
4966 * so it may be clear at this point.
4967 */
4968 clts();
4969 }
4970
4971 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4972 {
4973 preempt_enable();
4974 }
4975
4976 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4977 struct x86_instruction_info *info,
4978 enum x86_intercept_stage stage)
4979 {
4980 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4981 }
4982
4983 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4984 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4985 {
4986 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4987 }
4988
4989 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4990 {
4991 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4992 }
4993
4994 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4995 {
4996 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4997 }
4998
4999 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5000 {
5001 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5002 }
5003
5004 static const struct x86_emulate_ops emulate_ops = {
5005 .read_gpr = emulator_read_gpr,
5006 .write_gpr = emulator_write_gpr,
5007 .read_std = kvm_read_guest_virt_system,
5008 .write_std = kvm_write_guest_virt_system,
5009 .read_phys = kvm_read_guest_phys_system,
5010 .fetch = kvm_fetch_guest_virt,
5011 .read_emulated = emulator_read_emulated,
5012 .write_emulated = emulator_write_emulated,
5013 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5014 .invlpg = emulator_invlpg,
5015 .pio_in_emulated = emulator_pio_in_emulated,
5016 .pio_out_emulated = emulator_pio_out_emulated,
5017 .get_segment = emulator_get_segment,
5018 .set_segment = emulator_set_segment,
5019 .get_cached_segment_base = emulator_get_cached_segment_base,
5020 .get_gdt = emulator_get_gdt,
5021 .get_idt = emulator_get_idt,
5022 .set_gdt = emulator_set_gdt,
5023 .set_idt = emulator_set_idt,
5024 .get_cr = emulator_get_cr,
5025 .set_cr = emulator_set_cr,
5026 .cpl = emulator_get_cpl,
5027 .get_dr = emulator_get_dr,
5028 .set_dr = emulator_set_dr,
5029 .get_smbase = emulator_get_smbase,
5030 .set_smbase = emulator_set_smbase,
5031 .set_msr = emulator_set_msr,
5032 .get_msr = emulator_get_msr,
5033 .check_pmc = emulator_check_pmc,
5034 .read_pmc = emulator_read_pmc,
5035 .halt = emulator_halt,
5036 .wbinvd = emulator_wbinvd,
5037 .fix_hypercall = emulator_fix_hypercall,
5038 .get_fpu = emulator_get_fpu,
5039 .put_fpu = emulator_put_fpu,
5040 .intercept = emulator_intercept,
5041 .get_cpuid = emulator_get_cpuid,
5042 .set_nmi_mask = emulator_set_nmi_mask,
5043 };
5044
5045 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5046 {
5047 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5048 /*
5049 * an sti; sti; sequence only disable interrupts for the first
5050 * instruction. So, if the last instruction, be it emulated or
5051 * not, left the system with the INT_STI flag enabled, it
5052 * means that the last instruction is an sti. We should not
5053 * leave the flag on in this case. The same goes for mov ss
5054 */
5055 if (int_shadow & mask)
5056 mask = 0;
5057 if (unlikely(int_shadow || mask)) {
5058 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5059 if (!mask)
5060 kvm_make_request(KVM_REQ_EVENT, vcpu);
5061 }
5062 }
5063
5064 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5065 {
5066 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5067 if (ctxt->exception.vector == PF_VECTOR)
5068 return kvm_propagate_fault(vcpu, &ctxt->exception);
5069
5070 if (ctxt->exception.error_code_valid)
5071 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5072 ctxt->exception.error_code);
5073 else
5074 kvm_queue_exception(vcpu, ctxt->exception.vector);
5075 return false;
5076 }
5077
5078 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5079 {
5080 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5081 int cs_db, cs_l;
5082
5083 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5084
5085 ctxt->eflags = kvm_get_rflags(vcpu);
5086 ctxt->eip = kvm_rip_read(vcpu);
5087 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5088 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5089 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5090 cs_db ? X86EMUL_MODE_PROT32 :
5091 X86EMUL_MODE_PROT16;
5092 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5093 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5094 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5095 ctxt->emul_flags = vcpu->arch.hflags;
5096
5097 init_decode_cache(ctxt);
5098 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5099 }
5100
5101 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5102 {
5103 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5104 int ret;
5105
5106 init_emulate_ctxt(vcpu);
5107
5108 ctxt->op_bytes = 2;
5109 ctxt->ad_bytes = 2;
5110 ctxt->_eip = ctxt->eip + inc_eip;
5111 ret = emulate_int_real(ctxt, irq);
5112
5113 if (ret != X86EMUL_CONTINUE)
5114 return EMULATE_FAIL;
5115
5116 ctxt->eip = ctxt->_eip;
5117 kvm_rip_write(vcpu, ctxt->eip);
5118 kvm_set_rflags(vcpu, ctxt->eflags);
5119
5120 if (irq == NMI_VECTOR)
5121 vcpu->arch.nmi_pending = 0;
5122 else
5123 vcpu->arch.interrupt.pending = false;
5124
5125 return EMULATE_DONE;
5126 }
5127 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5128
5129 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5130 {
5131 int r = EMULATE_DONE;
5132
5133 ++vcpu->stat.insn_emulation_fail;
5134 trace_kvm_emulate_insn_failed(vcpu);
5135 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5136 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5137 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5138 vcpu->run->internal.ndata = 0;
5139 r = EMULATE_FAIL;
5140 }
5141 kvm_queue_exception(vcpu, UD_VECTOR);
5142
5143 return r;
5144 }
5145
5146 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5147 bool write_fault_to_shadow_pgtable,
5148 int emulation_type)
5149 {
5150 gpa_t gpa = cr2;
5151 kvm_pfn_t pfn;
5152
5153 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5154 return false;
5155
5156 if (!vcpu->arch.mmu.direct_map) {
5157 /*
5158 * Write permission should be allowed since only
5159 * write access need to be emulated.
5160 */
5161 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5162
5163 /*
5164 * If the mapping is invalid in guest, let cpu retry
5165 * it to generate fault.
5166 */
5167 if (gpa == UNMAPPED_GVA)
5168 return true;
5169 }
5170
5171 /*
5172 * Do not retry the unhandleable instruction if it faults on the
5173 * readonly host memory, otherwise it will goto a infinite loop:
5174 * retry instruction -> write #PF -> emulation fail -> retry
5175 * instruction -> ...
5176 */
5177 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5178
5179 /*
5180 * If the instruction failed on the error pfn, it can not be fixed,
5181 * report the error to userspace.
5182 */
5183 if (is_error_noslot_pfn(pfn))
5184 return false;
5185
5186 kvm_release_pfn_clean(pfn);
5187
5188 /* The instructions are well-emulated on direct mmu. */
5189 if (vcpu->arch.mmu.direct_map) {
5190 unsigned int indirect_shadow_pages;
5191
5192 spin_lock(&vcpu->kvm->mmu_lock);
5193 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5194 spin_unlock(&vcpu->kvm->mmu_lock);
5195
5196 if (indirect_shadow_pages)
5197 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5198
5199 return true;
5200 }
5201
5202 /*
5203 * if emulation was due to access to shadowed page table
5204 * and it failed try to unshadow page and re-enter the
5205 * guest to let CPU execute the instruction.
5206 */
5207 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5208
5209 /*
5210 * If the access faults on its page table, it can not
5211 * be fixed by unprotecting shadow page and it should
5212 * be reported to userspace.
5213 */
5214 return !write_fault_to_shadow_pgtable;
5215 }
5216
5217 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5218 unsigned long cr2, int emulation_type)
5219 {
5220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5221 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5222
5223 last_retry_eip = vcpu->arch.last_retry_eip;
5224 last_retry_addr = vcpu->arch.last_retry_addr;
5225
5226 /*
5227 * If the emulation is caused by #PF and it is non-page_table
5228 * writing instruction, it means the VM-EXIT is caused by shadow
5229 * page protected, we can zap the shadow page and retry this
5230 * instruction directly.
5231 *
5232 * Note: if the guest uses a non-page-table modifying instruction
5233 * on the PDE that points to the instruction, then we will unmap
5234 * the instruction and go to an infinite loop. So, we cache the
5235 * last retried eip and the last fault address, if we meet the eip
5236 * and the address again, we can break out of the potential infinite
5237 * loop.
5238 */
5239 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5240
5241 if (!(emulation_type & EMULTYPE_RETRY))
5242 return false;
5243
5244 if (x86_page_table_writing_insn(ctxt))
5245 return false;
5246
5247 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5248 return false;
5249
5250 vcpu->arch.last_retry_eip = ctxt->eip;
5251 vcpu->arch.last_retry_addr = cr2;
5252
5253 if (!vcpu->arch.mmu.direct_map)
5254 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5255
5256 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5257
5258 return true;
5259 }
5260
5261 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5262 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5263
5264 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5265 {
5266 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5267 /* This is a good place to trace that we are exiting SMM. */
5268 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5269
5270 if (unlikely(vcpu->arch.smi_pending)) {
5271 kvm_make_request(KVM_REQ_SMI, vcpu);
5272 vcpu->arch.smi_pending = 0;
5273 } else {
5274 /* Process a latched INIT, if any. */
5275 kvm_make_request(KVM_REQ_EVENT, vcpu);
5276 }
5277 }
5278
5279 kvm_mmu_reset_context(vcpu);
5280 }
5281
5282 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5283 {
5284 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5285
5286 vcpu->arch.hflags = emul_flags;
5287
5288 if (changed & HF_SMM_MASK)
5289 kvm_smm_changed(vcpu);
5290 }
5291
5292 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5293 unsigned long *db)
5294 {
5295 u32 dr6 = 0;
5296 int i;
5297 u32 enable, rwlen;
5298
5299 enable = dr7;
5300 rwlen = dr7 >> 16;
5301 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5302 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5303 dr6 |= (1 << i);
5304 return dr6;
5305 }
5306
5307 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5308 {
5309 struct kvm_run *kvm_run = vcpu->run;
5310
5311 /*
5312 * rflags is the old, "raw" value of the flags. The new value has
5313 * not been saved yet.
5314 *
5315 * This is correct even for TF set by the guest, because "the
5316 * processor will not generate this exception after the instruction
5317 * that sets the TF flag".
5318 */
5319 if (unlikely(rflags & X86_EFLAGS_TF)) {
5320 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5321 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5322 DR6_RTM;
5323 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5324 kvm_run->debug.arch.exception = DB_VECTOR;
5325 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5326 *r = EMULATE_USER_EXIT;
5327 } else {
5328 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5329 /*
5330 * "Certain debug exceptions may clear bit 0-3. The
5331 * remaining contents of the DR6 register are never
5332 * cleared by the processor".
5333 */
5334 vcpu->arch.dr6 &= ~15;
5335 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5336 kvm_queue_exception(vcpu, DB_VECTOR);
5337 }
5338 }
5339 }
5340
5341 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5342 {
5343 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5344 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5345 struct kvm_run *kvm_run = vcpu->run;
5346 unsigned long eip = kvm_get_linear_rip(vcpu);
5347 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5348 vcpu->arch.guest_debug_dr7,
5349 vcpu->arch.eff_db);
5350
5351 if (dr6 != 0) {
5352 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5353 kvm_run->debug.arch.pc = eip;
5354 kvm_run->debug.arch.exception = DB_VECTOR;
5355 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5356 *r = EMULATE_USER_EXIT;
5357 return true;
5358 }
5359 }
5360
5361 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5362 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5363 unsigned long eip = kvm_get_linear_rip(vcpu);
5364 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5365 vcpu->arch.dr7,
5366 vcpu->arch.db);
5367
5368 if (dr6 != 0) {
5369 vcpu->arch.dr6 &= ~15;
5370 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5371 kvm_queue_exception(vcpu, DB_VECTOR);
5372 *r = EMULATE_DONE;
5373 return true;
5374 }
5375 }
5376
5377 return false;
5378 }
5379
5380 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5381 unsigned long cr2,
5382 int emulation_type,
5383 void *insn,
5384 int insn_len)
5385 {
5386 int r;
5387 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5388 bool writeback = true;
5389 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5390
5391 /*
5392 * Clear write_fault_to_shadow_pgtable here to ensure it is
5393 * never reused.
5394 */
5395 vcpu->arch.write_fault_to_shadow_pgtable = false;
5396 kvm_clear_exception_queue(vcpu);
5397
5398 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5399 init_emulate_ctxt(vcpu);
5400
5401 /*
5402 * We will reenter on the same instruction since
5403 * we do not set complete_userspace_io. This does not
5404 * handle watchpoints yet, those would be handled in
5405 * the emulate_ops.
5406 */
5407 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5408 return r;
5409
5410 ctxt->interruptibility = 0;
5411 ctxt->have_exception = false;
5412 ctxt->exception.vector = -1;
5413 ctxt->perm_ok = false;
5414
5415 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5416
5417 r = x86_decode_insn(ctxt, insn, insn_len);
5418
5419 trace_kvm_emulate_insn_start(vcpu);
5420 ++vcpu->stat.insn_emulation;
5421 if (r != EMULATION_OK) {
5422 if (emulation_type & EMULTYPE_TRAP_UD)
5423 return EMULATE_FAIL;
5424 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5425 emulation_type))
5426 return EMULATE_DONE;
5427 if (emulation_type & EMULTYPE_SKIP)
5428 return EMULATE_FAIL;
5429 return handle_emulation_failure(vcpu);
5430 }
5431 }
5432
5433 if (emulation_type & EMULTYPE_SKIP) {
5434 kvm_rip_write(vcpu, ctxt->_eip);
5435 if (ctxt->eflags & X86_EFLAGS_RF)
5436 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5437 return EMULATE_DONE;
5438 }
5439
5440 if (retry_instruction(ctxt, cr2, emulation_type))
5441 return EMULATE_DONE;
5442
5443 /* this is needed for vmware backdoor interface to work since it
5444 changes registers values during IO operation */
5445 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5446 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5447 emulator_invalidate_register_cache(ctxt);
5448 }
5449
5450 restart:
5451 r = x86_emulate_insn(ctxt);
5452
5453 if (r == EMULATION_INTERCEPTED)
5454 return EMULATE_DONE;
5455
5456 if (r == EMULATION_FAILED) {
5457 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5458 emulation_type))
5459 return EMULATE_DONE;
5460
5461 return handle_emulation_failure(vcpu);
5462 }
5463
5464 if (ctxt->have_exception) {
5465 r = EMULATE_DONE;
5466 if (inject_emulated_exception(vcpu))
5467 return r;
5468 } else if (vcpu->arch.pio.count) {
5469 if (!vcpu->arch.pio.in) {
5470 /* FIXME: return into emulator if single-stepping. */
5471 vcpu->arch.pio.count = 0;
5472 } else {
5473 writeback = false;
5474 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5475 }
5476 r = EMULATE_USER_EXIT;
5477 } else if (vcpu->mmio_needed) {
5478 if (!vcpu->mmio_is_write)
5479 writeback = false;
5480 r = EMULATE_USER_EXIT;
5481 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5482 } else if (r == EMULATION_RESTART)
5483 goto restart;
5484 else
5485 r = EMULATE_DONE;
5486
5487 if (writeback) {
5488 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5489 toggle_interruptibility(vcpu, ctxt->interruptibility);
5490 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5491 if (vcpu->arch.hflags != ctxt->emul_flags)
5492 kvm_set_hflags(vcpu, ctxt->emul_flags);
5493 kvm_rip_write(vcpu, ctxt->eip);
5494 if (r == EMULATE_DONE)
5495 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5496 if (!ctxt->have_exception ||
5497 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5498 __kvm_set_rflags(vcpu, ctxt->eflags);
5499
5500 /*
5501 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5502 * do nothing, and it will be requested again as soon as
5503 * the shadow expires. But we still need to check here,
5504 * because POPF has no interrupt shadow.
5505 */
5506 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5507 kvm_make_request(KVM_REQ_EVENT, vcpu);
5508 } else
5509 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5510
5511 return r;
5512 }
5513 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5514
5515 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5516 {
5517 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5518 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5519 size, port, &val, 1);
5520 /* do not return to emulator after return from userspace */
5521 vcpu->arch.pio.count = 0;
5522 return ret;
5523 }
5524 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5525
5526 static void tsc_bad(void *info)
5527 {
5528 __this_cpu_write(cpu_tsc_khz, 0);
5529 }
5530
5531 static void tsc_khz_changed(void *data)
5532 {
5533 struct cpufreq_freqs *freq = data;
5534 unsigned long khz = 0;
5535
5536 if (data)
5537 khz = freq->new;
5538 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5539 khz = cpufreq_quick_get(raw_smp_processor_id());
5540 if (!khz)
5541 khz = tsc_khz;
5542 __this_cpu_write(cpu_tsc_khz, khz);
5543 }
5544
5545 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5546 void *data)
5547 {
5548 struct cpufreq_freqs *freq = data;
5549 struct kvm *kvm;
5550 struct kvm_vcpu *vcpu;
5551 int i, send_ipi = 0;
5552
5553 /*
5554 * We allow guests to temporarily run on slowing clocks,
5555 * provided we notify them after, or to run on accelerating
5556 * clocks, provided we notify them before. Thus time never
5557 * goes backwards.
5558 *
5559 * However, we have a problem. We can't atomically update
5560 * the frequency of a given CPU from this function; it is
5561 * merely a notifier, which can be called from any CPU.
5562 * Changing the TSC frequency at arbitrary points in time
5563 * requires a recomputation of local variables related to
5564 * the TSC for each VCPU. We must flag these local variables
5565 * to be updated and be sure the update takes place with the
5566 * new frequency before any guests proceed.
5567 *
5568 * Unfortunately, the combination of hotplug CPU and frequency
5569 * change creates an intractable locking scenario; the order
5570 * of when these callouts happen is undefined with respect to
5571 * CPU hotplug, and they can race with each other. As such,
5572 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5573 * undefined; you can actually have a CPU frequency change take
5574 * place in between the computation of X and the setting of the
5575 * variable. To protect against this problem, all updates of
5576 * the per_cpu tsc_khz variable are done in an interrupt
5577 * protected IPI, and all callers wishing to update the value
5578 * must wait for a synchronous IPI to complete (which is trivial
5579 * if the caller is on the CPU already). This establishes the
5580 * necessary total order on variable updates.
5581 *
5582 * Note that because a guest time update may take place
5583 * anytime after the setting of the VCPU's request bit, the
5584 * correct TSC value must be set before the request. However,
5585 * to ensure the update actually makes it to any guest which
5586 * starts running in hardware virtualization between the set
5587 * and the acquisition of the spinlock, we must also ping the
5588 * CPU after setting the request bit.
5589 *
5590 */
5591
5592 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5593 return 0;
5594 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5595 return 0;
5596
5597 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5598
5599 spin_lock(&kvm_lock);
5600 list_for_each_entry(kvm, &vm_list, vm_list) {
5601 kvm_for_each_vcpu(i, vcpu, kvm) {
5602 if (vcpu->cpu != freq->cpu)
5603 continue;
5604 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5605 if (vcpu->cpu != smp_processor_id())
5606 send_ipi = 1;
5607 }
5608 }
5609 spin_unlock(&kvm_lock);
5610
5611 if (freq->old < freq->new && send_ipi) {
5612 /*
5613 * We upscale the frequency. Must make the guest
5614 * doesn't see old kvmclock values while running with
5615 * the new frequency, otherwise we risk the guest sees
5616 * time go backwards.
5617 *
5618 * In case we update the frequency for another cpu
5619 * (which might be in guest context) send an interrupt
5620 * to kick the cpu out of guest context. Next time
5621 * guest context is entered kvmclock will be updated,
5622 * so the guest will not see stale values.
5623 */
5624 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5625 }
5626 return 0;
5627 }
5628
5629 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5630 .notifier_call = kvmclock_cpufreq_notifier
5631 };
5632
5633 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5634 unsigned long action, void *hcpu)
5635 {
5636 unsigned int cpu = (unsigned long)hcpu;
5637
5638 switch (action) {
5639 case CPU_ONLINE:
5640 case CPU_DOWN_FAILED:
5641 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5642 break;
5643 case CPU_DOWN_PREPARE:
5644 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5645 break;
5646 }
5647 return NOTIFY_OK;
5648 }
5649
5650 static struct notifier_block kvmclock_cpu_notifier_block = {
5651 .notifier_call = kvmclock_cpu_notifier,
5652 .priority = -INT_MAX
5653 };
5654
5655 static void kvm_timer_init(void)
5656 {
5657 int cpu;
5658
5659 max_tsc_khz = tsc_khz;
5660
5661 cpu_notifier_register_begin();
5662 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5663 #ifdef CONFIG_CPU_FREQ
5664 struct cpufreq_policy policy;
5665 memset(&policy, 0, sizeof(policy));
5666 cpu = get_cpu();
5667 cpufreq_get_policy(&policy, cpu);
5668 if (policy.cpuinfo.max_freq)
5669 max_tsc_khz = policy.cpuinfo.max_freq;
5670 put_cpu();
5671 #endif
5672 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5673 CPUFREQ_TRANSITION_NOTIFIER);
5674 }
5675 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5676 for_each_online_cpu(cpu)
5677 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5678
5679 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5680 cpu_notifier_register_done();
5681
5682 }
5683
5684 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5685
5686 int kvm_is_in_guest(void)
5687 {
5688 return __this_cpu_read(current_vcpu) != NULL;
5689 }
5690
5691 static int kvm_is_user_mode(void)
5692 {
5693 int user_mode = 3;
5694
5695 if (__this_cpu_read(current_vcpu))
5696 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5697
5698 return user_mode != 0;
5699 }
5700
5701 static unsigned long kvm_get_guest_ip(void)
5702 {
5703 unsigned long ip = 0;
5704
5705 if (__this_cpu_read(current_vcpu))
5706 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5707
5708 return ip;
5709 }
5710
5711 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5712 .is_in_guest = kvm_is_in_guest,
5713 .is_user_mode = kvm_is_user_mode,
5714 .get_guest_ip = kvm_get_guest_ip,
5715 };
5716
5717 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5718 {
5719 __this_cpu_write(current_vcpu, vcpu);
5720 }
5721 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5722
5723 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5724 {
5725 __this_cpu_write(current_vcpu, NULL);
5726 }
5727 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5728
5729 static void kvm_set_mmio_spte_mask(void)
5730 {
5731 u64 mask;
5732 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5733
5734 /*
5735 * Set the reserved bits and the present bit of an paging-structure
5736 * entry to generate page fault with PFER.RSV = 1.
5737 */
5738 /* Mask the reserved physical address bits. */
5739 mask = rsvd_bits(maxphyaddr, 51);
5740
5741 /* Bit 62 is always reserved for 32bit host. */
5742 mask |= 0x3ull << 62;
5743
5744 /* Set the present bit. */
5745 mask |= 1ull;
5746
5747 #ifdef CONFIG_X86_64
5748 /*
5749 * If reserved bit is not supported, clear the present bit to disable
5750 * mmio page fault.
5751 */
5752 if (maxphyaddr == 52)
5753 mask &= ~1ull;
5754 #endif
5755
5756 kvm_mmu_set_mmio_spte_mask(mask);
5757 }
5758
5759 #ifdef CONFIG_X86_64
5760 static void pvclock_gtod_update_fn(struct work_struct *work)
5761 {
5762 struct kvm *kvm;
5763
5764 struct kvm_vcpu *vcpu;
5765 int i;
5766
5767 spin_lock(&kvm_lock);
5768 list_for_each_entry(kvm, &vm_list, vm_list)
5769 kvm_for_each_vcpu(i, vcpu, kvm)
5770 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5771 atomic_set(&kvm_guest_has_master_clock, 0);
5772 spin_unlock(&kvm_lock);
5773 }
5774
5775 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5776
5777 /*
5778 * Notification about pvclock gtod data update.
5779 */
5780 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5781 void *priv)
5782 {
5783 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5784 struct timekeeper *tk = priv;
5785
5786 update_pvclock_gtod(tk);
5787
5788 /* disable master clock if host does not trust, or does not
5789 * use, TSC clocksource
5790 */
5791 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5792 atomic_read(&kvm_guest_has_master_clock) != 0)
5793 queue_work(system_long_wq, &pvclock_gtod_work);
5794
5795 return 0;
5796 }
5797
5798 static struct notifier_block pvclock_gtod_notifier = {
5799 .notifier_call = pvclock_gtod_notify,
5800 };
5801 #endif
5802
5803 int kvm_arch_init(void *opaque)
5804 {
5805 int r;
5806 struct kvm_x86_ops *ops = opaque;
5807
5808 if (kvm_x86_ops) {
5809 printk(KERN_ERR "kvm: already loaded the other module\n");
5810 r = -EEXIST;
5811 goto out;
5812 }
5813
5814 if (!ops->cpu_has_kvm_support()) {
5815 printk(KERN_ERR "kvm: no hardware support\n");
5816 r = -EOPNOTSUPP;
5817 goto out;
5818 }
5819 if (ops->disabled_by_bios()) {
5820 printk(KERN_ERR "kvm: disabled by bios\n");
5821 r = -EOPNOTSUPP;
5822 goto out;
5823 }
5824
5825 r = -ENOMEM;
5826 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5827 if (!shared_msrs) {
5828 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5829 goto out;
5830 }
5831
5832 r = kvm_mmu_module_init();
5833 if (r)
5834 goto out_free_percpu;
5835
5836 kvm_set_mmio_spte_mask();
5837
5838 kvm_x86_ops = ops;
5839
5840 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5841 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5842
5843 kvm_timer_init();
5844
5845 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5846
5847 if (cpu_has_xsave)
5848 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5849
5850 kvm_lapic_init();
5851 #ifdef CONFIG_X86_64
5852 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5853 #endif
5854
5855 return 0;
5856
5857 out_free_percpu:
5858 free_percpu(shared_msrs);
5859 out:
5860 return r;
5861 }
5862
5863 void kvm_arch_exit(void)
5864 {
5865 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5866
5867 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5868 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5869 CPUFREQ_TRANSITION_NOTIFIER);
5870 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5871 #ifdef CONFIG_X86_64
5872 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5873 #endif
5874 kvm_x86_ops = NULL;
5875 kvm_mmu_module_exit();
5876 free_percpu(shared_msrs);
5877 }
5878
5879 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5880 {
5881 ++vcpu->stat.halt_exits;
5882 if (lapic_in_kernel(vcpu)) {
5883 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5884 return 1;
5885 } else {
5886 vcpu->run->exit_reason = KVM_EXIT_HLT;
5887 return 0;
5888 }
5889 }
5890 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5891
5892 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5893 {
5894 kvm_x86_ops->skip_emulated_instruction(vcpu);
5895 return kvm_vcpu_halt(vcpu);
5896 }
5897 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5898
5899 /*
5900 * kvm_pv_kick_cpu_op: Kick a vcpu.
5901 *
5902 * @apicid - apicid of vcpu to be kicked.
5903 */
5904 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5905 {
5906 struct kvm_lapic_irq lapic_irq;
5907
5908 lapic_irq.shorthand = 0;
5909 lapic_irq.dest_mode = 0;
5910 lapic_irq.dest_id = apicid;
5911 lapic_irq.msi_redir_hint = false;
5912
5913 lapic_irq.delivery_mode = APIC_DM_REMRD;
5914 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5915 }
5916
5917 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5918 {
5919 vcpu->arch.apicv_active = false;
5920 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5921 }
5922
5923 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5924 {
5925 unsigned long nr, a0, a1, a2, a3, ret;
5926 int op_64_bit, r = 1;
5927
5928 kvm_x86_ops->skip_emulated_instruction(vcpu);
5929
5930 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5931 return kvm_hv_hypercall(vcpu);
5932
5933 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5934 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5935 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5936 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5937 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5938
5939 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5940
5941 op_64_bit = is_64_bit_mode(vcpu);
5942 if (!op_64_bit) {
5943 nr &= 0xFFFFFFFF;
5944 a0 &= 0xFFFFFFFF;
5945 a1 &= 0xFFFFFFFF;
5946 a2 &= 0xFFFFFFFF;
5947 a3 &= 0xFFFFFFFF;
5948 }
5949
5950 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5951 ret = -KVM_EPERM;
5952 goto out;
5953 }
5954
5955 switch (nr) {
5956 case KVM_HC_VAPIC_POLL_IRQ:
5957 ret = 0;
5958 break;
5959 case KVM_HC_KICK_CPU:
5960 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5961 ret = 0;
5962 break;
5963 default:
5964 ret = -KVM_ENOSYS;
5965 break;
5966 }
5967 out:
5968 if (!op_64_bit)
5969 ret = (u32)ret;
5970 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5971 ++vcpu->stat.hypercalls;
5972 return r;
5973 }
5974 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5975
5976 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5977 {
5978 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5979 char instruction[3];
5980 unsigned long rip = kvm_rip_read(vcpu);
5981
5982 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5983
5984 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5985 }
5986
5987 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5988 {
5989 return vcpu->run->request_interrupt_window &&
5990 likely(!pic_in_kernel(vcpu->kvm));
5991 }
5992
5993 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5994 {
5995 struct kvm_run *kvm_run = vcpu->run;
5996
5997 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5998 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
5999 kvm_run->cr8 = kvm_get_cr8(vcpu);
6000 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6001 kvm_run->ready_for_interrupt_injection =
6002 pic_in_kernel(vcpu->kvm) ||
6003 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6004 }
6005
6006 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6007 {
6008 int max_irr, tpr;
6009
6010 if (!kvm_x86_ops->update_cr8_intercept)
6011 return;
6012
6013 if (!vcpu->arch.apic)
6014 return;
6015
6016 if (vcpu->arch.apicv_active)
6017 return;
6018
6019 if (!vcpu->arch.apic->vapic_addr)
6020 max_irr = kvm_lapic_find_highest_irr(vcpu);
6021 else
6022 max_irr = -1;
6023
6024 if (max_irr != -1)
6025 max_irr >>= 4;
6026
6027 tpr = kvm_lapic_get_cr8(vcpu);
6028
6029 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6030 }
6031
6032 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6033 {
6034 int r;
6035
6036 /* try to reinject previous events if any */
6037 if (vcpu->arch.exception.pending) {
6038 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6039 vcpu->arch.exception.has_error_code,
6040 vcpu->arch.exception.error_code);
6041
6042 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6043 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6044 X86_EFLAGS_RF);
6045
6046 if (vcpu->arch.exception.nr == DB_VECTOR &&
6047 (vcpu->arch.dr7 & DR7_GD)) {
6048 vcpu->arch.dr7 &= ~DR7_GD;
6049 kvm_update_dr7(vcpu);
6050 }
6051
6052 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6053 vcpu->arch.exception.has_error_code,
6054 vcpu->arch.exception.error_code,
6055 vcpu->arch.exception.reinject);
6056 return 0;
6057 }
6058
6059 if (vcpu->arch.nmi_injected) {
6060 kvm_x86_ops->set_nmi(vcpu);
6061 return 0;
6062 }
6063
6064 if (vcpu->arch.interrupt.pending) {
6065 kvm_x86_ops->set_irq(vcpu);
6066 return 0;
6067 }
6068
6069 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6070 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6071 if (r != 0)
6072 return r;
6073 }
6074
6075 /* try to inject new event if pending */
6076 if (vcpu->arch.nmi_pending) {
6077 if (kvm_x86_ops->nmi_allowed(vcpu)) {
6078 --vcpu->arch.nmi_pending;
6079 vcpu->arch.nmi_injected = true;
6080 kvm_x86_ops->set_nmi(vcpu);
6081 }
6082 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6083 /*
6084 * Because interrupts can be injected asynchronously, we are
6085 * calling check_nested_events again here to avoid a race condition.
6086 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6087 * proposal and current concerns. Perhaps we should be setting
6088 * KVM_REQ_EVENT only on certain events and not unconditionally?
6089 */
6090 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6091 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6092 if (r != 0)
6093 return r;
6094 }
6095 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6096 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6097 false);
6098 kvm_x86_ops->set_irq(vcpu);
6099 }
6100 }
6101 return 0;
6102 }
6103
6104 static void process_nmi(struct kvm_vcpu *vcpu)
6105 {
6106 unsigned limit = 2;
6107
6108 /*
6109 * x86 is limited to one NMI running, and one NMI pending after it.
6110 * If an NMI is already in progress, limit further NMIs to just one.
6111 * Otherwise, allow two (and we'll inject the first one immediately).
6112 */
6113 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6114 limit = 1;
6115
6116 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6117 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6118 kvm_make_request(KVM_REQ_EVENT, vcpu);
6119 }
6120
6121 #define put_smstate(type, buf, offset, val) \
6122 *(type *)((buf) + (offset) - 0x7e00) = val
6123
6124 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6125 {
6126 u32 flags = 0;
6127 flags |= seg->g << 23;
6128 flags |= seg->db << 22;
6129 flags |= seg->l << 21;
6130 flags |= seg->avl << 20;
6131 flags |= seg->present << 15;
6132 flags |= seg->dpl << 13;
6133 flags |= seg->s << 12;
6134 flags |= seg->type << 8;
6135 return flags;
6136 }
6137
6138 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6139 {
6140 struct kvm_segment seg;
6141 int offset;
6142
6143 kvm_get_segment(vcpu, &seg, n);
6144 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6145
6146 if (n < 3)
6147 offset = 0x7f84 + n * 12;
6148 else
6149 offset = 0x7f2c + (n - 3) * 12;
6150
6151 put_smstate(u32, buf, offset + 8, seg.base);
6152 put_smstate(u32, buf, offset + 4, seg.limit);
6153 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6154 }
6155
6156 #ifdef CONFIG_X86_64
6157 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6158 {
6159 struct kvm_segment seg;
6160 int offset;
6161 u16 flags;
6162
6163 kvm_get_segment(vcpu, &seg, n);
6164 offset = 0x7e00 + n * 16;
6165
6166 flags = process_smi_get_segment_flags(&seg) >> 8;
6167 put_smstate(u16, buf, offset, seg.selector);
6168 put_smstate(u16, buf, offset + 2, flags);
6169 put_smstate(u32, buf, offset + 4, seg.limit);
6170 put_smstate(u64, buf, offset + 8, seg.base);
6171 }
6172 #endif
6173
6174 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6175 {
6176 struct desc_ptr dt;
6177 struct kvm_segment seg;
6178 unsigned long val;
6179 int i;
6180
6181 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6182 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6183 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6184 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6185
6186 for (i = 0; i < 8; i++)
6187 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6188
6189 kvm_get_dr(vcpu, 6, &val);
6190 put_smstate(u32, buf, 0x7fcc, (u32)val);
6191 kvm_get_dr(vcpu, 7, &val);
6192 put_smstate(u32, buf, 0x7fc8, (u32)val);
6193
6194 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6195 put_smstate(u32, buf, 0x7fc4, seg.selector);
6196 put_smstate(u32, buf, 0x7f64, seg.base);
6197 put_smstate(u32, buf, 0x7f60, seg.limit);
6198 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6199
6200 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6201 put_smstate(u32, buf, 0x7fc0, seg.selector);
6202 put_smstate(u32, buf, 0x7f80, seg.base);
6203 put_smstate(u32, buf, 0x7f7c, seg.limit);
6204 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6205
6206 kvm_x86_ops->get_gdt(vcpu, &dt);
6207 put_smstate(u32, buf, 0x7f74, dt.address);
6208 put_smstate(u32, buf, 0x7f70, dt.size);
6209
6210 kvm_x86_ops->get_idt(vcpu, &dt);
6211 put_smstate(u32, buf, 0x7f58, dt.address);
6212 put_smstate(u32, buf, 0x7f54, dt.size);
6213
6214 for (i = 0; i < 6; i++)
6215 process_smi_save_seg_32(vcpu, buf, i);
6216
6217 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6218
6219 /* revision id */
6220 put_smstate(u32, buf, 0x7efc, 0x00020000);
6221 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6222 }
6223
6224 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6225 {
6226 #ifdef CONFIG_X86_64
6227 struct desc_ptr dt;
6228 struct kvm_segment seg;
6229 unsigned long val;
6230 int i;
6231
6232 for (i = 0; i < 16; i++)
6233 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6234
6235 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6236 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6237
6238 kvm_get_dr(vcpu, 6, &val);
6239 put_smstate(u64, buf, 0x7f68, val);
6240 kvm_get_dr(vcpu, 7, &val);
6241 put_smstate(u64, buf, 0x7f60, val);
6242
6243 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6244 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6245 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6246
6247 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6248
6249 /* revision id */
6250 put_smstate(u32, buf, 0x7efc, 0x00020064);
6251
6252 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6253
6254 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6255 put_smstate(u16, buf, 0x7e90, seg.selector);
6256 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6257 put_smstate(u32, buf, 0x7e94, seg.limit);
6258 put_smstate(u64, buf, 0x7e98, seg.base);
6259
6260 kvm_x86_ops->get_idt(vcpu, &dt);
6261 put_smstate(u32, buf, 0x7e84, dt.size);
6262 put_smstate(u64, buf, 0x7e88, dt.address);
6263
6264 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6265 put_smstate(u16, buf, 0x7e70, seg.selector);
6266 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6267 put_smstate(u32, buf, 0x7e74, seg.limit);
6268 put_smstate(u64, buf, 0x7e78, seg.base);
6269
6270 kvm_x86_ops->get_gdt(vcpu, &dt);
6271 put_smstate(u32, buf, 0x7e64, dt.size);
6272 put_smstate(u64, buf, 0x7e68, dt.address);
6273
6274 for (i = 0; i < 6; i++)
6275 process_smi_save_seg_64(vcpu, buf, i);
6276 #else
6277 WARN_ON_ONCE(1);
6278 #endif
6279 }
6280
6281 static void process_smi(struct kvm_vcpu *vcpu)
6282 {
6283 struct kvm_segment cs, ds;
6284 struct desc_ptr dt;
6285 char buf[512];
6286 u32 cr0;
6287
6288 if (is_smm(vcpu)) {
6289 vcpu->arch.smi_pending = true;
6290 return;
6291 }
6292
6293 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6294 vcpu->arch.hflags |= HF_SMM_MASK;
6295 memset(buf, 0, 512);
6296 if (guest_cpuid_has_longmode(vcpu))
6297 process_smi_save_state_64(vcpu, buf);
6298 else
6299 process_smi_save_state_32(vcpu, buf);
6300
6301 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6302
6303 if (kvm_x86_ops->get_nmi_mask(vcpu))
6304 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6305 else
6306 kvm_x86_ops->set_nmi_mask(vcpu, true);
6307
6308 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6309 kvm_rip_write(vcpu, 0x8000);
6310
6311 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6312 kvm_x86_ops->set_cr0(vcpu, cr0);
6313 vcpu->arch.cr0 = cr0;
6314
6315 kvm_x86_ops->set_cr4(vcpu, 0);
6316
6317 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6318 dt.address = dt.size = 0;
6319 kvm_x86_ops->set_idt(vcpu, &dt);
6320
6321 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6322
6323 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6324 cs.base = vcpu->arch.smbase;
6325
6326 ds.selector = 0;
6327 ds.base = 0;
6328
6329 cs.limit = ds.limit = 0xffffffff;
6330 cs.type = ds.type = 0x3;
6331 cs.dpl = ds.dpl = 0;
6332 cs.db = ds.db = 0;
6333 cs.s = ds.s = 1;
6334 cs.l = ds.l = 0;
6335 cs.g = ds.g = 1;
6336 cs.avl = ds.avl = 0;
6337 cs.present = ds.present = 1;
6338 cs.unusable = ds.unusable = 0;
6339 cs.padding = ds.padding = 0;
6340
6341 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6342 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6343 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6344 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6345 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6346 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6347
6348 if (guest_cpuid_has_longmode(vcpu))
6349 kvm_x86_ops->set_efer(vcpu, 0);
6350
6351 kvm_update_cpuid(vcpu);
6352 kvm_mmu_reset_context(vcpu);
6353 }
6354
6355 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6356 {
6357 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6358 }
6359
6360 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6361 {
6362 u64 eoi_exit_bitmap[4];
6363
6364 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6365 return;
6366
6367 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6368
6369 if (irqchip_split(vcpu->kvm))
6370 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6371 else {
6372 if (vcpu->arch.apicv_active)
6373 kvm_x86_ops->sync_pir_to_irr(vcpu);
6374 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6375 }
6376 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6377 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6378 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6379 }
6380
6381 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6382 {
6383 ++vcpu->stat.tlb_flush;
6384 kvm_x86_ops->tlb_flush(vcpu);
6385 }
6386
6387 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6388 {
6389 struct page *page = NULL;
6390
6391 if (!lapic_in_kernel(vcpu))
6392 return;
6393
6394 if (!kvm_x86_ops->set_apic_access_page_addr)
6395 return;
6396
6397 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6398 if (is_error_page(page))
6399 return;
6400 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6401
6402 /*
6403 * Do not pin apic access page in memory, the MMU notifier
6404 * will call us again if it is migrated or swapped out.
6405 */
6406 put_page(page);
6407 }
6408 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6409
6410 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6411 unsigned long address)
6412 {
6413 /*
6414 * The physical address of apic access page is stored in the VMCS.
6415 * Update it when it becomes invalid.
6416 */
6417 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6418 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6419 }
6420
6421 /*
6422 * Returns 1 to let vcpu_run() continue the guest execution loop without
6423 * exiting to the userspace. Otherwise, the value will be returned to the
6424 * userspace.
6425 */
6426 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6427 {
6428 int r;
6429 bool req_int_win =
6430 dm_request_for_irq_injection(vcpu) &&
6431 kvm_cpu_accept_dm_intr(vcpu);
6432
6433 bool req_immediate_exit = false;
6434
6435 if (vcpu->requests) {
6436 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6437 kvm_mmu_unload(vcpu);
6438 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6439 __kvm_migrate_timers(vcpu);
6440 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6441 kvm_gen_update_masterclock(vcpu->kvm);
6442 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6443 kvm_gen_kvmclock_update(vcpu);
6444 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6445 r = kvm_guest_time_update(vcpu);
6446 if (unlikely(r))
6447 goto out;
6448 }
6449 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6450 kvm_mmu_sync_roots(vcpu);
6451 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6452 kvm_vcpu_flush_tlb(vcpu);
6453 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6454 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6455 r = 0;
6456 goto out;
6457 }
6458 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6459 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6460 r = 0;
6461 goto out;
6462 }
6463 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6464 vcpu->fpu_active = 0;
6465 kvm_x86_ops->fpu_deactivate(vcpu);
6466 }
6467 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6468 /* Page is swapped out. Do synthetic halt */
6469 vcpu->arch.apf.halted = true;
6470 r = 1;
6471 goto out;
6472 }
6473 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6474 record_steal_time(vcpu);
6475 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6476 process_smi(vcpu);
6477 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6478 process_nmi(vcpu);
6479 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6480 kvm_pmu_handle_event(vcpu);
6481 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6482 kvm_pmu_deliver_pmi(vcpu);
6483 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6484 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6485 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6486 vcpu->arch.ioapic_handled_vectors)) {
6487 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6488 vcpu->run->eoi.vector =
6489 vcpu->arch.pending_ioapic_eoi;
6490 r = 0;
6491 goto out;
6492 }
6493 }
6494 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6495 vcpu_scan_ioapic(vcpu);
6496 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6497 kvm_vcpu_reload_apic_access_page(vcpu);
6498 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6499 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6500 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6501 r = 0;
6502 goto out;
6503 }
6504 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6505 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6506 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6507 r = 0;
6508 goto out;
6509 }
6510 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6511 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6512 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6513 r = 0;
6514 goto out;
6515 }
6516
6517 /*
6518 * KVM_REQ_HV_STIMER has to be processed after
6519 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6520 * depend on the guest clock being up-to-date
6521 */
6522 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6523 kvm_hv_process_stimers(vcpu);
6524 }
6525
6526 /*
6527 * KVM_REQ_EVENT is not set when posted interrupts are set by
6528 * VT-d hardware, so we have to update RVI unconditionally.
6529 */
6530 if (kvm_lapic_enabled(vcpu)) {
6531 /*
6532 * Update architecture specific hints for APIC
6533 * virtual interrupt delivery.
6534 */
6535 if (vcpu->arch.apicv_active)
6536 kvm_x86_ops->hwapic_irr_update(vcpu,
6537 kvm_lapic_find_highest_irr(vcpu));
6538 }
6539
6540 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6541 kvm_apic_accept_events(vcpu);
6542 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6543 r = 1;
6544 goto out;
6545 }
6546
6547 if (inject_pending_event(vcpu, req_int_win) != 0)
6548 req_immediate_exit = true;
6549 /* enable NMI/IRQ window open exits if needed */
6550 else if (vcpu->arch.nmi_pending)
6551 kvm_x86_ops->enable_nmi_window(vcpu);
6552 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6553 kvm_x86_ops->enable_irq_window(vcpu);
6554
6555 if (kvm_lapic_enabled(vcpu)) {
6556 update_cr8_intercept(vcpu);
6557 kvm_lapic_sync_to_vapic(vcpu);
6558 }
6559 }
6560
6561 r = kvm_mmu_reload(vcpu);
6562 if (unlikely(r)) {
6563 goto cancel_injection;
6564 }
6565
6566 preempt_disable();
6567
6568 kvm_x86_ops->prepare_guest_switch(vcpu);
6569 if (vcpu->fpu_active)
6570 kvm_load_guest_fpu(vcpu);
6571 kvm_load_guest_xcr0(vcpu);
6572
6573 vcpu->mode = IN_GUEST_MODE;
6574
6575 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6576
6577 /* We should set ->mode before check ->requests,
6578 * see the comment in make_all_cpus_request.
6579 */
6580 smp_mb__after_srcu_read_unlock();
6581
6582 local_irq_disable();
6583
6584 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6585 || need_resched() || signal_pending(current)) {
6586 vcpu->mode = OUTSIDE_GUEST_MODE;
6587 smp_wmb();
6588 local_irq_enable();
6589 preempt_enable();
6590 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6591 r = 1;
6592 goto cancel_injection;
6593 }
6594
6595 if (req_immediate_exit)
6596 smp_send_reschedule(vcpu->cpu);
6597
6598 trace_kvm_entry(vcpu->vcpu_id);
6599 wait_lapic_expire(vcpu);
6600 __kvm_guest_enter();
6601
6602 if (unlikely(vcpu->arch.switch_db_regs)) {
6603 set_debugreg(0, 7);
6604 set_debugreg(vcpu->arch.eff_db[0], 0);
6605 set_debugreg(vcpu->arch.eff_db[1], 1);
6606 set_debugreg(vcpu->arch.eff_db[2], 2);
6607 set_debugreg(vcpu->arch.eff_db[3], 3);
6608 set_debugreg(vcpu->arch.dr6, 6);
6609 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6610 }
6611
6612 kvm_x86_ops->run(vcpu);
6613
6614 /*
6615 * Do this here before restoring debug registers on the host. And
6616 * since we do this before handling the vmexit, a DR access vmexit
6617 * can (a) read the correct value of the debug registers, (b) set
6618 * KVM_DEBUGREG_WONT_EXIT again.
6619 */
6620 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6621 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6622 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6623 kvm_update_dr0123(vcpu);
6624 kvm_update_dr6(vcpu);
6625 kvm_update_dr7(vcpu);
6626 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6627 }
6628
6629 /*
6630 * If the guest has used debug registers, at least dr7
6631 * will be disabled while returning to the host.
6632 * If we don't have active breakpoints in the host, we don't
6633 * care about the messed up debug address registers. But if
6634 * we have some of them active, restore the old state.
6635 */
6636 if (hw_breakpoint_active())
6637 hw_breakpoint_restore();
6638
6639 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6640
6641 vcpu->mode = OUTSIDE_GUEST_MODE;
6642 smp_wmb();
6643
6644 /* Interrupt is enabled by handle_external_intr() */
6645 kvm_x86_ops->handle_external_intr(vcpu);
6646
6647 ++vcpu->stat.exits;
6648
6649 /*
6650 * We must have an instruction between local_irq_enable() and
6651 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6652 * the interrupt shadow. The stat.exits increment will do nicely.
6653 * But we need to prevent reordering, hence this barrier():
6654 */
6655 barrier();
6656
6657 kvm_guest_exit();
6658
6659 preempt_enable();
6660
6661 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6662
6663 /*
6664 * Profile KVM exit RIPs:
6665 */
6666 if (unlikely(prof_on == KVM_PROFILING)) {
6667 unsigned long rip = kvm_rip_read(vcpu);
6668 profile_hit(KVM_PROFILING, (void *)rip);
6669 }
6670
6671 if (unlikely(vcpu->arch.tsc_always_catchup))
6672 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6673
6674 if (vcpu->arch.apic_attention)
6675 kvm_lapic_sync_from_vapic(vcpu);
6676
6677 r = kvm_x86_ops->handle_exit(vcpu);
6678 return r;
6679
6680 cancel_injection:
6681 kvm_x86_ops->cancel_injection(vcpu);
6682 if (unlikely(vcpu->arch.apic_attention))
6683 kvm_lapic_sync_from_vapic(vcpu);
6684 out:
6685 return r;
6686 }
6687
6688 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6689 {
6690 if (!kvm_arch_vcpu_runnable(vcpu) &&
6691 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6692 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6693 kvm_vcpu_block(vcpu);
6694 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6695
6696 if (kvm_x86_ops->post_block)
6697 kvm_x86_ops->post_block(vcpu);
6698
6699 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6700 return 1;
6701 }
6702
6703 kvm_apic_accept_events(vcpu);
6704 switch(vcpu->arch.mp_state) {
6705 case KVM_MP_STATE_HALTED:
6706 vcpu->arch.pv.pv_unhalted = false;
6707 vcpu->arch.mp_state =
6708 KVM_MP_STATE_RUNNABLE;
6709 case KVM_MP_STATE_RUNNABLE:
6710 vcpu->arch.apf.halted = false;
6711 break;
6712 case KVM_MP_STATE_INIT_RECEIVED:
6713 break;
6714 default:
6715 return -EINTR;
6716 break;
6717 }
6718 return 1;
6719 }
6720
6721 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6722 {
6723 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6724 !vcpu->arch.apf.halted);
6725 }
6726
6727 static int vcpu_run(struct kvm_vcpu *vcpu)
6728 {
6729 int r;
6730 struct kvm *kvm = vcpu->kvm;
6731
6732 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6733
6734 for (;;) {
6735 if (kvm_vcpu_running(vcpu)) {
6736 r = vcpu_enter_guest(vcpu);
6737 } else {
6738 r = vcpu_block(kvm, vcpu);
6739 }
6740
6741 if (r <= 0)
6742 break;
6743
6744 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6745 if (kvm_cpu_has_pending_timer(vcpu))
6746 kvm_inject_pending_timer_irqs(vcpu);
6747
6748 if (dm_request_for_irq_injection(vcpu) &&
6749 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6750 r = 0;
6751 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6752 ++vcpu->stat.request_irq_exits;
6753 break;
6754 }
6755
6756 kvm_check_async_pf_completion(vcpu);
6757
6758 if (signal_pending(current)) {
6759 r = -EINTR;
6760 vcpu->run->exit_reason = KVM_EXIT_INTR;
6761 ++vcpu->stat.signal_exits;
6762 break;
6763 }
6764 if (need_resched()) {
6765 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6766 cond_resched();
6767 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6768 }
6769 }
6770
6771 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6772
6773 return r;
6774 }
6775
6776 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6777 {
6778 int r;
6779 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6780 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6781 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6782 if (r != EMULATE_DONE)
6783 return 0;
6784 return 1;
6785 }
6786
6787 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6788 {
6789 BUG_ON(!vcpu->arch.pio.count);
6790
6791 return complete_emulated_io(vcpu);
6792 }
6793
6794 /*
6795 * Implements the following, as a state machine:
6796 *
6797 * read:
6798 * for each fragment
6799 * for each mmio piece in the fragment
6800 * write gpa, len
6801 * exit
6802 * copy data
6803 * execute insn
6804 *
6805 * write:
6806 * for each fragment
6807 * for each mmio piece in the fragment
6808 * write gpa, len
6809 * copy data
6810 * exit
6811 */
6812 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6813 {
6814 struct kvm_run *run = vcpu->run;
6815 struct kvm_mmio_fragment *frag;
6816 unsigned len;
6817
6818 BUG_ON(!vcpu->mmio_needed);
6819
6820 /* Complete previous fragment */
6821 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6822 len = min(8u, frag->len);
6823 if (!vcpu->mmio_is_write)
6824 memcpy(frag->data, run->mmio.data, len);
6825
6826 if (frag->len <= 8) {
6827 /* Switch to the next fragment. */
6828 frag++;
6829 vcpu->mmio_cur_fragment++;
6830 } else {
6831 /* Go forward to the next mmio piece. */
6832 frag->data += len;
6833 frag->gpa += len;
6834 frag->len -= len;
6835 }
6836
6837 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6838 vcpu->mmio_needed = 0;
6839
6840 /* FIXME: return into emulator if single-stepping. */
6841 if (vcpu->mmio_is_write)
6842 return 1;
6843 vcpu->mmio_read_completed = 1;
6844 return complete_emulated_io(vcpu);
6845 }
6846
6847 run->exit_reason = KVM_EXIT_MMIO;
6848 run->mmio.phys_addr = frag->gpa;
6849 if (vcpu->mmio_is_write)
6850 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6851 run->mmio.len = min(8u, frag->len);
6852 run->mmio.is_write = vcpu->mmio_is_write;
6853 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6854 return 0;
6855 }
6856
6857
6858 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6859 {
6860 struct fpu *fpu = &current->thread.fpu;
6861 int r;
6862 sigset_t sigsaved;
6863
6864 fpu__activate_curr(fpu);
6865
6866 if (vcpu->sigset_active)
6867 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6868
6869 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6870 kvm_vcpu_block(vcpu);
6871 kvm_apic_accept_events(vcpu);
6872 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6873 r = -EAGAIN;
6874 goto out;
6875 }
6876
6877 /* re-sync apic's tpr */
6878 if (!lapic_in_kernel(vcpu)) {
6879 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6880 r = -EINVAL;
6881 goto out;
6882 }
6883 }
6884
6885 if (unlikely(vcpu->arch.complete_userspace_io)) {
6886 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6887 vcpu->arch.complete_userspace_io = NULL;
6888 r = cui(vcpu);
6889 if (r <= 0)
6890 goto out;
6891 } else
6892 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6893
6894 r = vcpu_run(vcpu);
6895
6896 out:
6897 post_kvm_run_save(vcpu);
6898 if (vcpu->sigset_active)
6899 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6900
6901 return r;
6902 }
6903
6904 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6905 {
6906 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6907 /*
6908 * We are here if userspace calls get_regs() in the middle of
6909 * instruction emulation. Registers state needs to be copied
6910 * back from emulation context to vcpu. Userspace shouldn't do
6911 * that usually, but some bad designed PV devices (vmware
6912 * backdoor interface) need this to work
6913 */
6914 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6915 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6916 }
6917 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6918 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6919 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6920 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6921 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6922 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6923 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6924 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6925 #ifdef CONFIG_X86_64
6926 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6927 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6928 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6929 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6930 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6931 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6932 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6933 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6934 #endif
6935
6936 regs->rip = kvm_rip_read(vcpu);
6937 regs->rflags = kvm_get_rflags(vcpu);
6938
6939 return 0;
6940 }
6941
6942 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6943 {
6944 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6945 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6946
6947 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6948 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6949 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6950 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6951 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6952 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6953 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6954 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6955 #ifdef CONFIG_X86_64
6956 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6957 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6958 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6959 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6960 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6961 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6962 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6963 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6964 #endif
6965
6966 kvm_rip_write(vcpu, regs->rip);
6967 kvm_set_rflags(vcpu, regs->rflags);
6968
6969 vcpu->arch.exception.pending = false;
6970
6971 kvm_make_request(KVM_REQ_EVENT, vcpu);
6972
6973 return 0;
6974 }
6975
6976 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6977 {
6978 struct kvm_segment cs;
6979
6980 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6981 *db = cs.db;
6982 *l = cs.l;
6983 }
6984 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6985
6986 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6987 struct kvm_sregs *sregs)
6988 {
6989 struct desc_ptr dt;
6990
6991 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6992 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6993 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6994 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6995 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6996 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6997
6998 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6999 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7000
7001 kvm_x86_ops->get_idt(vcpu, &dt);
7002 sregs->idt.limit = dt.size;
7003 sregs->idt.base = dt.address;
7004 kvm_x86_ops->get_gdt(vcpu, &dt);
7005 sregs->gdt.limit = dt.size;
7006 sregs->gdt.base = dt.address;
7007
7008 sregs->cr0 = kvm_read_cr0(vcpu);
7009 sregs->cr2 = vcpu->arch.cr2;
7010 sregs->cr3 = kvm_read_cr3(vcpu);
7011 sregs->cr4 = kvm_read_cr4(vcpu);
7012 sregs->cr8 = kvm_get_cr8(vcpu);
7013 sregs->efer = vcpu->arch.efer;
7014 sregs->apic_base = kvm_get_apic_base(vcpu);
7015
7016 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7017
7018 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7019 set_bit(vcpu->arch.interrupt.nr,
7020 (unsigned long *)sregs->interrupt_bitmap);
7021
7022 return 0;
7023 }
7024
7025 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7026 struct kvm_mp_state *mp_state)
7027 {
7028 kvm_apic_accept_events(vcpu);
7029 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7030 vcpu->arch.pv.pv_unhalted)
7031 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7032 else
7033 mp_state->mp_state = vcpu->arch.mp_state;
7034
7035 return 0;
7036 }
7037
7038 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7039 struct kvm_mp_state *mp_state)
7040 {
7041 if (!kvm_vcpu_has_lapic(vcpu) &&
7042 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7043 return -EINVAL;
7044
7045 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7046 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7047 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7048 } else
7049 vcpu->arch.mp_state = mp_state->mp_state;
7050 kvm_make_request(KVM_REQ_EVENT, vcpu);
7051 return 0;
7052 }
7053
7054 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7055 int reason, bool has_error_code, u32 error_code)
7056 {
7057 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7058 int ret;
7059
7060 init_emulate_ctxt(vcpu);
7061
7062 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7063 has_error_code, error_code);
7064
7065 if (ret)
7066 return EMULATE_FAIL;
7067
7068 kvm_rip_write(vcpu, ctxt->eip);
7069 kvm_set_rflags(vcpu, ctxt->eflags);
7070 kvm_make_request(KVM_REQ_EVENT, vcpu);
7071 return EMULATE_DONE;
7072 }
7073 EXPORT_SYMBOL_GPL(kvm_task_switch);
7074
7075 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7076 struct kvm_sregs *sregs)
7077 {
7078 struct msr_data apic_base_msr;
7079 int mmu_reset_needed = 0;
7080 int pending_vec, max_bits, idx;
7081 struct desc_ptr dt;
7082
7083 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7084 return -EINVAL;
7085
7086 dt.size = sregs->idt.limit;
7087 dt.address = sregs->idt.base;
7088 kvm_x86_ops->set_idt(vcpu, &dt);
7089 dt.size = sregs->gdt.limit;
7090 dt.address = sregs->gdt.base;
7091 kvm_x86_ops->set_gdt(vcpu, &dt);
7092
7093 vcpu->arch.cr2 = sregs->cr2;
7094 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7095 vcpu->arch.cr3 = sregs->cr3;
7096 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7097
7098 kvm_set_cr8(vcpu, sregs->cr8);
7099
7100 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7101 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7102 apic_base_msr.data = sregs->apic_base;
7103 apic_base_msr.host_initiated = true;
7104 kvm_set_apic_base(vcpu, &apic_base_msr);
7105
7106 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7107 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7108 vcpu->arch.cr0 = sregs->cr0;
7109
7110 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7111 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7112 if (sregs->cr4 & X86_CR4_OSXSAVE)
7113 kvm_update_cpuid(vcpu);
7114
7115 idx = srcu_read_lock(&vcpu->kvm->srcu);
7116 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7117 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7118 mmu_reset_needed = 1;
7119 }
7120 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7121
7122 if (mmu_reset_needed)
7123 kvm_mmu_reset_context(vcpu);
7124
7125 max_bits = KVM_NR_INTERRUPTS;
7126 pending_vec = find_first_bit(
7127 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7128 if (pending_vec < max_bits) {
7129 kvm_queue_interrupt(vcpu, pending_vec, false);
7130 pr_debug("Set back pending irq %d\n", pending_vec);
7131 }
7132
7133 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7134 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7135 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7136 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7137 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7138 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7139
7140 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7141 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7142
7143 update_cr8_intercept(vcpu);
7144
7145 /* Older userspace won't unhalt the vcpu on reset. */
7146 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7147 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7148 !is_protmode(vcpu))
7149 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7150
7151 kvm_make_request(KVM_REQ_EVENT, vcpu);
7152
7153 return 0;
7154 }
7155
7156 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7157 struct kvm_guest_debug *dbg)
7158 {
7159 unsigned long rflags;
7160 int i, r;
7161
7162 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7163 r = -EBUSY;
7164 if (vcpu->arch.exception.pending)
7165 goto out;
7166 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7167 kvm_queue_exception(vcpu, DB_VECTOR);
7168 else
7169 kvm_queue_exception(vcpu, BP_VECTOR);
7170 }
7171
7172 /*
7173 * Read rflags as long as potentially injected trace flags are still
7174 * filtered out.
7175 */
7176 rflags = kvm_get_rflags(vcpu);
7177
7178 vcpu->guest_debug = dbg->control;
7179 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7180 vcpu->guest_debug = 0;
7181
7182 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7183 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7184 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7185 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7186 } else {
7187 for (i = 0; i < KVM_NR_DB_REGS; i++)
7188 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7189 }
7190 kvm_update_dr7(vcpu);
7191
7192 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7193 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7194 get_segment_base(vcpu, VCPU_SREG_CS);
7195
7196 /*
7197 * Trigger an rflags update that will inject or remove the trace
7198 * flags.
7199 */
7200 kvm_set_rflags(vcpu, rflags);
7201
7202 kvm_x86_ops->update_bp_intercept(vcpu);
7203
7204 r = 0;
7205
7206 out:
7207
7208 return r;
7209 }
7210
7211 /*
7212 * Translate a guest virtual address to a guest physical address.
7213 */
7214 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7215 struct kvm_translation *tr)
7216 {
7217 unsigned long vaddr = tr->linear_address;
7218 gpa_t gpa;
7219 int idx;
7220
7221 idx = srcu_read_lock(&vcpu->kvm->srcu);
7222 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7223 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7224 tr->physical_address = gpa;
7225 tr->valid = gpa != UNMAPPED_GVA;
7226 tr->writeable = 1;
7227 tr->usermode = 0;
7228
7229 return 0;
7230 }
7231
7232 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7233 {
7234 struct fxregs_state *fxsave =
7235 &vcpu->arch.guest_fpu.state.fxsave;
7236
7237 memcpy(fpu->fpr, fxsave->st_space, 128);
7238 fpu->fcw = fxsave->cwd;
7239 fpu->fsw = fxsave->swd;
7240 fpu->ftwx = fxsave->twd;
7241 fpu->last_opcode = fxsave->fop;
7242 fpu->last_ip = fxsave->rip;
7243 fpu->last_dp = fxsave->rdp;
7244 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7245
7246 return 0;
7247 }
7248
7249 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7250 {
7251 struct fxregs_state *fxsave =
7252 &vcpu->arch.guest_fpu.state.fxsave;
7253
7254 memcpy(fxsave->st_space, fpu->fpr, 128);
7255 fxsave->cwd = fpu->fcw;
7256 fxsave->swd = fpu->fsw;
7257 fxsave->twd = fpu->ftwx;
7258 fxsave->fop = fpu->last_opcode;
7259 fxsave->rip = fpu->last_ip;
7260 fxsave->rdp = fpu->last_dp;
7261 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7262
7263 return 0;
7264 }
7265
7266 static void fx_init(struct kvm_vcpu *vcpu)
7267 {
7268 fpstate_init(&vcpu->arch.guest_fpu.state);
7269 if (cpu_has_xsaves)
7270 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7271 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7272
7273 /*
7274 * Ensure guest xcr0 is valid for loading
7275 */
7276 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7277
7278 vcpu->arch.cr0 |= X86_CR0_ET;
7279 }
7280
7281 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7282 {
7283 if (vcpu->guest_fpu_loaded)
7284 return;
7285
7286 /*
7287 * Restore all possible states in the guest,
7288 * and assume host would use all available bits.
7289 * Guest xcr0 would be loaded later.
7290 */
7291 kvm_put_guest_xcr0(vcpu);
7292 vcpu->guest_fpu_loaded = 1;
7293 __kernel_fpu_begin();
7294 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7295 trace_kvm_fpu(1);
7296 }
7297
7298 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7299 {
7300 kvm_put_guest_xcr0(vcpu);
7301
7302 if (!vcpu->guest_fpu_loaded) {
7303 vcpu->fpu_counter = 0;
7304 return;
7305 }
7306
7307 vcpu->guest_fpu_loaded = 0;
7308 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7309 __kernel_fpu_end();
7310 ++vcpu->stat.fpu_reload;
7311 /*
7312 * If using eager FPU mode, or if the guest is a frequent user
7313 * of the FPU, just leave the FPU active for next time.
7314 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7315 * the FPU in bursts will revert to loading it on demand.
7316 */
7317 if (!vcpu->arch.eager_fpu) {
7318 if (++vcpu->fpu_counter < 5)
7319 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7320 }
7321 trace_kvm_fpu(0);
7322 }
7323
7324 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7325 {
7326 kvmclock_reset(vcpu);
7327
7328 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7329 kvm_x86_ops->vcpu_free(vcpu);
7330 }
7331
7332 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7333 unsigned int id)
7334 {
7335 struct kvm_vcpu *vcpu;
7336
7337 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7338 printk_once(KERN_WARNING
7339 "kvm: SMP vm created on host with unstable TSC; "
7340 "guest TSC will not be reliable\n");
7341
7342 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7343
7344 return vcpu;
7345 }
7346
7347 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7348 {
7349 int r;
7350
7351 kvm_vcpu_mtrr_init(vcpu);
7352 r = vcpu_load(vcpu);
7353 if (r)
7354 return r;
7355 kvm_vcpu_reset(vcpu, false);
7356 kvm_mmu_setup(vcpu);
7357 vcpu_put(vcpu);
7358 return r;
7359 }
7360
7361 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7362 {
7363 struct msr_data msr;
7364 struct kvm *kvm = vcpu->kvm;
7365
7366 if (vcpu_load(vcpu))
7367 return;
7368 msr.data = 0x0;
7369 msr.index = MSR_IA32_TSC;
7370 msr.host_initiated = true;
7371 kvm_write_tsc(vcpu, &msr);
7372 vcpu_put(vcpu);
7373
7374 if (!kvmclock_periodic_sync)
7375 return;
7376
7377 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7378 KVMCLOCK_SYNC_PERIOD);
7379 }
7380
7381 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7382 {
7383 int r;
7384 vcpu->arch.apf.msr_val = 0;
7385
7386 r = vcpu_load(vcpu);
7387 BUG_ON(r);
7388 kvm_mmu_unload(vcpu);
7389 vcpu_put(vcpu);
7390
7391 kvm_x86_ops->vcpu_free(vcpu);
7392 }
7393
7394 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7395 {
7396 vcpu->arch.hflags = 0;
7397
7398 atomic_set(&vcpu->arch.nmi_queued, 0);
7399 vcpu->arch.nmi_pending = 0;
7400 vcpu->arch.nmi_injected = false;
7401 kvm_clear_interrupt_queue(vcpu);
7402 kvm_clear_exception_queue(vcpu);
7403
7404 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7405 kvm_update_dr0123(vcpu);
7406 vcpu->arch.dr6 = DR6_INIT;
7407 kvm_update_dr6(vcpu);
7408 vcpu->arch.dr7 = DR7_FIXED_1;
7409 kvm_update_dr7(vcpu);
7410
7411 vcpu->arch.cr2 = 0;
7412
7413 kvm_make_request(KVM_REQ_EVENT, vcpu);
7414 vcpu->arch.apf.msr_val = 0;
7415 vcpu->arch.st.msr_val = 0;
7416
7417 kvmclock_reset(vcpu);
7418
7419 kvm_clear_async_pf_completion_queue(vcpu);
7420 kvm_async_pf_hash_reset(vcpu);
7421 vcpu->arch.apf.halted = false;
7422
7423 if (!init_event) {
7424 kvm_pmu_reset(vcpu);
7425 vcpu->arch.smbase = 0x30000;
7426 }
7427
7428 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7429 vcpu->arch.regs_avail = ~0;
7430 vcpu->arch.regs_dirty = ~0;
7431
7432 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7433 }
7434
7435 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7436 {
7437 struct kvm_segment cs;
7438
7439 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7440 cs.selector = vector << 8;
7441 cs.base = vector << 12;
7442 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7443 kvm_rip_write(vcpu, 0);
7444 }
7445
7446 int kvm_arch_hardware_enable(void)
7447 {
7448 struct kvm *kvm;
7449 struct kvm_vcpu *vcpu;
7450 int i;
7451 int ret;
7452 u64 local_tsc;
7453 u64 max_tsc = 0;
7454 bool stable, backwards_tsc = false;
7455
7456 kvm_shared_msr_cpu_online();
7457 ret = kvm_x86_ops->hardware_enable();
7458 if (ret != 0)
7459 return ret;
7460
7461 local_tsc = rdtsc();
7462 stable = !check_tsc_unstable();
7463 list_for_each_entry(kvm, &vm_list, vm_list) {
7464 kvm_for_each_vcpu(i, vcpu, kvm) {
7465 if (!stable && vcpu->cpu == smp_processor_id())
7466 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7467 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7468 backwards_tsc = true;
7469 if (vcpu->arch.last_host_tsc > max_tsc)
7470 max_tsc = vcpu->arch.last_host_tsc;
7471 }
7472 }
7473 }
7474
7475 /*
7476 * Sometimes, even reliable TSCs go backwards. This happens on
7477 * platforms that reset TSC during suspend or hibernate actions, but
7478 * maintain synchronization. We must compensate. Fortunately, we can
7479 * detect that condition here, which happens early in CPU bringup,
7480 * before any KVM threads can be running. Unfortunately, we can't
7481 * bring the TSCs fully up to date with real time, as we aren't yet far
7482 * enough into CPU bringup that we know how much real time has actually
7483 * elapsed; our helper function, get_kernel_ns() will be using boot
7484 * variables that haven't been updated yet.
7485 *
7486 * So we simply find the maximum observed TSC above, then record the
7487 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7488 * the adjustment will be applied. Note that we accumulate
7489 * adjustments, in case multiple suspend cycles happen before some VCPU
7490 * gets a chance to run again. In the event that no KVM threads get a
7491 * chance to run, we will miss the entire elapsed period, as we'll have
7492 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7493 * loose cycle time. This isn't too big a deal, since the loss will be
7494 * uniform across all VCPUs (not to mention the scenario is extremely
7495 * unlikely). It is possible that a second hibernate recovery happens
7496 * much faster than a first, causing the observed TSC here to be
7497 * smaller; this would require additional padding adjustment, which is
7498 * why we set last_host_tsc to the local tsc observed here.
7499 *
7500 * N.B. - this code below runs only on platforms with reliable TSC,
7501 * as that is the only way backwards_tsc is set above. Also note
7502 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7503 * have the same delta_cyc adjustment applied if backwards_tsc
7504 * is detected. Note further, this adjustment is only done once,
7505 * as we reset last_host_tsc on all VCPUs to stop this from being
7506 * called multiple times (one for each physical CPU bringup).
7507 *
7508 * Platforms with unreliable TSCs don't have to deal with this, they
7509 * will be compensated by the logic in vcpu_load, which sets the TSC to
7510 * catchup mode. This will catchup all VCPUs to real time, but cannot
7511 * guarantee that they stay in perfect synchronization.
7512 */
7513 if (backwards_tsc) {
7514 u64 delta_cyc = max_tsc - local_tsc;
7515 backwards_tsc_observed = true;
7516 list_for_each_entry(kvm, &vm_list, vm_list) {
7517 kvm_for_each_vcpu(i, vcpu, kvm) {
7518 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7519 vcpu->arch.last_host_tsc = local_tsc;
7520 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7521 }
7522
7523 /*
7524 * We have to disable TSC offset matching.. if you were
7525 * booting a VM while issuing an S4 host suspend....
7526 * you may have some problem. Solving this issue is
7527 * left as an exercise to the reader.
7528 */
7529 kvm->arch.last_tsc_nsec = 0;
7530 kvm->arch.last_tsc_write = 0;
7531 }
7532
7533 }
7534 return 0;
7535 }
7536
7537 void kvm_arch_hardware_disable(void)
7538 {
7539 kvm_x86_ops->hardware_disable();
7540 drop_user_return_notifiers();
7541 }
7542
7543 int kvm_arch_hardware_setup(void)
7544 {
7545 int r;
7546
7547 r = kvm_x86_ops->hardware_setup();
7548 if (r != 0)
7549 return r;
7550
7551 if (kvm_has_tsc_control) {
7552 /*
7553 * Make sure the user can only configure tsc_khz values that
7554 * fit into a signed integer.
7555 * A min value is not calculated needed because it will always
7556 * be 1 on all machines.
7557 */
7558 u64 max = min(0x7fffffffULL,
7559 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7560 kvm_max_guest_tsc_khz = max;
7561
7562 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7563 }
7564
7565 kvm_init_msr_list();
7566 return 0;
7567 }
7568
7569 void kvm_arch_hardware_unsetup(void)
7570 {
7571 kvm_x86_ops->hardware_unsetup();
7572 }
7573
7574 void kvm_arch_check_processor_compat(void *rtn)
7575 {
7576 kvm_x86_ops->check_processor_compatibility(rtn);
7577 }
7578
7579 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7580 {
7581 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7582 }
7583 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7584
7585 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7586 {
7587 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7588 }
7589
7590 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7591 {
7592 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7593 }
7594
7595 struct static_key kvm_no_apic_vcpu __read_mostly;
7596
7597 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7598 {
7599 struct page *page;
7600 struct kvm *kvm;
7601 int r;
7602
7603 BUG_ON(vcpu->kvm == NULL);
7604 kvm = vcpu->kvm;
7605
7606 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7607 vcpu->arch.pv.pv_unhalted = false;
7608 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7609 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7610 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7611 else
7612 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7613
7614 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7615 if (!page) {
7616 r = -ENOMEM;
7617 goto fail;
7618 }
7619 vcpu->arch.pio_data = page_address(page);
7620
7621 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7622
7623 r = kvm_mmu_create(vcpu);
7624 if (r < 0)
7625 goto fail_free_pio_data;
7626
7627 if (irqchip_in_kernel(kvm)) {
7628 r = kvm_create_lapic(vcpu);
7629 if (r < 0)
7630 goto fail_mmu_destroy;
7631 } else
7632 static_key_slow_inc(&kvm_no_apic_vcpu);
7633
7634 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7635 GFP_KERNEL);
7636 if (!vcpu->arch.mce_banks) {
7637 r = -ENOMEM;
7638 goto fail_free_lapic;
7639 }
7640 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7641
7642 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7643 r = -ENOMEM;
7644 goto fail_free_mce_banks;
7645 }
7646
7647 fx_init(vcpu);
7648
7649 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7650 vcpu->arch.pv_time_enabled = false;
7651
7652 vcpu->arch.guest_supported_xcr0 = 0;
7653 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7654
7655 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7656
7657 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7658
7659 kvm_async_pf_hash_reset(vcpu);
7660 kvm_pmu_init(vcpu);
7661
7662 vcpu->arch.pending_external_vector = -1;
7663
7664 kvm_hv_vcpu_init(vcpu);
7665
7666 return 0;
7667
7668 fail_free_mce_banks:
7669 kfree(vcpu->arch.mce_banks);
7670 fail_free_lapic:
7671 kvm_free_lapic(vcpu);
7672 fail_mmu_destroy:
7673 kvm_mmu_destroy(vcpu);
7674 fail_free_pio_data:
7675 free_page((unsigned long)vcpu->arch.pio_data);
7676 fail:
7677 return r;
7678 }
7679
7680 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7681 {
7682 int idx;
7683
7684 kvm_hv_vcpu_uninit(vcpu);
7685 kvm_pmu_destroy(vcpu);
7686 kfree(vcpu->arch.mce_banks);
7687 kvm_free_lapic(vcpu);
7688 idx = srcu_read_lock(&vcpu->kvm->srcu);
7689 kvm_mmu_destroy(vcpu);
7690 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7691 free_page((unsigned long)vcpu->arch.pio_data);
7692 if (!lapic_in_kernel(vcpu))
7693 static_key_slow_dec(&kvm_no_apic_vcpu);
7694 }
7695
7696 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7697 {
7698 kvm_x86_ops->sched_in(vcpu, cpu);
7699 }
7700
7701 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7702 {
7703 if (type)
7704 return -EINVAL;
7705
7706 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7707 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7708 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7709 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7710 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7711
7712 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7713 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7714 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7715 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7716 &kvm->arch.irq_sources_bitmap);
7717
7718 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7719 mutex_init(&kvm->arch.apic_map_lock);
7720 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7721
7722 pvclock_update_vm_gtod_copy(kvm);
7723
7724 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7725 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7726
7727 return 0;
7728 }
7729
7730 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7731 {
7732 int r;
7733 r = vcpu_load(vcpu);
7734 BUG_ON(r);
7735 kvm_mmu_unload(vcpu);
7736 vcpu_put(vcpu);
7737 }
7738
7739 static void kvm_free_vcpus(struct kvm *kvm)
7740 {
7741 unsigned int i;
7742 struct kvm_vcpu *vcpu;
7743
7744 /*
7745 * Unpin any mmu pages first.
7746 */
7747 kvm_for_each_vcpu(i, vcpu, kvm) {
7748 kvm_clear_async_pf_completion_queue(vcpu);
7749 kvm_unload_vcpu_mmu(vcpu);
7750 }
7751 kvm_for_each_vcpu(i, vcpu, kvm)
7752 kvm_arch_vcpu_free(vcpu);
7753
7754 mutex_lock(&kvm->lock);
7755 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7756 kvm->vcpus[i] = NULL;
7757
7758 atomic_set(&kvm->online_vcpus, 0);
7759 mutex_unlock(&kvm->lock);
7760 }
7761
7762 void kvm_arch_sync_events(struct kvm *kvm)
7763 {
7764 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7765 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7766 kvm_free_all_assigned_devices(kvm);
7767 kvm_free_pit(kvm);
7768 }
7769
7770 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7771 {
7772 int i, r;
7773 unsigned long hva;
7774 struct kvm_memslots *slots = kvm_memslots(kvm);
7775 struct kvm_memory_slot *slot, old;
7776
7777 /* Called with kvm->slots_lock held. */
7778 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7779 return -EINVAL;
7780
7781 slot = id_to_memslot(slots, id);
7782 if (size) {
7783 if (WARN_ON(slot->npages))
7784 return -EEXIST;
7785
7786 /*
7787 * MAP_SHARED to prevent internal slot pages from being moved
7788 * by fork()/COW.
7789 */
7790 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7791 MAP_SHARED | MAP_ANONYMOUS, 0);
7792 if (IS_ERR((void *)hva))
7793 return PTR_ERR((void *)hva);
7794 } else {
7795 if (!slot->npages)
7796 return 0;
7797
7798 hva = 0;
7799 }
7800
7801 old = *slot;
7802 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7803 struct kvm_userspace_memory_region m;
7804
7805 m.slot = id | (i << 16);
7806 m.flags = 0;
7807 m.guest_phys_addr = gpa;
7808 m.userspace_addr = hva;
7809 m.memory_size = size;
7810 r = __kvm_set_memory_region(kvm, &m);
7811 if (r < 0)
7812 return r;
7813 }
7814
7815 if (!size) {
7816 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7817 WARN_ON(r < 0);
7818 }
7819
7820 return 0;
7821 }
7822 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7823
7824 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7825 {
7826 int r;
7827
7828 mutex_lock(&kvm->slots_lock);
7829 r = __x86_set_memory_region(kvm, id, gpa, size);
7830 mutex_unlock(&kvm->slots_lock);
7831
7832 return r;
7833 }
7834 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7835
7836 void kvm_arch_destroy_vm(struct kvm *kvm)
7837 {
7838 if (current->mm == kvm->mm) {
7839 /*
7840 * Free memory regions allocated on behalf of userspace,
7841 * unless the the memory map has changed due to process exit
7842 * or fd copying.
7843 */
7844 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7845 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7846 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7847 }
7848 kvm_iommu_unmap_guest(kvm);
7849 kfree(kvm->arch.vpic);
7850 kfree(kvm->arch.vioapic);
7851 kvm_free_vcpus(kvm);
7852 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7853 }
7854
7855 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7856 struct kvm_memory_slot *dont)
7857 {
7858 int i;
7859
7860 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7861 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7862 kvfree(free->arch.rmap[i]);
7863 free->arch.rmap[i] = NULL;
7864 }
7865 if (i == 0)
7866 continue;
7867
7868 if (!dont || free->arch.lpage_info[i - 1] !=
7869 dont->arch.lpage_info[i - 1]) {
7870 kvfree(free->arch.lpage_info[i - 1]);
7871 free->arch.lpage_info[i - 1] = NULL;
7872 }
7873 }
7874 }
7875
7876 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7877 unsigned long npages)
7878 {
7879 int i;
7880
7881 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7882 unsigned long ugfn;
7883 int lpages;
7884 int level = i + 1;
7885
7886 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7887 slot->base_gfn, level) + 1;
7888
7889 slot->arch.rmap[i] =
7890 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7891 if (!slot->arch.rmap[i])
7892 goto out_free;
7893 if (i == 0)
7894 continue;
7895
7896 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7897 sizeof(*slot->arch.lpage_info[i - 1]));
7898 if (!slot->arch.lpage_info[i - 1])
7899 goto out_free;
7900
7901 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7902 slot->arch.lpage_info[i - 1][0].write_count = 1;
7903 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7904 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7905 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7906 /*
7907 * If the gfn and userspace address are not aligned wrt each
7908 * other, or if explicitly asked to, disable large page
7909 * support for this slot
7910 */
7911 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7912 !kvm_largepages_enabled()) {
7913 unsigned long j;
7914
7915 for (j = 0; j < lpages; ++j)
7916 slot->arch.lpage_info[i - 1][j].write_count = 1;
7917 }
7918 }
7919
7920 return 0;
7921
7922 out_free:
7923 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7924 kvfree(slot->arch.rmap[i]);
7925 slot->arch.rmap[i] = NULL;
7926 if (i == 0)
7927 continue;
7928
7929 kvfree(slot->arch.lpage_info[i - 1]);
7930 slot->arch.lpage_info[i - 1] = NULL;
7931 }
7932 return -ENOMEM;
7933 }
7934
7935 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7936 {
7937 /*
7938 * memslots->generation has been incremented.
7939 * mmio generation may have reached its maximum value.
7940 */
7941 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7942 }
7943
7944 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7945 struct kvm_memory_slot *memslot,
7946 const struct kvm_userspace_memory_region *mem,
7947 enum kvm_mr_change change)
7948 {
7949 return 0;
7950 }
7951
7952 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7953 struct kvm_memory_slot *new)
7954 {
7955 /* Still write protect RO slot */
7956 if (new->flags & KVM_MEM_READONLY) {
7957 kvm_mmu_slot_remove_write_access(kvm, new);
7958 return;
7959 }
7960
7961 /*
7962 * Call kvm_x86_ops dirty logging hooks when they are valid.
7963 *
7964 * kvm_x86_ops->slot_disable_log_dirty is called when:
7965 *
7966 * - KVM_MR_CREATE with dirty logging is disabled
7967 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7968 *
7969 * The reason is, in case of PML, we need to set D-bit for any slots
7970 * with dirty logging disabled in order to eliminate unnecessary GPA
7971 * logging in PML buffer (and potential PML buffer full VMEXT). This
7972 * guarantees leaving PML enabled during guest's lifetime won't have
7973 * any additonal overhead from PML when guest is running with dirty
7974 * logging disabled for memory slots.
7975 *
7976 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7977 * to dirty logging mode.
7978 *
7979 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7980 *
7981 * In case of write protect:
7982 *
7983 * Write protect all pages for dirty logging.
7984 *
7985 * All the sptes including the large sptes which point to this
7986 * slot are set to readonly. We can not create any new large
7987 * spte on this slot until the end of the logging.
7988 *
7989 * See the comments in fast_page_fault().
7990 */
7991 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7992 if (kvm_x86_ops->slot_enable_log_dirty)
7993 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7994 else
7995 kvm_mmu_slot_remove_write_access(kvm, new);
7996 } else {
7997 if (kvm_x86_ops->slot_disable_log_dirty)
7998 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7999 }
8000 }
8001
8002 void kvm_arch_commit_memory_region(struct kvm *kvm,
8003 const struct kvm_userspace_memory_region *mem,
8004 const struct kvm_memory_slot *old,
8005 const struct kvm_memory_slot *new,
8006 enum kvm_mr_change change)
8007 {
8008 int nr_mmu_pages = 0;
8009
8010 if (!kvm->arch.n_requested_mmu_pages)
8011 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8012
8013 if (nr_mmu_pages)
8014 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8015
8016 /*
8017 * Dirty logging tracks sptes in 4k granularity, meaning that large
8018 * sptes have to be split. If live migration is successful, the guest
8019 * in the source machine will be destroyed and large sptes will be
8020 * created in the destination. However, if the guest continues to run
8021 * in the source machine (for example if live migration fails), small
8022 * sptes will remain around and cause bad performance.
8023 *
8024 * Scan sptes if dirty logging has been stopped, dropping those
8025 * which can be collapsed into a single large-page spte. Later
8026 * page faults will create the large-page sptes.
8027 */
8028 if ((change != KVM_MR_DELETE) &&
8029 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8030 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8031 kvm_mmu_zap_collapsible_sptes(kvm, new);
8032
8033 /*
8034 * Set up write protection and/or dirty logging for the new slot.
8035 *
8036 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8037 * been zapped so no dirty logging staff is needed for old slot. For
8038 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8039 * new and it's also covered when dealing with the new slot.
8040 *
8041 * FIXME: const-ify all uses of struct kvm_memory_slot.
8042 */
8043 if (change != KVM_MR_DELETE)
8044 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8045 }
8046
8047 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8048 {
8049 kvm_mmu_invalidate_zap_all_pages(kvm);
8050 }
8051
8052 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8053 struct kvm_memory_slot *slot)
8054 {
8055 kvm_mmu_invalidate_zap_all_pages(kvm);
8056 }
8057
8058 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8059 {
8060 if (!list_empty_careful(&vcpu->async_pf.done))
8061 return true;
8062
8063 if (kvm_apic_has_events(vcpu))
8064 return true;
8065
8066 if (vcpu->arch.pv.pv_unhalted)
8067 return true;
8068
8069 if (atomic_read(&vcpu->arch.nmi_queued))
8070 return true;
8071
8072 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8073 return true;
8074
8075 if (kvm_arch_interrupt_allowed(vcpu) &&
8076 kvm_cpu_has_interrupt(vcpu))
8077 return true;
8078
8079 if (kvm_hv_has_stimer_pending(vcpu))
8080 return true;
8081
8082 return false;
8083 }
8084
8085 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8086 {
8087 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8088 kvm_x86_ops->check_nested_events(vcpu, false);
8089
8090 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8091 }
8092
8093 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8094 {
8095 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8096 }
8097
8098 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8099 {
8100 return kvm_x86_ops->interrupt_allowed(vcpu);
8101 }
8102
8103 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8104 {
8105 if (is_64_bit_mode(vcpu))
8106 return kvm_rip_read(vcpu);
8107 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8108 kvm_rip_read(vcpu));
8109 }
8110 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8111
8112 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8113 {
8114 return kvm_get_linear_rip(vcpu) == linear_rip;
8115 }
8116 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8117
8118 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8119 {
8120 unsigned long rflags;
8121
8122 rflags = kvm_x86_ops->get_rflags(vcpu);
8123 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8124 rflags &= ~X86_EFLAGS_TF;
8125 return rflags;
8126 }
8127 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8128
8129 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8130 {
8131 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8132 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8133 rflags |= X86_EFLAGS_TF;
8134 kvm_x86_ops->set_rflags(vcpu, rflags);
8135 }
8136
8137 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8138 {
8139 __kvm_set_rflags(vcpu, rflags);
8140 kvm_make_request(KVM_REQ_EVENT, vcpu);
8141 }
8142 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8143
8144 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8145 {
8146 int r;
8147
8148 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8149 work->wakeup_all)
8150 return;
8151
8152 r = kvm_mmu_reload(vcpu);
8153 if (unlikely(r))
8154 return;
8155
8156 if (!vcpu->arch.mmu.direct_map &&
8157 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8158 return;
8159
8160 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8161 }
8162
8163 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8164 {
8165 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8166 }
8167
8168 static inline u32 kvm_async_pf_next_probe(u32 key)
8169 {
8170 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8171 }
8172
8173 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8174 {
8175 u32 key = kvm_async_pf_hash_fn(gfn);
8176
8177 while (vcpu->arch.apf.gfns[key] != ~0)
8178 key = kvm_async_pf_next_probe(key);
8179
8180 vcpu->arch.apf.gfns[key] = gfn;
8181 }
8182
8183 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8184 {
8185 int i;
8186 u32 key = kvm_async_pf_hash_fn(gfn);
8187
8188 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8189 (vcpu->arch.apf.gfns[key] != gfn &&
8190 vcpu->arch.apf.gfns[key] != ~0); i++)
8191 key = kvm_async_pf_next_probe(key);
8192
8193 return key;
8194 }
8195
8196 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8197 {
8198 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8199 }
8200
8201 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8202 {
8203 u32 i, j, k;
8204
8205 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8206 while (true) {
8207 vcpu->arch.apf.gfns[i] = ~0;
8208 do {
8209 j = kvm_async_pf_next_probe(j);
8210 if (vcpu->arch.apf.gfns[j] == ~0)
8211 return;
8212 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8213 /*
8214 * k lies cyclically in ]i,j]
8215 * | i.k.j |
8216 * |....j i.k.| or |.k..j i...|
8217 */
8218 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8219 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8220 i = j;
8221 }
8222 }
8223
8224 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8225 {
8226
8227 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8228 sizeof(val));
8229 }
8230
8231 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8232 struct kvm_async_pf *work)
8233 {
8234 struct x86_exception fault;
8235
8236 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8237 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8238
8239 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8240 (vcpu->arch.apf.send_user_only &&
8241 kvm_x86_ops->get_cpl(vcpu) == 0))
8242 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8243 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8244 fault.vector = PF_VECTOR;
8245 fault.error_code_valid = true;
8246 fault.error_code = 0;
8247 fault.nested_page_fault = false;
8248 fault.address = work->arch.token;
8249 kvm_inject_page_fault(vcpu, &fault);
8250 }
8251 }
8252
8253 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8254 struct kvm_async_pf *work)
8255 {
8256 struct x86_exception fault;
8257
8258 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8259 if (work->wakeup_all)
8260 work->arch.token = ~0; /* broadcast wakeup */
8261 else
8262 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8263
8264 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8265 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8266 fault.vector = PF_VECTOR;
8267 fault.error_code_valid = true;
8268 fault.error_code = 0;
8269 fault.nested_page_fault = false;
8270 fault.address = work->arch.token;
8271 kvm_inject_page_fault(vcpu, &fault);
8272 }
8273 vcpu->arch.apf.halted = false;
8274 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8275 }
8276
8277 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8278 {
8279 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8280 return true;
8281 else
8282 return !kvm_event_needs_reinjection(vcpu) &&
8283 kvm_x86_ops->interrupt_allowed(vcpu);
8284 }
8285
8286 void kvm_arch_start_assignment(struct kvm *kvm)
8287 {
8288 atomic_inc(&kvm->arch.assigned_device_count);
8289 }
8290 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8291
8292 void kvm_arch_end_assignment(struct kvm *kvm)
8293 {
8294 atomic_dec(&kvm->arch.assigned_device_count);
8295 }
8296 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8297
8298 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8299 {
8300 return atomic_read(&kvm->arch.assigned_device_count);
8301 }
8302 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8303
8304 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8305 {
8306 atomic_inc(&kvm->arch.noncoherent_dma_count);
8307 }
8308 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8309
8310 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8311 {
8312 atomic_dec(&kvm->arch.noncoherent_dma_count);
8313 }
8314 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8315
8316 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8317 {
8318 return atomic_read(&kvm->arch.noncoherent_dma_count);
8319 }
8320 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8321
8322 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8323 struct irq_bypass_producer *prod)
8324 {
8325 struct kvm_kernel_irqfd *irqfd =
8326 container_of(cons, struct kvm_kernel_irqfd, consumer);
8327
8328 if (kvm_x86_ops->update_pi_irte) {
8329 irqfd->producer = prod;
8330 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8331 prod->irq, irqfd->gsi, 1);
8332 }
8333
8334 return -EINVAL;
8335 }
8336
8337 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8338 struct irq_bypass_producer *prod)
8339 {
8340 int ret;
8341 struct kvm_kernel_irqfd *irqfd =
8342 container_of(cons, struct kvm_kernel_irqfd, consumer);
8343
8344 if (!kvm_x86_ops->update_pi_irte) {
8345 WARN_ON(irqfd->producer != NULL);
8346 return;
8347 }
8348
8349 WARN_ON(irqfd->producer != prod);
8350 irqfd->producer = NULL;
8351
8352 /*
8353 * When producer of consumer is unregistered, we change back to
8354 * remapped mode, so we can re-use the current implementation
8355 * when the irq is masked/disabed or the consumer side (KVM
8356 * int this case doesn't want to receive the interrupts.
8357 */
8358 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8359 if (ret)
8360 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8361 " fails: %d\n", irqfd->consumer.token, ret);
8362 }
8363
8364 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8365 uint32_t guest_irq, bool set)
8366 {
8367 if (!kvm_x86_ops->update_pi_irte)
8368 return -EINVAL;
8369
8370 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8371 }
8372
8373 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8374 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8375 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8376 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8377 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8378 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8379 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8380 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8381 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8382 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8383 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8384 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8385 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8386 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8387 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8388 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8389 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
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