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[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <trace/events/kvm.h>
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68
69 #define CREATE_TRACE_POINTS
70 #include "trace.h"
71
72 #define MAX_IO_MSRS 256
73 #define KVM_MAX_MCE_BANKS 32
74 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
76
77 #define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
80 /* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84 #ifdef CONFIG_X86_64
85 static
86 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
87 #else
88 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
89 #endif
90
91 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
93
94 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
96
97 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
98 static void process_nmi(struct kvm_vcpu *vcpu);
99 static void enter_smm(struct kvm_vcpu *vcpu);
100 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
101
102 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
103 EXPORT_SYMBOL_GPL(kvm_x86_ops);
104
105 static bool __read_mostly ignore_msrs = 0;
106 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
107
108 unsigned int min_timer_period_us = 500;
109 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
111 static bool __read_mostly kvmclock_periodic_sync = true;
112 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
114 bool __read_mostly kvm_has_tsc_control;
115 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
116 u32 __read_mostly kvm_max_guest_tsc_khz;
117 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
118 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120 u64 __read_mostly kvm_max_tsc_scaling_ratio;
121 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
122 u64 __read_mostly kvm_default_tsc_scaling_ratio;
123 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
124
125 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
126 static u32 __read_mostly tsc_tolerance_ppm = 250;
127 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
129 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
130 unsigned int __read_mostly lapic_timer_advance_ns = 0;
131 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
133 static bool __read_mostly vector_hashing = true;
134 module_param(vector_hashing, bool, S_IRUGO);
135
136 static bool __read_mostly backwards_tsc_observed = false;
137
138 #define KVM_NR_SHARED_MSRS 16
139
140 struct kvm_shared_msrs_global {
141 int nr;
142 u32 msrs[KVM_NR_SHARED_MSRS];
143 };
144
145 struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
152 };
153
154 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
155 static struct kvm_shared_msrs __percpu *shared_msrs;
156
157 struct kvm_stats_debugfs_item debugfs_entries[] = {
158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
168 { "halt_exits", VCPU_STAT(halt_exits) },
169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
173 { "hypercalls", VCPU_STAT(hypercalls) },
174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
181 { "irq_injections", VCPU_STAT(irq_injections) },
182 { "nmi_injections", VCPU_STAT(nmi_injections) },
183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
190 { "mmu_unsync", VM_STAT(mmu_unsync) },
191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
192 { "largepages", VM_STAT(lpages) },
193 { "max_mmu_page_hash_collisions",
194 VM_STAT(max_mmu_page_hash_collisions) },
195 { NULL }
196 };
197
198 u64 __read_mostly host_xcr0;
199
200 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
201
202 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
203 {
204 int i;
205 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
206 vcpu->arch.apf.gfns[i] = ~0;
207 }
208
209 static void kvm_on_user_return(struct user_return_notifier *urn)
210 {
211 unsigned slot;
212 struct kvm_shared_msrs *locals
213 = container_of(urn, struct kvm_shared_msrs, urn);
214 struct kvm_shared_msr_values *values;
215 unsigned long flags;
216
217 /*
218 * Disabling irqs at this point since the following code could be
219 * interrupted and executed through kvm_arch_hardware_disable()
220 */
221 local_irq_save(flags);
222 if (locals->registered) {
223 locals->registered = false;
224 user_return_notifier_unregister(urn);
225 }
226 local_irq_restore(flags);
227 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
228 values = &locals->values[slot];
229 if (values->host != values->curr) {
230 wrmsrl(shared_msrs_global.msrs[slot], values->host);
231 values->curr = values->host;
232 }
233 }
234 }
235
236 static void shared_msr_update(unsigned slot, u32 msr)
237 {
238 u64 value;
239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
241
242 /* only read, and nobody should modify it at this time,
243 * so don't need lock */
244 if (slot >= shared_msrs_global.nr) {
245 printk(KERN_ERR "kvm: invalid MSR slot!");
246 return;
247 }
248 rdmsrl_safe(msr, &value);
249 smsr->values[slot].host = value;
250 smsr->values[slot].curr = value;
251 }
252
253 void kvm_define_shared_msr(unsigned slot, u32 msr)
254 {
255 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
256 shared_msrs_global.msrs[slot] = msr;
257 if (slot >= shared_msrs_global.nr)
258 shared_msrs_global.nr = slot + 1;
259 }
260 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
261
262 static void kvm_shared_msr_cpu_online(void)
263 {
264 unsigned i;
265
266 for (i = 0; i < shared_msrs_global.nr; ++i)
267 shared_msr_update(i, shared_msrs_global.msrs[i]);
268 }
269
270 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
271 {
272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
274 int err;
275
276 if (((value ^ smsr->values[slot].curr) & mask) == 0)
277 return 0;
278 smsr->values[slot].curr = value;
279 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
280 if (err)
281 return 1;
282
283 if (!smsr->registered) {
284 smsr->urn.on_user_return = kvm_on_user_return;
285 user_return_notifier_register(&smsr->urn);
286 smsr->registered = true;
287 }
288 return 0;
289 }
290 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
291
292 static void drop_user_return_notifiers(void)
293 {
294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
296
297 if (smsr->registered)
298 kvm_on_user_return(&smsr->urn);
299 }
300
301 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
302 {
303 return vcpu->arch.apic_base;
304 }
305 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
306
307 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
308 {
309 u64 old_state = vcpu->arch.apic_base &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 new_state = msr_info->data &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
314 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
315
316 if (!msr_info->host_initiated &&
317 ((msr_info->data & reserved_bits) != 0 ||
318 new_state == X2APIC_ENABLE ||
319 (new_state == MSR_IA32_APICBASE_ENABLE &&
320 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
321 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
322 old_state == 0)))
323 return 1;
324
325 kvm_lapic_set_base(vcpu, msr_info->data);
326 return 0;
327 }
328 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
329
330 asmlinkage __visible void kvm_spurious_fault(void)
331 {
332 /* Fault while not rebooting. We want the trace. */
333 BUG();
334 }
335 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
336
337 #define EXCPT_BENIGN 0
338 #define EXCPT_CONTRIBUTORY 1
339 #define EXCPT_PF 2
340
341 static int exception_class(int vector)
342 {
343 switch (vector) {
344 case PF_VECTOR:
345 return EXCPT_PF;
346 case DE_VECTOR:
347 case TS_VECTOR:
348 case NP_VECTOR:
349 case SS_VECTOR:
350 case GP_VECTOR:
351 return EXCPT_CONTRIBUTORY;
352 default:
353 break;
354 }
355 return EXCPT_BENIGN;
356 }
357
358 #define EXCPT_FAULT 0
359 #define EXCPT_TRAP 1
360 #define EXCPT_ABORT 2
361 #define EXCPT_INTERRUPT 3
362
363 static int exception_type(int vector)
364 {
365 unsigned int mask;
366
367 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
368 return EXCPT_INTERRUPT;
369
370 mask = 1 << vector;
371
372 /* #DB is trap, as instruction watchpoints are handled elsewhere */
373 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
374 return EXCPT_TRAP;
375
376 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
377 return EXCPT_ABORT;
378
379 /* Reserved exceptions will result in fault */
380 return EXCPT_FAULT;
381 }
382
383 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
384 unsigned nr, bool has_error, u32 error_code,
385 bool reinject)
386 {
387 u32 prev_nr;
388 int class1, class2;
389
390 kvm_make_request(KVM_REQ_EVENT, vcpu);
391
392 if (!vcpu->arch.exception.pending) {
393 queue:
394 if (has_error && !is_protmode(vcpu))
395 has_error = false;
396 vcpu->arch.exception.pending = true;
397 vcpu->arch.exception.has_error_code = has_error;
398 vcpu->arch.exception.nr = nr;
399 vcpu->arch.exception.error_code = error_code;
400 vcpu->arch.exception.reinject = reinject;
401 return;
402 }
403
404 /* to check exception */
405 prev_nr = vcpu->arch.exception.nr;
406 if (prev_nr == DF_VECTOR) {
407 /* triple fault -> shutdown */
408 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
409 return;
410 }
411 class1 = exception_class(prev_nr);
412 class2 = exception_class(nr);
413 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
414 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
415 /* generate double fault per SDM Table 5-5 */
416 vcpu->arch.exception.pending = true;
417 vcpu->arch.exception.has_error_code = true;
418 vcpu->arch.exception.nr = DF_VECTOR;
419 vcpu->arch.exception.error_code = 0;
420 } else
421 /* replace previous exception with a new one in a hope
422 that instruction re-execution will regenerate lost
423 exception */
424 goto queue;
425 }
426
427 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
428 {
429 kvm_multiple_exception(vcpu, nr, false, 0, false);
430 }
431 EXPORT_SYMBOL_GPL(kvm_queue_exception);
432
433 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
434 {
435 kvm_multiple_exception(vcpu, nr, false, 0, true);
436 }
437 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
438
439 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
440 {
441 if (err)
442 kvm_inject_gp(vcpu, 0);
443 else
444 return kvm_skip_emulated_instruction(vcpu);
445
446 return 1;
447 }
448 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
449
450 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
451 {
452 ++vcpu->stat.pf_guest;
453 vcpu->arch.cr2 = fault->address;
454 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
455 }
456 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
457
458 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
459 {
460 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
461 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
462 else
463 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
464
465 return fault->nested_page_fault;
466 }
467
468 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
469 {
470 atomic_inc(&vcpu->arch.nmi_queued);
471 kvm_make_request(KVM_REQ_NMI, vcpu);
472 }
473 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
474
475 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
476 {
477 kvm_multiple_exception(vcpu, nr, true, error_code, false);
478 }
479 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
480
481 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
482 {
483 kvm_multiple_exception(vcpu, nr, true, error_code, true);
484 }
485 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
486
487 /*
488 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
489 * a #GP and return false.
490 */
491 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
492 {
493 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
494 return true;
495 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
496 return false;
497 }
498 EXPORT_SYMBOL_GPL(kvm_require_cpl);
499
500 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
501 {
502 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
503 return true;
504
505 kvm_queue_exception(vcpu, UD_VECTOR);
506 return false;
507 }
508 EXPORT_SYMBOL_GPL(kvm_require_dr);
509
510 /*
511 * This function will be used to read from the physical memory of the currently
512 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
513 * can read from guest physical or from the guest's guest physical memory.
514 */
515 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
516 gfn_t ngfn, void *data, int offset, int len,
517 u32 access)
518 {
519 struct x86_exception exception;
520 gfn_t real_gfn;
521 gpa_t ngpa;
522
523 ngpa = gfn_to_gpa(ngfn);
524 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
525 if (real_gfn == UNMAPPED_GVA)
526 return -EFAULT;
527
528 real_gfn = gpa_to_gfn(real_gfn);
529
530 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
531 }
532 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
533
534 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
535 void *data, int offset, int len, u32 access)
536 {
537 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
538 data, offset, len, access);
539 }
540
541 /*
542 * Load the pae pdptrs. Return true is they are all valid.
543 */
544 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
545 {
546 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
547 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
548 int i;
549 int ret;
550 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
551
552 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
553 offset * sizeof(u64), sizeof(pdpte),
554 PFERR_USER_MASK|PFERR_WRITE_MASK);
555 if (ret < 0) {
556 ret = 0;
557 goto out;
558 }
559 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
560 if ((pdpte[i] & PT_PRESENT_MASK) &&
561 (pdpte[i] &
562 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
563 ret = 0;
564 goto out;
565 }
566 }
567 ret = 1;
568
569 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
570 __set_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail);
572 __set_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_dirty);
574 out:
575
576 return ret;
577 }
578 EXPORT_SYMBOL_GPL(load_pdptrs);
579
580 bool pdptrs_changed(struct kvm_vcpu *vcpu)
581 {
582 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
583 bool changed = true;
584 int offset;
585 gfn_t gfn;
586 int r;
587
588 if (is_long_mode(vcpu) || !is_pae(vcpu))
589 return false;
590
591 if (!test_bit(VCPU_EXREG_PDPTR,
592 (unsigned long *)&vcpu->arch.regs_avail))
593 return true;
594
595 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
596 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
597 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
598 PFERR_USER_MASK | PFERR_WRITE_MASK);
599 if (r < 0)
600 goto out;
601 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
602 out:
603
604 return changed;
605 }
606 EXPORT_SYMBOL_GPL(pdptrs_changed);
607
608 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
609 {
610 unsigned long old_cr0 = kvm_read_cr0(vcpu);
611 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
612
613 cr0 |= X86_CR0_ET;
614
615 #ifdef CONFIG_X86_64
616 if (cr0 & 0xffffffff00000000UL)
617 return 1;
618 #endif
619
620 cr0 &= ~CR0_RESERVED_BITS;
621
622 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
623 return 1;
624
625 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
626 return 1;
627
628 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
629 #ifdef CONFIG_X86_64
630 if ((vcpu->arch.efer & EFER_LME)) {
631 int cs_db, cs_l;
632
633 if (!is_pae(vcpu))
634 return 1;
635 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
636 if (cs_l)
637 return 1;
638 } else
639 #endif
640 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
641 kvm_read_cr3(vcpu)))
642 return 1;
643 }
644
645 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
646 return 1;
647
648 kvm_x86_ops->set_cr0(vcpu, cr0);
649
650 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
651 kvm_clear_async_pf_completion_queue(vcpu);
652 kvm_async_pf_hash_reset(vcpu);
653 }
654
655 if ((cr0 ^ old_cr0) & update_bits)
656 kvm_mmu_reset_context(vcpu);
657
658 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
659 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
660 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
661 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
662
663 return 0;
664 }
665 EXPORT_SYMBOL_GPL(kvm_set_cr0);
666
667 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
668 {
669 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
670 }
671 EXPORT_SYMBOL_GPL(kvm_lmsw);
672
673 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
674 {
675 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
676 !vcpu->guest_xcr0_loaded) {
677 /* kvm_set_xcr() also depends on this */
678 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
679 vcpu->guest_xcr0_loaded = 1;
680 }
681 }
682
683 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
684 {
685 if (vcpu->guest_xcr0_loaded) {
686 if (vcpu->arch.xcr0 != host_xcr0)
687 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
688 vcpu->guest_xcr0_loaded = 0;
689 }
690 }
691
692 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
693 {
694 u64 xcr0 = xcr;
695 u64 old_xcr0 = vcpu->arch.xcr0;
696 u64 valid_bits;
697
698 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
699 if (index != XCR_XFEATURE_ENABLED_MASK)
700 return 1;
701 if (!(xcr0 & XFEATURE_MASK_FP))
702 return 1;
703 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
704 return 1;
705
706 /*
707 * Do not allow the guest to set bits that we do not support
708 * saving. However, xcr0 bit 0 is always set, even if the
709 * emulated CPU does not support XSAVE (see fx_init).
710 */
711 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
712 if (xcr0 & ~valid_bits)
713 return 1;
714
715 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
716 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
717 return 1;
718
719 if (xcr0 & XFEATURE_MASK_AVX512) {
720 if (!(xcr0 & XFEATURE_MASK_YMM))
721 return 1;
722 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
723 return 1;
724 }
725 vcpu->arch.xcr0 = xcr0;
726
727 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
728 kvm_update_cpuid(vcpu);
729 return 0;
730 }
731
732 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
733 {
734 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
735 __kvm_set_xcr(vcpu, index, xcr)) {
736 kvm_inject_gp(vcpu, 0);
737 return 1;
738 }
739 return 0;
740 }
741 EXPORT_SYMBOL_GPL(kvm_set_xcr);
742
743 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
744 {
745 unsigned long old_cr4 = kvm_read_cr4(vcpu);
746 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
747 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
748
749 if (cr4 & CR4_RESERVED_BITS)
750 return 1;
751
752 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
753 return 1;
754
755 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
756 return 1;
757
758 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
759 return 1;
760
761 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
762 return 1;
763
764 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
765 return 1;
766
767 if (is_long_mode(vcpu)) {
768 if (!(cr4 & X86_CR4_PAE))
769 return 1;
770 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
771 && ((cr4 ^ old_cr4) & pdptr_bits)
772 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
773 kvm_read_cr3(vcpu)))
774 return 1;
775
776 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
777 if (!guest_cpuid_has_pcid(vcpu))
778 return 1;
779
780 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
781 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
782 return 1;
783 }
784
785 if (kvm_x86_ops->set_cr4(vcpu, cr4))
786 return 1;
787
788 if (((cr4 ^ old_cr4) & pdptr_bits) ||
789 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
790 kvm_mmu_reset_context(vcpu);
791
792 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
793 kvm_update_cpuid(vcpu);
794
795 return 0;
796 }
797 EXPORT_SYMBOL_GPL(kvm_set_cr4);
798
799 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
800 {
801 #ifdef CONFIG_X86_64
802 cr3 &= ~CR3_PCID_INVD;
803 #endif
804
805 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
806 kvm_mmu_sync_roots(vcpu);
807 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
808 return 0;
809 }
810
811 if (is_long_mode(vcpu)) {
812 if (cr3 & CR3_L_MODE_RESERVED_BITS)
813 return 1;
814 } else if (is_pae(vcpu) && is_paging(vcpu) &&
815 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
816 return 1;
817
818 vcpu->arch.cr3 = cr3;
819 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
820 kvm_mmu_new_cr3(vcpu);
821 return 0;
822 }
823 EXPORT_SYMBOL_GPL(kvm_set_cr3);
824
825 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
826 {
827 if (cr8 & CR8_RESERVED_BITS)
828 return 1;
829 if (lapic_in_kernel(vcpu))
830 kvm_lapic_set_tpr(vcpu, cr8);
831 else
832 vcpu->arch.cr8 = cr8;
833 return 0;
834 }
835 EXPORT_SYMBOL_GPL(kvm_set_cr8);
836
837 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
838 {
839 if (lapic_in_kernel(vcpu))
840 return kvm_lapic_get_cr8(vcpu);
841 else
842 return vcpu->arch.cr8;
843 }
844 EXPORT_SYMBOL_GPL(kvm_get_cr8);
845
846 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
847 {
848 int i;
849
850 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
851 for (i = 0; i < KVM_NR_DB_REGS; i++)
852 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
854 }
855 }
856
857 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
858 {
859 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
860 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
861 }
862
863 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
864 {
865 unsigned long dr7;
866
867 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
868 dr7 = vcpu->arch.guest_debug_dr7;
869 else
870 dr7 = vcpu->arch.dr7;
871 kvm_x86_ops->set_dr7(vcpu, dr7);
872 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
873 if (dr7 & DR7_BP_EN_MASK)
874 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
875 }
876
877 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
878 {
879 u64 fixed = DR6_FIXED_1;
880
881 if (!guest_cpuid_has_rtm(vcpu))
882 fixed |= DR6_RTM;
883 return fixed;
884 }
885
886 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
887 {
888 switch (dr) {
889 case 0 ... 3:
890 vcpu->arch.db[dr] = val;
891 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
892 vcpu->arch.eff_db[dr] = val;
893 break;
894 case 4:
895 /* fall through */
896 case 6:
897 if (val & 0xffffffff00000000ULL)
898 return -1; /* #GP */
899 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
900 kvm_update_dr6(vcpu);
901 break;
902 case 5:
903 /* fall through */
904 default: /* 7 */
905 if (val & 0xffffffff00000000ULL)
906 return -1; /* #GP */
907 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
908 kvm_update_dr7(vcpu);
909 break;
910 }
911
912 return 0;
913 }
914
915 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
916 {
917 if (__kvm_set_dr(vcpu, dr, val)) {
918 kvm_inject_gp(vcpu, 0);
919 return 1;
920 }
921 return 0;
922 }
923 EXPORT_SYMBOL_GPL(kvm_set_dr);
924
925 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
926 {
927 switch (dr) {
928 case 0 ... 3:
929 *val = vcpu->arch.db[dr];
930 break;
931 case 4:
932 /* fall through */
933 case 6:
934 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
935 *val = vcpu->arch.dr6;
936 else
937 *val = kvm_x86_ops->get_dr6(vcpu);
938 break;
939 case 5:
940 /* fall through */
941 default: /* 7 */
942 *val = vcpu->arch.dr7;
943 break;
944 }
945 return 0;
946 }
947 EXPORT_SYMBOL_GPL(kvm_get_dr);
948
949 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
950 {
951 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
952 u64 data;
953 int err;
954
955 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
956 if (err)
957 return err;
958 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
959 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
960 return err;
961 }
962 EXPORT_SYMBOL_GPL(kvm_rdpmc);
963
964 /*
965 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
966 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
967 *
968 * This list is modified at module load time to reflect the
969 * capabilities of the host cpu. This capabilities test skips MSRs that are
970 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
971 * may depend on host virtualization features rather than host cpu features.
972 */
973
974 static u32 msrs_to_save[] = {
975 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
976 MSR_STAR,
977 #ifdef CONFIG_X86_64
978 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
979 #endif
980 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
981 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
982 };
983
984 static unsigned num_msrs_to_save;
985
986 static u32 emulated_msrs[] = {
987 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
988 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
989 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
990 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
991 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
992 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
993 HV_X64_MSR_RESET,
994 HV_X64_MSR_VP_INDEX,
995 HV_X64_MSR_VP_RUNTIME,
996 HV_X64_MSR_SCONTROL,
997 HV_X64_MSR_STIMER0_CONFIG,
998 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
999 MSR_KVM_PV_EOI_EN,
1000
1001 MSR_IA32_TSC_ADJUST,
1002 MSR_IA32_TSCDEADLINE,
1003 MSR_IA32_MISC_ENABLE,
1004 MSR_IA32_MCG_STATUS,
1005 MSR_IA32_MCG_CTL,
1006 MSR_IA32_MCG_EXT_CTL,
1007 MSR_IA32_SMBASE,
1008 };
1009
1010 static unsigned num_emulated_msrs;
1011
1012 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1013 {
1014 if (efer & efer_reserved_bits)
1015 return false;
1016
1017 if (efer & EFER_FFXSR) {
1018 struct kvm_cpuid_entry2 *feat;
1019
1020 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1021 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1022 return false;
1023 }
1024
1025 if (efer & EFER_SVME) {
1026 struct kvm_cpuid_entry2 *feat;
1027
1028 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1029 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1030 return false;
1031 }
1032
1033 return true;
1034 }
1035 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1036
1037 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1038 {
1039 u64 old_efer = vcpu->arch.efer;
1040
1041 if (!kvm_valid_efer(vcpu, efer))
1042 return 1;
1043
1044 if (is_paging(vcpu)
1045 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1046 return 1;
1047
1048 efer &= ~EFER_LMA;
1049 efer |= vcpu->arch.efer & EFER_LMA;
1050
1051 kvm_x86_ops->set_efer(vcpu, efer);
1052
1053 /* Update reserved bits */
1054 if ((efer ^ old_efer) & EFER_NX)
1055 kvm_mmu_reset_context(vcpu);
1056
1057 return 0;
1058 }
1059
1060 void kvm_enable_efer_bits(u64 mask)
1061 {
1062 efer_reserved_bits &= ~mask;
1063 }
1064 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1065
1066 /*
1067 * Writes msr value into into the appropriate "register".
1068 * Returns 0 on success, non-0 otherwise.
1069 * Assumes vcpu_load() was already called.
1070 */
1071 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1072 {
1073 switch (msr->index) {
1074 case MSR_FS_BASE:
1075 case MSR_GS_BASE:
1076 case MSR_KERNEL_GS_BASE:
1077 case MSR_CSTAR:
1078 case MSR_LSTAR:
1079 if (is_noncanonical_address(msr->data))
1080 return 1;
1081 break;
1082 case MSR_IA32_SYSENTER_EIP:
1083 case MSR_IA32_SYSENTER_ESP:
1084 /*
1085 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1086 * non-canonical address is written on Intel but not on
1087 * AMD (which ignores the top 32-bits, because it does
1088 * not implement 64-bit SYSENTER).
1089 *
1090 * 64-bit code should hence be able to write a non-canonical
1091 * value on AMD. Making the address canonical ensures that
1092 * vmentry does not fail on Intel after writing a non-canonical
1093 * value, and that something deterministic happens if the guest
1094 * invokes 64-bit SYSENTER.
1095 */
1096 msr->data = get_canonical(msr->data);
1097 }
1098 return kvm_x86_ops->set_msr(vcpu, msr);
1099 }
1100 EXPORT_SYMBOL_GPL(kvm_set_msr);
1101
1102 /*
1103 * Adapt set_msr() to msr_io()'s calling convention
1104 */
1105 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1106 {
1107 struct msr_data msr;
1108 int r;
1109
1110 msr.index = index;
1111 msr.host_initiated = true;
1112 r = kvm_get_msr(vcpu, &msr);
1113 if (r)
1114 return r;
1115
1116 *data = msr.data;
1117 return 0;
1118 }
1119
1120 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1121 {
1122 struct msr_data msr;
1123
1124 msr.data = *data;
1125 msr.index = index;
1126 msr.host_initiated = true;
1127 return kvm_set_msr(vcpu, &msr);
1128 }
1129
1130 #ifdef CONFIG_X86_64
1131 struct pvclock_gtod_data {
1132 seqcount_t seq;
1133
1134 struct { /* extract of a clocksource struct */
1135 int vclock_mode;
1136 u64 cycle_last;
1137 u64 mask;
1138 u32 mult;
1139 u32 shift;
1140 } clock;
1141
1142 u64 boot_ns;
1143 u64 nsec_base;
1144 };
1145
1146 static struct pvclock_gtod_data pvclock_gtod_data;
1147
1148 static void update_pvclock_gtod(struct timekeeper *tk)
1149 {
1150 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1151 u64 boot_ns;
1152
1153 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1154
1155 write_seqcount_begin(&vdata->seq);
1156
1157 /* copy pvclock gtod data */
1158 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1159 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1160 vdata->clock.mask = tk->tkr_mono.mask;
1161 vdata->clock.mult = tk->tkr_mono.mult;
1162 vdata->clock.shift = tk->tkr_mono.shift;
1163
1164 vdata->boot_ns = boot_ns;
1165 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1166
1167 write_seqcount_end(&vdata->seq);
1168 }
1169 #endif
1170
1171 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1172 {
1173 /*
1174 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1175 * vcpu_enter_guest. This function is only called from
1176 * the physical CPU that is running vcpu.
1177 */
1178 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1179 }
1180
1181 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1182 {
1183 int version;
1184 int r;
1185 struct pvclock_wall_clock wc;
1186 struct timespec64 boot;
1187
1188 if (!wall_clock)
1189 return;
1190
1191 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1192 if (r)
1193 return;
1194
1195 if (version & 1)
1196 ++version; /* first time write, random junk */
1197
1198 ++version;
1199
1200 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1201 return;
1202
1203 /*
1204 * The guest calculates current wall clock time by adding
1205 * system time (updated by kvm_guest_time_update below) to the
1206 * wall clock specified here. guest system time equals host
1207 * system time for us, thus we must fill in host boot time here.
1208 */
1209 getboottime64(&boot);
1210
1211 if (kvm->arch.kvmclock_offset) {
1212 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1213 boot = timespec64_sub(boot, ts);
1214 }
1215 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1216 wc.nsec = boot.tv_nsec;
1217 wc.version = version;
1218
1219 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1220
1221 version++;
1222 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1223 }
1224
1225 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1226 {
1227 do_shl32_div32(dividend, divisor);
1228 return dividend;
1229 }
1230
1231 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1232 s8 *pshift, u32 *pmultiplier)
1233 {
1234 uint64_t scaled64;
1235 int32_t shift = 0;
1236 uint64_t tps64;
1237 uint32_t tps32;
1238
1239 tps64 = base_hz;
1240 scaled64 = scaled_hz;
1241 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1242 tps64 >>= 1;
1243 shift--;
1244 }
1245
1246 tps32 = (uint32_t)tps64;
1247 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1248 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1249 scaled64 >>= 1;
1250 else
1251 tps32 <<= 1;
1252 shift++;
1253 }
1254
1255 *pshift = shift;
1256 *pmultiplier = div_frac(scaled64, tps32);
1257
1258 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1259 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1260 }
1261
1262 #ifdef CONFIG_X86_64
1263 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1264 #endif
1265
1266 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1267 static unsigned long max_tsc_khz;
1268
1269 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1270 {
1271 u64 v = (u64)khz * (1000000 + ppm);
1272 do_div(v, 1000000);
1273 return v;
1274 }
1275
1276 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1277 {
1278 u64 ratio;
1279
1280 /* Guest TSC same frequency as host TSC? */
1281 if (!scale) {
1282 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1283 return 0;
1284 }
1285
1286 /* TSC scaling supported? */
1287 if (!kvm_has_tsc_control) {
1288 if (user_tsc_khz > tsc_khz) {
1289 vcpu->arch.tsc_catchup = 1;
1290 vcpu->arch.tsc_always_catchup = 1;
1291 return 0;
1292 } else {
1293 WARN(1, "user requested TSC rate below hardware speed\n");
1294 return -1;
1295 }
1296 }
1297
1298 /* TSC scaling required - calculate ratio */
1299 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1300 user_tsc_khz, tsc_khz);
1301
1302 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1303 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1304 user_tsc_khz);
1305 return -1;
1306 }
1307
1308 vcpu->arch.tsc_scaling_ratio = ratio;
1309 return 0;
1310 }
1311
1312 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1313 {
1314 u32 thresh_lo, thresh_hi;
1315 int use_scaling = 0;
1316
1317 /* tsc_khz can be zero if TSC calibration fails */
1318 if (user_tsc_khz == 0) {
1319 /* set tsc_scaling_ratio to a safe value */
1320 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1321 return -1;
1322 }
1323
1324 /* Compute a scale to convert nanoseconds in TSC cycles */
1325 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1326 &vcpu->arch.virtual_tsc_shift,
1327 &vcpu->arch.virtual_tsc_mult);
1328 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1329
1330 /*
1331 * Compute the variation in TSC rate which is acceptable
1332 * within the range of tolerance and decide if the
1333 * rate being applied is within that bounds of the hardware
1334 * rate. If so, no scaling or compensation need be done.
1335 */
1336 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1337 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1338 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1339 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1340 use_scaling = 1;
1341 }
1342 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1343 }
1344
1345 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1346 {
1347 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1348 vcpu->arch.virtual_tsc_mult,
1349 vcpu->arch.virtual_tsc_shift);
1350 tsc += vcpu->arch.this_tsc_write;
1351 return tsc;
1352 }
1353
1354 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1355 {
1356 #ifdef CONFIG_X86_64
1357 bool vcpus_matched;
1358 struct kvm_arch *ka = &vcpu->kvm->arch;
1359 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1360
1361 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1362 atomic_read(&vcpu->kvm->online_vcpus));
1363
1364 /*
1365 * Once the masterclock is enabled, always perform request in
1366 * order to update it.
1367 *
1368 * In order to enable masterclock, the host clocksource must be TSC
1369 * and the vcpus need to have matched TSCs. When that happens,
1370 * perform request to enable masterclock.
1371 */
1372 if (ka->use_master_clock ||
1373 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1374 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1375
1376 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1377 atomic_read(&vcpu->kvm->online_vcpus),
1378 ka->use_master_clock, gtod->clock.vclock_mode);
1379 #endif
1380 }
1381
1382 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1383 {
1384 u64 curr_offset = vcpu->arch.tsc_offset;
1385 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1386 }
1387
1388 /*
1389 * Multiply tsc by a fixed point number represented by ratio.
1390 *
1391 * The most significant 64-N bits (mult) of ratio represent the
1392 * integral part of the fixed point number; the remaining N bits
1393 * (frac) represent the fractional part, ie. ratio represents a fixed
1394 * point number (mult + frac * 2^(-N)).
1395 *
1396 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1397 */
1398 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1399 {
1400 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1401 }
1402
1403 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1404 {
1405 u64 _tsc = tsc;
1406 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1407
1408 if (ratio != kvm_default_tsc_scaling_ratio)
1409 _tsc = __scale_tsc(ratio, tsc);
1410
1411 return _tsc;
1412 }
1413 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1414
1415 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1416 {
1417 u64 tsc;
1418
1419 tsc = kvm_scale_tsc(vcpu, rdtsc());
1420
1421 return target_tsc - tsc;
1422 }
1423
1424 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1425 {
1426 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1427 }
1428 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1429
1430 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1431 {
1432 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1433 vcpu->arch.tsc_offset = offset;
1434 }
1435
1436 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1437 {
1438 struct kvm *kvm = vcpu->kvm;
1439 u64 offset, ns, elapsed;
1440 unsigned long flags;
1441 s64 usdiff;
1442 bool matched;
1443 bool already_matched;
1444 u64 data = msr->data;
1445
1446 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1447 offset = kvm_compute_tsc_offset(vcpu, data);
1448 ns = ktime_get_boot_ns();
1449 elapsed = ns - kvm->arch.last_tsc_nsec;
1450
1451 if (vcpu->arch.virtual_tsc_khz) {
1452 int faulted = 0;
1453
1454 /* n.b - signed multiplication and division required */
1455 usdiff = data - kvm->arch.last_tsc_write;
1456 #ifdef CONFIG_X86_64
1457 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1458 #else
1459 /* do_div() only does unsigned */
1460 asm("1: idivl %[divisor]\n"
1461 "2: xor %%edx, %%edx\n"
1462 " movl $0, %[faulted]\n"
1463 "3:\n"
1464 ".section .fixup,\"ax\"\n"
1465 "4: movl $1, %[faulted]\n"
1466 " jmp 3b\n"
1467 ".previous\n"
1468
1469 _ASM_EXTABLE(1b, 4b)
1470
1471 : "=A"(usdiff), [faulted] "=r" (faulted)
1472 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1473
1474 #endif
1475 do_div(elapsed, 1000);
1476 usdiff -= elapsed;
1477 if (usdiff < 0)
1478 usdiff = -usdiff;
1479
1480 /* idivl overflow => difference is larger than USEC_PER_SEC */
1481 if (faulted)
1482 usdiff = USEC_PER_SEC;
1483 } else
1484 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1485
1486 /*
1487 * Special case: TSC write with a small delta (1 second) of virtual
1488 * cycle time against real time is interpreted as an attempt to
1489 * synchronize the CPU.
1490 *
1491 * For a reliable TSC, we can match TSC offsets, and for an unstable
1492 * TSC, we add elapsed time in this computation. We could let the
1493 * compensation code attempt to catch up if we fall behind, but
1494 * it's better to try to match offsets from the beginning.
1495 */
1496 if (usdiff < USEC_PER_SEC &&
1497 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1498 if (!check_tsc_unstable()) {
1499 offset = kvm->arch.cur_tsc_offset;
1500 pr_debug("kvm: matched tsc offset for %llu\n", data);
1501 } else {
1502 u64 delta = nsec_to_cycles(vcpu, elapsed);
1503 data += delta;
1504 offset = kvm_compute_tsc_offset(vcpu, data);
1505 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1506 }
1507 matched = true;
1508 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1509 } else {
1510 /*
1511 * We split periods of matched TSC writes into generations.
1512 * For each generation, we track the original measured
1513 * nanosecond time, offset, and write, so if TSCs are in
1514 * sync, we can match exact offset, and if not, we can match
1515 * exact software computation in compute_guest_tsc()
1516 *
1517 * These values are tracked in kvm->arch.cur_xxx variables.
1518 */
1519 kvm->arch.cur_tsc_generation++;
1520 kvm->arch.cur_tsc_nsec = ns;
1521 kvm->arch.cur_tsc_write = data;
1522 kvm->arch.cur_tsc_offset = offset;
1523 matched = false;
1524 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1525 kvm->arch.cur_tsc_generation, data);
1526 }
1527
1528 /*
1529 * We also track th most recent recorded KHZ, write and time to
1530 * allow the matching interval to be extended at each write.
1531 */
1532 kvm->arch.last_tsc_nsec = ns;
1533 kvm->arch.last_tsc_write = data;
1534 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1535
1536 vcpu->arch.last_guest_tsc = data;
1537
1538 /* Keep track of which generation this VCPU has synchronized to */
1539 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1540 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1541 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1542
1543 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1544 update_ia32_tsc_adjust_msr(vcpu, offset);
1545 kvm_vcpu_write_tsc_offset(vcpu, offset);
1546 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1547
1548 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1549 if (!matched) {
1550 kvm->arch.nr_vcpus_matched_tsc = 0;
1551 } else if (!already_matched) {
1552 kvm->arch.nr_vcpus_matched_tsc++;
1553 }
1554
1555 kvm_track_tsc_matching(vcpu);
1556 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1557 }
1558
1559 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1560
1561 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1562 s64 adjustment)
1563 {
1564 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1565 }
1566
1567 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1568 {
1569 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1570 WARN_ON(adjustment < 0);
1571 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1572 adjust_tsc_offset_guest(vcpu, adjustment);
1573 }
1574
1575 #ifdef CONFIG_X86_64
1576
1577 static u64 read_tsc(void)
1578 {
1579 u64 ret = (u64)rdtsc_ordered();
1580 u64 last = pvclock_gtod_data.clock.cycle_last;
1581
1582 if (likely(ret >= last))
1583 return ret;
1584
1585 /*
1586 * GCC likes to generate cmov here, but this branch is extremely
1587 * predictable (it's just a function of time and the likely is
1588 * very likely) and there's a data dependence, so force GCC
1589 * to generate a branch instead. I don't barrier() because
1590 * we don't actually need a barrier, and if this function
1591 * ever gets inlined it will generate worse code.
1592 */
1593 asm volatile ("");
1594 return last;
1595 }
1596
1597 static inline u64 vgettsc(u64 *cycle_now)
1598 {
1599 long v;
1600 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1601
1602 *cycle_now = read_tsc();
1603
1604 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1605 return v * gtod->clock.mult;
1606 }
1607
1608 static int do_monotonic_boot(s64 *t, u64 *cycle_now)
1609 {
1610 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1611 unsigned long seq;
1612 int mode;
1613 u64 ns;
1614
1615 do {
1616 seq = read_seqcount_begin(&gtod->seq);
1617 mode = gtod->clock.vclock_mode;
1618 ns = gtod->nsec_base;
1619 ns += vgettsc(cycle_now);
1620 ns >>= gtod->clock.shift;
1621 ns += gtod->boot_ns;
1622 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1623 *t = ns;
1624
1625 return mode;
1626 }
1627
1628 /* returns true if host is using tsc clocksource */
1629 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
1630 {
1631 /* checked again under seqlock below */
1632 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1633 return false;
1634
1635 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1636 }
1637 #endif
1638
1639 /*
1640 *
1641 * Assuming a stable TSC across physical CPUS, and a stable TSC
1642 * across virtual CPUs, the following condition is possible.
1643 * Each numbered line represents an event visible to both
1644 * CPUs at the next numbered event.
1645 *
1646 * "timespecX" represents host monotonic time. "tscX" represents
1647 * RDTSC value.
1648 *
1649 * VCPU0 on CPU0 | VCPU1 on CPU1
1650 *
1651 * 1. read timespec0,tsc0
1652 * 2. | timespec1 = timespec0 + N
1653 * | tsc1 = tsc0 + M
1654 * 3. transition to guest | transition to guest
1655 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1656 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1657 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1658 *
1659 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1660 *
1661 * - ret0 < ret1
1662 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1663 * ...
1664 * - 0 < N - M => M < N
1665 *
1666 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1667 * always the case (the difference between two distinct xtime instances
1668 * might be smaller then the difference between corresponding TSC reads,
1669 * when updating guest vcpus pvclock areas).
1670 *
1671 * To avoid that problem, do not allow visibility of distinct
1672 * system_timestamp/tsc_timestamp values simultaneously: use a master
1673 * copy of host monotonic time values. Update that master copy
1674 * in lockstep.
1675 *
1676 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1677 *
1678 */
1679
1680 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1681 {
1682 #ifdef CONFIG_X86_64
1683 struct kvm_arch *ka = &kvm->arch;
1684 int vclock_mode;
1685 bool host_tsc_clocksource, vcpus_matched;
1686
1687 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1688 atomic_read(&kvm->online_vcpus));
1689
1690 /*
1691 * If the host uses TSC clock, then passthrough TSC as stable
1692 * to the guest.
1693 */
1694 host_tsc_clocksource = kvm_get_time_and_clockread(
1695 &ka->master_kernel_ns,
1696 &ka->master_cycle_now);
1697
1698 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1699 && !backwards_tsc_observed
1700 && !ka->boot_vcpu_runs_old_kvmclock;
1701
1702 if (ka->use_master_clock)
1703 atomic_set(&kvm_guest_has_master_clock, 1);
1704
1705 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1706 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1707 vcpus_matched);
1708 #endif
1709 }
1710
1711 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1712 {
1713 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1714 }
1715
1716 static void kvm_gen_update_masterclock(struct kvm *kvm)
1717 {
1718 #ifdef CONFIG_X86_64
1719 int i;
1720 struct kvm_vcpu *vcpu;
1721 struct kvm_arch *ka = &kvm->arch;
1722
1723 spin_lock(&ka->pvclock_gtod_sync_lock);
1724 kvm_make_mclock_inprogress_request(kvm);
1725 /* no guest entries from this point */
1726 pvclock_update_vm_gtod_copy(kvm);
1727
1728 kvm_for_each_vcpu(i, vcpu, kvm)
1729 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1730
1731 /* guest entries allowed */
1732 kvm_for_each_vcpu(i, vcpu, kvm)
1733 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1734
1735 spin_unlock(&ka->pvclock_gtod_sync_lock);
1736 #endif
1737 }
1738
1739 static u64 __get_kvmclock_ns(struct kvm *kvm)
1740 {
1741 struct kvm_arch *ka = &kvm->arch;
1742 struct pvclock_vcpu_time_info hv_clock;
1743
1744 spin_lock(&ka->pvclock_gtod_sync_lock);
1745 if (!ka->use_master_clock) {
1746 spin_unlock(&ka->pvclock_gtod_sync_lock);
1747 return ktime_get_boot_ns() + ka->kvmclock_offset;
1748 }
1749
1750 hv_clock.tsc_timestamp = ka->master_cycle_now;
1751 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1752 spin_unlock(&ka->pvclock_gtod_sync_lock);
1753
1754 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1755 &hv_clock.tsc_shift,
1756 &hv_clock.tsc_to_system_mul);
1757 return __pvclock_read_cycles(&hv_clock, rdtsc());
1758 }
1759
1760 u64 get_kvmclock_ns(struct kvm *kvm)
1761 {
1762 unsigned long flags;
1763 s64 ns;
1764
1765 local_irq_save(flags);
1766 ns = __get_kvmclock_ns(kvm);
1767 local_irq_restore(flags);
1768
1769 return ns;
1770 }
1771
1772 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1773 {
1774 struct kvm_vcpu_arch *vcpu = &v->arch;
1775 struct pvclock_vcpu_time_info guest_hv_clock;
1776
1777 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1778 &guest_hv_clock, sizeof(guest_hv_clock))))
1779 return;
1780
1781 /* This VCPU is paused, but it's legal for a guest to read another
1782 * VCPU's kvmclock, so we really have to follow the specification where
1783 * it says that version is odd if data is being modified, and even after
1784 * it is consistent.
1785 *
1786 * Version field updates must be kept separate. This is because
1787 * kvm_write_guest_cached might use a "rep movs" instruction, and
1788 * writes within a string instruction are weakly ordered. So there
1789 * are three writes overall.
1790 *
1791 * As a small optimization, only write the version field in the first
1792 * and third write. The vcpu->pv_time cache is still valid, because the
1793 * version field is the first in the struct.
1794 */
1795 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1796
1797 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1798 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1799 &vcpu->hv_clock,
1800 sizeof(vcpu->hv_clock.version));
1801
1802 smp_wmb();
1803
1804 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1805 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1806
1807 if (vcpu->pvclock_set_guest_stopped_request) {
1808 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1809 vcpu->pvclock_set_guest_stopped_request = false;
1810 }
1811
1812 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1813
1814 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1815 &vcpu->hv_clock,
1816 sizeof(vcpu->hv_clock));
1817
1818 smp_wmb();
1819
1820 vcpu->hv_clock.version++;
1821 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1822 &vcpu->hv_clock,
1823 sizeof(vcpu->hv_clock.version));
1824 }
1825
1826 static int kvm_guest_time_update(struct kvm_vcpu *v)
1827 {
1828 unsigned long flags, tgt_tsc_khz;
1829 struct kvm_vcpu_arch *vcpu = &v->arch;
1830 struct kvm_arch *ka = &v->kvm->arch;
1831 s64 kernel_ns;
1832 u64 tsc_timestamp, host_tsc;
1833 u8 pvclock_flags;
1834 bool use_master_clock;
1835
1836 kernel_ns = 0;
1837 host_tsc = 0;
1838
1839 /*
1840 * If the host uses TSC clock, then passthrough TSC as stable
1841 * to the guest.
1842 */
1843 spin_lock(&ka->pvclock_gtod_sync_lock);
1844 use_master_clock = ka->use_master_clock;
1845 if (use_master_clock) {
1846 host_tsc = ka->master_cycle_now;
1847 kernel_ns = ka->master_kernel_ns;
1848 }
1849 spin_unlock(&ka->pvclock_gtod_sync_lock);
1850
1851 /* Keep irq disabled to prevent changes to the clock */
1852 local_irq_save(flags);
1853 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1854 if (unlikely(tgt_tsc_khz == 0)) {
1855 local_irq_restore(flags);
1856 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1857 return 1;
1858 }
1859 if (!use_master_clock) {
1860 host_tsc = rdtsc();
1861 kernel_ns = ktime_get_boot_ns();
1862 }
1863
1864 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1865
1866 /*
1867 * We may have to catch up the TSC to match elapsed wall clock
1868 * time for two reasons, even if kvmclock is used.
1869 * 1) CPU could have been running below the maximum TSC rate
1870 * 2) Broken TSC compensation resets the base at each VCPU
1871 * entry to avoid unknown leaps of TSC even when running
1872 * again on the same CPU. This may cause apparent elapsed
1873 * time to disappear, and the guest to stand still or run
1874 * very slowly.
1875 */
1876 if (vcpu->tsc_catchup) {
1877 u64 tsc = compute_guest_tsc(v, kernel_ns);
1878 if (tsc > tsc_timestamp) {
1879 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1880 tsc_timestamp = tsc;
1881 }
1882 }
1883
1884 local_irq_restore(flags);
1885
1886 /* With all the info we got, fill in the values */
1887
1888 if (kvm_has_tsc_control)
1889 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1890
1891 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1892 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1893 &vcpu->hv_clock.tsc_shift,
1894 &vcpu->hv_clock.tsc_to_system_mul);
1895 vcpu->hw_tsc_khz = tgt_tsc_khz;
1896 }
1897
1898 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1899 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1900 vcpu->last_guest_tsc = tsc_timestamp;
1901
1902 /* If the host uses TSC clocksource, then it is stable */
1903 pvclock_flags = 0;
1904 if (use_master_clock)
1905 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1906
1907 vcpu->hv_clock.flags = pvclock_flags;
1908
1909 if (vcpu->pv_time_enabled)
1910 kvm_setup_pvclock_page(v);
1911 if (v == kvm_get_vcpu(v->kvm, 0))
1912 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
1913 return 0;
1914 }
1915
1916 /*
1917 * kvmclock updates which are isolated to a given vcpu, such as
1918 * vcpu->cpu migration, should not allow system_timestamp from
1919 * the rest of the vcpus to remain static. Otherwise ntp frequency
1920 * correction applies to one vcpu's system_timestamp but not
1921 * the others.
1922 *
1923 * So in those cases, request a kvmclock update for all vcpus.
1924 * We need to rate-limit these requests though, as they can
1925 * considerably slow guests that have a large number of vcpus.
1926 * The time for a remote vcpu to update its kvmclock is bound
1927 * by the delay we use to rate-limit the updates.
1928 */
1929
1930 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1931
1932 static void kvmclock_update_fn(struct work_struct *work)
1933 {
1934 int i;
1935 struct delayed_work *dwork = to_delayed_work(work);
1936 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1937 kvmclock_update_work);
1938 struct kvm *kvm = container_of(ka, struct kvm, arch);
1939 struct kvm_vcpu *vcpu;
1940
1941 kvm_for_each_vcpu(i, vcpu, kvm) {
1942 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1943 kvm_vcpu_kick(vcpu);
1944 }
1945 }
1946
1947 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1948 {
1949 struct kvm *kvm = v->kvm;
1950
1951 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1952 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1953 KVMCLOCK_UPDATE_DELAY);
1954 }
1955
1956 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1957
1958 static void kvmclock_sync_fn(struct work_struct *work)
1959 {
1960 struct delayed_work *dwork = to_delayed_work(work);
1961 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1962 kvmclock_sync_work);
1963 struct kvm *kvm = container_of(ka, struct kvm, arch);
1964
1965 if (!kvmclock_periodic_sync)
1966 return;
1967
1968 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1969 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1970 KVMCLOCK_SYNC_PERIOD);
1971 }
1972
1973 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1974 {
1975 u64 mcg_cap = vcpu->arch.mcg_cap;
1976 unsigned bank_num = mcg_cap & 0xff;
1977
1978 switch (msr) {
1979 case MSR_IA32_MCG_STATUS:
1980 vcpu->arch.mcg_status = data;
1981 break;
1982 case MSR_IA32_MCG_CTL:
1983 if (!(mcg_cap & MCG_CTL_P))
1984 return 1;
1985 if (data != 0 && data != ~(u64)0)
1986 return -1;
1987 vcpu->arch.mcg_ctl = data;
1988 break;
1989 default:
1990 if (msr >= MSR_IA32_MC0_CTL &&
1991 msr < MSR_IA32_MCx_CTL(bank_num)) {
1992 u32 offset = msr - MSR_IA32_MC0_CTL;
1993 /* only 0 or all 1s can be written to IA32_MCi_CTL
1994 * some Linux kernels though clear bit 10 in bank 4 to
1995 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1996 * this to avoid an uncatched #GP in the guest
1997 */
1998 if ((offset & 0x3) == 0 &&
1999 data != 0 && (data | (1 << 10)) != ~(u64)0)
2000 return -1;
2001 vcpu->arch.mce_banks[offset] = data;
2002 break;
2003 }
2004 return 1;
2005 }
2006 return 0;
2007 }
2008
2009 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2010 {
2011 struct kvm *kvm = vcpu->kvm;
2012 int lm = is_long_mode(vcpu);
2013 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2014 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2015 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2016 : kvm->arch.xen_hvm_config.blob_size_32;
2017 u32 page_num = data & ~PAGE_MASK;
2018 u64 page_addr = data & PAGE_MASK;
2019 u8 *page;
2020 int r;
2021
2022 r = -E2BIG;
2023 if (page_num >= blob_size)
2024 goto out;
2025 r = -ENOMEM;
2026 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2027 if (IS_ERR(page)) {
2028 r = PTR_ERR(page);
2029 goto out;
2030 }
2031 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2032 goto out_free;
2033 r = 0;
2034 out_free:
2035 kfree(page);
2036 out:
2037 return r;
2038 }
2039
2040 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2041 {
2042 gpa_t gpa = data & ~0x3f;
2043
2044 /* Bits 2:5 are reserved, Should be zero */
2045 if (data & 0x3c)
2046 return 1;
2047
2048 vcpu->arch.apf.msr_val = data;
2049
2050 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2051 kvm_clear_async_pf_completion_queue(vcpu);
2052 kvm_async_pf_hash_reset(vcpu);
2053 return 0;
2054 }
2055
2056 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2057 sizeof(u32)))
2058 return 1;
2059
2060 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2061 kvm_async_pf_wakeup_all(vcpu);
2062 return 0;
2063 }
2064
2065 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2066 {
2067 vcpu->arch.pv_time_enabled = false;
2068 }
2069
2070 static void record_steal_time(struct kvm_vcpu *vcpu)
2071 {
2072 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2073 return;
2074
2075 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2076 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2077 return;
2078
2079 vcpu->arch.st.steal.preempted = 0;
2080
2081 if (vcpu->arch.st.steal.version & 1)
2082 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2083
2084 vcpu->arch.st.steal.version += 1;
2085
2086 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2087 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2088
2089 smp_wmb();
2090
2091 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2092 vcpu->arch.st.last_steal;
2093 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2094
2095 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2096 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2097
2098 smp_wmb();
2099
2100 vcpu->arch.st.steal.version += 1;
2101
2102 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2103 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2104 }
2105
2106 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2107 {
2108 bool pr = false;
2109 u32 msr = msr_info->index;
2110 u64 data = msr_info->data;
2111
2112 switch (msr) {
2113 case MSR_AMD64_NB_CFG:
2114 case MSR_IA32_UCODE_REV:
2115 case MSR_IA32_UCODE_WRITE:
2116 case MSR_VM_HSAVE_PA:
2117 case MSR_AMD64_PATCH_LOADER:
2118 case MSR_AMD64_BU_CFG2:
2119 break;
2120
2121 case MSR_EFER:
2122 return set_efer(vcpu, data);
2123 case MSR_K7_HWCR:
2124 data &= ~(u64)0x40; /* ignore flush filter disable */
2125 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2126 data &= ~(u64)0x8; /* ignore TLB cache disable */
2127 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2128 if (data != 0) {
2129 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2130 data);
2131 return 1;
2132 }
2133 break;
2134 case MSR_FAM10H_MMIO_CONF_BASE:
2135 if (data != 0) {
2136 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2137 "0x%llx\n", data);
2138 return 1;
2139 }
2140 break;
2141 case MSR_IA32_DEBUGCTLMSR:
2142 if (!data) {
2143 /* We support the non-activated case already */
2144 break;
2145 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2146 /* Values other than LBR and BTF are vendor-specific,
2147 thus reserved and should throw a #GP */
2148 return 1;
2149 }
2150 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2151 __func__, data);
2152 break;
2153 case 0x200 ... 0x2ff:
2154 return kvm_mtrr_set_msr(vcpu, msr, data);
2155 case MSR_IA32_APICBASE:
2156 return kvm_set_apic_base(vcpu, msr_info);
2157 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2158 return kvm_x2apic_msr_write(vcpu, msr, data);
2159 case MSR_IA32_TSCDEADLINE:
2160 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2161 break;
2162 case MSR_IA32_TSC_ADJUST:
2163 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2164 if (!msr_info->host_initiated) {
2165 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2166 adjust_tsc_offset_guest(vcpu, adj);
2167 }
2168 vcpu->arch.ia32_tsc_adjust_msr = data;
2169 }
2170 break;
2171 case MSR_IA32_MISC_ENABLE:
2172 vcpu->arch.ia32_misc_enable_msr = data;
2173 break;
2174 case MSR_IA32_SMBASE:
2175 if (!msr_info->host_initiated)
2176 return 1;
2177 vcpu->arch.smbase = data;
2178 break;
2179 case MSR_KVM_WALL_CLOCK_NEW:
2180 case MSR_KVM_WALL_CLOCK:
2181 vcpu->kvm->arch.wall_clock = data;
2182 kvm_write_wall_clock(vcpu->kvm, data);
2183 break;
2184 case MSR_KVM_SYSTEM_TIME_NEW:
2185 case MSR_KVM_SYSTEM_TIME: {
2186 struct kvm_arch *ka = &vcpu->kvm->arch;
2187
2188 kvmclock_reset(vcpu);
2189
2190 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2191 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2192
2193 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2194 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2195 &vcpu->requests);
2196
2197 ka->boot_vcpu_runs_old_kvmclock = tmp;
2198 }
2199
2200 vcpu->arch.time = data;
2201 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2202
2203 /* we verify if the enable bit is set... */
2204 if (!(data & 1))
2205 break;
2206
2207 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2208 &vcpu->arch.pv_time, data & ~1ULL,
2209 sizeof(struct pvclock_vcpu_time_info)))
2210 vcpu->arch.pv_time_enabled = false;
2211 else
2212 vcpu->arch.pv_time_enabled = true;
2213
2214 break;
2215 }
2216 case MSR_KVM_ASYNC_PF_EN:
2217 if (kvm_pv_enable_async_pf(vcpu, data))
2218 return 1;
2219 break;
2220 case MSR_KVM_STEAL_TIME:
2221
2222 if (unlikely(!sched_info_on()))
2223 return 1;
2224
2225 if (data & KVM_STEAL_RESERVED_MASK)
2226 return 1;
2227
2228 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2229 data & KVM_STEAL_VALID_BITS,
2230 sizeof(struct kvm_steal_time)))
2231 return 1;
2232
2233 vcpu->arch.st.msr_val = data;
2234
2235 if (!(data & KVM_MSR_ENABLED))
2236 break;
2237
2238 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2239
2240 break;
2241 case MSR_KVM_PV_EOI_EN:
2242 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2243 return 1;
2244 break;
2245
2246 case MSR_IA32_MCG_CTL:
2247 case MSR_IA32_MCG_STATUS:
2248 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2249 return set_msr_mce(vcpu, msr, data);
2250
2251 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2252 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2253 pr = true; /* fall through */
2254 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2255 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2256 if (kvm_pmu_is_valid_msr(vcpu, msr))
2257 return kvm_pmu_set_msr(vcpu, msr_info);
2258
2259 if (pr || data != 0)
2260 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2261 "0x%x data 0x%llx\n", msr, data);
2262 break;
2263 case MSR_K7_CLK_CTL:
2264 /*
2265 * Ignore all writes to this no longer documented MSR.
2266 * Writes are only relevant for old K7 processors,
2267 * all pre-dating SVM, but a recommended workaround from
2268 * AMD for these chips. It is possible to specify the
2269 * affected processor models on the command line, hence
2270 * the need to ignore the workaround.
2271 */
2272 break;
2273 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2274 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2275 case HV_X64_MSR_CRASH_CTL:
2276 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2277 return kvm_hv_set_msr_common(vcpu, msr, data,
2278 msr_info->host_initiated);
2279 case MSR_IA32_BBL_CR_CTL3:
2280 /* Drop writes to this legacy MSR -- see rdmsr
2281 * counterpart for further detail.
2282 */
2283 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
2284 break;
2285 case MSR_AMD64_OSVW_ID_LENGTH:
2286 if (!guest_cpuid_has_osvw(vcpu))
2287 return 1;
2288 vcpu->arch.osvw.length = data;
2289 break;
2290 case MSR_AMD64_OSVW_STATUS:
2291 if (!guest_cpuid_has_osvw(vcpu))
2292 return 1;
2293 vcpu->arch.osvw.status = data;
2294 break;
2295 default:
2296 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2297 return xen_hvm_config(vcpu, data);
2298 if (kvm_pmu_is_valid_msr(vcpu, msr))
2299 return kvm_pmu_set_msr(vcpu, msr_info);
2300 if (!ignore_msrs) {
2301 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2302 msr, data);
2303 return 1;
2304 } else {
2305 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2306 msr, data);
2307 break;
2308 }
2309 }
2310 return 0;
2311 }
2312 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2313
2314
2315 /*
2316 * Reads an msr value (of 'msr_index') into 'pdata'.
2317 * Returns 0 on success, non-0 otherwise.
2318 * Assumes vcpu_load() was already called.
2319 */
2320 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2321 {
2322 return kvm_x86_ops->get_msr(vcpu, msr);
2323 }
2324 EXPORT_SYMBOL_GPL(kvm_get_msr);
2325
2326 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2327 {
2328 u64 data;
2329 u64 mcg_cap = vcpu->arch.mcg_cap;
2330 unsigned bank_num = mcg_cap & 0xff;
2331
2332 switch (msr) {
2333 case MSR_IA32_P5_MC_ADDR:
2334 case MSR_IA32_P5_MC_TYPE:
2335 data = 0;
2336 break;
2337 case MSR_IA32_MCG_CAP:
2338 data = vcpu->arch.mcg_cap;
2339 break;
2340 case MSR_IA32_MCG_CTL:
2341 if (!(mcg_cap & MCG_CTL_P))
2342 return 1;
2343 data = vcpu->arch.mcg_ctl;
2344 break;
2345 case MSR_IA32_MCG_STATUS:
2346 data = vcpu->arch.mcg_status;
2347 break;
2348 default:
2349 if (msr >= MSR_IA32_MC0_CTL &&
2350 msr < MSR_IA32_MCx_CTL(bank_num)) {
2351 u32 offset = msr - MSR_IA32_MC0_CTL;
2352 data = vcpu->arch.mce_banks[offset];
2353 break;
2354 }
2355 return 1;
2356 }
2357 *pdata = data;
2358 return 0;
2359 }
2360
2361 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2362 {
2363 switch (msr_info->index) {
2364 case MSR_IA32_PLATFORM_ID:
2365 case MSR_IA32_EBL_CR_POWERON:
2366 case MSR_IA32_DEBUGCTLMSR:
2367 case MSR_IA32_LASTBRANCHFROMIP:
2368 case MSR_IA32_LASTBRANCHTOIP:
2369 case MSR_IA32_LASTINTFROMIP:
2370 case MSR_IA32_LASTINTTOIP:
2371 case MSR_K8_SYSCFG:
2372 case MSR_K8_TSEG_ADDR:
2373 case MSR_K8_TSEG_MASK:
2374 case MSR_K7_HWCR:
2375 case MSR_VM_HSAVE_PA:
2376 case MSR_K8_INT_PENDING_MSG:
2377 case MSR_AMD64_NB_CFG:
2378 case MSR_FAM10H_MMIO_CONF_BASE:
2379 case MSR_AMD64_BU_CFG2:
2380 case MSR_IA32_PERF_CTL:
2381 msr_info->data = 0;
2382 break;
2383 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2384 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2385 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2386 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2387 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2388 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2389 msr_info->data = 0;
2390 break;
2391 case MSR_IA32_UCODE_REV:
2392 msr_info->data = 0x100000000ULL;
2393 break;
2394 case MSR_MTRRcap:
2395 case 0x200 ... 0x2ff:
2396 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2397 case 0xcd: /* fsb frequency */
2398 msr_info->data = 3;
2399 break;
2400 /*
2401 * MSR_EBC_FREQUENCY_ID
2402 * Conservative value valid for even the basic CPU models.
2403 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2404 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2405 * and 266MHz for model 3, or 4. Set Core Clock
2406 * Frequency to System Bus Frequency Ratio to 1 (bits
2407 * 31:24) even though these are only valid for CPU
2408 * models > 2, however guests may end up dividing or
2409 * multiplying by zero otherwise.
2410 */
2411 case MSR_EBC_FREQUENCY_ID:
2412 msr_info->data = 1 << 24;
2413 break;
2414 case MSR_IA32_APICBASE:
2415 msr_info->data = kvm_get_apic_base(vcpu);
2416 break;
2417 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2418 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2419 break;
2420 case MSR_IA32_TSCDEADLINE:
2421 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2422 break;
2423 case MSR_IA32_TSC_ADJUST:
2424 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2425 break;
2426 case MSR_IA32_MISC_ENABLE:
2427 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2428 break;
2429 case MSR_IA32_SMBASE:
2430 if (!msr_info->host_initiated)
2431 return 1;
2432 msr_info->data = vcpu->arch.smbase;
2433 break;
2434 case MSR_IA32_PERF_STATUS:
2435 /* TSC increment by tick */
2436 msr_info->data = 1000ULL;
2437 /* CPU multiplier */
2438 msr_info->data |= (((uint64_t)4ULL) << 40);
2439 break;
2440 case MSR_EFER:
2441 msr_info->data = vcpu->arch.efer;
2442 break;
2443 case MSR_KVM_WALL_CLOCK:
2444 case MSR_KVM_WALL_CLOCK_NEW:
2445 msr_info->data = vcpu->kvm->arch.wall_clock;
2446 break;
2447 case MSR_KVM_SYSTEM_TIME:
2448 case MSR_KVM_SYSTEM_TIME_NEW:
2449 msr_info->data = vcpu->arch.time;
2450 break;
2451 case MSR_KVM_ASYNC_PF_EN:
2452 msr_info->data = vcpu->arch.apf.msr_val;
2453 break;
2454 case MSR_KVM_STEAL_TIME:
2455 msr_info->data = vcpu->arch.st.msr_val;
2456 break;
2457 case MSR_KVM_PV_EOI_EN:
2458 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2459 break;
2460 case MSR_IA32_P5_MC_ADDR:
2461 case MSR_IA32_P5_MC_TYPE:
2462 case MSR_IA32_MCG_CAP:
2463 case MSR_IA32_MCG_CTL:
2464 case MSR_IA32_MCG_STATUS:
2465 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2466 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2467 case MSR_K7_CLK_CTL:
2468 /*
2469 * Provide expected ramp-up count for K7. All other
2470 * are set to zero, indicating minimum divisors for
2471 * every field.
2472 *
2473 * This prevents guest kernels on AMD host with CPU
2474 * type 6, model 8 and higher from exploding due to
2475 * the rdmsr failing.
2476 */
2477 msr_info->data = 0x20000000;
2478 break;
2479 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2480 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2481 case HV_X64_MSR_CRASH_CTL:
2482 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2483 return kvm_hv_get_msr_common(vcpu,
2484 msr_info->index, &msr_info->data);
2485 break;
2486 case MSR_IA32_BBL_CR_CTL3:
2487 /* This legacy MSR exists but isn't fully documented in current
2488 * silicon. It is however accessed by winxp in very narrow
2489 * scenarios where it sets bit #19, itself documented as
2490 * a "reserved" bit. Best effort attempt to source coherent
2491 * read data here should the balance of the register be
2492 * interpreted by the guest:
2493 *
2494 * L2 cache control register 3: 64GB range, 256KB size,
2495 * enabled, latency 0x1, configured
2496 */
2497 msr_info->data = 0xbe702111;
2498 break;
2499 case MSR_AMD64_OSVW_ID_LENGTH:
2500 if (!guest_cpuid_has_osvw(vcpu))
2501 return 1;
2502 msr_info->data = vcpu->arch.osvw.length;
2503 break;
2504 case MSR_AMD64_OSVW_STATUS:
2505 if (!guest_cpuid_has_osvw(vcpu))
2506 return 1;
2507 msr_info->data = vcpu->arch.osvw.status;
2508 break;
2509 default:
2510 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2511 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2512 if (!ignore_msrs) {
2513 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2514 msr_info->index);
2515 return 1;
2516 } else {
2517 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2518 msr_info->data = 0;
2519 }
2520 break;
2521 }
2522 return 0;
2523 }
2524 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2525
2526 /*
2527 * Read or write a bunch of msrs. All parameters are kernel addresses.
2528 *
2529 * @return number of msrs set successfully.
2530 */
2531 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2532 struct kvm_msr_entry *entries,
2533 int (*do_msr)(struct kvm_vcpu *vcpu,
2534 unsigned index, u64 *data))
2535 {
2536 int i, idx;
2537
2538 idx = srcu_read_lock(&vcpu->kvm->srcu);
2539 for (i = 0; i < msrs->nmsrs; ++i)
2540 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2541 break;
2542 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2543
2544 return i;
2545 }
2546
2547 /*
2548 * Read or write a bunch of msrs. Parameters are user addresses.
2549 *
2550 * @return number of msrs set successfully.
2551 */
2552 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2553 int (*do_msr)(struct kvm_vcpu *vcpu,
2554 unsigned index, u64 *data),
2555 int writeback)
2556 {
2557 struct kvm_msrs msrs;
2558 struct kvm_msr_entry *entries;
2559 int r, n;
2560 unsigned size;
2561
2562 r = -EFAULT;
2563 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2564 goto out;
2565
2566 r = -E2BIG;
2567 if (msrs.nmsrs >= MAX_IO_MSRS)
2568 goto out;
2569
2570 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2571 entries = memdup_user(user_msrs->entries, size);
2572 if (IS_ERR(entries)) {
2573 r = PTR_ERR(entries);
2574 goto out;
2575 }
2576
2577 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2578 if (r < 0)
2579 goto out_free;
2580
2581 r = -EFAULT;
2582 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2583 goto out_free;
2584
2585 r = n;
2586
2587 out_free:
2588 kfree(entries);
2589 out:
2590 return r;
2591 }
2592
2593 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2594 {
2595 int r;
2596
2597 switch (ext) {
2598 case KVM_CAP_IRQCHIP:
2599 case KVM_CAP_HLT:
2600 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2601 case KVM_CAP_SET_TSS_ADDR:
2602 case KVM_CAP_EXT_CPUID:
2603 case KVM_CAP_EXT_EMUL_CPUID:
2604 case KVM_CAP_CLOCKSOURCE:
2605 case KVM_CAP_PIT:
2606 case KVM_CAP_NOP_IO_DELAY:
2607 case KVM_CAP_MP_STATE:
2608 case KVM_CAP_SYNC_MMU:
2609 case KVM_CAP_USER_NMI:
2610 case KVM_CAP_REINJECT_CONTROL:
2611 case KVM_CAP_IRQ_INJECT_STATUS:
2612 case KVM_CAP_IOEVENTFD:
2613 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2614 case KVM_CAP_PIT2:
2615 case KVM_CAP_PIT_STATE2:
2616 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2617 case KVM_CAP_XEN_HVM:
2618 case KVM_CAP_VCPU_EVENTS:
2619 case KVM_CAP_HYPERV:
2620 case KVM_CAP_HYPERV_VAPIC:
2621 case KVM_CAP_HYPERV_SPIN:
2622 case KVM_CAP_HYPERV_SYNIC:
2623 case KVM_CAP_PCI_SEGMENT:
2624 case KVM_CAP_DEBUGREGS:
2625 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2626 case KVM_CAP_XSAVE:
2627 case KVM_CAP_ASYNC_PF:
2628 case KVM_CAP_GET_TSC_KHZ:
2629 case KVM_CAP_KVMCLOCK_CTRL:
2630 case KVM_CAP_READONLY_MEM:
2631 case KVM_CAP_HYPERV_TIME:
2632 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2633 case KVM_CAP_TSC_DEADLINE_TIMER:
2634 case KVM_CAP_ENABLE_CAP_VM:
2635 case KVM_CAP_DISABLE_QUIRKS:
2636 case KVM_CAP_SET_BOOT_CPU_ID:
2637 case KVM_CAP_SPLIT_IRQCHIP:
2638 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2639 case KVM_CAP_ASSIGN_DEV_IRQ:
2640 case KVM_CAP_PCI_2_3:
2641 #endif
2642 r = 1;
2643 break;
2644 case KVM_CAP_ADJUST_CLOCK:
2645 r = KVM_CLOCK_TSC_STABLE;
2646 break;
2647 case KVM_CAP_X86_SMM:
2648 /* SMBASE is usually relocated above 1M on modern chipsets,
2649 * and SMM handlers might indeed rely on 4G segment limits,
2650 * so do not report SMM to be available if real mode is
2651 * emulated via vm86 mode. Still, do not go to great lengths
2652 * to avoid userspace's usage of the feature, because it is a
2653 * fringe case that is not enabled except via specific settings
2654 * of the module parameters.
2655 */
2656 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2657 break;
2658 case KVM_CAP_COALESCED_MMIO:
2659 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2660 break;
2661 case KVM_CAP_VAPIC:
2662 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2663 break;
2664 case KVM_CAP_NR_VCPUS:
2665 r = KVM_SOFT_MAX_VCPUS;
2666 break;
2667 case KVM_CAP_MAX_VCPUS:
2668 r = KVM_MAX_VCPUS;
2669 break;
2670 case KVM_CAP_NR_MEMSLOTS:
2671 r = KVM_USER_MEM_SLOTS;
2672 break;
2673 case KVM_CAP_PV_MMU: /* obsolete */
2674 r = 0;
2675 break;
2676 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2677 case KVM_CAP_IOMMU:
2678 r = iommu_present(&pci_bus_type);
2679 break;
2680 #endif
2681 case KVM_CAP_MCE:
2682 r = KVM_MAX_MCE_BANKS;
2683 break;
2684 case KVM_CAP_XCRS:
2685 r = boot_cpu_has(X86_FEATURE_XSAVE);
2686 break;
2687 case KVM_CAP_TSC_CONTROL:
2688 r = kvm_has_tsc_control;
2689 break;
2690 case KVM_CAP_X2APIC_API:
2691 r = KVM_X2APIC_API_VALID_FLAGS;
2692 break;
2693 default:
2694 r = 0;
2695 break;
2696 }
2697 return r;
2698
2699 }
2700
2701 long kvm_arch_dev_ioctl(struct file *filp,
2702 unsigned int ioctl, unsigned long arg)
2703 {
2704 void __user *argp = (void __user *)arg;
2705 long r;
2706
2707 switch (ioctl) {
2708 case KVM_GET_MSR_INDEX_LIST: {
2709 struct kvm_msr_list __user *user_msr_list = argp;
2710 struct kvm_msr_list msr_list;
2711 unsigned n;
2712
2713 r = -EFAULT;
2714 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2715 goto out;
2716 n = msr_list.nmsrs;
2717 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2718 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2719 goto out;
2720 r = -E2BIG;
2721 if (n < msr_list.nmsrs)
2722 goto out;
2723 r = -EFAULT;
2724 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2725 num_msrs_to_save * sizeof(u32)))
2726 goto out;
2727 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2728 &emulated_msrs,
2729 num_emulated_msrs * sizeof(u32)))
2730 goto out;
2731 r = 0;
2732 break;
2733 }
2734 case KVM_GET_SUPPORTED_CPUID:
2735 case KVM_GET_EMULATED_CPUID: {
2736 struct kvm_cpuid2 __user *cpuid_arg = argp;
2737 struct kvm_cpuid2 cpuid;
2738
2739 r = -EFAULT;
2740 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2741 goto out;
2742
2743 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2744 ioctl);
2745 if (r)
2746 goto out;
2747
2748 r = -EFAULT;
2749 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2750 goto out;
2751 r = 0;
2752 break;
2753 }
2754 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2755 r = -EFAULT;
2756 if (copy_to_user(argp, &kvm_mce_cap_supported,
2757 sizeof(kvm_mce_cap_supported)))
2758 goto out;
2759 r = 0;
2760 break;
2761 }
2762 default:
2763 r = -EINVAL;
2764 }
2765 out:
2766 return r;
2767 }
2768
2769 static void wbinvd_ipi(void *garbage)
2770 {
2771 wbinvd();
2772 }
2773
2774 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2775 {
2776 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2777 }
2778
2779 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2780 {
2781 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2782 }
2783
2784 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2785 {
2786 /* Address WBINVD may be executed by guest */
2787 if (need_emulate_wbinvd(vcpu)) {
2788 if (kvm_x86_ops->has_wbinvd_exit())
2789 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2790 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2791 smp_call_function_single(vcpu->cpu,
2792 wbinvd_ipi, NULL, 1);
2793 }
2794
2795 kvm_x86_ops->vcpu_load(vcpu, cpu);
2796
2797 /* Apply any externally detected TSC adjustments (due to suspend) */
2798 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2799 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2800 vcpu->arch.tsc_offset_adjustment = 0;
2801 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2802 }
2803
2804 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2805 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2806 rdtsc() - vcpu->arch.last_host_tsc;
2807 if (tsc_delta < 0)
2808 mark_tsc_unstable("KVM discovered backwards TSC");
2809
2810 if (check_tsc_unstable()) {
2811 u64 offset = kvm_compute_tsc_offset(vcpu,
2812 vcpu->arch.last_guest_tsc);
2813 kvm_vcpu_write_tsc_offset(vcpu, offset);
2814 vcpu->arch.tsc_catchup = 1;
2815 }
2816 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2817 kvm_x86_ops->set_hv_timer(vcpu,
2818 kvm_get_lapic_target_expiration_tsc(vcpu)))
2819 kvm_lapic_switch_to_sw_timer(vcpu);
2820 /*
2821 * On a host with synchronized TSC, there is no need to update
2822 * kvmclock on vcpu->cpu migration
2823 */
2824 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2825 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2826 if (vcpu->cpu != cpu)
2827 kvm_migrate_timers(vcpu);
2828 vcpu->cpu = cpu;
2829 }
2830
2831 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2832 }
2833
2834 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2835 {
2836 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2837 return;
2838
2839 vcpu->arch.st.steal.preempted = 1;
2840
2841 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
2842 &vcpu->arch.st.steal.preempted,
2843 offsetof(struct kvm_steal_time, preempted),
2844 sizeof(vcpu->arch.st.steal.preempted));
2845 }
2846
2847 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2848 {
2849 int idx;
2850 /*
2851 * Disable page faults because we're in atomic context here.
2852 * kvm_write_guest_offset_cached() would call might_fault()
2853 * that relies on pagefault_disable() to tell if there's a
2854 * bug. NOTE: the write to guest memory may not go through if
2855 * during postcopy live migration or if there's heavy guest
2856 * paging.
2857 */
2858 pagefault_disable();
2859 /*
2860 * kvm_memslots() will be called by
2861 * kvm_write_guest_offset_cached() so take the srcu lock.
2862 */
2863 idx = srcu_read_lock(&vcpu->kvm->srcu);
2864 kvm_steal_time_set_preempted(vcpu);
2865 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2866 pagefault_enable();
2867 kvm_x86_ops->vcpu_put(vcpu);
2868 kvm_put_guest_fpu(vcpu);
2869 vcpu->arch.last_host_tsc = rdtsc();
2870 }
2871
2872 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2873 struct kvm_lapic_state *s)
2874 {
2875 if (vcpu->arch.apicv_active)
2876 kvm_x86_ops->sync_pir_to_irr(vcpu);
2877
2878 return kvm_apic_get_state(vcpu, s);
2879 }
2880
2881 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2882 struct kvm_lapic_state *s)
2883 {
2884 int r;
2885
2886 r = kvm_apic_set_state(vcpu, s);
2887 if (r)
2888 return r;
2889 update_cr8_intercept(vcpu);
2890
2891 return 0;
2892 }
2893
2894 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2895 {
2896 return (!lapic_in_kernel(vcpu) ||
2897 kvm_apic_accept_pic_intr(vcpu));
2898 }
2899
2900 /*
2901 * if userspace requested an interrupt window, check that the
2902 * interrupt window is open.
2903 *
2904 * No need to exit to userspace if we already have an interrupt queued.
2905 */
2906 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2907 {
2908 return kvm_arch_interrupt_allowed(vcpu) &&
2909 !kvm_cpu_has_interrupt(vcpu) &&
2910 !kvm_event_needs_reinjection(vcpu) &&
2911 kvm_cpu_accept_dm_intr(vcpu);
2912 }
2913
2914 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2915 struct kvm_interrupt *irq)
2916 {
2917 if (irq->irq >= KVM_NR_INTERRUPTS)
2918 return -EINVAL;
2919
2920 if (!irqchip_in_kernel(vcpu->kvm)) {
2921 kvm_queue_interrupt(vcpu, irq->irq, false);
2922 kvm_make_request(KVM_REQ_EVENT, vcpu);
2923 return 0;
2924 }
2925
2926 /*
2927 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2928 * fail for in-kernel 8259.
2929 */
2930 if (pic_in_kernel(vcpu->kvm))
2931 return -ENXIO;
2932
2933 if (vcpu->arch.pending_external_vector != -1)
2934 return -EEXIST;
2935
2936 vcpu->arch.pending_external_vector = irq->irq;
2937 kvm_make_request(KVM_REQ_EVENT, vcpu);
2938 return 0;
2939 }
2940
2941 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2942 {
2943 kvm_inject_nmi(vcpu);
2944
2945 return 0;
2946 }
2947
2948 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2949 {
2950 kvm_make_request(KVM_REQ_SMI, vcpu);
2951
2952 return 0;
2953 }
2954
2955 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2956 struct kvm_tpr_access_ctl *tac)
2957 {
2958 if (tac->flags)
2959 return -EINVAL;
2960 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2961 return 0;
2962 }
2963
2964 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2965 u64 mcg_cap)
2966 {
2967 int r;
2968 unsigned bank_num = mcg_cap & 0xff, bank;
2969
2970 r = -EINVAL;
2971 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2972 goto out;
2973 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
2974 goto out;
2975 r = 0;
2976 vcpu->arch.mcg_cap = mcg_cap;
2977 /* Init IA32_MCG_CTL to all 1s */
2978 if (mcg_cap & MCG_CTL_P)
2979 vcpu->arch.mcg_ctl = ~(u64)0;
2980 /* Init IA32_MCi_CTL to all 1s */
2981 for (bank = 0; bank < bank_num; bank++)
2982 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2983
2984 if (kvm_x86_ops->setup_mce)
2985 kvm_x86_ops->setup_mce(vcpu);
2986 out:
2987 return r;
2988 }
2989
2990 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2991 struct kvm_x86_mce *mce)
2992 {
2993 u64 mcg_cap = vcpu->arch.mcg_cap;
2994 unsigned bank_num = mcg_cap & 0xff;
2995 u64 *banks = vcpu->arch.mce_banks;
2996
2997 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2998 return -EINVAL;
2999 /*
3000 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3001 * reporting is disabled
3002 */
3003 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3004 vcpu->arch.mcg_ctl != ~(u64)0)
3005 return 0;
3006 banks += 4 * mce->bank;
3007 /*
3008 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3009 * reporting is disabled for the bank
3010 */
3011 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3012 return 0;
3013 if (mce->status & MCI_STATUS_UC) {
3014 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3015 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3016 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3017 return 0;
3018 }
3019 if (banks[1] & MCI_STATUS_VAL)
3020 mce->status |= MCI_STATUS_OVER;
3021 banks[2] = mce->addr;
3022 banks[3] = mce->misc;
3023 vcpu->arch.mcg_status = mce->mcg_status;
3024 banks[1] = mce->status;
3025 kvm_queue_exception(vcpu, MC_VECTOR);
3026 } else if (!(banks[1] & MCI_STATUS_VAL)
3027 || !(banks[1] & MCI_STATUS_UC)) {
3028 if (banks[1] & MCI_STATUS_VAL)
3029 mce->status |= MCI_STATUS_OVER;
3030 banks[2] = mce->addr;
3031 banks[3] = mce->misc;
3032 banks[1] = mce->status;
3033 } else
3034 banks[1] |= MCI_STATUS_OVER;
3035 return 0;
3036 }
3037
3038 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3039 struct kvm_vcpu_events *events)
3040 {
3041 process_nmi(vcpu);
3042 events->exception.injected =
3043 vcpu->arch.exception.pending &&
3044 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3045 events->exception.nr = vcpu->arch.exception.nr;
3046 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3047 events->exception.pad = 0;
3048 events->exception.error_code = vcpu->arch.exception.error_code;
3049
3050 events->interrupt.injected =
3051 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3052 events->interrupt.nr = vcpu->arch.interrupt.nr;
3053 events->interrupt.soft = 0;
3054 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3055
3056 events->nmi.injected = vcpu->arch.nmi_injected;
3057 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3058 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3059 events->nmi.pad = 0;
3060
3061 events->sipi_vector = 0; /* never valid when reporting to user space */
3062
3063 events->smi.smm = is_smm(vcpu);
3064 events->smi.pending = vcpu->arch.smi_pending;
3065 events->smi.smm_inside_nmi =
3066 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3067 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3068
3069 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3070 | KVM_VCPUEVENT_VALID_SHADOW
3071 | KVM_VCPUEVENT_VALID_SMM);
3072 memset(&events->reserved, 0, sizeof(events->reserved));
3073 }
3074
3075 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3076
3077 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3078 struct kvm_vcpu_events *events)
3079 {
3080 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3081 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3082 | KVM_VCPUEVENT_VALID_SHADOW
3083 | KVM_VCPUEVENT_VALID_SMM))
3084 return -EINVAL;
3085
3086 if (events->exception.injected &&
3087 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3088 return -EINVAL;
3089
3090 process_nmi(vcpu);
3091 vcpu->arch.exception.pending = events->exception.injected;
3092 vcpu->arch.exception.nr = events->exception.nr;
3093 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3094 vcpu->arch.exception.error_code = events->exception.error_code;
3095
3096 vcpu->arch.interrupt.pending = events->interrupt.injected;
3097 vcpu->arch.interrupt.nr = events->interrupt.nr;
3098 vcpu->arch.interrupt.soft = events->interrupt.soft;
3099 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3100 kvm_x86_ops->set_interrupt_shadow(vcpu,
3101 events->interrupt.shadow);
3102
3103 vcpu->arch.nmi_injected = events->nmi.injected;
3104 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3105 vcpu->arch.nmi_pending = events->nmi.pending;
3106 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3107
3108 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3109 lapic_in_kernel(vcpu))
3110 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3111
3112 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3113 u32 hflags = vcpu->arch.hflags;
3114 if (events->smi.smm)
3115 hflags |= HF_SMM_MASK;
3116 else
3117 hflags &= ~HF_SMM_MASK;
3118 kvm_set_hflags(vcpu, hflags);
3119
3120 vcpu->arch.smi_pending = events->smi.pending;
3121 if (events->smi.smm_inside_nmi)
3122 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3123 else
3124 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3125 if (lapic_in_kernel(vcpu)) {
3126 if (events->smi.latched_init)
3127 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3128 else
3129 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3130 }
3131 }
3132
3133 kvm_make_request(KVM_REQ_EVENT, vcpu);
3134
3135 return 0;
3136 }
3137
3138 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3139 struct kvm_debugregs *dbgregs)
3140 {
3141 unsigned long val;
3142
3143 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3144 kvm_get_dr(vcpu, 6, &val);
3145 dbgregs->dr6 = val;
3146 dbgregs->dr7 = vcpu->arch.dr7;
3147 dbgregs->flags = 0;
3148 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3149 }
3150
3151 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3152 struct kvm_debugregs *dbgregs)
3153 {
3154 if (dbgregs->flags)
3155 return -EINVAL;
3156
3157 if (dbgregs->dr6 & ~0xffffffffull)
3158 return -EINVAL;
3159 if (dbgregs->dr7 & ~0xffffffffull)
3160 return -EINVAL;
3161
3162 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3163 kvm_update_dr0123(vcpu);
3164 vcpu->arch.dr6 = dbgregs->dr6;
3165 kvm_update_dr6(vcpu);
3166 vcpu->arch.dr7 = dbgregs->dr7;
3167 kvm_update_dr7(vcpu);
3168
3169 return 0;
3170 }
3171
3172 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3173
3174 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3175 {
3176 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3177 u64 xstate_bv = xsave->header.xfeatures;
3178 u64 valid;
3179
3180 /*
3181 * Copy legacy XSAVE area, to avoid complications with CPUID
3182 * leaves 0 and 1 in the loop below.
3183 */
3184 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3185
3186 /* Set XSTATE_BV */
3187 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3188
3189 /*
3190 * Copy each region from the possibly compacted offset to the
3191 * non-compacted offset.
3192 */
3193 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3194 while (valid) {
3195 u64 feature = valid & -valid;
3196 int index = fls64(feature) - 1;
3197 void *src = get_xsave_addr(xsave, feature);
3198
3199 if (src) {
3200 u32 size, offset, ecx, edx;
3201 cpuid_count(XSTATE_CPUID, index,
3202 &size, &offset, &ecx, &edx);
3203 memcpy(dest + offset, src, size);
3204 }
3205
3206 valid -= feature;
3207 }
3208 }
3209
3210 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3211 {
3212 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3213 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3214 u64 valid;
3215
3216 /*
3217 * Copy legacy XSAVE area, to avoid complications with CPUID
3218 * leaves 0 and 1 in the loop below.
3219 */
3220 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3221
3222 /* Set XSTATE_BV and possibly XCOMP_BV. */
3223 xsave->header.xfeatures = xstate_bv;
3224 if (boot_cpu_has(X86_FEATURE_XSAVES))
3225 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3226
3227 /*
3228 * Copy each region from the non-compacted offset to the
3229 * possibly compacted offset.
3230 */
3231 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3232 while (valid) {
3233 u64 feature = valid & -valid;
3234 int index = fls64(feature) - 1;
3235 void *dest = get_xsave_addr(xsave, feature);
3236
3237 if (dest) {
3238 u32 size, offset, ecx, edx;
3239 cpuid_count(XSTATE_CPUID, index,
3240 &size, &offset, &ecx, &edx);
3241 memcpy(dest, src + offset, size);
3242 }
3243
3244 valid -= feature;
3245 }
3246 }
3247
3248 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3249 struct kvm_xsave *guest_xsave)
3250 {
3251 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3252 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3253 fill_xsave((u8 *) guest_xsave->region, vcpu);
3254 } else {
3255 memcpy(guest_xsave->region,
3256 &vcpu->arch.guest_fpu.state.fxsave,
3257 sizeof(struct fxregs_state));
3258 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3259 XFEATURE_MASK_FPSSE;
3260 }
3261 }
3262
3263 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3264 struct kvm_xsave *guest_xsave)
3265 {
3266 u64 xstate_bv =
3267 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3268
3269 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3270 /*
3271 * Here we allow setting states that are not present in
3272 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3273 * with old userspace.
3274 */
3275 if (xstate_bv & ~kvm_supported_xcr0())
3276 return -EINVAL;
3277 load_xsave(vcpu, (u8 *)guest_xsave->region);
3278 } else {
3279 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3280 return -EINVAL;
3281 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3282 guest_xsave->region, sizeof(struct fxregs_state));
3283 }
3284 return 0;
3285 }
3286
3287 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3288 struct kvm_xcrs *guest_xcrs)
3289 {
3290 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3291 guest_xcrs->nr_xcrs = 0;
3292 return;
3293 }
3294
3295 guest_xcrs->nr_xcrs = 1;
3296 guest_xcrs->flags = 0;
3297 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3298 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3299 }
3300
3301 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3302 struct kvm_xcrs *guest_xcrs)
3303 {
3304 int i, r = 0;
3305
3306 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3307 return -EINVAL;
3308
3309 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3310 return -EINVAL;
3311
3312 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3313 /* Only support XCR0 currently */
3314 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3315 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3316 guest_xcrs->xcrs[i].value);
3317 break;
3318 }
3319 if (r)
3320 r = -EINVAL;
3321 return r;
3322 }
3323
3324 /*
3325 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3326 * stopped by the hypervisor. This function will be called from the host only.
3327 * EINVAL is returned when the host attempts to set the flag for a guest that
3328 * does not support pv clocks.
3329 */
3330 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3331 {
3332 if (!vcpu->arch.pv_time_enabled)
3333 return -EINVAL;
3334 vcpu->arch.pvclock_set_guest_stopped_request = true;
3335 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3336 return 0;
3337 }
3338
3339 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3340 struct kvm_enable_cap *cap)
3341 {
3342 if (cap->flags)
3343 return -EINVAL;
3344
3345 switch (cap->cap) {
3346 case KVM_CAP_HYPERV_SYNIC:
3347 return kvm_hv_activate_synic(vcpu);
3348 default:
3349 return -EINVAL;
3350 }
3351 }
3352
3353 long kvm_arch_vcpu_ioctl(struct file *filp,
3354 unsigned int ioctl, unsigned long arg)
3355 {
3356 struct kvm_vcpu *vcpu = filp->private_data;
3357 void __user *argp = (void __user *)arg;
3358 int r;
3359 union {
3360 struct kvm_lapic_state *lapic;
3361 struct kvm_xsave *xsave;
3362 struct kvm_xcrs *xcrs;
3363 void *buffer;
3364 } u;
3365
3366 u.buffer = NULL;
3367 switch (ioctl) {
3368 case KVM_GET_LAPIC: {
3369 r = -EINVAL;
3370 if (!lapic_in_kernel(vcpu))
3371 goto out;
3372 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3373
3374 r = -ENOMEM;
3375 if (!u.lapic)
3376 goto out;
3377 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3378 if (r)
3379 goto out;
3380 r = -EFAULT;
3381 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3382 goto out;
3383 r = 0;
3384 break;
3385 }
3386 case KVM_SET_LAPIC: {
3387 r = -EINVAL;
3388 if (!lapic_in_kernel(vcpu))
3389 goto out;
3390 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3391 if (IS_ERR(u.lapic))
3392 return PTR_ERR(u.lapic);
3393
3394 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3395 break;
3396 }
3397 case KVM_INTERRUPT: {
3398 struct kvm_interrupt irq;
3399
3400 r = -EFAULT;
3401 if (copy_from_user(&irq, argp, sizeof irq))
3402 goto out;
3403 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3404 break;
3405 }
3406 case KVM_NMI: {
3407 r = kvm_vcpu_ioctl_nmi(vcpu);
3408 break;
3409 }
3410 case KVM_SMI: {
3411 r = kvm_vcpu_ioctl_smi(vcpu);
3412 break;
3413 }
3414 case KVM_SET_CPUID: {
3415 struct kvm_cpuid __user *cpuid_arg = argp;
3416 struct kvm_cpuid cpuid;
3417
3418 r = -EFAULT;
3419 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3420 goto out;
3421 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3422 break;
3423 }
3424 case KVM_SET_CPUID2: {
3425 struct kvm_cpuid2 __user *cpuid_arg = argp;
3426 struct kvm_cpuid2 cpuid;
3427
3428 r = -EFAULT;
3429 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3430 goto out;
3431 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3432 cpuid_arg->entries);
3433 break;
3434 }
3435 case KVM_GET_CPUID2: {
3436 struct kvm_cpuid2 __user *cpuid_arg = argp;
3437 struct kvm_cpuid2 cpuid;
3438
3439 r = -EFAULT;
3440 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3441 goto out;
3442 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3443 cpuid_arg->entries);
3444 if (r)
3445 goto out;
3446 r = -EFAULT;
3447 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3448 goto out;
3449 r = 0;
3450 break;
3451 }
3452 case KVM_GET_MSRS:
3453 r = msr_io(vcpu, argp, do_get_msr, 1);
3454 break;
3455 case KVM_SET_MSRS:
3456 r = msr_io(vcpu, argp, do_set_msr, 0);
3457 break;
3458 case KVM_TPR_ACCESS_REPORTING: {
3459 struct kvm_tpr_access_ctl tac;
3460
3461 r = -EFAULT;
3462 if (copy_from_user(&tac, argp, sizeof tac))
3463 goto out;
3464 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3465 if (r)
3466 goto out;
3467 r = -EFAULT;
3468 if (copy_to_user(argp, &tac, sizeof tac))
3469 goto out;
3470 r = 0;
3471 break;
3472 };
3473 case KVM_SET_VAPIC_ADDR: {
3474 struct kvm_vapic_addr va;
3475 int idx;
3476
3477 r = -EINVAL;
3478 if (!lapic_in_kernel(vcpu))
3479 goto out;
3480 r = -EFAULT;
3481 if (copy_from_user(&va, argp, sizeof va))
3482 goto out;
3483 idx = srcu_read_lock(&vcpu->kvm->srcu);
3484 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3485 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3486 break;
3487 }
3488 case KVM_X86_SETUP_MCE: {
3489 u64 mcg_cap;
3490
3491 r = -EFAULT;
3492 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3493 goto out;
3494 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3495 break;
3496 }
3497 case KVM_X86_SET_MCE: {
3498 struct kvm_x86_mce mce;
3499
3500 r = -EFAULT;
3501 if (copy_from_user(&mce, argp, sizeof mce))
3502 goto out;
3503 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3504 break;
3505 }
3506 case KVM_GET_VCPU_EVENTS: {
3507 struct kvm_vcpu_events events;
3508
3509 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3510
3511 r = -EFAULT;
3512 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3513 break;
3514 r = 0;
3515 break;
3516 }
3517 case KVM_SET_VCPU_EVENTS: {
3518 struct kvm_vcpu_events events;
3519
3520 r = -EFAULT;
3521 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3522 break;
3523
3524 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3525 break;
3526 }
3527 case KVM_GET_DEBUGREGS: {
3528 struct kvm_debugregs dbgregs;
3529
3530 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3531
3532 r = -EFAULT;
3533 if (copy_to_user(argp, &dbgregs,
3534 sizeof(struct kvm_debugregs)))
3535 break;
3536 r = 0;
3537 break;
3538 }
3539 case KVM_SET_DEBUGREGS: {
3540 struct kvm_debugregs dbgregs;
3541
3542 r = -EFAULT;
3543 if (copy_from_user(&dbgregs, argp,
3544 sizeof(struct kvm_debugregs)))
3545 break;
3546
3547 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3548 break;
3549 }
3550 case KVM_GET_XSAVE: {
3551 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3552 r = -ENOMEM;
3553 if (!u.xsave)
3554 break;
3555
3556 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3557
3558 r = -EFAULT;
3559 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3560 break;
3561 r = 0;
3562 break;
3563 }
3564 case KVM_SET_XSAVE: {
3565 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3566 if (IS_ERR(u.xsave))
3567 return PTR_ERR(u.xsave);
3568
3569 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3570 break;
3571 }
3572 case KVM_GET_XCRS: {
3573 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3574 r = -ENOMEM;
3575 if (!u.xcrs)
3576 break;
3577
3578 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3579
3580 r = -EFAULT;
3581 if (copy_to_user(argp, u.xcrs,
3582 sizeof(struct kvm_xcrs)))
3583 break;
3584 r = 0;
3585 break;
3586 }
3587 case KVM_SET_XCRS: {
3588 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3589 if (IS_ERR(u.xcrs))
3590 return PTR_ERR(u.xcrs);
3591
3592 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3593 break;
3594 }
3595 case KVM_SET_TSC_KHZ: {
3596 u32 user_tsc_khz;
3597
3598 r = -EINVAL;
3599 user_tsc_khz = (u32)arg;
3600
3601 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3602 goto out;
3603
3604 if (user_tsc_khz == 0)
3605 user_tsc_khz = tsc_khz;
3606
3607 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3608 r = 0;
3609
3610 goto out;
3611 }
3612 case KVM_GET_TSC_KHZ: {
3613 r = vcpu->arch.virtual_tsc_khz;
3614 goto out;
3615 }
3616 case KVM_KVMCLOCK_CTRL: {
3617 r = kvm_set_guest_paused(vcpu);
3618 goto out;
3619 }
3620 case KVM_ENABLE_CAP: {
3621 struct kvm_enable_cap cap;
3622
3623 r = -EFAULT;
3624 if (copy_from_user(&cap, argp, sizeof(cap)))
3625 goto out;
3626 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3627 break;
3628 }
3629 default:
3630 r = -EINVAL;
3631 }
3632 out:
3633 kfree(u.buffer);
3634 return r;
3635 }
3636
3637 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3638 {
3639 return VM_FAULT_SIGBUS;
3640 }
3641
3642 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3643 {
3644 int ret;
3645
3646 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3647 return -EINVAL;
3648 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3649 return ret;
3650 }
3651
3652 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3653 u64 ident_addr)
3654 {
3655 kvm->arch.ept_identity_map_addr = ident_addr;
3656 return 0;
3657 }
3658
3659 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3660 u32 kvm_nr_mmu_pages)
3661 {
3662 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3663 return -EINVAL;
3664
3665 mutex_lock(&kvm->slots_lock);
3666
3667 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3668 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3669
3670 mutex_unlock(&kvm->slots_lock);
3671 return 0;
3672 }
3673
3674 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3675 {
3676 return kvm->arch.n_max_mmu_pages;
3677 }
3678
3679 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3680 {
3681 int r;
3682
3683 r = 0;
3684 switch (chip->chip_id) {
3685 case KVM_IRQCHIP_PIC_MASTER:
3686 memcpy(&chip->chip.pic,
3687 &pic_irqchip(kvm)->pics[0],
3688 sizeof(struct kvm_pic_state));
3689 break;
3690 case KVM_IRQCHIP_PIC_SLAVE:
3691 memcpy(&chip->chip.pic,
3692 &pic_irqchip(kvm)->pics[1],
3693 sizeof(struct kvm_pic_state));
3694 break;
3695 case KVM_IRQCHIP_IOAPIC:
3696 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3697 break;
3698 default:
3699 r = -EINVAL;
3700 break;
3701 }
3702 return r;
3703 }
3704
3705 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3706 {
3707 int r;
3708
3709 r = 0;
3710 switch (chip->chip_id) {
3711 case KVM_IRQCHIP_PIC_MASTER:
3712 spin_lock(&pic_irqchip(kvm)->lock);
3713 memcpy(&pic_irqchip(kvm)->pics[0],
3714 &chip->chip.pic,
3715 sizeof(struct kvm_pic_state));
3716 spin_unlock(&pic_irqchip(kvm)->lock);
3717 break;
3718 case KVM_IRQCHIP_PIC_SLAVE:
3719 spin_lock(&pic_irqchip(kvm)->lock);
3720 memcpy(&pic_irqchip(kvm)->pics[1],
3721 &chip->chip.pic,
3722 sizeof(struct kvm_pic_state));
3723 spin_unlock(&pic_irqchip(kvm)->lock);
3724 break;
3725 case KVM_IRQCHIP_IOAPIC:
3726 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3727 break;
3728 default:
3729 r = -EINVAL;
3730 break;
3731 }
3732 kvm_pic_update_irq(pic_irqchip(kvm));
3733 return r;
3734 }
3735
3736 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3737 {
3738 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3739
3740 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3741
3742 mutex_lock(&kps->lock);
3743 memcpy(ps, &kps->channels, sizeof(*ps));
3744 mutex_unlock(&kps->lock);
3745 return 0;
3746 }
3747
3748 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3749 {
3750 int i;
3751 struct kvm_pit *pit = kvm->arch.vpit;
3752
3753 mutex_lock(&pit->pit_state.lock);
3754 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3755 for (i = 0; i < 3; i++)
3756 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3757 mutex_unlock(&pit->pit_state.lock);
3758 return 0;
3759 }
3760
3761 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3762 {
3763 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3764 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3765 sizeof(ps->channels));
3766 ps->flags = kvm->arch.vpit->pit_state.flags;
3767 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3768 memset(&ps->reserved, 0, sizeof(ps->reserved));
3769 return 0;
3770 }
3771
3772 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3773 {
3774 int start = 0;
3775 int i;
3776 u32 prev_legacy, cur_legacy;
3777 struct kvm_pit *pit = kvm->arch.vpit;
3778
3779 mutex_lock(&pit->pit_state.lock);
3780 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3781 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3782 if (!prev_legacy && cur_legacy)
3783 start = 1;
3784 memcpy(&pit->pit_state.channels, &ps->channels,
3785 sizeof(pit->pit_state.channels));
3786 pit->pit_state.flags = ps->flags;
3787 for (i = 0; i < 3; i++)
3788 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3789 start && i == 0);
3790 mutex_unlock(&pit->pit_state.lock);
3791 return 0;
3792 }
3793
3794 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3795 struct kvm_reinject_control *control)
3796 {
3797 struct kvm_pit *pit = kvm->arch.vpit;
3798
3799 if (!pit)
3800 return -ENXIO;
3801
3802 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3803 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3804 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3805 */
3806 mutex_lock(&pit->pit_state.lock);
3807 kvm_pit_set_reinject(pit, control->pit_reinject);
3808 mutex_unlock(&pit->pit_state.lock);
3809
3810 return 0;
3811 }
3812
3813 /**
3814 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3815 * @kvm: kvm instance
3816 * @log: slot id and address to which we copy the log
3817 *
3818 * Steps 1-4 below provide general overview of dirty page logging. See
3819 * kvm_get_dirty_log_protect() function description for additional details.
3820 *
3821 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3822 * always flush the TLB (step 4) even if previous step failed and the dirty
3823 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3824 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3825 * writes will be marked dirty for next log read.
3826 *
3827 * 1. Take a snapshot of the bit and clear it if needed.
3828 * 2. Write protect the corresponding page.
3829 * 3. Copy the snapshot to the userspace.
3830 * 4. Flush TLB's if needed.
3831 */
3832 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3833 {
3834 bool is_dirty = false;
3835 int r;
3836
3837 mutex_lock(&kvm->slots_lock);
3838
3839 /*
3840 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3841 */
3842 if (kvm_x86_ops->flush_log_dirty)
3843 kvm_x86_ops->flush_log_dirty(kvm);
3844
3845 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3846
3847 /*
3848 * All the TLBs can be flushed out of mmu lock, see the comments in
3849 * kvm_mmu_slot_remove_write_access().
3850 */
3851 lockdep_assert_held(&kvm->slots_lock);
3852 if (is_dirty)
3853 kvm_flush_remote_tlbs(kvm);
3854
3855 mutex_unlock(&kvm->slots_lock);
3856 return r;
3857 }
3858
3859 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3860 bool line_status)
3861 {
3862 if (!irqchip_in_kernel(kvm))
3863 return -ENXIO;
3864
3865 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3866 irq_event->irq, irq_event->level,
3867 line_status);
3868 return 0;
3869 }
3870
3871 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3872 struct kvm_enable_cap *cap)
3873 {
3874 int r;
3875
3876 if (cap->flags)
3877 return -EINVAL;
3878
3879 switch (cap->cap) {
3880 case KVM_CAP_DISABLE_QUIRKS:
3881 kvm->arch.disabled_quirks = cap->args[0];
3882 r = 0;
3883 break;
3884 case KVM_CAP_SPLIT_IRQCHIP: {
3885 mutex_lock(&kvm->lock);
3886 r = -EINVAL;
3887 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3888 goto split_irqchip_unlock;
3889 r = -EEXIST;
3890 if (irqchip_in_kernel(kvm))
3891 goto split_irqchip_unlock;
3892 if (kvm->created_vcpus)
3893 goto split_irqchip_unlock;
3894 r = kvm_setup_empty_irq_routing(kvm);
3895 if (r)
3896 goto split_irqchip_unlock;
3897 /* Pairs with irqchip_in_kernel. */
3898 smp_wmb();
3899 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
3900 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3901 r = 0;
3902 split_irqchip_unlock:
3903 mutex_unlock(&kvm->lock);
3904 break;
3905 }
3906 case KVM_CAP_X2APIC_API:
3907 r = -EINVAL;
3908 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3909 break;
3910
3911 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3912 kvm->arch.x2apic_format = true;
3913 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3914 kvm->arch.x2apic_broadcast_quirk_disabled = true;
3915
3916 r = 0;
3917 break;
3918 default:
3919 r = -EINVAL;
3920 break;
3921 }
3922 return r;
3923 }
3924
3925 long kvm_arch_vm_ioctl(struct file *filp,
3926 unsigned int ioctl, unsigned long arg)
3927 {
3928 struct kvm *kvm = filp->private_data;
3929 void __user *argp = (void __user *)arg;
3930 int r = -ENOTTY;
3931 /*
3932 * This union makes it completely explicit to gcc-3.x
3933 * that these two variables' stack usage should be
3934 * combined, not added together.
3935 */
3936 union {
3937 struct kvm_pit_state ps;
3938 struct kvm_pit_state2 ps2;
3939 struct kvm_pit_config pit_config;
3940 } u;
3941
3942 switch (ioctl) {
3943 case KVM_SET_TSS_ADDR:
3944 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3945 break;
3946 case KVM_SET_IDENTITY_MAP_ADDR: {
3947 u64 ident_addr;
3948
3949 r = -EFAULT;
3950 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3951 goto out;
3952 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3953 break;
3954 }
3955 case KVM_SET_NR_MMU_PAGES:
3956 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3957 break;
3958 case KVM_GET_NR_MMU_PAGES:
3959 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3960 break;
3961 case KVM_CREATE_IRQCHIP: {
3962 mutex_lock(&kvm->lock);
3963
3964 r = -EEXIST;
3965 if (irqchip_in_kernel(kvm))
3966 goto create_irqchip_unlock;
3967
3968 r = -EINVAL;
3969 if (kvm->created_vcpus)
3970 goto create_irqchip_unlock;
3971
3972 r = kvm_pic_init(kvm);
3973 if (r)
3974 goto create_irqchip_unlock;
3975
3976 r = kvm_ioapic_init(kvm);
3977 if (r) {
3978 mutex_lock(&kvm->slots_lock);
3979 kvm_pic_destroy(kvm);
3980 mutex_unlock(&kvm->slots_lock);
3981 goto create_irqchip_unlock;
3982 }
3983
3984 r = kvm_setup_default_irq_routing(kvm);
3985 if (r) {
3986 mutex_lock(&kvm->slots_lock);
3987 mutex_lock(&kvm->irq_lock);
3988 kvm_ioapic_destroy(kvm);
3989 kvm_pic_destroy(kvm);
3990 mutex_unlock(&kvm->irq_lock);
3991 mutex_unlock(&kvm->slots_lock);
3992 goto create_irqchip_unlock;
3993 }
3994 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
3995 smp_wmb();
3996 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3997 create_irqchip_unlock:
3998 mutex_unlock(&kvm->lock);
3999 break;
4000 }
4001 case KVM_CREATE_PIT:
4002 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4003 goto create_pit;
4004 case KVM_CREATE_PIT2:
4005 r = -EFAULT;
4006 if (copy_from_user(&u.pit_config, argp,
4007 sizeof(struct kvm_pit_config)))
4008 goto out;
4009 create_pit:
4010 mutex_lock(&kvm->lock);
4011 r = -EEXIST;
4012 if (kvm->arch.vpit)
4013 goto create_pit_unlock;
4014 r = -ENOMEM;
4015 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4016 if (kvm->arch.vpit)
4017 r = 0;
4018 create_pit_unlock:
4019 mutex_unlock(&kvm->lock);
4020 break;
4021 case KVM_GET_IRQCHIP: {
4022 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4023 struct kvm_irqchip *chip;
4024
4025 chip = memdup_user(argp, sizeof(*chip));
4026 if (IS_ERR(chip)) {
4027 r = PTR_ERR(chip);
4028 goto out;
4029 }
4030
4031 r = -ENXIO;
4032 if (!irqchip_kernel(kvm))
4033 goto get_irqchip_out;
4034 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4035 if (r)
4036 goto get_irqchip_out;
4037 r = -EFAULT;
4038 if (copy_to_user(argp, chip, sizeof *chip))
4039 goto get_irqchip_out;
4040 r = 0;
4041 get_irqchip_out:
4042 kfree(chip);
4043 break;
4044 }
4045 case KVM_SET_IRQCHIP: {
4046 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4047 struct kvm_irqchip *chip;
4048
4049 chip = memdup_user(argp, sizeof(*chip));
4050 if (IS_ERR(chip)) {
4051 r = PTR_ERR(chip);
4052 goto out;
4053 }
4054
4055 r = -ENXIO;
4056 if (!irqchip_kernel(kvm))
4057 goto set_irqchip_out;
4058 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4059 if (r)
4060 goto set_irqchip_out;
4061 r = 0;
4062 set_irqchip_out:
4063 kfree(chip);
4064 break;
4065 }
4066 case KVM_GET_PIT: {
4067 r = -EFAULT;
4068 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4069 goto out;
4070 r = -ENXIO;
4071 if (!kvm->arch.vpit)
4072 goto out;
4073 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4074 if (r)
4075 goto out;
4076 r = -EFAULT;
4077 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4078 goto out;
4079 r = 0;
4080 break;
4081 }
4082 case KVM_SET_PIT: {
4083 r = -EFAULT;
4084 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4085 goto out;
4086 r = -ENXIO;
4087 if (!kvm->arch.vpit)
4088 goto out;
4089 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4090 break;
4091 }
4092 case KVM_GET_PIT2: {
4093 r = -ENXIO;
4094 if (!kvm->arch.vpit)
4095 goto out;
4096 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4097 if (r)
4098 goto out;
4099 r = -EFAULT;
4100 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4101 goto out;
4102 r = 0;
4103 break;
4104 }
4105 case KVM_SET_PIT2: {
4106 r = -EFAULT;
4107 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4108 goto out;
4109 r = -ENXIO;
4110 if (!kvm->arch.vpit)
4111 goto out;
4112 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4113 break;
4114 }
4115 case KVM_REINJECT_CONTROL: {
4116 struct kvm_reinject_control control;
4117 r = -EFAULT;
4118 if (copy_from_user(&control, argp, sizeof(control)))
4119 goto out;
4120 r = kvm_vm_ioctl_reinject(kvm, &control);
4121 break;
4122 }
4123 case KVM_SET_BOOT_CPU_ID:
4124 r = 0;
4125 mutex_lock(&kvm->lock);
4126 if (kvm->created_vcpus)
4127 r = -EBUSY;
4128 else
4129 kvm->arch.bsp_vcpu_id = arg;
4130 mutex_unlock(&kvm->lock);
4131 break;
4132 case KVM_XEN_HVM_CONFIG: {
4133 r = -EFAULT;
4134 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4135 sizeof(struct kvm_xen_hvm_config)))
4136 goto out;
4137 r = -EINVAL;
4138 if (kvm->arch.xen_hvm_config.flags)
4139 goto out;
4140 r = 0;
4141 break;
4142 }
4143 case KVM_SET_CLOCK: {
4144 struct kvm_clock_data user_ns;
4145 u64 now_ns;
4146
4147 r = -EFAULT;
4148 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4149 goto out;
4150
4151 r = -EINVAL;
4152 if (user_ns.flags)
4153 goto out;
4154
4155 r = 0;
4156 local_irq_disable();
4157 now_ns = __get_kvmclock_ns(kvm);
4158 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4159 local_irq_enable();
4160 kvm_gen_update_masterclock(kvm);
4161 break;
4162 }
4163 case KVM_GET_CLOCK: {
4164 struct kvm_clock_data user_ns;
4165 u64 now_ns;
4166
4167 local_irq_disable();
4168 now_ns = __get_kvmclock_ns(kvm);
4169 user_ns.clock = now_ns;
4170 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4171 local_irq_enable();
4172 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4173
4174 r = -EFAULT;
4175 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4176 goto out;
4177 r = 0;
4178 break;
4179 }
4180 case KVM_ENABLE_CAP: {
4181 struct kvm_enable_cap cap;
4182
4183 r = -EFAULT;
4184 if (copy_from_user(&cap, argp, sizeof(cap)))
4185 goto out;
4186 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4187 break;
4188 }
4189 default:
4190 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4191 }
4192 out:
4193 return r;
4194 }
4195
4196 static void kvm_init_msr_list(void)
4197 {
4198 u32 dummy[2];
4199 unsigned i, j;
4200
4201 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4202 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4203 continue;
4204
4205 /*
4206 * Even MSRs that are valid in the host may not be exposed
4207 * to the guests in some cases.
4208 */
4209 switch (msrs_to_save[i]) {
4210 case MSR_IA32_BNDCFGS:
4211 if (!kvm_x86_ops->mpx_supported())
4212 continue;
4213 break;
4214 case MSR_TSC_AUX:
4215 if (!kvm_x86_ops->rdtscp_supported())
4216 continue;
4217 break;
4218 default:
4219 break;
4220 }
4221
4222 if (j < i)
4223 msrs_to_save[j] = msrs_to_save[i];
4224 j++;
4225 }
4226 num_msrs_to_save = j;
4227
4228 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4229 switch (emulated_msrs[i]) {
4230 case MSR_IA32_SMBASE:
4231 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4232 continue;
4233 break;
4234 default:
4235 break;
4236 }
4237
4238 if (j < i)
4239 emulated_msrs[j] = emulated_msrs[i];
4240 j++;
4241 }
4242 num_emulated_msrs = j;
4243 }
4244
4245 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4246 const void *v)
4247 {
4248 int handled = 0;
4249 int n;
4250
4251 do {
4252 n = min(len, 8);
4253 if (!(lapic_in_kernel(vcpu) &&
4254 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4255 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4256 break;
4257 handled += n;
4258 addr += n;
4259 len -= n;
4260 v += n;
4261 } while (len);
4262
4263 return handled;
4264 }
4265
4266 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4267 {
4268 int handled = 0;
4269 int n;
4270
4271 do {
4272 n = min(len, 8);
4273 if (!(lapic_in_kernel(vcpu) &&
4274 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4275 addr, n, v))
4276 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4277 break;
4278 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4279 handled += n;
4280 addr += n;
4281 len -= n;
4282 v += n;
4283 } while (len);
4284
4285 return handled;
4286 }
4287
4288 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4289 struct kvm_segment *var, int seg)
4290 {
4291 kvm_x86_ops->set_segment(vcpu, var, seg);
4292 }
4293
4294 void kvm_get_segment(struct kvm_vcpu *vcpu,
4295 struct kvm_segment *var, int seg)
4296 {
4297 kvm_x86_ops->get_segment(vcpu, var, seg);
4298 }
4299
4300 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4301 struct x86_exception *exception)
4302 {
4303 gpa_t t_gpa;
4304
4305 BUG_ON(!mmu_is_nested(vcpu));
4306
4307 /* NPT walks are always user-walks */
4308 access |= PFERR_USER_MASK;
4309 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4310
4311 return t_gpa;
4312 }
4313
4314 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4315 struct x86_exception *exception)
4316 {
4317 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4318 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4319 }
4320
4321 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4322 struct x86_exception *exception)
4323 {
4324 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4325 access |= PFERR_FETCH_MASK;
4326 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4327 }
4328
4329 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4330 struct x86_exception *exception)
4331 {
4332 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4333 access |= PFERR_WRITE_MASK;
4334 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4335 }
4336
4337 /* uses this to access any guest's mapped memory without checking CPL */
4338 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4339 struct x86_exception *exception)
4340 {
4341 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4342 }
4343
4344 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4345 struct kvm_vcpu *vcpu, u32 access,
4346 struct x86_exception *exception)
4347 {
4348 void *data = val;
4349 int r = X86EMUL_CONTINUE;
4350
4351 while (bytes) {
4352 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4353 exception);
4354 unsigned offset = addr & (PAGE_SIZE-1);
4355 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4356 int ret;
4357
4358 if (gpa == UNMAPPED_GVA)
4359 return X86EMUL_PROPAGATE_FAULT;
4360 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4361 offset, toread);
4362 if (ret < 0) {
4363 r = X86EMUL_IO_NEEDED;
4364 goto out;
4365 }
4366
4367 bytes -= toread;
4368 data += toread;
4369 addr += toread;
4370 }
4371 out:
4372 return r;
4373 }
4374
4375 /* used for instruction fetching */
4376 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4377 gva_t addr, void *val, unsigned int bytes,
4378 struct x86_exception *exception)
4379 {
4380 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4381 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4382 unsigned offset;
4383 int ret;
4384
4385 /* Inline kvm_read_guest_virt_helper for speed. */
4386 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4387 exception);
4388 if (unlikely(gpa == UNMAPPED_GVA))
4389 return X86EMUL_PROPAGATE_FAULT;
4390
4391 offset = addr & (PAGE_SIZE-1);
4392 if (WARN_ON(offset + bytes > PAGE_SIZE))
4393 bytes = (unsigned)PAGE_SIZE - offset;
4394 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4395 offset, bytes);
4396 if (unlikely(ret < 0))
4397 return X86EMUL_IO_NEEDED;
4398
4399 return X86EMUL_CONTINUE;
4400 }
4401
4402 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4403 gva_t addr, void *val, unsigned int bytes,
4404 struct x86_exception *exception)
4405 {
4406 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4407 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4408
4409 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4410 exception);
4411 }
4412 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4413
4414 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4415 gva_t addr, void *val, unsigned int bytes,
4416 struct x86_exception *exception)
4417 {
4418 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4419 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4420 }
4421
4422 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4423 unsigned long addr, void *val, unsigned int bytes)
4424 {
4425 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4426 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4427
4428 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4429 }
4430
4431 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4432 gva_t addr, void *val,
4433 unsigned int bytes,
4434 struct x86_exception *exception)
4435 {
4436 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4437 void *data = val;
4438 int r = X86EMUL_CONTINUE;
4439
4440 while (bytes) {
4441 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4442 PFERR_WRITE_MASK,
4443 exception);
4444 unsigned offset = addr & (PAGE_SIZE-1);
4445 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4446 int ret;
4447
4448 if (gpa == UNMAPPED_GVA)
4449 return X86EMUL_PROPAGATE_FAULT;
4450 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4451 if (ret < 0) {
4452 r = X86EMUL_IO_NEEDED;
4453 goto out;
4454 }
4455
4456 bytes -= towrite;
4457 data += towrite;
4458 addr += towrite;
4459 }
4460 out:
4461 return r;
4462 }
4463 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4464
4465 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4466 gpa_t gpa, bool write)
4467 {
4468 /* For APIC access vmexit */
4469 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4470 return 1;
4471
4472 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4473 trace_vcpu_match_mmio(gva, gpa, write, true);
4474 return 1;
4475 }
4476
4477 return 0;
4478 }
4479
4480 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4481 gpa_t *gpa, struct x86_exception *exception,
4482 bool write)
4483 {
4484 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4485 | (write ? PFERR_WRITE_MASK : 0);
4486
4487 /*
4488 * currently PKRU is only applied to ept enabled guest so
4489 * there is no pkey in EPT page table for L1 guest or EPT
4490 * shadow page table for L2 guest.
4491 */
4492 if (vcpu_match_mmio_gva(vcpu, gva)
4493 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4494 vcpu->arch.access, 0, access)) {
4495 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4496 (gva & (PAGE_SIZE - 1));
4497 trace_vcpu_match_mmio(gva, *gpa, write, false);
4498 return 1;
4499 }
4500
4501 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4502
4503 if (*gpa == UNMAPPED_GVA)
4504 return -1;
4505
4506 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
4507 }
4508
4509 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4510 const void *val, int bytes)
4511 {
4512 int ret;
4513
4514 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4515 if (ret < 0)
4516 return 0;
4517 kvm_page_track_write(vcpu, gpa, val, bytes);
4518 return 1;
4519 }
4520
4521 struct read_write_emulator_ops {
4522 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4523 int bytes);
4524 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4525 void *val, int bytes);
4526 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4527 int bytes, void *val);
4528 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4529 void *val, int bytes);
4530 bool write;
4531 };
4532
4533 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4534 {
4535 if (vcpu->mmio_read_completed) {
4536 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4537 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4538 vcpu->mmio_read_completed = 0;
4539 return 1;
4540 }
4541
4542 return 0;
4543 }
4544
4545 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4546 void *val, int bytes)
4547 {
4548 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4549 }
4550
4551 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4552 void *val, int bytes)
4553 {
4554 return emulator_write_phys(vcpu, gpa, val, bytes);
4555 }
4556
4557 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4558 {
4559 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4560 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4561 }
4562
4563 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4564 void *val, int bytes)
4565 {
4566 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4567 return X86EMUL_IO_NEEDED;
4568 }
4569
4570 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4571 void *val, int bytes)
4572 {
4573 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4574
4575 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4576 return X86EMUL_CONTINUE;
4577 }
4578
4579 static const struct read_write_emulator_ops read_emultor = {
4580 .read_write_prepare = read_prepare,
4581 .read_write_emulate = read_emulate,
4582 .read_write_mmio = vcpu_mmio_read,
4583 .read_write_exit_mmio = read_exit_mmio,
4584 };
4585
4586 static const struct read_write_emulator_ops write_emultor = {
4587 .read_write_emulate = write_emulate,
4588 .read_write_mmio = write_mmio,
4589 .read_write_exit_mmio = write_exit_mmio,
4590 .write = true,
4591 };
4592
4593 static int emulator_read_write_onepage(unsigned long addr, void *val,
4594 unsigned int bytes,
4595 struct x86_exception *exception,
4596 struct kvm_vcpu *vcpu,
4597 const struct read_write_emulator_ops *ops)
4598 {
4599 gpa_t gpa;
4600 int handled, ret;
4601 bool write = ops->write;
4602 struct kvm_mmio_fragment *frag;
4603 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4604
4605 /*
4606 * If the exit was due to a NPF we may already have a GPA.
4607 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4608 * Note, this cannot be used on string operations since string
4609 * operation using rep will only have the initial GPA from the NPF
4610 * occurred.
4611 */
4612 if (vcpu->arch.gpa_available &&
4613 emulator_can_use_gpa(ctxt) &&
4614 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4615 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4616 gpa = exception->address;
4617 goto mmio;
4618 }
4619
4620 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4621
4622 if (ret < 0)
4623 return X86EMUL_PROPAGATE_FAULT;
4624
4625 /* For APIC access vmexit */
4626 if (ret)
4627 goto mmio;
4628
4629 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4630 return X86EMUL_CONTINUE;
4631
4632 mmio:
4633 /*
4634 * Is this MMIO handled locally?
4635 */
4636 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4637 if (handled == bytes)
4638 return X86EMUL_CONTINUE;
4639
4640 gpa += handled;
4641 bytes -= handled;
4642 val += handled;
4643
4644 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4645 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4646 frag->gpa = gpa;
4647 frag->data = val;
4648 frag->len = bytes;
4649 return X86EMUL_CONTINUE;
4650 }
4651
4652 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4653 unsigned long addr,
4654 void *val, unsigned int bytes,
4655 struct x86_exception *exception,
4656 const struct read_write_emulator_ops *ops)
4657 {
4658 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4659 gpa_t gpa;
4660 int rc;
4661
4662 if (ops->read_write_prepare &&
4663 ops->read_write_prepare(vcpu, val, bytes))
4664 return X86EMUL_CONTINUE;
4665
4666 vcpu->mmio_nr_fragments = 0;
4667
4668 /* Crossing a page boundary? */
4669 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4670 int now;
4671
4672 now = -addr & ~PAGE_MASK;
4673 rc = emulator_read_write_onepage(addr, val, now, exception,
4674 vcpu, ops);
4675
4676 if (rc != X86EMUL_CONTINUE)
4677 return rc;
4678 addr += now;
4679 if (ctxt->mode != X86EMUL_MODE_PROT64)
4680 addr = (u32)addr;
4681 val += now;
4682 bytes -= now;
4683 }
4684
4685 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4686 vcpu, ops);
4687 if (rc != X86EMUL_CONTINUE)
4688 return rc;
4689
4690 if (!vcpu->mmio_nr_fragments)
4691 return rc;
4692
4693 gpa = vcpu->mmio_fragments[0].gpa;
4694
4695 vcpu->mmio_needed = 1;
4696 vcpu->mmio_cur_fragment = 0;
4697
4698 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4699 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4700 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4701 vcpu->run->mmio.phys_addr = gpa;
4702
4703 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4704 }
4705
4706 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4707 unsigned long addr,
4708 void *val,
4709 unsigned int bytes,
4710 struct x86_exception *exception)
4711 {
4712 return emulator_read_write(ctxt, addr, val, bytes,
4713 exception, &read_emultor);
4714 }
4715
4716 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4717 unsigned long addr,
4718 const void *val,
4719 unsigned int bytes,
4720 struct x86_exception *exception)
4721 {
4722 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4723 exception, &write_emultor);
4724 }
4725
4726 #define CMPXCHG_TYPE(t, ptr, old, new) \
4727 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4728
4729 #ifdef CONFIG_X86_64
4730 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4731 #else
4732 # define CMPXCHG64(ptr, old, new) \
4733 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4734 #endif
4735
4736 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4737 unsigned long addr,
4738 const void *old,
4739 const void *new,
4740 unsigned int bytes,
4741 struct x86_exception *exception)
4742 {
4743 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4744 gpa_t gpa;
4745 struct page *page;
4746 char *kaddr;
4747 bool exchanged;
4748
4749 /* guests cmpxchg8b have to be emulated atomically */
4750 if (bytes > 8 || (bytes & (bytes - 1)))
4751 goto emul_write;
4752
4753 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4754
4755 if (gpa == UNMAPPED_GVA ||
4756 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4757 goto emul_write;
4758
4759 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4760 goto emul_write;
4761
4762 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4763 if (is_error_page(page))
4764 goto emul_write;
4765
4766 kaddr = kmap_atomic(page);
4767 kaddr += offset_in_page(gpa);
4768 switch (bytes) {
4769 case 1:
4770 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4771 break;
4772 case 2:
4773 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4774 break;
4775 case 4:
4776 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4777 break;
4778 case 8:
4779 exchanged = CMPXCHG64(kaddr, old, new);
4780 break;
4781 default:
4782 BUG();
4783 }
4784 kunmap_atomic(kaddr);
4785 kvm_release_page_dirty(page);
4786
4787 if (!exchanged)
4788 return X86EMUL_CMPXCHG_FAILED;
4789
4790 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4791 kvm_page_track_write(vcpu, gpa, new, bytes);
4792
4793 return X86EMUL_CONTINUE;
4794
4795 emul_write:
4796 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4797
4798 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4799 }
4800
4801 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4802 {
4803 /* TODO: String I/O for in kernel device */
4804 int r;
4805
4806 if (vcpu->arch.pio.in)
4807 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4808 vcpu->arch.pio.size, pd);
4809 else
4810 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4811 vcpu->arch.pio.port, vcpu->arch.pio.size,
4812 pd);
4813 return r;
4814 }
4815
4816 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4817 unsigned short port, void *val,
4818 unsigned int count, bool in)
4819 {
4820 vcpu->arch.pio.port = port;
4821 vcpu->arch.pio.in = in;
4822 vcpu->arch.pio.count = count;
4823 vcpu->arch.pio.size = size;
4824
4825 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4826 vcpu->arch.pio.count = 0;
4827 return 1;
4828 }
4829
4830 vcpu->run->exit_reason = KVM_EXIT_IO;
4831 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4832 vcpu->run->io.size = size;
4833 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4834 vcpu->run->io.count = count;
4835 vcpu->run->io.port = port;
4836
4837 return 0;
4838 }
4839
4840 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4841 int size, unsigned short port, void *val,
4842 unsigned int count)
4843 {
4844 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4845 int ret;
4846
4847 if (vcpu->arch.pio.count)
4848 goto data_avail;
4849
4850 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4851 if (ret) {
4852 data_avail:
4853 memcpy(val, vcpu->arch.pio_data, size * count);
4854 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4855 vcpu->arch.pio.count = 0;
4856 return 1;
4857 }
4858
4859 return 0;
4860 }
4861
4862 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4863 int size, unsigned short port,
4864 const void *val, unsigned int count)
4865 {
4866 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4867
4868 memcpy(vcpu->arch.pio_data, val, size * count);
4869 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4870 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4871 }
4872
4873 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4874 {
4875 return kvm_x86_ops->get_segment_base(vcpu, seg);
4876 }
4877
4878 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4879 {
4880 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4881 }
4882
4883 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4884 {
4885 if (!need_emulate_wbinvd(vcpu))
4886 return X86EMUL_CONTINUE;
4887
4888 if (kvm_x86_ops->has_wbinvd_exit()) {
4889 int cpu = get_cpu();
4890
4891 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4892 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4893 wbinvd_ipi, NULL, 1);
4894 put_cpu();
4895 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4896 } else
4897 wbinvd();
4898 return X86EMUL_CONTINUE;
4899 }
4900
4901 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4902 {
4903 kvm_emulate_wbinvd_noskip(vcpu);
4904 return kvm_skip_emulated_instruction(vcpu);
4905 }
4906 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4907
4908
4909
4910 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4911 {
4912 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4913 }
4914
4915 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4916 unsigned long *dest)
4917 {
4918 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4919 }
4920
4921 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4922 unsigned long value)
4923 {
4924
4925 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4926 }
4927
4928 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4929 {
4930 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4931 }
4932
4933 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4934 {
4935 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4936 unsigned long value;
4937
4938 switch (cr) {
4939 case 0:
4940 value = kvm_read_cr0(vcpu);
4941 break;
4942 case 2:
4943 value = vcpu->arch.cr2;
4944 break;
4945 case 3:
4946 value = kvm_read_cr3(vcpu);
4947 break;
4948 case 4:
4949 value = kvm_read_cr4(vcpu);
4950 break;
4951 case 8:
4952 value = kvm_get_cr8(vcpu);
4953 break;
4954 default:
4955 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4956 return 0;
4957 }
4958
4959 return value;
4960 }
4961
4962 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4963 {
4964 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4965 int res = 0;
4966
4967 switch (cr) {
4968 case 0:
4969 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4970 break;
4971 case 2:
4972 vcpu->arch.cr2 = val;
4973 break;
4974 case 3:
4975 res = kvm_set_cr3(vcpu, val);
4976 break;
4977 case 4:
4978 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4979 break;
4980 case 8:
4981 res = kvm_set_cr8(vcpu, val);
4982 break;
4983 default:
4984 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4985 res = -1;
4986 }
4987
4988 return res;
4989 }
4990
4991 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4992 {
4993 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4994 }
4995
4996 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4997 {
4998 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4999 }
5000
5001 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5002 {
5003 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5004 }
5005
5006 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5007 {
5008 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5009 }
5010
5011 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5012 {
5013 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5014 }
5015
5016 static unsigned long emulator_get_cached_segment_base(
5017 struct x86_emulate_ctxt *ctxt, int seg)
5018 {
5019 return get_segment_base(emul_to_vcpu(ctxt), seg);
5020 }
5021
5022 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5023 struct desc_struct *desc, u32 *base3,
5024 int seg)
5025 {
5026 struct kvm_segment var;
5027
5028 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5029 *selector = var.selector;
5030
5031 if (var.unusable) {
5032 memset(desc, 0, sizeof(*desc));
5033 return false;
5034 }
5035
5036 if (var.g)
5037 var.limit >>= 12;
5038 set_desc_limit(desc, var.limit);
5039 set_desc_base(desc, (unsigned long)var.base);
5040 #ifdef CONFIG_X86_64
5041 if (base3)
5042 *base3 = var.base >> 32;
5043 #endif
5044 desc->type = var.type;
5045 desc->s = var.s;
5046 desc->dpl = var.dpl;
5047 desc->p = var.present;
5048 desc->avl = var.avl;
5049 desc->l = var.l;
5050 desc->d = var.db;
5051 desc->g = var.g;
5052
5053 return true;
5054 }
5055
5056 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5057 struct desc_struct *desc, u32 base3,
5058 int seg)
5059 {
5060 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5061 struct kvm_segment var;
5062
5063 var.selector = selector;
5064 var.base = get_desc_base(desc);
5065 #ifdef CONFIG_X86_64
5066 var.base |= ((u64)base3) << 32;
5067 #endif
5068 var.limit = get_desc_limit(desc);
5069 if (desc->g)
5070 var.limit = (var.limit << 12) | 0xfff;
5071 var.type = desc->type;
5072 var.dpl = desc->dpl;
5073 var.db = desc->d;
5074 var.s = desc->s;
5075 var.l = desc->l;
5076 var.g = desc->g;
5077 var.avl = desc->avl;
5078 var.present = desc->p;
5079 var.unusable = !var.present;
5080 var.padding = 0;
5081
5082 kvm_set_segment(vcpu, &var, seg);
5083 return;
5084 }
5085
5086 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5087 u32 msr_index, u64 *pdata)
5088 {
5089 struct msr_data msr;
5090 int r;
5091
5092 msr.index = msr_index;
5093 msr.host_initiated = false;
5094 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5095 if (r)
5096 return r;
5097
5098 *pdata = msr.data;
5099 return 0;
5100 }
5101
5102 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5103 u32 msr_index, u64 data)
5104 {
5105 struct msr_data msr;
5106
5107 msr.data = data;
5108 msr.index = msr_index;
5109 msr.host_initiated = false;
5110 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5111 }
5112
5113 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5114 {
5115 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5116
5117 return vcpu->arch.smbase;
5118 }
5119
5120 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5121 {
5122 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5123
5124 vcpu->arch.smbase = smbase;
5125 }
5126
5127 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5128 u32 pmc)
5129 {
5130 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5131 }
5132
5133 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5134 u32 pmc, u64 *pdata)
5135 {
5136 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5137 }
5138
5139 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5140 {
5141 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5142 }
5143
5144 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5145 {
5146 preempt_disable();
5147 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5148 }
5149
5150 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5151 {
5152 preempt_enable();
5153 }
5154
5155 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5156 struct x86_instruction_info *info,
5157 enum x86_intercept_stage stage)
5158 {
5159 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5160 }
5161
5162 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5163 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5164 {
5165 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5166 }
5167
5168 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5169 {
5170 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5171 }
5172
5173 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5174 {
5175 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5176 }
5177
5178 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5179 {
5180 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5181 }
5182
5183 static const struct x86_emulate_ops emulate_ops = {
5184 .read_gpr = emulator_read_gpr,
5185 .write_gpr = emulator_write_gpr,
5186 .read_std = kvm_read_guest_virt_system,
5187 .write_std = kvm_write_guest_virt_system,
5188 .read_phys = kvm_read_guest_phys_system,
5189 .fetch = kvm_fetch_guest_virt,
5190 .read_emulated = emulator_read_emulated,
5191 .write_emulated = emulator_write_emulated,
5192 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5193 .invlpg = emulator_invlpg,
5194 .pio_in_emulated = emulator_pio_in_emulated,
5195 .pio_out_emulated = emulator_pio_out_emulated,
5196 .get_segment = emulator_get_segment,
5197 .set_segment = emulator_set_segment,
5198 .get_cached_segment_base = emulator_get_cached_segment_base,
5199 .get_gdt = emulator_get_gdt,
5200 .get_idt = emulator_get_idt,
5201 .set_gdt = emulator_set_gdt,
5202 .set_idt = emulator_set_idt,
5203 .get_cr = emulator_get_cr,
5204 .set_cr = emulator_set_cr,
5205 .cpl = emulator_get_cpl,
5206 .get_dr = emulator_get_dr,
5207 .set_dr = emulator_set_dr,
5208 .get_smbase = emulator_get_smbase,
5209 .set_smbase = emulator_set_smbase,
5210 .set_msr = emulator_set_msr,
5211 .get_msr = emulator_get_msr,
5212 .check_pmc = emulator_check_pmc,
5213 .read_pmc = emulator_read_pmc,
5214 .halt = emulator_halt,
5215 .wbinvd = emulator_wbinvd,
5216 .fix_hypercall = emulator_fix_hypercall,
5217 .get_fpu = emulator_get_fpu,
5218 .put_fpu = emulator_put_fpu,
5219 .intercept = emulator_intercept,
5220 .get_cpuid = emulator_get_cpuid,
5221 .set_nmi_mask = emulator_set_nmi_mask,
5222 };
5223
5224 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5225 {
5226 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5227 /*
5228 * an sti; sti; sequence only disable interrupts for the first
5229 * instruction. So, if the last instruction, be it emulated or
5230 * not, left the system with the INT_STI flag enabled, it
5231 * means that the last instruction is an sti. We should not
5232 * leave the flag on in this case. The same goes for mov ss
5233 */
5234 if (int_shadow & mask)
5235 mask = 0;
5236 if (unlikely(int_shadow || mask)) {
5237 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5238 if (!mask)
5239 kvm_make_request(KVM_REQ_EVENT, vcpu);
5240 }
5241 }
5242
5243 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5244 {
5245 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5246 if (ctxt->exception.vector == PF_VECTOR)
5247 return kvm_propagate_fault(vcpu, &ctxt->exception);
5248
5249 if (ctxt->exception.error_code_valid)
5250 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5251 ctxt->exception.error_code);
5252 else
5253 kvm_queue_exception(vcpu, ctxt->exception.vector);
5254 return false;
5255 }
5256
5257 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5258 {
5259 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5260 int cs_db, cs_l;
5261
5262 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5263
5264 ctxt->eflags = kvm_get_rflags(vcpu);
5265 ctxt->eip = kvm_rip_read(vcpu);
5266 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5267 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5268 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5269 cs_db ? X86EMUL_MODE_PROT32 :
5270 X86EMUL_MODE_PROT16;
5271 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5272 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5273 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5274 ctxt->emul_flags = vcpu->arch.hflags;
5275
5276 init_decode_cache(ctxt);
5277 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5278 }
5279
5280 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5281 {
5282 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5283 int ret;
5284
5285 init_emulate_ctxt(vcpu);
5286
5287 ctxt->op_bytes = 2;
5288 ctxt->ad_bytes = 2;
5289 ctxt->_eip = ctxt->eip + inc_eip;
5290 ret = emulate_int_real(ctxt, irq);
5291
5292 if (ret != X86EMUL_CONTINUE)
5293 return EMULATE_FAIL;
5294
5295 ctxt->eip = ctxt->_eip;
5296 kvm_rip_write(vcpu, ctxt->eip);
5297 kvm_set_rflags(vcpu, ctxt->eflags);
5298
5299 if (irq == NMI_VECTOR)
5300 vcpu->arch.nmi_pending = 0;
5301 else
5302 vcpu->arch.interrupt.pending = false;
5303
5304 return EMULATE_DONE;
5305 }
5306 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5307
5308 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5309 {
5310 int r = EMULATE_DONE;
5311
5312 ++vcpu->stat.insn_emulation_fail;
5313 trace_kvm_emulate_insn_failed(vcpu);
5314 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5315 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5316 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5317 vcpu->run->internal.ndata = 0;
5318 r = EMULATE_FAIL;
5319 }
5320 kvm_queue_exception(vcpu, UD_VECTOR);
5321
5322 return r;
5323 }
5324
5325 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5326 bool write_fault_to_shadow_pgtable,
5327 int emulation_type)
5328 {
5329 gpa_t gpa = cr2;
5330 kvm_pfn_t pfn;
5331
5332 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5333 return false;
5334
5335 if (!vcpu->arch.mmu.direct_map) {
5336 /*
5337 * Write permission should be allowed since only
5338 * write access need to be emulated.
5339 */
5340 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5341
5342 /*
5343 * If the mapping is invalid in guest, let cpu retry
5344 * it to generate fault.
5345 */
5346 if (gpa == UNMAPPED_GVA)
5347 return true;
5348 }
5349
5350 /*
5351 * Do not retry the unhandleable instruction if it faults on the
5352 * readonly host memory, otherwise it will goto a infinite loop:
5353 * retry instruction -> write #PF -> emulation fail -> retry
5354 * instruction -> ...
5355 */
5356 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5357
5358 /*
5359 * If the instruction failed on the error pfn, it can not be fixed,
5360 * report the error to userspace.
5361 */
5362 if (is_error_noslot_pfn(pfn))
5363 return false;
5364
5365 kvm_release_pfn_clean(pfn);
5366
5367 /* The instructions are well-emulated on direct mmu. */
5368 if (vcpu->arch.mmu.direct_map) {
5369 unsigned int indirect_shadow_pages;
5370
5371 spin_lock(&vcpu->kvm->mmu_lock);
5372 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5373 spin_unlock(&vcpu->kvm->mmu_lock);
5374
5375 if (indirect_shadow_pages)
5376 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5377
5378 return true;
5379 }
5380
5381 /*
5382 * if emulation was due to access to shadowed page table
5383 * and it failed try to unshadow page and re-enter the
5384 * guest to let CPU execute the instruction.
5385 */
5386 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5387
5388 /*
5389 * If the access faults on its page table, it can not
5390 * be fixed by unprotecting shadow page and it should
5391 * be reported to userspace.
5392 */
5393 return !write_fault_to_shadow_pgtable;
5394 }
5395
5396 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5397 unsigned long cr2, int emulation_type)
5398 {
5399 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5400 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5401
5402 last_retry_eip = vcpu->arch.last_retry_eip;
5403 last_retry_addr = vcpu->arch.last_retry_addr;
5404
5405 /*
5406 * If the emulation is caused by #PF and it is non-page_table
5407 * writing instruction, it means the VM-EXIT is caused by shadow
5408 * page protected, we can zap the shadow page and retry this
5409 * instruction directly.
5410 *
5411 * Note: if the guest uses a non-page-table modifying instruction
5412 * on the PDE that points to the instruction, then we will unmap
5413 * the instruction and go to an infinite loop. So, we cache the
5414 * last retried eip and the last fault address, if we meet the eip
5415 * and the address again, we can break out of the potential infinite
5416 * loop.
5417 */
5418 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5419
5420 if (!(emulation_type & EMULTYPE_RETRY))
5421 return false;
5422
5423 if (x86_page_table_writing_insn(ctxt))
5424 return false;
5425
5426 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5427 return false;
5428
5429 vcpu->arch.last_retry_eip = ctxt->eip;
5430 vcpu->arch.last_retry_addr = cr2;
5431
5432 if (!vcpu->arch.mmu.direct_map)
5433 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5434
5435 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5436
5437 return true;
5438 }
5439
5440 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5441 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5442
5443 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5444 {
5445 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5446 /* This is a good place to trace that we are exiting SMM. */
5447 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5448
5449 /* Process a latched INIT or SMI, if any. */
5450 kvm_make_request(KVM_REQ_EVENT, vcpu);
5451 }
5452
5453 kvm_mmu_reset_context(vcpu);
5454 }
5455
5456 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5457 {
5458 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5459
5460 vcpu->arch.hflags = emul_flags;
5461
5462 if (changed & HF_SMM_MASK)
5463 kvm_smm_changed(vcpu);
5464 }
5465
5466 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5467 unsigned long *db)
5468 {
5469 u32 dr6 = 0;
5470 int i;
5471 u32 enable, rwlen;
5472
5473 enable = dr7;
5474 rwlen = dr7 >> 16;
5475 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5476 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5477 dr6 |= (1 << i);
5478 return dr6;
5479 }
5480
5481 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5482 {
5483 struct kvm_run *kvm_run = vcpu->run;
5484
5485 /*
5486 * rflags is the old, "raw" value of the flags. The new value has
5487 * not been saved yet.
5488 *
5489 * This is correct even for TF set by the guest, because "the
5490 * processor will not generate this exception after the instruction
5491 * that sets the TF flag".
5492 */
5493 if (unlikely(rflags & X86_EFLAGS_TF)) {
5494 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5495 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5496 DR6_RTM;
5497 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5498 kvm_run->debug.arch.exception = DB_VECTOR;
5499 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5500 *r = EMULATE_USER_EXIT;
5501 } else {
5502 /*
5503 * "Certain debug exceptions may clear bit 0-3. The
5504 * remaining contents of the DR6 register are never
5505 * cleared by the processor".
5506 */
5507 vcpu->arch.dr6 &= ~15;
5508 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5509 kvm_queue_exception(vcpu, DB_VECTOR);
5510 }
5511 }
5512 }
5513
5514 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5515 {
5516 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5517 int r = EMULATE_DONE;
5518
5519 kvm_x86_ops->skip_emulated_instruction(vcpu);
5520 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5521 return r == EMULATE_DONE;
5522 }
5523 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5524
5525 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5526 {
5527 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5528 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5529 struct kvm_run *kvm_run = vcpu->run;
5530 unsigned long eip = kvm_get_linear_rip(vcpu);
5531 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5532 vcpu->arch.guest_debug_dr7,
5533 vcpu->arch.eff_db);
5534
5535 if (dr6 != 0) {
5536 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5537 kvm_run->debug.arch.pc = eip;
5538 kvm_run->debug.arch.exception = DB_VECTOR;
5539 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5540 *r = EMULATE_USER_EXIT;
5541 return true;
5542 }
5543 }
5544
5545 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5546 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5547 unsigned long eip = kvm_get_linear_rip(vcpu);
5548 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5549 vcpu->arch.dr7,
5550 vcpu->arch.db);
5551
5552 if (dr6 != 0) {
5553 vcpu->arch.dr6 &= ~15;
5554 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5555 kvm_queue_exception(vcpu, DB_VECTOR);
5556 *r = EMULATE_DONE;
5557 return true;
5558 }
5559 }
5560
5561 return false;
5562 }
5563
5564 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5565 unsigned long cr2,
5566 int emulation_type,
5567 void *insn,
5568 int insn_len)
5569 {
5570 int r;
5571 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5572 bool writeback = true;
5573 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5574
5575 /*
5576 * Clear write_fault_to_shadow_pgtable here to ensure it is
5577 * never reused.
5578 */
5579 vcpu->arch.write_fault_to_shadow_pgtable = false;
5580 kvm_clear_exception_queue(vcpu);
5581
5582 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5583 init_emulate_ctxt(vcpu);
5584
5585 /*
5586 * We will reenter on the same instruction since
5587 * we do not set complete_userspace_io. This does not
5588 * handle watchpoints yet, those would be handled in
5589 * the emulate_ops.
5590 */
5591 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5592 return r;
5593
5594 ctxt->interruptibility = 0;
5595 ctxt->have_exception = false;
5596 ctxt->exception.vector = -1;
5597 ctxt->perm_ok = false;
5598
5599 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5600
5601 r = x86_decode_insn(ctxt, insn, insn_len);
5602
5603 trace_kvm_emulate_insn_start(vcpu);
5604 ++vcpu->stat.insn_emulation;
5605 if (r != EMULATION_OK) {
5606 if (emulation_type & EMULTYPE_TRAP_UD)
5607 return EMULATE_FAIL;
5608 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5609 emulation_type))
5610 return EMULATE_DONE;
5611 if (emulation_type & EMULTYPE_SKIP)
5612 return EMULATE_FAIL;
5613 return handle_emulation_failure(vcpu);
5614 }
5615 }
5616
5617 if (emulation_type & EMULTYPE_SKIP) {
5618 kvm_rip_write(vcpu, ctxt->_eip);
5619 if (ctxt->eflags & X86_EFLAGS_RF)
5620 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5621 return EMULATE_DONE;
5622 }
5623
5624 if (retry_instruction(ctxt, cr2, emulation_type))
5625 return EMULATE_DONE;
5626
5627 /* this is needed for vmware backdoor interface to work since it
5628 changes registers values during IO operation */
5629 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5630 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5631 emulator_invalidate_register_cache(ctxt);
5632 }
5633
5634 restart:
5635 /* Save the faulting GPA (cr2) in the address field */
5636 ctxt->exception.address = cr2;
5637
5638 r = x86_emulate_insn(ctxt);
5639
5640 if (r == EMULATION_INTERCEPTED)
5641 return EMULATE_DONE;
5642
5643 if (r == EMULATION_FAILED) {
5644 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5645 emulation_type))
5646 return EMULATE_DONE;
5647
5648 return handle_emulation_failure(vcpu);
5649 }
5650
5651 if (ctxt->have_exception) {
5652 r = EMULATE_DONE;
5653 if (inject_emulated_exception(vcpu))
5654 return r;
5655 } else if (vcpu->arch.pio.count) {
5656 if (!vcpu->arch.pio.in) {
5657 /* FIXME: return into emulator if single-stepping. */
5658 vcpu->arch.pio.count = 0;
5659 } else {
5660 writeback = false;
5661 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5662 }
5663 r = EMULATE_USER_EXIT;
5664 } else if (vcpu->mmio_needed) {
5665 if (!vcpu->mmio_is_write)
5666 writeback = false;
5667 r = EMULATE_USER_EXIT;
5668 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5669 } else if (r == EMULATION_RESTART)
5670 goto restart;
5671 else
5672 r = EMULATE_DONE;
5673
5674 if (writeback) {
5675 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5676 toggle_interruptibility(vcpu, ctxt->interruptibility);
5677 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5678 if (vcpu->arch.hflags != ctxt->emul_flags)
5679 kvm_set_hflags(vcpu, ctxt->emul_flags);
5680 kvm_rip_write(vcpu, ctxt->eip);
5681 if (r == EMULATE_DONE)
5682 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5683 if (!ctxt->have_exception ||
5684 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5685 __kvm_set_rflags(vcpu, ctxt->eflags);
5686
5687 /*
5688 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5689 * do nothing, and it will be requested again as soon as
5690 * the shadow expires. But we still need to check here,
5691 * because POPF has no interrupt shadow.
5692 */
5693 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5694 kvm_make_request(KVM_REQ_EVENT, vcpu);
5695 } else
5696 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5697
5698 return r;
5699 }
5700 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5701
5702 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5703 {
5704 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5705 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5706 size, port, &val, 1);
5707 /* do not return to emulator after return from userspace */
5708 vcpu->arch.pio.count = 0;
5709 return ret;
5710 }
5711 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5712
5713 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5714 {
5715 unsigned long val;
5716
5717 /* We should only ever be called with arch.pio.count equal to 1 */
5718 BUG_ON(vcpu->arch.pio.count != 1);
5719
5720 /* For size less than 4 we merge, else we zero extend */
5721 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5722 : 0;
5723
5724 /*
5725 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5726 * the copy and tracing
5727 */
5728 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5729 vcpu->arch.pio.port, &val, 1);
5730 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5731
5732 return 1;
5733 }
5734
5735 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5736 {
5737 unsigned long val;
5738 int ret;
5739
5740 /* For size less than 4 we merge, else we zero extend */
5741 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5742
5743 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5744 &val, 1);
5745 if (ret) {
5746 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5747 return ret;
5748 }
5749
5750 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5751
5752 return 0;
5753 }
5754 EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5755
5756 static int kvmclock_cpu_down_prep(unsigned int cpu)
5757 {
5758 __this_cpu_write(cpu_tsc_khz, 0);
5759 return 0;
5760 }
5761
5762 static void tsc_khz_changed(void *data)
5763 {
5764 struct cpufreq_freqs *freq = data;
5765 unsigned long khz = 0;
5766
5767 if (data)
5768 khz = freq->new;
5769 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5770 khz = cpufreq_quick_get(raw_smp_processor_id());
5771 if (!khz)
5772 khz = tsc_khz;
5773 __this_cpu_write(cpu_tsc_khz, khz);
5774 }
5775
5776 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5777 void *data)
5778 {
5779 struct cpufreq_freqs *freq = data;
5780 struct kvm *kvm;
5781 struct kvm_vcpu *vcpu;
5782 int i, send_ipi = 0;
5783
5784 /*
5785 * We allow guests to temporarily run on slowing clocks,
5786 * provided we notify them after, or to run on accelerating
5787 * clocks, provided we notify them before. Thus time never
5788 * goes backwards.
5789 *
5790 * However, we have a problem. We can't atomically update
5791 * the frequency of a given CPU from this function; it is
5792 * merely a notifier, which can be called from any CPU.
5793 * Changing the TSC frequency at arbitrary points in time
5794 * requires a recomputation of local variables related to
5795 * the TSC for each VCPU. We must flag these local variables
5796 * to be updated and be sure the update takes place with the
5797 * new frequency before any guests proceed.
5798 *
5799 * Unfortunately, the combination of hotplug CPU and frequency
5800 * change creates an intractable locking scenario; the order
5801 * of when these callouts happen is undefined with respect to
5802 * CPU hotplug, and they can race with each other. As such,
5803 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5804 * undefined; you can actually have a CPU frequency change take
5805 * place in between the computation of X and the setting of the
5806 * variable. To protect against this problem, all updates of
5807 * the per_cpu tsc_khz variable are done in an interrupt
5808 * protected IPI, and all callers wishing to update the value
5809 * must wait for a synchronous IPI to complete (which is trivial
5810 * if the caller is on the CPU already). This establishes the
5811 * necessary total order on variable updates.
5812 *
5813 * Note that because a guest time update may take place
5814 * anytime after the setting of the VCPU's request bit, the
5815 * correct TSC value must be set before the request. However,
5816 * to ensure the update actually makes it to any guest which
5817 * starts running in hardware virtualization between the set
5818 * and the acquisition of the spinlock, we must also ping the
5819 * CPU after setting the request bit.
5820 *
5821 */
5822
5823 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5824 return 0;
5825 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5826 return 0;
5827
5828 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5829
5830 spin_lock(&kvm_lock);
5831 list_for_each_entry(kvm, &vm_list, vm_list) {
5832 kvm_for_each_vcpu(i, vcpu, kvm) {
5833 if (vcpu->cpu != freq->cpu)
5834 continue;
5835 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5836 if (vcpu->cpu != smp_processor_id())
5837 send_ipi = 1;
5838 }
5839 }
5840 spin_unlock(&kvm_lock);
5841
5842 if (freq->old < freq->new && send_ipi) {
5843 /*
5844 * We upscale the frequency. Must make the guest
5845 * doesn't see old kvmclock values while running with
5846 * the new frequency, otherwise we risk the guest sees
5847 * time go backwards.
5848 *
5849 * In case we update the frequency for another cpu
5850 * (which might be in guest context) send an interrupt
5851 * to kick the cpu out of guest context. Next time
5852 * guest context is entered kvmclock will be updated,
5853 * so the guest will not see stale values.
5854 */
5855 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5856 }
5857 return 0;
5858 }
5859
5860 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5861 .notifier_call = kvmclock_cpufreq_notifier
5862 };
5863
5864 static int kvmclock_cpu_online(unsigned int cpu)
5865 {
5866 tsc_khz_changed(NULL);
5867 return 0;
5868 }
5869
5870 static void kvm_timer_init(void)
5871 {
5872 max_tsc_khz = tsc_khz;
5873
5874 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5875 #ifdef CONFIG_CPU_FREQ
5876 struct cpufreq_policy policy;
5877 int cpu;
5878
5879 memset(&policy, 0, sizeof(policy));
5880 cpu = get_cpu();
5881 cpufreq_get_policy(&policy, cpu);
5882 if (policy.cpuinfo.max_freq)
5883 max_tsc_khz = policy.cpuinfo.max_freq;
5884 put_cpu();
5885 #endif
5886 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5887 CPUFREQ_TRANSITION_NOTIFIER);
5888 }
5889 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5890
5891 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
5892 kvmclock_cpu_online, kvmclock_cpu_down_prep);
5893 }
5894
5895 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5896
5897 int kvm_is_in_guest(void)
5898 {
5899 return __this_cpu_read(current_vcpu) != NULL;
5900 }
5901
5902 static int kvm_is_user_mode(void)
5903 {
5904 int user_mode = 3;
5905
5906 if (__this_cpu_read(current_vcpu))
5907 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5908
5909 return user_mode != 0;
5910 }
5911
5912 static unsigned long kvm_get_guest_ip(void)
5913 {
5914 unsigned long ip = 0;
5915
5916 if (__this_cpu_read(current_vcpu))
5917 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5918
5919 return ip;
5920 }
5921
5922 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5923 .is_in_guest = kvm_is_in_guest,
5924 .is_user_mode = kvm_is_user_mode,
5925 .get_guest_ip = kvm_get_guest_ip,
5926 };
5927
5928 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5929 {
5930 __this_cpu_write(current_vcpu, vcpu);
5931 }
5932 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5933
5934 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5935 {
5936 __this_cpu_write(current_vcpu, NULL);
5937 }
5938 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5939
5940 static void kvm_set_mmio_spte_mask(void)
5941 {
5942 u64 mask;
5943 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5944
5945 /*
5946 * Set the reserved bits and the present bit of an paging-structure
5947 * entry to generate page fault with PFER.RSV = 1.
5948 */
5949 /* Mask the reserved physical address bits. */
5950 mask = rsvd_bits(maxphyaddr, 51);
5951
5952 /* Bit 62 is always reserved for 32bit host. */
5953 mask |= 0x3ull << 62;
5954
5955 /* Set the present bit. */
5956 mask |= 1ull;
5957
5958 #ifdef CONFIG_X86_64
5959 /*
5960 * If reserved bit is not supported, clear the present bit to disable
5961 * mmio page fault.
5962 */
5963 if (maxphyaddr == 52)
5964 mask &= ~1ull;
5965 #endif
5966
5967 kvm_mmu_set_mmio_spte_mask(mask);
5968 }
5969
5970 #ifdef CONFIG_X86_64
5971 static void pvclock_gtod_update_fn(struct work_struct *work)
5972 {
5973 struct kvm *kvm;
5974
5975 struct kvm_vcpu *vcpu;
5976 int i;
5977
5978 spin_lock(&kvm_lock);
5979 list_for_each_entry(kvm, &vm_list, vm_list)
5980 kvm_for_each_vcpu(i, vcpu, kvm)
5981 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5982 atomic_set(&kvm_guest_has_master_clock, 0);
5983 spin_unlock(&kvm_lock);
5984 }
5985
5986 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5987
5988 /*
5989 * Notification about pvclock gtod data update.
5990 */
5991 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5992 void *priv)
5993 {
5994 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5995 struct timekeeper *tk = priv;
5996
5997 update_pvclock_gtod(tk);
5998
5999 /* disable master clock if host does not trust, or does not
6000 * use, TSC clocksource
6001 */
6002 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6003 atomic_read(&kvm_guest_has_master_clock) != 0)
6004 queue_work(system_long_wq, &pvclock_gtod_work);
6005
6006 return 0;
6007 }
6008
6009 static struct notifier_block pvclock_gtod_notifier = {
6010 .notifier_call = pvclock_gtod_notify,
6011 };
6012 #endif
6013
6014 int kvm_arch_init(void *opaque)
6015 {
6016 int r;
6017 struct kvm_x86_ops *ops = opaque;
6018
6019 if (kvm_x86_ops) {
6020 printk(KERN_ERR "kvm: already loaded the other module\n");
6021 r = -EEXIST;
6022 goto out;
6023 }
6024
6025 if (!ops->cpu_has_kvm_support()) {
6026 printk(KERN_ERR "kvm: no hardware support\n");
6027 r = -EOPNOTSUPP;
6028 goto out;
6029 }
6030 if (ops->disabled_by_bios()) {
6031 printk(KERN_ERR "kvm: disabled by bios\n");
6032 r = -EOPNOTSUPP;
6033 goto out;
6034 }
6035
6036 r = -ENOMEM;
6037 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6038 if (!shared_msrs) {
6039 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6040 goto out;
6041 }
6042
6043 r = kvm_mmu_module_init();
6044 if (r)
6045 goto out_free_percpu;
6046
6047 kvm_set_mmio_spte_mask();
6048
6049 kvm_x86_ops = ops;
6050
6051 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6052 PT_DIRTY_MASK, PT64_NX_MASK, 0,
6053 PT_PRESENT_MASK, 0);
6054 kvm_timer_init();
6055
6056 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6057
6058 if (boot_cpu_has(X86_FEATURE_XSAVE))
6059 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6060
6061 kvm_lapic_init();
6062 #ifdef CONFIG_X86_64
6063 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6064 #endif
6065
6066 return 0;
6067
6068 out_free_percpu:
6069 free_percpu(shared_msrs);
6070 out:
6071 return r;
6072 }
6073
6074 void kvm_arch_exit(void)
6075 {
6076 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6077
6078 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6079 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6080 CPUFREQ_TRANSITION_NOTIFIER);
6081 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6082 #ifdef CONFIG_X86_64
6083 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6084 #endif
6085 kvm_x86_ops = NULL;
6086 kvm_mmu_module_exit();
6087 free_percpu(shared_msrs);
6088 }
6089
6090 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6091 {
6092 ++vcpu->stat.halt_exits;
6093 if (lapic_in_kernel(vcpu)) {
6094 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6095 return 1;
6096 } else {
6097 vcpu->run->exit_reason = KVM_EXIT_HLT;
6098 return 0;
6099 }
6100 }
6101 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6102
6103 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6104 {
6105 int ret = kvm_skip_emulated_instruction(vcpu);
6106 /*
6107 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6108 * KVM_EXIT_DEBUG here.
6109 */
6110 return kvm_vcpu_halt(vcpu) && ret;
6111 }
6112 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6113
6114 /*
6115 * kvm_pv_kick_cpu_op: Kick a vcpu.
6116 *
6117 * @apicid - apicid of vcpu to be kicked.
6118 */
6119 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6120 {
6121 struct kvm_lapic_irq lapic_irq;
6122
6123 lapic_irq.shorthand = 0;
6124 lapic_irq.dest_mode = 0;
6125 lapic_irq.dest_id = apicid;
6126 lapic_irq.msi_redir_hint = false;
6127
6128 lapic_irq.delivery_mode = APIC_DM_REMRD;
6129 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6130 }
6131
6132 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6133 {
6134 vcpu->arch.apicv_active = false;
6135 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6136 }
6137
6138 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6139 {
6140 unsigned long nr, a0, a1, a2, a3, ret;
6141 int op_64_bit, r;
6142
6143 r = kvm_skip_emulated_instruction(vcpu);
6144
6145 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6146 return kvm_hv_hypercall(vcpu);
6147
6148 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6149 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6150 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6151 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6152 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6153
6154 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6155
6156 op_64_bit = is_64_bit_mode(vcpu);
6157 if (!op_64_bit) {
6158 nr &= 0xFFFFFFFF;
6159 a0 &= 0xFFFFFFFF;
6160 a1 &= 0xFFFFFFFF;
6161 a2 &= 0xFFFFFFFF;
6162 a3 &= 0xFFFFFFFF;
6163 }
6164
6165 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6166 ret = -KVM_EPERM;
6167 goto out;
6168 }
6169
6170 switch (nr) {
6171 case KVM_HC_VAPIC_POLL_IRQ:
6172 ret = 0;
6173 break;
6174 case KVM_HC_KICK_CPU:
6175 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6176 ret = 0;
6177 break;
6178 default:
6179 ret = -KVM_ENOSYS;
6180 break;
6181 }
6182 out:
6183 if (!op_64_bit)
6184 ret = (u32)ret;
6185 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6186 ++vcpu->stat.hypercalls;
6187 return r;
6188 }
6189 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6190
6191 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6192 {
6193 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6194 char instruction[3];
6195 unsigned long rip = kvm_rip_read(vcpu);
6196
6197 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6198
6199 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
6200 }
6201
6202 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6203 {
6204 return vcpu->run->request_interrupt_window &&
6205 likely(!pic_in_kernel(vcpu->kvm));
6206 }
6207
6208 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6209 {
6210 struct kvm_run *kvm_run = vcpu->run;
6211
6212 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6213 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6214 kvm_run->cr8 = kvm_get_cr8(vcpu);
6215 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6216 kvm_run->ready_for_interrupt_injection =
6217 pic_in_kernel(vcpu->kvm) ||
6218 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6219 }
6220
6221 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6222 {
6223 int max_irr, tpr;
6224
6225 if (!kvm_x86_ops->update_cr8_intercept)
6226 return;
6227
6228 if (!lapic_in_kernel(vcpu))
6229 return;
6230
6231 if (vcpu->arch.apicv_active)
6232 return;
6233
6234 if (!vcpu->arch.apic->vapic_addr)
6235 max_irr = kvm_lapic_find_highest_irr(vcpu);
6236 else
6237 max_irr = -1;
6238
6239 if (max_irr != -1)
6240 max_irr >>= 4;
6241
6242 tpr = kvm_lapic_get_cr8(vcpu);
6243
6244 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6245 }
6246
6247 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6248 {
6249 int r;
6250
6251 /* try to reinject previous events if any */
6252 if (vcpu->arch.exception.pending) {
6253 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6254 vcpu->arch.exception.has_error_code,
6255 vcpu->arch.exception.error_code);
6256
6257 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6258 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6259 X86_EFLAGS_RF);
6260
6261 if (vcpu->arch.exception.nr == DB_VECTOR &&
6262 (vcpu->arch.dr7 & DR7_GD)) {
6263 vcpu->arch.dr7 &= ~DR7_GD;
6264 kvm_update_dr7(vcpu);
6265 }
6266
6267 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6268 vcpu->arch.exception.has_error_code,
6269 vcpu->arch.exception.error_code,
6270 vcpu->arch.exception.reinject);
6271 return 0;
6272 }
6273
6274 if (vcpu->arch.nmi_injected) {
6275 kvm_x86_ops->set_nmi(vcpu);
6276 return 0;
6277 }
6278
6279 if (vcpu->arch.interrupt.pending) {
6280 kvm_x86_ops->set_irq(vcpu);
6281 return 0;
6282 }
6283
6284 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6285 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6286 if (r != 0)
6287 return r;
6288 }
6289
6290 /* try to inject new event if pending */
6291 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6292 vcpu->arch.smi_pending = false;
6293 enter_smm(vcpu);
6294 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6295 --vcpu->arch.nmi_pending;
6296 vcpu->arch.nmi_injected = true;
6297 kvm_x86_ops->set_nmi(vcpu);
6298 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6299 /*
6300 * Because interrupts can be injected asynchronously, we are
6301 * calling check_nested_events again here to avoid a race condition.
6302 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6303 * proposal and current concerns. Perhaps we should be setting
6304 * KVM_REQ_EVENT only on certain events and not unconditionally?
6305 */
6306 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6307 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6308 if (r != 0)
6309 return r;
6310 }
6311 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6312 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6313 false);
6314 kvm_x86_ops->set_irq(vcpu);
6315 }
6316 }
6317
6318 return 0;
6319 }
6320
6321 static void process_nmi(struct kvm_vcpu *vcpu)
6322 {
6323 unsigned limit = 2;
6324
6325 /*
6326 * x86 is limited to one NMI running, and one NMI pending after it.
6327 * If an NMI is already in progress, limit further NMIs to just one.
6328 * Otherwise, allow two (and we'll inject the first one immediately).
6329 */
6330 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6331 limit = 1;
6332
6333 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6334 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6335 kvm_make_request(KVM_REQ_EVENT, vcpu);
6336 }
6337
6338 #define put_smstate(type, buf, offset, val) \
6339 *(type *)((buf) + (offset) - 0x7e00) = val
6340
6341 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6342 {
6343 u32 flags = 0;
6344 flags |= seg->g << 23;
6345 flags |= seg->db << 22;
6346 flags |= seg->l << 21;
6347 flags |= seg->avl << 20;
6348 flags |= seg->present << 15;
6349 flags |= seg->dpl << 13;
6350 flags |= seg->s << 12;
6351 flags |= seg->type << 8;
6352 return flags;
6353 }
6354
6355 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6356 {
6357 struct kvm_segment seg;
6358 int offset;
6359
6360 kvm_get_segment(vcpu, &seg, n);
6361 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6362
6363 if (n < 3)
6364 offset = 0x7f84 + n * 12;
6365 else
6366 offset = 0x7f2c + (n - 3) * 12;
6367
6368 put_smstate(u32, buf, offset + 8, seg.base);
6369 put_smstate(u32, buf, offset + 4, seg.limit);
6370 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6371 }
6372
6373 #ifdef CONFIG_X86_64
6374 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6375 {
6376 struct kvm_segment seg;
6377 int offset;
6378 u16 flags;
6379
6380 kvm_get_segment(vcpu, &seg, n);
6381 offset = 0x7e00 + n * 16;
6382
6383 flags = enter_smm_get_segment_flags(&seg) >> 8;
6384 put_smstate(u16, buf, offset, seg.selector);
6385 put_smstate(u16, buf, offset + 2, flags);
6386 put_smstate(u32, buf, offset + 4, seg.limit);
6387 put_smstate(u64, buf, offset + 8, seg.base);
6388 }
6389 #endif
6390
6391 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6392 {
6393 struct desc_ptr dt;
6394 struct kvm_segment seg;
6395 unsigned long val;
6396 int i;
6397
6398 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6399 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6400 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6401 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6402
6403 for (i = 0; i < 8; i++)
6404 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6405
6406 kvm_get_dr(vcpu, 6, &val);
6407 put_smstate(u32, buf, 0x7fcc, (u32)val);
6408 kvm_get_dr(vcpu, 7, &val);
6409 put_smstate(u32, buf, 0x7fc8, (u32)val);
6410
6411 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6412 put_smstate(u32, buf, 0x7fc4, seg.selector);
6413 put_smstate(u32, buf, 0x7f64, seg.base);
6414 put_smstate(u32, buf, 0x7f60, seg.limit);
6415 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6416
6417 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6418 put_smstate(u32, buf, 0x7fc0, seg.selector);
6419 put_smstate(u32, buf, 0x7f80, seg.base);
6420 put_smstate(u32, buf, 0x7f7c, seg.limit);
6421 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6422
6423 kvm_x86_ops->get_gdt(vcpu, &dt);
6424 put_smstate(u32, buf, 0x7f74, dt.address);
6425 put_smstate(u32, buf, 0x7f70, dt.size);
6426
6427 kvm_x86_ops->get_idt(vcpu, &dt);
6428 put_smstate(u32, buf, 0x7f58, dt.address);
6429 put_smstate(u32, buf, 0x7f54, dt.size);
6430
6431 for (i = 0; i < 6; i++)
6432 enter_smm_save_seg_32(vcpu, buf, i);
6433
6434 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6435
6436 /* revision id */
6437 put_smstate(u32, buf, 0x7efc, 0x00020000);
6438 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6439 }
6440
6441 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6442 {
6443 #ifdef CONFIG_X86_64
6444 struct desc_ptr dt;
6445 struct kvm_segment seg;
6446 unsigned long val;
6447 int i;
6448
6449 for (i = 0; i < 16; i++)
6450 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6451
6452 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6453 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6454
6455 kvm_get_dr(vcpu, 6, &val);
6456 put_smstate(u64, buf, 0x7f68, val);
6457 kvm_get_dr(vcpu, 7, &val);
6458 put_smstate(u64, buf, 0x7f60, val);
6459
6460 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6461 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6462 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6463
6464 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6465
6466 /* revision id */
6467 put_smstate(u32, buf, 0x7efc, 0x00020064);
6468
6469 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6470
6471 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6472 put_smstate(u16, buf, 0x7e90, seg.selector);
6473 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6474 put_smstate(u32, buf, 0x7e94, seg.limit);
6475 put_smstate(u64, buf, 0x7e98, seg.base);
6476
6477 kvm_x86_ops->get_idt(vcpu, &dt);
6478 put_smstate(u32, buf, 0x7e84, dt.size);
6479 put_smstate(u64, buf, 0x7e88, dt.address);
6480
6481 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6482 put_smstate(u16, buf, 0x7e70, seg.selector);
6483 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6484 put_smstate(u32, buf, 0x7e74, seg.limit);
6485 put_smstate(u64, buf, 0x7e78, seg.base);
6486
6487 kvm_x86_ops->get_gdt(vcpu, &dt);
6488 put_smstate(u32, buf, 0x7e64, dt.size);
6489 put_smstate(u64, buf, 0x7e68, dt.address);
6490
6491 for (i = 0; i < 6; i++)
6492 enter_smm_save_seg_64(vcpu, buf, i);
6493 #else
6494 WARN_ON_ONCE(1);
6495 #endif
6496 }
6497
6498 static void enter_smm(struct kvm_vcpu *vcpu)
6499 {
6500 struct kvm_segment cs, ds;
6501 struct desc_ptr dt;
6502 char buf[512];
6503 u32 cr0;
6504
6505 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6506 vcpu->arch.hflags |= HF_SMM_MASK;
6507 memset(buf, 0, 512);
6508 if (guest_cpuid_has_longmode(vcpu))
6509 enter_smm_save_state_64(vcpu, buf);
6510 else
6511 enter_smm_save_state_32(vcpu, buf);
6512
6513 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6514
6515 if (kvm_x86_ops->get_nmi_mask(vcpu))
6516 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6517 else
6518 kvm_x86_ops->set_nmi_mask(vcpu, true);
6519
6520 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6521 kvm_rip_write(vcpu, 0x8000);
6522
6523 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6524 kvm_x86_ops->set_cr0(vcpu, cr0);
6525 vcpu->arch.cr0 = cr0;
6526
6527 kvm_x86_ops->set_cr4(vcpu, 0);
6528
6529 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6530 dt.address = dt.size = 0;
6531 kvm_x86_ops->set_idt(vcpu, &dt);
6532
6533 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6534
6535 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6536 cs.base = vcpu->arch.smbase;
6537
6538 ds.selector = 0;
6539 ds.base = 0;
6540
6541 cs.limit = ds.limit = 0xffffffff;
6542 cs.type = ds.type = 0x3;
6543 cs.dpl = ds.dpl = 0;
6544 cs.db = ds.db = 0;
6545 cs.s = ds.s = 1;
6546 cs.l = ds.l = 0;
6547 cs.g = ds.g = 1;
6548 cs.avl = ds.avl = 0;
6549 cs.present = ds.present = 1;
6550 cs.unusable = ds.unusable = 0;
6551 cs.padding = ds.padding = 0;
6552
6553 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6554 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6555 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6556 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6557 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6558 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6559
6560 if (guest_cpuid_has_longmode(vcpu))
6561 kvm_x86_ops->set_efer(vcpu, 0);
6562
6563 kvm_update_cpuid(vcpu);
6564 kvm_mmu_reset_context(vcpu);
6565 }
6566
6567 static void process_smi(struct kvm_vcpu *vcpu)
6568 {
6569 vcpu->arch.smi_pending = true;
6570 kvm_make_request(KVM_REQ_EVENT, vcpu);
6571 }
6572
6573 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6574 {
6575 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6576 }
6577
6578 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6579 {
6580 u64 eoi_exit_bitmap[4];
6581
6582 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6583 return;
6584
6585 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6586
6587 if (irqchip_split(vcpu->kvm))
6588 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6589 else {
6590 if (vcpu->arch.apicv_active)
6591 kvm_x86_ops->sync_pir_to_irr(vcpu);
6592 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6593 }
6594 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6595 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6596 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6597 }
6598
6599 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6600 {
6601 ++vcpu->stat.tlb_flush;
6602 kvm_x86_ops->tlb_flush(vcpu);
6603 }
6604
6605 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6606 {
6607 struct page *page = NULL;
6608
6609 if (!lapic_in_kernel(vcpu))
6610 return;
6611
6612 if (!kvm_x86_ops->set_apic_access_page_addr)
6613 return;
6614
6615 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6616 if (is_error_page(page))
6617 return;
6618 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6619
6620 /*
6621 * Do not pin apic access page in memory, the MMU notifier
6622 * will call us again if it is migrated or swapped out.
6623 */
6624 put_page(page);
6625 }
6626 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6627
6628 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6629 unsigned long address)
6630 {
6631 /*
6632 * The physical address of apic access page is stored in the VMCS.
6633 * Update it when it becomes invalid.
6634 */
6635 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6636 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6637 }
6638
6639 /*
6640 * Returns 1 to let vcpu_run() continue the guest execution loop without
6641 * exiting to the userspace. Otherwise, the value will be returned to the
6642 * userspace.
6643 */
6644 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6645 {
6646 int r;
6647 bool req_int_win =
6648 dm_request_for_irq_injection(vcpu) &&
6649 kvm_cpu_accept_dm_intr(vcpu);
6650
6651 bool req_immediate_exit = false;
6652
6653 if (vcpu->requests) {
6654 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6655 kvm_mmu_unload(vcpu);
6656 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6657 __kvm_migrate_timers(vcpu);
6658 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6659 kvm_gen_update_masterclock(vcpu->kvm);
6660 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6661 kvm_gen_kvmclock_update(vcpu);
6662 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6663 r = kvm_guest_time_update(vcpu);
6664 if (unlikely(r))
6665 goto out;
6666 }
6667 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6668 kvm_mmu_sync_roots(vcpu);
6669 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6670 kvm_vcpu_flush_tlb(vcpu);
6671 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6672 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6673 r = 0;
6674 goto out;
6675 }
6676 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6677 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6678 r = 0;
6679 goto out;
6680 }
6681 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6682 vcpu->fpu_active = 0;
6683 kvm_x86_ops->fpu_deactivate(vcpu);
6684 }
6685 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6686 /* Page is swapped out. Do synthetic halt */
6687 vcpu->arch.apf.halted = true;
6688 r = 1;
6689 goto out;
6690 }
6691 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6692 record_steal_time(vcpu);
6693 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6694 process_smi(vcpu);
6695 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6696 process_nmi(vcpu);
6697 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6698 kvm_pmu_handle_event(vcpu);
6699 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6700 kvm_pmu_deliver_pmi(vcpu);
6701 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6702 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6703 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6704 vcpu->arch.ioapic_handled_vectors)) {
6705 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6706 vcpu->run->eoi.vector =
6707 vcpu->arch.pending_ioapic_eoi;
6708 r = 0;
6709 goto out;
6710 }
6711 }
6712 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6713 vcpu_scan_ioapic(vcpu);
6714 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6715 kvm_vcpu_reload_apic_access_page(vcpu);
6716 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6717 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6718 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6719 r = 0;
6720 goto out;
6721 }
6722 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6723 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6724 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6725 r = 0;
6726 goto out;
6727 }
6728 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6729 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6730 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6731 r = 0;
6732 goto out;
6733 }
6734
6735 /*
6736 * KVM_REQ_HV_STIMER has to be processed after
6737 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6738 * depend on the guest clock being up-to-date
6739 */
6740 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6741 kvm_hv_process_stimers(vcpu);
6742 }
6743
6744 /*
6745 * KVM_REQ_EVENT is not set when posted interrupts are set by
6746 * VT-d hardware, so we have to update RVI unconditionally.
6747 */
6748 if (kvm_lapic_enabled(vcpu)) {
6749 /*
6750 * Update architecture specific hints for APIC
6751 * virtual interrupt delivery.
6752 */
6753 if (vcpu->arch.apicv_active)
6754 kvm_x86_ops->hwapic_irr_update(vcpu,
6755 kvm_lapic_find_highest_irr(vcpu));
6756 }
6757
6758 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6759 kvm_apic_accept_events(vcpu);
6760 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6761 r = 1;
6762 goto out;
6763 }
6764
6765 if (inject_pending_event(vcpu, req_int_win) != 0)
6766 req_immediate_exit = true;
6767 else {
6768 /* Enable NMI/IRQ window open exits if needed.
6769 *
6770 * SMIs have two cases: 1) they can be nested, and
6771 * then there is nothing to do here because RSM will
6772 * cause a vmexit anyway; 2) or the SMI can be pending
6773 * because inject_pending_event has completed the
6774 * injection of an IRQ or NMI from the previous vmexit,
6775 * and then we request an immediate exit to inject the SMI.
6776 */
6777 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6778 req_immediate_exit = true;
6779 if (vcpu->arch.nmi_pending)
6780 kvm_x86_ops->enable_nmi_window(vcpu);
6781 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6782 kvm_x86_ops->enable_irq_window(vcpu);
6783 }
6784
6785 if (kvm_lapic_enabled(vcpu)) {
6786 update_cr8_intercept(vcpu);
6787 kvm_lapic_sync_to_vapic(vcpu);
6788 }
6789 }
6790
6791 r = kvm_mmu_reload(vcpu);
6792 if (unlikely(r)) {
6793 goto cancel_injection;
6794 }
6795
6796 preempt_disable();
6797
6798 kvm_x86_ops->prepare_guest_switch(vcpu);
6799 if (vcpu->fpu_active)
6800 kvm_load_guest_fpu(vcpu);
6801 vcpu->mode = IN_GUEST_MODE;
6802
6803 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6804
6805 /*
6806 * We should set ->mode before check ->requests,
6807 * Please see the comment in kvm_make_all_cpus_request.
6808 * This also orders the write to mode from any reads
6809 * to the page tables done while the VCPU is running.
6810 * Please see the comment in kvm_flush_remote_tlbs.
6811 */
6812 smp_mb__after_srcu_read_unlock();
6813
6814 local_irq_disable();
6815
6816 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6817 || need_resched() || signal_pending(current)) {
6818 vcpu->mode = OUTSIDE_GUEST_MODE;
6819 smp_wmb();
6820 local_irq_enable();
6821 preempt_enable();
6822 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6823 r = 1;
6824 goto cancel_injection;
6825 }
6826
6827 kvm_load_guest_xcr0(vcpu);
6828
6829 if (req_immediate_exit) {
6830 kvm_make_request(KVM_REQ_EVENT, vcpu);
6831 smp_send_reschedule(vcpu->cpu);
6832 }
6833
6834 trace_kvm_entry(vcpu->vcpu_id);
6835 wait_lapic_expire(vcpu);
6836 guest_enter_irqoff();
6837
6838 if (unlikely(vcpu->arch.switch_db_regs)) {
6839 set_debugreg(0, 7);
6840 set_debugreg(vcpu->arch.eff_db[0], 0);
6841 set_debugreg(vcpu->arch.eff_db[1], 1);
6842 set_debugreg(vcpu->arch.eff_db[2], 2);
6843 set_debugreg(vcpu->arch.eff_db[3], 3);
6844 set_debugreg(vcpu->arch.dr6, 6);
6845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6846 }
6847
6848 kvm_x86_ops->run(vcpu);
6849
6850 /*
6851 * Do this here before restoring debug registers on the host. And
6852 * since we do this before handling the vmexit, a DR access vmexit
6853 * can (a) read the correct value of the debug registers, (b) set
6854 * KVM_DEBUGREG_WONT_EXIT again.
6855 */
6856 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6857 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6858 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6859 kvm_update_dr0123(vcpu);
6860 kvm_update_dr6(vcpu);
6861 kvm_update_dr7(vcpu);
6862 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6863 }
6864
6865 /*
6866 * If the guest has used debug registers, at least dr7
6867 * will be disabled while returning to the host.
6868 * If we don't have active breakpoints in the host, we don't
6869 * care about the messed up debug address registers. But if
6870 * we have some of them active, restore the old state.
6871 */
6872 if (hw_breakpoint_active())
6873 hw_breakpoint_restore();
6874
6875 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6876
6877 vcpu->mode = OUTSIDE_GUEST_MODE;
6878 smp_wmb();
6879
6880 kvm_put_guest_xcr0(vcpu);
6881
6882 kvm_x86_ops->handle_external_intr(vcpu);
6883
6884 ++vcpu->stat.exits;
6885
6886 guest_exit_irqoff();
6887
6888 local_irq_enable();
6889 preempt_enable();
6890
6891 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6892
6893 /*
6894 * Profile KVM exit RIPs:
6895 */
6896 if (unlikely(prof_on == KVM_PROFILING)) {
6897 unsigned long rip = kvm_rip_read(vcpu);
6898 profile_hit(KVM_PROFILING, (void *)rip);
6899 }
6900
6901 if (unlikely(vcpu->arch.tsc_always_catchup))
6902 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6903
6904 if (vcpu->arch.apic_attention)
6905 kvm_lapic_sync_from_vapic(vcpu);
6906
6907 r = kvm_x86_ops->handle_exit(vcpu);
6908 return r;
6909
6910 cancel_injection:
6911 kvm_x86_ops->cancel_injection(vcpu);
6912 if (unlikely(vcpu->arch.apic_attention))
6913 kvm_lapic_sync_from_vapic(vcpu);
6914 out:
6915 return r;
6916 }
6917
6918 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6919 {
6920 if (!kvm_arch_vcpu_runnable(vcpu) &&
6921 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6922 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6923 kvm_vcpu_block(vcpu);
6924 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6925
6926 if (kvm_x86_ops->post_block)
6927 kvm_x86_ops->post_block(vcpu);
6928
6929 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6930 return 1;
6931 }
6932
6933 kvm_apic_accept_events(vcpu);
6934 switch(vcpu->arch.mp_state) {
6935 case KVM_MP_STATE_HALTED:
6936 vcpu->arch.pv.pv_unhalted = false;
6937 vcpu->arch.mp_state =
6938 KVM_MP_STATE_RUNNABLE;
6939 case KVM_MP_STATE_RUNNABLE:
6940 vcpu->arch.apf.halted = false;
6941 break;
6942 case KVM_MP_STATE_INIT_RECEIVED:
6943 break;
6944 default:
6945 return -EINTR;
6946 break;
6947 }
6948 return 1;
6949 }
6950
6951 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6952 {
6953 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6954 !vcpu->arch.apf.halted);
6955 }
6956
6957 static int vcpu_run(struct kvm_vcpu *vcpu)
6958 {
6959 int r;
6960 struct kvm *kvm = vcpu->kvm;
6961
6962 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6963
6964 for (;;) {
6965 if (kvm_vcpu_running(vcpu)) {
6966 r = vcpu_enter_guest(vcpu);
6967 } else {
6968 r = vcpu_block(kvm, vcpu);
6969 }
6970
6971 if (r <= 0)
6972 break;
6973
6974 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6975 if (kvm_cpu_has_pending_timer(vcpu))
6976 kvm_inject_pending_timer_irqs(vcpu);
6977
6978 if (dm_request_for_irq_injection(vcpu) &&
6979 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6980 r = 0;
6981 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6982 ++vcpu->stat.request_irq_exits;
6983 break;
6984 }
6985
6986 kvm_check_async_pf_completion(vcpu);
6987
6988 if (signal_pending(current)) {
6989 r = -EINTR;
6990 vcpu->run->exit_reason = KVM_EXIT_INTR;
6991 ++vcpu->stat.signal_exits;
6992 break;
6993 }
6994 if (need_resched()) {
6995 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6996 cond_resched();
6997 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6998 }
6999 }
7000
7001 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7002
7003 return r;
7004 }
7005
7006 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7007 {
7008 int r;
7009 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7010 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7011 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7012 if (r != EMULATE_DONE)
7013 return 0;
7014 return 1;
7015 }
7016
7017 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7018 {
7019 BUG_ON(!vcpu->arch.pio.count);
7020
7021 return complete_emulated_io(vcpu);
7022 }
7023
7024 /*
7025 * Implements the following, as a state machine:
7026 *
7027 * read:
7028 * for each fragment
7029 * for each mmio piece in the fragment
7030 * write gpa, len
7031 * exit
7032 * copy data
7033 * execute insn
7034 *
7035 * write:
7036 * for each fragment
7037 * for each mmio piece in the fragment
7038 * write gpa, len
7039 * copy data
7040 * exit
7041 */
7042 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
7043 {
7044 struct kvm_run *run = vcpu->run;
7045 struct kvm_mmio_fragment *frag;
7046 unsigned len;
7047
7048 BUG_ON(!vcpu->mmio_needed);
7049
7050 /* Complete previous fragment */
7051 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7052 len = min(8u, frag->len);
7053 if (!vcpu->mmio_is_write)
7054 memcpy(frag->data, run->mmio.data, len);
7055
7056 if (frag->len <= 8) {
7057 /* Switch to the next fragment. */
7058 frag++;
7059 vcpu->mmio_cur_fragment++;
7060 } else {
7061 /* Go forward to the next mmio piece. */
7062 frag->data += len;
7063 frag->gpa += len;
7064 frag->len -= len;
7065 }
7066
7067 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
7068 vcpu->mmio_needed = 0;
7069
7070 /* FIXME: return into emulator if single-stepping. */
7071 if (vcpu->mmio_is_write)
7072 return 1;
7073 vcpu->mmio_read_completed = 1;
7074 return complete_emulated_io(vcpu);
7075 }
7076
7077 run->exit_reason = KVM_EXIT_MMIO;
7078 run->mmio.phys_addr = frag->gpa;
7079 if (vcpu->mmio_is_write)
7080 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7081 run->mmio.len = min(8u, frag->len);
7082 run->mmio.is_write = vcpu->mmio_is_write;
7083 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7084 return 0;
7085 }
7086
7087
7088 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7089 {
7090 struct fpu *fpu = &current->thread.fpu;
7091 int r;
7092 sigset_t sigsaved;
7093
7094 fpu__activate_curr(fpu);
7095
7096 if (vcpu->sigset_active)
7097 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7098
7099 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7100 kvm_vcpu_block(vcpu);
7101 kvm_apic_accept_events(vcpu);
7102 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
7103 r = -EAGAIN;
7104 goto out;
7105 }
7106
7107 /* re-sync apic's tpr */
7108 if (!lapic_in_kernel(vcpu)) {
7109 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7110 r = -EINVAL;
7111 goto out;
7112 }
7113 }
7114
7115 if (unlikely(vcpu->arch.complete_userspace_io)) {
7116 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7117 vcpu->arch.complete_userspace_io = NULL;
7118 r = cui(vcpu);
7119 if (r <= 0)
7120 goto out;
7121 } else
7122 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7123
7124 r = vcpu_run(vcpu);
7125
7126 out:
7127 post_kvm_run_save(vcpu);
7128 if (vcpu->sigset_active)
7129 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7130
7131 return r;
7132 }
7133
7134 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7135 {
7136 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7137 /*
7138 * We are here if userspace calls get_regs() in the middle of
7139 * instruction emulation. Registers state needs to be copied
7140 * back from emulation context to vcpu. Userspace shouldn't do
7141 * that usually, but some bad designed PV devices (vmware
7142 * backdoor interface) need this to work
7143 */
7144 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7145 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7146 }
7147 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7148 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7149 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7150 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7151 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7152 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7153 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7154 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7155 #ifdef CONFIG_X86_64
7156 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7157 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7158 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7159 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7160 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7161 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7162 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7163 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7164 #endif
7165
7166 regs->rip = kvm_rip_read(vcpu);
7167 regs->rflags = kvm_get_rflags(vcpu);
7168
7169 return 0;
7170 }
7171
7172 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7173 {
7174 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7175 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7176
7177 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7178 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7179 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7180 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7181 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7182 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7183 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7184 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7185 #ifdef CONFIG_X86_64
7186 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7187 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7188 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7189 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7190 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7191 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7192 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7193 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7194 #endif
7195
7196 kvm_rip_write(vcpu, regs->rip);
7197 kvm_set_rflags(vcpu, regs->rflags);
7198
7199 vcpu->arch.exception.pending = false;
7200
7201 kvm_make_request(KVM_REQ_EVENT, vcpu);
7202
7203 return 0;
7204 }
7205
7206 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7207 {
7208 struct kvm_segment cs;
7209
7210 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7211 *db = cs.db;
7212 *l = cs.l;
7213 }
7214 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7215
7216 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7217 struct kvm_sregs *sregs)
7218 {
7219 struct desc_ptr dt;
7220
7221 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7222 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7223 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7224 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7225 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7226 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7227
7228 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7229 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7230
7231 kvm_x86_ops->get_idt(vcpu, &dt);
7232 sregs->idt.limit = dt.size;
7233 sregs->idt.base = dt.address;
7234 kvm_x86_ops->get_gdt(vcpu, &dt);
7235 sregs->gdt.limit = dt.size;
7236 sregs->gdt.base = dt.address;
7237
7238 sregs->cr0 = kvm_read_cr0(vcpu);
7239 sregs->cr2 = vcpu->arch.cr2;
7240 sregs->cr3 = kvm_read_cr3(vcpu);
7241 sregs->cr4 = kvm_read_cr4(vcpu);
7242 sregs->cr8 = kvm_get_cr8(vcpu);
7243 sregs->efer = vcpu->arch.efer;
7244 sregs->apic_base = kvm_get_apic_base(vcpu);
7245
7246 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7247
7248 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7249 set_bit(vcpu->arch.interrupt.nr,
7250 (unsigned long *)sregs->interrupt_bitmap);
7251
7252 return 0;
7253 }
7254
7255 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7256 struct kvm_mp_state *mp_state)
7257 {
7258 kvm_apic_accept_events(vcpu);
7259 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7260 vcpu->arch.pv.pv_unhalted)
7261 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7262 else
7263 mp_state->mp_state = vcpu->arch.mp_state;
7264
7265 return 0;
7266 }
7267
7268 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7269 struct kvm_mp_state *mp_state)
7270 {
7271 if (!lapic_in_kernel(vcpu) &&
7272 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7273 return -EINVAL;
7274
7275 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7276 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7277 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7278 } else
7279 vcpu->arch.mp_state = mp_state->mp_state;
7280 kvm_make_request(KVM_REQ_EVENT, vcpu);
7281 return 0;
7282 }
7283
7284 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7285 int reason, bool has_error_code, u32 error_code)
7286 {
7287 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7288 int ret;
7289
7290 init_emulate_ctxt(vcpu);
7291
7292 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7293 has_error_code, error_code);
7294
7295 if (ret)
7296 return EMULATE_FAIL;
7297
7298 kvm_rip_write(vcpu, ctxt->eip);
7299 kvm_set_rflags(vcpu, ctxt->eflags);
7300 kvm_make_request(KVM_REQ_EVENT, vcpu);
7301 return EMULATE_DONE;
7302 }
7303 EXPORT_SYMBOL_GPL(kvm_task_switch);
7304
7305 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7306 struct kvm_sregs *sregs)
7307 {
7308 struct msr_data apic_base_msr;
7309 int mmu_reset_needed = 0;
7310 int pending_vec, max_bits, idx;
7311 struct desc_ptr dt;
7312
7313 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7314 return -EINVAL;
7315
7316 dt.size = sregs->idt.limit;
7317 dt.address = sregs->idt.base;
7318 kvm_x86_ops->set_idt(vcpu, &dt);
7319 dt.size = sregs->gdt.limit;
7320 dt.address = sregs->gdt.base;
7321 kvm_x86_ops->set_gdt(vcpu, &dt);
7322
7323 vcpu->arch.cr2 = sregs->cr2;
7324 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7325 vcpu->arch.cr3 = sregs->cr3;
7326 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7327
7328 kvm_set_cr8(vcpu, sregs->cr8);
7329
7330 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7331 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7332 apic_base_msr.data = sregs->apic_base;
7333 apic_base_msr.host_initiated = true;
7334 kvm_set_apic_base(vcpu, &apic_base_msr);
7335
7336 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7337 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7338 vcpu->arch.cr0 = sregs->cr0;
7339
7340 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7341 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7342 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7343 kvm_update_cpuid(vcpu);
7344
7345 idx = srcu_read_lock(&vcpu->kvm->srcu);
7346 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7347 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7348 mmu_reset_needed = 1;
7349 }
7350 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7351
7352 if (mmu_reset_needed)
7353 kvm_mmu_reset_context(vcpu);
7354
7355 max_bits = KVM_NR_INTERRUPTS;
7356 pending_vec = find_first_bit(
7357 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7358 if (pending_vec < max_bits) {
7359 kvm_queue_interrupt(vcpu, pending_vec, false);
7360 pr_debug("Set back pending irq %d\n", pending_vec);
7361 }
7362
7363 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7364 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7365 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7366 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7367 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7368 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7369
7370 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7371 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7372
7373 update_cr8_intercept(vcpu);
7374
7375 /* Older userspace won't unhalt the vcpu on reset. */
7376 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7377 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7378 !is_protmode(vcpu))
7379 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7380
7381 kvm_make_request(KVM_REQ_EVENT, vcpu);
7382
7383 return 0;
7384 }
7385
7386 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7387 struct kvm_guest_debug *dbg)
7388 {
7389 unsigned long rflags;
7390 int i, r;
7391
7392 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7393 r = -EBUSY;
7394 if (vcpu->arch.exception.pending)
7395 goto out;
7396 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7397 kvm_queue_exception(vcpu, DB_VECTOR);
7398 else
7399 kvm_queue_exception(vcpu, BP_VECTOR);
7400 }
7401
7402 /*
7403 * Read rflags as long as potentially injected trace flags are still
7404 * filtered out.
7405 */
7406 rflags = kvm_get_rflags(vcpu);
7407
7408 vcpu->guest_debug = dbg->control;
7409 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7410 vcpu->guest_debug = 0;
7411
7412 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7413 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7414 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7415 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7416 } else {
7417 for (i = 0; i < KVM_NR_DB_REGS; i++)
7418 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7419 }
7420 kvm_update_dr7(vcpu);
7421
7422 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7423 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7424 get_segment_base(vcpu, VCPU_SREG_CS);
7425
7426 /*
7427 * Trigger an rflags update that will inject or remove the trace
7428 * flags.
7429 */
7430 kvm_set_rflags(vcpu, rflags);
7431
7432 kvm_x86_ops->update_bp_intercept(vcpu);
7433
7434 r = 0;
7435
7436 out:
7437
7438 return r;
7439 }
7440
7441 /*
7442 * Translate a guest virtual address to a guest physical address.
7443 */
7444 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7445 struct kvm_translation *tr)
7446 {
7447 unsigned long vaddr = tr->linear_address;
7448 gpa_t gpa;
7449 int idx;
7450
7451 idx = srcu_read_lock(&vcpu->kvm->srcu);
7452 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7453 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7454 tr->physical_address = gpa;
7455 tr->valid = gpa != UNMAPPED_GVA;
7456 tr->writeable = 1;
7457 tr->usermode = 0;
7458
7459 return 0;
7460 }
7461
7462 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7463 {
7464 struct fxregs_state *fxsave =
7465 &vcpu->arch.guest_fpu.state.fxsave;
7466
7467 memcpy(fpu->fpr, fxsave->st_space, 128);
7468 fpu->fcw = fxsave->cwd;
7469 fpu->fsw = fxsave->swd;
7470 fpu->ftwx = fxsave->twd;
7471 fpu->last_opcode = fxsave->fop;
7472 fpu->last_ip = fxsave->rip;
7473 fpu->last_dp = fxsave->rdp;
7474 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7475
7476 return 0;
7477 }
7478
7479 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7480 {
7481 struct fxregs_state *fxsave =
7482 &vcpu->arch.guest_fpu.state.fxsave;
7483
7484 memcpy(fxsave->st_space, fpu->fpr, 128);
7485 fxsave->cwd = fpu->fcw;
7486 fxsave->swd = fpu->fsw;
7487 fxsave->twd = fpu->ftwx;
7488 fxsave->fop = fpu->last_opcode;
7489 fxsave->rip = fpu->last_ip;
7490 fxsave->rdp = fpu->last_dp;
7491 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7492
7493 return 0;
7494 }
7495
7496 static void fx_init(struct kvm_vcpu *vcpu)
7497 {
7498 fpstate_init(&vcpu->arch.guest_fpu.state);
7499 if (boot_cpu_has(X86_FEATURE_XSAVES))
7500 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7501 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7502
7503 /*
7504 * Ensure guest xcr0 is valid for loading
7505 */
7506 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7507
7508 vcpu->arch.cr0 |= X86_CR0_ET;
7509 }
7510
7511 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7512 {
7513 if (vcpu->guest_fpu_loaded)
7514 return;
7515
7516 /*
7517 * Restore all possible states in the guest,
7518 * and assume host would use all available bits.
7519 * Guest xcr0 would be loaded later.
7520 */
7521 vcpu->guest_fpu_loaded = 1;
7522 __kernel_fpu_begin();
7523 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7524 trace_kvm_fpu(1);
7525 }
7526
7527 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7528 {
7529 if (!vcpu->guest_fpu_loaded)
7530 return;
7531
7532 vcpu->guest_fpu_loaded = 0;
7533 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7534 __kernel_fpu_end();
7535 ++vcpu->stat.fpu_reload;
7536 trace_kvm_fpu(0);
7537 }
7538
7539 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7540 {
7541 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7542
7543 kvmclock_reset(vcpu);
7544
7545 kvm_x86_ops->vcpu_free(vcpu);
7546 free_cpumask_var(wbinvd_dirty_mask);
7547 }
7548
7549 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7550 unsigned int id)
7551 {
7552 struct kvm_vcpu *vcpu;
7553
7554 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7555 printk_once(KERN_WARNING
7556 "kvm: SMP vm created on host with unstable TSC; "
7557 "guest TSC will not be reliable\n");
7558
7559 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7560
7561 return vcpu;
7562 }
7563
7564 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7565 {
7566 int r;
7567
7568 kvm_vcpu_mtrr_init(vcpu);
7569 r = vcpu_load(vcpu);
7570 if (r)
7571 return r;
7572 kvm_vcpu_reset(vcpu, false);
7573 kvm_mmu_setup(vcpu);
7574 vcpu_put(vcpu);
7575 return r;
7576 }
7577
7578 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7579 {
7580 struct msr_data msr;
7581 struct kvm *kvm = vcpu->kvm;
7582
7583 if (vcpu_load(vcpu))
7584 return;
7585 msr.data = 0x0;
7586 msr.index = MSR_IA32_TSC;
7587 msr.host_initiated = true;
7588 kvm_write_tsc(vcpu, &msr);
7589 vcpu_put(vcpu);
7590
7591 if (!kvmclock_periodic_sync)
7592 return;
7593
7594 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7595 KVMCLOCK_SYNC_PERIOD);
7596 }
7597
7598 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7599 {
7600 int r;
7601 vcpu->arch.apf.msr_val = 0;
7602
7603 r = vcpu_load(vcpu);
7604 BUG_ON(r);
7605 kvm_mmu_unload(vcpu);
7606 vcpu_put(vcpu);
7607
7608 kvm_x86_ops->vcpu_free(vcpu);
7609 }
7610
7611 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7612 {
7613 vcpu->arch.hflags = 0;
7614
7615 vcpu->arch.smi_pending = 0;
7616 atomic_set(&vcpu->arch.nmi_queued, 0);
7617 vcpu->arch.nmi_pending = 0;
7618 vcpu->arch.nmi_injected = false;
7619 kvm_clear_interrupt_queue(vcpu);
7620 kvm_clear_exception_queue(vcpu);
7621
7622 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7623 kvm_update_dr0123(vcpu);
7624 vcpu->arch.dr6 = DR6_INIT;
7625 kvm_update_dr6(vcpu);
7626 vcpu->arch.dr7 = DR7_FIXED_1;
7627 kvm_update_dr7(vcpu);
7628
7629 vcpu->arch.cr2 = 0;
7630
7631 kvm_make_request(KVM_REQ_EVENT, vcpu);
7632 vcpu->arch.apf.msr_val = 0;
7633 vcpu->arch.st.msr_val = 0;
7634
7635 kvmclock_reset(vcpu);
7636
7637 kvm_clear_async_pf_completion_queue(vcpu);
7638 kvm_async_pf_hash_reset(vcpu);
7639 vcpu->arch.apf.halted = false;
7640
7641 if (!init_event) {
7642 kvm_pmu_reset(vcpu);
7643 vcpu->arch.smbase = 0x30000;
7644 }
7645
7646 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7647 vcpu->arch.regs_avail = ~0;
7648 vcpu->arch.regs_dirty = ~0;
7649
7650 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7651 }
7652
7653 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7654 {
7655 struct kvm_segment cs;
7656
7657 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7658 cs.selector = vector << 8;
7659 cs.base = vector << 12;
7660 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7661 kvm_rip_write(vcpu, 0);
7662 }
7663
7664 int kvm_arch_hardware_enable(void)
7665 {
7666 struct kvm *kvm;
7667 struct kvm_vcpu *vcpu;
7668 int i;
7669 int ret;
7670 u64 local_tsc;
7671 u64 max_tsc = 0;
7672 bool stable, backwards_tsc = false;
7673
7674 kvm_shared_msr_cpu_online();
7675 ret = kvm_x86_ops->hardware_enable();
7676 if (ret != 0)
7677 return ret;
7678
7679 local_tsc = rdtsc();
7680 stable = !check_tsc_unstable();
7681 list_for_each_entry(kvm, &vm_list, vm_list) {
7682 kvm_for_each_vcpu(i, vcpu, kvm) {
7683 if (!stable && vcpu->cpu == smp_processor_id())
7684 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7685 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7686 backwards_tsc = true;
7687 if (vcpu->arch.last_host_tsc > max_tsc)
7688 max_tsc = vcpu->arch.last_host_tsc;
7689 }
7690 }
7691 }
7692
7693 /*
7694 * Sometimes, even reliable TSCs go backwards. This happens on
7695 * platforms that reset TSC during suspend or hibernate actions, but
7696 * maintain synchronization. We must compensate. Fortunately, we can
7697 * detect that condition here, which happens early in CPU bringup,
7698 * before any KVM threads can be running. Unfortunately, we can't
7699 * bring the TSCs fully up to date with real time, as we aren't yet far
7700 * enough into CPU bringup that we know how much real time has actually
7701 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
7702 * variables that haven't been updated yet.
7703 *
7704 * So we simply find the maximum observed TSC above, then record the
7705 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7706 * the adjustment will be applied. Note that we accumulate
7707 * adjustments, in case multiple suspend cycles happen before some VCPU
7708 * gets a chance to run again. In the event that no KVM threads get a
7709 * chance to run, we will miss the entire elapsed period, as we'll have
7710 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7711 * loose cycle time. This isn't too big a deal, since the loss will be
7712 * uniform across all VCPUs (not to mention the scenario is extremely
7713 * unlikely). It is possible that a second hibernate recovery happens
7714 * much faster than a first, causing the observed TSC here to be
7715 * smaller; this would require additional padding adjustment, which is
7716 * why we set last_host_tsc to the local tsc observed here.
7717 *
7718 * N.B. - this code below runs only on platforms with reliable TSC,
7719 * as that is the only way backwards_tsc is set above. Also note
7720 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7721 * have the same delta_cyc adjustment applied if backwards_tsc
7722 * is detected. Note further, this adjustment is only done once,
7723 * as we reset last_host_tsc on all VCPUs to stop this from being
7724 * called multiple times (one for each physical CPU bringup).
7725 *
7726 * Platforms with unreliable TSCs don't have to deal with this, they
7727 * will be compensated by the logic in vcpu_load, which sets the TSC to
7728 * catchup mode. This will catchup all VCPUs to real time, but cannot
7729 * guarantee that they stay in perfect synchronization.
7730 */
7731 if (backwards_tsc) {
7732 u64 delta_cyc = max_tsc - local_tsc;
7733 backwards_tsc_observed = true;
7734 list_for_each_entry(kvm, &vm_list, vm_list) {
7735 kvm_for_each_vcpu(i, vcpu, kvm) {
7736 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7737 vcpu->arch.last_host_tsc = local_tsc;
7738 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7739 }
7740
7741 /*
7742 * We have to disable TSC offset matching.. if you were
7743 * booting a VM while issuing an S4 host suspend....
7744 * you may have some problem. Solving this issue is
7745 * left as an exercise to the reader.
7746 */
7747 kvm->arch.last_tsc_nsec = 0;
7748 kvm->arch.last_tsc_write = 0;
7749 }
7750
7751 }
7752 return 0;
7753 }
7754
7755 void kvm_arch_hardware_disable(void)
7756 {
7757 kvm_x86_ops->hardware_disable();
7758 drop_user_return_notifiers();
7759 }
7760
7761 int kvm_arch_hardware_setup(void)
7762 {
7763 int r;
7764
7765 r = kvm_x86_ops->hardware_setup();
7766 if (r != 0)
7767 return r;
7768
7769 if (kvm_has_tsc_control) {
7770 /*
7771 * Make sure the user can only configure tsc_khz values that
7772 * fit into a signed integer.
7773 * A min value is not calculated needed because it will always
7774 * be 1 on all machines.
7775 */
7776 u64 max = min(0x7fffffffULL,
7777 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7778 kvm_max_guest_tsc_khz = max;
7779
7780 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7781 }
7782
7783 kvm_init_msr_list();
7784 return 0;
7785 }
7786
7787 void kvm_arch_hardware_unsetup(void)
7788 {
7789 kvm_x86_ops->hardware_unsetup();
7790 }
7791
7792 void kvm_arch_check_processor_compat(void *rtn)
7793 {
7794 kvm_x86_ops->check_processor_compatibility(rtn);
7795 }
7796
7797 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7798 {
7799 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7800 }
7801 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7802
7803 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7804 {
7805 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7806 }
7807
7808 struct static_key kvm_no_apic_vcpu __read_mostly;
7809 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7810
7811 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7812 {
7813 struct page *page;
7814 struct kvm *kvm;
7815 int r;
7816
7817 BUG_ON(vcpu->kvm == NULL);
7818 kvm = vcpu->kvm;
7819
7820 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7821 vcpu->arch.pv.pv_unhalted = false;
7822 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7823 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7824 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7825 else
7826 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7827
7828 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7829 if (!page) {
7830 r = -ENOMEM;
7831 goto fail;
7832 }
7833 vcpu->arch.pio_data = page_address(page);
7834
7835 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7836
7837 r = kvm_mmu_create(vcpu);
7838 if (r < 0)
7839 goto fail_free_pio_data;
7840
7841 if (irqchip_in_kernel(kvm)) {
7842 r = kvm_create_lapic(vcpu);
7843 if (r < 0)
7844 goto fail_mmu_destroy;
7845 } else
7846 static_key_slow_inc(&kvm_no_apic_vcpu);
7847
7848 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7849 GFP_KERNEL);
7850 if (!vcpu->arch.mce_banks) {
7851 r = -ENOMEM;
7852 goto fail_free_lapic;
7853 }
7854 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7855
7856 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7857 r = -ENOMEM;
7858 goto fail_free_mce_banks;
7859 }
7860
7861 fx_init(vcpu);
7862
7863 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7864 vcpu->arch.pv_time_enabled = false;
7865
7866 vcpu->arch.guest_supported_xcr0 = 0;
7867 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7868
7869 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7870
7871 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7872
7873 kvm_async_pf_hash_reset(vcpu);
7874 kvm_pmu_init(vcpu);
7875
7876 vcpu->arch.pending_external_vector = -1;
7877
7878 kvm_hv_vcpu_init(vcpu);
7879
7880 return 0;
7881
7882 fail_free_mce_banks:
7883 kfree(vcpu->arch.mce_banks);
7884 fail_free_lapic:
7885 kvm_free_lapic(vcpu);
7886 fail_mmu_destroy:
7887 kvm_mmu_destroy(vcpu);
7888 fail_free_pio_data:
7889 free_page((unsigned long)vcpu->arch.pio_data);
7890 fail:
7891 return r;
7892 }
7893
7894 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7895 {
7896 int idx;
7897
7898 kvm_hv_vcpu_uninit(vcpu);
7899 kvm_pmu_destroy(vcpu);
7900 kfree(vcpu->arch.mce_banks);
7901 kvm_free_lapic(vcpu);
7902 idx = srcu_read_lock(&vcpu->kvm->srcu);
7903 kvm_mmu_destroy(vcpu);
7904 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7905 free_page((unsigned long)vcpu->arch.pio_data);
7906 if (!lapic_in_kernel(vcpu))
7907 static_key_slow_dec(&kvm_no_apic_vcpu);
7908 }
7909
7910 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7911 {
7912 kvm_x86_ops->sched_in(vcpu, cpu);
7913 }
7914
7915 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7916 {
7917 if (type)
7918 return -EINVAL;
7919
7920 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7921 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7922 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7923 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7924 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7925
7926 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7927 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7928 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7929 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7930 &kvm->arch.irq_sources_bitmap);
7931
7932 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7933 mutex_init(&kvm->arch.apic_map_lock);
7934 mutex_init(&kvm->arch.hyperv.hv_lock);
7935 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7936
7937 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
7938 pvclock_update_vm_gtod_copy(kvm);
7939
7940 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7941 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7942
7943 kvm_page_track_init(kvm);
7944 kvm_mmu_init_vm(kvm);
7945
7946 if (kvm_x86_ops->vm_init)
7947 return kvm_x86_ops->vm_init(kvm);
7948
7949 return 0;
7950 }
7951
7952 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7953 {
7954 int r;
7955 r = vcpu_load(vcpu);
7956 BUG_ON(r);
7957 kvm_mmu_unload(vcpu);
7958 vcpu_put(vcpu);
7959 }
7960
7961 static void kvm_free_vcpus(struct kvm *kvm)
7962 {
7963 unsigned int i;
7964 struct kvm_vcpu *vcpu;
7965
7966 /*
7967 * Unpin any mmu pages first.
7968 */
7969 kvm_for_each_vcpu(i, vcpu, kvm) {
7970 kvm_clear_async_pf_completion_queue(vcpu);
7971 kvm_unload_vcpu_mmu(vcpu);
7972 }
7973 kvm_for_each_vcpu(i, vcpu, kvm)
7974 kvm_arch_vcpu_free(vcpu);
7975
7976 mutex_lock(&kvm->lock);
7977 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7978 kvm->vcpus[i] = NULL;
7979
7980 atomic_set(&kvm->online_vcpus, 0);
7981 mutex_unlock(&kvm->lock);
7982 }
7983
7984 void kvm_arch_sync_events(struct kvm *kvm)
7985 {
7986 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7987 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7988 kvm_free_all_assigned_devices(kvm);
7989 kvm_free_pit(kvm);
7990 }
7991
7992 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7993 {
7994 int i, r;
7995 unsigned long hva;
7996 struct kvm_memslots *slots = kvm_memslots(kvm);
7997 struct kvm_memory_slot *slot, old;
7998
7999 /* Called with kvm->slots_lock held. */
8000 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8001 return -EINVAL;
8002
8003 slot = id_to_memslot(slots, id);
8004 if (size) {
8005 if (slot->npages)
8006 return -EEXIST;
8007
8008 /*
8009 * MAP_SHARED to prevent internal slot pages from being moved
8010 * by fork()/COW.
8011 */
8012 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8013 MAP_SHARED | MAP_ANONYMOUS, 0);
8014 if (IS_ERR((void *)hva))
8015 return PTR_ERR((void *)hva);
8016 } else {
8017 if (!slot->npages)
8018 return 0;
8019
8020 hva = 0;
8021 }
8022
8023 old = *slot;
8024 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
8025 struct kvm_userspace_memory_region m;
8026
8027 m.slot = id | (i << 16);
8028 m.flags = 0;
8029 m.guest_phys_addr = gpa;
8030 m.userspace_addr = hva;
8031 m.memory_size = size;
8032 r = __kvm_set_memory_region(kvm, &m);
8033 if (r < 0)
8034 return r;
8035 }
8036
8037 if (!size) {
8038 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8039 WARN_ON(r < 0);
8040 }
8041
8042 return 0;
8043 }
8044 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8045
8046 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
8047 {
8048 int r;
8049
8050 mutex_lock(&kvm->slots_lock);
8051 r = __x86_set_memory_region(kvm, id, gpa, size);
8052 mutex_unlock(&kvm->slots_lock);
8053
8054 return r;
8055 }
8056 EXPORT_SYMBOL_GPL(x86_set_memory_region);
8057
8058 void kvm_arch_destroy_vm(struct kvm *kvm)
8059 {
8060 if (current->mm == kvm->mm) {
8061 /*
8062 * Free memory regions allocated on behalf of userspace,
8063 * unless the the memory map has changed due to process exit
8064 * or fd copying.
8065 */
8066 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8067 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8068 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8069 }
8070 if (kvm_x86_ops->vm_destroy)
8071 kvm_x86_ops->vm_destroy(kvm);
8072 kvm_iommu_unmap_guest(kvm);
8073 kfree(kvm->arch.vpic);
8074 kfree(kvm->arch.vioapic);
8075 kvm_free_vcpus(kvm);
8076 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8077 kvm_mmu_uninit_vm(kvm);
8078 }
8079
8080 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8081 struct kvm_memory_slot *dont)
8082 {
8083 int i;
8084
8085 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8086 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8087 kvfree(free->arch.rmap[i]);
8088 free->arch.rmap[i] = NULL;
8089 }
8090 if (i == 0)
8091 continue;
8092
8093 if (!dont || free->arch.lpage_info[i - 1] !=
8094 dont->arch.lpage_info[i - 1]) {
8095 kvfree(free->arch.lpage_info[i - 1]);
8096 free->arch.lpage_info[i - 1] = NULL;
8097 }
8098 }
8099
8100 kvm_page_track_free_memslot(free, dont);
8101 }
8102
8103 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8104 unsigned long npages)
8105 {
8106 int i;
8107
8108 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8109 struct kvm_lpage_info *linfo;
8110 unsigned long ugfn;
8111 int lpages;
8112 int level = i + 1;
8113
8114 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8115 slot->base_gfn, level) + 1;
8116
8117 slot->arch.rmap[i] =
8118 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8119 if (!slot->arch.rmap[i])
8120 goto out_free;
8121 if (i == 0)
8122 continue;
8123
8124 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8125 if (!linfo)
8126 goto out_free;
8127
8128 slot->arch.lpage_info[i - 1] = linfo;
8129
8130 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8131 linfo[0].disallow_lpage = 1;
8132 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8133 linfo[lpages - 1].disallow_lpage = 1;
8134 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8135 /*
8136 * If the gfn and userspace address are not aligned wrt each
8137 * other, or if explicitly asked to, disable large page
8138 * support for this slot
8139 */
8140 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8141 !kvm_largepages_enabled()) {
8142 unsigned long j;
8143
8144 for (j = 0; j < lpages; ++j)
8145 linfo[j].disallow_lpage = 1;
8146 }
8147 }
8148
8149 if (kvm_page_track_create_memslot(slot, npages))
8150 goto out_free;
8151
8152 return 0;
8153
8154 out_free:
8155 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8156 kvfree(slot->arch.rmap[i]);
8157 slot->arch.rmap[i] = NULL;
8158 if (i == 0)
8159 continue;
8160
8161 kvfree(slot->arch.lpage_info[i - 1]);
8162 slot->arch.lpage_info[i - 1] = NULL;
8163 }
8164 return -ENOMEM;
8165 }
8166
8167 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8168 {
8169 /*
8170 * memslots->generation has been incremented.
8171 * mmio generation may have reached its maximum value.
8172 */
8173 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8174 }
8175
8176 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8177 struct kvm_memory_slot *memslot,
8178 const struct kvm_userspace_memory_region *mem,
8179 enum kvm_mr_change change)
8180 {
8181 return 0;
8182 }
8183
8184 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8185 struct kvm_memory_slot *new)
8186 {
8187 /* Still write protect RO slot */
8188 if (new->flags & KVM_MEM_READONLY) {
8189 kvm_mmu_slot_remove_write_access(kvm, new);
8190 return;
8191 }
8192
8193 /*
8194 * Call kvm_x86_ops dirty logging hooks when they are valid.
8195 *
8196 * kvm_x86_ops->slot_disable_log_dirty is called when:
8197 *
8198 * - KVM_MR_CREATE with dirty logging is disabled
8199 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8200 *
8201 * The reason is, in case of PML, we need to set D-bit for any slots
8202 * with dirty logging disabled in order to eliminate unnecessary GPA
8203 * logging in PML buffer (and potential PML buffer full VMEXT). This
8204 * guarantees leaving PML enabled during guest's lifetime won't have
8205 * any additonal overhead from PML when guest is running with dirty
8206 * logging disabled for memory slots.
8207 *
8208 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8209 * to dirty logging mode.
8210 *
8211 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8212 *
8213 * In case of write protect:
8214 *
8215 * Write protect all pages for dirty logging.
8216 *
8217 * All the sptes including the large sptes which point to this
8218 * slot are set to readonly. We can not create any new large
8219 * spte on this slot until the end of the logging.
8220 *
8221 * See the comments in fast_page_fault().
8222 */
8223 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8224 if (kvm_x86_ops->slot_enable_log_dirty)
8225 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8226 else
8227 kvm_mmu_slot_remove_write_access(kvm, new);
8228 } else {
8229 if (kvm_x86_ops->slot_disable_log_dirty)
8230 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8231 }
8232 }
8233
8234 void kvm_arch_commit_memory_region(struct kvm *kvm,
8235 const struct kvm_userspace_memory_region *mem,
8236 const struct kvm_memory_slot *old,
8237 const struct kvm_memory_slot *new,
8238 enum kvm_mr_change change)
8239 {
8240 int nr_mmu_pages = 0;
8241
8242 if (!kvm->arch.n_requested_mmu_pages)
8243 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8244
8245 if (nr_mmu_pages)
8246 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8247
8248 /*
8249 * Dirty logging tracks sptes in 4k granularity, meaning that large
8250 * sptes have to be split. If live migration is successful, the guest
8251 * in the source machine will be destroyed and large sptes will be
8252 * created in the destination. However, if the guest continues to run
8253 * in the source machine (for example if live migration fails), small
8254 * sptes will remain around and cause bad performance.
8255 *
8256 * Scan sptes if dirty logging has been stopped, dropping those
8257 * which can be collapsed into a single large-page spte. Later
8258 * page faults will create the large-page sptes.
8259 */
8260 if ((change != KVM_MR_DELETE) &&
8261 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8262 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8263 kvm_mmu_zap_collapsible_sptes(kvm, new);
8264
8265 /*
8266 * Set up write protection and/or dirty logging for the new slot.
8267 *
8268 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8269 * been zapped so no dirty logging staff is needed for old slot. For
8270 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8271 * new and it's also covered when dealing with the new slot.
8272 *
8273 * FIXME: const-ify all uses of struct kvm_memory_slot.
8274 */
8275 if (change != KVM_MR_DELETE)
8276 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8277 }
8278
8279 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8280 {
8281 kvm_mmu_invalidate_zap_all_pages(kvm);
8282 }
8283
8284 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8285 struct kvm_memory_slot *slot)
8286 {
8287 kvm_page_track_flush_slot(kvm, slot);
8288 }
8289
8290 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8291 {
8292 if (!list_empty_careful(&vcpu->async_pf.done))
8293 return true;
8294
8295 if (kvm_apic_has_events(vcpu))
8296 return true;
8297
8298 if (vcpu->arch.pv.pv_unhalted)
8299 return true;
8300
8301 if (atomic_read(&vcpu->arch.nmi_queued))
8302 return true;
8303
8304 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8305 return true;
8306
8307 if (kvm_arch_interrupt_allowed(vcpu) &&
8308 kvm_cpu_has_interrupt(vcpu))
8309 return true;
8310
8311 if (kvm_hv_has_stimer_pending(vcpu))
8312 return true;
8313
8314 return false;
8315 }
8316
8317 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8318 {
8319 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8320 kvm_x86_ops->check_nested_events(vcpu, false);
8321
8322 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8323 }
8324
8325 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8326 {
8327 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8328 }
8329
8330 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8331 {
8332 return kvm_x86_ops->interrupt_allowed(vcpu);
8333 }
8334
8335 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8336 {
8337 if (is_64_bit_mode(vcpu))
8338 return kvm_rip_read(vcpu);
8339 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8340 kvm_rip_read(vcpu));
8341 }
8342 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8343
8344 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8345 {
8346 return kvm_get_linear_rip(vcpu) == linear_rip;
8347 }
8348 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8349
8350 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8351 {
8352 unsigned long rflags;
8353
8354 rflags = kvm_x86_ops->get_rflags(vcpu);
8355 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8356 rflags &= ~X86_EFLAGS_TF;
8357 return rflags;
8358 }
8359 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8360
8361 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8362 {
8363 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8364 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8365 rflags |= X86_EFLAGS_TF;
8366 kvm_x86_ops->set_rflags(vcpu, rflags);
8367 }
8368
8369 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8370 {
8371 __kvm_set_rflags(vcpu, rflags);
8372 kvm_make_request(KVM_REQ_EVENT, vcpu);
8373 }
8374 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8375
8376 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8377 {
8378 int r;
8379
8380 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8381 work->wakeup_all)
8382 return;
8383
8384 r = kvm_mmu_reload(vcpu);
8385 if (unlikely(r))
8386 return;
8387
8388 if (!vcpu->arch.mmu.direct_map &&
8389 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8390 return;
8391
8392 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8393 }
8394
8395 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8396 {
8397 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8398 }
8399
8400 static inline u32 kvm_async_pf_next_probe(u32 key)
8401 {
8402 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8403 }
8404
8405 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8406 {
8407 u32 key = kvm_async_pf_hash_fn(gfn);
8408
8409 while (vcpu->arch.apf.gfns[key] != ~0)
8410 key = kvm_async_pf_next_probe(key);
8411
8412 vcpu->arch.apf.gfns[key] = gfn;
8413 }
8414
8415 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8416 {
8417 int i;
8418 u32 key = kvm_async_pf_hash_fn(gfn);
8419
8420 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8421 (vcpu->arch.apf.gfns[key] != gfn &&
8422 vcpu->arch.apf.gfns[key] != ~0); i++)
8423 key = kvm_async_pf_next_probe(key);
8424
8425 return key;
8426 }
8427
8428 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8429 {
8430 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8431 }
8432
8433 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8434 {
8435 u32 i, j, k;
8436
8437 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8438 while (true) {
8439 vcpu->arch.apf.gfns[i] = ~0;
8440 do {
8441 j = kvm_async_pf_next_probe(j);
8442 if (vcpu->arch.apf.gfns[j] == ~0)
8443 return;
8444 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8445 /*
8446 * k lies cyclically in ]i,j]
8447 * | i.k.j |
8448 * |....j i.k.| or |.k..j i...|
8449 */
8450 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8451 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8452 i = j;
8453 }
8454 }
8455
8456 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8457 {
8458
8459 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8460 sizeof(val));
8461 }
8462
8463 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8464 struct kvm_async_pf *work)
8465 {
8466 struct x86_exception fault;
8467
8468 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8469 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8470
8471 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8472 (vcpu->arch.apf.send_user_only &&
8473 kvm_x86_ops->get_cpl(vcpu) == 0))
8474 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8475 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8476 fault.vector = PF_VECTOR;
8477 fault.error_code_valid = true;
8478 fault.error_code = 0;
8479 fault.nested_page_fault = false;
8480 fault.address = work->arch.token;
8481 kvm_inject_page_fault(vcpu, &fault);
8482 }
8483 }
8484
8485 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8486 struct kvm_async_pf *work)
8487 {
8488 struct x86_exception fault;
8489
8490 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8491 if (work->wakeup_all)
8492 work->arch.token = ~0; /* broadcast wakeup */
8493 else
8494 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8495
8496 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8497 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8498 fault.vector = PF_VECTOR;
8499 fault.error_code_valid = true;
8500 fault.error_code = 0;
8501 fault.nested_page_fault = false;
8502 fault.address = work->arch.token;
8503 kvm_inject_page_fault(vcpu, &fault);
8504 }
8505 vcpu->arch.apf.halted = false;
8506 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8507 }
8508
8509 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8510 {
8511 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8512 return true;
8513 else
8514 return !kvm_event_needs_reinjection(vcpu) &&
8515 kvm_x86_ops->interrupt_allowed(vcpu);
8516 }
8517
8518 void kvm_arch_start_assignment(struct kvm *kvm)
8519 {
8520 atomic_inc(&kvm->arch.assigned_device_count);
8521 }
8522 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8523
8524 void kvm_arch_end_assignment(struct kvm *kvm)
8525 {
8526 atomic_dec(&kvm->arch.assigned_device_count);
8527 }
8528 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8529
8530 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8531 {
8532 return atomic_read(&kvm->arch.assigned_device_count);
8533 }
8534 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8535
8536 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8537 {
8538 atomic_inc(&kvm->arch.noncoherent_dma_count);
8539 }
8540 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8541
8542 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8543 {
8544 atomic_dec(&kvm->arch.noncoherent_dma_count);
8545 }
8546 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8547
8548 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8549 {
8550 return atomic_read(&kvm->arch.noncoherent_dma_count);
8551 }
8552 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8553
8554 bool kvm_arch_has_irq_bypass(void)
8555 {
8556 return kvm_x86_ops->update_pi_irte != NULL;
8557 }
8558
8559 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8560 struct irq_bypass_producer *prod)
8561 {
8562 struct kvm_kernel_irqfd *irqfd =
8563 container_of(cons, struct kvm_kernel_irqfd, consumer);
8564
8565 irqfd->producer = prod;
8566
8567 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8568 prod->irq, irqfd->gsi, 1);
8569 }
8570
8571 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8572 struct irq_bypass_producer *prod)
8573 {
8574 int ret;
8575 struct kvm_kernel_irqfd *irqfd =
8576 container_of(cons, struct kvm_kernel_irqfd, consumer);
8577
8578 WARN_ON(irqfd->producer != prod);
8579 irqfd->producer = NULL;
8580
8581 /*
8582 * When producer of consumer is unregistered, we change back to
8583 * remapped mode, so we can re-use the current implementation
8584 * when the irq is masked/disabled or the consumer side (KVM
8585 * int this case doesn't want to receive the interrupts.
8586 */
8587 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8588 if (ret)
8589 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8590 " fails: %d\n", irqfd->consumer.token, ret);
8591 }
8592
8593 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8594 uint32_t guest_irq, bool set)
8595 {
8596 if (!kvm_x86_ops->update_pi_irte)
8597 return -EINVAL;
8598
8599 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8600 }
8601
8602 bool kvm_vector_hashing_enabled(void)
8603 {
8604 return vector_hashing;
8605 }
8606 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8607
8608 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8609 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8610 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8611 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8612 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8613 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8614 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8615 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8616 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8617 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8618 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8619 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8620 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8621 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8622 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8623 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8624 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8625 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8626 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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