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KVM: x86: Remove obsolete disabling of page faults in kvm_arch_vcpu_put()
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19 #include <linux/kvm_host.h>
20 #include "irq.h"
21 #include "ioapic.h"
22 #include "mmu.h"
23 #include "i8254.h"
24 #include "tss.h"
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
27 #include "x86.h"
28 #include "cpuid.h"
29 #include "pmu.h"
30 #include "hyperv.h"
31 #include "lapic.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
60
61 #include <trace/events/kvm.h>
62
63 #include <asm/debugreg.h>
64 #include <asm/msr.h>
65 #include <asm/desc.h>
66 #include <asm/mce.h>
67 #include <linux/kernel_stat.h>
68 #include <asm/fpu/internal.h> /* Ugh! */
69 #include <asm/pvclock.h>
70 #include <asm/div64.h>
71 #include <asm/irq_remapping.h>
72 #include <asm/mshyperv.h>
73 #include <asm/hypervisor.h>
74 #include <asm/tlbflush.h>
75 #include <asm/intel_pt.h>
76 #include <asm/emulate_prefix.h>
77 #include <clocksource/hyperv_timer.h>
78
79 #define CREATE_TRACE_POINTS
80 #include "trace.h"
81
82 #define MAX_IO_MSRS 256
83 #define KVM_MAX_MCE_BANKS 32
84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
86
87 #define emul_to_vcpu(ctxt) \
88 ((struct kvm_vcpu *)(ctxt)->vcpu)
89
90 /* EFER defaults:
91 * - enable syscall per default because its emulated by KVM
92 * - enable LME and LMA per default on 64 bit KVM
93 */
94 #ifdef CONFIG_X86_64
95 static
96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
97 #else
98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
99 #endif
100
101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
102
103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
105
106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
107 static void process_nmi(struct kvm_vcpu *vcpu);
108 static void process_smi(struct kvm_vcpu *vcpu);
109 static void enter_smm(struct kvm_vcpu *vcpu);
110 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
111 static void store_regs(struct kvm_vcpu *vcpu);
112 static int sync_regs(struct kvm_vcpu *vcpu);
113
114 struct kvm_x86_ops kvm_x86_ops __read_mostly;
115 EXPORT_SYMBOL_GPL(kvm_x86_ops);
116
117 static bool __read_mostly ignore_msrs = 0;
118 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
119
120 static bool __read_mostly report_ignored_msrs = true;
121 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
122
123 unsigned int min_timer_period_us = 200;
124 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
125
126 static bool __read_mostly kvmclock_periodic_sync = true;
127 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
128
129 bool __read_mostly kvm_has_tsc_control;
130 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
131 u32 __read_mostly kvm_max_guest_tsc_khz;
132 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
133 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
134 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
135 u64 __read_mostly kvm_max_tsc_scaling_ratio;
136 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
137 u64 __read_mostly kvm_default_tsc_scaling_ratio;
138 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
139
140 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
141 static u32 __read_mostly tsc_tolerance_ppm = 250;
142 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
143
144 /*
145 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
146 * adaptive tuning starting from default advancment of 1000ns. '0' disables
147 * advancement entirely. Any other value is used as-is and disables adaptive
148 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
149 */
150 static int __read_mostly lapic_timer_advance_ns = -1;
151 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
152
153 static bool __read_mostly vector_hashing = true;
154 module_param(vector_hashing, bool, S_IRUGO);
155
156 bool __read_mostly enable_vmware_backdoor = false;
157 module_param(enable_vmware_backdoor, bool, S_IRUGO);
158 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
159
160 static bool __read_mostly force_emulation_prefix = false;
161 module_param(force_emulation_prefix, bool, S_IRUGO);
162
163 int __read_mostly pi_inject_timer = -1;
164 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
165
166 /*
167 * Restoring the host value for MSRs that are only consumed when running in
168 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
169 * returns to userspace, i.e. the kernel can run with the guest's value.
170 */
171 #define KVM_MAX_NR_USER_RETURN_MSRS 16
172
173 struct kvm_user_return_msrs_global {
174 int nr;
175 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
176 };
177
178 struct kvm_user_return_msrs {
179 struct user_return_notifier urn;
180 bool registered;
181 struct kvm_user_return_msr_values {
182 u64 host;
183 u64 curr;
184 } values[KVM_MAX_NR_USER_RETURN_MSRS];
185 };
186
187 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
188 static struct kvm_user_return_msrs __percpu *user_return_msrs;
189
190 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
191 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
192 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
193 | XFEATURE_MASK_PKRU)
194
195 u64 __read_mostly host_efer;
196 EXPORT_SYMBOL_GPL(host_efer);
197
198 bool __read_mostly allow_smaller_maxphyaddr = 0;
199 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
200
201 u64 __read_mostly host_xss;
202 EXPORT_SYMBOL_GPL(host_xss);
203 u64 __read_mostly supported_xss;
204 EXPORT_SYMBOL_GPL(supported_xss);
205
206 struct kvm_stats_debugfs_item debugfs_entries[] = {
207 VCPU_STAT("pf_fixed", pf_fixed),
208 VCPU_STAT("pf_guest", pf_guest),
209 VCPU_STAT("tlb_flush", tlb_flush),
210 VCPU_STAT("invlpg", invlpg),
211 VCPU_STAT("exits", exits),
212 VCPU_STAT("io_exits", io_exits),
213 VCPU_STAT("mmio_exits", mmio_exits),
214 VCPU_STAT("signal_exits", signal_exits),
215 VCPU_STAT("irq_window", irq_window_exits),
216 VCPU_STAT("nmi_window", nmi_window_exits),
217 VCPU_STAT("halt_exits", halt_exits),
218 VCPU_STAT("halt_successful_poll", halt_successful_poll),
219 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
220 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
221 VCPU_STAT("halt_wakeup", halt_wakeup),
222 VCPU_STAT("hypercalls", hypercalls),
223 VCPU_STAT("request_irq", request_irq_exits),
224 VCPU_STAT("irq_exits", irq_exits),
225 VCPU_STAT("host_state_reload", host_state_reload),
226 VCPU_STAT("fpu_reload", fpu_reload),
227 VCPU_STAT("insn_emulation", insn_emulation),
228 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
229 VCPU_STAT("irq_injections", irq_injections),
230 VCPU_STAT("nmi_injections", nmi_injections),
231 VCPU_STAT("req_event", req_event),
232 VCPU_STAT("l1d_flush", l1d_flush),
233 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
234 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
235 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
236 VM_STAT("mmu_pte_write", mmu_pte_write),
237 VM_STAT("mmu_pte_updated", mmu_pte_updated),
238 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
239 VM_STAT("mmu_flooded", mmu_flooded),
240 VM_STAT("mmu_recycled", mmu_recycled),
241 VM_STAT("mmu_cache_miss", mmu_cache_miss),
242 VM_STAT("mmu_unsync", mmu_unsync),
243 VM_STAT("remote_tlb_flush", remote_tlb_flush),
244 VM_STAT("largepages", lpages, .mode = 0444),
245 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
246 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
247 { NULL }
248 };
249
250 u64 __read_mostly host_xcr0;
251 u64 __read_mostly supported_xcr0;
252 EXPORT_SYMBOL_GPL(supported_xcr0);
253
254 static struct kmem_cache *x86_fpu_cache;
255
256 static struct kmem_cache *x86_emulator_cache;
257
258 /*
259 * When called, it means the previous get/set msr reached an invalid msr.
260 * Return true if we want to ignore/silent this failed msr access.
261 */
262 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
263 u64 data, bool write)
264 {
265 const char *op = write ? "wrmsr" : "rdmsr";
266
267 if (ignore_msrs) {
268 if (report_ignored_msrs)
269 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
270 op, msr, data);
271 /* Mask the error */
272 return true;
273 } else {
274 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
275 op, msr, data);
276 return false;
277 }
278 }
279
280 static struct kmem_cache *kvm_alloc_emulator_cache(void)
281 {
282 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
283 unsigned int size = sizeof(struct x86_emulate_ctxt);
284
285 return kmem_cache_create_usercopy("x86_emulator", size,
286 __alignof__(struct x86_emulate_ctxt),
287 SLAB_ACCOUNT, useroffset,
288 size - useroffset, NULL);
289 }
290
291 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
292
293 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
294 {
295 int i;
296 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
297 vcpu->arch.apf.gfns[i] = ~0;
298 }
299
300 static void kvm_on_user_return(struct user_return_notifier *urn)
301 {
302 unsigned slot;
303 struct kvm_user_return_msrs *msrs
304 = container_of(urn, struct kvm_user_return_msrs, urn);
305 struct kvm_user_return_msr_values *values;
306 unsigned long flags;
307
308 /*
309 * Disabling irqs at this point since the following code could be
310 * interrupted and executed through kvm_arch_hardware_disable()
311 */
312 local_irq_save(flags);
313 if (msrs->registered) {
314 msrs->registered = false;
315 user_return_notifier_unregister(urn);
316 }
317 local_irq_restore(flags);
318 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
319 values = &msrs->values[slot];
320 if (values->host != values->curr) {
321 wrmsrl(user_return_msrs_global.msrs[slot], values->host);
322 values->curr = values->host;
323 }
324 }
325 }
326
327 void kvm_define_user_return_msr(unsigned slot, u32 msr)
328 {
329 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
330 user_return_msrs_global.msrs[slot] = msr;
331 if (slot >= user_return_msrs_global.nr)
332 user_return_msrs_global.nr = slot + 1;
333 }
334 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
335
336 static void kvm_user_return_msr_cpu_online(void)
337 {
338 unsigned int cpu = smp_processor_id();
339 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
340 u64 value;
341 int i;
342
343 for (i = 0; i < user_return_msrs_global.nr; ++i) {
344 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
345 msrs->values[i].host = value;
346 msrs->values[i].curr = value;
347 }
348 }
349
350 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
351 {
352 unsigned int cpu = smp_processor_id();
353 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
354 int err;
355
356 value = (value & mask) | (msrs->values[slot].host & ~mask);
357 if (value == msrs->values[slot].curr)
358 return 0;
359 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
360 if (err)
361 return 1;
362
363 msrs->values[slot].curr = value;
364 if (!msrs->registered) {
365 msrs->urn.on_user_return = kvm_on_user_return;
366 user_return_notifier_register(&msrs->urn);
367 msrs->registered = true;
368 }
369 return 0;
370 }
371 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
372
373 static void drop_user_return_notifiers(void)
374 {
375 unsigned int cpu = smp_processor_id();
376 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
377
378 if (msrs->registered)
379 kvm_on_user_return(&msrs->urn);
380 }
381
382 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
383 {
384 return vcpu->arch.apic_base;
385 }
386 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
387
388 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
389 {
390 return kvm_apic_mode(kvm_get_apic_base(vcpu));
391 }
392 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
393
394 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
395 {
396 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
397 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
398 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
399 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
400
401 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
402 return 1;
403 if (!msr_info->host_initiated) {
404 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
405 return 1;
406 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
407 return 1;
408 }
409
410 kvm_lapic_set_base(vcpu, msr_info->data);
411 kvm_recalculate_apic_map(vcpu->kvm);
412 return 0;
413 }
414 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
415
416 asmlinkage __visible noinstr void kvm_spurious_fault(void)
417 {
418 /* Fault while not rebooting. We want the trace. */
419 BUG_ON(!kvm_rebooting);
420 }
421 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
422
423 #define EXCPT_BENIGN 0
424 #define EXCPT_CONTRIBUTORY 1
425 #define EXCPT_PF 2
426
427 static int exception_class(int vector)
428 {
429 switch (vector) {
430 case PF_VECTOR:
431 return EXCPT_PF;
432 case DE_VECTOR:
433 case TS_VECTOR:
434 case NP_VECTOR:
435 case SS_VECTOR:
436 case GP_VECTOR:
437 return EXCPT_CONTRIBUTORY;
438 default:
439 break;
440 }
441 return EXCPT_BENIGN;
442 }
443
444 #define EXCPT_FAULT 0
445 #define EXCPT_TRAP 1
446 #define EXCPT_ABORT 2
447 #define EXCPT_INTERRUPT 3
448
449 static int exception_type(int vector)
450 {
451 unsigned int mask;
452
453 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
454 return EXCPT_INTERRUPT;
455
456 mask = 1 << vector;
457
458 /* #DB is trap, as instruction watchpoints are handled elsewhere */
459 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
460 return EXCPT_TRAP;
461
462 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
463 return EXCPT_ABORT;
464
465 /* Reserved exceptions will result in fault */
466 return EXCPT_FAULT;
467 }
468
469 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
470 {
471 unsigned nr = vcpu->arch.exception.nr;
472 bool has_payload = vcpu->arch.exception.has_payload;
473 unsigned long payload = vcpu->arch.exception.payload;
474
475 if (!has_payload)
476 return;
477
478 switch (nr) {
479 case DB_VECTOR:
480 /*
481 * "Certain debug exceptions may clear bit 0-3. The
482 * remaining contents of the DR6 register are never
483 * cleared by the processor".
484 */
485 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
486 /*
487 * DR6.RTM is set by all #DB exceptions that don't clear it.
488 */
489 vcpu->arch.dr6 |= DR6_RTM;
490 vcpu->arch.dr6 |= payload;
491 /*
492 * Bit 16 should be set in the payload whenever the #DB
493 * exception should clear DR6.RTM. This makes the payload
494 * compatible with the pending debug exceptions under VMX.
495 * Though not currently documented in the SDM, this also
496 * makes the payload compatible with the exit qualification
497 * for #DB exceptions under VMX.
498 */
499 vcpu->arch.dr6 ^= payload & DR6_RTM;
500
501 /*
502 * The #DB payload is defined as compatible with the 'pending
503 * debug exceptions' field under VMX, not DR6. While bit 12 is
504 * defined in the 'pending debug exceptions' field (enabled
505 * breakpoint), it is reserved and must be zero in DR6.
506 */
507 vcpu->arch.dr6 &= ~BIT(12);
508 break;
509 case PF_VECTOR:
510 vcpu->arch.cr2 = payload;
511 break;
512 }
513
514 vcpu->arch.exception.has_payload = false;
515 vcpu->arch.exception.payload = 0;
516 }
517 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
518
519 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
520 unsigned nr, bool has_error, u32 error_code,
521 bool has_payload, unsigned long payload, bool reinject)
522 {
523 u32 prev_nr;
524 int class1, class2;
525
526 kvm_make_request(KVM_REQ_EVENT, vcpu);
527
528 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
529 queue:
530 if (has_error && !is_protmode(vcpu))
531 has_error = false;
532 if (reinject) {
533 /*
534 * On vmentry, vcpu->arch.exception.pending is only
535 * true if an event injection was blocked by
536 * nested_run_pending. In that case, however,
537 * vcpu_enter_guest requests an immediate exit,
538 * and the guest shouldn't proceed far enough to
539 * need reinjection.
540 */
541 WARN_ON_ONCE(vcpu->arch.exception.pending);
542 vcpu->arch.exception.injected = true;
543 if (WARN_ON_ONCE(has_payload)) {
544 /*
545 * A reinjected event has already
546 * delivered its payload.
547 */
548 has_payload = false;
549 payload = 0;
550 }
551 } else {
552 vcpu->arch.exception.pending = true;
553 vcpu->arch.exception.injected = false;
554 }
555 vcpu->arch.exception.has_error_code = has_error;
556 vcpu->arch.exception.nr = nr;
557 vcpu->arch.exception.error_code = error_code;
558 vcpu->arch.exception.has_payload = has_payload;
559 vcpu->arch.exception.payload = payload;
560 if (!is_guest_mode(vcpu))
561 kvm_deliver_exception_payload(vcpu);
562 return;
563 }
564
565 /* to check exception */
566 prev_nr = vcpu->arch.exception.nr;
567 if (prev_nr == DF_VECTOR) {
568 /* triple fault -> shutdown */
569 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
570 return;
571 }
572 class1 = exception_class(prev_nr);
573 class2 = exception_class(nr);
574 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
575 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
576 /*
577 * Generate double fault per SDM Table 5-5. Set
578 * exception.pending = true so that the double fault
579 * can trigger a nested vmexit.
580 */
581 vcpu->arch.exception.pending = true;
582 vcpu->arch.exception.injected = false;
583 vcpu->arch.exception.has_error_code = true;
584 vcpu->arch.exception.nr = DF_VECTOR;
585 vcpu->arch.exception.error_code = 0;
586 vcpu->arch.exception.has_payload = false;
587 vcpu->arch.exception.payload = 0;
588 } else
589 /* replace previous exception with a new one in a hope
590 that instruction re-execution will regenerate lost
591 exception */
592 goto queue;
593 }
594
595 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
596 {
597 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
598 }
599 EXPORT_SYMBOL_GPL(kvm_queue_exception);
600
601 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
602 {
603 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
604 }
605 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
606
607 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
608 unsigned long payload)
609 {
610 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
611 }
612 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
613
614 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
615 u32 error_code, unsigned long payload)
616 {
617 kvm_multiple_exception(vcpu, nr, true, error_code,
618 true, payload, false);
619 }
620
621 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
622 {
623 if (err)
624 kvm_inject_gp(vcpu, 0);
625 else
626 return kvm_skip_emulated_instruction(vcpu);
627
628 return 1;
629 }
630 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
631
632 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
633 {
634 ++vcpu->stat.pf_guest;
635 vcpu->arch.exception.nested_apf =
636 is_guest_mode(vcpu) && fault->async_page_fault;
637 if (vcpu->arch.exception.nested_apf) {
638 vcpu->arch.apf.nested_apf_token = fault->address;
639 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
640 } else {
641 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
642 fault->address);
643 }
644 }
645 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
646
647 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
648 struct x86_exception *fault)
649 {
650 struct kvm_mmu *fault_mmu;
651 WARN_ON_ONCE(fault->vector != PF_VECTOR);
652
653 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
654 vcpu->arch.walk_mmu;
655
656 /*
657 * Invalidate the TLB entry for the faulting address, if it exists,
658 * else the access will fault indefinitely (and to emulate hardware).
659 */
660 if ((fault->error_code & PFERR_PRESENT_MASK) &&
661 !(fault->error_code & PFERR_RSVD_MASK))
662 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
663 fault_mmu->root_hpa);
664
665 fault_mmu->inject_page_fault(vcpu, fault);
666 return fault->nested_page_fault;
667 }
668 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
669
670 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
671 {
672 atomic_inc(&vcpu->arch.nmi_queued);
673 kvm_make_request(KVM_REQ_NMI, vcpu);
674 }
675 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
676
677 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
678 {
679 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
680 }
681 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
682
683 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
684 {
685 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
686 }
687 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
688
689 /*
690 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
691 * a #GP and return false.
692 */
693 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
694 {
695 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
696 return true;
697 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
698 return false;
699 }
700 EXPORT_SYMBOL_GPL(kvm_require_cpl);
701
702 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
703 {
704 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return true;
706
707 kvm_queue_exception(vcpu, UD_VECTOR);
708 return false;
709 }
710 EXPORT_SYMBOL_GPL(kvm_require_dr);
711
712 /*
713 * This function will be used to read from the physical memory of the currently
714 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
715 * can read from guest physical or from the guest's guest physical memory.
716 */
717 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
718 gfn_t ngfn, void *data, int offset, int len,
719 u32 access)
720 {
721 struct x86_exception exception;
722 gfn_t real_gfn;
723 gpa_t ngpa;
724
725 ngpa = gfn_to_gpa(ngfn);
726 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
727 if (real_gfn == UNMAPPED_GVA)
728 return -EFAULT;
729
730 real_gfn = gpa_to_gfn(real_gfn);
731
732 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
733 }
734 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
735
736 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
737 void *data, int offset, int len, u32 access)
738 {
739 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
740 data, offset, len, access);
741 }
742
743 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
744 {
745 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
746 rsvd_bits(1, 2);
747 }
748
749 /*
750 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
751 */
752 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
753 {
754 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
755 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
756 int i;
757 int ret;
758 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
759
760 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
761 offset * sizeof(u64), sizeof(pdpte),
762 PFERR_USER_MASK|PFERR_WRITE_MASK);
763 if (ret < 0) {
764 ret = 0;
765 goto out;
766 }
767 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
768 if ((pdpte[i] & PT_PRESENT_MASK) &&
769 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
770 ret = 0;
771 goto out;
772 }
773 }
774 ret = 1;
775
776 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
777 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
778
779 out:
780
781 return ret;
782 }
783 EXPORT_SYMBOL_GPL(load_pdptrs);
784
785 bool pdptrs_changed(struct kvm_vcpu *vcpu)
786 {
787 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
788 int offset;
789 gfn_t gfn;
790 int r;
791
792 if (!is_pae_paging(vcpu))
793 return false;
794
795 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
796 return true;
797
798 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
799 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
800 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
801 PFERR_USER_MASK | PFERR_WRITE_MASK);
802 if (r < 0)
803 return true;
804
805 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
806 }
807 EXPORT_SYMBOL_GPL(pdptrs_changed);
808
809 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
810 {
811 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
812
813 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
814 kvm_clear_async_pf_completion_queue(vcpu);
815 kvm_async_pf_hash_reset(vcpu);
816 }
817
818 if ((cr0 ^ old_cr0) & update_bits)
819 kvm_mmu_reset_context(vcpu);
820
821 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
822 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
823 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
824 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
825 }
826 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
827
828 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
829 {
830 unsigned long old_cr0 = kvm_read_cr0(vcpu);
831 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
832
833 cr0 |= X86_CR0_ET;
834
835 #ifdef CONFIG_X86_64
836 if (cr0 & 0xffffffff00000000UL)
837 return 1;
838 #endif
839
840 cr0 &= ~CR0_RESERVED_BITS;
841
842 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
843 return 1;
844
845 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
846 return 1;
847
848 #ifdef CONFIG_X86_64
849 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
850 (cr0 & X86_CR0_PG)) {
851 int cs_db, cs_l;
852
853 if (!is_pae(vcpu))
854 return 1;
855 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
856 if (cs_l)
857 return 1;
858 }
859 #endif
860 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
861 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
862 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
863 return 1;
864
865 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
866 return 1;
867
868 kvm_x86_ops.set_cr0(vcpu, cr0);
869
870 kvm_post_set_cr0(vcpu, old_cr0, cr0);
871
872 return 0;
873 }
874 EXPORT_SYMBOL_GPL(kvm_set_cr0);
875
876 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
877 {
878 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
879 }
880 EXPORT_SYMBOL_GPL(kvm_lmsw);
881
882 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
883 {
884 if (vcpu->arch.guest_state_protected)
885 return;
886
887 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
888
889 if (vcpu->arch.xcr0 != host_xcr0)
890 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
891
892 if (vcpu->arch.xsaves_enabled &&
893 vcpu->arch.ia32_xss != host_xss)
894 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
895 }
896
897 if (static_cpu_has(X86_FEATURE_PKU) &&
898 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
899 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
900 vcpu->arch.pkru != vcpu->arch.host_pkru)
901 __write_pkru(vcpu->arch.pkru);
902 }
903 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
904
905 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
906 {
907 if (vcpu->arch.guest_state_protected)
908 return;
909
910 if (static_cpu_has(X86_FEATURE_PKU) &&
911 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
912 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
913 vcpu->arch.pkru = rdpkru();
914 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
915 __write_pkru(vcpu->arch.host_pkru);
916 }
917
918 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
919
920 if (vcpu->arch.xcr0 != host_xcr0)
921 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
922
923 if (vcpu->arch.xsaves_enabled &&
924 vcpu->arch.ia32_xss != host_xss)
925 wrmsrl(MSR_IA32_XSS, host_xss);
926 }
927
928 }
929 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
930
931 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
932 {
933 u64 xcr0 = xcr;
934 u64 old_xcr0 = vcpu->arch.xcr0;
935 u64 valid_bits;
936
937 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
938 if (index != XCR_XFEATURE_ENABLED_MASK)
939 return 1;
940 if (!(xcr0 & XFEATURE_MASK_FP))
941 return 1;
942 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
943 return 1;
944
945 /*
946 * Do not allow the guest to set bits that we do not support
947 * saving. However, xcr0 bit 0 is always set, even if the
948 * emulated CPU does not support XSAVE (see fx_init).
949 */
950 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
951 if (xcr0 & ~valid_bits)
952 return 1;
953
954 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
955 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
956 return 1;
957
958 if (xcr0 & XFEATURE_MASK_AVX512) {
959 if (!(xcr0 & XFEATURE_MASK_YMM))
960 return 1;
961 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
962 return 1;
963 }
964 vcpu->arch.xcr0 = xcr0;
965
966 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
967 kvm_update_cpuid_runtime(vcpu);
968 return 0;
969 }
970
971 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
972 {
973 if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
974 __kvm_set_xcr(vcpu, index, xcr)) {
975 kvm_inject_gp(vcpu, 0);
976 return 1;
977 }
978 return 0;
979 }
980 EXPORT_SYMBOL_GPL(kvm_set_xcr);
981
982 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
983 {
984 if (cr4 & cr4_reserved_bits)
985 return false;
986
987 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
988 return false;
989
990 return kvm_x86_ops.is_valid_cr4(vcpu, cr4);
991 }
992 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
993
994 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
995 {
996 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
997 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
998
999 if (((cr4 ^ old_cr4) & mmu_role_bits) ||
1000 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1001 kvm_mmu_reset_context(vcpu);
1002 }
1003 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1004
1005 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1006 {
1007 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1008 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
1009 X86_CR4_SMEP;
1010
1011 if (!kvm_is_valid_cr4(vcpu, cr4))
1012 return 1;
1013
1014 if (is_long_mode(vcpu)) {
1015 if (!(cr4 & X86_CR4_PAE))
1016 return 1;
1017 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1018 return 1;
1019 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1020 && ((cr4 ^ old_cr4) & pdptr_bits)
1021 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
1022 kvm_read_cr3(vcpu)))
1023 return 1;
1024
1025 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1026 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1027 return 1;
1028
1029 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1030 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1031 return 1;
1032 }
1033
1034 kvm_x86_ops.set_cr4(vcpu, cr4);
1035
1036 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1037
1038 return 0;
1039 }
1040 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1041
1042 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1043 {
1044 bool skip_tlb_flush = false;
1045 #ifdef CONFIG_X86_64
1046 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1047
1048 if (pcid_enabled) {
1049 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1050 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1051 }
1052 #endif
1053
1054 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1055 if (!skip_tlb_flush) {
1056 kvm_mmu_sync_roots(vcpu);
1057 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1058 }
1059 return 0;
1060 }
1061
1062 if (is_long_mode(vcpu) &&
1063 (cr3 & vcpu->arch.cr3_lm_rsvd_bits))
1064 return 1;
1065 else if (is_pae_paging(vcpu) &&
1066 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1067 return 1;
1068
1069 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1070 vcpu->arch.cr3 = cr3;
1071 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1072
1073 return 0;
1074 }
1075 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1076
1077 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1078 {
1079 if (cr8 & CR8_RESERVED_BITS)
1080 return 1;
1081 if (lapic_in_kernel(vcpu))
1082 kvm_lapic_set_tpr(vcpu, cr8);
1083 else
1084 vcpu->arch.cr8 = cr8;
1085 return 0;
1086 }
1087 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1088
1089 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1090 {
1091 if (lapic_in_kernel(vcpu))
1092 return kvm_lapic_get_cr8(vcpu);
1093 else
1094 return vcpu->arch.cr8;
1095 }
1096 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1097
1098 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1099 {
1100 int i;
1101
1102 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1103 for (i = 0; i < KVM_NR_DB_REGS; i++)
1104 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1105 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1106 }
1107 }
1108
1109 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1110 {
1111 unsigned long dr7;
1112
1113 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1114 dr7 = vcpu->arch.guest_debug_dr7;
1115 else
1116 dr7 = vcpu->arch.dr7;
1117 kvm_x86_ops.set_dr7(vcpu, dr7);
1118 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1119 if (dr7 & DR7_BP_EN_MASK)
1120 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1121 }
1122 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1123
1124 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1125 {
1126 u64 fixed = DR6_FIXED_1;
1127
1128 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1129 fixed |= DR6_RTM;
1130 return fixed;
1131 }
1132
1133 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1134 {
1135 size_t size = ARRAY_SIZE(vcpu->arch.db);
1136
1137 switch (dr) {
1138 case 0 ... 3:
1139 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1140 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1141 vcpu->arch.eff_db[dr] = val;
1142 break;
1143 case 4:
1144 case 6:
1145 if (!kvm_dr6_valid(val))
1146 return -1; /* #GP */
1147 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1148 break;
1149 case 5:
1150 default: /* 7 */
1151 if (!kvm_dr7_valid(val))
1152 return -1; /* #GP */
1153 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1154 kvm_update_dr7(vcpu);
1155 break;
1156 }
1157
1158 return 0;
1159 }
1160
1161 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1162 {
1163 if (__kvm_set_dr(vcpu, dr, val)) {
1164 kvm_inject_gp(vcpu, 0);
1165 return 1;
1166 }
1167 return 0;
1168 }
1169 EXPORT_SYMBOL_GPL(kvm_set_dr);
1170
1171 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1172 {
1173 size_t size = ARRAY_SIZE(vcpu->arch.db);
1174
1175 switch (dr) {
1176 case 0 ... 3:
1177 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1178 break;
1179 case 4:
1180 case 6:
1181 *val = vcpu->arch.dr6;
1182 break;
1183 case 5:
1184 default: /* 7 */
1185 *val = vcpu->arch.dr7;
1186 break;
1187 }
1188 return 0;
1189 }
1190 EXPORT_SYMBOL_GPL(kvm_get_dr);
1191
1192 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1193 {
1194 u32 ecx = kvm_rcx_read(vcpu);
1195 u64 data;
1196 int err;
1197
1198 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1199 if (err)
1200 return err;
1201 kvm_rax_write(vcpu, (u32)data);
1202 kvm_rdx_write(vcpu, data >> 32);
1203 return err;
1204 }
1205 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1206
1207 /*
1208 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1209 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1210 *
1211 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1212 * extract the supported MSRs from the related const lists.
1213 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1214 * capabilities of the host cpu. This capabilities test skips MSRs that are
1215 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1216 * may depend on host virtualization features rather than host cpu features.
1217 */
1218
1219 static const u32 msrs_to_save_all[] = {
1220 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1221 MSR_STAR,
1222 #ifdef CONFIG_X86_64
1223 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1224 #endif
1225 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1226 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1227 MSR_IA32_SPEC_CTRL,
1228 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1229 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1230 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1231 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1232 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1233 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1234 MSR_IA32_UMWAIT_CONTROL,
1235
1236 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1237 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1238 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1239 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1240 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1241 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1242 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1243 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1244 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1245 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1246 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1247 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1248 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1249 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1250 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1251 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1252 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1253 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1254 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1255 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1256 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1257 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1258 };
1259
1260 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1261 static unsigned num_msrs_to_save;
1262
1263 static const u32 emulated_msrs_all[] = {
1264 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1265 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1266 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1267 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1268 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1269 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1270 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1271 HV_X64_MSR_RESET,
1272 HV_X64_MSR_VP_INDEX,
1273 HV_X64_MSR_VP_RUNTIME,
1274 HV_X64_MSR_SCONTROL,
1275 HV_X64_MSR_STIMER0_CONFIG,
1276 HV_X64_MSR_VP_ASSIST_PAGE,
1277 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1278 HV_X64_MSR_TSC_EMULATION_STATUS,
1279 HV_X64_MSR_SYNDBG_OPTIONS,
1280 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1281 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1282 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1283
1284 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1285 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1286
1287 MSR_IA32_TSC_ADJUST,
1288 MSR_IA32_TSCDEADLINE,
1289 MSR_IA32_ARCH_CAPABILITIES,
1290 MSR_IA32_PERF_CAPABILITIES,
1291 MSR_IA32_MISC_ENABLE,
1292 MSR_IA32_MCG_STATUS,
1293 MSR_IA32_MCG_CTL,
1294 MSR_IA32_MCG_EXT_CTL,
1295 MSR_IA32_SMBASE,
1296 MSR_SMI_COUNT,
1297 MSR_PLATFORM_INFO,
1298 MSR_MISC_FEATURES_ENABLES,
1299 MSR_AMD64_VIRT_SPEC_CTRL,
1300 MSR_IA32_POWER_CTL,
1301 MSR_IA32_UCODE_REV,
1302
1303 /*
1304 * The following list leaves out MSRs whose values are determined
1305 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1306 * We always support the "true" VMX control MSRs, even if the host
1307 * processor does not, so I am putting these registers here rather
1308 * than in msrs_to_save_all.
1309 */
1310 MSR_IA32_VMX_BASIC,
1311 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1312 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1313 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1314 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1315 MSR_IA32_VMX_MISC,
1316 MSR_IA32_VMX_CR0_FIXED0,
1317 MSR_IA32_VMX_CR4_FIXED0,
1318 MSR_IA32_VMX_VMCS_ENUM,
1319 MSR_IA32_VMX_PROCBASED_CTLS2,
1320 MSR_IA32_VMX_EPT_VPID_CAP,
1321 MSR_IA32_VMX_VMFUNC,
1322
1323 MSR_K7_HWCR,
1324 MSR_KVM_POLL_CONTROL,
1325 };
1326
1327 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1328 static unsigned num_emulated_msrs;
1329
1330 /*
1331 * List of msr numbers which are used to expose MSR-based features that
1332 * can be used by a hypervisor to validate requested CPU features.
1333 */
1334 static const u32 msr_based_features_all[] = {
1335 MSR_IA32_VMX_BASIC,
1336 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1337 MSR_IA32_VMX_PINBASED_CTLS,
1338 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1339 MSR_IA32_VMX_PROCBASED_CTLS,
1340 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1341 MSR_IA32_VMX_EXIT_CTLS,
1342 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1343 MSR_IA32_VMX_ENTRY_CTLS,
1344 MSR_IA32_VMX_MISC,
1345 MSR_IA32_VMX_CR0_FIXED0,
1346 MSR_IA32_VMX_CR0_FIXED1,
1347 MSR_IA32_VMX_CR4_FIXED0,
1348 MSR_IA32_VMX_CR4_FIXED1,
1349 MSR_IA32_VMX_VMCS_ENUM,
1350 MSR_IA32_VMX_PROCBASED_CTLS2,
1351 MSR_IA32_VMX_EPT_VPID_CAP,
1352 MSR_IA32_VMX_VMFUNC,
1353
1354 MSR_F10H_DECFG,
1355 MSR_IA32_UCODE_REV,
1356 MSR_IA32_ARCH_CAPABILITIES,
1357 MSR_IA32_PERF_CAPABILITIES,
1358 };
1359
1360 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1361 static unsigned int num_msr_based_features;
1362
1363 static u64 kvm_get_arch_capabilities(void)
1364 {
1365 u64 data = 0;
1366
1367 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1368 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1369
1370 /*
1371 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1372 * the nested hypervisor runs with NX huge pages. If it is not,
1373 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1374 * L1 guests, so it need not worry about its own (L2) guests.
1375 */
1376 data |= ARCH_CAP_PSCHANGE_MC_NO;
1377
1378 /*
1379 * If we're doing cache flushes (either "always" or "cond")
1380 * we will do one whenever the guest does a vmlaunch/vmresume.
1381 * If an outer hypervisor is doing the cache flush for us
1382 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1383 * capability to the guest too, and if EPT is disabled we're not
1384 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1385 * require a nested hypervisor to do a flush of its own.
1386 */
1387 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1388 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1389
1390 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1391 data |= ARCH_CAP_RDCL_NO;
1392 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1393 data |= ARCH_CAP_SSB_NO;
1394 if (!boot_cpu_has_bug(X86_BUG_MDS))
1395 data |= ARCH_CAP_MDS_NO;
1396
1397 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1398 /*
1399 * If RTM=0 because the kernel has disabled TSX, the host might
1400 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1401 * and therefore knows that there cannot be TAA) but keep
1402 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1403 * and we want to allow migrating those guests to tsx=off hosts.
1404 */
1405 data &= ~ARCH_CAP_TAA_NO;
1406 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1407 data |= ARCH_CAP_TAA_NO;
1408 } else {
1409 /*
1410 * Nothing to do here; we emulate TSX_CTRL if present on the
1411 * host so the guest can choose between disabling TSX or
1412 * using VERW to clear CPU buffers.
1413 */
1414 }
1415
1416 return data;
1417 }
1418
1419 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1420 {
1421 switch (msr->index) {
1422 case MSR_IA32_ARCH_CAPABILITIES:
1423 msr->data = kvm_get_arch_capabilities();
1424 break;
1425 case MSR_IA32_UCODE_REV:
1426 rdmsrl_safe(msr->index, &msr->data);
1427 break;
1428 default:
1429 return kvm_x86_ops.get_msr_feature(msr);
1430 }
1431 return 0;
1432 }
1433
1434 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1435 {
1436 struct kvm_msr_entry msr;
1437 int r;
1438
1439 msr.index = index;
1440 r = kvm_get_msr_feature(&msr);
1441
1442 if (r == KVM_MSR_RET_INVALID) {
1443 /* Unconditionally clear the output for simplicity */
1444 *data = 0;
1445 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1446 r = 0;
1447 }
1448
1449 if (r)
1450 return r;
1451
1452 *data = msr.data;
1453
1454 return 0;
1455 }
1456
1457 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1458 {
1459 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1460 return false;
1461
1462 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1463 return false;
1464
1465 if (efer & (EFER_LME | EFER_LMA) &&
1466 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1467 return false;
1468
1469 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1470 return false;
1471
1472 return true;
1473
1474 }
1475 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1476 {
1477 if (efer & efer_reserved_bits)
1478 return false;
1479
1480 return __kvm_valid_efer(vcpu, efer);
1481 }
1482 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1483
1484 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1485 {
1486 u64 old_efer = vcpu->arch.efer;
1487 u64 efer = msr_info->data;
1488 int r;
1489
1490 if (efer & efer_reserved_bits)
1491 return 1;
1492
1493 if (!msr_info->host_initiated) {
1494 if (!__kvm_valid_efer(vcpu, efer))
1495 return 1;
1496
1497 if (is_paging(vcpu) &&
1498 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1499 return 1;
1500 }
1501
1502 efer &= ~EFER_LMA;
1503 efer |= vcpu->arch.efer & EFER_LMA;
1504
1505 r = kvm_x86_ops.set_efer(vcpu, efer);
1506 if (r) {
1507 WARN_ON(r > 0);
1508 return r;
1509 }
1510
1511 /* Update reserved bits */
1512 if ((efer ^ old_efer) & EFER_NX)
1513 kvm_mmu_reset_context(vcpu);
1514
1515 return 0;
1516 }
1517
1518 void kvm_enable_efer_bits(u64 mask)
1519 {
1520 efer_reserved_bits &= ~mask;
1521 }
1522 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1523
1524 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1525 {
1526 struct kvm *kvm = vcpu->kvm;
1527 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
1528 u32 count = kvm->arch.msr_filter.count;
1529 u32 i;
1530 bool r = kvm->arch.msr_filter.default_allow;
1531 int idx;
1532
1533 /* MSR filtering not set up or x2APIC enabled, allow everything */
1534 if (!count || (index >= 0x800 && index <= 0x8ff))
1535 return true;
1536
1537 /* Prevent collision with set_msr_filter */
1538 idx = srcu_read_lock(&kvm->srcu);
1539
1540 for (i = 0; i < count; i++) {
1541 u32 start = ranges[i].base;
1542 u32 end = start + ranges[i].nmsrs;
1543 u32 flags = ranges[i].flags;
1544 unsigned long *bitmap = ranges[i].bitmap;
1545
1546 if ((index >= start) && (index < end) && (flags & type)) {
1547 r = !!test_bit(index - start, bitmap);
1548 break;
1549 }
1550 }
1551
1552 srcu_read_unlock(&kvm->srcu, idx);
1553
1554 return r;
1555 }
1556 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1557
1558 /*
1559 * Write @data into the MSR specified by @index. Select MSR specific fault
1560 * checks are bypassed if @host_initiated is %true.
1561 * Returns 0 on success, non-0 otherwise.
1562 * Assumes vcpu_load() was already called.
1563 */
1564 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1565 bool host_initiated)
1566 {
1567 struct msr_data msr;
1568
1569 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1570 return KVM_MSR_RET_FILTERED;
1571
1572 switch (index) {
1573 case MSR_FS_BASE:
1574 case MSR_GS_BASE:
1575 case MSR_KERNEL_GS_BASE:
1576 case MSR_CSTAR:
1577 case MSR_LSTAR:
1578 if (is_noncanonical_address(data, vcpu))
1579 return 1;
1580 break;
1581 case MSR_IA32_SYSENTER_EIP:
1582 case MSR_IA32_SYSENTER_ESP:
1583 /*
1584 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1585 * non-canonical address is written on Intel but not on
1586 * AMD (which ignores the top 32-bits, because it does
1587 * not implement 64-bit SYSENTER).
1588 *
1589 * 64-bit code should hence be able to write a non-canonical
1590 * value on AMD. Making the address canonical ensures that
1591 * vmentry does not fail on Intel after writing a non-canonical
1592 * value, and that something deterministic happens if the guest
1593 * invokes 64-bit SYSENTER.
1594 */
1595 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1596 }
1597
1598 msr.data = data;
1599 msr.index = index;
1600 msr.host_initiated = host_initiated;
1601
1602 return kvm_x86_ops.set_msr(vcpu, &msr);
1603 }
1604
1605 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1606 u32 index, u64 data, bool host_initiated)
1607 {
1608 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1609
1610 if (ret == KVM_MSR_RET_INVALID)
1611 if (kvm_msr_ignored_check(vcpu, index, data, true))
1612 ret = 0;
1613
1614 return ret;
1615 }
1616
1617 /*
1618 * Read the MSR specified by @index into @data. Select MSR specific fault
1619 * checks are bypassed if @host_initiated is %true.
1620 * Returns 0 on success, non-0 otherwise.
1621 * Assumes vcpu_load() was already called.
1622 */
1623 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1624 bool host_initiated)
1625 {
1626 struct msr_data msr;
1627 int ret;
1628
1629 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1630 return KVM_MSR_RET_FILTERED;
1631
1632 msr.index = index;
1633 msr.host_initiated = host_initiated;
1634
1635 ret = kvm_x86_ops.get_msr(vcpu, &msr);
1636 if (!ret)
1637 *data = msr.data;
1638 return ret;
1639 }
1640
1641 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1642 u32 index, u64 *data, bool host_initiated)
1643 {
1644 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1645
1646 if (ret == KVM_MSR_RET_INVALID) {
1647 /* Unconditionally clear *data for simplicity */
1648 *data = 0;
1649 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1650 ret = 0;
1651 }
1652
1653 return ret;
1654 }
1655
1656 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1657 {
1658 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1659 }
1660 EXPORT_SYMBOL_GPL(kvm_get_msr);
1661
1662 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1663 {
1664 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1665 }
1666 EXPORT_SYMBOL_GPL(kvm_set_msr);
1667
1668 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1669 {
1670 int err = vcpu->run->msr.error;
1671 if (!err) {
1672 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1673 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1674 }
1675
1676 return kvm_x86_ops.complete_emulated_msr(vcpu, err);
1677 }
1678
1679 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1680 {
1681 return kvm_x86_ops.complete_emulated_msr(vcpu, vcpu->run->msr.error);
1682 }
1683
1684 static u64 kvm_msr_reason(int r)
1685 {
1686 switch (r) {
1687 case KVM_MSR_RET_INVALID:
1688 return KVM_MSR_EXIT_REASON_UNKNOWN;
1689 case KVM_MSR_RET_FILTERED:
1690 return KVM_MSR_EXIT_REASON_FILTER;
1691 default:
1692 return KVM_MSR_EXIT_REASON_INVAL;
1693 }
1694 }
1695
1696 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1697 u32 exit_reason, u64 data,
1698 int (*completion)(struct kvm_vcpu *vcpu),
1699 int r)
1700 {
1701 u64 msr_reason = kvm_msr_reason(r);
1702
1703 /* Check if the user wanted to know about this MSR fault */
1704 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1705 return 0;
1706
1707 vcpu->run->exit_reason = exit_reason;
1708 vcpu->run->msr.error = 0;
1709 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1710 vcpu->run->msr.reason = msr_reason;
1711 vcpu->run->msr.index = index;
1712 vcpu->run->msr.data = data;
1713 vcpu->arch.complete_userspace_io = completion;
1714
1715 return 1;
1716 }
1717
1718 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1719 {
1720 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1721 complete_emulated_rdmsr, r);
1722 }
1723
1724 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1725 {
1726 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1727 complete_emulated_wrmsr, r);
1728 }
1729
1730 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1731 {
1732 u32 ecx = kvm_rcx_read(vcpu);
1733 u64 data;
1734 int r;
1735
1736 r = kvm_get_msr(vcpu, ecx, &data);
1737
1738 /* MSR read failed? See if we should ask user space */
1739 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1740 /* Bounce to user space */
1741 return 0;
1742 }
1743
1744 if (!r) {
1745 trace_kvm_msr_read(ecx, data);
1746
1747 kvm_rax_write(vcpu, data & -1u);
1748 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1749 } else {
1750 trace_kvm_msr_read_ex(ecx);
1751 }
1752
1753 return kvm_x86_ops.complete_emulated_msr(vcpu, r);
1754 }
1755 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1756
1757 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1758 {
1759 u32 ecx = kvm_rcx_read(vcpu);
1760 u64 data = kvm_read_edx_eax(vcpu);
1761 int r;
1762
1763 r = kvm_set_msr(vcpu, ecx, data);
1764
1765 /* MSR write failed? See if we should ask user space */
1766 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r))
1767 /* Bounce to user space */
1768 return 0;
1769
1770 /* Signal all other negative errors to userspace */
1771 if (r < 0)
1772 return r;
1773
1774 if (!r)
1775 trace_kvm_msr_write(ecx, data);
1776 else
1777 trace_kvm_msr_write_ex(ecx, data);
1778
1779 return kvm_x86_ops.complete_emulated_msr(vcpu, r);
1780 }
1781 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1782
1783 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1784 {
1785 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1786 xfer_to_guest_mode_work_pending();
1787 }
1788 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1789
1790 /*
1791 * The fast path for frequent and performance sensitive wrmsr emulation,
1792 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1793 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1794 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1795 * other cases which must be called after interrupts are enabled on the host.
1796 */
1797 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1798 {
1799 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1800 return 1;
1801
1802 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1803 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1804 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1805 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1806
1807 data &= ~(1 << 12);
1808 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1809 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1810 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1811 trace_kvm_apic_write(APIC_ICR, (u32)data);
1812 return 0;
1813 }
1814
1815 return 1;
1816 }
1817
1818 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1819 {
1820 if (!kvm_can_use_hv_timer(vcpu))
1821 return 1;
1822
1823 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1824 return 0;
1825 }
1826
1827 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1828 {
1829 u32 msr = kvm_rcx_read(vcpu);
1830 u64 data;
1831 fastpath_t ret = EXIT_FASTPATH_NONE;
1832
1833 switch (msr) {
1834 case APIC_BASE_MSR + (APIC_ICR >> 4):
1835 data = kvm_read_edx_eax(vcpu);
1836 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1837 kvm_skip_emulated_instruction(vcpu);
1838 ret = EXIT_FASTPATH_EXIT_HANDLED;
1839 }
1840 break;
1841 case MSR_IA32_TSCDEADLINE:
1842 data = kvm_read_edx_eax(vcpu);
1843 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1844 kvm_skip_emulated_instruction(vcpu);
1845 ret = EXIT_FASTPATH_REENTER_GUEST;
1846 }
1847 break;
1848 default:
1849 break;
1850 }
1851
1852 if (ret != EXIT_FASTPATH_NONE)
1853 trace_kvm_msr_write(msr, data);
1854
1855 return ret;
1856 }
1857 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1858
1859 /*
1860 * Adapt set_msr() to msr_io()'s calling convention
1861 */
1862 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1863 {
1864 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1865 }
1866
1867 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1868 {
1869 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1870 }
1871
1872 #ifdef CONFIG_X86_64
1873 struct pvclock_clock {
1874 int vclock_mode;
1875 u64 cycle_last;
1876 u64 mask;
1877 u32 mult;
1878 u32 shift;
1879 u64 base_cycles;
1880 u64 offset;
1881 };
1882
1883 struct pvclock_gtod_data {
1884 seqcount_t seq;
1885
1886 struct pvclock_clock clock; /* extract of a clocksource struct */
1887 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1888
1889 ktime_t offs_boot;
1890 u64 wall_time_sec;
1891 };
1892
1893 static struct pvclock_gtod_data pvclock_gtod_data;
1894
1895 static void update_pvclock_gtod(struct timekeeper *tk)
1896 {
1897 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1898
1899 write_seqcount_begin(&vdata->seq);
1900
1901 /* copy pvclock gtod data */
1902 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1903 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1904 vdata->clock.mask = tk->tkr_mono.mask;
1905 vdata->clock.mult = tk->tkr_mono.mult;
1906 vdata->clock.shift = tk->tkr_mono.shift;
1907 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1908 vdata->clock.offset = tk->tkr_mono.base;
1909
1910 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1911 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1912 vdata->raw_clock.mask = tk->tkr_raw.mask;
1913 vdata->raw_clock.mult = tk->tkr_raw.mult;
1914 vdata->raw_clock.shift = tk->tkr_raw.shift;
1915 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1916 vdata->raw_clock.offset = tk->tkr_raw.base;
1917
1918 vdata->wall_time_sec = tk->xtime_sec;
1919
1920 vdata->offs_boot = tk->offs_boot;
1921
1922 write_seqcount_end(&vdata->seq);
1923 }
1924
1925 static s64 get_kvmclock_base_ns(void)
1926 {
1927 /* Count up from boot time, but with the frequency of the raw clock. */
1928 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1929 }
1930 #else
1931 static s64 get_kvmclock_base_ns(void)
1932 {
1933 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1934 return ktime_get_boottime_ns();
1935 }
1936 #endif
1937
1938 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1939 {
1940 int version;
1941 int r;
1942 struct pvclock_wall_clock wc;
1943 u64 wall_nsec;
1944
1945 kvm->arch.wall_clock = wall_clock;
1946
1947 if (!wall_clock)
1948 return;
1949
1950 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1951 if (r)
1952 return;
1953
1954 if (version & 1)
1955 ++version; /* first time write, random junk */
1956
1957 ++version;
1958
1959 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1960 return;
1961
1962 /*
1963 * The guest calculates current wall clock time by adding
1964 * system time (updated by kvm_guest_time_update below) to the
1965 * wall clock specified here. We do the reverse here.
1966 */
1967 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1968
1969 wc.nsec = do_div(wall_nsec, 1000000000);
1970 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1971 wc.version = version;
1972
1973 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1974
1975 version++;
1976 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1977 }
1978
1979 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1980 bool old_msr, bool host_initiated)
1981 {
1982 struct kvm_arch *ka = &vcpu->kvm->arch;
1983
1984 if (vcpu->vcpu_id == 0 && !host_initiated) {
1985 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
1986 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1987
1988 ka->boot_vcpu_runs_old_kvmclock = old_msr;
1989 }
1990
1991 vcpu->arch.time = system_time;
1992 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
1993
1994 /* we verify if the enable bit is set... */
1995 vcpu->arch.pv_time_enabled = false;
1996 if (!(system_time & 1))
1997 return;
1998
1999 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2000 &vcpu->arch.pv_time, system_time & ~1ULL,
2001 sizeof(struct pvclock_vcpu_time_info)))
2002 vcpu->arch.pv_time_enabled = true;
2003
2004 return;
2005 }
2006
2007 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2008 {
2009 do_shl32_div32(dividend, divisor);
2010 return dividend;
2011 }
2012
2013 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2014 s8 *pshift, u32 *pmultiplier)
2015 {
2016 uint64_t scaled64;
2017 int32_t shift = 0;
2018 uint64_t tps64;
2019 uint32_t tps32;
2020
2021 tps64 = base_hz;
2022 scaled64 = scaled_hz;
2023 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2024 tps64 >>= 1;
2025 shift--;
2026 }
2027
2028 tps32 = (uint32_t)tps64;
2029 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2030 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2031 scaled64 >>= 1;
2032 else
2033 tps32 <<= 1;
2034 shift++;
2035 }
2036
2037 *pshift = shift;
2038 *pmultiplier = div_frac(scaled64, tps32);
2039 }
2040
2041 #ifdef CONFIG_X86_64
2042 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2043 #endif
2044
2045 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2046 static unsigned long max_tsc_khz;
2047
2048 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2049 {
2050 u64 v = (u64)khz * (1000000 + ppm);
2051 do_div(v, 1000000);
2052 return v;
2053 }
2054
2055 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2056 {
2057 u64 ratio;
2058
2059 /* Guest TSC same frequency as host TSC? */
2060 if (!scale) {
2061 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2062 return 0;
2063 }
2064
2065 /* TSC scaling supported? */
2066 if (!kvm_has_tsc_control) {
2067 if (user_tsc_khz > tsc_khz) {
2068 vcpu->arch.tsc_catchup = 1;
2069 vcpu->arch.tsc_always_catchup = 1;
2070 return 0;
2071 } else {
2072 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2073 return -1;
2074 }
2075 }
2076
2077 /* TSC scaling required - calculate ratio */
2078 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2079 user_tsc_khz, tsc_khz);
2080
2081 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2082 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2083 user_tsc_khz);
2084 return -1;
2085 }
2086
2087 vcpu->arch.tsc_scaling_ratio = ratio;
2088 return 0;
2089 }
2090
2091 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2092 {
2093 u32 thresh_lo, thresh_hi;
2094 int use_scaling = 0;
2095
2096 /* tsc_khz can be zero if TSC calibration fails */
2097 if (user_tsc_khz == 0) {
2098 /* set tsc_scaling_ratio to a safe value */
2099 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2100 return -1;
2101 }
2102
2103 /* Compute a scale to convert nanoseconds in TSC cycles */
2104 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2105 &vcpu->arch.virtual_tsc_shift,
2106 &vcpu->arch.virtual_tsc_mult);
2107 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2108
2109 /*
2110 * Compute the variation in TSC rate which is acceptable
2111 * within the range of tolerance and decide if the
2112 * rate being applied is within that bounds of the hardware
2113 * rate. If so, no scaling or compensation need be done.
2114 */
2115 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2116 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2117 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2118 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2119 use_scaling = 1;
2120 }
2121 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2122 }
2123
2124 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2125 {
2126 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2127 vcpu->arch.virtual_tsc_mult,
2128 vcpu->arch.virtual_tsc_shift);
2129 tsc += vcpu->arch.this_tsc_write;
2130 return tsc;
2131 }
2132
2133 static inline int gtod_is_based_on_tsc(int mode)
2134 {
2135 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2136 }
2137
2138 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2139 {
2140 #ifdef CONFIG_X86_64
2141 bool vcpus_matched;
2142 struct kvm_arch *ka = &vcpu->kvm->arch;
2143 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2144
2145 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2146 atomic_read(&vcpu->kvm->online_vcpus));
2147
2148 /*
2149 * Once the masterclock is enabled, always perform request in
2150 * order to update it.
2151 *
2152 * In order to enable masterclock, the host clocksource must be TSC
2153 * and the vcpus need to have matched TSCs. When that happens,
2154 * perform request to enable masterclock.
2155 */
2156 if (ka->use_master_clock ||
2157 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2158 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2159
2160 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2161 atomic_read(&vcpu->kvm->online_vcpus),
2162 ka->use_master_clock, gtod->clock.vclock_mode);
2163 #endif
2164 }
2165
2166 /*
2167 * Multiply tsc by a fixed point number represented by ratio.
2168 *
2169 * The most significant 64-N bits (mult) of ratio represent the
2170 * integral part of the fixed point number; the remaining N bits
2171 * (frac) represent the fractional part, ie. ratio represents a fixed
2172 * point number (mult + frac * 2^(-N)).
2173 *
2174 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2175 */
2176 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2177 {
2178 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2179 }
2180
2181 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2182 {
2183 u64 _tsc = tsc;
2184 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2185
2186 if (ratio != kvm_default_tsc_scaling_ratio)
2187 _tsc = __scale_tsc(ratio, tsc);
2188
2189 return _tsc;
2190 }
2191 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2192
2193 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2194 {
2195 u64 tsc;
2196
2197 tsc = kvm_scale_tsc(vcpu, rdtsc());
2198
2199 return target_tsc - tsc;
2200 }
2201
2202 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2203 {
2204 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2205 }
2206 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2207
2208 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2209 {
2210 vcpu->arch.l1_tsc_offset = offset;
2211 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2212 }
2213
2214 static inline bool kvm_check_tsc_unstable(void)
2215 {
2216 #ifdef CONFIG_X86_64
2217 /*
2218 * TSC is marked unstable when we're running on Hyper-V,
2219 * 'TSC page' clocksource is good.
2220 */
2221 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2222 return false;
2223 #endif
2224 return check_tsc_unstable();
2225 }
2226
2227 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2228 {
2229 struct kvm *kvm = vcpu->kvm;
2230 u64 offset, ns, elapsed;
2231 unsigned long flags;
2232 bool matched;
2233 bool already_matched;
2234 bool synchronizing = false;
2235
2236 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2237 offset = kvm_compute_tsc_offset(vcpu, data);
2238 ns = get_kvmclock_base_ns();
2239 elapsed = ns - kvm->arch.last_tsc_nsec;
2240
2241 if (vcpu->arch.virtual_tsc_khz) {
2242 if (data == 0) {
2243 /*
2244 * detection of vcpu initialization -- need to sync
2245 * with other vCPUs. This particularly helps to keep
2246 * kvm_clock stable after CPU hotplug
2247 */
2248 synchronizing = true;
2249 } else {
2250 u64 tsc_exp = kvm->arch.last_tsc_write +
2251 nsec_to_cycles(vcpu, elapsed);
2252 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2253 /*
2254 * Special case: TSC write with a small delta (1 second)
2255 * of virtual cycle time against real time is
2256 * interpreted as an attempt to synchronize the CPU.
2257 */
2258 synchronizing = data < tsc_exp + tsc_hz &&
2259 data + tsc_hz > tsc_exp;
2260 }
2261 }
2262
2263 /*
2264 * For a reliable TSC, we can match TSC offsets, and for an unstable
2265 * TSC, we add elapsed time in this computation. We could let the
2266 * compensation code attempt to catch up if we fall behind, but
2267 * it's better to try to match offsets from the beginning.
2268 */
2269 if (synchronizing &&
2270 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2271 if (!kvm_check_tsc_unstable()) {
2272 offset = kvm->arch.cur_tsc_offset;
2273 } else {
2274 u64 delta = nsec_to_cycles(vcpu, elapsed);
2275 data += delta;
2276 offset = kvm_compute_tsc_offset(vcpu, data);
2277 }
2278 matched = true;
2279 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2280 } else {
2281 /*
2282 * We split periods of matched TSC writes into generations.
2283 * For each generation, we track the original measured
2284 * nanosecond time, offset, and write, so if TSCs are in
2285 * sync, we can match exact offset, and if not, we can match
2286 * exact software computation in compute_guest_tsc()
2287 *
2288 * These values are tracked in kvm->arch.cur_xxx variables.
2289 */
2290 kvm->arch.cur_tsc_generation++;
2291 kvm->arch.cur_tsc_nsec = ns;
2292 kvm->arch.cur_tsc_write = data;
2293 kvm->arch.cur_tsc_offset = offset;
2294 matched = false;
2295 }
2296
2297 /*
2298 * We also track th most recent recorded KHZ, write and time to
2299 * allow the matching interval to be extended at each write.
2300 */
2301 kvm->arch.last_tsc_nsec = ns;
2302 kvm->arch.last_tsc_write = data;
2303 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2304
2305 vcpu->arch.last_guest_tsc = data;
2306
2307 /* Keep track of which generation this VCPU has synchronized to */
2308 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2309 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2310 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2311
2312 kvm_vcpu_write_tsc_offset(vcpu, offset);
2313 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2314
2315 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2316 if (!matched) {
2317 kvm->arch.nr_vcpus_matched_tsc = 0;
2318 } else if (!already_matched) {
2319 kvm->arch.nr_vcpus_matched_tsc++;
2320 }
2321
2322 kvm_track_tsc_matching(vcpu);
2323 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2324 }
2325
2326 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2327 s64 adjustment)
2328 {
2329 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2330 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2331 }
2332
2333 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2334 {
2335 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2336 WARN_ON(adjustment < 0);
2337 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2338 adjust_tsc_offset_guest(vcpu, adjustment);
2339 }
2340
2341 #ifdef CONFIG_X86_64
2342
2343 static u64 read_tsc(void)
2344 {
2345 u64 ret = (u64)rdtsc_ordered();
2346 u64 last = pvclock_gtod_data.clock.cycle_last;
2347
2348 if (likely(ret >= last))
2349 return ret;
2350
2351 /*
2352 * GCC likes to generate cmov here, but this branch is extremely
2353 * predictable (it's just a function of time and the likely is
2354 * very likely) and there's a data dependence, so force GCC
2355 * to generate a branch instead. I don't barrier() because
2356 * we don't actually need a barrier, and if this function
2357 * ever gets inlined it will generate worse code.
2358 */
2359 asm volatile ("");
2360 return last;
2361 }
2362
2363 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2364 int *mode)
2365 {
2366 long v;
2367 u64 tsc_pg_val;
2368
2369 switch (clock->vclock_mode) {
2370 case VDSO_CLOCKMODE_HVCLOCK:
2371 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2372 tsc_timestamp);
2373 if (tsc_pg_val != U64_MAX) {
2374 /* TSC page valid */
2375 *mode = VDSO_CLOCKMODE_HVCLOCK;
2376 v = (tsc_pg_val - clock->cycle_last) &
2377 clock->mask;
2378 } else {
2379 /* TSC page invalid */
2380 *mode = VDSO_CLOCKMODE_NONE;
2381 }
2382 break;
2383 case VDSO_CLOCKMODE_TSC:
2384 *mode = VDSO_CLOCKMODE_TSC;
2385 *tsc_timestamp = read_tsc();
2386 v = (*tsc_timestamp - clock->cycle_last) &
2387 clock->mask;
2388 break;
2389 default:
2390 *mode = VDSO_CLOCKMODE_NONE;
2391 }
2392
2393 if (*mode == VDSO_CLOCKMODE_NONE)
2394 *tsc_timestamp = v = 0;
2395
2396 return v * clock->mult;
2397 }
2398
2399 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2400 {
2401 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2402 unsigned long seq;
2403 int mode;
2404 u64 ns;
2405
2406 do {
2407 seq = read_seqcount_begin(&gtod->seq);
2408 ns = gtod->raw_clock.base_cycles;
2409 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2410 ns >>= gtod->raw_clock.shift;
2411 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2412 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2413 *t = ns;
2414
2415 return mode;
2416 }
2417
2418 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2419 {
2420 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2421 unsigned long seq;
2422 int mode;
2423 u64 ns;
2424
2425 do {
2426 seq = read_seqcount_begin(&gtod->seq);
2427 ts->tv_sec = gtod->wall_time_sec;
2428 ns = gtod->clock.base_cycles;
2429 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2430 ns >>= gtod->clock.shift;
2431 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2432
2433 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2434 ts->tv_nsec = ns;
2435
2436 return mode;
2437 }
2438
2439 /* returns true if host is using TSC based clocksource */
2440 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2441 {
2442 /* checked again under seqlock below */
2443 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2444 return false;
2445
2446 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2447 tsc_timestamp));
2448 }
2449
2450 /* returns true if host is using TSC based clocksource */
2451 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2452 u64 *tsc_timestamp)
2453 {
2454 /* checked again under seqlock below */
2455 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2456 return false;
2457
2458 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2459 }
2460 #endif
2461
2462 /*
2463 *
2464 * Assuming a stable TSC across physical CPUS, and a stable TSC
2465 * across virtual CPUs, the following condition is possible.
2466 * Each numbered line represents an event visible to both
2467 * CPUs at the next numbered event.
2468 *
2469 * "timespecX" represents host monotonic time. "tscX" represents
2470 * RDTSC value.
2471 *
2472 * VCPU0 on CPU0 | VCPU1 on CPU1
2473 *
2474 * 1. read timespec0,tsc0
2475 * 2. | timespec1 = timespec0 + N
2476 * | tsc1 = tsc0 + M
2477 * 3. transition to guest | transition to guest
2478 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2479 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2480 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2481 *
2482 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2483 *
2484 * - ret0 < ret1
2485 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2486 * ...
2487 * - 0 < N - M => M < N
2488 *
2489 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2490 * always the case (the difference between two distinct xtime instances
2491 * might be smaller then the difference between corresponding TSC reads,
2492 * when updating guest vcpus pvclock areas).
2493 *
2494 * To avoid that problem, do not allow visibility of distinct
2495 * system_timestamp/tsc_timestamp values simultaneously: use a master
2496 * copy of host monotonic time values. Update that master copy
2497 * in lockstep.
2498 *
2499 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2500 *
2501 */
2502
2503 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2504 {
2505 #ifdef CONFIG_X86_64
2506 struct kvm_arch *ka = &kvm->arch;
2507 int vclock_mode;
2508 bool host_tsc_clocksource, vcpus_matched;
2509
2510 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2511 atomic_read(&kvm->online_vcpus));
2512
2513 /*
2514 * If the host uses TSC clock, then passthrough TSC as stable
2515 * to the guest.
2516 */
2517 host_tsc_clocksource = kvm_get_time_and_clockread(
2518 &ka->master_kernel_ns,
2519 &ka->master_cycle_now);
2520
2521 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2522 && !ka->backwards_tsc_observed
2523 && !ka->boot_vcpu_runs_old_kvmclock;
2524
2525 if (ka->use_master_clock)
2526 atomic_set(&kvm_guest_has_master_clock, 1);
2527
2528 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2529 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2530 vcpus_matched);
2531 #endif
2532 }
2533
2534 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2535 {
2536 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2537 }
2538
2539 static void kvm_gen_update_masterclock(struct kvm *kvm)
2540 {
2541 #ifdef CONFIG_X86_64
2542 int i;
2543 struct kvm_vcpu *vcpu;
2544 struct kvm_arch *ka = &kvm->arch;
2545
2546 spin_lock(&ka->pvclock_gtod_sync_lock);
2547 kvm_make_mclock_inprogress_request(kvm);
2548 /* no guest entries from this point */
2549 pvclock_update_vm_gtod_copy(kvm);
2550
2551 kvm_for_each_vcpu(i, vcpu, kvm)
2552 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2553
2554 /* guest entries allowed */
2555 kvm_for_each_vcpu(i, vcpu, kvm)
2556 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2557
2558 spin_unlock(&ka->pvclock_gtod_sync_lock);
2559 #endif
2560 }
2561
2562 u64 get_kvmclock_ns(struct kvm *kvm)
2563 {
2564 struct kvm_arch *ka = &kvm->arch;
2565 struct pvclock_vcpu_time_info hv_clock;
2566 u64 ret;
2567
2568 spin_lock(&ka->pvclock_gtod_sync_lock);
2569 if (!ka->use_master_clock) {
2570 spin_unlock(&ka->pvclock_gtod_sync_lock);
2571 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2572 }
2573
2574 hv_clock.tsc_timestamp = ka->master_cycle_now;
2575 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2576 spin_unlock(&ka->pvclock_gtod_sync_lock);
2577
2578 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2579 get_cpu();
2580
2581 if (__this_cpu_read(cpu_tsc_khz)) {
2582 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2583 &hv_clock.tsc_shift,
2584 &hv_clock.tsc_to_system_mul);
2585 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2586 } else
2587 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2588
2589 put_cpu();
2590
2591 return ret;
2592 }
2593
2594 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2595 {
2596 struct kvm_vcpu_arch *vcpu = &v->arch;
2597 struct pvclock_vcpu_time_info guest_hv_clock;
2598
2599 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2600 &guest_hv_clock, sizeof(guest_hv_clock))))
2601 return;
2602
2603 /* This VCPU is paused, but it's legal for a guest to read another
2604 * VCPU's kvmclock, so we really have to follow the specification where
2605 * it says that version is odd if data is being modified, and even after
2606 * it is consistent.
2607 *
2608 * Version field updates must be kept separate. This is because
2609 * kvm_write_guest_cached might use a "rep movs" instruction, and
2610 * writes within a string instruction are weakly ordered. So there
2611 * are three writes overall.
2612 *
2613 * As a small optimization, only write the version field in the first
2614 * and third write. The vcpu->pv_time cache is still valid, because the
2615 * version field is the first in the struct.
2616 */
2617 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2618
2619 if (guest_hv_clock.version & 1)
2620 ++guest_hv_clock.version; /* first time write, random junk */
2621
2622 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2623 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2624 &vcpu->hv_clock,
2625 sizeof(vcpu->hv_clock.version));
2626
2627 smp_wmb();
2628
2629 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2630 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2631
2632 if (vcpu->pvclock_set_guest_stopped_request) {
2633 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2634 vcpu->pvclock_set_guest_stopped_request = false;
2635 }
2636
2637 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2638
2639 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2640 &vcpu->hv_clock,
2641 sizeof(vcpu->hv_clock));
2642
2643 smp_wmb();
2644
2645 vcpu->hv_clock.version++;
2646 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2647 &vcpu->hv_clock,
2648 sizeof(vcpu->hv_clock.version));
2649 }
2650
2651 static int kvm_guest_time_update(struct kvm_vcpu *v)
2652 {
2653 unsigned long flags, tgt_tsc_khz;
2654 struct kvm_vcpu_arch *vcpu = &v->arch;
2655 struct kvm_arch *ka = &v->kvm->arch;
2656 s64 kernel_ns;
2657 u64 tsc_timestamp, host_tsc;
2658 u8 pvclock_flags;
2659 bool use_master_clock;
2660
2661 kernel_ns = 0;
2662 host_tsc = 0;
2663
2664 /*
2665 * If the host uses TSC clock, then passthrough TSC as stable
2666 * to the guest.
2667 */
2668 spin_lock(&ka->pvclock_gtod_sync_lock);
2669 use_master_clock = ka->use_master_clock;
2670 if (use_master_clock) {
2671 host_tsc = ka->master_cycle_now;
2672 kernel_ns = ka->master_kernel_ns;
2673 }
2674 spin_unlock(&ka->pvclock_gtod_sync_lock);
2675
2676 /* Keep irq disabled to prevent changes to the clock */
2677 local_irq_save(flags);
2678 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2679 if (unlikely(tgt_tsc_khz == 0)) {
2680 local_irq_restore(flags);
2681 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2682 return 1;
2683 }
2684 if (!use_master_clock) {
2685 host_tsc = rdtsc();
2686 kernel_ns = get_kvmclock_base_ns();
2687 }
2688
2689 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2690
2691 /*
2692 * We may have to catch up the TSC to match elapsed wall clock
2693 * time for two reasons, even if kvmclock is used.
2694 * 1) CPU could have been running below the maximum TSC rate
2695 * 2) Broken TSC compensation resets the base at each VCPU
2696 * entry to avoid unknown leaps of TSC even when running
2697 * again on the same CPU. This may cause apparent elapsed
2698 * time to disappear, and the guest to stand still or run
2699 * very slowly.
2700 */
2701 if (vcpu->tsc_catchup) {
2702 u64 tsc = compute_guest_tsc(v, kernel_ns);
2703 if (tsc > tsc_timestamp) {
2704 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2705 tsc_timestamp = tsc;
2706 }
2707 }
2708
2709 local_irq_restore(flags);
2710
2711 /* With all the info we got, fill in the values */
2712
2713 if (kvm_has_tsc_control)
2714 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2715
2716 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2717 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2718 &vcpu->hv_clock.tsc_shift,
2719 &vcpu->hv_clock.tsc_to_system_mul);
2720 vcpu->hw_tsc_khz = tgt_tsc_khz;
2721 }
2722
2723 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2724 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2725 vcpu->last_guest_tsc = tsc_timestamp;
2726
2727 /* If the host uses TSC clocksource, then it is stable */
2728 pvclock_flags = 0;
2729 if (use_master_clock)
2730 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2731
2732 vcpu->hv_clock.flags = pvclock_flags;
2733
2734 if (vcpu->pv_time_enabled)
2735 kvm_setup_pvclock_page(v);
2736 if (v == kvm_get_vcpu(v->kvm, 0))
2737 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2738 return 0;
2739 }
2740
2741 /*
2742 * kvmclock updates which are isolated to a given vcpu, such as
2743 * vcpu->cpu migration, should not allow system_timestamp from
2744 * the rest of the vcpus to remain static. Otherwise ntp frequency
2745 * correction applies to one vcpu's system_timestamp but not
2746 * the others.
2747 *
2748 * So in those cases, request a kvmclock update for all vcpus.
2749 * We need to rate-limit these requests though, as they can
2750 * considerably slow guests that have a large number of vcpus.
2751 * The time for a remote vcpu to update its kvmclock is bound
2752 * by the delay we use to rate-limit the updates.
2753 */
2754
2755 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2756
2757 static void kvmclock_update_fn(struct work_struct *work)
2758 {
2759 int i;
2760 struct delayed_work *dwork = to_delayed_work(work);
2761 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2762 kvmclock_update_work);
2763 struct kvm *kvm = container_of(ka, struct kvm, arch);
2764 struct kvm_vcpu *vcpu;
2765
2766 kvm_for_each_vcpu(i, vcpu, kvm) {
2767 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2768 kvm_vcpu_kick(vcpu);
2769 }
2770 }
2771
2772 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2773 {
2774 struct kvm *kvm = v->kvm;
2775
2776 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2777 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2778 KVMCLOCK_UPDATE_DELAY);
2779 }
2780
2781 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2782
2783 static void kvmclock_sync_fn(struct work_struct *work)
2784 {
2785 struct delayed_work *dwork = to_delayed_work(work);
2786 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2787 kvmclock_sync_work);
2788 struct kvm *kvm = container_of(ka, struct kvm, arch);
2789
2790 if (!kvmclock_periodic_sync)
2791 return;
2792
2793 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2794 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2795 KVMCLOCK_SYNC_PERIOD);
2796 }
2797
2798 /*
2799 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2800 */
2801 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2802 {
2803 /* McStatusWrEn enabled? */
2804 if (guest_cpuid_is_amd_or_hygon(vcpu))
2805 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2806
2807 return false;
2808 }
2809
2810 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2811 {
2812 u64 mcg_cap = vcpu->arch.mcg_cap;
2813 unsigned bank_num = mcg_cap & 0xff;
2814 u32 msr = msr_info->index;
2815 u64 data = msr_info->data;
2816
2817 switch (msr) {
2818 case MSR_IA32_MCG_STATUS:
2819 vcpu->arch.mcg_status = data;
2820 break;
2821 case MSR_IA32_MCG_CTL:
2822 if (!(mcg_cap & MCG_CTL_P) &&
2823 (data || !msr_info->host_initiated))
2824 return 1;
2825 if (data != 0 && data != ~(u64)0)
2826 return 1;
2827 vcpu->arch.mcg_ctl = data;
2828 break;
2829 default:
2830 if (msr >= MSR_IA32_MC0_CTL &&
2831 msr < MSR_IA32_MCx_CTL(bank_num)) {
2832 u32 offset = array_index_nospec(
2833 msr - MSR_IA32_MC0_CTL,
2834 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2835
2836 /* only 0 or all 1s can be written to IA32_MCi_CTL
2837 * some Linux kernels though clear bit 10 in bank 4 to
2838 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2839 * this to avoid an uncatched #GP in the guest
2840 */
2841 if ((offset & 0x3) == 0 &&
2842 data != 0 && (data | (1 << 10)) != ~(u64)0)
2843 return -1;
2844
2845 /* MCi_STATUS */
2846 if (!msr_info->host_initiated &&
2847 (offset & 0x3) == 1 && data != 0) {
2848 if (!can_set_mci_status(vcpu))
2849 return -1;
2850 }
2851
2852 vcpu->arch.mce_banks[offset] = data;
2853 break;
2854 }
2855 return 1;
2856 }
2857 return 0;
2858 }
2859
2860 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2861 {
2862 struct kvm *kvm = vcpu->kvm;
2863 int lm = is_long_mode(vcpu);
2864 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2865 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2866 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2867 : kvm->arch.xen_hvm_config.blob_size_32;
2868 u32 page_num = data & ~PAGE_MASK;
2869 u64 page_addr = data & PAGE_MASK;
2870 u8 *page;
2871
2872 if (page_num >= blob_size)
2873 return 1;
2874
2875 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2876 if (IS_ERR(page))
2877 return PTR_ERR(page);
2878
2879 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) {
2880 kfree(page);
2881 return 1;
2882 }
2883 return 0;
2884 }
2885
2886 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2887 {
2888 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2889
2890 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2891 }
2892
2893 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2894 {
2895 gpa_t gpa = data & ~0x3f;
2896
2897 /* Bits 4:5 are reserved, Should be zero */
2898 if (data & 0x30)
2899 return 1;
2900
2901 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
2902 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
2903 return 1;
2904
2905 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
2906 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
2907 return 1;
2908
2909 if (!lapic_in_kernel(vcpu))
2910 return data ? 1 : 0;
2911
2912 vcpu->arch.apf.msr_en_val = data;
2913
2914 if (!kvm_pv_async_pf_enabled(vcpu)) {
2915 kvm_clear_async_pf_completion_queue(vcpu);
2916 kvm_async_pf_hash_reset(vcpu);
2917 return 0;
2918 }
2919
2920 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2921 sizeof(u64)))
2922 return 1;
2923
2924 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2925 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2926
2927 kvm_async_pf_wakeup_all(vcpu);
2928
2929 return 0;
2930 }
2931
2932 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2933 {
2934 /* Bits 8-63 are reserved */
2935 if (data >> 8)
2936 return 1;
2937
2938 if (!lapic_in_kernel(vcpu))
2939 return 1;
2940
2941 vcpu->arch.apf.msr_int_val = data;
2942
2943 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2944
2945 return 0;
2946 }
2947
2948 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2949 {
2950 vcpu->arch.pv_time_enabled = false;
2951 vcpu->arch.time = 0;
2952 }
2953
2954 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2955 {
2956 ++vcpu->stat.tlb_flush;
2957 kvm_x86_ops.tlb_flush_all(vcpu);
2958 }
2959
2960 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2961 {
2962 ++vcpu->stat.tlb_flush;
2963 kvm_x86_ops.tlb_flush_guest(vcpu);
2964 }
2965
2966 static void record_steal_time(struct kvm_vcpu *vcpu)
2967 {
2968 struct kvm_host_map map;
2969 struct kvm_steal_time *st;
2970
2971 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2972 return;
2973
2974 /* -EAGAIN is returned in atomic context so we can just return. */
2975 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2976 &map, &vcpu->arch.st.cache, false))
2977 return;
2978
2979 st = map.hva +
2980 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2981
2982 /*
2983 * Doing a TLB flush here, on the guest's behalf, can avoid
2984 * expensive IPIs.
2985 */
2986 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
2987 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2988 st->preempted & KVM_VCPU_FLUSH_TLB);
2989 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2990 kvm_vcpu_flush_tlb_guest(vcpu);
2991 }
2992
2993 vcpu->arch.st.preempted = 0;
2994
2995 if (st->version & 1)
2996 st->version += 1; /* first time write, random junk */
2997
2998 st->version += 1;
2999
3000 smp_wmb();
3001
3002 st->steal += current->sched_info.run_delay -
3003 vcpu->arch.st.last_steal;
3004 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3005
3006 smp_wmb();
3007
3008 st->version += 1;
3009
3010 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
3011 }
3012
3013 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3014 {
3015 bool pr = false;
3016 u32 msr = msr_info->index;
3017 u64 data = msr_info->data;
3018
3019 switch (msr) {
3020 case MSR_AMD64_NB_CFG:
3021 case MSR_IA32_UCODE_WRITE:
3022 case MSR_VM_HSAVE_PA:
3023 case MSR_AMD64_PATCH_LOADER:
3024 case MSR_AMD64_BU_CFG2:
3025 case MSR_AMD64_DC_CFG:
3026 case MSR_F15H_EX_CFG:
3027 break;
3028
3029 case MSR_IA32_UCODE_REV:
3030 if (msr_info->host_initiated)
3031 vcpu->arch.microcode_version = data;
3032 break;
3033 case MSR_IA32_ARCH_CAPABILITIES:
3034 if (!msr_info->host_initiated)
3035 return 1;
3036 vcpu->arch.arch_capabilities = data;
3037 break;
3038 case MSR_IA32_PERF_CAPABILITIES: {
3039 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3040
3041 if (!msr_info->host_initiated)
3042 return 1;
3043 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3044 return 1;
3045 if (data & ~msr_ent.data)
3046 return 1;
3047
3048 vcpu->arch.perf_capabilities = data;
3049
3050 return 0;
3051 }
3052 case MSR_EFER:
3053 return set_efer(vcpu, msr_info);
3054 case MSR_K7_HWCR:
3055 data &= ~(u64)0x40; /* ignore flush filter disable */
3056 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3057 data &= ~(u64)0x8; /* ignore TLB cache disable */
3058
3059 /* Handle McStatusWrEn */
3060 if (data == BIT_ULL(18)) {
3061 vcpu->arch.msr_hwcr = data;
3062 } else if (data != 0) {
3063 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3064 data);
3065 return 1;
3066 }
3067 break;
3068 case MSR_FAM10H_MMIO_CONF_BASE:
3069 if (data != 0) {
3070 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3071 "0x%llx\n", data);
3072 return 1;
3073 }
3074 break;
3075 case MSR_IA32_DEBUGCTLMSR:
3076 if (!data) {
3077 /* We support the non-activated case already */
3078 break;
3079 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
3080 /* Values other than LBR and BTF are vendor-specific,
3081 thus reserved and should throw a #GP */
3082 return 1;
3083 } else if (report_ignored_msrs)
3084 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
3085 __func__, data);
3086 break;
3087 case 0x200 ... 0x2ff:
3088 return kvm_mtrr_set_msr(vcpu, msr, data);
3089 case MSR_IA32_APICBASE:
3090 return kvm_set_apic_base(vcpu, msr_info);
3091 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3092 return kvm_x2apic_msr_write(vcpu, msr, data);
3093 case MSR_IA32_TSCDEADLINE:
3094 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3095 break;
3096 case MSR_IA32_TSC_ADJUST:
3097 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3098 if (!msr_info->host_initiated) {
3099 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3100 adjust_tsc_offset_guest(vcpu, adj);
3101 }
3102 vcpu->arch.ia32_tsc_adjust_msr = data;
3103 }
3104 break;
3105 case MSR_IA32_MISC_ENABLE:
3106 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3107 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3108 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3109 return 1;
3110 vcpu->arch.ia32_misc_enable_msr = data;
3111 kvm_update_cpuid_runtime(vcpu);
3112 } else {
3113 vcpu->arch.ia32_misc_enable_msr = data;
3114 }
3115 break;
3116 case MSR_IA32_SMBASE:
3117 if (!msr_info->host_initiated)
3118 return 1;
3119 vcpu->arch.smbase = data;
3120 break;
3121 case MSR_IA32_POWER_CTL:
3122 vcpu->arch.msr_ia32_power_ctl = data;
3123 break;
3124 case MSR_IA32_TSC:
3125 if (msr_info->host_initiated) {
3126 kvm_synchronize_tsc(vcpu, data);
3127 } else {
3128 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3129 adjust_tsc_offset_guest(vcpu, adj);
3130 vcpu->arch.ia32_tsc_adjust_msr += adj;
3131 }
3132 break;
3133 case MSR_IA32_XSS:
3134 if (!msr_info->host_initiated &&
3135 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3136 return 1;
3137 /*
3138 * KVM supports exposing PT to the guest, but does not support
3139 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3140 * XSAVES/XRSTORS to save/restore PT MSRs.
3141 */
3142 if (data & ~supported_xss)
3143 return 1;
3144 vcpu->arch.ia32_xss = data;
3145 break;
3146 case MSR_SMI_COUNT:
3147 if (!msr_info->host_initiated)
3148 return 1;
3149 vcpu->arch.smi_count = data;
3150 break;
3151 case MSR_KVM_WALL_CLOCK_NEW:
3152 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3153 return 1;
3154
3155 kvm_write_wall_clock(vcpu->kvm, data);
3156 break;
3157 case MSR_KVM_WALL_CLOCK:
3158 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3159 return 1;
3160
3161 kvm_write_wall_clock(vcpu->kvm, data);
3162 break;
3163 case MSR_KVM_SYSTEM_TIME_NEW:
3164 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3165 return 1;
3166
3167 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3168 break;
3169 case MSR_KVM_SYSTEM_TIME:
3170 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3171 return 1;
3172
3173 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3174 break;
3175 case MSR_KVM_ASYNC_PF_EN:
3176 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3177 return 1;
3178
3179 if (kvm_pv_enable_async_pf(vcpu, data))
3180 return 1;
3181 break;
3182 case MSR_KVM_ASYNC_PF_INT:
3183 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3184 return 1;
3185
3186 if (kvm_pv_enable_async_pf_int(vcpu, data))
3187 return 1;
3188 break;
3189 case MSR_KVM_ASYNC_PF_ACK:
3190 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3191 return 1;
3192 if (data & 0x1) {
3193 vcpu->arch.apf.pageready_pending = false;
3194 kvm_check_async_pf_completion(vcpu);
3195 }
3196 break;
3197 case MSR_KVM_STEAL_TIME:
3198 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3199 return 1;
3200
3201 if (unlikely(!sched_info_on()))
3202 return 1;
3203
3204 if (data & KVM_STEAL_RESERVED_MASK)
3205 return 1;
3206
3207 vcpu->arch.st.msr_val = data;
3208
3209 if (!(data & KVM_MSR_ENABLED))
3210 break;
3211
3212 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3213
3214 break;
3215 case MSR_KVM_PV_EOI_EN:
3216 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3217 return 1;
3218
3219 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3220 return 1;
3221 break;
3222
3223 case MSR_KVM_POLL_CONTROL:
3224 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3225 return 1;
3226
3227 /* only enable bit supported */
3228 if (data & (-1ULL << 1))
3229 return 1;
3230
3231 vcpu->arch.msr_kvm_poll_control = data;
3232 break;
3233
3234 case MSR_IA32_MCG_CTL:
3235 case MSR_IA32_MCG_STATUS:
3236 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3237 return set_msr_mce(vcpu, msr_info);
3238
3239 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3240 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3241 pr = true;
3242 fallthrough;
3243 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3244 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3245 if (kvm_pmu_is_valid_msr(vcpu, msr))
3246 return kvm_pmu_set_msr(vcpu, msr_info);
3247
3248 if (pr || data != 0)
3249 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3250 "0x%x data 0x%llx\n", msr, data);
3251 break;
3252 case MSR_K7_CLK_CTL:
3253 /*
3254 * Ignore all writes to this no longer documented MSR.
3255 * Writes are only relevant for old K7 processors,
3256 * all pre-dating SVM, but a recommended workaround from
3257 * AMD for these chips. It is possible to specify the
3258 * affected processor models on the command line, hence
3259 * the need to ignore the workaround.
3260 */
3261 break;
3262 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3263 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3264 case HV_X64_MSR_SYNDBG_OPTIONS:
3265 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3266 case HV_X64_MSR_CRASH_CTL:
3267 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3268 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3269 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3270 case HV_X64_MSR_TSC_EMULATION_STATUS:
3271 return kvm_hv_set_msr_common(vcpu, msr, data,
3272 msr_info->host_initiated);
3273 case MSR_IA32_BBL_CR_CTL3:
3274 /* Drop writes to this legacy MSR -- see rdmsr
3275 * counterpart for further detail.
3276 */
3277 if (report_ignored_msrs)
3278 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3279 msr, data);
3280 break;
3281 case MSR_AMD64_OSVW_ID_LENGTH:
3282 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3283 return 1;
3284 vcpu->arch.osvw.length = data;
3285 break;
3286 case MSR_AMD64_OSVW_STATUS:
3287 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3288 return 1;
3289 vcpu->arch.osvw.status = data;
3290 break;
3291 case MSR_PLATFORM_INFO:
3292 if (!msr_info->host_initiated ||
3293 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3294 cpuid_fault_enabled(vcpu)))
3295 return 1;
3296 vcpu->arch.msr_platform_info = data;
3297 break;
3298 case MSR_MISC_FEATURES_ENABLES:
3299 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3300 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3301 !supports_cpuid_fault(vcpu)))
3302 return 1;
3303 vcpu->arch.msr_misc_features_enables = data;
3304 break;
3305 default:
3306 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3307 return xen_hvm_config(vcpu, data);
3308 if (kvm_pmu_is_valid_msr(vcpu, msr))
3309 return kvm_pmu_set_msr(vcpu, msr_info);
3310 return KVM_MSR_RET_INVALID;
3311 }
3312 return 0;
3313 }
3314 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3315
3316 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3317 {
3318 u64 data;
3319 u64 mcg_cap = vcpu->arch.mcg_cap;
3320 unsigned bank_num = mcg_cap & 0xff;
3321
3322 switch (msr) {
3323 case MSR_IA32_P5_MC_ADDR:
3324 case MSR_IA32_P5_MC_TYPE:
3325 data = 0;
3326 break;
3327 case MSR_IA32_MCG_CAP:
3328 data = vcpu->arch.mcg_cap;
3329 break;
3330 case MSR_IA32_MCG_CTL:
3331 if (!(mcg_cap & MCG_CTL_P) && !host)
3332 return 1;
3333 data = vcpu->arch.mcg_ctl;
3334 break;
3335 case MSR_IA32_MCG_STATUS:
3336 data = vcpu->arch.mcg_status;
3337 break;
3338 default:
3339 if (msr >= MSR_IA32_MC0_CTL &&
3340 msr < MSR_IA32_MCx_CTL(bank_num)) {
3341 u32 offset = array_index_nospec(
3342 msr - MSR_IA32_MC0_CTL,
3343 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3344
3345 data = vcpu->arch.mce_banks[offset];
3346 break;
3347 }
3348 return 1;
3349 }
3350 *pdata = data;
3351 return 0;
3352 }
3353
3354 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3355 {
3356 switch (msr_info->index) {
3357 case MSR_IA32_PLATFORM_ID:
3358 case MSR_IA32_EBL_CR_POWERON:
3359 case MSR_IA32_DEBUGCTLMSR:
3360 case MSR_IA32_LASTBRANCHFROMIP:
3361 case MSR_IA32_LASTBRANCHTOIP:
3362 case MSR_IA32_LASTINTFROMIP:
3363 case MSR_IA32_LASTINTTOIP:
3364 case MSR_K8_SYSCFG:
3365 case MSR_K8_TSEG_ADDR:
3366 case MSR_K8_TSEG_MASK:
3367 case MSR_VM_HSAVE_PA:
3368 case MSR_K8_INT_PENDING_MSG:
3369 case MSR_AMD64_NB_CFG:
3370 case MSR_FAM10H_MMIO_CONF_BASE:
3371 case MSR_AMD64_BU_CFG2:
3372 case MSR_IA32_PERF_CTL:
3373 case MSR_AMD64_DC_CFG:
3374 case MSR_F15H_EX_CFG:
3375 /*
3376 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3377 * limit) MSRs. Just return 0, as we do not want to expose the host
3378 * data here. Do not conditionalize this on CPUID, as KVM does not do
3379 * so for existing CPU-specific MSRs.
3380 */
3381 case MSR_RAPL_POWER_UNIT:
3382 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3383 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3384 case MSR_PKG_ENERGY_STATUS: /* Total package */
3385 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3386 msr_info->data = 0;
3387 break;
3388 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3389 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3390 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3391 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3392 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3393 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3394 return kvm_pmu_get_msr(vcpu, msr_info);
3395 msr_info->data = 0;
3396 break;
3397 case MSR_IA32_UCODE_REV:
3398 msr_info->data = vcpu->arch.microcode_version;
3399 break;
3400 case MSR_IA32_ARCH_CAPABILITIES:
3401 if (!msr_info->host_initiated &&
3402 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3403 return 1;
3404 msr_info->data = vcpu->arch.arch_capabilities;
3405 break;
3406 case MSR_IA32_PERF_CAPABILITIES:
3407 if (!msr_info->host_initiated &&
3408 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3409 return 1;
3410 msr_info->data = vcpu->arch.perf_capabilities;
3411 break;
3412 case MSR_IA32_POWER_CTL:
3413 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3414 break;
3415 case MSR_IA32_TSC: {
3416 /*
3417 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3418 * even when not intercepted. AMD manual doesn't explicitly
3419 * state this but appears to behave the same.
3420 *
3421 * On userspace reads and writes, however, we unconditionally
3422 * return L1's TSC value to ensure backwards-compatible
3423 * behavior for migration.
3424 */
3425 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3426 vcpu->arch.tsc_offset;
3427
3428 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3429 break;
3430 }
3431 case MSR_MTRRcap:
3432 case 0x200 ... 0x2ff:
3433 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3434 case 0xcd: /* fsb frequency */
3435 msr_info->data = 3;
3436 break;
3437 /*
3438 * MSR_EBC_FREQUENCY_ID
3439 * Conservative value valid for even the basic CPU models.
3440 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3441 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3442 * and 266MHz for model 3, or 4. Set Core Clock
3443 * Frequency to System Bus Frequency Ratio to 1 (bits
3444 * 31:24) even though these are only valid for CPU
3445 * models > 2, however guests may end up dividing or
3446 * multiplying by zero otherwise.
3447 */
3448 case MSR_EBC_FREQUENCY_ID:
3449 msr_info->data = 1 << 24;
3450 break;
3451 case MSR_IA32_APICBASE:
3452 msr_info->data = kvm_get_apic_base(vcpu);
3453 break;
3454 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3455 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3456 case MSR_IA32_TSCDEADLINE:
3457 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3458 break;
3459 case MSR_IA32_TSC_ADJUST:
3460 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3461 break;
3462 case MSR_IA32_MISC_ENABLE:
3463 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3464 break;
3465 case MSR_IA32_SMBASE:
3466 if (!msr_info->host_initiated)
3467 return 1;
3468 msr_info->data = vcpu->arch.smbase;
3469 break;
3470 case MSR_SMI_COUNT:
3471 msr_info->data = vcpu->arch.smi_count;
3472 break;
3473 case MSR_IA32_PERF_STATUS:
3474 /* TSC increment by tick */
3475 msr_info->data = 1000ULL;
3476 /* CPU multiplier */
3477 msr_info->data |= (((uint64_t)4ULL) << 40);
3478 break;
3479 case MSR_EFER:
3480 msr_info->data = vcpu->arch.efer;
3481 break;
3482 case MSR_KVM_WALL_CLOCK:
3483 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3484 return 1;
3485
3486 msr_info->data = vcpu->kvm->arch.wall_clock;
3487 break;
3488 case MSR_KVM_WALL_CLOCK_NEW:
3489 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3490 return 1;
3491
3492 msr_info->data = vcpu->kvm->arch.wall_clock;
3493 break;
3494 case MSR_KVM_SYSTEM_TIME:
3495 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3496 return 1;
3497
3498 msr_info->data = vcpu->arch.time;
3499 break;
3500 case MSR_KVM_SYSTEM_TIME_NEW:
3501 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3502 return 1;
3503
3504 msr_info->data = vcpu->arch.time;
3505 break;
3506 case MSR_KVM_ASYNC_PF_EN:
3507 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3508 return 1;
3509
3510 msr_info->data = vcpu->arch.apf.msr_en_val;
3511 break;
3512 case MSR_KVM_ASYNC_PF_INT:
3513 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3514 return 1;
3515
3516 msr_info->data = vcpu->arch.apf.msr_int_val;
3517 break;
3518 case MSR_KVM_ASYNC_PF_ACK:
3519 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3520 return 1;
3521
3522 msr_info->data = 0;
3523 break;
3524 case MSR_KVM_STEAL_TIME:
3525 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3526 return 1;
3527
3528 msr_info->data = vcpu->arch.st.msr_val;
3529 break;
3530 case MSR_KVM_PV_EOI_EN:
3531 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3532 return 1;
3533
3534 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3535 break;
3536 case MSR_KVM_POLL_CONTROL:
3537 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3538 return 1;
3539
3540 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3541 break;
3542 case MSR_IA32_P5_MC_ADDR:
3543 case MSR_IA32_P5_MC_TYPE:
3544 case MSR_IA32_MCG_CAP:
3545 case MSR_IA32_MCG_CTL:
3546 case MSR_IA32_MCG_STATUS:
3547 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3548 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3549 msr_info->host_initiated);
3550 case MSR_IA32_XSS:
3551 if (!msr_info->host_initiated &&
3552 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3553 return 1;
3554 msr_info->data = vcpu->arch.ia32_xss;
3555 break;
3556 case MSR_K7_CLK_CTL:
3557 /*
3558 * Provide expected ramp-up count for K7. All other
3559 * are set to zero, indicating minimum divisors for
3560 * every field.
3561 *
3562 * This prevents guest kernels on AMD host with CPU
3563 * type 6, model 8 and higher from exploding due to
3564 * the rdmsr failing.
3565 */
3566 msr_info->data = 0x20000000;
3567 break;
3568 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3569 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3570 case HV_X64_MSR_SYNDBG_OPTIONS:
3571 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3572 case HV_X64_MSR_CRASH_CTL:
3573 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3574 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3575 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3576 case HV_X64_MSR_TSC_EMULATION_STATUS:
3577 return kvm_hv_get_msr_common(vcpu,
3578 msr_info->index, &msr_info->data,
3579 msr_info->host_initiated);
3580 case MSR_IA32_BBL_CR_CTL3:
3581 /* This legacy MSR exists but isn't fully documented in current
3582 * silicon. It is however accessed by winxp in very narrow
3583 * scenarios where it sets bit #19, itself documented as
3584 * a "reserved" bit. Best effort attempt to source coherent
3585 * read data here should the balance of the register be
3586 * interpreted by the guest:
3587 *
3588 * L2 cache control register 3: 64GB range, 256KB size,
3589 * enabled, latency 0x1, configured
3590 */
3591 msr_info->data = 0xbe702111;
3592 break;
3593 case MSR_AMD64_OSVW_ID_LENGTH:
3594 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3595 return 1;
3596 msr_info->data = vcpu->arch.osvw.length;
3597 break;
3598 case MSR_AMD64_OSVW_STATUS:
3599 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3600 return 1;
3601 msr_info->data = vcpu->arch.osvw.status;
3602 break;
3603 case MSR_PLATFORM_INFO:
3604 if (!msr_info->host_initiated &&
3605 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3606 return 1;
3607 msr_info->data = vcpu->arch.msr_platform_info;
3608 break;
3609 case MSR_MISC_FEATURES_ENABLES:
3610 msr_info->data = vcpu->arch.msr_misc_features_enables;
3611 break;
3612 case MSR_K7_HWCR:
3613 msr_info->data = vcpu->arch.msr_hwcr;
3614 break;
3615 default:
3616 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3617 return kvm_pmu_get_msr(vcpu, msr_info);
3618 return KVM_MSR_RET_INVALID;
3619 }
3620 return 0;
3621 }
3622 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3623
3624 /*
3625 * Read or write a bunch of msrs. All parameters are kernel addresses.
3626 *
3627 * @return number of msrs set successfully.
3628 */
3629 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3630 struct kvm_msr_entry *entries,
3631 int (*do_msr)(struct kvm_vcpu *vcpu,
3632 unsigned index, u64 *data))
3633 {
3634 int i;
3635
3636 for (i = 0; i < msrs->nmsrs; ++i)
3637 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3638 break;
3639
3640 return i;
3641 }
3642
3643 /*
3644 * Read or write a bunch of msrs. Parameters are user addresses.
3645 *
3646 * @return number of msrs set successfully.
3647 */
3648 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3649 int (*do_msr)(struct kvm_vcpu *vcpu,
3650 unsigned index, u64 *data),
3651 int writeback)
3652 {
3653 struct kvm_msrs msrs;
3654 struct kvm_msr_entry *entries;
3655 int r, n;
3656 unsigned size;
3657
3658 r = -EFAULT;
3659 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3660 goto out;
3661
3662 r = -E2BIG;
3663 if (msrs.nmsrs >= MAX_IO_MSRS)
3664 goto out;
3665
3666 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3667 entries = memdup_user(user_msrs->entries, size);
3668 if (IS_ERR(entries)) {
3669 r = PTR_ERR(entries);
3670 goto out;
3671 }
3672
3673 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3674 if (r < 0)
3675 goto out_free;
3676
3677 r = -EFAULT;
3678 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3679 goto out_free;
3680
3681 r = n;
3682
3683 out_free:
3684 kfree(entries);
3685 out:
3686 return r;
3687 }
3688
3689 static inline bool kvm_can_mwait_in_guest(void)
3690 {
3691 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3692 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3693 boot_cpu_has(X86_FEATURE_ARAT);
3694 }
3695
3696 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
3697 struct kvm_cpuid2 __user *cpuid_arg)
3698 {
3699 struct kvm_cpuid2 cpuid;
3700 int r;
3701
3702 r = -EFAULT;
3703 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3704 return r;
3705
3706 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3707 if (r)
3708 return r;
3709
3710 r = -EFAULT;
3711 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3712 return r;
3713
3714 return 0;
3715 }
3716
3717 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3718 {
3719 int r = 0;
3720
3721 switch (ext) {
3722 case KVM_CAP_IRQCHIP:
3723 case KVM_CAP_HLT:
3724 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3725 case KVM_CAP_SET_TSS_ADDR:
3726 case KVM_CAP_EXT_CPUID:
3727 case KVM_CAP_EXT_EMUL_CPUID:
3728 case KVM_CAP_CLOCKSOURCE:
3729 case KVM_CAP_PIT:
3730 case KVM_CAP_NOP_IO_DELAY:
3731 case KVM_CAP_MP_STATE:
3732 case KVM_CAP_SYNC_MMU:
3733 case KVM_CAP_USER_NMI:
3734 case KVM_CAP_REINJECT_CONTROL:
3735 case KVM_CAP_IRQ_INJECT_STATUS:
3736 case KVM_CAP_IOEVENTFD:
3737 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3738 case KVM_CAP_PIT2:
3739 case KVM_CAP_PIT_STATE2:
3740 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3741 case KVM_CAP_XEN_HVM:
3742 case KVM_CAP_VCPU_EVENTS:
3743 case KVM_CAP_HYPERV:
3744 case KVM_CAP_HYPERV_VAPIC:
3745 case KVM_CAP_HYPERV_SPIN:
3746 case KVM_CAP_HYPERV_SYNIC:
3747 case KVM_CAP_HYPERV_SYNIC2:
3748 case KVM_CAP_HYPERV_VP_INDEX:
3749 case KVM_CAP_HYPERV_EVENTFD:
3750 case KVM_CAP_HYPERV_TLBFLUSH:
3751 case KVM_CAP_HYPERV_SEND_IPI:
3752 case KVM_CAP_HYPERV_CPUID:
3753 case KVM_CAP_SYS_HYPERV_CPUID:
3754 case KVM_CAP_PCI_SEGMENT:
3755 case KVM_CAP_DEBUGREGS:
3756 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3757 case KVM_CAP_XSAVE:
3758 case KVM_CAP_ASYNC_PF:
3759 case KVM_CAP_ASYNC_PF_INT:
3760 case KVM_CAP_GET_TSC_KHZ:
3761 case KVM_CAP_KVMCLOCK_CTRL:
3762 case KVM_CAP_READONLY_MEM:
3763 case KVM_CAP_HYPERV_TIME:
3764 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3765 case KVM_CAP_TSC_DEADLINE_TIMER:
3766 case KVM_CAP_DISABLE_QUIRKS:
3767 case KVM_CAP_SET_BOOT_CPU_ID:
3768 case KVM_CAP_SPLIT_IRQCHIP:
3769 case KVM_CAP_IMMEDIATE_EXIT:
3770 case KVM_CAP_PMU_EVENT_FILTER:
3771 case KVM_CAP_GET_MSR_FEATURES:
3772 case KVM_CAP_MSR_PLATFORM_INFO:
3773 case KVM_CAP_EXCEPTION_PAYLOAD:
3774 case KVM_CAP_SET_GUEST_DEBUG:
3775 case KVM_CAP_LAST_CPU:
3776 case KVM_CAP_X86_USER_SPACE_MSR:
3777 case KVM_CAP_X86_MSR_FILTER:
3778 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
3779 r = 1;
3780 break;
3781 case KVM_CAP_SYNC_REGS:
3782 r = KVM_SYNC_X86_VALID_FIELDS;
3783 break;
3784 case KVM_CAP_ADJUST_CLOCK:
3785 r = KVM_CLOCK_TSC_STABLE;
3786 break;
3787 case KVM_CAP_X86_DISABLE_EXITS:
3788 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3789 KVM_X86_DISABLE_EXITS_CSTATE;
3790 if(kvm_can_mwait_in_guest())
3791 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3792 break;
3793 case KVM_CAP_X86_SMM:
3794 /* SMBASE is usually relocated above 1M on modern chipsets,
3795 * and SMM handlers might indeed rely on 4G segment limits,
3796 * so do not report SMM to be available if real mode is
3797 * emulated via vm86 mode. Still, do not go to great lengths
3798 * to avoid userspace's usage of the feature, because it is a
3799 * fringe case that is not enabled except via specific settings
3800 * of the module parameters.
3801 */
3802 r = kvm_x86_ops.has_emulated_msr(kvm, MSR_IA32_SMBASE);
3803 break;
3804 case KVM_CAP_VAPIC:
3805 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3806 break;
3807 case KVM_CAP_NR_VCPUS:
3808 r = KVM_SOFT_MAX_VCPUS;
3809 break;
3810 case KVM_CAP_MAX_VCPUS:
3811 r = KVM_MAX_VCPUS;
3812 break;
3813 case KVM_CAP_MAX_VCPU_ID:
3814 r = KVM_MAX_VCPU_ID;
3815 break;
3816 case KVM_CAP_PV_MMU: /* obsolete */
3817 r = 0;
3818 break;
3819 case KVM_CAP_MCE:
3820 r = KVM_MAX_MCE_BANKS;
3821 break;
3822 case KVM_CAP_XCRS:
3823 r = boot_cpu_has(X86_FEATURE_XSAVE);
3824 break;
3825 case KVM_CAP_TSC_CONTROL:
3826 r = kvm_has_tsc_control;
3827 break;
3828 case KVM_CAP_X2APIC_API:
3829 r = KVM_X2APIC_API_VALID_FLAGS;
3830 break;
3831 case KVM_CAP_NESTED_STATE:
3832 r = kvm_x86_ops.nested_ops->get_state ?
3833 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3834 break;
3835 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3836 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3837 break;
3838 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3839 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3840 break;
3841 case KVM_CAP_SMALLER_MAXPHYADDR:
3842 r = (int) allow_smaller_maxphyaddr;
3843 break;
3844 case KVM_CAP_STEAL_TIME:
3845 r = sched_info_on();
3846 break;
3847 default:
3848 break;
3849 }
3850 return r;
3851
3852 }
3853
3854 long kvm_arch_dev_ioctl(struct file *filp,
3855 unsigned int ioctl, unsigned long arg)
3856 {
3857 void __user *argp = (void __user *)arg;
3858 long r;
3859
3860 switch (ioctl) {
3861 case KVM_GET_MSR_INDEX_LIST: {
3862 struct kvm_msr_list __user *user_msr_list = argp;
3863 struct kvm_msr_list msr_list;
3864 unsigned n;
3865
3866 r = -EFAULT;
3867 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3868 goto out;
3869 n = msr_list.nmsrs;
3870 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3871 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3872 goto out;
3873 r = -E2BIG;
3874 if (n < msr_list.nmsrs)
3875 goto out;
3876 r = -EFAULT;
3877 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3878 num_msrs_to_save * sizeof(u32)))
3879 goto out;
3880 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3881 &emulated_msrs,
3882 num_emulated_msrs * sizeof(u32)))
3883 goto out;
3884 r = 0;
3885 break;
3886 }
3887 case KVM_GET_SUPPORTED_CPUID:
3888 case KVM_GET_EMULATED_CPUID: {
3889 struct kvm_cpuid2 __user *cpuid_arg = argp;
3890 struct kvm_cpuid2 cpuid;
3891
3892 r = -EFAULT;
3893 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3894 goto out;
3895
3896 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3897 ioctl);
3898 if (r)
3899 goto out;
3900
3901 r = -EFAULT;
3902 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3903 goto out;
3904 r = 0;
3905 break;
3906 }
3907 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3908 r = -EFAULT;
3909 if (copy_to_user(argp, &kvm_mce_cap_supported,
3910 sizeof(kvm_mce_cap_supported)))
3911 goto out;
3912 r = 0;
3913 break;
3914 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3915 struct kvm_msr_list __user *user_msr_list = argp;
3916 struct kvm_msr_list msr_list;
3917 unsigned int n;
3918
3919 r = -EFAULT;
3920 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3921 goto out;
3922 n = msr_list.nmsrs;
3923 msr_list.nmsrs = num_msr_based_features;
3924 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3925 goto out;
3926 r = -E2BIG;
3927 if (n < msr_list.nmsrs)
3928 goto out;
3929 r = -EFAULT;
3930 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3931 num_msr_based_features * sizeof(u32)))
3932 goto out;
3933 r = 0;
3934 break;
3935 }
3936 case KVM_GET_MSRS:
3937 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3938 break;
3939 case KVM_GET_SUPPORTED_HV_CPUID:
3940 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
3941 break;
3942 default:
3943 r = -EINVAL;
3944 break;
3945 }
3946 out:
3947 return r;
3948 }
3949
3950 static void wbinvd_ipi(void *garbage)
3951 {
3952 wbinvd();
3953 }
3954
3955 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3956 {
3957 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3958 }
3959
3960 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3961 {
3962 /* Address WBINVD may be executed by guest */
3963 if (need_emulate_wbinvd(vcpu)) {
3964 if (kvm_x86_ops.has_wbinvd_exit())
3965 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3966 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3967 smp_call_function_single(vcpu->cpu,
3968 wbinvd_ipi, NULL, 1);
3969 }
3970
3971 kvm_x86_ops.vcpu_load(vcpu, cpu);
3972
3973 /* Save host pkru register if supported */
3974 vcpu->arch.host_pkru = read_pkru();
3975
3976 /* Apply any externally detected TSC adjustments (due to suspend) */
3977 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3978 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3979 vcpu->arch.tsc_offset_adjustment = 0;
3980 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3981 }
3982
3983 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3984 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3985 rdtsc() - vcpu->arch.last_host_tsc;
3986 if (tsc_delta < 0)
3987 mark_tsc_unstable("KVM discovered backwards TSC");
3988
3989 if (kvm_check_tsc_unstable()) {
3990 u64 offset = kvm_compute_tsc_offset(vcpu,
3991 vcpu->arch.last_guest_tsc);
3992 kvm_vcpu_write_tsc_offset(vcpu, offset);
3993 vcpu->arch.tsc_catchup = 1;
3994 }
3995
3996 if (kvm_lapic_hv_timer_in_use(vcpu))
3997 kvm_lapic_restart_hv_timer(vcpu);
3998
3999 /*
4000 * On a host with synchronized TSC, there is no need to update
4001 * kvmclock on vcpu->cpu migration
4002 */
4003 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4004 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4005 if (vcpu->cpu != cpu)
4006 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4007 vcpu->cpu = cpu;
4008 }
4009
4010 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4011 }
4012
4013 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4014 {
4015 struct kvm_host_map map;
4016 struct kvm_steal_time *st;
4017
4018 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4019 return;
4020
4021 if (vcpu->arch.st.preempted)
4022 return;
4023
4024 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
4025 &vcpu->arch.st.cache, true))
4026 return;
4027
4028 st = map.hva +
4029 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
4030
4031 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4032
4033 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
4034 }
4035
4036 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4037 {
4038 int idx;
4039
4040 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4041 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
4042
4043 /*
4044 * kvm_memslots() will be called by
4045 * kvm_write_guest_offset_cached() so take the srcu lock.
4046 */
4047 idx = srcu_read_lock(&vcpu->kvm->srcu);
4048 kvm_steal_time_set_preempted(vcpu);
4049 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4050 kvm_x86_ops.vcpu_put(vcpu);
4051 vcpu->arch.last_host_tsc = rdtsc();
4052 /*
4053 * If userspace has set any breakpoints or watchpoints, dr6 is restored
4054 * on every vmexit, but if not, we might have a stale dr6 from the
4055 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
4056 */
4057 set_debugreg(0, 6);
4058 }
4059
4060 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4061 struct kvm_lapic_state *s)
4062 {
4063 if (vcpu->arch.apicv_active)
4064 kvm_x86_ops.sync_pir_to_irr(vcpu);
4065
4066 return kvm_apic_get_state(vcpu, s);
4067 }
4068
4069 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4070 struct kvm_lapic_state *s)
4071 {
4072 int r;
4073
4074 r = kvm_apic_set_state(vcpu, s);
4075 if (r)
4076 return r;
4077 update_cr8_intercept(vcpu);
4078
4079 return 0;
4080 }
4081
4082 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4083 {
4084 /*
4085 * We can accept userspace's request for interrupt injection
4086 * as long as we have a place to store the interrupt number.
4087 * The actual injection will happen when the CPU is able to
4088 * deliver the interrupt.
4089 */
4090 if (kvm_cpu_has_extint(vcpu))
4091 return false;
4092
4093 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4094 return (!lapic_in_kernel(vcpu) ||
4095 kvm_apic_accept_pic_intr(vcpu));
4096 }
4097
4098 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4099 {
4100 return kvm_arch_interrupt_allowed(vcpu) &&
4101 kvm_cpu_accept_dm_intr(vcpu);
4102 }
4103
4104 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4105 struct kvm_interrupt *irq)
4106 {
4107 if (irq->irq >= KVM_NR_INTERRUPTS)
4108 return -EINVAL;
4109
4110 if (!irqchip_in_kernel(vcpu->kvm)) {
4111 kvm_queue_interrupt(vcpu, irq->irq, false);
4112 kvm_make_request(KVM_REQ_EVENT, vcpu);
4113 return 0;
4114 }
4115
4116 /*
4117 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4118 * fail for in-kernel 8259.
4119 */
4120 if (pic_in_kernel(vcpu->kvm))
4121 return -ENXIO;
4122
4123 if (vcpu->arch.pending_external_vector != -1)
4124 return -EEXIST;
4125
4126 vcpu->arch.pending_external_vector = irq->irq;
4127 kvm_make_request(KVM_REQ_EVENT, vcpu);
4128 return 0;
4129 }
4130
4131 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4132 {
4133 kvm_inject_nmi(vcpu);
4134
4135 return 0;
4136 }
4137
4138 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4139 {
4140 kvm_make_request(KVM_REQ_SMI, vcpu);
4141
4142 return 0;
4143 }
4144
4145 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4146 struct kvm_tpr_access_ctl *tac)
4147 {
4148 if (tac->flags)
4149 return -EINVAL;
4150 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4151 return 0;
4152 }
4153
4154 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4155 u64 mcg_cap)
4156 {
4157 int r;
4158 unsigned bank_num = mcg_cap & 0xff, bank;
4159
4160 r = -EINVAL;
4161 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4162 goto out;
4163 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4164 goto out;
4165 r = 0;
4166 vcpu->arch.mcg_cap = mcg_cap;
4167 /* Init IA32_MCG_CTL to all 1s */
4168 if (mcg_cap & MCG_CTL_P)
4169 vcpu->arch.mcg_ctl = ~(u64)0;
4170 /* Init IA32_MCi_CTL to all 1s */
4171 for (bank = 0; bank < bank_num; bank++)
4172 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4173
4174 kvm_x86_ops.setup_mce(vcpu);
4175 out:
4176 return r;
4177 }
4178
4179 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4180 struct kvm_x86_mce *mce)
4181 {
4182 u64 mcg_cap = vcpu->arch.mcg_cap;
4183 unsigned bank_num = mcg_cap & 0xff;
4184 u64 *banks = vcpu->arch.mce_banks;
4185
4186 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4187 return -EINVAL;
4188 /*
4189 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4190 * reporting is disabled
4191 */
4192 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4193 vcpu->arch.mcg_ctl != ~(u64)0)
4194 return 0;
4195 banks += 4 * mce->bank;
4196 /*
4197 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4198 * reporting is disabled for the bank
4199 */
4200 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4201 return 0;
4202 if (mce->status & MCI_STATUS_UC) {
4203 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4204 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4205 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4206 return 0;
4207 }
4208 if (banks[1] & MCI_STATUS_VAL)
4209 mce->status |= MCI_STATUS_OVER;
4210 banks[2] = mce->addr;
4211 banks[3] = mce->misc;
4212 vcpu->arch.mcg_status = mce->mcg_status;
4213 banks[1] = mce->status;
4214 kvm_queue_exception(vcpu, MC_VECTOR);
4215 } else if (!(banks[1] & MCI_STATUS_VAL)
4216 || !(banks[1] & MCI_STATUS_UC)) {
4217 if (banks[1] & MCI_STATUS_VAL)
4218 mce->status |= MCI_STATUS_OVER;
4219 banks[2] = mce->addr;
4220 banks[3] = mce->misc;
4221 banks[1] = mce->status;
4222 } else
4223 banks[1] |= MCI_STATUS_OVER;
4224 return 0;
4225 }
4226
4227 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4228 struct kvm_vcpu_events *events)
4229 {
4230 process_nmi(vcpu);
4231
4232 if (kvm_check_request(KVM_REQ_SMI, vcpu))
4233 process_smi(vcpu);
4234
4235 /*
4236 * In guest mode, payload delivery should be deferred,
4237 * so that the L1 hypervisor can intercept #PF before
4238 * CR2 is modified (or intercept #DB before DR6 is
4239 * modified under nVMX). Unless the per-VM capability,
4240 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4241 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4242 * opportunistically defer the exception payload, deliver it if the
4243 * capability hasn't been requested before processing a
4244 * KVM_GET_VCPU_EVENTS.
4245 */
4246 if (!vcpu->kvm->arch.exception_payload_enabled &&
4247 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4248 kvm_deliver_exception_payload(vcpu);
4249
4250 /*
4251 * The API doesn't provide the instruction length for software
4252 * exceptions, so don't report them. As long as the guest RIP
4253 * isn't advanced, we should expect to encounter the exception
4254 * again.
4255 */
4256 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4257 events->exception.injected = 0;
4258 events->exception.pending = 0;
4259 } else {
4260 events->exception.injected = vcpu->arch.exception.injected;
4261 events->exception.pending = vcpu->arch.exception.pending;
4262 /*
4263 * For ABI compatibility, deliberately conflate
4264 * pending and injected exceptions when
4265 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4266 */
4267 if (!vcpu->kvm->arch.exception_payload_enabled)
4268 events->exception.injected |=
4269 vcpu->arch.exception.pending;
4270 }
4271 events->exception.nr = vcpu->arch.exception.nr;
4272 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4273 events->exception.error_code = vcpu->arch.exception.error_code;
4274 events->exception_has_payload = vcpu->arch.exception.has_payload;
4275 events->exception_payload = vcpu->arch.exception.payload;
4276
4277 events->interrupt.injected =
4278 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4279 events->interrupt.nr = vcpu->arch.interrupt.nr;
4280 events->interrupt.soft = 0;
4281 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4282
4283 events->nmi.injected = vcpu->arch.nmi_injected;
4284 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4285 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4286 events->nmi.pad = 0;
4287
4288 events->sipi_vector = 0; /* never valid when reporting to user space */
4289
4290 events->smi.smm = is_smm(vcpu);
4291 events->smi.pending = vcpu->arch.smi_pending;
4292 events->smi.smm_inside_nmi =
4293 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4294 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4295
4296 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4297 | KVM_VCPUEVENT_VALID_SHADOW
4298 | KVM_VCPUEVENT_VALID_SMM);
4299 if (vcpu->kvm->arch.exception_payload_enabled)
4300 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4301
4302 memset(&events->reserved, 0, sizeof(events->reserved));
4303 }
4304
4305 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4306
4307 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4308 struct kvm_vcpu_events *events)
4309 {
4310 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4311 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4312 | KVM_VCPUEVENT_VALID_SHADOW
4313 | KVM_VCPUEVENT_VALID_SMM
4314 | KVM_VCPUEVENT_VALID_PAYLOAD))
4315 return -EINVAL;
4316
4317 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4318 if (!vcpu->kvm->arch.exception_payload_enabled)
4319 return -EINVAL;
4320 if (events->exception.pending)
4321 events->exception.injected = 0;
4322 else
4323 events->exception_has_payload = 0;
4324 } else {
4325 events->exception.pending = 0;
4326 events->exception_has_payload = 0;
4327 }
4328
4329 if ((events->exception.injected || events->exception.pending) &&
4330 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4331 return -EINVAL;
4332
4333 /* INITs are latched while in SMM */
4334 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4335 (events->smi.smm || events->smi.pending) &&
4336 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4337 return -EINVAL;
4338
4339 process_nmi(vcpu);
4340 vcpu->arch.exception.injected = events->exception.injected;
4341 vcpu->arch.exception.pending = events->exception.pending;
4342 vcpu->arch.exception.nr = events->exception.nr;
4343 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4344 vcpu->arch.exception.error_code = events->exception.error_code;
4345 vcpu->arch.exception.has_payload = events->exception_has_payload;
4346 vcpu->arch.exception.payload = events->exception_payload;
4347
4348 vcpu->arch.interrupt.injected = events->interrupt.injected;
4349 vcpu->arch.interrupt.nr = events->interrupt.nr;
4350 vcpu->arch.interrupt.soft = events->interrupt.soft;
4351 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4352 kvm_x86_ops.set_interrupt_shadow(vcpu,
4353 events->interrupt.shadow);
4354
4355 vcpu->arch.nmi_injected = events->nmi.injected;
4356 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4357 vcpu->arch.nmi_pending = events->nmi.pending;
4358 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4359
4360 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4361 lapic_in_kernel(vcpu))
4362 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4363
4364 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4365 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4366 if (events->smi.smm)
4367 vcpu->arch.hflags |= HF_SMM_MASK;
4368 else
4369 vcpu->arch.hflags &= ~HF_SMM_MASK;
4370 kvm_smm_changed(vcpu);
4371 }
4372
4373 vcpu->arch.smi_pending = events->smi.pending;
4374
4375 if (events->smi.smm) {
4376 if (events->smi.smm_inside_nmi)
4377 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4378 else
4379 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4380 }
4381
4382 if (lapic_in_kernel(vcpu)) {
4383 if (events->smi.latched_init)
4384 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4385 else
4386 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4387 }
4388 }
4389
4390 kvm_make_request(KVM_REQ_EVENT, vcpu);
4391
4392 return 0;
4393 }
4394
4395 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4396 struct kvm_debugregs *dbgregs)
4397 {
4398 unsigned long val;
4399
4400 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4401 kvm_get_dr(vcpu, 6, &val);
4402 dbgregs->dr6 = val;
4403 dbgregs->dr7 = vcpu->arch.dr7;
4404 dbgregs->flags = 0;
4405 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4406 }
4407
4408 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4409 struct kvm_debugregs *dbgregs)
4410 {
4411 if (dbgregs->flags)
4412 return -EINVAL;
4413
4414 if (dbgregs->dr6 & ~0xffffffffull)
4415 return -EINVAL;
4416 if (dbgregs->dr7 & ~0xffffffffull)
4417 return -EINVAL;
4418
4419 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4420 kvm_update_dr0123(vcpu);
4421 vcpu->arch.dr6 = dbgregs->dr6;
4422 vcpu->arch.dr7 = dbgregs->dr7;
4423 kvm_update_dr7(vcpu);
4424
4425 return 0;
4426 }
4427
4428 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4429
4430 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4431 {
4432 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4433 u64 xstate_bv = xsave->header.xfeatures;
4434 u64 valid;
4435
4436 /*
4437 * Copy legacy XSAVE area, to avoid complications with CPUID
4438 * leaves 0 and 1 in the loop below.
4439 */
4440 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4441
4442 /* Set XSTATE_BV */
4443 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4444 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4445
4446 /*
4447 * Copy each region from the possibly compacted offset to the
4448 * non-compacted offset.
4449 */
4450 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4451 while (valid) {
4452 u64 xfeature_mask = valid & -valid;
4453 int xfeature_nr = fls64(xfeature_mask) - 1;
4454 void *src = get_xsave_addr(xsave, xfeature_nr);
4455
4456 if (src) {
4457 u32 size, offset, ecx, edx;
4458 cpuid_count(XSTATE_CPUID, xfeature_nr,
4459 &size, &offset, &ecx, &edx);
4460 if (xfeature_nr == XFEATURE_PKRU)
4461 memcpy(dest + offset, &vcpu->arch.pkru,
4462 sizeof(vcpu->arch.pkru));
4463 else
4464 memcpy(dest + offset, src, size);
4465
4466 }
4467
4468 valid -= xfeature_mask;
4469 }
4470 }
4471
4472 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4473 {
4474 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4475 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4476 u64 valid;
4477
4478 /*
4479 * Copy legacy XSAVE area, to avoid complications with CPUID
4480 * leaves 0 and 1 in the loop below.
4481 */
4482 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4483
4484 /* Set XSTATE_BV and possibly XCOMP_BV. */
4485 xsave->header.xfeatures = xstate_bv;
4486 if (boot_cpu_has(X86_FEATURE_XSAVES))
4487 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4488
4489 /*
4490 * Copy each region from the non-compacted offset to the
4491 * possibly compacted offset.
4492 */
4493 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4494 while (valid) {
4495 u64 xfeature_mask = valid & -valid;
4496 int xfeature_nr = fls64(xfeature_mask) - 1;
4497 void *dest = get_xsave_addr(xsave, xfeature_nr);
4498
4499 if (dest) {
4500 u32 size, offset, ecx, edx;
4501 cpuid_count(XSTATE_CPUID, xfeature_nr,
4502 &size, &offset, &ecx, &edx);
4503 if (xfeature_nr == XFEATURE_PKRU)
4504 memcpy(&vcpu->arch.pkru, src + offset,
4505 sizeof(vcpu->arch.pkru));
4506 else
4507 memcpy(dest, src + offset, size);
4508 }
4509
4510 valid -= xfeature_mask;
4511 }
4512 }
4513
4514 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4515 struct kvm_xsave *guest_xsave)
4516 {
4517 if (!vcpu->arch.guest_fpu)
4518 return;
4519
4520 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4521 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4522 fill_xsave((u8 *) guest_xsave->region, vcpu);
4523 } else {
4524 memcpy(guest_xsave->region,
4525 &vcpu->arch.guest_fpu->state.fxsave,
4526 sizeof(struct fxregs_state));
4527 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4528 XFEATURE_MASK_FPSSE;
4529 }
4530 }
4531
4532 #define XSAVE_MXCSR_OFFSET 24
4533
4534 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4535 struct kvm_xsave *guest_xsave)
4536 {
4537 u64 xstate_bv;
4538 u32 mxcsr;
4539
4540 if (!vcpu->arch.guest_fpu)
4541 return 0;
4542
4543 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4544 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4545
4546 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4547 /*
4548 * Here we allow setting states that are not present in
4549 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4550 * with old userspace.
4551 */
4552 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4553 return -EINVAL;
4554 load_xsave(vcpu, (u8 *)guest_xsave->region);
4555 } else {
4556 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4557 mxcsr & ~mxcsr_feature_mask)
4558 return -EINVAL;
4559 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4560 guest_xsave->region, sizeof(struct fxregs_state));
4561 }
4562 return 0;
4563 }
4564
4565 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4566 struct kvm_xcrs *guest_xcrs)
4567 {
4568 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4569 guest_xcrs->nr_xcrs = 0;
4570 return;
4571 }
4572
4573 guest_xcrs->nr_xcrs = 1;
4574 guest_xcrs->flags = 0;
4575 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4576 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4577 }
4578
4579 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4580 struct kvm_xcrs *guest_xcrs)
4581 {
4582 int i, r = 0;
4583
4584 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4585 return -EINVAL;
4586
4587 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4588 return -EINVAL;
4589
4590 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4591 /* Only support XCR0 currently */
4592 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4593 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4594 guest_xcrs->xcrs[i].value);
4595 break;
4596 }
4597 if (r)
4598 r = -EINVAL;
4599 return r;
4600 }
4601
4602 /*
4603 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4604 * stopped by the hypervisor. This function will be called from the host only.
4605 * EINVAL is returned when the host attempts to set the flag for a guest that
4606 * does not support pv clocks.
4607 */
4608 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4609 {
4610 if (!vcpu->arch.pv_time_enabled)
4611 return -EINVAL;
4612 vcpu->arch.pvclock_set_guest_stopped_request = true;
4613 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4614 return 0;
4615 }
4616
4617 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4618 struct kvm_enable_cap *cap)
4619 {
4620 int r;
4621 uint16_t vmcs_version;
4622 void __user *user_ptr;
4623
4624 if (cap->flags)
4625 return -EINVAL;
4626
4627 switch (cap->cap) {
4628 case KVM_CAP_HYPERV_SYNIC2:
4629 if (cap->args[0])
4630 return -EINVAL;
4631 fallthrough;
4632
4633 case KVM_CAP_HYPERV_SYNIC:
4634 if (!irqchip_in_kernel(vcpu->kvm))
4635 return -EINVAL;
4636 return kvm_hv_activate_synic(vcpu, cap->cap ==
4637 KVM_CAP_HYPERV_SYNIC2);
4638 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4639 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4640 return -ENOTTY;
4641 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4642 if (!r) {
4643 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4644 if (copy_to_user(user_ptr, &vmcs_version,
4645 sizeof(vmcs_version)))
4646 r = -EFAULT;
4647 }
4648 return r;
4649 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4650 if (!kvm_x86_ops.enable_direct_tlbflush)
4651 return -ENOTTY;
4652
4653 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4654
4655 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4656 vcpu->arch.pv_cpuid.enforce = cap->args[0];
4657 if (vcpu->arch.pv_cpuid.enforce)
4658 kvm_update_pv_runtime(vcpu);
4659
4660 return 0;
4661
4662 default:
4663 return -EINVAL;
4664 }
4665 }
4666
4667 long kvm_arch_vcpu_ioctl(struct file *filp,
4668 unsigned int ioctl, unsigned long arg)
4669 {
4670 struct kvm_vcpu *vcpu = filp->private_data;
4671 void __user *argp = (void __user *)arg;
4672 int r;
4673 union {
4674 struct kvm_lapic_state *lapic;
4675 struct kvm_xsave *xsave;
4676 struct kvm_xcrs *xcrs;
4677 void *buffer;
4678 } u;
4679
4680 vcpu_load(vcpu);
4681
4682 u.buffer = NULL;
4683 switch (ioctl) {
4684 case KVM_GET_LAPIC: {
4685 r = -EINVAL;
4686 if (!lapic_in_kernel(vcpu))
4687 goto out;
4688 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4689 GFP_KERNEL_ACCOUNT);
4690
4691 r = -ENOMEM;
4692 if (!u.lapic)
4693 goto out;
4694 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4695 if (r)
4696 goto out;
4697 r = -EFAULT;
4698 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4699 goto out;
4700 r = 0;
4701 break;
4702 }
4703 case KVM_SET_LAPIC: {
4704 r = -EINVAL;
4705 if (!lapic_in_kernel(vcpu))
4706 goto out;
4707 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4708 if (IS_ERR(u.lapic)) {
4709 r = PTR_ERR(u.lapic);
4710 goto out_nofree;
4711 }
4712
4713 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4714 break;
4715 }
4716 case KVM_INTERRUPT: {
4717 struct kvm_interrupt irq;
4718
4719 r = -EFAULT;
4720 if (copy_from_user(&irq, argp, sizeof(irq)))
4721 goto out;
4722 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4723 break;
4724 }
4725 case KVM_NMI: {
4726 r = kvm_vcpu_ioctl_nmi(vcpu);
4727 break;
4728 }
4729 case KVM_SMI: {
4730 r = kvm_vcpu_ioctl_smi(vcpu);
4731 break;
4732 }
4733 case KVM_SET_CPUID: {
4734 struct kvm_cpuid __user *cpuid_arg = argp;
4735 struct kvm_cpuid cpuid;
4736
4737 r = -EFAULT;
4738 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4739 goto out;
4740 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4741 break;
4742 }
4743 case KVM_SET_CPUID2: {
4744 struct kvm_cpuid2 __user *cpuid_arg = argp;
4745 struct kvm_cpuid2 cpuid;
4746
4747 r = -EFAULT;
4748 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4749 goto out;
4750 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4751 cpuid_arg->entries);
4752 break;
4753 }
4754 case KVM_GET_CPUID2: {
4755 struct kvm_cpuid2 __user *cpuid_arg = argp;
4756 struct kvm_cpuid2 cpuid;
4757
4758 r = -EFAULT;
4759 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4760 goto out;
4761 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4762 cpuid_arg->entries);
4763 if (r)
4764 goto out;
4765 r = -EFAULT;
4766 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4767 goto out;
4768 r = 0;
4769 break;
4770 }
4771 case KVM_GET_MSRS: {
4772 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4773 r = msr_io(vcpu, argp, do_get_msr, 1);
4774 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4775 break;
4776 }
4777 case KVM_SET_MSRS: {
4778 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4779 r = msr_io(vcpu, argp, do_set_msr, 0);
4780 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4781 break;
4782 }
4783 case KVM_TPR_ACCESS_REPORTING: {
4784 struct kvm_tpr_access_ctl tac;
4785
4786 r = -EFAULT;
4787 if (copy_from_user(&tac, argp, sizeof(tac)))
4788 goto out;
4789 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4790 if (r)
4791 goto out;
4792 r = -EFAULT;
4793 if (copy_to_user(argp, &tac, sizeof(tac)))
4794 goto out;
4795 r = 0;
4796 break;
4797 };
4798 case KVM_SET_VAPIC_ADDR: {
4799 struct kvm_vapic_addr va;
4800 int idx;
4801
4802 r = -EINVAL;
4803 if (!lapic_in_kernel(vcpu))
4804 goto out;
4805 r = -EFAULT;
4806 if (copy_from_user(&va, argp, sizeof(va)))
4807 goto out;
4808 idx = srcu_read_lock(&vcpu->kvm->srcu);
4809 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4810 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4811 break;
4812 }
4813 case KVM_X86_SETUP_MCE: {
4814 u64 mcg_cap;
4815
4816 r = -EFAULT;
4817 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4818 goto out;
4819 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4820 break;
4821 }
4822 case KVM_X86_SET_MCE: {
4823 struct kvm_x86_mce mce;
4824
4825 r = -EFAULT;
4826 if (copy_from_user(&mce, argp, sizeof(mce)))
4827 goto out;
4828 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4829 break;
4830 }
4831 case KVM_GET_VCPU_EVENTS: {
4832 struct kvm_vcpu_events events;
4833
4834 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4835
4836 r = -EFAULT;
4837 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4838 break;
4839 r = 0;
4840 break;
4841 }
4842 case KVM_SET_VCPU_EVENTS: {
4843 struct kvm_vcpu_events events;
4844
4845 r = -EFAULT;
4846 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4847 break;
4848
4849 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4850 break;
4851 }
4852 case KVM_GET_DEBUGREGS: {
4853 struct kvm_debugregs dbgregs;
4854
4855 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4856
4857 r = -EFAULT;
4858 if (copy_to_user(argp, &dbgregs,
4859 sizeof(struct kvm_debugregs)))
4860 break;
4861 r = 0;
4862 break;
4863 }
4864 case KVM_SET_DEBUGREGS: {
4865 struct kvm_debugregs dbgregs;
4866
4867 r = -EFAULT;
4868 if (copy_from_user(&dbgregs, argp,
4869 sizeof(struct kvm_debugregs)))
4870 break;
4871
4872 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4873 break;
4874 }
4875 case KVM_GET_XSAVE: {
4876 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4877 r = -ENOMEM;
4878 if (!u.xsave)
4879 break;
4880
4881 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4882
4883 r = -EFAULT;
4884 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4885 break;
4886 r = 0;
4887 break;
4888 }
4889 case KVM_SET_XSAVE: {
4890 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4891 if (IS_ERR(u.xsave)) {
4892 r = PTR_ERR(u.xsave);
4893 goto out_nofree;
4894 }
4895
4896 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4897 break;
4898 }
4899 case KVM_GET_XCRS: {
4900 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4901 r = -ENOMEM;
4902 if (!u.xcrs)
4903 break;
4904
4905 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4906
4907 r = -EFAULT;
4908 if (copy_to_user(argp, u.xcrs,
4909 sizeof(struct kvm_xcrs)))
4910 break;
4911 r = 0;
4912 break;
4913 }
4914 case KVM_SET_XCRS: {
4915 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4916 if (IS_ERR(u.xcrs)) {
4917 r = PTR_ERR(u.xcrs);
4918 goto out_nofree;
4919 }
4920
4921 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4922 break;
4923 }
4924 case KVM_SET_TSC_KHZ: {
4925 u32 user_tsc_khz;
4926
4927 r = -EINVAL;
4928 user_tsc_khz = (u32)arg;
4929
4930 if (kvm_has_tsc_control &&
4931 user_tsc_khz >= kvm_max_guest_tsc_khz)
4932 goto out;
4933
4934 if (user_tsc_khz == 0)
4935 user_tsc_khz = tsc_khz;
4936
4937 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4938 r = 0;
4939
4940 goto out;
4941 }
4942 case KVM_GET_TSC_KHZ: {
4943 r = vcpu->arch.virtual_tsc_khz;
4944 goto out;
4945 }
4946 case KVM_KVMCLOCK_CTRL: {
4947 r = kvm_set_guest_paused(vcpu);
4948 goto out;
4949 }
4950 case KVM_ENABLE_CAP: {
4951 struct kvm_enable_cap cap;
4952
4953 r = -EFAULT;
4954 if (copy_from_user(&cap, argp, sizeof(cap)))
4955 goto out;
4956 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4957 break;
4958 }
4959 case KVM_GET_NESTED_STATE: {
4960 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4961 u32 user_data_size;
4962
4963 r = -EINVAL;
4964 if (!kvm_x86_ops.nested_ops->get_state)
4965 break;
4966
4967 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4968 r = -EFAULT;
4969 if (get_user(user_data_size, &user_kvm_nested_state->size))
4970 break;
4971
4972 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4973 user_data_size);
4974 if (r < 0)
4975 break;
4976
4977 if (r > user_data_size) {
4978 if (put_user(r, &user_kvm_nested_state->size))
4979 r = -EFAULT;
4980 else
4981 r = -E2BIG;
4982 break;
4983 }
4984
4985 r = 0;
4986 break;
4987 }
4988 case KVM_SET_NESTED_STATE: {
4989 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4990 struct kvm_nested_state kvm_state;
4991 int idx;
4992
4993 r = -EINVAL;
4994 if (!kvm_x86_ops.nested_ops->set_state)
4995 break;
4996
4997 r = -EFAULT;
4998 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4999 break;
5000
5001 r = -EINVAL;
5002 if (kvm_state.size < sizeof(kvm_state))
5003 break;
5004
5005 if (kvm_state.flags &
5006 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5007 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5008 | KVM_STATE_NESTED_GIF_SET))
5009 break;
5010
5011 /* nested_run_pending implies guest_mode. */
5012 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5013 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5014 break;
5015
5016 idx = srcu_read_lock(&vcpu->kvm->srcu);
5017 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5018 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5019 break;
5020 }
5021 case KVM_GET_SUPPORTED_HV_CPUID:
5022 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5023 break;
5024 default:
5025 r = -EINVAL;
5026 }
5027 out:
5028 kfree(u.buffer);
5029 out_nofree:
5030 vcpu_put(vcpu);
5031 return r;
5032 }
5033
5034 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5035 {
5036 return VM_FAULT_SIGBUS;
5037 }
5038
5039 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5040 {
5041 int ret;
5042
5043 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5044 return -EINVAL;
5045 ret = kvm_x86_ops.set_tss_addr(kvm, addr);
5046 return ret;
5047 }
5048
5049 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5050 u64 ident_addr)
5051 {
5052 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
5053 }
5054
5055 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5056 unsigned long kvm_nr_mmu_pages)
5057 {
5058 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5059 return -EINVAL;
5060
5061 mutex_lock(&kvm->slots_lock);
5062
5063 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5064 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5065
5066 mutex_unlock(&kvm->slots_lock);
5067 return 0;
5068 }
5069
5070 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5071 {
5072 return kvm->arch.n_max_mmu_pages;
5073 }
5074
5075 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5076 {
5077 struct kvm_pic *pic = kvm->arch.vpic;
5078 int r;
5079
5080 r = 0;
5081 switch (chip->chip_id) {
5082 case KVM_IRQCHIP_PIC_MASTER:
5083 memcpy(&chip->chip.pic, &pic->pics[0],
5084 sizeof(struct kvm_pic_state));
5085 break;
5086 case KVM_IRQCHIP_PIC_SLAVE:
5087 memcpy(&chip->chip.pic, &pic->pics[1],
5088 sizeof(struct kvm_pic_state));
5089 break;
5090 case KVM_IRQCHIP_IOAPIC:
5091 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5092 break;
5093 default:
5094 r = -EINVAL;
5095 break;
5096 }
5097 return r;
5098 }
5099
5100 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5101 {
5102 struct kvm_pic *pic = kvm->arch.vpic;
5103 int r;
5104
5105 r = 0;
5106 switch (chip->chip_id) {
5107 case KVM_IRQCHIP_PIC_MASTER:
5108 spin_lock(&pic->lock);
5109 memcpy(&pic->pics[0], &chip->chip.pic,
5110 sizeof(struct kvm_pic_state));
5111 spin_unlock(&pic->lock);
5112 break;
5113 case KVM_IRQCHIP_PIC_SLAVE:
5114 spin_lock(&pic->lock);
5115 memcpy(&pic->pics[1], &chip->chip.pic,
5116 sizeof(struct kvm_pic_state));
5117 spin_unlock(&pic->lock);
5118 break;
5119 case KVM_IRQCHIP_IOAPIC:
5120 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5121 break;
5122 default:
5123 r = -EINVAL;
5124 break;
5125 }
5126 kvm_pic_update_irq(pic);
5127 return r;
5128 }
5129
5130 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5131 {
5132 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5133
5134 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5135
5136 mutex_lock(&kps->lock);
5137 memcpy(ps, &kps->channels, sizeof(*ps));
5138 mutex_unlock(&kps->lock);
5139 return 0;
5140 }
5141
5142 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5143 {
5144 int i;
5145 struct kvm_pit *pit = kvm->arch.vpit;
5146
5147 mutex_lock(&pit->pit_state.lock);
5148 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5149 for (i = 0; i < 3; i++)
5150 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5151 mutex_unlock(&pit->pit_state.lock);
5152 return 0;
5153 }
5154
5155 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5156 {
5157 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5158 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5159 sizeof(ps->channels));
5160 ps->flags = kvm->arch.vpit->pit_state.flags;
5161 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5162 memset(&ps->reserved, 0, sizeof(ps->reserved));
5163 return 0;
5164 }
5165
5166 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5167 {
5168 int start = 0;
5169 int i;
5170 u32 prev_legacy, cur_legacy;
5171 struct kvm_pit *pit = kvm->arch.vpit;
5172
5173 mutex_lock(&pit->pit_state.lock);
5174 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5175 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5176 if (!prev_legacy && cur_legacy)
5177 start = 1;
5178 memcpy(&pit->pit_state.channels, &ps->channels,
5179 sizeof(pit->pit_state.channels));
5180 pit->pit_state.flags = ps->flags;
5181 for (i = 0; i < 3; i++)
5182 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5183 start && i == 0);
5184 mutex_unlock(&pit->pit_state.lock);
5185 return 0;
5186 }
5187
5188 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5189 struct kvm_reinject_control *control)
5190 {
5191 struct kvm_pit *pit = kvm->arch.vpit;
5192
5193 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5194 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5195 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5196 */
5197 mutex_lock(&pit->pit_state.lock);
5198 kvm_pit_set_reinject(pit, control->pit_reinject);
5199 mutex_unlock(&pit->pit_state.lock);
5200
5201 return 0;
5202 }
5203
5204 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5205 {
5206 /*
5207 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
5208 */
5209 if (kvm_x86_ops.flush_log_dirty)
5210 kvm_x86_ops.flush_log_dirty(kvm);
5211 }
5212
5213 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5214 bool line_status)
5215 {
5216 if (!irqchip_in_kernel(kvm))
5217 return -ENXIO;
5218
5219 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5220 irq_event->irq, irq_event->level,
5221 line_status);
5222 return 0;
5223 }
5224
5225 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5226 struct kvm_enable_cap *cap)
5227 {
5228 int r;
5229
5230 if (cap->flags)
5231 return -EINVAL;
5232
5233 switch (cap->cap) {
5234 case KVM_CAP_DISABLE_QUIRKS:
5235 kvm->arch.disabled_quirks = cap->args[0];
5236 r = 0;
5237 break;
5238 case KVM_CAP_SPLIT_IRQCHIP: {
5239 mutex_lock(&kvm->lock);
5240 r = -EINVAL;
5241 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5242 goto split_irqchip_unlock;
5243 r = -EEXIST;
5244 if (irqchip_in_kernel(kvm))
5245 goto split_irqchip_unlock;
5246 if (kvm->created_vcpus)
5247 goto split_irqchip_unlock;
5248 r = kvm_setup_empty_irq_routing(kvm);
5249 if (r)
5250 goto split_irqchip_unlock;
5251 /* Pairs with irqchip_in_kernel. */
5252 smp_wmb();
5253 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5254 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5255 r = 0;
5256 split_irqchip_unlock:
5257 mutex_unlock(&kvm->lock);
5258 break;
5259 }
5260 case KVM_CAP_X2APIC_API:
5261 r = -EINVAL;
5262 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5263 break;
5264
5265 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5266 kvm->arch.x2apic_format = true;
5267 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5268 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5269
5270 r = 0;
5271 break;
5272 case KVM_CAP_X86_DISABLE_EXITS:
5273 r = -EINVAL;
5274 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5275 break;
5276
5277 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5278 kvm_can_mwait_in_guest())
5279 kvm->arch.mwait_in_guest = true;
5280 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5281 kvm->arch.hlt_in_guest = true;
5282 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5283 kvm->arch.pause_in_guest = true;
5284 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5285 kvm->arch.cstate_in_guest = true;
5286 r = 0;
5287 break;
5288 case KVM_CAP_MSR_PLATFORM_INFO:
5289 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5290 r = 0;
5291 break;
5292 case KVM_CAP_EXCEPTION_PAYLOAD:
5293 kvm->arch.exception_payload_enabled = cap->args[0];
5294 r = 0;
5295 break;
5296 case KVM_CAP_X86_USER_SPACE_MSR:
5297 kvm->arch.user_space_msr_mask = cap->args[0];
5298 r = 0;
5299 break;
5300 default:
5301 r = -EINVAL;
5302 break;
5303 }
5304 return r;
5305 }
5306
5307 static void kvm_clear_msr_filter(struct kvm *kvm)
5308 {
5309 u32 i;
5310 u32 count = kvm->arch.msr_filter.count;
5311 struct msr_bitmap_range ranges[16];
5312
5313 mutex_lock(&kvm->lock);
5314 kvm->arch.msr_filter.count = 0;
5315 memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0]));
5316 mutex_unlock(&kvm->lock);
5317 synchronize_srcu(&kvm->srcu);
5318
5319 for (i = 0; i < count; i++)
5320 kfree(ranges[i].bitmap);
5321 }
5322
5323 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range)
5324 {
5325 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
5326 struct msr_bitmap_range range;
5327 unsigned long *bitmap = NULL;
5328 size_t bitmap_size;
5329 int r;
5330
5331 if (!user_range->nmsrs)
5332 return 0;
5333
5334 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5335 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5336 return -EINVAL;
5337
5338 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5339 if (IS_ERR(bitmap))
5340 return PTR_ERR(bitmap);
5341
5342 range = (struct msr_bitmap_range) {
5343 .flags = user_range->flags,
5344 .base = user_range->base,
5345 .nmsrs = user_range->nmsrs,
5346 .bitmap = bitmap,
5347 };
5348
5349 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5350 r = -EINVAL;
5351 goto err;
5352 }
5353
5354 if (!range.flags) {
5355 r = -EINVAL;
5356 goto err;
5357 }
5358
5359 /* Everything ok, add this range identifier to our global pool */
5360 ranges[kvm->arch.msr_filter.count] = range;
5361 /* Make sure we filled the array before we tell anyone to walk it */
5362 smp_wmb();
5363 kvm->arch.msr_filter.count++;
5364
5365 return 0;
5366 err:
5367 kfree(bitmap);
5368 return r;
5369 }
5370
5371 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5372 {
5373 struct kvm_msr_filter __user *user_msr_filter = argp;
5374 struct kvm_msr_filter filter;
5375 bool default_allow;
5376 int r = 0;
5377 bool empty = true;
5378 u32 i;
5379
5380 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5381 return -EFAULT;
5382
5383 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5384 empty &= !filter.ranges[i].nmsrs;
5385
5386 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5387 if (empty && !default_allow)
5388 return -EINVAL;
5389
5390 kvm_clear_msr_filter(kvm);
5391
5392 kvm->arch.msr_filter.default_allow = default_allow;
5393
5394 /*
5395 * Protect from concurrent calls to this function that could trigger
5396 * a TOCTOU violation on kvm->arch.msr_filter.count.
5397 */
5398 mutex_lock(&kvm->lock);
5399 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5400 r = kvm_add_msr_filter(kvm, &filter.ranges[i]);
5401 if (r)
5402 break;
5403 }
5404
5405 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5406 mutex_unlock(&kvm->lock);
5407
5408 return r;
5409 }
5410
5411 long kvm_arch_vm_ioctl(struct file *filp,
5412 unsigned int ioctl, unsigned long arg)
5413 {
5414 struct kvm *kvm = filp->private_data;
5415 void __user *argp = (void __user *)arg;
5416 int r = -ENOTTY;
5417 /*
5418 * This union makes it completely explicit to gcc-3.x
5419 * that these two variables' stack usage should be
5420 * combined, not added together.
5421 */
5422 union {
5423 struct kvm_pit_state ps;
5424 struct kvm_pit_state2 ps2;
5425 struct kvm_pit_config pit_config;
5426 } u;
5427
5428 switch (ioctl) {
5429 case KVM_SET_TSS_ADDR:
5430 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5431 break;
5432 case KVM_SET_IDENTITY_MAP_ADDR: {
5433 u64 ident_addr;
5434
5435 mutex_lock(&kvm->lock);
5436 r = -EINVAL;
5437 if (kvm->created_vcpus)
5438 goto set_identity_unlock;
5439 r = -EFAULT;
5440 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5441 goto set_identity_unlock;
5442 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5443 set_identity_unlock:
5444 mutex_unlock(&kvm->lock);
5445 break;
5446 }
5447 case KVM_SET_NR_MMU_PAGES:
5448 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5449 break;
5450 case KVM_GET_NR_MMU_PAGES:
5451 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5452 break;
5453 case KVM_CREATE_IRQCHIP: {
5454 mutex_lock(&kvm->lock);
5455
5456 r = -EEXIST;
5457 if (irqchip_in_kernel(kvm))
5458 goto create_irqchip_unlock;
5459
5460 r = -EINVAL;
5461 if (kvm->created_vcpus)
5462 goto create_irqchip_unlock;
5463
5464 r = kvm_pic_init(kvm);
5465 if (r)
5466 goto create_irqchip_unlock;
5467
5468 r = kvm_ioapic_init(kvm);
5469 if (r) {
5470 kvm_pic_destroy(kvm);
5471 goto create_irqchip_unlock;
5472 }
5473
5474 r = kvm_setup_default_irq_routing(kvm);
5475 if (r) {
5476 kvm_ioapic_destroy(kvm);
5477 kvm_pic_destroy(kvm);
5478 goto create_irqchip_unlock;
5479 }
5480 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5481 smp_wmb();
5482 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5483 create_irqchip_unlock:
5484 mutex_unlock(&kvm->lock);
5485 break;
5486 }
5487 case KVM_CREATE_PIT:
5488 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5489 goto create_pit;
5490 case KVM_CREATE_PIT2:
5491 r = -EFAULT;
5492 if (copy_from_user(&u.pit_config, argp,
5493 sizeof(struct kvm_pit_config)))
5494 goto out;
5495 create_pit:
5496 mutex_lock(&kvm->lock);
5497 r = -EEXIST;
5498 if (kvm->arch.vpit)
5499 goto create_pit_unlock;
5500 r = -ENOMEM;
5501 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5502 if (kvm->arch.vpit)
5503 r = 0;
5504 create_pit_unlock:
5505 mutex_unlock(&kvm->lock);
5506 break;
5507 case KVM_GET_IRQCHIP: {
5508 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5509 struct kvm_irqchip *chip;
5510
5511 chip = memdup_user(argp, sizeof(*chip));
5512 if (IS_ERR(chip)) {
5513 r = PTR_ERR(chip);
5514 goto out;
5515 }
5516
5517 r = -ENXIO;
5518 if (!irqchip_kernel(kvm))
5519 goto get_irqchip_out;
5520 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5521 if (r)
5522 goto get_irqchip_out;
5523 r = -EFAULT;
5524 if (copy_to_user(argp, chip, sizeof(*chip)))
5525 goto get_irqchip_out;
5526 r = 0;
5527 get_irqchip_out:
5528 kfree(chip);
5529 break;
5530 }
5531 case KVM_SET_IRQCHIP: {
5532 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5533 struct kvm_irqchip *chip;
5534
5535 chip = memdup_user(argp, sizeof(*chip));
5536 if (IS_ERR(chip)) {
5537 r = PTR_ERR(chip);
5538 goto out;
5539 }
5540
5541 r = -ENXIO;
5542 if (!irqchip_kernel(kvm))
5543 goto set_irqchip_out;
5544 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5545 set_irqchip_out:
5546 kfree(chip);
5547 break;
5548 }
5549 case KVM_GET_PIT: {
5550 r = -EFAULT;
5551 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5552 goto out;
5553 r = -ENXIO;
5554 if (!kvm->arch.vpit)
5555 goto out;
5556 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5557 if (r)
5558 goto out;
5559 r = -EFAULT;
5560 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5561 goto out;
5562 r = 0;
5563 break;
5564 }
5565 case KVM_SET_PIT: {
5566 r = -EFAULT;
5567 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5568 goto out;
5569 mutex_lock(&kvm->lock);
5570 r = -ENXIO;
5571 if (!kvm->arch.vpit)
5572 goto set_pit_out;
5573 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5574 set_pit_out:
5575 mutex_unlock(&kvm->lock);
5576 break;
5577 }
5578 case KVM_GET_PIT2: {
5579 r = -ENXIO;
5580 if (!kvm->arch.vpit)
5581 goto out;
5582 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5583 if (r)
5584 goto out;
5585 r = -EFAULT;
5586 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5587 goto out;
5588 r = 0;
5589 break;
5590 }
5591 case KVM_SET_PIT2: {
5592 r = -EFAULT;
5593 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5594 goto out;
5595 mutex_lock(&kvm->lock);
5596 r = -ENXIO;
5597 if (!kvm->arch.vpit)
5598 goto set_pit2_out;
5599 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5600 set_pit2_out:
5601 mutex_unlock(&kvm->lock);
5602 break;
5603 }
5604 case KVM_REINJECT_CONTROL: {
5605 struct kvm_reinject_control control;
5606 r = -EFAULT;
5607 if (copy_from_user(&control, argp, sizeof(control)))
5608 goto out;
5609 r = -ENXIO;
5610 if (!kvm->arch.vpit)
5611 goto out;
5612 r = kvm_vm_ioctl_reinject(kvm, &control);
5613 break;
5614 }
5615 case KVM_SET_BOOT_CPU_ID:
5616 r = 0;
5617 mutex_lock(&kvm->lock);
5618 if (kvm->created_vcpus)
5619 r = -EBUSY;
5620 else
5621 kvm->arch.bsp_vcpu_id = arg;
5622 mutex_unlock(&kvm->lock);
5623 break;
5624 case KVM_XEN_HVM_CONFIG: {
5625 struct kvm_xen_hvm_config xhc;
5626 r = -EFAULT;
5627 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5628 goto out;
5629 r = -EINVAL;
5630 if (xhc.flags)
5631 goto out;
5632 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5633 r = 0;
5634 break;
5635 }
5636 case KVM_SET_CLOCK: {
5637 struct kvm_clock_data user_ns;
5638 u64 now_ns;
5639
5640 r = -EFAULT;
5641 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5642 goto out;
5643
5644 r = -EINVAL;
5645 if (user_ns.flags)
5646 goto out;
5647
5648 r = 0;
5649 /*
5650 * TODO: userspace has to take care of races with VCPU_RUN, so
5651 * kvm_gen_update_masterclock() can be cut down to locked
5652 * pvclock_update_vm_gtod_copy().
5653 */
5654 kvm_gen_update_masterclock(kvm);
5655 now_ns = get_kvmclock_ns(kvm);
5656 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5657 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5658 break;
5659 }
5660 case KVM_GET_CLOCK: {
5661 struct kvm_clock_data user_ns;
5662 u64 now_ns;
5663
5664 now_ns = get_kvmclock_ns(kvm);
5665 user_ns.clock = now_ns;
5666 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5667 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5668
5669 r = -EFAULT;
5670 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5671 goto out;
5672 r = 0;
5673 break;
5674 }
5675 case KVM_MEMORY_ENCRYPT_OP: {
5676 r = -ENOTTY;
5677 if (kvm_x86_ops.mem_enc_op)
5678 r = kvm_x86_ops.mem_enc_op(kvm, argp);
5679 break;
5680 }
5681 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5682 struct kvm_enc_region region;
5683
5684 r = -EFAULT;
5685 if (copy_from_user(&region, argp, sizeof(region)))
5686 goto out;
5687
5688 r = -ENOTTY;
5689 if (kvm_x86_ops.mem_enc_reg_region)
5690 r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5691 break;
5692 }
5693 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5694 struct kvm_enc_region region;
5695
5696 r = -EFAULT;
5697 if (copy_from_user(&region, argp, sizeof(region)))
5698 goto out;
5699
5700 r = -ENOTTY;
5701 if (kvm_x86_ops.mem_enc_unreg_region)
5702 r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5703 break;
5704 }
5705 case KVM_HYPERV_EVENTFD: {
5706 struct kvm_hyperv_eventfd hvevfd;
5707
5708 r = -EFAULT;
5709 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5710 goto out;
5711 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5712 break;
5713 }
5714 case KVM_SET_PMU_EVENT_FILTER:
5715 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5716 break;
5717 case KVM_X86_SET_MSR_FILTER:
5718 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5719 break;
5720 default:
5721 r = -ENOTTY;
5722 }
5723 out:
5724 return r;
5725 }
5726
5727 static void kvm_init_msr_list(void)
5728 {
5729 struct x86_pmu_capability x86_pmu;
5730 u32 dummy[2];
5731 unsigned i;
5732
5733 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5734 "Please update the fixed PMCs in msrs_to_saved_all[]");
5735
5736 perf_get_x86_pmu_capability(&x86_pmu);
5737
5738 num_msrs_to_save = 0;
5739 num_emulated_msrs = 0;
5740 num_msr_based_features = 0;
5741
5742 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5743 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5744 continue;
5745
5746 /*
5747 * Even MSRs that are valid in the host may not be exposed
5748 * to the guests in some cases.
5749 */
5750 switch (msrs_to_save_all[i]) {
5751 case MSR_IA32_BNDCFGS:
5752 if (!kvm_mpx_supported())
5753 continue;
5754 break;
5755 case MSR_TSC_AUX:
5756 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5757 continue;
5758 break;
5759 case MSR_IA32_UMWAIT_CONTROL:
5760 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5761 continue;
5762 break;
5763 case MSR_IA32_RTIT_CTL:
5764 case MSR_IA32_RTIT_STATUS:
5765 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5766 continue;
5767 break;
5768 case MSR_IA32_RTIT_CR3_MATCH:
5769 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5770 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5771 continue;
5772 break;
5773 case MSR_IA32_RTIT_OUTPUT_BASE:
5774 case MSR_IA32_RTIT_OUTPUT_MASK:
5775 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5776 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5777 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5778 continue;
5779 break;
5780 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5781 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5782 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5783 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5784 continue;
5785 break;
5786 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5787 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5788 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5789 continue;
5790 break;
5791 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5792 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5793 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5794 continue;
5795 break;
5796 default:
5797 break;
5798 }
5799
5800 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5801 }
5802
5803 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5804 if (!kvm_x86_ops.has_emulated_msr(NULL, emulated_msrs_all[i]))
5805 continue;
5806
5807 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5808 }
5809
5810 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5811 struct kvm_msr_entry msr;
5812
5813 msr.index = msr_based_features_all[i];
5814 if (kvm_get_msr_feature(&msr))
5815 continue;
5816
5817 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5818 }
5819 }
5820
5821 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5822 const void *v)
5823 {
5824 int handled = 0;
5825 int n;
5826
5827 do {
5828 n = min(len, 8);
5829 if (!(lapic_in_kernel(vcpu) &&
5830 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5831 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5832 break;
5833 handled += n;
5834 addr += n;
5835 len -= n;
5836 v += n;
5837 } while (len);
5838
5839 return handled;
5840 }
5841
5842 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5843 {
5844 int handled = 0;
5845 int n;
5846
5847 do {
5848 n = min(len, 8);
5849 if (!(lapic_in_kernel(vcpu) &&
5850 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5851 addr, n, v))
5852 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5853 break;
5854 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5855 handled += n;
5856 addr += n;
5857 len -= n;
5858 v += n;
5859 } while (len);
5860
5861 return handled;
5862 }
5863
5864 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5865 struct kvm_segment *var, int seg)
5866 {
5867 kvm_x86_ops.set_segment(vcpu, var, seg);
5868 }
5869
5870 void kvm_get_segment(struct kvm_vcpu *vcpu,
5871 struct kvm_segment *var, int seg)
5872 {
5873 kvm_x86_ops.get_segment(vcpu, var, seg);
5874 }
5875
5876 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5877 struct x86_exception *exception)
5878 {
5879 gpa_t t_gpa;
5880
5881 BUG_ON(!mmu_is_nested(vcpu));
5882
5883 /* NPT walks are always user-walks */
5884 access |= PFERR_USER_MASK;
5885 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5886
5887 return t_gpa;
5888 }
5889
5890 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5891 struct x86_exception *exception)
5892 {
5893 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5894 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5895 }
5896
5897 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5898 struct x86_exception *exception)
5899 {
5900 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5901 access |= PFERR_FETCH_MASK;
5902 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5903 }
5904
5905 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5906 struct x86_exception *exception)
5907 {
5908 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5909 access |= PFERR_WRITE_MASK;
5910 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5911 }
5912
5913 /* uses this to access any guest's mapped memory without checking CPL */
5914 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5915 struct x86_exception *exception)
5916 {
5917 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5918 }
5919
5920 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5921 struct kvm_vcpu *vcpu, u32 access,
5922 struct x86_exception *exception)
5923 {
5924 void *data = val;
5925 int r = X86EMUL_CONTINUE;
5926
5927 while (bytes) {
5928 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5929 exception);
5930 unsigned offset = addr & (PAGE_SIZE-1);
5931 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5932 int ret;
5933
5934 if (gpa == UNMAPPED_GVA)
5935 return X86EMUL_PROPAGATE_FAULT;
5936 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5937 offset, toread);
5938 if (ret < 0) {
5939 r = X86EMUL_IO_NEEDED;
5940 goto out;
5941 }
5942
5943 bytes -= toread;
5944 data += toread;
5945 addr += toread;
5946 }
5947 out:
5948 return r;
5949 }
5950
5951 /* used for instruction fetching */
5952 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5953 gva_t addr, void *val, unsigned int bytes,
5954 struct x86_exception *exception)
5955 {
5956 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5957 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5958 unsigned offset;
5959 int ret;
5960
5961 /* Inline kvm_read_guest_virt_helper for speed. */
5962 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5963 exception);
5964 if (unlikely(gpa == UNMAPPED_GVA))
5965 return X86EMUL_PROPAGATE_FAULT;
5966
5967 offset = addr & (PAGE_SIZE-1);
5968 if (WARN_ON(offset + bytes > PAGE_SIZE))
5969 bytes = (unsigned)PAGE_SIZE - offset;
5970 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5971 offset, bytes);
5972 if (unlikely(ret < 0))
5973 return X86EMUL_IO_NEEDED;
5974
5975 return X86EMUL_CONTINUE;
5976 }
5977
5978 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5979 gva_t addr, void *val, unsigned int bytes,
5980 struct x86_exception *exception)
5981 {
5982 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5983
5984 /*
5985 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5986 * is returned, but our callers are not ready for that and they blindly
5987 * call kvm_inject_page_fault. Ensure that they at least do not leak
5988 * uninitialized kernel stack memory into cr2 and error code.
5989 */
5990 memset(exception, 0, sizeof(*exception));
5991 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5992 exception);
5993 }
5994 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5995
5996 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5997 gva_t addr, void *val, unsigned int bytes,
5998 struct x86_exception *exception, bool system)
5999 {
6000 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6001 u32 access = 0;
6002
6003 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6004 access |= PFERR_USER_MASK;
6005
6006 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
6007 }
6008
6009 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
6010 unsigned long addr, void *val, unsigned int bytes)
6011 {
6012 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6013 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
6014
6015 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
6016 }
6017
6018 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6019 struct kvm_vcpu *vcpu, u32 access,
6020 struct x86_exception *exception)
6021 {
6022 void *data = val;
6023 int r = X86EMUL_CONTINUE;
6024
6025 while (bytes) {
6026 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
6027 access,
6028 exception);
6029 unsigned offset = addr & (PAGE_SIZE-1);
6030 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6031 int ret;
6032
6033 if (gpa == UNMAPPED_GVA)
6034 return X86EMUL_PROPAGATE_FAULT;
6035 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6036 if (ret < 0) {
6037 r = X86EMUL_IO_NEEDED;
6038 goto out;
6039 }
6040
6041 bytes -= towrite;
6042 data += towrite;
6043 addr += towrite;
6044 }
6045 out:
6046 return r;
6047 }
6048
6049 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6050 unsigned int bytes, struct x86_exception *exception,
6051 bool system)
6052 {
6053 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6054 u32 access = PFERR_WRITE_MASK;
6055
6056 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6057 access |= PFERR_USER_MASK;
6058
6059 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6060 access, exception);
6061 }
6062
6063 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6064 unsigned int bytes, struct x86_exception *exception)
6065 {
6066 /* kvm_write_guest_virt_system can pull in tons of pages. */
6067 vcpu->arch.l1tf_flush_l1d = true;
6068
6069 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6070 PFERR_WRITE_MASK, exception);
6071 }
6072 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6073
6074 int handle_ud(struct kvm_vcpu *vcpu)
6075 {
6076 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6077 int emul_type = EMULTYPE_TRAP_UD;
6078 char sig[5]; /* ud2; .ascii "kvm" */
6079 struct x86_exception e;
6080
6081 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0)))
6082 return 1;
6083
6084 if (force_emulation_prefix &&
6085 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6086 sig, sizeof(sig), &e) == 0 &&
6087 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6088 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6089 emul_type = EMULTYPE_TRAP_UD_FORCED;
6090 }
6091
6092 return kvm_emulate_instruction(vcpu, emul_type);
6093 }
6094 EXPORT_SYMBOL_GPL(handle_ud);
6095
6096 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6097 gpa_t gpa, bool write)
6098 {
6099 /* For APIC access vmexit */
6100 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6101 return 1;
6102
6103 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6104 trace_vcpu_match_mmio(gva, gpa, write, true);
6105 return 1;
6106 }
6107
6108 return 0;
6109 }
6110
6111 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6112 gpa_t *gpa, struct x86_exception *exception,
6113 bool write)
6114 {
6115 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
6116 | (write ? PFERR_WRITE_MASK : 0);
6117
6118 /*
6119 * currently PKRU is only applied to ept enabled guest so
6120 * there is no pkey in EPT page table for L1 guest or EPT
6121 * shadow page table for L2 guest.
6122 */
6123 if (vcpu_match_mmio_gva(vcpu, gva)
6124 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6125 vcpu->arch.mmio_access, 0, access)) {
6126 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6127 (gva & (PAGE_SIZE - 1));
6128 trace_vcpu_match_mmio(gva, *gpa, write, false);
6129 return 1;
6130 }
6131
6132 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6133
6134 if (*gpa == UNMAPPED_GVA)
6135 return -1;
6136
6137 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6138 }
6139
6140 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6141 const void *val, int bytes)
6142 {
6143 int ret;
6144
6145 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6146 if (ret < 0)
6147 return 0;
6148 kvm_page_track_write(vcpu, gpa, val, bytes);
6149 return 1;
6150 }
6151
6152 struct read_write_emulator_ops {
6153 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6154 int bytes);
6155 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6156 void *val, int bytes);
6157 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6158 int bytes, void *val);
6159 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6160 void *val, int bytes);
6161 bool write;
6162 };
6163
6164 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6165 {
6166 if (vcpu->mmio_read_completed) {
6167 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6168 vcpu->mmio_fragments[0].gpa, val);
6169 vcpu->mmio_read_completed = 0;
6170 return 1;
6171 }
6172
6173 return 0;
6174 }
6175
6176 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6177 void *val, int bytes)
6178 {
6179 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6180 }
6181
6182 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6183 void *val, int bytes)
6184 {
6185 return emulator_write_phys(vcpu, gpa, val, bytes);
6186 }
6187
6188 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6189 {
6190 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6191 return vcpu_mmio_write(vcpu, gpa, bytes, val);
6192 }
6193
6194 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6195 void *val, int bytes)
6196 {
6197 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6198 return X86EMUL_IO_NEEDED;
6199 }
6200
6201 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6202 void *val, int bytes)
6203 {
6204 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6205
6206 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6207 return X86EMUL_CONTINUE;
6208 }
6209
6210 static const struct read_write_emulator_ops read_emultor = {
6211 .read_write_prepare = read_prepare,
6212 .read_write_emulate = read_emulate,
6213 .read_write_mmio = vcpu_mmio_read,
6214 .read_write_exit_mmio = read_exit_mmio,
6215 };
6216
6217 static const struct read_write_emulator_ops write_emultor = {
6218 .read_write_emulate = write_emulate,
6219 .read_write_mmio = write_mmio,
6220 .read_write_exit_mmio = write_exit_mmio,
6221 .write = true,
6222 };
6223
6224 static int emulator_read_write_onepage(unsigned long addr, void *val,
6225 unsigned int bytes,
6226 struct x86_exception *exception,
6227 struct kvm_vcpu *vcpu,
6228 const struct read_write_emulator_ops *ops)
6229 {
6230 gpa_t gpa;
6231 int handled, ret;
6232 bool write = ops->write;
6233 struct kvm_mmio_fragment *frag;
6234 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6235
6236 /*
6237 * If the exit was due to a NPF we may already have a GPA.
6238 * If the GPA is present, use it to avoid the GVA to GPA table walk.
6239 * Note, this cannot be used on string operations since string
6240 * operation using rep will only have the initial GPA from the NPF
6241 * occurred.
6242 */
6243 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6244 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6245 gpa = ctxt->gpa_val;
6246 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6247 } else {
6248 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6249 if (ret < 0)
6250 return X86EMUL_PROPAGATE_FAULT;
6251 }
6252
6253 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6254 return X86EMUL_CONTINUE;
6255
6256 /*
6257 * Is this MMIO handled locally?
6258 */
6259 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6260 if (handled == bytes)
6261 return X86EMUL_CONTINUE;
6262
6263 gpa += handled;
6264 bytes -= handled;
6265 val += handled;
6266
6267 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6268 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6269 frag->gpa = gpa;
6270 frag->data = val;
6271 frag->len = bytes;
6272 return X86EMUL_CONTINUE;
6273 }
6274
6275 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6276 unsigned long addr,
6277 void *val, unsigned int bytes,
6278 struct x86_exception *exception,
6279 const struct read_write_emulator_ops *ops)
6280 {
6281 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6282 gpa_t gpa;
6283 int rc;
6284
6285 if (ops->read_write_prepare &&
6286 ops->read_write_prepare(vcpu, val, bytes))
6287 return X86EMUL_CONTINUE;
6288
6289 vcpu->mmio_nr_fragments = 0;
6290
6291 /* Crossing a page boundary? */
6292 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6293 int now;
6294
6295 now = -addr & ~PAGE_MASK;
6296 rc = emulator_read_write_onepage(addr, val, now, exception,
6297 vcpu, ops);
6298
6299 if (rc != X86EMUL_CONTINUE)
6300 return rc;
6301 addr += now;
6302 if (ctxt->mode != X86EMUL_MODE_PROT64)
6303 addr = (u32)addr;
6304 val += now;
6305 bytes -= now;
6306 }
6307
6308 rc = emulator_read_write_onepage(addr, val, bytes, exception,
6309 vcpu, ops);
6310 if (rc != X86EMUL_CONTINUE)
6311 return rc;
6312
6313 if (!vcpu->mmio_nr_fragments)
6314 return rc;
6315
6316 gpa = vcpu->mmio_fragments[0].gpa;
6317
6318 vcpu->mmio_needed = 1;
6319 vcpu->mmio_cur_fragment = 0;
6320
6321 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6322 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6323 vcpu->run->exit_reason = KVM_EXIT_MMIO;
6324 vcpu->run->mmio.phys_addr = gpa;
6325
6326 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6327 }
6328
6329 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6330 unsigned long addr,
6331 void *val,
6332 unsigned int bytes,
6333 struct x86_exception *exception)
6334 {
6335 return emulator_read_write(ctxt, addr, val, bytes,
6336 exception, &read_emultor);
6337 }
6338
6339 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6340 unsigned long addr,
6341 const void *val,
6342 unsigned int bytes,
6343 struct x86_exception *exception)
6344 {
6345 return emulator_read_write(ctxt, addr, (void *)val, bytes,
6346 exception, &write_emultor);
6347 }
6348
6349 #define CMPXCHG_TYPE(t, ptr, old, new) \
6350 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6351
6352 #ifdef CONFIG_X86_64
6353 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6354 #else
6355 # define CMPXCHG64(ptr, old, new) \
6356 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6357 #endif
6358
6359 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6360 unsigned long addr,
6361 const void *old,
6362 const void *new,
6363 unsigned int bytes,
6364 struct x86_exception *exception)
6365 {
6366 struct kvm_host_map map;
6367 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6368 u64 page_line_mask;
6369 gpa_t gpa;
6370 char *kaddr;
6371 bool exchanged;
6372
6373 /* guests cmpxchg8b have to be emulated atomically */
6374 if (bytes > 8 || (bytes & (bytes - 1)))
6375 goto emul_write;
6376
6377 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6378
6379 if (gpa == UNMAPPED_GVA ||
6380 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6381 goto emul_write;
6382
6383 /*
6384 * Emulate the atomic as a straight write to avoid #AC if SLD is
6385 * enabled in the host and the access splits a cache line.
6386 */
6387 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6388 page_line_mask = ~(cache_line_size() - 1);
6389 else
6390 page_line_mask = PAGE_MASK;
6391
6392 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6393 goto emul_write;
6394
6395 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6396 goto emul_write;
6397
6398 kaddr = map.hva + offset_in_page(gpa);
6399
6400 switch (bytes) {
6401 case 1:
6402 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6403 break;
6404 case 2:
6405 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6406 break;
6407 case 4:
6408 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6409 break;
6410 case 8:
6411 exchanged = CMPXCHG64(kaddr, old, new);
6412 break;
6413 default:
6414 BUG();
6415 }
6416
6417 kvm_vcpu_unmap(vcpu, &map, true);
6418
6419 if (!exchanged)
6420 return X86EMUL_CMPXCHG_FAILED;
6421
6422 kvm_page_track_write(vcpu, gpa, new, bytes);
6423
6424 return X86EMUL_CONTINUE;
6425
6426 emul_write:
6427 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6428
6429 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6430 }
6431
6432 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6433 {
6434 int r = 0, i;
6435
6436 for (i = 0; i < vcpu->arch.pio.count; i++) {
6437 if (vcpu->arch.pio.in)
6438 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6439 vcpu->arch.pio.size, pd);
6440 else
6441 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6442 vcpu->arch.pio.port, vcpu->arch.pio.size,
6443 pd);
6444 if (r)
6445 break;
6446 pd += vcpu->arch.pio.size;
6447 }
6448 return r;
6449 }
6450
6451 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6452 unsigned short port, void *val,
6453 unsigned int count, bool in)
6454 {
6455 vcpu->arch.pio.port = port;
6456 vcpu->arch.pio.in = in;
6457 vcpu->arch.pio.count = count;
6458 vcpu->arch.pio.size = size;
6459
6460 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6461 vcpu->arch.pio.count = 0;
6462 return 1;
6463 }
6464
6465 vcpu->run->exit_reason = KVM_EXIT_IO;
6466 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6467 vcpu->run->io.size = size;
6468 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6469 vcpu->run->io.count = count;
6470 vcpu->run->io.port = port;
6471
6472 return 0;
6473 }
6474
6475 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6476 unsigned short port, void *val, unsigned int count)
6477 {
6478 int ret;
6479
6480 if (vcpu->arch.pio.count)
6481 goto data_avail;
6482
6483 memset(vcpu->arch.pio_data, 0, size * count);
6484
6485 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6486 if (ret) {
6487 data_avail:
6488 memcpy(val, vcpu->arch.pio_data, size * count);
6489 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6490 vcpu->arch.pio.count = 0;
6491 return 1;
6492 }
6493
6494 return 0;
6495 }
6496
6497 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6498 int size, unsigned short port, void *val,
6499 unsigned int count)
6500 {
6501 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6502
6503 }
6504
6505 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6506 unsigned short port, const void *val,
6507 unsigned int count)
6508 {
6509 memcpy(vcpu->arch.pio_data, val, size * count);
6510 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6511 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6512 }
6513
6514 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6515 int size, unsigned short port,
6516 const void *val, unsigned int count)
6517 {
6518 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6519 }
6520
6521 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6522 {
6523 return kvm_x86_ops.get_segment_base(vcpu, seg);
6524 }
6525
6526 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6527 {
6528 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6529 }
6530
6531 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6532 {
6533 if (!need_emulate_wbinvd(vcpu))
6534 return X86EMUL_CONTINUE;
6535
6536 if (kvm_x86_ops.has_wbinvd_exit()) {
6537 int cpu = get_cpu();
6538
6539 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6540 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6541 wbinvd_ipi, NULL, 1);
6542 put_cpu();
6543 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6544 } else
6545 wbinvd();
6546 return X86EMUL_CONTINUE;
6547 }
6548
6549 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6550 {
6551 kvm_emulate_wbinvd_noskip(vcpu);
6552 return kvm_skip_emulated_instruction(vcpu);
6553 }
6554 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6555
6556
6557
6558 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6559 {
6560 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6561 }
6562
6563 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6564 unsigned long *dest)
6565 {
6566 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6567 }
6568
6569 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6570 unsigned long value)
6571 {
6572
6573 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6574 }
6575
6576 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6577 {
6578 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6579 }
6580
6581 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6582 {
6583 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6584 unsigned long value;
6585
6586 switch (cr) {
6587 case 0:
6588 value = kvm_read_cr0(vcpu);
6589 break;
6590 case 2:
6591 value = vcpu->arch.cr2;
6592 break;
6593 case 3:
6594 value = kvm_read_cr3(vcpu);
6595 break;
6596 case 4:
6597 value = kvm_read_cr4(vcpu);
6598 break;
6599 case 8:
6600 value = kvm_get_cr8(vcpu);
6601 break;
6602 default:
6603 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6604 return 0;
6605 }
6606
6607 return value;
6608 }
6609
6610 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6611 {
6612 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6613 int res = 0;
6614
6615 switch (cr) {
6616 case 0:
6617 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6618 break;
6619 case 2:
6620 vcpu->arch.cr2 = val;
6621 break;
6622 case 3:
6623 res = kvm_set_cr3(vcpu, val);
6624 break;
6625 case 4:
6626 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6627 break;
6628 case 8:
6629 res = kvm_set_cr8(vcpu, val);
6630 break;
6631 default:
6632 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6633 res = -1;
6634 }
6635
6636 return res;
6637 }
6638
6639 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6640 {
6641 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6642 }
6643
6644 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6645 {
6646 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6647 }
6648
6649 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6650 {
6651 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6652 }
6653
6654 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6655 {
6656 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6657 }
6658
6659 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6660 {
6661 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6662 }
6663
6664 static unsigned long emulator_get_cached_segment_base(
6665 struct x86_emulate_ctxt *ctxt, int seg)
6666 {
6667 return get_segment_base(emul_to_vcpu(ctxt), seg);
6668 }
6669
6670 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6671 struct desc_struct *desc, u32 *base3,
6672 int seg)
6673 {
6674 struct kvm_segment var;
6675
6676 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6677 *selector = var.selector;
6678
6679 if (var.unusable) {
6680 memset(desc, 0, sizeof(*desc));
6681 if (base3)
6682 *base3 = 0;
6683 return false;
6684 }
6685
6686 if (var.g)
6687 var.limit >>= 12;
6688 set_desc_limit(desc, var.limit);
6689 set_desc_base(desc, (unsigned long)var.base);
6690 #ifdef CONFIG_X86_64
6691 if (base3)
6692 *base3 = var.base >> 32;
6693 #endif
6694 desc->type = var.type;
6695 desc->s = var.s;
6696 desc->dpl = var.dpl;
6697 desc->p = var.present;
6698 desc->avl = var.avl;
6699 desc->l = var.l;
6700 desc->d = var.db;
6701 desc->g = var.g;
6702
6703 return true;
6704 }
6705
6706 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6707 struct desc_struct *desc, u32 base3,
6708 int seg)
6709 {
6710 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6711 struct kvm_segment var;
6712
6713 var.selector = selector;
6714 var.base = get_desc_base(desc);
6715 #ifdef CONFIG_X86_64
6716 var.base |= ((u64)base3) << 32;
6717 #endif
6718 var.limit = get_desc_limit(desc);
6719 if (desc->g)
6720 var.limit = (var.limit << 12) | 0xfff;
6721 var.type = desc->type;
6722 var.dpl = desc->dpl;
6723 var.db = desc->d;
6724 var.s = desc->s;
6725 var.l = desc->l;
6726 var.g = desc->g;
6727 var.avl = desc->avl;
6728 var.present = desc->p;
6729 var.unusable = !var.present;
6730 var.padding = 0;
6731
6732 kvm_set_segment(vcpu, &var, seg);
6733 return;
6734 }
6735
6736 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6737 u32 msr_index, u64 *pdata)
6738 {
6739 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6740 int r;
6741
6742 r = kvm_get_msr(vcpu, msr_index, pdata);
6743
6744 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6745 /* Bounce to user space */
6746 return X86EMUL_IO_NEEDED;
6747 }
6748
6749 return r;
6750 }
6751
6752 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6753 u32 msr_index, u64 data)
6754 {
6755 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6756 int r;
6757
6758 r = kvm_set_msr(vcpu, msr_index, data);
6759
6760 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6761 /* Bounce to user space */
6762 return X86EMUL_IO_NEEDED;
6763 }
6764
6765 return r;
6766 }
6767
6768 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6769 {
6770 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6771
6772 return vcpu->arch.smbase;
6773 }
6774
6775 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6776 {
6777 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6778
6779 vcpu->arch.smbase = smbase;
6780 }
6781
6782 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6783 u32 pmc)
6784 {
6785 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6786 }
6787
6788 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6789 u32 pmc, u64 *pdata)
6790 {
6791 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6792 }
6793
6794 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6795 {
6796 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6797 }
6798
6799 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6800 struct x86_instruction_info *info,
6801 enum x86_intercept_stage stage)
6802 {
6803 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6804 &ctxt->exception);
6805 }
6806
6807 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6808 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6809 bool exact_only)
6810 {
6811 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6812 }
6813
6814 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6815 {
6816 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6817 }
6818
6819 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6820 {
6821 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6822 }
6823
6824 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6825 {
6826 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6827 }
6828
6829 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6830 {
6831 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6832 }
6833
6834 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6835 {
6836 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6837 }
6838
6839 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6840 {
6841 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6842 }
6843
6844 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6845 {
6846 return emul_to_vcpu(ctxt)->arch.hflags;
6847 }
6848
6849 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6850 {
6851 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6852 }
6853
6854 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6855 const char *smstate)
6856 {
6857 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6858 }
6859
6860 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6861 {
6862 kvm_smm_changed(emul_to_vcpu(ctxt));
6863 }
6864
6865 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6866 {
6867 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6868 }
6869
6870 static const struct x86_emulate_ops emulate_ops = {
6871 .read_gpr = emulator_read_gpr,
6872 .write_gpr = emulator_write_gpr,
6873 .read_std = emulator_read_std,
6874 .write_std = emulator_write_std,
6875 .read_phys = kvm_read_guest_phys_system,
6876 .fetch = kvm_fetch_guest_virt,
6877 .read_emulated = emulator_read_emulated,
6878 .write_emulated = emulator_write_emulated,
6879 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6880 .invlpg = emulator_invlpg,
6881 .pio_in_emulated = emulator_pio_in_emulated,
6882 .pio_out_emulated = emulator_pio_out_emulated,
6883 .get_segment = emulator_get_segment,
6884 .set_segment = emulator_set_segment,
6885 .get_cached_segment_base = emulator_get_cached_segment_base,
6886 .get_gdt = emulator_get_gdt,
6887 .get_idt = emulator_get_idt,
6888 .set_gdt = emulator_set_gdt,
6889 .set_idt = emulator_set_idt,
6890 .get_cr = emulator_get_cr,
6891 .set_cr = emulator_set_cr,
6892 .cpl = emulator_get_cpl,
6893 .get_dr = emulator_get_dr,
6894 .set_dr = emulator_set_dr,
6895 .get_smbase = emulator_get_smbase,
6896 .set_smbase = emulator_set_smbase,
6897 .set_msr = emulator_set_msr,
6898 .get_msr = emulator_get_msr,
6899 .check_pmc = emulator_check_pmc,
6900 .read_pmc = emulator_read_pmc,
6901 .halt = emulator_halt,
6902 .wbinvd = emulator_wbinvd,
6903 .fix_hypercall = emulator_fix_hypercall,
6904 .intercept = emulator_intercept,
6905 .get_cpuid = emulator_get_cpuid,
6906 .guest_has_long_mode = emulator_guest_has_long_mode,
6907 .guest_has_movbe = emulator_guest_has_movbe,
6908 .guest_has_fxsr = emulator_guest_has_fxsr,
6909 .set_nmi_mask = emulator_set_nmi_mask,
6910 .get_hflags = emulator_get_hflags,
6911 .set_hflags = emulator_set_hflags,
6912 .pre_leave_smm = emulator_pre_leave_smm,
6913 .post_leave_smm = emulator_post_leave_smm,
6914 .set_xcr = emulator_set_xcr,
6915 };
6916
6917 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6918 {
6919 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6920 /*
6921 * an sti; sti; sequence only disable interrupts for the first
6922 * instruction. So, if the last instruction, be it emulated or
6923 * not, left the system with the INT_STI flag enabled, it
6924 * means that the last instruction is an sti. We should not
6925 * leave the flag on in this case. The same goes for mov ss
6926 */
6927 if (int_shadow & mask)
6928 mask = 0;
6929 if (unlikely(int_shadow || mask)) {
6930 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6931 if (!mask)
6932 kvm_make_request(KVM_REQ_EVENT, vcpu);
6933 }
6934 }
6935
6936 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6937 {
6938 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6939 if (ctxt->exception.vector == PF_VECTOR)
6940 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6941
6942 if (ctxt->exception.error_code_valid)
6943 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6944 ctxt->exception.error_code);
6945 else
6946 kvm_queue_exception(vcpu, ctxt->exception.vector);
6947 return false;
6948 }
6949
6950 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6951 {
6952 struct x86_emulate_ctxt *ctxt;
6953
6954 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6955 if (!ctxt) {
6956 pr_err("kvm: failed to allocate vcpu's emulator\n");
6957 return NULL;
6958 }
6959
6960 ctxt->vcpu = vcpu;
6961 ctxt->ops = &emulate_ops;
6962 vcpu->arch.emulate_ctxt = ctxt;
6963
6964 return ctxt;
6965 }
6966
6967 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6968 {
6969 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6970 int cs_db, cs_l;
6971
6972 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6973
6974 ctxt->gpa_available = false;
6975 ctxt->eflags = kvm_get_rflags(vcpu);
6976 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6977
6978 ctxt->eip = kvm_rip_read(vcpu);
6979 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6980 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6981 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6982 cs_db ? X86EMUL_MODE_PROT32 :
6983 X86EMUL_MODE_PROT16;
6984 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6985 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6986 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6987
6988 init_decode_cache(ctxt);
6989 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6990 }
6991
6992 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6993 {
6994 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6995 int ret;
6996
6997 init_emulate_ctxt(vcpu);
6998
6999 ctxt->op_bytes = 2;
7000 ctxt->ad_bytes = 2;
7001 ctxt->_eip = ctxt->eip + inc_eip;
7002 ret = emulate_int_real(ctxt, irq);
7003
7004 if (ret != X86EMUL_CONTINUE) {
7005 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7006 } else {
7007 ctxt->eip = ctxt->_eip;
7008 kvm_rip_write(vcpu, ctxt->eip);
7009 kvm_set_rflags(vcpu, ctxt->eflags);
7010 }
7011 }
7012 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
7013
7014 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
7015 {
7016 ++vcpu->stat.insn_emulation_fail;
7017 trace_kvm_emulate_insn_failed(vcpu);
7018
7019 if (emulation_type & EMULTYPE_VMWARE_GP) {
7020 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7021 return 1;
7022 }
7023
7024 if (emulation_type & EMULTYPE_SKIP) {
7025 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7026 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7027 vcpu->run->internal.ndata = 0;
7028 return 0;
7029 }
7030
7031 kvm_queue_exception(vcpu, UD_VECTOR);
7032
7033 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
7034 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7035 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7036 vcpu->run->internal.ndata = 0;
7037 return 0;
7038 }
7039
7040 return 1;
7041 }
7042
7043 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7044 bool write_fault_to_shadow_pgtable,
7045 int emulation_type)
7046 {
7047 gpa_t gpa = cr2_or_gpa;
7048 kvm_pfn_t pfn;
7049
7050 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7051 return false;
7052
7053 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7054 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7055 return false;
7056
7057 if (!vcpu->arch.mmu->direct_map) {
7058 /*
7059 * Write permission should be allowed since only
7060 * write access need to be emulated.
7061 */
7062 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7063
7064 /*
7065 * If the mapping is invalid in guest, let cpu retry
7066 * it to generate fault.
7067 */
7068 if (gpa == UNMAPPED_GVA)
7069 return true;
7070 }
7071
7072 /*
7073 * Do not retry the unhandleable instruction if it faults on the
7074 * readonly host memory, otherwise it will goto a infinite loop:
7075 * retry instruction -> write #PF -> emulation fail -> retry
7076 * instruction -> ...
7077 */
7078 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
7079
7080 /*
7081 * If the instruction failed on the error pfn, it can not be fixed,
7082 * report the error to userspace.
7083 */
7084 if (is_error_noslot_pfn(pfn))
7085 return false;
7086
7087 kvm_release_pfn_clean(pfn);
7088
7089 /* The instructions are well-emulated on direct mmu. */
7090 if (vcpu->arch.mmu->direct_map) {
7091 unsigned int indirect_shadow_pages;
7092
7093 spin_lock(&vcpu->kvm->mmu_lock);
7094 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
7095 spin_unlock(&vcpu->kvm->mmu_lock);
7096
7097 if (indirect_shadow_pages)
7098 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7099
7100 return true;
7101 }
7102
7103 /*
7104 * if emulation was due to access to shadowed page table
7105 * and it failed try to unshadow page and re-enter the
7106 * guest to let CPU execute the instruction.
7107 */
7108 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7109
7110 /*
7111 * If the access faults on its page table, it can not
7112 * be fixed by unprotecting shadow page and it should
7113 * be reported to userspace.
7114 */
7115 return !write_fault_to_shadow_pgtable;
7116 }
7117
7118 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7119 gpa_t cr2_or_gpa, int emulation_type)
7120 {
7121 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7122 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7123
7124 last_retry_eip = vcpu->arch.last_retry_eip;
7125 last_retry_addr = vcpu->arch.last_retry_addr;
7126
7127 /*
7128 * If the emulation is caused by #PF and it is non-page_table
7129 * writing instruction, it means the VM-EXIT is caused by shadow
7130 * page protected, we can zap the shadow page and retry this
7131 * instruction directly.
7132 *
7133 * Note: if the guest uses a non-page-table modifying instruction
7134 * on the PDE that points to the instruction, then we will unmap
7135 * the instruction and go to an infinite loop. So, we cache the
7136 * last retried eip and the last fault address, if we meet the eip
7137 * and the address again, we can break out of the potential infinite
7138 * loop.
7139 */
7140 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7141
7142 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7143 return false;
7144
7145 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7146 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7147 return false;
7148
7149 if (x86_page_table_writing_insn(ctxt))
7150 return false;
7151
7152 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7153 return false;
7154
7155 vcpu->arch.last_retry_eip = ctxt->eip;
7156 vcpu->arch.last_retry_addr = cr2_or_gpa;
7157
7158 if (!vcpu->arch.mmu->direct_map)
7159 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7160
7161 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7162
7163 return true;
7164 }
7165
7166 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7167 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7168
7169 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7170 {
7171 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7172 /* This is a good place to trace that we are exiting SMM. */
7173 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7174
7175 /* Process a latched INIT or SMI, if any. */
7176 kvm_make_request(KVM_REQ_EVENT, vcpu);
7177 }
7178
7179 kvm_mmu_reset_context(vcpu);
7180 }
7181
7182 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7183 unsigned long *db)
7184 {
7185 u32 dr6 = 0;
7186 int i;
7187 u32 enable, rwlen;
7188
7189 enable = dr7;
7190 rwlen = dr7 >> 16;
7191 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7192 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7193 dr6 |= (1 << i);
7194 return dr6;
7195 }
7196
7197 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7198 {
7199 struct kvm_run *kvm_run = vcpu->run;
7200
7201 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7202 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
7203 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7204 kvm_run->debug.arch.exception = DB_VECTOR;
7205 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7206 return 0;
7207 }
7208 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7209 return 1;
7210 }
7211
7212 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7213 {
7214 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7215 int r;
7216
7217 r = kvm_x86_ops.skip_emulated_instruction(vcpu);
7218 if (unlikely(!r))
7219 return 0;
7220
7221 /*
7222 * rflags is the old, "raw" value of the flags. The new value has
7223 * not been saved yet.
7224 *
7225 * This is correct even for TF set by the guest, because "the
7226 * processor will not generate this exception after the instruction
7227 * that sets the TF flag".
7228 */
7229 if (unlikely(rflags & X86_EFLAGS_TF))
7230 r = kvm_vcpu_do_singlestep(vcpu);
7231 return r;
7232 }
7233 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7234
7235 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7236 {
7237 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7238 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7239 struct kvm_run *kvm_run = vcpu->run;
7240 unsigned long eip = kvm_get_linear_rip(vcpu);
7241 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7242 vcpu->arch.guest_debug_dr7,
7243 vcpu->arch.eff_db);
7244
7245 if (dr6 != 0) {
7246 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
7247 kvm_run->debug.arch.pc = eip;
7248 kvm_run->debug.arch.exception = DB_VECTOR;
7249 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7250 *r = 0;
7251 return true;
7252 }
7253 }
7254
7255 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7256 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7257 unsigned long eip = kvm_get_linear_rip(vcpu);
7258 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7259 vcpu->arch.dr7,
7260 vcpu->arch.db);
7261
7262 if (dr6 != 0) {
7263 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7264 *r = 1;
7265 return true;
7266 }
7267 }
7268
7269 return false;
7270 }
7271
7272 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7273 {
7274 switch (ctxt->opcode_len) {
7275 case 1:
7276 switch (ctxt->b) {
7277 case 0xe4: /* IN */
7278 case 0xe5:
7279 case 0xec:
7280 case 0xed:
7281 case 0xe6: /* OUT */
7282 case 0xe7:
7283 case 0xee:
7284 case 0xef:
7285 case 0x6c: /* INS */
7286 case 0x6d:
7287 case 0x6e: /* OUTS */
7288 case 0x6f:
7289 return true;
7290 }
7291 break;
7292 case 2:
7293 switch (ctxt->b) {
7294 case 0x33: /* RDPMC */
7295 return true;
7296 }
7297 break;
7298 }
7299
7300 return false;
7301 }
7302
7303 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7304 int emulation_type, void *insn, int insn_len)
7305 {
7306 int r;
7307 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7308 bool writeback = true;
7309 bool write_fault_to_spt;
7310
7311 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len)))
7312 return 1;
7313
7314 vcpu->arch.l1tf_flush_l1d = true;
7315
7316 /*
7317 * Clear write_fault_to_shadow_pgtable here to ensure it is
7318 * never reused.
7319 */
7320 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7321 vcpu->arch.write_fault_to_shadow_pgtable = false;
7322 kvm_clear_exception_queue(vcpu);
7323
7324 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7325 init_emulate_ctxt(vcpu);
7326
7327 /*
7328 * We will reenter on the same instruction since
7329 * we do not set complete_userspace_io. This does not
7330 * handle watchpoints yet, those would be handled in
7331 * the emulate_ops.
7332 */
7333 if (!(emulation_type & EMULTYPE_SKIP) &&
7334 kvm_vcpu_check_breakpoint(vcpu, &r))
7335 return r;
7336
7337 ctxt->interruptibility = 0;
7338 ctxt->have_exception = false;
7339 ctxt->exception.vector = -1;
7340 ctxt->perm_ok = false;
7341
7342 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7343
7344 r = x86_decode_insn(ctxt, insn, insn_len);
7345
7346 trace_kvm_emulate_insn_start(vcpu);
7347 ++vcpu->stat.insn_emulation;
7348 if (r != EMULATION_OK) {
7349 if ((emulation_type & EMULTYPE_TRAP_UD) ||
7350 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7351 kvm_queue_exception(vcpu, UD_VECTOR);
7352 return 1;
7353 }
7354 if (reexecute_instruction(vcpu, cr2_or_gpa,
7355 write_fault_to_spt,
7356 emulation_type))
7357 return 1;
7358 if (ctxt->have_exception) {
7359 /*
7360 * #UD should result in just EMULATION_FAILED, and trap-like
7361 * exception should not be encountered during decode.
7362 */
7363 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7364 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7365 inject_emulated_exception(vcpu);
7366 return 1;
7367 }
7368 return handle_emulation_failure(vcpu, emulation_type);
7369 }
7370 }
7371
7372 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7373 !is_vmware_backdoor_opcode(ctxt)) {
7374 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7375 return 1;
7376 }
7377
7378 /*
7379 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7380 * for kvm_skip_emulated_instruction(). The caller is responsible for
7381 * updating interruptibility state and injecting single-step #DBs.
7382 */
7383 if (emulation_type & EMULTYPE_SKIP) {
7384 kvm_rip_write(vcpu, ctxt->_eip);
7385 if (ctxt->eflags & X86_EFLAGS_RF)
7386 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7387 return 1;
7388 }
7389
7390 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7391 return 1;
7392
7393 /* this is needed for vmware backdoor interface to work since it
7394 changes registers values during IO operation */
7395 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7396 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7397 emulator_invalidate_register_cache(ctxt);
7398 }
7399
7400 restart:
7401 if (emulation_type & EMULTYPE_PF) {
7402 /* Save the faulting GPA (cr2) in the address field */
7403 ctxt->exception.address = cr2_or_gpa;
7404
7405 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7406 if (vcpu->arch.mmu->direct_map) {
7407 ctxt->gpa_available = true;
7408 ctxt->gpa_val = cr2_or_gpa;
7409 }
7410 } else {
7411 /* Sanitize the address out of an abundance of paranoia. */
7412 ctxt->exception.address = 0;
7413 }
7414
7415 r = x86_emulate_insn(ctxt);
7416
7417 if (r == EMULATION_INTERCEPTED)
7418 return 1;
7419
7420 if (r == EMULATION_FAILED) {
7421 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7422 emulation_type))
7423 return 1;
7424
7425 return handle_emulation_failure(vcpu, emulation_type);
7426 }
7427
7428 if (ctxt->have_exception) {
7429 r = 1;
7430 if (inject_emulated_exception(vcpu))
7431 return r;
7432 } else if (vcpu->arch.pio.count) {
7433 if (!vcpu->arch.pio.in) {
7434 /* FIXME: return into emulator if single-stepping. */
7435 vcpu->arch.pio.count = 0;
7436 } else {
7437 writeback = false;
7438 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7439 }
7440 r = 0;
7441 } else if (vcpu->mmio_needed) {
7442 ++vcpu->stat.mmio_exits;
7443
7444 if (!vcpu->mmio_is_write)
7445 writeback = false;
7446 r = 0;
7447 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7448 } else if (r == EMULATION_RESTART)
7449 goto restart;
7450 else
7451 r = 1;
7452
7453 if (writeback) {
7454 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7455 toggle_interruptibility(vcpu, ctxt->interruptibility);
7456 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7457 if (!ctxt->have_exception ||
7458 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7459 kvm_rip_write(vcpu, ctxt->eip);
7460 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7461 r = kvm_vcpu_do_singlestep(vcpu);
7462 if (kvm_x86_ops.update_emulated_instruction)
7463 kvm_x86_ops.update_emulated_instruction(vcpu);
7464 __kvm_set_rflags(vcpu, ctxt->eflags);
7465 }
7466
7467 /*
7468 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7469 * do nothing, and it will be requested again as soon as
7470 * the shadow expires. But we still need to check here,
7471 * because POPF has no interrupt shadow.
7472 */
7473 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7474 kvm_make_request(KVM_REQ_EVENT, vcpu);
7475 } else
7476 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7477
7478 return r;
7479 }
7480
7481 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7482 {
7483 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7484 }
7485 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7486
7487 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7488 void *insn, int insn_len)
7489 {
7490 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7491 }
7492 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7493
7494 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7495 {
7496 vcpu->arch.pio.count = 0;
7497 return 1;
7498 }
7499
7500 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7501 {
7502 vcpu->arch.pio.count = 0;
7503
7504 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7505 return 1;
7506
7507 return kvm_skip_emulated_instruction(vcpu);
7508 }
7509
7510 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7511 unsigned short port)
7512 {
7513 unsigned long val = kvm_rax_read(vcpu);
7514 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7515
7516 if (ret)
7517 return ret;
7518
7519 /*
7520 * Workaround userspace that relies on old KVM behavior of %rip being
7521 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7522 */
7523 if (port == 0x7e &&
7524 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7525 vcpu->arch.complete_userspace_io =
7526 complete_fast_pio_out_port_0x7e;
7527 kvm_skip_emulated_instruction(vcpu);
7528 } else {
7529 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7530 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7531 }
7532 return 0;
7533 }
7534
7535 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7536 {
7537 unsigned long val;
7538
7539 /* We should only ever be called with arch.pio.count equal to 1 */
7540 BUG_ON(vcpu->arch.pio.count != 1);
7541
7542 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7543 vcpu->arch.pio.count = 0;
7544 return 1;
7545 }
7546
7547 /* For size less than 4 we merge, else we zero extend */
7548 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7549
7550 /*
7551 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7552 * the copy and tracing
7553 */
7554 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7555 kvm_rax_write(vcpu, val);
7556
7557 return kvm_skip_emulated_instruction(vcpu);
7558 }
7559
7560 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7561 unsigned short port)
7562 {
7563 unsigned long val;
7564 int ret;
7565
7566 /* For size less than 4 we merge, else we zero extend */
7567 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7568
7569 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7570 if (ret) {
7571 kvm_rax_write(vcpu, val);
7572 return ret;
7573 }
7574
7575 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7576 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7577
7578 return 0;
7579 }
7580
7581 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7582 {
7583 int ret;
7584
7585 if (in)
7586 ret = kvm_fast_pio_in(vcpu, size, port);
7587 else
7588 ret = kvm_fast_pio_out(vcpu, size, port);
7589 return ret && kvm_skip_emulated_instruction(vcpu);
7590 }
7591 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7592
7593 static int kvmclock_cpu_down_prep(unsigned int cpu)
7594 {
7595 __this_cpu_write(cpu_tsc_khz, 0);
7596 return 0;
7597 }
7598
7599 static void tsc_khz_changed(void *data)
7600 {
7601 struct cpufreq_freqs *freq = data;
7602 unsigned long khz = 0;
7603
7604 if (data)
7605 khz = freq->new;
7606 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7607 khz = cpufreq_quick_get(raw_smp_processor_id());
7608 if (!khz)
7609 khz = tsc_khz;
7610 __this_cpu_write(cpu_tsc_khz, khz);
7611 }
7612
7613 #ifdef CONFIG_X86_64
7614 static void kvm_hyperv_tsc_notifier(void)
7615 {
7616 struct kvm *kvm;
7617 struct kvm_vcpu *vcpu;
7618 int cpu;
7619
7620 mutex_lock(&kvm_lock);
7621 list_for_each_entry(kvm, &vm_list, vm_list)
7622 kvm_make_mclock_inprogress_request(kvm);
7623
7624 hyperv_stop_tsc_emulation();
7625
7626 /* TSC frequency always matches when on Hyper-V */
7627 for_each_present_cpu(cpu)
7628 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7629 kvm_max_guest_tsc_khz = tsc_khz;
7630
7631 list_for_each_entry(kvm, &vm_list, vm_list) {
7632 struct kvm_arch *ka = &kvm->arch;
7633
7634 spin_lock(&ka->pvclock_gtod_sync_lock);
7635
7636 pvclock_update_vm_gtod_copy(kvm);
7637
7638 kvm_for_each_vcpu(cpu, vcpu, kvm)
7639 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7640
7641 kvm_for_each_vcpu(cpu, vcpu, kvm)
7642 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7643
7644 spin_unlock(&ka->pvclock_gtod_sync_lock);
7645 }
7646 mutex_unlock(&kvm_lock);
7647 }
7648 #endif
7649
7650 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7651 {
7652 struct kvm *kvm;
7653 struct kvm_vcpu *vcpu;
7654 int i, send_ipi = 0;
7655
7656 /*
7657 * We allow guests to temporarily run on slowing clocks,
7658 * provided we notify them after, or to run on accelerating
7659 * clocks, provided we notify them before. Thus time never
7660 * goes backwards.
7661 *
7662 * However, we have a problem. We can't atomically update
7663 * the frequency of a given CPU from this function; it is
7664 * merely a notifier, which can be called from any CPU.
7665 * Changing the TSC frequency at arbitrary points in time
7666 * requires a recomputation of local variables related to
7667 * the TSC for each VCPU. We must flag these local variables
7668 * to be updated and be sure the update takes place with the
7669 * new frequency before any guests proceed.
7670 *
7671 * Unfortunately, the combination of hotplug CPU and frequency
7672 * change creates an intractable locking scenario; the order
7673 * of when these callouts happen is undefined with respect to
7674 * CPU hotplug, and they can race with each other. As such,
7675 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7676 * undefined; you can actually have a CPU frequency change take
7677 * place in between the computation of X and the setting of the
7678 * variable. To protect against this problem, all updates of
7679 * the per_cpu tsc_khz variable are done in an interrupt
7680 * protected IPI, and all callers wishing to update the value
7681 * must wait for a synchronous IPI to complete (which is trivial
7682 * if the caller is on the CPU already). This establishes the
7683 * necessary total order on variable updates.
7684 *
7685 * Note that because a guest time update may take place
7686 * anytime after the setting of the VCPU's request bit, the
7687 * correct TSC value must be set before the request. However,
7688 * to ensure the update actually makes it to any guest which
7689 * starts running in hardware virtualization between the set
7690 * and the acquisition of the spinlock, we must also ping the
7691 * CPU after setting the request bit.
7692 *
7693 */
7694
7695 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7696
7697 mutex_lock(&kvm_lock);
7698 list_for_each_entry(kvm, &vm_list, vm_list) {
7699 kvm_for_each_vcpu(i, vcpu, kvm) {
7700 if (vcpu->cpu != cpu)
7701 continue;
7702 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7703 if (vcpu->cpu != raw_smp_processor_id())
7704 send_ipi = 1;
7705 }
7706 }
7707 mutex_unlock(&kvm_lock);
7708
7709 if (freq->old < freq->new && send_ipi) {
7710 /*
7711 * We upscale the frequency. Must make the guest
7712 * doesn't see old kvmclock values while running with
7713 * the new frequency, otherwise we risk the guest sees
7714 * time go backwards.
7715 *
7716 * In case we update the frequency for another cpu
7717 * (which might be in guest context) send an interrupt
7718 * to kick the cpu out of guest context. Next time
7719 * guest context is entered kvmclock will be updated,
7720 * so the guest will not see stale values.
7721 */
7722 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7723 }
7724 }
7725
7726 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7727 void *data)
7728 {
7729 struct cpufreq_freqs *freq = data;
7730 int cpu;
7731
7732 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7733 return 0;
7734 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7735 return 0;
7736
7737 for_each_cpu(cpu, freq->policy->cpus)
7738 __kvmclock_cpufreq_notifier(freq, cpu);
7739
7740 return 0;
7741 }
7742
7743 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7744 .notifier_call = kvmclock_cpufreq_notifier
7745 };
7746
7747 static int kvmclock_cpu_online(unsigned int cpu)
7748 {
7749 tsc_khz_changed(NULL);
7750 return 0;
7751 }
7752
7753 static void kvm_timer_init(void)
7754 {
7755 max_tsc_khz = tsc_khz;
7756
7757 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7758 #ifdef CONFIG_CPU_FREQ
7759 struct cpufreq_policy *policy;
7760 int cpu;
7761
7762 cpu = get_cpu();
7763 policy = cpufreq_cpu_get(cpu);
7764 if (policy) {
7765 if (policy->cpuinfo.max_freq)
7766 max_tsc_khz = policy->cpuinfo.max_freq;
7767 cpufreq_cpu_put(policy);
7768 }
7769 put_cpu();
7770 #endif
7771 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7772 CPUFREQ_TRANSITION_NOTIFIER);
7773 }
7774
7775 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7776 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7777 }
7778
7779 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7780 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7781
7782 int kvm_is_in_guest(void)
7783 {
7784 return __this_cpu_read(current_vcpu) != NULL;
7785 }
7786
7787 static int kvm_is_user_mode(void)
7788 {
7789 int user_mode = 3;
7790
7791 if (__this_cpu_read(current_vcpu))
7792 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7793
7794 return user_mode != 0;
7795 }
7796
7797 static unsigned long kvm_get_guest_ip(void)
7798 {
7799 unsigned long ip = 0;
7800
7801 if (__this_cpu_read(current_vcpu))
7802 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7803
7804 return ip;
7805 }
7806
7807 static void kvm_handle_intel_pt_intr(void)
7808 {
7809 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7810
7811 kvm_make_request(KVM_REQ_PMI, vcpu);
7812 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7813 (unsigned long *)&vcpu->arch.pmu.global_status);
7814 }
7815
7816 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7817 .is_in_guest = kvm_is_in_guest,
7818 .is_user_mode = kvm_is_user_mode,
7819 .get_guest_ip = kvm_get_guest_ip,
7820 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7821 };
7822
7823 #ifdef CONFIG_X86_64
7824 static void pvclock_gtod_update_fn(struct work_struct *work)
7825 {
7826 struct kvm *kvm;
7827
7828 struct kvm_vcpu *vcpu;
7829 int i;
7830
7831 mutex_lock(&kvm_lock);
7832 list_for_each_entry(kvm, &vm_list, vm_list)
7833 kvm_for_each_vcpu(i, vcpu, kvm)
7834 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7835 atomic_set(&kvm_guest_has_master_clock, 0);
7836 mutex_unlock(&kvm_lock);
7837 }
7838
7839 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7840
7841 /*
7842 * Notification about pvclock gtod data update.
7843 */
7844 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7845 void *priv)
7846 {
7847 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7848 struct timekeeper *tk = priv;
7849
7850 update_pvclock_gtod(tk);
7851
7852 /* disable master clock if host does not trust, or does not
7853 * use, TSC based clocksource.
7854 */
7855 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7856 atomic_read(&kvm_guest_has_master_clock) != 0)
7857 queue_work(system_long_wq, &pvclock_gtod_work);
7858
7859 return 0;
7860 }
7861
7862 static struct notifier_block pvclock_gtod_notifier = {
7863 .notifier_call = pvclock_gtod_notify,
7864 };
7865 #endif
7866
7867 int kvm_arch_init(void *opaque)
7868 {
7869 struct kvm_x86_init_ops *ops = opaque;
7870 int r;
7871
7872 if (kvm_x86_ops.hardware_enable) {
7873 printk(KERN_ERR "kvm: already loaded the other module\n");
7874 r = -EEXIST;
7875 goto out;
7876 }
7877
7878 if (!ops->cpu_has_kvm_support()) {
7879 pr_err_ratelimited("kvm: no hardware support\n");
7880 r = -EOPNOTSUPP;
7881 goto out;
7882 }
7883 if (ops->disabled_by_bios()) {
7884 pr_err_ratelimited("kvm: disabled by bios\n");
7885 r = -EOPNOTSUPP;
7886 goto out;
7887 }
7888
7889 /*
7890 * KVM explicitly assumes that the guest has an FPU and
7891 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7892 * vCPU's FPU state as a fxregs_state struct.
7893 */
7894 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7895 printk(KERN_ERR "kvm: inadequate fpu\n");
7896 r = -EOPNOTSUPP;
7897 goto out;
7898 }
7899
7900 r = -ENOMEM;
7901 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7902 __alignof__(struct fpu), SLAB_ACCOUNT,
7903 NULL);
7904 if (!x86_fpu_cache) {
7905 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7906 goto out;
7907 }
7908
7909 x86_emulator_cache = kvm_alloc_emulator_cache();
7910 if (!x86_emulator_cache) {
7911 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7912 goto out_free_x86_fpu_cache;
7913 }
7914
7915 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7916 if (!user_return_msrs) {
7917 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7918 goto out_free_x86_emulator_cache;
7919 }
7920
7921 r = kvm_mmu_module_init();
7922 if (r)
7923 goto out_free_percpu;
7924
7925 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7926 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7927 PT_PRESENT_MASK, 0, sme_me_mask);
7928 kvm_timer_init();
7929
7930 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7931
7932 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7933 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7934 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7935 }
7936
7937 kvm_lapic_init();
7938 if (pi_inject_timer == -1)
7939 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7940 #ifdef CONFIG_X86_64
7941 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7942
7943 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7944 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7945 #endif
7946
7947 return 0;
7948
7949 out_free_percpu:
7950 free_percpu(user_return_msrs);
7951 out_free_x86_emulator_cache:
7952 kmem_cache_destroy(x86_emulator_cache);
7953 out_free_x86_fpu_cache:
7954 kmem_cache_destroy(x86_fpu_cache);
7955 out:
7956 return r;
7957 }
7958
7959 void kvm_arch_exit(void)
7960 {
7961 #ifdef CONFIG_X86_64
7962 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7963 clear_hv_tscchange_cb();
7964 #endif
7965 kvm_lapic_exit();
7966 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7967
7968 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7969 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7970 CPUFREQ_TRANSITION_NOTIFIER);
7971 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7972 #ifdef CONFIG_X86_64
7973 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7974 #endif
7975 kvm_x86_ops.hardware_enable = NULL;
7976 kvm_mmu_module_exit();
7977 free_percpu(user_return_msrs);
7978 kmem_cache_destroy(x86_fpu_cache);
7979 }
7980
7981 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason)
7982 {
7983 ++vcpu->stat.halt_exits;
7984 if (lapic_in_kernel(vcpu)) {
7985 vcpu->arch.mp_state = state;
7986 return 1;
7987 } else {
7988 vcpu->run->exit_reason = reason;
7989 return 0;
7990 }
7991 }
7992
7993 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7994 {
7995 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
7996 }
7997 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7998
7999 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
8000 {
8001 int ret = kvm_skip_emulated_instruction(vcpu);
8002 /*
8003 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
8004 * KVM_EXIT_DEBUG here.
8005 */
8006 return kvm_vcpu_halt(vcpu) && ret;
8007 }
8008 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
8009
8010 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
8011 {
8012 int ret = kvm_skip_emulated_instruction(vcpu);
8013
8014 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret;
8015 }
8016 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
8017
8018 #ifdef CONFIG_X86_64
8019 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
8020 unsigned long clock_type)
8021 {
8022 struct kvm_clock_pairing clock_pairing;
8023 struct timespec64 ts;
8024 u64 cycle;
8025 int ret;
8026
8027 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
8028 return -KVM_EOPNOTSUPP;
8029
8030 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
8031 return -KVM_EOPNOTSUPP;
8032
8033 clock_pairing.sec = ts.tv_sec;
8034 clock_pairing.nsec = ts.tv_nsec;
8035 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
8036 clock_pairing.flags = 0;
8037 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
8038
8039 ret = 0;
8040 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
8041 sizeof(struct kvm_clock_pairing)))
8042 ret = -KVM_EFAULT;
8043
8044 return ret;
8045 }
8046 #endif
8047
8048 /*
8049 * kvm_pv_kick_cpu_op: Kick a vcpu.
8050 *
8051 * @apicid - apicid of vcpu to be kicked.
8052 */
8053 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
8054 {
8055 struct kvm_lapic_irq lapic_irq;
8056
8057 lapic_irq.shorthand = APIC_DEST_NOSHORT;
8058 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
8059 lapic_irq.level = 0;
8060 lapic_irq.dest_id = apicid;
8061 lapic_irq.msi_redir_hint = false;
8062
8063 lapic_irq.delivery_mode = APIC_DM_REMRD;
8064 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
8065 }
8066
8067 bool kvm_apicv_activated(struct kvm *kvm)
8068 {
8069 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
8070 }
8071 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
8072
8073 void kvm_apicv_init(struct kvm *kvm, bool enable)
8074 {
8075 if (enable)
8076 clear_bit(APICV_INHIBIT_REASON_DISABLE,
8077 &kvm->arch.apicv_inhibit_reasons);
8078 else
8079 set_bit(APICV_INHIBIT_REASON_DISABLE,
8080 &kvm->arch.apicv_inhibit_reasons);
8081 }
8082 EXPORT_SYMBOL_GPL(kvm_apicv_init);
8083
8084 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
8085 {
8086 struct kvm_vcpu *target = NULL;
8087 struct kvm_apic_map *map;
8088
8089 rcu_read_lock();
8090 map = rcu_dereference(kvm->arch.apic_map);
8091
8092 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
8093 target = map->phys_map[dest_id]->vcpu;
8094
8095 rcu_read_unlock();
8096
8097 if (target && READ_ONCE(target->ready))
8098 kvm_vcpu_yield_to(target);
8099 }
8100
8101 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
8102 {
8103 unsigned long nr, a0, a1, a2, a3, ret;
8104 int op_64_bit;
8105
8106 if (kvm_hv_hypercall_enabled(vcpu->kvm))
8107 return kvm_hv_hypercall(vcpu);
8108
8109 nr = kvm_rax_read(vcpu);
8110 a0 = kvm_rbx_read(vcpu);
8111 a1 = kvm_rcx_read(vcpu);
8112 a2 = kvm_rdx_read(vcpu);
8113 a3 = kvm_rsi_read(vcpu);
8114
8115 trace_kvm_hypercall(nr, a0, a1, a2, a3);
8116
8117 op_64_bit = is_64_bit_mode(vcpu);
8118 if (!op_64_bit) {
8119 nr &= 0xFFFFFFFF;
8120 a0 &= 0xFFFFFFFF;
8121 a1 &= 0xFFFFFFFF;
8122 a2 &= 0xFFFFFFFF;
8123 a3 &= 0xFFFFFFFF;
8124 }
8125
8126 if (kvm_x86_ops.get_cpl(vcpu) != 0) {
8127 ret = -KVM_EPERM;
8128 goto out;
8129 }
8130
8131 ret = -KVM_ENOSYS;
8132
8133 switch (nr) {
8134 case KVM_HC_VAPIC_POLL_IRQ:
8135 ret = 0;
8136 break;
8137 case KVM_HC_KICK_CPU:
8138 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
8139 break;
8140
8141 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8142 kvm_sched_yield(vcpu->kvm, a1);
8143 ret = 0;
8144 break;
8145 #ifdef CONFIG_X86_64
8146 case KVM_HC_CLOCK_PAIRING:
8147 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8148 break;
8149 #endif
8150 case KVM_HC_SEND_IPI:
8151 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
8152 break;
8153
8154 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8155 break;
8156 case KVM_HC_SCHED_YIELD:
8157 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
8158 break;
8159
8160 kvm_sched_yield(vcpu->kvm, a0);
8161 ret = 0;
8162 break;
8163 default:
8164 ret = -KVM_ENOSYS;
8165 break;
8166 }
8167 out:
8168 if (!op_64_bit)
8169 ret = (u32)ret;
8170 kvm_rax_write(vcpu, ret);
8171
8172 ++vcpu->stat.hypercalls;
8173 return kvm_skip_emulated_instruction(vcpu);
8174 }
8175 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8176
8177 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8178 {
8179 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8180 char instruction[3];
8181 unsigned long rip = kvm_rip_read(vcpu);
8182
8183 kvm_x86_ops.patch_hypercall(vcpu, instruction);
8184
8185 return emulator_write_emulated(ctxt, rip, instruction, 3,
8186 &ctxt->exception);
8187 }
8188
8189 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8190 {
8191 return vcpu->run->request_interrupt_window &&
8192 likely(!pic_in_kernel(vcpu->kvm));
8193 }
8194
8195 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8196 {
8197 struct kvm_run *kvm_run = vcpu->run;
8198
8199 /*
8200 * if_flag is obsolete and useless, so do not bother
8201 * setting it for SEV-ES guests. Userspace can just
8202 * use kvm_run->ready_for_interrupt_injection.
8203 */
8204 kvm_run->if_flag = !vcpu->arch.guest_state_protected
8205 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8206
8207 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
8208 kvm_run->cr8 = kvm_get_cr8(vcpu);
8209 kvm_run->apic_base = kvm_get_apic_base(vcpu);
8210 kvm_run->ready_for_interrupt_injection =
8211 pic_in_kernel(vcpu->kvm) ||
8212 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8213 }
8214
8215 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8216 {
8217 int max_irr, tpr;
8218
8219 if (!kvm_x86_ops.update_cr8_intercept)
8220 return;
8221
8222 if (!lapic_in_kernel(vcpu))
8223 return;
8224
8225 if (vcpu->arch.apicv_active)
8226 return;
8227
8228 if (!vcpu->arch.apic->vapic_addr)
8229 max_irr = kvm_lapic_find_highest_irr(vcpu);
8230 else
8231 max_irr = -1;
8232
8233 if (max_irr != -1)
8234 max_irr >>= 4;
8235
8236 tpr = kvm_lapic_get_cr8(vcpu);
8237
8238 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
8239 }
8240
8241 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8242 {
8243 int r;
8244 bool can_inject = true;
8245
8246 /* try to reinject previous events if any */
8247
8248 if (vcpu->arch.exception.injected) {
8249 kvm_x86_ops.queue_exception(vcpu);
8250 can_inject = false;
8251 }
8252 /*
8253 * Do not inject an NMI or interrupt if there is a pending
8254 * exception. Exceptions and interrupts are recognized at
8255 * instruction boundaries, i.e. the start of an instruction.
8256 * Trap-like exceptions, e.g. #DB, have higher priority than
8257 * NMIs and interrupts, i.e. traps are recognized before an
8258 * NMI/interrupt that's pending on the same instruction.
8259 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8260 * priority, but are only generated (pended) during instruction
8261 * execution, i.e. a pending fault-like exception means the
8262 * fault occurred on the *previous* instruction and must be
8263 * serviced prior to recognizing any new events in order to
8264 * fully complete the previous instruction.
8265 */
8266 else if (!vcpu->arch.exception.pending) {
8267 if (vcpu->arch.nmi_injected) {
8268 kvm_x86_ops.set_nmi(vcpu);
8269 can_inject = false;
8270 } else if (vcpu->arch.interrupt.injected) {
8271 kvm_x86_ops.set_irq(vcpu);
8272 can_inject = false;
8273 }
8274 }
8275
8276 WARN_ON_ONCE(vcpu->arch.exception.injected &&
8277 vcpu->arch.exception.pending);
8278
8279 /*
8280 * Call check_nested_events() even if we reinjected a previous event
8281 * in order for caller to determine if it should require immediate-exit
8282 * from L2 to L1 due to pending L1 events which require exit
8283 * from L2 to L1.
8284 */
8285 if (is_guest_mode(vcpu)) {
8286 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8287 if (r < 0)
8288 goto busy;
8289 }
8290
8291 /* try to inject new event if pending */
8292 if (vcpu->arch.exception.pending) {
8293 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8294 vcpu->arch.exception.has_error_code,
8295 vcpu->arch.exception.error_code);
8296
8297 vcpu->arch.exception.pending = false;
8298 vcpu->arch.exception.injected = true;
8299
8300 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8301 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8302 X86_EFLAGS_RF);
8303
8304 if (vcpu->arch.exception.nr == DB_VECTOR) {
8305 kvm_deliver_exception_payload(vcpu);
8306 if (vcpu->arch.dr7 & DR7_GD) {
8307 vcpu->arch.dr7 &= ~DR7_GD;
8308 kvm_update_dr7(vcpu);
8309 }
8310 }
8311
8312 kvm_x86_ops.queue_exception(vcpu);
8313 can_inject = false;
8314 }
8315
8316 /*
8317 * Finally, inject interrupt events. If an event cannot be injected
8318 * due to architectural conditions (e.g. IF=0) a window-open exit
8319 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
8320 * and can architecturally be injected, but we cannot do it right now:
8321 * an interrupt could have arrived just now and we have to inject it
8322 * as a vmexit, or there could already an event in the queue, which is
8323 * indicated by can_inject. In that case we request an immediate exit
8324 * in order to make progress and get back here for another iteration.
8325 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8326 */
8327 if (vcpu->arch.smi_pending) {
8328 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
8329 if (r < 0)
8330 goto busy;
8331 if (r) {
8332 vcpu->arch.smi_pending = false;
8333 ++vcpu->arch.smi_count;
8334 enter_smm(vcpu);
8335 can_inject = false;
8336 } else
8337 kvm_x86_ops.enable_smi_window(vcpu);
8338 }
8339
8340 if (vcpu->arch.nmi_pending) {
8341 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
8342 if (r < 0)
8343 goto busy;
8344 if (r) {
8345 --vcpu->arch.nmi_pending;
8346 vcpu->arch.nmi_injected = true;
8347 kvm_x86_ops.set_nmi(vcpu);
8348 can_inject = false;
8349 WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
8350 }
8351 if (vcpu->arch.nmi_pending)
8352 kvm_x86_ops.enable_nmi_window(vcpu);
8353 }
8354
8355 if (kvm_cpu_has_injectable_intr(vcpu)) {
8356 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
8357 if (r < 0)
8358 goto busy;
8359 if (r) {
8360 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8361 kvm_x86_ops.set_irq(vcpu);
8362 WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
8363 }
8364 if (kvm_cpu_has_injectable_intr(vcpu))
8365 kvm_x86_ops.enable_irq_window(vcpu);
8366 }
8367
8368 if (is_guest_mode(vcpu) &&
8369 kvm_x86_ops.nested_ops->hv_timer_pending &&
8370 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8371 *req_immediate_exit = true;
8372
8373 WARN_ON(vcpu->arch.exception.pending);
8374 return;
8375
8376 busy:
8377 *req_immediate_exit = true;
8378 return;
8379 }
8380
8381 static void process_nmi(struct kvm_vcpu *vcpu)
8382 {
8383 unsigned limit = 2;
8384
8385 /*
8386 * x86 is limited to one NMI running, and one NMI pending after it.
8387 * If an NMI is already in progress, limit further NMIs to just one.
8388 * Otherwise, allow two (and we'll inject the first one immediately).
8389 */
8390 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
8391 limit = 1;
8392
8393 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8394 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8395 kvm_make_request(KVM_REQ_EVENT, vcpu);
8396 }
8397
8398 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8399 {
8400 u32 flags = 0;
8401 flags |= seg->g << 23;
8402 flags |= seg->db << 22;
8403 flags |= seg->l << 21;
8404 flags |= seg->avl << 20;
8405 flags |= seg->present << 15;
8406 flags |= seg->dpl << 13;
8407 flags |= seg->s << 12;
8408 flags |= seg->type << 8;
8409 return flags;
8410 }
8411
8412 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8413 {
8414 struct kvm_segment seg;
8415 int offset;
8416
8417 kvm_get_segment(vcpu, &seg, n);
8418 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8419
8420 if (n < 3)
8421 offset = 0x7f84 + n * 12;
8422 else
8423 offset = 0x7f2c + (n - 3) * 12;
8424
8425 put_smstate(u32, buf, offset + 8, seg.base);
8426 put_smstate(u32, buf, offset + 4, seg.limit);
8427 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8428 }
8429
8430 #ifdef CONFIG_X86_64
8431 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8432 {
8433 struct kvm_segment seg;
8434 int offset;
8435 u16 flags;
8436
8437 kvm_get_segment(vcpu, &seg, n);
8438 offset = 0x7e00 + n * 16;
8439
8440 flags = enter_smm_get_segment_flags(&seg) >> 8;
8441 put_smstate(u16, buf, offset, seg.selector);
8442 put_smstate(u16, buf, offset + 2, flags);
8443 put_smstate(u32, buf, offset + 4, seg.limit);
8444 put_smstate(u64, buf, offset + 8, seg.base);
8445 }
8446 #endif
8447
8448 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8449 {
8450 struct desc_ptr dt;
8451 struct kvm_segment seg;
8452 unsigned long val;
8453 int i;
8454
8455 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8456 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8457 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8458 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8459
8460 for (i = 0; i < 8; i++)
8461 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8462
8463 kvm_get_dr(vcpu, 6, &val);
8464 put_smstate(u32, buf, 0x7fcc, (u32)val);
8465 kvm_get_dr(vcpu, 7, &val);
8466 put_smstate(u32, buf, 0x7fc8, (u32)val);
8467
8468 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8469 put_smstate(u32, buf, 0x7fc4, seg.selector);
8470 put_smstate(u32, buf, 0x7f64, seg.base);
8471 put_smstate(u32, buf, 0x7f60, seg.limit);
8472 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8473
8474 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8475 put_smstate(u32, buf, 0x7fc0, seg.selector);
8476 put_smstate(u32, buf, 0x7f80, seg.base);
8477 put_smstate(u32, buf, 0x7f7c, seg.limit);
8478 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8479
8480 kvm_x86_ops.get_gdt(vcpu, &dt);
8481 put_smstate(u32, buf, 0x7f74, dt.address);
8482 put_smstate(u32, buf, 0x7f70, dt.size);
8483
8484 kvm_x86_ops.get_idt(vcpu, &dt);
8485 put_smstate(u32, buf, 0x7f58, dt.address);
8486 put_smstate(u32, buf, 0x7f54, dt.size);
8487
8488 for (i = 0; i < 6; i++)
8489 enter_smm_save_seg_32(vcpu, buf, i);
8490
8491 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8492
8493 /* revision id */
8494 put_smstate(u32, buf, 0x7efc, 0x00020000);
8495 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8496 }
8497
8498 #ifdef CONFIG_X86_64
8499 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8500 {
8501 struct desc_ptr dt;
8502 struct kvm_segment seg;
8503 unsigned long val;
8504 int i;
8505
8506 for (i = 0; i < 16; i++)
8507 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8508
8509 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8510 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8511
8512 kvm_get_dr(vcpu, 6, &val);
8513 put_smstate(u64, buf, 0x7f68, val);
8514 kvm_get_dr(vcpu, 7, &val);
8515 put_smstate(u64, buf, 0x7f60, val);
8516
8517 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8518 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8519 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8520
8521 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8522
8523 /* revision id */
8524 put_smstate(u32, buf, 0x7efc, 0x00020064);
8525
8526 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8527
8528 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8529 put_smstate(u16, buf, 0x7e90, seg.selector);
8530 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8531 put_smstate(u32, buf, 0x7e94, seg.limit);
8532 put_smstate(u64, buf, 0x7e98, seg.base);
8533
8534 kvm_x86_ops.get_idt(vcpu, &dt);
8535 put_smstate(u32, buf, 0x7e84, dt.size);
8536 put_smstate(u64, buf, 0x7e88, dt.address);
8537
8538 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8539 put_smstate(u16, buf, 0x7e70, seg.selector);
8540 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8541 put_smstate(u32, buf, 0x7e74, seg.limit);
8542 put_smstate(u64, buf, 0x7e78, seg.base);
8543
8544 kvm_x86_ops.get_gdt(vcpu, &dt);
8545 put_smstate(u32, buf, 0x7e64, dt.size);
8546 put_smstate(u64, buf, 0x7e68, dt.address);
8547
8548 for (i = 0; i < 6; i++)
8549 enter_smm_save_seg_64(vcpu, buf, i);
8550 }
8551 #endif
8552
8553 static void enter_smm(struct kvm_vcpu *vcpu)
8554 {
8555 struct kvm_segment cs, ds;
8556 struct desc_ptr dt;
8557 char buf[512];
8558 u32 cr0;
8559
8560 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8561 memset(buf, 0, 512);
8562 #ifdef CONFIG_X86_64
8563 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8564 enter_smm_save_state_64(vcpu, buf);
8565 else
8566 #endif
8567 enter_smm_save_state_32(vcpu, buf);
8568
8569 /*
8570 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8571 * vCPU state (e.g. leave guest mode) after we've saved the state into
8572 * the SMM state-save area.
8573 */
8574 kvm_x86_ops.pre_enter_smm(vcpu, buf);
8575
8576 vcpu->arch.hflags |= HF_SMM_MASK;
8577 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8578
8579 if (kvm_x86_ops.get_nmi_mask(vcpu))
8580 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8581 else
8582 kvm_x86_ops.set_nmi_mask(vcpu, true);
8583
8584 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8585 kvm_rip_write(vcpu, 0x8000);
8586
8587 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8588 kvm_x86_ops.set_cr0(vcpu, cr0);
8589 vcpu->arch.cr0 = cr0;
8590
8591 kvm_x86_ops.set_cr4(vcpu, 0);
8592
8593 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8594 dt.address = dt.size = 0;
8595 kvm_x86_ops.set_idt(vcpu, &dt);
8596
8597 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8598
8599 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8600 cs.base = vcpu->arch.smbase;
8601
8602 ds.selector = 0;
8603 ds.base = 0;
8604
8605 cs.limit = ds.limit = 0xffffffff;
8606 cs.type = ds.type = 0x3;
8607 cs.dpl = ds.dpl = 0;
8608 cs.db = ds.db = 0;
8609 cs.s = ds.s = 1;
8610 cs.l = ds.l = 0;
8611 cs.g = ds.g = 1;
8612 cs.avl = ds.avl = 0;
8613 cs.present = ds.present = 1;
8614 cs.unusable = ds.unusable = 0;
8615 cs.padding = ds.padding = 0;
8616
8617 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8618 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8619 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8620 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8621 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8622 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8623
8624 #ifdef CONFIG_X86_64
8625 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8626 kvm_x86_ops.set_efer(vcpu, 0);
8627 #endif
8628
8629 kvm_update_cpuid_runtime(vcpu);
8630 kvm_mmu_reset_context(vcpu);
8631 }
8632
8633 static void process_smi(struct kvm_vcpu *vcpu)
8634 {
8635 vcpu->arch.smi_pending = true;
8636 kvm_make_request(KVM_REQ_EVENT, vcpu);
8637 }
8638
8639 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8640 unsigned long *vcpu_bitmap)
8641 {
8642 cpumask_var_t cpus;
8643
8644 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8645
8646 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8647 NULL, vcpu_bitmap, cpus);
8648
8649 free_cpumask_var(cpus);
8650 }
8651
8652 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8653 {
8654 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8655 }
8656
8657 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8658 {
8659 if (!lapic_in_kernel(vcpu))
8660 return;
8661
8662 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8663 kvm_apic_update_apicv(vcpu);
8664 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8665 }
8666 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8667
8668 /*
8669 * NOTE: Do not hold any lock prior to calling this.
8670 *
8671 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8672 * locked, because it calls __x86_set_memory_region() which does
8673 * synchronize_srcu(&kvm->srcu).
8674 */
8675 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8676 {
8677 struct kvm_vcpu *except;
8678 unsigned long old, new, expected;
8679
8680 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8681 !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8682 return;
8683
8684 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8685 do {
8686 expected = new = old;
8687 if (activate)
8688 __clear_bit(bit, &new);
8689 else
8690 __set_bit(bit, &new);
8691 if (new == old)
8692 break;
8693 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8694 } while (old != expected);
8695
8696 if (!!old == !!new)
8697 return;
8698
8699 trace_kvm_apicv_update_request(activate, bit);
8700 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8701 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8702
8703 /*
8704 * Sending request to update APICV for all other vcpus,
8705 * while update the calling vcpu immediately instead of
8706 * waiting for another #VMEXIT to handle the request.
8707 */
8708 except = kvm_get_running_vcpu();
8709 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8710 except);
8711 if (except)
8712 kvm_vcpu_update_apicv(except);
8713 }
8714 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8715
8716 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8717 {
8718 if (!kvm_apic_present(vcpu))
8719 return;
8720
8721 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8722
8723 if (irqchip_split(vcpu->kvm))
8724 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8725 else {
8726 if (vcpu->arch.apicv_active)
8727 kvm_x86_ops.sync_pir_to_irr(vcpu);
8728 if (ioapic_in_kernel(vcpu->kvm))
8729 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8730 }
8731
8732 if (is_guest_mode(vcpu))
8733 vcpu->arch.load_eoi_exitmap_pending = true;
8734 else
8735 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8736 }
8737
8738 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8739 {
8740 u64 eoi_exit_bitmap[4];
8741
8742 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8743 return;
8744
8745 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8746 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8747 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8748 }
8749
8750 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8751 unsigned long start, unsigned long end)
8752 {
8753 unsigned long apic_address;
8754
8755 /*
8756 * The physical address of apic access page is stored in the VMCS.
8757 * Update it when it becomes invalid.
8758 */
8759 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8760 if (start <= apic_address && apic_address < end)
8761 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8762 }
8763
8764 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8765 {
8766 if (!lapic_in_kernel(vcpu))
8767 return;
8768
8769 if (!kvm_x86_ops.set_apic_access_page_addr)
8770 return;
8771
8772 kvm_x86_ops.set_apic_access_page_addr(vcpu);
8773 }
8774
8775 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8776 {
8777 smp_send_reschedule(vcpu->cpu);
8778 }
8779 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8780
8781 /*
8782 * Returns 1 to let vcpu_run() continue the guest execution loop without
8783 * exiting to the userspace. Otherwise, the value will be returned to the
8784 * userspace.
8785 */
8786 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8787 {
8788 int r;
8789 bool req_int_win =
8790 dm_request_for_irq_injection(vcpu) &&
8791 kvm_cpu_accept_dm_intr(vcpu);
8792 fastpath_t exit_fastpath;
8793
8794 bool req_immediate_exit = false;
8795
8796 /* Forbid vmenter if vcpu dirty ring is soft-full */
8797 if (unlikely(vcpu->kvm->dirty_ring_size &&
8798 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
8799 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
8800 trace_kvm_dirty_ring_exit(vcpu);
8801 r = 0;
8802 goto out;
8803 }
8804
8805 if (kvm_request_pending(vcpu)) {
8806 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8807 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8808 r = 0;
8809 goto out;
8810 }
8811 }
8812 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8813 kvm_mmu_unload(vcpu);
8814 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8815 __kvm_migrate_timers(vcpu);
8816 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8817 kvm_gen_update_masterclock(vcpu->kvm);
8818 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8819 kvm_gen_kvmclock_update(vcpu);
8820 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8821 r = kvm_guest_time_update(vcpu);
8822 if (unlikely(r))
8823 goto out;
8824 }
8825 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8826 kvm_mmu_sync_roots(vcpu);
8827 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8828 kvm_mmu_load_pgd(vcpu);
8829 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8830 kvm_vcpu_flush_tlb_all(vcpu);
8831
8832 /* Flushing all ASIDs flushes the current ASID... */
8833 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8834 }
8835 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8836 kvm_vcpu_flush_tlb_current(vcpu);
8837 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8838 kvm_vcpu_flush_tlb_guest(vcpu);
8839
8840 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8841 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8842 r = 0;
8843 goto out;
8844 }
8845 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8846 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8847 vcpu->mmio_needed = 0;
8848 r = 0;
8849 goto out;
8850 }
8851 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8852 /* Page is swapped out. Do synthetic halt */
8853 vcpu->arch.apf.halted = true;
8854 r = 1;
8855 goto out;
8856 }
8857 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8858 record_steal_time(vcpu);
8859 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8860 process_smi(vcpu);
8861 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8862 process_nmi(vcpu);
8863 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8864 kvm_pmu_handle_event(vcpu);
8865 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8866 kvm_pmu_deliver_pmi(vcpu);
8867 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8868 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8869 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8870 vcpu->arch.ioapic_handled_vectors)) {
8871 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8872 vcpu->run->eoi.vector =
8873 vcpu->arch.pending_ioapic_eoi;
8874 r = 0;
8875 goto out;
8876 }
8877 }
8878 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8879 vcpu_scan_ioapic(vcpu);
8880 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8881 vcpu_load_eoi_exitmap(vcpu);
8882 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8883 kvm_vcpu_reload_apic_access_page(vcpu);
8884 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8885 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8886 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8887 r = 0;
8888 goto out;
8889 }
8890 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8891 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8892 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8893 r = 0;
8894 goto out;
8895 }
8896 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8897 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8898 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8899 r = 0;
8900 goto out;
8901 }
8902
8903 /*
8904 * KVM_REQ_HV_STIMER has to be processed after
8905 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8906 * depend on the guest clock being up-to-date
8907 */
8908 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8909 kvm_hv_process_stimers(vcpu);
8910 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8911 kvm_vcpu_update_apicv(vcpu);
8912 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8913 kvm_check_async_pf_completion(vcpu);
8914 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8915 kvm_x86_ops.msr_filter_changed(vcpu);
8916 }
8917
8918 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8919 ++vcpu->stat.req_event;
8920 kvm_apic_accept_events(vcpu);
8921 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8922 r = 1;
8923 goto out;
8924 }
8925
8926 inject_pending_event(vcpu, &req_immediate_exit);
8927 if (req_int_win)
8928 kvm_x86_ops.enable_irq_window(vcpu);
8929
8930 if (kvm_lapic_enabled(vcpu)) {
8931 update_cr8_intercept(vcpu);
8932 kvm_lapic_sync_to_vapic(vcpu);
8933 }
8934 }
8935
8936 r = kvm_mmu_reload(vcpu);
8937 if (unlikely(r)) {
8938 goto cancel_injection;
8939 }
8940
8941 preempt_disable();
8942
8943 kvm_x86_ops.prepare_guest_switch(vcpu);
8944
8945 /*
8946 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8947 * IPI are then delayed after guest entry, which ensures that they
8948 * result in virtual interrupt delivery.
8949 */
8950 local_irq_disable();
8951 vcpu->mode = IN_GUEST_MODE;
8952
8953 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8954
8955 /*
8956 * 1) We should set ->mode before checking ->requests. Please see
8957 * the comment in kvm_vcpu_exiting_guest_mode().
8958 *
8959 * 2) For APICv, we should set ->mode before checking PID.ON. This
8960 * pairs with the memory barrier implicit in pi_test_and_set_on
8961 * (see vmx_deliver_posted_interrupt).
8962 *
8963 * 3) This also orders the write to mode from any reads to the page
8964 * tables done while the VCPU is running. Please see the comment
8965 * in kvm_flush_remote_tlbs.
8966 */
8967 smp_mb__after_srcu_read_unlock();
8968
8969 /*
8970 * This handles the case where a posted interrupt was
8971 * notified with kvm_vcpu_kick.
8972 */
8973 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8974 kvm_x86_ops.sync_pir_to_irr(vcpu);
8975
8976 if (kvm_vcpu_exit_request(vcpu)) {
8977 vcpu->mode = OUTSIDE_GUEST_MODE;
8978 smp_wmb();
8979 local_irq_enable();
8980 preempt_enable();
8981 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8982 r = 1;
8983 goto cancel_injection;
8984 }
8985
8986 if (req_immediate_exit) {
8987 kvm_make_request(KVM_REQ_EVENT, vcpu);
8988 kvm_x86_ops.request_immediate_exit(vcpu);
8989 }
8990
8991 fpregs_assert_state_consistent();
8992 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8993 switch_fpu_return();
8994
8995 if (unlikely(vcpu->arch.switch_db_regs)) {
8996 set_debugreg(0, 7);
8997 set_debugreg(vcpu->arch.eff_db[0], 0);
8998 set_debugreg(vcpu->arch.eff_db[1], 1);
8999 set_debugreg(vcpu->arch.eff_db[2], 2);
9000 set_debugreg(vcpu->arch.eff_db[3], 3);
9001 set_debugreg(vcpu->arch.dr6, 6);
9002 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9003 }
9004
9005 exit_fastpath = kvm_x86_ops.run(vcpu);
9006
9007 /*
9008 * Do this here before restoring debug registers on the host. And
9009 * since we do this before handling the vmexit, a DR access vmexit
9010 * can (a) read the correct value of the debug registers, (b) set
9011 * KVM_DEBUGREG_WONT_EXIT again.
9012 */
9013 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
9014 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
9015 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
9016 kvm_update_dr0123(vcpu);
9017 kvm_update_dr7(vcpu);
9018 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9019 }
9020
9021 /*
9022 * If the guest has used debug registers, at least dr7
9023 * will be disabled while returning to the host.
9024 * If we don't have active breakpoints in the host, we don't
9025 * care about the messed up debug address registers. But if
9026 * we have some of them active, restore the old state.
9027 */
9028 if (hw_breakpoint_active())
9029 hw_breakpoint_restore();
9030
9031 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
9032 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
9033
9034 vcpu->mode = OUTSIDE_GUEST_MODE;
9035 smp_wmb();
9036
9037 kvm_x86_ops.handle_exit_irqoff(vcpu);
9038
9039 /*
9040 * Consume any pending interrupts, including the possible source of
9041 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
9042 * An instruction is required after local_irq_enable() to fully unblock
9043 * interrupts on processors that implement an interrupt shadow, the
9044 * stat.exits increment will do nicely.
9045 */
9046 kvm_before_interrupt(vcpu);
9047 local_irq_enable();
9048 ++vcpu->stat.exits;
9049 local_irq_disable();
9050 kvm_after_interrupt(vcpu);
9051
9052 if (lapic_in_kernel(vcpu)) {
9053 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
9054 if (delta != S64_MIN) {
9055 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
9056 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
9057 }
9058 }
9059
9060 local_irq_enable();
9061 preempt_enable();
9062
9063 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9064
9065 /*
9066 * Profile KVM exit RIPs:
9067 */
9068 if (unlikely(prof_on == KVM_PROFILING)) {
9069 unsigned long rip = kvm_rip_read(vcpu);
9070 profile_hit(KVM_PROFILING, (void *)rip);
9071 }
9072
9073 if (unlikely(vcpu->arch.tsc_always_catchup))
9074 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9075
9076 if (vcpu->arch.apic_attention)
9077 kvm_lapic_sync_from_vapic(vcpu);
9078
9079 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
9080 return r;
9081
9082 cancel_injection:
9083 if (req_immediate_exit)
9084 kvm_make_request(KVM_REQ_EVENT, vcpu);
9085 kvm_x86_ops.cancel_injection(vcpu);
9086 if (unlikely(vcpu->arch.apic_attention))
9087 kvm_lapic_sync_from_vapic(vcpu);
9088 out:
9089 return r;
9090 }
9091
9092 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
9093 {
9094 if (!kvm_arch_vcpu_runnable(vcpu) &&
9095 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
9096 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9097 kvm_vcpu_block(vcpu);
9098 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9099
9100 if (kvm_x86_ops.post_block)
9101 kvm_x86_ops.post_block(vcpu);
9102
9103 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
9104 return 1;
9105 }
9106
9107 kvm_apic_accept_events(vcpu);
9108 switch(vcpu->arch.mp_state) {
9109 case KVM_MP_STATE_HALTED:
9110 case KVM_MP_STATE_AP_RESET_HOLD:
9111 vcpu->arch.pv.pv_unhalted = false;
9112 vcpu->arch.mp_state =
9113 KVM_MP_STATE_RUNNABLE;
9114 fallthrough;
9115 case KVM_MP_STATE_RUNNABLE:
9116 vcpu->arch.apf.halted = false;
9117 break;
9118 case KVM_MP_STATE_INIT_RECEIVED:
9119 break;
9120 default:
9121 return -EINTR;
9122 }
9123 return 1;
9124 }
9125
9126 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
9127 {
9128 if (is_guest_mode(vcpu))
9129 kvm_x86_ops.nested_ops->check_events(vcpu);
9130
9131 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
9132 !vcpu->arch.apf.halted);
9133 }
9134
9135 static int vcpu_run(struct kvm_vcpu *vcpu)
9136 {
9137 int r;
9138 struct kvm *kvm = vcpu->kvm;
9139
9140 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9141 vcpu->arch.l1tf_flush_l1d = true;
9142
9143 for (;;) {
9144 if (kvm_vcpu_running(vcpu)) {
9145 r = vcpu_enter_guest(vcpu);
9146 } else {
9147 r = vcpu_block(kvm, vcpu);
9148 }
9149
9150 if (r <= 0)
9151 break;
9152
9153 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
9154 if (kvm_cpu_has_pending_timer(vcpu))
9155 kvm_inject_pending_timer_irqs(vcpu);
9156
9157 if (dm_request_for_irq_injection(vcpu) &&
9158 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9159 r = 0;
9160 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9161 ++vcpu->stat.request_irq_exits;
9162 break;
9163 }
9164
9165 if (__xfer_to_guest_mode_work_pending()) {
9166 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9167 r = xfer_to_guest_mode_handle_work(vcpu);
9168 if (r)
9169 return r;
9170 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9171 }
9172 }
9173
9174 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9175
9176 return r;
9177 }
9178
9179 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9180 {
9181 int r;
9182
9183 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9184 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9185 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9186 return r;
9187 }
9188
9189 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9190 {
9191 BUG_ON(!vcpu->arch.pio.count);
9192
9193 return complete_emulated_io(vcpu);
9194 }
9195
9196 /*
9197 * Implements the following, as a state machine:
9198 *
9199 * read:
9200 * for each fragment
9201 * for each mmio piece in the fragment
9202 * write gpa, len
9203 * exit
9204 * copy data
9205 * execute insn
9206 *
9207 * write:
9208 * for each fragment
9209 * for each mmio piece in the fragment
9210 * write gpa, len
9211 * copy data
9212 * exit
9213 */
9214 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9215 {
9216 struct kvm_run *run = vcpu->run;
9217 struct kvm_mmio_fragment *frag;
9218 unsigned len;
9219
9220 BUG_ON(!vcpu->mmio_needed);
9221
9222 /* Complete previous fragment */
9223 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9224 len = min(8u, frag->len);
9225 if (!vcpu->mmio_is_write)
9226 memcpy(frag->data, run->mmio.data, len);
9227
9228 if (frag->len <= 8) {
9229 /* Switch to the next fragment. */
9230 frag++;
9231 vcpu->mmio_cur_fragment++;
9232 } else {
9233 /* Go forward to the next mmio piece. */
9234 frag->data += len;
9235 frag->gpa += len;
9236 frag->len -= len;
9237 }
9238
9239 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9240 vcpu->mmio_needed = 0;
9241
9242 /* FIXME: return into emulator if single-stepping. */
9243 if (vcpu->mmio_is_write)
9244 return 1;
9245 vcpu->mmio_read_completed = 1;
9246 return complete_emulated_io(vcpu);
9247 }
9248
9249 run->exit_reason = KVM_EXIT_MMIO;
9250 run->mmio.phys_addr = frag->gpa;
9251 if (vcpu->mmio_is_write)
9252 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9253 run->mmio.len = min(8u, frag->len);
9254 run->mmio.is_write = vcpu->mmio_is_write;
9255 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9256 return 0;
9257 }
9258
9259 static void kvm_save_current_fpu(struct fpu *fpu)
9260 {
9261 /*
9262 * If the target FPU state is not resident in the CPU registers, just
9263 * memcpy() from current, else save CPU state directly to the target.
9264 */
9265 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9266 memcpy(&fpu->state, &current->thread.fpu.state,
9267 fpu_kernel_xstate_size);
9268 else
9269 copy_fpregs_to_fpstate(fpu);
9270 }
9271
9272 /* Swap (qemu) user FPU context for the guest FPU context. */
9273 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9274 {
9275 fpregs_lock();
9276
9277 kvm_save_current_fpu(vcpu->arch.user_fpu);
9278
9279 /*
9280 * Guests with protected state can't have it set by the hypervisor,
9281 * so skip trying to set it.
9282 */
9283 if (vcpu->arch.guest_fpu)
9284 /* PKRU is separately restored in kvm_x86_ops.run. */
9285 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9286 ~XFEATURE_MASK_PKRU);
9287
9288 fpregs_mark_activate();
9289 fpregs_unlock();
9290
9291 trace_kvm_fpu(1);
9292 }
9293
9294 /* When vcpu_run ends, restore user space FPU context. */
9295 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9296 {
9297 fpregs_lock();
9298
9299 /*
9300 * Guests with protected state can't have it read by the hypervisor,
9301 * so skip trying to save it.
9302 */
9303 if (vcpu->arch.guest_fpu)
9304 kvm_save_current_fpu(vcpu->arch.guest_fpu);
9305
9306 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9307
9308 fpregs_mark_activate();
9309 fpregs_unlock();
9310
9311 ++vcpu->stat.fpu_reload;
9312 trace_kvm_fpu(0);
9313 }
9314
9315 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9316 {
9317 struct kvm_run *kvm_run = vcpu->run;
9318 int r;
9319
9320 vcpu_load(vcpu);
9321 kvm_sigset_activate(vcpu);
9322 kvm_load_guest_fpu(vcpu);
9323
9324 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9325 if (kvm_run->immediate_exit) {
9326 r = -EINTR;
9327 goto out;
9328 }
9329 kvm_vcpu_block(vcpu);
9330 kvm_apic_accept_events(vcpu);
9331 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9332 r = -EAGAIN;
9333 if (signal_pending(current)) {
9334 r = -EINTR;
9335 kvm_run->exit_reason = KVM_EXIT_INTR;
9336 ++vcpu->stat.signal_exits;
9337 }
9338 goto out;
9339 }
9340
9341 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9342 r = -EINVAL;
9343 goto out;
9344 }
9345
9346 if (kvm_run->kvm_dirty_regs) {
9347 r = sync_regs(vcpu);
9348 if (r != 0)
9349 goto out;
9350 }
9351
9352 /* re-sync apic's tpr */
9353 if (!lapic_in_kernel(vcpu)) {
9354 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9355 r = -EINVAL;
9356 goto out;
9357 }
9358 }
9359
9360 if (unlikely(vcpu->arch.complete_userspace_io)) {
9361 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9362 vcpu->arch.complete_userspace_io = NULL;
9363 r = cui(vcpu);
9364 if (r <= 0)
9365 goto out;
9366 } else
9367 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9368
9369 if (kvm_run->immediate_exit)
9370 r = -EINTR;
9371 else
9372 r = vcpu_run(vcpu);
9373
9374 out:
9375 kvm_put_guest_fpu(vcpu);
9376 if (kvm_run->kvm_valid_regs)
9377 store_regs(vcpu);
9378 post_kvm_run_save(vcpu);
9379 kvm_sigset_deactivate(vcpu);
9380
9381 vcpu_put(vcpu);
9382 return r;
9383 }
9384
9385 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9386 {
9387 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9388 /*
9389 * We are here if userspace calls get_regs() in the middle of
9390 * instruction emulation. Registers state needs to be copied
9391 * back from emulation context to vcpu. Userspace shouldn't do
9392 * that usually, but some bad designed PV devices (vmware
9393 * backdoor interface) need this to work
9394 */
9395 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9396 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9397 }
9398 regs->rax = kvm_rax_read(vcpu);
9399 regs->rbx = kvm_rbx_read(vcpu);
9400 regs->rcx = kvm_rcx_read(vcpu);
9401 regs->rdx = kvm_rdx_read(vcpu);
9402 regs->rsi = kvm_rsi_read(vcpu);
9403 regs->rdi = kvm_rdi_read(vcpu);
9404 regs->rsp = kvm_rsp_read(vcpu);
9405 regs->rbp = kvm_rbp_read(vcpu);
9406 #ifdef CONFIG_X86_64
9407 regs->r8 = kvm_r8_read(vcpu);
9408 regs->r9 = kvm_r9_read(vcpu);
9409 regs->r10 = kvm_r10_read(vcpu);
9410 regs->r11 = kvm_r11_read(vcpu);
9411 regs->r12 = kvm_r12_read(vcpu);
9412 regs->r13 = kvm_r13_read(vcpu);
9413 regs->r14 = kvm_r14_read(vcpu);
9414 regs->r15 = kvm_r15_read(vcpu);
9415 #endif
9416
9417 regs->rip = kvm_rip_read(vcpu);
9418 regs->rflags = kvm_get_rflags(vcpu);
9419 }
9420
9421 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9422 {
9423 vcpu_load(vcpu);
9424 __get_regs(vcpu, regs);
9425 vcpu_put(vcpu);
9426 return 0;
9427 }
9428
9429 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9430 {
9431 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9432 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9433
9434 kvm_rax_write(vcpu, regs->rax);
9435 kvm_rbx_write(vcpu, regs->rbx);
9436 kvm_rcx_write(vcpu, regs->rcx);
9437 kvm_rdx_write(vcpu, regs->rdx);
9438 kvm_rsi_write(vcpu, regs->rsi);
9439 kvm_rdi_write(vcpu, regs->rdi);
9440 kvm_rsp_write(vcpu, regs->rsp);
9441 kvm_rbp_write(vcpu, regs->rbp);
9442 #ifdef CONFIG_X86_64
9443 kvm_r8_write(vcpu, regs->r8);
9444 kvm_r9_write(vcpu, regs->r9);
9445 kvm_r10_write(vcpu, regs->r10);
9446 kvm_r11_write(vcpu, regs->r11);
9447 kvm_r12_write(vcpu, regs->r12);
9448 kvm_r13_write(vcpu, regs->r13);
9449 kvm_r14_write(vcpu, regs->r14);
9450 kvm_r15_write(vcpu, regs->r15);
9451 #endif
9452
9453 kvm_rip_write(vcpu, regs->rip);
9454 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9455
9456 vcpu->arch.exception.pending = false;
9457
9458 kvm_make_request(KVM_REQ_EVENT, vcpu);
9459 }
9460
9461 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9462 {
9463 vcpu_load(vcpu);
9464 __set_regs(vcpu, regs);
9465 vcpu_put(vcpu);
9466 return 0;
9467 }
9468
9469 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9470 {
9471 struct kvm_segment cs;
9472
9473 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9474 *db = cs.db;
9475 *l = cs.l;
9476 }
9477 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9478
9479 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9480 {
9481 struct desc_ptr dt;
9482
9483 if (vcpu->arch.guest_state_protected)
9484 goto skip_protected_regs;
9485
9486 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9487 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9488 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9489 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9490 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9491 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9492
9493 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9494 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9495
9496 kvm_x86_ops.get_idt(vcpu, &dt);
9497 sregs->idt.limit = dt.size;
9498 sregs->idt.base = dt.address;
9499 kvm_x86_ops.get_gdt(vcpu, &dt);
9500 sregs->gdt.limit = dt.size;
9501 sregs->gdt.base = dt.address;
9502
9503 sregs->cr2 = vcpu->arch.cr2;
9504 sregs->cr3 = kvm_read_cr3(vcpu);
9505
9506 skip_protected_regs:
9507 sregs->cr0 = kvm_read_cr0(vcpu);
9508 sregs->cr4 = kvm_read_cr4(vcpu);
9509 sregs->cr8 = kvm_get_cr8(vcpu);
9510 sregs->efer = vcpu->arch.efer;
9511 sregs->apic_base = kvm_get_apic_base(vcpu);
9512
9513 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9514
9515 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9516 set_bit(vcpu->arch.interrupt.nr,
9517 (unsigned long *)sregs->interrupt_bitmap);
9518 }
9519
9520 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9521 struct kvm_sregs *sregs)
9522 {
9523 vcpu_load(vcpu);
9524 __get_sregs(vcpu, sregs);
9525 vcpu_put(vcpu);
9526 return 0;
9527 }
9528
9529 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9530 struct kvm_mp_state *mp_state)
9531 {
9532 vcpu_load(vcpu);
9533 if (kvm_mpx_supported())
9534 kvm_load_guest_fpu(vcpu);
9535
9536 kvm_apic_accept_events(vcpu);
9537 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
9538 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
9539 vcpu->arch.pv.pv_unhalted)
9540 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9541 else
9542 mp_state->mp_state = vcpu->arch.mp_state;
9543
9544 if (kvm_mpx_supported())
9545 kvm_put_guest_fpu(vcpu);
9546 vcpu_put(vcpu);
9547 return 0;
9548 }
9549
9550 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9551 struct kvm_mp_state *mp_state)
9552 {
9553 int ret = -EINVAL;
9554
9555 vcpu_load(vcpu);
9556
9557 if (!lapic_in_kernel(vcpu) &&
9558 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9559 goto out;
9560
9561 /*
9562 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9563 * INIT state; latched init should be reported using
9564 * KVM_SET_VCPU_EVENTS, so reject it here.
9565 */
9566 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9567 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9568 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9569 goto out;
9570
9571 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9572 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9573 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9574 } else
9575 vcpu->arch.mp_state = mp_state->mp_state;
9576 kvm_make_request(KVM_REQ_EVENT, vcpu);
9577
9578 ret = 0;
9579 out:
9580 vcpu_put(vcpu);
9581 return ret;
9582 }
9583
9584 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9585 int reason, bool has_error_code, u32 error_code)
9586 {
9587 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9588 int ret;
9589
9590 init_emulate_ctxt(vcpu);
9591
9592 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9593 has_error_code, error_code);
9594 if (ret) {
9595 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9596 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9597 vcpu->run->internal.ndata = 0;
9598 return 0;
9599 }
9600
9601 kvm_rip_write(vcpu, ctxt->eip);
9602 kvm_set_rflags(vcpu, ctxt->eflags);
9603 return 1;
9604 }
9605 EXPORT_SYMBOL_GPL(kvm_task_switch);
9606
9607 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9608 {
9609 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9610 /*
9611 * When EFER.LME and CR0.PG are set, the processor is in
9612 * 64-bit mode (though maybe in a 32-bit code segment).
9613 * CR4.PAE and EFER.LMA must be set.
9614 */
9615 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
9616 return false;
9617 if (sregs->cr3 & vcpu->arch.cr3_lm_rsvd_bits)
9618 return false;
9619 } else {
9620 /*
9621 * Not in 64-bit mode: EFER.LMA is clear and the code
9622 * segment cannot be 64-bit.
9623 */
9624 if (sregs->efer & EFER_LMA || sregs->cs.l)
9625 return false;
9626 }
9627
9628 return kvm_is_valid_cr4(vcpu, sregs->cr4);
9629 }
9630
9631 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9632 {
9633 struct msr_data apic_base_msr;
9634 int mmu_reset_needed = 0;
9635 int pending_vec, max_bits, idx;
9636 struct desc_ptr dt;
9637 int ret = -EINVAL;
9638
9639 if (!kvm_is_valid_sregs(vcpu, sregs))
9640 goto out;
9641
9642 apic_base_msr.data = sregs->apic_base;
9643 apic_base_msr.host_initiated = true;
9644 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9645 goto out;
9646
9647 if (vcpu->arch.guest_state_protected)
9648 goto skip_protected_regs;
9649
9650 dt.size = sregs->idt.limit;
9651 dt.address = sregs->idt.base;
9652 kvm_x86_ops.set_idt(vcpu, &dt);
9653 dt.size = sregs->gdt.limit;
9654 dt.address = sregs->gdt.base;
9655 kvm_x86_ops.set_gdt(vcpu, &dt);
9656
9657 vcpu->arch.cr2 = sregs->cr2;
9658 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9659 vcpu->arch.cr3 = sregs->cr3;
9660 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9661
9662 kvm_set_cr8(vcpu, sregs->cr8);
9663
9664 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9665 kvm_x86_ops.set_efer(vcpu, sregs->efer);
9666
9667 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9668 kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9669 vcpu->arch.cr0 = sregs->cr0;
9670
9671 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9672 kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9673
9674 idx = srcu_read_lock(&vcpu->kvm->srcu);
9675 if (is_pae_paging(vcpu)) {
9676 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9677 mmu_reset_needed = 1;
9678 }
9679 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9680
9681 if (mmu_reset_needed)
9682 kvm_mmu_reset_context(vcpu);
9683
9684 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9685 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9686 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9687 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9688 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9689 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9690
9691 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9692 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9693
9694 update_cr8_intercept(vcpu);
9695
9696 /* Older userspace won't unhalt the vcpu on reset. */
9697 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9698 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9699 !is_protmode(vcpu))
9700 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9701
9702 skip_protected_regs:
9703 max_bits = KVM_NR_INTERRUPTS;
9704 pending_vec = find_first_bit(
9705 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9706 if (pending_vec < max_bits) {
9707 kvm_queue_interrupt(vcpu, pending_vec, false);
9708 pr_debug("Set back pending irq %d\n", pending_vec);
9709 }
9710
9711 kvm_make_request(KVM_REQ_EVENT, vcpu);
9712
9713 ret = 0;
9714 out:
9715 return ret;
9716 }
9717
9718 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9719 struct kvm_sregs *sregs)
9720 {
9721 int ret;
9722
9723 vcpu_load(vcpu);
9724 ret = __set_sregs(vcpu, sregs);
9725 vcpu_put(vcpu);
9726 return ret;
9727 }
9728
9729 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9730 struct kvm_guest_debug *dbg)
9731 {
9732 unsigned long rflags;
9733 int i, r;
9734
9735 if (vcpu->arch.guest_state_protected)
9736 return -EINVAL;
9737
9738 vcpu_load(vcpu);
9739
9740 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9741 r = -EBUSY;
9742 if (vcpu->arch.exception.pending)
9743 goto out;
9744 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9745 kvm_queue_exception(vcpu, DB_VECTOR);
9746 else
9747 kvm_queue_exception(vcpu, BP_VECTOR);
9748 }
9749
9750 /*
9751 * Read rflags as long as potentially injected trace flags are still
9752 * filtered out.
9753 */
9754 rflags = kvm_get_rflags(vcpu);
9755
9756 vcpu->guest_debug = dbg->control;
9757 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9758 vcpu->guest_debug = 0;
9759
9760 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9761 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9762 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9763 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9764 } else {
9765 for (i = 0; i < KVM_NR_DB_REGS; i++)
9766 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9767 }
9768 kvm_update_dr7(vcpu);
9769
9770 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9771 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9772 get_segment_base(vcpu, VCPU_SREG_CS);
9773
9774 /*
9775 * Trigger an rflags update that will inject or remove the trace
9776 * flags.
9777 */
9778 kvm_set_rflags(vcpu, rflags);
9779
9780 kvm_x86_ops.update_exception_bitmap(vcpu);
9781
9782 r = 0;
9783
9784 out:
9785 vcpu_put(vcpu);
9786 return r;
9787 }
9788
9789 /*
9790 * Translate a guest virtual address to a guest physical address.
9791 */
9792 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9793 struct kvm_translation *tr)
9794 {
9795 unsigned long vaddr = tr->linear_address;
9796 gpa_t gpa;
9797 int idx;
9798
9799 vcpu_load(vcpu);
9800
9801 idx = srcu_read_lock(&vcpu->kvm->srcu);
9802 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9803 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9804 tr->physical_address = gpa;
9805 tr->valid = gpa != UNMAPPED_GVA;
9806 tr->writeable = 1;
9807 tr->usermode = 0;
9808
9809 vcpu_put(vcpu);
9810 return 0;
9811 }
9812
9813 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9814 {
9815 struct fxregs_state *fxsave;
9816
9817 if (!vcpu->arch.guest_fpu)
9818 return 0;
9819
9820 vcpu_load(vcpu);
9821
9822 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9823 memcpy(fpu->fpr, fxsave->st_space, 128);
9824 fpu->fcw = fxsave->cwd;
9825 fpu->fsw = fxsave->swd;
9826 fpu->ftwx = fxsave->twd;
9827 fpu->last_opcode = fxsave->fop;
9828 fpu->last_ip = fxsave->rip;
9829 fpu->last_dp = fxsave->rdp;
9830 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9831
9832 vcpu_put(vcpu);
9833 return 0;
9834 }
9835
9836 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9837 {
9838 struct fxregs_state *fxsave;
9839
9840 if (!vcpu->arch.guest_fpu)
9841 return 0;
9842
9843 vcpu_load(vcpu);
9844
9845 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9846
9847 memcpy(fxsave->st_space, fpu->fpr, 128);
9848 fxsave->cwd = fpu->fcw;
9849 fxsave->swd = fpu->fsw;
9850 fxsave->twd = fpu->ftwx;
9851 fxsave->fop = fpu->last_opcode;
9852 fxsave->rip = fpu->last_ip;
9853 fxsave->rdp = fpu->last_dp;
9854 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9855
9856 vcpu_put(vcpu);
9857 return 0;
9858 }
9859
9860 static void store_regs(struct kvm_vcpu *vcpu)
9861 {
9862 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9863
9864 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9865 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9866
9867 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9868 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9869
9870 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9871 kvm_vcpu_ioctl_x86_get_vcpu_events(
9872 vcpu, &vcpu->run->s.regs.events);
9873 }
9874
9875 static int sync_regs(struct kvm_vcpu *vcpu)
9876 {
9877 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9878 return -EINVAL;
9879
9880 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9881 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9882 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9883 }
9884 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9885 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9886 return -EINVAL;
9887 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9888 }
9889 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9890 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9891 vcpu, &vcpu->run->s.regs.events))
9892 return -EINVAL;
9893 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9894 }
9895
9896 return 0;
9897 }
9898
9899 static void fx_init(struct kvm_vcpu *vcpu)
9900 {
9901 if (!vcpu->arch.guest_fpu)
9902 return;
9903
9904 fpstate_init(&vcpu->arch.guest_fpu->state);
9905 if (boot_cpu_has(X86_FEATURE_XSAVES))
9906 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9907 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9908
9909 /*
9910 * Ensure guest xcr0 is valid for loading
9911 */
9912 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9913
9914 vcpu->arch.cr0 |= X86_CR0_ET;
9915 }
9916
9917 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu)
9918 {
9919 if (vcpu->arch.guest_fpu) {
9920 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9921 vcpu->arch.guest_fpu = NULL;
9922 }
9923 }
9924 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu);
9925
9926 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9927 {
9928 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9929 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9930 "guest TSC will not be reliable\n");
9931
9932 return 0;
9933 }
9934
9935 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9936 {
9937 struct page *page;
9938 int r;
9939
9940 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9941 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9942 else
9943 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9944
9945 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9946
9947 r = kvm_mmu_create(vcpu);
9948 if (r < 0)
9949 return r;
9950
9951 if (irqchip_in_kernel(vcpu->kvm)) {
9952 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9953 if (r < 0)
9954 goto fail_mmu_destroy;
9955 if (kvm_apicv_activated(vcpu->kvm))
9956 vcpu->arch.apicv_active = true;
9957 } else
9958 static_key_slow_inc(&kvm_no_apic_vcpu);
9959
9960 r = -ENOMEM;
9961
9962 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
9963 if (!page)
9964 goto fail_free_lapic;
9965 vcpu->arch.pio_data = page_address(page);
9966
9967 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9968 GFP_KERNEL_ACCOUNT);
9969 if (!vcpu->arch.mce_banks)
9970 goto fail_free_pio_data;
9971 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9972
9973 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9974 GFP_KERNEL_ACCOUNT))
9975 goto fail_free_mce_banks;
9976
9977 if (!alloc_emulate_ctxt(vcpu))
9978 goto free_wbinvd_dirty_mask;
9979
9980 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9981 GFP_KERNEL_ACCOUNT);
9982 if (!vcpu->arch.user_fpu) {
9983 pr_err("kvm: failed to allocate userspace's fpu\n");
9984 goto free_emulate_ctxt;
9985 }
9986
9987 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9988 GFP_KERNEL_ACCOUNT);
9989 if (!vcpu->arch.guest_fpu) {
9990 pr_err("kvm: failed to allocate vcpu's fpu\n");
9991 goto free_user_fpu;
9992 }
9993 fx_init(vcpu);
9994
9995 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9996
9997 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9998
9999 kvm_async_pf_hash_reset(vcpu);
10000 kvm_pmu_init(vcpu);
10001
10002 vcpu->arch.pending_external_vector = -1;
10003 vcpu->arch.preempted_in_kernel = false;
10004
10005 kvm_hv_vcpu_init(vcpu);
10006
10007 r = kvm_x86_ops.vcpu_create(vcpu);
10008 if (r)
10009 goto free_guest_fpu;
10010
10011 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
10012 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
10013 kvm_vcpu_mtrr_init(vcpu);
10014 vcpu_load(vcpu);
10015 kvm_vcpu_reset(vcpu, false);
10016 kvm_init_mmu(vcpu, false);
10017 vcpu_put(vcpu);
10018 return 0;
10019
10020 free_guest_fpu:
10021 kvm_free_guest_fpu(vcpu);
10022 free_user_fpu:
10023 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10024 free_emulate_ctxt:
10025 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10026 free_wbinvd_dirty_mask:
10027 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10028 fail_free_mce_banks:
10029 kfree(vcpu->arch.mce_banks);
10030 fail_free_pio_data:
10031 free_page((unsigned long)vcpu->arch.pio_data);
10032 fail_free_lapic:
10033 kvm_free_lapic(vcpu);
10034 fail_mmu_destroy:
10035 kvm_mmu_destroy(vcpu);
10036 return r;
10037 }
10038
10039 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
10040 {
10041 struct kvm *kvm = vcpu->kvm;
10042
10043 kvm_hv_vcpu_postcreate(vcpu);
10044
10045 if (mutex_lock_killable(&vcpu->mutex))
10046 return;
10047 vcpu_load(vcpu);
10048 kvm_synchronize_tsc(vcpu, 0);
10049 vcpu_put(vcpu);
10050
10051 /* poll control enabled by default */
10052 vcpu->arch.msr_kvm_poll_control = 1;
10053
10054 mutex_unlock(&vcpu->mutex);
10055
10056 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
10057 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
10058 KVMCLOCK_SYNC_PERIOD);
10059 }
10060
10061 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
10062 {
10063 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
10064 int idx;
10065
10066 kvm_release_pfn(cache->pfn, cache->dirty, cache);
10067
10068 kvmclock_reset(vcpu);
10069
10070 kvm_x86_ops.vcpu_free(vcpu);
10071
10072 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10073 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10074 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10075 kvm_free_guest_fpu(vcpu);
10076
10077 kvm_hv_vcpu_uninit(vcpu);
10078 kvm_pmu_destroy(vcpu);
10079 kfree(vcpu->arch.mce_banks);
10080 kvm_free_lapic(vcpu);
10081 idx = srcu_read_lock(&vcpu->kvm->srcu);
10082 kvm_mmu_destroy(vcpu);
10083 srcu_read_unlock(&vcpu->kvm->srcu, idx);
10084 free_page((unsigned long)vcpu->arch.pio_data);
10085 kvfree(vcpu->arch.cpuid_entries);
10086 if (!lapic_in_kernel(vcpu))
10087 static_key_slow_dec(&kvm_no_apic_vcpu);
10088 }
10089
10090 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
10091 {
10092 kvm_lapic_reset(vcpu, init_event);
10093
10094 vcpu->arch.hflags = 0;
10095
10096 vcpu->arch.smi_pending = 0;
10097 vcpu->arch.smi_count = 0;
10098 atomic_set(&vcpu->arch.nmi_queued, 0);
10099 vcpu->arch.nmi_pending = 0;
10100 vcpu->arch.nmi_injected = false;
10101 kvm_clear_interrupt_queue(vcpu);
10102 kvm_clear_exception_queue(vcpu);
10103
10104 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
10105 kvm_update_dr0123(vcpu);
10106 vcpu->arch.dr6 = DR6_INIT;
10107 vcpu->arch.dr7 = DR7_FIXED_1;
10108 kvm_update_dr7(vcpu);
10109
10110 vcpu->arch.cr2 = 0;
10111
10112 kvm_make_request(KVM_REQ_EVENT, vcpu);
10113 vcpu->arch.apf.msr_en_val = 0;
10114 vcpu->arch.apf.msr_int_val = 0;
10115 vcpu->arch.st.msr_val = 0;
10116
10117 kvmclock_reset(vcpu);
10118
10119 kvm_clear_async_pf_completion_queue(vcpu);
10120 kvm_async_pf_hash_reset(vcpu);
10121 vcpu->arch.apf.halted = false;
10122
10123 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) {
10124 void *mpx_state_buffer;
10125
10126 /*
10127 * To avoid have the INIT path from kvm_apic_has_events() that be
10128 * called with loaded FPU and does not let userspace fix the state.
10129 */
10130 if (init_event)
10131 kvm_put_guest_fpu(vcpu);
10132 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10133 XFEATURE_BNDREGS);
10134 if (mpx_state_buffer)
10135 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
10136 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10137 XFEATURE_BNDCSR);
10138 if (mpx_state_buffer)
10139 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
10140 if (init_event)
10141 kvm_load_guest_fpu(vcpu);
10142 }
10143
10144 if (!init_event) {
10145 kvm_pmu_reset(vcpu);
10146 vcpu->arch.smbase = 0x30000;
10147
10148 vcpu->arch.msr_misc_features_enables = 0;
10149
10150 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
10151 }
10152
10153 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
10154 vcpu->arch.regs_avail = ~0;
10155 vcpu->arch.regs_dirty = ~0;
10156
10157 vcpu->arch.ia32_xss = 0;
10158
10159 kvm_x86_ops.vcpu_reset(vcpu, init_event);
10160 }
10161
10162 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
10163 {
10164 struct kvm_segment cs;
10165
10166 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
10167 cs.selector = vector << 8;
10168 cs.base = vector << 12;
10169 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10170 kvm_rip_write(vcpu, 0);
10171 }
10172 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
10173
10174 int kvm_arch_hardware_enable(void)
10175 {
10176 struct kvm *kvm;
10177 struct kvm_vcpu *vcpu;
10178 int i;
10179 int ret;
10180 u64 local_tsc;
10181 u64 max_tsc = 0;
10182 bool stable, backwards_tsc = false;
10183
10184 kvm_user_return_msr_cpu_online();
10185 ret = kvm_x86_ops.hardware_enable();
10186 if (ret != 0)
10187 return ret;
10188
10189 local_tsc = rdtsc();
10190 stable = !kvm_check_tsc_unstable();
10191 list_for_each_entry(kvm, &vm_list, vm_list) {
10192 kvm_for_each_vcpu(i, vcpu, kvm) {
10193 if (!stable && vcpu->cpu == smp_processor_id())
10194 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10195 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10196 backwards_tsc = true;
10197 if (vcpu->arch.last_host_tsc > max_tsc)
10198 max_tsc = vcpu->arch.last_host_tsc;
10199 }
10200 }
10201 }
10202
10203 /*
10204 * Sometimes, even reliable TSCs go backwards. This happens on
10205 * platforms that reset TSC during suspend or hibernate actions, but
10206 * maintain synchronization. We must compensate. Fortunately, we can
10207 * detect that condition here, which happens early in CPU bringup,
10208 * before any KVM threads can be running. Unfortunately, we can't
10209 * bring the TSCs fully up to date with real time, as we aren't yet far
10210 * enough into CPU bringup that we know how much real time has actually
10211 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10212 * variables that haven't been updated yet.
10213 *
10214 * So we simply find the maximum observed TSC above, then record the
10215 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
10216 * the adjustment will be applied. Note that we accumulate
10217 * adjustments, in case multiple suspend cycles happen before some VCPU
10218 * gets a chance to run again. In the event that no KVM threads get a
10219 * chance to run, we will miss the entire elapsed period, as we'll have
10220 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10221 * loose cycle time. This isn't too big a deal, since the loss will be
10222 * uniform across all VCPUs (not to mention the scenario is extremely
10223 * unlikely). It is possible that a second hibernate recovery happens
10224 * much faster than a first, causing the observed TSC here to be
10225 * smaller; this would require additional padding adjustment, which is
10226 * why we set last_host_tsc to the local tsc observed here.
10227 *
10228 * N.B. - this code below runs only on platforms with reliable TSC,
10229 * as that is the only way backwards_tsc is set above. Also note
10230 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10231 * have the same delta_cyc adjustment applied if backwards_tsc
10232 * is detected. Note further, this adjustment is only done once,
10233 * as we reset last_host_tsc on all VCPUs to stop this from being
10234 * called multiple times (one for each physical CPU bringup).
10235 *
10236 * Platforms with unreliable TSCs don't have to deal with this, they
10237 * will be compensated by the logic in vcpu_load, which sets the TSC to
10238 * catchup mode. This will catchup all VCPUs to real time, but cannot
10239 * guarantee that they stay in perfect synchronization.
10240 */
10241 if (backwards_tsc) {
10242 u64 delta_cyc = max_tsc - local_tsc;
10243 list_for_each_entry(kvm, &vm_list, vm_list) {
10244 kvm->arch.backwards_tsc_observed = true;
10245 kvm_for_each_vcpu(i, vcpu, kvm) {
10246 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10247 vcpu->arch.last_host_tsc = local_tsc;
10248 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10249 }
10250
10251 /*
10252 * We have to disable TSC offset matching.. if you were
10253 * booting a VM while issuing an S4 host suspend....
10254 * you may have some problem. Solving this issue is
10255 * left as an exercise to the reader.
10256 */
10257 kvm->arch.last_tsc_nsec = 0;
10258 kvm->arch.last_tsc_write = 0;
10259 }
10260
10261 }
10262 return 0;
10263 }
10264
10265 void kvm_arch_hardware_disable(void)
10266 {
10267 kvm_x86_ops.hardware_disable();
10268 drop_user_return_notifiers();
10269 }
10270
10271 int kvm_arch_hardware_setup(void *opaque)
10272 {
10273 struct kvm_x86_init_ops *ops = opaque;
10274 int r;
10275
10276 rdmsrl_safe(MSR_EFER, &host_efer);
10277
10278 if (boot_cpu_has(X86_FEATURE_XSAVES))
10279 rdmsrl(MSR_IA32_XSS, host_xss);
10280
10281 r = ops->hardware_setup();
10282 if (r != 0)
10283 return r;
10284
10285 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10286
10287 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10288 supported_xss = 0;
10289
10290 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10291 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10292 #undef __kvm_cpu_cap_has
10293
10294 if (kvm_has_tsc_control) {
10295 /*
10296 * Make sure the user can only configure tsc_khz values that
10297 * fit into a signed integer.
10298 * A min value is not calculated because it will always
10299 * be 1 on all machines.
10300 */
10301 u64 max = min(0x7fffffffULL,
10302 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10303 kvm_max_guest_tsc_khz = max;
10304
10305 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10306 }
10307
10308 kvm_init_msr_list();
10309 return 0;
10310 }
10311
10312 void kvm_arch_hardware_unsetup(void)
10313 {
10314 kvm_x86_ops.hardware_unsetup();
10315 }
10316
10317 int kvm_arch_check_processor_compat(void *opaque)
10318 {
10319 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10320 struct kvm_x86_init_ops *ops = opaque;
10321
10322 WARN_ON(!irqs_disabled());
10323
10324 if (__cr4_reserved_bits(cpu_has, c) !=
10325 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10326 return -EIO;
10327
10328 return ops->check_processor_compatibility();
10329 }
10330
10331 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10332 {
10333 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10334 }
10335 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10336
10337 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10338 {
10339 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10340 }
10341
10342 struct static_key kvm_no_apic_vcpu __read_mostly;
10343 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
10344
10345 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10346 {
10347 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10348
10349 vcpu->arch.l1tf_flush_l1d = true;
10350 if (pmu->version && unlikely(pmu->event_count)) {
10351 pmu->need_cleanup = true;
10352 kvm_make_request(KVM_REQ_PMU, vcpu);
10353 }
10354 kvm_x86_ops.sched_in(vcpu, cpu);
10355 }
10356
10357 void kvm_arch_free_vm(struct kvm *kvm)
10358 {
10359 kfree(kvm->arch.hyperv.hv_pa_pg);
10360 vfree(kvm);
10361 }
10362
10363
10364 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10365 {
10366 if (type)
10367 return -EINVAL;
10368
10369 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10370 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10371 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10372 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10373 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10374 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10375
10376 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10377 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10378 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10379 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10380 &kvm->arch.irq_sources_bitmap);
10381
10382 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10383 mutex_init(&kvm->arch.apic_map_lock);
10384 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10385
10386 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10387 pvclock_update_vm_gtod_copy(kvm);
10388
10389 kvm->arch.guest_can_read_msr_platform_info = true;
10390
10391 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10392 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10393
10394 kvm_hv_init_vm(kvm);
10395 kvm_page_track_init(kvm);
10396 kvm_mmu_init_vm(kvm);
10397
10398 return kvm_x86_ops.vm_init(kvm);
10399 }
10400
10401 int kvm_arch_post_init_vm(struct kvm *kvm)
10402 {
10403 return kvm_mmu_post_init_vm(kvm);
10404 }
10405
10406 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10407 {
10408 vcpu_load(vcpu);
10409 kvm_mmu_unload(vcpu);
10410 vcpu_put(vcpu);
10411 }
10412
10413 static void kvm_free_vcpus(struct kvm *kvm)
10414 {
10415 unsigned int i;
10416 struct kvm_vcpu *vcpu;
10417
10418 /*
10419 * Unpin any mmu pages first.
10420 */
10421 kvm_for_each_vcpu(i, vcpu, kvm) {
10422 kvm_clear_async_pf_completion_queue(vcpu);
10423 kvm_unload_vcpu_mmu(vcpu);
10424 }
10425 kvm_for_each_vcpu(i, vcpu, kvm)
10426 kvm_vcpu_destroy(vcpu);
10427
10428 mutex_lock(&kvm->lock);
10429 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10430 kvm->vcpus[i] = NULL;
10431
10432 atomic_set(&kvm->online_vcpus, 0);
10433 mutex_unlock(&kvm->lock);
10434 }
10435
10436 void kvm_arch_sync_events(struct kvm *kvm)
10437 {
10438 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10439 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10440 kvm_free_pit(kvm);
10441 }
10442
10443 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
10444
10445 /**
10446 * __x86_set_memory_region: Setup KVM internal memory slot
10447 *
10448 * @kvm: the kvm pointer to the VM.
10449 * @id: the slot ID to setup.
10450 * @gpa: the GPA to install the slot (unused when @size == 0).
10451 * @size: the size of the slot. Set to zero to uninstall a slot.
10452 *
10453 * This function helps to setup a KVM internal memory slot. Specify
10454 * @size > 0 to install a new slot, while @size == 0 to uninstall a
10455 * slot. The return code can be one of the following:
10456 *
10457 * HVA: on success (uninstall will return a bogus HVA)
10458 * -errno: on error
10459 *
10460 * The caller should always use IS_ERR() to check the return value
10461 * before use. Note, the KVM internal memory slots are guaranteed to
10462 * remain valid and unchanged until the VM is destroyed, i.e., the
10463 * GPA->HVA translation will not change. However, the HVA is a user
10464 * address, i.e. its accessibility is not guaranteed, and must be
10465 * accessed via __copy_{to,from}_user().
10466 */
10467 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
10468 u32 size)
10469 {
10470 int i, r;
10471 unsigned long hva, old_npages;
10472 struct kvm_memslots *slots = kvm_memslots(kvm);
10473 struct kvm_memory_slot *slot;
10474
10475 /* Called with kvm->slots_lock held. */
10476 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10477 return ERR_PTR_USR(-EINVAL);
10478
10479 slot = id_to_memslot(slots, id);
10480 if (size) {
10481 if (slot && slot->npages)
10482 return ERR_PTR_USR(-EEXIST);
10483
10484 /*
10485 * MAP_SHARED to prevent internal slot pages from being moved
10486 * by fork()/COW.
10487 */
10488 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10489 MAP_SHARED | MAP_ANONYMOUS, 0);
10490 if (IS_ERR((void *)hva))
10491 return (void __user *)hva;
10492 } else {
10493 if (!slot || !slot->npages)
10494 return 0;
10495
10496 old_npages = slot->npages;
10497 hva = slot->userspace_addr;
10498 }
10499
10500 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10501 struct kvm_userspace_memory_region m;
10502
10503 m.slot = id | (i << 16);
10504 m.flags = 0;
10505 m.guest_phys_addr = gpa;
10506 m.userspace_addr = hva;
10507 m.memory_size = size;
10508 r = __kvm_set_memory_region(kvm, &m);
10509 if (r < 0)
10510 return ERR_PTR_USR(r);
10511 }
10512
10513 if (!size)
10514 vm_munmap(hva, old_npages * PAGE_SIZE);
10515
10516 return (void __user *)hva;
10517 }
10518 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10519
10520 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10521 {
10522 kvm_mmu_pre_destroy_vm(kvm);
10523 }
10524
10525 void kvm_arch_destroy_vm(struct kvm *kvm)
10526 {
10527 u32 i;
10528
10529 if (current->mm == kvm->mm) {
10530 /*
10531 * Free memory regions allocated on behalf of userspace,
10532 * unless the the memory map has changed due to process exit
10533 * or fd copying.
10534 */
10535 mutex_lock(&kvm->slots_lock);
10536 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10537 0, 0);
10538 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10539 0, 0);
10540 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10541 mutex_unlock(&kvm->slots_lock);
10542 }
10543 if (kvm_x86_ops.vm_destroy)
10544 kvm_x86_ops.vm_destroy(kvm);
10545 for (i = 0; i < kvm->arch.msr_filter.count; i++)
10546 kfree(kvm->arch.msr_filter.ranges[i].bitmap);
10547 kvm_pic_destroy(kvm);
10548 kvm_ioapic_destroy(kvm);
10549 kvm_free_vcpus(kvm);
10550 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10551 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10552 kvm_mmu_uninit_vm(kvm);
10553 kvm_page_track_cleanup(kvm);
10554 kvm_hv_destroy_vm(kvm);
10555 }
10556
10557 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10558 {
10559 int i;
10560
10561 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10562 kvfree(slot->arch.rmap[i]);
10563 slot->arch.rmap[i] = NULL;
10564
10565 if (i == 0)
10566 continue;
10567
10568 kvfree(slot->arch.lpage_info[i - 1]);
10569 slot->arch.lpage_info[i - 1] = NULL;
10570 }
10571
10572 kvm_page_track_free_memslot(slot);
10573 }
10574
10575 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10576 unsigned long npages)
10577 {
10578 int i;
10579
10580 /*
10581 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10582 * old arrays will be freed by __kvm_set_memory_region() if installing
10583 * the new memslot is successful.
10584 */
10585 memset(&slot->arch, 0, sizeof(slot->arch));
10586
10587 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10588 struct kvm_lpage_info *linfo;
10589 unsigned long ugfn;
10590 int lpages;
10591 int level = i + 1;
10592
10593 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10594 slot->base_gfn, level) + 1;
10595
10596 slot->arch.rmap[i] =
10597 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10598 GFP_KERNEL_ACCOUNT);
10599 if (!slot->arch.rmap[i])
10600 goto out_free;
10601 if (i == 0)
10602 continue;
10603
10604 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10605 if (!linfo)
10606 goto out_free;
10607
10608 slot->arch.lpage_info[i - 1] = linfo;
10609
10610 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10611 linfo[0].disallow_lpage = 1;
10612 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10613 linfo[lpages - 1].disallow_lpage = 1;
10614 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10615 /*
10616 * If the gfn and userspace address are not aligned wrt each
10617 * other, disable large page support for this slot.
10618 */
10619 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10620 unsigned long j;
10621
10622 for (j = 0; j < lpages; ++j)
10623 linfo[j].disallow_lpage = 1;
10624 }
10625 }
10626
10627 if (kvm_page_track_create_memslot(slot, npages))
10628 goto out_free;
10629
10630 return 0;
10631
10632 out_free:
10633 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10634 kvfree(slot->arch.rmap[i]);
10635 slot->arch.rmap[i] = NULL;
10636 if (i == 0)
10637 continue;
10638
10639 kvfree(slot->arch.lpage_info[i - 1]);
10640 slot->arch.lpage_info[i - 1] = NULL;
10641 }
10642 return -ENOMEM;
10643 }
10644
10645 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10646 {
10647 struct kvm_vcpu *vcpu;
10648 int i;
10649
10650 /*
10651 * memslots->generation has been incremented.
10652 * mmio generation may have reached its maximum value.
10653 */
10654 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10655
10656 /* Force re-initialization of steal_time cache */
10657 kvm_for_each_vcpu(i, vcpu, kvm)
10658 kvm_vcpu_kick(vcpu);
10659 }
10660
10661 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10662 struct kvm_memory_slot *memslot,
10663 const struct kvm_userspace_memory_region *mem,
10664 enum kvm_mr_change change)
10665 {
10666 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10667 return kvm_alloc_memslot_metadata(memslot,
10668 mem->memory_size >> PAGE_SHIFT);
10669 return 0;
10670 }
10671
10672 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10673 struct kvm_memory_slot *old,
10674 struct kvm_memory_slot *new,
10675 enum kvm_mr_change change)
10676 {
10677 /*
10678 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10679 * See comments below.
10680 */
10681 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10682 return;
10683
10684 /*
10685 * Dirty logging tracks sptes in 4k granularity, meaning that large
10686 * sptes have to be split. If live migration is successful, the guest
10687 * in the source machine will be destroyed and large sptes will be
10688 * created in the destination. However, if the guest continues to run
10689 * in the source machine (for example if live migration fails), small
10690 * sptes will remain around and cause bad performance.
10691 *
10692 * Scan sptes if dirty logging has been stopped, dropping those
10693 * which can be collapsed into a single large-page spte. Later
10694 * page faults will create the large-page sptes.
10695 *
10696 * There is no need to do this in any of the following cases:
10697 * CREATE: No dirty mappings will already exist.
10698 * MOVE/DELETE: The old mappings will already have been cleaned up by
10699 * kvm_arch_flush_shadow_memslot()
10700 */
10701 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10702 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10703 kvm_mmu_zap_collapsible_sptes(kvm, new);
10704
10705 /*
10706 * Enable or disable dirty logging for the slot.
10707 *
10708 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10709 * slot have been zapped so no dirty logging updates are needed for
10710 * the old slot.
10711 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10712 * any mappings that might be created in it will consume the
10713 * properties of the new slot and do not need to be updated here.
10714 *
10715 * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10716 * called to enable/disable dirty logging.
10717 *
10718 * When disabling dirty logging with PML enabled, the D-bit is set
10719 * for sptes in the slot in order to prevent unnecessary GPA
10720 * logging in the PML buffer (and potential PML buffer full VMEXIT).
10721 * This guarantees leaving PML enabled for the guest's lifetime
10722 * won't have any additional overhead from PML when the guest is
10723 * running with dirty logging disabled.
10724 *
10725 * When enabling dirty logging, large sptes are write-protected
10726 * so they can be split on first write. New large sptes cannot
10727 * be created for this slot until the end of the logging.
10728 * See the comments in fast_page_fault().
10729 * For small sptes, nothing is done if the dirty log is in the
10730 * initial-all-set state. Otherwise, depending on whether pml
10731 * is enabled the D-bit or the W-bit will be cleared.
10732 */
10733 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10734 if (kvm_x86_ops.slot_enable_log_dirty) {
10735 kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10736 } else {
10737 int level =
10738 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10739 PG_LEVEL_2M : PG_LEVEL_4K;
10740
10741 /*
10742 * If we're with initial-all-set, we don't need
10743 * to write protect any small page because
10744 * they're reported as dirty already. However
10745 * we still need to write-protect huge pages
10746 * so that the page split can happen lazily on
10747 * the first write to the huge page.
10748 */
10749 kvm_mmu_slot_remove_write_access(kvm, new, level);
10750 }
10751 } else {
10752 if (kvm_x86_ops.slot_disable_log_dirty)
10753 kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10754 }
10755 }
10756
10757 void kvm_arch_commit_memory_region(struct kvm *kvm,
10758 const struct kvm_userspace_memory_region *mem,
10759 struct kvm_memory_slot *old,
10760 const struct kvm_memory_slot *new,
10761 enum kvm_mr_change change)
10762 {
10763 if (!kvm->arch.n_requested_mmu_pages)
10764 kvm_mmu_change_mmu_pages(kvm,
10765 kvm_mmu_calculate_default_mmu_pages(kvm));
10766
10767 /*
10768 * FIXME: const-ify all uses of struct kvm_memory_slot.
10769 */
10770 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10771
10772 /* Free the arrays associated with the old memslot. */
10773 if (change == KVM_MR_MOVE)
10774 kvm_arch_free_memslot(kvm, old);
10775 }
10776
10777 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10778 {
10779 kvm_mmu_zap_all(kvm);
10780 }
10781
10782 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10783 struct kvm_memory_slot *slot)
10784 {
10785 kvm_page_track_flush_slot(kvm, slot);
10786 }
10787
10788 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10789 {
10790 return (is_guest_mode(vcpu) &&
10791 kvm_x86_ops.guest_apic_has_interrupt &&
10792 kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10793 }
10794
10795 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10796 {
10797 if (!list_empty_careful(&vcpu->async_pf.done))
10798 return true;
10799
10800 if (kvm_apic_has_events(vcpu))
10801 return true;
10802
10803 if (vcpu->arch.pv.pv_unhalted)
10804 return true;
10805
10806 if (vcpu->arch.exception.pending)
10807 return true;
10808
10809 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10810 (vcpu->arch.nmi_pending &&
10811 kvm_x86_ops.nmi_allowed(vcpu, false)))
10812 return true;
10813
10814 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10815 (vcpu->arch.smi_pending &&
10816 kvm_x86_ops.smi_allowed(vcpu, false)))
10817 return true;
10818
10819 if (kvm_arch_interrupt_allowed(vcpu) &&
10820 (kvm_cpu_has_interrupt(vcpu) ||
10821 kvm_guest_apic_has_interrupt(vcpu)))
10822 return true;
10823
10824 if (kvm_hv_has_stimer_pending(vcpu))
10825 return true;
10826
10827 if (is_guest_mode(vcpu) &&
10828 kvm_x86_ops.nested_ops->hv_timer_pending &&
10829 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10830 return true;
10831
10832 return false;
10833 }
10834
10835 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10836 {
10837 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10838 }
10839
10840 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10841 {
10842 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10843 return true;
10844
10845 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10846 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10847 kvm_test_request(KVM_REQ_EVENT, vcpu))
10848 return true;
10849
10850 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10851 return true;
10852
10853 return false;
10854 }
10855
10856 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10857 {
10858 return vcpu->arch.preempted_in_kernel;
10859 }
10860
10861 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10862 {
10863 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10864 }
10865
10866 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10867 {
10868 return kvm_x86_ops.interrupt_allowed(vcpu, false);
10869 }
10870
10871 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10872 {
10873 /* Can't read the RIP when guest state is protected, just return 0 */
10874 if (vcpu->arch.guest_state_protected)
10875 return 0;
10876
10877 if (is_64_bit_mode(vcpu))
10878 return kvm_rip_read(vcpu);
10879 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10880 kvm_rip_read(vcpu));
10881 }
10882 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10883
10884 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10885 {
10886 return kvm_get_linear_rip(vcpu) == linear_rip;
10887 }
10888 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10889
10890 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10891 {
10892 unsigned long rflags;
10893
10894 rflags = kvm_x86_ops.get_rflags(vcpu);
10895 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10896 rflags &= ~X86_EFLAGS_TF;
10897 return rflags;
10898 }
10899 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10900
10901 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10902 {
10903 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10904 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10905 rflags |= X86_EFLAGS_TF;
10906 kvm_x86_ops.set_rflags(vcpu, rflags);
10907 }
10908
10909 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10910 {
10911 __kvm_set_rflags(vcpu, rflags);
10912 kvm_make_request(KVM_REQ_EVENT, vcpu);
10913 }
10914 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10915
10916 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10917 {
10918 int r;
10919
10920 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10921 work->wakeup_all)
10922 return;
10923
10924 r = kvm_mmu_reload(vcpu);
10925 if (unlikely(r))
10926 return;
10927
10928 if (!vcpu->arch.mmu->direct_map &&
10929 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10930 return;
10931
10932 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10933 }
10934
10935 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10936 {
10937 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10938
10939 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10940 }
10941
10942 static inline u32 kvm_async_pf_next_probe(u32 key)
10943 {
10944 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10945 }
10946
10947 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10948 {
10949 u32 key = kvm_async_pf_hash_fn(gfn);
10950
10951 while (vcpu->arch.apf.gfns[key] != ~0)
10952 key = kvm_async_pf_next_probe(key);
10953
10954 vcpu->arch.apf.gfns[key] = gfn;
10955 }
10956
10957 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10958 {
10959 int i;
10960 u32 key = kvm_async_pf_hash_fn(gfn);
10961
10962 for (i = 0; i < ASYNC_PF_PER_VCPU &&
10963 (vcpu->arch.apf.gfns[key] != gfn &&
10964 vcpu->arch.apf.gfns[key] != ~0); i++)
10965 key = kvm_async_pf_next_probe(key);
10966
10967 return key;
10968 }
10969
10970 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10971 {
10972 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10973 }
10974
10975 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10976 {
10977 u32 i, j, k;
10978
10979 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10980
10981 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10982 return;
10983
10984 while (true) {
10985 vcpu->arch.apf.gfns[i] = ~0;
10986 do {
10987 j = kvm_async_pf_next_probe(j);
10988 if (vcpu->arch.apf.gfns[j] == ~0)
10989 return;
10990 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10991 /*
10992 * k lies cyclically in ]i,j]
10993 * | i.k.j |
10994 * |....j i.k.| or |.k..j i...|
10995 */
10996 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10997 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10998 i = j;
10999 }
11000 }
11001
11002 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
11003 {
11004 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
11005
11006 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
11007 sizeof(reason));
11008 }
11009
11010 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
11011 {
11012 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11013
11014 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11015 &token, offset, sizeof(token));
11016 }
11017
11018 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
11019 {
11020 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11021 u32 val;
11022
11023 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11024 &val, offset, sizeof(val)))
11025 return false;
11026
11027 return !val;
11028 }
11029
11030 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
11031 {
11032 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
11033 return false;
11034
11035 if (!kvm_pv_async_pf_enabled(vcpu) ||
11036 (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
11037 return false;
11038
11039 return true;
11040 }
11041
11042 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
11043 {
11044 if (unlikely(!lapic_in_kernel(vcpu) ||
11045 kvm_event_needs_reinjection(vcpu) ||
11046 vcpu->arch.exception.pending))
11047 return false;
11048
11049 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
11050 return false;
11051
11052 /*
11053 * If interrupts are off we cannot even use an artificial
11054 * halt state.
11055 */
11056 return kvm_arch_interrupt_allowed(vcpu);
11057 }
11058
11059 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
11060 struct kvm_async_pf *work)
11061 {
11062 struct x86_exception fault;
11063
11064 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
11065 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
11066
11067 if (kvm_can_deliver_async_pf(vcpu) &&
11068 !apf_put_user_notpresent(vcpu)) {
11069 fault.vector = PF_VECTOR;
11070 fault.error_code_valid = true;
11071 fault.error_code = 0;
11072 fault.nested_page_fault = false;
11073 fault.address = work->arch.token;
11074 fault.async_page_fault = true;
11075 kvm_inject_page_fault(vcpu, &fault);
11076 return true;
11077 } else {
11078 /*
11079 * It is not possible to deliver a paravirtualized asynchronous
11080 * page fault, but putting the guest in an artificial halt state
11081 * can be beneficial nevertheless: if an interrupt arrives, we
11082 * can deliver it timely and perhaps the guest will schedule
11083 * another process. When the instruction that triggered a page
11084 * fault is retried, hopefully the page will be ready in the host.
11085 */
11086 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
11087 return false;
11088 }
11089 }
11090
11091 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
11092 struct kvm_async_pf *work)
11093 {
11094 struct kvm_lapic_irq irq = {
11095 .delivery_mode = APIC_DM_FIXED,
11096 .vector = vcpu->arch.apf.vec
11097 };
11098
11099 if (work->wakeup_all)
11100 work->arch.token = ~0; /* broadcast wakeup */
11101 else
11102 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
11103 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
11104
11105 if ((work->wakeup_all || work->notpresent_injected) &&
11106 kvm_pv_async_pf_enabled(vcpu) &&
11107 !apf_put_user_ready(vcpu, work->arch.token)) {
11108 vcpu->arch.apf.pageready_pending = true;
11109 kvm_apic_set_irq(vcpu, &irq, NULL);
11110 }
11111
11112 vcpu->arch.apf.halted = false;
11113 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11114 }
11115
11116 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
11117 {
11118 kvm_make_request(KVM_REQ_APF_READY, vcpu);
11119 if (!vcpu->arch.apf.pageready_pending)
11120 kvm_vcpu_kick(vcpu);
11121 }
11122
11123 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
11124 {
11125 if (!kvm_pv_async_pf_enabled(vcpu))
11126 return true;
11127 else
11128 return apf_pageready_slot_free(vcpu);
11129 }
11130
11131 void kvm_arch_start_assignment(struct kvm *kvm)
11132 {
11133 atomic_inc(&kvm->arch.assigned_device_count);
11134 }
11135 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
11136
11137 void kvm_arch_end_assignment(struct kvm *kvm)
11138 {
11139 atomic_dec(&kvm->arch.assigned_device_count);
11140 }
11141 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
11142
11143 bool kvm_arch_has_assigned_device(struct kvm *kvm)
11144 {
11145 return atomic_read(&kvm->arch.assigned_device_count);
11146 }
11147 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
11148
11149 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
11150 {
11151 atomic_inc(&kvm->arch.noncoherent_dma_count);
11152 }
11153 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
11154
11155 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
11156 {
11157 atomic_dec(&kvm->arch.noncoherent_dma_count);
11158 }
11159 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
11160
11161 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
11162 {
11163 return atomic_read(&kvm->arch.noncoherent_dma_count);
11164 }
11165 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
11166
11167 bool kvm_arch_has_irq_bypass(void)
11168 {
11169 return true;
11170 }
11171
11172 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
11173 struct irq_bypass_producer *prod)
11174 {
11175 struct kvm_kernel_irqfd *irqfd =
11176 container_of(cons, struct kvm_kernel_irqfd, consumer);
11177 int ret;
11178
11179 irqfd->producer = prod;
11180 kvm_arch_start_assignment(irqfd->kvm);
11181 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
11182 prod->irq, irqfd->gsi, 1);
11183
11184 if (ret)
11185 kvm_arch_end_assignment(irqfd->kvm);
11186
11187 return ret;
11188 }
11189
11190 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
11191 struct irq_bypass_producer *prod)
11192 {
11193 int ret;
11194 struct kvm_kernel_irqfd *irqfd =
11195 container_of(cons, struct kvm_kernel_irqfd, consumer);
11196
11197 WARN_ON(irqfd->producer != prod);
11198 irqfd->producer = NULL;
11199
11200 /*
11201 * When producer of consumer is unregistered, we change back to
11202 * remapped mode, so we can re-use the current implementation
11203 * when the irq is masked/disabled or the consumer side (KVM
11204 * int this case doesn't want to receive the interrupts.
11205 */
11206 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
11207 if (ret)
11208 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
11209 " fails: %d\n", irqfd->consumer.token, ret);
11210
11211 kvm_arch_end_assignment(irqfd->kvm);
11212 }
11213
11214 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
11215 uint32_t guest_irq, bool set)
11216 {
11217 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
11218 }
11219
11220 bool kvm_vector_hashing_enabled(void)
11221 {
11222 return vector_hashing;
11223 }
11224
11225 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11226 {
11227 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11228 }
11229 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11230
11231
11232 int kvm_spec_ctrl_test_value(u64 value)
11233 {
11234 /*
11235 * test that setting IA32_SPEC_CTRL to given value
11236 * is allowed by the host processor
11237 */
11238
11239 u64 saved_value;
11240 unsigned long flags;
11241 int ret = 0;
11242
11243 local_irq_save(flags);
11244
11245 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11246 ret = 1;
11247 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11248 ret = 1;
11249 else
11250 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11251
11252 local_irq_restore(flags);
11253
11254 return ret;
11255 }
11256 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11257
11258 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11259 {
11260 struct x86_exception fault;
11261 u32 access = error_code &
11262 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11263
11264 if (!(error_code & PFERR_PRESENT_MASK) ||
11265 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11266 /*
11267 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11268 * tables probably do not match the TLB. Just proceed
11269 * with the error code that the processor gave.
11270 */
11271 fault.vector = PF_VECTOR;
11272 fault.error_code_valid = true;
11273 fault.error_code = error_code;
11274 fault.nested_page_fault = false;
11275 fault.address = gva;
11276 }
11277 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11278 }
11279 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11280
11281 /*
11282 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11283 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11284 * indicates whether exit to userspace is needed.
11285 */
11286 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11287 struct x86_exception *e)
11288 {
11289 if (r == X86EMUL_PROPAGATE_FAULT) {
11290 kvm_inject_emulated_page_fault(vcpu, e);
11291 return 1;
11292 }
11293
11294 /*
11295 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11296 * while handling a VMX instruction KVM could've handled the request
11297 * correctly by exiting to userspace and performing I/O but there
11298 * doesn't seem to be a real use-case behind such requests, just return
11299 * KVM_EXIT_INTERNAL_ERROR for now.
11300 */
11301 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11302 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11303 vcpu->run->internal.ndata = 0;
11304
11305 return 0;
11306 }
11307 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11308
11309 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11310 {
11311 bool pcid_enabled;
11312 struct x86_exception e;
11313 unsigned i;
11314 unsigned long roots_to_free = 0;
11315 struct {
11316 u64 pcid;
11317 u64 gla;
11318 } operand;
11319 int r;
11320
11321 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11322 if (r != X86EMUL_CONTINUE)
11323 return kvm_handle_memory_failure(vcpu, r, &e);
11324
11325 if (operand.pcid >> 12 != 0) {
11326 kvm_inject_gp(vcpu, 0);
11327 return 1;
11328 }
11329
11330 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11331
11332 switch (type) {
11333 case INVPCID_TYPE_INDIV_ADDR:
11334 if ((!pcid_enabled && (operand.pcid != 0)) ||
11335 is_noncanonical_address(operand.gla, vcpu)) {
11336 kvm_inject_gp(vcpu, 0);
11337 return 1;
11338 }
11339 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11340 return kvm_skip_emulated_instruction(vcpu);
11341
11342 case INVPCID_TYPE_SINGLE_CTXT:
11343 if (!pcid_enabled && (operand.pcid != 0)) {
11344 kvm_inject_gp(vcpu, 0);
11345 return 1;
11346 }
11347
11348 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11349 kvm_mmu_sync_roots(vcpu);
11350 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11351 }
11352
11353 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11354 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11355 == operand.pcid)
11356 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11357
11358 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11359 /*
11360 * If neither the current cr3 nor any of the prev_roots use the
11361 * given PCID, then nothing needs to be done here because a
11362 * resync will happen anyway before switching to any other CR3.
11363 */
11364
11365 return kvm_skip_emulated_instruction(vcpu);
11366
11367 case INVPCID_TYPE_ALL_NON_GLOBAL:
11368 /*
11369 * Currently, KVM doesn't mark global entries in the shadow
11370 * page tables, so a non-global flush just degenerates to a
11371 * global flush. If needed, we could optimize this later by
11372 * keeping track of global entries in shadow page tables.
11373 */
11374
11375 fallthrough;
11376 case INVPCID_TYPE_ALL_INCL_GLOBAL:
11377 kvm_mmu_unload(vcpu);
11378 return kvm_skip_emulated_instruction(vcpu);
11379
11380 default:
11381 BUG(); /* We have already checked above that type <= 3 */
11382 }
11383 }
11384 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11385
11386 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
11387 {
11388 struct kvm_run *run = vcpu->run;
11389 struct kvm_mmio_fragment *frag;
11390 unsigned int len;
11391
11392 BUG_ON(!vcpu->mmio_needed);
11393
11394 /* Complete previous fragment */
11395 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11396 len = min(8u, frag->len);
11397 if (!vcpu->mmio_is_write)
11398 memcpy(frag->data, run->mmio.data, len);
11399
11400 if (frag->len <= 8) {
11401 /* Switch to the next fragment. */
11402 frag++;
11403 vcpu->mmio_cur_fragment++;
11404 } else {
11405 /* Go forward to the next mmio piece. */
11406 frag->data += len;
11407 frag->gpa += len;
11408 frag->len -= len;
11409 }
11410
11411 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11412 vcpu->mmio_needed = 0;
11413
11414 // VMG change, at this point, we're always done
11415 // RIP has already been advanced
11416 return 1;
11417 }
11418
11419 // More MMIO is needed
11420 run->mmio.phys_addr = frag->gpa;
11421 run->mmio.len = min(8u, frag->len);
11422 run->mmio.is_write = vcpu->mmio_is_write;
11423 if (run->mmio.is_write)
11424 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11425 run->exit_reason = KVM_EXIT_MMIO;
11426
11427 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11428
11429 return 0;
11430 }
11431
11432 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11433 void *data)
11434 {
11435 int handled;
11436 struct kvm_mmio_fragment *frag;
11437
11438 if (!data)
11439 return -EINVAL;
11440
11441 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11442 if (handled == bytes)
11443 return 1;
11444
11445 bytes -= handled;
11446 gpa += handled;
11447 data += handled;
11448
11449 /*TODO: Check if need to increment number of frags */
11450 frag = vcpu->mmio_fragments;
11451 vcpu->mmio_nr_fragments = 1;
11452 frag->len = bytes;
11453 frag->gpa = gpa;
11454 frag->data = data;
11455
11456 vcpu->mmio_needed = 1;
11457 vcpu->mmio_cur_fragment = 0;
11458
11459 vcpu->run->mmio.phys_addr = gpa;
11460 vcpu->run->mmio.len = min(8u, frag->len);
11461 vcpu->run->mmio.is_write = 1;
11462 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
11463 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11464
11465 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11466
11467 return 0;
11468 }
11469 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
11470
11471 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11472 void *data)
11473 {
11474 int handled;
11475 struct kvm_mmio_fragment *frag;
11476
11477 if (!data)
11478 return -EINVAL;
11479
11480 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11481 if (handled == bytes)
11482 return 1;
11483
11484 bytes -= handled;
11485 gpa += handled;
11486 data += handled;
11487
11488 /*TODO: Check if need to increment number of frags */
11489 frag = vcpu->mmio_fragments;
11490 vcpu->mmio_nr_fragments = 1;
11491 frag->len = bytes;
11492 frag->gpa = gpa;
11493 frag->data = data;
11494
11495 vcpu->mmio_needed = 1;
11496 vcpu->mmio_cur_fragment = 0;
11497
11498 vcpu->run->mmio.phys_addr = gpa;
11499 vcpu->run->mmio.len = min(8u, frag->len);
11500 vcpu->run->mmio.is_write = 0;
11501 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11502
11503 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11504
11505 return 0;
11506 }
11507 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
11508
11509 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
11510 {
11511 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data,
11512 vcpu->arch.pio.count * vcpu->arch.pio.size);
11513 vcpu->arch.pio.count = 0;
11514
11515 return 1;
11516 }
11517
11518 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
11519 unsigned int port, void *data, unsigned int count)
11520 {
11521 int ret;
11522
11523 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port,
11524 data, count);
11525 if (ret)
11526 return ret;
11527
11528 vcpu->arch.pio.count = 0;
11529
11530 return 0;
11531 }
11532
11533 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
11534 unsigned int port, void *data, unsigned int count)
11535 {
11536 int ret;
11537
11538 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port,
11539 data, count);
11540 if (ret) {
11541 vcpu->arch.pio.count = 0;
11542 } else {
11543 vcpu->arch.guest_ins_data = data;
11544 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
11545 }
11546
11547 return 0;
11548 }
11549
11550 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
11551 unsigned int port, void *data, unsigned int count,
11552 int in)
11553 {
11554 return in ? kvm_sev_es_ins(vcpu, size, port, data, count)
11555 : kvm_sev_es_outs(vcpu, size, port, data, count);
11556 }
11557 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
11558
11559 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
11560 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11561 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11562 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11563 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11564 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11565 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11579 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11580 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11581 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
11582 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
11583 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
11584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
11585 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
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