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Merge remote-tracking branch 'asoc/for-5.11' into asoc-linus
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19 #include <linux/kvm_host.h>
20 #include "irq.h"
21 #include "ioapic.h"
22 #include "mmu.h"
23 #include "i8254.h"
24 #include "tss.h"
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
27 #include "x86.h"
28 #include "cpuid.h"
29 #include "pmu.h"
30 #include "hyperv.h"
31 #include "lapic.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
60
61 #include <trace/events/kvm.h>
62
63 #include <asm/debugreg.h>
64 #include <asm/msr.h>
65 #include <asm/desc.h>
66 #include <asm/mce.h>
67 #include <linux/kernel_stat.h>
68 #include <asm/fpu/internal.h> /* Ugh! */
69 #include <asm/pvclock.h>
70 #include <asm/div64.h>
71 #include <asm/irq_remapping.h>
72 #include <asm/mshyperv.h>
73 #include <asm/hypervisor.h>
74 #include <asm/tlbflush.h>
75 #include <asm/intel_pt.h>
76 #include <asm/emulate_prefix.h>
77 #include <clocksource/hyperv_timer.h>
78
79 #define CREATE_TRACE_POINTS
80 #include "trace.h"
81
82 #define MAX_IO_MSRS 256
83 #define KVM_MAX_MCE_BANKS 32
84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
86
87 #define emul_to_vcpu(ctxt) \
88 ((struct kvm_vcpu *)(ctxt)->vcpu)
89
90 /* EFER defaults:
91 * - enable syscall per default because its emulated by KVM
92 * - enable LME and LMA per default on 64 bit KVM
93 */
94 #ifdef CONFIG_X86_64
95 static
96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
97 #else
98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
99 #endif
100
101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
102
103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
105
106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
107 static void process_nmi(struct kvm_vcpu *vcpu);
108 static void process_smi(struct kvm_vcpu *vcpu);
109 static void enter_smm(struct kvm_vcpu *vcpu);
110 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
111 static void store_regs(struct kvm_vcpu *vcpu);
112 static int sync_regs(struct kvm_vcpu *vcpu);
113
114 struct kvm_x86_ops kvm_x86_ops __read_mostly;
115 EXPORT_SYMBOL_GPL(kvm_x86_ops);
116
117 static bool __read_mostly ignore_msrs = 0;
118 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
119
120 static bool __read_mostly report_ignored_msrs = true;
121 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
122
123 unsigned int min_timer_period_us = 200;
124 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
125
126 static bool __read_mostly kvmclock_periodic_sync = true;
127 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
128
129 bool __read_mostly kvm_has_tsc_control;
130 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
131 u32 __read_mostly kvm_max_guest_tsc_khz;
132 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
133 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
134 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
135 u64 __read_mostly kvm_max_tsc_scaling_ratio;
136 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
137 u64 __read_mostly kvm_default_tsc_scaling_ratio;
138 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
139
140 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
141 static u32 __read_mostly tsc_tolerance_ppm = 250;
142 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
143
144 /*
145 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
146 * adaptive tuning starting from default advancment of 1000ns. '0' disables
147 * advancement entirely. Any other value is used as-is and disables adaptive
148 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
149 */
150 static int __read_mostly lapic_timer_advance_ns = -1;
151 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
152
153 static bool __read_mostly vector_hashing = true;
154 module_param(vector_hashing, bool, S_IRUGO);
155
156 bool __read_mostly enable_vmware_backdoor = false;
157 module_param(enable_vmware_backdoor, bool, S_IRUGO);
158 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
159
160 static bool __read_mostly force_emulation_prefix = false;
161 module_param(force_emulation_prefix, bool, S_IRUGO);
162
163 int __read_mostly pi_inject_timer = -1;
164 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
165
166 /*
167 * Restoring the host value for MSRs that are only consumed when running in
168 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
169 * returns to userspace, i.e. the kernel can run with the guest's value.
170 */
171 #define KVM_MAX_NR_USER_RETURN_MSRS 16
172
173 struct kvm_user_return_msrs_global {
174 int nr;
175 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
176 };
177
178 struct kvm_user_return_msrs {
179 struct user_return_notifier urn;
180 bool registered;
181 struct kvm_user_return_msr_values {
182 u64 host;
183 u64 curr;
184 } values[KVM_MAX_NR_USER_RETURN_MSRS];
185 };
186
187 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
188 static struct kvm_user_return_msrs __percpu *user_return_msrs;
189
190 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
191 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
192 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
193 | XFEATURE_MASK_PKRU)
194
195 u64 __read_mostly host_efer;
196 EXPORT_SYMBOL_GPL(host_efer);
197
198 bool __read_mostly allow_smaller_maxphyaddr = 0;
199 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
200
201 u64 __read_mostly host_xss;
202 EXPORT_SYMBOL_GPL(host_xss);
203 u64 __read_mostly supported_xss;
204 EXPORT_SYMBOL_GPL(supported_xss);
205
206 struct kvm_stats_debugfs_item debugfs_entries[] = {
207 VCPU_STAT("pf_fixed", pf_fixed),
208 VCPU_STAT("pf_guest", pf_guest),
209 VCPU_STAT("tlb_flush", tlb_flush),
210 VCPU_STAT("invlpg", invlpg),
211 VCPU_STAT("exits", exits),
212 VCPU_STAT("io_exits", io_exits),
213 VCPU_STAT("mmio_exits", mmio_exits),
214 VCPU_STAT("signal_exits", signal_exits),
215 VCPU_STAT("irq_window", irq_window_exits),
216 VCPU_STAT("nmi_window", nmi_window_exits),
217 VCPU_STAT("halt_exits", halt_exits),
218 VCPU_STAT("halt_successful_poll", halt_successful_poll),
219 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
220 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
221 VCPU_STAT("halt_wakeup", halt_wakeup),
222 VCPU_STAT("hypercalls", hypercalls),
223 VCPU_STAT("request_irq", request_irq_exits),
224 VCPU_STAT("irq_exits", irq_exits),
225 VCPU_STAT("host_state_reload", host_state_reload),
226 VCPU_STAT("fpu_reload", fpu_reload),
227 VCPU_STAT("insn_emulation", insn_emulation),
228 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
229 VCPU_STAT("irq_injections", irq_injections),
230 VCPU_STAT("nmi_injections", nmi_injections),
231 VCPU_STAT("req_event", req_event),
232 VCPU_STAT("l1d_flush", l1d_flush),
233 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
234 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
235 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
236 VM_STAT("mmu_pte_write", mmu_pte_write),
237 VM_STAT("mmu_pte_updated", mmu_pte_updated),
238 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
239 VM_STAT("mmu_flooded", mmu_flooded),
240 VM_STAT("mmu_recycled", mmu_recycled),
241 VM_STAT("mmu_cache_miss", mmu_cache_miss),
242 VM_STAT("mmu_unsync", mmu_unsync),
243 VM_STAT("remote_tlb_flush", remote_tlb_flush),
244 VM_STAT("largepages", lpages, .mode = 0444),
245 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
246 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
247 { NULL }
248 };
249
250 u64 __read_mostly host_xcr0;
251 u64 __read_mostly supported_xcr0;
252 EXPORT_SYMBOL_GPL(supported_xcr0);
253
254 static struct kmem_cache *x86_fpu_cache;
255
256 static struct kmem_cache *x86_emulator_cache;
257
258 /*
259 * When called, it means the previous get/set msr reached an invalid msr.
260 * Return true if we want to ignore/silent this failed msr access.
261 */
262 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
263 u64 data, bool write)
264 {
265 const char *op = write ? "wrmsr" : "rdmsr";
266
267 if (ignore_msrs) {
268 if (report_ignored_msrs)
269 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
270 op, msr, data);
271 /* Mask the error */
272 return true;
273 } else {
274 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
275 op, msr, data);
276 return false;
277 }
278 }
279
280 static struct kmem_cache *kvm_alloc_emulator_cache(void)
281 {
282 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
283 unsigned int size = sizeof(struct x86_emulate_ctxt);
284
285 return kmem_cache_create_usercopy("x86_emulator", size,
286 __alignof__(struct x86_emulate_ctxt),
287 SLAB_ACCOUNT, useroffset,
288 size - useroffset, NULL);
289 }
290
291 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
292
293 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
294 {
295 int i;
296 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
297 vcpu->arch.apf.gfns[i] = ~0;
298 }
299
300 static void kvm_on_user_return(struct user_return_notifier *urn)
301 {
302 unsigned slot;
303 struct kvm_user_return_msrs *msrs
304 = container_of(urn, struct kvm_user_return_msrs, urn);
305 struct kvm_user_return_msr_values *values;
306 unsigned long flags;
307
308 /*
309 * Disabling irqs at this point since the following code could be
310 * interrupted and executed through kvm_arch_hardware_disable()
311 */
312 local_irq_save(flags);
313 if (msrs->registered) {
314 msrs->registered = false;
315 user_return_notifier_unregister(urn);
316 }
317 local_irq_restore(flags);
318 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
319 values = &msrs->values[slot];
320 if (values->host != values->curr) {
321 wrmsrl(user_return_msrs_global.msrs[slot], values->host);
322 values->curr = values->host;
323 }
324 }
325 }
326
327 void kvm_define_user_return_msr(unsigned slot, u32 msr)
328 {
329 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
330 user_return_msrs_global.msrs[slot] = msr;
331 if (slot >= user_return_msrs_global.nr)
332 user_return_msrs_global.nr = slot + 1;
333 }
334 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
335
336 static void kvm_user_return_msr_cpu_online(void)
337 {
338 unsigned int cpu = smp_processor_id();
339 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
340 u64 value;
341 int i;
342
343 for (i = 0; i < user_return_msrs_global.nr; ++i) {
344 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
345 msrs->values[i].host = value;
346 msrs->values[i].curr = value;
347 }
348 }
349
350 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
351 {
352 unsigned int cpu = smp_processor_id();
353 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
354 int err;
355
356 value = (value & mask) | (msrs->values[slot].host & ~mask);
357 if (value == msrs->values[slot].curr)
358 return 0;
359 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
360 if (err)
361 return 1;
362
363 msrs->values[slot].curr = value;
364 if (!msrs->registered) {
365 msrs->urn.on_user_return = kvm_on_user_return;
366 user_return_notifier_register(&msrs->urn);
367 msrs->registered = true;
368 }
369 return 0;
370 }
371 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
372
373 static void drop_user_return_notifiers(void)
374 {
375 unsigned int cpu = smp_processor_id();
376 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
377
378 if (msrs->registered)
379 kvm_on_user_return(&msrs->urn);
380 }
381
382 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
383 {
384 return vcpu->arch.apic_base;
385 }
386 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
387
388 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
389 {
390 return kvm_apic_mode(kvm_get_apic_base(vcpu));
391 }
392 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
393
394 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
395 {
396 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
397 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
398 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
399 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
400
401 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
402 return 1;
403 if (!msr_info->host_initiated) {
404 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
405 return 1;
406 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
407 return 1;
408 }
409
410 kvm_lapic_set_base(vcpu, msr_info->data);
411 kvm_recalculate_apic_map(vcpu->kvm);
412 return 0;
413 }
414 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
415
416 asmlinkage __visible noinstr void kvm_spurious_fault(void)
417 {
418 /* Fault while not rebooting. We want the trace. */
419 BUG_ON(!kvm_rebooting);
420 }
421 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
422
423 #define EXCPT_BENIGN 0
424 #define EXCPT_CONTRIBUTORY 1
425 #define EXCPT_PF 2
426
427 static int exception_class(int vector)
428 {
429 switch (vector) {
430 case PF_VECTOR:
431 return EXCPT_PF;
432 case DE_VECTOR:
433 case TS_VECTOR:
434 case NP_VECTOR:
435 case SS_VECTOR:
436 case GP_VECTOR:
437 return EXCPT_CONTRIBUTORY;
438 default:
439 break;
440 }
441 return EXCPT_BENIGN;
442 }
443
444 #define EXCPT_FAULT 0
445 #define EXCPT_TRAP 1
446 #define EXCPT_ABORT 2
447 #define EXCPT_INTERRUPT 3
448
449 static int exception_type(int vector)
450 {
451 unsigned int mask;
452
453 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
454 return EXCPT_INTERRUPT;
455
456 mask = 1 << vector;
457
458 /* #DB is trap, as instruction watchpoints are handled elsewhere */
459 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
460 return EXCPT_TRAP;
461
462 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
463 return EXCPT_ABORT;
464
465 /* Reserved exceptions will result in fault */
466 return EXCPT_FAULT;
467 }
468
469 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
470 {
471 unsigned nr = vcpu->arch.exception.nr;
472 bool has_payload = vcpu->arch.exception.has_payload;
473 unsigned long payload = vcpu->arch.exception.payload;
474
475 if (!has_payload)
476 return;
477
478 switch (nr) {
479 case DB_VECTOR:
480 /*
481 * "Certain debug exceptions may clear bit 0-3. The
482 * remaining contents of the DR6 register are never
483 * cleared by the processor".
484 */
485 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
486 /*
487 * DR6.RTM is set by all #DB exceptions that don't clear it.
488 */
489 vcpu->arch.dr6 |= DR6_RTM;
490 vcpu->arch.dr6 |= payload;
491 /*
492 * Bit 16 should be set in the payload whenever the #DB
493 * exception should clear DR6.RTM. This makes the payload
494 * compatible with the pending debug exceptions under VMX.
495 * Though not currently documented in the SDM, this also
496 * makes the payload compatible with the exit qualification
497 * for #DB exceptions under VMX.
498 */
499 vcpu->arch.dr6 ^= payload & DR6_RTM;
500
501 /*
502 * The #DB payload is defined as compatible with the 'pending
503 * debug exceptions' field under VMX, not DR6. While bit 12 is
504 * defined in the 'pending debug exceptions' field (enabled
505 * breakpoint), it is reserved and must be zero in DR6.
506 */
507 vcpu->arch.dr6 &= ~BIT(12);
508 break;
509 case PF_VECTOR:
510 vcpu->arch.cr2 = payload;
511 break;
512 }
513
514 vcpu->arch.exception.has_payload = false;
515 vcpu->arch.exception.payload = 0;
516 }
517 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
518
519 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
520 unsigned nr, bool has_error, u32 error_code,
521 bool has_payload, unsigned long payload, bool reinject)
522 {
523 u32 prev_nr;
524 int class1, class2;
525
526 kvm_make_request(KVM_REQ_EVENT, vcpu);
527
528 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
529 queue:
530 if (has_error && !is_protmode(vcpu))
531 has_error = false;
532 if (reinject) {
533 /*
534 * On vmentry, vcpu->arch.exception.pending is only
535 * true if an event injection was blocked by
536 * nested_run_pending. In that case, however,
537 * vcpu_enter_guest requests an immediate exit,
538 * and the guest shouldn't proceed far enough to
539 * need reinjection.
540 */
541 WARN_ON_ONCE(vcpu->arch.exception.pending);
542 vcpu->arch.exception.injected = true;
543 if (WARN_ON_ONCE(has_payload)) {
544 /*
545 * A reinjected event has already
546 * delivered its payload.
547 */
548 has_payload = false;
549 payload = 0;
550 }
551 } else {
552 vcpu->arch.exception.pending = true;
553 vcpu->arch.exception.injected = false;
554 }
555 vcpu->arch.exception.has_error_code = has_error;
556 vcpu->arch.exception.nr = nr;
557 vcpu->arch.exception.error_code = error_code;
558 vcpu->arch.exception.has_payload = has_payload;
559 vcpu->arch.exception.payload = payload;
560 if (!is_guest_mode(vcpu))
561 kvm_deliver_exception_payload(vcpu);
562 return;
563 }
564
565 /* to check exception */
566 prev_nr = vcpu->arch.exception.nr;
567 if (prev_nr == DF_VECTOR) {
568 /* triple fault -> shutdown */
569 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
570 return;
571 }
572 class1 = exception_class(prev_nr);
573 class2 = exception_class(nr);
574 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
575 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
576 /*
577 * Generate double fault per SDM Table 5-5. Set
578 * exception.pending = true so that the double fault
579 * can trigger a nested vmexit.
580 */
581 vcpu->arch.exception.pending = true;
582 vcpu->arch.exception.injected = false;
583 vcpu->arch.exception.has_error_code = true;
584 vcpu->arch.exception.nr = DF_VECTOR;
585 vcpu->arch.exception.error_code = 0;
586 vcpu->arch.exception.has_payload = false;
587 vcpu->arch.exception.payload = 0;
588 } else
589 /* replace previous exception with a new one in a hope
590 that instruction re-execution will regenerate lost
591 exception */
592 goto queue;
593 }
594
595 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
596 {
597 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
598 }
599 EXPORT_SYMBOL_GPL(kvm_queue_exception);
600
601 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
602 {
603 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
604 }
605 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
606
607 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
608 unsigned long payload)
609 {
610 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
611 }
612 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
613
614 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
615 u32 error_code, unsigned long payload)
616 {
617 kvm_multiple_exception(vcpu, nr, true, error_code,
618 true, payload, false);
619 }
620
621 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
622 {
623 if (err)
624 kvm_inject_gp(vcpu, 0);
625 else
626 return kvm_skip_emulated_instruction(vcpu);
627
628 return 1;
629 }
630 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
631
632 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
633 {
634 ++vcpu->stat.pf_guest;
635 vcpu->arch.exception.nested_apf =
636 is_guest_mode(vcpu) && fault->async_page_fault;
637 if (vcpu->arch.exception.nested_apf) {
638 vcpu->arch.apf.nested_apf_token = fault->address;
639 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
640 } else {
641 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
642 fault->address);
643 }
644 }
645 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
646
647 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
648 struct x86_exception *fault)
649 {
650 struct kvm_mmu *fault_mmu;
651 WARN_ON_ONCE(fault->vector != PF_VECTOR);
652
653 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
654 vcpu->arch.walk_mmu;
655
656 /*
657 * Invalidate the TLB entry for the faulting address, if it exists,
658 * else the access will fault indefinitely (and to emulate hardware).
659 */
660 if ((fault->error_code & PFERR_PRESENT_MASK) &&
661 !(fault->error_code & PFERR_RSVD_MASK))
662 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
663 fault_mmu->root_hpa);
664
665 fault_mmu->inject_page_fault(vcpu, fault);
666 return fault->nested_page_fault;
667 }
668 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
669
670 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
671 {
672 atomic_inc(&vcpu->arch.nmi_queued);
673 kvm_make_request(KVM_REQ_NMI, vcpu);
674 }
675 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
676
677 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
678 {
679 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
680 }
681 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
682
683 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
684 {
685 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
686 }
687 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
688
689 /*
690 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
691 * a #GP and return false.
692 */
693 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
694 {
695 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
696 return true;
697 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
698 return false;
699 }
700 EXPORT_SYMBOL_GPL(kvm_require_cpl);
701
702 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
703 {
704 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return true;
706
707 kvm_queue_exception(vcpu, UD_VECTOR);
708 return false;
709 }
710 EXPORT_SYMBOL_GPL(kvm_require_dr);
711
712 /*
713 * This function will be used to read from the physical memory of the currently
714 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
715 * can read from guest physical or from the guest's guest physical memory.
716 */
717 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
718 gfn_t ngfn, void *data, int offset, int len,
719 u32 access)
720 {
721 struct x86_exception exception;
722 gfn_t real_gfn;
723 gpa_t ngpa;
724
725 ngpa = gfn_to_gpa(ngfn);
726 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
727 if (real_gfn == UNMAPPED_GVA)
728 return -EFAULT;
729
730 real_gfn = gpa_to_gfn(real_gfn);
731
732 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
733 }
734 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
735
736 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
737 void *data, int offset, int len, u32 access)
738 {
739 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
740 data, offset, len, access);
741 }
742
743 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
744 {
745 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
746 rsvd_bits(1, 2);
747 }
748
749 /*
750 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
751 */
752 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
753 {
754 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
755 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
756 int i;
757 int ret;
758 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
759
760 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
761 offset * sizeof(u64), sizeof(pdpte),
762 PFERR_USER_MASK|PFERR_WRITE_MASK);
763 if (ret < 0) {
764 ret = 0;
765 goto out;
766 }
767 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
768 if ((pdpte[i] & PT_PRESENT_MASK) &&
769 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
770 ret = 0;
771 goto out;
772 }
773 }
774 ret = 1;
775
776 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
777 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
778
779 out:
780
781 return ret;
782 }
783 EXPORT_SYMBOL_GPL(load_pdptrs);
784
785 bool pdptrs_changed(struct kvm_vcpu *vcpu)
786 {
787 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
788 int offset;
789 gfn_t gfn;
790 int r;
791
792 if (!is_pae_paging(vcpu))
793 return false;
794
795 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
796 return true;
797
798 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
799 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
800 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
801 PFERR_USER_MASK | PFERR_WRITE_MASK);
802 if (r < 0)
803 return true;
804
805 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
806 }
807 EXPORT_SYMBOL_GPL(pdptrs_changed);
808
809 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
810 {
811 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
812
813 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
814 kvm_clear_async_pf_completion_queue(vcpu);
815 kvm_async_pf_hash_reset(vcpu);
816 }
817
818 if ((cr0 ^ old_cr0) & update_bits)
819 kvm_mmu_reset_context(vcpu);
820
821 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
822 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
823 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
824 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
825 }
826 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
827
828 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
829 {
830 unsigned long old_cr0 = kvm_read_cr0(vcpu);
831 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
832
833 cr0 |= X86_CR0_ET;
834
835 #ifdef CONFIG_X86_64
836 if (cr0 & 0xffffffff00000000UL)
837 return 1;
838 #endif
839
840 cr0 &= ~CR0_RESERVED_BITS;
841
842 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
843 return 1;
844
845 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
846 return 1;
847
848 #ifdef CONFIG_X86_64
849 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
850 (cr0 & X86_CR0_PG)) {
851 int cs_db, cs_l;
852
853 if (!is_pae(vcpu))
854 return 1;
855 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
856 if (cs_l)
857 return 1;
858 }
859 #endif
860 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
861 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
862 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
863 return 1;
864
865 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
866 return 1;
867
868 kvm_x86_ops.set_cr0(vcpu, cr0);
869
870 kvm_post_set_cr0(vcpu, old_cr0, cr0);
871
872 return 0;
873 }
874 EXPORT_SYMBOL_GPL(kvm_set_cr0);
875
876 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
877 {
878 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
879 }
880 EXPORT_SYMBOL_GPL(kvm_lmsw);
881
882 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
883 {
884 if (vcpu->arch.guest_state_protected)
885 return;
886
887 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
888
889 if (vcpu->arch.xcr0 != host_xcr0)
890 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
891
892 if (vcpu->arch.xsaves_enabled &&
893 vcpu->arch.ia32_xss != host_xss)
894 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
895 }
896
897 if (static_cpu_has(X86_FEATURE_PKU) &&
898 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
899 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
900 vcpu->arch.pkru != vcpu->arch.host_pkru)
901 __write_pkru(vcpu->arch.pkru);
902 }
903 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
904
905 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
906 {
907 if (vcpu->arch.guest_state_protected)
908 return;
909
910 if (static_cpu_has(X86_FEATURE_PKU) &&
911 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
912 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
913 vcpu->arch.pkru = rdpkru();
914 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
915 __write_pkru(vcpu->arch.host_pkru);
916 }
917
918 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
919
920 if (vcpu->arch.xcr0 != host_xcr0)
921 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
922
923 if (vcpu->arch.xsaves_enabled &&
924 vcpu->arch.ia32_xss != host_xss)
925 wrmsrl(MSR_IA32_XSS, host_xss);
926 }
927
928 }
929 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
930
931 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
932 {
933 u64 xcr0 = xcr;
934 u64 old_xcr0 = vcpu->arch.xcr0;
935 u64 valid_bits;
936
937 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
938 if (index != XCR_XFEATURE_ENABLED_MASK)
939 return 1;
940 if (!(xcr0 & XFEATURE_MASK_FP))
941 return 1;
942 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
943 return 1;
944
945 /*
946 * Do not allow the guest to set bits that we do not support
947 * saving. However, xcr0 bit 0 is always set, even if the
948 * emulated CPU does not support XSAVE (see fx_init).
949 */
950 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
951 if (xcr0 & ~valid_bits)
952 return 1;
953
954 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
955 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
956 return 1;
957
958 if (xcr0 & XFEATURE_MASK_AVX512) {
959 if (!(xcr0 & XFEATURE_MASK_YMM))
960 return 1;
961 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
962 return 1;
963 }
964 vcpu->arch.xcr0 = xcr0;
965
966 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
967 kvm_update_cpuid_runtime(vcpu);
968 return 0;
969 }
970
971 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
972 {
973 if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
974 __kvm_set_xcr(vcpu, index, xcr)) {
975 kvm_inject_gp(vcpu, 0);
976 return 1;
977 }
978 return 0;
979 }
980 EXPORT_SYMBOL_GPL(kvm_set_xcr);
981
982 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
983 {
984 if (cr4 & cr4_reserved_bits)
985 return false;
986
987 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
988 return false;
989
990 return kvm_x86_ops.is_valid_cr4(vcpu, cr4);
991 }
992 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
993
994 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
995 {
996 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
997 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
998
999 if (((cr4 ^ old_cr4) & mmu_role_bits) ||
1000 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1001 kvm_mmu_reset_context(vcpu);
1002 }
1003 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1004
1005 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1006 {
1007 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1008 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
1009 X86_CR4_SMEP;
1010
1011 if (!kvm_is_valid_cr4(vcpu, cr4))
1012 return 1;
1013
1014 if (is_long_mode(vcpu)) {
1015 if (!(cr4 & X86_CR4_PAE))
1016 return 1;
1017 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1018 return 1;
1019 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1020 && ((cr4 ^ old_cr4) & pdptr_bits)
1021 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
1022 kvm_read_cr3(vcpu)))
1023 return 1;
1024
1025 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1026 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1027 return 1;
1028
1029 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1030 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1031 return 1;
1032 }
1033
1034 kvm_x86_ops.set_cr4(vcpu, cr4);
1035
1036 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1037
1038 return 0;
1039 }
1040 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1041
1042 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1043 {
1044 bool skip_tlb_flush = false;
1045 #ifdef CONFIG_X86_64
1046 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1047
1048 if (pcid_enabled) {
1049 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1050 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1051 }
1052 #endif
1053
1054 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1055 if (!skip_tlb_flush) {
1056 kvm_mmu_sync_roots(vcpu);
1057 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1058 }
1059 return 0;
1060 }
1061
1062 if (is_long_mode(vcpu) &&
1063 (cr3 & vcpu->arch.cr3_lm_rsvd_bits))
1064 return 1;
1065 else if (is_pae_paging(vcpu) &&
1066 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1067 return 1;
1068
1069 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1070 vcpu->arch.cr3 = cr3;
1071 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1072
1073 return 0;
1074 }
1075 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1076
1077 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1078 {
1079 if (cr8 & CR8_RESERVED_BITS)
1080 return 1;
1081 if (lapic_in_kernel(vcpu))
1082 kvm_lapic_set_tpr(vcpu, cr8);
1083 else
1084 vcpu->arch.cr8 = cr8;
1085 return 0;
1086 }
1087 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1088
1089 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1090 {
1091 if (lapic_in_kernel(vcpu))
1092 return kvm_lapic_get_cr8(vcpu);
1093 else
1094 return vcpu->arch.cr8;
1095 }
1096 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1097
1098 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1099 {
1100 int i;
1101
1102 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1103 for (i = 0; i < KVM_NR_DB_REGS; i++)
1104 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1105 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1106 }
1107 }
1108
1109 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1110 {
1111 unsigned long dr7;
1112
1113 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1114 dr7 = vcpu->arch.guest_debug_dr7;
1115 else
1116 dr7 = vcpu->arch.dr7;
1117 kvm_x86_ops.set_dr7(vcpu, dr7);
1118 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1119 if (dr7 & DR7_BP_EN_MASK)
1120 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1121 }
1122 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1123
1124 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1125 {
1126 u64 fixed = DR6_FIXED_1;
1127
1128 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1129 fixed |= DR6_RTM;
1130 return fixed;
1131 }
1132
1133 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1134 {
1135 size_t size = ARRAY_SIZE(vcpu->arch.db);
1136
1137 switch (dr) {
1138 case 0 ... 3:
1139 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1140 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1141 vcpu->arch.eff_db[dr] = val;
1142 break;
1143 case 4:
1144 case 6:
1145 if (!kvm_dr6_valid(val))
1146 return -1; /* #GP */
1147 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1148 break;
1149 case 5:
1150 default: /* 7 */
1151 if (!kvm_dr7_valid(val))
1152 return -1; /* #GP */
1153 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1154 kvm_update_dr7(vcpu);
1155 break;
1156 }
1157
1158 return 0;
1159 }
1160
1161 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1162 {
1163 if (__kvm_set_dr(vcpu, dr, val)) {
1164 kvm_inject_gp(vcpu, 0);
1165 return 1;
1166 }
1167 return 0;
1168 }
1169 EXPORT_SYMBOL_GPL(kvm_set_dr);
1170
1171 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1172 {
1173 size_t size = ARRAY_SIZE(vcpu->arch.db);
1174
1175 switch (dr) {
1176 case 0 ... 3:
1177 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1178 break;
1179 case 4:
1180 case 6:
1181 *val = vcpu->arch.dr6;
1182 break;
1183 case 5:
1184 default: /* 7 */
1185 *val = vcpu->arch.dr7;
1186 break;
1187 }
1188 return 0;
1189 }
1190 EXPORT_SYMBOL_GPL(kvm_get_dr);
1191
1192 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1193 {
1194 u32 ecx = kvm_rcx_read(vcpu);
1195 u64 data;
1196 int err;
1197
1198 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1199 if (err)
1200 return err;
1201 kvm_rax_write(vcpu, (u32)data);
1202 kvm_rdx_write(vcpu, data >> 32);
1203 return err;
1204 }
1205 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1206
1207 /*
1208 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1209 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1210 *
1211 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1212 * extract the supported MSRs from the related const lists.
1213 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1214 * capabilities of the host cpu. This capabilities test skips MSRs that are
1215 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1216 * may depend on host virtualization features rather than host cpu features.
1217 */
1218
1219 static const u32 msrs_to_save_all[] = {
1220 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1221 MSR_STAR,
1222 #ifdef CONFIG_X86_64
1223 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1224 #endif
1225 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1226 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1227 MSR_IA32_SPEC_CTRL,
1228 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1229 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1230 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1231 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1232 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1233 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1234 MSR_IA32_UMWAIT_CONTROL,
1235
1236 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1237 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1238 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1239 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1240 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1241 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1242 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1243 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1244 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1245 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1246 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1247 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1248 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1249 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1250 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1251 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1252 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1253 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1254 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1255 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1256 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1257 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1258 };
1259
1260 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1261 static unsigned num_msrs_to_save;
1262
1263 static const u32 emulated_msrs_all[] = {
1264 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1265 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1266 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1267 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1268 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1269 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1270 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1271 HV_X64_MSR_RESET,
1272 HV_X64_MSR_VP_INDEX,
1273 HV_X64_MSR_VP_RUNTIME,
1274 HV_X64_MSR_SCONTROL,
1275 HV_X64_MSR_STIMER0_CONFIG,
1276 HV_X64_MSR_VP_ASSIST_PAGE,
1277 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1278 HV_X64_MSR_TSC_EMULATION_STATUS,
1279 HV_X64_MSR_SYNDBG_OPTIONS,
1280 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1281 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1282 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1283
1284 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1285 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1286
1287 MSR_IA32_TSC_ADJUST,
1288 MSR_IA32_TSCDEADLINE,
1289 MSR_IA32_ARCH_CAPABILITIES,
1290 MSR_IA32_PERF_CAPABILITIES,
1291 MSR_IA32_MISC_ENABLE,
1292 MSR_IA32_MCG_STATUS,
1293 MSR_IA32_MCG_CTL,
1294 MSR_IA32_MCG_EXT_CTL,
1295 MSR_IA32_SMBASE,
1296 MSR_SMI_COUNT,
1297 MSR_PLATFORM_INFO,
1298 MSR_MISC_FEATURES_ENABLES,
1299 MSR_AMD64_VIRT_SPEC_CTRL,
1300 MSR_IA32_POWER_CTL,
1301 MSR_IA32_UCODE_REV,
1302
1303 /*
1304 * The following list leaves out MSRs whose values are determined
1305 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1306 * We always support the "true" VMX control MSRs, even if the host
1307 * processor does not, so I am putting these registers here rather
1308 * than in msrs_to_save_all.
1309 */
1310 MSR_IA32_VMX_BASIC,
1311 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1312 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1313 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1314 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1315 MSR_IA32_VMX_MISC,
1316 MSR_IA32_VMX_CR0_FIXED0,
1317 MSR_IA32_VMX_CR4_FIXED0,
1318 MSR_IA32_VMX_VMCS_ENUM,
1319 MSR_IA32_VMX_PROCBASED_CTLS2,
1320 MSR_IA32_VMX_EPT_VPID_CAP,
1321 MSR_IA32_VMX_VMFUNC,
1322
1323 MSR_K7_HWCR,
1324 MSR_KVM_POLL_CONTROL,
1325 };
1326
1327 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1328 static unsigned num_emulated_msrs;
1329
1330 /*
1331 * List of msr numbers which are used to expose MSR-based features that
1332 * can be used by a hypervisor to validate requested CPU features.
1333 */
1334 static const u32 msr_based_features_all[] = {
1335 MSR_IA32_VMX_BASIC,
1336 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1337 MSR_IA32_VMX_PINBASED_CTLS,
1338 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1339 MSR_IA32_VMX_PROCBASED_CTLS,
1340 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1341 MSR_IA32_VMX_EXIT_CTLS,
1342 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1343 MSR_IA32_VMX_ENTRY_CTLS,
1344 MSR_IA32_VMX_MISC,
1345 MSR_IA32_VMX_CR0_FIXED0,
1346 MSR_IA32_VMX_CR0_FIXED1,
1347 MSR_IA32_VMX_CR4_FIXED0,
1348 MSR_IA32_VMX_CR4_FIXED1,
1349 MSR_IA32_VMX_VMCS_ENUM,
1350 MSR_IA32_VMX_PROCBASED_CTLS2,
1351 MSR_IA32_VMX_EPT_VPID_CAP,
1352 MSR_IA32_VMX_VMFUNC,
1353
1354 MSR_F10H_DECFG,
1355 MSR_IA32_UCODE_REV,
1356 MSR_IA32_ARCH_CAPABILITIES,
1357 MSR_IA32_PERF_CAPABILITIES,
1358 };
1359
1360 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1361 static unsigned int num_msr_based_features;
1362
1363 static u64 kvm_get_arch_capabilities(void)
1364 {
1365 u64 data = 0;
1366
1367 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1368 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1369
1370 /*
1371 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1372 * the nested hypervisor runs with NX huge pages. If it is not,
1373 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1374 * L1 guests, so it need not worry about its own (L2) guests.
1375 */
1376 data |= ARCH_CAP_PSCHANGE_MC_NO;
1377
1378 /*
1379 * If we're doing cache flushes (either "always" or "cond")
1380 * we will do one whenever the guest does a vmlaunch/vmresume.
1381 * If an outer hypervisor is doing the cache flush for us
1382 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1383 * capability to the guest too, and if EPT is disabled we're not
1384 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1385 * require a nested hypervisor to do a flush of its own.
1386 */
1387 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1388 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1389
1390 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1391 data |= ARCH_CAP_RDCL_NO;
1392 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1393 data |= ARCH_CAP_SSB_NO;
1394 if (!boot_cpu_has_bug(X86_BUG_MDS))
1395 data |= ARCH_CAP_MDS_NO;
1396
1397 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1398 /*
1399 * If RTM=0 because the kernel has disabled TSX, the host might
1400 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1401 * and therefore knows that there cannot be TAA) but keep
1402 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1403 * and we want to allow migrating those guests to tsx=off hosts.
1404 */
1405 data &= ~ARCH_CAP_TAA_NO;
1406 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1407 data |= ARCH_CAP_TAA_NO;
1408 } else {
1409 /*
1410 * Nothing to do here; we emulate TSX_CTRL if present on the
1411 * host so the guest can choose between disabling TSX or
1412 * using VERW to clear CPU buffers.
1413 */
1414 }
1415
1416 return data;
1417 }
1418
1419 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1420 {
1421 switch (msr->index) {
1422 case MSR_IA32_ARCH_CAPABILITIES:
1423 msr->data = kvm_get_arch_capabilities();
1424 break;
1425 case MSR_IA32_UCODE_REV:
1426 rdmsrl_safe(msr->index, &msr->data);
1427 break;
1428 default:
1429 return kvm_x86_ops.get_msr_feature(msr);
1430 }
1431 return 0;
1432 }
1433
1434 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1435 {
1436 struct kvm_msr_entry msr;
1437 int r;
1438
1439 msr.index = index;
1440 r = kvm_get_msr_feature(&msr);
1441
1442 if (r == KVM_MSR_RET_INVALID) {
1443 /* Unconditionally clear the output for simplicity */
1444 *data = 0;
1445 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1446 r = 0;
1447 }
1448
1449 if (r)
1450 return r;
1451
1452 *data = msr.data;
1453
1454 return 0;
1455 }
1456
1457 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1458 {
1459 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1460 return false;
1461
1462 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1463 return false;
1464
1465 if (efer & (EFER_LME | EFER_LMA) &&
1466 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1467 return false;
1468
1469 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1470 return false;
1471
1472 return true;
1473
1474 }
1475 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1476 {
1477 if (efer & efer_reserved_bits)
1478 return false;
1479
1480 return __kvm_valid_efer(vcpu, efer);
1481 }
1482 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1483
1484 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1485 {
1486 u64 old_efer = vcpu->arch.efer;
1487 u64 efer = msr_info->data;
1488 int r;
1489
1490 if (efer & efer_reserved_bits)
1491 return 1;
1492
1493 if (!msr_info->host_initiated) {
1494 if (!__kvm_valid_efer(vcpu, efer))
1495 return 1;
1496
1497 if (is_paging(vcpu) &&
1498 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1499 return 1;
1500 }
1501
1502 efer &= ~EFER_LMA;
1503 efer |= vcpu->arch.efer & EFER_LMA;
1504
1505 r = kvm_x86_ops.set_efer(vcpu, efer);
1506 if (r) {
1507 WARN_ON(r > 0);
1508 return r;
1509 }
1510
1511 /* Update reserved bits */
1512 if ((efer ^ old_efer) & EFER_NX)
1513 kvm_mmu_reset_context(vcpu);
1514
1515 return 0;
1516 }
1517
1518 void kvm_enable_efer_bits(u64 mask)
1519 {
1520 efer_reserved_bits &= ~mask;
1521 }
1522 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1523
1524 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1525 {
1526 struct kvm *kvm = vcpu->kvm;
1527 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
1528 u32 count = kvm->arch.msr_filter.count;
1529 u32 i;
1530 bool r = kvm->arch.msr_filter.default_allow;
1531 int idx;
1532
1533 /* MSR filtering not set up or x2APIC enabled, allow everything */
1534 if (!count || (index >= 0x800 && index <= 0x8ff))
1535 return true;
1536
1537 /* Prevent collision with set_msr_filter */
1538 idx = srcu_read_lock(&kvm->srcu);
1539
1540 for (i = 0; i < count; i++) {
1541 u32 start = ranges[i].base;
1542 u32 end = start + ranges[i].nmsrs;
1543 u32 flags = ranges[i].flags;
1544 unsigned long *bitmap = ranges[i].bitmap;
1545
1546 if ((index >= start) && (index < end) && (flags & type)) {
1547 r = !!test_bit(index - start, bitmap);
1548 break;
1549 }
1550 }
1551
1552 srcu_read_unlock(&kvm->srcu, idx);
1553
1554 return r;
1555 }
1556 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1557
1558 /*
1559 * Write @data into the MSR specified by @index. Select MSR specific fault
1560 * checks are bypassed if @host_initiated is %true.
1561 * Returns 0 on success, non-0 otherwise.
1562 * Assumes vcpu_load() was already called.
1563 */
1564 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1565 bool host_initiated)
1566 {
1567 struct msr_data msr;
1568
1569 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1570 return KVM_MSR_RET_FILTERED;
1571
1572 switch (index) {
1573 case MSR_FS_BASE:
1574 case MSR_GS_BASE:
1575 case MSR_KERNEL_GS_BASE:
1576 case MSR_CSTAR:
1577 case MSR_LSTAR:
1578 if (is_noncanonical_address(data, vcpu))
1579 return 1;
1580 break;
1581 case MSR_IA32_SYSENTER_EIP:
1582 case MSR_IA32_SYSENTER_ESP:
1583 /*
1584 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1585 * non-canonical address is written on Intel but not on
1586 * AMD (which ignores the top 32-bits, because it does
1587 * not implement 64-bit SYSENTER).
1588 *
1589 * 64-bit code should hence be able to write a non-canonical
1590 * value on AMD. Making the address canonical ensures that
1591 * vmentry does not fail on Intel after writing a non-canonical
1592 * value, and that something deterministic happens if the guest
1593 * invokes 64-bit SYSENTER.
1594 */
1595 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1596 }
1597
1598 msr.data = data;
1599 msr.index = index;
1600 msr.host_initiated = host_initiated;
1601
1602 return kvm_x86_ops.set_msr(vcpu, &msr);
1603 }
1604
1605 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1606 u32 index, u64 data, bool host_initiated)
1607 {
1608 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1609
1610 if (ret == KVM_MSR_RET_INVALID)
1611 if (kvm_msr_ignored_check(vcpu, index, data, true))
1612 ret = 0;
1613
1614 return ret;
1615 }
1616
1617 /*
1618 * Read the MSR specified by @index into @data. Select MSR specific fault
1619 * checks are bypassed if @host_initiated is %true.
1620 * Returns 0 on success, non-0 otherwise.
1621 * Assumes vcpu_load() was already called.
1622 */
1623 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1624 bool host_initiated)
1625 {
1626 struct msr_data msr;
1627 int ret;
1628
1629 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1630 return KVM_MSR_RET_FILTERED;
1631
1632 msr.index = index;
1633 msr.host_initiated = host_initiated;
1634
1635 ret = kvm_x86_ops.get_msr(vcpu, &msr);
1636 if (!ret)
1637 *data = msr.data;
1638 return ret;
1639 }
1640
1641 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1642 u32 index, u64 *data, bool host_initiated)
1643 {
1644 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1645
1646 if (ret == KVM_MSR_RET_INVALID) {
1647 /* Unconditionally clear *data for simplicity */
1648 *data = 0;
1649 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1650 ret = 0;
1651 }
1652
1653 return ret;
1654 }
1655
1656 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1657 {
1658 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1659 }
1660 EXPORT_SYMBOL_GPL(kvm_get_msr);
1661
1662 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1663 {
1664 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1665 }
1666 EXPORT_SYMBOL_GPL(kvm_set_msr);
1667
1668 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1669 {
1670 int err = vcpu->run->msr.error;
1671 if (!err) {
1672 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1673 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1674 }
1675
1676 return kvm_x86_ops.complete_emulated_msr(vcpu, err);
1677 }
1678
1679 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1680 {
1681 return kvm_x86_ops.complete_emulated_msr(vcpu, vcpu->run->msr.error);
1682 }
1683
1684 static u64 kvm_msr_reason(int r)
1685 {
1686 switch (r) {
1687 case KVM_MSR_RET_INVALID:
1688 return KVM_MSR_EXIT_REASON_UNKNOWN;
1689 case KVM_MSR_RET_FILTERED:
1690 return KVM_MSR_EXIT_REASON_FILTER;
1691 default:
1692 return KVM_MSR_EXIT_REASON_INVAL;
1693 }
1694 }
1695
1696 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1697 u32 exit_reason, u64 data,
1698 int (*completion)(struct kvm_vcpu *vcpu),
1699 int r)
1700 {
1701 u64 msr_reason = kvm_msr_reason(r);
1702
1703 /* Check if the user wanted to know about this MSR fault */
1704 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1705 return 0;
1706
1707 vcpu->run->exit_reason = exit_reason;
1708 vcpu->run->msr.error = 0;
1709 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1710 vcpu->run->msr.reason = msr_reason;
1711 vcpu->run->msr.index = index;
1712 vcpu->run->msr.data = data;
1713 vcpu->arch.complete_userspace_io = completion;
1714
1715 return 1;
1716 }
1717
1718 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1719 {
1720 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1721 complete_emulated_rdmsr, r);
1722 }
1723
1724 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1725 {
1726 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1727 complete_emulated_wrmsr, r);
1728 }
1729
1730 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1731 {
1732 u32 ecx = kvm_rcx_read(vcpu);
1733 u64 data;
1734 int r;
1735
1736 r = kvm_get_msr(vcpu, ecx, &data);
1737
1738 /* MSR read failed? See if we should ask user space */
1739 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1740 /* Bounce to user space */
1741 return 0;
1742 }
1743
1744 if (!r) {
1745 trace_kvm_msr_read(ecx, data);
1746
1747 kvm_rax_write(vcpu, data & -1u);
1748 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1749 } else {
1750 trace_kvm_msr_read_ex(ecx);
1751 }
1752
1753 return kvm_x86_ops.complete_emulated_msr(vcpu, r);
1754 }
1755 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1756
1757 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1758 {
1759 u32 ecx = kvm_rcx_read(vcpu);
1760 u64 data = kvm_read_edx_eax(vcpu);
1761 int r;
1762
1763 r = kvm_set_msr(vcpu, ecx, data);
1764
1765 /* MSR write failed? See if we should ask user space */
1766 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r))
1767 /* Bounce to user space */
1768 return 0;
1769
1770 /* Signal all other negative errors to userspace */
1771 if (r < 0)
1772 return r;
1773
1774 if (!r)
1775 trace_kvm_msr_write(ecx, data);
1776 else
1777 trace_kvm_msr_write_ex(ecx, data);
1778
1779 return kvm_x86_ops.complete_emulated_msr(vcpu, r);
1780 }
1781 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1782
1783 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1784 {
1785 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1786 xfer_to_guest_mode_work_pending();
1787 }
1788 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1789
1790 /*
1791 * The fast path for frequent and performance sensitive wrmsr emulation,
1792 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1793 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1794 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1795 * other cases which must be called after interrupts are enabled on the host.
1796 */
1797 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1798 {
1799 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1800 return 1;
1801
1802 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1803 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1804 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1805 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1806
1807 data &= ~(1 << 12);
1808 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1809 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1810 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1811 trace_kvm_apic_write(APIC_ICR, (u32)data);
1812 return 0;
1813 }
1814
1815 return 1;
1816 }
1817
1818 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1819 {
1820 if (!kvm_can_use_hv_timer(vcpu))
1821 return 1;
1822
1823 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1824 return 0;
1825 }
1826
1827 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1828 {
1829 u32 msr = kvm_rcx_read(vcpu);
1830 u64 data;
1831 fastpath_t ret = EXIT_FASTPATH_NONE;
1832
1833 switch (msr) {
1834 case APIC_BASE_MSR + (APIC_ICR >> 4):
1835 data = kvm_read_edx_eax(vcpu);
1836 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1837 kvm_skip_emulated_instruction(vcpu);
1838 ret = EXIT_FASTPATH_EXIT_HANDLED;
1839 }
1840 break;
1841 case MSR_IA32_TSCDEADLINE:
1842 data = kvm_read_edx_eax(vcpu);
1843 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1844 kvm_skip_emulated_instruction(vcpu);
1845 ret = EXIT_FASTPATH_REENTER_GUEST;
1846 }
1847 break;
1848 default:
1849 break;
1850 }
1851
1852 if (ret != EXIT_FASTPATH_NONE)
1853 trace_kvm_msr_write(msr, data);
1854
1855 return ret;
1856 }
1857 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1858
1859 /*
1860 * Adapt set_msr() to msr_io()'s calling convention
1861 */
1862 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1863 {
1864 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1865 }
1866
1867 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1868 {
1869 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1870 }
1871
1872 #ifdef CONFIG_X86_64
1873 struct pvclock_clock {
1874 int vclock_mode;
1875 u64 cycle_last;
1876 u64 mask;
1877 u32 mult;
1878 u32 shift;
1879 u64 base_cycles;
1880 u64 offset;
1881 };
1882
1883 struct pvclock_gtod_data {
1884 seqcount_t seq;
1885
1886 struct pvclock_clock clock; /* extract of a clocksource struct */
1887 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1888
1889 ktime_t offs_boot;
1890 u64 wall_time_sec;
1891 };
1892
1893 static struct pvclock_gtod_data pvclock_gtod_data;
1894
1895 static void update_pvclock_gtod(struct timekeeper *tk)
1896 {
1897 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1898
1899 write_seqcount_begin(&vdata->seq);
1900
1901 /* copy pvclock gtod data */
1902 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1903 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1904 vdata->clock.mask = tk->tkr_mono.mask;
1905 vdata->clock.mult = tk->tkr_mono.mult;
1906 vdata->clock.shift = tk->tkr_mono.shift;
1907 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1908 vdata->clock.offset = tk->tkr_mono.base;
1909
1910 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1911 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1912 vdata->raw_clock.mask = tk->tkr_raw.mask;
1913 vdata->raw_clock.mult = tk->tkr_raw.mult;
1914 vdata->raw_clock.shift = tk->tkr_raw.shift;
1915 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1916 vdata->raw_clock.offset = tk->tkr_raw.base;
1917
1918 vdata->wall_time_sec = tk->xtime_sec;
1919
1920 vdata->offs_boot = tk->offs_boot;
1921
1922 write_seqcount_end(&vdata->seq);
1923 }
1924
1925 static s64 get_kvmclock_base_ns(void)
1926 {
1927 /* Count up from boot time, but with the frequency of the raw clock. */
1928 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1929 }
1930 #else
1931 static s64 get_kvmclock_base_ns(void)
1932 {
1933 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1934 return ktime_get_boottime_ns();
1935 }
1936 #endif
1937
1938 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1939 {
1940 int version;
1941 int r;
1942 struct pvclock_wall_clock wc;
1943 u64 wall_nsec;
1944
1945 kvm->arch.wall_clock = wall_clock;
1946
1947 if (!wall_clock)
1948 return;
1949
1950 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1951 if (r)
1952 return;
1953
1954 if (version & 1)
1955 ++version; /* first time write, random junk */
1956
1957 ++version;
1958
1959 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1960 return;
1961
1962 /*
1963 * The guest calculates current wall clock time by adding
1964 * system time (updated by kvm_guest_time_update below) to the
1965 * wall clock specified here. We do the reverse here.
1966 */
1967 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1968
1969 wc.nsec = do_div(wall_nsec, 1000000000);
1970 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1971 wc.version = version;
1972
1973 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1974
1975 version++;
1976 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1977 }
1978
1979 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1980 bool old_msr, bool host_initiated)
1981 {
1982 struct kvm_arch *ka = &vcpu->kvm->arch;
1983
1984 if (vcpu->vcpu_id == 0 && !host_initiated) {
1985 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
1986 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1987
1988 ka->boot_vcpu_runs_old_kvmclock = old_msr;
1989 }
1990
1991 vcpu->arch.time = system_time;
1992 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
1993
1994 /* we verify if the enable bit is set... */
1995 vcpu->arch.pv_time_enabled = false;
1996 if (!(system_time & 1))
1997 return;
1998
1999 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2000 &vcpu->arch.pv_time, system_time & ~1ULL,
2001 sizeof(struct pvclock_vcpu_time_info)))
2002 vcpu->arch.pv_time_enabled = true;
2003
2004 return;
2005 }
2006
2007 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2008 {
2009 do_shl32_div32(dividend, divisor);
2010 return dividend;
2011 }
2012
2013 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2014 s8 *pshift, u32 *pmultiplier)
2015 {
2016 uint64_t scaled64;
2017 int32_t shift = 0;
2018 uint64_t tps64;
2019 uint32_t tps32;
2020
2021 tps64 = base_hz;
2022 scaled64 = scaled_hz;
2023 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2024 tps64 >>= 1;
2025 shift--;
2026 }
2027
2028 tps32 = (uint32_t)tps64;
2029 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2030 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2031 scaled64 >>= 1;
2032 else
2033 tps32 <<= 1;
2034 shift++;
2035 }
2036
2037 *pshift = shift;
2038 *pmultiplier = div_frac(scaled64, tps32);
2039 }
2040
2041 #ifdef CONFIG_X86_64
2042 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2043 #endif
2044
2045 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2046 static unsigned long max_tsc_khz;
2047
2048 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2049 {
2050 u64 v = (u64)khz * (1000000 + ppm);
2051 do_div(v, 1000000);
2052 return v;
2053 }
2054
2055 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2056 {
2057 u64 ratio;
2058
2059 /* Guest TSC same frequency as host TSC? */
2060 if (!scale) {
2061 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2062 return 0;
2063 }
2064
2065 /* TSC scaling supported? */
2066 if (!kvm_has_tsc_control) {
2067 if (user_tsc_khz > tsc_khz) {
2068 vcpu->arch.tsc_catchup = 1;
2069 vcpu->arch.tsc_always_catchup = 1;
2070 return 0;
2071 } else {
2072 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2073 return -1;
2074 }
2075 }
2076
2077 /* TSC scaling required - calculate ratio */
2078 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2079 user_tsc_khz, tsc_khz);
2080
2081 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2082 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2083 user_tsc_khz);
2084 return -1;
2085 }
2086
2087 vcpu->arch.tsc_scaling_ratio = ratio;
2088 return 0;
2089 }
2090
2091 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2092 {
2093 u32 thresh_lo, thresh_hi;
2094 int use_scaling = 0;
2095
2096 /* tsc_khz can be zero if TSC calibration fails */
2097 if (user_tsc_khz == 0) {
2098 /* set tsc_scaling_ratio to a safe value */
2099 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2100 return -1;
2101 }
2102
2103 /* Compute a scale to convert nanoseconds in TSC cycles */
2104 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2105 &vcpu->arch.virtual_tsc_shift,
2106 &vcpu->arch.virtual_tsc_mult);
2107 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2108
2109 /*
2110 * Compute the variation in TSC rate which is acceptable
2111 * within the range of tolerance and decide if the
2112 * rate being applied is within that bounds of the hardware
2113 * rate. If so, no scaling or compensation need be done.
2114 */
2115 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2116 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2117 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2118 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2119 use_scaling = 1;
2120 }
2121 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2122 }
2123
2124 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2125 {
2126 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2127 vcpu->arch.virtual_tsc_mult,
2128 vcpu->arch.virtual_tsc_shift);
2129 tsc += vcpu->arch.this_tsc_write;
2130 return tsc;
2131 }
2132
2133 static inline int gtod_is_based_on_tsc(int mode)
2134 {
2135 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2136 }
2137
2138 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2139 {
2140 #ifdef CONFIG_X86_64
2141 bool vcpus_matched;
2142 struct kvm_arch *ka = &vcpu->kvm->arch;
2143 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2144
2145 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2146 atomic_read(&vcpu->kvm->online_vcpus));
2147
2148 /*
2149 * Once the masterclock is enabled, always perform request in
2150 * order to update it.
2151 *
2152 * In order to enable masterclock, the host clocksource must be TSC
2153 * and the vcpus need to have matched TSCs. When that happens,
2154 * perform request to enable masterclock.
2155 */
2156 if (ka->use_master_clock ||
2157 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2158 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2159
2160 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2161 atomic_read(&vcpu->kvm->online_vcpus),
2162 ka->use_master_clock, gtod->clock.vclock_mode);
2163 #endif
2164 }
2165
2166 /*
2167 * Multiply tsc by a fixed point number represented by ratio.
2168 *
2169 * The most significant 64-N bits (mult) of ratio represent the
2170 * integral part of the fixed point number; the remaining N bits
2171 * (frac) represent the fractional part, ie. ratio represents a fixed
2172 * point number (mult + frac * 2^(-N)).
2173 *
2174 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2175 */
2176 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2177 {
2178 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2179 }
2180
2181 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2182 {
2183 u64 _tsc = tsc;
2184 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2185
2186 if (ratio != kvm_default_tsc_scaling_ratio)
2187 _tsc = __scale_tsc(ratio, tsc);
2188
2189 return _tsc;
2190 }
2191 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2192
2193 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2194 {
2195 u64 tsc;
2196
2197 tsc = kvm_scale_tsc(vcpu, rdtsc());
2198
2199 return target_tsc - tsc;
2200 }
2201
2202 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2203 {
2204 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2205 }
2206 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2207
2208 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2209 {
2210 vcpu->arch.l1_tsc_offset = offset;
2211 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2212 }
2213
2214 static inline bool kvm_check_tsc_unstable(void)
2215 {
2216 #ifdef CONFIG_X86_64
2217 /*
2218 * TSC is marked unstable when we're running on Hyper-V,
2219 * 'TSC page' clocksource is good.
2220 */
2221 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2222 return false;
2223 #endif
2224 return check_tsc_unstable();
2225 }
2226
2227 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2228 {
2229 struct kvm *kvm = vcpu->kvm;
2230 u64 offset, ns, elapsed;
2231 unsigned long flags;
2232 bool matched;
2233 bool already_matched;
2234 bool synchronizing = false;
2235
2236 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2237 offset = kvm_compute_tsc_offset(vcpu, data);
2238 ns = get_kvmclock_base_ns();
2239 elapsed = ns - kvm->arch.last_tsc_nsec;
2240
2241 if (vcpu->arch.virtual_tsc_khz) {
2242 if (data == 0) {
2243 /*
2244 * detection of vcpu initialization -- need to sync
2245 * with other vCPUs. This particularly helps to keep
2246 * kvm_clock stable after CPU hotplug
2247 */
2248 synchronizing = true;
2249 } else {
2250 u64 tsc_exp = kvm->arch.last_tsc_write +
2251 nsec_to_cycles(vcpu, elapsed);
2252 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2253 /*
2254 * Special case: TSC write with a small delta (1 second)
2255 * of virtual cycle time against real time is
2256 * interpreted as an attempt to synchronize the CPU.
2257 */
2258 synchronizing = data < tsc_exp + tsc_hz &&
2259 data + tsc_hz > tsc_exp;
2260 }
2261 }
2262
2263 /*
2264 * For a reliable TSC, we can match TSC offsets, and for an unstable
2265 * TSC, we add elapsed time in this computation. We could let the
2266 * compensation code attempt to catch up if we fall behind, but
2267 * it's better to try to match offsets from the beginning.
2268 */
2269 if (synchronizing &&
2270 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2271 if (!kvm_check_tsc_unstable()) {
2272 offset = kvm->arch.cur_tsc_offset;
2273 } else {
2274 u64 delta = nsec_to_cycles(vcpu, elapsed);
2275 data += delta;
2276 offset = kvm_compute_tsc_offset(vcpu, data);
2277 }
2278 matched = true;
2279 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2280 } else {
2281 /*
2282 * We split periods of matched TSC writes into generations.
2283 * For each generation, we track the original measured
2284 * nanosecond time, offset, and write, so if TSCs are in
2285 * sync, we can match exact offset, and if not, we can match
2286 * exact software computation in compute_guest_tsc()
2287 *
2288 * These values are tracked in kvm->arch.cur_xxx variables.
2289 */
2290 kvm->arch.cur_tsc_generation++;
2291 kvm->arch.cur_tsc_nsec = ns;
2292 kvm->arch.cur_tsc_write = data;
2293 kvm->arch.cur_tsc_offset = offset;
2294 matched = false;
2295 }
2296
2297 /*
2298 * We also track th most recent recorded KHZ, write and time to
2299 * allow the matching interval to be extended at each write.
2300 */
2301 kvm->arch.last_tsc_nsec = ns;
2302 kvm->arch.last_tsc_write = data;
2303 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2304
2305 vcpu->arch.last_guest_tsc = data;
2306
2307 /* Keep track of which generation this VCPU has synchronized to */
2308 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2309 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2310 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2311
2312 kvm_vcpu_write_tsc_offset(vcpu, offset);
2313 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2314
2315 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2316 if (!matched) {
2317 kvm->arch.nr_vcpus_matched_tsc = 0;
2318 } else if (!already_matched) {
2319 kvm->arch.nr_vcpus_matched_tsc++;
2320 }
2321
2322 kvm_track_tsc_matching(vcpu);
2323 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2324 }
2325
2326 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2327 s64 adjustment)
2328 {
2329 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2330 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2331 }
2332
2333 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2334 {
2335 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2336 WARN_ON(adjustment < 0);
2337 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2338 adjust_tsc_offset_guest(vcpu, adjustment);
2339 }
2340
2341 #ifdef CONFIG_X86_64
2342
2343 static u64 read_tsc(void)
2344 {
2345 u64 ret = (u64)rdtsc_ordered();
2346 u64 last = pvclock_gtod_data.clock.cycle_last;
2347
2348 if (likely(ret >= last))
2349 return ret;
2350
2351 /*
2352 * GCC likes to generate cmov here, but this branch is extremely
2353 * predictable (it's just a function of time and the likely is
2354 * very likely) and there's a data dependence, so force GCC
2355 * to generate a branch instead. I don't barrier() because
2356 * we don't actually need a barrier, and if this function
2357 * ever gets inlined it will generate worse code.
2358 */
2359 asm volatile ("");
2360 return last;
2361 }
2362
2363 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2364 int *mode)
2365 {
2366 long v;
2367 u64 tsc_pg_val;
2368
2369 switch (clock->vclock_mode) {
2370 case VDSO_CLOCKMODE_HVCLOCK:
2371 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2372 tsc_timestamp);
2373 if (tsc_pg_val != U64_MAX) {
2374 /* TSC page valid */
2375 *mode = VDSO_CLOCKMODE_HVCLOCK;
2376 v = (tsc_pg_val - clock->cycle_last) &
2377 clock->mask;
2378 } else {
2379 /* TSC page invalid */
2380 *mode = VDSO_CLOCKMODE_NONE;
2381 }
2382 break;
2383 case VDSO_CLOCKMODE_TSC:
2384 *mode = VDSO_CLOCKMODE_TSC;
2385 *tsc_timestamp = read_tsc();
2386 v = (*tsc_timestamp - clock->cycle_last) &
2387 clock->mask;
2388 break;
2389 default:
2390 *mode = VDSO_CLOCKMODE_NONE;
2391 }
2392
2393 if (*mode == VDSO_CLOCKMODE_NONE)
2394 *tsc_timestamp = v = 0;
2395
2396 return v * clock->mult;
2397 }
2398
2399 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2400 {
2401 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2402 unsigned long seq;
2403 int mode;
2404 u64 ns;
2405
2406 do {
2407 seq = read_seqcount_begin(&gtod->seq);
2408 ns = gtod->raw_clock.base_cycles;
2409 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2410 ns >>= gtod->raw_clock.shift;
2411 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2412 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2413 *t = ns;
2414
2415 return mode;
2416 }
2417
2418 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2419 {
2420 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2421 unsigned long seq;
2422 int mode;
2423 u64 ns;
2424
2425 do {
2426 seq = read_seqcount_begin(&gtod->seq);
2427 ts->tv_sec = gtod->wall_time_sec;
2428 ns = gtod->clock.base_cycles;
2429 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2430 ns >>= gtod->clock.shift;
2431 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2432
2433 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2434 ts->tv_nsec = ns;
2435
2436 return mode;
2437 }
2438
2439 /* returns true if host is using TSC based clocksource */
2440 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2441 {
2442 /* checked again under seqlock below */
2443 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2444 return false;
2445
2446 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2447 tsc_timestamp));
2448 }
2449
2450 /* returns true if host is using TSC based clocksource */
2451 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2452 u64 *tsc_timestamp)
2453 {
2454 /* checked again under seqlock below */
2455 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2456 return false;
2457
2458 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2459 }
2460 #endif
2461
2462 /*
2463 *
2464 * Assuming a stable TSC across physical CPUS, and a stable TSC
2465 * across virtual CPUs, the following condition is possible.
2466 * Each numbered line represents an event visible to both
2467 * CPUs at the next numbered event.
2468 *
2469 * "timespecX" represents host monotonic time. "tscX" represents
2470 * RDTSC value.
2471 *
2472 * VCPU0 on CPU0 | VCPU1 on CPU1
2473 *
2474 * 1. read timespec0,tsc0
2475 * 2. | timespec1 = timespec0 + N
2476 * | tsc1 = tsc0 + M
2477 * 3. transition to guest | transition to guest
2478 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2479 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2480 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2481 *
2482 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2483 *
2484 * - ret0 < ret1
2485 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2486 * ...
2487 * - 0 < N - M => M < N
2488 *
2489 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2490 * always the case (the difference between two distinct xtime instances
2491 * might be smaller then the difference between corresponding TSC reads,
2492 * when updating guest vcpus pvclock areas).
2493 *
2494 * To avoid that problem, do not allow visibility of distinct
2495 * system_timestamp/tsc_timestamp values simultaneously: use a master
2496 * copy of host monotonic time values. Update that master copy
2497 * in lockstep.
2498 *
2499 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2500 *
2501 */
2502
2503 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2504 {
2505 #ifdef CONFIG_X86_64
2506 struct kvm_arch *ka = &kvm->arch;
2507 int vclock_mode;
2508 bool host_tsc_clocksource, vcpus_matched;
2509
2510 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2511 atomic_read(&kvm->online_vcpus));
2512
2513 /*
2514 * If the host uses TSC clock, then passthrough TSC as stable
2515 * to the guest.
2516 */
2517 host_tsc_clocksource = kvm_get_time_and_clockread(
2518 &ka->master_kernel_ns,
2519 &ka->master_cycle_now);
2520
2521 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2522 && !ka->backwards_tsc_observed
2523 && !ka->boot_vcpu_runs_old_kvmclock;
2524
2525 if (ka->use_master_clock)
2526 atomic_set(&kvm_guest_has_master_clock, 1);
2527
2528 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2529 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2530 vcpus_matched);
2531 #endif
2532 }
2533
2534 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2535 {
2536 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2537 }
2538
2539 static void kvm_gen_update_masterclock(struct kvm *kvm)
2540 {
2541 #ifdef CONFIG_X86_64
2542 int i;
2543 struct kvm_vcpu *vcpu;
2544 struct kvm_arch *ka = &kvm->arch;
2545
2546 spin_lock(&ka->pvclock_gtod_sync_lock);
2547 kvm_make_mclock_inprogress_request(kvm);
2548 /* no guest entries from this point */
2549 pvclock_update_vm_gtod_copy(kvm);
2550
2551 kvm_for_each_vcpu(i, vcpu, kvm)
2552 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2553
2554 /* guest entries allowed */
2555 kvm_for_each_vcpu(i, vcpu, kvm)
2556 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2557
2558 spin_unlock(&ka->pvclock_gtod_sync_lock);
2559 #endif
2560 }
2561
2562 u64 get_kvmclock_ns(struct kvm *kvm)
2563 {
2564 struct kvm_arch *ka = &kvm->arch;
2565 struct pvclock_vcpu_time_info hv_clock;
2566 u64 ret;
2567
2568 spin_lock(&ka->pvclock_gtod_sync_lock);
2569 if (!ka->use_master_clock) {
2570 spin_unlock(&ka->pvclock_gtod_sync_lock);
2571 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2572 }
2573
2574 hv_clock.tsc_timestamp = ka->master_cycle_now;
2575 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2576 spin_unlock(&ka->pvclock_gtod_sync_lock);
2577
2578 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2579 get_cpu();
2580
2581 if (__this_cpu_read(cpu_tsc_khz)) {
2582 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2583 &hv_clock.tsc_shift,
2584 &hv_clock.tsc_to_system_mul);
2585 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2586 } else
2587 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2588
2589 put_cpu();
2590
2591 return ret;
2592 }
2593
2594 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2595 {
2596 struct kvm_vcpu_arch *vcpu = &v->arch;
2597 struct pvclock_vcpu_time_info guest_hv_clock;
2598
2599 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2600 &guest_hv_clock, sizeof(guest_hv_clock))))
2601 return;
2602
2603 /* This VCPU is paused, but it's legal for a guest to read another
2604 * VCPU's kvmclock, so we really have to follow the specification where
2605 * it says that version is odd if data is being modified, and even after
2606 * it is consistent.
2607 *
2608 * Version field updates must be kept separate. This is because
2609 * kvm_write_guest_cached might use a "rep movs" instruction, and
2610 * writes within a string instruction are weakly ordered. So there
2611 * are three writes overall.
2612 *
2613 * As a small optimization, only write the version field in the first
2614 * and third write. The vcpu->pv_time cache is still valid, because the
2615 * version field is the first in the struct.
2616 */
2617 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2618
2619 if (guest_hv_clock.version & 1)
2620 ++guest_hv_clock.version; /* first time write, random junk */
2621
2622 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2623 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2624 &vcpu->hv_clock,
2625 sizeof(vcpu->hv_clock.version));
2626
2627 smp_wmb();
2628
2629 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2630 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2631
2632 if (vcpu->pvclock_set_guest_stopped_request) {
2633 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2634 vcpu->pvclock_set_guest_stopped_request = false;
2635 }
2636
2637 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2638
2639 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2640 &vcpu->hv_clock,
2641 sizeof(vcpu->hv_clock));
2642
2643 smp_wmb();
2644
2645 vcpu->hv_clock.version++;
2646 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2647 &vcpu->hv_clock,
2648 sizeof(vcpu->hv_clock.version));
2649 }
2650
2651 static int kvm_guest_time_update(struct kvm_vcpu *v)
2652 {
2653 unsigned long flags, tgt_tsc_khz;
2654 struct kvm_vcpu_arch *vcpu = &v->arch;
2655 struct kvm_arch *ka = &v->kvm->arch;
2656 s64 kernel_ns;
2657 u64 tsc_timestamp, host_tsc;
2658 u8 pvclock_flags;
2659 bool use_master_clock;
2660
2661 kernel_ns = 0;
2662 host_tsc = 0;
2663
2664 /*
2665 * If the host uses TSC clock, then passthrough TSC as stable
2666 * to the guest.
2667 */
2668 spin_lock(&ka->pvclock_gtod_sync_lock);
2669 use_master_clock = ka->use_master_clock;
2670 if (use_master_clock) {
2671 host_tsc = ka->master_cycle_now;
2672 kernel_ns = ka->master_kernel_ns;
2673 }
2674 spin_unlock(&ka->pvclock_gtod_sync_lock);
2675
2676 /* Keep irq disabled to prevent changes to the clock */
2677 local_irq_save(flags);
2678 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2679 if (unlikely(tgt_tsc_khz == 0)) {
2680 local_irq_restore(flags);
2681 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2682 return 1;
2683 }
2684 if (!use_master_clock) {
2685 host_tsc = rdtsc();
2686 kernel_ns = get_kvmclock_base_ns();
2687 }
2688
2689 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2690
2691 /*
2692 * We may have to catch up the TSC to match elapsed wall clock
2693 * time for two reasons, even if kvmclock is used.
2694 * 1) CPU could have been running below the maximum TSC rate
2695 * 2) Broken TSC compensation resets the base at each VCPU
2696 * entry to avoid unknown leaps of TSC even when running
2697 * again on the same CPU. This may cause apparent elapsed
2698 * time to disappear, and the guest to stand still or run
2699 * very slowly.
2700 */
2701 if (vcpu->tsc_catchup) {
2702 u64 tsc = compute_guest_tsc(v, kernel_ns);
2703 if (tsc > tsc_timestamp) {
2704 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2705 tsc_timestamp = tsc;
2706 }
2707 }
2708
2709 local_irq_restore(flags);
2710
2711 /* With all the info we got, fill in the values */
2712
2713 if (kvm_has_tsc_control)
2714 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2715
2716 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2717 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2718 &vcpu->hv_clock.tsc_shift,
2719 &vcpu->hv_clock.tsc_to_system_mul);
2720 vcpu->hw_tsc_khz = tgt_tsc_khz;
2721 }
2722
2723 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2724 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2725 vcpu->last_guest_tsc = tsc_timestamp;
2726
2727 /* If the host uses TSC clocksource, then it is stable */
2728 pvclock_flags = 0;
2729 if (use_master_clock)
2730 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2731
2732 vcpu->hv_clock.flags = pvclock_flags;
2733
2734 if (vcpu->pv_time_enabled)
2735 kvm_setup_pvclock_page(v);
2736 if (v == kvm_get_vcpu(v->kvm, 0))
2737 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2738 return 0;
2739 }
2740
2741 /*
2742 * kvmclock updates which are isolated to a given vcpu, such as
2743 * vcpu->cpu migration, should not allow system_timestamp from
2744 * the rest of the vcpus to remain static. Otherwise ntp frequency
2745 * correction applies to one vcpu's system_timestamp but not
2746 * the others.
2747 *
2748 * So in those cases, request a kvmclock update for all vcpus.
2749 * We need to rate-limit these requests though, as they can
2750 * considerably slow guests that have a large number of vcpus.
2751 * The time for a remote vcpu to update its kvmclock is bound
2752 * by the delay we use to rate-limit the updates.
2753 */
2754
2755 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2756
2757 static void kvmclock_update_fn(struct work_struct *work)
2758 {
2759 int i;
2760 struct delayed_work *dwork = to_delayed_work(work);
2761 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2762 kvmclock_update_work);
2763 struct kvm *kvm = container_of(ka, struct kvm, arch);
2764 struct kvm_vcpu *vcpu;
2765
2766 kvm_for_each_vcpu(i, vcpu, kvm) {
2767 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2768 kvm_vcpu_kick(vcpu);
2769 }
2770 }
2771
2772 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2773 {
2774 struct kvm *kvm = v->kvm;
2775
2776 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2777 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2778 KVMCLOCK_UPDATE_DELAY);
2779 }
2780
2781 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2782
2783 static void kvmclock_sync_fn(struct work_struct *work)
2784 {
2785 struct delayed_work *dwork = to_delayed_work(work);
2786 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2787 kvmclock_sync_work);
2788 struct kvm *kvm = container_of(ka, struct kvm, arch);
2789
2790 if (!kvmclock_periodic_sync)
2791 return;
2792
2793 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2794 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2795 KVMCLOCK_SYNC_PERIOD);
2796 }
2797
2798 /*
2799 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2800 */
2801 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2802 {
2803 /* McStatusWrEn enabled? */
2804 if (guest_cpuid_is_amd_or_hygon(vcpu))
2805 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2806
2807 return false;
2808 }
2809
2810 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2811 {
2812 u64 mcg_cap = vcpu->arch.mcg_cap;
2813 unsigned bank_num = mcg_cap & 0xff;
2814 u32 msr = msr_info->index;
2815 u64 data = msr_info->data;
2816
2817 switch (msr) {
2818 case MSR_IA32_MCG_STATUS:
2819 vcpu->arch.mcg_status = data;
2820 break;
2821 case MSR_IA32_MCG_CTL:
2822 if (!(mcg_cap & MCG_CTL_P) &&
2823 (data || !msr_info->host_initiated))
2824 return 1;
2825 if (data != 0 && data != ~(u64)0)
2826 return 1;
2827 vcpu->arch.mcg_ctl = data;
2828 break;
2829 default:
2830 if (msr >= MSR_IA32_MC0_CTL &&
2831 msr < MSR_IA32_MCx_CTL(bank_num)) {
2832 u32 offset = array_index_nospec(
2833 msr - MSR_IA32_MC0_CTL,
2834 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2835
2836 /* only 0 or all 1s can be written to IA32_MCi_CTL
2837 * some Linux kernels though clear bit 10 in bank 4 to
2838 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2839 * this to avoid an uncatched #GP in the guest
2840 */
2841 if ((offset & 0x3) == 0 &&
2842 data != 0 && (data | (1 << 10)) != ~(u64)0)
2843 return -1;
2844
2845 /* MCi_STATUS */
2846 if (!msr_info->host_initiated &&
2847 (offset & 0x3) == 1 && data != 0) {
2848 if (!can_set_mci_status(vcpu))
2849 return -1;
2850 }
2851
2852 vcpu->arch.mce_banks[offset] = data;
2853 break;
2854 }
2855 return 1;
2856 }
2857 return 0;
2858 }
2859
2860 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2861 {
2862 struct kvm *kvm = vcpu->kvm;
2863 int lm = is_long_mode(vcpu);
2864 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2865 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2866 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2867 : kvm->arch.xen_hvm_config.blob_size_32;
2868 u32 page_num = data & ~PAGE_MASK;
2869 u64 page_addr = data & PAGE_MASK;
2870 u8 *page;
2871
2872 if (page_num >= blob_size)
2873 return 1;
2874
2875 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2876 if (IS_ERR(page))
2877 return PTR_ERR(page);
2878
2879 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) {
2880 kfree(page);
2881 return 1;
2882 }
2883 return 0;
2884 }
2885
2886 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2887 {
2888 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2889
2890 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2891 }
2892
2893 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2894 {
2895 gpa_t gpa = data & ~0x3f;
2896
2897 /* Bits 4:5 are reserved, Should be zero */
2898 if (data & 0x30)
2899 return 1;
2900
2901 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
2902 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
2903 return 1;
2904
2905 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
2906 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
2907 return 1;
2908
2909 if (!lapic_in_kernel(vcpu))
2910 return data ? 1 : 0;
2911
2912 vcpu->arch.apf.msr_en_val = data;
2913
2914 if (!kvm_pv_async_pf_enabled(vcpu)) {
2915 kvm_clear_async_pf_completion_queue(vcpu);
2916 kvm_async_pf_hash_reset(vcpu);
2917 return 0;
2918 }
2919
2920 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2921 sizeof(u64)))
2922 return 1;
2923
2924 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2925 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2926
2927 kvm_async_pf_wakeup_all(vcpu);
2928
2929 return 0;
2930 }
2931
2932 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2933 {
2934 /* Bits 8-63 are reserved */
2935 if (data >> 8)
2936 return 1;
2937
2938 if (!lapic_in_kernel(vcpu))
2939 return 1;
2940
2941 vcpu->arch.apf.msr_int_val = data;
2942
2943 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2944
2945 return 0;
2946 }
2947
2948 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2949 {
2950 vcpu->arch.pv_time_enabled = false;
2951 vcpu->arch.time = 0;
2952 }
2953
2954 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2955 {
2956 ++vcpu->stat.tlb_flush;
2957 kvm_x86_ops.tlb_flush_all(vcpu);
2958 }
2959
2960 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2961 {
2962 ++vcpu->stat.tlb_flush;
2963 kvm_x86_ops.tlb_flush_guest(vcpu);
2964 }
2965
2966 static void record_steal_time(struct kvm_vcpu *vcpu)
2967 {
2968 struct kvm_host_map map;
2969 struct kvm_steal_time *st;
2970
2971 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2972 return;
2973
2974 /* -EAGAIN is returned in atomic context so we can just return. */
2975 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2976 &map, &vcpu->arch.st.cache, false))
2977 return;
2978
2979 st = map.hva +
2980 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2981
2982 /*
2983 * Doing a TLB flush here, on the guest's behalf, can avoid
2984 * expensive IPIs.
2985 */
2986 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
2987 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2988 st->preempted & KVM_VCPU_FLUSH_TLB);
2989 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2990 kvm_vcpu_flush_tlb_guest(vcpu);
2991 }
2992
2993 vcpu->arch.st.preempted = 0;
2994
2995 if (st->version & 1)
2996 st->version += 1; /* first time write, random junk */
2997
2998 st->version += 1;
2999
3000 smp_wmb();
3001
3002 st->steal += current->sched_info.run_delay -
3003 vcpu->arch.st.last_steal;
3004 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3005
3006 smp_wmb();
3007
3008 st->version += 1;
3009
3010 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
3011 }
3012
3013 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3014 {
3015 bool pr = false;
3016 u32 msr = msr_info->index;
3017 u64 data = msr_info->data;
3018
3019 switch (msr) {
3020 case MSR_AMD64_NB_CFG:
3021 case MSR_IA32_UCODE_WRITE:
3022 case MSR_VM_HSAVE_PA:
3023 case MSR_AMD64_PATCH_LOADER:
3024 case MSR_AMD64_BU_CFG2:
3025 case MSR_AMD64_DC_CFG:
3026 case MSR_F15H_EX_CFG:
3027 break;
3028
3029 case MSR_IA32_UCODE_REV:
3030 if (msr_info->host_initiated)
3031 vcpu->arch.microcode_version = data;
3032 break;
3033 case MSR_IA32_ARCH_CAPABILITIES:
3034 if (!msr_info->host_initiated)
3035 return 1;
3036 vcpu->arch.arch_capabilities = data;
3037 break;
3038 case MSR_IA32_PERF_CAPABILITIES: {
3039 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3040
3041 if (!msr_info->host_initiated)
3042 return 1;
3043 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3044 return 1;
3045 if (data & ~msr_ent.data)
3046 return 1;
3047
3048 vcpu->arch.perf_capabilities = data;
3049
3050 return 0;
3051 }
3052 case MSR_EFER:
3053 return set_efer(vcpu, msr_info);
3054 case MSR_K7_HWCR:
3055 data &= ~(u64)0x40; /* ignore flush filter disable */
3056 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3057 data &= ~(u64)0x8; /* ignore TLB cache disable */
3058
3059 /* Handle McStatusWrEn */
3060 if (data == BIT_ULL(18)) {
3061 vcpu->arch.msr_hwcr = data;
3062 } else if (data != 0) {
3063 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3064 data);
3065 return 1;
3066 }
3067 break;
3068 case MSR_FAM10H_MMIO_CONF_BASE:
3069 if (data != 0) {
3070 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3071 "0x%llx\n", data);
3072 return 1;
3073 }
3074 break;
3075 case MSR_IA32_DEBUGCTLMSR:
3076 if (!data) {
3077 /* We support the non-activated case already */
3078 break;
3079 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
3080 /* Values other than LBR and BTF are vendor-specific,
3081 thus reserved and should throw a #GP */
3082 return 1;
3083 } else if (report_ignored_msrs)
3084 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
3085 __func__, data);
3086 break;
3087 case 0x200 ... 0x2ff:
3088 return kvm_mtrr_set_msr(vcpu, msr, data);
3089 case MSR_IA32_APICBASE:
3090 return kvm_set_apic_base(vcpu, msr_info);
3091 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3092 return kvm_x2apic_msr_write(vcpu, msr, data);
3093 case MSR_IA32_TSCDEADLINE:
3094 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3095 break;
3096 case MSR_IA32_TSC_ADJUST:
3097 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3098 if (!msr_info->host_initiated) {
3099 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3100 adjust_tsc_offset_guest(vcpu, adj);
3101 }
3102 vcpu->arch.ia32_tsc_adjust_msr = data;
3103 }
3104 break;
3105 case MSR_IA32_MISC_ENABLE:
3106 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3107 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3108 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3109 return 1;
3110 vcpu->arch.ia32_misc_enable_msr = data;
3111 kvm_update_cpuid_runtime(vcpu);
3112 } else {
3113 vcpu->arch.ia32_misc_enable_msr = data;
3114 }
3115 break;
3116 case MSR_IA32_SMBASE:
3117 if (!msr_info->host_initiated)
3118 return 1;
3119 vcpu->arch.smbase = data;
3120 break;
3121 case MSR_IA32_POWER_CTL:
3122 vcpu->arch.msr_ia32_power_ctl = data;
3123 break;
3124 case MSR_IA32_TSC:
3125 if (msr_info->host_initiated) {
3126 kvm_synchronize_tsc(vcpu, data);
3127 } else {
3128 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3129 adjust_tsc_offset_guest(vcpu, adj);
3130 vcpu->arch.ia32_tsc_adjust_msr += adj;
3131 }
3132 break;
3133 case MSR_IA32_XSS:
3134 if (!msr_info->host_initiated &&
3135 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3136 return 1;
3137 /*
3138 * KVM supports exposing PT to the guest, but does not support
3139 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3140 * XSAVES/XRSTORS to save/restore PT MSRs.
3141 */
3142 if (data & ~supported_xss)
3143 return 1;
3144 vcpu->arch.ia32_xss = data;
3145 break;
3146 case MSR_SMI_COUNT:
3147 if (!msr_info->host_initiated)
3148 return 1;
3149 vcpu->arch.smi_count = data;
3150 break;
3151 case MSR_KVM_WALL_CLOCK_NEW:
3152 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3153 return 1;
3154
3155 kvm_write_wall_clock(vcpu->kvm, data);
3156 break;
3157 case MSR_KVM_WALL_CLOCK:
3158 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3159 return 1;
3160
3161 kvm_write_wall_clock(vcpu->kvm, data);
3162 break;
3163 case MSR_KVM_SYSTEM_TIME_NEW:
3164 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3165 return 1;
3166
3167 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3168 break;
3169 case MSR_KVM_SYSTEM_TIME:
3170 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3171 return 1;
3172
3173 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3174 break;
3175 case MSR_KVM_ASYNC_PF_EN:
3176 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3177 return 1;
3178
3179 if (kvm_pv_enable_async_pf(vcpu, data))
3180 return 1;
3181 break;
3182 case MSR_KVM_ASYNC_PF_INT:
3183 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3184 return 1;
3185
3186 if (kvm_pv_enable_async_pf_int(vcpu, data))
3187 return 1;
3188 break;
3189 case MSR_KVM_ASYNC_PF_ACK:
3190 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3191 return 1;
3192 if (data & 0x1) {
3193 vcpu->arch.apf.pageready_pending = false;
3194 kvm_check_async_pf_completion(vcpu);
3195 }
3196 break;
3197 case MSR_KVM_STEAL_TIME:
3198 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3199 return 1;
3200
3201 if (unlikely(!sched_info_on()))
3202 return 1;
3203
3204 if (data & KVM_STEAL_RESERVED_MASK)
3205 return 1;
3206
3207 vcpu->arch.st.msr_val = data;
3208
3209 if (!(data & KVM_MSR_ENABLED))
3210 break;
3211
3212 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3213
3214 break;
3215 case MSR_KVM_PV_EOI_EN:
3216 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3217 return 1;
3218
3219 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3220 return 1;
3221 break;
3222
3223 case MSR_KVM_POLL_CONTROL:
3224 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3225 return 1;
3226
3227 /* only enable bit supported */
3228 if (data & (-1ULL << 1))
3229 return 1;
3230
3231 vcpu->arch.msr_kvm_poll_control = data;
3232 break;
3233
3234 case MSR_IA32_MCG_CTL:
3235 case MSR_IA32_MCG_STATUS:
3236 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3237 return set_msr_mce(vcpu, msr_info);
3238
3239 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3240 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3241 pr = true;
3242 fallthrough;
3243 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3244 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3245 if (kvm_pmu_is_valid_msr(vcpu, msr))
3246 return kvm_pmu_set_msr(vcpu, msr_info);
3247
3248 if (pr || data != 0)
3249 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3250 "0x%x data 0x%llx\n", msr, data);
3251 break;
3252 case MSR_K7_CLK_CTL:
3253 /*
3254 * Ignore all writes to this no longer documented MSR.
3255 * Writes are only relevant for old K7 processors,
3256 * all pre-dating SVM, but a recommended workaround from
3257 * AMD for these chips. It is possible to specify the
3258 * affected processor models on the command line, hence
3259 * the need to ignore the workaround.
3260 */
3261 break;
3262 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3263 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3264 case HV_X64_MSR_SYNDBG_OPTIONS:
3265 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3266 case HV_X64_MSR_CRASH_CTL:
3267 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3268 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3269 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3270 case HV_X64_MSR_TSC_EMULATION_STATUS:
3271 return kvm_hv_set_msr_common(vcpu, msr, data,
3272 msr_info->host_initiated);
3273 case MSR_IA32_BBL_CR_CTL3:
3274 /* Drop writes to this legacy MSR -- see rdmsr
3275 * counterpart for further detail.
3276 */
3277 if (report_ignored_msrs)
3278 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3279 msr, data);
3280 break;
3281 case MSR_AMD64_OSVW_ID_LENGTH:
3282 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3283 return 1;
3284 vcpu->arch.osvw.length = data;
3285 break;
3286 case MSR_AMD64_OSVW_STATUS:
3287 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3288 return 1;
3289 vcpu->arch.osvw.status = data;
3290 break;
3291 case MSR_PLATFORM_INFO:
3292 if (!msr_info->host_initiated ||
3293 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3294 cpuid_fault_enabled(vcpu)))
3295 return 1;
3296 vcpu->arch.msr_platform_info = data;
3297 break;
3298 case MSR_MISC_FEATURES_ENABLES:
3299 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3300 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3301 !supports_cpuid_fault(vcpu)))
3302 return 1;
3303 vcpu->arch.msr_misc_features_enables = data;
3304 break;
3305 default:
3306 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3307 return xen_hvm_config(vcpu, data);
3308 if (kvm_pmu_is_valid_msr(vcpu, msr))
3309 return kvm_pmu_set_msr(vcpu, msr_info);
3310 return KVM_MSR_RET_INVALID;
3311 }
3312 return 0;
3313 }
3314 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3315
3316 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3317 {
3318 u64 data;
3319 u64 mcg_cap = vcpu->arch.mcg_cap;
3320 unsigned bank_num = mcg_cap & 0xff;
3321
3322 switch (msr) {
3323 case MSR_IA32_P5_MC_ADDR:
3324 case MSR_IA32_P5_MC_TYPE:
3325 data = 0;
3326 break;
3327 case MSR_IA32_MCG_CAP:
3328 data = vcpu->arch.mcg_cap;
3329 break;
3330 case MSR_IA32_MCG_CTL:
3331 if (!(mcg_cap & MCG_CTL_P) && !host)
3332 return 1;
3333 data = vcpu->arch.mcg_ctl;
3334 break;
3335 case MSR_IA32_MCG_STATUS:
3336 data = vcpu->arch.mcg_status;
3337 break;
3338 default:
3339 if (msr >= MSR_IA32_MC0_CTL &&
3340 msr < MSR_IA32_MCx_CTL(bank_num)) {
3341 u32 offset = array_index_nospec(
3342 msr - MSR_IA32_MC0_CTL,
3343 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3344
3345 data = vcpu->arch.mce_banks[offset];
3346 break;
3347 }
3348 return 1;
3349 }
3350 *pdata = data;
3351 return 0;
3352 }
3353
3354 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3355 {
3356 switch (msr_info->index) {
3357 case MSR_IA32_PLATFORM_ID:
3358 case MSR_IA32_EBL_CR_POWERON:
3359 case MSR_IA32_DEBUGCTLMSR:
3360 case MSR_IA32_LASTBRANCHFROMIP:
3361 case MSR_IA32_LASTBRANCHTOIP:
3362 case MSR_IA32_LASTINTFROMIP:
3363 case MSR_IA32_LASTINTTOIP:
3364 case MSR_K8_SYSCFG:
3365 case MSR_K8_TSEG_ADDR:
3366 case MSR_K8_TSEG_MASK:
3367 case MSR_VM_HSAVE_PA:
3368 case MSR_K8_INT_PENDING_MSG:
3369 case MSR_AMD64_NB_CFG:
3370 case MSR_FAM10H_MMIO_CONF_BASE:
3371 case MSR_AMD64_BU_CFG2:
3372 case MSR_IA32_PERF_CTL:
3373 case MSR_AMD64_DC_CFG:
3374 case MSR_F15H_EX_CFG:
3375 /*
3376 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3377 * limit) MSRs. Just return 0, as we do not want to expose the host
3378 * data here. Do not conditionalize this on CPUID, as KVM does not do
3379 * so for existing CPU-specific MSRs.
3380 */
3381 case MSR_RAPL_POWER_UNIT:
3382 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3383 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3384 case MSR_PKG_ENERGY_STATUS: /* Total package */
3385 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3386 msr_info->data = 0;
3387 break;
3388 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3389 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3390 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3391 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3392 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3393 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3394 return kvm_pmu_get_msr(vcpu, msr_info);
3395 msr_info->data = 0;
3396 break;
3397 case MSR_IA32_UCODE_REV:
3398 msr_info->data = vcpu->arch.microcode_version;
3399 break;
3400 case MSR_IA32_ARCH_CAPABILITIES:
3401 if (!msr_info->host_initiated &&
3402 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3403 return 1;
3404 msr_info->data = vcpu->arch.arch_capabilities;
3405 break;
3406 case MSR_IA32_PERF_CAPABILITIES:
3407 if (!msr_info->host_initiated &&
3408 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3409 return 1;
3410 msr_info->data = vcpu->arch.perf_capabilities;
3411 break;
3412 case MSR_IA32_POWER_CTL:
3413 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3414 break;
3415 case MSR_IA32_TSC: {
3416 /*
3417 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3418 * even when not intercepted. AMD manual doesn't explicitly
3419 * state this but appears to behave the same.
3420 *
3421 * On userspace reads and writes, however, we unconditionally
3422 * return L1's TSC value to ensure backwards-compatible
3423 * behavior for migration.
3424 */
3425 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3426 vcpu->arch.tsc_offset;
3427
3428 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3429 break;
3430 }
3431 case MSR_MTRRcap:
3432 case 0x200 ... 0x2ff:
3433 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3434 case 0xcd: /* fsb frequency */
3435 msr_info->data = 3;
3436 break;
3437 /*
3438 * MSR_EBC_FREQUENCY_ID
3439 * Conservative value valid for even the basic CPU models.
3440 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3441 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3442 * and 266MHz for model 3, or 4. Set Core Clock
3443 * Frequency to System Bus Frequency Ratio to 1 (bits
3444 * 31:24) even though these are only valid for CPU
3445 * models > 2, however guests may end up dividing or
3446 * multiplying by zero otherwise.
3447 */
3448 case MSR_EBC_FREQUENCY_ID:
3449 msr_info->data = 1 << 24;
3450 break;
3451 case MSR_IA32_APICBASE:
3452 msr_info->data = kvm_get_apic_base(vcpu);
3453 break;
3454 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3455 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3456 case MSR_IA32_TSCDEADLINE:
3457 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3458 break;
3459 case MSR_IA32_TSC_ADJUST:
3460 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3461 break;
3462 case MSR_IA32_MISC_ENABLE:
3463 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3464 break;
3465 case MSR_IA32_SMBASE:
3466 if (!msr_info->host_initiated)
3467 return 1;
3468 msr_info->data = vcpu->arch.smbase;
3469 break;
3470 case MSR_SMI_COUNT:
3471 msr_info->data = vcpu->arch.smi_count;
3472 break;
3473 case MSR_IA32_PERF_STATUS:
3474 /* TSC increment by tick */
3475 msr_info->data = 1000ULL;
3476 /* CPU multiplier */
3477 msr_info->data |= (((uint64_t)4ULL) << 40);
3478 break;
3479 case MSR_EFER:
3480 msr_info->data = vcpu->arch.efer;
3481 break;
3482 case MSR_KVM_WALL_CLOCK:
3483 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3484 return 1;
3485
3486 msr_info->data = vcpu->kvm->arch.wall_clock;
3487 break;
3488 case MSR_KVM_WALL_CLOCK_NEW:
3489 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3490 return 1;
3491
3492 msr_info->data = vcpu->kvm->arch.wall_clock;
3493 break;
3494 case MSR_KVM_SYSTEM_TIME:
3495 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3496 return 1;
3497
3498 msr_info->data = vcpu->arch.time;
3499 break;
3500 case MSR_KVM_SYSTEM_TIME_NEW:
3501 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3502 return 1;
3503
3504 msr_info->data = vcpu->arch.time;
3505 break;
3506 case MSR_KVM_ASYNC_PF_EN:
3507 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3508 return 1;
3509
3510 msr_info->data = vcpu->arch.apf.msr_en_val;
3511 break;
3512 case MSR_KVM_ASYNC_PF_INT:
3513 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3514 return 1;
3515
3516 msr_info->data = vcpu->arch.apf.msr_int_val;
3517 break;
3518 case MSR_KVM_ASYNC_PF_ACK:
3519 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3520 return 1;
3521
3522 msr_info->data = 0;
3523 break;
3524 case MSR_KVM_STEAL_TIME:
3525 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3526 return 1;
3527
3528 msr_info->data = vcpu->arch.st.msr_val;
3529 break;
3530 case MSR_KVM_PV_EOI_EN:
3531 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3532 return 1;
3533
3534 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3535 break;
3536 case MSR_KVM_POLL_CONTROL:
3537 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3538 return 1;
3539
3540 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3541 break;
3542 case MSR_IA32_P5_MC_ADDR:
3543 case MSR_IA32_P5_MC_TYPE:
3544 case MSR_IA32_MCG_CAP:
3545 case MSR_IA32_MCG_CTL:
3546 case MSR_IA32_MCG_STATUS:
3547 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3548 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3549 msr_info->host_initiated);
3550 case MSR_IA32_XSS:
3551 if (!msr_info->host_initiated &&
3552 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3553 return 1;
3554 msr_info->data = vcpu->arch.ia32_xss;
3555 break;
3556 case MSR_K7_CLK_CTL:
3557 /*
3558 * Provide expected ramp-up count for K7. All other
3559 * are set to zero, indicating minimum divisors for
3560 * every field.
3561 *
3562 * This prevents guest kernels on AMD host with CPU
3563 * type 6, model 8 and higher from exploding due to
3564 * the rdmsr failing.
3565 */
3566 msr_info->data = 0x20000000;
3567 break;
3568 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3569 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3570 case HV_X64_MSR_SYNDBG_OPTIONS:
3571 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3572 case HV_X64_MSR_CRASH_CTL:
3573 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3574 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3575 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3576 case HV_X64_MSR_TSC_EMULATION_STATUS:
3577 return kvm_hv_get_msr_common(vcpu,
3578 msr_info->index, &msr_info->data,
3579 msr_info->host_initiated);
3580 case MSR_IA32_BBL_CR_CTL3:
3581 /* This legacy MSR exists but isn't fully documented in current
3582 * silicon. It is however accessed by winxp in very narrow
3583 * scenarios where it sets bit #19, itself documented as
3584 * a "reserved" bit. Best effort attempt to source coherent
3585 * read data here should the balance of the register be
3586 * interpreted by the guest:
3587 *
3588 * L2 cache control register 3: 64GB range, 256KB size,
3589 * enabled, latency 0x1, configured
3590 */
3591 msr_info->data = 0xbe702111;
3592 break;
3593 case MSR_AMD64_OSVW_ID_LENGTH:
3594 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3595 return 1;
3596 msr_info->data = vcpu->arch.osvw.length;
3597 break;
3598 case MSR_AMD64_OSVW_STATUS:
3599 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3600 return 1;
3601 msr_info->data = vcpu->arch.osvw.status;
3602 break;
3603 case MSR_PLATFORM_INFO:
3604 if (!msr_info->host_initiated &&
3605 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3606 return 1;
3607 msr_info->data = vcpu->arch.msr_platform_info;
3608 break;
3609 case MSR_MISC_FEATURES_ENABLES:
3610 msr_info->data = vcpu->arch.msr_misc_features_enables;
3611 break;
3612 case MSR_K7_HWCR:
3613 msr_info->data = vcpu->arch.msr_hwcr;
3614 break;
3615 default:
3616 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3617 return kvm_pmu_get_msr(vcpu, msr_info);
3618 return KVM_MSR_RET_INVALID;
3619 }
3620 return 0;
3621 }
3622 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3623
3624 /*
3625 * Read or write a bunch of msrs. All parameters are kernel addresses.
3626 *
3627 * @return number of msrs set successfully.
3628 */
3629 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3630 struct kvm_msr_entry *entries,
3631 int (*do_msr)(struct kvm_vcpu *vcpu,
3632 unsigned index, u64 *data))
3633 {
3634 int i;
3635
3636 for (i = 0; i < msrs->nmsrs; ++i)
3637 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3638 break;
3639
3640 return i;
3641 }
3642
3643 /*
3644 * Read or write a bunch of msrs. Parameters are user addresses.
3645 *
3646 * @return number of msrs set successfully.
3647 */
3648 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3649 int (*do_msr)(struct kvm_vcpu *vcpu,
3650 unsigned index, u64 *data),
3651 int writeback)
3652 {
3653 struct kvm_msrs msrs;
3654 struct kvm_msr_entry *entries;
3655 int r, n;
3656 unsigned size;
3657
3658 r = -EFAULT;
3659 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3660 goto out;
3661
3662 r = -E2BIG;
3663 if (msrs.nmsrs >= MAX_IO_MSRS)
3664 goto out;
3665
3666 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3667 entries = memdup_user(user_msrs->entries, size);
3668 if (IS_ERR(entries)) {
3669 r = PTR_ERR(entries);
3670 goto out;
3671 }
3672
3673 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3674 if (r < 0)
3675 goto out_free;
3676
3677 r = -EFAULT;
3678 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3679 goto out_free;
3680
3681 r = n;
3682
3683 out_free:
3684 kfree(entries);
3685 out:
3686 return r;
3687 }
3688
3689 static inline bool kvm_can_mwait_in_guest(void)
3690 {
3691 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3692 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3693 boot_cpu_has(X86_FEATURE_ARAT);
3694 }
3695
3696 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
3697 struct kvm_cpuid2 __user *cpuid_arg)
3698 {
3699 struct kvm_cpuid2 cpuid;
3700 int r;
3701
3702 r = -EFAULT;
3703 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3704 return r;
3705
3706 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3707 if (r)
3708 return r;
3709
3710 r = -EFAULT;
3711 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3712 return r;
3713
3714 return 0;
3715 }
3716
3717 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3718 {
3719 int r = 0;
3720
3721 switch (ext) {
3722 case KVM_CAP_IRQCHIP:
3723 case KVM_CAP_HLT:
3724 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3725 case KVM_CAP_SET_TSS_ADDR:
3726 case KVM_CAP_EXT_CPUID:
3727 case KVM_CAP_EXT_EMUL_CPUID:
3728 case KVM_CAP_CLOCKSOURCE:
3729 case KVM_CAP_PIT:
3730 case KVM_CAP_NOP_IO_DELAY:
3731 case KVM_CAP_MP_STATE:
3732 case KVM_CAP_SYNC_MMU:
3733 case KVM_CAP_USER_NMI:
3734 case KVM_CAP_REINJECT_CONTROL:
3735 case KVM_CAP_IRQ_INJECT_STATUS:
3736 case KVM_CAP_IOEVENTFD:
3737 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3738 case KVM_CAP_PIT2:
3739 case KVM_CAP_PIT_STATE2:
3740 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3741 case KVM_CAP_XEN_HVM:
3742 case KVM_CAP_VCPU_EVENTS:
3743 case KVM_CAP_HYPERV:
3744 case KVM_CAP_HYPERV_VAPIC:
3745 case KVM_CAP_HYPERV_SPIN:
3746 case KVM_CAP_HYPERV_SYNIC:
3747 case KVM_CAP_HYPERV_SYNIC2:
3748 case KVM_CAP_HYPERV_VP_INDEX:
3749 case KVM_CAP_HYPERV_EVENTFD:
3750 case KVM_CAP_HYPERV_TLBFLUSH:
3751 case KVM_CAP_HYPERV_SEND_IPI:
3752 case KVM_CAP_HYPERV_CPUID:
3753 case KVM_CAP_SYS_HYPERV_CPUID:
3754 case KVM_CAP_PCI_SEGMENT:
3755 case KVM_CAP_DEBUGREGS:
3756 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3757 case KVM_CAP_XSAVE:
3758 case KVM_CAP_ASYNC_PF:
3759 case KVM_CAP_ASYNC_PF_INT:
3760 case KVM_CAP_GET_TSC_KHZ:
3761 case KVM_CAP_KVMCLOCK_CTRL:
3762 case KVM_CAP_READONLY_MEM:
3763 case KVM_CAP_HYPERV_TIME:
3764 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3765 case KVM_CAP_TSC_DEADLINE_TIMER:
3766 case KVM_CAP_DISABLE_QUIRKS:
3767 case KVM_CAP_SET_BOOT_CPU_ID:
3768 case KVM_CAP_SPLIT_IRQCHIP:
3769 case KVM_CAP_IMMEDIATE_EXIT:
3770 case KVM_CAP_PMU_EVENT_FILTER:
3771 case KVM_CAP_GET_MSR_FEATURES:
3772 case KVM_CAP_MSR_PLATFORM_INFO:
3773 case KVM_CAP_EXCEPTION_PAYLOAD:
3774 case KVM_CAP_SET_GUEST_DEBUG:
3775 case KVM_CAP_LAST_CPU:
3776 case KVM_CAP_X86_USER_SPACE_MSR:
3777 case KVM_CAP_X86_MSR_FILTER:
3778 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
3779 r = 1;
3780 break;
3781 case KVM_CAP_SYNC_REGS:
3782 r = KVM_SYNC_X86_VALID_FIELDS;
3783 break;
3784 case KVM_CAP_ADJUST_CLOCK:
3785 r = KVM_CLOCK_TSC_STABLE;
3786 break;
3787 case KVM_CAP_X86_DISABLE_EXITS:
3788 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3789 KVM_X86_DISABLE_EXITS_CSTATE;
3790 if(kvm_can_mwait_in_guest())
3791 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3792 break;
3793 case KVM_CAP_X86_SMM:
3794 /* SMBASE is usually relocated above 1M on modern chipsets,
3795 * and SMM handlers might indeed rely on 4G segment limits,
3796 * so do not report SMM to be available if real mode is
3797 * emulated via vm86 mode. Still, do not go to great lengths
3798 * to avoid userspace's usage of the feature, because it is a
3799 * fringe case that is not enabled except via specific settings
3800 * of the module parameters.
3801 */
3802 r = kvm_x86_ops.has_emulated_msr(kvm, MSR_IA32_SMBASE);
3803 break;
3804 case KVM_CAP_VAPIC:
3805 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3806 break;
3807 case KVM_CAP_NR_VCPUS:
3808 r = KVM_SOFT_MAX_VCPUS;
3809 break;
3810 case KVM_CAP_MAX_VCPUS:
3811 r = KVM_MAX_VCPUS;
3812 break;
3813 case KVM_CAP_MAX_VCPU_ID:
3814 r = KVM_MAX_VCPU_ID;
3815 break;
3816 case KVM_CAP_PV_MMU: /* obsolete */
3817 r = 0;
3818 break;
3819 case KVM_CAP_MCE:
3820 r = KVM_MAX_MCE_BANKS;
3821 break;
3822 case KVM_CAP_XCRS:
3823 r = boot_cpu_has(X86_FEATURE_XSAVE);
3824 break;
3825 case KVM_CAP_TSC_CONTROL:
3826 r = kvm_has_tsc_control;
3827 break;
3828 case KVM_CAP_X2APIC_API:
3829 r = KVM_X2APIC_API_VALID_FLAGS;
3830 break;
3831 case KVM_CAP_NESTED_STATE:
3832 r = kvm_x86_ops.nested_ops->get_state ?
3833 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3834 break;
3835 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3836 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3837 break;
3838 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3839 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3840 break;
3841 case KVM_CAP_SMALLER_MAXPHYADDR:
3842 r = (int) allow_smaller_maxphyaddr;
3843 break;
3844 case KVM_CAP_STEAL_TIME:
3845 r = sched_info_on();
3846 break;
3847 default:
3848 break;
3849 }
3850 return r;
3851
3852 }
3853
3854 long kvm_arch_dev_ioctl(struct file *filp,
3855 unsigned int ioctl, unsigned long arg)
3856 {
3857 void __user *argp = (void __user *)arg;
3858 long r;
3859
3860 switch (ioctl) {
3861 case KVM_GET_MSR_INDEX_LIST: {
3862 struct kvm_msr_list __user *user_msr_list = argp;
3863 struct kvm_msr_list msr_list;
3864 unsigned n;
3865
3866 r = -EFAULT;
3867 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3868 goto out;
3869 n = msr_list.nmsrs;
3870 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3871 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3872 goto out;
3873 r = -E2BIG;
3874 if (n < msr_list.nmsrs)
3875 goto out;
3876 r = -EFAULT;
3877 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3878 num_msrs_to_save * sizeof(u32)))
3879 goto out;
3880 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3881 &emulated_msrs,
3882 num_emulated_msrs * sizeof(u32)))
3883 goto out;
3884 r = 0;
3885 break;
3886 }
3887 case KVM_GET_SUPPORTED_CPUID:
3888 case KVM_GET_EMULATED_CPUID: {
3889 struct kvm_cpuid2 __user *cpuid_arg = argp;
3890 struct kvm_cpuid2 cpuid;
3891
3892 r = -EFAULT;
3893 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3894 goto out;
3895
3896 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3897 ioctl);
3898 if (r)
3899 goto out;
3900
3901 r = -EFAULT;
3902 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3903 goto out;
3904 r = 0;
3905 break;
3906 }
3907 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3908 r = -EFAULT;
3909 if (copy_to_user(argp, &kvm_mce_cap_supported,
3910 sizeof(kvm_mce_cap_supported)))
3911 goto out;
3912 r = 0;
3913 break;
3914 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3915 struct kvm_msr_list __user *user_msr_list = argp;
3916 struct kvm_msr_list msr_list;
3917 unsigned int n;
3918
3919 r = -EFAULT;
3920 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3921 goto out;
3922 n = msr_list.nmsrs;
3923 msr_list.nmsrs = num_msr_based_features;
3924 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3925 goto out;
3926 r = -E2BIG;
3927 if (n < msr_list.nmsrs)
3928 goto out;
3929 r = -EFAULT;
3930 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3931 num_msr_based_features * sizeof(u32)))
3932 goto out;
3933 r = 0;
3934 break;
3935 }
3936 case KVM_GET_MSRS:
3937 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3938 break;
3939 case KVM_GET_SUPPORTED_HV_CPUID:
3940 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
3941 break;
3942 default:
3943 r = -EINVAL;
3944 break;
3945 }
3946 out:
3947 return r;
3948 }
3949
3950 static void wbinvd_ipi(void *garbage)
3951 {
3952 wbinvd();
3953 }
3954
3955 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3956 {
3957 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3958 }
3959
3960 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3961 {
3962 /* Address WBINVD may be executed by guest */
3963 if (need_emulate_wbinvd(vcpu)) {
3964 if (kvm_x86_ops.has_wbinvd_exit())
3965 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3966 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3967 smp_call_function_single(vcpu->cpu,
3968 wbinvd_ipi, NULL, 1);
3969 }
3970
3971 kvm_x86_ops.vcpu_load(vcpu, cpu);
3972
3973 /* Save host pkru register if supported */
3974 vcpu->arch.host_pkru = read_pkru();
3975
3976 /* Apply any externally detected TSC adjustments (due to suspend) */
3977 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3978 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3979 vcpu->arch.tsc_offset_adjustment = 0;
3980 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3981 }
3982
3983 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3984 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3985 rdtsc() - vcpu->arch.last_host_tsc;
3986 if (tsc_delta < 0)
3987 mark_tsc_unstable("KVM discovered backwards TSC");
3988
3989 if (kvm_check_tsc_unstable()) {
3990 u64 offset = kvm_compute_tsc_offset(vcpu,
3991 vcpu->arch.last_guest_tsc);
3992 kvm_vcpu_write_tsc_offset(vcpu, offset);
3993 vcpu->arch.tsc_catchup = 1;
3994 }
3995
3996 if (kvm_lapic_hv_timer_in_use(vcpu))
3997 kvm_lapic_restart_hv_timer(vcpu);
3998
3999 /*
4000 * On a host with synchronized TSC, there is no need to update
4001 * kvmclock on vcpu->cpu migration
4002 */
4003 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4004 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4005 if (vcpu->cpu != cpu)
4006 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4007 vcpu->cpu = cpu;
4008 }
4009
4010 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4011 }
4012
4013 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4014 {
4015 struct kvm_host_map map;
4016 struct kvm_steal_time *st;
4017
4018 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4019 return;
4020
4021 if (vcpu->arch.st.preempted)
4022 return;
4023
4024 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
4025 &vcpu->arch.st.cache, true))
4026 return;
4027
4028 st = map.hva +
4029 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
4030
4031 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4032
4033 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
4034 }
4035
4036 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4037 {
4038 int idx;
4039
4040 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4041 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
4042
4043 /*
4044 * Disable page faults because we're in atomic context here.
4045 * kvm_write_guest_offset_cached() would call might_fault()
4046 * that relies on pagefault_disable() to tell if there's a
4047 * bug. NOTE: the write to guest memory may not go through if
4048 * during postcopy live migration or if there's heavy guest
4049 * paging.
4050 */
4051 pagefault_disable();
4052 /*
4053 * kvm_memslots() will be called by
4054 * kvm_write_guest_offset_cached() so take the srcu lock.
4055 */
4056 idx = srcu_read_lock(&vcpu->kvm->srcu);
4057 kvm_steal_time_set_preempted(vcpu);
4058 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4059 pagefault_enable();
4060 kvm_x86_ops.vcpu_put(vcpu);
4061 vcpu->arch.last_host_tsc = rdtsc();
4062 /*
4063 * If userspace has set any breakpoints or watchpoints, dr6 is restored
4064 * on every vmexit, but if not, we might have a stale dr6 from the
4065 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
4066 */
4067 set_debugreg(0, 6);
4068 }
4069
4070 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4071 struct kvm_lapic_state *s)
4072 {
4073 if (vcpu->arch.apicv_active)
4074 kvm_x86_ops.sync_pir_to_irr(vcpu);
4075
4076 return kvm_apic_get_state(vcpu, s);
4077 }
4078
4079 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4080 struct kvm_lapic_state *s)
4081 {
4082 int r;
4083
4084 r = kvm_apic_set_state(vcpu, s);
4085 if (r)
4086 return r;
4087 update_cr8_intercept(vcpu);
4088
4089 return 0;
4090 }
4091
4092 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4093 {
4094 /*
4095 * We can accept userspace's request for interrupt injection
4096 * as long as we have a place to store the interrupt number.
4097 * The actual injection will happen when the CPU is able to
4098 * deliver the interrupt.
4099 */
4100 if (kvm_cpu_has_extint(vcpu))
4101 return false;
4102
4103 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4104 return (!lapic_in_kernel(vcpu) ||
4105 kvm_apic_accept_pic_intr(vcpu));
4106 }
4107
4108 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4109 {
4110 return kvm_arch_interrupt_allowed(vcpu) &&
4111 kvm_cpu_accept_dm_intr(vcpu);
4112 }
4113
4114 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4115 struct kvm_interrupt *irq)
4116 {
4117 if (irq->irq >= KVM_NR_INTERRUPTS)
4118 return -EINVAL;
4119
4120 if (!irqchip_in_kernel(vcpu->kvm)) {
4121 kvm_queue_interrupt(vcpu, irq->irq, false);
4122 kvm_make_request(KVM_REQ_EVENT, vcpu);
4123 return 0;
4124 }
4125
4126 /*
4127 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4128 * fail for in-kernel 8259.
4129 */
4130 if (pic_in_kernel(vcpu->kvm))
4131 return -ENXIO;
4132
4133 if (vcpu->arch.pending_external_vector != -1)
4134 return -EEXIST;
4135
4136 vcpu->arch.pending_external_vector = irq->irq;
4137 kvm_make_request(KVM_REQ_EVENT, vcpu);
4138 return 0;
4139 }
4140
4141 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4142 {
4143 kvm_inject_nmi(vcpu);
4144
4145 return 0;
4146 }
4147
4148 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4149 {
4150 kvm_make_request(KVM_REQ_SMI, vcpu);
4151
4152 return 0;
4153 }
4154
4155 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4156 struct kvm_tpr_access_ctl *tac)
4157 {
4158 if (tac->flags)
4159 return -EINVAL;
4160 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4161 return 0;
4162 }
4163
4164 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4165 u64 mcg_cap)
4166 {
4167 int r;
4168 unsigned bank_num = mcg_cap & 0xff, bank;
4169
4170 r = -EINVAL;
4171 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4172 goto out;
4173 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4174 goto out;
4175 r = 0;
4176 vcpu->arch.mcg_cap = mcg_cap;
4177 /* Init IA32_MCG_CTL to all 1s */
4178 if (mcg_cap & MCG_CTL_P)
4179 vcpu->arch.mcg_ctl = ~(u64)0;
4180 /* Init IA32_MCi_CTL to all 1s */
4181 for (bank = 0; bank < bank_num; bank++)
4182 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4183
4184 kvm_x86_ops.setup_mce(vcpu);
4185 out:
4186 return r;
4187 }
4188
4189 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4190 struct kvm_x86_mce *mce)
4191 {
4192 u64 mcg_cap = vcpu->arch.mcg_cap;
4193 unsigned bank_num = mcg_cap & 0xff;
4194 u64 *banks = vcpu->arch.mce_banks;
4195
4196 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4197 return -EINVAL;
4198 /*
4199 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4200 * reporting is disabled
4201 */
4202 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4203 vcpu->arch.mcg_ctl != ~(u64)0)
4204 return 0;
4205 banks += 4 * mce->bank;
4206 /*
4207 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4208 * reporting is disabled for the bank
4209 */
4210 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4211 return 0;
4212 if (mce->status & MCI_STATUS_UC) {
4213 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4214 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4215 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4216 return 0;
4217 }
4218 if (banks[1] & MCI_STATUS_VAL)
4219 mce->status |= MCI_STATUS_OVER;
4220 banks[2] = mce->addr;
4221 banks[3] = mce->misc;
4222 vcpu->arch.mcg_status = mce->mcg_status;
4223 banks[1] = mce->status;
4224 kvm_queue_exception(vcpu, MC_VECTOR);
4225 } else if (!(banks[1] & MCI_STATUS_VAL)
4226 || !(banks[1] & MCI_STATUS_UC)) {
4227 if (banks[1] & MCI_STATUS_VAL)
4228 mce->status |= MCI_STATUS_OVER;
4229 banks[2] = mce->addr;
4230 banks[3] = mce->misc;
4231 banks[1] = mce->status;
4232 } else
4233 banks[1] |= MCI_STATUS_OVER;
4234 return 0;
4235 }
4236
4237 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4238 struct kvm_vcpu_events *events)
4239 {
4240 process_nmi(vcpu);
4241
4242 if (kvm_check_request(KVM_REQ_SMI, vcpu))
4243 process_smi(vcpu);
4244
4245 /*
4246 * In guest mode, payload delivery should be deferred,
4247 * so that the L1 hypervisor can intercept #PF before
4248 * CR2 is modified (or intercept #DB before DR6 is
4249 * modified under nVMX). Unless the per-VM capability,
4250 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4251 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4252 * opportunistically defer the exception payload, deliver it if the
4253 * capability hasn't been requested before processing a
4254 * KVM_GET_VCPU_EVENTS.
4255 */
4256 if (!vcpu->kvm->arch.exception_payload_enabled &&
4257 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4258 kvm_deliver_exception_payload(vcpu);
4259
4260 /*
4261 * The API doesn't provide the instruction length for software
4262 * exceptions, so don't report them. As long as the guest RIP
4263 * isn't advanced, we should expect to encounter the exception
4264 * again.
4265 */
4266 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4267 events->exception.injected = 0;
4268 events->exception.pending = 0;
4269 } else {
4270 events->exception.injected = vcpu->arch.exception.injected;
4271 events->exception.pending = vcpu->arch.exception.pending;
4272 /*
4273 * For ABI compatibility, deliberately conflate
4274 * pending and injected exceptions when
4275 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4276 */
4277 if (!vcpu->kvm->arch.exception_payload_enabled)
4278 events->exception.injected |=
4279 vcpu->arch.exception.pending;
4280 }
4281 events->exception.nr = vcpu->arch.exception.nr;
4282 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4283 events->exception.error_code = vcpu->arch.exception.error_code;
4284 events->exception_has_payload = vcpu->arch.exception.has_payload;
4285 events->exception_payload = vcpu->arch.exception.payload;
4286
4287 events->interrupt.injected =
4288 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4289 events->interrupt.nr = vcpu->arch.interrupt.nr;
4290 events->interrupt.soft = 0;
4291 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4292
4293 events->nmi.injected = vcpu->arch.nmi_injected;
4294 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4295 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4296 events->nmi.pad = 0;
4297
4298 events->sipi_vector = 0; /* never valid when reporting to user space */
4299
4300 events->smi.smm = is_smm(vcpu);
4301 events->smi.pending = vcpu->arch.smi_pending;
4302 events->smi.smm_inside_nmi =
4303 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4304 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4305
4306 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4307 | KVM_VCPUEVENT_VALID_SHADOW
4308 | KVM_VCPUEVENT_VALID_SMM);
4309 if (vcpu->kvm->arch.exception_payload_enabled)
4310 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4311
4312 memset(&events->reserved, 0, sizeof(events->reserved));
4313 }
4314
4315 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4316
4317 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4318 struct kvm_vcpu_events *events)
4319 {
4320 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4321 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4322 | KVM_VCPUEVENT_VALID_SHADOW
4323 | KVM_VCPUEVENT_VALID_SMM
4324 | KVM_VCPUEVENT_VALID_PAYLOAD))
4325 return -EINVAL;
4326
4327 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4328 if (!vcpu->kvm->arch.exception_payload_enabled)
4329 return -EINVAL;
4330 if (events->exception.pending)
4331 events->exception.injected = 0;
4332 else
4333 events->exception_has_payload = 0;
4334 } else {
4335 events->exception.pending = 0;
4336 events->exception_has_payload = 0;
4337 }
4338
4339 if ((events->exception.injected || events->exception.pending) &&
4340 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4341 return -EINVAL;
4342
4343 /* INITs are latched while in SMM */
4344 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4345 (events->smi.smm || events->smi.pending) &&
4346 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4347 return -EINVAL;
4348
4349 process_nmi(vcpu);
4350 vcpu->arch.exception.injected = events->exception.injected;
4351 vcpu->arch.exception.pending = events->exception.pending;
4352 vcpu->arch.exception.nr = events->exception.nr;
4353 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4354 vcpu->arch.exception.error_code = events->exception.error_code;
4355 vcpu->arch.exception.has_payload = events->exception_has_payload;
4356 vcpu->arch.exception.payload = events->exception_payload;
4357
4358 vcpu->arch.interrupt.injected = events->interrupt.injected;
4359 vcpu->arch.interrupt.nr = events->interrupt.nr;
4360 vcpu->arch.interrupt.soft = events->interrupt.soft;
4361 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4362 kvm_x86_ops.set_interrupt_shadow(vcpu,
4363 events->interrupt.shadow);
4364
4365 vcpu->arch.nmi_injected = events->nmi.injected;
4366 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4367 vcpu->arch.nmi_pending = events->nmi.pending;
4368 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4369
4370 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4371 lapic_in_kernel(vcpu))
4372 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4373
4374 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4375 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4376 if (events->smi.smm)
4377 vcpu->arch.hflags |= HF_SMM_MASK;
4378 else
4379 vcpu->arch.hflags &= ~HF_SMM_MASK;
4380 kvm_smm_changed(vcpu);
4381 }
4382
4383 vcpu->arch.smi_pending = events->smi.pending;
4384
4385 if (events->smi.smm) {
4386 if (events->smi.smm_inside_nmi)
4387 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4388 else
4389 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4390 }
4391
4392 if (lapic_in_kernel(vcpu)) {
4393 if (events->smi.latched_init)
4394 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4395 else
4396 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4397 }
4398 }
4399
4400 kvm_make_request(KVM_REQ_EVENT, vcpu);
4401
4402 return 0;
4403 }
4404
4405 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4406 struct kvm_debugregs *dbgregs)
4407 {
4408 unsigned long val;
4409
4410 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4411 kvm_get_dr(vcpu, 6, &val);
4412 dbgregs->dr6 = val;
4413 dbgregs->dr7 = vcpu->arch.dr7;
4414 dbgregs->flags = 0;
4415 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4416 }
4417
4418 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4419 struct kvm_debugregs *dbgregs)
4420 {
4421 if (dbgregs->flags)
4422 return -EINVAL;
4423
4424 if (dbgregs->dr6 & ~0xffffffffull)
4425 return -EINVAL;
4426 if (dbgregs->dr7 & ~0xffffffffull)
4427 return -EINVAL;
4428
4429 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4430 kvm_update_dr0123(vcpu);
4431 vcpu->arch.dr6 = dbgregs->dr6;
4432 vcpu->arch.dr7 = dbgregs->dr7;
4433 kvm_update_dr7(vcpu);
4434
4435 return 0;
4436 }
4437
4438 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4439
4440 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4441 {
4442 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4443 u64 xstate_bv = xsave->header.xfeatures;
4444 u64 valid;
4445
4446 /*
4447 * Copy legacy XSAVE area, to avoid complications with CPUID
4448 * leaves 0 and 1 in the loop below.
4449 */
4450 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4451
4452 /* Set XSTATE_BV */
4453 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4454 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4455
4456 /*
4457 * Copy each region from the possibly compacted offset to the
4458 * non-compacted offset.
4459 */
4460 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4461 while (valid) {
4462 u64 xfeature_mask = valid & -valid;
4463 int xfeature_nr = fls64(xfeature_mask) - 1;
4464 void *src = get_xsave_addr(xsave, xfeature_nr);
4465
4466 if (src) {
4467 u32 size, offset, ecx, edx;
4468 cpuid_count(XSTATE_CPUID, xfeature_nr,
4469 &size, &offset, &ecx, &edx);
4470 if (xfeature_nr == XFEATURE_PKRU)
4471 memcpy(dest + offset, &vcpu->arch.pkru,
4472 sizeof(vcpu->arch.pkru));
4473 else
4474 memcpy(dest + offset, src, size);
4475
4476 }
4477
4478 valid -= xfeature_mask;
4479 }
4480 }
4481
4482 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4483 {
4484 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4485 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4486 u64 valid;
4487
4488 /*
4489 * Copy legacy XSAVE area, to avoid complications with CPUID
4490 * leaves 0 and 1 in the loop below.
4491 */
4492 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4493
4494 /* Set XSTATE_BV and possibly XCOMP_BV. */
4495 xsave->header.xfeatures = xstate_bv;
4496 if (boot_cpu_has(X86_FEATURE_XSAVES))
4497 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4498
4499 /*
4500 * Copy each region from the non-compacted offset to the
4501 * possibly compacted offset.
4502 */
4503 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4504 while (valid) {
4505 u64 xfeature_mask = valid & -valid;
4506 int xfeature_nr = fls64(xfeature_mask) - 1;
4507 void *dest = get_xsave_addr(xsave, xfeature_nr);
4508
4509 if (dest) {
4510 u32 size, offset, ecx, edx;
4511 cpuid_count(XSTATE_CPUID, xfeature_nr,
4512 &size, &offset, &ecx, &edx);
4513 if (xfeature_nr == XFEATURE_PKRU)
4514 memcpy(&vcpu->arch.pkru, src + offset,
4515 sizeof(vcpu->arch.pkru));
4516 else
4517 memcpy(dest, src + offset, size);
4518 }
4519
4520 valid -= xfeature_mask;
4521 }
4522 }
4523
4524 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4525 struct kvm_xsave *guest_xsave)
4526 {
4527 if (!vcpu->arch.guest_fpu)
4528 return;
4529
4530 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4531 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4532 fill_xsave((u8 *) guest_xsave->region, vcpu);
4533 } else {
4534 memcpy(guest_xsave->region,
4535 &vcpu->arch.guest_fpu->state.fxsave,
4536 sizeof(struct fxregs_state));
4537 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4538 XFEATURE_MASK_FPSSE;
4539 }
4540 }
4541
4542 #define XSAVE_MXCSR_OFFSET 24
4543
4544 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4545 struct kvm_xsave *guest_xsave)
4546 {
4547 u64 xstate_bv;
4548 u32 mxcsr;
4549
4550 if (!vcpu->arch.guest_fpu)
4551 return 0;
4552
4553 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4554 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4555
4556 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4557 /*
4558 * Here we allow setting states that are not present in
4559 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4560 * with old userspace.
4561 */
4562 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4563 return -EINVAL;
4564 load_xsave(vcpu, (u8 *)guest_xsave->region);
4565 } else {
4566 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4567 mxcsr & ~mxcsr_feature_mask)
4568 return -EINVAL;
4569 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4570 guest_xsave->region, sizeof(struct fxregs_state));
4571 }
4572 return 0;
4573 }
4574
4575 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4576 struct kvm_xcrs *guest_xcrs)
4577 {
4578 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4579 guest_xcrs->nr_xcrs = 0;
4580 return;
4581 }
4582
4583 guest_xcrs->nr_xcrs = 1;
4584 guest_xcrs->flags = 0;
4585 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4586 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4587 }
4588
4589 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4590 struct kvm_xcrs *guest_xcrs)
4591 {
4592 int i, r = 0;
4593
4594 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4595 return -EINVAL;
4596
4597 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4598 return -EINVAL;
4599
4600 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4601 /* Only support XCR0 currently */
4602 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4603 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4604 guest_xcrs->xcrs[i].value);
4605 break;
4606 }
4607 if (r)
4608 r = -EINVAL;
4609 return r;
4610 }
4611
4612 /*
4613 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4614 * stopped by the hypervisor. This function will be called from the host only.
4615 * EINVAL is returned when the host attempts to set the flag for a guest that
4616 * does not support pv clocks.
4617 */
4618 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4619 {
4620 if (!vcpu->arch.pv_time_enabled)
4621 return -EINVAL;
4622 vcpu->arch.pvclock_set_guest_stopped_request = true;
4623 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4624 return 0;
4625 }
4626
4627 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4628 struct kvm_enable_cap *cap)
4629 {
4630 int r;
4631 uint16_t vmcs_version;
4632 void __user *user_ptr;
4633
4634 if (cap->flags)
4635 return -EINVAL;
4636
4637 switch (cap->cap) {
4638 case KVM_CAP_HYPERV_SYNIC2:
4639 if (cap->args[0])
4640 return -EINVAL;
4641 fallthrough;
4642
4643 case KVM_CAP_HYPERV_SYNIC:
4644 if (!irqchip_in_kernel(vcpu->kvm))
4645 return -EINVAL;
4646 return kvm_hv_activate_synic(vcpu, cap->cap ==
4647 KVM_CAP_HYPERV_SYNIC2);
4648 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4649 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4650 return -ENOTTY;
4651 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4652 if (!r) {
4653 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4654 if (copy_to_user(user_ptr, &vmcs_version,
4655 sizeof(vmcs_version)))
4656 r = -EFAULT;
4657 }
4658 return r;
4659 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4660 if (!kvm_x86_ops.enable_direct_tlbflush)
4661 return -ENOTTY;
4662
4663 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4664
4665 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4666 vcpu->arch.pv_cpuid.enforce = cap->args[0];
4667 if (vcpu->arch.pv_cpuid.enforce)
4668 kvm_update_pv_runtime(vcpu);
4669
4670 return 0;
4671
4672 default:
4673 return -EINVAL;
4674 }
4675 }
4676
4677 long kvm_arch_vcpu_ioctl(struct file *filp,
4678 unsigned int ioctl, unsigned long arg)
4679 {
4680 struct kvm_vcpu *vcpu = filp->private_data;
4681 void __user *argp = (void __user *)arg;
4682 int r;
4683 union {
4684 struct kvm_lapic_state *lapic;
4685 struct kvm_xsave *xsave;
4686 struct kvm_xcrs *xcrs;
4687 void *buffer;
4688 } u;
4689
4690 vcpu_load(vcpu);
4691
4692 u.buffer = NULL;
4693 switch (ioctl) {
4694 case KVM_GET_LAPIC: {
4695 r = -EINVAL;
4696 if (!lapic_in_kernel(vcpu))
4697 goto out;
4698 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4699 GFP_KERNEL_ACCOUNT);
4700
4701 r = -ENOMEM;
4702 if (!u.lapic)
4703 goto out;
4704 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4705 if (r)
4706 goto out;
4707 r = -EFAULT;
4708 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4709 goto out;
4710 r = 0;
4711 break;
4712 }
4713 case KVM_SET_LAPIC: {
4714 r = -EINVAL;
4715 if (!lapic_in_kernel(vcpu))
4716 goto out;
4717 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4718 if (IS_ERR(u.lapic)) {
4719 r = PTR_ERR(u.lapic);
4720 goto out_nofree;
4721 }
4722
4723 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4724 break;
4725 }
4726 case KVM_INTERRUPT: {
4727 struct kvm_interrupt irq;
4728
4729 r = -EFAULT;
4730 if (copy_from_user(&irq, argp, sizeof(irq)))
4731 goto out;
4732 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4733 break;
4734 }
4735 case KVM_NMI: {
4736 r = kvm_vcpu_ioctl_nmi(vcpu);
4737 break;
4738 }
4739 case KVM_SMI: {
4740 r = kvm_vcpu_ioctl_smi(vcpu);
4741 break;
4742 }
4743 case KVM_SET_CPUID: {
4744 struct kvm_cpuid __user *cpuid_arg = argp;
4745 struct kvm_cpuid cpuid;
4746
4747 r = -EFAULT;
4748 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4749 goto out;
4750 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4751 break;
4752 }
4753 case KVM_SET_CPUID2: {
4754 struct kvm_cpuid2 __user *cpuid_arg = argp;
4755 struct kvm_cpuid2 cpuid;
4756
4757 r = -EFAULT;
4758 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4759 goto out;
4760 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4761 cpuid_arg->entries);
4762 break;
4763 }
4764 case KVM_GET_CPUID2: {
4765 struct kvm_cpuid2 __user *cpuid_arg = argp;
4766 struct kvm_cpuid2 cpuid;
4767
4768 r = -EFAULT;
4769 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4770 goto out;
4771 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4772 cpuid_arg->entries);
4773 if (r)
4774 goto out;
4775 r = -EFAULT;
4776 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4777 goto out;
4778 r = 0;
4779 break;
4780 }
4781 case KVM_GET_MSRS: {
4782 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4783 r = msr_io(vcpu, argp, do_get_msr, 1);
4784 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4785 break;
4786 }
4787 case KVM_SET_MSRS: {
4788 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4789 r = msr_io(vcpu, argp, do_set_msr, 0);
4790 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4791 break;
4792 }
4793 case KVM_TPR_ACCESS_REPORTING: {
4794 struct kvm_tpr_access_ctl tac;
4795
4796 r = -EFAULT;
4797 if (copy_from_user(&tac, argp, sizeof(tac)))
4798 goto out;
4799 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4800 if (r)
4801 goto out;
4802 r = -EFAULT;
4803 if (copy_to_user(argp, &tac, sizeof(tac)))
4804 goto out;
4805 r = 0;
4806 break;
4807 };
4808 case KVM_SET_VAPIC_ADDR: {
4809 struct kvm_vapic_addr va;
4810 int idx;
4811
4812 r = -EINVAL;
4813 if (!lapic_in_kernel(vcpu))
4814 goto out;
4815 r = -EFAULT;
4816 if (copy_from_user(&va, argp, sizeof(va)))
4817 goto out;
4818 idx = srcu_read_lock(&vcpu->kvm->srcu);
4819 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4820 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4821 break;
4822 }
4823 case KVM_X86_SETUP_MCE: {
4824 u64 mcg_cap;
4825
4826 r = -EFAULT;
4827 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4828 goto out;
4829 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4830 break;
4831 }
4832 case KVM_X86_SET_MCE: {
4833 struct kvm_x86_mce mce;
4834
4835 r = -EFAULT;
4836 if (copy_from_user(&mce, argp, sizeof(mce)))
4837 goto out;
4838 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4839 break;
4840 }
4841 case KVM_GET_VCPU_EVENTS: {
4842 struct kvm_vcpu_events events;
4843
4844 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4845
4846 r = -EFAULT;
4847 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4848 break;
4849 r = 0;
4850 break;
4851 }
4852 case KVM_SET_VCPU_EVENTS: {
4853 struct kvm_vcpu_events events;
4854
4855 r = -EFAULT;
4856 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4857 break;
4858
4859 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4860 break;
4861 }
4862 case KVM_GET_DEBUGREGS: {
4863 struct kvm_debugregs dbgregs;
4864
4865 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4866
4867 r = -EFAULT;
4868 if (copy_to_user(argp, &dbgregs,
4869 sizeof(struct kvm_debugregs)))
4870 break;
4871 r = 0;
4872 break;
4873 }
4874 case KVM_SET_DEBUGREGS: {
4875 struct kvm_debugregs dbgregs;
4876
4877 r = -EFAULT;
4878 if (copy_from_user(&dbgregs, argp,
4879 sizeof(struct kvm_debugregs)))
4880 break;
4881
4882 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4883 break;
4884 }
4885 case KVM_GET_XSAVE: {
4886 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4887 r = -ENOMEM;
4888 if (!u.xsave)
4889 break;
4890
4891 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4892
4893 r = -EFAULT;
4894 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4895 break;
4896 r = 0;
4897 break;
4898 }
4899 case KVM_SET_XSAVE: {
4900 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4901 if (IS_ERR(u.xsave)) {
4902 r = PTR_ERR(u.xsave);
4903 goto out_nofree;
4904 }
4905
4906 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4907 break;
4908 }
4909 case KVM_GET_XCRS: {
4910 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4911 r = -ENOMEM;
4912 if (!u.xcrs)
4913 break;
4914
4915 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4916
4917 r = -EFAULT;
4918 if (copy_to_user(argp, u.xcrs,
4919 sizeof(struct kvm_xcrs)))
4920 break;
4921 r = 0;
4922 break;
4923 }
4924 case KVM_SET_XCRS: {
4925 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4926 if (IS_ERR(u.xcrs)) {
4927 r = PTR_ERR(u.xcrs);
4928 goto out_nofree;
4929 }
4930
4931 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4932 break;
4933 }
4934 case KVM_SET_TSC_KHZ: {
4935 u32 user_tsc_khz;
4936
4937 r = -EINVAL;
4938 user_tsc_khz = (u32)arg;
4939
4940 if (kvm_has_tsc_control &&
4941 user_tsc_khz >= kvm_max_guest_tsc_khz)
4942 goto out;
4943
4944 if (user_tsc_khz == 0)
4945 user_tsc_khz = tsc_khz;
4946
4947 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4948 r = 0;
4949
4950 goto out;
4951 }
4952 case KVM_GET_TSC_KHZ: {
4953 r = vcpu->arch.virtual_tsc_khz;
4954 goto out;
4955 }
4956 case KVM_KVMCLOCK_CTRL: {
4957 r = kvm_set_guest_paused(vcpu);
4958 goto out;
4959 }
4960 case KVM_ENABLE_CAP: {
4961 struct kvm_enable_cap cap;
4962
4963 r = -EFAULT;
4964 if (copy_from_user(&cap, argp, sizeof(cap)))
4965 goto out;
4966 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4967 break;
4968 }
4969 case KVM_GET_NESTED_STATE: {
4970 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4971 u32 user_data_size;
4972
4973 r = -EINVAL;
4974 if (!kvm_x86_ops.nested_ops->get_state)
4975 break;
4976
4977 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4978 r = -EFAULT;
4979 if (get_user(user_data_size, &user_kvm_nested_state->size))
4980 break;
4981
4982 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4983 user_data_size);
4984 if (r < 0)
4985 break;
4986
4987 if (r > user_data_size) {
4988 if (put_user(r, &user_kvm_nested_state->size))
4989 r = -EFAULT;
4990 else
4991 r = -E2BIG;
4992 break;
4993 }
4994
4995 r = 0;
4996 break;
4997 }
4998 case KVM_SET_NESTED_STATE: {
4999 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5000 struct kvm_nested_state kvm_state;
5001 int idx;
5002
5003 r = -EINVAL;
5004 if (!kvm_x86_ops.nested_ops->set_state)
5005 break;
5006
5007 r = -EFAULT;
5008 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5009 break;
5010
5011 r = -EINVAL;
5012 if (kvm_state.size < sizeof(kvm_state))
5013 break;
5014
5015 if (kvm_state.flags &
5016 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5017 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5018 | KVM_STATE_NESTED_GIF_SET))
5019 break;
5020
5021 /* nested_run_pending implies guest_mode. */
5022 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5023 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5024 break;
5025
5026 idx = srcu_read_lock(&vcpu->kvm->srcu);
5027 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5028 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5029 break;
5030 }
5031 case KVM_GET_SUPPORTED_HV_CPUID:
5032 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5033 break;
5034 default:
5035 r = -EINVAL;
5036 }
5037 out:
5038 kfree(u.buffer);
5039 out_nofree:
5040 vcpu_put(vcpu);
5041 return r;
5042 }
5043
5044 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5045 {
5046 return VM_FAULT_SIGBUS;
5047 }
5048
5049 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5050 {
5051 int ret;
5052
5053 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5054 return -EINVAL;
5055 ret = kvm_x86_ops.set_tss_addr(kvm, addr);
5056 return ret;
5057 }
5058
5059 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5060 u64 ident_addr)
5061 {
5062 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
5063 }
5064
5065 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5066 unsigned long kvm_nr_mmu_pages)
5067 {
5068 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5069 return -EINVAL;
5070
5071 mutex_lock(&kvm->slots_lock);
5072
5073 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5074 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5075
5076 mutex_unlock(&kvm->slots_lock);
5077 return 0;
5078 }
5079
5080 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5081 {
5082 return kvm->arch.n_max_mmu_pages;
5083 }
5084
5085 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5086 {
5087 struct kvm_pic *pic = kvm->arch.vpic;
5088 int r;
5089
5090 r = 0;
5091 switch (chip->chip_id) {
5092 case KVM_IRQCHIP_PIC_MASTER:
5093 memcpy(&chip->chip.pic, &pic->pics[0],
5094 sizeof(struct kvm_pic_state));
5095 break;
5096 case KVM_IRQCHIP_PIC_SLAVE:
5097 memcpy(&chip->chip.pic, &pic->pics[1],
5098 sizeof(struct kvm_pic_state));
5099 break;
5100 case KVM_IRQCHIP_IOAPIC:
5101 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5102 break;
5103 default:
5104 r = -EINVAL;
5105 break;
5106 }
5107 return r;
5108 }
5109
5110 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5111 {
5112 struct kvm_pic *pic = kvm->arch.vpic;
5113 int r;
5114
5115 r = 0;
5116 switch (chip->chip_id) {
5117 case KVM_IRQCHIP_PIC_MASTER:
5118 spin_lock(&pic->lock);
5119 memcpy(&pic->pics[0], &chip->chip.pic,
5120 sizeof(struct kvm_pic_state));
5121 spin_unlock(&pic->lock);
5122 break;
5123 case KVM_IRQCHIP_PIC_SLAVE:
5124 spin_lock(&pic->lock);
5125 memcpy(&pic->pics[1], &chip->chip.pic,
5126 sizeof(struct kvm_pic_state));
5127 spin_unlock(&pic->lock);
5128 break;
5129 case KVM_IRQCHIP_IOAPIC:
5130 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5131 break;
5132 default:
5133 r = -EINVAL;
5134 break;
5135 }
5136 kvm_pic_update_irq(pic);
5137 return r;
5138 }
5139
5140 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5141 {
5142 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5143
5144 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5145
5146 mutex_lock(&kps->lock);
5147 memcpy(ps, &kps->channels, sizeof(*ps));
5148 mutex_unlock(&kps->lock);
5149 return 0;
5150 }
5151
5152 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5153 {
5154 int i;
5155 struct kvm_pit *pit = kvm->arch.vpit;
5156
5157 mutex_lock(&pit->pit_state.lock);
5158 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5159 for (i = 0; i < 3; i++)
5160 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5161 mutex_unlock(&pit->pit_state.lock);
5162 return 0;
5163 }
5164
5165 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5166 {
5167 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5168 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5169 sizeof(ps->channels));
5170 ps->flags = kvm->arch.vpit->pit_state.flags;
5171 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5172 memset(&ps->reserved, 0, sizeof(ps->reserved));
5173 return 0;
5174 }
5175
5176 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5177 {
5178 int start = 0;
5179 int i;
5180 u32 prev_legacy, cur_legacy;
5181 struct kvm_pit *pit = kvm->arch.vpit;
5182
5183 mutex_lock(&pit->pit_state.lock);
5184 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5185 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5186 if (!prev_legacy && cur_legacy)
5187 start = 1;
5188 memcpy(&pit->pit_state.channels, &ps->channels,
5189 sizeof(pit->pit_state.channels));
5190 pit->pit_state.flags = ps->flags;
5191 for (i = 0; i < 3; i++)
5192 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5193 start && i == 0);
5194 mutex_unlock(&pit->pit_state.lock);
5195 return 0;
5196 }
5197
5198 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5199 struct kvm_reinject_control *control)
5200 {
5201 struct kvm_pit *pit = kvm->arch.vpit;
5202
5203 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5204 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5205 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5206 */
5207 mutex_lock(&pit->pit_state.lock);
5208 kvm_pit_set_reinject(pit, control->pit_reinject);
5209 mutex_unlock(&pit->pit_state.lock);
5210
5211 return 0;
5212 }
5213
5214 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5215 {
5216 /*
5217 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
5218 */
5219 if (kvm_x86_ops.flush_log_dirty)
5220 kvm_x86_ops.flush_log_dirty(kvm);
5221 }
5222
5223 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5224 bool line_status)
5225 {
5226 if (!irqchip_in_kernel(kvm))
5227 return -ENXIO;
5228
5229 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5230 irq_event->irq, irq_event->level,
5231 line_status);
5232 return 0;
5233 }
5234
5235 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5236 struct kvm_enable_cap *cap)
5237 {
5238 int r;
5239
5240 if (cap->flags)
5241 return -EINVAL;
5242
5243 switch (cap->cap) {
5244 case KVM_CAP_DISABLE_QUIRKS:
5245 kvm->arch.disabled_quirks = cap->args[0];
5246 r = 0;
5247 break;
5248 case KVM_CAP_SPLIT_IRQCHIP: {
5249 mutex_lock(&kvm->lock);
5250 r = -EINVAL;
5251 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5252 goto split_irqchip_unlock;
5253 r = -EEXIST;
5254 if (irqchip_in_kernel(kvm))
5255 goto split_irqchip_unlock;
5256 if (kvm->created_vcpus)
5257 goto split_irqchip_unlock;
5258 r = kvm_setup_empty_irq_routing(kvm);
5259 if (r)
5260 goto split_irqchip_unlock;
5261 /* Pairs with irqchip_in_kernel. */
5262 smp_wmb();
5263 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5264 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5265 r = 0;
5266 split_irqchip_unlock:
5267 mutex_unlock(&kvm->lock);
5268 break;
5269 }
5270 case KVM_CAP_X2APIC_API:
5271 r = -EINVAL;
5272 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5273 break;
5274
5275 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5276 kvm->arch.x2apic_format = true;
5277 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5278 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5279
5280 r = 0;
5281 break;
5282 case KVM_CAP_X86_DISABLE_EXITS:
5283 r = -EINVAL;
5284 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5285 break;
5286
5287 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5288 kvm_can_mwait_in_guest())
5289 kvm->arch.mwait_in_guest = true;
5290 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5291 kvm->arch.hlt_in_guest = true;
5292 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5293 kvm->arch.pause_in_guest = true;
5294 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5295 kvm->arch.cstate_in_guest = true;
5296 r = 0;
5297 break;
5298 case KVM_CAP_MSR_PLATFORM_INFO:
5299 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5300 r = 0;
5301 break;
5302 case KVM_CAP_EXCEPTION_PAYLOAD:
5303 kvm->arch.exception_payload_enabled = cap->args[0];
5304 r = 0;
5305 break;
5306 case KVM_CAP_X86_USER_SPACE_MSR:
5307 kvm->arch.user_space_msr_mask = cap->args[0];
5308 r = 0;
5309 break;
5310 default:
5311 r = -EINVAL;
5312 break;
5313 }
5314 return r;
5315 }
5316
5317 static void kvm_clear_msr_filter(struct kvm *kvm)
5318 {
5319 u32 i;
5320 u32 count = kvm->arch.msr_filter.count;
5321 struct msr_bitmap_range ranges[16];
5322
5323 mutex_lock(&kvm->lock);
5324 kvm->arch.msr_filter.count = 0;
5325 memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0]));
5326 mutex_unlock(&kvm->lock);
5327 synchronize_srcu(&kvm->srcu);
5328
5329 for (i = 0; i < count; i++)
5330 kfree(ranges[i].bitmap);
5331 }
5332
5333 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range)
5334 {
5335 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
5336 struct msr_bitmap_range range;
5337 unsigned long *bitmap = NULL;
5338 size_t bitmap_size;
5339 int r;
5340
5341 if (!user_range->nmsrs)
5342 return 0;
5343
5344 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5345 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5346 return -EINVAL;
5347
5348 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5349 if (IS_ERR(bitmap))
5350 return PTR_ERR(bitmap);
5351
5352 range = (struct msr_bitmap_range) {
5353 .flags = user_range->flags,
5354 .base = user_range->base,
5355 .nmsrs = user_range->nmsrs,
5356 .bitmap = bitmap,
5357 };
5358
5359 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5360 r = -EINVAL;
5361 goto err;
5362 }
5363
5364 if (!range.flags) {
5365 r = -EINVAL;
5366 goto err;
5367 }
5368
5369 /* Everything ok, add this range identifier to our global pool */
5370 ranges[kvm->arch.msr_filter.count] = range;
5371 /* Make sure we filled the array before we tell anyone to walk it */
5372 smp_wmb();
5373 kvm->arch.msr_filter.count++;
5374
5375 return 0;
5376 err:
5377 kfree(bitmap);
5378 return r;
5379 }
5380
5381 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5382 {
5383 struct kvm_msr_filter __user *user_msr_filter = argp;
5384 struct kvm_msr_filter filter;
5385 bool default_allow;
5386 int r = 0;
5387 bool empty = true;
5388 u32 i;
5389
5390 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5391 return -EFAULT;
5392
5393 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5394 empty &= !filter.ranges[i].nmsrs;
5395
5396 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5397 if (empty && !default_allow)
5398 return -EINVAL;
5399
5400 kvm_clear_msr_filter(kvm);
5401
5402 kvm->arch.msr_filter.default_allow = default_allow;
5403
5404 /*
5405 * Protect from concurrent calls to this function that could trigger
5406 * a TOCTOU violation on kvm->arch.msr_filter.count.
5407 */
5408 mutex_lock(&kvm->lock);
5409 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5410 r = kvm_add_msr_filter(kvm, &filter.ranges[i]);
5411 if (r)
5412 break;
5413 }
5414
5415 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5416 mutex_unlock(&kvm->lock);
5417
5418 return r;
5419 }
5420
5421 long kvm_arch_vm_ioctl(struct file *filp,
5422 unsigned int ioctl, unsigned long arg)
5423 {
5424 struct kvm *kvm = filp->private_data;
5425 void __user *argp = (void __user *)arg;
5426 int r = -ENOTTY;
5427 /*
5428 * This union makes it completely explicit to gcc-3.x
5429 * that these two variables' stack usage should be
5430 * combined, not added together.
5431 */
5432 union {
5433 struct kvm_pit_state ps;
5434 struct kvm_pit_state2 ps2;
5435 struct kvm_pit_config pit_config;
5436 } u;
5437
5438 switch (ioctl) {
5439 case KVM_SET_TSS_ADDR:
5440 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5441 break;
5442 case KVM_SET_IDENTITY_MAP_ADDR: {
5443 u64 ident_addr;
5444
5445 mutex_lock(&kvm->lock);
5446 r = -EINVAL;
5447 if (kvm->created_vcpus)
5448 goto set_identity_unlock;
5449 r = -EFAULT;
5450 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5451 goto set_identity_unlock;
5452 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5453 set_identity_unlock:
5454 mutex_unlock(&kvm->lock);
5455 break;
5456 }
5457 case KVM_SET_NR_MMU_PAGES:
5458 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5459 break;
5460 case KVM_GET_NR_MMU_PAGES:
5461 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5462 break;
5463 case KVM_CREATE_IRQCHIP: {
5464 mutex_lock(&kvm->lock);
5465
5466 r = -EEXIST;
5467 if (irqchip_in_kernel(kvm))
5468 goto create_irqchip_unlock;
5469
5470 r = -EINVAL;
5471 if (kvm->created_vcpus)
5472 goto create_irqchip_unlock;
5473
5474 r = kvm_pic_init(kvm);
5475 if (r)
5476 goto create_irqchip_unlock;
5477
5478 r = kvm_ioapic_init(kvm);
5479 if (r) {
5480 kvm_pic_destroy(kvm);
5481 goto create_irqchip_unlock;
5482 }
5483
5484 r = kvm_setup_default_irq_routing(kvm);
5485 if (r) {
5486 kvm_ioapic_destroy(kvm);
5487 kvm_pic_destroy(kvm);
5488 goto create_irqchip_unlock;
5489 }
5490 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5491 smp_wmb();
5492 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5493 create_irqchip_unlock:
5494 mutex_unlock(&kvm->lock);
5495 break;
5496 }
5497 case KVM_CREATE_PIT:
5498 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5499 goto create_pit;
5500 case KVM_CREATE_PIT2:
5501 r = -EFAULT;
5502 if (copy_from_user(&u.pit_config, argp,
5503 sizeof(struct kvm_pit_config)))
5504 goto out;
5505 create_pit:
5506 mutex_lock(&kvm->lock);
5507 r = -EEXIST;
5508 if (kvm->arch.vpit)
5509 goto create_pit_unlock;
5510 r = -ENOMEM;
5511 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5512 if (kvm->arch.vpit)
5513 r = 0;
5514 create_pit_unlock:
5515 mutex_unlock(&kvm->lock);
5516 break;
5517 case KVM_GET_IRQCHIP: {
5518 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5519 struct kvm_irqchip *chip;
5520
5521 chip = memdup_user(argp, sizeof(*chip));
5522 if (IS_ERR(chip)) {
5523 r = PTR_ERR(chip);
5524 goto out;
5525 }
5526
5527 r = -ENXIO;
5528 if (!irqchip_kernel(kvm))
5529 goto get_irqchip_out;
5530 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5531 if (r)
5532 goto get_irqchip_out;
5533 r = -EFAULT;
5534 if (copy_to_user(argp, chip, sizeof(*chip)))
5535 goto get_irqchip_out;
5536 r = 0;
5537 get_irqchip_out:
5538 kfree(chip);
5539 break;
5540 }
5541 case KVM_SET_IRQCHIP: {
5542 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5543 struct kvm_irqchip *chip;
5544
5545 chip = memdup_user(argp, sizeof(*chip));
5546 if (IS_ERR(chip)) {
5547 r = PTR_ERR(chip);
5548 goto out;
5549 }
5550
5551 r = -ENXIO;
5552 if (!irqchip_kernel(kvm))
5553 goto set_irqchip_out;
5554 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5555 set_irqchip_out:
5556 kfree(chip);
5557 break;
5558 }
5559 case KVM_GET_PIT: {
5560 r = -EFAULT;
5561 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5562 goto out;
5563 r = -ENXIO;
5564 if (!kvm->arch.vpit)
5565 goto out;
5566 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5567 if (r)
5568 goto out;
5569 r = -EFAULT;
5570 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5571 goto out;
5572 r = 0;
5573 break;
5574 }
5575 case KVM_SET_PIT: {
5576 r = -EFAULT;
5577 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5578 goto out;
5579 mutex_lock(&kvm->lock);
5580 r = -ENXIO;
5581 if (!kvm->arch.vpit)
5582 goto set_pit_out;
5583 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5584 set_pit_out:
5585 mutex_unlock(&kvm->lock);
5586 break;
5587 }
5588 case KVM_GET_PIT2: {
5589 r = -ENXIO;
5590 if (!kvm->arch.vpit)
5591 goto out;
5592 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5593 if (r)
5594 goto out;
5595 r = -EFAULT;
5596 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5597 goto out;
5598 r = 0;
5599 break;
5600 }
5601 case KVM_SET_PIT2: {
5602 r = -EFAULT;
5603 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5604 goto out;
5605 mutex_lock(&kvm->lock);
5606 r = -ENXIO;
5607 if (!kvm->arch.vpit)
5608 goto set_pit2_out;
5609 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5610 set_pit2_out:
5611 mutex_unlock(&kvm->lock);
5612 break;
5613 }
5614 case KVM_REINJECT_CONTROL: {
5615 struct kvm_reinject_control control;
5616 r = -EFAULT;
5617 if (copy_from_user(&control, argp, sizeof(control)))
5618 goto out;
5619 r = -ENXIO;
5620 if (!kvm->arch.vpit)
5621 goto out;
5622 r = kvm_vm_ioctl_reinject(kvm, &control);
5623 break;
5624 }
5625 case KVM_SET_BOOT_CPU_ID:
5626 r = 0;
5627 mutex_lock(&kvm->lock);
5628 if (kvm->created_vcpus)
5629 r = -EBUSY;
5630 else
5631 kvm->arch.bsp_vcpu_id = arg;
5632 mutex_unlock(&kvm->lock);
5633 break;
5634 case KVM_XEN_HVM_CONFIG: {
5635 struct kvm_xen_hvm_config xhc;
5636 r = -EFAULT;
5637 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5638 goto out;
5639 r = -EINVAL;
5640 if (xhc.flags)
5641 goto out;
5642 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5643 r = 0;
5644 break;
5645 }
5646 case KVM_SET_CLOCK: {
5647 struct kvm_clock_data user_ns;
5648 u64 now_ns;
5649
5650 r = -EFAULT;
5651 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5652 goto out;
5653
5654 r = -EINVAL;
5655 if (user_ns.flags)
5656 goto out;
5657
5658 r = 0;
5659 /*
5660 * TODO: userspace has to take care of races with VCPU_RUN, so
5661 * kvm_gen_update_masterclock() can be cut down to locked
5662 * pvclock_update_vm_gtod_copy().
5663 */
5664 kvm_gen_update_masterclock(kvm);
5665 now_ns = get_kvmclock_ns(kvm);
5666 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5667 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5668 break;
5669 }
5670 case KVM_GET_CLOCK: {
5671 struct kvm_clock_data user_ns;
5672 u64 now_ns;
5673
5674 now_ns = get_kvmclock_ns(kvm);
5675 user_ns.clock = now_ns;
5676 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5677 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5678
5679 r = -EFAULT;
5680 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5681 goto out;
5682 r = 0;
5683 break;
5684 }
5685 case KVM_MEMORY_ENCRYPT_OP: {
5686 r = -ENOTTY;
5687 if (kvm_x86_ops.mem_enc_op)
5688 r = kvm_x86_ops.mem_enc_op(kvm, argp);
5689 break;
5690 }
5691 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5692 struct kvm_enc_region region;
5693
5694 r = -EFAULT;
5695 if (copy_from_user(&region, argp, sizeof(region)))
5696 goto out;
5697
5698 r = -ENOTTY;
5699 if (kvm_x86_ops.mem_enc_reg_region)
5700 r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5701 break;
5702 }
5703 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5704 struct kvm_enc_region region;
5705
5706 r = -EFAULT;
5707 if (copy_from_user(&region, argp, sizeof(region)))
5708 goto out;
5709
5710 r = -ENOTTY;
5711 if (kvm_x86_ops.mem_enc_unreg_region)
5712 r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5713 break;
5714 }
5715 case KVM_HYPERV_EVENTFD: {
5716 struct kvm_hyperv_eventfd hvevfd;
5717
5718 r = -EFAULT;
5719 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5720 goto out;
5721 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5722 break;
5723 }
5724 case KVM_SET_PMU_EVENT_FILTER:
5725 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5726 break;
5727 case KVM_X86_SET_MSR_FILTER:
5728 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5729 break;
5730 default:
5731 r = -ENOTTY;
5732 }
5733 out:
5734 return r;
5735 }
5736
5737 static void kvm_init_msr_list(void)
5738 {
5739 struct x86_pmu_capability x86_pmu;
5740 u32 dummy[2];
5741 unsigned i;
5742
5743 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5744 "Please update the fixed PMCs in msrs_to_saved_all[]");
5745
5746 perf_get_x86_pmu_capability(&x86_pmu);
5747
5748 num_msrs_to_save = 0;
5749 num_emulated_msrs = 0;
5750 num_msr_based_features = 0;
5751
5752 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5753 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5754 continue;
5755
5756 /*
5757 * Even MSRs that are valid in the host may not be exposed
5758 * to the guests in some cases.
5759 */
5760 switch (msrs_to_save_all[i]) {
5761 case MSR_IA32_BNDCFGS:
5762 if (!kvm_mpx_supported())
5763 continue;
5764 break;
5765 case MSR_TSC_AUX:
5766 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5767 continue;
5768 break;
5769 case MSR_IA32_UMWAIT_CONTROL:
5770 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5771 continue;
5772 break;
5773 case MSR_IA32_RTIT_CTL:
5774 case MSR_IA32_RTIT_STATUS:
5775 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5776 continue;
5777 break;
5778 case MSR_IA32_RTIT_CR3_MATCH:
5779 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5780 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5781 continue;
5782 break;
5783 case MSR_IA32_RTIT_OUTPUT_BASE:
5784 case MSR_IA32_RTIT_OUTPUT_MASK:
5785 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5786 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5787 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5788 continue;
5789 break;
5790 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5791 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5792 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5793 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5794 continue;
5795 break;
5796 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5797 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5798 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5799 continue;
5800 break;
5801 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5802 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5803 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5804 continue;
5805 break;
5806 default:
5807 break;
5808 }
5809
5810 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5811 }
5812
5813 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5814 if (!kvm_x86_ops.has_emulated_msr(NULL, emulated_msrs_all[i]))
5815 continue;
5816
5817 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5818 }
5819
5820 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5821 struct kvm_msr_entry msr;
5822
5823 msr.index = msr_based_features_all[i];
5824 if (kvm_get_msr_feature(&msr))
5825 continue;
5826
5827 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5828 }
5829 }
5830
5831 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5832 const void *v)
5833 {
5834 int handled = 0;
5835 int n;
5836
5837 do {
5838 n = min(len, 8);
5839 if (!(lapic_in_kernel(vcpu) &&
5840 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5841 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5842 break;
5843 handled += n;
5844 addr += n;
5845 len -= n;
5846 v += n;
5847 } while (len);
5848
5849 return handled;
5850 }
5851
5852 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5853 {
5854 int handled = 0;
5855 int n;
5856
5857 do {
5858 n = min(len, 8);
5859 if (!(lapic_in_kernel(vcpu) &&
5860 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5861 addr, n, v))
5862 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5863 break;
5864 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5865 handled += n;
5866 addr += n;
5867 len -= n;
5868 v += n;
5869 } while (len);
5870
5871 return handled;
5872 }
5873
5874 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5875 struct kvm_segment *var, int seg)
5876 {
5877 kvm_x86_ops.set_segment(vcpu, var, seg);
5878 }
5879
5880 void kvm_get_segment(struct kvm_vcpu *vcpu,
5881 struct kvm_segment *var, int seg)
5882 {
5883 kvm_x86_ops.get_segment(vcpu, var, seg);
5884 }
5885
5886 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5887 struct x86_exception *exception)
5888 {
5889 gpa_t t_gpa;
5890
5891 BUG_ON(!mmu_is_nested(vcpu));
5892
5893 /* NPT walks are always user-walks */
5894 access |= PFERR_USER_MASK;
5895 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5896
5897 return t_gpa;
5898 }
5899
5900 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5901 struct x86_exception *exception)
5902 {
5903 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5904 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5905 }
5906
5907 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5908 struct x86_exception *exception)
5909 {
5910 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5911 access |= PFERR_FETCH_MASK;
5912 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5913 }
5914
5915 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5916 struct x86_exception *exception)
5917 {
5918 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5919 access |= PFERR_WRITE_MASK;
5920 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5921 }
5922
5923 /* uses this to access any guest's mapped memory without checking CPL */
5924 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5925 struct x86_exception *exception)
5926 {
5927 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5928 }
5929
5930 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5931 struct kvm_vcpu *vcpu, u32 access,
5932 struct x86_exception *exception)
5933 {
5934 void *data = val;
5935 int r = X86EMUL_CONTINUE;
5936
5937 while (bytes) {
5938 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5939 exception);
5940 unsigned offset = addr & (PAGE_SIZE-1);
5941 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5942 int ret;
5943
5944 if (gpa == UNMAPPED_GVA)
5945 return X86EMUL_PROPAGATE_FAULT;
5946 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5947 offset, toread);
5948 if (ret < 0) {
5949 r = X86EMUL_IO_NEEDED;
5950 goto out;
5951 }
5952
5953 bytes -= toread;
5954 data += toread;
5955 addr += toread;
5956 }
5957 out:
5958 return r;
5959 }
5960
5961 /* used for instruction fetching */
5962 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5963 gva_t addr, void *val, unsigned int bytes,
5964 struct x86_exception *exception)
5965 {
5966 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5967 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5968 unsigned offset;
5969 int ret;
5970
5971 /* Inline kvm_read_guest_virt_helper for speed. */
5972 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5973 exception);
5974 if (unlikely(gpa == UNMAPPED_GVA))
5975 return X86EMUL_PROPAGATE_FAULT;
5976
5977 offset = addr & (PAGE_SIZE-1);
5978 if (WARN_ON(offset + bytes > PAGE_SIZE))
5979 bytes = (unsigned)PAGE_SIZE - offset;
5980 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5981 offset, bytes);
5982 if (unlikely(ret < 0))
5983 return X86EMUL_IO_NEEDED;
5984
5985 return X86EMUL_CONTINUE;
5986 }
5987
5988 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5989 gva_t addr, void *val, unsigned int bytes,
5990 struct x86_exception *exception)
5991 {
5992 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5993
5994 /*
5995 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5996 * is returned, but our callers are not ready for that and they blindly
5997 * call kvm_inject_page_fault. Ensure that they at least do not leak
5998 * uninitialized kernel stack memory into cr2 and error code.
5999 */
6000 memset(exception, 0, sizeof(*exception));
6001 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
6002 exception);
6003 }
6004 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
6005
6006 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
6007 gva_t addr, void *val, unsigned int bytes,
6008 struct x86_exception *exception, bool system)
6009 {
6010 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6011 u32 access = 0;
6012
6013 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6014 access |= PFERR_USER_MASK;
6015
6016 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
6017 }
6018
6019 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
6020 unsigned long addr, void *val, unsigned int bytes)
6021 {
6022 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6023 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
6024
6025 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
6026 }
6027
6028 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6029 struct kvm_vcpu *vcpu, u32 access,
6030 struct x86_exception *exception)
6031 {
6032 void *data = val;
6033 int r = X86EMUL_CONTINUE;
6034
6035 while (bytes) {
6036 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
6037 access,
6038 exception);
6039 unsigned offset = addr & (PAGE_SIZE-1);
6040 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6041 int ret;
6042
6043 if (gpa == UNMAPPED_GVA)
6044 return X86EMUL_PROPAGATE_FAULT;
6045 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6046 if (ret < 0) {
6047 r = X86EMUL_IO_NEEDED;
6048 goto out;
6049 }
6050
6051 bytes -= towrite;
6052 data += towrite;
6053 addr += towrite;
6054 }
6055 out:
6056 return r;
6057 }
6058
6059 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6060 unsigned int bytes, struct x86_exception *exception,
6061 bool system)
6062 {
6063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6064 u32 access = PFERR_WRITE_MASK;
6065
6066 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6067 access |= PFERR_USER_MASK;
6068
6069 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6070 access, exception);
6071 }
6072
6073 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6074 unsigned int bytes, struct x86_exception *exception)
6075 {
6076 /* kvm_write_guest_virt_system can pull in tons of pages. */
6077 vcpu->arch.l1tf_flush_l1d = true;
6078
6079 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6080 PFERR_WRITE_MASK, exception);
6081 }
6082 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6083
6084 int handle_ud(struct kvm_vcpu *vcpu)
6085 {
6086 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6087 int emul_type = EMULTYPE_TRAP_UD;
6088 char sig[5]; /* ud2; .ascii "kvm" */
6089 struct x86_exception e;
6090
6091 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0)))
6092 return 1;
6093
6094 if (force_emulation_prefix &&
6095 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6096 sig, sizeof(sig), &e) == 0 &&
6097 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6098 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6099 emul_type = EMULTYPE_TRAP_UD_FORCED;
6100 }
6101
6102 return kvm_emulate_instruction(vcpu, emul_type);
6103 }
6104 EXPORT_SYMBOL_GPL(handle_ud);
6105
6106 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6107 gpa_t gpa, bool write)
6108 {
6109 /* For APIC access vmexit */
6110 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6111 return 1;
6112
6113 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6114 trace_vcpu_match_mmio(gva, gpa, write, true);
6115 return 1;
6116 }
6117
6118 return 0;
6119 }
6120
6121 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6122 gpa_t *gpa, struct x86_exception *exception,
6123 bool write)
6124 {
6125 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
6126 | (write ? PFERR_WRITE_MASK : 0);
6127
6128 /*
6129 * currently PKRU is only applied to ept enabled guest so
6130 * there is no pkey in EPT page table for L1 guest or EPT
6131 * shadow page table for L2 guest.
6132 */
6133 if (vcpu_match_mmio_gva(vcpu, gva)
6134 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6135 vcpu->arch.mmio_access, 0, access)) {
6136 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6137 (gva & (PAGE_SIZE - 1));
6138 trace_vcpu_match_mmio(gva, *gpa, write, false);
6139 return 1;
6140 }
6141
6142 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6143
6144 if (*gpa == UNMAPPED_GVA)
6145 return -1;
6146
6147 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6148 }
6149
6150 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6151 const void *val, int bytes)
6152 {
6153 int ret;
6154
6155 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6156 if (ret < 0)
6157 return 0;
6158 kvm_page_track_write(vcpu, gpa, val, bytes);
6159 return 1;
6160 }
6161
6162 struct read_write_emulator_ops {
6163 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6164 int bytes);
6165 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6166 void *val, int bytes);
6167 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6168 int bytes, void *val);
6169 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6170 void *val, int bytes);
6171 bool write;
6172 };
6173
6174 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6175 {
6176 if (vcpu->mmio_read_completed) {
6177 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6178 vcpu->mmio_fragments[0].gpa, val);
6179 vcpu->mmio_read_completed = 0;
6180 return 1;
6181 }
6182
6183 return 0;
6184 }
6185
6186 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6187 void *val, int bytes)
6188 {
6189 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6190 }
6191
6192 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6193 void *val, int bytes)
6194 {
6195 return emulator_write_phys(vcpu, gpa, val, bytes);
6196 }
6197
6198 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6199 {
6200 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6201 return vcpu_mmio_write(vcpu, gpa, bytes, val);
6202 }
6203
6204 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6205 void *val, int bytes)
6206 {
6207 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6208 return X86EMUL_IO_NEEDED;
6209 }
6210
6211 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6212 void *val, int bytes)
6213 {
6214 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6215
6216 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6217 return X86EMUL_CONTINUE;
6218 }
6219
6220 static const struct read_write_emulator_ops read_emultor = {
6221 .read_write_prepare = read_prepare,
6222 .read_write_emulate = read_emulate,
6223 .read_write_mmio = vcpu_mmio_read,
6224 .read_write_exit_mmio = read_exit_mmio,
6225 };
6226
6227 static const struct read_write_emulator_ops write_emultor = {
6228 .read_write_emulate = write_emulate,
6229 .read_write_mmio = write_mmio,
6230 .read_write_exit_mmio = write_exit_mmio,
6231 .write = true,
6232 };
6233
6234 static int emulator_read_write_onepage(unsigned long addr, void *val,
6235 unsigned int bytes,
6236 struct x86_exception *exception,
6237 struct kvm_vcpu *vcpu,
6238 const struct read_write_emulator_ops *ops)
6239 {
6240 gpa_t gpa;
6241 int handled, ret;
6242 bool write = ops->write;
6243 struct kvm_mmio_fragment *frag;
6244 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6245
6246 /*
6247 * If the exit was due to a NPF we may already have a GPA.
6248 * If the GPA is present, use it to avoid the GVA to GPA table walk.
6249 * Note, this cannot be used on string operations since string
6250 * operation using rep will only have the initial GPA from the NPF
6251 * occurred.
6252 */
6253 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6254 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6255 gpa = ctxt->gpa_val;
6256 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6257 } else {
6258 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6259 if (ret < 0)
6260 return X86EMUL_PROPAGATE_FAULT;
6261 }
6262
6263 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6264 return X86EMUL_CONTINUE;
6265
6266 /*
6267 * Is this MMIO handled locally?
6268 */
6269 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6270 if (handled == bytes)
6271 return X86EMUL_CONTINUE;
6272
6273 gpa += handled;
6274 bytes -= handled;
6275 val += handled;
6276
6277 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6278 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6279 frag->gpa = gpa;
6280 frag->data = val;
6281 frag->len = bytes;
6282 return X86EMUL_CONTINUE;
6283 }
6284
6285 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6286 unsigned long addr,
6287 void *val, unsigned int bytes,
6288 struct x86_exception *exception,
6289 const struct read_write_emulator_ops *ops)
6290 {
6291 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6292 gpa_t gpa;
6293 int rc;
6294
6295 if (ops->read_write_prepare &&
6296 ops->read_write_prepare(vcpu, val, bytes))
6297 return X86EMUL_CONTINUE;
6298
6299 vcpu->mmio_nr_fragments = 0;
6300
6301 /* Crossing a page boundary? */
6302 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6303 int now;
6304
6305 now = -addr & ~PAGE_MASK;
6306 rc = emulator_read_write_onepage(addr, val, now, exception,
6307 vcpu, ops);
6308
6309 if (rc != X86EMUL_CONTINUE)
6310 return rc;
6311 addr += now;
6312 if (ctxt->mode != X86EMUL_MODE_PROT64)
6313 addr = (u32)addr;
6314 val += now;
6315 bytes -= now;
6316 }
6317
6318 rc = emulator_read_write_onepage(addr, val, bytes, exception,
6319 vcpu, ops);
6320 if (rc != X86EMUL_CONTINUE)
6321 return rc;
6322
6323 if (!vcpu->mmio_nr_fragments)
6324 return rc;
6325
6326 gpa = vcpu->mmio_fragments[0].gpa;
6327
6328 vcpu->mmio_needed = 1;
6329 vcpu->mmio_cur_fragment = 0;
6330
6331 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6332 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6333 vcpu->run->exit_reason = KVM_EXIT_MMIO;
6334 vcpu->run->mmio.phys_addr = gpa;
6335
6336 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6337 }
6338
6339 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6340 unsigned long addr,
6341 void *val,
6342 unsigned int bytes,
6343 struct x86_exception *exception)
6344 {
6345 return emulator_read_write(ctxt, addr, val, bytes,
6346 exception, &read_emultor);
6347 }
6348
6349 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6350 unsigned long addr,
6351 const void *val,
6352 unsigned int bytes,
6353 struct x86_exception *exception)
6354 {
6355 return emulator_read_write(ctxt, addr, (void *)val, bytes,
6356 exception, &write_emultor);
6357 }
6358
6359 #define CMPXCHG_TYPE(t, ptr, old, new) \
6360 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6361
6362 #ifdef CONFIG_X86_64
6363 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6364 #else
6365 # define CMPXCHG64(ptr, old, new) \
6366 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6367 #endif
6368
6369 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6370 unsigned long addr,
6371 const void *old,
6372 const void *new,
6373 unsigned int bytes,
6374 struct x86_exception *exception)
6375 {
6376 struct kvm_host_map map;
6377 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6378 u64 page_line_mask;
6379 gpa_t gpa;
6380 char *kaddr;
6381 bool exchanged;
6382
6383 /* guests cmpxchg8b have to be emulated atomically */
6384 if (bytes > 8 || (bytes & (bytes - 1)))
6385 goto emul_write;
6386
6387 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6388
6389 if (gpa == UNMAPPED_GVA ||
6390 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6391 goto emul_write;
6392
6393 /*
6394 * Emulate the atomic as a straight write to avoid #AC if SLD is
6395 * enabled in the host and the access splits a cache line.
6396 */
6397 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6398 page_line_mask = ~(cache_line_size() - 1);
6399 else
6400 page_line_mask = PAGE_MASK;
6401
6402 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6403 goto emul_write;
6404
6405 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6406 goto emul_write;
6407
6408 kaddr = map.hva + offset_in_page(gpa);
6409
6410 switch (bytes) {
6411 case 1:
6412 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6413 break;
6414 case 2:
6415 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6416 break;
6417 case 4:
6418 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6419 break;
6420 case 8:
6421 exchanged = CMPXCHG64(kaddr, old, new);
6422 break;
6423 default:
6424 BUG();
6425 }
6426
6427 kvm_vcpu_unmap(vcpu, &map, true);
6428
6429 if (!exchanged)
6430 return X86EMUL_CMPXCHG_FAILED;
6431
6432 kvm_page_track_write(vcpu, gpa, new, bytes);
6433
6434 return X86EMUL_CONTINUE;
6435
6436 emul_write:
6437 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6438
6439 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6440 }
6441
6442 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6443 {
6444 int r = 0, i;
6445
6446 for (i = 0; i < vcpu->arch.pio.count; i++) {
6447 if (vcpu->arch.pio.in)
6448 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6449 vcpu->arch.pio.size, pd);
6450 else
6451 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6452 vcpu->arch.pio.port, vcpu->arch.pio.size,
6453 pd);
6454 if (r)
6455 break;
6456 pd += vcpu->arch.pio.size;
6457 }
6458 return r;
6459 }
6460
6461 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6462 unsigned short port, void *val,
6463 unsigned int count, bool in)
6464 {
6465 vcpu->arch.pio.port = port;
6466 vcpu->arch.pio.in = in;
6467 vcpu->arch.pio.count = count;
6468 vcpu->arch.pio.size = size;
6469
6470 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6471 vcpu->arch.pio.count = 0;
6472 return 1;
6473 }
6474
6475 vcpu->run->exit_reason = KVM_EXIT_IO;
6476 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6477 vcpu->run->io.size = size;
6478 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6479 vcpu->run->io.count = count;
6480 vcpu->run->io.port = port;
6481
6482 return 0;
6483 }
6484
6485 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6486 unsigned short port, void *val, unsigned int count)
6487 {
6488 int ret;
6489
6490 if (vcpu->arch.pio.count)
6491 goto data_avail;
6492
6493 memset(vcpu->arch.pio_data, 0, size * count);
6494
6495 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6496 if (ret) {
6497 data_avail:
6498 memcpy(val, vcpu->arch.pio_data, size * count);
6499 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6500 vcpu->arch.pio.count = 0;
6501 return 1;
6502 }
6503
6504 return 0;
6505 }
6506
6507 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6508 int size, unsigned short port, void *val,
6509 unsigned int count)
6510 {
6511 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6512
6513 }
6514
6515 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6516 unsigned short port, const void *val,
6517 unsigned int count)
6518 {
6519 memcpy(vcpu->arch.pio_data, val, size * count);
6520 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6521 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6522 }
6523
6524 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6525 int size, unsigned short port,
6526 const void *val, unsigned int count)
6527 {
6528 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6529 }
6530
6531 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6532 {
6533 return kvm_x86_ops.get_segment_base(vcpu, seg);
6534 }
6535
6536 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6537 {
6538 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6539 }
6540
6541 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6542 {
6543 if (!need_emulate_wbinvd(vcpu))
6544 return X86EMUL_CONTINUE;
6545
6546 if (kvm_x86_ops.has_wbinvd_exit()) {
6547 int cpu = get_cpu();
6548
6549 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6550 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6551 wbinvd_ipi, NULL, 1);
6552 put_cpu();
6553 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6554 } else
6555 wbinvd();
6556 return X86EMUL_CONTINUE;
6557 }
6558
6559 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6560 {
6561 kvm_emulate_wbinvd_noskip(vcpu);
6562 return kvm_skip_emulated_instruction(vcpu);
6563 }
6564 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6565
6566
6567
6568 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6569 {
6570 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6571 }
6572
6573 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6574 unsigned long *dest)
6575 {
6576 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6577 }
6578
6579 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6580 unsigned long value)
6581 {
6582
6583 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6584 }
6585
6586 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6587 {
6588 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6589 }
6590
6591 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6592 {
6593 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6594 unsigned long value;
6595
6596 switch (cr) {
6597 case 0:
6598 value = kvm_read_cr0(vcpu);
6599 break;
6600 case 2:
6601 value = vcpu->arch.cr2;
6602 break;
6603 case 3:
6604 value = kvm_read_cr3(vcpu);
6605 break;
6606 case 4:
6607 value = kvm_read_cr4(vcpu);
6608 break;
6609 case 8:
6610 value = kvm_get_cr8(vcpu);
6611 break;
6612 default:
6613 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6614 return 0;
6615 }
6616
6617 return value;
6618 }
6619
6620 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6621 {
6622 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6623 int res = 0;
6624
6625 switch (cr) {
6626 case 0:
6627 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6628 break;
6629 case 2:
6630 vcpu->arch.cr2 = val;
6631 break;
6632 case 3:
6633 res = kvm_set_cr3(vcpu, val);
6634 break;
6635 case 4:
6636 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6637 break;
6638 case 8:
6639 res = kvm_set_cr8(vcpu, val);
6640 break;
6641 default:
6642 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6643 res = -1;
6644 }
6645
6646 return res;
6647 }
6648
6649 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6650 {
6651 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6652 }
6653
6654 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6655 {
6656 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6657 }
6658
6659 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6660 {
6661 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6662 }
6663
6664 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6665 {
6666 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6667 }
6668
6669 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6670 {
6671 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6672 }
6673
6674 static unsigned long emulator_get_cached_segment_base(
6675 struct x86_emulate_ctxt *ctxt, int seg)
6676 {
6677 return get_segment_base(emul_to_vcpu(ctxt), seg);
6678 }
6679
6680 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6681 struct desc_struct *desc, u32 *base3,
6682 int seg)
6683 {
6684 struct kvm_segment var;
6685
6686 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6687 *selector = var.selector;
6688
6689 if (var.unusable) {
6690 memset(desc, 0, sizeof(*desc));
6691 if (base3)
6692 *base3 = 0;
6693 return false;
6694 }
6695
6696 if (var.g)
6697 var.limit >>= 12;
6698 set_desc_limit(desc, var.limit);
6699 set_desc_base(desc, (unsigned long)var.base);
6700 #ifdef CONFIG_X86_64
6701 if (base3)
6702 *base3 = var.base >> 32;
6703 #endif
6704 desc->type = var.type;
6705 desc->s = var.s;
6706 desc->dpl = var.dpl;
6707 desc->p = var.present;
6708 desc->avl = var.avl;
6709 desc->l = var.l;
6710 desc->d = var.db;
6711 desc->g = var.g;
6712
6713 return true;
6714 }
6715
6716 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6717 struct desc_struct *desc, u32 base3,
6718 int seg)
6719 {
6720 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6721 struct kvm_segment var;
6722
6723 var.selector = selector;
6724 var.base = get_desc_base(desc);
6725 #ifdef CONFIG_X86_64
6726 var.base |= ((u64)base3) << 32;
6727 #endif
6728 var.limit = get_desc_limit(desc);
6729 if (desc->g)
6730 var.limit = (var.limit << 12) | 0xfff;
6731 var.type = desc->type;
6732 var.dpl = desc->dpl;
6733 var.db = desc->d;
6734 var.s = desc->s;
6735 var.l = desc->l;
6736 var.g = desc->g;
6737 var.avl = desc->avl;
6738 var.present = desc->p;
6739 var.unusable = !var.present;
6740 var.padding = 0;
6741
6742 kvm_set_segment(vcpu, &var, seg);
6743 return;
6744 }
6745
6746 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6747 u32 msr_index, u64 *pdata)
6748 {
6749 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6750 int r;
6751
6752 r = kvm_get_msr(vcpu, msr_index, pdata);
6753
6754 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6755 /* Bounce to user space */
6756 return X86EMUL_IO_NEEDED;
6757 }
6758
6759 return r;
6760 }
6761
6762 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6763 u32 msr_index, u64 data)
6764 {
6765 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6766 int r;
6767
6768 r = kvm_set_msr(vcpu, msr_index, data);
6769
6770 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6771 /* Bounce to user space */
6772 return X86EMUL_IO_NEEDED;
6773 }
6774
6775 return r;
6776 }
6777
6778 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6779 {
6780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6781
6782 return vcpu->arch.smbase;
6783 }
6784
6785 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6786 {
6787 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6788
6789 vcpu->arch.smbase = smbase;
6790 }
6791
6792 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6793 u32 pmc)
6794 {
6795 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6796 }
6797
6798 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6799 u32 pmc, u64 *pdata)
6800 {
6801 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6802 }
6803
6804 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6805 {
6806 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6807 }
6808
6809 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6810 struct x86_instruction_info *info,
6811 enum x86_intercept_stage stage)
6812 {
6813 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6814 &ctxt->exception);
6815 }
6816
6817 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6818 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6819 bool exact_only)
6820 {
6821 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6822 }
6823
6824 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6825 {
6826 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6827 }
6828
6829 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6830 {
6831 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6832 }
6833
6834 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6835 {
6836 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6837 }
6838
6839 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6840 {
6841 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6842 }
6843
6844 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6845 {
6846 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6847 }
6848
6849 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6850 {
6851 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6852 }
6853
6854 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6855 {
6856 return emul_to_vcpu(ctxt)->arch.hflags;
6857 }
6858
6859 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6860 {
6861 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6862 }
6863
6864 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6865 const char *smstate)
6866 {
6867 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6868 }
6869
6870 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6871 {
6872 kvm_smm_changed(emul_to_vcpu(ctxt));
6873 }
6874
6875 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6876 {
6877 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6878 }
6879
6880 static const struct x86_emulate_ops emulate_ops = {
6881 .read_gpr = emulator_read_gpr,
6882 .write_gpr = emulator_write_gpr,
6883 .read_std = emulator_read_std,
6884 .write_std = emulator_write_std,
6885 .read_phys = kvm_read_guest_phys_system,
6886 .fetch = kvm_fetch_guest_virt,
6887 .read_emulated = emulator_read_emulated,
6888 .write_emulated = emulator_write_emulated,
6889 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6890 .invlpg = emulator_invlpg,
6891 .pio_in_emulated = emulator_pio_in_emulated,
6892 .pio_out_emulated = emulator_pio_out_emulated,
6893 .get_segment = emulator_get_segment,
6894 .set_segment = emulator_set_segment,
6895 .get_cached_segment_base = emulator_get_cached_segment_base,
6896 .get_gdt = emulator_get_gdt,
6897 .get_idt = emulator_get_idt,
6898 .set_gdt = emulator_set_gdt,
6899 .set_idt = emulator_set_idt,
6900 .get_cr = emulator_get_cr,
6901 .set_cr = emulator_set_cr,
6902 .cpl = emulator_get_cpl,
6903 .get_dr = emulator_get_dr,
6904 .set_dr = emulator_set_dr,
6905 .get_smbase = emulator_get_smbase,
6906 .set_smbase = emulator_set_smbase,
6907 .set_msr = emulator_set_msr,
6908 .get_msr = emulator_get_msr,
6909 .check_pmc = emulator_check_pmc,
6910 .read_pmc = emulator_read_pmc,
6911 .halt = emulator_halt,
6912 .wbinvd = emulator_wbinvd,
6913 .fix_hypercall = emulator_fix_hypercall,
6914 .intercept = emulator_intercept,
6915 .get_cpuid = emulator_get_cpuid,
6916 .guest_has_long_mode = emulator_guest_has_long_mode,
6917 .guest_has_movbe = emulator_guest_has_movbe,
6918 .guest_has_fxsr = emulator_guest_has_fxsr,
6919 .set_nmi_mask = emulator_set_nmi_mask,
6920 .get_hflags = emulator_get_hflags,
6921 .set_hflags = emulator_set_hflags,
6922 .pre_leave_smm = emulator_pre_leave_smm,
6923 .post_leave_smm = emulator_post_leave_smm,
6924 .set_xcr = emulator_set_xcr,
6925 };
6926
6927 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6928 {
6929 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6930 /*
6931 * an sti; sti; sequence only disable interrupts for the first
6932 * instruction. So, if the last instruction, be it emulated or
6933 * not, left the system with the INT_STI flag enabled, it
6934 * means that the last instruction is an sti. We should not
6935 * leave the flag on in this case. The same goes for mov ss
6936 */
6937 if (int_shadow & mask)
6938 mask = 0;
6939 if (unlikely(int_shadow || mask)) {
6940 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6941 if (!mask)
6942 kvm_make_request(KVM_REQ_EVENT, vcpu);
6943 }
6944 }
6945
6946 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6947 {
6948 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6949 if (ctxt->exception.vector == PF_VECTOR)
6950 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6951
6952 if (ctxt->exception.error_code_valid)
6953 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6954 ctxt->exception.error_code);
6955 else
6956 kvm_queue_exception(vcpu, ctxt->exception.vector);
6957 return false;
6958 }
6959
6960 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6961 {
6962 struct x86_emulate_ctxt *ctxt;
6963
6964 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6965 if (!ctxt) {
6966 pr_err("kvm: failed to allocate vcpu's emulator\n");
6967 return NULL;
6968 }
6969
6970 ctxt->vcpu = vcpu;
6971 ctxt->ops = &emulate_ops;
6972 vcpu->arch.emulate_ctxt = ctxt;
6973
6974 return ctxt;
6975 }
6976
6977 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6978 {
6979 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6980 int cs_db, cs_l;
6981
6982 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6983
6984 ctxt->gpa_available = false;
6985 ctxt->eflags = kvm_get_rflags(vcpu);
6986 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6987
6988 ctxt->eip = kvm_rip_read(vcpu);
6989 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6990 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6991 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6992 cs_db ? X86EMUL_MODE_PROT32 :
6993 X86EMUL_MODE_PROT16;
6994 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6995 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6996 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6997
6998 init_decode_cache(ctxt);
6999 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7000 }
7001
7002 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
7003 {
7004 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7005 int ret;
7006
7007 init_emulate_ctxt(vcpu);
7008
7009 ctxt->op_bytes = 2;
7010 ctxt->ad_bytes = 2;
7011 ctxt->_eip = ctxt->eip + inc_eip;
7012 ret = emulate_int_real(ctxt, irq);
7013
7014 if (ret != X86EMUL_CONTINUE) {
7015 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7016 } else {
7017 ctxt->eip = ctxt->_eip;
7018 kvm_rip_write(vcpu, ctxt->eip);
7019 kvm_set_rflags(vcpu, ctxt->eflags);
7020 }
7021 }
7022 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
7023
7024 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
7025 {
7026 ++vcpu->stat.insn_emulation_fail;
7027 trace_kvm_emulate_insn_failed(vcpu);
7028
7029 if (emulation_type & EMULTYPE_VMWARE_GP) {
7030 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7031 return 1;
7032 }
7033
7034 if (emulation_type & EMULTYPE_SKIP) {
7035 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7036 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7037 vcpu->run->internal.ndata = 0;
7038 return 0;
7039 }
7040
7041 kvm_queue_exception(vcpu, UD_VECTOR);
7042
7043 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
7044 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7045 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7046 vcpu->run->internal.ndata = 0;
7047 return 0;
7048 }
7049
7050 return 1;
7051 }
7052
7053 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7054 bool write_fault_to_shadow_pgtable,
7055 int emulation_type)
7056 {
7057 gpa_t gpa = cr2_or_gpa;
7058 kvm_pfn_t pfn;
7059
7060 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7061 return false;
7062
7063 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7064 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7065 return false;
7066
7067 if (!vcpu->arch.mmu->direct_map) {
7068 /*
7069 * Write permission should be allowed since only
7070 * write access need to be emulated.
7071 */
7072 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7073
7074 /*
7075 * If the mapping is invalid in guest, let cpu retry
7076 * it to generate fault.
7077 */
7078 if (gpa == UNMAPPED_GVA)
7079 return true;
7080 }
7081
7082 /*
7083 * Do not retry the unhandleable instruction if it faults on the
7084 * readonly host memory, otherwise it will goto a infinite loop:
7085 * retry instruction -> write #PF -> emulation fail -> retry
7086 * instruction -> ...
7087 */
7088 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
7089
7090 /*
7091 * If the instruction failed on the error pfn, it can not be fixed,
7092 * report the error to userspace.
7093 */
7094 if (is_error_noslot_pfn(pfn))
7095 return false;
7096
7097 kvm_release_pfn_clean(pfn);
7098
7099 /* The instructions are well-emulated on direct mmu. */
7100 if (vcpu->arch.mmu->direct_map) {
7101 unsigned int indirect_shadow_pages;
7102
7103 spin_lock(&vcpu->kvm->mmu_lock);
7104 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
7105 spin_unlock(&vcpu->kvm->mmu_lock);
7106
7107 if (indirect_shadow_pages)
7108 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7109
7110 return true;
7111 }
7112
7113 /*
7114 * if emulation was due to access to shadowed page table
7115 * and it failed try to unshadow page and re-enter the
7116 * guest to let CPU execute the instruction.
7117 */
7118 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7119
7120 /*
7121 * If the access faults on its page table, it can not
7122 * be fixed by unprotecting shadow page and it should
7123 * be reported to userspace.
7124 */
7125 return !write_fault_to_shadow_pgtable;
7126 }
7127
7128 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7129 gpa_t cr2_or_gpa, int emulation_type)
7130 {
7131 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7132 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7133
7134 last_retry_eip = vcpu->arch.last_retry_eip;
7135 last_retry_addr = vcpu->arch.last_retry_addr;
7136
7137 /*
7138 * If the emulation is caused by #PF and it is non-page_table
7139 * writing instruction, it means the VM-EXIT is caused by shadow
7140 * page protected, we can zap the shadow page and retry this
7141 * instruction directly.
7142 *
7143 * Note: if the guest uses a non-page-table modifying instruction
7144 * on the PDE that points to the instruction, then we will unmap
7145 * the instruction and go to an infinite loop. So, we cache the
7146 * last retried eip and the last fault address, if we meet the eip
7147 * and the address again, we can break out of the potential infinite
7148 * loop.
7149 */
7150 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7151
7152 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7153 return false;
7154
7155 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7156 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7157 return false;
7158
7159 if (x86_page_table_writing_insn(ctxt))
7160 return false;
7161
7162 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7163 return false;
7164
7165 vcpu->arch.last_retry_eip = ctxt->eip;
7166 vcpu->arch.last_retry_addr = cr2_or_gpa;
7167
7168 if (!vcpu->arch.mmu->direct_map)
7169 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7170
7171 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7172
7173 return true;
7174 }
7175
7176 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7177 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7178
7179 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7180 {
7181 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7182 /* This is a good place to trace that we are exiting SMM. */
7183 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7184
7185 /* Process a latched INIT or SMI, if any. */
7186 kvm_make_request(KVM_REQ_EVENT, vcpu);
7187 }
7188
7189 kvm_mmu_reset_context(vcpu);
7190 }
7191
7192 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7193 unsigned long *db)
7194 {
7195 u32 dr6 = 0;
7196 int i;
7197 u32 enable, rwlen;
7198
7199 enable = dr7;
7200 rwlen = dr7 >> 16;
7201 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7202 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7203 dr6 |= (1 << i);
7204 return dr6;
7205 }
7206
7207 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7208 {
7209 struct kvm_run *kvm_run = vcpu->run;
7210
7211 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7212 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
7213 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7214 kvm_run->debug.arch.exception = DB_VECTOR;
7215 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7216 return 0;
7217 }
7218 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7219 return 1;
7220 }
7221
7222 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7223 {
7224 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7225 int r;
7226
7227 r = kvm_x86_ops.skip_emulated_instruction(vcpu);
7228 if (unlikely(!r))
7229 return 0;
7230
7231 /*
7232 * rflags is the old, "raw" value of the flags. The new value has
7233 * not been saved yet.
7234 *
7235 * This is correct even for TF set by the guest, because "the
7236 * processor will not generate this exception after the instruction
7237 * that sets the TF flag".
7238 */
7239 if (unlikely(rflags & X86_EFLAGS_TF))
7240 r = kvm_vcpu_do_singlestep(vcpu);
7241 return r;
7242 }
7243 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7244
7245 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7246 {
7247 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7248 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7249 struct kvm_run *kvm_run = vcpu->run;
7250 unsigned long eip = kvm_get_linear_rip(vcpu);
7251 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7252 vcpu->arch.guest_debug_dr7,
7253 vcpu->arch.eff_db);
7254
7255 if (dr6 != 0) {
7256 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
7257 kvm_run->debug.arch.pc = eip;
7258 kvm_run->debug.arch.exception = DB_VECTOR;
7259 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7260 *r = 0;
7261 return true;
7262 }
7263 }
7264
7265 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7266 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7267 unsigned long eip = kvm_get_linear_rip(vcpu);
7268 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7269 vcpu->arch.dr7,
7270 vcpu->arch.db);
7271
7272 if (dr6 != 0) {
7273 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7274 *r = 1;
7275 return true;
7276 }
7277 }
7278
7279 return false;
7280 }
7281
7282 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7283 {
7284 switch (ctxt->opcode_len) {
7285 case 1:
7286 switch (ctxt->b) {
7287 case 0xe4: /* IN */
7288 case 0xe5:
7289 case 0xec:
7290 case 0xed:
7291 case 0xe6: /* OUT */
7292 case 0xe7:
7293 case 0xee:
7294 case 0xef:
7295 case 0x6c: /* INS */
7296 case 0x6d:
7297 case 0x6e: /* OUTS */
7298 case 0x6f:
7299 return true;
7300 }
7301 break;
7302 case 2:
7303 switch (ctxt->b) {
7304 case 0x33: /* RDPMC */
7305 return true;
7306 }
7307 break;
7308 }
7309
7310 return false;
7311 }
7312
7313 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7314 int emulation_type, void *insn, int insn_len)
7315 {
7316 int r;
7317 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7318 bool writeback = true;
7319 bool write_fault_to_spt;
7320
7321 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len)))
7322 return 1;
7323
7324 vcpu->arch.l1tf_flush_l1d = true;
7325
7326 /*
7327 * Clear write_fault_to_shadow_pgtable here to ensure it is
7328 * never reused.
7329 */
7330 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7331 vcpu->arch.write_fault_to_shadow_pgtable = false;
7332 kvm_clear_exception_queue(vcpu);
7333
7334 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7335 init_emulate_ctxt(vcpu);
7336
7337 /*
7338 * We will reenter on the same instruction since
7339 * we do not set complete_userspace_io. This does not
7340 * handle watchpoints yet, those would be handled in
7341 * the emulate_ops.
7342 */
7343 if (!(emulation_type & EMULTYPE_SKIP) &&
7344 kvm_vcpu_check_breakpoint(vcpu, &r))
7345 return r;
7346
7347 ctxt->interruptibility = 0;
7348 ctxt->have_exception = false;
7349 ctxt->exception.vector = -1;
7350 ctxt->perm_ok = false;
7351
7352 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7353
7354 r = x86_decode_insn(ctxt, insn, insn_len);
7355
7356 trace_kvm_emulate_insn_start(vcpu);
7357 ++vcpu->stat.insn_emulation;
7358 if (r != EMULATION_OK) {
7359 if ((emulation_type & EMULTYPE_TRAP_UD) ||
7360 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7361 kvm_queue_exception(vcpu, UD_VECTOR);
7362 return 1;
7363 }
7364 if (reexecute_instruction(vcpu, cr2_or_gpa,
7365 write_fault_to_spt,
7366 emulation_type))
7367 return 1;
7368 if (ctxt->have_exception) {
7369 /*
7370 * #UD should result in just EMULATION_FAILED, and trap-like
7371 * exception should not be encountered during decode.
7372 */
7373 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7374 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7375 inject_emulated_exception(vcpu);
7376 return 1;
7377 }
7378 return handle_emulation_failure(vcpu, emulation_type);
7379 }
7380 }
7381
7382 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7383 !is_vmware_backdoor_opcode(ctxt)) {
7384 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7385 return 1;
7386 }
7387
7388 /*
7389 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7390 * for kvm_skip_emulated_instruction(). The caller is responsible for
7391 * updating interruptibility state and injecting single-step #DBs.
7392 */
7393 if (emulation_type & EMULTYPE_SKIP) {
7394 kvm_rip_write(vcpu, ctxt->_eip);
7395 if (ctxt->eflags & X86_EFLAGS_RF)
7396 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7397 return 1;
7398 }
7399
7400 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7401 return 1;
7402
7403 /* this is needed for vmware backdoor interface to work since it
7404 changes registers values during IO operation */
7405 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7406 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7407 emulator_invalidate_register_cache(ctxt);
7408 }
7409
7410 restart:
7411 if (emulation_type & EMULTYPE_PF) {
7412 /* Save the faulting GPA (cr2) in the address field */
7413 ctxt->exception.address = cr2_or_gpa;
7414
7415 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7416 if (vcpu->arch.mmu->direct_map) {
7417 ctxt->gpa_available = true;
7418 ctxt->gpa_val = cr2_or_gpa;
7419 }
7420 } else {
7421 /* Sanitize the address out of an abundance of paranoia. */
7422 ctxt->exception.address = 0;
7423 }
7424
7425 r = x86_emulate_insn(ctxt);
7426
7427 if (r == EMULATION_INTERCEPTED)
7428 return 1;
7429
7430 if (r == EMULATION_FAILED) {
7431 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7432 emulation_type))
7433 return 1;
7434
7435 return handle_emulation_failure(vcpu, emulation_type);
7436 }
7437
7438 if (ctxt->have_exception) {
7439 r = 1;
7440 if (inject_emulated_exception(vcpu))
7441 return r;
7442 } else if (vcpu->arch.pio.count) {
7443 if (!vcpu->arch.pio.in) {
7444 /* FIXME: return into emulator if single-stepping. */
7445 vcpu->arch.pio.count = 0;
7446 } else {
7447 writeback = false;
7448 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7449 }
7450 r = 0;
7451 } else if (vcpu->mmio_needed) {
7452 ++vcpu->stat.mmio_exits;
7453
7454 if (!vcpu->mmio_is_write)
7455 writeback = false;
7456 r = 0;
7457 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7458 } else if (r == EMULATION_RESTART)
7459 goto restart;
7460 else
7461 r = 1;
7462
7463 if (writeback) {
7464 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7465 toggle_interruptibility(vcpu, ctxt->interruptibility);
7466 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7467 if (!ctxt->have_exception ||
7468 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7469 kvm_rip_write(vcpu, ctxt->eip);
7470 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7471 r = kvm_vcpu_do_singlestep(vcpu);
7472 if (kvm_x86_ops.update_emulated_instruction)
7473 kvm_x86_ops.update_emulated_instruction(vcpu);
7474 __kvm_set_rflags(vcpu, ctxt->eflags);
7475 }
7476
7477 /*
7478 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7479 * do nothing, and it will be requested again as soon as
7480 * the shadow expires. But we still need to check here,
7481 * because POPF has no interrupt shadow.
7482 */
7483 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7484 kvm_make_request(KVM_REQ_EVENT, vcpu);
7485 } else
7486 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7487
7488 return r;
7489 }
7490
7491 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7492 {
7493 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7494 }
7495 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7496
7497 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7498 void *insn, int insn_len)
7499 {
7500 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7501 }
7502 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7503
7504 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7505 {
7506 vcpu->arch.pio.count = 0;
7507 return 1;
7508 }
7509
7510 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7511 {
7512 vcpu->arch.pio.count = 0;
7513
7514 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7515 return 1;
7516
7517 return kvm_skip_emulated_instruction(vcpu);
7518 }
7519
7520 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7521 unsigned short port)
7522 {
7523 unsigned long val = kvm_rax_read(vcpu);
7524 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7525
7526 if (ret)
7527 return ret;
7528
7529 /*
7530 * Workaround userspace that relies on old KVM behavior of %rip being
7531 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7532 */
7533 if (port == 0x7e &&
7534 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7535 vcpu->arch.complete_userspace_io =
7536 complete_fast_pio_out_port_0x7e;
7537 kvm_skip_emulated_instruction(vcpu);
7538 } else {
7539 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7540 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7541 }
7542 return 0;
7543 }
7544
7545 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7546 {
7547 unsigned long val;
7548
7549 /* We should only ever be called with arch.pio.count equal to 1 */
7550 BUG_ON(vcpu->arch.pio.count != 1);
7551
7552 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7553 vcpu->arch.pio.count = 0;
7554 return 1;
7555 }
7556
7557 /* For size less than 4 we merge, else we zero extend */
7558 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7559
7560 /*
7561 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7562 * the copy and tracing
7563 */
7564 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7565 kvm_rax_write(vcpu, val);
7566
7567 return kvm_skip_emulated_instruction(vcpu);
7568 }
7569
7570 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7571 unsigned short port)
7572 {
7573 unsigned long val;
7574 int ret;
7575
7576 /* For size less than 4 we merge, else we zero extend */
7577 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7578
7579 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7580 if (ret) {
7581 kvm_rax_write(vcpu, val);
7582 return ret;
7583 }
7584
7585 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7586 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7587
7588 return 0;
7589 }
7590
7591 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7592 {
7593 int ret;
7594
7595 if (in)
7596 ret = kvm_fast_pio_in(vcpu, size, port);
7597 else
7598 ret = kvm_fast_pio_out(vcpu, size, port);
7599 return ret && kvm_skip_emulated_instruction(vcpu);
7600 }
7601 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7602
7603 static int kvmclock_cpu_down_prep(unsigned int cpu)
7604 {
7605 __this_cpu_write(cpu_tsc_khz, 0);
7606 return 0;
7607 }
7608
7609 static void tsc_khz_changed(void *data)
7610 {
7611 struct cpufreq_freqs *freq = data;
7612 unsigned long khz = 0;
7613
7614 if (data)
7615 khz = freq->new;
7616 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7617 khz = cpufreq_quick_get(raw_smp_processor_id());
7618 if (!khz)
7619 khz = tsc_khz;
7620 __this_cpu_write(cpu_tsc_khz, khz);
7621 }
7622
7623 #ifdef CONFIG_X86_64
7624 static void kvm_hyperv_tsc_notifier(void)
7625 {
7626 struct kvm *kvm;
7627 struct kvm_vcpu *vcpu;
7628 int cpu;
7629
7630 mutex_lock(&kvm_lock);
7631 list_for_each_entry(kvm, &vm_list, vm_list)
7632 kvm_make_mclock_inprogress_request(kvm);
7633
7634 hyperv_stop_tsc_emulation();
7635
7636 /* TSC frequency always matches when on Hyper-V */
7637 for_each_present_cpu(cpu)
7638 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7639 kvm_max_guest_tsc_khz = tsc_khz;
7640
7641 list_for_each_entry(kvm, &vm_list, vm_list) {
7642 struct kvm_arch *ka = &kvm->arch;
7643
7644 spin_lock(&ka->pvclock_gtod_sync_lock);
7645
7646 pvclock_update_vm_gtod_copy(kvm);
7647
7648 kvm_for_each_vcpu(cpu, vcpu, kvm)
7649 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7650
7651 kvm_for_each_vcpu(cpu, vcpu, kvm)
7652 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7653
7654 spin_unlock(&ka->pvclock_gtod_sync_lock);
7655 }
7656 mutex_unlock(&kvm_lock);
7657 }
7658 #endif
7659
7660 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7661 {
7662 struct kvm *kvm;
7663 struct kvm_vcpu *vcpu;
7664 int i, send_ipi = 0;
7665
7666 /*
7667 * We allow guests to temporarily run on slowing clocks,
7668 * provided we notify them after, or to run on accelerating
7669 * clocks, provided we notify them before. Thus time never
7670 * goes backwards.
7671 *
7672 * However, we have a problem. We can't atomically update
7673 * the frequency of a given CPU from this function; it is
7674 * merely a notifier, which can be called from any CPU.
7675 * Changing the TSC frequency at arbitrary points in time
7676 * requires a recomputation of local variables related to
7677 * the TSC for each VCPU. We must flag these local variables
7678 * to be updated and be sure the update takes place with the
7679 * new frequency before any guests proceed.
7680 *
7681 * Unfortunately, the combination of hotplug CPU and frequency
7682 * change creates an intractable locking scenario; the order
7683 * of when these callouts happen is undefined with respect to
7684 * CPU hotplug, and they can race with each other. As such,
7685 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7686 * undefined; you can actually have a CPU frequency change take
7687 * place in between the computation of X and the setting of the
7688 * variable. To protect against this problem, all updates of
7689 * the per_cpu tsc_khz variable are done in an interrupt
7690 * protected IPI, and all callers wishing to update the value
7691 * must wait for a synchronous IPI to complete (which is trivial
7692 * if the caller is on the CPU already). This establishes the
7693 * necessary total order on variable updates.
7694 *
7695 * Note that because a guest time update may take place
7696 * anytime after the setting of the VCPU's request bit, the
7697 * correct TSC value must be set before the request. However,
7698 * to ensure the update actually makes it to any guest which
7699 * starts running in hardware virtualization between the set
7700 * and the acquisition of the spinlock, we must also ping the
7701 * CPU after setting the request bit.
7702 *
7703 */
7704
7705 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7706
7707 mutex_lock(&kvm_lock);
7708 list_for_each_entry(kvm, &vm_list, vm_list) {
7709 kvm_for_each_vcpu(i, vcpu, kvm) {
7710 if (vcpu->cpu != cpu)
7711 continue;
7712 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7713 if (vcpu->cpu != raw_smp_processor_id())
7714 send_ipi = 1;
7715 }
7716 }
7717 mutex_unlock(&kvm_lock);
7718
7719 if (freq->old < freq->new && send_ipi) {
7720 /*
7721 * We upscale the frequency. Must make the guest
7722 * doesn't see old kvmclock values while running with
7723 * the new frequency, otherwise we risk the guest sees
7724 * time go backwards.
7725 *
7726 * In case we update the frequency for another cpu
7727 * (which might be in guest context) send an interrupt
7728 * to kick the cpu out of guest context. Next time
7729 * guest context is entered kvmclock will be updated,
7730 * so the guest will not see stale values.
7731 */
7732 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7733 }
7734 }
7735
7736 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7737 void *data)
7738 {
7739 struct cpufreq_freqs *freq = data;
7740 int cpu;
7741
7742 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7743 return 0;
7744 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7745 return 0;
7746
7747 for_each_cpu(cpu, freq->policy->cpus)
7748 __kvmclock_cpufreq_notifier(freq, cpu);
7749
7750 return 0;
7751 }
7752
7753 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7754 .notifier_call = kvmclock_cpufreq_notifier
7755 };
7756
7757 static int kvmclock_cpu_online(unsigned int cpu)
7758 {
7759 tsc_khz_changed(NULL);
7760 return 0;
7761 }
7762
7763 static void kvm_timer_init(void)
7764 {
7765 max_tsc_khz = tsc_khz;
7766
7767 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7768 #ifdef CONFIG_CPU_FREQ
7769 struct cpufreq_policy *policy;
7770 int cpu;
7771
7772 cpu = get_cpu();
7773 policy = cpufreq_cpu_get(cpu);
7774 if (policy) {
7775 if (policy->cpuinfo.max_freq)
7776 max_tsc_khz = policy->cpuinfo.max_freq;
7777 cpufreq_cpu_put(policy);
7778 }
7779 put_cpu();
7780 #endif
7781 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7782 CPUFREQ_TRANSITION_NOTIFIER);
7783 }
7784
7785 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7786 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7787 }
7788
7789 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7790 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7791
7792 int kvm_is_in_guest(void)
7793 {
7794 return __this_cpu_read(current_vcpu) != NULL;
7795 }
7796
7797 static int kvm_is_user_mode(void)
7798 {
7799 int user_mode = 3;
7800
7801 if (__this_cpu_read(current_vcpu))
7802 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7803
7804 return user_mode != 0;
7805 }
7806
7807 static unsigned long kvm_get_guest_ip(void)
7808 {
7809 unsigned long ip = 0;
7810
7811 if (__this_cpu_read(current_vcpu))
7812 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7813
7814 return ip;
7815 }
7816
7817 static void kvm_handle_intel_pt_intr(void)
7818 {
7819 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7820
7821 kvm_make_request(KVM_REQ_PMI, vcpu);
7822 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7823 (unsigned long *)&vcpu->arch.pmu.global_status);
7824 }
7825
7826 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7827 .is_in_guest = kvm_is_in_guest,
7828 .is_user_mode = kvm_is_user_mode,
7829 .get_guest_ip = kvm_get_guest_ip,
7830 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7831 };
7832
7833 #ifdef CONFIG_X86_64
7834 static void pvclock_gtod_update_fn(struct work_struct *work)
7835 {
7836 struct kvm *kvm;
7837
7838 struct kvm_vcpu *vcpu;
7839 int i;
7840
7841 mutex_lock(&kvm_lock);
7842 list_for_each_entry(kvm, &vm_list, vm_list)
7843 kvm_for_each_vcpu(i, vcpu, kvm)
7844 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7845 atomic_set(&kvm_guest_has_master_clock, 0);
7846 mutex_unlock(&kvm_lock);
7847 }
7848
7849 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7850
7851 /*
7852 * Notification about pvclock gtod data update.
7853 */
7854 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7855 void *priv)
7856 {
7857 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7858 struct timekeeper *tk = priv;
7859
7860 update_pvclock_gtod(tk);
7861
7862 /* disable master clock if host does not trust, or does not
7863 * use, TSC based clocksource.
7864 */
7865 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7866 atomic_read(&kvm_guest_has_master_clock) != 0)
7867 queue_work(system_long_wq, &pvclock_gtod_work);
7868
7869 return 0;
7870 }
7871
7872 static struct notifier_block pvclock_gtod_notifier = {
7873 .notifier_call = pvclock_gtod_notify,
7874 };
7875 #endif
7876
7877 int kvm_arch_init(void *opaque)
7878 {
7879 struct kvm_x86_init_ops *ops = opaque;
7880 int r;
7881
7882 if (kvm_x86_ops.hardware_enable) {
7883 printk(KERN_ERR "kvm: already loaded the other module\n");
7884 r = -EEXIST;
7885 goto out;
7886 }
7887
7888 if (!ops->cpu_has_kvm_support()) {
7889 pr_err_ratelimited("kvm: no hardware support\n");
7890 r = -EOPNOTSUPP;
7891 goto out;
7892 }
7893 if (ops->disabled_by_bios()) {
7894 pr_err_ratelimited("kvm: disabled by bios\n");
7895 r = -EOPNOTSUPP;
7896 goto out;
7897 }
7898
7899 /*
7900 * KVM explicitly assumes that the guest has an FPU and
7901 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7902 * vCPU's FPU state as a fxregs_state struct.
7903 */
7904 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7905 printk(KERN_ERR "kvm: inadequate fpu\n");
7906 r = -EOPNOTSUPP;
7907 goto out;
7908 }
7909
7910 r = -ENOMEM;
7911 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7912 __alignof__(struct fpu), SLAB_ACCOUNT,
7913 NULL);
7914 if (!x86_fpu_cache) {
7915 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7916 goto out;
7917 }
7918
7919 x86_emulator_cache = kvm_alloc_emulator_cache();
7920 if (!x86_emulator_cache) {
7921 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7922 goto out_free_x86_fpu_cache;
7923 }
7924
7925 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7926 if (!user_return_msrs) {
7927 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7928 goto out_free_x86_emulator_cache;
7929 }
7930
7931 r = kvm_mmu_module_init();
7932 if (r)
7933 goto out_free_percpu;
7934
7935 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7936 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7937 PT_PRESENT_MASK, 0, sme_me_mask);
7938 kvm_timer_init();
7939
7940 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7941
7942 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7943 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7944 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7945 }
7946
7947 kvm_lapic_init();
7948 if (pi_inject_timer == -1)
7949 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7950 #ifdef CONFIG_X86_64
7951 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7952
7953 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7954 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7955 #endif
7956
7957 return 0;
7958
7959 out_free_percpu:
7960 free_percpu(user_return_msrs);
7961 out_free_x86_emulator_cache:
7962 kmem_cache_destroy(x86_emulator_cache);
7963 out_free_x86_fpu_cache:
7964 kmem_cache_destroy(x86_fpu_cache);
7965 out:
7966 return r;
7967 }
7968
7969 void kvm_arch_exit(void)
7970 {
7971 #ifdef CONFIG_X86_64
7972 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7973 clear_hv_tscchange_cb();
7974 #endif
7975 kvm_lapic_exit();
7976 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7977
7978 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7979 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7980 CPUFREQ_TRANSITION_NOTIFIER);
7981 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7982 #ifdef CONFIG_X86_64
7983 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7984 #endif
7985 kvm_x86_ops.hardware_enable = NULL;
7986 kvm_mmu_module_exit();
7987 free_percpu(user_return_msrs);
7988 kmem_cache_destroy(x86_fpu_cache);
7989 }
7990
7991 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason)
7992 {
7993 ++vcpu->stat.halt_exits;
7994 if (lapic_in_kernel(vcpu)) {
7995 vcpu->arch.mp_state = state;
7996 return 1;
7997 } else {
7998 vcpu->run->exit_reason = reason;
7999 return 0;
8000 }
8001 }
8002
8003 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8004 {
8005 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
8006 }
8007 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
8008
8009 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
8010 {
8011 int ret = kvm_skip_emulated_instruction(vcpu);
8012 /*
8013 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
8014 * KVM_EXIT_DEBUG here.
8015 */
8016 return kvm_vcpu_halt(vcpu) && ret;
8017 }
8018 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
8019
8020 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
8021 {
8022 int ret = kvm_skip_emulated_instruction(vcpu);
8023
8024 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret;
8025 }
8026 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
8027
8028 #ifdef CONFIG_X86_64
8029 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
8030 unsigned long clock_type)
8031 {
8032 struct kvm_clock_pairing clock_pairing;
8033 struct timespec64 ts;
8034 u64 cycle;
8035 int ret;
8036
8037 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
8038 return -KVM_EOPNOTSUPP;
8039
8040 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
8041 return -KVM_EOPNOTSUPP;
8042
8043 clock_pairing.sec = ts.tv_sec;
8044 clock_pairing.nsec = ts.tv_nsec;
8045 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
8046 clock_pairing.flags = 0;
8047 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
8048
8049 ret = 0;
8050 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
8051 sizeof(struct kvm_clock_pairing)))
8052 ret = -KVM_EFAULT;
8053
8054 return ret;
8055 }
8056 #endif
8057
8058 /*
8059 * kvm_pv_kick_cpu_op: Kick a vcpu.
8060 *
8061 * @apicid - apicid of vcpu to be kicked.
8062 */
8063 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
8064 {
8065 struct kvm_lapic_irq lapic_irq;
8066
8067 lapic_irq.shorthand = APIC_DEST_NOSHORT;
8068 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
8069 lapic_irq.level = 0;
8070 lapic_irq.dest_id = apicid;
8071 lapic_irq.msi_redir_hint = false;
8072
8073 lapic_irq.delivery_mode = APIC_DM_REMRD;
8074 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
8075 }
8076
8077 bool kvm_apicv_activated(struct kvm *kvm)
8078 {
8079 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
8080 }
8081 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
8082
8083 void kvm_apicv_init(struct kvm *kvm, bool enable)
8084 {
8085 if (enable)
8086 clear_bit(APICV_INHIBIT_REASON_DISABLE,
8087 &kvm->arch.apicv_inhibit_reasons);
8088 else
8089 set_bit(APICV_INHIBIT_REASON_DISABLE,
8090 &kvm->arch.apicv_inhibit_reasons);
8091 }
8092 EXPORT_SYMBOL_GPL(kvm_apicv_init);
8093
8094 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
8095 {
8096 struct kvm_vcpu *target = NULL;
8097 struct kvm_apic_map *map;
8098
8099 rcu_read_lock();
8100 map = rcu_dereference(kvm->arch.apic_map);
8101
8102 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
8103 target = map->phys_map[dest_id]->vcpu;
8104
8105 rcu_read_unlock();
8106
8107 if (target && READ_ONCE(target->ready))
8108 kvm_vcpu_yield_to(target);
8109 }
8110
8111 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
8112 {
8113 unsigned long nr, a0, a1, a2, a3, ret;
8114 int op_64_bit;
8115
8116 if (kvm_hv_hypercall_enabled(vcpu->kvm))
8117 return kvm_hv_hypercall(vcpu);
8118
8119 nr = kvm_rax_read(vcpu);
8120 a0 = kvm_rbx_read(vcpu);
8121 a1 = kvm_rcx_read(vcpu);
8122 a2 = kvm_rdx_read(vcpu);
8123 a3 = kvm_rsi_read(vcpu);
8124
8125 trace_kvm_hypercall(nr, a0, a1, a2, a3);
8126
8127 op_64_bit = is_64_bit_mode(vcpu);
8128 if (!op_64_bit) {
8129 nr &= 0xFFFFFFFF;
8130 a0 &= 0xFFFFFFFF;
8131 a1 &= 0xFFFFFFFF;
8132 a2 &= 0xFFFFFFFF;
8133 a3 &= 0xFFFFFFFF;
8134 }
8135
8136 if (kvm_x86_ops.get_cpl(vcpu) != 0) {
8137 ret = -KVM_EPERM;
8138 goto out;
8139 }
8140
8141 ret = -KVM_ENOSYS;
8142
8143 switch (nr) {
8144 case KVM_HC_VAPIC_POLL_IRQ:
8145 ret = 0;
8146 break;
8147 case KVM_HC_KICK_CPU:
8148 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
8149 break;
8150
8151 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8152 kvm_sched_yield(vcpu->kvm, a1);
8153 ret = 0;
8154 break;
8155 #ifdef CONFIG_X86_64
8156 case KVM_HC_CLOCK_PAIRING:
8157 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8158 break;
8159 #endif
8160 case KVM_HC_SEND_IPI:
8161 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
8162 break;
8163
8164 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8165 break;
8166 case KVM_HC_SCHED_YIELD:
8167 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
8168 break;
8169
8170 kvm_sched_yield(vcpu->kvm, a0);
8171 ret = 0;
8172 break;
8173 default:
8174 ret = -KVM_ENOSYS;
8175 break;
8176 }
8177 out:
8178 if (!op_64_bit)
8179 ret = (u32)ret;
8180 kvm_rax_write(vcpu, ret);
8181
8182 ++vcpu->stat.hypercalls;
8183 return kvm_skip_emulated_instruction(vcpu);
8184 }
8185 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8186
8187 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8188 {
8189 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8190 char instruction[3];
8191 unsigned long rip = kvm_rip_read(vcpu);
8192
8193 kvm_x86_ops.patch_hypercall(vcpu, instruction);
8194
8195 return emulator_write_emulated(ctxt, rip, instruction, 3,
8196 &ctxt->exception);
8197 }
8198
8199 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8200 {
8201 return vcpu->run->request_interrupt_window &&
8202 likely(!pic_in_kernel(vcpu->kvm));
8203 }
8204
8205 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8206 {
8207 struct kvm_run *kvm_run = vcpu->run;
8208
8209 /*
8210 * if_flag is obsolete and useless, so do not bother
8211 * setting it for SEV-ES guests. Userspace can just
8212 * use kvm_run->ready_for_interrupt_injection.
8213 */
8214 kvm_run->if_flag = !vcpu->arch.guest_state_protected
8215 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8216
8217 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
8218 kvm_run->cr8 = kvm_get_cr8(vcpu);
8219 kvm_run->apic_base = kvm_get_apic_base(vcpu);
8220 kvm_run->ready_for_interrupt_injection =
8221 pic_in_kernel(vcpu->kvm) ||
8222 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8223 }
8224
8225 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8226 {
8227 int max_irr, tpr;
8228
8229 if (!kvm_x86_ops.update_cr8_intercept)
8230 return;
8231
8232 if (!lapic_in_kernel(vcpu))
8233 return;
8234
8235 if (vcpu->arch.apicv_active)
8236 return;
8237
8238 if (!vcpu->arch.apic->vapic_addr)
8239 max_irr = kvm_lapic_find_highest_irr(vcpu);
8240 else
8241 max_irr = -1;
8242
8243 if (max_irr != -1)
8244 max_irr >>= 4;
8245
8246 tpr = kvm_lapic_get_cr8(vcpu);
8247
8248 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
8249 }
8250
8251 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8252 {
8253 int r;
8254 bool can_inject = true;
8255
8256 /* try to reinject previous events if any */
8257
8258 if (vcpu->arch.exception.injected) {
8259 kvm_x86_ops.queue_exception(vcpu);
8260 can_inject = false;
8261 }
8262 /*
8263 * Do not inject an NMI or interrupt if there is a pending
8264 * exception. Exceptions and interrupts are recognized at
8265 * instruction boundaries, i.e. the start of an instruction.
8266 * Trap-like exceptions, e.g. #DB, have higher priority than
8267 * NMIs and interrupts, i.e. traps are recognized before an
8268 * NMI/interrupt that's pending on the same instruction.
8269 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8270 * priority, but are only generated (pended) during instruction
8271 * execution, i.e. a pending fault-like exception means the
8272 * fault occurred on the *previous* instruction and must be
8273 * serviced prior to recognizing any new events in order to
8274 * fully complete the previous instruction.
8275 */
8276 else if (!vcpu->arch.exception.pending) {
8277 if (vcpu->arch.nmi_injected) {
8278 kvm_x86_ops.set_nmi(vcpu);
8279 can_inject = false;
8280 } else if (vcpu->arch.interrupt.injected) {
8281 kvm_x86_ops.set_irq(vcpu);
8282 can_inject = false;
8283 }
8284 }
8285
8286 WARN_ON_ONCE(vcpu->arch.exception.injected &&
8287 vcpu->arch.exception.pending);
8288
8289 /*
8290 * Call check_nested_events() even if we reinjected a previous event
8291 * in order for caller to determine if it should require immediate-exit
8292 * from L2 to L1 due to pending L1 events which require exit
8293 * from L2 to L1.
8294 */
8295 if (is_guest_mode(vcpu)) {
8296 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8297 if (r < 0)
8298 goto busy;
8299 }
8300
8301 /* try to inject new event if pending */
8302 if (vcpu->arch.exception.pending) {
8303 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8304 vcpu->arch.exception.has_error_code,
8305 vcpu->arch.exception.error_code);
8306
8307 vcpu->arch.exception.pending = false;
8308 vcpu->arch.exception.injected = true;
8309
8310 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8311 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8312 X86_EFLAGS_RF);
8313
8314 if (vcpu->arch.exception.nr == DB_VECTOR) {
8315 kvm_deliver_exception_payload(vcpu);
8316 if (vcpu->arch.dr7 & DR7_GD) {
8317 vcpu->arch.dr7 &= ~DR7_GD;
8318 kvm_update_dr7(vcpu);
8319 }
8320 }
8321
8322 kvm_x86_ops.queue_exception(vcpu);
8323 can_inject = false;
8324 }
8325
8326 /*
8327 * Finally, inject interrupt events. If an event cannot be injected
8328 * due to architectural conditions (e.g. IF=0) a window-open exit
8329 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
8330 * and can architecturally be injected, but we cannot do it right now:
8331 * an interrupt could have arrived just now and we have to inject it
8332 * as a vmexit, or there could already an event in the queue, which is
8333 * indicated by can_inject. In that case we request an immediate exit
8334 * in order to make progress and get back here for another iteration.
8335 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8336 */
8337 if (vcpu->arch.smi_pending) {
8338 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
8339 if (r < 0)
8340 goto busy;
8341 if (r) {
8342 vcpu->arch.smi_pending = false;
8343 ++vcpu->arch.smi_count;
8344 enter_smm(vcpu);
8345 can_inject = false;
8346 } else
8347 kvm_x86_ops.enable_smi_window(vcpu);
8348 }
8349
8350 if (vcpu->arch.nmi_pending) {
8351 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
8352 if (r < 0)
8353 goto busy;
8354 if (r) {
8355 --vcpu->arch.nmi_pending;
8356 vcpu->arch.nmi_injected = true;
8357 kvm_x86_ops.set_nmi(vcpu);
8358 can_inject = false;
8359 WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
8360 }
8361 if (vcpu->arch.nmi_pending)
8362 kvm_x86_ops.enable_nmi_window(vcpu);
8363 }
8364
8365 if (kvm_cpu_has_injectable_intr(vcpu)) {
8366 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
8367 if (r < 0)
8368 goto busy;
8369 if (r) {
8370 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8371 kvm_x86_ops.set_irq(vcpu);
8372 WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
8373 }
8374 if (kvm_cpu_has_injectable_intr(vcpu))
8375 kvm_x86_ops.enable_irq_window(vcpu);
8376 }
8377
8378 if (is_guest_mode(vcpu) &&
8379 kvm_x86_ops.nested_ops->hv_timer_pending &&
8380 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8381 *req_immediate_exit = true;
8382
8383 WARN_ON(vcpu->arch.exception.pending);
8384 return;
8385
8386 busy:
8387 *req_immediate_exit = true;
8388 return;
8389 }
8390
8391 static void process_nmi(struct kvm_vcpu *vcpu)
8392 {
8393 unsigned limit = 2;
8394
8395 /*
8396 * x86 is limited to one NMI running, and one NMI pending after it.
8397 * If an NMI is already in progress, limit further NMIs to just one.
8398 * Otherwise, allow two (and we'll inject the first one immediately).
8399 */
8400 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
8401 limit = 1;
8402
8403 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8404 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8405 kvm_make_request(KVM_REQ_EVENT, vcpu);
8406 }
8407
8408 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8409 {
8410 u32 flags = 0;
8411 flags |= seg->g << 23;
8412 flags |= seg->db << 22;
8413 flags |= seg->l << 21;
8414 flags |= seg->avl << 20;
8415 flags |= seg->present << 15;
8416 flags |= seg->dpl << 13;
8417 flags |= seg->s << 12;
8418 flags |= seg->type << 8;
8419 return flags;
8420 }
8421
8422 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8423 {
8424 struct kvm_segment seg;
8425 int offset;
8426
8427 kvm_get_segment(vcpu, &seg, n);
8428 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8429
8430 if (n < 3)
8431 offset = 0x7f84 + n * 12;
8432 else
8433 offset = 0x7f2c + (n - 3) * 12;
8434
8435 put_smstate(u32, buf, offset + 8, seg.base);
8436 put_smstate(u32, buf, offset + 4, seg.limit);
8437 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8438 }
8439
8440 #ifdef CONFIG_X86_64
8441 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8442 {
8443 struct kvm_segment seg;
8444 int offset;
8445 u16 flags;
8446
8447 kvm_get_segment(vcpu, &seg, n);
8448 offset = 0x7e00 + n * 16;
8449
8450 flags = enter_smm_get_segment_flags(&seg) >> 8;
8451 put_smstate(u16, buf, offset, seg.selector);
8452 put_smstate(u16, buf, offset + 2, flags);
8453 put_smstate(u32, buf, offset + 4, seg.limit);
8454 put_smstate(u64, buf, offset + 8, seg.base);
8455 }
8456 #endif
8457
8458 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8459 {
8460 struct desc_ptr dt;
8461 struct kvm_segment seg;
8462 unsigned long val;
8463 int i;
8464
8465 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8466 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8467 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8468 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8469
8470 for (i = 0; i < 8; i++)
8471 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8472
8473 kvm_get_dr(vcpu, 6, &val);
8474 put_smstate(u32, buf, 0x7fcc, (u32)val);
8475 kvm_get_dr(vcpu, 7, &val);
8476 put_smstate(u32, buf, 0x7fc8, (u32)val);
8477
8478 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8479 put_smstate(u32, buf, 0x7fc4, seg.selector);
8480 put_smstate(u32, buf, 0x7f64, seg.base);
8481 put_smstate(u32, buf, 0x7f60, seg.limit);
8482 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8483
8484 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8485 put_smstate(u32, buf, 0x7fc0, seg.selector);
8486 put_smstate(u32, buf, 0x7f80, seg.base);
8487 put_smstate(u32, buf, 0x7f7c, seg.limit);
8488 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8489
8490 kvm_x86_ops.get_gdt(vcpu, &dt);
8491 put_smstate(u32, buf, 0x7f74, dt.address);
8492 put_smstate(u32, buf, 0x7f70, dt.size);
8493
8494 kvm_x86_ops.get_idt(vcpu, &dt);
8495 put_smstate(u32, buf, 0x7f58, dt.address);
8496 put_smstate(u32, buf, 0x7f54, dt.size);
8497
8498 for (i = 0; i < 6; i++)
8499 enter_smm_save_seg_32(vcpu, buf, i);
8500
8501 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8502
8503 /* revision id */
8504 put_smstate(u32, buf, 0x7efc, 0x00020000);
8505 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8506 }
8507
8508 #ifdef CONFIG_X86_64
8509 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8510 {
8511 struct desc_ptr dt;
8512 struct kvm_segment seg;
8513 unsigned long val;
8514 int i;
8515
8516 for (i = 0; i < 16; i++)
8517 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8518
8519 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8520 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8521
8522 kvm_get_dr(vcpu, 6, &val);
8523 put_smstate(u64, buf, 0x7f68, val);
8524 kvm_get_dr(vcpu, 7, &val);
8525 put_smstate(u64, buf, 0x7f60, val);
8526
8527 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8528 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8529 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8530
8531 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8532
8533 /* revision id */
8534 put_smstate(u32, buf, 0x7efc, 0x00020064);
8535
8536 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8537
8538 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8539 put_smstate(u16, buf, 0x7e90, seg.selector);
8540 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8541 put_smstate(u32, buf, 0x7e94, seg.limit);
8542 put_smstate(u64, buf, 0x7e98, seg.base);
8543
8544 kvm_x86_ops.get_idt(vcpu, &dt);
8545 put_smstate(u32, buf, 0x7e84, dt.size);
8546 put_smstate(u64, buf, 0x7e88, dt.address);
8547
8548 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8549 put_smstate(u16, buf, 0x7e70, seg.selector);
8550 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8551 put_smstate(u32, buf, 0x7e74, seg.limit);
8552 put_smstate(u64, buf, 0x7e78, seg.base);
8553
8554 kvm_x86_ops.get_gdt(vcpu, &dt);
8555 put_smstate(u32, buf, 0x7e64, dt.size);
8556 put_smstate(u64, buf, 0x7e68, dt.address);
8557
8558 for (i = 0; i < 6; i++)
8559 enter_smm_save_seg_64(vcpu, buf, i);
8560 }
8561 #endif
8562
8563 static void enter_smm(struct kvm_vcpu *vcpu)
8564 {
8565 struct kvm_segment cs, ds;
8566 struct desc_ptr dt;
8567 char buf[512];
8568 u32 cr0;
8569
8570 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8571 memset(buf, 0, 512);
8572 #ifdef CONFIG_X86_64
8573 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8574 enter_smm_save_state_64(vcpu, buf);
8575 else
8576 #endif
8577 enter_smm_save_state_32(vcpu, buf);
8578
8579 /*
8580 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8581 * vCPU state (e.g. leave guest mode) after we've saved the state into
8582 * the SMM state-save area.
8583 */
8584 kvm_x86_ops.pre_enter_smm(vcpu, buf);
8585
8586 vcpu->arch.hflags |= HF_SMM_MASK;
8587 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8588
8589 if (kvm_x86_ops.get_nmi_mask(vcpu))
8590 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8591 else
8592 kvm_x86_ops.set_nmi_mask(vcpu, true);
8593
8594 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8595 kvm_rip_write(vcpu, 0x8000);
8596
8597 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8598 kvm_x86_ops.set_cr0(vcpu, cr0);
8599 vcpu->arch.cr0 = cr0;
8600
8601 kvm_x86_ops.set_cr4(vcpu, 0);
8602
8603 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8604 dt.address = dt.size = 0;
8605 kvm_x86_ops.set_idt(vcpu, &dt);
8606
8607 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8608
8609 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8610 cs.base = vcpu->arch.smbase;
8611
8612 ds.selector = 0;
8613 ds.base = 0;
8614
8615 cs.limit = ds.limit = 0xffffffff;
8616 cs.type = ds.type = 0x3;
8617 cs.dpl = ds.dpl = 0;
8618 cs.db = ds.db = 0;
8619 cs.s = ds.s = 1;
8620 cs.l = ds.l = 0;
8621 cs.g = ds.g = 1;
8622 cs.avl = ds.avl = 0;
8623 cs.present = ds.present = 1;
8624 cs.unusable = ds.unusable = 0;
8625 cs.padding = ds.padding = 0;
8626
8627 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8628 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8629 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8630 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8631 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8632 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8633
8634 #ifdef CONFIG_X86_64
8635 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8636 kvm_x86_ops.set_efer(vcpu, 0);
8637 #endif
8638
8639 kvm_update_cpuid_runtime(vcpu);
8640 kvm_mmu_reset_context(vcpu);
8641 }
8642
8643 static void process_smi(struct kvm_vcpu *vcpu)
8644 {
8645 vcpu->arch.smi_pending = true;
8646 kvm_make_request(KVM_REQ_EVENT, vcpu);
8647 }
8648
8649 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8650 unsigned long *vcpu_bitmap)
8651 {
8652 cpumask_var_t cpus;
8653
8654 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8655
8656 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8657 NULL, vcpu_bitmap, cpus);
8658
8659 free_cpumask_var(cpus);
8660 }
8661
8662 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8663 {
8664 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8665 }
8666
8667 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8668 {
8669 if (!lapic_in_kernel(vcpu))
8670 return;
8671
8672 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8673 kvm_apic_update_apicv(vcpu);
8674 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8675 }
8676 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8677
8678 /*
8679 * NOTE: Do not hold any lock prior to calling this.
8680 *
8681 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8682 * locked, because it calls __x86_set_memory_region() which does
8683 * synchronize_srcu(&kvm->srcu).
8684 */
8685 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8686 {
8687 struct kvm_vcpu *except;
8688 unsigned long old, new, expected;
8689
8690 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8691 !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8692 return;
8693
8694 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8695 do {
8696 expected = new = old;
8697 if (activate)
8698 __clear_bit(bit, &new);
8699 else
8700 __set_bit(bit, &new);
8701 if (new == old)
8702 break;
8703 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8704 } while (old != expected);
8705
8706 if (!!old == !!new)
8707 return;
8708
8709 trace_kvm_apicv_update_request(activate, bit);
8710 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8711 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8712
8713 /*
8714 * Sending request to update APICV for all other vcpus,
8715 * while update the calling vcpu immediately instead of
8716 * waiting for another #VMEXIT to handle the request.
8717 */
8718 except = kvm_get_running_vcpu();
8719 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8720 except);
8721 if (except)
8722 kvm_vcpu_update_apicv(except);
8723 }
8724 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8725
8726 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8727 {
8728 if (!kvm_apic_present(vcpu))
8729 return;
8730
8731 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8732
8733 if (irqchip_split(vcpu->kvm))
8734 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8735 else {
8736 if (vcpu->arch.apicv_active)
8737 kvm_x86_ops.sync_pir_to_irr(vcpu);
8738 if (ioapic_in_kernel(vcpu->kvm))
8739 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8740 }
8741
8742 if (is_guest_mode(vcpu))
8743 vcpu->arch.load_eoi_exitmap_pending = true;
8744 else
8745 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8746 }
8747
8748 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8749 {
8750 u64 eoi_exit_bitmap[4];
8751
8752 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8753 return;
8754
8755 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8756 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8757 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8758 }
8759
8760 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8761 unsigned long start, unsigned long end)
8762 {
8763 unsigned long apic_address;
8764
8765 /*
8766 * The physical address of apic access page is stored in the VMCS.
8767 * Update it when it becomes invalid.
8768 */
8769 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8770 if (start <= apic_address && apic_address < end)
8771 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8772 }
8773
8774 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8775 {
8776 if (!lapic_in_kernel(vcpu))
8777 return;
8778
8779 if (!kvm_x86_ops.set_apic_access_page_addr)
8780 return;
8781
8782 kvm_x86_ops.set_apic_access_page_addr(vcpu);
8783 }
8784
8785 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8786 {
8787 smp_send_reschedule(vcpu->cpu);
8788 }
8789 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8790
8791 /*
8792 * Returns 1 to let vcpu_run() continue the guest execution loop without
8793 * exiting to the userspace. Otherwise, the value will be returned to the
8794 * userspace.
8795 */
8796 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8797 {
8798 int r;
8799 bool req_int_win =
8800 dm_request_for_irq_injection(vcpu) &&
8801 kvm_cpu_accept_dm_intr(vcpu);
8802 fastpath_t exit_fastpath;
8803
8804 bool req_immediate_exit = false;
8805
8806 /* Forbid vmenter if vcpu dirty ring is soft-full */
8807 if (unlikely(vcpu->kvm->dirty_ring_size &&
8808 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
8809 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
8810 trace_kvm_dirty_ring_exit(vcpu);
8811 r = 0;
8812 goto out;
8813 }
8814
8815 if (kvm_request_pending(vcpu)) {
8816 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8817 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8818 r = 0;
8819 goto out;
8820 }
8821 }
8822 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8823 kvm_mmu_unload(vcpu);
8824 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8825 __kvm_migrate_timers(vcpu);
8826 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8827 kvm_gen_update_masterclock(vcpu->kvm);
8828 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8829 kvm_gen_kvmclock_update(vcpu);
8830 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8831 r = kvm_guest_time_update(vcpu);
8832 if (unlikely(r))
8833 goto out;
8834 }
8835 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8836 kvm_mmu_sync_roots(vcpu);
8837 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8838 kvm_mmu_load_pgd(vcpu);
8839 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8840 kvm_vcpu_flush_tlb_all(vcpu);
8841
8842 /* Flushing all ASIDs flushes the current ASID... */
8843 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8844 }
8845 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8846 kvm_vcpu_flush_tlb_current(vcpu);
8847 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8848 kvm_vcpu_flush_tlb_guest(vcpu);
8849
8850 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8851 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8852 r = 0;
8853 goto out;
8854 }
8855 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8856 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8857 vcpu->mmio_needed = 0;
8858 r = 0;
8859 goto out;
8860 }
8861 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8862 /* Page is swapped out. Do synthetic halt */
8863 vcpu->arch.apf.halted = true;
8864 r = 1;
8865 goto out;
8866 }
8867 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8868 record_steal_time(vcpu);
8869 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8870 process_smi(vcpu);
8871 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8872 process_nmi(vcpu);
8873 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8874 kvm_pmu_handle_event(vcpu);
8875 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8876 kvm_pmu_deliver_pmi(vcpu);
8877 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8878 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8879 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8880 vcpu->arch.ioapic_handled_vectors)) {
8881 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8882 vcpu->run->eoi.vector =
8883 vcpu->arch.pending_ioapic_eoi;
8884 r = 0;
8885 goto out;
8886 }
8887 }
8888 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8889 vcpu_scan_ioapic(vcpu);
8890 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8891 vcpu_load_eoi_exitmap(vcpu);
8892 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8893 kvm_vcpu_reload_apic_access_page(vcpu);
8894 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8895 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8896 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8897 r = 0;
8898 goto out;
8899 }
8900 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8901 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8902 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8903 r = 0;
8904 goto out;
8905 }
8906 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8907 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8908 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8909 r = 0;
8910 goto out;
8911 }
8912
8913 /*
8914 * KVM_REQ_HV_STIMER has to be processed after
8915 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8916 * depend on the guest clock being up-to-date
8917 */
8918 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8919 kvm_hv_process_stimers(vcpu);
8920 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8921 kvm_vcpu_update_apicv(vcpu);
8922 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8923 kvm_check_async_pf_completion(vcpu);
8924 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8925 kvm_x86_ops.msr_filter_changed(vcpu);
8926 }
8927
8928 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8929 ++vcpu->stat.req_event;
8930 kvm_apic_accept_events(vcpu);
8931 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8932 r = 1;
8933 goto out;
8934 }
8935
8936 inject_pending_event(vcpu, &req_immediate_exit);
8937 if (req_int_win)
8938 kvm_x86_ops.enable_irq_window(vcpu);
8939
8940 if (kvm_lapic_enabled(vcpu)) {
8941 update_cr8_intercept(vcpu);
8942 kvm_lapic_sync_to_vapic(vcpu);
8943 }
8944 }
8945
8946 r = kvm_mmu_reload(vcpu);
8947 if (unlikely(r)) {
8948 goto cancel_injection;
8949 }
8950
8951 preempt_disable();
8952
8953 kvm_x86_ops.prepare_guest_switch(vcpu);
8954
8955 /*
8956 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8957 * IPI are then delayed after guest entry, which ensures that they
8958 * result in virtual interrupt delivery.
8959 */
8960 local_irq_disable();
8961 vcpu->mode = IN_GUEST_MODE;
8962
8963 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8964
8965 /*
8966 * 1) We should set ->mode before checking ->requests. Please see
8967 * the comment in kvm_vcpu_exiting_guest_mode().
8968 *
8969 * 2) For APICv, we should set ->mode before checking PID.ON. This
8970 * pairs with the memory barrier implicit in pi_test_and_set_on
8971 * (see vmx_deliver_posted_interrupt).
8972 *
8973 * 3) This also orders the write to mode from any reads to the page
8974 * tables done while the VCPU is running. Please see the comment
8975 * in kvm_flush_remote_tlbs.
8976 */
8977 smp_mb__after_srcu_read_unlock();
8978
8979 /*
8980 * This handles the case where a posted interrupt was
8981 * notified with kvm_vcpu_kick.
8982 */
8983 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8984 kvm_x86_ops.sync_pir_to_irr(vcpu);
8985
8986 if (kvm_vcpu_exit_request(vcpu)) {
8987 vcpu->mode = OUTSIDE_GUEST_MODE;
8988 smp_wmb();
8989 local_irq_enable();
8990 preempt_enable();
8991 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8992 r = 1;
8993 goto cancel_injection;
8994 }
8995
8996 if (req_immediate_exit) {
8997 kvm_make_request(KVM_REQ_EVENT, vcpu);
8998 kvm_x86_ops.request_immediate_exit(vcpu);
8999 }
9000
9001 fpregs_assert_state_consistent();
9002 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9003 switch_fpu_return();
9004
9005 if (unlikely(vcpu->arch.switch_db_regs)) {
9006 set_debugreg(0, 7);
9007 set_debugreg(vcpu->arch.eff_db[0], 0);
9008 set_debugreg(vcpu->arch.eff_db[1], 1);
9009 set_debugreg(vcpu->arch.eff_db[2], 2);
9010 set_debugreg(vcpu->arch.eff_db[3], 3);
9011 set_debugreg(vcpu->arch.dr6, 6);
9012 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9013 }
9014
9015 exit_fastpath = kvm_x86_ops.run(vcpu);
9016
9017 /*
9018 * Do this here before restoring debug registers on the host. And
9019 * since we do this before handling the vmexit, a DR access vmexit
9020 * can (a) read the correct value of the debug registers, (b) set
9021 * KVM_DEBUGREG_WONT_EXIT again.
9022 */
9023 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
9024 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
9025 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
9026 kvm_update_dr0123(vcpu);
9027 kvm_update_dr7(vcpu);
9028 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9029 }
9030
9031 /*
9032 * If the guest has used debug registers, at least dr7
9033 * will be disabled while returning to the host.
9034 * If we don't have active breakpoints in the host, we don't
9035 * care about the messed up debug address registers. But if
9036 * we have some of them active, restore the old state.
9037 */
9038 if (hw_breakpoint_active())
9039 hw_breakpoint_restore();
9040
9041 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
9042 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
9043
9044 vcpu->mode = OUTSIDE_GUEST_MODE;
9045 smp_wmb();
9046
9047 kvm_x86_ops.handle_exit_irqoff(vcpu);
9048
9049 /*
9050 * Consume any pending interrupts, including the possible source of
9051 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
9052 * An instruction is required after local_irq_enable() to fully unblock
9053 * interrupts on processors that implement an interrupt shadow, the
9054 * stat.exits increment will do nicely.
9055 */
9056 kvm_before_interrupt(vcpu);
9057 local_irq_enable();
9058 ++vcpu->stat.exits;
9059 local_irq_disable();
9060 kvm_after_interrupt(vcpu);
9061
9062 if (lapic_in_kernel(vcpu)) {
9063 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
9064 if (delta != S64_MIN) {
9065 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
9066 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
9067 }
9068 }
9069
9070 local_irq_enable();
9071 preempt_enable();
9072
9073 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9074
9075 /*
9076 * Profile KVM exit RIPs:
9077 */
9078 if (unlikely(prof_on == KVM_PROFILING)) {
9079 unsigned long rip = kvm_rip_read(vcpu);
9080 profile_hit(KVM_PROFILING, (void *)rip);
9081 }
9082
9083 if (unlikely(vcpu->arch.tsc_always_catchup))
9084 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9085
9086 if (vcpu->arch.apic_attention)
9087 kvm_lapic_sync_from_vapic(vcpu);
9088
9089 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
9090 return r;
9091
9092 cancel_injection:
9093 if (req_immediate_exit)
9094 kvm_make_request(KVM_REQ_EVENT, vcpu);
9095 kvm_x86_ops.cancel_injection(vcpu);
9096 if (unlikely(vcpu->arch.apic_attention))
9097 kvm_lapic_sync_from_vapic(vcpu);
9098 out:
9099 return r;
9100 }
9101
9102 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
9103 {
9104 if (!kvm_arch_vcpu_runnable(vcpu) &&
9105 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
9106 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9107 kvm_vcpu_block(vcpu);
9108 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9109
9110 if (kvm_x86_ops.post_block)
9111 kvm_x86_ops.post_block(vcpu);
9112
9113 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
9114 return 1;
9115 }
9116
9117 kvm_apic_accept_events(vcpu);
9118 switch(vcpu->arch.mp_state) {
9119 case KVM_MP_STATE_HALTED:
9120 case KVM_MP_STATE_AP_RESET_HOLD:
9121 vcpu->arch.pv.pv_unhalted = false;
9122 vcpu->arch.mp_state =
9123 KVM_MP_STATE_RUNNABLE;
9124 fallthrough;
9125 case KVM_MP_STATE_RUNNABLE:
9126 vcpu->arch.apf.halted = false;
9127 break;
9128 case KVM_MP_STATE_INIT_RECEIVED:
9129 break;
9130 default:
9131 return -EINTR;
9132 }
9133 return 1;
9134 }
9135
9136 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
9137 {
9138 if (is_guest_mode(vcpu))
9139 kvm_x86_ops.nested_ops->check_events(vcpu);
9140
9141 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
9142 !vcpu->arch.apf.halted);
9143 }
9144
9145 static int vcpu_run(struct kvm_vcpu *vcpu)
9146 {
9147 int r;
9148 struct kvm *kvm = vcpu->kvm;
9149
9150 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9151 vcpu->arch.l1tf_flush_l1d = true;
9152
9153 for (;;) {
9154 if (kvm_vcpu_running(vcpu)) {
9155 r = vcpu_enter_guest(vcpu);
9156 } else {
9157 r = vcpu_block(kvm, vcpu);
9158 }
9159
9160 if (r <= 0)
9161 break;
9162
9163 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
9164 if (kvm_cpu_has_pending_timer(vcpu))
9165 kvm_inject_pending_timer_irqs(vcpu);
9166
9167 if (dm_request_for_irq_injection(vcpu) &&
9168 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9169 r = 0;
9170 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9171 ++vcpu->stat.request_irq_exits;
9172 break;
9173 }
9174
9175 if (__xfer_to_guest_mode_work_pending()) {
9176 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9177 r = xfer_to_guest_mode_handle_work(vcpu);
9178 if (r)
9179 return r;
9180 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9181 }
9182 }
9183
9184 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9185
9186 return r;
9187 }
9188
9189 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9190 {
9191 int r;
9192
9193 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9194 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9195 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9196 return r;
9197 }
9198
9199 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9200 {
9201 BUG_ON(!vcpu->arch.pio.count);
9202
9203 return complete_emulated_io(vcpu);
9204 }
9205
9206 /*
9207 * Implements the following, as a state machine:
9208 *
9209 * read:
9210 * for each fragment
9211 * for each mmio piece in the fragment
9212 * write gpa, len
9213 * exit
9214 * copy data
9215 * execute insn
9216 *
9217 * write:
9218 * for each fragment
9219 * for each mmio piece in the fragment
9220 * write gpa, len
9221 * copy data
9222 * exit
9223 */
9224 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9225 {
9226 struct kvm_run *run = vcpu->run;
9227 struct kvm_mmio_fragment *frag;
9228 unsigned len;
9229
9230 BUG_ON(!vcpu->mmio_needed);
9231
9232 /* Complete previous fragment */
9233 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9234 len = min(8u, frag->len);
9235 if (!vcpu->mmio_is_write)
9236 memcpy(frag->data, run->mmio.data, len);
9237
9238 if (frag->len <= 8) {
9239 /* Switch to the next fragment. */
9240 frag++;
9241 vcpu->mmio_cur_fragment++;
9242 } else {
9243 /* Go forward to the next mmio piece. */
9244 frag->data += len;
9245 frag->gpa += len;
9246 frag->len -= len;
9247 }
9248
9249 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9250 vcpu->mmio_needed = 0;
9251
9252 /* FIXME: return into emulator if single-stepping. */
9253 if (vcpu->mmio_is_write)
9254 return 1;
9255 vcpu->mmio_read_completed = 1;
9256 return complete_emulated_io(vcpu);
9257 }
9258
9259 run->exit_reason = KVM_EXIT_MMIO;
9260 run->mmio.phys_addr = frag->gpa;
9261 if (vcpu->mmio_is_write)
9262 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9263 run->mmio.len = min(8u, frag->len);
9264 run->mmio.is_write = vcpu->mmio_is_write;
9265 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9266 return 0;
9267 }
9268
9269 static void kvm_save_current_fpu(struct fpu *fpu)
9270 {
9271 /*
9272 * If the target FPU state is not resident in the CPU registers, just
9273 * memcpy() from current, else save CPU state directly to the target.
9274 */
9275 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9276 memcpy(&fpu->state, &current->thread.fpu.state,
9277 fpu_kernel_xstate_size);
9278 else
9279 copy_fpregs_to_fpstate(fpu);
9280 }
9281
9282 /* Swap (qemu) user FPU context for the guest FPU context. */
9283 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9284 {
9285 fpregs_lock();
9286
9287 kvm_save_current_fpu(vcpu->arch.user_fpu);
9288
9289 /*
9290 * Guests with protected state can't have it set by the hypervisor,
9291 * so skip trying to set it.
9292 */
9293 if (vcpu->arch.guest_fpu)
9294 /* PKRU is separately restored in kvm_x86_ops.run. */
9295 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9296 ~XFEATURE_MASK_PKRU);
9297
9298 fpregs_mark_activate();
9299 fpregs_unlock();
9300
9301 trace_kvm_fpu(1);
9302 }
9303
9304 /* When vcpu_run ends, restore user space FPU context. */
9305 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9306 {
9307 fpregs_lock();
9308
9309 /*
9310 * Guests with protected state can't have it read by the hypervisor,
9311 * so skip trying to save it.
9312 */
9313 if (vcpu->arch.guest_fpu)
9314 kvm_save_current_fpu(vcpu->arch.guest_fpu);
9315
9316 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9317
9318 fpregs_mark_activate();
9319 fpregs_unlock();
9320
9321 ++vcpu->stat.fpu_reload;
9322 trace_kvm_fpu(0);
9323 }
9324
9325 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9326 {
9327 struct kvm_run *kvm_run = vcpu->run;
9328 int r;
9329
9330 vcpu_load(vcpu);
9331 kvm_sigset_activate(vcpu);
9332 kvm_load_guest_fpu(vcpu);
9333
9334 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9335 if (kvm_run->immediate_exit) {
9336 r = -EINTR;
9337 goto out;
9338 }
9339 kvm_vcpu_block(vcpu);
9340 kvm_apic_accept_events(vcpu);
9341 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9342 r = -EAGAIN;
9343 if (signal_pending(current)) {
9344 r = -EINTR;
9345 kvm_run->exit_reason = KVM_EXIT_INTR;
9346 ++vcpu->stat.signal_exits;
9347 }
9348 goto out;
9349 }
9350
9351 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9352 r = -EINVAL;
9353 goto out;
9354 }
9355
9356 if (kvm_run->kvm_dirty_regs) {
9357 r = sync_regs(vcpu);
9358 if (r != 0)
9359 goto out;
9360 }
9361
9362 /* re-sync apic's tpr */
9363 if (!lapic_in_kernel(vcpu)) {
9364 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9365 r = -EINVAL;
9366 goto out;
9367 }
9368 }
9369
9370 if (unlikely(vcpu->arch.complete_userspace_io)) {
9371 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9372 vcpu->arch.complete_userspace_io = NULL;
9373 r = cui(vcpu);
9374 if (r <= 0)
9375 goto out;
9376 } else
9377 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9378
9379 if (kvm_run->immediate_exit)
9380 r = -EINTR;
9381 else
9382 r = vcpu_run(vcpu);
9383
9384 out:
9385 kvm_put_guest_fpu(vcpu);
9386 if (kvm_run->kvm_valid_regs)
9387 store_regs(vcpu);
9388 post_kvm_run_save(vcpu);
9389 kvm_sigset_deactivate(vcpu);
9390
9391 vcpu_put(vcpu);
9392 return r;
9393 }
9394
9395 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9396 {
9397 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9398 /*
9399 * We are here if userspace calls get_regs() in the middle of
9400 * instruction emulation. Registers state needs to be copied
9401 * back from emulation context to vcpu. Userspace shouldn't do
9402 * that usually, but some bad designed PV devices (vmware
9403 * backdoor interface) need this to work
9404 */
9405 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9406 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9407 }
9408 regs->rax = kvm_rax_read(vcpu);
9409 regs->rbx = kvm_rbx_read(vcpu);
9410 regs->rcx = kvm_rcx_read(vcpu);
9411 regs->rdx = kvm_rdx_read(vcpu);
9412 regs->rsi = kvm_rsi_read(vcpu);
9413 regs->rdi = kvm_rdi_read(vcpu);
9414 regs->rsp = kvm_rsp_read(vcpu);
9415 regs->rbp = kvm_rbp_read(vcpu);
9416 #ifdef CONFIG_X86_64
9417 regs->r8 = kvm_r8_read(vcpu);
9418 regs->r9 = kvm_r9_read(vcpu);
9419 regs->r10 = kvm_r10_read(vcpu);
9420 regs->r11 = kvm_r11_read(vcpu);
9421 regs->r12 = kvm_r12_read(vcpu);
9422 regs->r13 = kvm_r13_read(vcpu);
9423 regs->r14 = kvm_r14_read(vcpu);
9424 regs->r15 = kvm_r15_read(vcpu);
9425 #endif
9426
9427 regs->rip = kvm_rip_read(vcpu);
9428 regs->rflags = kvm_get_rflags(vcpu);
9429 }
9430
9431 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9432 {
9433 vcpu_load(vcpu);
9434 __get_regs(vcpu, regs);
9435 vcpu_put(vcpu);
9436 return 0;
9437 }
9438
9439 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9440 {
9441 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9442 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9443
9444 kvm_rax_write(vcpu, regs->rax);
9445 kvm_rbx_write(vcpu, regs->rbx);
9446 kvm_rcx_write(vcpu, regs->rcx);
9447 kvm_rdx_write(vcpu, regs->rdx);
9448 kvm_rsi_write(vcpu, regs->rsi);
9449 kvm_rdi_write(vcpu, regs->rdi);
9450 kvm_rsp_write(vcpu, regs->rsp);
9451 kvm_rbp_write(vcpu, regs->rbp);
9452 #ifdef CONFIG_X86_64
9453 kvm_r8_write(vcpu, regs->r8);
9454 kvm_r9_write(vcpu, regs->r9);
9455 kvm_r10_write(vcpu, regs->r10);
9456 kvm_r11_write(vcpu, regs->r11);
9457 kvm_r12_write(vcpu, regs->r12);
9458 kvm_r13_write(vcpu, regs->r13);
9459 kvm_r14_write(vcpu, regs->r14);
9460 kvm_r15_write(vcpu, regs->r15);
9461 #endif
9462
9463 kvm_rip_write(vcpu, regs->rip);
9464 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9465
9466 vcpu->arch.exception.pending = false;
9467
9468 kvm_make_request(KVM_REQ_EVENT, vcpu);
9469 }
9470
9471 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9472 {
9473 vcpu_load(vcpu);
9474 __set_regs(vcpu, regs);
9475 vcpu_put(vcpu);
9476 return 0;
9477 }
9478
9479 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9480 {
9481 struct kvm_segment cs;
9482
9483 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9484 *db = cs.db;
9485 *l = cs.l;
9486 }
9487 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9488
9489 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9490 {
9491 struct desc_ptr dt;
9492
9493 if (vcpu->arch.guest_state_protected)
9494 goto skip_protected_regs;
9495
9496 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9497 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9498 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9499 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9500 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9501 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9502
9503 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9504 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9505
9506 kvm_x86_ops.get_idt(vcpu, &dt);
9507 sregs->idt.limit = dt.size;
9508 sregs->idt.base = dt.address;
9509 kvm_x86_ops.get_gdt(vcpu, &dt);
9510 sregs->gdt.limit = dt.size;
9511 sregs->gdt.base = dt.address;
9512
9513 sregs->cr2 = vcpu->arch.cr2;
9514 sregs->cr3 = kvm_read_cr3(vcpu);
9515
9516 skip_protected_regs:
9517 sregs->cr0 = kvm_read_cr0(vcpu);
9518 sregs->cr4 = kvm_read_cr4(vcpu);
9519 sregs->cr8 = kvm_get_cr8(vcpu);
9520 sregs->efer = vcpu->arch.efer;
9521 sregs->apic_base = kvm_get_apic_base(vcpu);
9522
9523 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9524
9525 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9526 set_bit(vcpu->arch.interrupt.nr,
9527 (unsigned long *)sregs->interrupt_bitmap);
9528 }
9529
9530 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9531 struct kvm_sregs *sregs)
9532 {
9533 vcpu_load(vcpu);
9534 __get_sregs(vcpu, sregs);
9535 vcpu_put(vcpu);
9536 return 0;
9537 }
9538
9539 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9540 struct kvm_mp_state *mp_state)
9541 {
9542 vcpu_load(vcpu);
9543 if (kvm_mpx_supported())
9544 kvm_load_guest_fpu(vcpu);
9545
9546 kvm_apic_accept_events(vcpu);
9547 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
9548 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
9549 vcpu->arch.pv.pv_unhalted)
9550 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9551 else
9552 mp_state->mp_state = vcpu->arch.mp_state;
9553
9554 if (kvm_mpx_supported())
9555 kvm_put_guest_fpu(vcpu);
9556 vcpu_put(vcpu);
9557 return 0;
9558 }
9559
9560 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9561 struct kvm_mp_state *mp_state)
9562 {
9563 int ret = -EINVAL;
9564
9565 vcpu_load(vcpu);
9566
9567 if (!lapic_in_kernel(vcpu) &&
9568 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9569 goto out;
9570
9571 /*
9572 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9573 * INIT state; latched init should be reported using
9574 * KVM_SET_VCPU_EVENTS, so reject it here.
9575 */
9576 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9577 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9578 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9579 goto out;
9580
9581 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9582 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9583 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9584 } else
9585 vcpu->arch.mp_state = mp_state->mp_state;
9586 kvm_make_request(KVM_REQ_EVENT, vcpu);
9587
9588 ret = 0;
9589 out:
9590 vcpu_put(vcpu);
9591 return ret;
9592 }
9593
9594 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9595 int reason, bool has_error_code, u32 error_code)
9596 {
9597 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9598 int ret;
9599
9600 init_emulate_ctxt(vcpu);
9601
9602 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9603 has_error_code, error_code);
9604 if (ret) {
9605 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9606 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9607 vcpu->run->internal.ndata = 0;
9608 return 0;
9609 }
9610
9611 kvm_rip_write(vcpu, ctxt->eip);
9612 kvm_set_rflags(vcpu, ctxt->eflags);
9613 return 1;
9614 }
9615 EXPORT_SYMBOL_GPL(kvm_task_switch);
9616
9617 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9618 {
9619 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9620 /*
9621 * When EFER.LME and CR0.PG are set, the processor is in
9622 * 64-bit mode (though maybe in a 32-bit code segment).
9623 * CR4.PAE and EFER.LMA must be set.
9624 */
9625 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
9626 return false;
9627 if (sregs->cr3 & vcpu->arch.cr3_lm_rsvd_bits)
9628 return false;
9629 } else {
9630 /*
9631 * Not in 64-bit mode: EFER.LMA is clear and the code
9632 * segment cannot be 64-bit.
9633 */
9634 if (sregs->efer & EFER_LMA || sregs->cs.l)
9635 return false;
9636 }
9637
9638 return kvm_is_valid_cr4(vcpu, sregs->cr4);
9639 }
9640
9641 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9642 {
9643 struct msr_data apic_base_msr;
9644 int mmu_reset_needed = 0;
9645 int pending_vec, max_bits, idx;
9646 struct desc_ptr dt;
9647 int ret = -EINVAL;
9648
9649 if (!kvm_is_valid_sregs(vcpu, sregs))
9650 goto out;
9651
9652 apic_base_msr.data = sregs->apic_base;
9653 apic_base_msr.host_initiated = true;
9654 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9655 goto out;
9656
9657 if (vcpu->arch.guest_state_protected)
9658 goto skip_protected_regs;
9659
9660 dt.size = sregs->idt.limit;
9661 dt.address = sregs->idt.base;
9662 kvm_x86_ops.set_idt(vcpu, &dt);
9663 dt.size = sregs->gdt.limit;
9664 dt.address = sregs->gdt.base;
9665 kvm_x86_ops.set_gdt(vcpu, &dt);
9666
9667 vcpu->arch.cr2 = sregs->cr2;
9668 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9669 vcpu->arch.cr3 = sregs->cr3;
9670 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9671
9672 kvm_set_cr8(vcpu, sregs->cr8);
9673
9674 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9675 kvm_x86_ops.set_efer(vcpu, sregs->efer);
9676
9677 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9678 kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9679 vcpu->arch.cr0 = sregs->cr0;
9680
9681 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9682 kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9683
9684 idx = srcu_read_lock(&vcpu->kvm->srcu);
9685 if (is_pae_paging(vcpu)) {
9686 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9687 mmu_reset_needed = 1;
9688 }
9689 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9690
9691 if (mmu_reset_needed)
9692 kvm_mmu_reset_context(vcpu);
9693
9694 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9695 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9696 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9697 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9698 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9699 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9700
9701 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9702 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9703
9704 update_cr8_intercept(vcpu);
9705
9706 /* Older userspace won't unhalt the vcpu on reset. */
9707 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9708 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9709 !is_protmode(vcpu))
9710 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9711
9712 skip_protected_regs:
9713 max_bits = KVM_NR_INTERRUPTS;
9714 pending_vec = find_first_bit(
9715 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9716 if (pending_vec < max_bits) {
9717 kvm_queue_interrupt(vcpu, pending_vec, false);
9718 pr_debug("Set back pending irq %d\n", pending_vec);
9719 }
9720
9721 kvm_make_request(KVM_REQ_EVENT, vcpu);
9722
9723 ret = 0;
9724 out:
9725 return ret;
9726 }
9727
9728 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9729 struct kvm_sregs *sregs)
9730 {
9731 int ret;
9732
9733 vcpu_load(vcpu);
9734 ret = __set_sregs(vcpu, sregs);
9735 vcpu_put(vcpu);
9736 return ret;
9737 }
9738
9739 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9740 struct kvm_guest_debug *dbg)
9741 {
9742 unsigned long rflags;
9743 int i, r;
9744
9745 if (vcpu->arch.guest_state_protected)
9746 return -EINVAL;
9747
9748 vcpu_load(vcpu);
9749
9750 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9751 r = -EBUSY;
9752 if (vcpu->arch.exception.pending)
9753 goto out;
9754 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9755 kvm_queue_exception(vcpu, DB_VECTOR);
9756 else
9757 kvm_queue_exception(vcpu, BP_VECTOR);
9758 }
9759
9760 /*
9761 * Read rflags as long as potentially injected trace flags are still
9762 * filtered out.
9763 */
9764 rflags = kvm_get_rflags(vcpu);
9765
9766 vcpu->guest_debug = dbg->control;
9767 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9768 vcpu->guest_debug = 0;
9769
9770 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9771 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9772 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9773 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9774 } else {
9775 for (i = 0; i < KVM_NR_DB_REGS; i++)
9776 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9777 }
9778 kvm_update_dr7(vcpu);
9779
9780 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9781 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9782 get_segment_base(vcpu, VCPU_SREG_CS);
9783
9784 /*
9785 * Trigger an rflags update that will inject or remove the trace
9786 * flags.
9787 */
9788 kvm_set_rflags(vcpu, rflags);
9789
9790 kvm_x86_ops.update_exception_bitmap(vcpu);
9791
9792 r = 0;
9793
9794 out:
9795 vcpu_put(vcpu);
9796 return r;
9797 }
9798
9799 /*
9800 * Translate a guest virtual address to a guest physical address.
9801 */
9802 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9803 struct kvm_translation *tr)
9804 {
9805 unsigned long vaddr = tr->linear_address;
9806 gpa_t gpa;
9807 int idx;
9808
9809 vcpu_load(vcpu);
9810
9811 idx = srcu_read_lock(&vcpu->kvm->srcu);
9812 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9813 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9814 tr->physical_address = gpa;
9815 tr->valid = gpa != UNMAPPED_GVA;
9816 tr->writeable = 1;
9817 tr->usermode = 0;
9818
9819 vcpu_put(vcpu);
9820 return 0;
9821 }
9822
9823 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9824 {
9825 struct fxregs_state *fxsave;
9826
9827 if (!vcpu->arch.guest_fpu)
9828 return 0;
9829
9830 vcpu_load(vcpu);
9831
9832 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9833 memcpy(fpu->fpr, fxsave->st_space, 128);
9834 fpu->fcw = fxsave->cwd;
9835 fpu->fsw = fxsave->swd;
9836 fpu->ftwx = fxsave->twd;
9837 fpu->last_opcode = fxsave->fop;
9838 fpu->last_ip = fxsave->rip;
9839 fpu->last_dp = fxsave->rdp;
9840 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9841
9842 vcpu_put(vcpu);
9843 return 0;
9844 }
9845
9846 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9847 {
9848 struct fxregs_state *fxsave;
9849
9850 if (!vcpu->arch.guest_fpu)
9851 return 0;
9852
9853 vcpu_load(vcpu);
9854
9855 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9856
9857 memcpy(fxsave->st_space, fpu->fpr, 128);
9858 fxsave->cwd = fpu->fcw;
9859 fxsave->swd = fpu->fsw;
9860 fxsave->twd = fpu->ftwx;
9861 fxsave->fop = fpu->last_opcode;
9862 fxsave->rip = fpu->last_ip;
9863 fxsave->rdp = fpu->last_dp;
9864 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9865
9866 vcpu_put(vcpu);
9867 return 0;
9868 }
9869
9870 static void store_regs(struct kvm_vcpu *vcpu)
9871 {
9872 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9873
9874 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9875 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9876
9877 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9878 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9879
9880 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9881 kvm_vcpu_ioctl_x86_get_vcpu_events(
9882 vcpu, &vcpu->run->s.regs.events);
9883 }
9884
9885 static int sync_regs(struct kvm_vcpu *vcpu)
9886 {
9887 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9888 return -EINVAL;
9889
9890 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9891 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9892 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9893 }
9894 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9895 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9896 return -EINVAL;
9897 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9898 }
9899 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9900 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9901 vcpu, &vcpu->run->s.regs.events))
9902 return -EINVAL;
9903 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9904 }
9905
9906 return 0;
9907 }
9908
9909 static void fx_init(struct kvm_vcpu *vcpu)
9910 {
9911 if (!vcpu->arch.guest_fpu)
9912 return;
9913
9914 fpstate_init(&vcpu->arch.guest_fpu->state);
9915 if (boot_cpu_has(X86_FEATURE_XSAVES))
9916 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9917 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9918
9919 /*
9920 * Ensure guest xcr0 is valid for loading
9921 */
9922 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9923
9924 vcpu->arch.cr0 |= X86_CR0_ET;
9925 }
9926
9927 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu)
9928 {
9929 if (vcpu->arch.guest_fpu) {
9930 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9931 vcpu->arch.guest_fpu = NULL;
9932 }
9933 }
9934 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu);
9935
9936 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9937 {
9938 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9939 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9940 "guest TSC will not be reliable\n");
9941
9942 return 0;
9943 }
9944
9945 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9946 {
9947 struct page *page;
9948 int r;
9949
9950 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9951 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9952 else
9953 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9954
9955 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9956
9957 r = kvm_mmu_create(vcpu);
9958 if (r < 0)
9959 return r;
9960
9961 if (irqchip_in_kernel(vcpu->kvm)) {
9962 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9963 if (r < 0)
9964 goto fail_mmu_destroy;
9965 if (kvm_apicv_activated(vcpu->kvm))
9966 vcpu->arch.apicv_active = true;
9967 } else
9968 static_key_slow_inc(&kvm_no_apic_vcpu);
9969
9970 r = -ENOMEM;
9971
9972 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
9973 if (!page)
9974 goto fail_free_lapic;
9975 vcpu->arch.pio_data = page_address(page);
9976
9977 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9978 GFP_KERNEL_ACCOUNT);
9979 if (!vcpu->arch.mce_banks)
9980 goto fail_free_pio_data;
9981 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9982
9983 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9984 GFP_KERNEL_ACCOUNT))
9985 goto fail_free_mce_banks;
9986
9987 if (!alloc_emulate_ctxt(vcpu))
9988 goto free_wbinvd_dirty_mask;
9989
9990 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9991 GFP_KERNEL_ACCOUNT);
9992 if (!vcpu->arch.user_fpu) {
9993 pr_err("kvm: failed to allocate userspace's fpu\n");
9994 goto free_emulate_ctxt;
9995 }
9996
9997 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9998 GFP_KERNEL_ACCOUNT);
9999 if (!vcpu->arch.guest_fpu) {
10000 pr_err("kvm: failed to allocate vcpu's fpu\n");
10001 goto free_user_fpu;
10002 }
10003 fx_init(vcpu);
10004
10005 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
10006 vcpu->arch.cr3_lm_rsvd_bits = rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
10007
10008 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
10009
10010 kvm_async_pf_hash_reset(vcpu);
10011 kvm_pmu_init(vcpu);
10012
10013 vcpu->arch.pending_external_vector = -1;
10014 vcpu->arch.preempted_in_kernel = false;
10015
10016 kvm_hv_vcpu_init(vcpu);
10017
10018 r = kvm_x86_ops.vcpu_create(vcpu);
10019 if (r)
10020 goto free_guest_fpu;
10021
10022 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
10023 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
10024 kvm_vcpu_mtrr_init(vcpu);
10025 vcpu_load(vcpu);
10026 kvm_vcpu_reset(vcpu, false);
10027 kvm_init_mmu(vcpu, false);
10028 vcpu_put(vcpu);
10029 return 0;
10030
10031 free_guest_fpu:
10032 kvm_free_guest_fpu(vcpu);
10033 free_user_fpu:
10034 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10035 free_emulate_ctxt:
10036 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10037 free_wbinvd_dirty_mask:
10038 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10039 fail_free_mce_banks:
10040 kfree(vcpu->arch.mce_banks);
10041 fail_free_pio_data:
10042 free_page((unsigned long)vcpu->arch.pio_data);
10043 fail_free_lapic:
10044 kvm_free_lapic(vcpu);
10045 fail_mmu_destroy:
10046 kvm_mmu_destroy(vcpu);
10047 return r;
10048 }
10049
10050 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
10051 {
10052 struct kvm *kvm = vcpu->kvm;
10053
10054 kvm_hv_vcpu_postcreate(vcpu);
10055
10056 if (mutex_lock_killable(&vcpu->mutex))
10057 return;
10058 vcpu_load(vcpu);
10059 kvm_synchronize_tsc(vcpu, 0);
10060 vcpu_put(vcpu);
10061
10062 /* poll control enabled by default */
10063 vcpu->arch.msr_kvm_poll_control = 1;
10064
10065 mutex_unlock(&vcpu->mutex);
10066
10067 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
10068 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
10069 KVMCLOCK_SYNC_PERIOD);
10070 }
10071
10072 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
10073 {
10074 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
10075 int idx;
10076
10077 kvm_release_pfn(cache->pfn, cache->dirty, cache);
10078
10079 kvmclock_reset(vcpu);
10080
10081 kvm_x86_ops.vcpu_free(vcpu);
10082
10083 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10084 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10085 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10086 kvm_free_guest_fpu(vcpu);
10087
10088 kvm_hv_vcpu_uninit(vcpu);
10089 kvm_pmu_destroy(vcpu);
10090 kfree(vcpu->arch.mce_banks);
10091 kvm_free_lapic(vcpu);
10092 idx = srcu_read_lock(&vcpu->kvm->srcu);
10093 kvm_mmu_destroy(vcpu);
10094 srcu_read_unlock(&vcpu->kvm->srcu, idx);
10095 free_page((unsigned long)vcpu->arch.pio_data);
10096 kvfree(vcpu->arch.cpuid_entries);
10097 if (!lapic_in_kernel(vcpu))
10098 static_key_slow_dec(&kvm_no_apic_vcpu);
10099 }
10100
10101 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
10102 {
10103 kvm_lapic_reset(vcpu, init_event);
10104
10105 vcpu->arch.hflags = 0;
10106
10107 vcpu->arch.smi_pending = 0;
10108 vcpu->arch.smi_count = 0;
10109 atomic_set(&vcpu->arch.nmi_queued, 0);
10110 vcpu->arch.nmi_pending = 0;
10111 vcpu->arch.nmi_injected = false;
10112 kvm_clear_interrupt_queue(vcpu);
10113 kvm_clear_exception_queue(vcpu);
10114
10115 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
10116 kvm_update_dr0123(vcpu);
10117 vcpu->arch.dr6 = DR6_INIT;
10118 vcpu->arch.dr7 = DR7_FIXED_1;
10119 kvm_update_dr7(vcpu);
10120
10121 vcpu->arch.cr2 = 0;
10122
10123 kvm_make_request(KVM_REQ_EVENT, vcpu);
10124 vcpu->arch.apf.msr_en_val = 0;
10125 vcpu->arch.apf.msr_int_val = 0;
10126 vcpu->arch.st.msr_val = 0;
10127
10128 kvmclock_reset(vcpu);
10129
10130 kvm_clear_async_pf_completion_queue(vcpu);
10131 kvm_async_pf_hash_reset(vcpu);
10132 vcpu->arch.apf.halted = false;
10133
10134 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) {
10135 void *mpx_state_buffer;
10136
10137 /*
10138 * To avoid have the INIT path from kvm_apic_has_events() that be
10139 * called with loaded FPU and does not let userspace fix the state.
10140 */
10141 if (init_event)
10142 kvm_put_guest_fpu(vcpu);
10143 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10144 XFEATURE_BNDREGS);
10145 if (mpx_state_buffer)
10146 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
10147 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10148 XFEATURE_BNDCSR);
10149 if (mpx_state_buffer)
10150 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
10151 if (init_event)
10152 kvm_load_guest_fpu(vcpu);
10153 }
10154
10155 if (!init_event) {
10156 kvm_pmu_reset(vcpu);
10157 vcpu->arch.smbase = 0x30000;
10158
10159 vcpu->arch.msr_misc_features_enables = 0;
10160
10161 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
10162 }
10163
10164 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
10165 vcpu->arch.regs_avail = ~0;
10166 vcpu->arch.regs_dirty = ~0;
10167
10168 vcpu->arch.ia32_xss = 0;
10169
10170 kvm_x86_ops.vcpu_reset(vcpu, init_event);
10171 }
10172
10173 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
10174 {
10175 struct kvm_segment cs;
10176
10177 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
10178 cs.selector = vector << 8;
10179 cs.base = vector << 12;
10180 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10181 kvm_rip_write(vcpu, 0);
10182 }
10183 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
10184
10185 int kvm_arch_hardware_enable(void)
10186 {
10187 struct kvm *kvm;
10188 struct kvm_vcpu *vcpu;
10189 int i;
10190 int ret;
10191 u64 local_tsc;
10192 u64 max_tsc = 0;
10193 bool stable, backwards_tsc = false;
10194
10195 kvm_user_return_msr_cpu_online();
10196 ret = kvm_x86_ops.hardware_enable();
10197 if (ret != 0)
10198 return ret;
10199
10200 local_tsc = rdtsc();
10201 stable = !kvm_check_tsc_unstable();
10202 list_for_each_entry(kvm, &vm_list, vm_list) {
10203 kvm_for_each_vcpu(i, vcpu, kvm) {
10204 if (!stable && vcpu->cpu == smp_processor_id())
10205 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10206 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10207 backwards_tsc = true;
10208 if (vcpu->arch.last_host_tsc > max_tsc)
10209 max_tsc = vcpu->arch.last_host_tsc;
10210 }
10211 }
10212 }
10213
10214 /*
10215 * Sometimes, even reliable TSCs go backwards. This happens on
10216 * platforms that reset TSC during suspend or hibernate actions, but
10217 * maintain synchronization. We must compensate. Fortunately, we can
10218 * detect that condition here, which happens early in CPU bringup,
10219 * before any KVM threads can be running. Unfortunately, we can't
10220 * bring the TSCs fully up to date with real time, as we aren't yet far
10221 * enough into CPU bringup that we know how much real time has actually
10222 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10223 * variables that haven't been updated yet.
10224 *
10225 * So we simply find the maximum observed TSC above, then record the
10226 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
10227 * the adjustment will be applied. Note that we accumulate
10228 * adjustments, in case multiple suspend cycles happen before some VCPU
10229 * gets a chance to run again. In the event that no KVM threads get a
10230 * chance to run, we will miss the entire elapsed period, as we'll have
10231 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10232 * loose cycle time. This isn't too big a deal, since the loss will be
10233 * uniform across all VCPUs (not to mention the scenario is extremely
10234 * unlikely). It is possible that a second hibernate recovery happens
10235 * much faster than a first, causing the observed TSC here to be
10236 * smaller; this would require additional padding adjustment, which is
10237 * why we set last_host_tsc to the local tsc observed here.
10238 *
10239 * N.B. - this code below runs only on platforms with reliable TSC,
10240 * as that is the only way backwards_tsc is set above. Also note
10241 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10242 * have the same delta_cyc adjustment applied if backwards_tsc
10243 * is detected. Note further, this adjustment is only done once,
10244 * as we reset last_host_tsc on all VCPUs to stop this from being
10245 * called multiple times (one for each physical CPU bringup).
10246 *
10247 * Platforms with unreliable TSCs don't have to deal with this, they
10248 * will be compensated by the logic in vcpu_load, which sets the TSC to
10249 * catchup mode. This will catchup all VCPUs to real time, but cannot
10250 * guarantee that they stay in perfect synchronization.
10251 */
10252 if (backwards_tsc) {
10253 u64 delta_cyc = max_tsc - local_tsc;
10254 list_for_each_entry(kvm, &vm_list, vm_list) {
10255 kvm->arch.backwards_tsc_observed = true;
10256 kvm_for_each_vcpu(i, vcpu, kvm) {
10257 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10258 vcpu->arch.last_host_tsc = local_tsc;
10259 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10260 }
10261
10262 /*
10263 * We have to disable TSC offset matching.. if you were
10264 * booting a VM while issuing an S4 host suspend....
10265 * you may have some problem. Solving this issue is
10266 * left as an exercise to the reader.
10267 */
10268 kvm->arch.last_tsc_nsec = 0;
10269 kvm->arch.last_tsc_write = 0;
10270 }
10271
10272 }
10273 return 0;
10274 }
10275
10276 void kvm_arch_hardware_disable(void)
10277 {
10278 kvm_x86_ops.hardware_disable();
10279 drop_user_return_notifiers();
10280 }
10281
10282 int kvm_arch_hardware_setup(void *opaque)
10283 {
10284 struct kvm_x86_init_ops *ops = opaque;
10285 int r;
10286
10287 rdmsrl_safe(MSR_EFER, &host_efer);
10288
10289 if (boot_cpu_has(X86_FEATURE_XSAVES))
10290 rdmsrl(MSR_IA32_XSS, host_xss);
10291
10292 r = ops->hardware_setup();
10293 if (r != 0)
10294 return r;
10295
10296 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10297
10298 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10299 supported_xss = 0;
10300
10301 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10302 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10303 #undef __kvm_cpu_cap_has
10304
10305 if (kvm_has_tsc_control) {
10306 /*
10307 * Make sure the user can only configure tsc_khz values that
10308 * fit into a signed integer.
10309 * A min value is not calculated because it will always
10310 * be 1 on all machines.
10311 */
10312 u64 max = min(0x7fffffffULL,
10313 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10314 kvm_max_guest_tsc_khz = max;
10315
10316 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10317 }
10318
10319 kvm_init_msr_list();
10320 return 0;
10321 }
10322
10323 void kvm_arch_hardware_unsetup(void)
10324 {
10325 kvm_x86_ops.hardware_unsetup();
10326 }
10327
10328 int kvm_arch_check_processor_compat(void *opaque)
10329 {
10330 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10331 struct kvm_x86_init_ops *ops = opaque;
10332
10333 WARN_ON(!irqs_disabled());
10334
10335 if (__cr4_reserved_bits(cpu_has, c) !=
10336 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10337 return -EIO;
10338
10339 return ops->check_processor_compatibility();
10340 }
10341
10342 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10343 {
10344 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10345 }
10346 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10347
10348 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10349 {
10350 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10351 }
10352
10353 struct static_key kvm_no_apic_vcpu __read_mostly;
10354 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
10355
10356 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10357 {
10358 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10359
10360 vcpu->arch.l1tf_flush_l1d = true;
10361 if (pmu->version && unlikely(pmu->event_count)) {
10362 pmu->need_cleanup = true;
10363 kvm_make_request(KVM_REQ_PMU, vcpu);
10364 }
10365 kvm_x86_ops.sched_in(vcpu, cpu);
10366 }
10367
10368 void kvm_arch_free_vm(struct kvm *kvm)
10369 {
10370 kfree(kvm->arch.hyperv.hv_pa_pg);
10371 vfree(kvm);
10372 }
10373
10374
10375 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10376 {
10377 if (type)
10378 return -EINVAL;
10379
10380 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10381 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10382 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10383 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10384 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10385 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10386
10387 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10388 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10389 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10390 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10391 &kvm->arch.irq_sources_bitmap);
10392
10393 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10394 mutex_init(&kvm->arch.apic_map_lock);
10395 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10396
10397 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10398 pvclock_update_vm_gtod_copy(kvm);
10399
10400 kvm->arch.guest_can_read_msr_platform_info = true;
10401
10402 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10403 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10404
10405 kvm_hv_init_vm(kvm);
10406 kvm_page_track_init(kvm);
10407 kvm_mmu_init_vm(kvm);
10408
10409 return kvm_x86_ops.vm_init(kvm);
10410 }
10411
10412 int kvm_arch_post_init_vm(struct kvm *kvm)
10413 {
10414 return kvm_mmu_post_init_vm(kvm);
10415 }
10416
10417 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10418 {
10419 vcpu_load(vcpu);
10420 kvm_mmu_unload(vcpu);
10421 vcpu_put(vcpu);
10422 }
10423
10424 static void kvm_free_vcpus(struct kvm *kvm)
10425 {
10426 unsigned int i;
10427 struct kvm_vcpu *vcpu;
10428
10429 /*
10430 * Unpin any mmu pages first.
10431 */
10432 kvm_for_each_vcpu(i, vcpu, kvm) {
10433 kvm_clear_async_pf_completion_queue(vcpu);
10434 kvm_unload_vcpu_mmu(vcpu);
10435 }
10436 kvm_for_each_vcpu(i, vcpu, kvm)
10437 kvm_vcpu_destroy(vcpu);
10438
10439 mutex_lock(&kvm->lock);
10440 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10441 kvm->vcpus[i] = NULL;
10442
10443 atomic_set(&kvm->online_vcpus, 0);
10444 mutex_unlock(&kvm->lock);
10445 }
10446
10447 void kvm_arch_sync_events(struct kvm *kvm)
10448 {
10449 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10450 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10451 kvm_free_pit(kvm);
10452 }
10453
10454 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
10455
10456 /**
10457 * __x86_set_memory_region: Setup KVM internal memory slot
10458 *
10459 * @kvm: the kvm pointer to the VM.
10460 * @id: the slot ID to setup.
10461 * @gpa: the GPA to install the slot (unused when @size == 0).
10462 * @size: the size of the slot. Set to zero to uninstall a slot.
10463 *
10464 * This function helps to setup a KVM internal memory slot. Specify
10465 * @size > 0 to install a new slot, while @size == 0 to uninstall a
10466 * slot. The return code can be one of the following:
10467 *
10468 * HVA: on success (uninstall will return a bogus HVA)
10469 * -errno: on error
10470 *
10471 * The caller should always use IS_ERR() to check the return value
10472 * before use. Note, the KVM internal memory slots are guaranteed to
10473 * remain valid and unchanged until the VM is destroyed, i.e., the
10474 * GPA->HVA translation will not change. However, the HVA is a user
10475 * address, i.e. its accessibility is not guaranteed, and must be
10476 * accessed via __copy_{to,from}_user().
10477 */
10478 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
10479 u32 size)
10480 {
10481 int i, r;
10482 unsigned long hva, old_npages;
10483 struct kvm_memslots *slots = kvm_memslots(kvm);
10484 struct kvm_memory_slot *slot;
10485
10486 /* Called with kvm->slots_lock held. */
10487 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10488 return ERR_PTR_USR(-EINVAL);
10489
10490 slot = id_to_memslot(slots, id);
10491 if (size) {
10492 if (slot && slot->npages)
10493 return ERR_PTR_USR(-EEXIST);
10494
10495 /*
10496 * MAP_SHARED to prevent internal slot pages from being moved
10497 * by fork()/COW.
10498 */
10499 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10500 MAP_SHARED | MAP_ANONYMOUS, 0);
10501 if (IS_ERR((void *)hva))
10502 return (void __user *)hva;
10503 } else {
10504 if (!slot || !slot->npages)
10505 return 0;
10506
10507 old_npages = slot->npages;
10508 hva = slot->userspace_addr;
10509 }
10510
10511 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10512 struct kvm_userspace_memory_region m;
10513
10514 m.slot = id | (i << 16);
10515 m.flags = 0;
10516 m.guest_phys_addr = gpa;
10517 m.userspace_addr = hva;
10518 m.memory_size = size;
10519 r = __kvm_set_memory_region(kvm, &m);
10520 if (r < 0)
10521 return ERR_PTR_USR(r);
10522 }
10523
10524 if (!size)
10525 vm_munmap(hva, old_npages * PAGE_SIZE);
10526
10527 return (void __user *)hva;
10528 }
10529 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10530
10531 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10532 {
10533 kvm_mmu_pre_destroy_vm(kvm);
10534 }
10535
10536 void kvm_arch_destroy_vm(struct kvm *kvm)
10537 {
10538 u32 i;
10539
10540 if (current->mm == kvm->mm) {
10541 /*
10542 * Free memory regions allocated on behalf of userspace,
10543 * unless the the memory map has changed due to process exit
10544 * or fd copying.
10545 */
10546 mutex_lock(&kvm->slots_lock);
10547 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10548 0, 0);
10549 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10550 0, 0);
10551 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10552 mutex_unlock(&kvm->slots_lock);
10553 }
10554 if (kvm_x86_ops.vm_destroy)
10555 kvm_x86_ops.vm_destroy(kvm);
10556 for (i = 0; i < kvm->arch.msr_filter.count; i++)
10557 kfree(kvm->arch.msr_filter.ranges[i].bitmap);
10558 kvm_pic_destroy(kvm);
10559 kvm_ioapic_destroy(kvm);
10560 kvm_free_vcpus(kvm);
10561 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10562 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10563 kvm_mmu_uninit_vm(kvm);
10564 kvm_page_track_cleanup(kvm);
10565 kvm_hv_destroy_vm(kvm);
10566 }
10567
10568 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10569 {
10570 int i;
10571
10572 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10573 kvfree(slot->arch.rmap[i]);
10574 slot->arch.rmap[i] = NULL;
10575
10576 if (i == 0)
10577 continue;
10578
10579 kvfree(slot->arch.lpage_info[i - 1]);
10580 slot->arch.lpage_info[i - 1] = NULL;
10581 }
10582
10583 kvm_page_track_free_memslot(slot);
10584 }
10585
10586 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10587 unsigned long npages)
10588 {
10589 int i;
10590
10591 /*
10592 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10593 * old arrays will be freed by __kvm_set_memory_region() if installing
10594 * the new memslot is successful.
10595 */
10596 memset(&slot->arch, 0, sizeof(slot->arch));
10597
10598 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10599 struct kvm_lpage_info *linfo;
10600 unsigned long ugfn;
10601 int lpages;
10602 int level = i + 1;
10603
10604 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10605 slot->base_gfn, level) + 1;
10606
10607 slot->arch.rmap[i] =
10608 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10609 GFP_KERNEL_ACCOUNT);
10610 if (!slot->arch.rmap[i])
10611 goto out_free;
10612 if (i == 0)
10613 continue;
10614
10615 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10616 if (!linfo)
10617 goto out_free;
10618
10619 slot->arch.lpage_info[i - 1] = linfo;
10620
10621 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10622 linfo[0].disallow_lpage = 1;
10623 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10624 linfo[lpages - 1].disallow_lpage = 1;
10625 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10626 /*
10627 * If the gfn and userspace address are not aligned wrt each
10628 * other, disable large page support for this slot.
10629 */
10630 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10631 unsigned long j;
10632
10633 for (j = 0; j < lpages; ++j)
10634 linfo[j].disallow_lpage = 1;
10635 }
10636 }
10637
10638 if (kvm_page_track_create_memslot(slot, npages))
10639 goto out_free;
10640
10641 return 0;
10642
10643 out_free:
10644 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10645 kvfree(slot->arch.rmap[i]);
10646 slot->arch.rmap[i] = NULL;
10647 if (i == 0)
10648 continue;
10649
10650 kvfree(slot->arch.lpage_info[i - 1]);
10651 slot->arch.lpage_info[i - 1] = NULL;
10652 }
10653 return -ENOMEM;
10654 }
10655
10656 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10657 {
10658 struct kvm_vcpu *vcpu;
10659 int i;
10660
10661 /*
10662 * memslots->generation has been incremented.
10663 * mmio generation may have reached its maximum value.
10664 */
10665 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10666
10667 /* Force re-initialization of steal_time cache */
10668 kvm_for_each_vcpu(i, vcpu, kvm)
10669 kvm_vcpu_kick(vcpu);
10670 }
10671
10672 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10673 struct kvm_memory_slot *memslot,
10674 const struct kvm_userspace_memory_region *mem,
10675 enum kvm_mr_change change)
10676 {
10677 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10678 return kvm_alloc_memslot_metadata(memslot,
10679 mem->memory_size >> PAGE_SHIFT);
10680 return 0;
10681 }
10682
10683 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10684 struct kvm_memory_slot *old,
10685 struct kvm_memory_slot *new,
10686 enum kvm_mr_change change)
10687 {
10688 /*
10689 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10690 * See comments below.
10691 */
10692 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10693 return;
10694
10695 /*
10696 * Dirty logging tracks sptes in 4k granularity, meaning that large
10697 * sptes have to be split. If live migration is successful, the guest
10698 * in the source machine will be destroyed and large sptes will be
10699 * created in the destination. However, if the guest continues to run
10700 * in the source machine (for example if live migration fails), small
10701 * sptes will remain around and cause bad performance.
10702 *
10703 * Scan sptes if dirty logging has been stopped, dropping those
10704 * which can be collapsed into a single large-page spte. Later
10705 * page faults will create the large-page sptes.
10706 *
10707 * There is no need to do this in any of the following cases:
10708 * CREATE: No dirty mappings will already exist.
10709 * MOVE/DELETE: The old mappings will already have been cleaned up by
10710 * kvm_arch_flush_shadow_memslot()
10711 */
10712 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10713 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10714 kvm_mmu_zap_collapsible_sptes(kvm, new);
10715
10716 /*
10717 * Enable or disable dirty logging for the slot.
10718 *
10719 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10720 * slot have been zapped so no dirty logging updates are needed for
10721 * the old slot.
10722 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10723 * any mappings that might be created in it will consume the
10724 * properties of the new slot and do not need to be updated here.
10725 *
10726 * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10727 * called to enable/disable dirty logging.
10728 *
10729 * When disabling dirty logging with PML enabled, the D-bit is set
10730 * for sptes in the slot in order to prevent unnecessary GPA
10731 * logging in the PML buffer (and potential PML buffer full VMEXIT).
10732 * This guarantees leaving PML enabled for the guest's lifetime
10733 * won't have any additional overhead from PML when the guest is
10734 * running with dirty logging disabled.
10735 *
10736 * When enabling dirty logging, large sptes are write-protected
10737 * so they can be split on first write. New large sptes cannot
10738 * be created for this slot until the end of the logging.
10739 * See the comments in fast_page_fault().
10740 * For small sptes, nothing is done if the dirty log is in the
10741 * initial-all-set state. Otherwise, depending on whether pml
10742 * is enabled the D-bit or the W-bit will be cleared.
10743 */
10744 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10745 if (kvm_x86_ops.slot_enable_log_dirty) {
10746 kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10747 } else {
10748 int level =
10749 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10750 PG_LEVEL_2M : PG_LEVEL_4K;
10751
10752 /*
10753 * If we're with initial-all-set, we don't need
10754 * to write protect any small page because
10755 * they're reported as dirty already. However
10756 * we still need to write-protect huge pages
10757 * so that the page split can happen lazily on
10758 * the first write to the huge page.
10759 */
10760 kvm_mmu_slot_remove_write_access(kvm, new, level);
10761 }
10762 } else {
10763 if (kvm_x86_ops.slot_disable_log_dirty)
10764 kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10765 }
10766 }
10767
10768 void kvm_arch_commit_memory_region(struct kvm *kvm,
10769 const struct kvm_userspace_memory_region *mem,
10770 struct kvm_memory_slot *old,
10771 const struct kvm_memory_slot *new,
10772 enum kvm_mr_change change)
10773 {
10774 if (!kvm->arch.n_requested_mmu_pages)
10775 kvm_mmu_change_mmu_pages(kvm,
10776 kvm_mmu_calculate_default_mmu_pages(kvm));
10777
10778 /*
10779 * FIXME: const-ify all uses of struct kvm_memory_slot.
10780 */
10781 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10782
10783 /* Free the arrays associated with the old memslot. */
10784 if (change == KVM_MR_MOVE)
10785 kvm_arch_free_memslot(kvm, old);
10786 }
10787
10788 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10789 {
10790 kvm_mmu_zap_all(kvm);
10791 }
10792
10793 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10794 struct kvm_memory_slot *slot)
10795 {
10796 kvm_page_track_flush_slot(kvm, slot);
10797 }
10798
10799 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10800 {
10801 return (is_guest_mode(vcpu) &&
10802 kvm_x86_ops.guest_apic_has_interrupt &&
10803 kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10804 }
10805
10806 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10807 {
10808 if (!list_empty_careful(&vcpu->async_pf.done))
10809 return true;
10810
10811 if (kvm_apic_has_events(vcpu))
10812 return true;
10813
10814 if (vcpu->arch.pv.pv_unhalted)
10815 return true;
10816
10817 if (vcpu->arch.exception.pending)
10818 return true;
10819
10820 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10821 (vcpu->arch.nmi_pending &&
10822 kvm_x86_ops.nmi_allowed(vcpu, false)))
10823 return true;
10824
10825 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10826 (vcpu->arch.smi_pending &&
10827 kvm_x86_ops.smi_allowed(vcpu, false)))
10828 return true;
10829
10830 if (kvm_arch_interrupt_allowed(vcpu) &&
10831 (kvm_cpu_has_interrupt(vcpu) ||
10832 kvm_guest_apic_has_interrupt(vcpu)))
10833 return true;
10834
10835 if (kvm_hv_has_stimer_pending(vcpu))
10836 return true;
10837
10838 if (is_guest_mode(vcpu) &&
10839 kvm_x86_ops.nested_ops->hv_timer_pending &&
10840 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10841 return true;
10842
10843 return false;
10844 }
10845
10846 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10847 {
10848 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10849 }
10850
10851 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10852 {
10853 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10854 return true;
10855
10856 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10857 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10858 kvm_test_request(KVM_REQ_EVENT, vcpu))
10859 return true;
10860
10861 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10862 return true;
10863
10864 return false;
10865 }
10866
10867 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10868 {
10869 return vcpu->arch.preempted_in_kernel;
10870 }
10871
10872 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10873 {
10874 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10875 }
10876
10877 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10878 {
10879 return kvm_x86_ops.interrupt_allowed(vcpu, false);
10880 }
10881
10882 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10883 {
10884 /* Can't read the RIP when guest state is protected, just return 0 */
10885 if (vcpu->arch.guest_state_protected)
10886 return 0;
10887
10888 if (is_64_bit_mode(vcpu))
10889 return kvm_rip_read(vcpu);
10890 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10891 kvm_rip_read(vcpu));
10892 }
10893 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10894
10895 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10896 {
10897 return kvm_get_linear_rip(vcpu) == linear_rip;
10898 }
10899 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10900
10901 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10902 {
10903 unsigned long rflags;
10904
10905 rflags = kvm_x86_ops.get_rflags(vcpu);
10906 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10907 rflags &= ~X86_EFLAGS_TF;
10908 return rflags;
10909 }
10910 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10911
10912 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10913 {
10914 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10915 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10916 rflags |= X86_EFLAGS_TF;
10917 kvm_x86_ops.set_rflags(vcpu, rflags);
10918 }
10919
10920 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10921 {
10922 __kvm_set_rflags(vcpu, rflags);
10923 kvm_make_request(KVM_REQ_EVENT, vcpu);
10924 }
10925 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10926
10927 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10928 {
10929 int r;
10930
10931 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10932 work->wakeup_all)
10933 return;
10934
10935 r = kvm_mmu_reload(vcpu);
10936 if (unlikely(r))
10937 return;
10938
10939 if (!vcpu->arch.mmu->direct_map &&
10940 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10941 return;
10942
10943 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10944 }
10945
10946 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10947 {
10948 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10949
10950 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10951 }
10952
10953 static inline u32 kvm_async_pf_next_probe(u32 key)
10954 {
10955 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10956 }
10957
10958 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10959 {
10960 u32 key = kvm_async_pf_hash_fn(gfn);
10961
10962 while (vcpu->arch.apf.gfns[key] != ~0)
10963 key = kvm_async_pf_next_probe(key);
10964
10965 vcpu->arch.apf.gfns[key] = gfn;
10966 }
10967
10968 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10969 {
10970 int i;
10971 u32 key = kvm_async_pf_hash_fn(gfn);
10972
10973 for (i = 0; i < ASYNC_PF_PER_VCPU &&
10974 (vcpu->arch.apf.gfns[key] != gfn &&
10975 vcpu->arch.apf.gfns[key] != ~0); i++)
10976 key = kvm_async_pf_next_probe(key);
10977
10978 return key;
10979 }
10980
10981 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10982 {
10983 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10984 }
10985
10986 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10987 {
10988 u32 i, j, k;
10989
10990 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10991
10992 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10993 return;
10994
10995 while (true) {
10996 vcpu->arch.apf.gfns[i] = ~0;
10997 do {
10998 j = kvm_async_pf_next_probe(j);
10999 if (vcpu->arch.apf.gfns[j] == ~0)
11000 return;
11001 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
11002 /*
11003 * k lies cyclically in ]i,j]
11004 * | i.k.j |
11005 * |....j i.k.| or |.k..j i...|
11006 */
11007 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
11008 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
11009 i = j;
11010 }
11011 }
11012
11013 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
11014 {
11015 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
11016
11017 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
11018 sizeof(reason));
11019 }
11020
11021 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
11022 {
11023 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11024
11025 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11026 &token, offset, sizeof(token));
11027 }
11028
11029 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
11030 {
11031 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11032 u32 val;
11033
11034 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11035 &val, offset, sizeof(val)))
11036 return false;
11037
11038 return !val;
11039 }
11040
11041 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
11042 {
11043 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
11044 return false;
11045
11046 if (!kvm_pv_async_pf_enabled(vcpu) ||
11047 (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
11048 return false;
11049
11050 return true;
11051 }
11052
11053 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
11054 {
11055 if (unlikely(!lapic_in_kernel(vcpu) ||
11056 kvm_event_needs_reinjection(vcpu) ||
11057 vcpu->arch.exception.pending))
11058 return false;
11059
11060 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
11061 return false;
11062
11063 /*
11064 * If interrupts are off we cannot even use an artificial
11065 * halt state.
11066 */
11067 return kvm_arch_interrupt_allowed(vcpu);
11068 }
11069
11070 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
11071 struct kvm_async_pf *work)
11072 {
11073 struct x86_exception fault;
11074
11075 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
11076 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
11077
11078 if (kvm_can_deliver_async_pf(vcpu) &&
11079 !apf_put_user_notpresent(vcpu)) {
11080 fault.vector = PF_VECTOR;
11081 fault.error_code_valid = true;
11082 fault.error_code = 0;
11083 fault.nested_page_fault = false;
11084 fault.address = work->arch.token;
11085 fault.async_page_fault = true;
11086 kvm_inject_page_fault(vcpu, &fault);
11087 return true;
11088 } else {
11089 /*
11090 * It is not possible to deliver a paravirtualized asynchronous
11091 * page fault, but putting the guest in an artificial halt state
11092 * can be beneficial nevertheless: if an interrupt arrives, we
11093 * can deliver it timely and perhaps the guest will schedule
11094 * another process. When the instruction that triggered a page
11095 * fault is retried, hopefully the page will be ready in the host.
11096 */
11097 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
11098 return false;
11099 }
11100 }
11101
11102 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
11103 struct kvm_async_pf *work)
11104 {
11105 struct kvm_lapic_irq irq = {
11106 .delivery_mode = APIC_DM_FIXED,
11107 .vector = vcpu->arch.apf.vec
11108 };
11109
11110 if (work->wakeup_all)
11111 work->arch.token = ~0; /* broadcast wakeup */
11112 else
11113 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
11114 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
11115
11116 if ((work->wakeup_all || work->notpresent_injected) &&
11117 kvm_pv_async_pf_enabled(vcpu) &&
11118 !apf_put_user_ready(vcpu, work->arch.token)) {
11119 vcpu->arch.apf.pageready_pending = true;
11120 kvm_apic_set_irq(vcpu, &irq, NULL);
11121 }
11122
11123 vcpu->arch.apf.halted = false;
11124 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11125 }
11126
11127 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
11128 {
11129 kvm_make_request(KVM_REQ_APF_READY, vcpu);
11130 if (!vcpu->arch.apf.pageready_pending)
11131 kvm_vcpu_kick(vcpu);
11132 }
11133
11134 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
11135 {
11136 if (!kvm_pv_async_pf_enabled(vcpu))
11137 return true;
11138 else
11139 return apf_pageready_slot_free(vcpu);
11140 }
11141
11142 void kvm_arch_start_assignment(struct kvm *kvm)
11143 {
11144 atomic_inc(&kvm->arch.assigned_device_count);
11145 }
11146 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
11147
11148 void kvm_arch_end_assignment(struct kvm *kvm)
11149 {
11150 atomic_dec(&kvm->arch.assigned_device_count);
11151 }
11152 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
11153
11154 bool kvm_arch_has_assigned_device(struct kvm *kvm)
11155 {
11156 return atomic_read(&kvm->arch.assigned_device_count);
11157 }
11158 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
11159
11160 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
11161 {
11162 atomic_inc(&kvm->arch.noncoherent_dma_count);
11163 }
11164 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
11165
11166 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
11167 {
11168 atomic_dec(&kvm->arch.noncoherent_dma_count);
11169 }
11170 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
11171
11172 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
11173 {
11174 return atomic_read(&kvm->arch.noncoherent_dma_count);
11175 }
11176 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
11177
11178 bool kvm_arch_has_irq_bypass(void)
11179 {
11180 return true;
11181 }
11182
11183 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
11184 struct irq_bypass_producer *prod)
11185 {
11186 struct kvm_kernel_irqfd *irqfd =
11187 container_of(cons, struct kvm_kernel_irqfd, consumer);
11188 int ret;
11189
11190 irqfd->producer = prod;
11191 kvm_arch_start_assignment(irqfd->kvm);
11192 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
11193 prod->irq, irqfd->gsi, 1);
11194
11195 if (ret)
11196 kvm_arch_end_assignment(irqfd->kvm);
11197
11198 return ret;
11199 }
11200
11201 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
11202 struct irq_bypass_producer *prod)
11203 {
11204 int ret;
11205 struct kvm_kernel_irqfd *irqfd =
11206 container_of(cons, struct kvm_kernel_irqfd, consumer);
11207
11208 WARN_ON(irqfd->producer != prod);
11209 irqfd->producer = NULL;
11210
11211 /*
11212 * When producer of consumer is unregistered, we change back to
11213 * remapped mode, so we can re-use the current implementation
11214 * when the irq is masked/disabled or the consumer side (KVM
11215 * int this case doesn't want to receive the interrupts.
11216 */
11217 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
11218 if (ret)
11219 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
11220 " fails: %d\n", irqfd->consumer.token, ret);
11221
11222 kvm_arch_end_assignment(irqfd->kvm);
11223 }
11224
11225 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
11226 uint32_t guest_irq, bool set)
11227 {
11228 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
11229 }
11230
11231 bool kvm_vector_hashing_enabled(void)
11232 {
11233 return vector_hashing;
11234 }
11235
11236 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11237 {
11238 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11239 }
11240 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11241
11242
11243 int kvm_spec_ctrl_test_value(u64 value)
11244 {
11245 /*
11246 * test that setting IA32_SPEC_CTRL to given value
11247 * is allowed by the host processor
11248 */
11249
11250 u64 saved_value;
11251 unsigned long flags;
11252 int ret = 0;
11253
11254 local_irq_save(flags);
11255
11256 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11257 ret = 1;
11258 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11259 ret = 1;
11260 else
11261 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11262
11263 local_irq_restore(flags);
11264
11265 return ret;
11266 }
11267 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11268
11269 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11270 {
11271 struct x86_exception fault;
11272 u32 access = error_code &
11273 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11274
11275 if (!(error_code & PFERR_PRESENT_MASK) ||
11276 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11277 /*
11278 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11279 * tables probably do not match the TLB. Just proceed
11280 * with the error code that the processor gave.
11281 */
11282 fault.vector = PF_VECTOR;
11283 fault.error_code_valid = true;
11284 fault.error_code = error_code;
11285 fault.nested_page_fault = false;
11286 fault.address = gva;
11287 }
11288 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11289 }
11290 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11291
11292 /*
11293 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11294 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11295 * indicates whether exit to userspace is needed.
11296 */
11297 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11298 struct x86_exception *e)
11299 {
11300 if (r == X86EMUL_PROPAGATE_FAULT) {
11301 kvm_inject_emulated_page_fault(vcpu, e);
11302 return 1;
11303 }
11304
11305 /*
11306 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11307 * while handling a VMX instruction KVM could've handled the request
11308 * correctly by exiting to userspace and performing I/O but there
11309 * doesn't seem to be a real use-case behind such requests, just return
11310 * KVM_EXIT_INTERNAL_ERROR for now.
11311 */
11312 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11313 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11314 vcpu->run->internal.ndata = 0;
11315
11316 return 0;
11317 }
11318 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11319
11320 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11321 {
11322 bool pcid_enabled;
11323 struct x86_exception e;
11324 unsigned i;
11325 unsigned long roots_to_free = 0;
11326 struct {
11327 u64 pcid;
11328 u64 gla;
11329 } operand;
11330 int r;
11331
11332 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11333 if (r != X86EMUL_CONTINUE)
11334 return kvm_handle_memory_failure(vcpu, r, &e);
11335
11336 if (operand.pcid >> 12 != 0) {
11337 kvm_inject_gp(vcpu, 0);
11338 return 1;
11339 }
11340
11341 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11342
11343 switch (type) {
11344 case INVPCID_TYPE_INDIV_ADDR:
11345 if ((!pcid_enabled && (operand.pcid != 0)) ||
11346 is_noncanonical_address(operand.gla, vcpu)) {
11347 kvm_inject_gp(vcpu, 0);
11348 return 1;
11349 }
11350 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11351 return kvm_skip_emulated_instruction(vcpu);
11352
11353 case INVPCID_TYPE_SINGLE_CTXT:
11354 if (!pcid_enabled && (operand.pcid != 0)) {
11355 kvm_inject_gp(vcpu, 0);
11356 return 1;
11357 }
11358
11359 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11360 kvm_mmu_sync_roots(vcpu);
11361 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11362 }
11363
11364 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11365 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11366 == operand.pcid)
11367 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11368
11369 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11370 /*
11371 * If neither the current cr3 nor any of the prev_roots use the
11372 * given PCID, then nothing needs to be done here because a
11373 * resync will happen anyway before switching to any other CR3.
11374 */
11375
11376 return kvm_skip_emulated_instruction(vcpu);
11377
11378 case INVPCID_TYPE_ALL_NON_GLOBAL:
11379 /*
11380 * Currently, KVM doesn't mark global entries in the shadow
11381 * page tables, so a non-global flush just degenerates to a
11382 * global flush. If needed, we could optimize this later by
11383 * keeping track of global entries in shadow page tables.
11384 */
11385
11386 fallthrough;
11387 case INVPCID_TYPE_ALL_INCL_GLOBAL:
11388 kvm_mmu_unload(vcpu);
11389 return kvm_skip_emulated_instruction(vcpu);
11390
11391 default:
11392 BUG(); /* We have already checked above that type <= 3 */
11393 }
11394 }
11395 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11396
11397 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
11398 {
11399 struct kvm_run *run = vcpu->run;
11400 struct kvm_mmio_fragment *frag;
11401 unsigned int len;
11402
11403 BUG_ON(!vcpu->mmio_needed);
11404
11405 /* Complete previous fragment */
11406 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11407 len = min(8u, frag->len);
11408 if (!vcpu->mmio_is_write)
11409 memcpy(frag->data, run->mmio.data, len);
11410
11411 if (frag->len <= 8) {
11412 /* Switch to the next fragment. */
11413 frag++;
11414 vcpu->mmio_cur_fragment++;
11415 } else {
11416 /* Go forward to the next mmio piece. */
11417 frag->data += len;
11418 frag->gpa += len;
11419 frag->len -= len;
11420 }
11421
11422 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11423 vcpu->mmio_needed = 0;
11424
11425 // VMG change, at this point, we're always done
11426 // RIP has already been advanced
11427 return 1;
11428 }
11429
11430 // More MMIO is needed
11431 run->mmio.phys_addr = frag->gpa;
11432 run->mmio.len = min(8u, frag->len);
11433 run->mmio.is_write = vcpu->mmio_is_write;
11434 if (run->mmio.is_write)
11435 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11436 run->exit_reason = KVM_EXIT_MMIO;
11437
11438 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11439
11440 return 0;
11441 }
11442
11443 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11444 void *data)
11445 {
11446 int handled;
11447 struct kvm_mmio_fragment *frag;
11448
11449 if (!data)
11450 return -EINVAL;
11451
11452 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11453 if (handled == bytes)
11454 return 1;
11455
11456 bytes -= handled;
11457 gpa += handled;
11458 data += handled;
11459
11460 /*TODO: Check if need to increment number of frags */
11461 frag = vcpu->mmio_fragments;
11462 vcpu->mmio_nr_fragments = 1;
11463 frag->len = bytes;
11464 frag->gpa = gpa;
11465 frag->data = data;
11466
11467 vcpu->mmio_needed = 1;
11468 vcpu->mmio_cur_fragment = 0;
11469
11470 vcpu->run->mmio.phys_addr = gpa;
11471 vcpu->run->mmio.len = min(8u, frag->len);
11472 vcpu->run->mmio.is_write = 1;
11473 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
11474 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11475
11476 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11477
11478 return 0;
11479 }
11480 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
11481
11482 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11483 void *data)
11484 {
11485 int handled;
11486 struct kvm_mmio_fragment *frag;
11487
11488 if (!data)
11489 return -EINVAL;
11490
11491 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11492 if (handled == bytes)
11493 return 1;
11494
11495 bytes -= handled;
11496 gpa += handled;
11497 data += handled;
11498
11499 /*TODO: Check if need to increment number of frags */
11500 frag = vcpu->mmio_fragments;
11501 vcpu->mmio_nr_fragments = 1;
11502 frag->len = bytes;
11503 frag->gpa = gpa;
11504 frag->data = data;
11505
11506 vcpu->mmio_needed = 1;
11507 vcpu->mmio_cur_fragment = 0;
11508
11509 vcpu->run->mmio.phys_addr = gpa;
11510 vcpu->run->mmio.len = min(8u, frag->len);
11511 vcpu->run->mmio.is_write = 0;
11512 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11513
11514 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11515
11516 return 0;
11517 }
11518 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
11519
11520 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
11521 {
11522 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data,
11523 vcpu->arch.pio.count * vcpu->arch.pio.size);
11524 vcpu->arch.pio.count = 0;
11525
11526 return 1;
11527 }
11528
11529 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
11530 unsigned int port, void *data, unsigned int count)
11531 {
11532 int ret;
11533
11534 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port,
11535 data, count);
11536 if (ret)
11537 return ret;
11538
11539 vcpu->arch.pio.count = 0;
11540
11541 return 0;
11542 }
11543
11544 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
11545 unsigned int port, void *data, unsigned int count)
11546 {
11547 int ret;
11548
11549 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port,
11550 data, count);
11551 if (ret) {
11552 vcpu->arch.pio.count = 0;
11553 } else {
11554 vcpu->arch.guest_ins_data = data;
11555 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
11556 }
11557
11558 return 0;
11559 }
11560
11561 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
11562 unsigned int port, void *data, unsigned int count,
11563 int in)
11564 {
11565 return in ? kvm_sev_es_ins(vcpu, size, port, data, count)
11566 : kvm_sev_es_outs(vcpu, size, port, data, count);
11567 }
11568 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
11569
11570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
11571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11579 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11580 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11581 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11582 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11583 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11585 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11586 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11587 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11588 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11589 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11590 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11591 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11592 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
11593 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
11594 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
11595 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
11596 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
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