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Merge branch '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19 #include <linux/kvm_host.h>
20 #include "irq.h"
21 #include "ioapic.h"
22 #include "mmu.h"
23 #include "i8254.h"
24 #include "tss.h"
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
27 #include "x86.h"
28 #include "cpuid.h"
29 #include "pmu.h"
30 #include "hyperv.h"
31 #include "lapic.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
60
61 #include <trace/events/kvm.h>
62
63 #include <asm/debugreg.h>
64 #include <asm/msr.h>
65 #include <asm/desc.h>
66 #include <asm/mce.h>
67 #include <linux/kernel_stat.h>
68 #include <asm/fpu/internal.h> /* Ugh! */
69 #include <asm/pvclock.h>
70 #include <asm/div64.h>
71 #include <asm/irq_remapping.h>
72 #include <asm/mshyperv.h>
73 #include <asm/hypervisor.h>
74 #include <asm/tlbflush.h>
75 #include <asm/intel_pt.h>
76 #include <asm/emulate_prefix.h>
77 #include <clocksource/hyperv_timer.h>
78
79 #define CREATE_TRACE_POINTS
80 #include "trace.h"
81
82 #define MAX_IO_MSRS 256
83 #define KVM_MAX_MCE_BANKS 32
84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
86
87 #define emul_to_vcpu(ctxt) \
88 ((struct kvm_vcpu *)(ctxt)->vcpu)
89
90 /* EFER defaults:
91 * - enable syscall per default because its emulated by KVM
92 * - enable LME and LMA per default on 64 bit KVM
93 */
94 #ifdef CONFIG_X86_64
95 static
96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
97 #else
98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
99 #endif
100
101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
102
103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
105
106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
107 static void process_nmi(struct kvm_vcpu *vcpu);
108 static void process_smi(struct kvm_vcpu *vcpu);
109 static void enter_smm(struct kvm_vcpu *vcpu);
110 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
111 static void store_regs(struct kvm_vcpu *vcpu);
112 static int sync_regs(struct kvm_vcpu *vcpu);
113
114 struct kvm_x86_ops kvm_x86_ops __read_mostly;
115 EXPORT_SYMBOL_GPL(kvm_x86_ops);
116
117 static bool __read_mostly ignore_msrs = 0;
118 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
119
120 static bool __read_mostly report_ignored_msrs = true;
121 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
122
123 unsigned int min_timer_period_us = 200;
124 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
125
126 static bool __read_mostly kvmclock_periodic_sync = true;
127 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
128
129 bool __read_mostly kvm_has_tsc_control;
130 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
131 u32 __read_mostly kvm_max_guest_tsc_khz;
132 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
133 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
134 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
135 u64 __read_mostly kvm_max_tsc_scaling_ratio;
136 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
137 u64 __read_mostly kvm_default_tsc_scaling_ratio;
138 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
139
140 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
141 static u32 __read_mostly tsc_tolerance_ppm = 250;
142 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
143
144 /*
145 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
146 * adaptive tuning starting from default advancment of 1000ns. '0' disables
147 * advancement entirely. Any other value is used as-is and disables adaptive
148 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
149 */
150 static int __read_mostly lapic_timer_advance_ns = -1;
151 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
152
153 static bool __read_mostly vector_hashing = true;
154 module_param(vector_hashing, bool, S_IRUGO);
155
156 bool __read_mostly enable_vmware_backdoor = false;
157 module_param(enable_vmware_backdoor, bool, S_IRUGO);
158 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
159
160 static bool __read_mostly force_emulation_prefix = false;
161 module_param(force_emulation_prefix, bool, S_IRUGO);
162
163 int __read_mostly pi_inject_timer = -1;
164 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
165
166 /*
167 * Restoring the host value for MSRs that are only consumed when running in
168 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
169 * returns to userspace, i.e. the kernel can run with the guest's value.
170 */
171 #define KVM_MAX_NR_USER_RETURN_MSRS 16
172
173 struct kvm_user_return_msrs_global {
174 int nr;
175 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
176 };
177
178 struct kvm_user_return_msrs {
179 struct user_return_notifier urn;
180 bool registered;
181 struct kvm_user_return_msr_values {
182 u64 host;
183 u64 curr;
184 } values[KVM_MAX_NR_USER_RETURN_MSRS];
185 };
186
187 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
188 static struct kvm_user_return_msrs __percpu *user_return_msrs;
189
190 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
191 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
192 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
193 | XFEATURE_MASK_PKRU)
194
195 u64 __read_mostly host_efer;
196 EXPORT_SYMBOL_GPL(host_efer);
197
198 bool __read_mostly allow_smaller_maxphyaddr = 0;
199 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
200
201 u64 __read_mostly host_xss;
202 EXPORT_SYMBOL_GPL(host_xss);
203 u64 __read_mostly supported_xss;
204 EXPORT_SYMBOL_GPL(supported_xss);
205
206 struct kvm_stats_debugfs_item debugfs_entries[] = {
207 VCPU_STAT("pf_fixed", pf_fixed),
208 VCPU_STAT("pf_guest", pf_guest),
209 VCPU_STAT("tlb_flush", tlb_flush),
210 VCPU_STAT("invlpg", invlpg),
211 VCPU_STAT("exits", exits),
212 VCPU_STAT("io_exits", io_exits),
213 VCPU_STAT("mmio_exits", mmio_exits),
214 VCPU_STAT("signal_exits", signal_exits),
215 VCPU_STAT("irq_window", irq_window_exits),
216 VCPU_STAT("nmi_window", nmi_window_exits),
217 VCPU_STAT("halt_exits", halt_exits),
218 VCPU_STAT("halt_successful_poll", halt_successful_poll),
219 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
220 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
221 VCPU_STAT("halt_wakeup", halt_wakeup),
222 VCPU_STAT("hypercalls", hypercalls),
223 VCPU_STAT("request_irq", request_irq_exits),
224 VCPU_STAT("irq_exits", irq_exits),
225 VCPU_STAT("host_state_reload", host_state_reload),
226 VCPU_STAT("fpu_reload", fpu_reload),
227 VCPU_STAT("insn_emulation", insn_emulation),
228 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
229 VCPU_STAT("irq_injections", irq_injections),
230 VCPU_STAT("nmi_injections", nmi_injections),
231 VCPU_STAT("req_event", req_event),
232 VCPU_STAT("l1d_flush", l1d_flush),
233 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
234 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
235 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
236 VM_STAT("mmu_pte_write", mmu_pte_write),
237 VM_STAT("mmu_pte_updated", mmu_pte_updated),
238 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
239 VM_STAT("mmu_flooded", mmu_flooded),
240 VM_STAT("mmu_recycled", mmu_recycled),
241 VM_STAT("mmu_cache_miss", mmu_cache_miss),
242 VM_STAT("mmu_unsync", mmu_unsync),
243 VM_STAT("remote_tlb_flush", remote_tlb_flush),
244 VM_STAT("largepages", lpages, .mode = 0444),
245 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
246 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
247 { NULL }
248 };
249
250 u64 __read_mostly host_xcr0;
251 u64 __read_mostly supported_xcr0;
252 EXPORT_SYMBOL_GPL(supported_xcr0);
253
254 static struct kmem_cache *x86_fpu_cache;
255
256 static struct kmem_cache *x86_emulator_cache;
257
258 /*
259 * When called, it means the previous get/set msr reached an invalid msr.
260 * Return true if we want to ignore/silent this failed msr access.
261 */
262 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
263 u64 data, bool write)
264 {
265 const char *op = write ? "wrmsr" : "rdmsr";
266
267 if (ignore_msrs) {
268 if (report_ignored_msrs)
269 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
270 op, msr, data);
271 /* Mask the error */
272 return true;
273 } else {
274 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
275 op, msr, data);
276 return false;
277 }
278 }
279
280 static struct kmem_cache *kvm_alloc_emulator_cache(void)
281 {
282 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
283 unsigned int size = sizeof(struct x86_emulate_ctxt);
284
285 return kmem_cache_create_usercopy("x86_emulator", size,
286 __alignof__(struct x86_emulate_ctxt),
287 SLAB_ACCOUNT, useroffset,
288 size - useroffset, NULL);
289 }
290
291 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
292
293 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
294 {
295 int i;
296 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
297 vcpu->arch.apf.gfns[i] = ~0;
298 }
299
300 static void kvm_on_user_return(struct user_return_notifier *urn)
301 {
302 unsigned slot;
303 struct kvm_user_return_msrs *msrs
304 = container_of(urn, struct kvm_user_return_msrs, urn);
305 struct kvm_user_return_msr_values *values;
306 unsigned long flags;
307
308 /*
309 * Disabling irqs at this point since the following code could be
310 * interrupted and executed through kvm_arch_hardware_disable()
311 */
312 local_irq_save(flags);
313 if (msrs->registered) {
314 msrs->registered = false;
315 user_return_notifier_unregister(urn);
316 }
317 local_irq_restore(flags);
318 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
319 values = &msrs->values[slot];
320 if (values->host != values->curr) {
321 wrmsrl(user_return_msrs_global.msrs[slot], values->host);
322 values->curr = values->host;
323 }
324 }
325 }
326
327 void kvm_define_user_return_msr(unsigned slot, u32 msr)
328 {
329 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
330 user_return_msrs_global.msrs[slot] = msr;
331 if (slot >= user_return_msrs_global.nr)
332 user_return_msrs_global.nr = slot + 1;
333 }
334 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
335
336 static void kvm_user_return_msr_cpu_online(void)
337 {
338 unsigned int cpu = smp_processor_id();
339 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
340 u64 value;
341 int i;
342
343 for (i = 0; i < user_return_msrs_global.nr; ++i) {
344 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
345 msrs->values[i].host = value;
346 msrs->values[i].curr = value;
347 }
348 }
349
350 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
351 {
352 unsigned int cpu = smp_processor_id();
353 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
354 int err;
355
356 value = (value & mask) | (msrs->values[slot].host & ~mask);
357 if (value == msrs->values[slot].curr)
358 return 0;
359 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
360 if (err)
361 return 1;
362
363 msrs->values[slot].curr = value;
364 if (!msrs->registered) {
365 msrs->urn.on_user_return = kvm_on_user_return;
366 user_return_notifier_register(&msrs->urn);
367 msrs->registered = true;
368 }
369 return 0;
370 }
371 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
372
373 static void drop_user_return_notifiers(void)
374 {
375 unsigned int cpu = smp_processor_id();
376 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
377
378 if (msrs->registered)
379 kvm_on_user_return(&msrs->urn);
380 }
381
382 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
383 {
384 return vcpu->arch.apic_base;
385 }
386 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
387
388 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
389 {
390 return kvm_apic_mode(kvm_get_apic_base(vcpu));
391 }
392 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
393
394 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
395 {
396 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
397 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
398 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
399 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
400
401 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
402 return 1;
403 if (!msr_info->host_initiated) {
404 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
405 return 1;
406 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
407 return 1;
408 }
409
410 kvm_lapic_set_base(vcpu, msr_info->data);
411 kvm_recalculate_apic_map(vcpu->kvm);
412 return 0;
413 }
414 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
415
416 asmlinkage __visible noinstr void kvm_spurious_fault(void)
417 {
418 /* Fault while not rebooting. We want the trace. */
419 BUG_ON(!kvm_rebooting);
420 }
421 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
422
423 #define EXCPT_BENIGN 0
424 #define EXCPT_CONTRIBUTORY 1
425 #define EXCPT_PF 2
426
427 static int exception_class(int vector)
428 {
429 switch (vector) {
430 case PF_VECTOR:
431 return EXCPT_PF;
432 case DE_VECTOR:
433 case TS_VECTOR:
434 case NP_VECTOR:
435 case SS_VECTOR:
436 case GP_VECTOR:
437 return EXCPT_CONTRIBUTORY;
438 default:
439 break;
440 }
441 return EXCPT_BENIGN;
442 }
443
444 #define EXCPT_FAULT 0
445 #define EXCPT_TRAP 1
446 #define EXCPT_ABORT 2
447 #define EXCPT_INTERRUPT 3
448
449 static int exception_type(int vector)
450 {
451 unsigned int mask;
452
453 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
454 return EXCPT_INTERRUPT;
455
456 mask = 1 << vector;
457
458 /* #DB is trap, as instruction watchpoints are handled elsewhere */
459 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
460 return EXCPT_TRAP;
461
462 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
463 return EXCPT_ABORT;
464
465 /* Reserved exceptions will result in fault */
466 return EXCPT_FAULT;
467 }
468
469 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
470 {
471 unsigned nr = vcpu->arch.exception.nr;
472 bool has_payload = vcpu->arch.exception.has_payload;
473 unsigned long payload = vcpu->arch.exception.payload;
474
475 if (!has_payload)
476 return;
477
478 switch (nr) {
479 case DB_VECTOR:
480 /*
481 * "Certain debug exceptions may clear bit 0-3. The
482 * remaining contents of the DR6 register are never
483 * cleared by the processor".
484 */
485 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
486 /*
487 * DR6.RTM is set by all #DB exceptions that don't clear it.
488 */
489 vcpu->arch.dr6 |= DR6_RTM;
490 vcpu->arch.dr6 |= payload;
491 /*
492 * Bit 16 should be set in the payload whenever the #DB
493 * exception should clear DR6.RTM. This makes the payload
494 * compatible with the pending debug exceptions under VMX.
495 * Though not currently documented in the SDM, this also
496 * makes the payload compatible with the exit qualification
497 * for #DB exceptions under VMX.
498 */
499 vcpu->arch.dr6 ^= payload & DR6_RTM;
500
501 /*
502 * The #DB payload is defined as compatible with the 'pending
503 * debug exceptions' field under VMX, not DR6. While bit 12 is
504 * defined in the 'pending debug exceptions' field (enabled
505 * breakpoint), it is reserved and must be zero in DR6.
506 */
507 vcpu->arch.dr6 &= ~BIT(12);
508 break;
509 case PF_VECTOR:
510 vcpu->arch.cr2 = payload;
511 break;
512 }
513
514 vcpu->arch.exception.has_payload = false;
515 vcpu->arch.exception.payload = 0;
516 }
517 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
518
519 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
520 unsigned nr, bool has_error, u32 error_code,
521 bool has_payload, unsigned long payload, bool reinject)
522 {
523 u32 prev_nr;
524 int class1, class2;
525
526 kvm_make_request(KVM_REQ_EVENT, vcpu);
527
528 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
529 queue:
530 if (has_error && !is_protmode(vcpu))
531 has_error = false;
532 if (reinject) {
533 /*
534 * On vmentry, vcpu->arch.exception.pending is only
535 * true if an event injection was blocked by
536 * nested_run_pending. In that case, however,
537 * vcpu_enter_guest requests an immediate exit,
538 * and the guest shouldn't proceed far enough to
539 * need reinjection.
540 */
541 WARN_ON_ONCE(vcpu->arch.exception.pending);
542 vcpu->arch.exception.injected = true;
543 if (WARN_ON_ONCE(has_payload)) {
544 /*
545 * A reinjected event has already
546 * delivered its payload.
547 */
548 has_payload = false;
549 payload = 0;
550 }
551 } else {
552 vcpu->arch.exception.pending = true;
553 vcpu->arch.exception.injected = false;
554 }
555 vcpu->arch.exception.has_error_code = has_error;
556 vcpu->arch.exception.nr = nr;
557 vcpu->arch.exception.error_code = error_code;
558 vcpu->arch.exception.has_payload = has_payload;
559 vcpu->arch.exception.payload = payload;
560 if (!is_guest_mode(vcpu))
561 kvm_deliver_exception_payload(vcpu);
562 return;
563 }
564
565 /* to check exception */
566 prev_nr = vcpu->arch.exception.nr;
567 if (prev_nr == DF_VECTOR) {
568 /* triple fault -> shutdown */
569 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
570 return;
571 }
572 class1 = exception_class(prev_nr);
573 class2 = exception_class(nr);
574 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
575 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
576 /*
577 * Generate double fault per SDM Table 5-5. Set
578 * exception.pending = true so that the double fault
579 * can trigger a nested vmexit.
580 */
581 vcpu->arch.exception.pending = true;
582 vcpu->arch.exception.injected = false;
583 vcpu->arch.exception.has_error_code = true;
584 vcpu->arch.exception.nr = DF_VECTOR;
585 vcpu->arch.exception.error_code = 0;
586 vcpu->arch.exception.has_payload = false;
587 vcpu->arch.exception.payload = 0;
588 } else
589 /* replace previous exception with a new one in a hope
590 that instruction re-execution will regenerate lost
591 exception */
592 goto queue;
593 }
594
595 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
596 {
597 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
598 }
599 EXPORT_SYMBOL_GPL(kvm_queue_exception);
600
601 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
602 {
603 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
604 }
605 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
606
607 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
608 unsigned long payload)
609 {
610 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
611 }
612 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
613
614 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
615 u32 error_code, unsigned long payload)
616 {
617 kvm_multiple_exception(vcpu, nr, true, error_code,
618 true, payload, false);
619 }
620
621 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
622 {
623 if (err)
624 kvm_inject_gp(vcpu, 0);
625 else
626 return kvm_skip_emulated_instruction(vcpu);
627
628 return 1;
629 }
630 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
631
632 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
633 {
634 ++vcpu->stat.pf_guest;
635 vcpu->arch.exception.nested_apf =
636 is_guest_mode(vcpu) && fault->async_page_fault;
637 if (vcpu->arch.exception.nested_apf) {
638 vcpu->arch.apf.nested_apf_token = fault->address;
639 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
640 } else {
641 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
642 fault->address);
643 }
644 }
645 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
646
647 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
648 struct x86_exception *fault)
649 {
650 struct kvm_mmu *fault_mmu;
651 WARN_ON_ONCE(fault->vector != PF_VECTOR);
652
653 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
654 vcpu->arch.walk_mmu;
655
656 /*
657 * Invalidate the TLB entry for the faulting address, if it exists,
658 * else the access will fault indefinitely (and to emulate hardware).
659 */
660 if ((fault->error_code & PFERR_PRESENT_MASK) &&
661 !(fault->error_code & PFERR_RSVD_MASK))
662 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
663 fault_mmu->root_hpa);
664
665 fault_mmu->inject_page_fault(vcpu, fault);
666 return fault->nested_page_fault;
667 }
668 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
669
670 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
671 {
672 atomic_inc(&vcpu->arch.nmi_queued);
673 kvm_make_request(KVM_REQ_NMI, vcpu);
674 }
675 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
676
677 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
678 {
679 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
680 }
681 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
682
683 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
684 {
685 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
686 }
687 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
688
689 /*
690 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
691 * a #GP and return false.
692 */
693 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
694 {
695 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
696 return true;
697 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
698 return false;
699 }
700 EXPORT_SYMBOL_GPL(kvm_require_cpl);
701
702 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
703 {
704 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return true;
706
707 kvm_queue_exception(vcpu, UD_VECTOR);
708 return false;
709 }
710 EXPORT_SYMBOL_GPL(kvm_require_dr);
711
712 /*
713 * This function will be used to read from the physical memory of the currently
714 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
715 * can read from guest physical or from the guest's guest physical memory.
716 */
717 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
718 gfn_t ngfn, void *data, int offset, int len,
719 u32 access)
720 {
721 struct x86_exception exception;
722 gfn_t real_gfn;
723 gpa_t ngpa;
724
725 ngpa = gfn_to_gpa(ngfn);
726 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
727 if (real_gfn == UNMAPPED_GVA)
728 return -EFAULT;
729
730 real_gfn = gpa_to_gfn(real_gfn);
731
732 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
733 }
734 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
735
736 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
737 void *data, int offset, int len, u32 access)
738 {
739 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
740 data, offset, len, access);
741 }
742
743 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
744 {
745 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
746 rsvd_bits(1, 2);
747 }
748
749 /*
750 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
751 */
752 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
753 {
754 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
755 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
756 int i;
757 int ret;
758 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
759
760 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
761 offset * sizeof(u64), sizeof(pdpte),
762 PFERR_USER_MASK|PFERR_WRITE_MASK);
763 if (ret < 0) {
764 ret = 0;
765 goto out;
766 }
767 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
768 if ((pdpte[i] & PT_PRESENT_MASK) &&
769 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
770 ret = 0;
771 goto out;
772 }
773 }
774 ret = 1;
775
776 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
777 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
778
779 out:
780
781 return ret;
782 }
783 EXPORT_SYMBOL_GPL(load_pdptrs);
784
785 bool pdptrs_changed(struct kvm_vcpu *vcpu)
786 {
787 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
788 int offset;
789 gfn_t gfn;
790 int r;
791
792 if (!is_pae_paging(vcpu))
793 return false;
794
795 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
796 return true;
797
798 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
799 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
800 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
801 PFERR_USER_MASK | PFERR_WRITE_MASK);
802 if (r < 0)
803 return true;
804
805 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
806 }
807 EXPORT_SYMBOL_GPL(pdptrs_changed);
808
809 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
810 {
811 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
812
813 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
814 kvm_clear_async_pf_completion_queue(vcpu);
815 kvm_async_pf_hash_reset(vcpu);
816 }
817
818 if ((cr0 ^ old_cr0) & update_bits)
819 kvm_mmu_reset_context(vcpu);
820
821 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
822 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
823 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
824 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
825 }
826 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
827
828 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
829 {
830 unsigned long old_cr0 = kvm_read_cr0(vcpu);
831 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
832
833 cr0 |= X86_CR0_ET;
834
835 #ifdef CONFIG_X86_64
836 if (cr0 & 0xffffffff00000000UL)
837 return 1;
838 #endif
839
840 cr0 &= ~CR0_RESERVED_BITS;
841
842 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
843 return 1;
844
845 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
846 return 1;
847
848 #ifdef CONFIG_X86_64
849 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
850 (cr0 & X86_CR0_PG)) {
851 int cs_db, cs_l;
852
853 if (!is_pae(vcpu))
854 return 1;
855 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
856 if (cs_l)
857 return 1;
858 }
859 #endif
860 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
861 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
862 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
863 return 1;
864
865 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
866 return 1;
867
868 kvm_x86_ops.set_cr0(vcpu, cr0);
869
870 kvm_post_set_cr0(vcpu, old_cr0, cr0);
871
872 return 0;
873 }
874 EXPORT_SYMBOL_GPL(kvm_set_cr0);
875
876 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
877 {
878 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
879 }
880 EXPORT_SYMBOL_GPL(kvm_lmsw);
881
882 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
883 {
884 if (vcpu->arch.guest_state_protected)
885 return;
886
887 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
888
889 if (vcpu->arch.xcr0 != host_xcr0)
890 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
891
892 if (vcpu->arch.xsaves_enabled &&
893 vcpu->arch.ia32_xss != host_xss)
894 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
895 }
896
897 if (static_cpu_has(X86_FEATURE_PKU) &&
898 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
899 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
900 vcpu->arch.pkru != vcpu->arch.host_pkru)
901 __write_pkru(vcpu->arch.pkru);
902 }
903 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
904
905 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
906 {
907 if (vcpu->arch.guest_state_protected)
908 return;
909
910 if (static_cpu_has(X86_FEATURE_PKU) &&
911 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
912 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
913 vcpu->arch.pkru = rdpkru();
914 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
915 __write_pkru(vcpu->arch.host_pkru);
916 }
917
918 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
919
920 if (vcpu->arch.xcr0 != host_xcr0)
921 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
922
923 if (vcpu->arch.xsaves_enabled &&
924 vcpu->arch.ia32_xss != host_xss)
925 wrmsrl(MSR_IA32_XSS, host_xss);
926 }
927
928 }
929 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
930
931 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
932 {
933 u64 xcr0 = xcr;
934 u64 old_xcr0 = vcpu->arch.xcr0;
935 u64 valid_bits;
936
937 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
938 if (index != XCR_XFEATURE_ENABLED_MASK)
939 return 1;
940 if (!(xcr0 & XFEATURE_MASK_FP))
941 return 1;
942 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
943 return 1;
944
945 /*
946 * Do not allow the guest to set bits that we do not support
947 * saving. However, xcr0 bit 0 is always set, even if the
948 * emulated CPU does not support XSAVE (see fx_init).
949 */
950 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
951 if (xcr0 & ~valid_bits)
952 return 1;
953
954 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
955 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
956 return 1;
957
958 if (xcr0 & XFEATURE_MASK_AVX512) {
959 if (!(xcr0 & XFEATURE_MASK_YMM))
960 return 1;
961 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
962 return 1;
963 }
964 vcpu->arch.xcr0 = xcr0;
965
966 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
967 kvm_update_cpuid_runtime(vcpu);
968 return 0;
969 }
970
971 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
972 {
973 if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
974 __kvm_set_xcr(vcpu, index, xcr)) {
975 kvm_inject_gp(vcpu, 0);
976 return 1;
977 }
978 return 0;
979 }
980 EXPORT_SYMBOL_GPL(kvm_set_xcr);
981
982 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
983 {
984 if (cr4 & cr4_reserved_bits)
985 return false;
986
987 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
988 return false;
989
990 return kvm_x86_ops.is_valid_cr4(vcpu, cr4);
991 }
992 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
993
994 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
995 {
996 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
997 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
998
999 if (((cr4 ^ old_cr4) & mmu_role_bits) ||
1000 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1001 kvm_mmu_reset_context(vcpu);
1002 }
1003 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1004
1005 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1006 {
1007 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1008 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
1009 X86_CR4_SMEP;
1010
1011 if (!kvm_is_valid_cr4(vcpu, cr4))
1012 return 1;
1013
1014 if (is_long_mode(vcpu)) {
1015 if (!(cr4 & X86_CR4_PAE))
1016 return 1;
1017 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1018 return 1;
1019 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1020 && ((cr4 ^ old_cr4) & pdptr_bits)
1021 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
1022 kvm_read_cr3(vcpu)))
1023 return 1;
1024
1025 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1026 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1027 return 1;
1028
1029 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1030 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1031 return 1;
1032 }
1033
1034 kvm_x86_ops.set_cr4(vcpu, cr4);
1035
1036 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1037
1038 return 0;
1039 }
1040 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1041
1042 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1043 {
1044 bool skip_tlb_flush = false;
1045 #ifdef CONFIG_X86_64
1046 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1047
1048 if (pcid_enabled) {
1049 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1050 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1051 }
1052 #endif
1053
1054 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1055 if (!skip_tlb_flush) {
1056 kvm_mmu_sync_roots(vcpu);
1057 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1058 }
1059 return 0;
1060 }
1061
1062 if (is_long_mode(vcpu) &&
1063 (cr3 & vcpu->arch.cr3_lm_rsvd_bits))
1064 return 1;
1065 else if (is_pae_paging(vcpu) &&
1066 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1067 return 1;
1068
1069 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1070 vcpu->arch.cr3 = cr3;
1071 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1072
1073 return 0;
1074 }
1075 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1076
1077 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1078 {
1079 if (cr8 & CR8_RESERVED_BITS)
1080 return 1;
1081 if (lapic_in_kernel(vcpu))
1082 kvm_lapic_set_tpr(vcpu, cr8);
1083 else
1084 vcpu->arch.cr8 = cr8;
1085 return 0;
1086 }
1087 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1088
1089 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1090 {
1091 if (lapic_in_kernel(vcpu))
1092 return kvm_lapic_get_cr8(vcpu);
1093 else
1094 return vcpu->arch.cr8;
1095 }
1096 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1097
1098 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1099 {
1100 int i;
1101
1102 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1103 for (i = 0; i < KVM_NR_DB_REGS; i++)
1104 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1105 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1106 }
1107 }
1108
1109 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1110 {
1111 unsigned long dr7;
1112
1113 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1114 dr7 = vcpu->arch.guest_debug_dr7;
1115 else
1116 dr7 = vcpu->arch.dr7;
1117 kvm_x86_ops.set_dr7(vcpu, dr7);
1118 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1119 if (dr7 & DR7_BP_EN_MASK)
1120 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1121 }
1122 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1123
1124 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1125 {
1126 u64 fixed = DR6_FIXED_1;
1127
1128 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1129 fixed |= DR6_RTM;
1130 return fixed;
1131 }
1132
1133 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1134 {
1135 size_t size = ARRAY_SIZE(vcpu->arch.db);
1136
1137 switch (dr) {
1138 case 0 ... 3:
1139 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1140 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1141 vcpu->arch.eff_db[dr] = val;
1142 break;
1143 case 4:
1144 case 6:
1145 if (!kvm_dr6_valid(val))
1146 return -1; /* #GP */
1147 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1148 break;
1149 case 5:
1150 default: /* 7 */
1151 if (!kvm_dr7_valid(val))
1152 return -1; /* #GP */
1153 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1154 kvm_update_dr7(vcpu);
1155 break;
1156 }
1157
1158 return 0;
1159 }
1160
1161 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1162 {
1163 if (__kvm_set_dr(vcpu, dr, val)) {
1164 kvm_inject_gp(vcpu, 0);
1165 return 1;
1166 }
1167 return 0;
1168 }
1169 EXPORT_SYMBOL_GPL(kvm_set_dr);
1170
1171 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1172 {
1173 size_t size = ARRAY_SIZE(vcpu->arch.db);
1174
1175 switch (dr) {
1176 case 0 ... 3:
1177 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1178 break;
1179 case 4:
1180 case 6:
1181 *val = vcpu->arch.dr6;
1182 break;
1183 case 5:
1184 default: /* 7 */
1185 *val = vcpu->arch.dr7;
1186 break;
1187 }
1188 return 0;
1189 }
1190 EXPORT_SYMBOL_GPL(kvm_get_dr);
1191
1192 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1193 {
1194 u32 ecx = kvm_rcx_read(vcpu);
1195 u64 data;
1196 int err;
1197
1198 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1199 if (err)
1200 return err;
1201 kvm_rax_write(vcpu, (u32)data);
1202 kvm_rdx_write(vcpu, data >> 32);
1203 return err;
1204 }
1205 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1206
1207 /*
1208 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1209 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1210 *
1211 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1212 * extract the supported MSRs from the related const lists.
1213 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1214 * capabilities of the host cpu. This capabilities test skips MSRs that are
1215 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1216 * may depend on host virtualization features rather than host cpu features.
1217 */
1218
1219 static const u32 msrs_to_save_all[] = {
1220 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1221 MSR_STAR,
1222 #ifdef CONFIG_X86_64
1223 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1224 #endif
1225 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1226 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1227 MSR_IA32_SPEC_CTRL,
1228 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1229 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1230 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1231 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1232 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1233 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1234 MSR_IA32_UMWAIT_CONTROL,
1235
1236 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1237 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1238 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1239 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1240 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1241 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1242 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1243 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1244 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1245 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1246 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1247 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1248 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1249 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1250 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1251 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1252 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1253 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1254 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1255 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1256 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1257 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1258 };
1259
1260 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1261 static unsigned num_msrs_to_save;
1262
1263 static const u32 emulated_msrs_all[] = {
1264 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1265 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1266 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1267 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1268 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1269 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1270 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1271 HV_X64_MSR_RESET,
1272 HV_X64_MSR_VP_INDEX,
1273 HV_X64_MSR_VP_RUNTIME,
1274 HV_X64_MSR_SCONTROL,
1275 HV_X64_MSR_STIMER0_CONFIG,
1276 HV_X64_MSR_VP_ASSIST_PAGE,
1277 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1278 HV_X64_MSR_TSC_EMULATION_STATUS,
1279 HV_X64_MSR_SYNDBG_OPTIONS,
1280 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1281 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1282 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1283
1284 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1285 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1286
1287 MSR_IA32_TSC_ADJUST,
1288 MSR_IA32_TSCDEADLINE,
1289 MSR_IA32_ARCH_CAPABILITIES,
1290 MSR_IA32_PERF_CAPABILITIES,
1291 MSR_IA32_MISC_ENABLE,
1292 MSR_IA32_MCG_STATUS,
1293 MSR_IA32_MCG_CTL,
1294 MSR_IA32_MCG_EXT_CTL,
1295 MSR_IA32_SMBASE,
1296 MSR_SMI_COUNT,
1297 MSR_PLATFORM_INFO,
1298 MSR_MISC_FEATURES_ENABLES,
1299 MSR_AMD64_VIRT_SPEC_CTRL,
1300 MSR_IA32_POWER_CTL,
1301 MSR_IA32_UCODE_REV,
1302
1303 /*
1304 * The following list leaves out MSRs whose values are determined
1305 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1306 * We always support the "true" VMX control MSRs, even if the host
1307 * processor does not, so I am putting these registers here rather
1308 * than in msrs_to_save_all.
1309 */
1310 MSR_IA32_VMX_BASIC,
1311 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1312 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1313 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1314 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1315 MSR_IA32_VMX_MISC,
1316 MSR_IA32_VMX_CR0_FIXED0,
1317 MSR_IA32_VMX_CR4_FIXED0,
1318 MSR_IA32_VMX_VMCS_ENUM,
1319 MSR_IA32_VMX_PROCBASED_CTLS2,
1320 MSR_IA32_VMX_EPT_VPID_CAP,
1321 MSR_IA32_VMX_VMFUNC,
1322
1323 MSR_K7_HWCR,
1324 MSR_KVM_POLL_CONTROL,
1325 };
1326
1327 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1328 static unsigned num_emulated_msrs;
1329
1330 /*
1331 * List of msr numbers which are used to expose MSR-based features that
1332 * can be used by a hypervisor to validate requested CPU features.
1333 */
1334 static const u32 msr_based_features_all[] = {
1335 MSR_IA32_VMX_BASIC,
1336 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1337 MSR_IA32_VMX_PINBASED_CTLS,
1338 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1339 MSR_IA32_VMX_PROCBASED_CTLS,
1340 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1341 MSR_IA32_VMX_EXIT_CTLS,
1342 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1343 MSR_IA32_VMX_ENTRY_CTLS,
1344 MSR_IA32_VMX_MISC,
1345 MSR_IA32_VMX_CR0_FIXED0,
1346 MSR_IA32_VMX_CR0_FIXED1,
1347 MSR_IA32_VMX_CR4_FIXED0,
1348 MSR_IA32_VMX_CR4_FIXED1,
1349 MSR_IA32_VMX_VMCS_ENUM,
1350 MSR_IA32_VMX_PROCBASED_CTLS2,
1351 MSR_IA32_VMX_EPT_VPID_CAP,
1352 MSR_IA32_VMX_VMFUNC,
1353
1354 MSR_F10H_DECFG,
1355 MSR_IA32_UCODE_REV,
1356 MSR_IA32_ARCH_CAPABILITIES,
1357 MSR_IA32_PERF_CAPABILITIES,
1358 };
1359
1360 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1361 static unsigned int num_msr_based_features;
1362
1363 static u64 kvm_get_arch_capabilities(void)
1364 {
1365 u64 data = 0;
1366
1367 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1368 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1369
1370 /*
1371 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1372 * the nested hypervisor runs with NX huge pages. If it is not,
1373 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1374 * L1 guests, so it need not worry about its own (L2) guests.
1375 */
1376 data |= ARCH_CAP_PSCHANGE_MC_NO;
1377
1378 /*
1379 * If we're doing cache flushes (either "always" or "cond")
1380 * we will do one whenever the guest does a vmlaunch/vmresume.
1381 * If an outer hypervisor is doing the cache flush for us
1382 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1383 * capability to the guest too, and if EPT is disabled we're not
1384 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1385 * require a nested hypervisor to do a flush of its own.
1386 */
1387 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1388 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1389
1390 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1391 data |= ARCH_CAP_RDCL_NO;
1392 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1393 data |= ARCH_CAP_SSB_NO;
1394 if (!boot_cpu_has_bug(X86_BUG_MDS))
1395 data |= ARCH_CAP_MDS_NO;
1396
1397 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1398 /*
1399 * If RTM=0 because the kernel has disabled TSX, the host might
1400 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1401 * and therefore knows that there cannot be TAA) but keep
1402 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1403 * and we want to allow migrating those guests to tsx=off hosts.
1404 */
1405 data &= ~ARCH_CAP_TAA_NO;
1406 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1407 data |= ARCH_CAP_TAA_NO;
1408 } else {
1409 /*
1410 * Nothing to do here; we emulate TSX_CTRL if present on the
1411 * host so the guest can choose between disabling TSX or
1412 * using VERW to clear CPU buffers.
1413 */
1414 }
1415
1416 return data;
1417 }
1418
1419 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1420 {
1421 switch (msr->index) {
1422 case MSR_IA32_ARCH_CAPABILITIES:
1423 msr->data = kvm_get_arch_capabilities();
1424 break;
1425 case MSR_IA32_UCODE_REV:
1426 rdmsrl_safe(msr->index, &msr->data);
1427 break;
1428 default:
1429 return kvm_x86_ops.get_msr_feature(msr);
1430 }
1431 return 0;
1432 }
1433
1434 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1435 {
1436 struct kvm_msr_entry msr;
1437 int r;
1438
1439 msr.index = index;
1440 r = kvm_get_msr_feature(&msr);
1441
1442 if (r == KVM_MSR_RET_INVALID) {
1443 /* Unconditionally clear the output for simplicity */
1444 *data = 0;
1445 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1446 r = 0;
1447 }
1448
1449 if (r)
1450 return r;
1451
1452 *data = msr.data;
1453
1454 return 0;
1455 }
1456
1457 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1458 {
1459 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1460 return false;
1461
1462 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1463 return false;
1464
1465 if (efer & (EFER_LME | EFER_LMA) &&
1466 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1467 return false;
1468
1469 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1470 return false;
1471
1472 return true;
1473
1474 }
1475 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1476 {
1477 if (efer & efer_reserved_bits)
1478 return false;
1479
1480 return __kvm_valid_efer(vcpu, efer);
1481 }
1482 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1483
1484 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1485 {
1486 u64 old_efer = vcpu->arch.efer;
1487 u64 efer = msr_info->data;
1488 int r;
1489
1490 if (efer & efer_reserved_bits)
1491 return 1;
1492
1493 if (!msr_info->host_initiated) {
1494 if (!__kvm_valid_efer(vcpu, efer))
1495 return 1;
1496
1497 if (is_paging(vcpu) &&
1498 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1499 return 1;
1500 }
1501
1502 efer &= ~EFER_LMA;
1503 efer |= vcpu->arch.efer & EFER_LMA;
1504
1505 r = kvm_x86_ops.set_efer(vcpu, efer);
1506 if (r) {
1507 WARN_ON(r > 0);
1508 return r;
1509 }
1510
1511 /* Update reserved bits */
1512 if ((efer ^ old_efer) & EFER_NX)
1513 kvm_mmu_reset_context(vcpu);
1514
1515 return 0;
1516 }
1517
1518 void kvm_enable_efer_bits(u64 mask)
1519 {
1520 efer_reserved_bits &= ~mask;
1521 }
1522 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1523
1524 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1525 {
1526 struct kvm *kvm = vcpu->kvm;
1527 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
1528 u32 count = kvm->arch.msr_filter.count;
1529 u32 i;
1530 bool r = kvm->arch.msr_filter.default_allow;
1531 int idx;
1532
1533 /* MSR filtering not set up or x2APIC enabled, allow everything */
1534 if (!count || (index >= 0x800 && index <= 0x8ff))
1535 return true;
1536
1537 /* Prevent collision with set_msr_filter */
1538 idx = srcu_read_lock(&kvm->srcu);
1539
1540 for (i = 0; i < count; i++) {
1541 u32 start = ranges[i].base;
1542 u32 end = start + ranges[i].nmsrs;
1543 u32 flags = ranges[i].flags;
1544 unsigned long *bitmap = ranges[i].bitmap;
1545
1546 if ((index >= start) && (index < end) && (flags & type)) {
1547 r = !!test_bit(index - start, bitmap);
1548 break;
1549 }
1550 }
1551
1552 srcu_read_unlock(&kvm->srcu, idx);
1553
1554 return r;
1555 }
1556 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1557
1558 /*
1559 * Write @data into the MSR specified by @index. Select MSR specific fault
1560 * checks are bypassed if @host_initiated is %true.
1561 * Returns 0 on success, non-0 otherwise.
1562 * Assumes vcpu_load() was already called.
1563 */
1564 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1565 bool host_initiated)
1566 {
1567 struct msr_data msr;
1568
1569 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1570 return KVM_MSR_RET_FILTERED;
1571
1572 switch (index) {
1573 case MSR_FS_BASE:
1574 case MSR_GS_BASE:
1575 case MSR_KERNEL_GS_BASE:
1576 case MSR_CSTAR:
1577 case MSR_LSTAR:
1578 if (is_noncanonical_address(data, vcpu))
1579 return 1;
1580 break;
1581 case MSR_IA32_SYSENTER_EIP:
1582 case MSR_IA32_SYSENTER_ESP:
1583 /*
1584 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1585 * non-canonical address is written on Intel but not on
1586 * AMD (which ignores the top 32-bits, because it does
1587 * not implement 64-bit SYSENTER).
1588 *
1589 * 64-bit code should hence be able to write a non-canonical
1590 * value on AMD. Making the address canonical ensures that
1591 * vmentry does not fail on Intel after writing a non-canonical
1592 * value, and that something deterministic happens if the guest
1593 * invokes 64-bit SYSENTER.
1594 */
1595 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1596 }
1597
1598 msr.data = data;
1599 msr.index = index;
1600 msr.host_initiated = host_initiated;
1601
1602 return kvm_x86_ops.set_msr(vcpu, &msr);
1603 }
1604
1605 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1606 u32 index, u64 data, bool host_initiated)
1607 {
1608 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1609
1610 if (ret == KVM_MSR_RET_INVALID)
1611 if (kvm_msr_ignored_check(vcpu, index, data, true))
1612 ret = 0;
1613
1614 return ret;
1615 }
1616
1617 /*
1618 * Read the MSR specified by @index into @data. Select MSR specific fault
1619 * checks are bypassed if @host_initiated is %true.
1620 * Returns 0 on success, non-0 otherwise.
1621 * Assumes vcpu_load() was already called.
1622 */
1623 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1624 bool host_initiated)
1625 {
1626 struct msr_data msr;
1627 int ret;
1628
1629 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1630 return KVM_MSR_RET_FILTERED;
1631
1632 msr.index = index;
1633 msr.host_initiated = host_initiated;
1634
1635 ret = kvm_x86_ops.get_msr(vcpu, &msr);
1636 if (!ret)
1637 *data = msr.data;
1638 return ret;
1639 }
1640
1641 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1642 u32 index, u64 *data, bool host_initiated)
1643 {
1644 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1645
1646 if (ret == KVM_MSR_RET_INVALID) {
1647 /* Unconditionally clear *data for simplicity */
1648 *data = 0;
1649 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1650 ret = 0;
1651 }
1652
1653 return ret;
1654 }
1655
1656 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1657 {
1658 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1659 }
1660 EXPORT_SYMBOL_GPL(kvm_get_msr);
1661
1662 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1663 {
1664 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1665 }
1666 EXPORT_SYMBOL_GPL(kvm_set_msr);
1667
1668 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1669 {
1670 int err = vcpu->run->msr.error;
1671 if (!err) {
1672 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1673 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1674 }
1675
1676 return kvm_x86_ops.complete_emulated_msr(vcpu, err);
1677 }
1678
1679 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1680 {
1681 return kvm_x86_ops.complete_emulated_msr(vcpu, vcpu->run->msr.error);
1682 }
1683
1684 static u64 kvm_msr_reason(int r)
1685 {
1686 switch (r) {
1687 case KVM_MSR_RET_INVALID:
1688 return KVM_MSR_EXIT_REASON_UNKNOWN;
1689 case KVM_MSR_RET_FILTERED:
1690 return KVM_MSR_EXIT_REASON_FILTER;
1691 default:
1692 return KVM_MSR_EXIT_REASON_INVAL;
1693 }
1694 }
1695
1696 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1697 u32 exit_reason, u64 data,
1698 int (*completion)(struct kvm_vcpu *vcpu),
1699 int r)
1700 {
1701 u64 msr_reason = kvm_msr_reason(r);
1702
1703 /* Check if the user wanted to know about this MSR fault */
1704 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1705 return 0;
1706
1707 vcpu->run->exit_reason = exit_reason;
1708 vcpu->run->msr.error = 0;
1709 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1710 vcpu->run->msr.reason = msr_reason;
1711 vcpu->run->msr.index = index;
1712 vcpu->run->msr.data = data;
1713 vcpu->arch.complete_userspace_io = completion;
1714
1715 return 1;
1716 }
1717
1718 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1719 {
1720 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1721 complete_emulated_rdmsr, r);
1722 }
1723
1724 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1725 {
1726 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1727 complete_emulated_wrmsr, r);
1728 }
1729
1730 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1731 {
1732 u32 ecx = kvm_rcx_read(vcpu);
1733 u64 data;
1734 int r;
1735
1736 r = kvm_get_msr(vcpu, ecx, &data);
1737
1738 /* MSR read failed? See if we should ask user space */
1739 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1740 /* Bounce to user space */
1741 return 0;
1742 }
1743
1744 if (!r) {
1745 trace_kvm_msr_read(ecx, data);
1746
1747 kvm_rax_write(vcpu, data & -1u);
1748 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1749 } else {
1750 trace_kvm_msr_read_ex(ecx);
1751 }
1752
1753 return kvm_x86_ops.complete_emulated_msr(vcpu, r);
1754 }
1755 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1756
1757 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1758 {
1759 u32 ecx = kvm_rcx_read(vcpu);
1760 u64 data = kvm_read_edx_eax(vcpu);
1761 int r;
1762
1763 r = kvm_set_msr(vcpu, ecx, data);
1764
1765 /* MSR write failed? See if we should ask user space */
1766 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r))
1767 /* Bounce to user space */
1768 return 0;
1769
1770 /* Signal all other negative errors to userspace */
1771 if (r < 0)
1772 return r;
1773
1774 if (!r)
1775 trace_kvm_msr_write(ecx, data);
1776 else
1777 trace_kvm_msr_write_ex(ecx, data);
1778
1779 return kvm_x86_ops.complete_emulated_msr(vcpu, r);
1780 }
1781 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1782
1783 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1784 {
1785 xfer_to_guest_mode_prepare();
1786 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1787 xfer_to_guest_mode_work_pending();
1788 }
1789 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1790
1791 /*
1792 * The fast path for frequent and performance sensitive wrmsr emulation,
1793 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1794 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1795 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1796 * other cases which must be called after interrupts are enabled on the host.
1797 */
1798 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1799 {
1800 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1801 return 1;
1802
1803 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1804 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1805 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1806 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1807
1808 data &= ~(1 << 12);
1809 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1810 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1811 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1812 trace_kvm_apic_write(APIC_ICR, (u32)data);
1813 return 0;
1814 }
1815
1816 return 1;
1817 }
1818
1819 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1820 {
1821 if (!kvm_can_use_hv_timer(vcpu))
1822 return 1;
1823
1824 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1825 return 0;
1826 }
1827
1828 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1829 {
1830 u32 msr = kvm_rcx_read(vcpu);
1831 u64 data;
1832 fastpath_t ret = EXIT_FASTPATH_NONE;
1833
1834 switch (msr) {
1835 case APIC_BASE_MSR + (APIC_ICR >> 4):
1836 data = kvm_read_edx_eax(vcpu);
1837 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1838 kvm_skip_emulated_instruction(vcpu);
1839 ret = EXIT_FASTPATH_EXIT_HANDLED;
1840 }
1841 break;
1842 case MSR_IA32_TSCDEADLINE:
1843 data = kvm_read_edx_eax(vcpu);
1844 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1845 kvm_skip_emulated_instruction(vcpu);
1846 ret = EXIT_FASTPATH_REENTER_GUEST;
1847 }
1848 break;
1849 default:
1850 break;
1851 }
1852
1853 if (ret != EXIT_FASTPATH_NONE)
1854 trace_kvm_msr_write(msr, data);
1855
1856 return ret;
1857 }
1858 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1859
1860 /*
1861 * Adapt set_msr() to msr_io()'s calling convention
1862 */
1863 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1864 {
1865 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1866 }
1867
1868 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1869 {
1870 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1871 }
1872
1873 #ifdef CONFIG_X86_64
1874 struct pvclock_clock {
1875 int vclock_mode;
1876 u64 cycle_last;
1877 u64 mask;
1878 u32 mult;
1879 u32 shift;
1880 u64 base_cycles;
1881 u64 offset;
1882 };
1883
1884 struct pvclock_gtod_data {
1885 seqcount_t seq;
1886
1887 struct pvclock_clock clock; /* extract of a clocksource struct */
1888 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1889
1890 ktime_t offs_boot;
1891 u64 wall_time_sec;
1892 };
1893
1894 static struct pvclock_gtod_data pvclock_gtod_data;
1895
1896 static void update_pvclock_gtod(struct timekeeper *tk)
1897 {
1898 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1899
1900 write_seqcount_begin(&vdata->seq);
1901
1902 /* copy pvclock gtod data */
1903 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1904 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1905 vdata->clock.mask = tk->tkr_mono.mask;
1906 vdata->clock.mult = tk->tkr_mono.mult;
1907 vdata->clock.shift = tk->tkr_mono.shift;
1908 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1909 vdata->clock.offset = tk->tkr_mono.base;
1910
1911 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1912 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1913 vdata->raw_clock.mask = tk->tkr_raw.mask;
1914 vdata->raw_clock.mult = tk->tkr_raw.mult;
1915 vdata->raw_clock.shift = tk->tkr_raw.shift;
1916 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1917 vdata->raw_clock.offset = tk->tkr_raw.base;
1918
1919 vdata->wall_time_sec = tk->xtime_sec;
1920
1921 vdata->offs_boot = tk->offs_boot;
1922
1923 write_seqcount_end(&vdata->seq);
1924 }
1925
1926 static s64 get_kvmclock_base_ns(void)
1927 {
1928 /* Count up from boot time, but with the frequency of the raw clock. */
1929 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1930 }
1931 #else
1932 static s64 get_kvmclock_base_ns(void)
1933 {
1934 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1935 return ktime_get_boottime_ns();
1936 }
1937 #endif
1938
1939 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1940 {
1941 int version;
1942 int r;
1943 struct pvclock_wall_clock wc;
1944 u64 wall_nsec;
1945
1946 kvm->arch.wall_clock = wall_clock;
1947
1948 if (!wall_clock)
1949 return;
1950
1951 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1952 if (r)
1953 return;
1954
1955 if (version & 1)
1956 ++version; /* first time write, random junk */
1957
1958 ++version;
1959
1960 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1961 return;
1962
1963 /*
1964 * The guest calculates current wall clock time by adding
1965 * system time (updated by kvm_guest_time_update below) to the
1966 * wall clock specified here. We do the reverse here.
1967 */
1968 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1969
1970 wc.nsec = do_div(wall_nsec, 1000000000);
1971 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1972 wc.version = version;
1973
1974 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1975
1976 version++;
1977 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1978 }
1979
1980 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1981 bool old_msr, bool host_initiated)
1982 {
1983 struct kvm_arch *ka = &vcpu->kvm->arch;
1984
1985 if (vcpu->vcpu_id == 0 && !host_initiated) {
1986 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
1987 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1988
1989 ka->boot_vcpu_runs_old_kvmclock = old_msr;
1990 }
1991
1992 vcpu->arch.time = system_time;
1993 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
1994
1995 /* we verify if the enable bit is set... */
1996 vcpu->arch.pv_time_enabled = false;
1997 if (!(system_time & 1))
1998 return;
1999
2000 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2001 &vcpu->arch.pv_time, system_time & ~1ULL,
2002 sizeof(struct pvclock_vcpu_time_info)))
2003 vcpu->arch.pv_time_enabled = true;
2004
2005 return;
2006 }
2007
2008 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2009 {
2010 do_shl32_div32(dividend, divisor);
2011 return dividend;
2012 }
2013
2014 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2015 s8 *pshift, u32 *pmultiplier)
2016 {
2017 uint64_t scaled64;
2018 int32_t shift = 0;
2019 uint64_t tps64;
2020 uint32_t tps32;
2021
2022 tps64 = base_hz;
2023 scaled64 = scaled_hz;
2024 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2025 tps64 >>= 1;
2026 shift--;
2027 }
2028
2029 tps32 = (uint32_t)tps64;
2030 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2031 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2032 scaled64 >>= 1;
2033 else
2034 tps32 <<= 1;
2035 shift++;
2036 }
2037
2038 *pshift = shift;
2039 *pmultiplier = div_frac(scaled64, tps32);
2040 }
2041
2042 #ifdef CONFIG_X86_64
2043 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2044 #endif
2045
2046 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2047 static unsigned long max_tsc_khz;
2048
2049 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2050 {
2051 u64 v = (u64)khz * (1000000 + ppm);
2052 do_div(v, 1000000);
2053 return v;
2054 }
2055
2056 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2057 {
2058 u64 ratio;
2059
2060 /* Guest TSC same frequency as host TSC? */
2061 if (!scale) {
2062 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2063 return 0;
2064 }
2065
2066 /* TSC scaling supported? */
2067 if (!kvm_has_tsc_control) {
2068 if (user_tsc_khz > tsc_khz) {
2069 vcpu->arch.tsc_catchup = 1;
2070 vcpu->arch.tsc_always_catchup = 1;
2071 return 0;
2072 } else {
2073 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2074 return -1;
2075 }
2076 }
2077
2078 /* TSC scaling required - calculate ratio */
2079 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2080 user_tsc_khz, tsc_khz);
2081
2082 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2083 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2084 user_tsc_khz);
2085 return -1;
2086 }
2087
2088 vcpu->arch.tsc_scaling_ratio = ratio;
2089 return 0;
2090 }
2091
2092 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2093 {
2094 u32 thresh_lo, thresh_hi;
2095 int use_scaling = 0;
2096
2097 /* tsc_khz can be zero if TSC calibration fails */
2098 if (user_tsc_khz == 0) {
2099 /* set tsc_scaling_ratio to a safe value */
2100 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2101 return -1;
2102 }
2103
2104 /* Compute a scale to convert nanoseconds in TSC cycles */
2105 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2106 &vcpu->arch.virtual_tsc_shift,
2107 &vcpu->arch.virtual_tsc_mult);
2108 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2109
2110 /*
2111 * Compute the variation in TSC rate which is acceptable
2112 * within the range of tolerance and decide if the
2113 * rate being applied is within that bounds of the hardware
2114 * rate. If so, no scaling or compensation need be done.
2115 */
2116 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2117 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2118 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2119 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2120 use_scaling = 1;
2121 }
2122 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2123 }
2124
2125 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2126 {
2127 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2128 vcpu->arch.virtual_tsc_mult,
2129 vcpu->arch.virtual_tsc_shift);
2130 tsc += vcpu->arch.this_tsc_write;
2131 return tsc;
2132 }
2133
2134 static inline int gtod_is_based_on_tsc(int mode)
2135 {
2136 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2137 }
2138
2139 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2140 {
2141 #ifdef CONFIG_X86_64
2142 bool vcpus_matched;
2143 struct kvm_arch *ka = &vcpu->kvm->arch;
2144 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2145
2146 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2147 atomic_read(&vcpu->kvm->online_vcpus));
2148
2149 /*
2150 * Once the masterclock is enabled, always perform request in
2151 * order to update it.
2152 *
2153 * In order to enable masterclock, the host clocksource must be TSC
2154 * and the vcpus need to have matched TSCs. When that happens,
2155 * perform request to enable masterclock.
2156 */
2157 if (ka->use_master_clock ||
2158 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2159 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2160
2161 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2162 atomic_read(&vcpu->kvm->online_vcpus),
2163 ka->use_master_clock, gtod->clock.vclock_mode);
2164 #endif
2165 }
2166
2167 /*
2168 * Multiply tsc by a fixed point number represented by ratio.
2169 *
2170 * The most significant 64-N bits (mult) of ratio represent the
2171 * integral part of the fixed point number; the remaining N bits
2172 * (frac) represent the fractional part, ie. ratio represents a fixed
2173 * point number (mult + frac * 2^(-N)).
2174 *
2175 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2176 */
2177 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2178 {
2179 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2180 }
2181
2182 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2183 {
2184 u64 _tsc = tsc;
2185 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2186
2187 if (ratio != kvm_default_tsc_scaling_ratio)
2188 _tsc = __scale_tsc(ratio, tsc);
2189
2190 return _tsc;
2191 }
2192 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2193
2194 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2195 {
2196 u64 tsc;
2197
2198 tsc = kvm_scale_tsc(vcpu, rdtsc());
2199
2200 return target_tsc - tsc;
2201 }
2202
2203 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2204 {
2205 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2206 }
2207 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2208
2209 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2210 {
2211 vcpu->arch.l1_tsc_offset = offset;
2212 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2213 }
2214
2215 static inline bool kvm_check_tsc_unstable(void)
2216 {
2217 #ifdef CONFIG_X86_64
2218 /*
2219 * TSC is marked unstable when we're running on Hyper-V,
2220 * 'TSC page' clocksource is good.
2221 */
2222 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2223 return false;
2224 #endif
2225 return check_tsc_unstable();
2226 }
2227
2228 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2229 {
2230 struct kvm *kvm = vcpu->kvm;
2231 u64 offset, ns, elapsed;
2232 unsigned long flags;
2233 bool matched;
2234 bool already_matched;
2235 bool synchronizing = false;
2236
2237 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2238 offset = kvm_compute_tsc_offset(vcpu, data);
2239 ns = get_kvmclock_base_ns();
2240 elapsed = ns - kvm->arch.last_tsc_nsec;
2241
2242 if (vcpu->arch.virtual_tsc_khz) {
2243 if (data == 0) {
2244 /*
2245 * detection of vcpu initialization -- need to sync
2246 * with other vCPUs. This particularly helps to keep
2247 * kvm_clock stable after CPU hotplug
2248 */
2249 synchronizing = true;
2250 } else {
2251 u64 tsc_exp = kvm->arch.last_tsc_write +
2252 nsec_to_cycles(vcpu, elapsed);
2253 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2254 /*
2255 * Special case: TSC write with a small delta (1 second)
2256 * of virtual cycle time against real time is
2257 * interpreted as an attempt to synchronize the CPU.
2258 */
2259 synchronizing = data < tsc_exp + tsc_hz &&
2260 data + tsc_hz > tsc_exp;
2261 }
2262 }
2263
2264 /*
2265 * For a reliable TSC, we can match TSC offsets, and for an unstable
2266 * TSC, we add elapsed time in this computation. We could let the
2267 * compensation code attempt to catch up if we fall behind, but
2268 * it's better to try to match offsets from the beginning.
2269 */
2270 if (synchronizing &&
2271 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2272 if (!kvm_check_tsc_unstable()) {
2273 offset = kvm->arch.cur_tsc_offset;
2274 } else {
2275 u64 delta = nsec_to_cycles(vcpu, elapsed);
2276 data += delta;
2277 offset = kvm_compute_tsc_offset(vcpu, data);
2278 }
2279 matched = true;
2280 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2281 } else {
2282 /*
2283 * We split periods of matched TSC writes into generations.
2284 * For each generation, we track the original measured
2285 * nanosecond time, offset, and write, so if TSCs are in
2286 * sync, we can match exact offset, and if not, we can match
2287 * exact software computation in compute_guest_tsc()
2288 *
2289 * These values are tracked in kvm->arch.cur_xxx variables.
2290 */
2291 kvm->arch.cur_tsc_generation++;
2292 kvm->arch.cur_tsc_nsec = ns;
2293 kvm->arch.cur_tsc_write = data;
2294 kvm->arch.cur_tsc_offset = offset;
2295 matched = false;
2296 }
2297
2298 /*
2299 * We also track th most recent recorded KHZ, write and time to
2300 * allow the matching interval to be extended at each write.
2301 */
2302 kvm->arch.last_tsc_nsec = ns;
2303 kvm->arch.last_tsc_write = data;
2304 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2305
2306 vcpu->arch.last_guest_tsc = data;
2307
2308 /* Keep track of which generation this VCPU has synchronized to */
2309 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2310 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2311 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2312
2313 kvm_vcpu_write_tsc_offset(vcpu, offset);
2314 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2315
2316 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2317 if (!matched) {
2318 kvm->arch.nr_vcpus_matched_tsc = 0;
2319 } else if (!already_matched) {
2320 kvm->arch.nr_vcpus_matched_tsc++;
2321 }
2322
2323 kvm_track_tsc_matching(vcpu);
2324 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2325 }
2326
2327 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2328 s64 adjustment)
2329 {
2330 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2331 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2332 }
2333
2334 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2335 {
2336 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2337 WARN_ON(adjustment < 0);
2338 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2339 adjust_tsc_offset_guest(vcpu, adjustment);
2340 }
2341
2342 #ifdef CONFIG_X86_64
2343
2344 static u64 read_tsc(void)
2345 {
2346 u64 ret = (u64)rdtsc_ordered();
2347 u64 last = pvclock_gtod_data.clock.cycle_last;
2348
2349 if (likely(ret >= last))
2350 return ret;
2351
2352 /*
2353 * GCC likes to generate cmov here, but this branch is extremely
2354 * predictable (it's just a function of time and the likely is
2355 * very likely) and there's a data dependence, so force GCC
2356 * to generate a branch instead. I don't barrier() because
2357 * we don't actually need a barrier, and if this function
2358 * ever gets inlined it will generate worse code.
2359 */
2360 asm volatile ("");
2361 return last;
2362 }
2363
2364 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2365 int *mode)
2366 {
2367 long v;
2368 u64 tsc_pg_val;
2369
2370 switch (clock->vclock_mode) {
2371 case VDSO_CLOCKMODE_HVCLOCK:
2372 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2373 tsc_timestamp);
2374 if (tsc_pg_val != U64_MAX) {
2375 /* TSC page valid */
2376 *mode = VDSO_CLOCKMODE_HVCLOCK;
2377 v = (tsc_pg_val - clock->cycle_last) &
2378 clock->mask;
2379 } else {
2380 /* TSC page invalid */
2381 *mode = VDSO_CLOCKMODE_NONE;
2382 }
2383 break;
2384 case VDSO_CLOCKMODE_TSC:
2385 *mode = VDSO_CLOCKMODE_TSC;
2386 *tsc_timestamp = read_tsc();
2387 v = (*tsc_timestamp - clock->cycle_last) &
2388 clock->mask;
2389 break;
2390 default:
2391 *mode = VDSO_CLOCKMODE_NONE;
2392 }
2393
2394 if (*mode == VDSO_CLOCKMODE_NONE)
2395 *tsc_timestamp = v = 0;
2396
2397 return v * clock->mult;
2398 }
2399
2400 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2401 {
2402 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2403 unsigned long seq;
2404 int mode;
2405 u64 ns;
2406
2407 do {
2408 seq = read_seqcount_begin(&gtod->seq);
2409 ns = gtod->raw_clock.base_cycles;
2410 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2411 ns >>= gtod->raw_clock.shift;
2412 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2413 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2414 *t = ns;
2415
2416 return mode;
2417 }
2418
2419 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2420 {
2421 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2422 unsigned long seq;
2423 int mode;
2424 u64 ns;
2425
2426 do {
2427 seq = read_seqcount_begin(&gtod->seq);
2428 ts->tv_sec = gtod->wall_time_sec;
2429 ns = gtod->clock.base_cycles;
2430 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2431 ns >>= gtod->clock.shift;
2432 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2433
2434 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2435 ts->tv_nsec = ns;
2436
2437 return mode;
2438 }
2439
2440 /* returns true if host is using TSC based clocksource */
2441 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2442 {
2443 /* checked again under seqlock below */
2444 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2445 return false;
2446
2447 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2448 tsc_timestamp));
2449 }
2450
2451 /* returns true if host is using TSC based clocksource */
2452 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2453 u64 *tsc_timestamp)
2454 {
2455 /* checked again under seqlock below */
2456 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2457 return false;
2458
2459 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2460 }
2461 #endif
2462
2463 /*
2464 *
2465 * Assuming a stable TSC across physical CPUS, and a stable TSC
2466 * across virtual CPUs, the following condition is possible.
2467 * Each numbered line represents an event visible to both
2468 * CPUs at the next numbered event.
2469 *
2470 * "timespecX" represents host monotonic time. "tscX" represents
2471 * RDTSC value.
2472 *
2473 * VCPU0 on CPU0 | VCPU1 on CPU1
2474 *
2475 * 1. read timespec0,tsc0
2476 * 2. | timespec1 = timespec0 + N
2477 * | tsc1 = tsc0 + M
2478 * 3. transition to guest | transition to guest
2479 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2480 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2481 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2482 *
2483 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2484 *
2485 * - ret0 < ret1
2486 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2487 * ...
2488 * - 0 < N - M => M < N
2489 *
2490 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2491 * always the case (the difference between two distinct xtime instances
2492 * might be smaller then the difference between corresponding TSC reads,
2493 * when updating guest vcpus pvclock areas).
2494 *
2495 * To avoid that problem, do not allow visibility of distinct
2496 * system_timestamp/tsc_timestamp values simultaneously: use a master
2497 * copy of host monotonic time values. Update that master copy
2498 * in lockstep.
2499 *
2500 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2501 *
2502 */
2503
2504 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2505 {
2506 #ifdef CONFIG_X86_64
2507 struct kvm_arch *ka = &kvm->arch;
2508 int vclock_mode;
2509 bool host_tsc_clocksource, vcpus_matched;
2510
2511 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2512 atomic_read(&kvm->online_vcpus));
2513
2514 /*
2515 * If the host uses TSC clock, then passthrough TSC as stable
2516 * to the guest.
2517 */
2518 host_tsc_clocksource = kvm_get_time_and_clockread(
2519 &ka->master_kernel_ns,
2520 &ka->master_cycle_now);
2521
2522 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2523 && !ka->backwards_tsc_observed
2524 && !ka->boot_vcpu_runs_old_kvmclock;
2525
2526 if (ka->use_master_clock)
2527 atomic_set(&kvm_guest_has_master_clock, 1);
2528
2529 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2530 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2531 vcpus_matched);
2532 #endif
2533 }
2534
2535 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2536 {
2537 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2538 }
2539
2540 static void kvm_gen_update_masterclock(struct kvm *kvm)
2541 {
2542 #ifdef CONFIG_X86_64
2543 int i;
2544 struct kvm_vcpu *vcpu;
2545 struct kvm_arch *ka = &kvm->arch;
2546
2547 spin_lock(&ka->pvclock_gtod_sync_lock);
2548 kvm_make_mclock_inprogress_request(kvm);
2549 /* no guest entries from this point */
2550 pvclock_update_vm_gtod_copy(kvm);
2551
2552 kvm_for_each_vcpu(i, vcpu, kvm)
2553 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2554
2555 /* guest entries allowed */
2556 kvm_for_each_vcpu(i, vcpu, kvm)
2557 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2558
2559 spin_unlock(&ka->pvclock_gtod_sync_lock);
2560 #endif
2561 }
2562
2563 u64 get_kvmclock_ns(struct kvm *kvm)
2564 {
2565 struct kvm_arch *ka = &kvm->arch;
2566 struct pvclock_vcpu_time_info hv_clock;
2567 u64 ret;
2568
2569 spin_lock(&ka->pvclock_gtod_sync_lock);
2570 if (!ka->use_master_clock) {
2571 spin_unlock(&ka->pvclock_gtod_sync_lock);
2572 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2573 }
2574
2575 hv_clock.tsc_timestamp = ka->master_cycle_now;
2576 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2577 spin_unlock(&ka->pvclock_gtod_sync_lock);
2578
2579 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2580 get_cpu();
2581
2582 if (__this_cpu_read(cpu_tsc_khz)) {
2583 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2584 &hv_clock.tsc_shift,
2585 &hv_clock.tsc_to_system_mul);
2586 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2587 } else
2588 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2589
2590 put_cpu();
2591
2592 return ret;
2593 }
2594
2595 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2596 {
2597 struct kvm_vcpu_arch *vcpu = &v->arch;
2598 struct pvclock_vcpu_time_info guest_hv_clock;
2599
2600 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2601 &guest_hv_clock, sizeof(guest_hv_clock))))
2602 return;
2603
2604 /* This VCPU is paused, but it's legal for a guest to read another
2605 * VCPU's kvmclock, so we really have to follow the specification where
2606 * it says that version is odd if data is being modified, and even after
2607 * it is consistent.
2608 *
2609 * Version field updates must be kept separate. This is because
2610 * kvm_write_guest_cached might use a "rep movs" instruction, and
2611 * writes within a string instruction are weakly ordered. So there
2612 * are three writes overall.
2613 *
2614 * As a small optimization, only write the version field in the first
2615 * and third write. The vcpu->pv_time cache is still valid, because the
2616 * version field is the first in the struct.
2617 */
2618 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2619
2620 if (guest_hv_clock.version & 1)
2621 ++guest_hv_clock.version; /* first time write, random junk */
2622
2623 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2624 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2625 &vcpu->hv_clock,
2626 sizeof(vcpu->hv_clock.version));
2627
2628 smp_wmb();
2629
2630 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2631 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2632
2633 if (vcpu->pvclock_set_guest_stopped_request) {
2634 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2635 vcpu->pvclock_set_guest_stopped_request = false;
2636 }
2637
2638 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2639
2640 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2641 &vcpu->hv_clock,
2642 sizeof(vcpu->hv_clock));
2643
2644 smp_wmb();
2645
2646 vcpu->hv_clock.version++;
2647 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2648 &vcpu->hv_clock,
2649 sizeof(vcpu->hv_clock.version));
2650 }
2651
2652 static int kvm_guest_time_update(struct kvm_vcpu *v)
2653 {
2654 unsigned long flags, tgt_tsc_khz;
2655 struct kvm_vcpu_arch *vcpu = &v->arch;
2656 struct kvm_arch *ka = &v->kvm->arch;
2657 s64 kernel_ns;
2658 u64 tsc_timestamp, host_tsc;
2659 u8 pvclock_flags;
2660 bool use_master_clock;
2661
2662 kernel_ns = 0;
2663 host_tsc = 0;
2664
2665 /*
2666 * If the host uses TSC clock, then passthrough TSC as stable
2667 * to the guest.
2668 */
2669 spin_lock(&ka->pvclock_gtod_sync_lock);
2670 use_master_clock = ka->use_master_clock;
2671 if (use_master_clock) {
2672 host_tsc = ka->master_cycle_now;
2673 kernel_ns = ka->master_kernel_ns;
2674 }
2675 spin_unlock(&ka->pvclock_gtod_sync_lock);
2676
2677 /* Keep irq disabled to prevent changes to the clock */
2678 local_irq_save(flags);
2679 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2680 if (unlikely(tgt_tsc_khz == 0)) {
2681 local_irq_restore(flags);
2682 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2683 return 1;
2684 }
2685 if (!use_master_clock) {
2686 host_tsc = rdtsc();
2687 kernel_ns = get_kvmclock_base_ns();
2688 }
2689
2690 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2691
2692 /*
2693 * We may have to catch up the TSC to match elapsed wall clock
2694 * time for two reasons, even if kvmclock is used.
2695 * 1) CPU could have been running below the maximum TSC rate
2696 * 2) Broken TSC compensation resets the base at each VCPU
2697 * entry to avoid unknown leaps of TSC even when running
2698 * again on the same CPU. This may cause apparent elapsed
2699 * time to disappear, and the guest to stand still or run
2700 * very slowly.
2701 */
2702 if (vcpu->tsc_catchup) {
2703 u64 tsc = compute_guest_tsc(v, kernel_ns);
2704 if (tsc > tsc_timestamp) {
2705 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2706 tsc_timestamp = tsc;
2707 }
2708 }
2709
2710 local_irq_restore(flags);
2711
2712 /* With all the info we got, fill in the values */
2713
2714 if (kvm_has_tsc_control)
2715 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2716
2717 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2718 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2719 &vcpu->hv_clock.tsc_shift,
2720 &vcpu->hv_clock.tsc_to_system_mul);
2721 vcpu->hw_tsc_khz = tgt_tsc_khz;
2722 }
2723
2724 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2725 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2726 vcpu->last_guest_tsc = tsc_timestamp;
2727
2728 /* If the host uses TSC clocksource, then it is stable */
2729 pvclock_flags = 0;
2730 if (use_master_clock)
2731 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2732
2733 vcpu->hv_clock.flags = pvclock_flags;
2734
2735 if (vcpu->pv_time_enabled)
2736 kvm_setup_pvclock_page(v);
2737 if (v == kvm_get_vcpu(v->kvm, 0))
2738 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2739 return 0;
2740 }
2741
2742 /*
2743 * kvmclock updates which are isolated to a given vcpu, such as
2744 * vcpu->cpu migration, should not allow system_timestamp from
2745 * the rest of the vcpus to remain static. Otherwise ntp frequency
2746 * correction applies to one vcpu's system_timestamp but not
2747 * the others.
2748 *
2749 * So in those cases, request a kvmclock update for all vcpus.
2750 * We need to rate-limit these requests though, as they can
2751 * considerably slow guests that have a large number of vcpus.
2752 * The time for a remote vcpu to update its kvmclock is bound
2753 * by the delay we use to rate-limit the updates.
2754 */
2755
2756 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2757
2758 static void kvmclock_update_fn(struct work_struct *work)
2759 {
2760 int i;
2761 struct delayed_work *dwork = to_delayed_work(work);
2762 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2763 kvmclock_update_work);
2764 struct kvm *kvm = container_of(ka, struct kvm, arch);
2765 struct kvm_vcpu *vcpu;
2766
2767 kvm_for_each_vcpu(i, vcpu, kvm) {
2768 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2769 kvm_vcpu_kick(vcpu);
2770 }
2771 }
2772
2773 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2774 {
2775 struct kvm *kvm = v->kvm;
2776
2777 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2778 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2779 KVMCLOCK_UPDATE_DELAY);
2780 }
2781
2782 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2783
2784 static void kvmclock_sync_fn(struct work_struct *work)
2785 {
2786 struct delayed_work *dwork = to_delayed_work(work);
2787 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2788 kvmclock_sync_work);
2789 struct kvm *kvm = container_of(ka, struct kvm, arch);
2790
2791 if (!kvmclock_periodic_sync)
2792 return;
2793
2794 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2795 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2796 KVMCLOCK_SYNC_PERIOD);
2797 }
2798
2799 /*
2800 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2801 */
2802 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2803 {
2804 /* McStatusWrEn enabled? */
2805 if (guest_cpuid_is_amd_or_hygon(vcpu))
2806 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2807
2808 return false;
2809 }
2810
2811 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2812 {
2813 u64 mcg_cap = vcpu->arch.mcg_cap;
2814 unsigned bank_num = mcg_cap & 0xff;
2815 u32 msr = msr_info->index;
2816 u64 data = msr_info->data;
2817
2818 switch (msr) {
2819 case MSR_IA32_MCG_STATUS:
2820 vcpu->arch.mcg_status = data;
2821 break;
2822 case MSR_IA32_MCG_CTL:
2823 if (!(mcg_cap & MCG_CTL_P) &&
2824 (data || !msr_info->host_initiated))
2825 return 1;
2826 if (data != 0 && data != ~(u64)0)
2827 return 1;
2828 vcpu->arch.mcg_ctl = data;
2829 break;
2830 default:
2831 if (msr >= MSR_IA32_MC0_CTL &&
2832 msr < MSR_IA32_MCx_CTL(bank_num)) {
2833 u32 offset = array_index_nospec(
2834 msr - MSR_IA32_MC0_CTL,
2835 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2836
2837 /* only 0 or all 1s can be written to IA32_MCi_CTL
2838 * some Linux kernels though clear bit 10 in bank 4 to
2839 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2840 * this to avoid an uncatched #GP in the guest
2841 */
2842 if ((offset & 0x3) == 0 &&
2843 data != 0 && (data | (1 << 10)) != ~(u64)0)
2844 return -1;
2845
2846 /* MCi_STATUS */
2847 if (!msr_info->host_initiated &&
2848 (offset & 0x3) == 1 && data != 0) {
2849 if (!can_set_mci_status(vcpu))
2850 return -1;
2851 }
2852
2853 vcpu->arch.mce_banks[offset] = data;
2854 break;
2855 }
2856 return 1;
2857 }
2858 return 0;
2859 }
2860
2861 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2862 {
2863 struct kvm *kvm = vcpu->kvm;
2864 int lm = is_long_mode(vcpu);
2865 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2866 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2867 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2868 : kvm->arch.xen_hvm_config.blob_size_32;
2869 u32 page_num = data & ~PAGE_MASK;
2870 u64 page_addr = data & PAGE_MASK;
2871 u8 *page;
2872
2873 if (page_num >= blob_size)
2874 return 1;
2875
2876 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2877 if (IS_ERR(page))
2878 return PTR_ERR(page);
2879
2880 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) {
2881 kfree(page);
2882 return 1;
2883 }
2884 return 0;
2885 }
2886
2887 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2888 {
2889 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2890
2891 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2892 }
2893
2894 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2895 {
2896 gpa_t gpa = data & ~0x3f;
2897
2898 /* Bits 4:5 are reserved, Should be zero */
2899 if (data & 0x30)
2900 return 1;
2901
2902 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
2903 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
2904 return 1;
2905
2906 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
2907 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
2908 return 1;
2909
2910 if (!lapic_in_kernel(vcpu))
2911 return data ? 1 : 0;
2912
2913 vcpu->arch.apf.msr_en_val = data;
2914
2915 if (!kvm_pv_async_pf_enabled(vcpu)) {
2916 kvm_clear_async_pf_completion_queue(vcpu);
2917 kvm_async_pf_hash_reset(vcpu);
2918 return 0;
2919 }
2920
2921 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2922 sizeof(u64)))
2923 return 1;
2924
2925 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2926 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2927
2928 kvm_async_pf_wakeup_all(vcpu);
2929
2930 return 0;
2931 }
2932
2933 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2934 {
2935 /* Bits 8-63 are reserved */
2936 if (data >> 8)
2937 return 1;
2938
2939 if (!lapic_in_kernel(vcpu))
2940 return 1;
2941
2942 vcpu->arch.apf.msr_int_val = data;
2943
2944 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2945
2946 return 0;
2947 }
2948
2949 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2950 {
2951 vcpu->arch.pv_time_enabled = false;
2952 vcpu->arch.time = 0;
2953 }
2954
2955 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2956 {
2957 ++vcpu->stat.tlb_flush;
2958 kvm_x86_ops.tlb_flush_all(vcpu);
2959 }
2960
2961 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2962 {
2963 ++vcpu->stat.tlb_flush;
2964 kvm_x86_ops.tlb_flush_guest(vcpu);
2965 }
2966
2967 static void record_steal_time(struct kvm_vcpu *vcpu)
2968 {
2969 struct kvm_host_map map;
2970 struct kvm_steal_time *st;
2971
2972 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2973 return;
2974
2975 /* -EAGAIN is returned in atomic context so we can just return. */
2976 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2977 &map, &vcpu->arch.st.cache, false))
2978 return;
2979
2980 st = map.hva +
2981 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2982
2983 /*
2984 * Doing a TLB flush here, on the guest's behalf, can avoid
2985 * expensive IPIs.
2986 */
2987 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
2988 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2989 st->preempted & KVM_VCPU_FLUSH_TLB);
2990 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2991 kvm_vcpu_flush_tlb_guest(vcpu);
2992 }
2993
2994 vcpu->arch.st.preempted = 0;
2995
2996 if (st->version & 1)
2997 st->version += 1; /* first time write, random junk */
2998
2999 st->version += 1;
3000
3001 smp_wmb();
3002
3003 st->steal += current->sched_info.run_delay -
3004 vcpu->arch.st.last_steal;
3005 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3006
3007 smp_wmb();
3008
3009 st->version += 1;
3010
3011 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
3012 }
3013
3014 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3015 {
3016 bool pr = false;
3017 u32 msr = msr_info->index;
3018 u64 data = msr_info->data;
3019
3020 switch (msr) {
3021 case MSR_AMD64_NB_CFG:
3022 case MSR_IA32_UCODE_WRITE:
3023 case MSR_VM_HSAVE_PA:
3024 case MSR_AMD64_PATCH_LOADER:
3025 case MSR_AMD64_BU_CFG2:
3026 case MSR_AMD64_DC_CFG:
3027 case MSR_F15H_EX_CFG:
3028 break;
3029
3030 case MSR_IA32_UCODE_REV:
3031 if (msr_info->host_initiated)
3032 vcpu->arch.microcode_version = data;
3033 break;
3034 case MSR_IA32_ARCH_CAPABILITIES:
3035 if (!msr_info->host_initiated)
3036 return 1;
3037 vcpu->arch.arch_capabilities = data;
3038 break;
3039 case MSR_IA32_PERF_CAPABILITIES: {
3040 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3041
3042 if (!msr_info->host_initiated)
3043 return 1;
3044 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3045 return 1;
3046 if (data & ~msr_ent.data)
3047 return 1;
3048
3049 vcpu->arch.perf_capabilities = data;
3050
3051 return 0;
3052 }
3053 case MSR_EFER:
3054 return set_efer(vcpu, msr_info);
3055 case MSR_K7_HWCR:
3056 data &= ~(u64)0x40; /* ignore flush filter disable */
3057 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3058 data &= ~(u64)0x8; /* ignore TLB cache disable */
3059
3060 /* Handle McStatusWrEn */
3061 if (data == BIT_ULL(18)) {
3062 vcpu->arch.msr_hwcr = data;
3063 } else if (data != 0) {
3064 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3065 data);
3066 return 1;
3067 }
3068 break;
3069 case MSR_FAM10H_MMIO_CONF_BASE:
3070 if (data != 0) {
3071 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3072 "0x%llx\n", data);
3073 return 1;
3074 }
3075 break;
3076 case MSR_IA32_DEBUGCTLMSR:
3077 if (!data) {
3078 /* We support the non-activated case already */
3079 break;
3080 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
3081 /* Values other than LBR and BTF are vendor-specific,
3082 thus reserved and should throw a #GP */
3083 return 1;
3084 } else if (report_ignored_msrs)
3085 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
3086 __func__, data);
3087 break;
3088 case 0x200 ... 0x2ff:
3089 return kvm_mtrr_set_msr(vcpu, msr, data);
3090 case MSR_IA32_APICBASE:
3091 return kvm_set_apic_base(vcpu, msr_info);
3092 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3093 return kvm_x2apic_msr_write(vcpu, msr, data);
3094 case MSR_IA32_TSCDEADLINE:
3095 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3096 break;
3097 case MSR_IA32_TSC_ADJUST:
3098 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3099 if (!msr_info->host_initiated) {
3100 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3101 adjust_tsc_offset_guest(vcpu, adj);
3102 }
3103 vcpu->arch.ia32_tsc_adjust_msr = data;
3104 }
3105 break;
3106 case MSR_IA32_MISC_ENABLE:
3107 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3108 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3109 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3110 return 1;
3111 vcpu->arch.ia32_misc_enable_msr = data;
3112 kvm_update_cpuid_runtime(vcpu);
3113 } else {
3114 vcpu->arch.ia32_misc_enable_msr = data;
3115 }
3116 break;
3117 case MSR_IA32_SMBASE:
3118 if (!msr_info->host_initiated)
3119 return 1;
3120 vcpu->arch.smbase = data;
3121 break;
3122 case MSR_IA32_POWER_CTL:
3123 vcpu->arch.msr_ia32_power_ctl = data;
3124 break;
3125 case MSR_IA32_TSC:
3126 if (msr_info->host_initiated) {
3127 kvm_synchronize_tsc(vcpu, data);
3128 } else {
3129 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3130 adjust_tsc_offset_guest(vcpu, adj);
3131 vcpu->arch.ia32_tsc_adjust_msr += adj;
3132 }
3133 break;
3134 case MSR_IA32_XSS:
3135 if (!msr_info->host_initiated &&
3136 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3137 return 1;
3138 /*
3139 * KVM supports exposing PT to the guest, but does not support
3140 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3141 * XSAVES/XRSTORS to save/restore PT MSRs.
3142 */
3143 if (data & ~supported_xss)
3144 return 1;
3145 vcpu->arch.ia32_xss = data;
3146 break;
3147 case MSR_SMI_COUNT:
3148 if (!msr_info->host_initiated)
3149 return 1;
3150 vcpu->arch.smi_count = data;
3151 break;
3152 case MSR_KVM_WALL_CLOCK_NEW:
3153 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3154 return 1;
3155
3156 kvm_write_wall_clock(vcpu->kvm, data);
3157 break;
3158 case MSR_KVM_WALL_CLOCK:
3159 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3160 return 1;
3161
3162 kvm_write_wall_clock(vcpu->kvm, data);
3163 break;
3164 case MSR_KVM_SYSTEM_TIME_NEW:
3165 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3166 return 1;
3167
3168 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3169 break;
3170 case MSR_KVM_SYSTEM_TIME:
3171 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3172 return 1;
3173
3174 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3175 break;
3176 case MSR_KVM_ASYNC_PF_EN:
3177 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3178 return 1;
3179
3180 if (kvm_pv_enable_async_pf(vcpu, data))
3181 return 1;
3182 break;
3183 case MSR_KVM_ASYNC_PF_INT:
3184 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3185 return 1;
3186
3187 if (kvm_pv_enable_async_pf_int(vcpu, data))
3188 return 1;
3189 break;
3190 case MSR_KVM_ASYNC_PF_ACK:
3191 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3192 return 1;
3193 if (data & 0x1) {
3194 vcpu->arch.apf.pageready_pending = false;
3195 kvm_check_async_pf_completion(vcpu);
3196 }
3197 break;
3198 case MSR_KVM_STEAL_TIME:
3199 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3200 return 1;
3201
3202 if (unlikely(!sched_info_on()))
3203 return 1;
3204
3205 if (data & KVM_STEAL_RESERVED_MASK)
3206 return 1;
3207
3208 vcpu->arch.st.msr_val = data;
3209
3210 if (!(data & KVM_MSR_ENABLED))
3211 break;
3212
3213 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3214
3215 break;
3216 case MSR_KVM_PV_EOI_EN:
3217 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3218 return 1;
3219
3220 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3221 return 1;
3222 break;
3223
3224 case MSR_KVM_POLL_CONTROL:
3225 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3226 return 1;
3227
3228 /* only enable bit supported */
3229 if (data & (-1ULL << 1))
3230 return 1;
3231
3232 vcpu->arch.msr_kvm_poll_control = data;
3233 break;
3234
3235 case MSR_IA32_MCG_CTL:
3236 case MSR_IA32_MCG_STATUS:
3237 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3238 return set_msr_mce(vcpu, msr_info);
3239
3240 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3241 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3242 pr = true;
3243 fallthrough;
3244 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3245 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3246 if (kvm_pmu_is_valid_msr(vcpu, msr))
3247 return kvm_pmu_set_msr(vcpu, msr_info);
3248
3249 if (pr || data != 0)
3250 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3251 "0x%x data 0x%llx\n", msr, data);
3252 break;
3253 case MSR_K7_CLK_CTL:
3254 /*
3255 * Ignore all writes to this no longer documented MSR.
3256 * Writes are only relevant for old K7 processors,
3257 * all pre-dating SVM, but a recommended workaround from
3258 * AMD for these chips. It is possible to specify the
3259 * affected processor models on the command line, hence
3260 * the need to ignore the workaround.
3261 */
3262 break;
3263 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3264 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3265 case HV_X64_MSR_SYNDBG_OPTIONS:
3266 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3267 case HV_X64_MSR_CRASH_CTL:
3268 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3269 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3270 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3271 case HV_X64_MSR_TSC_EMULATION_STATUS:
3272 return kvm_hv_set_msr_common(vcpu, msr, data,
3273 msr_info->host_initiated);
3274 case MSR_IA32_BBL_CR_CTL3:
3275 /* Drop writes to this legacy MSR -- see rdmsr
3276 * counterpart for further detail.
3277 */
3278 if (report_ignored_msrs)
3279 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3280 msr, data);
3281 break;
3282 case MSR_AMD64_OSVW_ID_LENGTH:
3283 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3284 return 1;
3285 vcpu->arch.osvw.length = data;
3286 break;
3287 case MSR_AMD64_OSVW_STATUS:
3288 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3289 return 1;
3290 vcpu->arch.osvw.status = data;
3291 break;
3292 case MSR_PLATFORM_INFO:
3293 if (!msr_info->host_initiated ||
3294 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3295 cpuid_fault_enabled(vcpu)))
3296 return 1;
3297 vcpu->arch.msr_platform_info = data;
3298 break;
3299 case MSR_MISC_FEATURES_ENABLES:
3300 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3301 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3302 !supports_cpuid_fault(vcpu)))
3303 return 1;
3304 vcpu->arch.msr_misc_features_enables = data;
3305 break;
3306 default:
3307 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3308 return xen_hvm_config(vcpu, data);
3309 if (kvm_pmu_is_valid_msr(vcpu, msr))
3310 return kvm_pmu_set_msr(vcpu, msr_info);
3311 return KVM_MSR_RET_INVALID;
3312 }
3313 return 0;
3314 }
3315 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3316
3317 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3318 {
3319 u64 data;
3320 u64 mcg_cap = vcpu->arch.mcg_cap;
3321 unsigned bank_num = mcg_cap & 0xff;
3322
3323 switch (msr) {
3324 case MSR_IA32_P5_MC_ADDR:
3325 case MSR_IA32_P5_MC_TYPE:
3326 data = 0;
3327 break;
3328 case MSR_IA32_MCG_CAP:
3329 data = vcpu->arch.mcg_cap;
3330 break;
3331 case MSR_IA32_MCG_CTL:
3332 if (!(mcg_cap & MCG_CTL_P) && !host)
3333 return 1;
3334 data = vcpu->arch.mcg_ctl;
3335 break;
3336 case MSR_IA32_MCG_STATUS:
3337 data = vcpu->arch.mcg_status;
3338 break;
3339 default:
3340 if (msr >= MSR_IA32_MC0_CTL &&
3341 msr < MSR_IA32_MCx_CTL(bank_num)) {
3342 u32 offset = array_index_nospec(
3343 msr - MSR_IA32_MC0_CTL,
3344 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3345
3346 data = vcpu->arch.mce_banks[offset];
3347 break;
3348 }
3349 return 1;
3350 }
3351 *pdata = data;
3352 return 0;
3353 }
3354
3355 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3356 {
3357 switch (msr_info->index) {
3358 case MSR_IA32_PLATFORM_ID:
3359 case MSR_IA32_EBL_CR_POWERON:
3360 case MSR_IA32_DEBUGCTLMSR:
3361 case MSR_IA32_LASTBRANCHFROMIP:
3362 case MSR_IA32_LASTBRANCHTOIP:
3363 case MSR_IA32_LASTINTFROMIP:
3364 case MSR_IA32_LASTINTTOIP:
3365 case MSR_K8_SYSCFG:
3366 case MSR_K8_TSEG_ADDR:
3367 case MSR_K8_TSEG_MASK:
3368 case MSR_VM_HSAVE_PA:
3369 case MSR_K8_INT_PENDING_MSG:
3370 case MSR_AMD64_NB_CFG:
3371 case MSR_FAM10H_MMIO_CONF_BASE:
3372 case MSR_AMD64_BU_CFG2:
3373 case MSR_IA32_PERF_CTL:
3374 case MSR_AMD64_DC_CFG:
3375 case MSR_F15H_EX_CFG:
3376 /*
3377 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3378 * limit) MSRs. Just return 0, as we do not want to expose the host
3379 * data here. Do not conditionalize this on CPUID, as KVM does not do
3380 * so for existing CPU-specific MSRs.
3381 */
3382 case MSR_RAPL_POWER_UNIT:
3383 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3384 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3385 case MSR_PKG_ENERGY_STATUS: /* Total package */
3386 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3387 msr_info->data = 0;
3388 break;
3389 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3390 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3391 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3392 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3393 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3394 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3395 return kvm_pmu_get_msr(vcpu, msr_info);
3396 msr_info->data = 0;
3397 break;
3398 case MSR_IA32_UCODE_REV:
3399 msr_info->data = vcpu->arch.microcode_version;
3400 break;
3401 case MSR_IA32_ARCH_CAPABILITIES:
3402 if (!msr_info->host_initiated &&
3403 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3404 return 1;
3405 msr_info->data = vcpu->arch.arch_capabilities;
3406 break;
3407 case MSR_IA32_PERF_CAPABILITIES:
3408 if (!msr_info->host_initiated &&
3409 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3410 return 1;
3411 msr_info->data = vcpu->arch.perf_capabilities;
3412 break;
3413 case MSR_IA32_POWER_CTL:
3414 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3415 break;
3416 case MSR_IA32_TSC: {
3417 /*
3418 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3419 * even when not intercepted. AMD manual doesn't explicitly
3420 * state this but appears to behave the same.
3421 *
3422 * On userspace reads and writes, however, we unconditionally
3423 * return L1's TSC value to ensure backwards-compatible
3424 * behavior for migration.
3425 */
3426 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3427 vcpu->arch.tsc_offset;
3428
3429 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3430 break;
3431 }
3432 case MSR_MTRRcap:
3433 case 0x200 ... 0x2ff:
3434 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3435 case 0xcd: /* fsb frequency */
3436 msr_info->data = 3;
3437 break;
3438 /*
3439 * MSR_EBC_FREQUENCY_ID
3440 * Conservative value valid for even the basic CPU models.
3441 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3442 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3443 * and 266MHz for model 3, or 4. Set Core Clock
3444 * Frequency to System Bus Frequency Ratio to 1 (bits
3445 * 31:24) even though these are only valid for CPU
3446 * models > 2, however guests may end up dividing or
3447 * multiplying by zero otherwise.
3448 */
3449 case MSR_EBC_FREQUENCY_ID:
3450 msr_info->data = 1 << 24;
3451 break;
3452 case MSR_IA32_APICBASE:
3453 msr_info->data = kvm_get_apic_base(vcpu);
3454 break;
3455 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3456 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3457 case MSR_IA32_TSCDEADLINE:
3458 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3459 break;
3460 case MSR_IA32_TSC_ADJUST:
3461 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3462 break;
3463 case MSR_IA32_MISC_ENABLE:
3464 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3465 break;
3466 case MSR_IA32_SMBASE:
3467 if (!msr_info->host_initiated)
3468 return 1;
3469 msr_info->data = vcpu->arch.smbase;
3470 break;
3471 case MSR_SMI_COUNT:
3472 msr_info->data = vcpu->arch.smi_count;
3473 break;
3474 case MSR_IA32_PERF_STATUS:
3475 /* TSC increment by tick */
3476 msr_info->data = 1000ULL;
3477 /* CPU multiplier */
3478 msr_info->data |= (((uint64_t)4ULL) << 40);
3479 break;
3480 case MSR_EFER:
3481 msr_info->data = vcpu->arch.efer;
3482 break;
3483 case MSR_KVM_WALL_CLOCK:
3484 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3485 return 1;
3486
3487 msr_info->data = vcpu->kvm->arch.wall_clock;
3488 break;
3489 case MSR_KVM_WALL_CLOCK_NEW:
3490 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3491 return 1;
3492
3493 msr_info->data = vcpu->kvm->arch.wall_clock;
3494 break;
3495 case MSR_KVM_SYSTEM_TIME:
3496 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3497 return 1;
3498
3499 msr_info->data = vcpu->arch.time;
3500 break;
3501 case MSR_KVM_SYSTEM_TIME_NEW:
3502 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3503 return 1;
3504
3505 msr_info->data = vcpu->arch.time;
3506 break;
3507 case MSR_KVM_ASYNC_PF_EN:
3508 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3509 return 1;
3510
3511 msr_info->data = vcpu->arch.apf.msr_en_val;
3512 break;
3513 case MSR_KVM_ASYNC_PF_INT:
3514 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3515 return 1;
3516
3517 msr_info->data = vcpu->arch.apf.msr_int_val;
3518 break;
3519 case MSR_KVM_ASYNC_PF_ACK:
3520 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3521 return 1;
3522
3523 msr_info->data = 0;
3524 break;
3525 case MSR_KVM_STEAL_TIME:
3526 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3527 return 1;
3528
3529 msr_info->data = vcpu->arch.st.msr_val;
3530 break;
3531 case MSR_KVM_PV_EOI_EN:
3532 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3533 return 1;
3534
3535 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3536 break;
3537 case MSR_KVM_POLL_CONTROL:
3538 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3539 return 1;
3540
3541 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3542 break;
3543 case MSR_IA32_P5_MC_ADDR:
3544 case MSR_IA32_P5_MC_TYPE:
3545 case MSR_IA32_MCG_CAP:
3546 case MSR_IA32_MCG_CTL:
3547 case MSR_IA32_MCG_STATUS:
3548 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3549 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3550 msr_info->host_initiated);
3551 case MSR_IA32_XSS:
3552 if (!msr_info->host_initiated &&
3553 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3554 return 1;
3555 msr_info->data = vcpu->arch.ia32_xss;
3556 break;
3557 case MSR_K7_CLK_CTL:
3558 /*
3559 * Provide expected ramp-up count for K7. All other
3560 * are set to zero, indicating minimum divisors for
3561 * every field.
3562 *
3563 * This prevents guest kernels on AMD host with CPU
3564 * type 6, model 8 and higher from exploding due to
3565 * the rdmsr failing.
3566 */
3567 msr_info->data = 0x20000000;
3568 break;
3569 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3570 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3571 case HV_X64_MSR_SYNDBG_OPTIONS:
3572 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3573 case HV_X64_MSR_CRASH_CTL:
3574 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3575 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3576 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3577 case HV_X64_MSR_TSC_EMULATION_STATUS:
3578 return kvm_hv_get_msr_common(vcpu,
3579 msr_info->index, &msr_info->data,
3580 msr_info->host_initiated);
3581 case MSR_IA32_BBL_CR_CTL3:
3582 /* This legacy MSR exists but isn't fully documented in current
3583 * silicon. It is however accessed by winxp in very narrow
3584 * scenarios where it sets bit #19, itself documented as
3585 * a "reserved" bit. Best effort attempt to source coherent
3586 * read data here should the balance of the register be
3587 * interpreted by the guest:
3588 *
3589 * L2 cache control register 3: 64GB range, 256KB size,
3590 * enabled, latency 0x1, configured
3591 */
3592 msr_info->data = 0xbe702111;
3593 break;
3594 case MSR_AMD64_OSVW_ID_LENGTH:
3595 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3596 return 1;
3597 msr_info->data = vcpu->arch.osvw.length;
3598 break;
3599 case MSR_AMD64_OSVW_STATUS:
3600 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3601 return 1;
3602 msr_info->data = vcpu->arch.osvw.status;
3603 break;
3604 case MSR_PLATFORM_INFO:
3605 if (!msr_info->host_initiated &&
3606 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3607 return 1;
3608 msr_info->data = vcpu->arch.msr_platform_info;
3609 break;
3610 case MSR_MISC_FEATURES_ENABLES:
3611 msr_info->data = vcpu->arch.msr_misc_features_enables;
3612 break;
3613 case MSR_K7_HWCR:
3614 msr_info->data = vcpu->arch.msr_hwcr;
3615 break;
3616 default:
3617 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3618 return kvm_pmu_get_msr(vcpu, msr_info);
3619 return KVM_MSR_RET_INVALID;
3620 }
3621 return 0;
3622 }
3623 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3624
3625 /*
3626 * Read or write a bunch of msrs. All parameters are kernel addresses.
3627 *
3628 * @return number of msrs set successfully.
3629 */
3630 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3631 struct kvm_msr_entry *entries,
3632 int (*do_msr)(struct kvm_vcpu *vcpu,
3633 unsigned index, u64 *data))
3634 {
3635 int i;
3636
3637 for (i = 0; i < msrs->nmsrs; ++i)
3638 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3639 break;
3640
3641 return i;
3642 }
3643
3644 /*
3645 * Read or write a bunch of msrs. Parameters are user addresses.
3646 *
3647 * @return number of msrs set successfully.
3648 */
3649 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3650 int (*do_msr)(struct kvm_vcpu *vcpu,
3651 unsigned index, u64 *data),
3652 int writeback)
3653 {
3654 struct kvm_msrs msrs;
3655 struct kvm_msr_entry *entries;
3656 int r, n;
3657 unsigned size;
3658
3659 r = -EFAULT;
3660 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3661 goto out;
3662
3663 r = -E2BIG;
3664 if (msrs.nmsrs >= MAX_IO_MSRS)
3665 goto out;
3666
3667 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3668 entries = memdup_user(user_msrs->entries, size);
3669 if (IS_ERR(entries)) {
3670 r = PTR_ERR(entries);
3671 goto out;
3672 }
3673
3674 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3675 if (r < 0)
3676 goto out_free;
3677
3678 r = -EFAULT;
3679 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3680 goto out_free;
3681
3682 r = n;
3683
3684 out_free:
3685 kfree(entries);
3686 out:
3687 return r;
3688 }
3689
3690 static inline bool kvm_can_mwait_in_guest(void)
3691 {
3692 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3693 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3694 boot_cpu_has(X86_FEATURE_ARAT);
3695 }
3696
3697 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
3698 struct kvm_cpuid2 __user *cpuid_arg)
3699 {
3700 struct kvm_cpuid2 cpuid;
3701 int r;
3702
3703 r = -EFAULT;
3704 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3705 return r;
3706
3707 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3708 if (r)
3709 return r;
3710
3711 r = -EFAULT;
3712 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3713 return r;
3714
3715 return 0;
3716 }
3717
3718 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3719 {
3720 int r = 0;
3721
3722 switch (ext) {
3723 case KVM_CAP_IRQCHIP:
3724 case KVM_CAP_HLT:
3725 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3726 case KVM_CAP_SET_TSS_ADDR:
3727 case KVM_CAP_EXT_CPUID:
3728 case KVM_CAP_EXT_EMUL_CPUID:
3729 case KVM_CAP_CLOCKSOURCE:
3730 case KVM_CAP_PIT:
3731 case KVM_CAP_NOP_IO_DELAY:
3732 case KVM_CAP_MP_STATE:
3733 case KVM_CAP_SYNC_MMU:
3734 case KVM_CAP_USER_NMI:
3735 case KVM_CAP_REINJECT_CONTROL:
3736 case KVM_CAP_IRQ_INJECT_STATUS:
3737 case KVM_CAP_IOEVENTFD:
3738 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3739 case KVM_CAP_PIT2:
3740 case KVM_CAP_PIT_STATE2:
3741 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3742 case KVM_CAP_XEN_HVM:
3743 case KVM_CAP_VCPU_EVENTS:
3744 case KVM_CAP_HYPERV:
3745 case KVM_CAP_HYPERV_VAPIC:
3746 case KVM_CAP_HYPERV_SPIN:
3747 case KVM_CAP_HYPERV_SYNIC:
3748 case KVM_CAP_HYPERV_SYNIC2:
3749 case KVM_CAP_HYPERV_VP_INDEX:
3750 case KVM_CAP_HYPERV_EVENTFD:
3751 case KVM_CAP_HYPERV_TLBFLUSH:
3752 case KVM_CAP_HYPERV_SEND_IPI:
3753 case KVM_CAP_HYPERV_CPUID:
3754 case KVM_CAP_SYS_HYPERV_CPUID:
3755 case KVM_CAP_PCI_SEGMENT:
3756 case KVM_CAP_DEBUGREGS:
3757 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3758 case KVM_CAP_XSAVE:
3759 case KVM_CAP_ASYNC_PF:
3760 case KVM_CAP_ASYNC_PF_INT:
3761 case KVM_CAP_GET_TSC_KHZ:
3762 case KVM_CAP_KVMCLOCK_CTRL:
3763 case KVM_CAP_READONLY_MEM:
3764 case KVM_CAP_HYPERV_TIME:
3765 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3766 case KVM_CAP_TSC_DEADLINE_TIMER:
3767 case KVM_CAP_DISABLE_QUIRKS:
3768 case KVM_CAP_SET_BOOT_CPU_ID:
3769 case KVM_CAP_SPLIT_IRQCHIP:
3770 case KVM_CAP_IMMEDIATE_EXIT:
3771 case KVM_CAP_PMU_EVENT_FILTER:
3772 case KVM_CAP_GET_MSR_FEATURES:
3773 case KVM_CAP_MSR_PLATFORM_INFO:
3774 case KVM_CAP_EXCEPTION_PAYLOAD:
3775 case KVM_CAP_SET_GUEST_DEBUG:
3776 case KVM_CAP_LAST_CPU:
3777 case KVM_CAP_X86_USER_SPACE_MSR:
3778 case KVM_CAP_X86_MSR_FILTER:
3779 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
3780 r = 1;
3781 break;
3782 case KVM_CAP_SYNC_REGS:
3783 r = KVM_SYNC_X86_VALID_FIELDS;
3784 break;
3785 case KVM_CAP_ADJUST_CLOCK:
3786 r = KVM_CLOCK_TSC_STABLE;
3787 break;
3788 case KVM_CAP_X86_DISABLE_EXITS:
3789 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3790 KVM_X86_DISABLE_EXITS_CSTATE;
3791 if(kvm_can_mwait_in_guest())
3792 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3793 break;
3794 case KVM_CAP_X86_SMM:
3795 /* SMBASE is usually relocated above 1M on modern chipsets,
3796 * and SMM handlers might indeed rely on 4G segment limits,
3797 * so do not report SMM to be available if real mode is
3798 * emulated via vm86 mode. Still, do not go to great lengths
3799 * to avoid userspace's usage of the feature, because it is a
3800 * fringe case that is not enabled except via specific settings
3801 * of the module parameters.
3802 */
3803 r = kvm_x86_ops.has_emulated_msr(kvm, MSR_IA32_SMBASE);
3804 break;
3805 case KVM_CAP_VAPIC:
3806 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3807 break;
3808 case KVM_CAP_NR_VCPUS:
3809 r = KVM_SOFT_MAX_VCPUS;
3810 break;
3811 case KVM_CAP_MAX_VCPUS:
3812 r = KVM_MAX_VCPUS;
3813 break;
3814 case KVM_CAP_MAX_VCPU_ID:
3815 r = KVM_MAX_VCPU_ID;
3816 break;
3817 case KVM_CAP_PV_MMU: /* obsolete */
3818 r = 0;
3819 break;
3820 case KVM_CAP_MCE:
3821 r = KVM_MAX_MCE_BANKS;
3822 break;
3823 case KVM_CAP_XCRS:
3824 r = boot_cpu_has(X86_FEATURE_XSAVE);
3825 break;
3826 case KVM_CAP_TSC_CONTROL:
3827 r = kvm_has_tsc_control;
3828 break;
3829 case KVM_CAP_X2APIC_API:
3830 r = KVM_X2APIC_API_VALID_FLAGS;
3831 break;
3832 case KVM_CAP_NESTED_STATE:
3833 r = kvm_x86_ops.nested_ops->get_state ?
3834 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3835 break;
3836 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3837 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3838 break;
3839 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3840 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3841 break;
3842 case KVM_CAP_SMALLER_MAXPHYADDR:
3843 r = (int) allow_smaller_maxphyaddr;
3844 break;
3845 case KVM_CAP_STEAL_TIME:
3846 r = sched_info_on();
3847 break;
3848 default:
3849 break;
3850 }
3851 return r;
3852
3853 }
3854
3855 long kvm_arch_dev_ioctl(struct file *filp,
3856 unsigned int ioctl, unsigned long arg)
3857 {
3858 void __user *argp = (void __user *)arg;
3859 long r;
3860
3861 switch (ioctl) {
3862 case KVM_GET_MSR_INDEX_LIST: {
3863 struct kvm_msr_list __user *user_msr_list = argp;
3864 struct kvm_msr_list msr_list;
3865 unsigned n;
3866
3867 r = -EFAULT;
3868 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3869 goto out;
3870 n = msr_list.nmsrs;
3871 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3872 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3873 goto out;
3874 r = -E2BIG;
3875 if (n < msr_list.nmsrs)
3876 goto out;
3877 r = -EFAULT;
3878 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3879 num_msrs_to_save * sizeof(u32)))
3880 goto out;
3881 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3882 &emulated_msrs,
3883 num_emulated_msrs * sizeof(u32)))
3884 goto out;
3885 r = 0;
3886 break;
3887 }
3888 case KVM_GET_SUPPORTED_CPUID:
3889 case KVM_GET_EMULATED_CPUID: {
3890 struct kvm_cpuid2 __user *cpuid_arg = argp;
3891 struct kvm_cpuid2 cpuid;
3892
3893 r = -EFAULT;
3894 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3895 goto out;
3896
3897 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3898 ioctl);
3899 if (r)
3900 goto out;
3901
3902 r = -EFAULT;
3903 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3904 goto out;
3905 r = 0;
3906 break;
3907 }
3908 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3909 r = -EFAULT;
3910 if (copy_to_user(argp, &kvm_mce_cap_supported,
3911 sizeof(kvm_mce_cap_supported)))
3912 goto out;
3913 r = 0;
3914 break;
3915 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3916 struct kvm_msr_list __user *user_msr_list = argp;
3917 struct kvm_msr_list msr_list;
3918 unsigned int n;
3919
3920 r = -EFAULT;
3921 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3922 goto out;
3923 n = msr_list.nmsrs;
3924 msr_list.nmsrs = num_msr_based_features;
3925 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3926 goto out;
3927 r = -E2BIG;
3928 if (n < msr_list.nmsrs)
3929 goto out;
3930 r = -EFAULT;
3931 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3932 num_msr_based_features * sizeof(u32)))
3933 goto out;
3934 r = 0;
3935 break;
3936 }
3937 case KVM_GET_MSRS:
3938 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3939 break;
3940 case KVM_GET_SUPPORTED_HV_CPUID:
3941 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
3942 break;
3943 default:
3944 r = -EINVAL;
3945 break;
3946 }
3947 out:
3948 return r;
3949 }
3950
3951 static void wbinvd_ipi(void *garbage)
3952 {
3953 wbinvd();
3954 }
3955
3956 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3957 {
3958 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3959 }
3960
3961 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3962 {
3963 /* Address WBINVD may be executed by guest */
3964 if (need_emulate_wbinvd(vcpu)) {
3965 if (kvm_x86_ops.has_wbinvd_exit())
3966 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3967 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3968 smp_call_function_single(vcpu->cpu,
3969 wbinvd_ipi, NULL, 1);
3970 }
3971
3972 kvm_x86_ops.vcpu_load(vcpu, cpu);
3973
3974 /* Save host pkru register if supported */
3975 vcpu->arch.host_pkru = read_pkru();
3976
3977 /* Apply any externally detected TSC adjustments (due to suspend) */
3978 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3979 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3980 vcpu->arch.tsc_offset_adjustment = 0;
3981 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3982 }
3983
3984 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3985 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3986 rdtsc() - vcpu->arch.last_host_tsc;
3987 if (tsc_delta < 0)
3988 mark_tsc_unstable("KVM discovered backwards TSC");
3989
3990 if (kvm_check_tsc_unstable()) {
3991 u64 offset = kvm_compute_tsc_offset(vcpu,
3992 vcpu->arch.last_guest_tsc);
3993 kvm_vcpu_write_tsc_offset(vcpu, offset);
3994 vcpu->arch.tsc_catchup = 1;
3995 }
3996
3997 if (kvm_lapic_hv_timer_in_use(vcpu))
3998 kvm_lapic_restart_hv_timer(vcpu);
3999
4000 /*
4001 * On a host with synchronized TSC, there is no need to update
4002 * kvmclock on vcpu->cpu migration
4003 */
4004 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4005 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4006 if (vcpu->cpu != cpu)
4007 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4008 vcpu->cpu = cpu;
4009 }
4010
4011 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4012 }
4013
4014 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4015 {
4016 struct kvm_host_map map;
4017 struct kvm_steal_time *st;
4018
4019 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4020 return;
4021
4022 if (vcpu->arch.st.preempted)
4023 return;
4024
4025 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
4026 &vcpu->arch.st.cache, true))
4027 return;
4028
4029 st = map.hva +
4030 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
4031
4032 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4033
4034 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
4035 }
4036
4037 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4038 {
4039 int idx;
4040
4041 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4042 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
4043
4044 /*
4045 * Disable page faults because we're in atomic context here.
4046 * kvm_write_guest_offset_cached() would call might_fault()
4047 * that relies on pagefault_disable() to tell if there's a
4048 * bug. NOTE: the write to guest memory may not go through if
4049 * during postcopy live migration or if there's heavy guest
4050 * paging.
4051 */
4052 pagefault_disable();
4053 /*
4054 * kvm_memslots() will be called by
4055 * kvm_write_guest_offset_cached() so take the srcu lock.
4056 */
4057 idx = srcu_read_lock(&vcpu->kvm->srcu);
4058 kvm_steal_time_set_preempted(vcpu);
4059 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4060 pagefault_enable();
4061 kvm_x86_ops.vcpu_put(vcpu);
4062 vcpu->arch.last_host_tsc = rdtsc();
4063 /*
4064 * If userspace has set any breakpoints or watchpoints, dr6 is restored
4065 * on every vmexit, but if not, we might have a stale dr6 from the
4066 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
4067 */
4068 set_debugreg(0, 6);
4069 }
4070
4071 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4072 struct kvm_lapic_state *s)
4073 {
4074 if (vcpu->arch.apicv_active)
4075 kvm_x86_ops.sync_pir_to_irr(vcpu);
4076
4077 return kvm_apic_get_state(vcpu, s);
4078 }
4079
4080 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4081 struct kvm_lapic_state *s)
4082 {
4083 int r;
4084
4085 r = kvm_apic_set_state(vcpu, s);
4086 if (r)
4087 return r;
4088 update_cr8_intercept(vcpu);
4089
4090 return 0;
4091 }
4092
4093 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4094 {
4095 /*
4096 * We can accept userspace's request for interrupt injection
4097 * as long as we have a place to store the interrupt number.
4098 * The actual injection will happen when the CPU is able to
4099 * deliver the interrupt.
4100 */
4101 if (kvm_cpu_has_extint(vcpu))
4102 return false;
4103
4104 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4105 return (!lapic_in_kernel(vcpu) ||
4106 kvm_apic_accept_pic_intr(vcpu));
4107 }
4108
4109 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4110 {
4111 return kvm_arch_interrupt_allowed(vcpu) &&
4112 kvm_cpu_accept_dm_intr(vcpu);
4113 }
4114
4115 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4116 struct kvm_interrupt *irq)
4117 {
4118 if (irq->irq >= KVM_NR_INTERRUPTS)
4119 return -EINVAL;
4120
4121 if (!irqchip_in_kernel(vcpu->kvm)) {
4122 kvm_queue_interrupt(vcpu, irq->irq, false);
4123 kvm_make_request(KVM_REQ_EVENT, vcpu);
4124 return 0;
4125 }
4126
4127 /*
4128 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4129 * fail for in-kernel 8259.
4130 */
4131 if (pic_in_kernel(vcpu->kvm))
4132 return -ENXIO;
4133
4134 if (vcpu->arch.pending_external_vector != -1)
4135 return -EEXIST;
4136
4137 vcpu->arch.pending_external_vector = irq->irq;
4138 kvm_make_request(KVM_REQ_EVENT, vcpu);
4139 return 0;
4140 }
4141
4142 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4143 {
4144 kvm_inject_nmi(vcpu);
4145
4146 return 0;
4147 }
4148
4149 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4150 {
4151 kvm_make_request(KVM_REQ_SMI, vcpu);
4152
4153 return 0;
4154 }
4155
4156 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4157 struct kvm_tpr_access_ctl *tac)
4158 {
4159 if (tac->flags)
4160 return -EINVAL;
4161 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4162 return 0;
4163 }
4164
4165 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4166 u64 mcg_cap)
4167 {
4168 int r;
4169 unsigned bank_num = mcg_cap & 0xff, bank;
4170
4171 r = -EINVAL;
4172 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4173 goto out;
4174 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4175 goto out;
4176 r = 0;
4177 vcpu->arch.mcg_cap = mcg_cap;
4178 /* Init IA32_MCG_CTL to all 1s */
4179 if (mcg_cap & MCG_CTL_P)
4180 vcpu->arch.mcg_ctl = ~(u64)0;
4181 /* Init IA32_MCi_CTL to all 1s */
4182 for (bank = 0; bank < bank_num; bank++)
4183 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4184
4185 kvm_x86_ops.setup_mce(vcpu);
4186 out:
4187 return r;
4188 }
4189
4190 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4191 struct kvm_x86_mce *mce)
4192 {
4193 u64 mcg_cap = vcpu->arch.mcg_cap;
4194 unsigned bank_num = mcg_cap & 0xff;
4195 u64 *banks = vcpu->arch.mce_banks;
4196
4197 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4198 return -EINVAL;
4199 /*
4200 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4201 * reporting is disabled
4202 */
4203 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4204 vcpu->arch.mcg_ctl != ~(u64)0)
4205 return 0;
4206 banks += 4 * mce->bank;
4207 /*
4208 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4209 * reporting is disabled for the bank
4210 */
4211 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4212 return 0;
4213 if (mce->status & MCI_STATUS_UC) {
4214 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4215 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4216 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4217 return 0;
4218 }
4219 if (banks[1] & MCI_STATUS_VAL)
4220 mce->status |= MCI_STATUS_OVER;
4221 banks[2] = mce->addr;
4222 banks[3] = mce->misc;
4223 vcpu->arch.mcg_status = mce->mcg_status;
4224 banks[1] = mce->status;
4225 kvm_queue_exception(vcpu, MC_VECTOR);
4226 } else if (!(banks[1] & MCI_STATUS_VAL)
4227 || !(banks[1] & MCI_STATUS_UC)) {
4228 if (banks[1] & MCI_STATUS_VAL)
4229 mce->status |= MCI_STATUS_OVER;
4230 banks[2] = mce->addr;
4231 banks[3] = mce->misc;
4232 banks[1] = mce->status;
4233 } else
4234 banks[1] |= MCI_STATUS_OVER;
4235 return 0;
4236 }
4237
4238 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4239 struct kvm_vcpu_events *events)
4240 {
4241 process_nmi(vcpu);
4242
4243 if (kvm_check_request(KVM_REQ_SMI, vcpu))
4244 process_smi(vcpu);
4245
4246 /*
4247 * In guest mode, payload delivery should be deferred,
4248 * so that the L1 hypervisor can intercept #PF before
4249 * CR2 is modified (or intercept #DB before DR6 is
4250 * modified under nVMX). Unless the per-VM capability,
4251 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4252 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4253 * opportunistically defer the exception payload, deliver it if the
4254 * capability hasn't been requested before processing a
4255 * KVM_GET_VCPU_EVENTS.
4256 */
4257 if (!vcpu->kvm->arch.exception_payload_enabled &&
4258 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4259 kvm_deliver_exception_payload(vcpu);
4260
4261 /*
4262 * The API doesn't provide the instruction length for software
4263 * exceptions, so don't report them. As long as the guest RIP
4264 * isn't advanced, we should expect to encounter the exception
4265 * again.
4266 */
4267 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4268 events->exception.injected = 0;
4269 events->exception.pending = 0;
4270 } else {
4271 events->exception.injected = vcpu->arch.exception.injected;
4272 events->exception.pending = vcpu->arch.exception.pending;
4273 /*
4274 * For ABI compatibility, deliberately conflate
4275 * pending and injected exceptions when
4276 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4277 */
4278 if (!vcpu->kvm->arch.exception_payload_enabled)
4279 events->exception.injected |=
4280 vcpu->arch.exception.pending;
4281 }
4282 events->exception.nr = vcpu->arch.exception.nr;
4283 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4284 events->exception.error_code = vcpu->arch.exception.error_code;
4285 events->exception_has_payload = vcpu->arch.exception.has_payload;
4286 events->exception_payload = vcpu->arch.exception.payload;
4287
4288 events->interrupt.injected =
4289 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4290 events->interrupt.nr = vcpu->arch.interrupt.nr;
4291 events->interrupt.soft = 0;
4292 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4293
4294 events->nmi.injected = vcpu->arch.nmi_injected;
4295 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4296 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4297 events->nmi.pad = 0;
4298
4299 events->sipi_vector = 0; /* never valid when reporting to user space */
4300
4301 events->smi.smm = is_smm(vcpu);
4302 events->smi.pending = vcpu->arch.smi_pending;
4303 events->smi.smm_inside_nmi =
4304 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4305 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4306
4307 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4308 | KVM_VCPUEVENT_VALID_SHADOW
4309 | KVM_VCPUEVENT_VALID_SMM);
4310 if (vcpu->kvm->arch.exception_payload_enabled)
4311 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4312
4313 memset(&events->reserved, 0, sizeof(events->reserved));
4314 }
4315
4316 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4317
4318 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4319 struct kvm_vcpu_events *events)
4320 {
4321 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4322 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4323 | KVM_VCPUEVENT_VALID_SHADOW
4324 | KVM_VCPUEVENT_VALID_SMM
4325 | KVM_VCPUEVENT_VALID_PAYLOAD))
4326 return -EINVAL;
4327
4328 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4329 if (!vcpu->kvm->arch.exception_payload_enabled)
4330 return -EINVAL;
4331 if (events->exception.pending)
4332 events->exception.injected = 0;
4333 else
4334 events->exception_has_payload = 0;
4335 } else {
4336 events->exception.pending = 0;
4337 events->exception_has_payload = 0;
4338 }
4339
4340 if ((events->exception.injected || events->exception.pending) &&
4341 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4342 return -EINVAL;
4343
4344 /* INITs are latched while in SMM */
4345 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4346 (events->smi.smm || events->smi.pending) &&
4347 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4348 return -EINVAL;
4349
4350 process_nmi(vcpu);
4351 vcpu->arch.exception.injected = events->exception.injected;
4352 vcpu->arch.exception.pending = events->exception.pending;
4353 vcpu->arch.exception.nr = events->exception.nr;
4354 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4355 vcpu->arch.exception.error_code = events->exception.error_code;
4356 vcpu->arch.exception.has_payload = events->exception_has_payload;
4357 vcpu->arch.exception.payload = events->exception_payload;
4358
4359 vcpu->arch.interrupt.injected = events->interrupt.injected;
4360 vcpu->arch.interrupt.nr = events->interrupt.nr;
4361 vcpu->arch.interrupt.soft = events->interrupt.soft;
4362 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4363 kvm_x86_ops.set_interrupt_shadow(vcpu,
4364 events->interrupt.shadow);
4365
4366 vcpu->arch.nmi_injected = events->nmi.injected;
4367 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4368 vcpu->arch.nmi_pending = events->nmi.pending;
4369 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4370
4371 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4372 lapic_in_kernel(vcpu))
4373 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4374
4375 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4376 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4377 if (events->smi.smm)
4378 vcpu->arch.hflags |= HF_SMM_MASK;
4379 else
4380 vcpu->arch.hflags &= ~HF_SMM_MASK;
4381 kvm_smm_changed(vcpu);
4382 }
4383
4384 vcpu->arch.smi_pending = events->smi.pending;
4385
4386 if (events->smi.smm) {
4387 if (events->smi.smm_inside_nmi)
4388 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4389 else
4390 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4391 }
4392
4393 if (lapic_in_kernel(vcpu)) {
4394 if (events->smi.latched_init)
4395 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4396 else
4397 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4398 }
4399 }
4400
4401 kvm_make_request(KVM_REQ_EVENT, vcpu);
4402
4403 return 0;
4404 }
4405
4406 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4407 struct kvm_debugregs *dbgregs)
4408 {
4409 unsigned long val;
4410
4411 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4412 kvm_get_dr(vcpu, 6, &val);
4413 dbgregs->dr6 = val;
4414 dbgregs->dr7 = vcpu->arch.dr7;
4415 dbgregs->flags = 0;
4416 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4417 }
4418
4419 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4420 struct kvm_debugregs *dbgregs)
4421 {
4422 if (dbgregs->flags)
4423 return -EINVAL;
4424
4425 if (dbgregs->dr6 & ~0xffffffffull)
4426 return -EINVAL;
4427 if (dbgregs->dr7 & ~0xffffffffull)
4428 return -EINVAL;
4429
4430 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4431 kvm_update_dr0123(vcpu);
4432 vcpu->arch.dr6 = dbgregs->dr6;
4433 vcpu->arch.dr7 = dbgregs->dr7;
4434 kvm_update_dr7(vcpu);
4435
4436 return 0;
4437 }
4438
4439 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4440
4441 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4442 {
4443 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4444 u64 xstate_bv = xsave->header.xfeatures;
4445 u64 valid;
4446
4447 /*
4448 * Copy legacy XSAVE area, to avoid complications with CPUID
4449 * leaves 0 and 1 in the loop below.
4450 */
4451 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4452
4453 /* Set XSTATE_BV */
4454 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4455 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4456
4457 /*
4458 * Copy each region from the possibly compacted offset to the
4459 * non-compacted offset.
4460 */
4461 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4462 while (valid) {
4463 u64 xfeature_mask = valid & -valid;
4464 int xfeature_nr = fls64(xfeature_mask) - 1;
4465 void *src = get_xsave_addr(xsave, xfeature_nr);
4466
4467 if (src) {
4468 u32 size, offset, ecx, edx;
4469 cpuid_count(XSTATE_CPUID, xfeature_nr,
4470 &size, &offset, &ecx, &edx);
4471 if (xfeature_nr == XFEATURE_PKRU)
4472 memcpy(dest + offset, &vcpu->arch.pkru,
4473 sizeof(vcpu->arch.pkru));
4474 else
4475 memcpy(dest + offset, src, size);
4476
4477 }
4478
4479 valid -= xfeature_mask;
4480 }
4481 }
4482
4483 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4484 {
4485 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4486 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4487 u64 valid;
4488
4489 /*
4490 * Copy legacy XSAVE area, to avoid complications with CPUID
4491 * leaves 0 and 1 in the loop below.
4492 */
4493 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4494
4495 /* Set XSTATE_BV and possibly XCOMP_BV. */
4496 xsave->header.xfeatures = xstate_bv;
4497 if (boot_cpu_has(X86_FEATURE_XSAVES))
4498 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4499
4500 /*
4501 * Copy each region from the non-compacted offset to the
4502 * possibly compacted offset.
4503 */
4504 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4505 while (valid) {
4506 u64 xfeature_mask = valid & -valid;
4507 int xfeature_nr = fls64(xfeature_mask) - 1;
4508 void *dest = get_xsave_addr(xsave, xfeature_nr);
4509
4510 if (dest) {
4511 u32 size, offset, ecx, edx;
4512 cpuid_count(XSTATE_CPUID, xfeature_nr,
4513 &size, &offset, &ecx, &edx);
4514 if (xfeature_nr == XFEATURE_PKRU)
4515 memcpy(&vcpu->arch.pkru, src + offset,
4516 sizeof(vcpu->arch.pkru));
4517 else
4518 memcpy(dest, src + offset, size);
4519 }
4520
4521 valid -= xfeature_mask;
4522 }
4523 }
4524
4525 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4526 struct kvm_xsave *guest_xsave)
4527 {
4528 if (!vcpu->arch.guest_fpu)
4529 return;
4530
4531 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4532 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4533 fill_xsave((u8 *) guest_xsave->region, vcpu);
4534 } else {
4535 memcpy(guest_xsave->region,
4536 &vcpu->arch.guest_fpu->state.fxsave,
4537 sizeof(struct fxregs_state));
4538 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4539 XFEATURE_MASK_FPSSE;
4540 }
4541 }
4542
4543 #define XSAVE_MXCSR_OFFSET 24
4544
4545 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4546 struct kvm_xsave *guest_xsave)
4547 {
4548 u64 xstate_bv;
4549 u32 mxcsr;
4550
4551 if (!vcpu->arch.guest_fpu)
4552 return 0;
4553
4554 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4555 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4556
4557 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4558 /*
4559 * Here we allow setting states that are not present in
4560 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4561 * with old userspace.
4562 */
4563 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4564 return -EINVAL;
4565 load_xsave(vcpu, (u8 *)guest_xsave->region);
4566 } else {
4567 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4568 mxcsr & ~mxcsr_feature_mask)
4569 return -EINVAL;
4570 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4571 guest_xsave->region, sizeof(struct fxregs_state));
4572 }
4573 return 0;
4574 }
4575
4576 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4577 struct kvm_xcrs *guest_xcrs)
4578 {
4579 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4580 guest_xcrs->nr_xcrs = 0;
4581 return;
4582 }
4583
4584 guest_xcrs->nr_xcrs = 1;
4585 guest_xcrs->flags = 0;
4586 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4587 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4588 }
4589
4590 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4591 struct kvm_xcrs *guest_xcrs)
4592 {
4593 int i, r = 0;
4594
4595 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4596 return -EINVAL;
4597
4598 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4599 return -EINVAL;
4600
4601 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4602 /* Only support XCR0 currently */
4603 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4604 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4605 guest_xcrs->xcrs[i].value);
4606 break;
4607 }
4608 if (r)
4609 r = -EINVAL;
4610 return r;
4611 }
4612
4613 /*
4614 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4615 * stopped by the hypervisor. This function will be called from the host only.
4616 * EINVAL is returned when the host attempts to set the flag for a guest that
4617 * does not support pv clocks.
4618 */
4619 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4620 {
4621 if (!vcpu->arch.pv_time_enabled)
4622 return -EINVAL;
4623 vcpu->arch.pvclock_set_guest_stopped_request = true;
4624 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4625 return 0;
4626 }
4627
4628 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4629 struct kvm_enable_cap *cap)
4630 {
4631 int r;
4632 uint16_t vmcs_version;
4633 void __user *user_ptr;
4634
4635 if (cap->flags)
4636 return -EINVAL;
4637
4638 switch (cap->cap) {
4639 case KVM_CAP_HYPERV_SYNIC2:
4640 if (cap->args[0])
4641 return -EINVAL;
4642 fallthrough;
4643
4644 case KVM_CAP_HYPERV_SYNIC:
4645 if (!irqchip_in_kernel(vcpu->kvm))
4646 return -EINVAL;
4647 return kvm_hv_activate_synic(vcpu, cap->cap ==
4648 KVM_CAP_HYPERV_SYNIC2);
4649 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4650 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4651 return -ENOTTY;
4652 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4653 if (!r) {
4654 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4655 if (copy_to_user(user_ptr, &vmcs_version,
4656 sizeof(vmcs_version)))
4657 r = -EFAULT;
4658 }
4659 return r;
4660 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4661 if (!kvm_x86_ops.enable_direct_tlbflush)
4662 return -ENOTTY;
4663
4664 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4665
4666 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4667 vcpu->arch.pv_cpuid.enforce = cap->args[0];
4668 if (vcpu->arch.pv_cpuid.enforce)
4669 kvm_update_pv_runtime(vcpu);
4670
4671 return 0;
4672
4673 default:
4674 return -EINVAL;
4675 }
4676 }
4677
4678 long kvm_arch_vcpu_ioctl(struct file *filp,
4679 unsigned int ioctl, unsigned long arg)
4680 {
4681 struct kvm_vcpu *vcpu = filp->private_data;
4682 void __user *argp = (void __user *)arg;
4683 int r;
4684 union {
4685 struct kvm_lapic_state *lapic;
4686 struct kvm_xsave *xsave;
4687 struct kvm_xcrs *xcrs;
4688 void *buffer;
4689 } u;
4690
4691 vcpu_load(vcpu);
4692
4693 u.buffer = NULL;
4694 switch (ioctl) {
4695 case KVM_GET_LAPIC: {
4696 r = -EINVAL;
4697 if (!lapic_in_kernel(vcpu))
4698 goto out;
4699 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4700 GFP_KERNEL_ACCOUNT);
4701
4702 r = -ENOMEM;
4703 if (!u.lapic)
4704 goto out;
4705 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4706 if (r)
4707 goto out;
4708 r = -EFAULT;
4709 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4710 goto out;
4711 r = 0;
4712 break;
4713 }
4714 case KVM_SET_LAPIC: {
4715 r = -EINVAL;
4716 if (!lapic_in_kernel(vcpu))
4717 goto out;
4718 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4719 if (IS_ERR(u.lapic)) {
4720 r = PTR_ERR(u.lapic);
4721 goto out_nofree;
4722 }
4723
4724 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4725 break;
4726 }
4727 case KVM_INTERRUPT: {
4728 struct kvm_interrupt irq;
4729
4730 r = -EFAULT;
4731 if (copy_from_user(&irq, argp, sizeof(irq)))
4732 goto out;
4733 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4734 break;
4735 }
4736 case KVM_NMI: {
4737 r = kvm_vcpu_ioctl_nmi(vcpu);
4738 break;
4739 }
4740 case KVM_SMI: {
4741 r = kvm_vcpu_ioctl_smi(vcpu);
4742 break;
4743 }
4744 case KVM_SET_CPUID: {
4745 struct kvm_cpuid __user *cpuid_arg = argp;
4746 struct kvm_cpuid cpuid;
4747
4748 r = -EFAULT;
4749 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4750 goto out;
4751 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4752 break;
4753 }
4754 case KVM_SET_CPUID2: {
4755 struct kvm_cpuid2 __user *cpuid_arg = argp;
4756 struct kvm_cpuid2 cpuid;
4757
4758 r = -EFAULT;
4759 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4760 goto out;
4761 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4762 cpuid_arg->entries);
4763 break;
4764 }
4765 case KVM_GET_CPUID2: {
4766 struct kvm_cpuid2 __user *cpuid_arg = argp;
4767 struct kvm_cpuid2 cpuid;
4768
4769 r = -EFAULT;
4770 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4771 goto out;
4772 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4773 cpuid_arg->entries);
4774 if (r)
4775 goto out;
4776 r = -EFAULT;
4777 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4778 goto out;
4779 r = 0;
4780 break;
4781 }
4782 case KVM_GET_MSRS: {
4783 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4784 r = msr_io(vcpu, argp, do_get_msr, 1);
4785 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4786 break;
4787 }
4788 case KVM_SET_MSRS: {
4789 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4790 r = msr_io(vcpu, argp, do_set_msr, 0);
4791 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4792 break;
4793 }
4794 case KVM_TPR_ACCESS_REPORTING: {
4795 struct kvm_tpr_access_ctl tac;
4796
4797 r = -EFAULT;
4798 if (copy_from_user(&tac, argp, sizeof(tac)))
4799 goto out;
4800 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4801 if (r)
4802 goto out;
4803 r = -EFAULT;
4804 if (copy_to_user(argp, &tac, sizeof(tac)))
4805 goto out;
4806 r = 0;
4807 break;
4808 };
4809 case KVM_SET_VAPIC_ADDR: {
4810 struct kvm_vapic_addr va;
4811 int idx;
4812
4813 r = -EINVAL;
4814 if (!lapic_in_kernel(vcpu))
4815 goto out;
4816 r = -EFAULT;
4817 if (copy_from_user(&va, argp, sizeof(va)))
4818 goto out;
4819 idx = srcu_read_lock(&vcpu->kvm->srcu);
4820 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4821 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4822 break;
4823 }
4824 case KVM_X86_SETUP_MCE: {
4825 u64 mcg_cap;
4826
4827 r = -EFAULT;
4828 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4829 goto out;
4830 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4831 break;
4832 }
4833 case KVM_X86_SET_MCE: {
4834 struct kvm_x86_mce mce;
4835
4836 r = -EFAULT;
4837 if (copy_from_user(&mce, argp, sizeof(mce)))
4838 goto out;
4839 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4840 break;
4841 }
4842 case KVM_GET_VCPU_EVENTS: {
4843 struct kvm_vcpu_events events;
4844
4845 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4846
4847 r = -EFAULT;
4848 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4849 break;
4850 r = 0;
4851 break;
4852 }
4853 case KVM_SET_VCPU_EVENTS: {
4854 struct kvm_vcpu_events events;
4855
4856 r = -EFAULT;
4857 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4858 break;
4859
4860 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4861 break;
4862 }
4863 case KVM_GET_DEBUGREGS: {
4864 struct kvm_debugregs dbgregs;
4865
4866 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4867
4868 r = -EFAULT;
4869 if (copy_to_user(argp, &dbgregs,
4870 sizeof(struct kvm_debugregs)))
4871 break;
4872 r = 0;
4873 break;
4874 }
4875 case KVM_SET_DEBUGREGS: {
4876 struct kvm_debugregs dbgregs;
4877
4878 r = -EFAULT;
4879 if (copy_from_user(&dbgregs, argp,
4880 sizeof(struct kvm_debugregs)))
4881 break;
4882
4883 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4884 break;
4885 }
4886 case KVM_GET_XSAVE: {
4887 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4888 r = -ENOMEM;
4889 if (!u.xsave)
4890 break;
4891
4892 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4893
4894 r = -EFAULT;
4895 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4896 break;
4897 r = 0;
4898 break;
4899 }
4900 case KVM_SET_XSAVE: {
4901 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4902 if (IS_ERR(u.xsave)) {
4903 r = PTR_ERR(u.xsave);
4904 goto out_nofree;
4905 }
4906
4907 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4908 break;
4909 }
4910 case KVM_GET_XCRS: {
4911 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4912 r = -ENOMEM;
4913 if (!u.xcrs)
4914 break;
4915
4916 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4917
4918 r = -EFAULT;
4919 if (copy_to_user(argp, u.xcrs,
4920 sizeof(struct kvm_xcrs)))
4921 break;
4922 r = 0;
4923 break;
4924 }
4925 case KVM_SET_XCRS: {
4926 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4927 if (IS_ERR(u.xcrs)) {
4928 r = PTR_ERR(u.xcrs);
4929 goto out_nofree;
4930 }
4931
4932 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4933 break;
4934 }
4935 case KVM_SET_TSC_KHZ: {
4936 u32 user_tsc_khz;
4937
4938 r = -EINVAL;
4939 user_tsc_khz = (u32)arg;
4940
4941 if (kvm_has_tsc_control &&
4942 user_tsc_khz >= kvm_max_guest_tsc_khz)
4943 goto out;
4944
4945 if (user_tsc_khz == 0)
4946 user_tsc_khz = tsc_khz;
4947
4948 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4949 r = 0;
4950
4951 goto out;
4952 }
4953 case KVM_GET_TSC_KHZ: {
4954 r = vcpu->arch.virtual_tsc_khz;
4955 goto out;
4956 }
4957 case KVM_KVMCLOCK_CTRL: {
4958 r = kvm_set_guest_paused(vcpu);
4959 goto out;
4960 }
4961 case KVM_ENABLE_CAP: {
4962 struct kvm_enable_cap cap;
4963
4964 r = -EFAULT;
4965 if (copy_from_user(&cap, argp, sizeof(cap)))
4966 goto out;
4967 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4968 break;
4969 }
4970 case KVM_GET_NESTED_STATE: {
4971 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4972 u32 user_data_size;
4973
4974 r = -EINVAL;
4975 if (!kvm_x86_ops.nested_ops->get_state)
4976 break;
4977
4978 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4979 r = -EFAULT;
4980 if (get_user(user_data_size, &user_kvm_nested_state->size))
4981 break;
4982
4983 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4984 user_data_size);
4985 if (r < 0)
4986 break;
4987
4988 if (r > user_data_size) {
4989 if (put_user(r, &user_kvm_nested_state->size))
4990 r = -EFAULT;
4991 else
4992 r = -E2BIG;
4993 break;
4994 }
4995
4996 r = 0;
4997 break;
4998 }
4999 case KVM_SET_NESTED_STATE: {
5000 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5001 struct kvm_nested_state kvm_state;
5002 int idx;
5003
5004 r = -EINVAL;
5005 if (!kvm_x86_ops.nested_ops->set_state)
5006 break;
5007
5008 r = -EFAULT;
5009 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5010 break;
5011
5012 r = -EINVAL;
5013 if (kvm_state.size < sizeof(kvm_state))
5014 break;
5015
5016 if (kvm_state.flags &
5017 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5018 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5019 | KVM_STATE_NESTED_GIF_SET))
5020 break;
5021
5022 /* nested_run_pending implies guest_mode. */
5023 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5024 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5025 break;
5026
5027 idx = srcu_read_lock(&vcpu->kvm->srcu);
5028 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5029 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5030 break;
5031 }
5032 case KVM_GET_SUPPORTED_HV_CPUID:
5033 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5034 break;
5035 default:
5036 r = -EINVAL;
5037 }
5038 out:
5039 kfree(u.buffer);
5040 out_nofree:
5041 vcpu_put(vcpu);
5042 return r;
5043 }
5044
5045 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5046 {
5047 return VM_FAULT_SIGBUS;
5048 }
5049
5050 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5051 {
5052 int ret;
5053
5054 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5055 return -EINVAL;
5056 ret = kvm_x86_ops.set_tss_addr(kvm, addr);
5057 return ret;
5058 }
5059
5060 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5061 u64 ident_addr)
5062 {
5063 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
5064 }
5065
5066 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5067 unsigned long kvm_nr_mmu_pages)
5068 {
5069 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5070 return -EINVAL;
5071
5072 mutex_lock(&kvm->slots_lock);
5073
5074 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5075 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5076
5077 mutex_unlock(&kvm->slots_lock);
5078 return 0;
5079 }
5080
5081 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5082 {
5083 return kvm->arch.n_max_mmu_pages;
5084 }
5085
5086 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5087 {
5088 struct kvm_pic *pic = kvm->arch.vpic;
5089 int r;
5090
5091 r = 0;
5092 switch (chip->chip_id) {
5093 case KVM_IRQCHIP_PIC_MASTER:
5094 memcpy(&chip->chip.pic, &pic->pics[0],
5095 sizeof(struct kvm_pic_state));
5096 break;
5097 case KVM_IRQCHIP_PIC_SLAVE:
5098 memcpy(&chip->chip.pic, &pic->pics[1],
5099 sizeof(struct kvm_pic_state));
5100 break;
5101 case KVM_IRQCHIP_IOAPIC:
5102 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5103 break;
5104 default:
5105 r = -EINVAL;
5106 break;
5107 }
5108 return r;
5109 }
5110
5111 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5112 {
5113 struct kvm_pic *pic = kvm->arch.vpic;
5114 int r;
5115
5116 r = 0;
5117 switch (chip->chip_id) {
5118 case KVM_IRQCHIP_PIC_MASTER:
5119 spin_lock(&pic->lock);
5120 memcpy(&pic->pics[0], &chip->chip.pic,
5121 sizeof(struct kvm_pic_state));
5122 spin_unlock(&pic->lock);
5123 break;
5124 case KVM_IRQCHIP_PIC_SLAVE:
5125 spin_lock(&pic->lock);
5126 memcpy(&pic->pics[1], &chip->chip.pic,
5127 sizeof(struct kvm_pic_state));
5128 spin_unlock(&pic->lock);
5129 break;
5130 case KVM_IRQCHIP_IOAPIC:
5131 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5132 break;
5133 default:
5134 r = -EINVAL;
5135 break;
5136 }
5137 kvm_pic_update_irq(pic);
5138 return r;
5139 }
5140
5141 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5142 {
5143 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5144
5145 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5146
5147 mutex_lock(&kps->lock);
5148 memcpy(ps, &kps->channels, sizeof(*ps));
5149 mutex_unlock(&kps->lock);
5150 return 0;
5151 }
5152
5153 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5154 {
5155 int i;
5156 struct kvm_pit *pit = kvm->arch.vpit;
5157
5158 mutex_lock(&pit->pit_state.lock);
5159 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5160 for (i = 0; i < 3; i++)
5161 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5162 mutex_unlock(&pit->pit_state.lock);
5163 return 0;
5164 }
5165
5166 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5167 {
5168 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5169 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5170 sizeof(ps->channels));
5171 ps->flags = kvm->arch.vpit->pit_state.flags;
5172 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5173 memset(&ps->reserved, 0, sizeof(ps->reserved));
5174 return 0;
5175 }
5176
5177 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5178 {
5179 int start = 0;
5180 int i;
5181 u32 prev_legacy, cur_legacy;
5182 struct kvm_pit *pit = kvm->arch.vpit;
5183
5184 mutex_lock(&pit->pit_state.lock);
5185 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5186 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5187 if (!prev_legacy && cur_legacy)
5188 start = 1;
5189 memcpy(&pit->pit_state.channels, &ps->channels,
5190 sizeof(pit->pit_state.channels));
5191 pit->pit_state.flags = ps->flags;
5192 for (i = 0; i < 3; i++)
5193 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5194 start && i == 0);
5195 mutex_unlock(&pit->pit_state.lock);
5196 return 0;
5197 }
5198
5199 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5200 struct kvm_reinject_control *control)
5201 {
5202 struct kvm_pit *pit = kvm->arch.vpit;
5203
5204 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5205 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5206 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5207 */
5208 mutex_lock(&pit->pit_state.lock);
5209 kvm_pit_set_reinject(pit, control->pit_reinject);
5210 mutex_unlock(&pit->pit_state.lock);
5211
5212 return 0;
5213 }
5214
5215 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5216 {
5217 /*
5218 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
5219 */
5220 if (kvm_x86_ops.flush_log_dirty)
5221 kvm_x86_ops.flush_log_dirty(kvm);
5222 }
5223
5224 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5225 bool line_status)
5226 {
5227 if (!irqchip_in_kernel(kvm))
5228 return -ENXIO;
5229
5230 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5231 irq_event->irq, irq_event->level,
5232 line_status);
5233 return 0;
5234 }
5235
5236 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5237 struct kvm_enable_cap *cap)
5238 {
5239 int r;
5240
5241 if (cap->flags)
5242 return -EINVAL;
5243
5244 switch (cap->cap) {
5245 case KVM_CAP_DISABLE_QUIRKS:
5246 kvm->arch.disabled_quirks = cap->args[0];
5247 r = 0;
5248 break;
5249 case KVM_CAP_SPLIT_IRQCHIP: {
5250 mutex_lock(&kvm->lock);
5251 r = -EINVAL;
5252 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5253 goto split_irqchip_unlock;
5254 r = -EEXIST;
5255 if (irqchip_in_kernel(kvm))
5256 goto split_irqchip_unlock;
5257 if (kvm->created_vcpus)
5258 goto split_irqchip_unlock;
5259 r = kvm_setup_empty_irq_routing(kvm);
5260 if (r)
5261 goto split_irqchip_unlock;
5262 /* Pairs with irqchip_in_kernel. */
5263 smp_wmb();
5264 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5265 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5266 r = 0;
5267 split_irqchip_unlock:
5268 mutex_unlock(&kvm->lock);
5269 break;
5270 }
5271 case KVM_CAP_X2APIC_API:
5272 r = -EINVAL;
5273 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5274 break;
5275
5276 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5277 kvm->arch.x2apic_format = true;
5278 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5279 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5280
5281 r = 0;
5282 break;
5283 case KVM_CAP_X86_DISABLE_EXITS:
5284 r = -EINVAL;
5285 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5286 break;
5287
5288 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5289 kvm_can_mwait_in_guest())
5290 kvm->arch.mwait_in_guest = true;
5291 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5292 kvm->arch.hlt_in_guest = true;
5293 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5294 kvm->arch.pause_in_guest = true;
5295 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5296 kvm->arch.cstate_in_guest = true;
5297 r = 0;
5298 break;
5299 case KVM_CAP_MSR_PLATFORM_INFO:
5300 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5301 r = 0;
5302 break;
5303 case KVM_CAP_EXCEPTION_PAYLOAD:
5304 kvm->arch.exception_payload_enabled = cap->args[0];
5305 r = 0;
5306 break;
5307 case KVM_CAP_X86_USER_SPACE_MSR:
5308 kvm->arch.user_space_msr_mask = cap->args[0];
5309 r = 0;
5310 break;
5311 default:
5312 r = -EINVAL;
5313 break;
5314 }
5315 return r;
5316 }
5317
5318 static void kvm_clear_msr_filter(struct kvm *kvm)
5319 {
5320 u32 i;
5321 u32 count = kvm->arch.msr_filter.count;
5322 struct msr_bitmap_range ranges[16];
5323
5324 mutex_lock(&kvm->lock);
5325 kvm->arch.msr_filter.count = 0;
5326 memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0]));
5327 mutex_unlock(&kvm->lock);
5328 synchronize_srcu(&kvm->srcu);
5329
5330 for (i = 0; i < count; i++)
5331 kfree(ranges[i].bitmap);
5332 }
5333
5334 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range)
5335 {
5336 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
5337 struct msr_bitmap_range range;
5338 unsigned long *bitmap = NULL;
5339 size_t bitmap_size;
5340 int r;
5341
5342 if (!user_range->nmsrs)
5343 return 0;
5344
5345 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5346 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5347 return -EINVAL;
5348
5349 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5350 if (IS_ERR(bitmap))
5351 return PTR_ERR(bitmap);
5352
5353 range = (struct msr_bitmap_range) {
5354 .flags = user_range->flags,
5355 .base = user_range->base,
5356 .nmsrs = user_range->nmsrs,
5357 .bitmap = bitmap,
5358 };
5359
5360 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5361 r = -EINVAL;
5362 goto err;
5363 }
5364
5365 if (!range.flags) {
5366 r = -EINVAL;
5367 goto err;
5368 }
5369
5370 /* Everything ok, add this range identifier to our global pool */
5371 ranges[kvm->arch.msr_filter.count] = range;
5372 /* Make sure we filled the array before we tell anyone to walk it */
5373 smp_wmb();
5374 kvm->arch.msr_filter.count++;
5375
5376 return 0;
5377 err:
5378 kfree(bitmap);
5379 return r;
5380 }
5381
5382 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5383 {
5384 struct kvm_msr_filter __user *user_msr_filter = argp;
5385 struct kvm_msr_filter filter;
5386 bool default_allow;
5387 int r = 0;
5388 bool empty = true;
5389 u32 i;
5390
5391 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5392 return -EFAULT;
5393
5394 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5395 empty &= !filter.ranges[i].nmsrs;
5396
5397 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5398 if (empty && !default_allow)
5399 return -EINVAL;
5400
5401 kvm_clear_msr_filter(kvm);
5402
5403 kvm->arch.msr_filter.default_allow = default_allow;
5404
5405 /*
5406 * Protect from concurrent calls to this function that could trigger
5407 * a TOCTOU violation on kvm->arch.msr_filter.count.
5408 */
5409 mutex_lock(&kvm->lock);
5410 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5411 r = kvm_add_msr_filter(kvm, &filter.ranges[i]);
5412 if (r)
5413 break;
5414 }
5415
5416 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5417 mutex_unlock(&kvm->lock);
5418
5419 return r;
5420 }
5421
5422 long kvm_arch_vm_ioctl(struct file *filp,
5423 unsigned int ioctl, unsigned long arg)
5424 {
5425 struct kvm *kvm = filp->private_data;
5426 void __user *argp = (void __user *)arg;
5427 int r = -ENOTTY;
5428 /*
5429 * This union makes it completely explicit to gcc-3.x
5430 * that these two variables' stack usage should be
5431 * combined, not added together.
5432 */
5433 union {
5434 struct kvm_pit_state ps;
5435 struct kvm_pit_state2 ps2;
5436 struct kvm_pit_config pit_config;
5437 } u;
5438
5439 switch (ioctl) {
5440 case KVM_SET_TSS_ADDR:
5441 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5442 break;
5443 case KVM_SET_IDENTITY_MAP_ADDR: {
5444 u64 ident_addr;
5445
5446 mutex_lock(&kvm->lock);
5447 r = -EINVAL;
5448 if (kvm->created_vcpus)
5449 goto set_identity_unlock;
5450 r = -EFAULT;
5451 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5452 goto set_identity_unlock;
5453 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5454 set_identity_unlock:
5455 mutex_unlock(&kvm->lock);
5456 break;
5457 }
5458 case KVM_SET_NR_MMU_PAGES:
5459 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5460 break;
5461 case KVM_GET_NR_MMU_PAGES:
5462 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5463 break;
5464 case KVM_CREATE_IRQCHIP: {
5465 mutex_lock(&kvm->lock);
5466
5467 r = -EEXIST;
5468 if (irqchip_in_kernel(kvm))
5469 goto create_irqchip_unlock;
5470
5471 r = -EINVAL;
5472 if (kvm->created_vcpus)
5473 goto create_irqchip_unlock;
5474
5475 r = kvm_pic_init(kvm);
5476 if (r)
5477 goto create_irqchip_unlock;
5478
5479 r = kvm_ioapic_init(kvm);
5480 if (r) {
5481 kvm_pic_destroy(kvm);
5482 goto create_irqchip_unlock;
5483 }
5484
5485 r = kvm_setup_default_irq_routing(kvm);
5486 if (r) {
5487 kvm_ioapic_destroy(kvm);
5488 kvm_pic_destroy(kvm);
5489 goto create_irqchip_unlock;
5490 }
5491 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5492 smp_wmb();
5493 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5494 create_irqchip_unlock:
5495 mutex_unlock(&kvm->lock);
5496 break;
5497 }
5498 case KVM_CREATE_PIT:
5499 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5500 goto create_pit;
5501 case KVM_CREATE_PIT2:
5502 r = -EFAULT;
5503 if (copy_from_user(&u.pit_config, argp,
5504 sizeof(struct kvm_pit_config)))
5505 goto out;
5506 create_pit:
5507 mutex_lock(&kvm->lock);
5508 r = -EEXIST;
5509 if (kvm->arch.vpit)
5510 goto create_pit_unlock;
5511 r = -ENOMEM;
5512 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5513 if (kvm->arch.vpit)
5514 r = 0;
5515 create_pit_unlock:
5516 mutex_unlock(&kvm->lock);
5517 break;
5518 case KVM_GET_IRQCHIP: {
5519 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5520 struct kvm_irqchip *chip;
5521
5522 chip = memdup_user(argp, sizeof(*chip));
5523 if (IS_ERR(chip)) {
5524 r = PTR_ERR(chip);
5525 goto out;
5526 }
5527
5528 r = -ENXIO;
5529 if (!irqchip_kernel(kvm))
5530 goto get_irqchip_out;
5531 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5532 if (r)
5533 goto get_irqchip_out;
5534 r = -EFAULT;
5535 if (copy_to_user(argp, chip, sizeof(*chip)))
5536 goto get_irqchip_out;
5537 r = 0;
5538 get_irqchip_out:
5539 kfree(chip);
5540 break;
5541 }
5542 case KVM_SET_IRQCHIP: {
5543 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5544 struct kvm_irqchip *chip;
5545
5546 chip = memdup_user(argp, sizeof(*chip));
5547 if (IS_ERR(chip)) {
5548 r = PTR_ERR(chip);
5549 goto out;
5550 }
5551
5552 r = -ENXIO;
5553 if (!irqchip_kernel(kvm))
5554 goto set_irqchip_out;
5555 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5556 set_irqchip_out:
5557 kfree(chip);
5558 break;
5559 }
5560 case KVM_GET_PIT: {
5561 r = -EFAULT;
5562 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5563 goto out;
5564 r = -ENXIO;
5565 if (!kvm->arch.vpit)
5566 goto out;
5567 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5568 if (r)
5569 goto out;
5570 r = -EFAULT;
5571 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5572 goto out;
5573 r = 0;
5574 break;
5575 }
5576 case KVM_SET_PIT: {
5577 r = -EFAULT;
5578 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5579 goto out;
5580 mutex_lock(&kvm->lock);
5581 r = -ENXIO;
5582 if (!kvm->arch.vpit)
5583 goto set_pit_out;
5584 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5585 set_pit_out:
5586 mutex_unlock(&kvm->lock);
5587 break;
5588 }
5589 case KVM_GET_PIT2: {
5590 r = -ENXIO;
5591 if (!kvm->arch.vpit)
5592 goto out;
5593 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5594 if (r)
5595 goto out;
5596 r = -EFAULT;
5597 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5598 goto out;
5599 r = 0;
5600 break;
5601 }
5602 case KVM_SET_PIT2: {
5603 r = -EFAULT;
5604 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5605 goto out;
5606 mutex_lock(&kvm->lock);
5607 r = -ENXIO;
5608 if (!kvm->arch.vpit)
5609 goto set_pit2_out;
5610 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5611 set_pit2_out:
5612 mutex_unlock(&kvm->lock);
5613 break;
5614 }
5615 case KVM_REINJECT_CONTROL: {
5616 struct kvm_reinject_control control;
5617 r = -EFAULT;
5618 if (copy_from_user(&control, argp, sizeof(control)))
5619 goto out;
5620 r = -ENXIO;
5621 if (!kvm->arch.vpit)
5622 goto out;
5623 r = kvm_vm_ioctl_reinject(kvm, &control);
5624 break;
5625 }
5626 case KVM_SET_BOOT_CPU_ID:
5627 r = 0;
5628 mutex_lock(&kvm->lock);
5629 if (kvm->created_vcpus)
5630 r = -EBUSY;
5631 else
5632 kvm->arch.bsp_vcpu_id = arg;
5633 mutex_unlock(&kvm->lock);
5634 break;
5635 case KVM_XEN_HVM_CONFIG: {
5636 struct kvm_xen_hvm_config xhc;
5637 r = -EFAULT;
5638 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5639 goto out;
5640 r = -EINVAL;
5641 if (xhc.flags)
5642 goto out;
5643 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5644 r = 0;
5645 break;
5646 }
5647 case KVM_SET_CLOCK: {
5648 struct kvm_clock_data user_ns;
5649 u64 now_ns;
5650
5651 r = -EFAULT;
5652 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5653 goto out;
5654
5655 r = -EINVAL;
5656 if (user_ns.flags)
5657 goto out;
5658
5659 r = 0;
5660 /*
5661 * TODO: userspace has to take care of races with VCPU_RUN, so
5662 * kvm_gen_update_masterclock() can be cut down to locked
5663 * pvclock_update_vm_gtod_copy().
5664 */
5665 kvm_gen_update_masterclock(kvm);
5666 now_ns = get_kvmclock_ns(kvm);
5667 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5668 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5669 break;
5670 }
5671 case KVM_GET_CLOCK: {
5672 struct kvm_clock_data user_ns;
5673 u64 now_ns;
5674
5675 now_ns = get_kvmclock_ns(kvm);
5676 user_ns.clock = now_ns;
5677 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5678 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5679
5680 r = -EFAULT;
5681 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5682 goto out;
5683 r = 0;
5684 break;
5685 }
5686 case KVM_MEMORY_ENCRYPT_OP: {
5687 r = -ENOTTY;
5688 if (kvm_x86_ops.mem_enc_op)
5689 r = kvm_x86_ops.mem_enc_op(kvm, argp);
5690 break;
5691 }
5692 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5693 struct kvm_enc_region region;
5694
5695 r = -EFAULT;
5696 if (copy_from_user(&region, argp, sizeof(region)))
5697 goto out;
5698
5699 r = -ENOTTY;
5700 if (kvm_x86_ops.mem_enc_reg_region)
5701 r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5702 break;
5703 }
5704 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5705 struct kvm_enc_region region;
5706
5707 r = -EFAULT;
5708 if (copy_from_user(&region, argp, sizeof(region)))
5709 goto out;
5710
5711 r = -ENOTTY;
5712 if (kvm_x86_ops.mem_enc_unreg_region)
5713 r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5714 break;
5715 }
5716 case KVM_HYPERV_EVENTFD: {
5717 struct kvm_hyperv_eventfd hvevfd;
5718
5719 r = -EFAULT;
5720 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5721 goto out;
5722 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5723 break;
5724 }
5725 case KVM_SET_PMU_EVENT_FILTER:
5726 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5727 break;
5728 case KVM_X86_SET_MSR_FILTER:
5729 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5730 break;
5731 default:
5732 r = -ENOTTY;
5733 }
5734 out:
5735 return r;
5736 }
5737
5738 static void kvm_init_msr_list(void)
5739 {
5740 struct x86_pmu_capability x86_pmu;
5741 u32 dummy[2];
5742 unsigned i;
5743
5744 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5745 "Please update the fixed PMCs in msrs_to_saved_all[]");
5746
5747 perf_get_x86_pmu_capability(&x86_pmu);
5748
5749 num_msrs_to_save = 0;
5750 num_emulated_msrs = 0;
5751 num_msr_based_features = 0;
5752
5753 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5754 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5755 continue;
5756
5757 /*
5758 * Even MSRs that are valid in the host may not be exposed
5759 * to the guests in some cases.
5760 */
5761 switch (msrs_to_save_all[i]) {
5762 case MSR_IA32_BNDCFGS:
5763 if (!kvm_mpx_supported())
5764 continue;
5765 break;
5766 case MSR_TSC_AUX:
5767 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5768 continue;
5769 break;
5770 case MSR_IA32_UMWAIT_CONTROL:
5771 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5772 continue;
5773 break;
5774 case MSR_IA32_RTIT_CTL:
5775 case MSR_IA32_RTIT_STATUS:
5776 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5777 continue;
5778 break;
5779 case MSR_IA32_RTIT_CR3_MATCH:
5780 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5781 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5782 continue;
5783 break;
5784 case MSR_IA32_RTIT_OUTPUT_BASE:
5785 case MSR_IA32_RTIT_OUTPUT_MASK:
5786 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5787 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5788 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5789 continue;
5790 break;
5791 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5792 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5793 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5794 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5795 continue;
5796 break;
5797 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5798 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5799 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5800 continue;
5801 break;
5802 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5803 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5804 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5805 continue;
5806 break;
5807 default:
5808 break;
5809 }
5810
5811 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5812 }
5813
5814 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5815 if (!kvm_x86_ops.has_emulated_msr(NULL, emulated_msrs_all[i]))
5816 continue;
5817
5818 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5819 }
5820
5821 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5822 struct kvm_msr_entry msr;
5823
5824 msr.index = msr_based_features_all[i];
5825 if (kvm_get_msr_feature(&msr))
5826 continue;
5827
5828 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5829 }
5830 }
5831
5832 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5833 const void *v)
5834 {
5835 int handled = 0;
5836 int n;
5837
5838 do {
5839 n = min(len, 8);
5840 if (!(lapic_in_kernel(vcpu) &&
5841 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5842 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5843 break;
5844 handled += n;
5845 addr += n;
5846 len -= n;
5847 v += n;
5848 } while (len);
5849
5850 return handled;
5851 }
5852
5853 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5854 {
5855 int handled = 0;
5856 int n;
5857
5858 do {
5859 n = min(len, 8);
5860 if (!(lapic_in_kernel(vcpu) &&
5861 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5862 addr, n, v))
5863 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5864 break;
5865 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5866 handled += n;
5867 addr += n;
5868 len -= n;
5869 v += n;
5870 } while (len);
5871
5872 return handled;
5873 }
5874
5875 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5876 struct kvm_segment *var, int seg)
5877 {
5878 kvm_x86_ops.set_segment(vcpu, var, seg);
5879 }
5880
5881 void kvm_get_segment(struct kvm_vcpu *vcpu,
5882 struct kvm_segment *var, int seg)
5883 {
5884 kvm_x86_ops.get_segment(vcpu, var, seg);
5885 }
5886
5887 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5888 struct x86_exception *exception)
5889 {
5890 gpa_t t_gpa;
5891
5892 BUG_ON(!mmu_is_nested(vcpu));
5893
5894 /* NPT walks are always user-walks */
5895 access |= PFERR_USER_MASK;
5896 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5897
5898 return t_gpa;
5899 }
5900
5901 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5902 struct x86_exception *exception)
5903 {
5904 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5905 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5906 }
5907
5908 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5909 struct x86_exception *exception)
5910 {
5911 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5912 access |= PFERR_FETCH_MASK;
5913 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5914 }
5915
5916 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5917 struct x86_exception *exception)
5918 {
5919 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5920 access |= PFERR_WRITE_MASK;
5921 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5922 }
5923
5924 /* uses this to access any guest's mapped memory without checking CPL */
5925 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5926 struct x86_exception *exception)
5927 {
5928 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5929 }
5930
5931 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5932 struct kvm_vcpu *vcpu, u32 access,
5933 struct x86_exception *exception)
5934 {
5935 void *data = val;
5936 int r = X86EMUL_CONTINUE;
5937
5938 while (bytes) {
5939 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5940 exception);
5941 unsigned offset = addr & (PAGE_SIZE-1);
5942 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5943 int ret;
5944
5945 if (gpa == UNMAPPED_GVA)
5946 return X86EMUL_PROPAGATE_FAULT;
5947 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5948 offset, toread);
5949 if (ret < 0) {
5950 r = X86EMUL_IO_NEEDED;
5951 goto out;
5952 }
5953
5954 bytes -= toread;
5955 data += toread;
5956 addr += toread;
5957 }
5958 out:
5959 return r;
5960 }
5961
5962 /* used for instruction fetching */
5963 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5964 gva_t addr, void *val, unsigned int bytes,
5965 struct x86_exception *exception)
5966 {
5967 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5968 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5969 unsigned offset;
5970 int ret;
5971
5972 /* Inline kvm_read_guest_virt_helper for speed. */
5973 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5974 exception);
5975 if (unlikely(gpa == UNMAPPED_GVA))
5976 return X86EMUL_PROPAGATE_FAULT;
5977
5978 offset = addr & (PAGE_SIZE-1);
5979 if (WARN_ON(offset + bytes > PAGE_SIZE))
5980 bytes = (unsigned)PAGE_SIZE - offset;
5981 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5982 offset, bytes);
5983 if (unlikely(ret < 0))
5984 return X86EMUL_IO_NEEDED;
5985
5986 return X86EMUL_CONTINUE;
5987 }
5988
5989 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5990 gva_t addr, void *val, unsigned int bytes,
5991 struct x86_exception *exception)
5992 {
5993 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5994
5995 /*
5996 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5997 * is returned, but our callers are not ready for that and they blindly
5998 * call kvm_inject_page_fault. Ensure that they at least do not leak
5999 * uninitialized kernel stack memory into cr2 and error code.
6000 */
6001 memset(exception, 0, sizeof(*exception));
6002 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
6003 exception);
6004 }
6005 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
6006
6007 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
6008 gva_t addr, void *val, unsigned int bytes,
6009 struct x86_exception *exception, bool system)
6010 {
6011 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6012 u32 access = 0;
6013
6014 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6015 access |= PFERR_USER_MASK;
6016
6017 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
6018 }
6019
6020 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
6021 unsigned long addr, void *val, unsigned int bytes)
6022 {
6023 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6024 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
6025
6026 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
6027 }
6028
6029 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6030 struct kvm_vcpu *vcpu, u32 access,
6031 struct x86_exception *exception)
6032 {
6033 void *data = val;
6034 int r = X86EMUL_CONTINUE;
6035
6036 while (bytes) {
6037 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
6038 access,
6039 exception);
6040 unsigned offset = addr & (PAGE_SIZE-1);
6041 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6042 int ret;
6043
6044 if (gpa == UNMAPPED_GVA)
6045 return X86EMUL_PROPAGATE_FAULT;
6046 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6047 if (ret < 0) {
6048 r = X86EMUL_IO_NEEDED;
6049 goto out;
6050 }
6051
6052 bytes -= towrite;
6053 data += towrite;
6054 addr += towrite;
6055 }
6056 out:
6057 return r;
6058 }
6059
6060 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6061 unsigned int bytes, struct x86_exception *exception,
6062 bool system)
6063 {
6064 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6065 u32 access = PFERR_WRITE_MASK;
6066
6067 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6068 access |= PFERR_USER_MASK;
6069
6070 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6071 access, exception);
6072 }
6073
6074 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6075 unsigned int bytes, struct x86_exception *exception)
6076 {
6077 /* kvm_write_guest_virt_system can pull in tons of pages. */
6078 vcpu->arch.l1tf_flush_l1d = true;
6079
6080 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6081 PFERR_WRITE_MASK, exception);
6082 }
6083 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6084
6085 int handle_ud(struct kvm_vcpu *vcpu)
6086 {
6087 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6088 int emul_type = EMULTYPE_TRAP_UD;
6089 char sig[5]; /* ud2; .ascii "kvm" */
6090 struct x86_exception e;
6091
6092 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0)))
6093 return 1;
6094
6095 if (force_emulation_prefix &&
6096 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6097 sig, sizeof(sig), &e) == 0 &&
6098 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6099 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6100 emul_type = EMULTYPE_TRAP_UD_FORCED;
6101 }
6102
6103 return kvm_emulate_instruction(vcpu, emul_type);
6104 }
6105 EXPORT_SYMBOL_GPL(handle_ud);
6106
6107 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6108 gpa_t gpa, bool write)
6109 {
6110 /* For APIC access vmexit */
6111 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6112 return 1;
6113
6114 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6115 trace_vcpu_match_mmio(gva, gpa, write, true);
6116 return 1;
6117 }
6118
6119 return 0;
6120 }
6121
6122 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6123 gpa_t *gpa, struct x86_exception *exception,
6124 bool write)
6125 {
6126 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
6127 | (write ? PFERR_WRITE_MASK : 0);
6128
6129 /*
6130 * currently PKRU is only applied to ept enabled guest so
6131 * there is no pkey in EPT page table for L1 guest or EPT
6132 * shadow page table for L2 guest.
6133 */
6134 if (vcpu_match_mmio_gva(vcpu, gva)
6135 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6136 vcpu->arch.mmio_access, 0, access)) {
6137 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6138 (gva & (PAGE_SIZE - 1));
6139 trace_vcpu_match_mmio(gva, *gpa, write, false);
6140 return 1;
6141 }
6142
6143 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6144
6145 if (*gpa == UNMAPPED_GVA)
6146 return -1;
6147
6148 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6149 }
6150
6151 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6152 const void *val, int bytes)
6153 {
6154 int ret;
6155
6156 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6157 if (ret < 0)
6158 return 0;
6159 kvm_page_track_write(vcpu, gpa, val, bytes);
6160 return 1;
6161 }
6162
6163 struct read_write_emulator_ops {
6164 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6165 int bytes);
6166 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6167 void *val, int bytes);
6168 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6169 int bytes, void *val);
6170 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6171 void *val, int bytes);
6172 bool write;
6173 };
6174
6175 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6176 {
6177 if (vcpu->mmio_read_completed) {
6178 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6179 vcpu->mmio_fragments[0].gpa, val);
6180 vcpu->mmio_read_completed = 0;
6181 return 1;
6182 }
6183
6184 return 0;
6185 }
6186
6187 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6188 void *val, int bytes)
6189 {
6190 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6191 }
6192
6193 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6194 void *val, int bytes)
6195 {
6196 return emulator_write_phys(vcpu, gpa, val, bytes);
6197 }
6198
6199 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6200 {
6201 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6202 return vcpu_mmio_write(vcpu, gpa, bytes, val);
6203 }
6204
6205 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6206 void *val, int bytes)
6207 {
6208 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6209 return X86EMUL_IO_NEEDED;
6210 }
6211
6212 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6213 void *val, int bytes)
6214 {
6215 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6216
6217 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6218 return X86EMUL_CONTINUE;
6219 }
6220
6221 static const struct read_write_emulator_ops read_emultor = {
6222 .read_write_prepare = read_prepare,
6223 .read_write_emulate = read_emulate,
6224 .read_write_mmio = vcpu_mmio_read,
6225 .read_write_exit_mmio = read_exit_mmio,
6226 };
6227
6228 static const struct read_write_emulator_ops write_emultor = {
6229 .read_write_emulate = write_emulate,
6230 .read_write_mmio = write_mmio,
6231 .read_write_exit_mmio = write_exit_mmio,
6232 .write = true,
6233 };
6234
6235 static int emulator_read_write_onepage(unsigned long addr, void *val,
6236 unsigned int bytes,
6237 struct x86_exception *exception,
6238 struct kvm_vcpu *vcpu,
6239 const struct read_write_emulator_ops *ops)
6240 {
6241 gpa_t gpa;
6242 int handled, ret;
6243 bool write = ops->write;
6244 struct kvm_mmio_fragment *frag;
6245 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6246
6247 /*
6248 * If the exit was due to a NPF we may already have a GPA.
6249 * If the GPA is present, use it to avoid the GVA to GPA table walk.
6250 * Note, this cannot be used on string operations since string
6251 * operation using rep will only have the initial GPA from the NPF
6252 * occurred.
6253 */
6254 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6255 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6256 gpa = ctxt->gpa_val;
6257 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6258 } else {
6259 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6260 if (ret < 0)
6261 return X86EMUL_PROPAGATE_FAULT;
6262 }
6263
6264 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6265 return X86EMUL_CONTINUE;
6266
6267 /*
6268 * Is this MMIO handled locally?
6269 */
6270 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6271 if (handled == bytes)
6272 return X86EMUL_CONTINUE;
6273
6274 gpa += handled;
6275 bytes -= handled;
6276 val += handled;
6277
6278 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6279 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6280 frag->gpa = gpa;
6281 frag->data = val;
6282 frag->len = bytes;
6283 return X86EMUL_CONTINUE;
6284 }
6285
6286 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6287 unsigned long addr,
6288 void *val, unsigned int bytes,
6289 struct x86_exception *exception,
6290 const struct read_write_emulator_ops *ops)
6291 {
6292 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6293 gpa_t gpa;
6294 int rc;
6295
6296 if (ops->read_write_prepare &&
6297 ops->read_write_prepare(vcpu, val, bytes))
6298 return X86EMUL_CONTINUE;
6299
6300 vcpu->mmio_nr_fragments = 0;
6301
6302 /* Crossing a page boundary? */
6303 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6304 int now;
6305
6306 now = -addr & ~PAGE_MASK;
6307 rc = emulator_read_write_onepage(addr, val, now, exception,
6308 vcpu, ops);
6309
6310 if (rc != X86EMUL_CONTINUE)
6311 return rc;
6312 addr += now;
6313 if (ctxt->mode != X86EMUL_MODE_PROT64)
6314 addr = (u32)addr;
6315 val += now;
6316 bytes -= now;
6317 }
6318
6319 rc = emulator_read_write_onepage(addr, val, bytes, exception,
6320 vcpu, ops);
6321 if (rc != X86EMUL_CONTINUE)
6322 return rc;
6323
6324 if (!vcpu->mmio_nr_fragments)
6325 return rc;
6326
6327 gpa = vcpu->mmio_fragments[0].gpa;
6328
6329 vcpu->mmio_needed = 1;
6330 vcpu->mmio_cur_fragment = 0;
6331
6332 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6333 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6334 vcpu->run->exit_reason = KVM_EXIT_MMIO;
6335 vcpu->run->mmio.phys_addr = gpa;
6336
6337 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6338 }
6339
6340 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6341 unsigned long addr,
6342 void *val,
6343 unsigned int bytes,
6344 struct x86_exception *exception)
6345 {
6346 return emulator_read_write(ctxt, addr, val, bytes,
6347 exception, &read_emultor);
6348 }
6349
6350 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6351 unsigned long addr,
6352 const void *val,
6353 unsigned int bytes,
6354 struct x86_exception *exception)
6355 {
6356 return emulator_read_write(ctxt, addr, (void *)val, bytes,
6357 exception, &write_emultor);
6358 }
6359
6360 #define CMPXCHG_TYPE(t, ptr, old, new) \
6361 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6362
6363 #ifdef CONFIG_X86_64
6364 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6365 #else
6366 # define CMPXCHG64(ptr, old, new) \
6367 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6368 #endif
6369
6370 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6371 unsigned long addr,
6372 const void *old,
6373 const void *new,
6374 unsigned int bytes,
6375 struct x86_exception *exception)
6376 {
6377 struct kvm_host_map map;
6378 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6379 u64 page_line_mask;
6380 gpa_t gpa;
6381 char *kaddr;
6382 bool exchanged;
6383
6384 /* guests cmpxchg8b have to be emulated atomically */
6385 if (bytes > 8 || (bytes & (bytes - 1)))
6386 goto emul_write;
6387
6388 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6389
6390 if (gpa == UNMAPPED_GVA ||
6391 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6392 goto emul_write;
6393
6394 /*
6395 * Emulate the atomic as a straight write to avoid #AC if SLD is
6396 * enabled in the host and the access splits a cache line.
6397 */
6398 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6399 page_line_mask = ~(cache_line_size() - 1);
6400 else
6401 page_line_mask = PAGE_MASK;
6402
6403 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6404 goto emul_write;
6405
6406 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6407 goto emul_write;
6408
6409 kaddr = map.hva + offset_in_page(gpa);
6410
6411 switch (bytes) {
6412 case 1:
6413 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6414 break;
6415 case 2:
6416 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6417 break;
6418 case 4:
6419 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6420 break;
6421 case 8:
6422 exchanged = CMPXCHG64(kaddr, old, new);
6423 break;
6424 default:
6425 BUG();
6426 }
6427
6428 kvm_vcpu_unmap(vcpu, &map, true);
6429
6430 if (!exchanged)
6431 return X86EMUL_CMPXCHG_FAILED;
6432
6433 kvm_page_track_write(vcpu, gpa, new, bytes);
6434
6435 return X86EMUL_CONTINUE;
6436
6437 emul_write:
6438 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6439
6440 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6441 }
6442
6443 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6444 {
6445 int r = 0, i;
6446
6447 for (i = 0; i < vcpu->arch.pio.count; i++) {
6448 if (vcpu->arch.pio.in)
6449 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6450 vcpu->arch.pio.size, pd);
6451 else
6452 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6453 vcpu->arch.pio.port, vcpu->arch.pio.size,
6454 pd);
6455 if (r)
6456 break;
6457 pd += vcpu->arch.pio.size;
6458 }
6459 return r;
6460 }
6461
6462 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6463 unsigned short port, void *val,
6464 unsigned int count, bool in)
6465 {
6466 vcpu->arch.pio.port = port;
6467 vcpu->arch.pio.in = in;
6468 vcpu->arch.pio.count = count;
6469 vcpu->arch.pio.size = size;
6470
6471 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6472 vcpu->arch.pio.count = 0;
6473 return 1;
6474 }
6475
6476 vcpu->run->exit_reason = KVM_EXIT_IO;
6477 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6478 vcpu->run->io.size = size;
6479 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6480 vcpu->run->io.count = count;
6481 vcpu->run->io.port = port;
6482
6483 return 0;
6484 }
6485
6486 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6487 unsigned short port, void *val, unsigned int count)
6488 {
6489 int ret;
6490
6491 if (vcpu->arch.pio.count)
6492 goto data_avail;
6493
6494 memset(vcpu->arch.pio_data, 0, size * count);
6495
6496 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6497 if (ret) {
6498 data_avail:
6499 memcpy(val, vcpu->arch.pio_data, size * count);
6500 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6501 vcpu->arch.pio.count = 0;
6502 return 1;
6503 }
6504
6505 return 0;
6506 }
6507
6508 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6509 int size, unsigned short port, void *val,
6510 unsigned int count)
6511 {
6512 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6513
6514 }
6515
6516 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6517 unsigned short port, const void *val,
6518 unsigned int count)
6519 {
6520 memcpy(vcpu->arch.pio_data, val, size * count);
6521 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6522 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6523 }
6524
6525 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6526 int size, unsigned short port,
6527 const void *val, unsigned int count)
6528 {
6529 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6530 }
6531
6532 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6533 {
6534 return kvm_x86_ops.get_segment_base(vcpu, seg);
6535 }
6536
6537 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6538 {
6539 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6540 }
6541
6542 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6543 {
6544 if (!need_emulate_wbinvd(vcpu))
6545 return X86EMUL_CONTINUE;
6546
6547 if (kvm_x86_ops.has_wbinvd_exit()) {
6548 int cpu = get_cpu();
6549
6550 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6551 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6552 wbinvd_ipi, NULL, 1);
6553 put_cpu();
6554 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6555 } else
6556 wbinvd();
6557 return X86EMUL_CONTINUE;
6558 }
6559
6560 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6561 {
6562 kvm_emulate_wbinvd_noskip(vcpu);
6563 return kvm_skip_emulated_instruction(vcpu);
6564 }
6565 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6566
6567
6568
6569 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6570 {
6571 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6572 }
6573
6574 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6575 unsigned long *dest)
6576 {
6577 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6578 }
6579
6580 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6581 unsigned long value)
6582 {
6583
6584 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6585 }
6586
6587 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6588 {
6589 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6590 }
6591
6592 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6593 {
6594 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6595 unsigned long value;
6596
6597 switch (cr) {
6598 case 0:
6599 value = kvm_read_cr0(vcpu);
6600 break;
6601 case 2:
6602 value = vcpu->arch.cr2;
6603 break;
6604 case 3:
6605 value = kvm_read_cr3(vcpu);
6606 break;
6607 case 4:
6608 value = kvm_read_cr4(vcpu);
6609 break;
6610 case 8:
6611 value = kvm_get_cr8(vcpu);
6612 break;
6613 default:
6614 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6615 return 0;
6616 }
6617
6618 return value;
6619 }
6620
6621 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6622 {
6623 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6624 int res = 0;
6625
6626 switch (cr) {
6627 case 0:
6628 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6629 break;
6630 case 2:
6631 vcpu->arch.cr2 = val;
6632 break;
6633 case 3:
6634 res = kvm_set_cr3(vcpu, val);
6635 break;
6636 case 4:
6637 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6638 break;
6639 case 8:
6640 res = kvm_set_cr8(vcpu, val);
6641 break;
6642 default:
6643 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6644 res = -1;
6645 }
6646
6647 return res;
6648 }
6649
6650 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6651 {
6652 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6653 }
6654
6655 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6656 {
6657 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6658 }
6659
6660 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6661 {
6662 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6663 }
6664
6665 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6666 {
6667 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6668 }
6669
6670 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6671 {
6672 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6673 }
6674
6675 static unsigned long emulator_get_cached_segment_base(
6676 struct x86_emulate_ctxt *ctxt, int seg)
6677 {
6678 return get_segment_base(emul_to_vcpu(ctxt), seg);
6679 }
6680
6681 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6682 struct desc_struct *desc, u32 *base3,
6683 int seg)
6684 {
6685 struct kvm_segment var;
6686
6687 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6688 *selector = var.selector;
6689
6690 if (var.unusable) {
6691 memset(desc, 0, sizeof(*desc));
6692 if (base3)
6693 *base3 = 0;
6694 return false;
6695 }
6696
6697 if (var.g)
6698 var.limit >>= 12;
6699 set_desc_limit(desc, var.limit);
6700 set_desc_base(desc, (unsigned long)var.base);
6701 #ifdef CONFIG_X86_64
6702 if (base3)
6703 *base3 = var.base >> 32;
6704 #endif
6705 desc->type = var.type;
6706 desc->s = var.s;
6707 desc->dpl = var.dpl;
6708 desc->p = var.present;
6709 desc->avl = var.avl;
6710 desc->l = var.l;
6711 desc->d = var.db;
6712 desc->g = var.g;
6713
6714 return true;
6715 }
6716
6717 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6718 struct desc_struct *desc, u32 base3,
6719 int seg)
6720 {
6721 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6722 struct kvm_segment var;
6723
6724 var.selector = selector;
6725 var.base = get_desc_base(desc);
6726 #ifdef CONFIG_X86_64
6727 var.base |= ((u64)base3) << 32;
6728 #endif
6729 var.limit = get_desc_limit(desc);
6730 if (desc->g)
6731 var.limit = (var.limit << 12) | 0xfff;
6732 var.type = desc->type;
6733 var.dpl = desc->dpl;
6734 var.db = desc->d;
6735 var.s = desc->s;
6736 var.l = desc->l;
6737 var.g = desc->g;
6738 var.avl = desc->avl;
6739 var.present = desc->p;
6740 var.unusable = !var.present;
6741 var.padding = 0;
6742
6743 kvm_set_segment(vcpu, &var, seg);
6744 return;
6745 }
6746
6747 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6748 u32 msr_index, u64 *pdata)
6749 {
6750 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6751 int r;
6752
6753 r = kvm_get_msr(vcpu, msr_index, pdata);
6754
6755 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6756 /* Bounce to user space */
6757 return X86EMUL_IO_NEEDED;
6758 }
6759
6760 return r;
6761 }
6762
6763 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6764 u32 msr_index, u64 data)
6765 {
6766 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6767 int r;
6768
6769 r = kvm_set_msr(vcpu, msr_index, data);
6770
6771 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6772 /* Bounce to user space */
6773 return X86EMUL_IO_NEEDED;
6774 }
6775
6776 return r;
6777 }
6778
6779 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6780 {
6781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6782
6783 return vcpu->arch.smbase;
6784 }
6785
6786 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6787 {
6788 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6789
6790 vcpu->arch.smbase = smbase;
6791 }
6792
6793 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6794 u32 pmc)
6795 {
6796 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6797 }
6798
6799 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6800 u32 pmc, u64 *pdata)
6801 {
6802 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6803 }
6804
6805 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6806 {
6807 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6808 }
6809
6810 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6811 struct x86_instruction_info *info,
6812 enum x86_intercept_stage stage)
6813 {
6814 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6815 &ctxt->exception);
6816 }
6817
6818 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6819 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6820 bool exact_only)
6821 {
6822 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6823 }
6824
6825 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6826 {
6827 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6828 }
6829
6830 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6831 {
6832 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6833 }
6834
6835 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6836 {
6837 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6838 }
6839
6840 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6841 {
6842 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6843 }
6844
6845 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6846 {
6847 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6848 }
6849
6850 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6851 {
6852 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6853 }
6854
6855 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6856 {
6857 return emul_to_vcpu(ctxt)->arch.hflags;
6858 }
6859
6860 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6861 {
6862 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6863 }
6864
6865 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6866 const char *smstate)
6867 {
6868 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6869 }
6870
6871 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6872 {
6873 kvm_smm_changed(emul_to_vcpu(ctxt));
6874 }
6875
6876 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6877 {
6878 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6879 }
6880
6881 static const struct x86_emulate_ops emulate_ops = {
6882 .read_gpr = emulator_read_gpr,
6883 .write_gpr = emulator_write_gpr,
6884 .read_std = emulator_read_std,
6885 .write_std = emulator_write_std,
6886 .read_phys = kvm_read_guest_phys_system,
6887 .fetch = kvm_fetch_guest_virt,
6888 .read_emulated = emulator_read_emulated,
6889 .write_emulated = emulator_write_emulated,
6890 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6891 .invlpg = emulator_invlpg,
6892 .pio_in_emulated = emulator_pio_in_emulated,
6893 .pio_out_emulated = emulator_pio_out_emulated,
6894 .get_segment = emulator_get_segment,
6895 .set_segment = emulator_set_segment,
6896 .get_cached_segment_base = emulator_get_cached_segment_base,
6897 .get_gdt = emulator_get_gdt,
6898 .get_idt = emulator_get_idt,
6899 .set_gdt = emulator_set_gdt,
6900 .set_idt = emulator_set_idt,
6901 .get_cr = emulator_get_cr,
6902 .set_cr = emulator_set_cr,
6903 .cpl = emulator_get_cpl,
6904 .get_dr = emulator_get_dr,
6905 .set_dr = emulator_set_dr,
6906 .get_smbase = emulator_get_smbase,
6907 .set_smbase = emulator_set_smbase,
6908 .set_msr = emulator_set_msr,
6909 .get_msr = emulator_get_msr,
6910 .check_pmc = emulator_check_pmc,
6911 .read_pmc = emulator_read_pmc,
6912 .halt = emulator_halt,
6913 .wbinvd = emulator_wbinvd,
6914 .fix_hypercall = emulator_fix_hypercall,
6915 .intercept = emulator_intercept,
6916 .get_cpuid = emulator_get_cpuid,
6917 .guest_has_long_mode = emulator_guest_has_long_mode,
6918 .guest_has_movbe = emulator_guest_has_movbe,
6919 .guest_has_fxsr = emulator_guest_has_fxsr,
6920 .set_nmi_mask = emulator_set_nmi_mask,
6921 .get_hflags = emulator_get_hflags,
6922 .set_hflags = emulator_set_hflags,
6923 .pre_leave_smm = emulator_pre_leave_smm,
6924 .post_leave_smm = emulator_post_leave_smm,
6925 .set_xcr = emulator_set_xcr,
6926 };
6927
6928 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6929 {
6930 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6931 /*
6932 * an sti; sti; sequence only disable interrupts for the first
6933 * instruction. So, if the last instruction, be it emulated or
6934 * not, left the system with the INT_STI flag enabled, it
6935 * means that the last instruction is an sti. We should not
6936 * leave the flag on in this case. The same goes for mov ss
6937 */
6938 if (int_shadow & mask)
6939 mask = 0;
6940 if (unlikely(int_shadow || mask)) {
6941 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6942 if (!mask)
6943 kvm_make_request(KVM_REQ_EVENT, vcpu);
6944 }
6945 }
6946
6947 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6948 {
6949 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6950 if (ctxt->exception.vector == PF_VECTOR)
6951 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6952
6953 if (ctxt->exception.error_code_valid)
6954 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6955 ctxt->exception.error_code);
6956 else
6957 kvm_queue_exception(vcpu, ctxt->exception.vector);
6958 return false;
6959 }
6960
6961 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6962 {
6963 struct x86_emulate_ctxt *ctxt;
6964
6965 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6966 if (!ctxt) {
6967 pr_err("kvm: failed to allocate vcpu's emulator\n");
6968 return NULL;
6969 }
6970
6971 ctxt->vcpu = vcpu;
6972 ctxt->ops = &emulate_ops;
6973 vcpu->arch.emulate_ctxt = ctxt;
6974
6975 return ctxt;
6976 }
6977
6978 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6979 {
6980 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6981 int cs_db, cs_l;
6982
6983 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6984
6985 ctxt->gpa_available = false;
6986 ctxt->eflags = kvm_get_rflags(vcpu);
6987 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6988
6989 ctxt->eip = kvm_rip_read(vcpu);
6990 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6991 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6992 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6993 cs_db ? X86EMUL_MODE_PROT32 :
6994 X86EMUL_MODE_PROT16;
6995 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6996 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6997 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6998
6999 init_decode_cache(ctxt);
7000 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7001 }
7002
7003 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
7004 {
7005 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7006 int ret;
7007
7008 init_emulate_ctxt(vcpu);
7009
7010 ctxt->op_bytes = 2;
7011 ctxt->ad_bytes = 2;
7012 ctxt->_eip = ctxt->eip + inc_eip;
7013 ret = emulate_int_real(ctxt, irq);
7014
7015 if (ret != X86EMUL_CONTINUE) {
7016 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7017 } else {
7018 ctxt->eip = ctxt->_eip;
7019 kvm_rip_write(vcpu, ctxt->eip);
7020 kvm_set_rflags(vcpu, ctxt->eflags);
7021 }
7022 }
7023 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
7024
7025 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
7026 {
7027 ++vcpu->stat.insn_emulation_fail;
7028 trace_kvm_emulate_insn_failed(vcpu);
7029
7030 if (emulation_type & EMULTYPE_VMWARE_GP) {
7031 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7032 return 1;
7033 }
7034
7035 if (emulation_type & EMULTYPE_SKIP) {
7036 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7037 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7038 vcpu->run->internal.ndata = 0;
7039 return 0;
7040 }
7041
7042 kvm_queue_exception(vcpu, UD_VECTOR);
7043
7044 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
7045 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7046 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7047 vcpu->run->internal.ndata = 0;
7048 return 0;
7049 }
7050
7051 return 1;
7052 }
7053
7054 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7055 bool write_fault_to_shadow_pgtable,
7056 int emulation_type)
7057 {
7058 gpa_t gpa = cr2_or_gpa;
7059 kvm_pfn_t pfn;
7060
7061 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7062 return false;
7063
7064 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7065 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7066 return false;
7067
7068 if (!vcpu->arch.mmu->direct_map) {
7069 /*
7070 * Write permission should be allowed since only
7071 * write access need to be emulated.
7072 */
7073 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7074
7075 /*
7076 * If the mapping is invalid in guest, let cpu retry
7077 * it to generate fault.
7078 */
7079 if (gpa == UNMAPPED_GVA)
7080 return true;
7081 }
7082
7083 /*
7084 * Do not retry the unhandleable instruction if it faults on the
7085 * readonly host memory, otherwise it will goto a infinite loop:
7086 * retry instruction -> write #PF -> emulation fail -> retry
7087 * instruction -> ...
7088 */
7089 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
7090
7091 /*
7092 * If the instruction failed on the error pfn, it can not be fixed,
7093 * report the error to userspace.
7094 */
7095 if (is_error_noslot_pfn(pfn))
7096 return false;
7097
7098 kvm_release_pfn_clean(pfn);
7099
7100 /* The instructions are well-emulated on direct mmu. */
7101 if (vcpu->arch.mmu->direct_map) {
7102 unsigned int indirect_shadow_pages;
7103
7104 spin_lock(&vcpu->kvm->mmu_lock);
7105 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
7106 spin_unlock(&vcpu->kvm->mmu_lock);
7107
7108 if (indirect_shadow_pages)
7109 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7110
7111 return true;
7112 }
7113
7114 /*
7115 * if emulation was due to access to shadowed page table
7116 * and it failed try to unshadow page and re-enter the
7117 * guest to let CPU execute the instruction.
7118 */
7119 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7120
7121 /*
7122 * If the access faults on its page table, it can not
7123 * be fixed by unprotecting shadow page and it should
7124 * be reported to userspace.
7125 */
7126 return !write_fault_to_shadow_pgtable;
7127 }
7128
7129 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7130 gpa_t cr2_or_gpa, int emulation_type)
7131 {
7132 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7133 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7134
7135 last_retry_eip = vcpu->arch.last_retry_eip;
7136 last_retry_addr = vcpu->arch.last_retry_addr;
7137
7138 /*
7139 * If the emulation is caused by #PF and it is non-page_table
7140 * writing instruction, it means the VM-EXIT is caused by shadow
7141 * page protected, we can zap the shadow page and retry this
7142 * instruction directly.
7143 *
7144 * Note: if the guest uses a non-page-table modifying instruction
7145 * on the PDE that points to the instruction, then we will unmap
7146 * the instruction and go to an infinite loop. So, we cache the
7147 * last retried eip and the last fault address, if we meet the eip
7148 * and the address again, we can break out of the potential infinite
7149 * loop.
7150 */
7151 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7152
7153 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7154 return false;
7155
7156 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7157 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7158 return false;
7159
7160 if (x86_page_table_writing_insn(ctxt))
7161 return false;
7162
7163 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7164 return false;
7165
7166 vcpu->arch.last_retry_eip = ctxt->eip;
7167 vcpu->arch.last_retry_addr = cr2_or_gpa;
7168
7169 if (!vcpu->arch.mmu->direct_map)
7170 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7171
7172 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7173
7174 return true;
7175 }
7176
7177 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7178 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7179
7180 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7181 {
7182 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7183 /* This is a good place to trace that we are exiting SMM. */
7184 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7185
7186 /* Process a latched INIT or SMI, if any. */
7187 kvm_make_request(KVM_REQ_EVENT, vcpu);
7188 }
7189
7190 kvm_mmu_reset_context(vcpu);
7191 }
7192
7193 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7194 unsigned long *db)
7195 {
7196 u32 dr6 = 0;
7197 int i;
7198 u32 enable, rwlen;
7199
7200 enable = dr7;
7201 rwlen = dr7 >> 16;
7202 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7203 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7204 dr6 |= (1 << i);
7205 return dr6;
7206 }
7207
7208 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7209 {
7210 struct kvm_run *kvm_run = vcpu->run;
7211
7212 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7213 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
7214 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7215 kvm_run->debug.arch.exception = DB_VECTOR;
7216 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7217 return 0;
7218 }
7219 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7220 return 1;
7221 }
7222
7223 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7224 {
7225 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7226 int r;
7227
7228 r = kvm_x86_ops.skip_emulated_instruction(vcpu);
7229 if (unlikely(!r))
7230 return 0;
7231
7232 /*
7233 * rflags is the old, "raw" value of the flags. The new value has
7234 * not been saved yet.
7235 *
7236 * This is correct even for TF set by the guest, because "the
7237 * processor will not generate this exception after the instruction
7238 * that sets the TF flag".
7239 */
7240 if (unlikely(rflags & X86_EFLAGS_TF))
7241 r = kvm_vcpu_do_singlestep(vcpu);
7242 return r;
7243 }
7244 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7245
7246 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7247 {
7248 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7249 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7250 struct kvm_run *kvm_run = vcpu->run;
7251 unsigned long eip = kvm_get_linear_rip(vcpu);
7252 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7253 vcpu->arch.guest_debug_dr7,
7254 vcpu->arch.eff_db);
7255
7256 if (dr6 != 0) {
7257 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
7258 kvm_run->debug.arch.pc = eip;
7259 kvm_run->debug.arch.exception = DB_VECTOR;
7260 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7261 *r = 0;
7262 return true;
7263 }
7264 }
7265
7266 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7267 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7268 unsigned long eip = kvm_get_linear_rip(vcpu);
7269 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7270 vcpu->arch.dr7,
7271 vcpu->arch.db);
7272
7273 if (dr6 != 0) {
7274 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7275 *r = 1;
7276 return true;
7277 }
7278 }
7279
7280 return false;
7281 }
7282
7283 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7284 {
7285 switch (ctxt->opcode_len) {
7286 case 1:
7287 switch (ctxt->b) {
7288 case 0xe4: /* IN */
7289 case 0xe5:
7290 case 0xec:
7291 case 0xed:
7292 case 0xe6: /* OUT */
7293 case 0xe7:
7294 case 0xee:
7295 case 0xef:
7296 case 0x6c: /* INS */
7297 case 0x6d:
7298 case 0x6e: /* OUTS */
7299 case 0x6f:
7300 return true;
7301 }
7302 break;
7303 case 2:
7304 switch (ctxt->b) {
7305 case 0x33: /* RDPMC */
7306 return true;
7307 }
7308 break;
7309 }
7310
7311 return false;
7312 }
7313
7314 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7315 int emulation_type, void *insn, int insn_len)
7316 {
7317 int r;
7318 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7319 bool writeback = true;
7320 bool write_fault_to_spt;
7321
7322 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len)))
7323 return 1;
7324
7325 vcpu->arch.l1tf_flush_l1d = true;
7326
7327 /*
7328 * Clear write_fault_to_shadow_pgtable here to ensure it is
7329 * never reused.
7330 */
7331 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7332 vcpu->arch.write_fault_to_shadow_pgtable = false;
7333 kvm_clear_exception_queue(vcpu);
7334
7335 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7336 init_emulate_ctxt(vcpu);
7337
7338 /*
7339 * We will reenter on the same instruction since
7340 * we do not set complete_userspace_io. This does not
7341 * handle watchpoints yet, those would be handled in
7342 * the emulate_ops.
7343 */
7344 if (!(emulation_type & EMULTYPE_SKIP) &&
7345 kvm_vcpu_check_breakpoint(vcpu, &r))
7346 return r;
7347
7348 ctxt->interruptibility = 0;
7349 ctxt->have_exception = false;
7350 ctxt->exception.vector = -1;
7351 ctxt->perm_ok = false;
7352
7353 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7354
7355 r = x86_decode_insn(ctxt, insn, insn_len);
7356
7357 trace_kvm_emulate_insn_start(vcpu);
7358 ++vcpu->stat.insn_emulation;
7359 if (r != EMULATION_OK) {
7360 if ((emulation_type & EMULTYPE_TRAP_UD) ||
7361 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7362 kvm_queue_exception(vcpu, UD_VECTOR);
7363 return 1;
7364 }
7365 if (reexecute_instruction(vcpu, cr2_or_gpa,
7366 write_fault_to_spt,
7367 emulation_type))
7368 return 1;
7369 if (ctxt->have_exception) {
7370 /*
7371 * #UD should result in just EMULATION_FAILED, and trap-like
7372 * exception should not be encountered during decode.
7373 */
7374 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7375 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7376 inject_emulated_exception(vcpu);
7377 return 1;
7378 }
7379 return handle_emulation_failure(vcpu, emulation_type);
7380 }
7381 }
7382
7383 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7384 !is_vmware_backdoor_opcode(ctxt)) {
7385 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7386 return 1;
7387 }
7388
7389 /*
7390 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7391 * for kvm_skip_emulated_instruction(). The caller is responsible for
7392 * updating interruptibility state and injecting single-step #DBs.
7393 */
7394 if (emulation_type & EMULTYPE_SKIP) {
7395 kvm_rip_write(vcpu, ctxt->_eip);
7396 if (ctxt->eflags & X86_EFLAGS_RF)
7397 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7398 return 1;
7399 }
7400
7401 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7402 return 1;
7403
7404 /* this is needed for vmware backdoor interface to work since it
7405 changes registers values during IO operation */
7406 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7407 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7408 emulator_invalidate_register_cache(ctxt);
7409 }
7410
7411 restart:
7412 if (emulation_type & EMULTYPE_PF) {
7413 /* Save the faulting GPA (cr2) in the address field */
7414 ctxt->exception.address = cr2_or_gpa;
7415
7416 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7417 if (vcpu->arch.mmu->direct_map) {
7418 ctxt->gpa_available = true;
7419 ctxt->gpa_val = cr2_or_gpa;
7420 }
7421 } else {
7422 /* Sanitize the address out of an abundance of paranoia. */
7423 ctxt->exception.address = 0;
7424 }
7425
7426 r = x86_emulate_insn(ctxt);
7427
7428 if (r == EMULATION_INTERCEPTED)
7429 return 1;
7430
7431 if (r == EMULATION_FAILED) {
7432 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7433 emulation_type))
7434 return 1;
7435
7436 return handle_emulation_failure(vcpu, emulation_type);
7437 }
7438
7439 if (ctxt->have_exception) {
7440 r = 1;
7441 if (inject_emulated_exception(vcpu))
7442 return r;
7443 } else if (vcpu->arch.pio.count) {
7444 if (!vcpu->arch.pio.in) {
7445 /* FIXME: return into emulator if single-stepping. */
7446 vcpu->arch.pio.count = 0;
7447 } else {
7448 writeback = false;
7449 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7450 }
7451 r = 0;
7452 } else if (vcpu->mmio_needed) {
7453 ++vcpu->stat.mmio_exits;
7454
7455 if (!vcpu->mmio_is_write)
7456 writeback = false;
7457 r = 0;
7458 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7459 } else if (r == EMULATION_RESTART)
7460 goto restart;
7461 else
7462 r = 1;
7463
7464 if (writeback) {
7465 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7466 toggle_interruptibility(vcpu, ctxt->interruptibility);
7467 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7468 if (!ctxt->have_exception ||
7469 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7470 kvm_rip_write(vcpu, ctxt->eip);
7471 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7472 r = kvm_vcpu_do_singlestep(vcpu);
7473 if (kvm_x86_ops.update_emulated_instruction)
7474 kvm_x86_ops.update_emulated_instruction(vcpu);
7475 __kvm_set_rflags(vcpu, ctxt->eflags);
7476 }
7477
7478 /*
7479 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7480 * do nothing, and it will be requested again as soon as
7481 * the shadow expires. But we still need to check here,
7482 * because POPF has no interrupt shadow.
7483 */
7484 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7485 kvm_make_request(KVM_REQ_EVENT, vcpu);
7486 } else
7487 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7488
7489 return r;
7490 }
7491
7492 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7493 {
7494 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7495 }
7496 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7497
7498 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7499 void *insn, int insn_len)
7500 {
7501 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7502 }
7503 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7504
7505 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7506 {
7507 vcpu->arch.pio.count = 0;
7508 return 1;
7509 }
7510
7511 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7512 {
7513 vcpu->arch.pio.count = 0;
7514
7515 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7516 return 1;
7517
7518 return kvm_skip_emulated_instruction(vcpu);
7519 }
7520
7521 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7522 unsigned short port)
7523 {
7524 unsigned long val = kvm_rax_read(vcpu);
7525 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7526
7527 if (ret)
7528 return ret;
7529
7530 /*
7531 * Workaround userspace that relies on old KVM behavior of %rip being
7532 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7533 */
7534 if (port == 0x7e &&
7535 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7536 vcpu->arch.complete_userspace_io =
7537 complete_fast_pio_out_port_0x7e;
7538 kvm_skip_emulated_instruction(vcpu);
7539 } else {
7540 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7541 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7542 }
7543 return 0;
7544 }
7545
7546 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7547 {
7548 unsigned long val;
7549
7550 /* We should only ever be called with arch.pio.count equal to 1 */
7551 BUG_ON(vcpu->arch.pio.count != 1);
7552
7553 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7554 vcpu->arch.pio.count = 0;
7555 return 1;
7556 }
7557
7558 /* For size less than 4 we merge, else we zero extend */
7559 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7560
7561 /*
7562 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7563 * the copy and tracing
7564 */
7565 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7566 kvm_rax_write(vcpu, val);
7567
7568 return kvm_skip_emulated_instruction(vcpu);
7569 }
7570
7571 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7572 unsigned short port)
7573 {
7574 unsigned long val;
7575 int ret;
7576
7577 /* For size less than 4 we merge, else we zero extend */
7578 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7579
7580 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7581 if (ret) {
7582 kvm_rax_write(vcpu, val);
7583 return ret;
7584 }
7585
7586 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7587 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7588
7589 return 0;
7590 }
7591
7592 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7593 {
7594 int ret;
7595
7596 if (in)
7597 ret = kvm_fast_pio_in(vcpu, size, port);
7598 else
7599 ret = kvm_fast_pio_out(vcpu, size, port);
7600 return ret && kvm_skip_emulated_instruction(vcpu);
7601 }
7602 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7603
7604 static int kvmclock_cpu_down_prep(unsigned int cpu)
7605 {
7606 __this_cpu_write(cpu_tsc_khz, 0);
7607 return 0;
7608 }
7609
7610 static void tsc_khz_changed(void *data)
7611 {
7612 struct cpufreq_freqs *freq = data;
7613 unsigned long khz = 0;
7614
7615 if (data)
7616 khz = freq->new;
7617 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7618 khz = cpufreq_quick_get(raw_smp_processor_id());
7619 if (!khz)
7620 khz = tsc_khz;
7621 __this_cpu_write(cpu_tsc_khz, khz);
7622 }
7623
7624 #ifdef CONFIG_X86_64
7625 static void kvm_hyperv_tsc_notifier(void)
7626 {
7627 struct kvm *kvm;
7628 struct kvm_vcpu *vcpu;
7629 int cpu;
7630
7631 mutex_lock(&kvm_lock);
7632 list_for_each_entry(kvm, &vm_list, vm_list)
7633 kvm_make_mclock_inprogress_request(kvm);
7634
7635 hyperv_stop_tsc_emulation();
7636
7637 /* TSC frequency always matches when on Hyper-V */
7638 for_each_present_cpu(cpu)
7639 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7640 kvm_max_guest_tsc_khz = tsc_khz;
7641
7642 list_for_each_entry(kvm, &vm_list, vm_list) {
7643 struct kvm_arch *ka = &kvm->arch;
7644
7645 spin_lock(&ka->pvclock_gtod_sync_lock);
7646
7647 pvclock_update_vm_gtod_copy(kvm);
7648
7649 kvm_for_each_vcpu(cpu, vcpu, kvm)
7650 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7651
7652 kvm_for_each_vcpu(cpu, vcpu, kvm)
7653 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7654
7655 spin_unlock(&ka->pvclock_gtod_sync_lock);
7656 }
7657 mutex_unlock(&kvm_lock);
7658 }
7659 #endif
7660
7661 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7662 {
7663 struct kvm *kvm;
7664 struct kvm_vcpu *vcpu;
7665 int i, send_ipi = 0;
7666
7667 /*
7668 * We allow guests to temporarily run on slowing clocks,
7669 * provided we notify them after, or to run on accelerating
7670 * clocks, provided we notify them before. Thus time never
7671 * goes backwards.
7672 *
7673 * However, we have a problem. We can't atomically update
7674 * the frequency of a given CPU from this function; it is
7675 * merely a notifier, which can be called from any CPU.
7676 * Changing the TSC frequency at arbitrary points in time
7677 * requires a recomputation of local variables related to
7678 * the TSC for each VCPU. We must flag these local variables
7679 * to be updated and be sure the update takes place with the
7680 * new frequency before any guests proceed.
7681 *
7682 * Unfortunately, the combination of hotplug CPU and frequency
7683 * change creates an intractable locking scenario; the order
7684 * of when these callouts happen is undefined with respect to
7685 * CPU hotplug, and they can race with each other. As such,
7686 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7687 * undefined; you can actually have a CPU frequency change take
7688 * place in between the computation of X and the setting of the
7689 * variable. To protect against this problem, all updates of
7690 * the per_cpu tsc_khz variable are done in an interrupt
7691 * protected IPI, and all callers wishing to update the value
7692 * must wait for a synchronous IPI to complete (which is trivial
7693 * if the caller is on the CPU already). This establishes the
7694 * necessary total order on variable updates.
7695 *
7696 * Note that because a guest time update may take place
7697 * anytime after the setting of the VCPU's request bit, the
7698 * correct TSC value must be set before the request. However,
7699 * to ensure the update actually makes it to any guest which
7700 * starts running in hardware virtualization between the set
7701 * and the acquisition of the spinlock, we must also ping the
7702 * CPU after setting the request bit.
7703 *
7704 */
7705
7706 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7707
7708 mutex_lock(&kvm_lock);
7709 list_for_each_entry(kvm, &vm_list, vm_list) {
7710 kvm_for_each_vcpu(i, vcpu, kvm) {
7711 if (vcpu->cpu != cpu)
7712 continue;
7713 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7714 if (vcpu->cpu != raw_smp_processor_id())
7715 send_ipi = 1;
7716 }
7717 }
7718 mutex_unlock(&kvm_lock);
7719
7720 if (freq->old < freq->new && send_ipi) {
7721 /*
7722 * We upscale the frequency. Must make the guest
7723 * doesn't see old kvmclock values while running with
7724 * the new frequency, otherwise we risk the guest sees
7725 * time go backwards.
7726 *
7727 * In case we update the frequency for another cpu
7728 * (which might be in guest context) send an interrupt
7729 * to kick the cpu out of guest context. Next time
7730 * guest context is entered kvmclock will be updated,
7731 * so the guest will not see stale values.
7732 */
7733 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7734 }
7735 }
7736
7737 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7738 void *data)
7739 {
7740 struct cpufreq_freqs *freq = data;
7741 int cpu;
7742
7743 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7744 return 0;
7745 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7746 return 0;
7747
7748 for_each_cpu(cpu, freq->policy->cpus)
7749 __kvmclock_cpufreq_notifier(freq, cpu);
7750
7751 return 0;
7752 }
7753
7754 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7755 .notifier_call = kvmclock_cpufreq_notifier
7756 };
7757
7758 static int kvmclock_cpu_online(unsigned int cpu)
7759 {
7760 tsc_khz_changed(NULL);
7761 return 0;
7762 }
7763
7764 static void kvm_timer_init(void)
7765 {
7766 max_tsc_khz = tsc_khz;
7767
7768 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7769 #ifdef CONFIG_CPU_FREQ
7770 struct cpufreq_policy *policy;
7771 int cpu;
7772
7773 cpu = get_cpu();
7774 policy = cpufreq_cpu_get(cpu);
7775 if (policy) {
7776 if (policy->cpuinfo.max_freq)
7777 max_tsc_khz = policy->cpuinfo.max_freq;
7778 cpufreq_cpu_put(policy);
7779 }
7780 put_cpu();
7781 #endif
7782 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7783 CPUFREQ_TRANSITION_NOTIFIER);
7784 }
7785
7786 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7787 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7788 }
7789
7790 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7791 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7792
7793 int kvm_is_in_guest(void)
7794 {
7795 return __this_cpu_read(current_vcpu) != NULL;
7796 }
7797
7798 static int kvm_is_user_mode(void)
7799 {
7800 int user_mode = 3;
7801
7802 if (__this_cpu_read(current_vcpu))
7803 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7804
7805 return user_mode != 0;
7806 }
7807
7808 static unsigned long kvm_get_guest_ip(void)
7809 {
7810 unsigned long ip = 0;
7811
7812 if (__this_cpu_read(current_vcpu))
7813 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7814
7815 return ip;
7816 }
7817
7818 static void kvm_handle_intel_pt_intr(void)
7819 {
7820 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7821
7822 kvm_make_request(KVM_REQ_PMI, vcpu);
7823 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7824 (unsigned long *)&vcpu->arch.pmu.global_status);
7825 }
7826
7827 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7828 .is_in_guest = kvm_is_in_guest,
7829 .is_user_mode = kvm_is_user_mode,
7830 .get_guest_ip = kvm_get_guest_ip,
7831 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7832 };
7833
7834 #ifdef CONFIG_X86_64
7835 static void pvclock_gtod_update_fn(struct work_struct *work)
7836 {
7837 struct kvm *kvm;
7838
7839 struct kvm_vcpu *vcpu;
7840 int i;
7841
7842 mutex_lock(&kvm_lock);
7843 list_for_each_entry(kvm, &vm_list, vm_list)
7844 kvm_for_each_vcpu(i, vcpu, kvm)
7845 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7846 atomic_set(&kvm_guest_has_master_clock, 0);
7847 mutex_unlock(&kvm_lock);
7848 }
7849
7850 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7851
7852 /*
7853 * Notification about pvclock gtod data update.
7854 */
7855 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7856 void *priv)
7857 {
7858 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7859 struct timekeeper *tk = priv;
7860
7861 update_pvclock_gtod(tk);
7862
7863 /* disable master clock if host does not trust, or does not
7864 * use, TSC based clocksource.
7865 */
7866 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7867 atomic_read(&kvm_guest_has_master_clock) != 0)
7868 queue_work(system_long_wq, &pvclock_gtod_work);
7869
7870 return 0;
7871 }
7872
7873 static struct notifier_block pvclock_gtod_notifier = {
7874 .notifier_call = pvclock_gtod_notify,
7875 };
7876 #endif
7877
7878 int kvm_arch_init(void *opaque)
7879 {
7880 struct kvm_x86_init_ops *ops = opaque;
7881 int r;
7882
7883 if (kvm_x86_ops.hardware_enable) {
7884 printk(KERN_ERR "kvm: already loaded the other module\n");
7885 r = -EEXIST;
7886 goto out;
7887 }
7888
7889 if (!ops->cpu_has_kvm_support()) {
7890 pr_err_ratelimited("kvm: no hardware support\n");
7891 r = -EOPNOTSUPP;
7892 goto out;
7893 }
7894 if (ops->disabled_by_bios()) {
7895 pr_err_ratelimited("kvm: disabled by bios\n");
7896 r = -EOPNOTSUPP;
7897 goto out;
7898 }
7899
7900 /*
7901 * KVM explicitly assumes that the guest has an FPU and
7902 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7903 * vCPU's FPU state as a fxregs_state struct.
7904 */
7905 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7906 printk(KERN_ERR "kvm: inadequate fpu\n");
7907 r = -EOPNOTSUPP;
7908 goto out;
7909 }
7910
7911 r = -ENOMEM;
7912 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7913 __alignof__(struct fpu), SLAB_ACCOUNT,
7914 NULL);
7915 if (!x86_fpu_cache) {
7916 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7917 goto out;
7918 }
7919
7920 x86_emulator_cache = kvm_alloc_emulator_cache();
7921 if (!x86_emulator_cache) {
7922 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7923 goto out_free_x86_fpu_cache;
7924 }
7925
7926 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7927 if (!user_return_msrs) {
7928 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7929 goto out_free_x86_emulator_cache;
7930 }
7931
7932 r = kvm_mmu_module_init();
7933 if (r)
7934 goto out_free_percpu;
7935
7936 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7937 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7938 PT_PRESENT_MASK, 0, sme_me_mask);
7939 kvm_timer_init();
7940
7941 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7942
7943 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7944 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7945 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7946 }
7947
7948 kvm_lapic_init();
7949 if (pi_inject_timer == -1)
7950 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7951 #ifdef CONFIG_X86_64
7952 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7953
7954 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7955 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7956 #endif
7957
7958 return 0;
7959
7960 out_free_percpu:
7961 free_percpu(user_return_msrs);
7962 out_free_x86_emulator_cache:
7963 kmem_cache_destroy(x86_emulator_cache);
7964 out_free_x86_fpu_cache:
7965 kmem_cache_destroy(x86_fpu_cache);
7966 out:
7967 return r;
7968 }
7969
7970 void kvm_arch_exit(void)
7971 {
7972 #ifdef CONFIG_X86_64
7973 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7974 clear_hv_tscchange_cb();
7975 #endif
7976 kvm_lapic_exit();
7977 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7978
7979 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7980 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7981 CPUFREQ_TRANSITION_NOTIFIER);
7982 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7983 #ifdef CONFIG_X86_64
7984 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7985 #endif
7986 kvm_x86_ops.hardware_enable = NULL;
7987 kvm_mmu_module_exit();
7988 free_percpu(user_return_msrs);
7989 kmem_cache_destroy(x86_fpu_cache);
7990 }
7991
7992 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason)
7993 {
7994 ++vcpu->stat.halt_exits;
7995 if (lapic_in_kernel(vcpu)) {
7996 vcpu->arch.mp_state = state;
7997 return 1;
7998 } else {
7999 vcpu->run->exit_reason = reason;
8000 return 0;
8001 }
8002 }
8003
8004 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8005 {
8006 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
8007 }
8008 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
8009
8010 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
8011 {
8012 int ret = kvm_skip_emulated_instruction(vcpu);
8013 /*
8014 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
8015 * KVM_EXIT_DEBUG here.
8016 */
8017 return kvm_vcpu_halt(vcpu) && ret;
8018 }
8019 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
8020
8021 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
8022 {
8023 int ret = kvm_skip_emulated_instruction(vcpu);
8024
8025 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret;
8026 }
8027 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
8028
8029 #ifdef CONFIG_X86_64
8030 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
8031 unsigned long clock_type)
8032 {
8033 struct kvm_clock_pairing clock_pairing;
8034 struct timespec64 ts;
8035 u64 cycle;
8036 int ret;
8037
8038 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
8039 return -KVM_EOPNOTSUPP;
8040
8041 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
8042 return -KVM_EOPNOTSUPP;
8043
8044 clock_pairing.sec = ts.tv_sec;
8045 clock_pairing.nsec = ts.tv_nsec;
8046 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
8047 clock_pairing.flags = 0;
8048 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
8049
8050 ret = 0;
8051 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
8052 sizeof(struct kvm_clock_pairing)))
8053 ret = -KVM_EFAULT;
8054
8055 return ret;
8056 }
8057 #endif
8058
8059 /*
8060 * kvm_pv_kick_cpu_op: Kick a vcpu.
8061 *
8062 * @apicid - apicid of vcpu to be kicked.
8063 */
8064 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
8065 {
8066 struct kvm_lapic_irq lapic_irq;
8067
8068 lapic_irq.shorthand = APIC_DEST_NOSHORT;
8069 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
8070 lapic_irq.level = 0;
8071 lapic_irq.dest_id = apicid;
8072 lapic_irq.msi_redir_hint = false;
8073
8074 lapic_irq.delivery_mode = APIC_DM_REMRD;
8075 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
8076 }
8077
8078 bool kvm_apicv_activated(struct kvm *kvm)
8079 {
8080 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
8081 }
8082 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
8083
8084 void kvm_apicv_init(struct kvm *kvm, bool enable)
8085 {
8086 if (enable)
8087 clear_bit(APICV_INHIBIT_REASON_DISABLE,
8088 &kvm->arch.apicv_inhibit_reasons);
8089 else
8090 set_bit(APICV_INHIBIT_REASON_DISABLE,
8091 &kvm->arch.apicv_inhibit_reasons);
8092 }
8093 EXPORT_SYMBOL_GPL(kvm_apicv_init);
8094
8095 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
8096 {
8097 struct kvm_vcpu *target = NULL;
8098 struct kvm_apic_map *map;
8099
8100 rcu_read_lock();
8101 map = rcu_dereference(kvm->arch.apic_map);
8102
8103 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
8104 target = map->phys_map[dest_id]->vcpu;
8105
8106 rcu_read_unlock();
8107
8108 if (target && READ_ONCE(target->ready))
8109 kvm_vcpu_yield_to(target);
8110 }
8111
8112 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
8113 {
8114 unsigned long nr, a0, a1, a2, a3, ret;
8115 int op_64_bit;
8116
8117 if (kvm_hv_hypercall_enabled(vcpu->kvm))
8118 return kvm_hv_hypercall(vcpu);
8119
8120 nr = kvm_rax_read(vcpu);
8121 a0 = kvm_rbx_read(vcpu);
8122 a1 = kvm_rcx_read(vcpu);
8123 a2 = kvm_rdx_read(vcpu);
8124 a3 = kvm_rsi_read(vcpu);
8125
8126 trace_kvm_hypercall(nr, a0, a1, a2, a3);
8127
8128 op_64_bit = is_64_bit_mode(vcpu);
8129 if (!op_64_bit) {
8130 nr &= 0xFFFFFFFF;
8131 a0 &= 0xFFFFFFFF;
8132 a1 &= 0xFFFFFFFF;
8133 a2 &= 0xFFFFFFFF;
8134 a3 &= 0xFFFFFFFF;
8135 }
8136
8137 if (kvm_x86_ops.get_cpl(vcpu) != 0) {
8138 ret = -KVM_EPERM;
8139 goto out;
8140 }
8141
8142 ret = -KVM_ENOSYS;
8143
8144 switch (nr) {
8145 case KVM_HC_VAPIC_POLL_IRQ:
8146 ret = 0;
8147 break;
8148 case KVM_HC_KICK_CPU:
8149 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
8150 break;
8151
8152 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8153 kvm_sched_yield(vcpu->kvm, a1);
8154 ret = 0;
8155 break;
8156 #ifdef CONFIG_X86_64
8157 case KVM_HC_CLOCK_PAIRING:
8158 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8159 break;
8160 #endif
8161 case KVM_HC_SEND_IPI:
8162 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
8163 break;
8164
8165 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8166 break;
8167 case KVM_HC_SCHED_YIELD:
8168 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
8169 break;
8170
8171 kvm_sched_yield(vcpu->kvm, a0);
8172 ret = 0;
8173 break;
8174 default:
8175 ret = -KVM_ENOSYS;
8176 break;
8177 }
8178 out:
8179 if (!op_64_bit)
8180 ret = (u32)ret;
8181 kvm_rax_write(vcpu, ret);
8182
8183 ++vcpu->stat.hypercalls;
8184 return kvm_skip_emulated_instruction(vcpu);
8185 }
8186 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8187
8188 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8189 {
8190 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8191 char instruction[3];
8192 unsigned long rip = kvm_rip_read(vcpu);
8193
8194 kvm_x86_ops.patch_hypercall(vcpu, instruction);
8195
8196 return emulator_write_emulated(ctxt, rip, instruction, 3,
8197 &ctxt->exception);
8198 }
8199
8200 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8201 {
8202 return vcpu->run->request_interrupt_window &&
8203 likely(!pic_in_kernel(vcpu->kvm));
8204 }
8205
8206 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8207 {
8208 struct kvm_run *kvm_run = vcpu->run;
8209
8210 /*
8211 * if_flag is obsolete and useless, so do not bother
8212 * setting it for SEV-ES guests. Userspace can just
8213 * use kvm_run->ready_for_interrupt_injection.
8214 */
8215 kvm_run->if_flag = !vcpu->arch.guest_state_protected
8216 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8217
8218 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
8219 kvm_run->cr8 = kvm_get_cr8(vcpu);
8220 kvm_run->apic_base = kvm_get_apic_base(vcpu);
8221 kvm_run->ready_for_interrupt_injection =
8222 pic_in_kernel(vcpu->kvm) ||
8223 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8224 }
8225
8226 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8227 {
8228 int max_irr, tpr;
8229
8230 if (!kvm_x86_ops.update_cr8_intercept)
8231 return;
8232
8233 if (!lapic_in_kernel(vcpu))
8234 return;
8235
8236 if (vcpu->arch.apicv_active)
8237 return;
8238
8239 if (!vcpu->arch.apic->vapic_addr)
8240 max_irr = kvm_lapic_find_highest_irr(vcpu);
8241 else
8242 max_irr = -1;
8243
8244 if (max_irr != -1)
8245 max_irr >>= 4;
8246
8247 tpr = kvm_lapic_get_cr8(vcpu);
8248
8249 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
8250 }
8251
8252 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8253 {
8254 int r;
8255 bool can_inject = true;
8256
8257 /* try to reinject previous events if any */
8258
8259 if (vcpu->arch.exception.injected) {
8260 kvm_x86_ops.queue_exception(vcpu);
8261 can_inject = false;
8262 }
8263 /*
8264 * Do not inject an NMI or interrupt if there is a pending
8265 * exception. Exceptions and interrupts are recognized at
8266 * instruction boundaries, i.e. the start of an instruction.
8267 * Trap-like exceptions, e.g. #DB, have higher priority than
8268 * NMIs and interrupts, i.e. traps are recognized before an
8269 * NMI/interrupt that's pending on the same instruction.
8270 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8271 * priority, but are only generated (pended) during instruction
8272 * execution, i.e. a pending fault-like exception means the
8273 * fault occurred on the *previous* instruction and must be
8274 * serviced prior to recognizing any new events in order to
8275 * fully complete the previous instruction.
8276 */
8277 else if (!vcpu->arch.exception.pending) {
8278 if (vcpu->arch.nmi_injected) {
8279 kvm_x86_ops.set_nmi(vcpu);
8280 can_inject = false;
8281 } else if (vcpu->arch.interrupt.injected) {
8282 kvm_x86_ops.set_irq(vcpu);
8283 can_inject = false;
8284 }
8285 }
8286
8287 WARN_ON_ONCE(vcpu->arch.exception.injected &&
8288 vcpu->arch.exception.pending);
8289
8290 /*
8291 * Call check_nested_events() even if we reinjected a previous event
8292 * in order for caller to determine if it should require immediate-exit
8293 * from L2 to L1 due to pending L1 events which require exit
8294 * from L2 to L1.
8295 */
8296 if (is_guest_mode(vcpu)) {
8297 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8298 if (r < 0)
8299 goto busy;
8300 }
8301
8302 /* try to inject new event if pending */
8303 if (vcpu->arch.exception.pending) {
8304 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8305 vcpu->arch.exception.has_error_code,
8306 vcpu->arch.exception.error_code);
8307
8308 vcpu->arch.exception.pending = false;
8309 vcpu->arch.exception.injected = true;
8310
8311 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8312 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8313 X86_EFLAGS_RF);
8314
8315 if (vcpu->arch.exception.nr == DB_VECTOR) {
8316 kvm_deliver_exception_payload(vcpu);
8317 if (vcpu->arch.dr7 & DR7_GD) {
8318 vcpu->arch.dr7 &= ~DR7_GD;
8319 kvm_update_dr7(vcpu);
8320 }
8321 }
8322
8323 kvm_x86_ops.queue_exception(vcpu);
8324 can_inject = false;
8325 }
8326
8327 /*
8328 * Finally, inject interrupt events. If an event cannot be injected
8329 * due to architectural conditions (e.g. IF=0) a window-open exit
8330 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
8331 * and can architecturally be injected, but we cannot do it right now:
8332 * an interrupt could have arrived just now and we have to inject it
8333 * as a vmexit, or there could already an event in the queue, which is
8334 * indicated by can_inject. In that case we request an immediate exit
8335 * in order to make progress and get back here for another iteration.
8336 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8337 */
8338 if (vcpu->arch.smi_pending) {
8339 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
8340 if (r < 0)
8341 goto busy;
8342 if (r) {
8343 vcpu->arch.smi_pending = false;
8344 ++vcpu->arch.smi_count;
8345 enter_smm(vcpu);
8346 can_inject = false;
8347 } else
8348 kvm_x86_ops.enable_smi_window(vcpu);
8349 }
8350
8351 if (vcpu->arch.nmi_pending) {
8352 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
8353 if (r < 0)
8354 goto busy;
8355 if (r) {
8356 --vcpu->arch.nmi_pending;
8357 vcpu->arch.nmi_injected = true;
8358 kvm_x86_ops.set_nmi(vcpu);
8359 can_inject = false;
8360 WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
8361 }
8362 if (vcpu->arch.nmi_pending)
8363 kvm_x86_ops.enable_nmi_window(vcpu);
8364 }
8365
8366 if (kvm_cpu_has_injectable_intr(vcpu)) {
8367 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
8368 if (r < 0)
8369 goto busy;
8370 if (r) {
8371 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8372 kvm_x86_ops.set_irq(vcpu);
8373 WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
8374 }
8375 if (kvm_cpu_has_injectable_intr(vcpu))
8376 kvm_x86_ops.enable_irq_window(vcpu);
8377 }
8378
8379 if (is_guest_mode(vcpu) &&
8380 kvm_x86_ops.nested_ops->hv_timer_pending &&
8381 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8382 *req_immediate_exit = true;
8383
8384 WARN_ON(vcpu->arch.exception.pending);
8385 return;
8386
8387 busy:
8388 *req_immediate_exit = true;
8389 return;
8390 }
8391
8392 static void process_nmi(struct kvm_vcpu *vcpu)
8393 {
8394 unsigned limit = 2;
8395
8396 /*
8397 * x86 is limited to one NMI running, and one NMI pending after it.
8398 * If an NMI is already in progress, limit further NMIs to just one.
8399 * Otherwise, allow two (and we'll inject the first one immediately).
8400 */
8401 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
8402 limit = 1;
8403
8404 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8405 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8406 kvm_make_request(KVM_REQ_EVENT, vcpu);
8407 }
8408
8409 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8410 {
8411 u32 flags = 0;
8412 flags |= seg->g << 23;
8413 flags |= seg->db << 22;
8414 flags |= seg->l << 21;
8415 flags |= seg->avl << 20;
8416 flags |= seg->present << 15;
8417 flags |= seg->dpl << 13;
8418 flags |= seg->s << 12;
8419 flags |= seg->type << 8;
8420 return flags;
8421 }
8422
8423 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8424 {
8425 struct kvm_segment seg;
8426 int offset;
8427
8428 kvm_get_segment(vcpu, &seg, n);
8429 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8430
8431 if (n < 3)
8432 offset = 0x7f84 + n * 12;
8433 else
8434 offset = 0x7f2c + (n - 3) * 12;
8435
8436 put_smstate(u32, buf, offset + 8, seg.base);
8437 put_smstate(u32, buf, offset + 4, seg.limit);
8438 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8439 }
8440
8441 #ifdef CONFIG_X86_64
8442 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8443 {
8444 struct kvm_segment seg;
8445 int offset;
8446 u16 flags;
8447
8448 kvm_get_segment(vcpu, &seg, n);
8449 offset = 0x7e00 + n * 16;
8450
8451 flags = enter_smm_get_segment_flags(&seg) >> 8;
8452 put_smstate(u16, buf, offset, seg.selector);
8453 put_smstate(u16, buf, offset + 2, flags);
8454 put_smstate(u32, buf, offset + 4, seg.limit);
8455 put_smstate(u64, buf, offset + 8, seg.base);
8456 }
8457 #endif
8458
8459 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8460 {
8461 struct desc_ptr dt;
8462 struct kvm_segment seg;
8463 unsigned long val;
8464 int i;
8465
8466 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8467 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8468 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8469 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8470
8471 for (i = 0; i < 8; i++)
8472 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8473
8474 kvm_get_dr(vcpu, 6, &val);
8475 put_smstate(u32, buf, 0x7fcc, (u32)val);
8476 kvm_get_dr(vcpu, 7, &val);
8477 put_smstate(u32, buf, 0x7fc8, (u32)val);
8478
8479 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8480 put_smstate(u32, buf, 0x7fc4, seg.selector);
8481 put_smstate(u32, buf, 0x7f64, seg.base);
8482 put_smstate(u32, buf, 0x7f60, seg.limit);
8483 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8484
8485 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8486 put_smstate(u32, buf, 0x7fc0, seg.selector);
8487 put_smstate(u32, buf, 0x7f80, seg.base);
8488 put_smstate(u32, buf, 0x7f7c, seg.limit);
8489 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8490
8491 kvm_x86_ops.get_gdt(vcpu, &dt);
8492 put_smstate(u32, buf, 0x7f74, dt.address);
8493 put_smstate(u32, buf, 0x7f70, dt.size);
8494
8495 kvm_x86_ops.get_idt(vcpu, &dt);
8496 put_smstate(u32, buf, 0x7f58, dt.address);
8497 put_smstate(u32, buf, 0x7f54, dt.size);
8498
8499 for (i = 0; i < 6; i++)
8500 enter_smm_save_seg_32(vcpu, buf, i);
8501
8502 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8503
8504 /* revision id */
8505 put_smstate(u32, buf, 0x7efc, 0x00020000);
8506 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8507 }
8508
8509 #ifdef CONFIG_X86_64
8510 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8511 {
8512 struct desc_ptr dt;
8513 struct kvm_segment seg;
8514 unsigned long val;
8515 int i;
8516
8517 for (i = 0; i < 16; i++)
8518 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8519
8520 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8521 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8522
8523 kvm_get_dr(vcpu, 6, &val);
8524 put_smstate(u64, buf, 0x7f68, val);
8525 kvm_get_dr(vcpu, 7, &val);
8526 put_smstate(u64, buf, 0x7f60, val);
8527
8528 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8529 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8530 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8531
8532 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8533
8534 /* revision id */
8535 put_smstate(u32, buf, 0x7efc, 0x00020064);
8536
8537 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8538
8539 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8540 put_smstate(u16, buf, 0x7e90, seg.selector);
8541 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8542 put_smstate(u32, buf, 0x7e94, seg.limit);
8543 put_smstate(u64, buf, 0x7e98, seg.base);
8544
8545 kvm_x86_ops.get_idt(vcpu, &dt);
8546 put_smstate(u32, buf, 0x7e84, dt.size);
8547 put_smstate(u64, buf, 0x7e88, dt.address);
8548
8549 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8550 put_smstate(u16, buf, 0x7e70, seg.selector);
8551 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8552 put_smstate(u32, buf, 0x7e74, seg.limit);
8553 put_smstate(u64, buf, 0x7e78, seg.base);
8554
8555 kvm_x86_ops.get_gdt(vcpu, &dt);
8556 put_smstate(u32, buf, 0x7e64, dt.size);
8557 put_smstate(u64, buf, 0x7e68, dt.address);
8558
8559 for (i = 0; i < 6; i++)
8560 enter_smm_save_seg_64(vcpu, buf, i);
8561 }
8562 #endif
8563
8564 static void enter_smm(struct kvm_vcpu *vcpu)
8565 {
8566 struct kvm_segment cs, ds;
8567 struct desc_ptr dt;
8568 char buf[512];
8569 u32 cr0;
8570
8571 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8572 memset(buf, 0, 512);
8573 #ifdef CONFIG_X86_64
8574 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8575 enter_smm_save_state_64(vcpu, buf);
8576 else
8577 #endif
8578 enter_smm_save_state_32(vcpu, buf);
8579
8580 /*
8581 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8582 * vCPU state (e.g. leave guest mode) after we've saved the state into
8583 * the SMM state-save area.
8584 */
8585 kvm_x86_ops.pre_enter_smm(vcpu, buf);
8586
8587 vcpu->arch.hflags |= HF_SMM_MASK;
8588 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8589
8590 if (kvm_x86_ops.get_nmi_mask(vcpu))
8591 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8592 else
8593 kvm_x86_ops.set_nmi_mask(vcpu, true);
8594
8595 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8596 kvm_rip_write(vcpu, 0x8000);
8597
8598 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8599 kvm_x86_ops.set_cr0(vcpu, cr0);
8600 vcpu->arch.cr0 = cr0;
8601
8602 kvm_x86_ops.set_cr4(vcpu, 0);
8603
8604 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8605 dt.address = dt.size = 0;
8606 kvm_x86_ops.set_idt(vcpu, &dt);
8607
8608 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8609
8610 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8611 cs.base = vcpu->arch.smbase;
8612
8613 ds.selector = 0;
8614 ds.base = 0;
8615
8616 cs.limit = ds.limit = 0xffffffff;
8617 cs.type = ds.type = 0x3;
8618 cs.dpl = ds.dpl = 0;
8619 cs.db = ds.db = 0;
8620 cs.s = ds.s = 1;
8621 cs.l = ds.l = 0;
8622 cs.g = ds.g = 1;
8623 cs.avl = ds.avl = 0;
8624 cs.present = ds.present = 1;
8625 cs.unusable = ds.unusable = 0;
8626 cs.padding = ds.padding = 0;
8627
8628 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8629 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8630 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8631 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8632 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8633 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8634
8635 #ifdef CONFIG_X86_64
8636 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8637 kvm_x86_ops.set_efer(vcpu, 0);
8638 #endif
8639
8640 kvm_update_cpuid_runtime(vcpu);
8641 kvm_mmu_reset_context(vcpu);
8642 }
8643
8644 static void process_smi(struct kvm_vcpu *vcpu)
8645 {
8646 vcpu->arch.smi_pending = true;
8647 kvm_make_request(KVM_REQ_EVENT, vcpu);
8648 }
8649
8650 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8651 unsigned long *vcpu_bitmap)
8652 {
8653 cpumask_var_t cpus;
8654
8655 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8656
8657 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8658 NULL, vcpu_bitmap, cpus);
8659
8660 free_cpumask_var(cpus);
8661 }
8662
8663 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8664 {
8665 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8666 }
8667
8668 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8669 {
8670 if (!lapic_in_kernel(vcpu))
8671 return;
8672
8673 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8674 kvm_apic_update_apicv(vcpu);
8675 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8676 }
8677 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8678
8679 /*
8680 * NOTE: Do not hold any lock prior to calling this.
8681 *
8682 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8683 * locked, because it calls __x86_set_memory_region() which does
8684 * synchronize_srcu(&kvm->srcu).
8685 */
8686 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8687 {
8688 struct kvm_vcpu *except;
8689 unsigned long old, new, expected;
8690
8691 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8692 !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8693 return;
8694
8695 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8696 do {
8697 expected = new = old;
8698 if (activate)
8699 __clear_bit(bit, &new);
8700 else
8701 __set_bit(bit, &new);
8702 if (new == old)
8703 break;
8704 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8705 } while (old != expected);
8706
8707 if (!!old == !!new)
8708 return;
8709
8710 trace_kvm_apicv_update_request(activate, bit);
8711 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8712 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8713
8714 /*
8715 * Sending request to update APICV for all other vcpus,
8716 * while update the calling vcpu immediately instead of
8717 * waiting for another #VMEXIT to handle the request.
8718 */
8719 except = kvm_get_running_vcpu();
8720 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8721 except);
8722 if (except)
8723 kvm_vcpu_update_apicv(except);
8724 }
8725 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8726
8727 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8728 {
8729 if (!kvm_apic_present(vcpu))
8730 return;
8731
8732 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8733
8734 if (irqchip_split(vcpu->kvm))
8735 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8736 else {
8737 if (vcpu->arch.apicv_active)
8738 kvm_x86_ops.sync_pir_to_irr(vcpu);
8739 if (ioapic_in_kernel(vcpu->kvm))
8740 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8741 }
8742
8743 if (is_guest_mode(vcpu))
8744 vcpu->arch.load_eoi_exitmap_pending = true;
8745 else
8746 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8747 }
8748
8749 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8750 {
8751 u64 eoi_exit_bitmap[4];
8752
8753 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8754 return;
8755
8756 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8757 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8758 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8759 }
8760
8761 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8762 unsigned long start, unsigned long end)
8763 {
8764 unsigned long apic_address;
8765
8766 /*
8767 * The physical address of apic access page is stored in the VMCS.
8768 * Update it when it becomes invalid.
8769 */
8770 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8771 if (start <= apic_address && apic_address < end)
8772 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8773 }
8774
8775 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8776 {
8777 if (!lapic_in_kernel(vcpu))
8778 return;
8779
8780 if (!kvm_x86_ops.set_apic_access_page_addr)
8781 return;
8782
8783 kvm_x86_ops.set_apic_access_page_addr(vcpu);
8784 }
8785
8786 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8787 {
8788 smp_send_reschedule(vcpu->cpu);
8789 }
8790 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8791
8792 /*
8793 * Returns 1 to let vcpu_run() continue the guest execution loop without
8794 * exiting to the userspace. Otherwise, the value will be returned to the
8795 * userspace.
8796 */
8797 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8798 {
8799 int r;
8800 bool req_int_win =
8801 dm_request_for_irq_injection(vcpu) &&
8802 kvm_cpu_accept_dm_intr(vcpu);
8803 fastpath_t exit_fastpath;
8804
8805 bool req_immediate_exit = false;
8806
8807 /* Forbid vmenter if vcpu dirty ring is soft-full */
8808 if (unlikely(vcpu->kvm->dirty_ring_size &&
8809 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
8810 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
8811 trace_kvm_dirty_ring_exit(vcpu);
8812 r = 0;
8813 goto out;
8814 }
8815
8816 if (kvm_request_pending(vcpu)) {
8817 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8818 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8819 r = 0;
8820 goto out;
8821 }
8822 }
8823 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8824 kvm_mmu_unload(vcpu);
8825 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8826 __kvm_migrate_timers(vcpu);
8827 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8828 kvm_gen_update_masterclock(vcpu->kvm);
8829 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8830 kvm_gen_kvmclock_update(vcpu);
8831 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8832 r = kvm_guest_time_update(vcpu);
8833 if (unlikely(r))
8834 goto out;
8835 }
8836 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8837 kvm_mmu_sync_roots(vcpu);
8838 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8839 kvm_mmu_load_pgd(vcpu);
8840 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8841 kvm_vcpu_flush_tlb_all(vcpu);
8842
8843 /* Flushing all ASIDs flushes the current ASID... */
8844 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8845 }
8846 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8847 kvm_vcpu_flush_tlb_current(vcpu);
8848 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8849 kvm_vcpu_flush_tlb_guest(vcpu);
8850
8851 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8852 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8853 r = 0;
8854 goto out;
8855 }
8856 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8857 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8858 vcpu->mmio_needed = 0;
8859 r = 0;
8860 goto out;
8861 }
8862 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8863 /* Page is swapped out. Do synthetic halt */
8864 vcpu->arch.apf.halted = true;
8865 r = 1;
8866 goto out;
8867 }
8868 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8869 record_steal_time(vcpu);
8870 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8871 process_smi(vcpu);
8872 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8873 process_nmi(vcpu);
8874 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8875 kvm_pmu_handle_event(vcpu);
8876 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8877 kvm_pmu_deliver_pmi(vcpu);
8878 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8879 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8880 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8881 vcpu->arch.ioapic_handled_vectors)) {
8882 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8883 vcpu->run->eoi.vector =
8884 vcpu->arch.pending_ioapic_eoi;
8885 r = 0;
8886 goto out;
8887 }
8888 }
8889 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8890 vcpu_scan_ioapic(vcpu);
8891 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8892 vcpu_load_eoi_exitmap(vcpu);
8893 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8894 kvm_vcpu_reload_apic_access_page(vcpu);
8895 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8896 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8897 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8898 r = 0;
8899 goto out;
8900 }
8901 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8902 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8903 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8904 r = 0;
8905 goto out;
8906 }
8907 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8908 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8909 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8910 r = 0;
8911 goto out;
8912 }
8913
8914 /*
8915 * KVM_REQ_HV_STIMER has to be processed after
8916 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8917 * depend on the guest clock being up-to-date
8918 */
8919 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8920 kvm_hv_process_stimers(vcpu);
8921 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8922 kvm_vcpu_update_apicv(vcpu);
8923 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8924 kvm_check_async_pf_completion(vcpu);
8925 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8926 kvm_x86_ops.msr_filter_changed(vcpu);
8927 }
8928
8929 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8930 ++vcpu->stat.req_event;
8931 kvm_apic_accept_events(vcpu);
8932 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8933 r = 1;
8934 goto out;
8935 }
8936
8937 inject_pending_event(vcpu, &req_immediate_exit);
8938 if (req_int_win)
8939 kvm_x86_ops.enable_irq_window(vcpu);
8940
8941 if (kvm_lapic_enabled(vcpu)) {
8942 update_cr8_intercept(vcpu);
8943 kvm_lapic_sync_to_vapic(vcpu);
8944 }
8945 }
8946
8947 r = kvm_mmu_reload(vcpu);
8948 if (unlikely(r)) {
8949 goto cancel_injection;
8950 }
8951
8952 preempt_disable();
8953
8954 kvm_x86_ops.prepare_guest_switch(vcpu);
8955
8956 /*
8957 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8958 * IPI are then delayed after guest entry, which ensures that they
8959 * result in virtual interrupt delivery.
8960 */
8961 local_irq_disable();
8962 vcpu->mode = IN_GUEST_MODE;
8963
8964 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8965
8966 /*
8967 * 1) We should set ->mode before checking ->requests. Please see
8968 * the comment in kvm_vcpu_exiting_guest_mode().
8969 *
8970 * 2) For APICv, we should set ->mode before checking PID.ON. This
8971 * pairs with the memory barrier implicit in pi_test_and_set_on
8972 * (see vmx_deliver_posted_interrupt).
8973 *
8974 * 3) This also orders the write to mode from any reads to the page
8975 * tables done while the VCPU is running. Please see the comment
8976 * in kvm_flush_remote_tlbs.
8977 */
8978 smp_mb__after_srcu_read_unlock();
8979
8980 /*
8981 * This handles the case where a posted interrupt was
8982 * notified with kvm_vcpu_kick.
8983 */
8984 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8985 kvm_x86_ops.sync_pir_to_irr(vcpu);
8986
8987 if (kvm_vcpu_exit_request(vcpu)) {
8988 vcpu->mode = OUTSIDE_GUEST_MODE;
8989 smp_wmb();
8990 local_irq_enable();
8991 preempt_enable();
8992 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8993 r = 1;
8994 goto cancel_injection;
8995 }
8996
8997 if (req_immediate_exit) {
8998 kvm_make_request(KVM_REQ_EVENT, vcpu);
8999 kvm_x86_ops.request_immediate_exit(vcpu);
9000 }
9001
9002 fpregs_assert_state_consistent();
9003 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9004 switch_fpu_return();
9005
9006 if (unlikely(vcpu->arch.switch_db_regs)) {
9007 set_debugreg(0, 7);
9008 set_debugreg(vcpu->arch.eff_db[0], 0);
9009 set_debugreg(vcpu->arch.eff_db[1], 1);
9010 set_debugreg(vcpu->arch.eff_db[2], 2);
9011 set_debugreg(vcpu->arch.eff_db[3], 3);
9012 set_debugreg(vcpu->arch.dr6, 6);
9013 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9014 }
9015
9016 exit_fastpath = kvm_x86_ops.run(vcpu);
9017
9018 /*
9019 * Do this here before restoring debug registers on the host. And
9020 * since we do this before handling the vmexit, a DR access vmexit
9021 * can (a) read the correct value of the debug registers, (b) set
9022 * KVM_DEBUGREG_WONT_EXIT again.
9023 */
9024 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
9025 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
9026 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
9027 kvm_update_dr0123(vcpu);
9028 kvm_update_dr7(vcpu);
9029 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9030 }
9031
9032 /*
9033 * If the guest has used debug registers, at least dr7
9034 * will be disabled while returning to the host.
9035 * If we don't have active breakpoints in the host, we don't
9036 * care about the messed up debug address registers. But if
9037 * we have some of them active, restore the old state.
9038 */
9039 if (hw_breakpoint_active())
9040 hw_breakpoint_restore();
9041
9042 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
9043 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
9044
9045 vcpu->mode = OUTSIDE_GUEST_MODE;
9046 smp_wmb();
9047
9048 kvm_x86_ops.handle_exit_irqoff(vcpu);
9049
9050 /*
9051 * Consume any pending interrupts, including the possible source of
9052 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
9053 * An instruction is required after local_irq_enable() to fully unblock
9054 * interrupts on processors that implement an interrupt shadow, the
9055 * stat.exits increment will do nicely.
9056 */
9057 kvm_before_interrupt(vcpu);
9058 local_irq_enable();
9059 ++vcpu->stat.exits;
9060 local_irq_disable();
9061 kvm_after_interrupt(vcpu);
9062
9063 if (lapic_in_kernel(vcpu)) {
9064 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
9065 if (delta != S64_MIN) {
9066 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
9067 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
9068 }
9069 }
9070
9071 local_irq_enable();
9072 preempt_enable();
9073
9074 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9075
9076 /*
9077 * Profile KVM exit RIPs:
9078 */
9079 if (unlikely(prof_on == KVM_PROFILING)) {
9080 unsigned long rip = kvm_rip_read(vcpu);
9081 profile_hit(KVM_PROFILING, (void *)rip);
9082 }
9083
9084 if (unlikely(vcpu->arch.tsc_always_catchup))
9085 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9086
9087 if (vcpu->arch.apic_attention)
9088 kvm_lapic_sync_from_vapic(vcpu);
9089
9090 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
9091 return r;
9092
9093 cancel_injection:
9094 if (req_immediate_exit)
9095 kvm_make_request(KVM_REQ_EVENT, vcpu);
9096 kvm_x86_ops.cancel_injection(vcpu);
9097 if (unlikely(vcpu->arch.apic_attention))
9098 kvm_lapic_sync_from_vapic(vcpu);
9099 out:
9100 return r;
9101 }
9102
9103 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
9104 {
9105 if (!kvm_arch_vcpu_runnable(vcpu) &&
9106 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
9107 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9108 kvm_vcpu_block(vcpu);
9109 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9110
9111 if (kvm_x86_ops.post_block)
9112 kvm_x86_ops.post_block(vcpu);
9113
9114 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
9115 return 1;
9116 }
9117
9118 kvm_apic_accept_events(vcpu);
9119 switch(vcpu->arch.mp_state) {
9120 case KVM_MP_STATE_HALTED:
9121 case KVM_MP_STATE_AP_RESET_HOLD:
9122 vcpu->arch.pv.pv_unhalted = false;
9123 vcpu->arch.mp_state =
9124 KVM_MP_STATE_RUNNABLE;
9125 fallthrough;
9126 case KVM_MP_STATE_RUNNABLE:
9127 vcpu->arch.apf.halted = false;
9128 break;
9129 case KVM_MP_STATE_INIT_RECEIVED:
9130 break;
9131 default:
9132 return -EINTR;
9133 }
9134 return 1;
9135 }
9136
9137 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
9138 {
9139 if (is_guest_mode(vcpu))
9140 kvm_x86_ops.nested_ops->check_events(vcpu);
9141
9142 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
9143 !vcpu->arch.apf.halted);
9144 }
9145
9146 static int vcpu_run(struct kvm_vcpu *vcpu)
9147 {
9148 int r;
9149 struct kvm *kvm = vcpu->kvm;
9150
9151 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9152 vcpu->arch.l1tf_flush_l1d = true;
9153
9154 for (;;) {
9155 if (kvm_vcpu_running(vcpu)) {
9156 r = vcpu_enter_guest(vcpu);
9157 } else {
9158 r = vcpu_block(kvm, vcpu);
9159 }
9160
9161 if (r <= 0)
9162 break;
9163
9164 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
9165 if (kvm_cpu_has_pending_timer(vcpu))
9166 kvm_inject_pending_timer_irqs(vcpu);
9167
9168 if (dm_request_for_irq_injection(vcpu) &&
9169 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9170 r = 0;
9171 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9172 ++vcpu->stat.request_irq_exits;
9173 break;
9174 }
9175
9176 if (__xfer_to_guest_mode_work_pending()) {
9177 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9178 r = xfer_to_guest_mode_handle_work(vcpu);
9179 if (r)
9180 return r;
9181 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9182 }
9183 }
9184
9185 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9186
9187 return r;
9188 }
9189
9190 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9191 {
9192 int r;
9193
9194 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9195 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9196 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9197 return r;
9198 }
9199
9200 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9201 {
9202 BUG_ON(!vcpu->arch.pio.count);
9203
9204 return complete_emulated_io(vcpu);
9205 }
9206
9207 /*
9208 * Implements the following, as a state machine:
9209 *
9210 * read:
9211 * for each fragment
9212 * for each mmio piece in the fragment
9213 * write gpa, len
9214 * exit
9215 * copy data
9216 * execute insn
9217 *
9218 * write:
9219 * for each fragment
9220 * for each mmio piece in the fragment
9221 * write gpa, len
9222 * copy data
9223 * exit
9224 */
9225 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9226 {
9227 struct kvm_run *run = vcpu->run;
9228 struct kvm_mmio_fragment *frag;
9229 unsigned len;
9230
9231 BUG_ON(!vcpu->mmio_needed);
9232
9233 /* Complete previous fragment */
9234 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9235 len = min(8u, frag->len);
9236 if (!vcpu->mmio_is_write)
9237 memcpy(frag->data, run->mmio.data, len);
9238
9239 if (frag->len <= 8) {
9240 /* Switch to the next fragment. */
9241 frag++;
9242 vcpu->mmio_cur_fragment++;
9243 } else {
9244 /* Go forward to the next mmio piece. */
9245 frag->data += len;
9246 frag->gpa += len;
9247 frag->len -= len;
9248 }
9249
9250 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9251 vcpu->mmio_needed = 0;
9252
9253 /* FIXME: return into emulator if single-stepping. */
9254 if (vcpu->mmio_is_write)
9255 return 1;
9256 vcpu->mmio_read_completed = 1;
9257 return complete_emulated_io(vcpu);
9258 }
9259
9260 run->exit_reason = KVM_EXIT_MMIO;
9261 run->mmio.phys_addr = frag->gpa;
9262 if (vcpu->mmio_is_write)
9263 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9264 run->mmio.len = min(8u, frag->len);
9265 run->mmio.is_write = vcpu->mmio_is_write;
9266 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9267 return 0;
9268 }
9269
9270 static void kvm_save_current_fpu(struct fpu *fpu)
9271 {
9272 /*
9273 * If the target FPU state is not resident in the CPU registers, just
9274 * memcpy() from current, else save CPU state directly to the target.
9275 */
9276 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9277 memcpy(&fpu->state, &current->thread.fpu.state,
9278 fpu_kernel_xstate_size);
9279 else
9280 copy_fpregs_to_fpstate(fpu);
9281 }
9282
9283 /* Swap (qemu) user FPU context for the guest FPU context. */
9284 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9285 {
9286 fpregs_lock();
9287
9288 kvm_save_current_fpu(vcpu->arch.user_fpu);
9289
9290 /*
9291 * Guests with protected state can't have it set by the hypervisor,
9292 * so skip trying to set it.
9293 */
9294 if (vcpu->arch.guest_fpu)
9295 /* PKRU is separately restored in kvm_x86_ops.run. */
9296 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9297 ~XFEATURE_MASK_PKRU);
9298
9299 fpregs_mark_activate();
9300 fpregs_unlock();
9301
9302 trace_kvm_fpu(1);
9303 }
9304
9305 /* When vcpu_run ends, restore user space FPU context. */
9306 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9307 {
9308 fpregs_lock();
9309
9310 /*
9311 * Guests with protected state can't have it read by the hypervisor,
9312 * so skip trying to save it.
9313 */
9314 if (vcpu->arch.guest_fpu)
9315 kvm_save_current_fpu(vcpu->arch.guest_fpu);
9316
9317 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9318
9319 fpregs_mark_activate();
9320 fpregs_unlock();
9321
9322 ++vcpu->stat.fpu_reload;
9323 trace_kvm_fpu(0);
9324 }
9325
9326 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9327 {
9328 struct kvm_run *kvm_run = vcpu->run;
9329 int r;
9330
9331 vcpu_load(vcpu);
9332 kvm_sigset_activate(vcpu);
9333 kvm_load_guest_fpu(vcpu);
9334
9335 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9336 if (kvm_run->immediate_exit) {
9337 r = -EINTR;
9338 goto out;
9339 }
9340 kvm_vcpu_block(vcpu);
9341 kvm_apic_accept_events(vcpu);
9342 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9343 r = -EAGAIN;
9344 if (signal_pending(current)) {
9345 r = -EINTR;
9346 kvm_run->exit_reason = KVM_EXIT_INTR;
9347 ++vcpu->stat.signal_exits;
9348 }
9349 goto out;
9350 }
9351
9352 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9353 r = -EINVAL;
9354 goto out;
9355 }
9356
9357 if (kvm_run->kvm_dirty_regs) {
9358 r = sync_regs(vcpu);
9359 if (r != 0)
9360 goto out;
9361 }
9362
9363 /* re-sync apic's tpr */
9364 if (!lapic_in_kernel(vcpu)) {
9365 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9366 r = -EINVAL;
9367 goto out;
9368 }
9369 }
9370
9371 if (unlikely(vcpu->arch.complete_userspace_io)) {
9372 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9373 vcpu->arch.complete_userspace_io = NULL;
9374 r = cui(vcpu);
9375 if (r <= 0)
9376 goto out;
9377 } else
9378 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9379
9380 if (kvm_run->immediate_exit)
9381 r = -EINTR;
9382 else
9383 r = vcpu_run(vcpu);
9384
9385 out:
9386 kvm_put_guest_fpu(vcpu);
9387 if (kvm_run->kvm_valid_regs)
9388 store_regs(vcpu);
9389 post_kvm_run_save(vcpu);
9390 kvm_sigset_deactivate(vcpu);
9391
9392 vcpu_put(vcpu);
9393 return r;
9394 }
9395
9396 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9397 {
9398 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9399 /*
9400 * We are here if userspace calls get_regs() in the middle of
9401 * instruction emulation. Registers state needs to be copied
9402 * back from emulation context to vcpu. Userspace shouldn't do
9403 * that usually, but some bad designed PV devices (vmware
9404 * backdoor interface) need this to work
9405 */
9406 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9407 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9408 }
9409 regs->rax = kvm_rax_read(vcpu);
9410 regs->rbx = kvm_rbx_read(vcpu);
9411 regs->rcx = kvm_rcx_read(vcpu);
9412 regs->rdx = kvm_rdx_read(vcpu);
9413 regs->rsi = kvm_rsi_read(vcpu);
9414 regs->rdi = kvm_rdi_read(vcpu);
9415 regs->rsp = kvm_rsp_read(vcpu);
9416 regs->rbp = kvm_rbp_read(vcpu);
9417 #ifdef CONFIG_X86_64
9418 regs->r8 = kvm_r8_read(vcpu);
9419 regs->r9 = kvm_r9_read(vcpu);
9420 regs->r10 = kvm_r10_read(vcpu);
9421 regs->r11 = kvm_r11_read(vcpu);
9422 regs->r12 = kvm_r12_read(vcpu);
9423 regs->r13 = kvm_r13_read(vcpu);
9424 regs->r14 = kvm_r14_read(vcpu);
9425 regs->r15 = kvm_r15_read(vcpu);
9426 #endif
9427
9428 regs->rip = kvm_rip_read(vcpu);
9429 regs->rflags = kvm_get_rflags(vcpu);
9430 }
9431
9432 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9433 {
9434 vcpu_load(vcpu);
9435 __get_regs(vcpu, regs);
9436 vcpu_put(vcpu);
9437 return 0;
9438 }
9439
9440 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9441 {
9442 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9443 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9444
9445 kvm_rax_write(vcpu, regs->rax);
9446 kvm_rbx_write(vcpu, regs->rbx);
9447 kvm_rcx_write(vcpu, regs->rcx);
9448 kvm_rdx_write(vcpu, regs->rdx);
9449 kvm_rsi_write(vcpu, regs->rsi);
9450 kvm_rdi_write(vcpu, regs->rdi);
9451 kvm_rsp_write(vcpu, regs->rsp);
9452 kvm_rbp_write(vcpu, regs->rbp);
9453 #ifdef CONFIG_X86_64
9454 kvm_r8_write(vcpu, regs->r8);
9455 kvm_r9_write(vcpu, regs->r9);
9456 kvm_r10_write(vcpu, regs->r10);
9457 kvm_r11_write(vcpu, regs->r11);
9458 kvm_r12_write(vcpu, regs->r12);
9459 kvm_r13_write(vcpu, regs->r13);
9460 kvm_r14_write(vcpu, regs->r14);
9461 kvm_r15_write(vcpu, regs->r15);
9462 #endif
9463
9464 kvm_rip_write(vcpu, regs->rip);
9465 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9466
9467 vcpu->arch.exception.pending = false;
9468
9469 kvm_make_request(KVM_REQ_EVENT, vcpu);
9470 }
9471
9472 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9473 {
9474 vcpu_load(vcpu);
9475 __set_regs(vcpu, regs);
9476 vcpu_put(vcpu);
9477 return 0;
9478 }
9479
9480 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9481 {
9482 struct kvm_segment cs;
9483
9484 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9485 *db = cs.db;
9486 *l = cs.l;
9487 }
9488 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9489
9490 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9491 {
9492 struct desc_ptr dt;
9493
9494 if (vcpu->arch.guest_state_protected)
9495 goto skip_protected_regs;
9496
9497 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9498 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9499 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9500 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9501 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9502 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9503
9504 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9505 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9506
9507 kvm_x86_ops.get_idt(vcpu, &dt);
9508 sregs->idt.limit = dt.size;
9509 sregs->idt.base = dt.address;
9510 kvm_x86_ops.get_gdt(vcpu, &dt);
9511 sregs->gdt.limit = dt.size;
9512 sregs->gdt.base = dt.address;
9513
9514 sregs->cr2 = vcpu->arch.cr2;
9515 sregs->cr3 = kvm_read_cr3(vcpu);
9516
9517 skip_protected_regs:
9518 sregs->cr0 = kvm_read_cr0(vcpu);
9519 sregs->cr4 = kvm_read_cr4(vcpu);
9520 sregs->cr8 = kvm_get_cr8(vcpu);
9521 sregs->efer = vcpu->arch.efer;
9522 sregs->apic_base = kvm_get_apic_base(vcpu);
9523
9524 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9525
9526 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9527 set_bit(vcpu->arch.interrupt.nr,
9528 (unsigned long *)sregs->interrupt_bitmap);
9529 }
9530
9531 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9532 struct kvm_sregs *sregs)
9533 {
9534 vcpu_load(vcpu);
9535 __get_sregs(vcpu, sregs);
9536 vcpu_put(vcpu);
9537 return 0;
9538 }
9539
9540 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9541 struct kvm_mp_state *mp_state)
9542 {
9543 vcpu_load(vcpu);
9544 if (kvm_mpx_supported())
9545 kvm_load_guest_fpu(vcpu);
9546
9547 kvm_apic_accept_events(vcpu);
9548 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
9549 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
9550 vcpu->arch.pv.pv_unhalted)
9551 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9552 else
9553 mp_state->mp_state = vcpu->arch.mp_state;
9554
9555 if (kvm_mpx_supported())
9556 kvm_put_guest_fpu(vcpu);
9557 vcpu_put(vcpu);
9558 return 0;
9559 }
9560
9561 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9562 struct kvm_mp_state *mp_state)
9563 {
9564 int ret = -EINVAL;
9565
9566 vcpu_load(vcpu);
9567
9568 if (!lapic_in_kernel(vcpu) &&
9569 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9570 goto out;
9571
9572 /*
9573 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9574 * INIT state; latched init should be reported using
9575 * KVM_SET_VCPU_EVENTS, so reject it here.
9576 */
9577 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9578 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9579 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9580 goto out;
9581
9582 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9583 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9584 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9585 } else
9586 vcpu->arch.mp_state = mp_state->mp_state;
9587 kvm_make_request(KVM_REQ_EVENT, vcpu);
9588
9589 ret = 0;
9590 out:
9591 vcpu_put(vcpu);
9592 return ret;
9593 }
9594
9595 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9596 int reason, bool has_error_code, u32 error_code)
9597 {
9598 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9599 int ret;
9600
9601 init_emulate_ctxt(vcpu);
9602
9603 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9604 has_error_code, error_code);
9605 if (ret) {
9606 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9607 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9608 vcpu->run->internal.ndata = 0;
9609 return 0;
9610 }
9611
9612 kvm_rip_write(vcpu, ctxt->eip);
9613 kvm_set_rflags(vcpu, ctxt->eflags);
9614 return 1;
9615 }
9616 EXPORT_SYMBOL_GPL(kvm_task_switch);
9617
9618 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9619 {
9620 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9621 /*
9622 * When EFER.LME and CR0.PG are set, the processor is in
9623 * 64-bit mode (though maybe in a 32-bit code segment).
9624 * CR4.PAE and EFER.LMA must be set.
9625 */
9626 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
9627 return false;
9628 if (sregs->cr3 & vcpu->arch.cr3_lm_rsvd_bits)
9629 return false;
9630 } else {
9631 /*
9632 * Not in 64-bit mode: EFER.LMA is clear and the code
9633 * segment cannot be 64-bit.
9634 */
9635 if (sregs->efer & EFER_LMA || sregs->cs.l)
9636 return false;
9637 }
9638
9639 return kvm_is_valid_cr4(vcpu, sregs->cr4);
9640 }
9641
9642 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9643 {
9644 struct msr_data apic_base_msr;
9645 int mmu_reset_needed = 0;
9646 int pending_vec, max_bits, idx;
9647 struct desc_ptr dt;
9648 int ret = -EINVAL;
9649
9650 if (!kvm_is_valid_sregs(vcpu, sregs))
9651 goto out;
9652
9653 apic_base_msr.data = sregs->apic_base;
9654 apic_base_msr.host_initiated = true;
9655 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9656 goto out;
9657
9658 if (vcpu->arch.guest_state_protected)
9659 goto skip_protected_regs;
9660
9661 dt.size = sregs->idt.limit;
9662 dt.address = sregs->idt.base;
9663 kvm_x86_ops.set_idt(vcpu, &dt);
9664 dt.size = sregs->gdt.limit;
9665 dt.address = sregs->gdt.base;
9666 kvm_x86_ops.set_gdt(vcpu, &dt);
9667
9668 vcpu->arch.cr2 = sregs->cr2;
9669 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9670 vcpu->arch.cr3 = sregs->cr3;
9671 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9672
9673 kvm_set_cr8(vcpu, sregs->cr8);
9674
9675 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9676 kvm_x86_ops.set_efer(vcpu, sregs->efer);
9677
9678 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9679 kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9680 vcpu->arch.cr0 = sregs->cr0;
9681
9682 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9683 kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9684
9685 idx = srcu_read_lock(&vcpu->kvm->srcu);
9686 if (is_pae_paging(vcpu)) {
9687 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9688 mmu_reset_needed = 1;
9689 }
9690 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9691
9692 if (mmu_reset_needed)
9693 kvm_mmu_reset_context(vcpu);
9694
9695 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9696 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9697 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9698 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9699 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9700 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9701
9702 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9703 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9704
9705 update_cr8_intercept(vcpu);
9706
9707 /* Older userspace won't unhalt the vcpu on reset. */
9708 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9709 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9710 !is_protmode(vcpu))
9711 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9712
9713 skip_protected_regs:
9714 max_bits = KVM_NR_INTERRUPTS;
9715 pending_vec = find_first_bit(
9716 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9717 if (pending_vec < max_bits) {
9718 kvm_queue_interrupt(vcpu, pending_vec, false);
9719 pr_debug("Set back pending irq %d\n", pending_vec);
9720 }
9721
9722 kvm_make_request(KVM_REQ_EVENT, vcpu);
9723
9724 ret = 0;
9725 out:
9726 return ret;
9727 }
9728
9729 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9730 struct kvm_sregs *sregs)
9731 {
9732 int ret;
9733
9734 vcpu_load(vcpu);
9735 ret = __set_sregs(vcpu, sregs);
9736 vcpu_put(vcpu);
9737 return ret;
9738 }
9739
9740 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9741 struct kvm_guest_debug *dbg)
9742 {
9743 unsigned long rflags;
9744 int i, r;
9745
9746 if (vcpu->arch.guest_state_protected)
9747 return -EINVAL;
9748
9749 vcpu_load(vcpu);
9750
9751 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9752 r = -EBUSY;
9753 if (vcpu->arch.exception.pending)
9754 goto out;
9755 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9756 kvm_queue_exception(vcpu, DB_VECTOR);
9757 else
9758 kvm_queue_exception(vcpu, BP_VECTOR);
9759 }
9760
9761 /*
9762 * Read rflags as long as potentially injected trace flags are still
9763 * filtered out.
9764 */
9765 rflags = kvm_get_rflags(vcpu);
9766
9767 vcpu->guest_debug = dbg->control;
9768 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9769 vcpu->guest_debug = 0;
9770
9771 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9772 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9773 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9774 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9775 } else {
9776 for (i = 0; i < KVM_NR_DB_REGS; i++)
9777 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9778 }
9779 kvm_update_dr7(vcpu);
9780
9781 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9782 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9783 get_segment_base(vcpu, VCPU_SREG_CS);
9784
9785 /*
9786 * Trigger an rflags update that will inject or remove the trace
9787 * flags.
9788 */
9789 kvm_set_rflags(vcpu, rflags);
9790
9791 kvm_x86_ops.update_exception_bitmap(vcpu);
9792
9793 r = 0;
9794
9795 out:
9796 vcpu_put(vcpu);
9797 return r;
9798 }
9799
9800 /*
9801 * Translate a guest virtual address to a guest physical address.
9802 */
9803 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9804 struct kvm_translation *tr)
9805 {
9806 unsigned long vaddr = tr->linear_address;
9807 gpa_t gpa;
9808 int idx;
9809
9810 vcpu_load(vcpu);
9811
9812 idx = srcu_read_lock(&vcpu->kvm->srcu);
9813 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9814 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9815 tr->physical_address = gpa;
9816 tr->valid = gpa != UNMAPPED_GVA;
9817 tr->writeable = 1;
9818 tr->usermode = 0;
9819
9820 vcpu_put(vcpu);
9821 return 0;
9822 }
9823
9824 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9825 {
9826 struct fxregs_state *fxsave;
9827
9828 if (!vcpu->arch.guest_fpu)
9829 return 0;
9830
9831 vcpu_load(vcpu);
9832
9833 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9834 memcpy(fpu->fpr, fxsave->st_space, 128);
9835 fpu->fcw = fxsave->cwd;
9836 fpu->fsw = fxsave->swd;
9837 fpu->ftwx = fxsave->twd;
9838 fpu->last_opcode = fxsave->fop;
9839 fpu->last_ip = fxsave->rip;
9840 fpu->last_dp = fxsave->rdp;
9841 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9842
9843 vcpu_put(vcpu);
9844 return 0;
9845 }
9846
9847 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9848 {
9849 struct fxregs_state *fxsave;
9850
9851 if (!vcpu->arch.guest_fpu)
9852 return 0;
9853
9854 vcpu_load(vcpu);
9855
9856 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9857
9858 memcpy(fxsave->st_space, fpu->fpr, 128);
9859 fxsave->cwd = fpu->fcw;
9860 fxsave->swd = fpu->fsw;
9861 fxsave->twd = fpu->ftwx;
9862 fxsave->fop = fpu->last_opcode;
9863 fxsave->rip = fpu->last_ip;
9864 fxsave->rdp = fpu->last_dp;
9865 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9866
9867 vcpu_put(vcpu);
9868 return 0;
9869 }
9870
9871 static void store_regs(struct kvm_vcpu *vcpu)
9872 {
9873 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9874
9875 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9876 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9877
9878 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9879 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9880
9881 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9882 kvm_vcpu_ioctl_x86_get_vcpu_events(
9883 vcpu, &vcpu->run->s.regs.events);
9884 }
9885
9886 static int sync_regs(struct kvm_vcpu *vcpu)
9887 {
9888 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9889 return -EINVAL;
9890
9891 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9892 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9893 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9894 }
9895 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9896 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9897 return -EINVAL;
9898 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9899 }
9900 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9901 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9902 vcpu, &vcpu->run->s.regs.events))
9903 return -EINVAL;
9904 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9905 }
9906
9907 return 0;
9908 }
9909
9910 static void fx_init(struct kvm_vcpu *vcpu)
9911 {
9912 if (!vcpu->arch.guest_fpu)
9913 return;
9914
9915 fpstate_init(&vcpu->arch.guest_fpu->state);
9916 if (boot_cpu_has(X86_FEATURE_XSAVES))
9917 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9918 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9919
9920 /*
9921 * Ensure guest xcr0 is valid for loading
9922 */
9923 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9924
9925 vcpu->arch.cr0 |= X86_CR0_ET;
9926 }
9927
9928 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu)
9929 {
9930 if (vcpu->arch.guest_fpu) {
9931 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9932 vcpu->arch.guest_fpu = NULL;
9933 }
9934 }
9935 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu);
9936
9937 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9938 {
9939 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9940 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9941 "guest TSC will not be reliable\n");
9942
9943 return 0;
9944 }
9945
9946 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9947 {
9948 struct page *page;
9949 int r;
9950
9951 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9952 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9953 else
9954 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9955
9956 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9957
9958 r = kvm_mmu_create(vcpu);
9959 if (r < 0)
9960 return r;
9961
9962 if (irqchip_in_kernel(vcpu->kvm)) {
9963 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9964 if (r < 0)
9965 goto fail_mmu_destroy;
9966 if (kvm_apicv_activated(vcpu->kvm))
9967 vcpu->arch.apicv_active = true;
9968 } else
9969 static_key_slow_inc(&kvm_no_apic_vcpu);
9970
9971 r = -ENOMEM;
9972
9973 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
9974 if (!page)
9975 goto fail_free_lapic;
9976 vcpu->arch.pio_data = page_address(page);
9977
9978 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9979 GFP_KERNEL_ACCOUNT);
9980 if (!vcpu->arch.mce_banks)
9981 goto fail_free_pio_data;
9982 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9983
9984 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9985 GFP_KERNEL_ACCOUNT))
9986 goto fail_free_mce_banks;
9987
9988 if (!alloc_emulate_ctxt(vcpu))
9989 goto free_wbinvd_dirty_mask;
9990
9991 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9992 GFP_KERNEL_ACCOUNT);
9993 if (!vcpu->arch.user_fpu) {
9994 pr_err("kvm: failed to allocate userspace's fpu\n");
9995 goto free_emulate_ctxt;
9996 }
9997
9998 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9999 GFP_KERNEL_ACCOUNT);
10000 if (!vcpu->arch.guest_fpu) {
10001 pr_err("kvm: failed to allocate vcpu's fpu\n");
10002 goto free_user_fpu;
10003 }
10004 fx_init(vcpu);
10005
10006 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
10007 vcpu->arch.cr3_lm_rsvd_bits = rsvd_bits(cpuid_maxphyaddr(vcpu), 63);
10008
10009 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
10010
10011 kvm_async_pf_hash_reset(vcpu);
10012 kvm_pmu_init(vcpu);
10013
10014 vcpu->arch.pending_external_vector = -1;
10015 vcpu->arch.preempted_in_kernel = false;
10016
10017 kvm_hv_vcpu_init(vcpu);
10018
10019 r = kvm_x86_ops.vcpu_create(vcpu);
10020 if (r)
10021 goto free_guest_fpu;
10022
10023 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
10024 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
10025 kvm_vcpu_mtrr_init(vcpu);
10026 vcpu_load(vcpu);
10027 kvm_vcpu_reset(vcpu, false);
10028 kvm_init_mmu(vcpu, false);
10029 vcpu_put(vcpu);
10030 return 0;
10031
10032 free_guest_fpu:
10033 kvm_free_guest_fpu(vcpu);
10034 free_user_fpu:
10035 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10036 free_emulate_ctxt:
10037 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10038 free_wbinvd_dirty_mask:
10039 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10040 fail_free_mce_banks:
10041 kfree(vcpu->arch.mce_banks);
10042 fail_free_pio_data:
10043 free_page((unsigned long)vcpu->arch.pio_data);
10044 fail_free_lapic:
10045 kvm_free_lapic(vcpu);
10046 fail_mmu_destroy:
10047 kvm_mmu_destroy(vcpu);
10048 return r;
10049 }
10050
10051 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
10052 {
10053 struct kvm *kvm = vcpu->kvm;
10054
10055 kvm_hv_vcpu_postcreate(vcpu);
10056
10057 if (mutex_lock_killable(&vcpu->mutex))
10058 return;
10059 vcpu_load(vcpu);
10060 kvm_synchronize_tsc(vcpu, 0);
10061 vcpu_put(vcpu);
10062
10063 /* poll control enabled by default */
10064 vcpu->arch.msr_kvm_poll_control = 1;
10065
10066 mutex_unlock(&vcpu->mutex);
10067
10068 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
10069 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
10070 KVMCLOCK_SYNC_PERIOD);
10071 }
10072
10073 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
10074 {
10075 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
10076 int idx;
10077
10078 kvm_release_pfn(cache->pfn, cache->dirty, cache);
10079
10080 kvmclock_reset(vcpu);
10081
10082 kvm_x86_ops.vcpu_free(vcpu);
10083
10084 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10085 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10086 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10087 kvm_free_guest_fpu(vcpu);
10088
10089 kvm_hv_vcpu_uninit(vcpu);
10090 kvm_pmu_destroy(vcpu);
10091 kfree(vcpu->arch.mce_banks);
10092 kvm_free_lapic(vcpu);
10093 idx = srcu_read_lock(&vcpu->kvm->srcu);
10094 kvm_mmu_destroy(vcpu);
10095 srcu_read_unlock(&vcpu->kvm->srcu, idx);
10096 free_page((unsigned long)vcpu->arch.pio_data);
10097 kvfree(vcpu->arch.cpuid_entries);
10098 if (!lapic_in_kernel(vcpu))
10099 static_key_slow_dec(&kvm_no_apic_vcpu);
10100 }
10101
10102 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
10103 {
10104 kvm_lapic_reset(vcpu, init_event);
10105
10106 vcpu->arch.hflags = 0;
10107
10108 vcpu->arch.smi_pending = 0;
10109 vcpu->arch.smi_count = 0;
10110 atomic_set(&vcpu->arch.nmi_queued, 0);
10111 vcpu->arch.nmi_pending = 0;
10112 vcpu->arch.nmi_injected = false;
10113 kvm_clear_interrupt_queue(vcpu);
10114 kvm_clear_exception_queue(vcpu);
10115
10116 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
10117 kvm_update_dr0123(vcpu);
10118 vcpu->arch.dr6 = DR6_INIT;
10119 vcpu->arch.dr7 = DR7_FIXED_1;
10120 kvm_update_dr7(vcpu);
10121
10122 vcpu->arch.cr2 = 0;
10123
10124 kvm_make_request(KVM_REQ_EVENT, vcpu);
10125 vcpu->arch.apf.msr_en_val = 0;
10126 vcpu->arch.apf.msr_int_val = 0;
10127 vcpu->arch.st.msr_val = 0;
10128
10129 kvmclock_reset(vcpu);
10130
10131 kvm_clear_async_pf_completion_queue(vcpu);
10132 kvm_async_pf_hash_reset(vcpu);
10133 vcpu->arch.apf.halted = false;
10134
10135 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) {
10136 void *mpx_state_buffer;
10137
10138 /*
10139 * To avoid have the INIT path from kvm_apic_has_events() that be
10140 * called with loaded FPU and does not let userspace fix the state.
10141 */
10142 if (init_event)
10143 kvm_put_guest_fpu(vcpu);
10144 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10145 XFEATURE_BNDREGS);
10146 if (mpx_state_buffer)
10147 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
10148 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10149 XFEATURE_BNDCSR);
10150 if (mpx_state_buffer)
10151 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
10152 if (init_event)
10153 kvm_load_guest_fpu(vcpu);
10154 }
10155
10156 if (!init_event) {
10157 kvm_pmu_reset(vcpu);
10158 vcpu->arch.smbase = 0x30000;
10159
10160 vcpu->arch.msr_misc_features_enables = 0;
10161
10162 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
10163 }
10164
10165 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
10166 vcpu->arch.regs_avail = ~0;
10167 vcpu->arch.regs_dirty = ~0;
10168
10169 vcpu->arch.ia32_xss = 0;
10170
10171 kvm_x86_ops.vcpu_reset(vcpu, init_event);
10172 }
10173
10174 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
10175 {
10176 struct kvm_segment cs;
10177
10178 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
10179 cs.selector = vector << 8;
10180 cs.base = vector << 12;
10181 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10182 kvm_rip_write(vcpu, 0);
10183 }
10184 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
10185
10186 int kvm_arch_hardware_enable(void)
10187 {
10188 struct kvm *kvm;
10189 struct kvm_vcpu *vcpu;
10190 int i;
10191 int ret;
10192 u64 local_tsc;
10193 u64 max_tsc = 0;
10194 bool stable, backwards_tsc = false;
10195
10196 kvm_user_return_msr_cpu_online();
10197 ret = kvm_x86_ops.hardware_enable();
10198 if (ret != 0)
10199 return ret;
10200
10201 local_tsc = rdtsc();
10202 stable = !kvm_check_tsc_unstable();
10203 list_for_each_entry(kvm, &vm_list, vm_list) {
10204 kvm_for_each_vcpu(i, vcpu, kvm) {
10205 if (!stable && vcpu->cpu == smp_processor_id())
10206 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10207 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10208 backwards_tsc = true;
10209 if (vcpu->arch.last_host_tsc > max_tsc)
10210 max_tsc = vcpu->arch.last_host_tsc;
10211 }
10212 }
10213 }
10214
10215 /*
10216 * Sometimes, even reliable TSCs go backwards. This happens on
10217 * platforms that reset TSC during suspend or hibernate actions, but
10218 * maintain synchronization. We must compensate. Fortunately, we can
10219 * detect that condition here, which happens early in CPU bringup,
10220 * before any KVM threads can be running. Unfortunately, we can't
10221 * bring the TSCs fully up to date with real time, as we aren't yet far
10222 * enough into CPU bringup that we know how much real time has actually
10223 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10224 * variables that haven't been updated yet.
10225 *
10226 * So we simply find the maximum observed TSC above, then record the
10227 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
10228 * the adjustment will be applied. Note that we accumulate
10229 * adjustments, in case multiple suspend cycles happen before some VCPU
10230 * gets a chance to run again. In the event that no KVM threads get a
10231 * chance to run, we will miss the entire elapsed period, as we'll have
10232 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10233 * loose cycle time. This isn't too big a deal, since the loss will be
10234 * uniform across all VCPUs (not to mention the scenario is extremely
10235 * unlikely). It is possible that a second hibernate recovery happens
10236 * much faster than a first, causing the observed TSC here to be
10237 * smaller; this would require additional padding adjustment, which is
10238 * why we set last_host_tsc to the local tsc observed here.
10239 *
10240 * N.B. - this code below runs only on platforms with reliable TSC,
10241 * as that is the only way backwards_tsc is set above. Also note
10242 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10243 * have the same delta_cyc adjustment applied if backwards_tsc
10244 * is detected. Note further, this adjustment is only done once,
10245 * as we reset last_host_tsc on all VCPUs to stop this from being
10246 * called multiple times (one for each physical CPU bringup).
10247 *
10248 * Platforms with unreliable TSCs don't have to deal with this, they
10249 * will be compensated by the logic in vcpu_load, which sets the TSC to
10250 * catchup mode. This will catchup all VCPUs to real time, but cannot
10251 * guarantee that they stay in perfect synchronization.
10252 */
10253 if (backwards_tsc) {
10254 u64 delta_cyc = max_tsc - local_tsc;
10255 list_for_each_entry(kvm, &vm_list, vm_list) {
10256 kvm->arch.backwards_tsc_observed = true;
10257 kvm_for_each_vcpu(i, vcpu, kvm) {
10258 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10259 vcpu->arch.last_host_tsc = local_tsc;
10260 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10261 }
10262
10263 /*
10264 * We have to disable TSC offset matching.. if you were
10265 * booting a VM while issuing an S4 host suspend....
10266 * you may have some problem. Solving this issue is
10267 * left as an exercise to the reader.
10268 */
10269 kvm->arch.last_tsc_nsec = 0;
10270 kvm->arch.last_tsc_write = 0;
10271 }
10272
10273 }
10274 return 0;
10275 }
10276
10277 void kvm_arch_hardware_disable(void)
10278 {
10279 kvm_x86_ops.hardware_disable();
10280 drop_user_return_notifiers();
10281 }
10282
10283 int kvm_arch_hardware_setup(void *opaque)
10284 {
10285 struct kvm_x86_init_ops *ops = opaque;
10286 int r;
10287
10288 rdmsrl_safe(MSR_EFER, &host_efer);
10289
10290 if (boot_cpu_has(X86_FEATURE_XSAVES))
10291 rdmsrl(MSR_IA32_XSS, host_xss);
10292
10293 r = ops->hardware_setup();
10294 if (r != 0)
10295 return r;
10296
10297 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10298
10299 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10300 supported_xss = 0;
10301
10302 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10303 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10304 #undef __kvm_cpu_cap_has
10305
10306 if (kvm_has_tsc_control) {
10307 /*
10308 * Make sure the user can only configure tsc_khz values that
10309 * fit into a signed integer.
10310 * A min value is not calculated because it will always
10311 * be 1 on all machines.
10312 */
10313 u64 max = min(0x7fffffffULL,
10314 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10315 kvm_max_guest_tsc_khz = max;
10316
10317 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10318 }
10319
10320 kvm_init_msr_list();
10321 return 0;
10322 }
10323
10324 void kvm_arch_hardware_unsetup(void)
10325 {
10326 kvm_x86_ops.hardware_unsetup();
10327 }
10328
10329 int kvm_arch_check_processor_compat(void *opaque)
10330 {
10331 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10332 struct kvm_x86_init_ops *ops = opaque;
10333
10334 WARN_ON(!irqs_disabled());
10335
10336 if (__cr4_reserved_bits(cpu_has, c) !=
10337 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10338 return -EIO;
10339
10340 return ops->check_processor_compatibility();
10341 }
10342
10343 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10344 {
10345 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10346 }
10347 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10348
10349 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10350 {
10351 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10352 }
10353
10354 struct static_key kvm_no_apic_vcpu __read_mostly;
10355 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
10356
10357 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10358 {
10359 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10360
10361 vcpu->arch.l1tf_flush_l1d = true;
10362 if (pmu->version && unlikely(pmu->event_count)) {
10363 pmu->need_cleanup = true;
10364 kvm_make_request(KVM_REQ_PMU, vcpu);
10365 }
10366 kvm_x86_ops.sched_in(vcpu, cpu);
10367 }
10368
10369 void kvm_arch_free_vm(struct kvm *kvm)
10370 {
10371 kfree(kvm->arch.hyperv.hv_pa_pg);
10372 vfree(kvm);
10373 }
10374
10375
10376 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10377 {
10378 if (type)
10379 return -EINVAL;
10380
10381 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10382 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10383 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10384 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10385 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10386 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10387
10388 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10389 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10390 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10391 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10392 &kvm->arch.irq_sources_bitmap);
10393
10394 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10395 mutex_init(&kvm->arch.apic_map_lock);
10396 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10397
10398 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10399 pvclock_update_vm_gtod_copy(kvm);
10400
10401 kvm->arch.guest_can_read_msr_platform_info = true;
10402
10403 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10404 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10405
10406 kvm_hv_init_vm(kvm);
10407 kvm_page_track_init(kvm);
10408 kvm_mmu_init_vm(kvm);
10409
10410 return kvm_x86_ops.vm_init(kvm);
10411 }
10412
10413 int kvm_arch_post_init_vm(struct kvm *kvm)
10414 {
10415 return kvm_mmu_post_init_vm(kvm);
10416 }
10417
10418 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10419 {
10420 vcpu_load(vcpu);
10421 kvm_mmu_unload(vcpu);
10422 vcpu_put(vcpu);
10423 }
10424
10425 static void kvm_free_vcpus(struct kvm *kvm)
10426 {
10427 unsigned int i;
10428 struct kvm_vcpu *vcpu;
10429
10430 /*
10431 * Unpin any mmu pages first.
10432 */
10433 kvm_for_each_vcpu(i, vcpu, kvm) {
10434 kvm_clear_async_pf_completion_queue(vcpu);
10435 kvm_unload_vcpu_mmu(vcpu);
10436 }
10437 kvm_for_each_vcpu(i, vcpu, kvm)
10438 kvm_vcpu_destroy(vcpu);
10439
10440 mutex_lock(&kvm->lock);
10441 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10442 kvm->vcpus[i] = NULL;
10443
10444 atomic_set(&kvm->online_vcpus, 0);
10445 mutex_unlock(&kvm->lock);
10446 }
10447
10448 void kvm_arch_sync_events(struct kvm *kvm)
10449 {
10450 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10451 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10452 kvm_free_pit(kvm);
10453 }
10454
10455 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
10456
10457 /**
10458 * __x86_set_memory_region: Setup KVM internal memory slot
10459 *
10460 * @kvm: the kvm pointer to the VM.
10461 * @id: the slot ID to setup.
10462 * @gpa: the GPA to install the slot (unused when @size == 0).
10463 * @size: the size of the slot. Set to zero to uninstall a slot.
10464 *
10465 * This function helps to setup a KVM internal memory slot. Specify
10466 * @size > 0 to install a new slot, while @size == 0 to uninstall a
10467 * slot. The return code can be one of the following:
10468 *
10469 * HVA: on success (uninstall will return a bogus HVA)
10470 * -errno: on error
10471 *
10472 * The caller should always use IS_ERR() to check the return value
10473 * before use. Note, the KVM internal memory slots are guaranteed to
10474 * remain valid and unchanged until the VM is destroyed, i.e., the
10475 * GPA->HVA translation will not change. However, the HVA is a user
10476 * address, i.e. its accessibility is not guaranteed, and must be
10477 * accessed via __copy_{to,from}_user().
10478 */
10479 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
10480 u32 size)
10481 {
10482 int i, r;
10483 unsigned long hva, old_npages;
10484 struct kvm_memslots *slots = kvm_memslots(kvm);
10485 struct kvm_memory_slot *slot;
10486
10487 /* Called with kvm->slots_lock held. */
10488 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10489 return ERR_PTR_USR(-EINVAL);
10490
10491 slot = id_to_memslot(slots, id);
10492 if (size) {
10493 if (slot && slot->npages)
10494 return ERR_PTR_USR(-EEXIST);
10495
10496 /*
10497 * MAP_SHARED to prevent internal slot pages from being moved
10498 * by fork()/COW.
10499 */
10500 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10501 MAP_SHARED | MAP_ANONYMOUS, 0);
10502 if (IS_ERR((void *)hva))
10503 return (void __user *)hva;
10504 } else {
10505 if (!slot || !slot->npages)
10506 return 0;
10507
10508 old_npages = slot->npages;
10509 hva = slot->userspace_addr;
10510 }
10511
10512 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10513 struct kvm_userspace_memory_region m;
10514
10515 m.slot = id | (i << 16);
10516 m.flags = 0;
10517 m.guest_phys_addr = gpa;
10518 m.userspace_addr = hva;
10519 m.memory_size = size;
10520 r = __kvm_set_memory_region(kvm, &m);
10521 if (r < 0)
10522 return ERR_PTR_USR(r);
10523 }
10524
10525 if (!size)
10526 vm_munmap(hva, old_npages * PAGE_SIZE);
10527
10528 return (void __user *)hva;
10529 }
10530 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10531
10532 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10533 {
10534 kvm_mmu_pre_destroy_vm(kvm);
10535 }
10536
10537 void kvm_arch_destroy_vm(struct kvm *kvm)
10538 {
10539 u32 i;
10540
10541 if (current->mm == kvm->mm) {
10542 /*
10543 * Free memory regions allocated on behalf of userspace,
10544 * unless the the memory map has changed due to process exit
10545 * or fd copying.
10546 */
10547 mutex_lock(&kvm->slots_lock);
10548 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10549 0, 0);
10550 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10551 0, 0);
10552 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10553 mutex_unlock(&kvm->slots_lock);
10554 }
10555 if (kvm_x86_ops.vm_destroy)
10556 kvm_x86_ops.vm_destroy(kvm);
10557 for (i = 0; i < kvm->arch.msr_filter.count; i++)
10558 kfree(kvm->arch.msr_filter.ranges[i].bitmap);
10559 kvm_pic_destroy(kvm);
10560 kvm_ioapic_destroy(kvm);
10561 kvm_free_vcpus(kvm);
10562 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10563 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10564 kvm_mmu_uninit_vm(kvm);
10565 kvm_page_track_cleanup(kvm);
10566 kvm_hv_destroy_vm(kvm);
10567 }
10568
10569 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10570 {
10571 int i;
10572
10573 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10574 kvfree(slot->arch.rmap[i]);
10575 slot->arch.rmap[i] = NULL;
10576
10577 if (i == 0)
10578 continue;
10579
10580 kvfree(slot->arch.lpage_info[i - 1]);
10581 slot->arch.lpage_info[i - 1] = NULL;
10582 }
10583
10584 kvm_page_track_free_memslot(slot);
10585 }
10586
10587 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10588 unsigned long npages)
10589 {
10590 int i;
10591
10592 /*
10593 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10594 * old arrays will be freed by __kvm_set_memory_region() if installing
10595 * the new memslot is successful.
10596 */
10597 memset(&slot->arch, 0, sizeof(slot->arch));
10598
10599 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10600 struct kvm_lpage_info *linfo;
10601 unsigned long ugfn;
10602 int lpages;
10603 int level = i + 1;
10604
10605 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10606 slot->base_gfn, level) + 1;
10607
10608 slot->arch.rmap[i] =
10609 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10610 GFP_KERNEL_ACCOUNT);
10611 if (!slot->arch.rmap[i])
10612 goto out_free;
10613 if (i == 0)
10614 continue;
10615
10616 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10617 if (!linfo)
10618 goto out_free;
10619
10620 slot->arch.lpage_info[i - 1] = linfo;
10621
10622 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10623 linfo[0].disallow_lpage = 1;
10624 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10625 linfo[lpages - 1].disallow_lpage = 1;
10626 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10627 /*
10628 * If the gfn and userspace address are not aligned wrt each
10629 * other, disable large page support for this slot.
10630 */
10631 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10632 unsigned long j;
10633
10634 for (j = 0; j < lpages; ++j)
10635 linfo[j].disallow_lpage = 1;
10636 }
10637 }
10638
10639 if (kvm_page_track_create_memslot(slot, npages))
10640 goto out_free;
10641
10642 return 0;
10643
10644 out_free:
10645 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10646 kvfree(slot->arch.rmap[i]);
10647 slot->arch.rmap[i] = NULL;
10648 if (i == 0)
10649 continue;
10650
10651 kvfree(slot->arch.lpage_info[i - 1]);
10652 slot->arch.lpage_info[i - 1] = NULL;
10653 }
10654 return -ENOMEM;
10655 }
10656
10657 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10658 {
10659 struct kvm_vcpu *vcpu;
10660 int i;
10661
10662 /*
10663 * memslots->generation has been incremented.
10664 * mmio generation may have reached its maximum value.
10665 */
10666 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10667
10668 /* Force re-initialization of steal_time cache */
10669 kvm_for_each_vcpu(i, vcpu, kvm)
10670 kvm_vcpu_kick(vcpu);
10671 }
10672
10673 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10674 struct kvm_memory_slot *memslot,
10675 const struct kvm_userspace_memory_region *mem,
10676 enum kvm_mr_change change)
10677 {
10678 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10679 return kvm_alloc_memslot_metadata(memslot,
10680 mem->memory_size >> PAGE_SHIFT);
10681 return 0;
10682 }
10683
10684 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10685 struct kvm_memory_slot *old,
10686 struct kvm_memory_slot *new,
10687 enum kvm_mr_change change)
10688 {
10689 /*
10690 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10691 * See comments below.
10692 */
10693 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10694 return;
10695
10696 /*
10697 * Dirty logging tracks sptes in 4k granularity, meaning that large
10698 * sptes have to be split. If live migration is successful, the guest
10699 * in the source machine will be destroyed and large sptes will be
10700 * created in the destination. However, if the guest continues to run
10701 * in the source machine (for example if live migration fails), small
10702 * sptes will remain around and cause bad performance.
10703 *
10704 * Scan sptes if dirty logging has been stopped, dropping those
10705 * which can be collapsed into a single large-page spte. Later
10706 * page faults will create the large-page sptes.
10707 *
10708 * There is no need to do this in any of the following cases:
10709 * CREATE: No dirty mappings will already exist.
10710 * MOVE/DELETE: The old mappings will already have been cleaned up by
10711 * kvm_arch_flush_shadow_memslot()
10712 */
10713 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10714 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10715 kvm_mmu_zap_collapsible_sptes(kvm, new);
10716
10717 /*
10718 * Enable or disable dirty logging for the slot.
10719 *
10720 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10721 * slot have been zapped so no dirty logging updates are needed for
10722 * the old slot.
10723 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10724 * any mappings that might be created in it will consume the
10725 * properties of the new slot and do not need to be updated here.
10726 *
10727 * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10728 * called to enable/disable dirty logging.
10729 *
10730 * When disabling dirty logging with PML enabled, the D-bit is set
10731 * for sptes in the slot in order to prevent unnecessary GPA
10732 * logging in the PML buffer (and potential PML buffer full VMEXIT).
10733 * This guarantees leaving PML enabled for the guest's lifetime
10734 * won't have any additional overhead from PML when the guest is
10735 * running with dirty logging disabled.
10736 *
10737 * When enabling dirty logging, large sptes are write-protected
10738 * so they can be split on first write. New large sptes cannot
10739 * be created for this slot until the end of the logging.
10740 * See the comments in fast_page_fault().
10741 * For small sptes, nothing is done if the dirty log is in the
10742 * initial-all-set state. Otherwise, depending on whether pml
10743 * is enabled the D-bit or the W-bit will be cleared.
10744 */
10745 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10746 if (kvm_x86_ops.slot_enable_log_dirty) {
10747 kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10748 } else {
10749 int level =
10750 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10751 PG_LEVEL_2M : PG_LEVEL_4K;
10752
10753 /*
10754 * If we're with initial-all-set, we don't need
10755 * to write protect any small page because
10756 * they're reported as dirty already. However
10757 * we still need to write-protect huge pages
10758 * so that the page split can happen lazily on
10759 * the first write to the huge page.
10760 */
10761 kvm_mmu_slot_remove_write_access(kvm, new, level);
10762 }
10763 } else {
10764 if (kvm_x86_ops.slot_disable_log_dirty)
10765 kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10766 }
10767 }
10768
10769 void kvm_arch_commit_memory_region(struct kvm *kvm,
10770 const struct kvm_userspace_memory_region *mem,
10771 struct kvm_memory_slot *old,
10772 const struct kvm_memory_slot *new,
10773 enum kvm_mr_change change)
10774 {
10775 if (!kvm->arch.n_requested_mmu_pages)
10776 kvm_mmu_change_mmu_pages(kvm,
10777 kvm_mmu_calculate_default_mmu_pages(kvm));
10778
10779 /*
10780 * FIXME: const-ify all uses of struct kvm_memory_slot.
10781 */
10782 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10783
10784 /* Free the arrays associated with the old memslot. */
10785 if (change == KVM_MR_MOVE)
10786 kvm_arch_free_memslot(kvm, old);
10787 }
10788
10789 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10790 {
10791 kvm_mmu_zap_all(kvm);
10792 }
10793
10794 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10795 struct kvm_memory_slot *slot)
10796 {
10797 kvm_page_track_flush_slot(kvm, slot);
10798 }
10799
10800 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10801 {
10802 return (is_guest_mode(vcpu) &&
10803 kvm_x86_ops.guest_apic_has_interrupt &&
10804 kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10805 }
10806
10807 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10808 {
10809 if (!list_empty_careful(&vcpu->async_pf.done))
10810 return true;
10811
10812 if (kvm_apic_has_events(vcpu))
10813 return true;
10814
10815 if (vcpu->arch.pv.pv_unhalted)
10816 return true;
10817
10818 if (vcpu->arch.exception.pending)
10819 return true;
10820
10821 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10822 (vcpu->arch.nmi_pending &&
10823 kvm_x86_ops.nmi_allowed(vcpu, false)))
10824 return true;
10825
10826 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10827 (vcpu->arch.smi_pending &&
10828 kvm_x86_ops.smi_allowed(vcpu, false)))
10829 return true;
10830
10831 if (kvm_arch_interrupt_allowed(vcpu) &&
10832 (kvm_cpu_has_interrupt(vcpu) ||
10833 kvm_guest_apic_has_interrupt(vcpu)))
10834 return true;
10835
10836 if (kvm_hv_has_stimer_pending(vcpu))
10837 return true;
10838
10839 if (is_guest_mode(vcpu) &&
10840 kvm_x86_ops.nested_ops->hv_timer_pending &&
10841 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10842 return true;
10843
10844 return false;
10845 }
10846
10847 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10848 {
10849 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10850 }
10851
10852 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10853 {
10854 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10855 return true;
10856
10857 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10858 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10859 kvm_test_request(KVM_REQ_EVENT, vcpu))
10860 return true;
10861
10862 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10863 return true;
10864
10865 return false;
10866 }
10867
10868 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10869 {
10870 return vcpu->arch.preempted_in_kernel;
10871 }
10872
10873 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10874 {
10875 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10876 }
10877
10878 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10879 {
10880 return kvm_x86_ops.interrupt_allowed(vcpu, false);
10881 }
10882
10883 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10884 {
10885 /* Can't read the RIP when guest state is protected, just return 0 */
10886 if (vcpu->arch.guest_state_protected)
10887 return 0;
10888
10889 if (is_64_bit_mode(vcpu))
10890 return kvm_rip_read(vcpu);
10891 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10892 kvm_rip_read(vcpu));
10893 }
10894 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10895
10896 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10897 {
10898 return kvm_get_linear_rip(vcpu) == linear_rip;
10899 }
10900 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10901
10902 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10903 {
10904 unsigned long rflags;
10905
10906 rflags = kvm_x86_ops.get_rflags(vcpu);
10907 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10908 rflags &= ~X86_EFLAGS_TF;
10909 return rflags;
10910 }
10911 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10912
10913 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10914 {
10915 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10916 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10917 rflags |= X86_EFLAGS_TF;
10918 kvm_x86_ops.set_rflags(vcpu, rflags);
10919 }
10920
10921 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10922 {
10923 __kvm_set_rflags(vcpu, rflags);
10924 kvm_make_request(KVM_REQ_EVENT, vcpu);
10925 }
10926 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10927
10928 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10929 {
10930 int r;
10931
10932 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10933 work->wakeup_all)
10934 return;
10935
10936 r = kvm_mmu_reload(vcpu);
10937 if (unlikely(r))
10938 return;
10939
10940 if (!vcpu->arch.mmu->direct_map &&
10941 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10942 return;
10943
10944 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10945 }
10946
10947 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10948 {
10949 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10950
10951 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10952 }
10953
10954 static inline u32 kvm_async_pf_next_probe(u32 key)
10955 {
10956 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10957 }
10958
10959 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10960 {
10961 u32 key = kvm_async_pf_hash_fn(gfn);
10962
10963 while (vcpu->arch.apf.gfns[key] != ~0)
10964 key = kvm_async_pf_next_probe(key);
10965
10966 vcpu->arch.apf.gfns[key] = gfn;
10967 }
10968
10969 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10970 {
10971 int i;
10972 u32 key = kvm_async_pf_hash_fn(gfn);
10973
10974 for (i = 0; i < ASYNC_PF_PER_VCPU &&
10975 (vcpu->arch.apf.gfns[key] != gfn &&
10976 vcpu->arch.apf.gfns[key] != ~0); i++)
10977 key = kvm_async_pf_next_probe(key);
10978
10979 return key;
10980 }
10981
10982 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10983 {
10984 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10985 }
10986
10987 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10988 {
10989 u32 i, j, k;
10990
10991 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10992
10993 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10994 return;
10995
10996 while (true) {
10997 vcpu->arch.apf.gfns[i] = ~0;
10998 do {
10999 j = kvm_async_pf_next_probe(j);
11000 if (vcpu->arch.apf.gfns[j] == ~0)
11001 return;
11002 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
11003 /*
11004 * k lies cyclically in ]i,j]
11005 * | i.k.j |
11006 * |....j i.k.| or |.k..j i...|
11007 */
11008 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
11009 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
11010 i = j;
11011 }
11012 }
11013
11014 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
11015 {
11016 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
11017
11018 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
11019 sizeof(reason));
11020 }
11021
11022 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
11023 {
11024 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11025
11026 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11027 &token, offset, sizeof(token));
11028 }
11029
11030 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
11031 {
11032 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11033 u32 val;
11034
11035 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11036 &val, offset, sizeof(val)))
11037 return false;
11038
11039 return !val;
11040 }
11041
11042 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
11043 {
11044 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
11045 return false;
11046
11047 if (!kvm_pv_async_pf_enabled(vcpu) ||
11048 (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
11049 return false;
11050
11051 return true;
11052 }
11053
11054 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
11055 {
11056 if (unlikely(!lapic_in_kernel(vcpu) ||
11057 kvm_event_needs_reinjection(vcpu) ||
11058 vcpu->arch.exception.pending))
11059 return false;
11060
11061 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
11062 return false;
11063
11064 /*
11065 * If interrupts are off we cannot even use an artificial
11066 * halt state.
11067 */
11068 return kvm_arch_interrupt_allowed(vcpu);
11069 }
11070
11071 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
11072 struct kvm_async_pf *work)
11073 {
11074 struct x86_exception fault;
11075
11076 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
11077 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
11078
11079 if (kvm_can_deliver_async_pf(vcpu) &&
11080 !apf_put_user_notpresent(vcpu)) {
11081 fault.vector = PF_VECTOR;
11082 fault.error_code_valid = true;
11083 fault.error_code = 0;
11084 fault.nested_page_fault = false;
11085 fault.address = work->arch.token;
11086 fault.async_page_fault = true;
11087 kvm_inject_page_fault(vcpu, &fault);
11088 return true;
11089 } else {
11090 /*
11091 * It is not possible to deliver a paravirtualized asynchronous
11092 * page fault, but putting the guest in an artificial halt state
11093 * can be beneficial nevertheless: if an interrupt arrives, we
11094 * can deliver it timely and perhaps the guest will schedule
11095 * another process. When the instruction that triggered a page
11096 * fault is retried, hopefully the page will be ready in the host.
11097 */
11098 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
11099 return false;
11100 }
11101 }
11102
11103 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
11104 struct kvm_async_pf *work)
11105 {
11106 struct kvm_lapic_irq irq = {
11107 .delivery_mode = APIC_DM_FIXED,
11108 .vector = vcpu->arch.apf.vec
11109 };
11110
11111 if (work->wakeup_all)
11112 work->arch.token = ~0; /* broadcast wakeup */
11113 else
11114 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
11115 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
11116
11117 if ((work->wakeup_all || work->notpresent_injected) &&
11118 kvm_pv_async_pf_enabled(vcpu) &&
11119 !apf_put_user_ready(vcpu, work->arch.token)) {
11120 vcpu->arch.apf.pageready_pending = true;
11121 kvm_apic_set_irq(vcpu, &irq, NULL);
11122 }
11123
11124 vcpu->arch.apf.halted = false;
11125 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11126 }
11127
11128 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
11129 {
11130 kvm_make_request(KVM_REQ_APF_READY, vcpu);
11131 if (!vcpu->arch.apf.pageready_pending)
11132 kvm_vcpu_kick(vcpu);
11133 }
11134
11135 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
11136 {
11137 if (!kvm_pv_async_pf_enabled(vcpu))
11138 return true;
11139 else
11140 return apf_pageready_slot_free(vcpu);
11141 }
11142
11143 void kvm_arch_start_assignment(struct kvm *kvm)
11144 {
11145 atomic_inc(&kvm->arch.assigned_device_count);
11146 }
11147 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
11148
11149 void kvm_arch_end_assignment(struct kvm *kvm)
11150 {
11151 atomic_dec(&kvm->arch.assigned_device_count);
11152 }
11153 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
11154
11155 bool kvm_arch_has_assigned_device(struct kvm *kvm)
11156 {
11157 return atomic_read(&kvm->arch.assigned_device_count);
11158 }
11159 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
11160
11161 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
11162 {
11163 atomic_inc(&kvm->arch.noncoherent_dma_count);
11164 }
11165 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
11166
11167 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
11168 {
11169 atomic_dec(&kvm->arch.noncoherent_dma_count);
11170 }
11171 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
11172
11173 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
11174 {
11175 return atomic_read(&kvm->arch.noncoherent_dma_count);
11176 }
11177 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
11178
11179 bool kvm_arch_has_irq_bypass(void)
11180 {
11181 return true;
11182 }
11183
11184 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
11185 struct irq_bypass_producer *prod)
11186 {
11187 struct kvm_kernel_irqfd *irqfd =
11188 container_of(cons, struct kvm_kernel_irqfd, consumer);
11189 int ret;
11190
11191 irqfd->producer = prod;
11192 kvm_arch_start_assignment(irqfd->kvm);
11193 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
11194 prod->irq, irqfd->gsi, 1);
11195
11196 if (ret)
11197 kvm_arch_end_assignment(irqfd->kvm);
11198
11199 return ret;
11200 }
11201
11202 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
11203 struct irq_bypass_producer *prod)
11204 {
11205 int ret;
11206 struct kvm_kernel_irqfd *irqfd =
11207 container_of(cons, struct kvm_kernel_irqfd, consumer);
11208
11209 WARN_ON(irqfd->producer != prod);
11210 irqfd->producer = NULL;
11211
11212 /*
11213 * When producer of consumer is unregistered, we change back to
11214 * remapped mode, so we can re-use the current implementation
11215 * when the irq is masked/disabled or the consumer side (KVM
11216 * int this case doesn't want to receive the interrupts.
11217 */
11218 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
11219 if (ret)
11220 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
11221 " fails: %d\n", irqfd->consumer.token, ret);
11222
11223 kvm_arch_end_assignment(irqfd->kvm);
11224 }
11225
11226 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
11227 uint32_t guest_irq, bool set)
11228 {
11229 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
11230 }
11231
11232 bool kvm_vector_hashing_enabled(void)
11233 {
11234 return vector_hashing;
11235 }
11236
11237 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11238 {
11239 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11240 }
11241 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11242
11243
11244 int kvm_spec_ctrl_test_value(u64 value)
11245 {
11246 /*
11247 * test that setting IA32_SPEC_CTRL to given value
11248 * is allowed by the host processor
11249 */
11250
11251 u64 saved_value;
11252 unsigned long flags;
11253 int ret = 0;
11254
11255 local_irq_save(flags);
11256
11257 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11258 ret = 1;
11259 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11260 ret = 1;
11261 else
11262 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11263
11264 local_irq_restore(flags);
11265
11266 return ret;
11267 }
11268 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11269
11270 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11271 {
11272 struct x86_exception fault;
11273 u32 access = error_code &
11274 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11275
11276 if (!(error_code & PFERR_PRESENT_MASK) ||
11277 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11278 /*
11279 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11280 * tables probably do not match the TLB. Just proceed
11281 * with the error code that the processor gave.
11282 */
11283 fault.vector = PF_VECTOR;
11284 fault.error_code_valid = true;
11285 fault.error_code = error_code;
11286 fault.nested_page_fault = false;
11287 fault.address = gva;
11288 }
11289 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11290 }
11291 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11292
11293 /*
11294 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11295 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11296 * indicates whether exit to userspace is needed.
11297 */
11298 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11299 struct x86_exception *e)
11300 {
11301 if (r == X86EMUL_PROPAGATE_FAULT) {
11302 kvm_inject_emulated_page_fault(vcpu, e);
11303 return 1;
11304 }
11305
11306 /*
11307 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11308 * while handling a VMX instruction KVM could've handled the request
11309 * correctly by exiting to userspace and performing I/O but there
11310 * doesn't seem to be a real use-case behind such requests, just return
11311 * KVM_EXIT_INTERNAL_ERROR for now.
11312 */
11313 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11314 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11315 vcpu->run->internal.ndata = 0;
11316
11317 return 0;
11318 }
11319 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11320
11321 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11322 {
11323 bool pcid_enabled;
11324 struct x86_exception e;
11325 unsigned i;
11326 unsigned long roots_to_free = 0;
11327 struct {
11328 u64 pcid;
11329 u64 gla;
11330 } operand;
11331 int r;
11332
11333 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11334 if (r != X86EMUL_CONTINUE)
11335 return kvm_handle_memory_failure(vcpu, r, &e);
11336
11337 if (operand.pcid >> 12 != 0) {
11338 kvm_inject_gp(vcpu, 0);
11339 return 1;
11340 }
11341
11342 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11343
11344 switch (type) {
11345 case INVPCID_TYPE_INDIV_ADDR:
11346 if ((!pcid_enabled && (operand.pcid != 0)) ||
11347 is_noncanonical_address(operand.gla, vcpu)) {
11348 kvm_inject_gp(vcpu, 0);
11349 return 1;
11350 }
11351 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11352 return kvm_skip_emulated_instruction(vcpu);
11353
11354 case INVPCID_TYPE_SINGLE_CTXT:
11355 if (!pcid_enabled && (operand.pcid != 0)) {
11356 kvm_inject_gp(vcpu, 0);
11357 return 1;
11358 }
11359
11360 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11361 kvm_mmu_sync_roots(vcpu);
11362 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11363 }
11364
11365 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11366 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11367 == operand.pcid)
11368 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11369
11370 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11371 /*
11372 * If neither the current cr3 nor any of the prev_roots use the
11373 * given PCID, then nothing needs to be done here because a
11374 * resync will happen anyway before switching to any other CR3.
11375 */
11376
11377 return kvm_skip_emulated_instruction(vcpu);
11378
11379 case INVPCID_TYPE_ALL_NON_GLOBAL:
11380 /*
11381 * Currently, KVM doesn't mark global entries in the shadow
11382 * page tables, so a non-global flush just degenerates to a
11383 * global flush. If needed, we could optimize this later by
11384 * keeping track of global entries in shadow page tables.
11385 */
11386
11387 fallthrough;
11388 case INVPCID_TYPE_ALL_INCL_GLOBAL:
11389 kvm_mmu_unload(vcpu);
11390 return kvm_skip_emulated_instruction(vcpu);
11391
11392 default:
11393 BUG(); /* We have already checked above that type <= 3 */
11394 }
11395 }
11396 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11397
11398 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
11399 {
11400 struct kvm_run *run = vcpu->run;
11401 struct kvm_mmio_fragment *frag;
11402 unsigned int len;
11403
11404 BUG_ON(!vcpu->mmio_needed);
11405
11406 /* Complete previous fragment */
11407 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11408 len = min(8u, frag->len);
11409 if (!vcpu->mmio_is_write)
11410 memcpy(frag->data, run->mmio.data, len);
11411
11412 if (frag->len <= 8) {
11413 /* Switch to the next fragment. */
11414 frag++;
11415 vcpu->mmio_cur_fragment++;
11416 } else {
11417 /* Go forward to the next mmio piece. */
11418 frag->data += len;
11419 frag->gpa += len;
11420 frag->len -= len;
11421 }
11422
11423 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11424 vcpu->mmio_needed = 0;
11425
11426 // VMG change, at this point, we're always done
11427 // RIP has already been advanced
11428 return 1;
11429 }
11430
11431 // More MMIO is needed
11432 run->mmio.phys_addr = frag->gpa;
11433 run->mmio.len = min(8u, frag->len);
11434 run->mmio.is_write = vcpu->mmio_is_write;
11435 if (run->mmio.is_write)
11436 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11437 run->exit_reason = KVM_EXIT_MMIO;
11438
11439 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11440
11441 return 0;
11442 }
11443
11444 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11445 void *data)
11446 {
11447 int handled;
11448 struct kvm_mmio_fragment *frag;
11449
11450 if (!data)
11451 return -EINVAL;
11452
11453 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11454 if (handled == bytes)
11455 return 1;
11456
11457 bytes -= handled;
11458 gpa += handled;
11459 data += handled;
11460
11461 /*TODO: Check if need to increment number of frags */
11462 frag = vcpu->mmio_fragments;
11463 vcpu->mmio_nr_fragments = 1;
11464 frag->len = bytes;
11465 frag->gpa = gpa;
11466 frag->data = data;
11467
11468 vcpu->mmio_needed = 1;
11469 vcpu->mmio_cur_fragment = 0;
11470
11471 vcpu->run->mmio.phys_addr = gpa;
11472 vcpu->run->mmio.len = min(8u, frag->len);
11473 vcpu->run->mmio.is_write = 1;
11474 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
11475 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11476
11477 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11478
11479 return 0;
11480 }
11481 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
11482
11483 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11484 void *data)
11485 {
11486 int handled;
11487 struct kvm_mmio_fragment *frag;
11488
11489 if (!data)
11490 return -EINVAL;
11491
11492 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11493 if (handled == bytes)
11494 return 1;
11495
11496 bytes -= handled;
11497 gpa += handled;
11498 data += handled;
11499
11500 /*TODO: Check if need to increment number of frags */
11501 frag = vcpu->mmio_fragments;
11502 vcpu->mmio_nr_fragments = 1;
11503 frag->len = bytes;
11504 frag->gpa = gpa;
11505 frag->data = data;
11506
11507 vcpu->mmio_needed = 1;
11508 vcpu->mmio_cur_fragment = 0;
11509
11510 vcpu->run->mmio.phys_addr = gpa;
11511 vcpu->run->mmio.len = min(8u, frag->len);
11512 vcpu->run->mmio.is_write = 0;
11513 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11514
11515 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11516
11517 return 0;
11518 }
11519 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
11520
11521 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
11522 {
11523 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data,
11524 vcpu->arch.pio.count * vcpu->arch.pio.size);
11525 vcpu->arch.pio.count = 0;
11526
11527 return 1;
11528 }
11529
11530 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
11531 unsigned int port, void *data, unsigned int count)
11532 {
11533 int ret;
11534
11535 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port,
11536 data, count);
11537 if (ret)
11538 return ret;
11539
11540 vcpu->arch.pio.count = 0;
11541
11542 return 0;
11543 }
11544
11545 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
11546 unsigned int port, void *data, unsigned int count)
11547 {
11548 int ret;
11549
11550 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port,
11551 data, count);
11552 if (ret) {
11553 vcpu->arch.pio.count = 0;
11554 } else {
11555 vcpu->arch.guest_ins_data = data;
11556 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
11557 }
11558
11559 return 0;
11560 }
11561
11562 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
11563 unsigned int port, void *data, unsigned int count,
11564 int in)
11565 {
11566 return in ? kvm_sev_es_ins(vcpu, size, port, data, count)
11567 : kvm_sev_es_outs(vcpu, size, port, data, count);
11568 }
11569 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
11570
11571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
11572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11579 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11580 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11581 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11582 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11583 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11585 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11586 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11587 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11588 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11589 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11590 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11591 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11592 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11593 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
11594 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
11595 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
11596 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
11597 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
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