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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
109 #define KVM_NR_SHARED_MSRS 16
110
111 struct kvm_shared_msrs_global {
112 int nr;
113 u32 msrs[KVM_NR_SHARED_MSRS];
114 };
115
116 struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
123 };
124
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
127
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141 { "hypercalls", VCPU_STAT(hypercalls) },
142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149 { "irq_injections", VCPU_STAT(irq_injections) },
150 { "nmi_injections", VCPU_STAT(nmi_injections) },
151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158 { "mmu_unsync", VM_STAT(mmu_unsync) },
159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160 { "largepages", VM_STAT(lpages) },
161 { NULL }
162 };
163
164 u64 __read_mostly host_xcr0;
165
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
167
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169 {
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173 }
174
175 static void kvm_on_user_return(struct user_return_notifier *urn)
176 {
177 unsigned slot;
178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
180 struct kvm_shared_msr_values *values;
181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191 }
192
193 static void shared_msr_update(unsigned slot, u32 msr)
194 {
195 u64 value;
196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
198
199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208 }
209
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
211 {
212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
217 }
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220 static void kvm_shared_msr_cpu_online(void)
221 {
222 unsigned i;
223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
225 shared_msr_update(i, shared_msrs_global.msrs[i]);
226 }
227
228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
229 {
230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
232
233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
234 return;
235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242 }
243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
245 static void drop_user_return_notifiers(void *ignore)
246 {
247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252 }
253
254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255 {
256 return vcpu->arch.apic_base;
257 }
258 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
260 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261 {
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
280 }
281 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
283 asmlinkage void kvm_spurious_fault(void)
284 {
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287 }
288 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
290 #define EXCPT_BENIGN 0
291 #define EXCPT_CONTRIBUTORY 1
292 #define EXCPT_PF 2
293
294 static int exception_class(int vector)
295 {
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309 }
310
311 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
314 {
315 u32 prev_nr;
316 int class1, class2;
317
318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
326 vcpu->arch.exception.reinject = reinject;
327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351 }
352
353 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354 {
355 kvm_multiple_exception(vcpu, nr, false, 0, false);
356 }
357 EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
359 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360 {
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362 }
363 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
365 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
366 {
367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371 }
372 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
373
374 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
375 {
376 ++vcpu->stat.pf_guest;
377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
379 }
380 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
381
382 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
383 {
384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
386 else
387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
388 }
389
390 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391 {
392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
394 }
395 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
397 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398 {
399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
400 }
401 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
403 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404 {
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406 }
407 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
409 /*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
414 {
415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
419 }
420 EXPORT_SYMBOL_GPL(kvm_require_cpl);
421
422 /*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430 {
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442 }
443 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
445 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447 {
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450 }
451
452 /*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
455 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
456 {
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
462
463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
471 if (is_present_gpte(pdpte[i]) &&
472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
484 out:
485
486 return ret;
487 }
488 EXPORT_SYMBOL_GPL(load_pdptrs);
489
490 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491 {
492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
493 bool changed = true;
494 int offset;
495 gfn_t gfn;
496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
509 if (r < 0)
510 goto out;
511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
512 out:
513
514 return changed;
515 }
516
517 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
518 {
519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
523 cr0 |= X86_CR0_ET;
524
525 #ifdef CONFIG_X86_64
526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
528 #endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
531
532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
534
535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539 #ifdef CONFIG_X86_64
540 if ((vcpu->arch.efer & EFER_LME)) {
541 int cs_db, cs_l;
542
543 if (!is_pae(vcpu))
544 return 1;
545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
546 if (cs_l)
547 return 1;
548 } else
549 #endif
550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
551 kvm_read_cr3(vcpu)))
552 return 1;
553 }
554
555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
558 kvm_x86_ops->set_cr0(vcpu, cr0);
559
560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
561 kvm_clear_async_pf_completion_queue(vcpu);
562 kvm_async_pf_hash_reset(vcpu);
563 }
564
565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
567 return 0;
568 }
569 EXPORT_SYMBOL_GPL(kvm_set_cr0);
570
571 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
572 {
573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
574 }
575 EXPORT_SYMBOL_GPL(kvm_lmsw);
576
577 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578 {
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585 }
586
587 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588 {
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594 }
595
596 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597 {
598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
600 u64 valid_bits;
601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
617 return 1;
618
619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620 return 1;
621
622 kvm_put_guest_xcr0(vcpu);
623 vcpu->arch.xcr0 = xcr0;
624
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
627 return 0;
628 }
629
630 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631 {
632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
634 kvm_inject_gp(vcpu, 0);
635 return 1;
636 }
637 return 0;
638 }
639 EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
641 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
642 {
643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
646 if (cr4 & CR4_RESERVED_BITS)
647 return 1;
648
649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650 return 1;
651
652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653 return 1;
654
655 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
656 return 1;
657
658 if (is_long_mode(vcpu)) {
659 if (!(cr4 & X86_CR4_PAE))
660 return 1;
661 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
662 && ((cr4 ^ old_cr4) & pdptr_bits)
663 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
664 kvm_read_cr3(vcpu)))
665 return 1;
666
667 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
668 if (!guest_cpuid_has_pcid(vcpu))
669 return 1;
670
671 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
672 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
673 return 1;
674 }
675
676 if (kvm_x86_ops->set_cr4(vcpu, cr4))
677 return 1;
678
679 if (((cr4 ^ old_cr4) & pdptr_bits) ||
680 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
681 kvm_mmu_reset_context(vcpu);
682
683 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
684 kvm_update_cpuid(vcpu);
685
686 return 0;
687 }
688 EXPORT_SYMBOL_GPL(kvm_set_cr4);
689
690 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
691 {
692 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
693 kvm_mmu_sync_roots(vcpu);
694 kvm_mmu_flush_tlb(vcpu);
695 return 0;
696 }
697
698 if (is_long_mode(vcpu)) {
699 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
700 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
701 return 1;
702 } else
703 if (cr3 & CR3_L_MODE_RESERVED_BITS)
704 return 1;
705 } else {
706 if (is_pae(vcpu)) {
707 if (cr3 & CR3_PAE_RESERVED_BITS)
708 return 1;
709 if (is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
711 return 1;
712 }
713 /*
714 * We don't check reserved bits in nonpae mode, because
715 * this isn't enforced, and VMware depends on this.
716 */
717 }
718
719 vcpu->arch.cr3 = cr3;
720 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
721 kvm_mmu_new_cr3(vcpu);
722 return 0;
723 }
724 EXPORT_SYMBOL_GPL(kvm_set_cr3);
725
726 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
727 {
728 if (cr8 & CR8_RESERVED_BITS)
729 return 1;
730 if (irqchip_in_kernel(vcpu->kvm))
731 kvm_lapic_set_tpr(vcpu, cr8);
732 else
733 vcpu->arch.cr8 = cr8;
734 return 0;
735 }
736 EXPORT_SYMBOL_GPL(kvm_set_cr8);
737
738 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
739 {
740 if (irqchip_in_kernel(vcpu->kvm))
741 return kvm_lapic_get_cr8(vcpu);
742 else
743 return vcpu->arch.cr8;
744 }
745 EXPORT_SYMBOL_GPL(kvm_get_cr8);
746
747 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
748 {
749 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
750 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
751 }
752
753 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
754 {
755 unsigned long dr7;
756
757 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
758 dr7 = vcpu->arch.guest_debug_dr7;
759 else
760 dr7 = vcpu->arch.dr7;
761 kvm_x86_ops->set_dr7(vcpu, dr7);
762 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
763 if (dr7 & DR7_BP_EN_MASK)
764 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
765 }
766
767 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
768 {
769 switch (dr) {
770 case 0 ... 3:
771 vcpu->arch.db[dr] = val;
772 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
773 vcpu->arch.eff_db[dr] = val;
774 break;
775 case 4:
776 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
777 return 1; /* #UD */
778 /* fall through */
779 case 6:
780 if (val & 0xffffffff00000000ULL)
781 return -1; /* #GP */
782 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
783 kvm_update_dr6(vcpu);
784 break;
785 case 5:
786 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
787 return 1; /* #UD */
788 /* fall through */
789 default: /* 7 */
790 if (val & 0xffffffff00000000ULL)
791 return -1; /* #GP */
792 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
793 kvm_update_dr7(vcpu);
794 break;
795 }
796
797 return 0;
798 }
799
800 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
801 {
802 int res;
803
804 res = __kvm_set_dr(vcpu, dr, val);
805 if (res > 0)
806 kvm_queue_exception(vcpu, UD_VECTOR);
807 else if (res < 0)
808 kvm_inject_gp(vcpu, 0);
809
810 return res;
811 }
812 EXPORT_SYMBOL_GPL(kvm_set_dr);
813
814 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
815 {
816 switch (dr) {
817 case 0 ... 3:
818 *val = vcpu->arch.db[dr];
819 break;
820 case 4:
821 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
822 return 1;
823 /* fall through */
824 case 6:
825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826 *val = vcpu->arch.dr6;
827 else
828 *val = kvm_x86_ops->get_dr6(vcpu);
829 break;
830 case 5:
831 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
832 return 1;
833 /* fall through */
834 default: /* 7 */
835 *val = vcpu->arch.dr7;
836 break;
837 }
838
839 return 0;
840 }
841
842 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
843 {
844 if (_kvm_get_dr(vcpu, dr, val)) {
845 kvm_queue_exception(vcpu, UD_VECTOR);
846 return 1;
847 }
848 return 0;
849 }
850 EXPORT_SYMBOL_GPL(kvm_get_dr);
851
852 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
853 {
854 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
855 u64 data;
856 int err;
857
858 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
859 if (err)
860 return err;
861 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
862 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
863 return err;
864 }
865 EXPORT_SYMBOL_GPL(kvm_rdpmc);
866
867 /*
868 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
869 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
870 *
871 * This list is modified at module load time to reflect the
872 * capabilities of the host cpu. This capabilities test skips MSRs that are
873 * kvm-specific. Those are put in the beginning of the list.
874 */
875
876 #define KVM_SAVE_MSRS_BEGIN 12
877 static u32 msrs_to_save[] = {
878 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
879 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
880 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
881 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
882 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
883 MSR_KVM_PV_EOI_EN,
884 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
885 MSR_STAR,
886 #ifdef CONFIG_X86_64
887 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
888 #endif
889 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
890 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
891 };
892
893 static unsigned num_msrs_to_save;
894
895 static const u32 emulated_msrs[] = {
896 MSR_IA32_TSC_ADJUST,
897 MSR_IA32_TSCDEADLINE,
898 MSR_IA32_MISC_ENABLE,
899 MSR_IA32_MCG_STATUS,
900 MSR_IA32_MCG_CTL,
901 };
902
903 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
904 {
905 if (efer & efer_reserved_bits)
906 return false;
907
908 if (efer & EFER_FFXSR) {
909 struct kvm_cpuid_entry2 *feat;
910
911 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
912 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
913 return false;
914 }
915
916 if (efer & EFER_SVME) {
917 struct kvm_cpuid_entry2 *feat;
918
919 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
920 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
921 return false;
922 }
923
924 return true;
925 }
926 EXPORT_SYMBOL_GPL(kvm_valid_efer);
927
928 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
929 {
930 u64 old_efer = vcpu->arch.efer;
931
932 if (!kvm_valid_efer(vcpu, efer))
933 return 1;
934
935 if (is_paging(vcpu)
936 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
937 return 1;
938
939 efer &= ~EFER_LMA;
940 efer |= vcpu->arch.efer & EFER_LMA;
941
942 kvm_x86_ops->set_efer(vcpu, efer);
943
944 /* Update reserved bits */
945 if ((efer ^ old_efer) & EFER_NX)
946 kvm_mmu_reset_context(vcpu);
947
948 return 0;
949 }
950
951 void kvm_enable_efer_bits(u64 mask)
952 {
953 efer_reserved_bits &= ~mask;
954 }
955 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
956
957
958 /*
959 * Writes msr value into into the appropriate "register".
960 * Returns 0 on success, non-0 otherwise.
961 * Assumes vcpu_load() was already called.
962 */
963 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
964 {
965 return kvm_x86_ops->set_msr(vcpu, msr);
966 }
967
968 /*
969 * Adapt set_msr() to msr_io()'s calling convention
970 */
971 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
972 {
973 struct msr_data msr;
974
975 msr.data = *data;
976 msr.index = index;
977 msr.host_initiated = true;
978 return kvm_set_msr(vcpu, &msr);
979 }
980
981 #ifdef CONFIG_X86_64
982 struct pvclock_gtod_data {
983 seqcount_t seq;
984
985 struct { /* extract of a clocksource struct */
986 int vclock_mode;
987 cycle_t cycle_last;
988 cycle_t mask;
989 u32 mult;
990 u32 shift;
991 } clock;
992
993 /* open coded 'struct timespec' */
994 u64 monotonic_time_snsec;
995 time_t monotonic_time_sec;
996 };
997
998 static struct pvclock_gtod_data pvclock_gtod_data;
999
1000 static void update_pvclock_gtod(struct timekeeper *tk)
1001 {
1002 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1003
1004 write_seqcount_begin(&vdata->seq);
1005
1006 /* copy pvclock gtod data */
1007 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1008 vdata->clock.cycle_last = tk->clock->cycle_last;
1009 vdata->clock.mask = tk->clock->mask;
1010 vdata->clock.mult = tk->mult;
1011 vdata->clock.shift = tk->shift;
1012
1013 vdata->monotonic_time_sec = tk->xtime_sec
1014 + tk->wall_to_monotonic.tv_sec;
1015 vdata->monotonic_time_snsec = tk->xtime_nsec
1016 + (tk->wall_to_monotonic.tv_nsec
1017 << tk->shift);
1018 while (vdata->monotonic_time_snsec >=
1019 (((u64)NSEC_PER_SEC) << tk->shift)) {
1020 vdata->monotonic_time_snsec -=
1021 ((u64)NSEC_PER_SEC) << tk->shift;
1022 vdata->monotonic_time_sec++;
1023 }
1024
1025 write_seqcount_end(&vdata->seq);
1026 }
1027 #endif
1028
1029
1030 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1031 {
1032 int version;
1033 int r;
1034 struct pvclock_wall_clock wc;
1035 struct timespec boot;
1036
1037 if (!wall_clock)
1038 return;
1039
1040 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1041 if (r)
1042 return;
1043
1044 if (version & 1)
1045 ++version; /* first time write, random junk */
1046
1047 ++version;
1048
1049 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1050
1051 /*
1052 * The guest calculates current wall clock time by adding
1053 * system time (updated by kvm_guest_time_update below) to the
1054 * wall clock specified here. guest system time equals host
1055 * system time for us, thus we must fill in host boot time here.
1056 */
1057 getboottime(&boot);
1058
1059 if (kvm->arch.kvmclock_offset) {
1060 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1061 boot = timespec_sub(boot, ts);
1062 }
1063 wc.sec = boot.tv_sec;
1064 wc.nsec = boot.tv_nsec;
1065 wc.version = version;
1066
1067 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1068
1069 version++;
1070 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1071 }
1072
1073 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1074 {
1075 uint32_t quotient, remainder;
1076
1077 /* Don't try to replace with do_div(), this one calculates
1078 * "(dividend << 32) / divisor" */
1079 __asm__ ( "divl %4"
1080 : "=a" (quotient), "=d" (remainder)
1081 : "0" (0), "1" (dividend), "r" (divisor) );
1082 return quotient;
1083 }
1084
1085 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1086 s8 *pshift, u32 *pmultiplier)
1087 {
1088 uint64_t scaled64;
1089 int32_t shift = 0;
1090 uint64_t tps64;
1091 uint32_t tps32;
1092
1093 tps64 = base_khz * 1000LL;
1094 scaled64 = scaled_khz * 1000LL;
1095 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1096 tps64 >>= 1;
1097 shift--;
1098 }
1099
1100 tps32 = (uint32_t)tps64;
1101 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1102 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1103 scaled64 >>= 1;
1104 else
1105 tps32 <<= 1;
1106 shift++;
1107 }
1108
1109 *pshift = shift;
1110 *pmultiplier = div_frac(scaled64, tps32);
1111
1112 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1113 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1114 }
1115
1116 static inline u64 get_kernel_ns(void)
1117 {
1118 struct timespec ts;
1119
1120 WARN_ON(preemptible());
1121 ktime_get_ts(&ts);
1122 monotonic_to_bootbased(&ts);
1123 return timespec_to_ns(&ts);
1124 }
1125
1126 #ifdef CONFIG_X86_64
1127 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1128 #endif
1129
1130 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1131 unsigned long max_tsc_khz;
1132
1133 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1134 {
1135 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1136 vcpu->arch.virtual_tsc_shift);
1137 }
1138
1139 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1140 {
1141 u64 v = (u64)khz * (1000000 + ppm);
1142 do_div(v, 1000000);
1143 return v;
1144 }
1145
1146 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1147 {
1148 u32 thresh_lo, thresh_hi;
1149 int use_scaling = 0;
1150
1151 /* tsc_khz can be zero if TSC calibration fails */
1152 if (this_tsc_khz == 0)
1153 return;
1154
1155 /* Compute a scale to convert nanoseconds in TSC cycles */
1156 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1157 &vcpu->arch.virtual_tsc_shift,
1158 &vcpu->arch.virtual_tsc_mult);
1159 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1160
1161 /*
1162 * Compute the variation in TSC rate which is acceptable
1163 * within the range of tolerance and decide if the
1164 * rate being applied is within that bounds of the hardware
1165 * rate. If so, no scaling or compensation need be done.
1166 */
1167 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1168 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1169 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1170 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1171 use_scaling = 1;
1172 }
1173 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1174 }
1175
1176 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1177 {
1178 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1179 vcpu->arch.virtual_tsc_mult,
1180 vcpu->arch.virtual_tsc_shift);
1181 tsc += vcpu->arch.this_tsc_write;
1182 return tsc;
1183 }
1184
1185 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1186 {
1187 #ifdef CONFIG_X86_64
1188 bool vcpus_matched;
1189 bool do_request = false;
1190 struct kvm_arch *ka = &vcpu->kvm->arch;
1191 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1192
1193 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1194 atomic_read(&vcpu->kvm->online_vcpus));
1195
1196 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1197 if (!ka->use_master_clock)
1198 do_request = 1;
1199
1200 if (!vcpus_matched && ka->use_master_clock)
1201 do_request = 1;
1202
1203 if (do_request)
1204 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1205
1206 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1207 atomic_read(&vcpu->kvm->online_vcpus),
1208 ka->use_master_clock, gtod->clock.vclock_mode);
1209 #endif
1210 }
1211
1212 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1213 {
1214 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1215 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1216 }
1217
1218 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1219 {
1220 struct kvm *kvm = vcpu->kvm;
1221 u64 offset, ns, elapsed;
1222 unsigned long flags;
1223 s64 usdiff;
1224 bool matched;
1225 u64 data = msr->data;
1226
1227 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1228 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1229 ns = get_kernel_ns();
1230 elapsed = ns - kvm->arch.last_tsc_nsec;
1231
1232 if (vcpu->arch.virtual_tsc_khz) {
1233 int faulted = 0;
1234
1235 /* n.b - signed multiplication and division required */
1236 usdiff = data - kvm->arch.last_tsc_write;
1237 #ifdef CONFIG_X86_64
1238 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1239 #else
1240 /* do_div() only does unsigned */
1241 asm("1: idivl %[divisor]\n"
1242 "2: xor %%edx, %%edx\n"
1243 " movl $0, %[faulted]\n"
1244 "3:\n"
1245 ".section .fixup,\"ax\"\n"
1246 "4: movl $1, %[faulted]\n"
1247 " jmp 3b\n"
1248 ".previous\n"
1249
1250 _ASM_EXTABLE(1b, 4b)
1251
1252 : "=A"(usdiff), [faulted] "=r" (faulted)
1253 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1254
1255 #endif
1256 do_div(elapsed, 1000);
1257 usdiff -= elapsed;
1258 if (usdiff < 0)
1259 usdiff = -usdiff;
1260
1261 /* idivl overflow => difference is larger than USEC_PER_SEC */
1262 if (faulted)
1263 usdiff = USEC_PER_SEC;
1264 } else
1265 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1266
1267 /*
1268 * Special case: TSC write with a small delta (1 second) of virtual
1269 * cycle time against real time is interpreted as an attempt to
1270 * synchronize the CPU.
1271 *
1272 * For a reliable TSC, we can match TSC offsets, and for an unstable
1273 * TSC, we add elapsed time in this computation. We could let the
1274 * compensation code attempt to catch up if we fall behind, but
1275 * it's better to try to match offsets from the beginning.
1276 */
1277 if (usdiff < USEC_PER_SEC &&
1278 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1279 if (!check_tsc_unstable()) {
1280 offset = kvm->arch.cur_tsc_offset;
1281 pr_debug("kvm: matched tsc offset for %llu\n", data);
1282 } else {
1283 u64 delta = nsec_to_cycles(vcpu, elapsed);
1284 data += delta;
1285 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1286 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1287 }
1288 matched = true;
1289 } else {
1290 /*
1291 * We split periods of matched TSC writes into generations.
1292 * For each generation, we track the original measured
1293 * nanosecond time, offset, and write, so if TSCs are in
1294 * sync, we can match exact offset, and if not, we can match
1295 * exact software computation in compute_guest_tsc()
1296 *
1297 * These values are tracked in kvm->arch.cur_xxx variables.
1298 */
1299 kvm->arch.cur_tsc_generation++;
1300 kvm->arch.cur_tsc_nsec = ns;
1301 kvm->arch.cur_tsc_write = data;
1302 kvm->arch.cur_tsc_offset = offset;
1303 matched = false;
1304 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1305 kvm->arch.cur_tsc_generation, data);
1306 }
1307
1308 /*
1309 * We also track th most recent recorded KHZ, write and time to
1310 * allow the matching interval to be extended at each write.
1311 */
1312 kvm->arch.last_tsc_nsec = ns;
1313 kvm->arch.last_tsc_write = data;
1314 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1315
1316 vcpu->arch.last_guest_tsc = data;
1317
1318 /* Keep track of which generation this VCPU has synchronized to */
1319 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1320 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1321 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1322
1323 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1324 update_ia32_tsc_adjust_msr(vcpu, offset);
1325 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1326 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1327
1328 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1329 if (matched)
1330 kvm->arch.nr_vcpus_matched_tsc++;
1331 else
1332 kvm->arch.nr_vcpus_matched_tsc = 0;
1333
1334 kvm_track_tsc_matching(vcpu);
1335 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1336 }
1337
1338 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1339
1340 #ifdef CONFIG_X86_64
1341
1342 static cycle_t read_tsc(void)
1343 {
1344 cycle_t ret;
1345 u64 last;
1346
1347 /*
1348 * Empirically, a fence (of type that depends on the CPU)
1349 * before rdtsc is enough to ensure that rdtsc is ordered
1350 * with respect to loads. The various CPU manuals are unclear
1351 * as to whether rdtsc can be reordered with later loads,
1352 * but no one has ever seen it happen.
1353 */
1354 rdtsc_barrier();
1355 ret = (cycle_t)vget_cycles();
1356
1357 last = pvclock_gtod_data.clock.cycle_last;
1358
1359 if (likely(ret >= last))
1360 return ret;
1361
1362 /*
1363 * GCC likes to generate cmov here, but this branch is extremely
1364 * predictable (it's just a funciton of time and the likely is
1365 * very likely) and there's a data dependence, so force GCC
1366 * to generate a branch instead. I don't barrier() because
1367 * we don't actually need a barrier, and if this function
1368 * ever gets inlined it will generate worse code.
1369 */
1370 asm volatile ("");
1371 return last;
1372 }
1373
1374 static inline u64 vgettsc(cycle_t *cycle_now)
1375 {
1376 long v;
1377 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1378
1379 *cycle_now = read_tsc();
1380
1381 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1382 return v * gtod->clock.mult;
1383 }
1384
1385 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1386 {
1387 unsigned long seq;
1388 u64 ns;
1389 int mode;
1390 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1391
1392 ts->tv_nsec = 0;
1393 do {
1394 seq = read_seqcount_begin(&gtod->seq);
1395 mode = gtod->clock.vclock_mode;
1396 ts->tv_sec = gtod->monotonic_time_sec;
1397 ns = gtod->monotonic_time_snsec;
1398 ns += vgettsc(cycle_now);
1399 ns >>= gtod->clock.shift;
1400 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1401 timespec_add_ns(ts, ns);
1402
1403 return mode;
1404 }
1405
1406 /* returns true if host is using tsc clocksource */
1407 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1408 {
1409 struct timespec ts;
1410
1411 /* checked again under seqlock below */
1412 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1413 return false;
1414
1415 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1416 return false;
1417
1418 monotonic_to_bootbased(&ts);
1419 *kernel_ns = timespec_to_ns(&ts);
1420
1421 return true;
1422 }
1423 #endif
1424
1425 /*
1426 *
1427 * Assuming a stable TSC across physical CPUS, and a stable TSC
1428 * across virtual CPUs, the following condition is possible.
1429 * Each numbered line represents an event visible to both
1430 * CPUs at the next numbered event.
1431 *
1432 * "timespecX" represents host monotonic time. "tscX" represents
1433 * RDTSC value.
1434 *
1435 * VCPU0 on CPU0 | VCPU1 on CPU1
1436 *
1437 * 1. read timespec0,tsc0
1438 * 2. | timespec1 = timespec0 + N
1439 * | tsc1 = tsc0 + M
1440 * 3. transition to guest | transition to guest
1441 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1442 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1443 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1444 *
1445 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1446 *
1447 * - ret0 < ret1
1448 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1449 * ...
1450 * - 0 < N - M => M < N
1451 *
1452 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1453 * always the case (the difference between two distinct xtime instances
1454 * might be smaller then the difference between corresponding TSC reads,
1455 * when updating guest vcpus pvclock areas).
1456 *
1457 * To avoid that problem, do not allow visibility of distinct
1458 * system_timestamp/tsc_timestamp values simultaneously: use a master
1459 * copy of host monotonic time values. Update that master copy
1460 * in lockstep.
1461 *
1462 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1463 *
1464 */
1465
1466 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1467 {
1468 #ifdef CONFIG_X86_64
1469 struct kvm_arch *ka = &kvm->arch;
1470 int vclock_mode;
1471 bool host_tsc_clocksource, vcpus_matched;
1472
1473 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1474 atomic_read(&kvm->online_vcpus));
1475
1476 /*
1477 * If the host uses TSC clock, then passthrough TSC as stable
1478 * to the guest.
1479 */
1480 host_tsc_clocksource = kvm_get_time_and_clockread(
1481 &ka->master_kernel_ns,
1482 &ka->master_cycle_now);
1483
1484 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1485
1486 if (ka->use_master_clock)
1487 atomic_set(&kvm_guest_has_master_clock, 1);
1488
1489 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1490 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1491 vcpus_matched);
1492 #endif
1493 }
1494
1495 static void kvm_gen_update_masterclock(struct kvm *kvm)
1496 {
1497 #ifdef CONFIG_X86_64
1498 int i;
1499 struct kvm_vcpu *vcpu;
1500 struct kvm_arch *ka = &kvm->arch;
1501
1502 spin_lock(&ka->pvclock_gtod_sync_lock);
1503 kvm_make_mclock_inprogress_request(kvm);
1504 /* no guest entries from this point */
1505 pvclock_update_vm_gtod_copy(kvm);
1506
1507 kvm_for_each_vcpu(i, vcpu, kvm)
1508 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1509
1510 /* guest entries allowed */
1511 kvm_for_each_vcpu(i, vcpu, kvm)
1512 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1513
1514 spin_unlock(&ka->pvclock_gtod_sync_lock);
1515 #endif
1516 }
1517
1518 static int kvm_guest_time_update(struct kvm_vcpu *v)
1519 {
1520 unsigned long flags, this_tsc_khz;
1521 struct kvm_vcpu_arch *vcpu = &v->arch;
1522 struct kvm_arch *ka = &v->kvm->arch;
1523 s64 kernel_ns;
1524 u64 tsc_timestamp, host_tsc;
1525 struct pvclock_vcpu_time_info guest_hv_clock;
1526 u8 pvclock_flags;
1527 bool use_master_clock;
1528
1529 kernel_ns = 0;
1530 host_tsc = 0;
1531
1532 /*
1533 * If the host uses TSC clock, then passthrough TSC as stable
1534 * to the guest.
1535 */
1536 spin_lock(&ka->pvclock_gtod_sync_lock);
1537 use_master_clock = ka->use_master_clock;
1538 if (use_master_clock) {
1539 host_tsc = ka->master_cycle_now;
1540 kernel_ns = ka->master_kernel_ns;
1541 }
1542 spin_unlock(&ka->pvclock_gtod_sync_lock);
1543
1544 /* Keep irq disabled to prevent changes to the clock */
1545 local_irq_save(flags);
1546 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1547 if (unlikely(this_tsc_khz == 0)) {
1548 local_irq_restore(flags);
1549 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1550 return 1;
1551 }
1552 if (!use_master_clock) {
1553 host_tsc = native_read_tsc();
1554 kernel_ns = get_kernel_ns();
1555 }
1556
1557 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1558
1559 /*
1560 * We may have to catch up the TSC to match elapsed wall clock
1561 * time for two reasons, even if kvmclock is used.
1562 * 1) CPU could have been running below the maximum TSC rate
1563 * 2) Broken TSC compensation resets the base at each VCPU
1564 * entry to avoid unknown leaps of TSC even when running
1565 * again on the same CPU. This may cause apparent elapsed
1566 * time to disappear, and the guest to stand still or run
1567 * very slowly.
1568 */
1569 if (vcpu->tsc_catchup) {
1570 u64 tsc = compute_guest_tsc(v, kernel_ns);
1571 if (tsc > tsc_timestamp) {
1572 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1573 tsc_timestamp = tsc;
1574 }
1575 }
1576
1577 local_irq_restore(flags);
1578
1579 if (!vcpu->pv_time_enabled)
1580 return 0;
1581
1582 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1583 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1584 &vcpu->hv_clock.tsc_shift,
1585 &vcpu->hv_clock.tsc_to_system_mul);
1586 vcpu->hw_tsc_khz = this_tsc_khz;
1587 }
1588
1589 /* With all the info we got, fill in the values */
1590 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1591 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1592 vcpu->last_guest_tsc = tsc_timestamp;
1593
1594 /*
1595 * The interface expects us to write an even number signaling that the
1596 * update is finished. Since the guest won't see the intermediate
1597 * state, we just increase by 2 at the end.
1598 */
1599 vcpu->hv_clock.version += 2;
1600
1601 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1602 &guest_hv_clock, sizeof(guest_hv_clock))))
1603 return 0;
1604
1605 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1606 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1607
1608 if (vcpu->pvclock_set_guest_stopped_request) {
1609 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1610 vcpu->pvclock_set_guest_stopped_request = false;
1611 }
1612
1613 /* If the host uses TSC clocksource, then it is stable */
1614 if (use_master_clock)
1615 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1616
1617 vcpu->hv_clock.flags = pvclock_flags;
1618
1619 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1620 &vcpu->hv_clock,
1621 sizeof(vcpu->hv_clock));
1622 return 0;
1623 }
1624
1625 /*
1626 * kvmclock updates which are isolated to a given vcpu, such as
1627 * vcpu->cpu migration, should not allow system_timestamp from
1628 * the rest of the vcpus to remain static. Otherwise ntp frequency
1629 * correction applies to one vcpu's system_timestamp but not
1630 * the others.
1631 *
1632 * So in those cases, request a kvmclock update for all vcpus.
1633 * We need to rate-limit these requests though, as they can
1634 * considerably slow guests that have a large number of vcpus.
1635 * The time for a remote vcpu to update its kvmclock is bound
1636 * by the delay we use to rate-limit the updates.
1637 */
1638
1639 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1640
1641 static void kvmclock_update_fn(struct work_struct *work)
1642 {
1643 int i;
1644 struct delayed_work *dwork = to_delayed_work(work);
1645 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1646 kvmclock_update_work);
1647 struct kvm *kvm = container_of(ka, struct kvm, arch);
1648 struct kvm_vcpu *vcpu;
1649
1650 kvm_for_each_vcpu(i, vcpu, kvm) {
1651 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1652 kvm_vcpu_kick(vcpu);
1653 }
1654 }
1655
1656 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1657 {
1658 struct kvm *kvm = v->kvm;
1659
1660 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1661 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1662 KVMCLOCK_UPDATE_DELAY);
1663 }
1664
1665 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1666
1667 static void kvmclock_sync_fn(struct work_struct *work)
1668 {
1669 struct delayed_work *dwork = to_delayed_work(work);
1670 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1671 kvmclock_sync_work);
1672 struct kvm *kvm = container_of(ka, struct kvm, arch);
1673
1674 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1675 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1676 KVMCLOCK_SYNC_PERIOD);
1677 }
1678
1679 static bool msr_mtrr_valid(unsigned msr)
1680 {
1681 switch (msr) {
1682 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1683 case MSR_MTRRfix64K_00000:
1684 case MSR_MTRRfix16K_80000:
1685 case MSR_MTRRfix16K_A0000:
1686 case MSR_MTRRfix4K_C0000:
1687 case MSR_MTRRfix4K_C8000:
1688 case MSR_MTRRfix4K_D0000:
1689 case MSR_MTRRfix4K_D8000:
1690 case MSR_MTRRfix4K_E0000:
1691 case MSR_MTRRfix4K_E8000:
1692 case MSR_MTRRfix4K_F0000:
1693 case MSR_MTRRfix4K_F8000:
1694 case MSR_MTRRdefType:
1695 case MSR_IA32_CR_PAT:
1696 return true;
1697 case 0x2f8:
1698 return true;
1699 }
1700 return false;
1701 }
1702
1703 static bool valid_pat_type(unsigned t)
1704 {
1705 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1706 }
1707
1708 static bool valid_mtrr_type(unsigned t)
1709 {
1710 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1711 }
1712
1713 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1714 {
1715 int i;
1716
1717 if (!msr_mtrr_valid(msr))
1718 return false;
1719
1720 if (msr == MSR_IA32_CR_PAT) {
1721 for (i = 0; i < 8; i++)
1722 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1723 return false;
1724 return true;
1725 } else if (msr == MSR_MTRRdefType) {
1726 if (data & ~0xcff)
1727 return false;
1728 return valid_mtrr_type(data & 0xff);
1729 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1730 for (i = 0; i < 8 ; i++)
1731 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1732 return false;
1733 return true;
1734 }
1735
1736 /* variable MTRRs */
1737 return valid_mtrr_type(data & 0xff);
1738 }
1739
1740 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1741 {
1742 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1743
1744 if (!mtrr_valid(vcpu, msr, data))
1745 return 1;
1746
1747 if (msr == MSR_MTRRdefType) {
1748 vcpu->arch.mtrr_state.def_type = data;
1749 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1750 } else if (msr == MSR_MTRRfix64K_00000)
1751 p[0] = data;
1752 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1753 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1754 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1755 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1756 else if (msr == MSR_IA32_CR_PAT)
1757 vcpu->arch.pat = data;
1758 else { /* Variable MTRRs */
1759 int idx, is_mtrr_mask;
1760 u64 *pt;
1761
1762 idx = (msr - 0x200) / 2;
1763 is_mtrr_mask = msr - 0x200 - 2 * idx;
1764 if (!is_mtrr_mask)
1765 pt =
1766 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1767 else
1768 pt =
1769 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1770 *pt = data;
1771 }
1772
1773 kvm_mmu_reset_context(vcpu);
1774 return 0;
1775 }
1776
1777 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1778 {
1779 u64 mcg_cap = vcpu->arch.mcg_cap;
1780 unsigned bank_num = mcg_cap & 0xff;
1781
1782 switch (msr) {
1783 case MSR_IA32_MCG_STATUS:
1784 vcpu->arch.mcg_status = data;
1785 break;
1786 case MSR_IA32_MCG_CTL:
1787 if (!(mcg_cap & MCG_CTL_P))
1788 return 1;
1789 if (data != 0 && data != ~(u64)0)
1790 return -1;
1791 vcpu->arch.mcg_ctl = data;
1792 break;
1793 default:
1794 if (msr >= MSR_IA32_MC0_CTL &&
1795 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1796 u32 offset = msr - MSR_IA32_MC0_CTL;
1797 /* only 0 or all 1s can be written to IA32_MCi_CTL
1798 * some Linux kernels though clear bit 10 in bank 4 to
1799 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1800 * this to avoid an uncatched #GP in the guest
1801 */
1802 if ((offset & 0x3) == 0 &&
1803 data != 0 && (data | (1 << 10)) != ~(u64)0)
1804 return -1;
1805 vcpu->arch.mce_banks[offset] = data;
1806 break;
1807 }
1808 return 1;
1809 }
1810 return 0;
1811 }
1812
1813 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1814 {
1815 struct kvm *kvm = vcpu->kvm;
1816 int lm = is_long_mode(vcpu);
1817 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1818 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1819 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1820 : kvm->arch.xen_hvm_config.blob_size_32;
1821 u32 page_num = data & ~PAGE_MASK;
1822 u64 page_addr = data & PAGE_MASK;
1823 u8 *page;
1824 int r;
1825
1826 r = -E2BIG;
1827 if (page_num >= blob_size)
1828 goto out;
1829 r = -ENOMEM;
1830 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1831 if (IS_ERR(page)) {
1832 r = PTR_ERR(page);
1833 goto out;
1834 }
1835 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1836 goto out_free;
1837 r = 0;
1838 out_free:
1839 kfree(page);
1840 out:
1841 return r;
1842 }
1843
1844 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1845 {
1846 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1847 }
1848
1849 static bool kvm_hv_msr_partition_wide(u32 msr)
1850 {
1851 bool r = false;
1852 switch (msr) {
1853 case HV_X64_MSR_GUEST_OS_ID:
1854 case HV_X64_MSR_HYPERCALL:
1855 case HV_X64_MSR_REFERENCE_TSC:
1856 case HV_X64_MSR_TIME_REF_COUNT:
1857 r = true;
1858 break;
1859 }
1860
1861 return r;
1862 }
1863
1864 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1865 {
1866 struct kvm *kvm = vcpu->kvm;
1867
1868 switch (msr) {
1869 case HV_X64_MSR_GUEST_OS_ID:
1870 kvm->arch.hv_guest_os_id = data;
1871 /* setting guest os id to zero disables hypercall page */
1872 if (!kvm->arch.hv_guest_os_id)
1873 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1874 break;
1875 case HV_X64_MSR_HYPERCALL: {
1876 u64 gfn;
1877 unsigned long addr;
1878 u8 instructions[4];
1879
1880 /* if guest os id is not set hypercall should remain disabled */
1881 if (!kvm->arch.hv_guest_os_id)
1882 break;
1883 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1884 kvm->arch.hv_hypercall = data;
1885 break;
1886 }
1887 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1888 addr = gfn_to_hva(kvm, gfn);
1889 if (kvm_is_error_hva(addr))
1890 return 1;
1891 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1892 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1893 if (__copy_to_user((void __user *)addr, instructions, 4))
1894 return 1;
1895 kvm->arch.hv_hypercall = data;
1896 mark_page_dirty(kvm, gfn);
1897 break;
1898 }
1899 case HV_X64_MSR_REFERENCE_TSC: {
1900 u64 gfn;
1901 HV_REFERENCE_TSC_PAGE tsc_ref;
1902 memset(&tsc_ref, 0, sizeof(tsc_ref));
1903 kvm->arch.hv_tsc_page = data;
1904 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1905 break;
1906 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1907 if (kvm_write_guest(kvm, data,
1908 &tsc_ref, sizeof(tsc_ref)))
1909 return 1;
1910 mark_page_dirty(kvm, gfn);
1911 break;
1912 }
1913 default:
1914 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1915 "data 0x%llx\n", msr, data);
1916 return 1;
1917 }
1918 return 0;
1919 }
1920
1921 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1922 {
1923 switch (msr) {
1924 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1925 u64 gfn;
1926 unsigned long addr;
1927
1928 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1929 vcpu->arch.hv_vapic = data;
1930 break;
1931 }
1932 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1933 addr = gfn_to_hva(vcpu->kvm, gfn);
1934 if (kvm_is_error_hva(addr))
1935 return 1;
1936 if (__clear_user((void __user *)addr, PAGE_SIZE))
1937 return 1;
1938 vcpu->arch.hv_vapic = data;
1939 mark_page_dirty(vcpu->kvm, gfn);
1940 break;
1941 }
1942 case HV_X64_MSR_EOI:
1943 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1944 case HV_X64_MSR_ICR:
1945 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1946 case HV_X64_MSR_TPR:
1947 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1948 default:
1949 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1950 "data 0x%llx\n", msr, data);
1951 return 1;
1952 }
1953
1954 return 0;
1955 }
1956
1957 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1958 {
1959 gpa_t gpa = data & ~0x3f;
1960
1961 /* Bits 2:5 are reserved, Should be zero */
1962 if (data & 0x3c)
1963 return 1;
1964
1965 vcpu->arch.apf.msr_val = data;
1966
1967 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1968 kvm_clear_async_pf_completion_queue(vcpu);
1969 kvm_async_pf_hash_reset(vcpu);
1970 return 0;
1971 }
1972
1973 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1974 sizeof(u32)))
1975 return 1;
1976
1977 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1978 kvm_async_pf_wakeup_all(vcpu);
1979 return 0;
1980 }
1981
1982 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1983 {
1984 vcpu->arch.pv_time_enabled = false;
1985 }
1986
1987 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1988 {
1989 u64 delta;
1990
1991 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1992 return;
1993
1994 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1995 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1996 vcpu->arch.st.accum_steal = delta;
1997 }
1998
1999 static void record_steal_time(struct kvm_vcpu *vcpu)
2000 {
2001 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2002 return;
2003
2004 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2005 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2006 return;
2007
2008 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2009 vcpu->arch.st.steal.version += 2;
2010 vcpu->arch.st.accum_steal = 0;
2011
2012 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2013 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2014 }
2015
2016 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2017 {
2018 bool pr = false;
2019 u32 msr = msr_info->index;
2020 u64 data = msr_info->data;
2021
2022 switch (msr) {
2023 case MSR_AMD64_NB_CFG:
2024 case MSR_IA32_UCODE_REV:
2025 case MSR_IA32_UCODE_WRITE:
2026 case MSR_VM_HSAVE_PA:
2027 case MSR_AMD64_PATCH_LOADER:
2028 case MSR_AMD64_BU_CFG2:
2029 break;
2030
2031 case MSR_EFER:
2032 return set_efer(vcpu, data);
2033 case MSR_K7_HWCR:
2034 data &= ~(u64)0x40; /* ignore flush filter disable */
2035 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2036 data &= ~(u64)0x8; /* ignore TLB cache disable */
2037 if (data != 0) {
2038 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2039 data);
2040 return 1;
2041 }
2042 break;
2043 case MSR_FAM10H_MMIO_CONF_BASE:
2044 if (data != 0) {
2045 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2046 "0x%llx\n", data);
2047 return 1;
2048 }
2049 break;
2050 case MSR_IA32_DEBUGCTLMSR:
2051 if (!data) {
2052 /* We support the non-activated case already */
2053 break;
2054 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2055 /* Values other than LBR and BTF are vendor-specific,
2056 thus reserved and should throw a #GP */
2057 return 1;
2058 }
2059 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2060 __func__, data);
2061 break;
2062 case 0x200 ... 0x2ff:
2063 return set_msr_mtrr(vcpu, msr, data);
2064 case MSR_IA32_APICBASE:
2065 return kvm_set_apic_base(vcpu, msr_info);
2066 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2067 return kvm_x2apic_msr_write(vcpu, msr, data);
2068 case MSR_IA32_TSCDEADLINE:
2069 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2070 break;
2071 case MSR_IA32_TSC_ADJUST:
2072 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2073 if (!msr_info->host_initiated) {
2074 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2075 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2076 }
2077 vcpu->arch.ia32_tsc_adjust_msr = data;
2078 }
2079 break;
2080 case MSR_IA32_MISC_ENABLE:
2081 vcpu->arch.ia32_misc_enable_msr = data;
2082 break;
2083 case MSR_KVM_WALL_CLOCK_NEW:
2084 case MSR_KVM_WALL_CLOCK:
2085 vcpu->kvm->arch.wall_clock = data;
2086 kvm_write_wall_clock(vcpu->kvm, data);
2087 break;
2088 case MSR_KVM_SYSTEM_TIME_NEW:
2089 case MSR_KVM_SYSTEM_TIME: {
2090 u64 gpa_offset;
2091 kvmclock_reset(vcpu);
2092
2093 vcpu->arch.time = data;
2094 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2095
2096 /* we verify if the enable bit is set... */
2097 if (!(data & 1))
2098 break;
2099
2100 gpa_offset = data & ~(PAGE_MASK | 1);
2101
2102 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2103 &vcpu->arch.pv_time, data & ~1ULL,
2104 sizeof(struct pvclock_vcpu_time_info)))
2105 vcpu->arch.pv_time_enabled = false;
2106 else
2107 vcpu->arch.pv_time_enabled = true;
2108
2109 break;
2110 }
2111 case MSR_KVM_ASYNC_PF_EN:
2112 if (kvm_pv_enable_async_pf(vcpu, data))
2113 return 1;
2114 break;
2115 case MSR_KVM_STEAL_TIME:
2116
2117 if (unlikely(!sched_info_on()))
2118 return 1;
2119
2120 if (data & KVM_STEAL_RESERVED_MASK)
2121 return 1;
2122
2123 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2124 data & KVM_STEAL_VALID_BITS,
2125 sizeof(struct kvm_steal_time)))
2126 return 1;
2127
2128 vcpu->arch.st.msr_val = data;
2129
2130 if (!(data & KVM_MSR_ENABLED))
2131 break;
2132
2133 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2134
2135 preempt_disable();
2136 accumulate_steal_time(vcpu);
2137 preempt_enable();
2138
2139 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2140
2141 break;
2142 case MSR_KVM_PV_EOI_EN:
2143 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2144 return 1;
2145 break;
2146
2147 case MSR_IA32_MCG_CTL:
2148 case MSR_IA32_MCG_STATUS:
2149 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2150 return set_msr_mce(vcpu, msr, data);
2151
2152 /* Performance counters are not protected by a CPUID bit,
2153 * so we should check all of them in the generic path for the sake of
2154 * cross vendor migration.
2155 * Writing a zero into the event select MSRs disables them,
2156 * which we perfectly emulate ;-). Any other value should be at least
2157 * reported, some guests depend on them.
2158 */
2159 case MSR_K7_EVNTSEL0:
2160 case MSR_K7_EVNTSEL1:
2161 case MSR_K7_EVNTSEL2:
2162 case MSR_K7_EVNTSEL3:
2163 if (data != 0)
2164 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2165 "0x%x data 0x%llx\n", msr, data);
2166 break;
2167 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2168 * so we ignore writes to make it happy.
2169 */
2170 case MSR_K7_PERFCTR0:
2171 case MSR_K7_PERFCTR1:
2172 case MSR_K7_PERFCTR2:
2173 case MSR_K7_PERFCTR3:
2174 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2175 "0x%x data 0x%llx\n", msr, data);
2176 break;
2177 case MSR_P6_PERFCTR0:
2178 case MSR_P6_PERFCTR1:
2179 pr = true;
2180 case MSR_P6_EVNTSEL0:
2181 case MSR_P6_EVNTSEL1:
2182 if (kvm_pmu_msr(vcpu, msr))
2183 return kvm_pmu_set_msr(vcpu, msr_info);
2184
2185 if (pr || data != 0)
2186 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2187 "0x%x data 0x%llx\n", msr, data);
2188 break;
2189 case MSR_K7_CLK_CTL:
2190 /*
2191 * Ignore all writes to this no longer documented MSR.
2192 * Writes are only relevant for old K7 processors,
2193 * all pre-dating SVM, but a recommended workaround from
2194 * AMD for these chips. It is possible to specify the
2195 * affected processor models on the command line, hence
2196 * the need to ignore the workaround.
2197 */
2198 break;
2199 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2200 if (kvm_hv_msr_partition_wide(msr)) {
2201 int r;
2202 mutex_lock(&vcpu->kvm->lock);
2203 r = set_msr_hyperv_pw(vcpu, msr, data);
2204 mutex_unlock(&vcpu->kvm->lock);
2205 return r;
2206 } else
2207 return set_msr_hyperv(vcpu, msr, data);
2208 break;
2209 case MSR_IA32_BBL_CR_CTL3:
2210 /* Drop writes to this legacy MSR -- see rdmsr
2211 * counterpart for further detail.
2212 */
2213 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2214 break;
2215 case MSR_AMD64_OSVW_ID_LENGTH:
2216 if (!guest_cpuid_has_osvw(vcpu))
2217 return 1;
2218 vcpu->arch.osvw.length = data;
2219 break;
2220 case MSR_AMD64_OSVW_STATUS:
2221 if (!guest_cpuid_has_osvw(vcpu))
2222 return 1;
2223 vcpu->arch.osvw.status = data;
2224 break;
2225 default:
2226 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2227 return xen_hvm_config(vcpu, data);
2228 if (kvm_pmu_msr(vcpu, msr))
2229 return kvm_pmu_set_msr(vcpu, msr_info);
2230 if (!ignore_msrs) {
2231 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2232 msr, data);
2233 return 1;
2234 } else {
2235 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2236 msr, data);
2237 break;
2238 }
2239 }
2240 return 0;
2241 }
2242 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2243
2244
2245 /*
2246 * Reads an msr value (of 'msr_index') into 'pdata'.
2247 * Returns 0 on success, non-0 otherwise.
2248 * Assumes vcpu_load() was already called.
2249 */
2250 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2251 {
2252 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2253 }
2254
2255 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2256 {
2257 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2258
2259 if (!msr_mtrr_valid(msr))
2260 return 1;
2261
2262 if (msr == MSR_MTRRdefType)
2263 *pdata = vcpu->arch.mtrr_state.def_type +
2264 (vcpu->arch.mtrr_state.enabled << 10);
2265 else if (msr == MSR_MTRRfix64K_00000)
2266 *pdata = p[0];
2267 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2268 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2269 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2270 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2271 else if (msr == MSR_IA32_CR_PAT)
2272 *pdata = vcpu->arch.pat;
2273 else { /* Variable MTRRs */
2274 int idx, is_mtrr_mask;
2275 u64 *pt;
2276
2277 idx = (msr - 0x200) / 2;
2278 is_mtrr_mask = msr - 0x200 - 2 * idx;
2279 if (!is_mtrr_mask)
2280 pt =
2281 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2282 else
2283 pt =
2284 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2285 *pdata = *pt;
2286 }
2287
2288 return 0;
2289 }
2290
2291 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2292 {
2293 u64 data;
2294 u64 mcg_cap = vcpu->arch.mcg_cap;
2295 unsigned bank_num = mcg_cap & 0xff;
2296
2297 switch (msr) {
2298 case MSR_IA32_P5_MC_ADDR:
2299 case MSR_IA32_P5_MC_TYPE:
2300 data = 0;
2301 break;
2302 case MSR_IA32_MCG_CAP:
2303 data = vcpu->arch.mcg_cap;
2304 break;
2305 case MSR_IA32_MCG_CTL:
2306 if (!(mcg_cap & MCG_CTL_P))
2307 return 1;
2308 data = vcpu->arch.mcg_ctl;
2309 break;
2310 case MSR_IA32_MCG_STATUS:
2311 data = vcpu->arch.mcg_status;
2312 break;
2313 default:
2314 if (msr >= MSR_IA32_MC0_CTL &&
2315 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2316 u32 offset = msr - MSR_IA32_MC0_CTL;
2317 data = vcpu->arch.mce_banks[offset];
2318 break;
2319 }
2320 return 1;
2321 }
2322 *pdata = data;
2323 return 0;
2324 }
2325
2326 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2327 {
2328 u64 data = 0;
2329 struct kvm *kvm = vcpu->kvm;
2330
2331 switch (msr) {
2332 case HV_X64_MSR_GUEST_OS_ID:
2333 data = kvm->arch.hv_guest_os_id;
2334 break;
2335 case HV_X64_MSR_HYPERCALL:
2336 data = kvm->arch.hv_hypercall;
2337 break;
2338 case HV_X64_MSR_TIME_REF_COUNT: {
2339 data =
2340 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2341 break;
2342 }
2343 case HV_X64_MSR_REFERENCE_TSC:
2344 data = kvm->arch.hv_tsc_page;
2345 break;
2346 default:
2347 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2348 return 1;
2349 }
2350
2351 *pdata = data;
2352 return 0;
2353 }
2354
2355 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2356 {
2357 u64 data = 0;
2358
2359 switch (msr) {
2360 case HV_X64_MSR_VP_INDEX: {
2361 int r;
2362 struct kvm_vcpu *v;
2363 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2364 if (v == vcpu) {
2365 data = r;
2366 break;
2367 }
2368 }
2369 break;
2370 }
2371 case HV_X64_MSR_EOI:
2372 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2373 case HV_X64_MSR_ICR:
2374 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2375 case HV_X64_MSR_TPR:
2376 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2377 case HV_X64_MSR_APIC_ASSIST_PAGE:
2378 data = vcpu->arch.hv_vapic;
2379 break;
2380 default:
2381 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2382 return 1;
2383 }
2384 *pdata = data;
2385 return 0;
2386 }
2387
2388 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2389 {
2390 u64 data;
2391
2392 switch (msr) {
2393 case MSR_IA32_PLATFORM_ID:
2394 case MSR_IA32_EBL_CR_POWERON:
2395 case MSR_IA32_DEBUGCTLMSR:
2396 case MSR_IA32_LASTBRANCHFROMIP:
2397 case MSR_IA32_LASTBRANCHTOIP:
2398 case MSR_IA32_LASTINTFROMIP:
2399 case MSR_IA32_LASTINTTOIP:
2400 case MSR_K8_SYSCFG:
2401 case MSR_K7_HWCR:
2402 case MSR_VM_HSAVE_PA:
2403 case MSR_K7_EVNTSEL0:
2404 case MSR_K7_PERFCTR0:
2405 case MSR_K8_INT_PENDING_MSG:
2406 case MSR_AMD64_NB_CFG:
2407 case MSR_FAM10H_MMIO_CONF_BASE:
2408 case MSR_AMD64_BU_CFG2:
2409 data = 0;
2410 break;
2411 case MSR_P6_PERFCTR0:
2412 case MSR_P6_PERFCTR1:
2413 case MSR_P6_EVNTSEL0:
2414 case MSR_P6_EVNTSEL1:
2415 if (kvm_pmu_msr(vcpu, msr))
2416 return kvm_pmu_get_msr(vcpu, msr, pdata);
2417 data = 0;
2418 break;
2419 case MSR_IA32_UCODE_REV:
2420 data = 0x100000000ULL;
2421 break;
2422 case MSR_MTRRcap:
2423 data = 0x500 | KVM_NR_VAR_MTRR;
2424 break;
2425 case 0x200 ... 0x2ff:
2426 return get_msr_mtrr(vcpu, msr, pdata);
2427 case 0xcd: /* fsb frequency */
2428 data = 3;
2429 break;
2430 /*
2431 * MSR_EBC_FREQUENCY_ID
2432 * Conservative value valid for even the basic CPU models.
2433 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2434 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2435 * and 266MHz for model 3, or 4. Set Core Clock
2436 * Frequency to System Bus Frequency Ratio to 1 (bits
2437 * 31:24) even though these are only valid for CPU
2438 * models > 2, however guests may end up dividing or
2439 * multiplying by zero otherwise.
2440 */
2441 case MSR_EBC_FREQUENCY_ID:
2442 data = 1 << 24;
2443 break;
2444 case MSR_IA32_APICBASE:
2445 data = kvm_get_apic_base(vcpu);
2446 break;
2447 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2448 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2449 break;
2450 case MSR_IA32_TSCDEADLINE:
2451 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2452 break;
2453 case MSR_IA32_TSC_ADJUST:
2454 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2455 break;
2456 case MSR_IA32_MISC_ENABLE:
2457 data = vcpu->arch.ia32_misc_enable_msr;
2458 break;
2459 case MSR_IA32_PERF_STATUS:
2460 /* TSC increment by tick */
2461 data = 1000ULL;
2462 /* CPU multiplier */
2463 data |= (((uint64_t)4ULL) << 40);
2464 break;
2465 case MSR_EFER:
2466 data = vcpu->arch.efer;
2467 break;
2468 case MSR_KVM_WALL_CLOCK:
2469 case MSR_KVM_WALL_CLOCK_NEW:
2470 data = vcpu->kvm->arch.wall_clock;
2471 break;
2472 case MSR_KVM_SYSTEM_TIME:
2473 case MSR_KVM_SYSTEM_TIME_NEW:
2474 data = vcpu->arch.time;
2475 break;
2476 case MSR_KVM_ASYNC_PF_EN:
2477 data = vcpu->arch.apf.msr_val;
2478 break;
2479 case MSR_KVM_STEAL_TIME:
2480 data = vcpu->arch.st.msr_val;
2481 break;
2482 case MSR_KVM_PV_EOI_EN:
2483 data = vcpu->arch.pv_eoi.msr_val;
2484 break;
2485 case MSR_IA32_P5_MC_ADDR:
2486 case MSR_IA32_P5_MC_TYPE:
2487 case MSR_IA32_MCG_CAP:
2488 case MSR_IA32_MCG_CTL:
2489 case MSR_IA32_MCG_STATUS:
2490 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2491 return get_msr_mce(vcpu, msr, pdata);
2492 case MSR_K7_CLK_CTL:
2493 /*
2494 * Provide expected ramp-up count for K7. All other
2495 * are set to zero, indicating minimum divisors for
2496 * every field.
2497 *
2498 * This prevents guest kernels on AMD host with CPU
2499 * type 6, model 8 and higher from exploding due to
2500 * the rdmsr failing.
2501 */
2502 data = 0x20000000;
2503 break;
2504 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2505 if (kvm_hv_msr_partition_wide(msr)) {
2506 int r;
2507 mutex_lock(&vcpu->kvm->lock);
2508 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2509 mutex_unlock(&vcpu->kvm->lock);
2510 return r;
2511 } else
2512 return get_msr_hyperv(vcpu, msr, pdata);
2513 break;
2514 case MSR_IA32_BBL_CR_CTL3:
2515 /* This legacy MSR exists but isn't fully documented in current
2516 * silicon. It is however accessed by winxp in very narrow
2517 * scenarios where it sets bit #19, itself documented as
2518 * a "reserved" bit. Best effort attempt to source coherent
2519 * read data here should the balance of the register be
2520 * interpreted by the guest:
2521 *
2522 * L2 cache control register 3: 64GB range, 256KB size,
2523 * enabled, latency 0x1, configured
2524 */
2525 data = 0xbe702111;
2526 break;
2527 case MSR_AMD64_OSVW_ID_LENGTH:
2528 if (!guest_cpuid_has_osvw(vcpu))
2529 return 1;
2530 data = vcpu->arch.osvw.length;
2531 break;
2532 case MSR_AMD64_OSVW_STATUS:
2533 if (!guest_cpuid_has_osvw(vcpu))
2534 return 1;
2535 data = vcpu->arch.osvw.status;
2536 break;
2537 default:
2538 if (kvm_pmu_msr(vcpu, msr))
2539 return kvm_pmu_get_msr(vcpu, msr, pdata);
2540 if (!ignore_msrs) {
2541 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2542 return 1;
2543 } else {
2544 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2545 data = 0;
2546 }
2547 break;
2548 }
2549 *pdata = data;
2550 return 0;
2551 }
2552 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2553
2554 /*
2555 * Read or write a bunch of msrs. All parameters are kernel addresses.
2556 *
2557 * @return number of msrs set successfully.
2558 */
2559 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2560 struct kvm_msr_entry *entries,
2561 int (*do_msr)(struct kvm_vcpu *vcpu,
2562 unsigned index, u64 *data))
2563 {
2564 int i, idx;
2565
2566 idx = srcu_read_lock(&vcpu->kvm->srcu);
2567 for (i = 0; i < msrs->nmsrs; ++i)
2568 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2569 break;
2570 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2571
2572 return i;
2573 }
2574
2575 /*
2576 * Read or write a bunch of msrs. Parameters are user addresses.
2577 *
2578 * @return number of msrs set successfully.
2579 */
2580 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2581 int (*do_msr)(struct kvm_vcpu *vcpu,
2582 unsigned index, u64 *data),
2583 int writeback)
2584 {
2585 struct kvm_msrs msrs;
2586 struct kvm_msr_entry *entries;
2587 int r, n;
2588 unsigned size;
2589
2590 r = -EFAULT;
2591 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2592 goto out;
2593
2594 r = -E2BIG;
2595 if (msrs.nmsrs >= MAX_IO_MSRS)
2596 goto out;
2597
2598 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2599 entries = memdup_user(user_msrs->entries, size);
2600 if (IS_ERR(entries)) {
2601 r = PTR_ERR(entries);
2602 goto out;
2603 }
2604
2605 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2606 if (r < 0)
2607 goto out_free;
2608
2609 r = -EFAULT;
2610 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2611 goto out_free;
2612
2613 r = n;
2614
2615 out_free:
2616 kfree(entries);
2617 out:
2618 return r;
2619 }
2620
2621 int kvm_dev_ioctl_check_extension(long ext)
2622 {
2623 int r;
2624
2625 switch (ext) {
2626 case KVM_CAP_IRQCHIP:
2627 case KVM_CAP_HLT:
2628 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2629 case KVM_CAP_SET_TSS_ADDR:
2630 case KVM_CAP_EXT_CPUID:
2631 case KVM_CAP_EXT_EMUL_CPUID:
2632 case KVM_CAP_CLOCKSOURCE:
2633 case KVM_CAP_PIT:
2634 case KVM_CAP_NOP_IO_DELAY:
2635 case KVM_CAP_MP_STATE:
2636 case KVM_CAP_SYNC_MMU:
2637 case KVM_CAP_USER_NMI:
2638 case KVM_CAP_REINJECT_CONTROL:
2639 case KVM_CAP_IRQ_INJECT_STATUS:
2640 case KVM_CAP_IRQFD:
2641 case KVM_CAP_IOEVENTFD:
2642 case KVM_CAP_PIT2:
2643 case KVM_CAP_PIT_STATE2:
2644 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2645 case KVM_CAP_XEN_HVM:
2646 case KVM_CAP_ADJUST_CLOCK:
2647 case KVM_CAP_VCPU_EVENTS:
2648 case KVM_CAP_HYPERV:
2649 case KVM_CAP_HYPERV_VAPIC:
2650 case KVM_CAP_HYPERV_SPIN:
2651 case KVM_CAP_PCI_SEGMENT:
2652 case KVM_CAP_DEBUGREGS:
2653 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2654 case KVM_CAP_XSAVE:
2655 case KVM_CAP_ASYNC_PF:
2656 case KVM_CAP_GET_TSC_KHZ:
2657 case KVM_CAP_KVMCLOCK_CTRL:
2658 case KVM_CAP_READONLY_MEM:
2659 case KVM_CAP_HYPERV_TIME:
2660 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2661 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2662 case KVM_CAP_ASSIGN_DEV_IRQ:
2663 case KVM_CAP_PCI_2_3:
2664 #endif
2665 r = 1;
2666 break;
2667 case KVM_CAP_COALESCED_MMIO:
2668 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2669 break;
2670 case KVM_CAP_VAPIC:
2671 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2672 break;
2673 case KVM_CAP_NR_VCPUS:
2674 r = KVM_SOFT_MAX_VCPUS;
2675 break;
2676 case KVM_CAP_MAX_VCPUS:
2677 r = KVM_MAX_VCPUS;
2678 break;
2679 case KVM_CAP_NR_MEMSLOTS:
2680 r = KVM_USER_MEM_SLOTS;
2681 break;
2682 case KVM_CAP_PV_MMU: /* obsolete */
2683 r = 0;
2684 break;
2685 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2686 case KVM_CAP_IOMMU:
2687 r = iommu_present(&pci_bus_type);
2688 break;
2689 #endif
2690 case KVM_CAP_MCE:
2691 r = KVM_MAX_MCE_BANKS;
2692 break;
2693 case KVM_CAP_XCRS:
2694 r = cpu_has_xsave;
2695 break;
2696 case KVM_CAP_TSC_CONTROL:
2697 r = kvm_has_tsc_control;
2698 break;
2699 case KVM_CAP_TSC_DEADLINE_TIMER:
2700 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2701 break;
2702 default:
2703 r = 0;
2704 break;
2705 }
2706 return r;
2707
2708 }
2709
2710 long kvm_arch_dev_ioctl(struct file *filp,
2711 unsigned int ioctl, unsigned long arg)
2712 {
2713 void __user *argp = (void __user *)arg;
2714 long r;
2715
2716 switch (ioctl) {
2717 case KVM_GET_MSR_INDEX_LIST: {
2718 struct kvm_msr_list __user *user_msr_list = argp;
2719 struct kvm_msr_list msr_list;
2720 unsigned n;
2721
2722 r = -EFAULT;
2723 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2724 goto out;
2725 n = msr_list.nmsrs;
2726 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2727 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2728 goto out;
2729 r = -E2BIG;
2730 if (n < msr_list.nmsrs)
2731 goto out;
2732 r = -EFAULT;
2733 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2734 num_msrs_to_save * sizeof(u32)))
2735 goto out;
2736 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2737 &emulated_msrs,
2738 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2739 goto out;
2740 r = 0;
2741 break;
2742 }
2743 case KVM_GET_SUPPORTED_CPUID:
2744 case KVM_GET_EMULATED_CPUID: {
2745 struct kvm_cpuid2 __user *cpuid_arg = argp;
2746 struct kvm_cpuid2 cpuid;
2747
2748 r = -EFAULT;
2749 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2750 goto out;
2751
2752 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2753 ioctl);
2754 if (r)
2755 goto out;
2756
2757 r = -EFAULT;
2758 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2759 goto out;
2760 r = 0;
2761 break;
2762 }
2763 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2764 u64 mce_cap;
2765
2766 mce_cap = KVM_MCE_CAP_SUPPORTED;
2767 r = -EFAULT;
2768 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2769 goto out;
2770 r = 0;
2771 break;
2772 }
2773 default:
2774 r = -EINVAL;
2775 }
2776 out:
2777 return r;
2778 }
2779
2780 static void wbinvd_ipi(void *garbage)
2781 {
2782 wbinvd();
2783 }
2784
2785 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2786 {
2787 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2788 }
2789
2790 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2791 {
2792 /* Address WBINVD may be executed by guest */
2793 if (need_emulate_wbinvd(vcpu)) {
2794 if (kvm_x86_ops->has_wbinvd_exit())
2795 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2796 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2797 smp_call_function_single(vcpu->cpu,
2798 wbinvd_ipi, NULL, 1);
2799 }
2800
2801 kvm_x86_ops->vcpu_load(vcpu, cpu);
2802
2803 /* Apply any externally detected TSC adjustments (due to suspend) */
2804 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2805 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2806 vcpu->arch.tsc_offset_adjustment = 0;
2807 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2808 }
2809
2810 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2811 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2812 native_read_tsc() - vcpu->arch.last_host_tsc;
2813 if (tsc_delta < 0)
2814 mark_tsc_unstable("KVM discovered backwards TSC");
2815 if (check_tsc_unstable()) {
2816 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2817 vcpu->arch.last_guest_tsc);
2818 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2819 vcpu->arch.tsc_catchup = 1;
2820 }
2821 /*
2822 * On a host with synchronized TSC, there is no need to update
2823 * kvmclock on vcpu->cpu migration
2824 */
2825 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2826 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2827 if (vcpu->cpu != cpu)
2828 kvm_migrate_timers(vcpu);
2829 vcpu->cpu = cpu;
2830 }
2831
2832 accumulate_steal_time(vcpu);
2833 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2834 }
2835
2836 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2837 {
2838 kvm_x86_ops->vcpu_put(vcpu);
2839 kvm_put_guest_fpu(vcpu);
2840 vcpu->arch.last_host_tsc = native_read_tsc();
2841 }
2842
2843 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2844 struct kvm_lapic_state *s)
2845 {
2846 kvm_x86_ops->sync_pir_to_irr(vcpu);
2847 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2848
2849 return 0;
2850 }
2851
2852 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2853 struct kvm_lapic_state *s)
2854 {
2855 kvm_apic_post_state_restore(vcpu, s);
2856 update_cr8_intercept(vcpu);
2857
2858 return 0;
2859 }
2860
2861 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2862 struct kvm_interrupt *irq)
2863 {
2864 if (irq->irq >= KVM_NR_INTERRUPTS)
2865 return -EINVAL;
2866 if (irqchip_in_kernel(vcpu->kvm))
2867 return -ENXIO;
2868
2869 kvm_queue_interrupt(vcpu, irq->irq, false);
2870 kvm_make_request(KVM_REQ_EVENT, vcpu);
2871
2872 return 0;
2873 }
2874
2875 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2876 {
2877 kvm_inject_nmi(vcpu);
2878
2879 return 0;
2880 }
2881
2882 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2883 struct kvm_tpr_access_ctl *tac)
2884 {
2885 if (tac->flags)
2886 return -EINVAL;
2887 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2888 return 0;
2889 }
2890
2891 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2892 u64 mcg_cap)
2893 {
2894 int r;
2895 unsigned bank_num = mcg_cap & 0xff, bank;
2896
2897 r = -EINVAL;
2898 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2899 goto out;
2900 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2901 goto out;
2902 r = 0;
2903 vcpu->arch.mcg_cap = mcg_cap;
2904 /* Init IA32_MCG_CTL to all 1s */
2905 if (mcg_cap & MCG_CTL_P)
2906 vcpu->arch.mcg_ctl = ~(u64)0;
2907 /* Init IA32_MCi_CTL to all 1s */
2908 for (bank = 0; bank < bank_num; bank++)
2909 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2910 out:
2911 return r;
2912 }
2913
2914 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2915 struct kvm_x86_mce *mce)
2916 {
2917 u64 mcg_cap = vcpu->arch.mcg_cap;
2918 unsigned bank_num = mcg_cap & 0xff;
2919 u64 *banks = vcpu->arch.mce_banks;
2920
2921 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2922 return -EINVAL;
2923 /*
2924 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2925 * reporting is disabled
2926 */
2927 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2928 vcpu->arch.mcg_ctl != ~(u64)0)
2929 return 0;
2930 banks += 4 * mce->bank;
2931 /*
2932 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2933 * reporting is disabled for the bank
2934 */
2935 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2936 return 0;
2937 if (mce->status & MCI_STATUS_UC) {
2938 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2939 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2940 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2941 return 0;
2942 }
2943 if (banks[1] & MCI_STATUS_VAL)
2944 mce->status |= MCI_STATUS_OVER;
2945 banks[2] = mce->addr;
2946 banks[3] = mce->misc;
2947 vcpu->arch.mcg_status = mce->mcg_status;
2948 banks[1] = mce->status;
2949 kvm_queue_exception(vcpu, MC_VECTOR);
2950 } else if (!(banks[1] & MCI_STATUS_VAL)
2951 || !(banks[1] & MCI_STATUS_UC)) {
2952 if (banks[1] & MCI_STATUS_VAL)
2953 mce->status |= MCI_STATUS_OVER;
2954 banks[2] = mce->addr;
2955 banks[3] = mce->misc;
2956 banks[1] = mce->status;
2957 } else
2958 banks[1] |= MCI_STATUS_OVER;
2959 return 0;
2960 }
2961
2962 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2963 struct kvm_vcpu_events *events)
2964 {
2965 process_nmi(vcpu);
2966 events->exception.injected =
2967 vcpu->arch.exception.pending &&
2968 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2969 events->exception.nr = vcpu->arch.exception.nr;
2970 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2971 events->exception.pad = 0;
2972 events->exception.error_code = vcpu->arch.exception.error_code;
2973
2974 events->interrupt.injected =
2975 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2976 events->interrupt.nr = vcpu->arch.interrupt.nr;
2977 events->interrupt.soft = 0;
2978 events->interrupt.shadow =
2979 kvm_x86_ops->get_interrupt_shadow(vcpu,
2980 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2981
2982 events->nmi.injected = vcpu->arch.nmi_injected;
2983 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2984 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2985 events->nmi.pad = 0;
2986
2987 events->sipi_vector = 0; /* never valid when reporting to user space */
2988
2989 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2990 | KVM_VCPUEVENT_VALID_SHADOW);
2991 memset(&events->reserved, 0, sizeof(events->reserved));
2992 }
2993
2994 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2995 struct kvm_vcpu_events *events)
2996 {
2997 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2998 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2999 | KVM_VCPUEVENT_VALID_SHADOW))
3000 return -EINVAL;
3001
3002 process_nmi(vcpu);
3003 vcpu->arch.exception.pending = events->exception.injected;
3004 vcpu->arch.exception.nr = events->exception.nr;
3005 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3006 vcpu->arch.exception.error_code = events->exception.error_code;
3007
3008 vcpu->arch.interrupt.pending = events->interrupt.injected;
3009 vcpu->arch.interrupt.nr = events->interrupt.nr;
3010 vcpu->arch.interrupt.soft = events->interrupt.soft;
3011 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3012 kvm_x86_ops->set_interrupt_shadow(vcpu,
3013 events->interrupt.shadow);
3014
3015 vcpu->arch.nmi_injected = events->nmi.injected;
3016 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3017 vcpu->arch.nmi_pending = events->nmi.pending;
3018 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3019
3020 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3021 kvm_vcpu_has_lapic(vcpu))
3022 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3023
3024 kvm_make_request(KVM_REQ_EVENT, vcpu);
3025
3026 return 0;
3027 }
3028
3029 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3030 struct kvm_debugregs *dbgregs)
3031 {
3032 unsigned long val;
3033
3034 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3035 _kvm_get_dr(vcpu, 6, &val);
3036 dbgregs->dr6 = val;
3037 dbgregs->dr7 = vcpu->arch.dr7;
3038 dbgregs->flags = 0;
3039 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3040 }
3041
3042 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3043 struct kvm_debugregs *dbgregs)
3044 {
3045 if (dbgregs->flags)
3046 return -EINVAL;
3047
3048 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3049 vcpu->arch.dr6 = dbgregs->dr6;
3050 kvm_update_dr6(vcpu);
3051 vcpu->arch.dr7 = dbgregs->dr7;
3052 kvm_update_dr7(vcpu);
3053
3054 return 0;
3055 }
3056
3057 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3058 struct kvm_xsave *guest_xsave)
3059 {
3060 if (cpu_has_xsave) {
3061 memcpy(guest_xsave->region,
3062 &vcpu->arch.guest_fpu.state->xsave,
3063 vcpu->arch.guest_xstate_size);
3064 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3065 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3066 } else {
3067 memcpy(guest_xsave->region,
3068 &vcpu->arch.guest_fpu.state->fxsave,
3069 sizeof(struct i387_fxsave_struct));
3070 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3071 XSTATE_FPSSE;
3072 }
3073 }
3074
3075 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3076 struct kvm_xsave *guest_xsave)
3077 {
3078 u64 xstate_bv =
3079 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3080
3081 if (cpu_has_xsave) {
3082 /*
3083 * Here we allow setting states that are not present in
3084 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3085 * with old userspace.
3086 */
3087 if (xstate_bv & ~kvm_supported_xcr0())
3088 return -EINVAL;
3089 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3090 guest_xsave->region, vcpu->arch.guest_xstate_size);
3091 } else {
3092 if (xstate_bv & ~XSTATE_FPSSE)
3093 return -EINVAL;
3094 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3095 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3096 }
3097 return 0;
3098 }
3099
3100 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3101 struct kvm_xcrs *guest_xcrs)
3102 {
3103 if (!cpu_has_xsave) {
3104 guest_xcrs->nr_xcrs = 0;
3105 return;
3106 }
3107
3108 guest_xcrs->nr_xcrs = 1;
3109 guest_xcrs->flags = 0;
3110 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3111 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3112 }
3113
3114 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3115 struct kvm_xcrs *guest_xcrs)
3116 {
3117 int i, r = 0;
3118
3119 if (!cpu_has_xsave)
3120 return -EINVAL;
3121
3122 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3123 return -EINVAL;
3124
3125 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3126 /* Only support XCR0 currently */
3127 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3128 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3129 guest_xcrs->xcrs[i].value);
3130 break;
3131 }
3132 if (r)
3133 r = -EINVAL;
3134 return r;
3135 }
3136
3137 /*
3138 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3139 * stopped by the hypervisor. This function will be called from the host only.
3140 * EINVAL is returned when the host attempts to set the flag for a guest that
3141 * does not support pv clocks.
3142 */
3143 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3144 {
3145 if (!vcpu->arch.pv_time_enabled)
3146 return -EINVAL;
3147 vcpu->arch.pvclock_set_guest_stopped_request = true;
3148 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3149 return 0;
3150 }
3151
3152 long kvm_arch_vcpu_ioctl(struct file *filp,
3153 unsigned int ioctl, unsigned long arg)
3154 {
3155 struct kvm_vcpu *vcpu = filp->private_data;
3156 void __user *argp = (void __user *)arg;
3157 int r;
3158 union {
3159 struct kvm_lapic_state *lapic;
3160 struct kvm_xsave *xsave;
3161 struct kvm_xcrs *xcrs;
3162 void *buffer;
3163 } u;
3164
3165 u.buffer = NULL;
3166 switch (ioctl) {
3167 case KVM_GET_LAPIC: {
3168 r = -EINVAL;
3169 if (!vcpu->arch.apic)
3170 goto out;
3171 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3172
3173 r = -ENOMEM;
3174 if (!u.lapic)
3175 goto out;
3176 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3177 if (r)
3178 goto out;
3179 r = -EFAULT;
3180 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3181 goto out;
3182 r = 0;
3183 break;
3184 }
3185 case KVM_SET_LAPIC: {
3186 r = -EINVAL;
3187 if (!vcpu->arch.apic)
3188 goto out;
3189 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3190 if (IS_ERR(u.lapic))
3191 return PTR_ERR(u.lapic);
3192
3193 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3194 break;
3195 }
3196 case KVM_INTERRUPT: {
3197 struct kvm_interrupt irq;
3198
3199 r = -EFAULT;
3200 if (copy_from_user(&irq, argp, sizeof irq))
3201 goto out;
3202 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3203 break;
3204 }
3205 case KVM_NMI: {
3206 r = kvm_vcpu_ioctl_nmi(vcpu);
3207 break;
3208 }
3209 case KVM_SET_CPUID: {
3210 struct kvm_cpuid __user *cpuid_arg = argp;
3211 struct kvm_cpuid cpuid;
3212
3213 r = -EFAULT;
3214 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3215 goto out;
3216 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3217 break;
3218 }
3219 case KVM_SET_CPUID2: {
3220 struct kvm_cpuid2 __user *cpuid_arg = argp;
3221 struct kvm_cpuid2 cpuid;
3222
3223 r = -EFAULT;
3224 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3225 goto out;
3226 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3227 cpuid_arg->entries);
3228 break;
3229 }
3230 case KVM_GET_CPUID2: {
3231 struct kvm_cpuid2 __user *cpuid_arg = argp;
3232 struct kvm_cpuid2 cpuid;
3233
3234 r = -EFAULT;
3235 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3236 goto out;
3237 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3238 cpuid_arg->entries);
3239 if (r)
3240 goto out;
3241 r = -EFAULT;
3242 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3243 goto out;
3244 r = 0;
3245 break;
3246 }
3247 case KVM_GET_MSRS:
3248 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3249 break;
3250 case KVM_SET_MSRS:
3251 r = msr_io(vcpu, argp, do_set_msr, 0);
3252 break;
3253 case KVM_TPR_ACCESS_REPORTING: {
3254 struct kvm_tpr_access_ctl tac;
3255
3256 r = -EFAULT;
3257 if (copy_from_user(&tac, argp, sizeof tac))
3258 goto out;
3259 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3260 if (r)
3261 goto out;
3262 r = -EFAULT;
3263 if (copy_to_user(argp, &tac, sizeof tac))
3264 goto out;
3265 r = 0;
3266 break;
3267 };
3268 case KVM_SET_VAPIC_ADDR: {
3269 struct kvm_vapic_addr va;
3270
3271 r = -EINVAL;
3272 if (!irqchip_in_kernel(vcpu->kvm))
3273 goto out;
3274 r = -EFAULT;
3275 if (copy_from_user(&va, argp, sizeof va))
3276 goto out;
3277 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3278 break;
3279 }
3280 case KVM_X86_SETUP_MCE: {
3281 u64 mcg_cap;
3282
3283 r = -EFAULT;
3284 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3285 goto out;
3286 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3287 break;
3288 }
3289 case KVM_X86_SET_MCE: {
3290 struct kvm_x86_mce mce;
3291
3292 r = -EFAULT;
3293 if (copy_from_user(&mce, argp, sizeof mce))
3294 goto out;
3295 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3296 break;
3297 }
3298 case KVM_GET_VCPU_EVENTS: {
3299 struct kvm_vcpu_events events;
3300
3301 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3302
3303 r = -EFAULT;
3304 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3305 break;
3306 r = 0;
3307 break;
3308 }
3309 case KVM_SET_VCPU_EVENTS: {
3310 struct kvm_vcpu_events events;
3311
3312 r = -EFAULT;
3313 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3314 break;
3315
3316 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3317 break;
3318 }
3319 case KVM_GET_DEBUGREGS: {
3320 struct kvm_debugregs dbgregs;
3321
3322 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3323
3324 r = -EFAULT;
3325 if (copy_to_user(argp, &dbgregs,
3326 sizeof(struct kvm_debugregs)))
3327 break;
3328 r = 0;
3329 break;
3330 }
3331 case KVM_SET_DEBUGREGS: {
3332 struct kvm_debugregs dbgregs;
3333
3334 r = -EFAULT;
3335 if (copy_from_user(&dbgregs, argp,
3336 sizeof(struct kvm_debugregs)))
3337 break;
3338
3339 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3340 break;
3341 }
3342 case KVM_GET_XSAVE: {
3343 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3344 r = -ENOMEM;
3345 if (!u.xsave)
3346 break;
3347
3348 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3349
3350 r = -EFAULT;
3351 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3352 break;
3353 r = 0;
3354 break;
3355 }
3356 case KVM_SET_XSAVE: {
3357 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3358 if (IS_ERR(u.xsave))
3359 return PTR_ERR(u.xsave);
3360
3361 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3362 break;
3363 }
3364 case KVM_GET_XCRS: {
3365 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3366 r = -ENOMEM;
3367 if (!u.xcrs)
3368 break;
3369
3370 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3371
3372 r = -EFAULT;
3373 if (copy_to_user(argp, u.xcrs,
3374 sizeof(struct kvm_xcrs)))
3375 break;
3376 r = 0;
3377 break;
3378 }
3379 case KVM_SET_XCRS: {
3380 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3381 if (IS_ERR(u.xcrs))
3382 return PTR_ERR(u.xcrs);
3383
3384 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3385 break;
3386 }
3387 case KVM_SET_TSC_KHZ: {
3388 u32 user_tsc_khz;
3389
3390 r = -EINVAL;
3391 user_tsc_khz = (u32)arg;
3392
3393 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3394 goto out;
3395
3396 if (user_tsc_khz == 0)
3397 user_tsc_khz = tsc_khz;
3398
3399 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3400
3401 r = 0;
3402 goto out;
3403 }
3404 case KVM_GET_TSC_KHZ: {
3405 r = vcpu->arch.virtual_tsc_khz;
3406 goto out;
3407 }
3408 case KVM_KVMCLOCK_CTRL: {
3409 r = kvm_set_guest_paused(vcpu);
3410 goto out;
3411 }
3412 default:
3413 r = -EINVAL;
3414 }
3415 out:
3416 kfree(u.buffer);
3417 return r;
3418 }
3419
3420 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3421 {
3422 return VM_FAULT_SIGBUS;
3423 }
3424
3425 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3426 {
3427 int ret;
3428
3429 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3430 return -EINVAL;
3431 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3432 return ret;
3433 }
3434
3435 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3436 u64 ident_addr)
3437 {
3438 kvm->arch.ept_identity_map_addr = ident_addr;
3439 return 0;
3440 }
3441
3442 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3443 u32 kvm_nr_mmu_pages)
3444 {
3445 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3446 return -EINVAL;
3447
3448 mutex_lock(&kvm->slots_lock);
3449
3450 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3451 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3452
3453 mutex_unlock(&kvm->slots_lock);
3454 return 0;
3455 }
3456
3457 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3458 {
3459 return kvm->arch.n_max_mmu_pages;
3460 }
3461
3462 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3463 {
3464 int r;
3465
3466 r = 0;
3467 switch (chip->chip_id) {
3468 case KVM_IRQCHIP_PIC_MASTER:
3469 memcpy(&chip->chip.pic,
3470 &pic_irqchip(kvm)->pics[0],
3471 sizeof(struct kvm_pic_state));
3472 break;
3473 case KVM_IRQCHIP_PIC_SLAVE:
3474 memcpy(&chip->chip.pic,
3475 &pic_irqchip(kvm)->pics[1],
3476 sizeof(struct kvm_pic_state));
3477 break;
3478 case KVM_IRQCHIP_IOAPIC:
3479 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3480 break;
3481 default:
3482 r = -EINVAL;
3483 break;
3484 }
3485 return r;
3486 }
3487
3488 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3489 {
3490 int r;
3491
3492 r = 0;
3493 switch (chip->chip_id) {
3494 case KVM_IRQCHIP_PIC_MASTER:
3495 spin_lock(&pic_irqchip(kvm)->lock);
3496 memcpy(&pic_irqchip(kvm)->pics[0],
3497 &chip->chip.pic,
3498 sizeof(struct kvm_pic_state));
3499 spin_unlock(&pic_irqchip(kvm)->lock);
3500 break;
3501 case KVM_IRQCHIP_PIC_SLAVE:
3502 spin_lock(&pic_irqchip(kvm)->lock);
3503 memcpy(&pic_irqchip(kvm)->pics[1],
3504 &chip->chip.pic,
3505 sizeof(struct kvm_pic_state));
3506 spin_unlock(&pic_irqchip(kvm)->lock);
3507 break;
3508 case KVM_IRQCHIP_IOAPIC:
3509 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3510 break;
3511 default:
3512 r = -EINVAL;
3513 break;
3514 }
3515 kvm_pic_update_irq(pic_irqchip(kvm));
3516 return r;
3517 }
3518
3519 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3520 {
3521 int r = 0;
3522
3523 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3524 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3525 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3526 return r;
3527 }
3528
3529 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3530 {
3531 int r = 0;
3532
3533 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3534 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3535 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3536 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3537 return r;
3538 }
3539
3540 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3541 {
3542 int r = 0;
3543
3544 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3545 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3546 sizeof(ps->channels));
3547 ps->flags = kvm->arch.vpit->pit_state.flags;
3548 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3549 memset(&ps->reserved, 0, sizeof(ps->reserved));
3550 return r;
3551 }
3552
3553 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3554 {
3555 int r = 0, start = 0;
3556 u32 prev_legacy, cur_legacy;
3557 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3558 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3559 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3560 if (!prev_legacy && cur_legacy)
3561 start = 1;
3562 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3563 sizeof(kvm->arch.vpit->pit_state.channels));
3564 kvm->arch.vpit->pit_state.flags = ps->flags;
3565 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3566 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3567 return r;
3568 }
3569
3570 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3571 struct kvm_reinject_control *control)
3572 {
3573 if (!kvm->arch.vpit)
3574 return -ENXIO;
3575 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3576 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3577 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3578 return 0;
3579 }
3580
3581 /**
3582 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3583 * @kvm: kvm instance
3584 * @log: slot id and address to which we copy the log
3585 *
3586 * We need to keep it in mind that VCPU threads can write to the bitmap
3587 * concurrently. So, to avoid losing data, we keep the following order for
3588 * each bit:
3589 *
3590 * 1. Take a snapshot of the bit and clear it if needed.
3591 * 2. Write protect the corresponding page.
3592 * 3. Flush TLB's if needed.
3593 * 4. Copy the snapshot to the userspace.
3594 *
3595 * Between 2 and 3, the guest may write to the page using the remaining TLB
3596 * entry. This is not a problem because the page will be reported dirty at
3597 * step 4 using the snapshot taken before and step 3 ensures that successive
3598 * writes will be logged for the next call.
3599 */
3600 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3601 {
3602 int r;
3603 struct kvm_memory_slot *memslot;
3604 unsigned long n, i;
3605 unsigned long *dirty_bitmap;
3606 unsigned long *dirty_bitmap_buffer;
3607 bool is_dirty = false;
3608
3609 mutex_lock(&kvm->slots_lock);
3610
3611 r = -EINVAL;
3612 if (log->slot >= KVM_USER_MEM_SLOTS)
3613 goto out;
3614
3615 memslot = id_to_memslot(kvm->memslots, log->slot);
3616
3617 dirty_bitmap = memslot->dirty_bitmap;
3618 r = -ENOENT;
3619 if (!dirty_bitmap)
3620 goto out;
3621
3622 n = kvm_dirty_bitmap_bytes(memslot);
3623
3624 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3625 memset(dirty_bitmap_buffer, 0, n);
3626
3627 spin_lock(&kvm->mmu_lock);
3628
3629 for (i = 0; i < n / sizeof(long); i++) {
3630 unsigned long mask;
3631 gfn_t offset;
3632
3633 if (!dirty_bitmap[i])
3634 continue;
3635
3636 is_dirty = true;
3637
3638 mask = xchg(&dirty_bitmap[i], 0);
3639 dirty_bitmap_buffer[i] = mask;
3640
3641 offset = i * BITS_PER_LONG;
3642 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3643 }
3644 if (is_dirty)
3645 kvm_flush_remote_tlbs(kvm);
3646
3647 spin_unlock(&kvm->mmu_lock);
3648
3649 r = -EFAULT;
3650 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3651 goto out;
3652
3653 r = 0;
3654 out:
3655 mutex_unlock(&kvm->slots_lock);
3656 return r;
3657 }
3658
3659 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3660 bool line_status)
3661 {
3662 if (!irqchip_in_kernel(kvm))
3663 return -ENXIO;
3664
3665 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3666 irq_event->irq, irq_event->level,
3667 line_status);
3668 return 0;
3669 }
3670
3671 long kvm_arch_vm_ioctl(struct file *filp,
3672 unsigned int ioctl, unsigned long arg)
3673 {
3674 struct kvm *kvm = filp->private_data;
3675 void __user *argp = (void __user *)arg;
3676 int r = -ENOTTY;
3677 /*
3678 * This union makes it completely explicit to gcc-3.x
3679 * that these two variables' stack usage should be
3680 * combined, not added together.
3681 */
3682 union {
3683 struct kvm_pit_state ps;
3684 struct kvm_pit_state2 ps2;
3685 struct kvm_pit_config pit_config;
3686 } u;
3687
3688 switch (ioctl) {
3689 case KVM_SET_TSS_ADDR:
3690 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3691 break;
3692 case KVM_SET_IDENTITY_MAP_ADDR: {
3693 u64 ident_addr;
3694
3695 r = -EFAULT;
3696 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3697 goto out;
3698 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3699 break;
3700 }
3701 case KVM_SET_NR_MMU_PAGES:
3702 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3703 break;
3704 case KVM_GET_NR_MMU_PAGES:
3705 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3706 break;
3707 case KVM_CREATE_IRQCHIP: {
3708 struct kvm_pic *vpic;
3709
3710 mutex_lock(&kvm->lock);
3711 r = -EEXIST;
3712 if (kvm->arch.vpic)
3713 goto create_irqchip_unlock;
3714 r = -EINVAL;
3715 if (atomic_read(&kvm->online_vcpus))
3716 goto create_irqchip_unlock;
3717 r = -ENOMEM;
3718 vpic = kvm_create_pic(kvm);
3719 if (vpic) {
3720 r = kvm_ioapic_init(kvm);
3721 if (r) {
3722 mutex_lock(&kvm->slots_lock);
3723 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3724 &vpic->dev_master);
3725 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3726 &vpic->dev_slave);
3727 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3728 &vpic->dev_eclr);
3729 mutex_unlock(&kvm->slots_lock);
3730 kfree(vpic);
3731 goto create_irqchip_unlock;
3732 }
3733 } else
3734 goto create_irqchip_unlock;
3735 smp_wmb();
3736 kvm->arch.vpic = vpic;
3737 smp_wmb();
3738 r = kvm_setup_default_irq_routing(kvm);
3739 if (r) {
3740 mutex_lock(&kvm->slots_lock);
3741 mutex_lock(&kvm->irq_lock);
3742 kvm_ioapic_destroy(kvm);
3743 kvm_destroy_pic(kvm);
3744 mutex_unlock(&kvm->irq_lock);
3745 mutex_unlock(&kvm->slots_lock);
3746 }
3747 create_irqchip_unlock:
3748 mutex_unlock(&kvm->lock);
3749 break;
3750 }
3751 case KVM_CREATE_PIT:
3752 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3753 goto create_pit;
3754 case KVM_CREATE_PIT2:
3755 r = -EFAULT;
3756 if (copy_from_user(&u.pit_config, argp,
3757 sizeof(struct kvm_pit_config)))
3758 goto out;
3759 create_pit:
3760 mutex_lock(&kvm->slots_lock);
3761 r = -EEXIST;
3762 if (kvm->arch.vpit)
3763 goto create_pit_unlock;
3764 r = -ENOMEM;
3765 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3766 if (kvm->arch.vpit)
3767 r = 0;
3768 create_pit_unlock:
3769 mutex_unlock(&kvm->slots_lock);
3770 break;
3771 case KVM_GET_IRQCHIP: {
3772 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3773 struct kvm_irqchip *chip;
3774
3775 chip = memdup_user(argp, sizeof(*chip));
3776 if (IS_ERR(chip)) {
3777 r = PTR_ERR(chip);
3778 goto out;
3779 }
3780
3781 r = -ENXIO;
3782 if (!irqchip_in_kernel(kvm))
3783 goto get_irqchip_out;
3784 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3785 if (r)
3786 goto get_irqchip_out;
3787 r = -EFAULT;
3788 if (copy_to_user(argp, chip, sizeof *chip))
3789 goto get_irqchip_out;
3790 r = 0;
3791 get_irqchip_out:
3792 kfree(chip);
3793 break;
3794 }
3795 case KVM_SET_IRQCHIP: {
3796 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3797 struct kvm_irqchip *chip;
3798
3799 chip = memdup_user(argp, sizeof(*chip));
3800 if (IS_ERR(chip)) {
3801 r = PTR_ERR(chip);
3802 goto out;
3803 }
3804
3805 r = -ENXIO;
3806 if (!irqchip_in_kernel(kvm))
3807 goto set_irqchip_out;
3808 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3809 if (r)
3810 goto set_irqchip_out;
3811 r = 0;
3812 set_irqchip_out:
3813 kfree(chip);
3814 break;
3815 }
3816 case KVM_GET_PIT: {
3817 r = -EFAULT;
3818 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3819 goto out;
3820 r = -ENXIO;
3821 if (!kvm->arch.vpit)
3822 goto out;
3823 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3824 if (r)
3825 goto out;
3826 r = -EFAULT;
3827 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3828 goto out;
3829 r = 0;
3830 break;
3831 }
3832 case KVM_SET_PIT: {
3833 r = -EFAULT;
3834 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3835 goto out;
3836 r = -ENXIO;
3837 if (!kvm->arch.vpit)
3838 goto out;
3839 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3840 break;
3841 }
3842 case KVM_GET_PIT2: {
3843 r = -ENXIO;
3844 if (!kvm->arch.vpit)
3845 goto out;
3846 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3847 if (r)
3848 goto out;
3849 r = -EFAULT;
3850 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3851 goto out;
3852 r = 0;
3853 break;
3854 }
3855 case KVM_SET_PIT2: {
3856 r = -EFAULT;
3857 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3858 goto out;
3859 r = -ENXIO;
3860 if (!kvm->arch.vpit)
3861 goto out;
3862 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3863 break;
3864 }
3865 case KVM_REINJECT_CONTROL: {
3866 struct kvm_reinject_control control;
3867 r = -EFAULT;
3868 if (copy_from_user(&control, argp, sizeof(control)))
3869 goto out;
3870 r = kvm_vm_ioctl_reinject(kvm, &control);
3871 break;
3872 }
3873 case KVM_XEN_HVM_CONFIG: {
3874 r = -EFAULT;
3875 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3876 sizeof(struct kvm_xen_hvm_config)))
3877 goto out;
3878 r = -EINVAL;
3879 if (kvm->arch.xen_hvm_config.flags)
3880 goto out;
3881 r = 0;
3882 break;
3883 }
3884 case KVM_SET_CLOCK: {
3885 struct kvm_clock_data user_ns;
3886 u64 now_ns;
3887 s64 delta;
3888
3889 r = -EFAULT;
3890 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3891 goto out;
3892
3893 r = -EINVAL;
3894 if (user_ns.flags)
3895 goto out;
3896
3897 r = 0;
3898 local_irq_disable();
3899 now_ns = get_kernel_ns();
3900 delta = user_ns.clock - now_ns;
3901 local_irq_enable();
3902 kvm->arch.kvmclock_offset = delta;
3903 kvm_gen_update_masterclock(kvm);
3904 break;
3905 }
3906 case KVM_GET_CLOCK: {
3907 struct kvm_clock_data user_ns;
3908 u64 now_ns;
3909
3910 local_irq_disable();
3911 now_ns = get_kernel_ns();
3912 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3913 local_irq_enable();
3914 user_ns.flags = 0;
3915 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3916
3917 r = -EFAULT;
3918 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3919 goto out;
3920 r = 0;
3921 break;
3922 }
3923
3924 default:
3925 ;
3926 }
3927 out:
3928 return r;
3929 }
3930
3931 static void kvm_init_msr_list(void)
3932 {
3933 u32 dummy[2];
3934 unsigned i, j;
3935
3936 /* skip the first msrs in the list. KVM-specific */
3937 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3938 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3939 continue;
3940
3941 /*
3942 * Even MSRs that are valid in the host may not be exposed
3943 * to the guests in some cases. We could work around this
3944 * in VMX with the generic MSR save/load machinery, but it
3945 * is not really worthwhile since it will really only
3946 * happen with nested virtualization.
3947 */
3948 switch (msrs_to_save[i]) {
3949 case MSR_IA32_BNDCFGS:
3950 if (!kvm_x86_ops->mpx_supported())
3951 continue;
3952 break;
3953 default:
3954 break;
3955 }
3956
3957 if (j < i)
3958 msrs_to_save[j] = msrs_to_save[i];
3959 j++;
3960 }
3961 num_msrs_to_save = j;
3962 }
3963
3964 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3965 const void *v)
3966 {
3967 int handled = 0;
3968 int n;
3969
3970 do {
3971 n = min(len, 8);
3972 if (!(vcpu->arch.apic &&
3973 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3974 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3975 break;
3976 handled += n;
3977 addr += n;
3978 len -= n;
3979 v += n;
3980 } while (len);
3981
3982 return handled;
3983 }
3984
3985 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3986 {
3987 int handled = 0;
3988 int n;
3989
3990 do {
3991 n = min(len, 8);
3992 if (!(vcpu->arch.apic &&
3993 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3994 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3995 break;
3996 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3997 handled += n;
3998 addr += n;
3999 len -= n;
4000 v += n;
4001 } while (len);
4002
4003 return handled;
4004 }
4005
4006 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4007 struct kvm_segment *var, int seg)
4008 {
4009 kvm_x86_ops->set_segment(vcpu, var, seg);
4010 }
4011
4012 void kvm_get_segment(struct kvm_vcpu *vcpu,
4013 struct kvm_segment *var, int seg)
4014 {
4015 kvm_x86_ops->get_segment(vcpu, var, seg);
4016 }
4017
4018 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
4019 {
4020 gpa_t t_gpa;
4021 struct x86_exception exception;
4022
4023 BUG_ON(!mmu_is_nested(vcpu));
4024
4025 /* NPT walks are always user-walks */
4026 access |= PFERR_USER_MASK;
4027 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
4028
4029 return t_gpa;
4030 }
4031
4032 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4033 struct x86_exception *exception)
4034 {
4035 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4036 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4037 }
4038
4039 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4040 struct x86_exception *exception)
4041 {
4042 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4043 access |= PFERR_FETCH_MASK;
4044 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4045 }
4046
4047 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4048 struct x86_exception *exception)
4049 {
4050 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4051 access |= PFERR_WRITE_MASK;
4052 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4053 }
4054
4055 /* uses this to access any guest's mapped memory without checking CPL */
4056 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4057 struct x86_exception *exception)
4058 {
4059 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4060 }
4061
4062 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4063 struct kvm_vcpu *vcpu, u32 access,
4064 struct x86_exception *exception)
4065 {
4066 void *data = val;
4067 int r = X86EMUL_CONTINUE;
4068
4069 while (bytes) {
4070 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4071 exception);
4072 unsigned offset = addr & (PAGE_SIZE-1);
4073 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4074 int ret;
4075
4076 if (gpa == UNMAPPED_GVA)
4077 return X86EMUL_PROPAGATE_FAULT;
4078 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4079 if (ret < 0) {
4080 r = X86EMUL_IO_NEEDED;
4081 goto out;
4082 }
4083
4084 bytes -= toread;
4085 data += toread;
4086 addr += toread;
4087 }
4088 out:
4089 return r;
4090 }
4091
4092 /* used for instruction fetching */
4093 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4094 gva_t addr, void *val, unsigned int bytes,
4095 struct x86_exception *exception)
4096 {
4097 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4098 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4099
4100 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4101 access | PFERR_FETCH_MASK,
4102 exception);
4103 }
4104
4105 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4106 gva_t addr, void *val, unsigned int bytes,
4107 struct x86_exception *exception)
4108 {
4109 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4110 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4111
4112 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4113 exception);
4114 }
4115 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4116
4117 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4118 gva_t addr, void *val, unsigned int bytes,
4119 struct x86_exception *exception)
4120 {
4121 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4122 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4123 }
4124
4125 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4126 gva_t addr, void *val,
4127 unsigned int bytes,
4128 struct x86_exception *exception)
4129 {
4130 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4131 void *data = val;
4132 int r = X86EMUL_CONTINUE;
4133
4134 while (bytes) {
4135 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4136 PFERR_WRITE_MASK,
4137 exception);
4138 unsigned offset = addr & (PAGE_SIZE-1);
4139 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4140 int ret;
4141
4142 if (gpa == UNMAPPED_GVA)
4143 return X86EMUL_PROPAGATE_FAULT;
4144 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4145 if (ret < 0) {
4146 r = X86EMUL_IO_NEEDED;
4147 goto out;
4148 }
4149
4150 bytes -= towrite;
4151 data += towrite;
4152 addr += towrite;
4153 }
4154 out:
4155 return r;
4156 }
4157 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4158
4159 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4160 gpa_t *gpa, struct x86_exception *exception,
4161 bool write)
4162 {
4163 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4164 | (write ? PFERR_WRITE_MASK : 0);
4165
4166 if (vcpu_match_mmio_gva(vcpu, gva)
4167 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4168 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4169 (gva & (PAGE_SIZE - 1));
4170 trace_vcpu_match_mmio(gva, *gpa, write, false);
4171 return 1;
4172 }
4173
4174 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4175
4176 if (*gpa == UNMAPPED_GVA)
4177 return -1;
4178
4179 /* For APIC access vmexit */
4180 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4181 return 1;
4182
4183 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4184 trace_vcpu_match_mmio(gva, *gpa, write, true);
4185 return 1;
4186 }
4187
4188 return 0;
4189 }
4190
4191 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4192 const void *val, int bytes)
4193 {
4194 int ret;
4195
4196 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4197 if (ret < 0)
4198 return 0;
4199 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4200 return 1;
4201 }
4202
4203 struct read_write_emulator_ops {
4204 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4205 int bytes);
4206 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4207 void *val, int bytes);
4208 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4209 int bytes, void *val);
4210 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4211 void *val, int bytes);
4212 bool write;
4213 };
4214
4215 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4216 {
4217 if (vcpu->mmio_read_completed) {
4218 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4219 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4220 vcpu->mmio_read_completed = 0;
4221 return 1;
4222 }
4223
4224 return 0;
4225 }
4226
4227 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4228 void *val, int bytes)
4229 {
4230 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4231 }
4232
4233 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4234 void *val, int bytes)
4235 {
4236 return emulator_write_phys(vcpu, gpa, val, bytes);
4237 }
4238
4239 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4240 {
4241 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4242 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4243 }
4244
4245 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4246 void *val, int bytes)
4247 {
4248 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4249 return X86EMUL_IO_NEEDED;
4250 }
4251
4252 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4253 void *val, int bytes)
4254 {
4255 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4256
4257 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4258 return X86EMUL_CONTINUE;
4259 }
4260
4261 static const struct read_write_emulator_ops read_emultor = {
4262 .read_write_prepare = read_prepare,
4263 .read_write_emulate = read_emulate,
4264 .read_write_mmio = vcpu_mmio_read,
4265 .read_write_exit_mmio = read_exit_mmio,
4266 };
4267
4268 static const struct read_write_emulator_ops write_emultor = {
4269 .read_write_emulate = write_emulate,
4270 .read_write_mmio = write_mmio,
4271 .read_write_exit_mmio = write_exit_mmio,
4272 .write = true,
4273 };
4274
4275 static int emulator_read_write_onepage(unsigned long addr, void *val,
4276 unsigned int bytes,
4277 struct x86_exception *exception,
4278 struct kvm_vcpu *vcpu,
4279 const struct read_write_emulator_ops *ops)
4280 {
4281 gpa_t gpa;
4282 int handled, ret;
4283 bool write = ops->write;
4284 struct kvm_mmio_fragment *frag;
4285
4286 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4287
4288 if (ret < 0)
4289 return X86EMUL_PROPAGATE_FAULT;
4290
4291 /* For APIC access vmexit */
4292 if (ret)
4293 goto mmio;
4294
4295 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4296 return X86EMUL_CONTINUE;
4297
4298 mmio:
4299 /*
4300 * Is this MMIO handled locally?
4301 */
4302 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4303 if (handled == bytes)
4304 return X86EMUL_CONTINUE;
4305
4306 gpa += handled;
4307 bytes -= handled;
4308 val += handled;
4309
4310 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4311 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4312 frag->gpa = gpa;
4313 frag->data = val;
4314 frag->len = bytes;
4315 return X86EMUL_CONTINUE;
4316 }
4317
4318 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4319 void *val, unsigned int bytes,
4320 struct x86_exception *exception,
4321 const struct read_write_emulator_ops *ops)
4322 {
4323 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4324 gpa_t gpa;
4325 int rc;
4326
4327 if (ops->read_write_prepare &&
4328 ops->read_write_prepare(vcpu, val, bytes))
4329 return X86EMUL_CONTINUE;
4330
4331 vcpu->mmio_nr_fragments = 0;
4332
4333 /* Crossing a page boundary? */
4334 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4335 int now;
4336
4337 now = -addr & ~PAGE_MASK;
4338 rc = emulator_read_write_onepage(addr, val, now, exception,
4339 vcpu, ops);
4340
4341 if (rc != X86EMUL_CONTINUE)
4342 return rc;
4343 addr += now;
4344 val += now;
4345 bytes -= now;
4346 }
4347
4348 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4349 vcpu, ops);
4350 if (rc != X86EMUL_CONTINUE)
4351 return rc;
4352
4353 if (!vcpu->mmio_nr_fragments)
4354 return rc;
4355
4356 gpa = vcpu->mmio_fragments[0].gpa;
4357
4358 vcpu->mmio_needed = 1;
4359 vcpu->mmio_cur_fragment = 0;
4360
4361 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4362 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4363 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4364 vcpu->run->mmio.phys_addr = gpa;
4365
4366 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4367 }
4368
4369 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4370 unsigned long addr,
4371 void *val,
4372 unsigned int bytes,
4373 struct x86_exception *exception)
4374 {
4375 return emulator_read_write(ctxt, addr, val, bytes,
4376 exception, &read_emultor);
4377 }
4378
4379 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4380 unsigned long addr,
4381 const void *val,
4382 unsigned int bytes,
4383 struct x86_exception *exception)
4384 {
4385 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4386 exception, &write_emultor);
4387 }
4388
4389 #define CMPXCHG_TYPE(t, ptr, old, new) \
4390 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4391
4392 #ifdef CONFIG_X86_64
4393 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4394 #else
4395 # define CMPXCHG64(ptr, old, new) \
4396 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4397 #endif
4398
4399 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4400 unsigned long addr,
4401 const void *old,
4402 const void *new,
4403 unsigned int bytes,
4404 struct x86_exception *exception)
4405 {
4406 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4407 gpa_t gpa;
4408 struct page *page;
4409 char *kaddr;
4410 bool exchanged;
4411
4412 /* guests cmpxchg8b have to be emulated atomically */
4413 if (bytes > 8 || (bytes & (bytes - 1)))
4414 goto emul_write;
4415
4416 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4417
4418 if (gpa == UNMAPPED_GVA ||
4419 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4420 goto emul_write;
4421
4422 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4423 goto emul_write;
4424
4425 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4426 if (is_error_page(page))
4427 goto emul_write;
4428
4429 kaddr = kmap_atomic(page);
4430 kaddr += offset_in_page(gpa);
4431 switch (bytes) {
4432 case 1:
4433 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4434 break;
4435 case 2:
4436 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4437 break;
4438 case 4:
4439 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4440 break;
4441 case 8:
4442 exchanged = CMPXCHG64(kaddr, old, new);
4443 break;
4444 default:
4445 BUG();
4446 }
4447 kunmap_atomic(kaddr);
4448 kvm_release_page_dirty(page);
4449
4450 if (!exchanged)
4451 return X86EMUL_CMPXCHG_FAILED;
4452
4453 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4454 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4455
4456 return X86EMUL_CONTINUE;
4457
4458 emul_write:
4459 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4460
4461 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4462 }
4463
4464 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4465 {
4466 /* TODO: String I/O for in kernel device */
4467 int r;
4468
4469 if (vcpu->arch.pio.in)
4470 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4471 vcpu->arch.pio.size, pd);
4472 else
4473 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4474 vcpu->arch.pio.port, vcpu->arch.pio.size,
4475 pd);
4476 return r;
4477 }
4478
4479 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4480 unsigned short port, void *val,
4481 unsigned int count, bool in)
4482 {
4483 trace_kvm_pio(!in, port, size, count);
4484
4485 vcpu->arch.pio.port = port;
4486 vcpu->arch.pio.in = in;
4487 vcpu->arch.pio.count = count;
4488 vcpu->arch.pio.size = size;
4489
4490 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4491 vcpu->arch.pio.count = 0;
4492 return 1;
4493 }
4494
4495 vcpu->run->exit_reason = KVM_EXIT_IO;
4496 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4497 vcpu->run->io.size = size;
4498 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4499 vcpu->run->io.count = count;
4500 vcpu->run->io.port = port;
4501
4502 return 0;
4503 }
4504
4505 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4506 int size, unsigned short port, void *val,
4507 unsigned int count)
4508 {
4509 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4510 int ret;
4511
4512 if (vcpu->arch.pio.count)
4513 goto data_avail;
4514
4515 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4516 if (ret) {
4517 data_avail:
4518 memcpy(val, vcpu->arch.pio_data, size * count);
4519 vcpu->arch.pio.count = 0;
4520 return 1;
4521 }
4522
4523 return 0;
4524 }
4525
4526 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4527 int size, unsigned short port,
4528 const void *val, unsigned int count)
4529 {
4530 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4531
4532 memcpy(vcpu->arch.pio_data, val, size * count);
4533 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4534 }
4535
4536 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4537 {
4538 return kvm_x86_ops->get_segment_base(vcpu, seg);
4539 }
4540
4541 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4542 {
4543 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4544 }
4545
4546 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4547 {
4548 if (!need_emulate_wbinvd(vcpu))
4549 return X86EMUL_CONTINUE;
4550
4551 if (kvm_x86_ops->has_wbinvd_exit()) {
4552 int cpu = get_cpu();
4553
4554 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4555 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4556 wbinvd_ipi, NULL, 1);
4557 put_cpu();
4558 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4559 } else
4560 wbinvd();
4561 return X86EMUL_CONTINUE;
4562 }
4563 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4564
4565 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4566 {
4567 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4568 }
4569
4570 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4571 {
4572 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4573 }
4574
4575 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4576 {
4577
4578 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4579 }
4580
4581 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4582 {
4583 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4584 }
4585
4586 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4587 {
4588 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4589 unsigned long value;
4590
4591 switch (cr) {
4592 case 0:
4593 value = kvm_read_cr0(vcpu);
4594 break;
4595 case 2:
4596 value = vcpu->arch.cr2;
4597 break;
4598 case 3:
4599 value = kvm_read_cr3(vcpu);
4600 break;
4601 case 4:
4602 value = kvm_read_cr4(vcpu);
4603 break;
4604 case 8:
4605 value = kvm_get_cr8(vcpu);
4606 break;
4607 default:
4608 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4609 return 0;
4610 }
4611
4612 return value;
4613 }
4614
4615 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4616 {
4617 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4618 int res = 0;
4619
4620 switch (cr) {
4621 case 0:
4622 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4623 break;
4624 case 2:
4625 vcpu->arch.cr2 = val;
4626 break;
4627 case 3:
4628 res = kvm_set_cr3(vcpu, val);
4629 break;
4630 case 4:
4631 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4632 break;
4633 case 8:
4634 res = kvm_set_cr8(vcpu, val);
4635 break;
4636 default:
4637 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4638 res = -1;
4639 }
4640
4641 return res;
4642 }
4643
4644 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4645 {
4646 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4647 }
4648
4649 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4650 {
4651 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4652 }
4653
4654 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4655 {
4656 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4657 }
4658
4659 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4660 {
4661 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4662 }
4663
4664 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4665 {
4666 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4667 }
4668
4669 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4670 {
4671 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4672 }
4673
4674 static unsigned long emulator_get_cached_segment_base(
4675 struct x86_emulate_ctxt *ctxt, int seg)
4676 {
4677 return get_segment_base(emul_to_vcpu(ctxt), seg);
4678 }
4679
4680 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4681 struct desc_struct *desc, u32 *base3,
4682 int seg)
4683 {
4684 struct kvm_segment var;
4685
4686 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4687 *selector = var.selector;
4688
4689 if (var.unusable) {
4690 memset(desc, 0, sizeof(*desc));
4691 return false;
4692 }
4693
4694 if (var.g)
4695 var.limit >>= 12;
4696 set_desc_limit(desc, var.limit);
4697 set_desc_base(desc, (unsigned long)var.base);
4698 #ifdef CONFIG_X86_64
4699 if (base3)
4700 *base3 = var.base >> 32;
4701 #endif
4702 desc->type = var.type;
4703 desc->s = var.s;
4704 desc->dpl = var.dpl;
4705 desc->p = var.present;
4706 desc->avl = var.avl;
4707 desc->l = var.l;
4708 desc->d = var.db;
4709 desc->g = var.g;
4710
4711 return true;
4712 }
4713
4714 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4715 struct desc_struct *desc, u32 base3,
4716 int seg)
4717 {
4718 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4719 struct kvm_segment var;
4720
4721 var.selector = selector;
4722 var.base = get_desc_base(desc);
4723 #ifdef CONFIG_X86_64
4724 var.base |= ((u64)base3) << 32;
4725 #endif
4726 var.limit = get_desc_limit(desc);
4727 if (desc->g)
4728 var.limit = (var.limit << 12) | 0xfff;
4729 var.type = desc->type;
4730 var.present = desc->p;
4731 var.dpl = desc->dpl;
4732 var.db = desc->d;
4733 var.s = desc->s;
4734 var.l = desc->l;
4735 var.g = desc->g;
4736 var.avl = desc->avl;
4737 var.present = desc->p;
4738 var.unusable = !var.present;
4739 var.padding = 0;
4740
4741 kvm_set_segment(vcpu, &var, seg);
4742 return;
4743 }
4744
4745 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4746 u32 msr_index, u64 *pdata)
4747 {
4748 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4749 }
4750
4751 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4752 u32 msr_index, u64 data)
4753 {
4754 struct msr_data msr;
4755
4756 msr.data = data;
4757 msr.index = msr_index;
4758 msr.host_initiated = false;
4759 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4760 }
4761
4762 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4763 u32 pmc, u64 *pdata)
4764 {
4765 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4766 }
4767
4768 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4769 {
4770 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4771 }
4772
4773 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4774 {
4775 preempt_disable();
4776 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4777 /*
4778 * CR0.TS may reference the host fpu state, not the guest fpu state,
4779 * so it may be clear at this point.
4780 */
4781 clts();
4782 }
4783
4784 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4785 {
4786 preempt_enable();
4787 }
4788
4789 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4790 struct x86_instruction_info *info,
4791 enum x86_intercept_stage stage)
4792 {
4793 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4794 }
4795
4796 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4797 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4798 {
4799 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4800 }
4801
4802 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4803 {
4804 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4805 }
4806
4807 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4808 {
4809 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4810 }
4811
4812 static const struct x86_emulate_ops emulate_ops = {
4813 .read_gpr = emulator_read_gpr,
4814 .write_gpr = emulator_write_gpr,
4815 .read_std = kvm_read_guest_virt_system,
4816 .write_std = kvm_write_guest_virt_system,
4817 .fetch = kvm_fetch_guest_virt,
4818 .read_emulated = emulator_read_emulated,
4819 .write_emulated = emulator_write_emulated,
4820 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4821 .invlpg = emulator_invlpg,
4822 .pio_in_emulated = emulator_pio_in_emulated,
4823 .pio_out_emulated = emulator_pio_out_emulated,
4824 .get_segment = emulator_get_segment,
4825 .set_segment = emulator_set_segment,
4826 .get_cached_segment_base = emulator_get_cached_segment_base,
4827 .get_gdt = emulator_get_gdt,
4828 .get_idt = emulator_get_idt,
4829 .set_gdt = emulator_set_gdt,
4830 .set_idt = emulator_set_idt,
4831 .get_cr = emulator_get_cr,
4832 .set_cr = emulator_set_cr,
4833 .set_rflags = emulator_set_rflags,
4834 .cpl = emulator_get_cpl,
4835 .get_dr = emulator_get_dr,
4836 .set_dr = emulator_set_dr,
4837 .set_msr = emulator_set_msr,
4838 .get_msr = emulator_get_msr,
4839 .read_pmc = emulator_read_pmc,
4840 .halt = emulator_halt,
4841 .wbinvd = emulator_wbinvd,
4842 .fix_hypercall = emulator_fix_hypercall,
4843 .get_fpu = emulator_get_fpu,
4844 .put_fpu = emulator_put_fpu,
4845 .intercept = emulator_intercept,
4846 .get_cpuid = emulator_get_cpuid,
4847 };
4848
4849 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4850 {
4851 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4852 /*
4853 * an sti; sti; sequence only disable interrupts for the first
4854 * instruction. So, if the last instruction, be it emulated or
4855 * not, left the system with the INT_STI flag enabled, it
4856 * means that the last instruction is an sti. We should not
4857 * leave the flag on in this case. The same goes for mov ss
4858 */
4859 if (!(int_shadow & mask))
4860 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4861 }
4862
4863 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4864 {
4865 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4866 if (ctxt->exception.vector == PF_VECTOR)
4867 kvm_propagate_fault(vcpu, &ctxt->exception);
4868 else if (ctxt->exception.error_code_valid)
4869 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4870 ctxt->exception.error_code);
4871 else
4872 kvm_queue_exception(vcpu, ctxt->exception.vector);
4873 }
4874
4875 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4876 {
4877 memset(&ctxt->opcode_len, 0,
4878 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4879
4880 ctxt->fetch.start = 0;
4881 ctxt->fetch.end = 0;
4882 ctxt->io_read.pos = 0;
4883 ctxt->io_read.end = 0;
4884 ctxt->mem_read.pos = 0;
4885 ctxt->mem_read.end = 0;
4886 }
4887
4888 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4889 {
4890 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4891 int cs_db, cs_l;
4892
4893 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4894
4895 ctxt->eflags = kvm_get_rflags(vcpu);
4896 ctxt->eip = kvm_rip_read(vcpu);
4897 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4898 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4899 cs_l ? X86EMUL_MODE_PROT64 :
4900 cs_db ? X86EMUL_MODE_PROT32 :
4901 X86EMUL_MODE_PROT16;
4902 ctxt->guest_mode = is_guest_mode(vcpu);
4903
4904 init_decode_cache(ctxt);
4905 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4906 }
4907
4908 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4909 {
4910 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4911 int ret;
4912
4913 init_emulate_ctxt(vcpu);
4914
4915 ctxt->op_bytes = 2;
4916 ctxt->ad_bytes = 2;
4917 ctxt->_eip = ctxt->eip + inc_eip;
4918 ret = emulate_int_real(ctxt, irq);
4919
4920 if (ret != X86EMUL_CONTINUE)
4921 return EMULATE_FAIL;
4922
4923 ctxt->eip = ctxt->_eip;
4924 kvm_rip_write(vcpu, ctxt->eip);
4925 kvm_set_rflags(vcpu, ctxt->eflags);
4926
4927 if (irq == NMI_VECTOR)
4928 vcpu->arch.nmi_pending = 0;
4929 else
4930 vcpu->arch.interrupt.pending = false;
4931
4932 return EMULATE_DONE;
4933 }
4934 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4935
4936 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4937 {
4938 int r = EMULATE_DONE;
4939
4940 ++vcpu->stat.insn_emulation_fail;
4941 trace_kvm_emulate_insn_failed(vcpu);
4942 if (!is_guest_mode(vcpu)) {
4943 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4944 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4945 vcpu->run->internal.ndata = 0;
4946 r = EMULATE_FAIL;
4947 }
4948 kvm_queue_exception(vcpu, UD_VECTOR);
4949
4950 return r;
4951 }
4952
4953 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4954 bool write_fault_to_shadow_pgtable,
4955 int emulation_type)
4956 {
4957 gpa_t gpa = cr2;
4958 pfn_t pfn;
4959
4960 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4961 return false;
4962
4963 if (!vcpu->arch.mmu.direct_map) {
4964 /*
4965 * Write permission should be allowed since only
4966 * write access need to be emulated.
4967 */
4968 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4969
4970 /*
4971 * If the mapping is invalid in guest, let cpu retry
4972 * it to generate fault.
4973 */
4974 if (gpa == UNMAPPED_GVA)
4975 return true;
4976 }
4977
4978 /*
4979 * Do not retry the unhandleable instruction if it faults on the
4980 * readonly host memory, otherwise it will goto a infinite loop:
4981 * retry instruction -> write #PF -> emulation fail -> retry
4982 * instruction -> ...
4983 */
4984 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4985
4986 /*
4987 * If the instruction failed on the error pfn, it can not be fixed,
4988 * report the error to userspace.
4989 */
4990 if (is_error_noslot_pfn(pfn))
4991 return false;
4992
4993 kvm_release_pfn_clean(pfn);
4994
4995 /* The instructions are well-emulated on direct mmu. */
4996 if (vcpu->arch.mmu.direct_map) {
4997 unsigned int indirect_shadow_pages;
4998
4999 spin_lock(&vcpu->kvm->mmu_lock);
5000 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5001 spin_unlock(&vcpu->kvm->mmu_lock);
5002
5003 if (indirect_shadow_pages)
5004 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5005
5006 return true;
5007 }
5008
5009 /*
5010 * if emulation was due to access to shadowed page table
5011 * and it failed try to unshadow page and re-enter the
5012 * guest to let CPU execute the instruction.
5013 */
5014 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5015
5016 /*
5017 * If the access faults on its page table, it can not
5018 * be fixed by unprotecting shadow page and it should
5019 * be reported to userspace.
5020 */
5021 return !write_fault_to_shadow_pgtable;
5022 }
5023
5024 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5025 unsigned long cr2, int emulation_type)
5026 {
5027 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5028 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5029
5030 last_retry_eip = vcpu->arch.last_retry_eip;
5031 last_retry_addr = vcpu->arch.last_retry_addr;
5032
5033 /*
5034 * If the emulation is caused by #PF and it is non-page_table
5035 * writing instruction, it means the VM-EXIT is caused by shadow
5036 * page protected, we can zap the shadow page and retry this
5037 * instruction directly.
5038 *
5039 * Note: if the guest uses a non-page-table modifying instruction
5040 * on the PDE that points to the instruction, then we will unmap
5041 * the instruction and go to an infinite loop. So, we cache the
5042 * last retried eip and the last fault address, if we meet the eip
5043 * and the address again, we can break out of the potential infinite
5044 * loop.
5045 */
5046 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5047
5048 if (!(emulation_type & EMULTYPE_RETRY))
5049 return false;
5050
5051 if (x86_page_table_writing_insn(ctxt))
5052 return false;
5053
5054 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5055 return false;
5056
5057 vcpu->arch.last_retry_eip = ctxt->eip;
5058 vcpu->arch.last_retry_addr = cr2;
5059
5060 if (!vcpu->arch.mmu.direct_map)
5061 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5062
5063 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5064
5065 return true;
5066 }
5067
5068 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5069 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5070
5071 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5072 unsigned long *db)
5073 {
5074 u32 dr6 = 0;
5075 int i;
5076 u32 enable, rwlen;
5077
5078 enable = dr7;
5079 rwlen = dr7 >> 16;
5080 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5081 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5082 dr6 |= (1 << i);
5083 return dr6;
5084 }
5085
5086 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5087 {
5088 struct kvm_run *kvm_run = vcpu->run;
5089
5090 /*
5091 * Use the "raw" value to see if TF was passed to the processor.
5092 * Note that the new value of the flags has not been saved yet.
5093 *
5094 * This is correct even for TF set by the guest, because "the
5095 * processor will not generate this exception after the instruction
5096 * that sets the TF flag".
5097 */
5098 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5099
5100 if (unlikely(rflags & X86_EFLAGS_TF)) {
5101 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5102 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5103 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5104 kvm_run->debug.arch.exception = DB_VECTOR;
5105 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5106 *r = EMULATE_USER_EXIT;
5107 } else {
5108 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5109 /*
5110 * "Certain debug exceptions may clear bit 0-3. The
5111 * remaining contents of the DR6 register are never
5112 * cleared by the processor".
5113 */
5114 vcpu->arch.dr6 &= ~15;
5115 vcpu->arch.dr6 |= DR6_BS;
5116 kvm_queue_exception(vcpu, DB_VECTOR);
5117 }
5118 }
5119 }
5120
5121 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5122 {
5123 struct kvm_run *kvm_run = vcpu->run;
5124 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5125 u32 dr6 = 0;
5126
5127 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5128 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5129 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5130 vcpu->arch.guest_debug_dr7,
5131 vcpu->arch.eff_db);
5132
5133 if (dr6 != 0) {
5134 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5135 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5136 get_segment_base(vcpu, VCPU_SREG_CS);
5137
5138 kvm_run->debug.arch.exception = DB_VECTOR;
5139 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5140 *r = EMULATE_USER_EXIT;
5141 return true;
5142 }
5143 }
5144
5145 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5146 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5147 vcpu->arch.dr7,
5148 vcpu->arch.db);
5149
5150 if (dr6 != 0) {
5151 vcpu->arch.dr6 &= ~15;
5152 vcpu->arch.dr6 |= dr6;
5153 kvm_queue_exception(vcpu, DB_VECTOR);
5154 *r = EMULATE_DONE;
5155 return true;
5156 }
5157 }
5158
5159 return false;
5160 }
5161
5162 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5163 unsigned long cr2,
5164 int emulation_type,
5165 void *insn,
5166 int insn_len)
5167 {
5168 int r;
5169 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5170 bool writeback = true;
5171 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5172
5173 /*
5174 * Clear write_fault_to_shadow_pgtable here to ensure it is
5175 * never reused.
5176 */
5177 vcpu->arch.write_fault_to_shadow_pgtable = false;
5178 kvm_clear_exception_queue(vcpu);
5179
5180 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5181 init_emulate_ctxt(vcpu);
5182
5183 /*
5184 * We will reenter on the same instruction since
5185 * we do not set complete_userspace_io. This does not
5186 * handle watchpoints yet, those would be handled in
5187 * the emulate_ops.
5188 */
5189 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5190 return r;
5191
5192 ctxt->interruptibility = 0;
5193 ctxt->have_exception = false;
5194 ctxt->perm_ok = false;
5195
5196 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5197
5198 r = x86_decode_insn(ctxt, insn, insn_len);
5199
5200 trace_kvm_emulate_insn_start(vcpu);
5201 ++vcpu->stat.insn_emulation;
5202 if (r != EMULATION_OK) {
5203 if (emulation_type & EMULTYPE_TRAP_UD)
5204 return EMULATE_FAIL;
5205 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5206 emulation_type))
5207 return EMULATE_DONE;
5208 if (emulation_type & EMULTYPE_SKIP)
5209 return EMULATE_FAIL;
5210 return handle_emulation_failure(vcpu);
5211 }
5212 }
5213
5214 if (emulation_type & EMULTYPE_SKIP) {
5215 kvm_rip_write(vcpu, ctxt->_eip);
5216 return EMULATE_DONE;
5217 }
5218
5219 if (retry_instruction(ctxt, cr2, emulation_type))
5220 return EMULATE_DONE;
5221
5222 /* this is needed for vmware backdoor interface to work since it
5223 changes registers values during IO operation */
5224 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5225 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5226 emulator_invalidate_register_cache(ctxt);
5227 }
5228
5229 restart:
5230 r = x86_emulate_insn(ctxt);
5231
5232 if (r == EMULATION_INTERCEPTED)
5233 return EMULATE_DONE;
5234
5235 if (r == EMULATION_FAILED) {
5236 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5237 emulation_type))
5238 return EMULATE_DONE;
5239
5240 return handle_emulation_failure(vcpu);
5241 }
5242
5243 if (ctxt->have_exception) {
5244 inject_emulated_exception(vcpu);
5245 r = EMULATE_DONE;
5246 } else if (vcpu->arch.pio.count) {
5247 if (!vcpu->arch.pio.in) {
5248 /* FIXME: return into emulator if single-stepping. */
5249 vcpu->arch.pio.count = 0;
5250 } else {
5251 writeback = false;
5252 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5253 }
5254 r = EMULATE_USER_EXIT;
5255 } else if (vcpu->mmio_needed) {
5256 if (!vcpu->mmio_is_write)
5257 writeback = false;
5258 r = EMULATE_USER_EXIT;
5259 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5260 } else if (r == EMULATION_RESTART)
5261 goto restart;
5262 else
5263 r = EMULATE_DONE;
5264
5265 if (writeback) {
5266 toggle_interruptibility(vcpu, ctxt->interruptibility);
5267 kvm_make_request(KVM_REQ_EVENT, vcpu);
5268 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5269 kvm_rip_write(vcpu, ctxt->eip);
5270 if (r == EMULATE_DONE)
5271 kvm_vcpu_check_singlestep(vcpu, &r);
5272 kvm_set_rflags(vcpu, ctxt->eflags);
5273 } else
5274 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5275
5276 return r;
5277 }
5278 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5279
5280 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5281 {
5282 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5283 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5284 size, port, &val, 1);
5285 /* do not return to emulator after return from userspace */
5286 vcpu->arch.pio.count = 0;
5287 return ret;
5288 }
5289 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5290
5291 static void tsc_bad(void *info)
5292 {
5293 __this_cpu_write(cpu_tsc_khz, 0);
5294 }
5295
5296 static void tsc_khz_changed(void *data)
5297 {
5298 struct cpufreq_freqs *freq = data;
5299 unsigned long khz = 0;
5300
5301 if (data)
5302 khz = freq->new;
5303 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5304 khz = cpufreq_quick_get(raw_smp_processor_id());
5305 if (!khz)
5306 khz = tsc_khz;
5307 __this_cpu_write(cpu_tsc_khz, khz);
5308 }
5309
5310 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5311 void *data)
5312 {
5313 struct cpufreq_freqs *freq = data;
5314 struct kvm *kvm;
5315 struct kvm_vcpu *vcpu;
5316 int i, send_ipi = 0;
5317
5318 /*
5319 * We allow guests to temporarily run on slowing clocks,
5320 * provided we notify them after, or to run on accelerating
5321 * clocks, provided we notify them before. Thus time never
5322 * goes backwards.
5323 *
5324 * However, we have a problem. We can't atomically update
5325 * the frequency of a given CPU from this function; it is
5326 * merely a notifier, which can be called from any CPU.
5327 * Changing the TSC frequency at arbitrary points in time
5328 * requires a recomputation of local variables related to
5329 * the TSC for each VCPU. We must flag these local variables
5330 * to be updated and be sure the update takes place with the
5331 * new frequency before any guests proceed.
5332 *
5333 * Unfortunately, the combination of hotplug CPU and frequency
5334 * change creates an intractable locking scenario; the order
5335 * of when these callouts happen is undefined with respect to
5336 * CPU hotplug, and they can race with each other. As such,
5337 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5338 * undefined; you can actually have a CPU frequency change take
5339 * place in between the computation of X and the setting of the
5340 * variable. To protect against this problem, all updates of
5341 * the per_cpu tsc_khz variable are done in an interrupt
5342 * protected IPI, and all callers wishing to update the value
5343 * must wait for a synchronous IPI to complete (which is trivial
5344 * if the caller is on the CPU already). This establishes the
5345 * necessary total order on variable updates.
5346 *
5347 * Note that because a guest time update may take place
5348 * anytime after the setting of the VCPU's request bit, the
5349 * correct TSC value must be set before the request. However,
5350 * to ensure the update actually makes it to any guest which
5351 * starts running in hardware virtualization between the set
5352 * and the acquisition of the spinlock, we must also ping the
5353 * CPU after setting the request bit.
5354 *
5355 */
5356
5357 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5358 return 0;
5359 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5360 return 0;
5361
5362 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5363
5364 spin_lock(&kvm_lock);
5365 list_for_each_entry(kvm, &vm_list, vm_list) {
5366 kvm_for_each_vcpu(i, vcpu, kvm) {
5367 if (vcpu->cpu != freq->cpu)
5368 continue;
5369 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5370 if (vcpu->cpu != smp_processor_id())
5371 send_ipi = 1;
5372 }
5373 }
5374 spin_unlock(&kvm_lock);
5375
5376 if (freq->old < freq->new && send_ipi) {
5377 /*
5378 * We upscale the frequency. Must make the guest
5379 * doesn't see old kvmclock values while running with
5380 * the new frequency, otherwise we risk the guest sees
5381 * time go backwards.
5382 *
5383 * In case we update the frequency for another cpu
5384 * (which might be in guest context) send an interrupt
5385 * to kick the cpu out of guest context. Next time
5386 * guest context is entered kvmclock will be updated,
5387 * so the guest will not see stale values.
5388 */
5389 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5390 }
5391 return 0;
5392 }
5393
5394 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5395 .notifier_call = kvmclock_cpufreq_notifier
5396 };
5397
5398 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5399 unsigned long action, void *hcpu)
5400 {
5401 unsigned int cpu = (unsigned long)hcpu;
5402
5403 switch (action) {
5404 case CPU_ONLINE:
5405 case CPU_DOWN_FAILED:
5406 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5407 break;
5408 case CPU_DOWN_PREPARE:
5409 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5410 break;
5411 }
5412 return NOTIFY_OK;
5413 }
5414
5415 static struct notifier_block kvmclock_cpu_notifier_block = {
5416 .notifier_call = kvmclock_cpu_notifier,
5417 .priority = -INT_MAX
5418 };
5419
5420 static void kvm_timer_init(void)
5421 {
5422 int cpu;
5423
5424 max_tsc_khz = tsc_khz;
5425 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5426 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5427 #ifdef CONFIG_CPU_FREQ
5428 struct cpufreq_policy policy;
5429 memset(&policy, 0, sizeof(policy));
5430 cpu = get_cpu();
5431 cpufreq_get_policy(&policy, cpu);
5432 if (policy.cpuinfo.max_freq)
5433 max_tsc_khz = policy.cpuinfo.max_freq;
5434 put_cpu();
5435 #endif
5436 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5437 CPUFREQ_TRANSITION_NOTIFIER);
5438 }
5439 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5440 for_each_online_cpu(cpu)
5441 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5442 }
5443
5444 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5445
5446 int kvm_is_in_guest(void)
5447 {
5448 return __this_cpu_read(current_vcpu) != NULL;
5449 }
5450
5451 static int kvm_is_user_mode(void)
5452 {
5453 int user_mode = 3;
5454
5455 if (__this_cpu_read(current_vcpu))
5456 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5457
5458 return user_mode != 0;
5459 }
5460
5461 static unsigned long kvm_get_guest_ip(void)
5462 {
5463 unsigned long ip = 0;
5464
5465 if (__this_cpu_read(current_vcpu))
5466 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5467
5468 return ip;
5469 }
5470
5471 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5472 .is_in_guest = kvm_is_in_guest,
5473 .is_user_mode = kvm_is_user_mode,
5474 .get_guest_ip = kvm_get_guest_ip,
5475 };
5476
5477 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5478 {
5479 __this_cpu_write(current_vcpu, vcpu);
5480 }
5481 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5482
5483 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5484 {
5485 __this_cpu_write(current_vcpu, NULL);
5486 }
5487 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5488
5489 static void kvm_set_mmio_spte_mask(void)
5490 {
5491 u64 mask;
5492 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5493
5494 /*
5495 * Set the reserved bits and the present bit of an paging-structure
5496 * entry to generate page fault with PFER.RSV = 1.
5497 */
5498 /* Mask the reserved physical address bits. */
5499 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5500
5501 /* Bit 62 is always reserved for 32bit host. */
5502 mask |= 0x3ull << 62;
5503
5504 /* Set the present bit. */
5505 mask |= 1ull;
5506
5507 #ifdef CONFIG_X86_64
5508 /*
5509 * If reserved bit is not supported, clear the present bit to disable
5510 * mmio page fault.
5511 */
5512 if (maxphyaddr == 52)
5513 mask &= ~1ull;
5514 #endif
5515
5516 kvm_mmu_set_mmio_spte_mask(mask);
5517 }
5518
5519 #ifdef CONFIG_X86_64
5520 static void pvclock_gtod_update_fn(struct work_struct *work)
5521 {
5522 struct kvm *kvm;
5523
5524 struct kvm_vcpu *vcpu;
5525 int i;
5526
5527 spin_lock(&kvm_lock);
5528 list_for_each_entry(kvm, &vm_list, vm_list)
5529 kvm_for_each_vcpu(i, vcpu, kvm)
5530 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5531 atomic_set(&kvm_guest_has_master_clock, 0);
5532 spin_unlock(&kvm_lock);
5533 }
5534
5535 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5536
5537 /*
5538 * Notification about pvclock gtod data update.
5539 */
5540 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5541 void *priv)
5542 {
5543 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5544 struct timekeeper *tk = priv;
5545
5546 update_pvclock_gtod(tk);
5547
5548 /* disable master clock if host does not trust, or does not
5549 * use, TSC clocksource
5550 */
5551 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5552 atomic_read(&kvm_guest_has_master_clock) != 0)
5553 queue_work(system_long_wq, &pvclock_gtod_work);
5554
5555 return 0;
5556 }
5557
5558 static struct notifier_block pvclock_gtod_notifier = {
5559 .notifier_call = pvclock_gtod_notify,
5560 };
5561 #endif
5562
5563 int kvm_arch_init(void *opaque)
5564 {
5565 int r;
5566 struct kvm_x86_ops *ops = opaque;
5567
5568 if (kvm_x86_ops) {
5569 printk(KERN_ERR "kvm: already loaded the other module\n");
5570 r = -EEXIST;
5571 goto out;
5572 }
5573
5574 if (!ops->cpu_has_kvm_support()) {
5575 printk(KERN_ERR "kvm: no hardware support\n");
5576 r = -EOPNOTSUPP;
5577 goto out;
5578 }
5579 if (ops->disabled_by_bios()) {
5580 printk(KERN_ERR "kvm: disabled by bios\n");
5581 r = -EOPNOTSUPP;
5582 goto out;
5583 }
5584
5585 r = -ENOMEM;
5586 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5587 if (!shared_msrs) {
5588 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5589 goto out;
5590 }
5591
5592 r = kvm_mmu_module_init();
5593 if (r)
5594 goto out_free_percpu;
5595
5596 kvm_set_mmio_spte_mask();
5597
5598 kvm_x86_ops = ops;
5599 kvm_init_msr_list();
5600
5601 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5602 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5603
5604 kvm_timer_init();
5605
5606 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5607
5608 if (cpu_has_xsave)
5609 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5610
5611 kvm_lapic_init();
5612 #ifdef CONFIG_X86_64
5613 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5614 #endif
5615
5616 return 0;
5617
5618 out_free_percpu:
5619 free_percpu(shared_msrs);
5620 out:
5621 return r;
5622 }
5623
5624 void kvm_arch_exit(void)
5625 {
5626 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5627
5628 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5629 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5630 CPUFREQ_TRANSITION_NOTIFIER);
5631 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5632 #ifdef CONFIG_X86_64
5633 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5634 #endif
5635 kvm_x86_ops = NULL;
5636 kvm_mmu_module_exit();
5637 free_percpu(shared_msrs);
5638 }
5639
5640 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5641 {
5642 ++vcpu->stat.halt_exits;
5643 if (irqchip_in_kernel(vcpu->kvm)) {
5644 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5645 return 1;
5646 } else {
5647 vcpu->run->exit_reason = KVM_EXIT_HLT;
5648 return 0;
5649 }
5650 }
5651 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5652
5653 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5654 {
5655 u64 param, ingpa, outgpa, ret;
5656 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5657 bool fast, longmode;
5658 int cs_db, cs_l;
5659
5660 /*
5661 * hypercall generates UD from non zero cpl and real mode
5662 * per HYPER-V spec
5663 */
5664 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5665 kvm_queue_exception(vcpu, UD_VECTOR);
5666 return 0;
5667 }
5668
5669 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5670 longmode = is_long_mode(vcpu) && cs_l == 1;
5671
5672 if (!longmode) {
5673 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5674 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5675 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5676 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5677 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5678 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5679 }
5680 #ifdef CONFIG_X86_64
5681 else {
5682 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5683 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5684 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5685 }
5686 #endif
5687
5688 code = param & 0xffff;
5689 fast = (param >> 16) & 0x1;
5690 rep_cnt = (param >> 32) & 0xfff;
5691 rep_idx = (param >> 48) & 0xfff;
5692
5693 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5694
5695 switch (code) {
5696 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5697 kvm_vcpu_on_spin(vcpu);
5698 break;
5699 default:
5700 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5701 break;
5702 }
5703
5704 ret = res | (((u64)rep_done & 0xfff) << 32);
5705 if (longmode) {
5706 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5707 } else {
5708 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5709 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5710 }
5711
5712 return 1;
5713 }
5714
5715 /*
5716 * kvm_pv_kick_cpu_op: Kick a vcpu.
5717 *
5718 * @apicid - apicid of vcpu to be kicked.
5719 */
5720 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5721 {
5722 struct kvm_lapic_irq lapic_irq;
5723
5724 lapic_irq.shorthand = 0;
5725 lapic_irq.dest_mode = 0;
5726 lapic_irq.dest_id = apicid;
5727
5728 lapic_irq.delivery_mode = APIC_DM_REMRD;
5729 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5730 }
5731
5732 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5733 {
5734 unsigned long nr, a0, a1, a2, a3, ret;
5735 int r = 1;
5736
5737 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5738 return kvm_hv_hypercall(vcpu);
5739
5740 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5741 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5742 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5743 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5744 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5745
5746 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5747
5748 if (!is_long_mode(vcpu)) {
5749 nr &= 0xFFFFFFFF;
5750 a0 &= 0xFFFFFFFF;
5751 a1 &= 0xFFFFFFFF;
5752 a2 &= 0xFFFFFFFF;
5753 a3 &= 0xFFFFFFFF;
5754 }
5755
5756 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5757 ret = -KVM_EPERM;
5758 goto out;
5759 }
5760
5761 switch (nr) {
5762 case KVM_HC_VAPIC_POLL_IRQ:
5763 ret = 0;
5764 break;
5765 case KVM_HC_KICK_CPU:
5766 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5767 ret = 0;
5768 break;
5769 default:
5770 ret = -KVM_ENOSYS;
5771 break;
5772 }
5773 out:
5774 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5775 ++vcpu->stat.hypercalls;
5776 return r;
5777 }
5778 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5779
5780 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5781 {
5782 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5783 char instruction[3];
5784 unsigned long rip = kvm_rip_read(vcpu);
5785
5786 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5787
5788 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5789 }
5790
5791 /*
5792 * Check if userspace requested an interrupt window, and that the
5793 * interrupt window is open.
5794 *
5795 * No need to exit to userspace if we already have an interrupt queued.
5796 */
5797 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5798 {
5799 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5800 vcpu->run->request_interrupt_window &&
5801 kvm_arch_interrupt_allowed(vcpu));
5802 }
5803
5804 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5805 {
5806 struct kvm_run *kvm_run = vcpu->run;
5807
5808 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5809 kvm_run->cr8 = kvm_get_cr8(vcpu);
5810 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5811 if (irqchip_in_kernel(vcpu->kvm))
5812 kvm_run->ready_for_interrupt_injection = 1;
5813 else
5814 kvm_run->ready_for_interrupt_injection =
5815 kvm_arch_interrupt_allowed(vcpu) &&
5816 !kvm_cpu_has_interrupt(vcpu) &&
5817 !kvm_event_needs_reinjection(vcpu);
5818 }
5819
5820 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5821 {
5822 int max_irr, tpr;
5823
5824 if (!kvm_x86_ops->update_cr8_intercept)
5825 return;
5826
5827 if (!vcpu->arch.apic)
5828 return;
5829
5830 if (!vcpu->arch.apic->vapic_addr)
5831 max_irr = kvm_lapic_find_highest_irr(vcpu);
5832 else
5833 max_irr = -1;
5834
5835 if (max_irr != -1)
5836 max_irr >>= 4;
5837
5838 tpr = kvm_lapic_get_cr8(vcpu);
5839
5840 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5841 }
5842
5843 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
5844 {
5845 int r;
5846
5847 /* try to reinject previous events if any */
5848 if (vcpu->arch.exception.pending) {
5849 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5850 vcpu->arch.exception.has_error_code,
5851 vcpu->arch.exception.error_code);
5852 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5853 vcpu->arch.exception.has_error_code,
5854 vcpu->arch.exception.error_code,
5855 vcpu->arch.exception.reinject);
5856 return 0;
5857 }
5858
5859 if (vcpu->arch.nmi_injected) {
5860 kvm_x86_ops->set_nmi(vcpu);
5861 return 0;
5862 }
5863
5864 if (vcpu->arch.interrupt.pending) {
5865 kvm_x86_ops->set_irq(vcpu);
5866 return 0;
5867 }
5868
5869 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5870 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5871 if (r != 0)
5872 return r;
5873 }
5874
5875 /* try to inject new event if pending */
5876 if (vcpu->arch.nmi_pending) {
5877 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5878 --vcpu->arch.nmi_pending;
5879 vcpu->arch.nmi_injected = true;
5880 kvm_x86_ops->set_nmi(vcpu);
5881 }
5882 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5883 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5884 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5885 false);
5886 kvm_x86_ops->set_irq(vcpu);
5887 }
5888 }
5889 return 0;
5890 }
5891
5892 static void process_nmi(struct kvm_vcpu *vcpu)
5893 {
5894 unsigned limit = 2;
5895
5896 /*
5897 * x86 is limited to one NMI running, and one NMI pending after it.
5898 * If an NMI is already in progress, limit further NMIs to just one.
5899 * Otherwise, allow two (and we'll inject the first one immediately).
5900 */
5901 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5902 limit = 1;
5903
5904 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5905 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5906 kvm_make_request(KVM_REQ_EVENT, vcpu);
5907 }
5908
5909 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5910 {
5911 u64 eoi_exit_bitmap[4];
5912 u32 tmr[8];
5913
5914 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5915 return;
5916
5917 memset(eoi_exit_bitmap, 0, 32);
5918 memset(tmr, 0, 32);
5919
5920 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5921 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5922 kvm_apic_update_tmr(vcpu, tmr);
5923 }
5924
5925 /*
5926 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5927 * exiting to the userspace. Otherwise, the value will be returned to the
5928 * userspace.
5929 */
5930 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5931 {
5932 int r;
5933 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5934 vcpu->run->request_interrupt_window;
5935 bool req_immediate_exit = false;
5936
5937 if (vcpu->requests) {
5938 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5939 kvm_mmu_unload(vcpu);
5940 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5941 __kvm_migrate_timers(vcpu);
5942 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5943 kvm_gen_update_masterclock(vcpu->kvm);
5944 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5945 kvm_gen_kvmclock_update(vcpu);
5946 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5947 r = kvm_guest_time_update(vcpu);
5948 if (unlikely(r))
5949 goto out;
5950 }
5951 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5952 kvm_mmu_sync_roots(vcpu);
5953 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5954 kvm_x86_ops->tlb_flush(vcpu);
5955 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5956 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5957 r = 0;
5958 goto out;
5959 }
5960 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5961 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5962 r = 0;
5963 goto out;
5964 }
5965 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5966 vcpu->fpu_active = 0;
5967 kvm_x86_ops->fpu_deactivate(vcpu);
5968 }
5969 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5970 /* Page is swapped out. Do synthetic halt */
5971 vcpu->arch.apf.halted = true;
5972 r = 1;
5973 goto out;
5974 }
5975 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5976 record_steal_time(vcpu);
5977 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5978 process_nmi(vcpu);
5979 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5980 kvm_handle_pmu_event(vcpu);
5981 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5982 kvm_deliver_pmi(vcpu);
5983 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5984 vcpu_scan_ioapic(vcpu);
5985 }
5986
5987 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5988 kvm_apic_accept_events(vcpu);
5989 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5990 r = 1;
5991 goto out;
5992 }
5993
5994 if (inject_pending_event(vcpu, req_int_win) != 0)
5995 req_immediate_exit = true;
5996 /* enable NMI/IRQ window open exits if needed */
5997 else if (vcpu->arch.nmi_pending)
5998 kvm_x86_ops->enable_nmi_window(vcpu);
5999 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6000 kvm_x86_ops->enable_irq_window(vcpu);
6001
6002 if (kvm_lapic_enabled(vcpu)) {
6003 /*
6004 * Update architecture specific hints for APIC
6005 * virtual interrupt delivery.
6006 */
6007 if (kvm_x86_ops->hwapic_irr_update)
6008 kvm_x86_ops->hwapic_irr_update(vcpu,
6009 kvm_lapic_find_highest_irr(vcpu));
6010 update_cr8_intercept(vcpu);
6011 kvm_lapic_sync_to_vapic(vcpu);
6012 }
6013 }
6014
6015 r = kvm_mmu_reload(vcpu);
6016 if (unlikely(r)) {
6017 goto cancel_injection;
6018 }
6019
6020 preempt_disable();
6021
6022 kvm_x86_ops->prepare_guest_switch(vcpu);
6023 if (vcpu->fpu_active)
6024 kvm_load_guest_fpu(vcpu);
6025 kvm_load_guest_xcr0(vcpu);
6026
6027 vcpu->mode = IN_GUEST_MODE;
6028
6029 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6030
6031 /* We should set ->mode before check ->requests,
6032 * see the comment in make_all_cpus_request.
6033 */
6034 smp_mb__after_srcu_read_unlock();
6035
6036 local_irq_disable();
6037
6038 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6039 || need_resched() || signal_pending(current)) {
6040 vcpu->mode = OUTSIDE_GUEST_MODE;
6041 smp_wmb();
6042 local_irq_enable();
6043 preempt_enable();
6044 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6045 r = 1;
6046 goto cancel_injection;
6047 }
6048
6049 if (req_immediate_exit)
6050 smp_send_reschedule(vcpu->cpu);
6051
6052 kvm_guest_enter();
6053
6054 if (unlikely(vcpu->arch.switch_db_regs)) {
6055 set_debugreg(0, 7);
6056 set_debugreg(vcpu->arch.eff_db[0], 0);
6057 set_debugreg(vcpu->arch.eff_db[1], 1);
6058 set_debugreg(vcpu->arch.eff_db[2], 2);
6059 set_debugreg(vcpu->arch.eff_db[3], 3);
6060 set_debugreg(vcpu->arch.dr6, 6);
6061 }
6062
6063 trace_kvm_entry(vcpu->vcpu_id);
6064 kvm_x86_ops->run(vcpu);
6065
6066 /*
6067 * Do this here before restoring debug registers on the host. And
6068 * since we do this before handling the vmexit, a DR access vmexit
6069 * can (a) read the correct value of the debug registers, (b) set
6070 * KVM_DEBUGREG_WONT_EXIT again.
6071 */
6072 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6073 int i;
6074
6075 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6076 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6077 for (i = 0; i < KVM_NR_DB_REGS; i++)
6078 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6079 }
6080
6081 /*
6082 * If the guest has used debug registers, at least dr7
6083 * will be disabled while returning to the host.
6084 * If we don't have active breakpoints in the host, we don't
6085 * care about the messed up debug address registers. But if
6086 * we have some of them active, restore the old state.
6087 */
6088 if (hw_breakpoint_active())
6089 hw_breakpoint_restore();
6090
6091 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6092 native_read_tsc());
6093
6094 vcpu->mode = OUTSIDE_GUEST_MODE;
6095 smp_wmb();
6096
6097 /* Interrupt is enabled by handle_external_intr() */
6098 kvm_x86_ops->handle_external_intr(vcpu);
6099
6100 ++vcpu->stat.exits;
6101
6102 /*
6103 * We must have an instruction between local_irq_enable() and
6104 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6105 * the interrupt shadow. The stat.exits increment will do nicely.
6106 * But we need to prevent reordering, hence this barrier():
6107 */
6108 barrier();
6109
6110 kvm_guest_exit();
6111
6112 preempt_enable();
6113
6114 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6115
6116 /*
6117 * Profile KVM exit RIPs:
6118 */
6119 if (unlikely(prof_on == KVM_PROFILING)) {
6120 unsigned long rip = kvm_rip_read(vcpu);
6121 profile_hit(KVM_PROFILING, (void *)rip);
6122 }
6123
6124 if (unlikely(vcpu->arch.tsc_always_catchup))
6125 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6126
6127 if (vcpu->arch.apic_attention)
6128 kvm_lapic_sync_from_vapic(vcpu);
6129
6130 r = kvm_x86_ops->handle_exit(vcpu);
6131 return r;
6132
6133 cancel_injection:
6134 kvm_x86_ops->cancel_injection(vcpu);
6135 if (unlikely(vcpu->arch.apic_attention))
6136 kvm_lapic_sync_from_vapic(vcpu);
6137 out:
6138 return r;
6139 }
6140
6141
6142 static int __vcpu_run(struct kvm_vcpu *vcpu)
6143 {
6144 int r;
6145 struct kvm *kvm = vcpu->kvm;
6146
6147 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6148
6149 r = 1;
6150 while (r > 0) {
6151 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6152 !vcpu->arch.apf.halted)
6153 r = vcpu_enter_guest(vcpu);
6154 else {
6155 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6156 kvm_vcpu_block(vcpu);
6157 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6158 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6159 kvm_apic_accept_events(vcpu);
6160 switch(vcpu->arch.mp_state) {
6161 case KVM_MP_STATE_HALTED:
6162 vcpu->arch.pv.pv_unhalted = false;
6163 vcpu->arch.mp_state =
6164 KVM_MP_STATE_RUNNABLE;
6165 case KVM_MP_STATE_RUNNABLE:
6166 vcpu->arch.apf.halted = false;
6167 break;
6168 case KVM_MP_STATE_INIT_RECEIVED:
6169 break;
6170 default:
6171 r = -EINTR;
6172 break;
6173 }
6174 }
6175 }
6176
6177 if (r <= 0)
6178 break;
6179
6180 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6181 if (kvm_cpu_has_pending_timer(vcpu))
6182 kvm_inject_pending_timer_irqs(vcpu);
6183
6184 if (dm_request_for_irq_injection(vcpu)) {
6185 r = -EINTR;
6186 vcpu->run->exit_reason = KVM_EXIT_INTR;
6187 ++vcpu->stat.request_irq_exits;
6188 }
6189
6190 kvm_check_async_pf_completion(vcpu);
6191
6192 if (signal_pending(current)) {
6193 r = -EINTR;
6194 vcpu->run->exit_reason = KVM_EXIT_INTR;
6195 ++vcpu->stat.signal_exits;
6196 }
6197 if (need_resched()) {
6198 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6199 cond_resched();
6200 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6201 }
6202 }
6203
6204 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6205
6206 return r;
6207 }
6208
6209 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6210 {
6211 int r;
6212 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6213 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6214 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6215 if (r != EMULATE_DONE)
6216 return 0;
6217 return 1;
6218 }
6219
6220 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6221 {
6222 BUG_ON(!vcpu->arch.pio.count);
6223
6224 return complete_emulated_io(vcpu);
6225 }
6226
6227 /*
6228 * Implements the following, as a state machine:
6229 *
6230 * read:
6231 * for each fragment
6232 * for each mmio piece in the fragment
6233 * write gpa, len
6234 * exit
6235 * copy data
6236 * execute insn
6237 *
6238 * write:
6239 * for each fragment
6240 * for each mmio piece in the fragment
6241 * write gpa, len
6242 * copy data
6243 * exit
6244 */
6245 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6246 {
6247 struct kvm_run *run = vcpu->run;
6248 struct kvm_mmio_fragment *frag;
6249 unsigned len;
6250
6251 BUG_ON(!vcpu->mmio_needed);
6252
6253 /* Complete previous fragment */
6254 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6255 len = min(8u, frag->len);
6256 if (!vcpu->mmio_is_write)
6257 memcpy(frag->data, run->mmio.data, len);
6258
6259 if (frag->len <= 8) {
6260 /* Switch to the next fragment. */
6261 frag++;
6262 vcpu->mmio_cur_fragment++;
6263 } else {
6264 /* Go forward to the next mmio piece. */
6265 frag->data += len;
6266 frag->gpa += len;
6267 frag->len -= len;
6268 }
6269
6270 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6271 vcpu->mmio_needed = 0;
6272
6273 /* FIXME: return into emulator if single-stepping. */
6274 if (vcpu->mmio_is_write)
6275 return 1;
6276 vcpu->mmio_read_completed = 1;
6277 return complete_emulated_io(vcpu);
6278 }
6279
6280 run->exit_reason = KVM_EXIT_MMIO;
6281 run->mmio.phys_addr = frag->gpa;
6282 if (vcpu->mmio_is_write)
6283 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6284 run->mmio.len = min(8u, frag->len);
6285 run->mmio.is_write = vcpu->mmio_is_write;
6286 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6287 return 0;
6288 }
6289
6290
6291 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6292 {
6293 int r;
6294 sigset_t sigsaved;
6295
6296 if (!tsk_used_math(current) && init_fpu(current))
6297 return -ENOMEM;
6298
6299 if (vcpu->sigset_active)
6300 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6301
6302 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6303 kvm_vcpu_block(vcpu);
6304 kvm_apic_accept_events(vcpu);
6305 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6306 r = -EAGAIN;
6307 goto out;
6308 }
6309
6310 /* re-sync apic's tpr */
6311 if (!irqchip_in_kernel(vcpu->kvm)) {
6312 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6313 r = -EINVAL;
6314 goto out;
6315 }
6316 }
6317
6318 if (unlikely(vcpu->arch.complete_userspace_io)) {
6319 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6320 vcpu->arch.complete_userspace_io = NULL;
6321 r = cui(vcpu);
6322 if (r <= 0)
6323 goto out;
6324 } else
6325 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6326
6327 r = __vcpu_run(vcpu);
6328
6329 out:
6330 post_kvm_run_save(vcpu);
6331 if (vcpu->sigset_active)
6332 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6333
6334 return r;
6335 }
6336
6337 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6338 {
6339 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6340 /*
6341 * We are here if userspace calls get_regs() in the middle of
6342 * instruction emulation. Registers state needs to be copied
6343 * back from emulation context to vcpu. Userspace shouldn't do
6344 * that usually, but some bad designed PV devices (vmware
6345 * backdoor interface) need this to work
6346 */
6347 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6348 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6349 }
6350 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6351 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6352 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6353 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6354 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6355 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6356 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6357 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6358 #ifdef CONFIG_X86_64
6359 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6360 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6361 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6362 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6363 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6364 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6365 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6366 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6367 #endif
6368
6369 regs->rip = kvm_rip_read(vcpu);
6370 regs->rflags = kvm_get_rflags(vcpu);
6371
6372 return 0;
6373 }
6374
6375 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6376 {
6377 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6378 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6379
6380 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6381 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6382 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6383 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6384 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6385 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6386 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6387 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6388 #ifdef CONFIG_X86_64
6389 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6390 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6391 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6392 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6393 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6394 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6395 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6396 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6397 #endif
6398
6399 kvm_rip_write(vcpu, regs->rip);
6400 kvm_set_rflags(vcpu, regs->rflags);
6401
6402 vcpu->arch.exception.pending = false;
6403
6404 kvm_make_request(KVM_REQ_EVENT, vcpu);
6405
6406 return 0;
6407 }
6408
6409 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6410 {
6411 struct kvm_segment cs;
6412
6413 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6414 *db = cs.db;
6415 *l = cs.l;
6416 }
6417 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6418
6419 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6420 struct kvm_sregs *sregs)
6421 {
6422 struct desc_ptr dt;
6423
6424 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6425 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6426 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6427 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6428 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6429 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6430
6431 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6432 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6433
6434 kvm_x86_ops->get_idt(vcpu, &dt);
6435 sregs->idt.limit = dt.size;
6436 sregs->idt.base = dt.address;
6437 kvm_x86_ops->get_gdt(vcpu, &dt);
6438 sregs->gdt.limit = dt.size;
6439 sregs->gdt.base = dt.address;
6440
6441 sregs->cr0 = kvm_read_cr0(vcpu);
6442 sregs->cr2 = vcpu->arch.cr2;
6443 sregs->cr3 = kvm_read_cr3(vcpu);
6444 sregs->cr4 = kvm_read_cr4(vcpu);
6445 sregs->cr8 = kvm_get_cr8(vcpu);
6446 sregs->efer = vcpu->arch.efer;
6447 sregs->apic_base = kvm_get_apic_base(vcpu);
6448
6449 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6450
6451 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6452 set_bit(vcpu->arch.interrupt.nr,
6453 (unsigned long *)sregs->interrupt_bitmap);
6454
6455 return 0;
6456 }
6457
6458 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6459 struct kvm_mp_state *mp_state)
6460 {
6461 kvm_apic_accept_events(vcpu);
6462 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6463 vcpu->arch.pv.pv_unhalted)
6464 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6465 else
6466 mp_state->mp_state = vcpu->arch.mp_state;
6467
6468 return 0;
6469 }
6470
6471 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6472 struct kvm_mp_state *mp_state)
6473 {
6474 if (!kvm_vcpu_has_lapic(vcpu) &&
6475 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6476 return -EINVAL;
6477
6478 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6479 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6480 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6481 } else
6482 vcpu->arch.mp_state = mp_state->mp_state;
6483 kvm_make_request(KVM_REQ_EVENT, vcpu);
6484 return 0;
6485 }
6486
6487 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6488 int reason, bool has_error_code, u32 error_code)
6489 {
6490 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6491 int ret;
6492
6493 init_emulate_ctxt(vcpu);
6494
6495 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6496 has_error_code, error_code);
6497
6498 if (ret)
6499 return EMULATE_FAIL;
6500
6501 kvm_rip_write(vcpu, ctxt->eip);
6502 kvm_set_rflags(vcpu, ctxt->eflags);
6503 kvm_make_request(KVM_REQ_EVENT, vcpu);
6504 return EMULATE_DONE;
6505 }
6506 EXPORT_SYMBOL_GPL(kvm_task_switch);
6507
6508 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6509 struct kvm_sregs *sregs)
6510 {
6511 struct msr_data apic_base_msr;
6512 int mmu_reset_needed = 0;
6513 int pending_vec, max_bits, idx;
6514 struct desc_ptr dt;
6515
6516 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6517 return -EINVAL;
6518
6519 dt.size = sregs->idt.limit;
6520 dt.address = sregs->idt.base;
6521 kvm_x86_ops->set_idt(vcpu, &dt);
6522 dt.size = sregs->gdt.limit;
6523 dt.address = sregs->gdt.base;
6524 kvm_x86_ops->set_gdt(vcpu, &dt);
6525
6526 vcpu->arch.cr2 = sregs->cr2;
6527 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6528 vcpu->arch.cr3 = sregs->cr3;
6529 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6530
6531 kvm_set_cr8(vcpu, sregs->cr8);
6532
6533 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6534 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6535 apic_base_msr.data = sregs->apic_base;
6536 apic_base_msr.host_initiated = true;
6537 kvm_set_apic_base(vcpu, &apic_base_msr);
6538
6539 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6540 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6541 vcpu->arch.cr0 = sregs->cr0;
6542
6543 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6544 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6545 if (sregs->cr4 & X86_CR4_OSXSAVE)
6546 kvm_update_cpuid(vcpu);
6547
6548 idx = srcu_read_lock(&vcpu->kvm->srcu);
6549 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6550 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6551 mmu_reset_needed = 1;
6552 }
6553 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6554
6555 if (mmu_reset_needed)
6556 kvm_mmu_reset_context(vcpu);
6557
6558 max_bits = KVM_NR_INTERRUPTS;
6559 pending_vec = find_first_bit(
6560 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6561 if (pending_vec < max_bits) {
6562 kvm_queue_interrupt(vcpu, pending_vec, false);
6563 pr_debug("Set back pending irq %d\n", pending_vec);
6564 }
6565
6566 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6567 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6568 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6569 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6570 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6571 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6572
6573 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6574 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6575
6576 update_cr8_intercept(vcpu);
6577
6578 /* Older userspace won't unhalt the vcpu on reset. */
6579 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6580 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6581 !is_protmode(vcpu))
6582 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6583
6584 kvm_make_request(KVM_REQ_EVENT, vcpu);
6585
6586 return 0;
6587 }
6588
6589 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6590 struct kvm_guest_debug *dbg)
6591 {
6592 unsigned long rflags;
6593 int i, r;
6594
6595 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6596 r = -EBUSY;
6597 if (vcpu->arch.exception.pending)
6598 goto out;
6599 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6600 kvm_queue_exception(vcpu, DB_VECTOR);
6601 else
6602 kvm_queue_exception(vcpu, BP_VECTOR);
6603 }
6604
6605 /*
6606 * Read rflags as long as potentially injected trace flags are still
6607 * filtered out.
6608 */
6609 rflags = kvm_get_rflags(vcpu);
6610
6611 vcpu->guest_debug = dbg->control;
6612 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6613 vcpu->guest_debug = 0;
6614
6615 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6616 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6617 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6618 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6619 } else {
6620 for (i = 0; i < KVM_NR_DB_REGS; i++)
6621 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6622 }
6623 kvm_update_dr7(vcpu);
6624
6625 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6626 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6627 get_segment_base(vcpu, VCPU_SREG_CS);
6628
6629 /*
6630 * Trigger an rflags update that will inject or remove the trace
6631 * flags.
6632 */
6633 kvm_set_rflags(vcpu, rflags);
6634
6635 kvm_x86_ops->update_db_bp_intercept(vcpu);
6636
6637 r = 0;
6638
6639 out:
6640
6641 return r;
6642 }
6643
6644 /*
6645 * Translate a guest virtual address to a guest physical address.
6646 */
6647 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6648 struct kvm_translation *tr)
6649 {
6650 unsigned long vaddr = tr->linear_address;
6651 gpa_t gpa;
6652 int idx;
6653
6654 idx = srcu_read_lock(&vcpu->kvm->srcu);
6655 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6656 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6657 tr->physical_address = gpa;
6658 tr->valid = gpa != UNMAPPED_GVA;
6659 tr->writeable = 1;
6660 tr->usermode = 0;
6661
6662 return 0;
6663 }
6664
6665 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6666 {
6667 struct i387_fxsave_struct *fxsave =
6668 &vcpu->arch.guest_fpu.state->fxsave;
6669
6670 memcpy(fpu->fpr, fxsave->st_space, 128);
6671 fpu->fcw = fxsave->cwd;
6672 fpu->fsw = fxsave->swd;
6673 fpu->ftwx = fxsave->twd;
6674 fpu->last_opcode = fxsave->fop;
6675 fpu->last_ip = fxsave->rip;
6676 fpu->last_dp = fxsave->rdp;
6677 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6678
6679 return 0;
6680 }
6681
6682 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6683 {
6684 struct i387_fxsave_struct *fxsave =
6685 &vcpu->arch.guest_fpu.state->fxsave;
6686
6687 memcpy(fxsave->st_space, fpu->fpr, 128);
6688 fxsave->cwd = fpu->fcw;
6689 fxsave->swd = fpu->fsw;
6690 fxsave->twd = fpu->ftwx;
6691 fxsave->fop = fpu->last_opcode;
6692 fxsave->rip = fpu->last_ip;
6693 fxsave->rdp = fpu->last_dp;
6694 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6695
6696 return 0;
6697 }
6698
6699 int fx_init(struct kvm_vcpu *vcpu)
6700 {
6701 int err;
6702
6703 err = fpu_alloc(&vcpu->arch.guest_fpu);
6704 if (err)
6705 return err;
6706
6707 fpu_finit(&vcpu->arch.guest_fpu);
6708
6709 /*
6710 * Ensure guest xcr0 is valid for loading
6711 */
6712 vcpu->arch.xcr0 = XSTATE_FP;
6713
6714 vcpu->arch.cr0 |= X86_CR0_ET;
6715
6716 return 0;
6717 }
6718 EXPORT_SYMBOL_GPL(fx_init);
6719
6720 static void fx_free(struct kvm_vcpu *vcpu)
6721 {
6722 fpu_free(&vcpu->arch.guest_fpu);
6723 }
6724
6725 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6726 {
6727 if (vcpu->guest_fpu_loaded)
6728 return;
6729
6730 /*
6731 * Restore all possible states in the guest,
6732 * and assume host would use all available bits.
6733 * Guest xcr0 would be loaded later.
6734 */
6735 kvm_put_guest_xcr0(vcpu);
6736 vcpu->guest_fpu_loaded = 1;
6737 __kernel_fpu_begin();
6738 fpu_restore_checking(&vcpu->arch.guest_fpu);
6739 trace_kvm_fpu(1);
6740 }
6741
6742 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6743 {
6744 kvm_put_guest_xcr0(vcpu);
6745
6746 if (!vcpu->guest_fpu_loaded)
6747 return;
6748
6749 vcpu->guest_fpu_loaded = 0;
6750 fpu_save_init(&vcpu->arch.guest_fpu);
6751 __kernel_fpu_end();
6752 ++vcpu->stat.fpu_reload;
6753 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6754 trace_kvm_fpu(0);
6755 }
6756
6757 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6758 {
6759 kvmclock_reset(vcpu);
6760
6761 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6762 fx_free(vcpu);
6763 kvm_x86_ops->vcpu_free(vcpu);
6764 }
6765
6766 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6767 unsigned int id)
6768 {
6769 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6770 printk_once(KERN_WARNING
6771 "kvm: SMP vm created on host with unstable TSC; "
6772 "guest TSC will not be reliable\n");
6773 return kvm_x86_ops->vcpu_create(kvm, id);
6774 }
6775
6776 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6777 {
6778 int r;
6779
6780 vcpu->arch.mtrr_state.have_fixed = 1;
6781 r = vcpu_load(vcpu);
6782 if (r)
6783 return r;
6784 kvm_vcpu_reset(vcpu);
6785 kvm_mmu_setup(vcpu);
6786 vcpu_put(vcpu);
6787
6788 return r;
6789 }
6790
6791 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6792 {
6793 int r;
6794 struct msr_data msr;
6795 struct kvm *kvm = vcpu->kvm;
6796
6797 r = vcpu_load(vcpu);
6798 if (r)
6799 return r;
6800 msr.data = 0x0;
6801 msr.index = MSR_IA32_TSC;
6802 msr.host_initiated = true;
6803 kvm_write_tsc(vcpu, &msr);
6804 vcpu_put(vcpu);
6805
6806 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6807 KVMCLOCK_SYNC_PERIOD);
6808
6809 return r;
6810 }
6811
6812 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6813 {
6814 int r;
6815 vcpu->arch.apf.msr_val = 0;
6816
6817 r = vcpu_load(vcpu);
6818 BUG_ON(r);
6819 kvm_mmu_unload(vcpu);
6820 vcpu_put(vcpu);
6821
6822 fx_free(vcpu);
6823 kvm_x86_ops->vcpu_free(vcpu);
6824 }
6825
6826 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6827 {
6828 atomic_set(&vcpu->arch.nmi_queued, 0);
6829 vcpu->arch.nmi_pending = 0;
6830 vcpu->arch.nmi_injected = false;
6831
6832 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6833 vcpu->arch.dr6 = DR6_FIXED_1;
6834 kvm_update_dr6(vcpu);
6835 vcpu->arch.dr7 = DR7_FIXED_1;
6836 kvm_update_dr7(vcpu);
6837
6838 kvm_make_request(KVM_REQ_EVENT, vcpu);
6839 vcpu->arch.apf.msr_val = 0;
6840 vcpu->arch.st.msr_val = 0;
6841
6842 kvmclock_reset(vcpu);
6843
6844 kvm_clear_async_pf_completion_queue(vcpu);
6845 kvm_async_pf_hash_reset(vcpu);
6846 vcpu->arch.apf.halted = false;
6847
6848 kvm_pmu_reset(vcpu);
6849
6850 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6851 vcpu->arch.regs_avail = ~0;
6852 vcpu->arch.regs_dirty = ~0;
6853
6854 kvm_x86_ops->vcpu_reset(vcpu);
6855 }
6856
6857 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6858 {
6859 struct kvm_segment cs;
6860
6861 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6862 cs.selector = vector << 8;
6863 cs.base = vector << 12;
6864 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6865 kvm_rip_write(vcpu, 0);
6866 }
6867
6868 int kvm_arch_hardware_enable(void *garbage)
6869 {
6870 struct kvm *kvm;
6871 struct kvm_vcpu *vcpu;
6872 int i;
6873 int ret;
6874 u64 local_tsc;
6875 u64 max_tsc = 0;
6876 bool stable, backwards_tsc = false;
6877
6878 kvm_shared_msr_cpu_online();
6879 ret = kvm_x86_ops->hardware_enable(garbage);
6880 if (ret != 0)
6881 return ret;
6882
6883 local_tsc = native_read_tsc();
6884 stable = !check_tsc_unstable();
6885 list_for_each_entry(kvm, &vm_list, vm_list) {
6886 kvm_for_each_vcpu(i, vcpu, kvm) {
6887 if (!stable && vcpu->cpu == smp_processor_id())
6888 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6889 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6890 backwards_tsc = true;
6891 if (vcpu->arch.last_host_tsc > max_tsc)
6892 max_tsc = vcpu->arch.last_host_tsc;
6893 }
6894 }
6895 }
6896
6897 /*
6898 * Sometimes, even reliable TSCs go backwards. This happens on
6899 * platforms that reset TSC during suspend or hibernate actions, but
6900 * maintain synchronization. We must compensate. Fortunately, we can
6901 * detect that condition here, which happens early in CPU bringup,
6902 * before any KVM threads can be running. Unfortunately, we can't
6903 * bring the TSCs fully up to date with real time, as we aren't yet far
6904 * enough into CPU bringup that we know how much real time has actually
6905 * elapsed; our helper function, get_kernel_ns() will be using boot
6906 * variables that haven't been updated yet.
6907 *
6908 * So we simply find the maximum observed TSC above, then record the
6909 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6910 * the adjustment will be applied. Note that we accumulate
6911 * adjustments, in case multiple suspend cycles happen before some VCPU
6912 * gets a chance to run again. In the event that no KVM threads get a
6913 * chance to run, we will miss the entire elapsed period, as we'll have
6914 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6915 * loose cycle time. This isn't too big a deal, since the loss will be
6916 * uniform across all VCPUs (not to mention the scenario is extremely
6917 * unlikely). It is possible that a second hibernate recovery happens
6918 * much faster than a first, causing the observed TSC here to be
6919 * smaller; this would require additional padding adjustment, which is
6920 * why we set last_host_tsc to the local tsc observed here.
6921 *
6922 * N.B. - this code below runs only on platforms with reliable TSC,
6923 * as that is the only way backwards_tsc is set above. Also note
6924 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6925 * have the same delta_cyc adjustment applied if backwards_tsc
6926 * is detected. Note further, this adjustment is only done once,
6927 * as we reset last_host_tsc on all VCPUs to stop this from being
6928 * called multiple times (one for each physical CPU bringup).
6929 *
6930 * Platforms with unreliable TSCs don't have to deal with this, they
6931 * will be compensated by the logic in vcpu_load, which sets the TSC to
6932 * catchup mode. This will catchup all VCPUs to real time, but cannot
6933 * guarantee that they stay in perfect synchronization.
6934 */
6935 if (backwards_tsc) {
6936 u64 delta_cyc = max_tsc - local_tsc;
6937 list_for_each_entry(kvm, &vm_list, vm_list) {
6938 kvm_for_each_vcpu(i, vcpu, kvm) {
6939 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6940 vcpu->arch.last_host_tsc = local_tsc;
6941 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6942 &vcpu->requests);
6943 }
6944
6945 /*
6946 * We have to disable TSC offset matching.. if you were
6947 * booting a VM while issuing an S4 host suspend....
6948 * you may have some problem. Solving this issue is
6949 * left as an exercise to the reader.
6950 */
6951 kvm->arch.last_tsc_nsec = 0;
6952 kvm->arch.last_tsc_write = 0;
6953 }
6954
6955 }
6956 return 0;
6957 }
6958
6959 void kvm_arch_hardware_disable(void *garbage)
6960 {
6961 kvm_x86_ops->hardware_disable(garbage);
6962 drop_user_return_notifiers(garbage);
6963 }
6964
6965 int kvm_arch_hardware_setup(void)
6966 {
6967 return kvm_x86_ops->hardware_setup();
6968 }
6969
6970 void kvm_arch_hardware_unsetup(void)
6971 {
6972 kvm_x86_ops->hardware_unsetup();
6973 }
6974
6975 void kvm_arch_check_processor_compat(void *rtn)
6976 {
6977 kvm_x86_ops->check_processor_compatibility(rtn);
6978 }
6979
6980 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6981 {
6982 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6983 }
6984
6985 struct static_key kvm_no_apic_vcpu __read_mostly;
6986
6987 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6988 {
6989 struct page *page;
6990 struct kvm *kvm;
6991 int r;
6992
6993 BUG_ON(vcpu->kvm == NULL);
6994 kvm = vcpu->kvm;
6995
6996 vcpu->arch.pv.pv_unhalted = false;
6997 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6998 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6999 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7000 else
7001 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7002
7003 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7004 if (!page) {
7005 r = -ENOMEM;
7006 goto fail;
7007 }
7008 vcpu->arch.pio_data = page_address(page);
7009
7010 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7011
7012 r = kvm_mmu_create(vcpu);
7013 if (r < 0)
7014 goto fail_free_pio_data;
7015
7016 if (irqchip_in_kernel(kvm)) {
7017 r = kvm_create_lapic(vcpu);
7018 if (r < 0)
7019 goto fail_mmu_destroy;
7020 } else
7021 static_key_slow_inc(&kvm_no_apic_vcpu);
7022
7023 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7024 GFP_KERNEL);
7025 if (!vcpu->arch.mce_banks) {
7026 r = -ENOMEM;
7027 goto fail_free_lapic;
7028 }
7029 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7030
7031 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7032 r = -ENOMEM;
7033 goto fail_free_mce_banks;
7034 }
7035
7036 r = fx_init(vcpu);
7037 if (r)
7038 goto fail_free_wbinvd_dirty_mask;
7039
7040 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7041 vcpu->arch.pv_time_enabled = false;
7042
7043 vcpu->arch.guest_supported_xcr0 = 0;
7044 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7045
7046 kvm_async_pf_hash_reset(vcpu);
7047 kvm_pmu_init(vcpu);
7048
7049 return 0;
7050 fail_free_wbinvd_dirty_mask:
7051 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7052 fail_free_mce_banks:
7053 kfree(vcpu->arch.mce_banks);
7054 fail_free_lapic:
7055 kvm_free_lapic(vcpu);
7056 fail_mmu_destroy:
7057 kvm_mmu_destroy(vcpu);
7058 fail_free_pio_data:
7059 free_page((unsigned long)vcpu->arch.pio_data);
7060 fail:
7061 return r;
7062 }
7063
7064 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7065 {
7066 int idx;
7067
7068 kvm_pmu_destroy(vcpu);
7069 kfree(vcpu->arch.mce_banks);
7070 kvm_free_lapic(vcpu);
7071 idx = srcu_read_lock(&vcpu->kvm->srcu);
7072 kvm_mmu_destroy(vcpu);
7073 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7074 free_page((unsigned long)vcpu->arch.pio_data);
7075 if (!irqchip_in_kernel(vcpu->kvm))
7076 static_key_slow_dec(&kvm_no_apic_vcpu);
7077 }
7078
7079 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7080 {
7081 if (type)
7082 return -EINVAL;
7083
7084 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7085 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7086 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7087 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7088
7089 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7090 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7091 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7092 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7093 &kvm->arch.irq_sources_bitmap);
7094
7095 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7096 mutex_init(&kvm->arch.apic_map_lock);
7097 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7098
7099 pvclock_update_vm_gtod_copy(kvm);
7100
7101 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7102 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7103
7104 return 0;
7105 }
7106
7107 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7108 {
7109 int r;
7110 r = vcpu_load(vcpu);
7111 BUG_ON(r);
7112 kvm_mmu_unload(vcpu);
7113 vcpu_put(vcpu);
7114 }
7115
7116 static void kvm_free_vcpus(struct kvm *kvm)
7117 {
7118 unsigned int i;
7119 struct kvm_vcpu *vcpu;
7120
7121 /*
7122 * Unpin any mmu pages first.
7123 */
7124 kvm_for_each_vcpu(i, vcpu, kvm) {
7125 kvm_clear_async_pf_completion_queue(vcpu);
7126 kvm_unload_vcpu_mmu(vcpu);
7127 }
7128 kvm_for_each_vcpu(i, vcpu, kvm)
7129 kvm_arch_vcpu_free(vcpu);
7130
7131 mutex_lock(&kvm->lock);
7132 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7133 kvm->vcpus[i] = NULL;
7134
7135 atomic_set(&kvm->online_vcpus, 0);
7136 mutex_unlock(&kvm->lock);
7137 }
7138
7139 void kvm_arch_sync_events(struct kvm *kvm)
7140 {
7141 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7142 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7143 kvm_free_all_assigned_devices(kvm);
7144 kvm_free_pit(kvm);
7145 }
7146
7147 void kvm_arch_destroy_vm(struct kvm *kvm)
7148 {
7149 if (current->mm == kvm->mm) {
7150 /*
7151 * Free memory regions allocated on behalf of userspace,
7152 * unless the the memory map has changed due to process exit
7153 * or fd copying.
7154 */
7155 struct kvm_userspace_memory_region mem;
7156 memset(&mem, 0, sizeof(mem));
7157 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7158 kvm_set_memory_region(kvm, &mem);
7159
7160 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7161 kvm_set_memory_region(kvm, &mem);
7162
7163 mem.slot = TSS_PRIVATE_MEMSLOT;
7164 kvm_set_memory_region(kvm, &mem);
7165 }
7166 kvm_iommu_unmap_guest(kvm);
7167 kfree(kvm->arch.vpic);
7168 kfree(kvm->arch.vioapic);
7169 kvm_free_vcpus(kvm);
7170 if (kvm->arch.apic_access_page)
7171 put_page(kvm->arch.apic_access_page);
7172 if (kvm->arch.ept_identity_pagetable)
7173 put_page(kvm->arch.ept_identity_pagetable);
7174 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7175 }
7176
7177 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7178 struct kvm_memory_slot *dont)
7179 {
7180 int i;
7181
7182 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7183 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7184 kvm_kvfree(free->arch.rmap[i]);
7185 free->arch.rmap[i] = NULL;
7186 }
7187 if (i == 0)
7188 continue;
7189
7190 if (!dont || free->arch.lpage_info[i - 1] !=
7191 dont->arch.lpage_info[i - 1]) {
7192 kvm_kvfree(free->arch.lpage_info[i - 1]);
7193 free->arch.lpage_info[i - 1] = NULL;
7194 }
7195 }
7196 }
7197
7198 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7199 unsigned long npages)
7200 {
7201 int i;
7202
7203 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7204 unsigned long ugfn;
7205 int lpages;
7206 int level = i + 1;
7207
7208 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7209 slot->base_gfn, level) + 1;
7210
7211 slot->arch.rmap[i] =
7212 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7213 if (!slot->arch.rmap[i])
7214 goto out_free;
7215 if (i == 0)
7216 continue;
7217
7218 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7219 sizeof(*slot->arch.lpage_info[i - 1]));
7220 if (!slot->arch.lpage_info[i - 1])
7221 goto out_free;
7222
7223 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7224 slot->arch.lpage_info[i - 1][0].write_count = 1;
7225 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7226 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7227 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7228 /*
7229 * If the gfn and userspace address are not aligned wrt each
7230 * other, or if explicitly asked to, disable large page
7231 * support for this slot
7232 */
7233 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7234 !kvm_largepages_enabled()) {
7235 unsigned long j;
7236
7237 for (j = 0; j < lpages; ++j)
7238 slot->arch.lpage_info[i - 1][j].write_count = 1;
7239 }
7240 }
7241
7242 return 0;
7243
7244 out_free:
7245 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7246 kvm_kvfree(slot->arch.rmap[i]);
7247 slot->arch.rmap[i] = NULL;
7248 if (i == 0)
7249 continue;
7250
7251 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7252 slot->arch.lpage_info[i - 1] = NULL;
7253 }
7254 return -ENOMEM;
7255 }
7256
7257 void kvm_arch_memslots_updated(struct kvm *kvm)
7258 {
7259 /*
7260 * memslots->generation has been incremented.
7261 * mmio generation may have reached its maximum value.
7262 */
7263 kvm_mmu_invalidate_mmio_sptes(kvm);
7264 }
7265
7266 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7267 struct kvm_memory_slot *memslot,
7268 struct kvm_userspace_memory_region *mem,
7269 enum kvm_mr_change change)
7270 {
7271 /*
7272 * Only private memory slots need to be mapped here since
7273 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7274 */
7275 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7276 unsigned long userspace_addr;
7277
7278 /*
7279 * MAP_SHARED to prevent internal slot pages from being moved
7280 * by fork()/COW.
7281 */
7282 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7283 PROT_READ | PROT_WRITE,
7284 MAP_SHARED | MAP_ANONYMOUS, 0);
7285
7286 if (IS_ERR((void *)userspace_addr))
7287 return PTR_ERR((void *)userspace_addr);
7288
7289 memslot->userspace_addr = userspace_addr;
7290 }
7291
7292 return 0;
7293 }
7294
7295 void kvm_arch_commit_memory_region(struct kvm *kvm,
7296 struct kvm_userspace_memory_region *mem,
7297 const struct kvm_memory_slot *old,
7298 enum kvm_mr_change change)
7299 {
7300
7301 int nr_mmu_pages = 0;
7302
7303 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7304 int ret;
7305
7306 ret = vm_munmap(old->userspace_addr,
7307 old->npages * PAGE_SIZE);
7308 if (ret < 0)
7309 printk(KERN_WARNING
7310 "kvm_vm_ioctl_set_memory_region: "
7311 "failed to munmap memory\n");
7312 }
7313
7314 if (!kvm->arch.n_requested_mmu_pages)
7315 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7316
7317 if (nr_mmu_pages)
7318 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7319 /*
7320 * Write protect all pages for dirty logging.
7321 * Existing largepage mappings are destroyed here and new ones will
7322 * not be created until the end of the logging.
7323 */
7324 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7325 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7326 }
7327
7328 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7329 {
7330 kvm_mmu_invalidate_zap_all_pages(kvm);
7331 }
7332
7333 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7334 struct kvm_memory_slot *slot)
7335 {
7336 kvm_mmu_invalidate_zap_all_pages(kvm);
7337 }
7338
7339 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7340 {
7341 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7342 kvm_x86_ops->check_nested_events(vcpu, false);
7343
7344 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7345 !vcpu->arch.apf.halted)
7346 || !list_empty_careful(&vcpu->async_pf.done)
7347 || kvm_apic_has_events(vcpu)
7348 || vcpu->arch.pv.pv_unhalted
7349 || atomic_read(&vcpu->arch.nmi_queued) ||
7350 (kvm_arch_interrupt_allowed(vcpu) &&
7351 kvm_cpu_has_interrupt(vcpu));
7352 }
7353
7354 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7355 {
7356 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7357 }
7358
7359 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7360 {
7361 return kvm_x86_ops->interrupt_allowed(vcpu);
7362 }
7363
7364 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7365 {
7366 unsigned long current_rip = kvm_rip_read(vcpu) +
7367 get_segment_base(vcpu, VCPU_SREG_CS);
7368
7369 return current_rip == linear_rip;
7370 }
7371 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7372
7373 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7374 {
7375 unsigned long rflags;
7376
7377 rflags = kvm_x86_ops->get_rflags(vcpu);
7378 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7379 rflags &= ~X86_EFLAGS_TF;
7380 return rflags;
7381 }
7382 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7383
7384 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7385 {
7386 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7387 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7388 rflags |= X86_EFLAGS_TF;
7389 kvm_x86_ops->set_rflags(vcpu, rflags);
7390 kvm_make_request(KVM_REQ_EVENT, vcpu);
7391 }
7392 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7393
7394 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7395 {
7396 int r;
7397
7398 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7399 work->wakeup_all)
7400 return;
7401
7402 r = kvm_mmu_reload(vcpu);
7403 if (unlikely(r))
7404 return;
7405
7406 if (!vcpu->arch.mmu.direct_map &&
7407 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7408 return;
7409
7410 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7411 }
7412
7413 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7414 {
7415 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7416 }
7417
7418 static inline u32 kvm_async_pf_next_probe(u32 key)
7419 {
7420 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7421 }
7422
7423 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7424 {
7425 u32 key = kvm_async_pf_hash_fn(gfn);
7426
7427 while (vcpu->arch.apf.gfns[key] != ~0)
7428 key = kvm_async_pf_next_probe(key);
7429
7430 vcpu->arch.apf.gfns[key] = gfn;
7431 }
7432
7433 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7434 {
7435 int i;
7436 u32 key = kvm_async_pf_hash_fn(gfn);
7437
7438 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7439 (vcpu->arch.apf.gfns[key] != gfn &&
7440 vcpu->arch.apf.gfns[key] != ~0); i++)
7441 key = kvm_async_pf_next_probe(key);
7442
7443 return key;
7444 }
7445
7446 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7447 {
7448 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7449 }
7450
7451 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7452 {
7453 u32 i, j, k;
7454
7455 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7456 while (true) {
7457 vcpu->arch.apf.gfns[i] = ~0;
7458 do {
7459 j = kvm_async_pf_next_probe(j);
7460 if (vcpu->arch.apf.gfns[j] == ~0)
7461 return;
7462 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7463 /*
7464 * k lies cyclically in ]i,j]
7465 * | i.k.j |
7466 * |....j i.k.| or |.k..j i...|
7467 */
7468 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7469 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7470 i = j;
7471 }
7472 }
7473
7474 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7475 {
7476
7477 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7478 sizeof(val));
7479 }
7480
7481 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7482 struct kvm_async_pf *work)
7483 {
7484 struct x86_exception fault;
7485
7486 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7487 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7488
7489 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7490 (vcpu->arch.apf.send_user_only &&
7491 kvm_x86_ops->get_cpl(vcpu) == 0))
7492 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7493 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7494 fault.vector = PF_VECTOR;
7495 fault.error_code_valid = true;
7496 fault.error_code = 0;
7497 fault.nested_page_fault = false;
7498 fault.address = work->arch.token;
7499 kvm_inject_page_fault(vcpu, &fault);
7500 }
7501 }
7502
7503 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7504 struct kvm_async_pf *work)
7505 {
7506 struct x86_exception fault;
7507
7508 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7509 if (work->wakeup_all)
7510 work->arch.token = ~0; /* broadcast wakeup */
7511 else
7512 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7513
7514 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7515 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7516 fault.vector = PF_VECTOR;
7517 fault.error_code_valid = true;
7518 fault.error_code = 0;
7519 fault.nested_page_fault = false;
7520 fault.address = work->arch.token;
7521 kvm_inject_page_fault(vcpu, &fault);
7522 }
7523 vcpu->arch.apf.halted = false;
7524 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7525 }
7526
7527 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7528 {
7529 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7530 return true;
7531 else
7532 return !kvm_event_needs_reinjection(vcpu) &&
7533 kvm_x86_ops->interrupt_allowed(vcpu);
7534 }
7535
7536 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7537 {
7538 atomic_inc(&kvm->arch.noncoherent_dma_count);
7539 }
7540 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7541
7542 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7543 {
7544 atomic_dec(&kvm->arch.noncoherent_dma_count);
7545 }
7546 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7547
7548 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7549 {
7550 return atomic_read(&kvm->arch.noncoherent_dma_count);
7551 }
7552 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7553
7554 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7555 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7556 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7557 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7558 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7559 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7560 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7561 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7562 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7563 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7564 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7565 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
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