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KVM: x86/xen: Fix __user pointer handling for hypercall page installation
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19 #include <linux/kvm_host.h>
20 #include "irq.h"
21 #include "ioapic.h"
22 #include "mmu.h"
23 #include "i8254.h"
24 #include "tss.h"
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
27 #include "x86.h"
28 #include "cpuid.h"
29 #include "pmu.h"
30 #include "hyperv.h"
31 #include "lapic.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
60
61 #include <trace/events/kvm.h>
62
63 #include <asm/debugreg.h>
64 #include <asm/msr.h>
65 #include <asm/desc.h>
66 #include <asm/mce.h>
67 #include <linux/kernel_stat.h>
68 #include <asm/fpu/internal.h> /* Ugh! */
69 #include <asm/pvclock.h>
70 #include <asm/div64.h>
71 #include <asm/irq_remapping.h>
72 #include <asm/mshyperv.h>
73 #include <asm/hypervisor.h>
74 #include <asm/tlbflush.h>
75 #include <asm/intel_pt.h>
76 #include <asm/emulate_prefix.h>
77 #include <clocksource/hyperv_timer.h>
78
79 #define CREATE_TRACE_POINTS
80 #include "trace.h"
81
82 #define MAX_IO_MSRS 256
83 #define KVM_MAX_MCE_BANKS 32
84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
86
87 #define emul_to_vcpu(ctxt) \
88 ((struct kvm_vcpu *)(ctxt)->vcpu)
89
90 /* EFER defaults:
91 * - enable syscall per default because its emulated by KVM
92 * - enable LME and LMA per default on 64 bit KVM
93 */
94 #ifdef CONFIG_X86_64
95 static
96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
97 #else
98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
99 #endif
100
101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
102
103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
105
106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
107 static void process_nmi(struct kvm_vcpu *vcpu);
108 static void process_smi(struct kvm_vcpu *vcpu);
109 static void enter_smm(struct kvm_vcpu *vcpu);
110 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
111 static void store_regs(struct kvm_vcpu *vcpu);
112 static int sync_regs(struct kvm_vcpu *vcpu);
113
114 struct kvm_x86_ops kvm_x86_ops __read_mostly;
115 EXPORT_SYMBOL_GPL(kvm_x86_ops);
116
117 #define KVM_X86_OP(func) \
118 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
119 *(((struct kvm_x86_ops *)0)->func));
120 #define KVM_X86_OP_NULL KVM_X86_OP
121 #include <asm/kvm-x86-ops.h>
122 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
123 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
124 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current);
125
126 static bool __read_mostly ignore_msrs = 0;
127 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
128
129 bool __read_mostly report_ignored_msrs = true;
130 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
131 EXPORT_SYMBOL_GPL(report_ignored_msrs);
132
133 unsigned int min_timer_period_us = 200;
134 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
135
136 static bool __read_mostly kvmclock_periodic_sync = true;
137 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
138
139 bool __read_mostly kvm_has_tsc_control;
140 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
141 u32 __read_mostly kvm_max_guest_tsc_khz;
142 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
143 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
144 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
145 u64 __read_mostly kvm_max_tsc_scaling_ratio;
146 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
147 u64 __read_mostly kvm_default_tsc_scaling_ratio;
148 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
149 bool __read_mostly kvm_has_bus_lock_exit;
150 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit);
151
152 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
153 static u32 __read_mostly tsc_tolerance_ppm = 250;
154 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
155
156 /*
157 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
158 * adaptive tuning starting from default advancment of 1000ns. '0' disables
159 * advancement entirely. Any other value is used as-is and disables adaptive
160 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
161 */
162 static int __read_mostly lapic_timer_advance_ns = -1;
163 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
164
165 static bool __read_mostly vector_hashing = true;
166 module_param(vector_hashing, bool, S_IRUGO);
167
168 bool __read_mostly enable_vmware_backdoor = false;
169 module_param(enable_vmware_backdoor, bool, S_IRUGO);
170 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
171
172 static bool __read_mostly force_emulation_prefix = false;
173 module_param(force_emulation_prefix, bool, S_IRUGO);
174
175 int __read_mostly pi_inject_timer = -1;
176 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
177
178 /*
179 * Restoring the host value for MSRs that are only consumed when running in
180 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
181 * returns to userspace, i.e. the kernel can run with the guest's value.
182 */
183 #define KVM_MAX_NR_USER_RETURN_MSRS 16
184
185 struct kvm_user_return_msrs_global {
186 int nr;
187 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
188 };
189
190 struct kvm_user_return_msrs {
191 struct user_return_notifier urn;
192 bool registered;
193 struct kvm_user_return_msr_values {
194 u64 host;
195 u64 curr;
196 } values[KVM_MAX_NR_USER_RETURN_MSRS];
197 };
198
199 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
200 static struct kvm_user_return_msrs __percpu *user_return_msrs;
201
202 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
203 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
204 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
205 | XFEATURE_MASK_PKRU)
206
207 u64 __read_mostly host_efer;
208 EXPORT_SYMBOL_GPL(host_efer);
209
210 bool __read_mostly allow_smaller_maxphyaddr = 0;
211 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
212
213 u64 __read_mostly host_xss;
214 EXPORT_SYMBOL_GPL(host_xss);
215 u64 __read_mostly supported_xss;
216 EXPORT_SYMBOL_GPL(supported_xss);
217
218 struct kvm_stats_debugfs_item debugfs_entries[] = {
219 VCPU_STAT("pf_fixed", pf_fixed),
220 VCPU_STAT("pf_guest", pf_guest),
221 VCPU_STAT("tlb_flush", tlb_flush),
222 VCPU_STAT("invlpg", invlpg),
223 VCPU_STAT("exits", exits),
224 VCPU_STAT("io_exits", io_exits),
225 VCPU_STAT("mmio_exits", mmio_exits),
226 VCPU_STAT("signal_exits", signal_exits),
227 VCPU_STAT("irq_window", irq_window_exits),
228 VCPU_STAT("nmi_window", nmi_window_exits),
229 VCPU_STAT("halt_exits", halt_exits),
230 VCPU_STAT("halt_successful_poll", halt_successful_poll),
231 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
232 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
233 VCPU_STAT("halt_wakeup", halt_wakeup),
234 VCPU_STAT("hypercalls", hypercalls),
235 VCPU_STAT("request_irq", request_irq_exits),
236 VCPU_STAT("irq_exits", irq_exits),
237 VCPU_STAT("host_state_reload", host_state_reload),
238 VCPU_STAT("fpu_reload", fpu_reload),
239 VCPU_STAT("insn_emulation", insn_emulation),
240 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
241 VCPU_STAT("irq_injections", irq_injections),
242 VCPU_STAT("nmi_injections", nmi_injections),
243 VCPU_STAT("req_event", req_event),
244 VCPU_STAT("l1d_flush", l1d_flush),
245 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
246 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
247 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
248 VM_STAT("mmu_pte_write", mmu_pte_write),
249 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
250 VM_STAT("mmu_flooded", mmu_flooded),
251 VM_STAT("mmu_recycled", mmu_recycled),
252 VM_STAT("mmu_cache_miss", mmu_cache_miss),
253 VM_STAT("mmu_unsync", mmu_unsync),
254 VM_STAT("remote_tlb_flush", remote_tlb_flush),
255 VM_STAT("largepages", lpages, .mode = 0444),
256 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
257 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
258 { NULL }
259 };
260
261 u64 __read_mostly host_xcr0;
262 u64 __read_mostly supported_xcr0;
263 EXPORT_SYMBOL_GPL(supported_xcr0);
264
265 static struct kmem_cache *x86_fpu_cache;
266
267 static struct kmem_cache *x86_emulator_cache;
268
269 /*
270 * When called, it means the previous get/set msr reached an invalid msr.
271 * Return true if we want to ignore/silent this failed msr access.
272 */
273 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
274 u64 data, bool write)
275 {
276 const char *op = write ? "wrmsr" : "rdmsr";
277
278 if (ignore_msrs) {
279 if (report_ignored_msrs)
280 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
281 op, msr, data);
282 /* Mask the error */
283 return true;
284 } else {
285 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
286 op, msr, data);
287 return false;
288 }
289 }
290
291 static struct kmem_cache *kvm_alloc_emulator_cache(void)
292 {
293 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
294 unsigned int size = sizeof(struct x86_emulate_ctxt);
295
296 return kmem_cache_create_usercopy("x86_emulator", size,
297 __alignof__(struct x86_emulate_ctxt),
298 SLAB_ACCOUNT, useroffset,
299 size - useroffset, NULL);
300 }
301
302 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
303
304 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
305 {
306 int i;
307 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
308 vcpu->arch.apf.gfns[i] = ~0;
309 }
310
311 static void kvm_on_user_return(struct user_return_notifier *urn)
312 {
313 unsigned slot;
314 struct kvm_user_return_msrs *msrs
315 = container_of(urn, struct kvm_user_return_msrs, urn);
316 struct kvm_user_return_msr_values *values;
317 unsigned long flags;
318
319 /*
320 * Disabling irqs at this point since the following code could be
321 * interrupted and executed through kvm_arch_hardware_disable()
322 */
323 local_irq_save(flags);
324 if (msrs->registered) {
325 msrs->registered = false;
326 user_return_notifier_unregister(urn);
327 }
328 local_irq_restore(flags);
329 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
330 values = &msrs->values[slot];
331 if (values->host != values->curr) {
332 wrmsrl(user_return_msrs_global.msrs[slot], values->host);
333 values->curr = values->host;
334 }
335 }
336 }
337
338 void kvm_define_user_return_msr(unsigned slot, u32 msr)
339 {
340 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
341 user_return_msrs_global.msrs[slot] = msr;
342 if (slot >= user_return_msrs_global.nr)
343 user_return_msrs_global.nr = slot + 1;
344 }
345 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
346
347 static void kvm_user_return_msr_cpu_online(void)
348 {
349 unsigned int cpu = smp_processor_id();
350 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
351 u64 value;
352 int i;
353
354 for (i = 0; i < user_return_msrs_global.nr; ++i) {
355 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
356 msrs->values[i].host = value;
357 msrs->values[i].curr = value;
358 }
359 }
360
361 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
362 {
363 unsigned int cpu = smp_processor_id();
364 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
365 int err;
366
367 value = (value & mask) | (msrs->values[slot].host & ~mask);
368 if (value == msrs->values[slot].curr)
369 return 0;
370 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
371 if (err)
372 return 1;
373
374 msrs->values[slot].curr = value;
375 if (!msrs->registered) {
376 msrs->urn.on_user_return = kvm_on_user_return;
377 user_return_notifier_register(&msrs->urn);
378 msrs->registered = true;
379 }
380 return 0;
381 }
382 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
383
384 static void drop_user_return_notifiers(void)
385 {
386 unsigned int cpu = smp_processor_id();
387 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
388
389 if (msrs->registered)
390 kvm_on_user_return(&msrs->urn);
391 }
392
393 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
394 {
395 return vcpu->arch.apic_base;
396 }
397 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
398
399 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
400 {
401 return kvm_apic_mode(kvm_get_apic_base(vcpu));
402 }
403 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
404
405 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
406 {
407 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
408 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
409 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
410 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
411
412 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
413 return 1;
414 if (!msr_info->host_initiated) {
415 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
416 return 1;
417 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
418 return 1;
419 }
420
421 kvm_lapic_set_base(vcpu, msr_info->data);
422 kvm_recalculate_apic_map(vcpu->kvm);
423 return 0;
424 }
425 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
426
427 asmlinkage __visible noinstr void kvm_spurious_fault(void)
428 {
429 /* Fault while not rebooting. We want the trace. */
430 BUG_ON(!kvm_rebooting);
431 }
432 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
433
434 #define EXCPT_BENIGN 0
435 #define EXCPT_CONTRIBUTORY 1
436 #define EXCPT_PF 2
437
438 static int exception_class(int vector)
439 {
440 switch (vector) {
441 case PF_VECTOR:
442 return EXCPT_PF;
443 case DE_VECTOR:
444 case TS_VECTOR:
445 case NP_VECTOR:
446 case SS_VECTOR:
447 case GP_VECTOR:
448 return EXCPT_CONTRIBUTORY;
449 default:
450 break;
451 }
452 return EXCPT_BENIGN;
453 }
454
455 #define EXCPT_FAULT 0
456 #define EXCPT_TRAP 1
457 #define EXCPT_ABORT 2
458 #define EXCPT_INTERRUPT 3
459
460 static int exception_type(int vector)
461 {
462 unsigned int mask;
463
464 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
465 return EXCPT_INTERRUPT;
466
467 mask = 1 << vector;
468
469 /* #DB is trap, as instruction watchpoints are handled elsewhere */
470 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
471 return EXCPT_TRAP;
472
473 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
474 return EXCPT_ABORT;
475
476 /* Reserved exceptions will result in fault */
477 return EXCPT_FAULT;
478 }
479
480 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
481 {
482 unsigned nr = vcpu->arch.exception.nr;
483 bool has_payload = vcpu->arch.exception.has_payload;
484 unsigned long payload = vcpu->arch.exception.payload;
485
486 if (!has_payload)
487 return;
488
489 switch (nr) {
490 case DB_VECTOR:
491 /*
492 * "Certain debug exceptions may clear bit 0-3. The
493 * remaining contents of the DR6 register are never
494 * cleared by the processor".
495 */
496 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
497 /*
498 * In order to reflect the #DB exception payload in guest
499 * dr6, three components need to be considered: active low
500 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
501 * DR6_BS and DR6_BT)
502 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
503 * In the target guest dr6:
504 * FIXED_1 bits should always be set.
505 * Active low bits should be cleared if 1-setting in payload.
506 * Active high bits should be set if 1-setting in payload.
507 *
508 * Note, the payload is compatible with the pending debug
509 * exceptions/exit qualification under VMX, that active_low bits
510 * are active high in payload.
511 * So they need to be flipped for DR6.
512 */
513 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
514 vcpu->arch.dr6 |= payload;
515 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW;
516
517 /*
518 * The #DB payload is defined as compatible with the 'pending
519 * debug exceptions' field under VMX, not DR6. While bit 12 is
520 * defined in the 'pending debug exceptions' field (enabled
521 * breakpoint), it is reserved and must be zero in DR6.
522 */
523 vcpu->arch.dr6 &= ~BIT(12);
524 break;
525 case PF_VECTOR:
526 vcpu->arch.cr2 = payload;
527 break;
528 }
529
530 vcpu->arch.exception.has_payload = false;
531 vcpu->arch.exception.payload = 0;
532 }
533 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
534
535 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
536 unsigned nr, bool has_error, u32 error_code,
537 bool has_payload, unsigned long payload, bool reinject)
538 {
539 u32 prev_nr;
540 int class1, class2;
541
542 kvm_make_request(KVM_REQ_EVENT, vcpu);
543
544 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
545 queue:
546 if (has_error && !is_protmode(vcpu))
547 has_error = false;
548 if (reinject) {
549 /*
550 * On vmentry, vcpu->arch.exception.pending is only
551 * true if an event injection was blocked by
552 * nested_run_pending. In that case, however,
553 * vcpu_enter_guest requests an immediate exit,
554 * and the guest shouldn't proceed far enough to
555 * need reinjection.
556 */
557 WARN_ON_ONCE(vcpu->arch.exception.pending);
558 vcpu->arch.exception.injected = true;
559 if (WARN_ON_ONCE(has_payload)) {
560 /*
561 * A reinjected event has already
562 * delivered its payload.
563 */
564 has_payload = false;
565 payload = 0;
566 }
567 } else {
568 vcpu->arch.exception.pending = true;
569 vcpu->arch.exception.injected = false;
570 }
571 vcpu->arch.exception.has_error_code = has_error;
572 vcpu->arch.exception.nr = nr;
573 vcpu->arch.exception.error_code = error_code;
574 vcpu->arch.exception.has_payload = has_payload;
575 vcpu->arch.exception.payload = payload;
576 if (!is_guest_mode(vcpu))
577 kvm_deliver_exception_payload(vcpu);
578 return;
579 }
580
581 /* to check exception */
582 prev_nr = vcpu->arch.exception.nr;
583 if (prev_nr == DF_VECTOR) {
584 /* triple fault -> shutdown */
585 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
586 return;
587 }
588 class1 = exception_class(prev_nr);
589 class2 = exception_class(nr);
590 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
591 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
592 /*
593 * Generate double fault per SDM Table 5-5. Set
594 * exception.pending = true so that the double fault
595 * can trigger a nested vmexit.
596 */
597 vcpu->arch.exception.pending = true;
598 vcpu->arch.exception.injected = false;
599 vcpu->arch.exception.has_error_code = true;
600 vcpu->arch.exception.nr = DF_VECTOR;
601 vcpu->arch.exception.error_code = 0;
602 vcpu->arch.exception.has_payload = false;
603 vcpu->arch.exception.payload = 0;
604 } else
605 /* replace previous exception with a new one in a hope
606 that instruction re-execution will regenerate lost
607 exception */
608 goto queue;
609 }
610
611 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
612 {
613 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
614 }
615 EXPORT_SYMBOL_GPL(kvm_queue_exception);
616
617 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
618 {
619 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
620 }
621 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
622
623 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
624 unsigned long payload)
625 {
626 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
627 }
628 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
629
630 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
631 u32 error_code, unsigned long payload)
632 {
633 kvm_multiple_exception(vcpu, nr, true, error_code,
634 true, payload, false);
635 }
636
637 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
638 {
639 if (err)
640 kvm_inject_gp(vcpu, 0);
641 else
642 return kvm_skip_emulated_instruction(vcpu);
643
644 return 1;
645 }
646 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
647
648 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
649 {
650 ++vcpu->stat.pf_guest;
651 vcpu->arch.exception.nested_apf =
652 is_guest_mode(vcpu) && fault->async_page_fault;
653 if (vcpu->arch.exception.nested_apf) {
654 vcpu->arch.apf.nested_apf_token = fault->address;
655 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
656 } else {
657 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
658 fault->address);
659 }
660 }
661 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
662
663 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
664 struct x86_exception *fault)
665 {
666 struct kvm_mmu *fault_mmu;
667 WARN_ON_ONCE(fault->vector != PF_VECTOR);
668
669 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
670 vcpu->arch.walk_mmu;
671
672 /*
673 * Invalidate the TLB entry for the faulting address, if it exists,
674 * else the access will fault indefinitely (and to emulate hardware).
675 */
676 if ((fault->error_code & PFERR_PRESENT_MASK) &&
677 !(fault->error_code & PFERR_RSVD_MASK))
678 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
679 fault_mmu->root_hpa);
680
681 fault_mmu->inject_page_fault(vcpu, fault);
682 return fault->nested_page_fault;
683 }
684 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
685
686 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
687 {
688 atomic_inc(&vcpu->arch.nmi_queued);
689 kvm_make_request(KVM_REQ_NMI, vcpu);
690 }
691 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
692
693 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
694 {
695 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
696 }
697 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
698
699 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
700 {
701 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
702 }
703 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
704
705 /*
706 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
707 * a #GP and return false.
708 */
709 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
710 {
711 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
712 return true;
713 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
714 return false;
715 }
716 EXPORT_SYMBOL_GPL(kvm_require_cpl);
717
718 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
719 {
720 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
721 return true;
722
723 kvm_queue_exception(vcpu, UD_VECTOR);
724 return false;
725 }
726 EXPORT_SYMBOL_GPL(kvm_require_dr);
727
728 /*
729 * This function will be used to read from the physical memory of the currently
730 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
731 * can read from guest physical or from the guest's guest physical memory.
732 */
733 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
734 gfn_t ngfn, void *data, int offset, int len,
735 u32 access)
736 {
737 struct x86_exception exception;
738 gfn_t real_gfn;
739 gpa_t ngpa;
740
741 ngpa = gfn_to_gpa(ngfn);
742 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
743 if (real_gfn == UNMAPPED_GVA)
744 return -EFAULT;
745
746 real_gfn = gpa_to_gfn(real_gfn);
747
748 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
749 }
750 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
751
752 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
753 void *data, int offset, int len, u32 access)
754 {
755 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
756 data, offset, len, access);
757 }
758
759 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
760 {
761 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
762 rsvd_bits(1, 2);
763 }
764
765 /*
766 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
767 */
768 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
769 {
770 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
771 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
772 int i;
773 int ret;
774 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
775
776 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
777 offset * sizeof(u64), sizeof(pdpte),
778 PFERR_USER_MASK|PFERR_WRITE_MASK);
779 if (ret < 0) {
780 ret = 0;
781 goto out;
782 }
783 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
784 if ((pdpte[i] & PT_PRESENT_MASK) &&
785 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
786 ret = 0;
787 goto out;
788 }
789 }
790 ret = 1;
791
792 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
793 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
794
795 out:
796
797 return ret;
798 }
799 EXPORT_SYMBOL_GPL(load_pdptrs);
800
801 bool pdptrs_changed(struct kvm_vcpu *vcpu)
802 {
803 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
804 int offset;
805 gfn_t gfn;
806 int r;
807
808 if (!is_pae_paging(vcpu))
809 return false;
810
811 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
812 return true;
813
814 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
815 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
816 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
817 PFERR_USER_MASK | PFERR_WRITE_MASK);
818 if (r < 0)
819 return true;
820
821 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
822 }
823 EXPORT_SYMBOL_GPL(pdptrs_changed);
824
825 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
826 {
827 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
828
829 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
830 kvm_clear_async_pf_completion_queue(vcpu);
831 kvm_async_pf_hash_reset(vcpu);
832 }
833
834 if ((cr0 ^ old_cr0) & update_bits)
835 kvm_mmu_reset_context(vcpu);
836
837 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
838 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
839 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
840 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
841 }
842 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
843
844 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
845 {
846 unsigned long old_cr0 = kvm_read_cr0(vcpu);
847 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
848
849 cr0 |= X86_CR0_ET;
850
851 #ifdef CONFIG_X86_64
852 if (cr0 & 0xffffffff00000000UL)
853 return 1;
854 #endif
855
856 cr0 &= ~CR0_RESERVED_BITS;
857
858 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
859 return 1;
860
861 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
862 return 1;
863
864 #ifdef CONFIG_X86_64
865 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
866 (cr0 & X86_CR0_PG)) {
867 int cs_db, cs_l;
868
869 if (!is_pae(vcpu))
870 return 1;
871 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
872 if (cs_l)
873 return 1;
874 }
875 #endif
876 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
877 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
878 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
879 return 1;
880
881 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
882 return 1;
883
884 static_call(kvm_x86_set_cr0)(vcpu, cr0);
885
886 kvm_post_set_cr0(vcpu, old_cr0, cr0);
887
888 return 0;
889 }
890 EXPORT_SYMBOL_GPL(kvm_set_cr0);
891
892 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
893 {
894 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
895 }
896 EXPORT_SYMBOL_GPL(kvm_lmsw);
897
898 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
899 {
900 if (vcpu->arch.guest_state_protected)
901 return;
902
903 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
904
905 if (vcpu->arch.xcr0 != host_xcr0)
906 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
907
908 if (vcpu->arch.xsaves_enabled &&
909 vcpu->arch.ia32_xss != host_xss)
910 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
911 }
912
913 if (static_cpu_has(X86_FEATURE_PKU) &&
914 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
915 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
916 vcpu->arch.pkru != vcpu->arch.host_pkru)
917 __write_pkru(vcpu->arch.pkru);
918 }
919 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
920
921 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
922 {
923 if (vcpu->arch.guest_state_protected)
924 return;
925
926 if (static_cpu_has(X86_FEATURE_PKU) &&
927 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
928 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
929 vcpu->arch.pkru = rdpkru();
930 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
931 __write_pkru(vcpu->arch.host_pkru);
932 }
933
934 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
935
936 if (vcpu->arch.xcr0 != host_xcr0)
937 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
938
939 if (vcpu->arch.xsaves_enabled &&
940 vcpu->arch.ia32_xss != host_xss)
941 wrmsrl(MSR_IA32_XSS, host_xss);
942 }
943
944 }
945 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
946
947 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
948 {
949 u64 xcr0 = xcr;
950 u64 old_xcr0 = vcpu->arch.xcr0;
951 u64 valid_bits;
952
953 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
954 if (index != XCR_XFEATURE_ENABLED_MASK)
955 return 1;
956 if (!(xcr0 & XFEATURE_MASK_FP))
957 return 1;
958 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
959 return 1;
960
961 /*
962 * Do not allow the guest to set bits that we do not support
963 * saving. However, xcr0 bit 0 is always set, even if the
964 * emulated CPU does not support XSAVE (see fx_init).
965 */
966 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
967 if (xcr0 & ~valid_bits)
968 return 1;
969
970 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
971 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
972 return 1;
973
974 if (xcr0 & XFEATURE_MASK_AVX512) {
975 if (!(xcr0 & XFEATURE_MASK_YMM))
976 return 1;
977 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
978 return 1;
979 }
980 vcpu->arch.xcr0 = xcr0;
981
982 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
983 kvm_update_cpuid_runtime(vcpu);
984 return 0;
985 }
986
987 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
988 {
989 if (static_call(kvm_x86_get_cpl)(vcpu) == 0)
990 return __kvm_set_xcr(vcpu, index, xcr);
991
992 return 1;
993 }
994 EXPORT_SYMBOL_GPL(kvm_set_xcr);
995
996 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
997 {
998 if (cr4 & cr4_reserved_bits)
999 return false;
1000
1001 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1002 return false;
1003
1004 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1005 }
1006 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
1007
1008 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1009 {
1010 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
1011 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
1012
1013 if (((cr4 ^ old_cr4) & mmu_role_bits) ||
1014 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1015 kvm_mmu_reset_context(vcpu);
1016 }
1017 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1018
1019 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1020 {
1021 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1022 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
1023 X86_CR4_SMEP;
1024
1025 if (!kvm_is_valid_cr4(vcpu, cr4))
1026 return 1;
1027
1028 if (is_long_mode(vcpu)) {
1029 if (!(cr4 & X86_CR4_PAE))
1030 return 1;
1031 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1032 return 1;
1033 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1034 && ((cr4 ^ old_cr4) & pdptr_bits)
1035 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
1036 kvm_read_cr3(vcpu)))
1037 return 1;
1038
1039 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1040 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1041 return 1;
1042
1043 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1044 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1045 return 1;
1046 }
1047
1048 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1049
1050 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1051
1052 return 0;
1053 }
1054 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1055
1056 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1057 {
1058 bool skip_tlb_flush = false;
1059 #ifdef CONFIG_X86_64
1060 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1061
1062 if (pcid_enabled) {
1063 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1064 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1065 }
1066 #endif
1067
1068 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1069 if (!skip_tlb_flush) {
1070 kvm_mmu_sync_roots(vcpu);
1071 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1072 }
1073 return 0;
1074 }
1075
1076 if (is_long_mode(vcpu) &&
1077 (cr3 & vcpu->arch.cr3_lm_rsvd_bits))
1078 return 1;
1079 else if (is_pae_paging(vcpu) &&
1080 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1081 return 1;
1082
1083 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1084 vcpu->arch.cr3 = cr3;
1085 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1086
1087 return 0;
1088 }
1089 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1090
1091 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1092 {
1093 if (cr8 & CR8_RESERVED_BITS)
1094 return 1;
1095 if (lapic_in_kernel(vcpu))
1096 kvm_lapic_set_tpr(vcpu, cr8);
1097 else
1098 vcpu->arch.cr8 = cr8;
1099 return 0;
1100 }
1101 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1102
1103 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1104 {
1105 if (lapic_in_kernel(vcpu))
1106 return kvm_lapic_get_cr8(vcpu);
1107 else
1108 return vcpu->arch.cr8;
1109 }
1110 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1111
1112 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1113 {
1114 int i;
1115
1116 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1117 for (i = 0; i < KVM_NR_DB_REGS; i++)
1118 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1119 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1120 }
1121 }
1122
1123 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1124 {
1125 unsigned long dr7;
1126
1127 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1128 dr7 = vcpu->arch.guest_debug_dr7;
1129 else
1130 dr7 = vcpu->arch.dr7;
1131 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1132 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1133 if (dr7 & DR7_BP_EN_MASK)
1134 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1135 }
1136 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1137
1138 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1139 {
1140 u64 fixed = DR6_FIXED_1;
1141
1142 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1143 fixed |= DR6_RTM;
1144 return fixed;
1145 }
1146
1147 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1148 {
1149 size_t size = ARRAY_SIZE(vcpu->arch.db);
1150
1151 switch (dr) {
1152 case 0 ... 3:
1153 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1154 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1155 vcpu->arch.eff_db[dr] = val;
1156 break;
1157 case 4:
1158 case 6:
1159 if (!kvm_dr6_valid(val))
1160 return -1; /* #GP */
1161 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1162 break;
1163 case 5:
1164 default: /* 7 */
1165 if (!kvm_dr7_valid(val))
1166 return -1; /* #GP */
1167 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1168 kvm_update_dr7(vcpu);
1169 break;
1170 }
1171
1172 return 0;
1173 }
1174
1175 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1176 {
1177 if (__kvm_set_dr(vcpu, dr, val)) {
1178 kvm_inject_gp(vcpu, 0);
1179 return 1;
1180 }
1181 return 0;
1182 }
1183 EXPORT_SYMBOL_GPL(kvm_set_dr);
1184
1185 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1186 {
1187 size_t size = ARRAY_SIZE(vcpu->arch.db);
1188
1189 switch (dr) {
1190 case 0 ... 3:
1191 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1192 break;
1193 case 4:
1194 case 6:
1195 *val = vcpu->arch.dr6;
1196 break;
1197 case 5:
1198 default: /* 7 */
1199 *val = vcpu->arch.dr7;
1200 break;
1201 }
1202 return 0;
1203 }
1204 EXPORT_SYMBOL_GPL(kvm_get_dr);
1205
1206 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1207 {
1208 u32 ecx = kvm_rcx_read(vcpu);
1209 u64 data;
1210 int err;
1211
1212 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1213 if (err)
1214 return err;
1215 kvm_rax_write(vcpu, (u32)data);
1216 kvm_rdx_write(vcpu, data >> 32);
1217 return err;
1218 }
1219 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1220
1221 /*
1222 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1223 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1224 *
1225 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1226 * extract the supported MSRs from the related const lists.
1227 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1228 * capabilities of the host cpu. This capabilities test skips MSRs that are
1229 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1230 * may depend on host virtualization features rather than host cpu features.
1231 */
1232
1233 static const u32 msrs_to_save_all[] = {
1234 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1235 MSR_STAR,
1236 #ifdef CONFIG_X86_64
1237 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1238 #endif
1239 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1240 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1241 MSR_IA32_SPEC_CTRL,
1242 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1243 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1244 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1245 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1246 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1247 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1248 MSR_IA32_UMWAIT_CONTROL,
1249
1250 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1251 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1252 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1253 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1254 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1255 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1256 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1257 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1258 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1259 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1260 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1261 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1262 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1263 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1264 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1265 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1266 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1267 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1268 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1269 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1270 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1271 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1272 };
1273
1274 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1275 static unsigned num_msrs_to_save;
1276
1277 static const u32 emulated_msrs_all[] = {
1278 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1279 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1280 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1281 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1282 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1283 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1284 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1285 HV_X64_MSR_RESET,
1286 HV_X64_MSR_VP_INDEX,
1287 HV_X64_MSR_VP_RUNTIME,
1288 HV_X64_MSR_SCONTROL,
1289 HV_X64_MSR_STIMER0_CONFIG,
1290 HV_X64_MSR_VP_ASSIST_PAGE,
1291 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1292 HV_X64_MSR_TSC_EMULATION_STATUS,
1293 HV_X64_MSR_SYNDBG_OPTIONS,
1294 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1295 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1296 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1297
1298 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1299 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1300
1301 MSR_IA32_TSC_ADJUST,
1302 MSR_IA32_TSCDEADLINE,
1303 MSR_IA32_ARCH_CAPABILITIES,
1304 MSR_IA32_PERF_CAPABILITIES,
1305 MSR_IA32_MISC_ENABLE,
1306 MSR_IA32_MCG_STATUS,
1307 MSR_IA32_MCG_CTL,
1308 MSR_IA32_MCG_EXT_CTL,
1309 MSR_IA32_SMBASE,
1310 MSR_SMI_COUNT,
1311 MSR_PLATFORM_INFO,
1312 MSR_MISC_FEATURES_ENABLES,
1313 MSR_AMD64_VIRT_SPEC_CTRL,
1314 MSR_IA32_POWER_CTL,
1315 MSR_IA32_UCODE_REV,
1316
1317 /*
1318 * The following list leaves out MSRs whose values are determined
1319 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1320 * We always support the "true" VMX control MSRs, even if the host
1321 * processor does not, so I am putting these registers here rather
1322 * than in msrs_to_save_all.
1323 */
1324 MSR_IA32_VMX_BASIC,
1325 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1326 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1327 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1328 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1329 MSR_IA32_VMX_MISC,
1330 MSR_IA32_VMX_CR0_FIXED0,
1331 MSR_IA32_VMX_CR4_FIXED0,
1332 MSR_IA32_VMX_VMCS_ENUM,
1333 MSR_IA32_VMX_PROCBASED_CTLS2,
1334 MSR_IA32_VMX_EPT_VPID_CAP,
1335 MSR_IA32_VMX_VMFUNC,
1336
1337 MSR_K7_HWCR,
1338 MSR_KVM_POLL_CONTROL,
1339 };
1340
1341 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1342 static unsigned num_emulated_msrs;
1343
1344 /*
1345 * List of msr numbers which are used to expose MSR-based features that
1346 * can be used by a hypervisor to validate requested CPU features.
1347 */
1348 static const u32 msr_based_features_all[] = {
1349 MSR_IA32_VMX_BASIC,
1350 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1351 MSR_IA32_VMX_PINBASED_CTLS,
1352 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1353 MSR_IA32_VMX_PROCBASED_CTLS,
1354 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1355 MSR_IA32_VMX_EXIT_CTLS,
1356 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1357 MSR_IA32_VMX_ENTRY_CTLS,
1358 MSR_IA32_VMX_MISC,
1359 MSR_IA32_VMX_CR0_FIXED0,
1360 MSR_IA32_VMX_CR0_FIXED1,
1361 MSR_IA32_VMX_CR4_FIXED0,
1362 MSR_IA32_VMX_CR4_FIXED1,
1363 MSR_IA32_VMX_VMCS_ENUM,
1364 MSR_IA32_VMX_PROCBASED_CTLS2,
1365 MSR_IA32_VMX_EPT_VPID_CAP,
1366 MSR_IA32_VMX_VMFUNC,
1367
1368 MSR_F10H_DECFG,
1369 MSR_IA32_UCODE_REV,
1370 MSR_IA32_ARCH_CAPABILITIES,
1371 MSR_IA32_PERF_CAPABILITIES,
1372 };
1373
1374 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1375 static unsigned int num_msr_based_features;
1376
1377 static u64 kvm_get_arch_capabilities(void)
1378 {
1379 u64 data = 0;
1380
1381 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1382 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1383
1384 /*
1385 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1386 * the nested hypervisor runs with NX huge pages. If it is not,
1387 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1388 * L1 guests, so it need not worry about its own (L2) guests.
1389 */
1390 data |= ARCH_CAP_PSCHANGE_MC_NO;
1391
1392 /*
1393 * If we're doing cache flushes (either "always" or "cond")
1394 * we will do one whenever the guest does a vmlaunch/vmresume.
1395 * If an outer hypervisor is doing the cache flush for us
1396 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1397 * capability to the guest too, and if EPT is disabled we're not
1398 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1399 * require a nested hypervisor to do a flush of its own.
1400 */
1401 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1402 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1403
1404 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1405 data |= ARCH_CAP_RDCL_NO;
1406 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1407 data |= ARCH_CAP_SSB_NO;
1408 if (!boot_cpu_has_bug(X86_BUG_MDS))
1409 data |= ARCH_CAP_MDS_NO;
1410
1411 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1412 /*
1413 * If RTM=0 because the kernel has disabled TSX, the host might
1414 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1415 * and therefore knows that there cannot be TAA) but keep
1416 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1417 * and we want to allow migrating those guests to tsx=off hosts.
1418 */
1419 data &= ~ARCH_CAP_TAA_NO;
1420 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1421 data |= ARCH_CAP_TAA_NO;
1422 } else {
1423 /*
1424 * Nothing to do here; we emulate TSX_CTRL if present on the
1425 * host so the guest can choose between disabling TSX or
1426 * using VERW to clear CPU buffers.
1427 */
1428 }
1429
1430 return data;
1431 }
1432
1433 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1434 {
1435 switch (msr->index) {
1436 case MSR_IA32_ARCH_CAPABILITIES:
1437 msr->data = kvm_get_arch_capabilities();
1438 break;
1439 case MSR_IA32_UCODE_REV:
1440 rdmsrl_safe(msr->index, &msr->data);
1441 break;
1442 default:
1443 return static_call(kvm_x86_get_msr_feature)(msr);
1444 }
1445 return 0;
1446 }
1447
1448 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1449 {
1450 struct kvm_msr_entry msr;
1451 int r;
1452
1453 msr.index = index;
1454 r = kvm_get_msr_feature(&msr);
1455
1456 if (r == KVM_MSR_RET_INVALID) {
1457 /* Unconditionally clear the output for simplicity */
1458 *data = 0;
1459 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1460 r = 0;
1461 }
1462
1463 if (r)
1464 return r;
1465
1466 *data = msr.data;
1467
1468 return 0;
1469 }
1470
1471 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1472 {
1473 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1474 return false;
1475
1476 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1477 return false;
1478
1479 if (efer & (EFER_LME | EFER_LMA) &&
1480 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1481 return false;
1482
1483 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1484 return false;
1485
1486 return true;
1487
1488 }
1489 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1490 {
1491 if (efer & efer_reserved_bits)
1492 return false;
1493
1494 return __kvm_valid_efer(vcpu, efer);
1495 }
1496 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1497
1498 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1499 {
1500 u64 old_efer = vcpu->arch.efer;
1501 u64 efer = msr_info->data;
1502 int r;
1503
1504 if (efer & efer_reserved_bits)
1505 return 1;
1506
1507 if (!msr_info->host_initiated) {
1508 if (!__kvm_valid_efer(vcpu, efer))
1509 return 1;
1510
1511 if (is_paging(vcpu) &&
1512 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1513 return 1;
1514 }
1515
1516 efer &= ~EFER_LMA;
1517 efer |= vcpu->arch.efer & EFER_LMA;
1518
1519 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1520 if (r) {
1521 WARN_ON(r > 0);
1522 return r;
1523 }
1524
1525 /* Update reserved bits */
1526 if ((efer ^ old_efer) & EFER_NX)
1527 kvm_mmu_reset_context(vcpu);
1528
1529 return 0;
1530 }
1531
1532 void kvm_enable_efer_bits(u64 mask)
1533 {
1534 efer_reserved_bits &= ~mask;
1535 }
1536 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1537
1538 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1539 {
1540 struct kvm *kvm = vcpu->kvm;
1541 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
1542 u32 count = kvm->arch.msr_filter.count;
1543 u32 i;
1544 bool r = kvm->arch.msr_filter.default_allow;
1545 int idx;
1546
1547 /* MSR filtering not set up or x2APIC enabled, allow everything */
1548 if (!count || (index >= 0x800 && index <= 0x8ff))
1549 return true;
1550
1551 /* Prevent collision with set_msr_filter */
1552 idx = srcu_read_lock(&kvm->srcu);
1553
1554 for (i = 0; i < count; i++) {
1555 u32 start = ranges[i].base;
1556 u32 end = start + ranges[i].nmsrs;
1557 u32 flags = ranges[i].flags;
1558 unsigned long *bitmap = ranges[i].bitmap;
1559
1560 if ((index >= start) && (index < end) && (flags & type)) {
1561 r = !!test_bit(index - start, bitmap);
1562 break;
1563 }
1564 }
1565
1566 srcu_read_unlock(&kvm->srcu, idx);
1567
1568 return r;
1569 }
1570 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1571
1572 /*
1573 * Write @data into the MSR specified by @index. Select MSR specific fault
1574 * checks are bypassed if @host_initiated is %true.
1575 * Returns 0 on success, non-0 otherwise.
1576 * Assumes vcpu_load() was already called.
1577 */
1578 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1579 bool host_initiated)
1580 {
1581 struct msr_data msr;
1582
1583 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1584 return KVM_MSR_RET_FILTERED;
1585
1586 switch (index) {
1587 case MSR_FS_BASE:
1588 case MSR_GS_BASE:
1589 case MSR_KERNEL_GS_BASE:
1590 case MSR_CSTAR:
1591 case MSR_LSTAR:
1592 if (is_noncanonical_address(data, vcpu))
1593 return 1;
1594 break;
1595 case MSR_IA32_SYSENTER_EIP:
1596 case MSR_IA32_SYSENTER_ESP:
1597 /*
1598 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1599 * non-canonical address is written on Intel but not on
1600 * AMD (which ignores the top 32-bits, because it does
1601 * not implement 64-bit SYSENTER).
1602 *
1603 * 64-bit code should hence be able to write a non-canonical
1604 * value on AMD. Making the address canonical ensures that
1605 * vmentry does not fail on Intel after writing a non-canonical
1606 * value, and that something deterministic happens if the guest
1607 * invokes 64-bit SYSENTER.
1608 */
1609 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1610 }
1611
1612 msr.data = data;
1613 msr.index = index;
1614 msr.host_initiated = host_initiated;
1615
1616 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1617 }
1618
1619 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1620 u32 index, u64 data, bool host_initiated)
1621 {
1622 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1623
1624 if (ret == KVM_MSR_RET_INVALID)
1625 if (kvm_msr_ignored_check(vcpu, index, data, true))
1626 ret = 0;
1627
1628 return ret;
1629 }
1630
1631 /*
1632 * Read the MSR specified by @index into @data. Select MSR specific fault
1633 * checks are bypassed if @host_initiated is %true.
1634 * Returns 0 on success, non-0 otherwise.
1635 * Assumes vcpu_load() was already called.
1636 */
1637 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1638 bool host_initiated)
1639 {
1640 struct msr_data msr;
1641 int ret;
1642
1643 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1644 return KVM_MSR_RET_FILTERED;
1645
1646 msr.index = index;
1647 msr.host_initiated = host_initiated;
1648
1649 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1650 if (!ret)
1651 *data = msr.data;
1652 return ret;
1653 }
1654
1655 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1656 u32 index, u64 *data, bool host_initiated)
1657 {
1658 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1659
1660 if (ret == KVM_MSR_RET_INVALID) {
1661 /* Unconditionally clear *data for simplicity */
1662 *data = 0;
1663 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1664 ret = 0;
1665 }
1666
1667 return ret;
1668 }
1669
1670 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1671 {
1672 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1673 }
1674 EXPORT_SYMBOL_GPL(kvm_get_msr);
1675
1676 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1677 {
1678 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1679 }
1680 EXPORT_SYMBOL_GPL(kvm_set_msr);
1681
1682 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1683 {
1684 int err = vcpu->run->msr.error;
1685 if (!err) {
1686 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1687 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1688 }
1689
1690 return static_call(kvm_x86_complete_emulated_msr)(vcpu, err);
1691 }
1692
1693 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1694 {
1695 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1696 }
1697
1698 static u64 kvm_msr_reason(int r)
1699 {
1700 switch (r) {
1701 case KVM_MSR_RET_INVALID:
1702 return KVM_MSR_EXIT_REASON_UNKNOWN;
1703 case KVM_MSR_RET_FILTERED:
1704 return KVM_MSR_EXIT_REASON_FILTER;
1705 default:
1706 return KVM_MSR_EXIT_REASON_INVAL;
1707 }
1708 }
1709
1710 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1711 u32 exit_reason, u64 data,
1712 int (*completion)(struct kvm_vcpu *vcpu),
1713 int r)
1714 {
1715 u64 msr_reason = kvm_msr_reason(r);
1716
1717 /* Check if the user wanted to know about this MSR fault */
1718 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1719 return 0;
1720
1721 vcpu->run->exit_reason = exit_reason;
1722 vcpu->run->msr.error = 0;
1723 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1724 vcpu->run->msr.reason = msr_reason;
1725 vcpu->run->msr.index = index;
1726 vcpu->run->msr.data = data;
1727 vcpu->arch.complete_userspace_io = completion;
1728
1729 return 1;
1730 }
1731
1732 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1733 {
1734 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1735 complete_emulated_rdmsr, r);
1736 }
1737
1738 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1739 {
1740 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1741 complete_emulated_wrmsr, r);
1742 }
1743
1744 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1745 {
1746 u32 ecx = kvm_rcx_read(vcpu);
1747 u64 data;
1748 int r;
1749
1750 r = kvm_get_msr(vcpu, ecx, &data);
1751
1752 /* MSR read failed? See if we should ask user space */
1753 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1754 /* Bounce to user space */
1755 return 0;
1756 }
1757
1758 if (!r) {
1759 trace_kvm_msr_read(ecx, data);
1760
1761 kvm_rax_write(vcpu, data & -1u);
1762 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1763 } else {
1764 trace_kvm_msr_read_ex(ecx);
1765 }
1766
1767 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
1768 }
1769 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1770
1771 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1772 {
1773 u32 ecx = kvm_rcx_read(vcpu);
1774 u64 data = kvm_read_edx_eax(vcpu);
1775 int r;
1776
1777 r = kvm_set_msr(vcpu, ecx, data);
1778
1779 /* MSR write failed? See if we should ask user space */
1780 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r))
1781 /* Bounce to user space */
1782 return 0;
1783
1784 /* Signal all other negative errors to userspace */
1785 if (r < 0)
1786 return r;
1787
1788 if (!r)
1789 trace_kvm_msr_write(ecx, data);
1790 else
1791 trace_kvm_msr_write_ex(ecx, data);
1792
1793 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
1794 }
1795 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1796
1797 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1798 {
1799 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1800 xfer_to_guest_mode_work_pending();
1801 }
1802
1803 /*
1804 * The fast path for frequent and performance sensitive wrmsr emulation,
1805 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1806 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1807 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1808 * other cases which must be called after interrupts are enabled on the host.
1809 */
1810 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1811 {
1812 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1813 return 1;
1814
1815 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1816 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1817 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1818 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1819
1820 data &= ~(1 << 12);
1821 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1822 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1823 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1824 trace_kvm_apic_write(APIC_ICR, (u32)data);
1825 return 0;
1826 }
1827
1828 return 1;
1829 }
1830
1831 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1832 {
1833 if (!kvm_can_use_hv_timer(vcpu))
1834 return 1;
1835
1836 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1837 return 0;
1838 }
1839
1840 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1841 {
1842 u32 msr = kvm_rcx_read(vcpu);
1843 u64 data;
1844 fastpath_t ret = EXIT_FASTPATH_NONE;
1845
1846 switch (msr) {
1847 case APIC_BASE_MSR + (APIC_ICR >> 4):
1848 data = kvm_read_edx_eax(vcpu);
1849 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1850 kvm_skip_emulated_instruction(vcpu);
1851 ret = EXIT_FASTPATH_EXIT_HANDLED;
1852 }
1853 break;
1854 case MSR_IA32_TSCDEADLINE:
1855 data = kvm_read_edx_eax(vcpu);
1856 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1857 kvm_skip_emulated_instruction(vcpu);
1858 ret = EXIT_FASTPATH_REENTER_GUEST;
1859 }
1860 break;
1861 default:
1862 break;
1863 }
1864
1865 if (ret != EXIT_FASTPATH_NONE)
1866 trace_kvm_msr_write(msr, data);
1867
1868 return ret;
1869 }
1870 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1871
1872 /*
1873 * Adapt set_msr() to msr_io()'s calling convention
1874 */
1875 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1876 {
1877 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1878 }
1879
1880 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1881 {
1882 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1883 }
1884
1885 #ifdef CONFIG_X86_64
1886 struct pvclock_clock {
1887 int vclock_mode;
1888 u64 cycle_last;
1889 u64 mask;
1890 u32 mult;
1891 u32 shift;
1892 u64 base_cycles;
1893 u64 offset;
1894 };
1895
1896 struct pvclock_gtod_data {
1897 seqcount_t seq;
1898
1899 struct pvclock_clock clock; /* extract of a clocksource struct */
1900 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1901
1902 ktime_t offs_boot;
1903 u64 wall_time_sec;
1904 };
1905
1906 static struct pvclock_gtod_data pvclock_gtod_data;
1907
1908 static void update_pvclock_gtod(struct timekeeper *tk)
1909 {
1910 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1911
1912 write_seqcount_begin(&vdata->seq);
1913
1914 /* copy pvclock gtod data */
1915 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1916 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1917 vdata->clock.mask = tk->tkr_mono.mask;
1918 vdata->clock.mult = tk->tkr_mono.mult;
1919 vdata->clock.shift = tk->tkr_mono.shift;
1920 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1921 vdata->clock.offset = tk->tkr_mono.base;
1922
1923 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1924 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1925 vdata->raw_clock.mask = tk->tkr_raw.mask;
1926 vdata->raw_clock.mult = tk->tkr_raw.mult;
1927 vdata->raw_clock.shift = tk->tkr_raw.shift;
1928 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1929 vdata->raw_clock.offset = tk->tkr_raw.base;
1930
1931 vdata->wall_time_sec = tk->xtime_sec;
1932
1933 vdata->offs_boot = tk->offs_boot;
1934
1935 write_seqcount_end(&vdata->seq);
1936 }
1937
1938 static s64 get_kvmclock_base_ns(void)
1939 {
1940 /* Count up from boot time, but with the frequency of the raw clock. */
1941 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1942 }
1943 #else
1944 static s64 get_kvmclock_base_ns(void)
1945 {
1946 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1947 return ktime_get_boottime_ns();
1948 }
1949 #endif
1950
1951 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1952 {
1953 int version;
1954 int r;
1955 struct pvclock_wall_clock wc;
1956 u64 wall_nsec;
1957
1958 kvm->arch.wall_clock = wall_clock;
1959
1960 if (!wall_clock)
1961 return;
1962
1963 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1964 if (r)
1965 return;
1966
1967 if (version & 1)
1968 ++version; /* first time write, random junk */
1969
1970 ++version;
1971
1972 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1973 return;
1974
1975 /*
1976 * The guest calculates current wall clock time by adding
1977 * system time (updated by kvm_guest_time_update below) to the
1978 * wall clock specified here. We do the reverse here.
1979 */
1980 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1981
1982 wc.nsec = do_div(wall_nsec, 1000000000);
1983 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1984 wc.version = version;
1985
1986 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1987
1988 version++;
1989 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1990 }
1991
1992 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1993 bool old_msr, bool host_initiated)
1994 {
1995 struct kvm_arch *ka = &vcpu->kvm->arch;
1996
1997 if (vcpu->vcpu_id == 0 && !host_initiated) {
1998 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
1999 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2000
2001 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2002 }
2003
2004 vcpu->arch.time = system_time;
2005 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2006
2007 /* we verify if the enable bit is set... */
2008 vcpu->arch.pv_time_enabled = false;
2009 if (!(system_time & 1))
2010 return;
2011
2012 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2013 &vcpu->arch.pv_time, system_time & ~1ULL,
2014 sizeof(struct pvclock_vcpu_time_info)))
2015 vcpu->arch.pv_time_enabled = true;
2016
2017 return;
2018 }
2019
2020 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2021 {
2022 do_shl32_div32(dividend, divisor);
2023 return dividend;
2024 }
2025
2026 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2027 s8 *pshift, u32 *pmultiplier)
2028 {
2029 uint64_t scaled64;
2030 int32_t shift = 0;
2031 uint64_t tps64;
2032 uint32_t tps32;
2033
2034 tps64 = base_hz;
2035 scaled64 = scaled_hz;
2036 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2037 tps64 >>= 1;
2038 shift--;
2039 }
2040
2041 tps32 = (uint32_t)tps64;
2042 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2043 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2044 scaled64 >>= 1;
2045 else
2046 tps32 <<= 1;
2047 shift++;
2048 }
2049
2050 *pshift = shift;
2051 *pmultiplier = div_frac(scaled64, tps32);
2052 }
2053
2054 #ifdef CONFIG_X86_64
2055 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2056 #endif
2057
2058 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2059 static unsigned long max_tsc_khz;
2060
2061 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2062 {
2063 u64 v = (u64)khz * (1000000 + ppm);
2064 do_div(v, 1000000);
2065 return v;
2066 }
2067
2068 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2069 {
2070 u64 ratio;
2071
2072 /* Guest TSC same frequency as host TSC? */
2073 if (!scale) {
2074 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2075 return 0;
2076 }
2077
2078 /* TSC scaling supported? */
2079 if (!kvm_has_tsc_control) {
2080 if (user_tsc_khz > tsc_khz) {
2081 vcpu->arch.tsc_catchup = 1;
2082 vcpu->arch.tsc_always_catchup = 1;
2083 return 0;
2084 } else {
2085 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2086 return -1;
2087 }
2088 }
2089
2090 /* TSC scaling required - calculate ratio */
2091 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2092 user_tsc_khz, tsc_khz);
2093
2094 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2095 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2096 user_tsc_khz);
2097 return -1;
2098 }
2099
2100 vcpu->arch.tsc_scaling_ratio = ratio;
2101 return 0;
2102 }
2103
2104 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2105 {
2106 u32 thresh_lo, thresh_hi;
2107 int use_scaling = 0;
2108
2109 /* tsc_khz can be zero if TSC calibration fails */
2110 if (user_tsc_khz == 0) {
2111 /* set tsc_scaling_ratio to a safe value */
2112 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2113 return -1;
2114 }
2115
2116 /* Compute a scale to convert nanoseconds in TSC cycles */
2117 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2118 &vcpu->arch.virtual_tsc_shift,
2119 &vcpu->arch.virtual_tsc_mult);
2120 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2121
2122 /*
2123 * Compute the variation in TSC rate which is acceptable
2124 * within the range of tolerance and decide if the
2125 * rate being applied is within that bounds of the hardware
2126 * rate. If so, no scaling or compensation need be done.
2127 */
2128 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2129 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2130 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2131 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2132 use_scaling = 1;
2133 }
2134 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2135 }
2136
2137 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2138 {
2139 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2140 vcpu->arch.virtual_tsc_mult,
2141 vcpu->arch.virtual_tsc_shift);
2142 tsc += vcpu->arch.this_tsc_write;
2143 return tsc;
2144 }
2145
2146 static inline int gtod_is_based_on_tsc(int mode)
2147 {
2148 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2149 }
2150
2151 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2152 {
2153 #ifdef CONFIG_X86_64
2154 bool vcpus_matched;
2155 struct kvm_arch *ka = &vcpu->kvm->arch;
2156 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2157
2158 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2159 atomic_read(&vcpu->kvm->online_vcpus));
2160
2161 /*
2162 * Once the masterclock is enabled, always perform request in
2163 * order to update it.
2164 *
2165 * In order to enable masterclock, the host clocksource must be TSC
2166 * and the vcpus need to have matched TSCs. When that happens,
2167 * perform request to enable masterclock.
2168 */
2169 if (ka->use_master_clock ||
2170 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2171 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2172
2173 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2174 atomic_read(&vcpu->kvm->online_vcpus),
2175 ka->use_master_clock, gtod->clock.vclock_mode);
2176 #endif
2177 }
2178
2179 /*
2180 * Multiply tsc by a fixed point number represented by ratio.
2181 *
2182 * The most significant 64-N bits (mult) of ratio represent the
2183 * integral part of the fixed point number; the remaining N bits
2184 * (frac) represent the fractional part, ie. ratio represents a fixed
2185 * point number (mult + frac * 2^(-N)).
2186 *
2187 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2188 */
2189 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2190 {
2191 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2192 }
2193
2194 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2195 {
2196 u64 _tsc = tsc;
2197 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2198
2199 if (ratio != kvm_default_tsc_scaling_ratio)
2200 _tsc = __scale_tsc(ratio, tsc);
2201
2202 return _tsc;
2203 }
2204 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2205
2206 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2207 {
2208 u64 tsc;
2209
2210 tsc = kvm_scale_tsc(vcpu, rdtsc());
2211
2212 return target_tsc - tsc;
2213 }
2214
2215 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2216 {
2217 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2218 }
2219 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2220
2221 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2222 {
2223 vcpu->arch.l1_tsc_offset = offset;
2224 vcpu->arch.tsc_offset = static_call(kvm_x86_write_l1_tsc_offset)(vcpu, offset);
2225 }
2226
2227 static inline bool kvm_check_tsc_unstable(void)
2228 {
2229 #ifdef CONFIG_X86_64
2230 /*
2231 * TSC is marked unstable when we're running on Hyper-V,
2232 * 'TSC page' clocksource is good.
2233 */
2234 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2235 return false;
2236 #endif
2237 return check_tsc_unstable();
2238 }
2239
2240 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2241 {
2242 struct kvm *kvm = vcpu->kvm;
2243 u64 offset, ns, elapsed;
2244 unsigned long flags;
2245 bool matched;
2246 bool already_matched;
2247 bool synchronizing = false;
2248
2249 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2250 offset = kvm_compute_tsc_offset(vcpu, data);
2251 ns = get_kvmclock_base_ns();
2252 elapsed = ns - kvm->arch.last_tsc_nsec;
2253
2254 if (vcpu->arch.virtual_tsc_khz) {
2255 if (data == 0) {
2256 /*
2257 * detection of vcpu initialization -- need to sync
2258 * with other vCPUs. This particularly helps to keep
2259 * kvm_clock stable after CPU hotplug
2260 */
2261 synchronizing = true;
2262 } else {
2263 u64 tsc_exp = kvm->arch.last_tsc_write +
2264 nsec_to_cycles(vcpu, elapsed);
2265 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2266 /*
2267 * Special case: TSC write with a small delta (1 second)
2268 * of virtual cycle time against real time is
2269 * interpreted as an attempt to synchronize the CPU.
2270 */
2271 synchronizing = data < tsc_exp + tsc_hz &&
2272 data + tsc_hz > tsc_exp;
2273 }
2274 }
2275
2276 /*
2277 * For a reliable TSC, we can match TSC offsets, and for an unstable
2278 * TSC, we add elapsed time in this computation. We could let the
2279 * compensation code attempt to catch up if we fall behind, but
2280 * it's better to try to match offsets from the beginning.
2281 */
2282 if (synchronizing &&
2283 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2284 if (!kvm_check_tsc_unstable()) {
2285 offset = kvm->arch.cur_tsc_offset;
2286 } else {
2287 u64 delta = nsec_to_cycles(vcpu, elapsed);
2288 data += delta;
2289 offset = kvm_compute_tsc_offset(vcpu, data);
2290 }
2291 matched = true;
2292 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2293 } else {
2294 /*
2295 * We split periods of matched TSC writes into generations.
2296 * For each generation, we track the original measured
2297 * nanosecond time, offset, and write, so if TSCs are in
2298 * sync, we can match exact offset, and if not, we can match
2299 * exact software computation in compute_guest_tsc()
2300 *
2301 * These values are tracked in kvm->arch.cur_xxx variables.
2302 */
2303 kvm->arch.cur_tsc_generation++;
2304 kvm->arch.cur_tsc_nsec = ns;
2305 kvm->arch.cur_tsc_write = data;
2306 kvm->arch.cur_tsc_offset = offset;
2307 matched = false;
2308 }
2309
2310 /*
2311 * We also track th most recent recorded KHZ, write and time to
2312 * allow the matching interval to be extended at each write.
2313 */
2314 kvm->arch.last_tsc_nsec = ns;
2315 kvm->arch.last_tsc_write = data;
2316 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2317
2318 vcpu->arch.last_guest_tsc = data;
2319
2320 /* Keep track of which generation this VCPU has synchronized to */
2321 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2322 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2323 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2324
2325 kvm_vcpu_write_tsc_offset(vcpu, offset);
2326 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2327
2328 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2329 if (!matched) {
2330 kvm->arch.nr_vcpus_matched_tsc = 0;
2331 } else if (!already_matched) {
2332 kvm->arch.nr_vcpus_matched_tsc++;
2333 }
2334
2335 kvm_track_tsc_matching(vcpu);
2336 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2337 }
2338
2339 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2340 s64 adjustment)
2341 {
2342 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2343 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2344 }
2345
2346 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2347 {
2348 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2349 WARN_ON(adjustment < 0);
2350 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2351 adjust_tsc_offset_guest(vcpu, adjustment);
2352 }
2353
2354 #ifdef CONFIG_X86_64
2355
2356 static u64 read_tsc(void)
2357 {
2358 u64 ret = (u64)rdtsc_ordered();
2359 u64 last = pvclock_gtod_data.clock.cycle_last;
2360
2361 if (likely(ret >= last))
2362 return ret;
2363
2364 /*
2365 * GCC likes to generate cmov here, but this branch is extremely
2366 * predictable (it's just a function of time and the likely is
2367 * very likely) and there's a data dependence, so force GCC
2368 * to generate a branch instead. I don't barrier() because
2369 * we don't actually need a barrier, and if this function
2370 * ever gets inlined it will generate worse code.
2371 */
2372 asm volatile ("");
2373 return last;
2374 }
2375
2376 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2377 int *mode)
2378 {
2379 long v;
2380 u64 tsc_pg_val;
2381
2382 switch (clock->vclock_mode) {
2383 case VDSO_CLOCKMODE_HVCLOCK:
2384 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2385 tsc_timestamp);
2386 if (tsc_pg_val != U64_MAX) {
2387 /* TSC page valid */
2388 *mode = VDSO_CLOCKMODE_HVCLOCK;
2389 v = (tsc_pg_val - clock->cycle_last) &
2390 clock->mask;
2391 } else {
2392 /* TSC page invalid */
2393 *mode = VDSO_CLOCKMODE_NONE;
2394 }
2395 break;
2396 case VDSO_CLOCKMODE_TSC:
2397 *mode = VDSO_CLOCKMODE_TSC;
2398 *tsc_timestamp = read_tsc();
2399 v = (*tsc_timestamp - clock->cycle_last) &
2400 clock->mask;
2401 break;
2402 default:
2403 *mode = VDSO_CLOCKMODE_NONE;
2404 }
2405
2406 if (*mode == VDSO_CLOCKMODE_NONE)
2407 *tsc_timestamp = v = 0;
2408
2409 return v * clock->mult;
2410 }
2411
2412 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2413 {
2414 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2415 unsigned long seq;
2416 int mode;
2417 u64 ns;
2418
2419 do {
2420 seq = read_seqcount_begin(&gtod->seq);
2421 ns = gtod->raw_clock.base_cycles;
2422 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2423 ns >>= gtod->raw_clock.shift;
2424 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2425 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2426 *t = ns;
2427
2428 return mode;
2429 }
2430
2431 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2432 {
2433 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2434 unsigned long seq;
2435 int mode;
2436 u64 ns;
2437
2438 do {
2439 seq = read_seqcount_begin(&gtod->seq);
2440 ts->tv_sec = gtod->wall_time_sec;
2441 ns = gtod->clock.base_cycles;
2442 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2443 ns >>= gtod->clock.shift;
2444 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2445
2446 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2447 ts->tv_nsec = ns;
2448
2449 return mode;
2450 }
2451
2452 /* returns true if host is using TSC based clocksource */
2453 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2454 {
2455 /* checked again under seqlock below */
2456 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2457 return false;
2458
2459 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2460 tsc_timestamp));
2461 }
2462
2463 /* returns true if host is using TSC based clocksource */
2464 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2465 u64 *tsc_timestamp)
2466 {
2467 /* checked again under seqlock below */
2468 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2469 return false;
2470
2471 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2472 }
2473 #endif
2474
2475 /*
2476 *
2477 * Assuming a stable TSC across physical CPUS, and a stable TSC
2478 * across virtual CPUs, the following condition is possible.
2479 * Each numbered line represents an event visible to both
2480 * CPUs at the next numbered event.
2481 *
2482 * "timespecX" represents host monotonic time. "tscX" represents
2483 * RDTSC value.
2484 *
2485 * VCPU0 on CPU0 | VCPU1 on CPU1
2486 *
2487 * 1. read timespec0,tsc0
2488 * 2. | timespec1 = timespec0 + N
2489 * | tsc1 = tsc0 + M
2490 * 3. transition to guest | transition to guest
2491 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2492 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2493 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2494 *
2495 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2496 *
2497 * - ret0 < ret1
2498 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2499 * ...
2500 * - 0 < N - M => M < N
2501 *
2502 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2503 * always the case (the difference between two distinct xtime instances
2504 * might be smaller then the difference between corresponding TSC reads,
2505 * when updating guest vcpus pvclock areas).
2506 *
2507 * To avoid that problem, do not allow visibility of distinct
2508 * system_timestamp/tsc_timestamp values simultaneously: use a master
2509 * copy of host monotonic time values. Update that master copy
2510 * in lockstep.
2511 *
2512 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2513 *
2514 */
2515
2516 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2517 {
2518 #ifdef CONFIG_X86_64
2519 struct kvm_arch *ka = &kvm->arch;
2520 int vclock_mode;
2521 bool host_tsc_clocksource, vcpus_matched;
2522
2523 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2524 atomic_read(&kvm->online_vcpus));
2525
2526 /*
2527 * If the host uses TSC clock, then passthrough TSC as stable
2528 * to the guest.
2529 */
2530 host_tsc_clocksource = kvm_get_time_and_clockread(
2531 &ka->master_kernel_ns,
2532 &ka->master_cycle_now);
2533
2534 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2535 && !ka->backwards_tsc_observed
2536 && !ka->boot_vcpu_runs_old_kvmclock;
2537
2538 if (ka->use_master_clock)
2539 atomic_set(&kvm_guest_has_master_clock, 1);
2540
2541 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2542 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2543 vcpus_matched);
2544 #endif
2545 }
2546
2547 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2548 {
2549 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2550 }
2551
2552 static void kvm_gen_update_masterclock(struct kvm *kvm)
2553 {
2554 #ifdef CONFIG_X86_64
2555 int i;
2556 struct kvm_vcpu *vcpu;
2557 struct kvm_arch *ka = &kvm->arch;
2558
2559 spin_lock(&ka->pvclock_gtod_sync_lock);
2560 kvm_make_mclock_inprogress_request(kvm);
2561 /* no guest entries from this point */
2562 pvclock_update_vm_gtod_copy(kvm);
2563
2564 kvm_for_each_vcpu(i, vcpu, kvm)
2565 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2566
2567 /* guest entries allowed */
2568 kvm_for_each_vcpu(i, vcpu, kvm)
2569 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2570
2571 spin_unlock(&ka->pvclock_gtod_sync_lock);
2572 #endif
2573 }
2574
2575 u64 get_kvmclock_ns(struct kvm *kvm)
2576 {
2577 struct kvm_arch *ka = &kvm->arch;
2578 struct pvclock_vcpu_time_info hv_clock;
2579 u64 ret;
2580
2581 spin_lock(&ka->pvclock_gtod_sync_lock);
2582 if (!ka->use_master_clock) {
2583 spin_unlock(&ka->pvclock_gtod_sync_lock);
2584 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2585 }
2586
2587 hv_clock.tsc_timestamp = ka->master_cycle_now;
2588 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2589 spin_unlock(&ka->pvclock_gtod_sync_lock);
2590
2591 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2592 get_cpu();
2593
2594 if (__this_cpu_read(cpu_tsc_khz)) {
2595 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2596 &hv_clock.tsc_shift,
2597 &hv_clock.tsc_to_system_mul);
2598 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2599 } else
2600 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2601
2602 put_cpu();
2603
2604 return ret;
2605 }
2606
2607 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2608 {
2609 struct kvm_vcpu_arch *vcpu = &v->arch;
2610 struct pvclock_vcpu_time_info guest_hv_clock;
2611
2612 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2613 &guest_hv_clock, sizeof(guest_hv_clock))))
2614 return;
2615
2616 /* This VCPU is paused, but it's legal for a guest to read another
2617 * VCPU's kvmclock, so we really have to follow the specification where
2618 * it says that version is odd if data is being modified, and even after
2619 * it is consistent.
2620 *
2621 * Version field updates must be kept separate. This is because
2622 * kvm_write_guest_cached might use a "rep movs" instruction, and
2623 * writes within a string instruction are weakly ordered. So there
2624 * are three writes overall.
2625 *
2626 * As a small optimization, only write the version field in the first
2627 * and third write. The vcpu->pv_time cache is still valid, because the
2628 * version field is the first in the struct.
2629 */
2630 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2631
2632 if (guest_hv_clock.version & 1)
2633 ++guest_hv_clock.version; /* first time write, random junk */
2634
2635 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2636 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2637 &vcpu->hv_clock,
2638 sizeof(vcpu->hv_clock.version));
2639
2640 smp_wmb();
2641
2642 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2643 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2644
2645 if (vcpu->pvclock_set_guest_stopped_request) {
2646 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2647 vcpu->pvclock_set_guest_stopped_request = false;
2648 }
2649
2650 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2651
2652 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2653 &vcpu->hv_clock,
2654 sizeof(vcpu->hv_clock));
2655
2656 smp_wmb();
2657
2658 vcpu->hv_clock.version++;
2659 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2660 &vcpu->hv_clock,
2661 sizeof(vcpu->hv_clock.version));
2662 }
2663
2664 static int kvm_guest_time_update(struct kvm_vcpu *v)
2665 {
2666 unsigned long flags, tgt_tsc_khz;
2667 struct kvm_vcpu_arch *vcpu = &v->arch;
2668 struct kvm_arch *ka = &v->kvm->arch;
2669 s64 kernel_ns;
2670 u64 tsc_timestamp, host_tsc;
2671 u8 pvclock_flags;
2672 bool use_master_clock;
2673
2674 kernel_ns = 0;
2675 host_tsc = 0;
2676
2677 /*
2678 * If the host uses TSC clock, then passthrough TSC as stable
2679 * to the guest.
2680 */
2681 spin_lock(&ka->pvclock_gtod_sync_lock);
2682 use_master_clock = ka->use_master_clock;
2683 if (use_master_clock) {
2684 host_tsc = ka->master_cycle_now;
2685 kernel_ns = ka->master_kernel_ns;
2686 }
2687 spin_unlock(&ka->pvclock_gtod_sync_lock);
2688
2689 /* Keep irq disabled to prevent changes to the clock */
2690 local_irq_save(flags);
2691 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2692 if (unlikely(tgt_tsc_khz == 0)) {
2693 local_irq_restore(flags);
2694 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2695 return 1;
2696 }
2697 if (!use_master_clock) {
2698 host_tsc = rdtsc();
2699 kernel_ns = get_kvmclock_base_ns();
2700 }
2701
2702 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2703
2704 /*
2705 * We may have to catch up the TSC to match elapsed wall clock
2706 * time for two reasons, even if kvmclock is used.
2707 * 1) CPU could have been running below the maximum TSC rate
2708 * 2) Broken TSC compensation resets the base at each VCPU
2709 * entry to avoid unknown leaps of TSC even when running
2710 * again on the same CPU. This may cause apparent elapsed
2711 * time to disappear, and the guest to stand still or run
2712 * very slowly.
2713 */
2714 if (vcpu->tsc_catchup) {
2715 u64 tsc = compute_guest_tsc(v, kernel_ns);
2716 if (tsc > tsc_timestamp) {
2717 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2718 tsc_timestamp = tsc;
2719 }
2720 }
2721
2722 local_irq_restore(flags);
2723
2724 /* With all the info we got, fill in the values */
2725
2726 if (kvm_has_tsc_control)
2727 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2728
2729 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2730 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2731 &vcpu->hv_clock.tsc_shift,
2732 &vcpu->hv_clock.tsc_to_system_mul);
2733 vcpu->hw_tsc_khz = tgt_tsc_khz;
2734 }
2735
2736 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2737 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2738 vcpu->last_guest_tsc = tsc_timestamp;
2739
2740 /* If the host uses TSC clocksource, then it is stable */
2741 pvclock_flags = 0;
2742 if (use_master_clock)
2743 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2744
2745 vcpu->hv_clock.flags = pvclock_flags;
2746
2747 if (vcpu->pv_time_enabled)
2748 kvm_setup_pvclock_page(v);
2749 if (v == kvm_get_vcpu(v->kvm, 0))
2750 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2751 return 0;
2752 }
2753
2754 /*
2755 * kvmclock updates which are isolated to a given vcpu, such as
2756 * vcpu->cpu migration, should not allow system_timestamp from
2757 * the rest of the vcpus to remain static. Otherwise ntp frequency
2758 * correction applies to one vcpu's system_timestamp but not
2759 * the others.
2760 *
2761 * So in those cases, request a kvmclock update for all vcpus.
2762 * We need to rate-limit these requests though, as they can
2763 * considerably slow guests that have a large number of vcpus.
2764 * The time for a remote vcpu to update its kvmclock is bound
2765 * by the delay we use to rate-limit the updates.
2766 */
2767
2768 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2769
2770 static void kvmclock_update_fn(struct work_struct *work)
2771 {
2772 int i;
2773 struct delayed_work *dwork = to_delayed_work(work);
2774 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2775 kvmclock_update_work);
2776 struct kvm *kvm = container_of(ka, struct kvm, arch);
2777 struct kvm_vcpu *vcpu;
2778
2779 kvm_for_each_vcpu(i, vcpu, kvm) {
2780 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2781 kvm_vcpu_kick(vcpu);
2782 }
2783 }
2784
2785 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2786 {
2787 struct kvm *kvm = v->kvm;
2788
2789 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2790 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2791 KVMCLOCK_UPDATE_DELAY);
2792 }
2793
2794 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2795
2796 static void kvmclock_sync_fn(struct work_struct *work)
2797 {
2798 struct delayed_work *dwork = to_delayed_work(work);
2799 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2800 kvmclock_sync_work);
2801 struct kvm *kvm = container_of(ka, struct kvm, arch);
2802
2803 if (!kvmclock_periodic_sync)
2804 return;
2805
2806 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2807 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2808 KVMCLOCK_SYNC_PERIOD);
2809 }
2810
2811 /*
2812 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2813 */
2814 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2815 {
2816 /* McStatusWrEn enabled? */
2817 if (guest_cpuid_is_amd_or_hygon(vcpu))
2818 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2819
2820 return false;
2821 }
2822
2823 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2824 {
2825 u64 mcg_cap = vcpu->arch.mcg_cap;
2826 unsigned bank_num = mcg_cap & 0xff;
2827 u32 msr = msr_info->index;
2828 u64 data = msr_info->data;
2829
2830 switch (msr) {
2831 case MSR_IA32_MCG_STATUS:
2832 vcpu->arch.mcg_status = data;
2833 break;
2834 case MSR_IA32_MCG_CTL:
2835 if (!(mcg_cap & MCG_CTL_P) &&
2836 (data || !msr_info->host_initiated))
2837 return 1;
2838 if (data != 0 && data != ~(u64)0)
2839 return 1;
2840 vcpu->arch.mcg_ctl = data;
2841 break;
2842 default:
2843 if (msr >= MSR_IA32_MC0_CTL &&
2844 msr < MSR_IA32_MCx_CTL(bank_num)) {
2845 u32 offset = array_index_nospec(
2846 msr - MSR_IA32_MC0_CTL,
2847 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2848
2849 /* only 0 or all 1s can be written to IA32_MCi_CTL
2850 * some Linux kernels though clear bit 10 in bank 4 to
2851 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2852 * this to avoid an uncatched #GP in the guest
2853 */
2854 if ((offset & 0x3) == 0 &&
2855 data != 0 && (data | (1 << 10)) != ~(u64)0)
2856 return -1;
2857
2858 /* MCi_STATUS */
2859 if (!msr_info->host_initiated &&
2860 (offset & 0x3) == 1 && data != 0) {
2861 if (!can_set_mci_status(vcpu))
2862 return -1;
2863 }
2864
2865 vcpu->arch.mce_banks[offset] = data;
2866 break;
2867 }
2868 return 1;
2869 }
2870 return 0;
2871 }
2872
2873 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2874 {
2875 struct kvm *kvm = vcpu->kvm;
2876 int lm = is_long_mode(vcpu);
2877 u64 blob_addr = lm ? kvm->arch.xen_hvm_config.blob_addr_64
2878 : kvm->arch.xen_hvm_config.blob_addr_32;
2879 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2880 : kvm->arch.xen_hvm_config.blob_size_32;
2881 u32 page_num = data & ~PAGE_MASK;
2882 u64 page_addr = data & PAGE_MASK;
2883 u8 *page;
2884
2885 if (page_num >= blob_size)
2886 return 1;
2887
2888 blob_addr += page_num * PAGE_SIZE;
2889
2890 page = memdup_user((u8 __user *)blob_addr, PAGE_SIZE);
2891 if (IS_ERR(page))
2892 return PTR_ERR(page);
2893
2894 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) {
2895 kfree(page);
2896 return 1;
2897 }
2898 return 0;
2899 }
2900
2901 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2902 {
2903 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2904
2905 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2906 }
2907
2908 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2909 {
2910 gpa_t gpa = data & ~0x3f;
2911
2912 /* Bits 4:5 are reserved, Should be zero */
2913 if (data & 0x30)
2914 return 1;
2915
2916 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
2917 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
2918 return 1;
2919
2920 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
2921 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
2922 return 1;
2923
2924 if (!lapic_in_kernel(vcpu))
2925 return data ? 1 : 0;
2926
2927 vcpu->arch.apf.msr_en_val = data;
2928
2929 if (!kvm_pv_async_pf_enabled(vcpu)) {
2930 kvm_clear_async_pf_completion_queue(vcpu);
2931 kvm_async_pf_hash_reset(vcpu);
2932 return 0;
2933 }
2934
2935 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2936 sizeof(u64)))
2937 return 1;
2938
2939 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2940 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2941
2942 kvm_async_pf_wakeup_all(vcpu);
2943
2944 return 0;
2945 }
2946
2947 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2948 {
2949 /* Bits 8-63 are reserved */
2950 if (data >> 8)
2951 return 1;
2952
2953 if (!lapic_in_kernel(vcpu))
2954 return 1;
2955
2956 vcpu->arch.apf.msr_int_val = data;
2957
2958 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2959
2960 return 0;
2961 }
2962
2963 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2964 {
2965 vcpu->arch.pv_time_enabled = false;
2966 vcpu->arch.time = 0;
2967 }
2968
2969 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2970 {
2971 ++vcpu->stat.tlb_flush;
2972 static_call(kvm_x86_tlb_flush_all)(vcpu);
2973 }
2974
2975 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2976 {
2977 ++vcpu->stat.tlb_flush;
2978 static_call(kvm_x86_tlb_flush_guest)(vcpu);
2979 }
2980
2981 static void record_steal_time(struct kvm_vcpu *vcpu)
2982 {
2983 struct kvm_host_map map;
2984 struct kvm_steal_time *st;
2985
2986 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2987 return;
2988
2989 /* -EAGAIN is returned in atomic context so we can just return. */
2990 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2991 &map, &vcpu->arch.st.cache, false))
2992 return;
2993
2994 st = map.hva +
2995 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2996
2997 /*
2998 * Doing a TLB flush here, on the guest's behalf, can avoid
2999 * expensive IPIs.
3000 */
3001 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3002 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3003 st->preempted & KVM_VCPU_FLUSH_TLB);
3004 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
3005 kvm_vcpu_flush_tlb_guest(vcpu);
3006 }
3007
3008 vcpu->arch.st.preempted = 0;
3009
3010 if (st->version & 1)
3011 st->version += 1; /* first time write, random junk */
3012
3013 st->version += 1;
3014
3015 smp_wmb();
3016
3017 st->steal += current->sched_info.run_delay -
3018 vcpu->arch.st.last_steal;
3019 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3020
3021 smp_wmb();
3022
3023 st->version += 1;
3024
3025 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
3026 }
3027
3028 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3029 {
3030 bool pr = false;
3031 u32 msr = msr_info->index;
3032 u64 data = msr_info->data;
3033
3034 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3035 return xen_hvm_config(vcpu, data);
3036
3037 switch (msr) {
3038 case MSR_AMD64_NB_CFG:
3039 case MSR_IA32_UCODE_WRITE:
3040 case MSR_VM_HSAVE_PA:
3041 case MSR_AMD64_PATCH_LOADER:
3042 case MSR_AMD64_BU_CFG2:
3043 case MSR_AMD64_DC_CFG:
3044 case MSR_F15H_EX_CFG:
3045 break;
3046
3047 case MSR_IA32_UCODE_REV:
3048 if (msr_info->host_initiated)
3049 vcpu->arch.microcode_version = data;
3050 break;
3051 case MSR_IA32_ARCH_CAPABILITIES:
3052 if (!msr_info->host_initiated)
3053 return 1;
3054 vcpu->arch.arch_capabilities = data;
3055 break;
3056 case MSR_IA32_PERF_CAPABILITIES: {
3057 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3058
3059 if (!msr_info->host_initiated)
3060 return 1;
3061 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3062 return 1;
3063 if (data & ~msr_ent.data)
3064 return 1;
3065
3066 vcpu->arch.perf_capabilities = data;
3067
3068 return 0;
3069 }
3070 case MSR_EFER:
3071 return set_efer(vcpu, msr_info);
3072 case MSR_K7_HWCR:
3073 data &= ~(u64)0x40; /* ignore flush filter disable */
3074 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3075 data &= ~(u64)0x8; /* ignore TLB cache disable */
3076
3077 /* Handle McStatusWrEn */
3078 if (data == BIT_ULL(18)) {
3079 vcpu->arch.msr_hwcr = data;
3080 } else if (data != 0) {
3081 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3082 data);
3083 return 1;
3084 }
3085 break;
3086 case MSR_FAM10H_MMIO_CONF_BASE:
3087 if (data != 0) {
3088 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3089 "0x%llx\n", data);
3090 return 1;
3091 }
3092 break;
3093 case 0x200 ... 0x2ff:
3094 return kvm_mtrr_set_msr(vcpu, msr, data);
3095 case MSR_IA32_APICBASE:
3096 return kvm_set_apic_base(vcpu, msr_info);
3097 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3098 return kvm_x2apic_msr_write(vcpu, msr, data);
3099 case MSR_IA32_TSCDEADLINE:
3100 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3101 break;
3102 case MSR_IA32_TSC_ADJUST:
3103 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3104 if (!msr_info->host_initiated) {
3105 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3106 adjust_tsc_offset_guest(vcpu, adj);
3107 }
3108 vcpu->arch.ia32_tsc_adjust_msr = data;
3109 }
3110 break;
3111 case MSR_IA32_MISC_ENABLE:
3112 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3113 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3114 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3115 return 1;
3116 vcpu->arch.ia32_misc_enable_msr = data;
3117 kvm_update_cpuid_runtime(vcpu);
3118 } else {
3119 vcpu->arch.ia32_misc_enable_msr = data;
3120 }
3121 break;
3122 case MSR_IA32_SMBASE:
3123 if (!msr_info->host_initiated)
3124 return 1;
3125 vcpu->arch.smbase = data;
3126 break;
3127 case MSR_IA32_POWER_CTL:
3128 vcpu->arch.msr_ia32_power_ctl = data;
3129 break;
3130 case MSR_IA32_TSC:
3131 if (msr_info->host_initiated) {
3132 kvm_synchronize_tsc(vcpu, data);
3133 } else {
3134 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3135 adjust_tsc_offset_guest(vcpu, adj);
3136 vcpu->arch.ia32_tsc_adjust_msr += adj;
3137 }
3138 break;
3139 case MSR_IA32_XSS:
3140 if (!msr_info->host_initiated &&
3141 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3142 return 1;
3143 /*
3144 * KVM supports exposing PT to the guest, but does not support
3145 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3146 * XSAVES/XRSTORS to save/restore PT MSRs.
3147 */
3148 if (data & ~supported_xss)
3149 return 1;
3150 vcpu->arch.ia32_xss = data;
3151 break;
3152 case MSR_SMI_COUNT:
3153 if (!msr_info->host_initiated)
3154 return 1;
3155 vcpu->arch.smi_count = data;
3156 break;
3157 case MSR_KVM_WALL_CLOCK_NEW:
3158 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3159 return 1;
3160
3161 kvm_write_wall_clock(vcpu->kvm, data);
3162 break;
3163 case MSR_KVM_WALL_CLOCK:
3164 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3165 return 1;
3166
3167 kvm_write_wall_clock(vcpu->kvm, data);
3168 break;
3169 case MSR_KVM_SYSTEM_TIME_NEW:
3170 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3171 return 1;
3172
3173 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3174 break;
3175 case MSR_KVM_SYSTEM_TIME:
3176 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3177 return 1;
3178
3179 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3180 break;
3181 case MSR_KVM_ASYNC_PF_EN:
3182 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3183 return 1;
3184
3185 if (kvm_pv_enable_async_pf(vcpu, data))
3186 return 1;
3187 break;
3188 case MSR_KVM_ASYNC_PF_INT:
3189 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3190 return 1;
3191
3192 if (kvm_pv_enable_async_pf_int(vcpu, data))
3193 return 1;
3194 break;
3195 case MSR_KVM_ASYNC_PF_ACK:
3196 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3197 return 1;
3198 if (data & 0x1) {
3199 vcpu->arch.apf.pageready_pending = false;
3200 kvm_check_async_pf_completion(vcpu);
3201 }
3202 break;
3203 case MSR_KVM_STEAL_TIME:
3204 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3205 return 1;
3206
3207 if (unlikely(!sched_info_on()))
3208 return 1;
3209
3210 if (data & KVM_STEAL_RESERVED_MASK)
3211 return 1;
3212
3213 vcpu->arch.st.msr_val = data;
3214
3215 if (!(data & KVM_MSR_ENABLED))
3216 break;
3217
3218 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3219
3220 break;
3221 case MSR_KVM_PV_EOI_EN:
3222 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3223 return 1;
3224
3225 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3226 return 1;
3227 break;
3228
3229 case MSR_KVM_POLL_CONTROL:
3230 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3231 return 1;
3232
3233 /* only enable bit supported */
3234 if (data & (-1ULL << 1))
3235 return 1;
3236
3237 vcpu->arch.msr_kvm_poll_control = data;
3238 break;
3239
3240 case MSR_IA32_MCG_CTL:
3241 case MSR_IA32_MCG_STATUS:
3242 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3243 return set_msr_mce(vcpu, msr_info);
3244
3245 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3246 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3247 pr = true;
3248 fallthrough;
3249 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3250 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3251 if (kvm_pmu_is_valid_msr(vcpu, msr))
3252 return kvm_pmu_set_msr(vcpu, msr_info);
3253
3254 if (pr || data != 0)
3255 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3256 "0x%x data 0x%llx\n", msr, data);
3257 break;
3258 case MSR_K7_CLK_CTL:
3259 /*
3260 * Ignore all writes to this no longer documented MSR.
3261 * Writes are only relevant for old K7 processors,
3262 * all pre-dating SVM, but a recommended workaround from
3263 * AMD for these chips. It is possible to specify the
3264 * affected processor models on the command line, hence
3265 * the need to ignore the workaround.
3266 */
3267 break;
3268 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3269 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3270 case HV_X64_MSR_SYNDBG_OPTIONS:
3271 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3272 case HV_X64_MSR_CRASH_CTL:
3273 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3274 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3275 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3276 case HV_X64_MSR_TSC_EMULATION_STATUS:
3277 return kvm_hv_set_msr_common(vcpu, msr, data,
3278 msr_info->host_initiated);
3279 case MSR_IA32_BBL_CR_CTL3:
3280 /* Drop writes to this legacy MSR -- see rdmsr
3281 * counterpart for further detail.
3282 */
3283 if (report_ignored_msrs)
3284 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3285 msr, data);
3286 break;
3287 case MSR_AMD64_OSVW_ID_LENGTH:
3288 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3289 return 1;
3290 vcpu->arch.osvw.length = data;
3291 break;
3292 case MSR_AMD64_OSVW_STATUS:
3293 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3294 return 1;
3295 vcpu->arch.osvw.status = data;
3296 break;
3297 case MSR_PLATFORM_INFO:
3298 if (!msr_info->host_initiated ||
3299 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3300 cpuid_fault_enabled(vcpu)))
3301 return 1;
3302 vcpu->arch.msr_platform_info = data;
3303 break;
3304 case MSR_MISC_FEATURES_ENABLES:
3305 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3306 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3307 !supports_cpuid_fault(vcpu)))
3308 return 1;
3309 vcpu->arch.msr_misc_features_enables = data;
3310 break;
3311 default:
3312 if (kvm_pmu_is_valid_msr(vcpu, msr))
3313 return kvm_pmu_set_msr(vcpu, msr_info);
3314 return KVM_MSR_RET_INVALID;
3315 }
3316 return 0;
3317 }
3318 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3319
3320 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3321 {
3322 u64 data;
3323 u64 mcg_cap = vcpu->arch.mcg_cap;
3324 unsigned bank_num = mcg_cap & 0xff;
3325
3326 switch (msr) {
3327 case MSR_IA32_P5_MC_ADDR:
3328 case MSR_IA32_P5_MC_TYPE:
3329 data = 0;
3330 break;
3331 case MSR_IA32_MCG_CAP:
3332 data = vcpu->arch.mcg_cap;
3333 break;
3334 case MSR_IA32_MCG_CTL:
3335 if (!(mcg_cap & MCG_CTL_P) && !host)
3336 return 1;
3337 data = vcpu->arch.mcg_ctl;
3338 break;
3339 case MSR_IA32_MCG_STATUS:
3340 data = vcpu->arch.mcg_status;
3341 break;
3342 default:
3343 if (msr >= MSR_IA32_MC0_CTL &&
3344 msr < MSR_IA32_MCx_CTL(bank_num)) {
3345 u32 offset = array_index_nospec(
3346 msr - MSR_IA32_MC0_CTL,
3347 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3348
3349 data = vcpu->arch.mce_banks[offset];
3350 break;
3351 }
3352 return 1;
3353 }
3354 *pdata = data;
3355 return 0;
3356 }
3357
3358 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3359 {
3360 switch (msr_info->index) {
3361 case MSR_IA32_PLATFORM_ID:
3362 case MSR_IA32_EBL_CR_POWERON:
3363 case MSR_IA32_LASTBRANCHFROMIP:
3364 case MSR_IA32_LASTBRANCHTOIP:
3365 case MSR_IA32_LASTINTFROMIP:
3366 case MSR_IA32_LASTINTTOIP:
3367 case MSR_K8_SYSCFG:
3368 case MSR_K8_TSEG_ADDR:
3369 case MSR_K8_TSEG_MASK:
3370 case MSR_VM_HSAVE_PA:
3371 case MSR_K8_INT_PENDING_MSG:
3372 case MSR_AMD64_NB_CFG:
3373 case MSR_FAM10H_MMIO_CONF_BASE:
3374 case MSR_AMD64_BU_CFG2:
3375 case MSR_IA32_PERF_CTL:
3376 case MSR_AMD64_DC_CFG:
3377 case MSR_F15H_EX_CFG:
3378 /*
3379 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3380 * limit) MSRs. Just return 0, as we do not want to expose the host
3381 * data here. Do not conditionalize this on CPUID, as KVM does not do
3382 * so for existing CPU-specific MSRs.
3383 */
3384 case MSR_RAPL_POWER_UNIT:
3385 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3386 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3387 case MSR_PKG_ENERGY_STATUS: /* Total package */
3388 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3389 msr_info->data = 0;
3390 break;
3391 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3392 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3393 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3394 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3395 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3396 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3397 return kvm_pmu_get_msr(vcpu, msr_info);
3398 msr_info->data = 0;
3399 break;
3400 case MSR_IA32_UCODE_REV:
3401 msr_info->data = vcpu->arch.microcode_version;
3402 break;
3403 case MSR_IA32_ARCH_CAPABILITIES:
3404 if (!msr_info->host_initiated &&
3405 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3406 return 1;
3407 msr_info->data = vcpu->arch.arch_capabilities;
3408 break;
3409 case MSR_IA32_PERF_CAPABILITIES:
3410 if (!msr_info->host_initiated &&
3411 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3412 return 1;
3413 msr_info->data = vcpu->arch.perf_capabilities;
3414 break;
3415 case MSR_IA32_POWER_CTL:
3416 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3417 break;
3418 case MSR_IA32_TSC: {
3419 /*
3420 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3421 * even when not intercepted. AMD manual doesn't explicitly
3422 * state this but appears to behave the same.
3423 *
3424 * On userspace reads and writes, however, we unconditionally
3425 * return L1's TSC value to ensure backwards-compatible
3426 * behavior for migration.
3427 */
3428 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3429 vcpu->arch.tsc_offset;
3430
3431 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3432 break;
3433 }
3434 case MSR_MTRRcap:
3435 case 0x200 ... 0x2ff:
3436 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3437 case 0xcd: /* fsb frequency */
3438 msr_info->data = 3;
3439 break;
3440 /*
3441 * MSR_EBC_FREQUENCY_ID
3442 * Conservative value valid for even the basic CPU models.
3443 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3444 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3445 * and 266MHz for model 3, or 4. Set Core Clock
3446 * Frequency to System Bus Frequency Ratio to 1 (bits
3447 * 31:24) even though these are only valid for CPU
3448 * models > 2, however guests may end up dividing or
3449 * multiplying by zero otherwise.
3450 */
3451 case MSR_EBC_FREQUENCY_ID:
3452 msr_info->data = 1 << 24;
3453 break;
3454 case MSR_IA32_APICBASE:
3455 msr_info->data = kvm_get_apic_base(vcpu);
3456 break;
3457 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3458 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3459 case MSR_IA32_TSCDEADLINE:
3460 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3461 break;
3462 case MSR_IA32_TSC_ADJUST:
3463 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3464 break;
3465 case MSR_IA32_MISC_ENABLE:
3466 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3467 break;
3468 case MSR_IA32_SMBASE:
3469 if (!msr_info->host_initiated)
3470 return 1;
3471 msr_info->data = vcpu->arch.smbase;
3472 break;
3473 case MSR_SMI_COUNT:
3474 msr_info->data = vcpu->arch.smi_count;
3475 break;
3476 case MSR_IA32_PERF_STATUS:
3477 /* TSC increment by tick */
3478 msr_info->data = 1000ULL;
3479 /* CPU multiplier */
3480 msr_info->data |= (((uint64_t)4ULL) << 40);
3481 break;
3482 case MSR_EFER:
3483 msr_info->data = vcpu->arch.efer;
3484 break;
3485 case MSR_KVM_WALL_CLOCK:
3486 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3487 return 1;
3488
3489 msr_info->data = vcpu->kvm->arch.wall_clock;
3490 break;
3491 case MSR_KVM_WALL_CLOCK_NEW:
3492 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3493 return 1;
3494
3495 msr_info->data = vcpu->kvm->arch.wall_clock;
3496 break;
3497 case MSR_KVM_SYSTEM_TIME:
3498 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3499 return 1;
3500
3501 msr_info->data = vcpu->arch.time;
3502 break;
3503 case MSR_KVM_SYSTEM_TIME_NEW:
3504 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3505 return 1;
3506
3507 msr_info->data = vcpu->arch.time;
3508 break;
3509 case MSR_KVM_ASYNC_PF_EN:
3510 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3511 return 1;
3512
3513 msr_info->data = vcpu->arch.apf.msr_en_val;
3514 break;
3515 case MSR_KVM_ASYNC_PF_INT:
3516 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3517 return 1;
3518
3519 msr_info->data = vcpu->arch.apf.msr_int_val;
3520 break;
3521 case MSR_KVM_ASYNC_PF_ACK:
3522 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3523 return 1;
3524
3525 msr_info->data = 0;
3526 break;
3527 case MSR_KVM_STEAL_TIME:
3528 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3529 return 1;
3530
3531 msr_info->data = vcpu->arch.st.msr_val;
3532 break;
3533 case MSR_KVM_PV_EOI_EN:
3534 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3535 return 1;
3536
3537 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3538 break;
3539 case MSR_KVM_POLL_CONTROL:
3540 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3541 return 1;
3542
3543 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3544 break;
3545 case MSR_IA32_P5_MC_ADDR:
3546 case MSR_IA32_P5_MC_TYPE:
3547 case MSR_IA32_MCG_CAP:
3548 case MSR_IA32_MCG_CTL:
3549 case MSR_IA32_MCG_STATUS:
3550 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3551 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3552 msr_info->host_initiated);
3553 case MSR_IA32_XSS:
3554 if (!msr_info->host_initiated &&
3555 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3556 return 1;
3557 msr_info->data = vcpu->arch.ia32_xss;
3558 break;
3559 case MSR_K7_CLK_CTL:
3560 /*
3561 * Provide expected ramp-up count for K7. All other
3562 * are set to zero, indicating minimum divisors for
3563 * every field.
3564 *
3565 * This prevents guest kernels on AMD host with CPU
3566 * type 6, model 8 and higher from exploding due to
3567 * the rdmsr failing.
3568 */
3569 msr_info->data = 0x20000000;
3570 break;
3571 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3572 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3573 case HV_X64_MSR_SYNDBG_OPTIONS:
3574 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3575 case HV_X64_MSR_CRASH_CTL:
3576 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3577 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3578 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3579 case HV_X64_MSR_TSC_EMULATION_STATUS:
3580 return kvm_hv_get_msr_common(vcpu,
3581 msr_info->index, &msr_info->data,
3582 msr_info->host_initiated);
3583 case MSR_IA32_BBL_CR_CTL3:
3584 /* This legacy MSR exists but isn't fully documented in current
3585 * silicon. It is however accessed by winxp in very narrow
3586 * scenarios where it sets bit #19, itself documented as
3587 * a "reserved" bit. Best effort attempt to source coherent
3588 * read data here should the balance of the register be
3589 * interpreted by the guest:
3590 *
3591 * L2 cache control register 3: 64GB range, 256KB size,
3592 * enabled, latency 0x1, configured
3593 */
3594 msr_info->data = 0xbe702111;
3595 break;
3596 case MSR_AMD64_OSVW_ID_LENGTH:
3597 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3598 return 1;
3599 msr_info->data = vcpu->arch.osvw.length;
3600 break;
3601 case MSR_AMD64_OSVW_STATUS:
3602 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3603 return 1;
3604 msr_info->data = vcpu->arch.osvw.status;
3605 break;
3606 case MSR_PLATFORM_INFO:
3607 if (!msr_info->host_initiated &&
3608 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3609 return 1;
3610 msr_info->data = vcpu->arch.msr_platform_info;
3611 break;
3612 case MSR_MISC_FEATURES_ENABLES:
3613 msr_info->data = vcpu->arch.msr_misc_features_enables;
3614 break;
3615 case MSR_K7_HWCR:
3616 msr_info->data = vcpu->arch.msr_hwcr;
3617 break;
3618 default:
3619 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3620 return kvm_pmu_get_msr(vcpu, msr_info);
3621 return KVM_MSR_RET_INVALID;
3622 }
3623 return 0;
3624 }
3625 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3626
3627 /*
3628 * Read or write a bunch of msrs. All parameters are kernel addresses.
3629 *
3630 * @return number of msrs set successfully.
3631 */
3632 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3633 struct kvm_msr_entry *entries,
3634 int (*do_msr)(struct kvm_vcpu *vcpu,
3635 unsigned index, u64 *data))
3636 {
3637 int i;
3638
3639 for (i = 0; i < msrs->nmsrs; ++i)
3640 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3641 break;
3642
3643 return i;
3644 }
3645
3646 /*
3647 * Read or write a bunch of msrs. Parameters are user addresses.
3648 *
3649 * @return number of msrs set successfully.
3650 */
3651 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3652 int (*do_msr)(struct kvm_vcpu *vcpu,
3653 unsigned index, u64 *data),
3654 int writeback)
3655 {
3656 struct kvm_msrs msrs;
3657 struct kvm_msr_entry *entries;
3658 int r, n;
3659 unsigned size;
3660
3661 r = -EFAULT;
3662 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3663 goto out;
3664
3665 r = -E2BIG;
3666 if (msrs.nmsrs >= MAX_IO_MSRS)
3667 goto out;
3668
3669 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3670 entries = memdup_user(user_msrs->entries, size);
3671 if (IS_ERR(entries)) {
3672 r = PTR_ERR(entries);
3673 goto out;
3674 }
3675
3676 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3677 if (r < 0)
3678 goto out_free;
3679
3680 r = -EFAULT;
3681 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3682 goto out_free;
3683
3684 r = n;
3685
3686 out_free:
3687 kfree(entries);
3688 out:
3689 return r;
3690 }
3691
3692 static inline bool kvm_can_mwait_in_guest(void)
3693 {
3694 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3695 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3696 boot_cpu_has(X86_FEATURE_ARAT);
3697 }
3698
3699 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
3700 struct kvm_cpuid2 __user *cpuid_arg)
3701 {
3702 struct kvm_cpuid2 cpuid;
3703 int r;
3704
3705 r = -EFAULT;
3706 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3707 return r;
3708
3709 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3710 if (r)
3711 return r;
3712
3713 r = -EFAULT;
3714 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3715 return r;
3716
3717 return 0;
3718 }
3719
3720 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3721 {
3722 int r = 0;
3723
3724 switch (ext) {
3725 case KVM_CAP_IRQCHIP:
3726 case KVM_CAP_HLT:
3727 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3728 case KVM_CAP_SET_TSS_ADDR:
3729 case KVM_CAP_EXT_CPUID:
3730 case KVM_CAP_EXT_EMUL_CPUID:
3731 case KVM_CAP_CLOCKSOURCE:
3732 case KVM_CAP_PIT:
3733 case KVM_CAP_NOP_IO_DELAY:
3734 case KVM_CAP_MP_STATE:
3735 case KVM_CAP_SYNC_MMU:
3736 case KVM_CAP_USER_NMI:
3737 case KVM_CAP_REINJECT_CONTROL:
3738 case KVM_CAP_IRQ_INJECT_STATUS:
3739 case KVM_CAP_IOEVENTFD:
3740 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3741 case KVM_CAP_PIT2:
3742 case KVM_CAP_PIT_STATE2:
3743 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3744 case KVM_CAP_XEN_HVM:
3745 case KVM_CAP_VCPU_EVENTS:
3746 case KVM_CAP_HYPERV:
3747 case KVM_CAP_HYPERV_VAPIC:
3748 case KVM_CAP_HYPERV_SPIN:
3749 case KVM_CAP_HYPERV_SYNIC:
3750 case KVM_CAP_HYPERV_SYNIC2:
3751 case KVM_CAP_HYPERV_VP_INDEX:
3752 case KVM_CAP_HYPERV_EVENTFD:
3753 case KVM_CAP_HYPERV_TLBFLUSH:
3754 case KVM_CAP_HYPERV_SEND_IPI:
3755 case KVM_CAP_HYPERV_CPUID:
3756 case KVM_CAP_SYS_HYPERV_CPUID:
3757 case KVM_CAP_PCI_SEGMENT:
3758 case KVM_CAP_DEBUGREGS:
3759 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3760 case KVM_CAP_XSAVE:
3761 case KVM_CAP_ASYNC_PF:
3762 case KVM_CAP_ASYNC_PF_INT:
3763 case KVM_CAP_GET_TSC_KHZ:
3764 case KVM_CAP_KVMCLOCK_CTRL:
3765 case KVM_CAP_READONLY_MEM:
3766 case KVM_CAP_HYPERV_TIME:
3767 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3768 case KVM_CAP_TSC_DEADLINE_TIMER:
3769 case KVM_CAP_DISABLE_QUIRKS:
3770 case KVM_CAP_SET_BOOT_CPU_ID:
3771 case KVM_CAP_SPLIT_IRQCHIP:
3772 case KVM_CAP_IMMEDIATE_EXIT:
3773 case KVM_CAP_PMU_EVENT_FILTER:
3774 case KVM_CAP_GET_MSR_FEATURES:
3775 case KVM_CAP_MSR_PLATFORM_INFO:
3776 case KVM_CAP_EXCEPTION_PAYLOAD:
3777 case KVM_CAP_SET_GUEST_DEBUG:
3778 case KVM_CAP_LAST_CPU:
3779 case KVM_CAP_X86_USER_SPACE_MSR:
3780 case KVM_CAP_X86_MSR_FILTER:
3781 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
3782 r = 1;
3783 break;
3784 case KVM_CAP_SYNC_REGS:
3785 r = KVM_SYNC_X86_VALID_FIELDS;
3786 break;
3787 case KVM_CAP_ADJUST_CLOCK:
3788 r = KVM_CLOCK_TSC_STABLE;
3789 break;
3790 case KVM_CAP_X86_DISABLE_EXITS:
3791 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3792 KVM_X86_DISABLE_EXITS_CSTATE;
3793 if(kvm_can_mwait_in_guest())
3794 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3795 break;
3796 case KVM_CAP_X86_SMM:
3797 /* SMBASE is usually relocated above 1M on modern chipsets,
3798 * and SMM handlers might indeed rely on 4G segment limits,
3799 * so do not report SMM to be available if real mode is
3800 * emulated via vm86 mode. Still, do not go to great lengths
3801 * to avoid userspace's usage of the feature, because it is a
3802 * fringe case that is not enabled except via specific settings
3803 * of the module parameters.
3804 */
3805 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
3806 break;
3807 case KVM_CAP_VAPIC:
3808 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)();
3809 break;
3810 case KVM_CAP_NR_VCPUS:
3811 r = KVM_SOFT_MAX_VCPUS;
3812 break;
3813 case KVM_CAP_MAX_VCPUS:
3814 r = KVM_MAX_VCPUS;
3815 break;
3816 case KVM_CAP_MAX_VCPU_ID:
3817 r = KVM_MAX_VCPU_ID;
3818 break;
3819 case KVM_CAP_PV_MMU: /* obsolete */
3820 r = 0;
3821 break;
3822 case KVM_CAP_MCE:
3823 r = KVM_MAX_MCE_BANKS;
3824 break;
3825 case KVM_CAP_XCRS:
3826 r = boot_cpu_has(X86_FEATURE_XSAVE);
3827 break;
3828 case KVM_CAP_TSC_CONTROL:
3829 r = kvm_has_tsc_control;
3830 break;
3831 case KVM_CAP_X2APIC_API:
3832 r = KVM_X2APIC_API_VALID_FLAGS;
3833 break;
3834 case KVM_CAP_NESTED_STATE:
3835 r = kvm_x86_ops.nested_ops->get_state ?
3836 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3837 break;
3838 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3839 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3840 break;
3841 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3842 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3843 break;
3844 case KVM_CAP_SMALLER_MAXPHYADDR:
3845 r = (int) allow_smaller_maxphyaddr;
3846 break;
3847 case KVM_CAP_STEAL_TIME:
3848 r = sched_info_on();
3849 break;
3850 case KVM_CAP_X86_BUS_LOCK_EXIT:
3851 if (kvm_has_bus_lock_exit)
3852 r = KVM_BUS_LOCK_DETECTION_OFF |
3853 KVM_BUS_LOCK_DETECTION_EXIT;
3854 else
3855 r = 0;
3856 break;
3857 default:
3858 break;
3859 }
3860 return r;
3861
3862 }
3863
3864 long kvm_arch_dev_ioctl(struct file *filp,
3865 unsigned int ioctl, unsigned long arg)
3866 {
3867 void __user *argp = (void __user *)arg;
3868 long r;
3869
3870 switch (ioctl) {
3871 case KVM_GET_MSR_INDEX_LIST: {
3872 struct kvm_msr_list __user *user_msr_list = argp;
3873 struct kvm_msr_list msr_list;
3874 unsigned n;
3875
3876 r = -EFAULT;
3877 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3878 goto out;
3879 n = msr_list.nmsrs;
3880 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3881 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3882 goto out;
3883 r = -E2BIG;
3884 if (n < msr_list.nmsrs)
3885 goto out;
3886 r = -EFAULT;
3887 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3888 num_msrs_to_save * sizeof(u32)))
3889 goto out;
3890 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3891 &emulated_msrs,
3892 num_emulated_msrs * sizeof(u32)))
3893 goto out;
3894 r = 0;
3895 break;
3896 }
3897 case KVM_GET_SUPPORTED_CPUID:
3898 case KVM_GET_EMULATED_CPUID: {
3899 struct kvm_cpuid2 __user *cpuid_arg = argp;
3900 struct kvm_cpuid2 cpuid;
3901
3902 r = -EFAULT;
3903 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3904 goto out;
3905
3906 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3907 ioctl);
3908 if (r)
3909 goto out;
3910
3911 r = -EFAULT;
3912 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3913 goto out;
3914 r = 0;
3915 break;
3916 }
3917 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3918 r = -EFAULT;
3919 if (copy_to_user(argp, &kvm_mce_cap_supported,
3920 sizeof(kvm_mce_cap_supported)))
3921 goto out;
3922 r = 0;
3923 break;
3924 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3925 struct kvm_msr_list __user *user_msr_list = argp;
3926 struct kvm_msr_list msr_list;
3927 unsigned int n;
3928
3929 r = -EFAULT;
3930 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3931 goto out;
3932 n = msr_list.nmsrs;
3933 msr_list.nmsrs = num_msr_based_features;
3934 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3935 goto out;
3936 r = -E2BIG;
3937 if (n < msr_list.nmsrs)
3938 goto out;
3939 r = -EFAULT;
3940 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3941 num_msr_based_features * sizeof(u32)))
3942 goto out;
3943 r = 0;
3944 break;
3945 }
3946 case KVM_GET_MSRS:
3947 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3948 break;
3949 case KVM_GET_SUPPORTED_HV_CPUID:
3950 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
3951 break;
3952 default:
3953 r = -EINVAL;
3954 break;
3955 }
3956 out:
3957 return r;
3958 }
3959
3960 static void wbinvd_ipi(void *garbage)
3961 {
3962 wbinvd();
3963 }
3964
3965 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3966 {
3967 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3968 }
3969
3970 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3971 {
3972 /* Address WBINVD may be executed by guest */
3973 if (need_emulate_wbinvd(vcpu)) {
3974 if (static_call(kvm_x86_has_wbinvd_exit)())
3975 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3976 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3977 smp_call_function_single(vcpu->cpu,
3978 wbinvd_ipi, NULL, 1);
3979 }
3980
3981 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
3982
3983 /* Save host pkru register if supported */
3984 vcpu->arch.host_pkru = read_pkru();
3985
3986 /* Apply any externally detected TSC adjustments (due to suspend) */
3987 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3988 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3989 vcpu->arch.tsc_offset_adjustment = 0;
3990 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3991 }
3992
3993 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3994 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3995 rdtsc() - vcpu->arch.last_host_tsc;
3996 if (tsc_delta < 0)
3997 mark_tsc_unstable("KVM discovered backwards TSC");
3998
3999 if (kvm_check_tsc_unstable()) {
4000 u64 offset = kvm_compute_tsc_offset(vcpu,
4001 vcpu->arch.last_guest_tsc);
4002 kvm_vcpu_write_tsc_offset(vcpu, offset);
4003 vcpu->arch.tsc_catchup = 1;
4004 }
4005
4006 if (kvm_lapic_hv_timer_in_use(vcpu))
4007 kvm_lapic_restart_hv_timer(vcpu);
4008
4009 /*
4010 * On a host with synchronized TSC, there is no need to update
4011 * kvmclock on vcpu->cpu migration
4012 */
4013 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4014 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4015 if (vcpu->cpu != cpu)
4016 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4017 vcpu->cpu = cpu;
4018 }
4019
4020 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4021 }
4022
4023 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4024 {
4025 struct kvm_host_map map;
4026 struct kvm_steal_time *st;
4027 int idx;
4028
4029 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4030 return;
4031
4032 if (vcpu->arch.st.preempted)
4033 return;
4034
4035 /*
4036 * Take the srcu lock as memslots will be accessed to check the gfn
4037 * cache generation against the memslots generation.
4038 */
4039 idx = srcu_read_lock(&vcpu->kvm->srcu);
4040
4041 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
4042 &vcpu->arch.st.cache, true))
4043 goto out;
4044
4045 st = map.hva +
4046 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
4047
4048 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4049
4050 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
4051
4052 out:
4053 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4054 }
4055
4056 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4057 {
4058 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4059 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4060
4061 kvm_steal_time_set_preempted(vcpu);
4062 static_call(kvm_x86_vcpu_put)(vcpu);
4063 vcpu->arch.last_host_tsc = rdtsc();
4064 /*
4065 * If userspace has set any breakpoints or watchpoints, dr6 is restored
4066 * on every vmexit, but if not, we might have a stale dr6 from the
4067 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
4068 */
4069 set_debugreg(0, 6);
4070 }
4071
4072 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4073 struct kvm_lapic_state *s)
4074 {
4075 if (vcpu->arch.apicv_active)
4076 static_call(kvm_x86_sync_pir_to_irr)(vcpu);
4077
4078 return kvm_apic_get_state(vcpu, s);
4079 }
4080
4081 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4082 struct kvm_lapic_state *s)
4083 {
4084 int r;
4085
4086 r = kvm_apic_set_state(vcpu, s);
4087 if (r)
4088 return r;
4089 update_cr8_intercept(vcpu);
4090
4091 return 0;
4092 }
4093
4094 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4095 {
4096 /*
4097 * We can accept userspace's request for interrupt injection
4098 * as long as we have a place to store the interrupt number.
4099 * The actual injection will happen when the CPU is able to
4100 * deliver the interrupt.
4101 */
4102 if (kvm_cpu_has_extint(vcpu))
4103 return false;
4104
4105 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4106 return (!lapic_in_kernel(vcpu) ||
4107 kvm_apic_accept_pic_intr(vcpu));
4108 }
4109
4110 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4111 {
4112 return kvm_arch_interrupt_allowed(vcpu) &&
4113 kvm_cpu_accept_dm_intr(vcpu);
4114 }
4115
4116 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4117 struct kvm_interrupt *irq)
4118 {
4119 if (irq->irq >= KVM_NR_INTERRUPTS)
4120 return -EINVAL;
4121
4122 if (!irqchip_in_kernel(vcpu->kvm)) {
4123 kvm_queue_interrupt(vcpu, irq->irq, false);
4124 kvm_make_request(KVM_REQ_EVENT, vcpu);
4125 return 0;
4126 }
4127
4128 /*
4129 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4130 * fail for in-kernel 8259.
4131 */
4132 if (pic_in_kernel(vcpu->kvm))
4133 return -ENXIO;
4134
4135 if (vcpu->arch.pending_external_vector != -1)
4136 return -EEXIST;
4137
4138 vcpu->arch.pending_external_vector = irq->irq;
4139 kvm_make_request(KVM_REQ_EVENT, vcpu);
4140 return 0;
4141 }
4142
4143 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4144 {
4145 kvm_inject_nmi(vcpu);
4146
4147 return 0;
4148 }
4149
4150 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4151 {
4152 kvm_make_request(KVM_REQ_SMI, vcpu);
4153
4154 return 0;
4155 }
4156
4157 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4158 struct kvm_tpr_access_ctl *tac)
4159 {
4160 if (tac->flags)
4161 return -EINVAL;
4162 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4163 return 0;
4164 }
4165
4166 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4167 u64 mcg_cap)
4168 {
4169 int r;
4170 unsigned bank_num = mcg_cap & 0xff, bank;
4171
4172 r = -EINVAL;
4173 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4174 goto out;
4175 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4176 goto out;
4177 r = 0;
4178 vcpu->arch.mcg_cap = mcg_cap;
4179 /* Init IA32_MCG_CTL to all 1s */
4180 if (mcg_cap & MCG_CTL_P)
4181 vcpu->arch.mcg_ctl = ~(u64)0;
4182 /* Init IA32_MCi_CTL to all 1s */
4183 for (bank = 0; bank < bank_num; bank++)
4184 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4185
4186 static_call(kvm_x86_setup_mce)(vcpu);
4187 out:
4188 return r;
4189 }
4190
4191 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4192 struct kvm_x86_mce *mce)
4193 {
4194 u64 mcg_cap = vcpu->arch.mcg_cap;
4195 unsigned bank_num = mcg_cap & 0xff;
4196 u64 *banks = vcpu->arch.mce_banks;
4197
4198 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4199 return -EINVAL;
4200 /*
4201 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4202 * reporting is disabled
4203 */
4204 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4205 vcpu->arch.mcg_ctl != ~(u64)0)
4206 return 0;
4207 banks += 4 * mce->bank;
4208 /*
4209 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4210 * reporting is disabled for the bank
4211 */
4212 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4213 return 0;
4214 if (mce->status & MCI_STATUS_UC) {
4215 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4216 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4217 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4218 return 0;
4219 }
4220 if (banks[1] & MCI_STATUS_VAL)
4221 mce->status |= MCI_STATUS_OVER;
4222 banks[2] = mce->addr;
4223 banks[3] = mce->misc;
4224 vcpu->arch.mcg_status = mce->mcg_status;
4225 banks[1] = mce->status;
4226 kvm_queue_exception(vcpu, MC_VECTOR);
4227 } else if (!(banks[1] & MCI_STATUS_VAL)
4228 || !(banks[1] & MCI_STATUS_UC)) {
4229 if (banks[1] & MCI_STATUS_VAL)
4230 mce->status |= MCI_STATUS_OVER;
4231 banks[2] = mce->addr;
4232 banks[3] = mce->misc;
4233 banks[1] = mce->status;
4234 } else
4235 banks[1] |= MCI_STATUS_OVER;
4236 return 0;
4237 }
4238
4239 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4240 struct kvm_vcpu_events *events)
4241 {
4242 process_nmi(vcpu);
4243
4244 if (kvm_check_request(KVM_REQ_SMI, vcpu))
4245 process_smi(vcpu);
4246
4247 /*
4248 * In guest mode, payload delivery should be deferred,
4249 * so that the L1 hypervisor can intercept #PF before
4250 * CR2 is modified (or intercept #DB before DR6 is
4251 * modified under nVMX). Unless the per-VM capability,
4252 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4253 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4254 * opportunistically defer the exception payload, deliver it if the
4255 * capability hasn't been requested before processing a
4256 * KVM_GET_VCPU_EVENTS.
4257 */
4258 if (!vcpu->kvm->arch.exception_payload_enabled &&
4259 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4260 kvm_deliver_exception_payload(vcpu);
4261
4262 /*
4263 * The API doesn't provide the instruction length for software
4264 * exceptions, so don't report them. As long as the guest RIP
4265 * isn't advanced, we should expect to encounter the exception
4266 * again.
4267 */
4268 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4269 events->exception.injected = 0;
4270 events->exception.pending = 0;
4271 } else {
4272 events->exception.injected = vcpu->arch.exception.injected;
4273 events->exception.pending = vcpu->arch.exception.pending;
4274 /*
4275 * For ABI compatibility, deliberately conflate
4276 * pending and injected exceptions when
4277 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4278 */
4279 if (!vcpu->kvm->arch.exception_payload_enabled)
4280 events->exception.injected |=
4281 vcpu->arch.exception.pending;
4282 }
4283 events->exception.nr = vcpu->arch.exception.nr;
4284 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4285 events->exception.error_code = vcpu->arch.exception.error_code;
4286 events->exception_has_payload = vcpu->arch.exception.has_payload;
4287 events->exception_payload = vcpu->arch.exception.payload;
4288
4289 events->interrupt.injected =
4290 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4291 events->interrupt.nr = vcpu->arch.interrupt.nr;
4292 events->interrupt.soft = 0;
4293 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
4294
4295 events->nmi.injected = vcpu->arch.nmi_injected;
4296 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4297 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
4298 events->nmi.pad = 0;
4299
4300 events->sipi_vector = 0; /* never valid when reporting to user space */
4301
4302 events->smi.smm = is_smm(vcpu);
4303 events->smi.pending = vcpu->arch.smi_pending;
4304 events->smi.smm_inside_nmi =
4305 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4306 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4307
4308 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4309 | KVM_VCPUEVENT_VALID_SHADOW
4310 | KVM_VCPUEVENT_VALID_SMM);
4311 if (vcpu->kvm->arch.exception_payload_enabled)
4312 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4313
4314 memset(&events->reserved, 0, sizeof(events->reserved));
4315 }
4316
4317 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4318
4319 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4320 struct kvm_vcpu_events *events)
4321 {
4322 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4323 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4324 | KVM_VCPUEVENT_VALID_SHADOW
4325 | KVM_VCPUEVENT_VALID_SMM
4326 | KVM_VCPUEVENT_VALID_PAYLOAD))
4327 return -EINVAL;
4328
4329 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4330 if (!vcpu->kvm->arch.exception_payload_enabled)
4331 return -EINVAL;
4332 if (events->exception.pending)
4333 events->exception.injected = 0;
4334 else
4335 events->exception_has_payload = 0;
4336 } else {
4337 events->exception.pending = 0;
4338 events->exception_has_payload = 0;
4339 }
4340
4341 if ((events->exception.injected || events->exception.pending) &&
4342 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4343 return -EINVAL;
4344
4345 /* INITs are latched while in SMM */
4346 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4347 (events->smi.smm || events->smi.pending) &&
4348 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4349 return -EINVAL;
4350
4351 process_nmi(vcpu);
4352 vcpu->arch.exception.injected = events->exception.injected;
4353 vcpu->arch.exception.pending = events->exception.pending;
4354 vcpu->arch.exception.nr = events->exception.nr;
4355 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4356 vcpu->arch.exception.error_code = events->exception.error_code;
4357 vcpu->arch.exception.has_payload = events->exception_has_payload;
4358 vcpu->arch.exception.payload = events->exception_payload;
4359
4360 vcpu->arch.interrupt.injected = events->interrupt.injected;
4361 vcpu->arch.interrupt.nr = events->interrupt.nr;
4362 vcpu->arch.interrupt.soft = events->interrupt.soft;
4363 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4364 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
4365 events->interrupt.shadow);
4366
4367 vcpu->arch.nmi_injected = events->nmi.injected;
4368 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4369 vcpu->arch.nmi_pending = events->nmi.pending;
4370 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
4371
4372 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4373 lapic_in_kernel(vcpu))
4374 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4375
4376 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4377 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4378 if (events->smi.smm)
4379 vcpu->arch.hflags |= HF_SMM_MASK;
4380 else
4381 vcpu->arch.hflags &= ~HF_SMM_MASK;
4382 kvm_smm_changed(vcpu);
4383 }
4384
4385 vcpu->arch.smi_pending = events->smi.pending;
4386
4387 if (events->smi.smm) {
4388 if (events->smi.smm_inside_nmi)
4389 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4390 else
4391 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4392 }
4393
4394 if (lapic_in_kernel(vcpu)) {
4395 if (events->smi.latched_init)
4396 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4397 else
4398 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4399 }
4400 }
4401
4402 kvm_make_request(KVM_REQ_EVENT, vcpu);
4403
4404 return 0;
4405 }
4406
4407 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4408 struct kvm_debugregs *dbgregs)
4409 {
4410 unsigned long val;
4411
4412 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4413 kvm_get_dr(vcpu, 6, &val);
4414 dbgregs->dr6 = val;
4415 dbgregs->dr7 = vcpu->arch.dr7;
4416 dbgregs->flags = 0;
4417 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4418 }
4419
4420 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4421 struct kvm_debugregs *dbgregs)
4422 {
4423 if (dbgregs->flags)
4424 return -EINVAL;
4425
4426 if (!kvm_dr6_valid(dbgregs->dr6))
4427 return -EINVAL;
4428 if (!kvm_dr7_valid(dbgregs->dr7))
4429 return -EINVAL;
4430
4431 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4432 kvm_update_dr0123(vcpu);
4433 vcpu->arch.dr6 = dbgregs->dr6;
4434 vcpu->arch.dr7 = dbgregs->dr7;
4435 kvm_update_dr7(vcpu);
4436
4437 return 0;
4438 }
4439
4440 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4441
4442 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4443 {
4444 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4445 u64 xstate_bv = xsave->header.xfeatures;
4446 u64 valid;
4447
4448 /*
4449 * Copy legacy XSAVE area, to avoid complications with CPUID
4450 * leaves 0 and 1 in the loop below.
4451 */
4452 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4453
4454 /* Set XSTATE_BV */
4455 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4456 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4457
4458 /*
4459 * Copy each region from the possibly compacted offset to the
4460 * non-compacted offset.
4461 */
4462 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4463 while (valid) {
4464 u64 xfeature_mask = valid & -valid;
4465 int xfeature_nr = fls64(xfeature_mask) - 1;
4466 void *src = get_xsave_addr(xsave, xfeature_nr);
4467
4468 if (src) {
4469 u32 size, offset, ecx, edx;
4470 cpuid_count(XSTATE_CPUID, xfeature_nr,
4471 &size, &offset, &ecx, &edx);
4472 if (xfeature_nr == XFEATURE_PKRU)
4473 memcpy(dest + offset, &vcpu->arch.pkru,
4474 sizeof(vcpu->arch.pkru));
4475 else
4476 memcpy(dest + offset, src, size);
4477
4478 }
4479
4480 valid -= xfeature_mask;
4481 }
4482 }
4483
4484 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4485 {
4486 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4487 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4488 u64 valid;
4489
4490 /*
4491 * Copy legacy XSAVE area, to avoid complications with CPUID
4492 * leaves 0 and 1 in the loop below.
4493 */
4494 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4495
4496 /* Set XSTATE_BV and possibly XCOMP_BV. */
4497 xsave->header.xfeatures = xstate_bv;
4498 if (boot_cpu_has(X86_FEATURE_XSAVES))
4499 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4500
4501 /*
4502 * Copy each region from the non-compacted offset to the
4503 * possibly compacted offset.
4504 */
4505 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4506 while (valid) {
4507 u64 xfeature_mask = valid & -valid;
4508 int xfeature_nr = fls64(xfeature_mask) - 1;
4509 void *dest = get_xsave_addr(xsave, xfeature_nr);
4510
4511 if (dest) {
4512 u32 size, offset, ecx, edx;
4513 cpuid_count(XSTATE_CPUID, xfeature_nr,
4514 &size, &offset, &ecx, &edx);
4515 if (xfeature_nr == XFEATURE_PKRU)
4516 memcpy(&vcpu->arch.pkru, src + offset,
4517 sizeof(vcpu->arch.pkru));
4518 else
4519 memcpy(dest, src + offset, size);
4520 }
4521
4522 valid -= xfeature_mask;
4523 }
4524 }
4525
4526 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4527 struct kvm_xsave *guest_xsave)
4528 {
4529 if (!vcpu->arch.guest_fpu)
4530 return;
4531
4532 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4533 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4534 fill_xsave((u8 *) guest_xsave->region, vcpu);
4535 } else {
4536 memcpy(guest_xsave->region,
4537 &vcpu->arch.guest_fpu->state.fxsave,
4538 sizeof(struct fxregs_state));
4539 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4540 XFEATURE_MASK_FPSSE;
4541 }
4542 }
4543
4544 #define XSAVE_MXCSR_OFFSET 24
4545
4546 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4547 struct kvm_xsave *guest_xsave)
4548 {
4549 u64 xstate_bv;
4550 u32 mxcsr;
4551
4552 if (!vcpu->arch.guest_fpu)
4553 return 0;
4554
4555 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4556 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4557
4558 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4559 /*
4560 * Here we allow setting states that are not present in
4561 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4562 * with old userspace.
4563 */
4564 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4565 return -EINVAL;
4566 load_xsave(vcpu, (u8 *)guest_xsave->region);
4567 } else {
4568 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4569 mxcsr & ~mxcsr_feature_mask)
4570 return -EINVAL;
4571 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4572 guest_xsave->region, sizeof(struct fxregs_state));
4573 }
4574 return 0;
4575 }
4576
4577 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4578 struct kvm_xcrs *guest_xcrs)
4579 {
4580 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4581 guest_xcrs->nr_xcrs = 0;
4582 return;
4583 }
4584
4585 guest_xcrs->nr_xcrs = 1;
4586 guest_xcrs->flags = 0;
4587 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4588 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4589 }
4590
4591 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4592 struct kvm_xcrs *guest_xcrs)
4593 {
4594 int i, r = 0;
4595
4596 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4597 return -EINVAL;
4598
4599 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4600 return -EINVAL;
4601
4602 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4603 /* Only support XCR0 currently */
4604 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4605 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4606 guest_xcrs->xcrs[i].value);
4607 break;
4608 }
4609 if (r)
4610 r = -EINVAL;
4611 return r;
4612 }
4613
4614 /*
4615 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4616 * stopped by the hypervisor. This function will be called from the host only.
4617 * EINVAL is returned when the host attempts to set the flag for a guest that
4618 * does not support pv clocks.
4619 */
4620 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4621 {
4622 if (!vcpu->arch.pv_time_enabled)
4623 return -EINVAL;
4624 vcpu->arch.pvclock_set_guest_stopped_request = true;
4625 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4626 return 0;
4627 }
4628
4629 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4630 struct kvm_enable_cap *cap)
4631 {
4632 int r;
4633 uint16_t vmcs_version;
4634 void __user *user_ptr;
4635
4636 if (cap->flags)
4637 return -EINVAL;
4638
4639 switch (cap->cap) {
4640 case KVM_CAP_HYPERV_SYNIC2:
4641 if (cap->args[0])
4642 return -EINVAL;
4643 fallthrough;
4644
4645 case KVM_CAP_HYPERV_SYNIC:
4646 if (!irqchip_in_kernel(vcpu->kvm))
4647 return -EINVAL;
4648 return kvm_hv_activate_synic(vcpu, cap->cap ==
4649 KVM_CAP_HYPERV_SYNIC2);
4650 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4651 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4652 return -ENOTTY;
4653 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4654 if (!r) {
4655 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4656 if (copy_to_user(user_ptr, &vmcs_version,
4657 sizeof(vmcs_version)))
4658 r = -EFAULT;
4659 }
4660 return r;
4661 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4662 if (!kvm_x86_ops.enable_direct_tlbflush)
4663 return -ENOTTY;
4664
4665 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu);
4666
4667 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4668 vcpu->arch.pv_cpuid.enforce = cap->args[0];
4669 if (vcpu->arch.pv_cpuid.enforce)
4670 kvm_update_pv_runtime(vcpu);
4671
4672 return 0;
4673
4674 default:
4675 return -EINVAL;
4676 }
4677 }
4678
4679 long kvm_arch_vcpu_ioctl(struct file *filp,
4680 unsigned int ioctl, unsigned long arg)
4681 {
4682 struct kvm_vcpu *vcpu = filp->private_data;
4683 void __user *argp = (void __user *)arg;
4684 int r;
4685 union {
4686 struct kvm_lapic_state *lapic;
4687 struct kvm_xsave *xsave;
4688 struct kvm_xcrs *xcrs;
4689 void *buffer;
4690 } u;
4691
4692 vcpu_load(vcpu);
4693
4694 u.buffer = NULL;
4695 switch (ioctl) {
4696 case KVM_GET_LAPIC: {
4697 r = -EINVAL;
4698 if (!lapic_in_kernel(vcpu))
4699 goto out;
4700 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4701 GFP_KERNEL_ACCOUNT);
4702
4703 r = -ENOMEM;
4704 if (!u.lapic)
4705 goto out;
4706 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4707 if (r)
4708 goto out;
4709 r = -EFAULT;
4710 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4711 goto out;
4712 r = 0;
4713 break;
4714 }
4715 case KVM_SET_LAPIC: {
4716 r = -EINVAL;
4717 if (!lapic_in_kernel(vcpu))
4718 goto out;
4719 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4720 if (IS_ERR(u.lapic)) {
4721 r = PTR_ERR(u.lapic);
4722 goto out_nofree;
4723 }
4724
4725 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4726 break;
4727 }
4728 case KVM_INTERRUPT: {
4729 struct kvm_interrupt irq;
4730
4731 r = -EFAULT;
4732 if (copy_from_user(&irq, argp, sizeof(irq)))
4733 goto out;
4734 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4735 break;
4736 }
4737 case KVM_NMI: {
4738 r = kvm_vcpu_ioctl_nmi(vcpu);
4739 break;
4740 }
4741 case KVM_SMI: {
4742 r = kvm_vcpu_ioctl_smi(vcpu);
4743 break;
4744 }
4745 case KVM_SET_CPUID: {
4746 struct kvm_cpuid __user *cpuid_arg = argp;
4747 struct kvm_cpuid cpuid;
4748
4749 r = -EFAULT;
4750 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4751 goto out;
4752 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4753 break;
4754 }
4755 case KVM_SET_CPUID2: {
4756 struct kvm_cpuid2 __user *cpuid_arg = argp;
4757 struct kvm_cpuid2 cpuid;
4758
4759 r = -EFAULT;
4760 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4761 goto out;
4762 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4763 cpuid_arg->entries);
4764 break;
4765 }
4766 case KVM_GET_CPUID2: {
4767 struct kvm_cpuid2 __user *cpuid_arg = argp;
4768 struct kvm_cpuid2 cpuid;
4769
4770 r = -EFAULT;
4771 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4772 goto out;
4773 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4774 cpuid_arg->entries);
4775 if (r)
4776 goto out;
4777 r = -EFAULT;
4778 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4779 goto out;
4780 r = 0;
4781 break;
4782 }
4783 case KVM_GET_MSRS: {
4784 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4785 r = msr_io(vcpu, argp, do_get_msr, 1);
4786 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4787 break;
4788 }
4789 case KVM_SET_MSRS: {
4790 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4791 r = msr_io(vcpu, argp, do_set_msr, 0);
4792 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4793 break;
4794 }
4795 case KVM_TPR_ACCESS_REPORTING: {
4796 struct kvm_tpr_access_ctl tac;
4797
4798 r = -EFAULT;
4799 if (copy_from_user(&tac, argp, sizeof(tac)))
4800 goto out;
4801 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4802 if (r)
4803 goto out;
4804 r = -EFAULT;
4805 if (copy_to_user(argp, &tac, sizeof(tac)))
4806 goto out;
4807 r = 0;
4808 break;
4809 };
4810 case KVM_SET_VAPIC_ADDR: {
4811 struct kvm_vapic_addr va;
4812 int idx;
4813
4814 r = -EINVAL;
4815 if (!lapic_in_kernel(vcpu))
4816 goto out;
4817 r = -EFAULT;
4818 if (copy_from_user(&va, argp, sizeof(va)))
4819 goto out;
4820 idx = srcu_read_lock(&vcpu->kvm->srcu);
4821 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4822 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4823 break;
4824 }
4825 case KVM_X86_SETUP_MCE: {
4826 u64 mcg_cap;
4827
4828 r = -EFAULT;
4829 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4830 goto out;
4831 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4832 break;
4833 }
4834 case KVM_X86_SET_MCE: {
4835 struct kvm_x86_mce mce;
4836
4837 r = -EFAULT;
4838 if (copy_from_user(&mce, argp, sizeof(mce)))
4839 goto out;
4840 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4841 break;
4842 }
4843 case KVM_GET_VCPU_EVENTS: {
4844 struct kvm_vcpu_events events;
4845
4846 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4847
4848 r = -EFAULT;
4849 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4850 break;
4851 r = 0;
4852 break;
4853 }
4854 case KVM_SET_VCPU_EVENTS: {
4855 struct kvm_vcpu_events events;
4856
4857 r = -EFAULT;
4858 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4859 break;
4860
4861 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4862 break;
4863 }
4864 case KVM_GET_DEBUGREGS: {
4865 struct kvm_debugregs dbgregs;
4866
4867 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4868
4869 r = -EFAULT;
4870 if (copy_to_user(argp, &dbgregs,
4871 sizeof(struct kvm_debugregs)))
4872 break;
4873 r = 0;
4874 break;
4875 }
4876 case KVM_SET_DEBUGREGS: {
4877 struct kvm_debugregs dbgregs;
4878
4879 r = -EFAULT;
4880 if (copy_from_user(&dbgregs, argp,
4881 sizeof(struct kvm_debugregs)))
4882 break;
4883
4884 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4885 break;
4886 }
4887 case KVM_GET_XSAVE: {
4888 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4889 r = -ENOMEM;
4890 if (!u.xsave)
4891 break;
4892
4893 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4894
4895 r = -EFAULT;
4896 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4897 break;
4898 r = 0;
4899 break;
4900 }
4901 case KVM_SET_XSAVE: {
4902 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4903 if (IS_ERR(u.xsave)) {
4904 r = PTR_ERR(u.xsave);
4905 goto out_nofree;
4906 }
4907
4908 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4909 break;
4910 }
4911 case KVM_GET_XCRS: {
4912 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4913 r = -ENOMEM;
4914 if (!u.xcrs)
4915 break;
4916
4917 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4918
4919 r = -EFAULT;
4920 if (copy_to_user(argp, u.xcrs,
4921 sizeof(struct kvm_xcrs)))
4922 break;
4923 r = 0;
4924 break;
4925 }
4926 case KVM_SET_XCRS: {
4927 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4928 if (IS_ERR(u.xcrs)) {
4929 r = PTR_ERR(u.xcrs);
4930 goto out_nofree;
4931 }
4932
4933 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4934 break;
4935 }
4936 case KVM_SET_TSC_KHZ: {
4937 u32 user_tsc_khz;
4938
4939 r = -EINVAL;
4940 user_tsc_khz = (u32)arg;
4941
4942 if (kvm_has_tsc_control &&
4943 user_tsc_khz >= kvm_max_guest_tsc_khz)
4944 goto out;
4945
4946 if (user_tsc_khz == 0)
4947 user_tsc_khz = tsc_khz;
4948
4949 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4950 r = 0;
4951
4952 goto out;
4953 }
4954 case KVM_GET_TSC_KHZ: {
4955 r = vcpu->arch.virtual_tsc_khz;
4956 goto out;
4957 }
4958 case KVM_KVMCLOCK_CTRL: {
4959 r = kvm_set_guest_paused(vcpu);
4960 goto out;
4961 }
4962 case KVM_ENABLE_CAP: {
4963 struct kvm_enable_cap cap;
4964
4965 r = -EFAULT;
4966 if (copy_from_user(&cap, argp, sizeof(cap)))
4967 goto out;
4968 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4969 break;
4970 }
4971 case KVM_GET_NESTED_STATE: {
4972 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4973 u32 user_data_size;
4974
4975 r = -EINVAL;
4976 if (!kvm_x86_ops.nested_ops->get_state)
4977 break;
4978
4979 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4980 r = -EFAULT;
4981 if (get_user(user_data_size, &user_kvm_nested_state->size))
4982 break;
4983
4984 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4985 user_data_size);
4986 if (r < 0)
4987 break;
4988
4989 if (r > user_data_size) {
4990 if (put_user(r, &user_kvm_nested_state->size))
4991 r = -EFAULT;
4992 else
4993 r = -E2BIG;
4994 break;
4995 }
4996
4997 r = 0;
4998 break;
4999 }
5000 case KVM_SET_NESTED_STATE: {
5001 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5002 struct kvm_nested_state kvm_state;
5003 int idx;
5004
5005 r = -EINVAL;
5006 if (!kvm_x86_ops.nested_ops->set_state)
5007 break;
5008
5009 r = -EFAULT;
5010 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5011 break;
5012
5013 r = -EINVAL;
5014 if (kvm_state.size < sizeof(kvm_state))
5015 break;
5016
5017 if (kvm_state.flags &
5018 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5019 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5020 | KVM_STATE_NESTED_GIF_SET))
5021 break;
5022
5023 /* nested_run_pending implies guest_mode. */
5024 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5025 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5026 break;
5027
5028 idx = srcu_read_lock(&vcpu->kvm->srcu);
5029 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5030 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5031 break;
5032 }
5033 case KVM_GET_SUPPORTED_HV_CPUID:
5034 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5035 break;
5036 default:
5037 r = -EINVAL;
5038 }
5039 out:
5040 kfree(u.buffer);
5041 out_nofree:
5042 vcpu_put(vcpu);
5043 return r;
5044 }
5045
5046 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5047 {
5048 return VM_FAULT_SIGBUS;
5049 }
5050
5051 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5052 {
5053 int ret;
5054
5055 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5056 return -EINVAL;
5057 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
5058 return ret;
5059 }
5060
5061 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5062 u64 ident_addr)
5063 {
5064 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
5065 }
5066
5067 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5068 unsigned long kvm_nr_mmu_pages)
5069 {
5070 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5071 return -EINVAL;
5072
5073 mutex_lock(&kvm->slots_lock);
5074
5075 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5076 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5077
5078 mutex_unlock(&kvm->slots_lock);
5079 return 0;
5080 }
5081
5082 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5083 {
5084 return kvm->arch.n_max_mmu_pages;
5085 }
5086
5087 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5088 {
5089 struct kvm_pic *pic = kvm->arch.vpic;
5090 int r;
5091
5092 r = 0;
5093 switch (chip->chip_id) {
5094 case KVM_IRQCHIP_PIC_MASTER:
5095 memcpy(&chip->chip.pic, &pic->pics[0],
5096 sizeof(struct kvm_pic_state));
5097 break;
5098 case KVM_IRQCHIP_PIC_SLAVE:
5099 memcpy(&chip->chip.pic, &pic->pics[1],
5100 sizeof(struct kvm_pic_state));
5101 break;
5102 case KVM_IRQCHIP_IOAPIC:
5103 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5104 break;
5105 default:
5106 r = -EINVAL;
5107 break;
5108 }
5109 return r;
5110 }
5111
5112 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5113 {
5114 struct kvm_pic *pic = kvm->arch.vpic;
5115 int r;
5116
5117 r = 0;
5118 switch (chip->chip_id) {
5119 case KVM_IRQCHIP_PIC_MASTER:
5120 spin_lock(&pic->lock);
5121 memcpy(&pic->pics[0], &chip->chip.pic,
5122 sizeof(struct kvm_pic_state));
5123 spin_unlock(&pic->lock);
5124 break;
5125 case KVM_IRQCHIP_PIC_SLAVE:
5126 spin_lock(&pic->lock);
5127 memcpy(&pic->pics[1], &chip->chip.pic,
5128 sizeof(struct kvm_pic_state));
5129 spin_unlock(&pic->lock);
5130 break;
5131 case KVM_IRQCHIP_IOAPIC:
5132 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5133 break;
5134 default:
5135 r = -EINVAL;
5136 break;
5137 }
5138 kvm_pic_update_irq(pic);
5139 return r;
5140 }
5141
5142 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5143 {
5144 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5145
5146 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5147
5148 mutex_lock(&kps->lock);
5149 memcpy(ps, &kps->channels, sizeof(*ps));
5150 mutex_unlock(&kps->lock);
5151 return 0;
5152 }
5153
5154 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5155 {
5156 int i;
5157 struct kvm_pit *pit = kvm->arch.vpit;
5158
5159 mutex_lock(&pit->pit_state.lock);
5160 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5161 for (i = 0; i < 3; i++)
5162 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5163 mutex_unlock(&pit->pit_state.lock);
5164 return 0;
5165 }
5166
5167 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5168 {
5169 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5170 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5171 sizeof(ps->channels));
5172 ps->flags = kvm->arch.vpit->pit_state.flags;
5173 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5174 memset(&ps->reserved, 0, sizeof(ps->reserved));
5175 return 0;
5176 }
5177
5178 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5179 {
5180 int start = 0;
5181 int i;
5182 u32 prev_legacy, cur_legacy;
5183 struct kvm_pit *pit = kvm->arch.vpit;
5184
5185 mutex_lock(&pit->pit_state.lock);
5186 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5187 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5188 if (!prev_legacy && cur_legacy)
5189 start = 1;
5190 memcpy(&pit->pit_state.channels, &ps->channels,
5191 sizeof(pit->pit_state.channels));
5192 pit->pit_state.flags = ps->flags;
5193 for (i = 0; i < 3; i++)
5194 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5195 start && i == 0);
5196 mutex_unlock(&pit->pit_state.lock);
5197 return 0;
5198 }
5199
5200 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5201 struct kvm_reinject_control *control)
5202 {
5203 struct kvm_pit *pit = kvm->arch.vpit;
5204
5205 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5206 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5207 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5208 */
5209 mutex_lock(&pit->pit_state.lock);
5210 kvm_pit_set_reinject(pit, control->pit_reinject);
5211 mutex_unlock(&pit->pit_state.lock);
5212
5213 return 0;
5214 }
5215
5216 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5217 {
5218 /*
5219 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
5220 */
5221 static_call_cond(kvm_x86_flush_log_dirty)(kvm);
5222 }
5223
5224 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5225 bool line_status)
5226 {
5227 if (!irqchip_in_kernel(kvm))
5228 return -ENXIO;
5229
5230 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5231 irq_event->irq, irq_event->level,
5232 line_status);
5233 return 0;
5234 }
5235
5236 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5237 struct kvm_enable_cap *cap)
5238 {
5239 int r;
5240
5241 if (cap->flags)
5242 return -EINVAL;
5243
5244 switch (cap->cap) {
5245 case KVM_CAP_DISABLE_QUIRKS:
5246 kvm->arch.disabled_quirks = cap->args[0];
5247 r = 0;
5248 break;
5249 case KVM_CAP_SPLIT_IRQCHIP: {
5250 mutex_lock(&kvm->lock);
5251 r = -EINVAL;
5252 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5253 goto split_irqchip_unlock;
5254 r = -EEXIST;
5255 if (irqchip_in_kernel(kvm))
5256 goto split_irqchip_unlock;
5257 if (kvm->created_vcpus)
5258 goto split_irqchip_unlock;
5259 r = kvm_setup_empty_irq_routing(kvm);
5260 if (r)
5261 goto split_irqchip_unlock;
5262 /* Pairs with irqchip_in_kernel. */
5263 smp_wmb();
5264 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5265 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5266 r = 0;
5267 split_irqchip_unlock:
5268 mutex_unlock(&kvm->lock);
5269 break;
5270 }
5271 case KVM_CAP_X2APIC_API:
5272 r = -EINVAL;
5273 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5274 break;
5275
5276 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5277 kvm->arch.x2apic_format = true;
5278 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5279 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5280
5281 r = 0;
5282 break;
5283 case KVM_CAP_X86_DISABLE_EXITS:
5284 r = -EINVAL;
5285 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5286 break;
5287
5288 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5289 kvm_can_mwait_in_guest())
5290 kvm->arch.mwait_in_guest = true;
5291 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5292 kvm->arch.hlt_in_guest = true;
5293 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5294 kvm->arch.pause_in_guest = true;
5295 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5296 kvm->arch.cstate_in_guest = true;
5297 r = 0;
5298 break;
5299 case KVM_CAP_MSR_PLATFORM_INFO:
5300 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5301 r = 0;
5302 break;
5303 case KVM_CAP_EXCEPTION_PAYLOAD:
5304 kvm->arch.exception_payload_enabled = cap->args[0];
5305 r = 0;
5306 break;
5307 case KVM_CAP_X86_USER_SPACE_MSR:
5308 kvm->arch.user_space_msr_mask = cap->args[0];
5309 r = 0;
5310 break;
5311 case KVM_CAP_X86_BUS_LOCK_EXIT:
5312 r = -EINVAL;
5313 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
5314 break;
5315
5316 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
5317 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
5318 break;
5319
5320 if (kvm_has_bus_lock_exit &&
5321 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
5322 kvm->arch.bus_lock_detection_enabled = true;
5323 r = 0;
5324 break;
5325 default:
5326 r = -EINVAL;
5327 break;
5328 }
5329 return r;
5330 }
5331
5332 static void kvm_clear_msr_filter(struct kvm *kvm)
5333 {
5334 u32 i;
5335 u32 count = kvm->arch.msr_filter.count;
5336 struct msr_bitmap_range ranges[16];
5337
5338 mutex_lock(&kvm->lock);
5339 kvm->arch.msr_filter.count = 0;
5340 memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0]));
5341 mutex_unlock(&kvm->lock);
5342 synchronize_srcu(&kvm->srcu);
5343
5344 for (i = 0; i < count; i++)
5345 kfree(ranges[i].bitmap);
5346 }
5347
5348 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range)
5349 {
5350 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
5351 struct msr_bitmap_range range;
5352 unsigned long *bitmap = NULL;
5353 size_t bitmap_size;
5354 int r;
5355
5356 if (!user_range->nmsrs)
5357 return 0;
5358
5359 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5360 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5361 return -EINVAL;
5362
5363 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5364 if (IS_ERR(bitmap))
5365 return PTR_ERR(bitmap);
5366
5367 range = (struct msr_bitmap_range) {
5368 .flags = user_range->flags,
5369 .base = user_range->base,
5370 .nmsrs = user_range->nmsrs,
5371 .bitmap = bitmap,
5372 };
5373
5374 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5375 r = -EINVAL;
5376 goto err;
5377 }
5378
5379 if (!range.flags) {
5380 r = -EINVAL;
5381 goto err;
5382 }
5383
5384 /* Everything ok, add this range identifier to our global pool */
5385 ranges[kvm->arch.msr_filter.count] = range;
5386 /* Make sure we filled the array before we tell anyone to walk it */
5387 smp_wmb();
5388 kvm->arch.msr_filter.count++;
5389
5390 return 0;
5391 err:
5392 kfree(bitmap);
5393 return r;
5394 }
5395
5396 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5397 {
5398 struct kvm_msr_filter __user *user_msr_filter = argp;
5399 struct kvm_msr_filter filter;
5400 bool default_allow;
5401 int r = 0;
5402 bool empty = true;
5403 u32 i;
5404
5405 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5406 return -EFAULT;
5407
5408 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5409 empty &= !filter.ranges[i].nmsrs;
5410
5411 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5412 if (empty && !default_allow)
5413 return -EINVAL;
5414
5415 kvm_clear_msr_filter(kvm);
5416
5417 kvm->arch.msr_filter.default_allow = default_allow;
5418
5419 /*
5420 * Protect from concurrent calls to this function that could trigger
5421 * a TOCTOU violation on kvm->arch.msr_filter.count.
5422 */
5423 mutex_lock(&kvm->lock);
5424 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5425 r = kvm_add_msr_filter(kvm, &filter.ranges[i]);
5426 if (r)
5427 break;
5428 }
5429
5430 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5431 mutex_unlock(&kvm->lock);
5432
5433 return r;
5434 }
5435
5436 long kvm_arch_vm_ioctl(struct file *filp,
5437 unsigned int ioctl, unsigned long arg)
5438 {
5439 struct kvm *kvm = filp->private_data;
5440 void __user *argp = (void __user *)arg;
5441 int r = -ENOTTY;
5442 /*
5443 * This union makes it completely explicit to gcc-3.x
5444 * that these two variables' stack usage should be
5445 * combined, not added together.
5446 */
5447 union {
5448 struct kvm_pit_state ps;
5449 struct kvm_pit_state2 ps2;
5450 struct kvm_pit_config pit_config;
5451 } u;
5452
5453 switch (ioctl) {
5454 case KVM_SET_TSS_ADDR:
5455 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5456 break;
5457 case KVM_SET_IDENTITY_MAP_ADDR: {
5458 u64 ident_addr;
5459
5460 mutex_lock(&kvm->lock);
5461 r = -EINVAL;
5462 if (kvm->created_vcpus)
5463 goto set_identity_unlock;
5464 r = -EFAULT;
5465 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5466 goto set_identity_unlock;
5467 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5468 set_identity_unlock:
5469 mutex_unlock(&kvm->lock);
5470 break;
5471 }
5472 case KVM_SET_NR_MMU_PAGES:
5473 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5474 break;
5475 case KVM_GET_NR_MMU_PAGES:
5476 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5477 break;
5478 case KVM_CREATE_IRQCHIP: {
5479 mutex_lock(&kvm->lock);
5480
5481 r = -EEXIST;
5482 if (irqchip_in_kernel(kvm))
5483 goto create_irqchip_unlock;
5484
5485 r = -EINVAL;
5486 if (kvm->created_vcpus)
5487 goto create_irqchip_unlock;
5488
5489 r = kvm_pic_init(kvm);
5490 if (r)
5491 goto create_irqchip_unlock;
5492
5493 r = kvm_ioapic_init(kvm);
5494 if (r) {
5495 kvm_pic_destroy(kvm);
5496 goto create_irqchip_unlock;
5497 }
5498
5499 r = kvm_setup_default_irq_routing(kvm);
5500 if (r) {
5501 kvm_ioapic_destroy(kvm);
5502 kvm_pic_destroy(kvm);
5503 goto create_irqchip_unlock;
5504 }
5505 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5506 smp_wmb();
5507 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5508 create_irqchip_unlock:
5509 mutex_unlock(&kvm->lock);
5510 break;
5511 }
5512 case KVM_CREATE_PIT:
5513 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5514 goto create_pit;
5515 case KVM_CREATE_PIT2:
5516 r = -EFAULT;
5517 if (copy_from_user(&u.pit_config, argp,
5518 sizeof(struct kvm_pit_config)))
5519 goto out;
5520 create_pit:
5521 mutex_lock(&kvm->lock);
5522 r = -EEXIST;
5523 if (kvm->arch.vpit)
5524 goto create_pit_unlock;
5525 r = -ENOMEM;
5526 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5527 if (kvm->arch.vpit)
5528 r = 0;
5529 create_pit_unlock:
5530 mutex_unlock(&kvm->lock);
5531 break;
5532 case KVM_GET_IRQCHIP: {
5533 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5534 struct kvm_irqchip *chip;
5535
5536 chip = memdup_user(argp, sizeof(*chip));
5537 if (IS_ERR(chip)) {
5538 r = PTR_ERR(chip);
5539 goto out;
5540 }
5541
5542 r = -ENXIO;
5543 if (!irqchip_kernel(kvm))
5544 goto get_irqchip_out;
5545 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5546 if (r)
5547 goto get_irqchip_out;
5548 r = -EFAULT;
5549 if (copy_to_user(argp, chip, sizeof(*chip)))
5550 goto get_irqchip_out;
5551 r = 0;
5552 get_irqchip_out:
5553 kfree(chip);
5554 break;
5555 }
5556 case KVM_SET_IRQCHIP: {
5557 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5558 struct kvm_irqchip *chip;
5559
5560 chip = memdup_user(argp, sizeof(*chip));
5561 if (IS_ERR(chip)) {
5562 r = PTR_ERR(chip);
5563 goto out;
5564 }
5565
5566 r = -ENXIO;
5567 if (!irqchip_kernel(kvm))
5568 goto set_irqchip_out;
5569 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5570 set_irqchip_out:
5571 kfree(chip);
5572 break;
5573 }
5574 case KVM_GET_PIT: {
5575 r = -EFAULT;
5576 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5577 goto out;
5578 r = -ENXIO;
5579 if (!kvm->arch.vpit)
5580 goto out;
5581 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5582 if (r)
5583 goto out;
5584 r = -EFAULT;
5585 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5586 goto out;
5587 r = 0;
5588 break;
5589 }
5590 case KVM_SET_PIT: {
5591 r = -EFAULT;
5592 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5593 goto out;
5594 mutex_lock(&kvm->lock);
5595 r = -ENXIO;
5596 if (!kvm->arch.vpit)
5597 goto set_pit_out;
5598 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5599 set_pit_out:
5600 mutex_unlock(&kvm->lock);
5601 break;
5602 }
5603 case KVM_GET_PIT2: {
5604 r = -ENXIO;
5605 if (!kvm->arch.vpit)
5606 goto out;
5607 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5608 if (r)
5609 goto out;
5610 r = -EFAULT;
5611 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5612 goto out;
5613 r = 0;
5614 break;
5615 }
5616 case KVM_SET_PIT2: {
5617 r = -EFAULT;
5618 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5619 goto out;
5620 mutex_lock(&kvm->lock);
5621 r = -ENXIO;
5622 if (!kvm->arch.vpit)
5623 goto set_pit2_out;
5624 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5625 set_pit2_out:
5626 mutex_unlock(&kvm->lock);
5627 break;
5628 }
5629 case KVM_REINJECT_CONTROL: {
5630 struct kvm_reinject_control control;
5631 r = -EFAULT;
5632 if (copy_from_user(&control, argp, sizeof(control)))
5633 goto out;
5634 r = -ENXIO;
5635 if (!kvm->arch.vpit)
5636 goto out;
5637 r = kvm_vm_ioctl_reinject(kvm, &control);
5638 break;
5639 }
5640 case KVM_SET_BOOT_CPU_ID:
5641 r = 0;
5642 mutex_lock(&kvm->lock);
5643 if (kvm->created_vcpus)
5644 r = -EBUSY;
5645 else
5646 kvm->arch.bsp_vcpu_id = arg;
5647 mutex_unlock(&kvm->lock);
5648 break;
5649 case KVM_XEN_HVM_CONFIG: {
5650 struct kvm_xen_hvm_config xhc;
5651 r = -EFAULT;
5652 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5653 goto out;
5654 r = -EINVAL;
5655 if (xhc.flags)
5656 goto out;
5657 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5658 r = 0;
5659 break;
5660 }
5661 case KVM_SET_CLOCK: {
5662 struct kvm_clock_data user_ns;
5663 u64 now_ns;
5664
5665 r = -EFAULT;
5666 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5667 goto out;
5668
5669 r = -EINVAL;
5670 if (user_ns.flags)
5671 goto out;
5672
5673 r = 0;
5674 /*
5675 * TODO: userspace has to take care of races with VCPU_RUN, so
5676 * kvm_gen_update_masterclock() can be cut down to locked
5677 * pvclock_update_vm_gtod_copy().
5678 */
5679 kvm_gen_update_masterclock(kvm);
5680 now_ns = get_kvmclock_ns(kvm);
5681 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5682 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5683 break;
5684 }
5685 case KVM_GET_CLOCK: {
5686 struct kvm_clock_data user_ns;
5687 u64 now_ns;
5688
5689 now_ns = get_kvmclock_ns(kvm);
5690 user_ns.clock = now_ns;
5691 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5692 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5693
5694 r = -EFAULT;
5695 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5696 goto out;
5697 r = 0;
5698 break;
5699 }
5700 case KVM_MEMORY_ENCRYPT_OP: {
5701 r = -ENOTTY;
5702 if (kvm_x86_ops.mem_enc_op)
5703 r = static_call(kvm_x86_mem_enc_op)(kvm, argp);
5704 break;
5705 }
5706 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5707 struct kvm_enc_region region;
5708
5709 r = -EFAULT;
5710 if (copy_from_user(&region, argp, sizeof(region)))
5711 goto out;
5712
5713 r = -ENOTTY;
5714 if (kvm_x86_ops.mem_enc_reg_region)
5715 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, &region);
5716 break;
5717 }
5718 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5719 struct kvm_enc_region region;
5720
5721 r = -EFAULT;
5722 if (copy_from_user(&region, argp, sizeof(region)))
5723 goto out;
5724
5725 r = -ENOTTY;
5726 if (kvm_x86_ops.mem_enc_unreg_region)
5727 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, &region);
5728 break;
5729 }
5730 case KVM_HYPERV_EVENTFD: {
5731 struct kvm_hyperv_eventfd hvevfd;
5732
5733 r = -EFAULT;
5734 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5735 goto out;
5736 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5737 break;
5738 }
5739 case KVM_SET_PMU_EVENT_FILTER:
5740 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5741 break;
5742 case KVM_X86_SET_MSR_FILTER:
5743 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5744 break;
5745 default:
5746 r = -ENOTTY;
5747 }
5748 out:
5749 return r;
5750 }
5751
5752 static void kvm_init_msr_list(void)
5753 {
5754 struct x86_pmu_capability x86_pmu;
5755 u32 dummy[2];
5756 unsigned i;
5757
5758 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5759 "Please update the fixed PMCs in msrs_to_saved_all[]");
5760
5761 perf_get_x86_pmu_capability(&x86_pmu);
5762
5763 num_msrs_to_save = 0;
5764 num_emulated_msrs = 0;
5765 num_msr_based_features = 0;
5766
5767 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5768 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5769 continue;
5770
5771 /*
5772 * Even MSRs that are valid in the host may not be exposed
5773 * to the guests in some cases.
5774 */
5775 switch (msrs_to_save_all[i]) {
5776 case MSR_IA32_BNDCFGS:
5777 if (!kvm_mpx_supported())
5778 continue;
5779 break;
5780 case MSR_TSC_AUX:
5781 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5782 continue;
5783 break;
5784 case MSR_IA32_UMWAIT_CONTROL:
5785 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5786 continue;
5787 break;
5788 case MSR_IA32_RTIT_CTL:
5789 case MSR_IA32_RTIT_STATUS:
5790 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5791 continue;
5792 break;
5793 case MSR_IA32_RTIT_CR3_MATCH:
5794 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5795 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5796 continue;
5797 break;
5798 case MSR_IA32_RTIT_OUTPUT_BASE:
5799 case MSR_IA32_RTIT_OUTPUT_MASK:
5800 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5801 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5802 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5803 continue;
5804 break;
5805 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5806 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5807 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5808 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5809 continue;
5810 break;
5811 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5812 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5813 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5814 continue;
5815 break;
5816 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5817 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5818 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5819 continue;
5820 break;
5821 default:
5822 break;
5823 }
5824
5825 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5826 }
5827
5828 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5829 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
5830 continue;
5831
5832 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5833 }
5834
5835 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5836 struct kvm_msr_entry msr;
5837
5838 msr.index = msr_based_features_all[i];
5839 if (kvm_get_msr_feature(&msr))
5840 continue;
5841
5842 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5843 }
5844 }
5845
5846 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5847 const void *v)
5848 {
5849 int handled = 0;
5850 int n;
5851
5852 do {
5853 n = min(len, 8);
5854 if (!(lapic_in_kernel(vcpu) &&
5855 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5856 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5857 break;
5858 handled += n;
5859 addr += n;
5860 len -= n;
5861 v += n;
5862 } while (len);
5863
5864 return handled;
5865 }
5866
5867 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5868 {
5869 int handled = 0;
5870 int n;
5871
5872 do {
5873 n = min(len, 8);
5874 if (!(lapic_in_kernel(vcpu) &&
5875 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5876 addr, n, v))
5877 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5878 break;
5879 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5880 handled += n;
5881 addr += n;
5882 len -= n;
5883 v += n;
5884 } while (len);
5885
5886 return handled;
5887 }
5888
5889 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5890 struct kvm_segment *var, int seg)
5891 {
5892 static_call(kvm_x86_set_segment)(vcpu, var, seg);
5893 }
5894
5895 void kvm_get_segment(struct kvm_vcpu *vcpu,
5896 struct kvm_segment *var, int seg)
5897 {
5898 static_call(kvm_x86_get_segment)(vcpu, var, seg);
5899 }
5900
5901 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5902 struct x86_exception *exception)
5903 {
5904 gpa_t t_gpa;
5905
5906 BUG_ON(!mmu_is_nested(vcpu));
5907
5908 /* NPT walks are always user-walks */
5909 access |= PFERR_USER_MASK;
5910 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5911
5912 return t_gpa;
5913 }
5914
5915 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5916 struct x86_exception *exception)
5917 {
5918 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
5919 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5920 }
5921
5922 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5923 struct x86_exception *exception)
5924 {
5925 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
5926 access |= PFERR_FETCH_MASK;
5927 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5928 }
5929
5930 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5931 struct x86_exception *exception)
5932 {
5933 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
5934 access |= PFERR_WRITE_MASK;
5935 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5936 }
5937
5938 /* uses this to access any guest's mapped memory without checking CPL */
5939 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5940 struct x86_exception *exception)
5941 {
5942 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5943 }
5944
5945 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5946 struct kvm_vcpu *vcpu, u32 access,
5947 struct x86_exception *exception)
5948 {
5949 void *data = val;
5950 int r = X86EMUL_CONTINUE;
5951
5952 while (bytes) {
5953 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5954 exception);
5955 unsigned offset = addr & (PAGE_SIZE-1);
5956 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5957 int ret;
5958
5959 if (gpa == UNMAPPED_GVA)
5960 return X86EMUL_PROPAGATE_FAULT;
5961 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5962 offset, toread);
5963 if (ret < 0) {
5964 r = X86EMUL_IO_NEEDED;
5965 goto out;
5966 }
5967
5968 bytes -= toread;
5969 data += toread;
5970 addr += toread;
5971 }
5972 out:
5973 return r;
5974 }
5975
5976 /* used for instruction fetching */
5977 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5978 gva_t addr, void *val, unsigned int bytes,
5979 struct x86_exception *exception)
5980 {
5981 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5982 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
5983 unsigned offset;
5984 int ret;
5985
5986 /* Inline kvm_read_guest_virt_helper for speed. */
5987 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5988 exception);
5989 if (unlikely(gpa == UNMAPPED_GVA))
5990 return X86EMUL_PROPAGATE_FAULT;
5991
5992 offset = addr & (PAGE_SIZE-1);
5993 if (WARN_ON(offset + bytes > PAGE_SIZE))
5994 bytes = (unsigned)PAGE_SIZE - offset;
5995 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5996 offset, bytes);
5997 if (unlikely(ret < 0))
5998 return X86EMUL_IO_NEEDED;
5999
6000 return X86EMUL_CONTINUE;
6001 }
6002
6003 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
6004 gva_t addr, void *val, unsigned int bytes,
6005 struct x86_exception *exception)
6006 {
6007 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6008
6009 /*
6010 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
6011 * is returned, but our callers are not ready for that and they blindly
6012 * call kvm_inject_page_fault. Ensure that they at least do not leak
6013 * uninitialized kernel stack memory into cr2 and error code.
6014 */
6015 memset(exception, 0, sizeof(*exception));
6016 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
6017 exception);
6018 }
6019 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
6020
6021 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
6022 gva_t addr, void *val, unsigned int bytes,
6023 struct x86_exception *exception, bool system)
6024 {
6025 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6026 u32 access = 0;
6027
6028 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3)
6029 access |= PFERR_USER_MASK;
6030
6031 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
6032 }
6033
6034 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
6035 unsigned long addr, void *val, unsigned int bytes)
6036 {
6037 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6038 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
6039
6040 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
6041 }
6042
6043 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6044 struct kvm_vcpu *vcpu, u32 access,
6045 struct x86_exception *exception)
6046 {
6047 void *data = val;
6048 int r = X86EMUL_CONTINUE;
6049
6050 while (bytes) {
6051 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
6052 access,
6053 exception);
6054 unsigned offset = addr & (PAGE_SIZE-1);
6055 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6056 int ret;
6057
6058 if (gpa == UNMAPPED_GVA)
6059 return X86EMUL_PROPAGATE_FAULT;
6060 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6061 if (ret < 0) {
6062 r = X86EMUL_IO_NEEDED;
6063 goto out;
6064 }
6065
6066 bytes -= towrite;
6067 data += towrite;
6068 addr += towrite;
6069 }
6070 out:
6071 return r;
6072 }
6073
6074 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6075 unsigned int bytes, struct x86_exception *exception,
6076 bool system)
6077 {
6078 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6079 u32 access = PFERR_WRITE_MASK;
6080
6081 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3)
6082 access |= PFERR_USER_MASK;
6083
6084 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6085 access, exception);
6086 }
6087
6088 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6089 unsigned int bytes, struct x86_exception *exception)
6090 {
6091 /* kvm_write_guest_virt_system can pull in tons of pages. */
6092 vcpu->arch.l1tf_flush_l1d = true;
6093
6094 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6095 PFERR_WRITE_MASK, exception);
6096 }
6097 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6098
6099 int handle_ud(struct kvm_vcpu *vcpu)
6100 {
6101 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6102 int emul_type = EMULTYPE_TRAP_UD;
6103 char sig[5]; /* ud2; .ascii "kvm" */
6104 struct x86_exception e;
6105
6106 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0)))
6107 return 1;
6108
6109 if (force_emulation_prefix &&
6110 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6111 sig, sizeof(sig), &e) == 0 &&
6112 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6113 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6114 emul_type = EMULTYPE_TRAP_UD_FORCED;
6115 }
6116
6117 return kvm_emulate_instruction(vcpu, emul_type);
6118 }
6119 EXPORT_SYMBOL_GPL(handle_ud);
6120
6121 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6122 gpa_t gpa, bool write)
6123 {
6124 /* For APIC access vmexit */
6125 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6126 return 1;
6127
6128 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6129 trace_vcpu_match_mmio(gva, gpa, write, true);
6130 return 1;
6131 }
6132
6133 return 0;
6134 }
6135
6136 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6137 gpa_t *gpa, struct x86_exception *exception,
6138 bool write)
6139 {
6140 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
6141 | (write ? PFERR_WRITE_MASK : 0);
6142
6143 /*
6144 * currently PKRU is only applied to ept enabled guest so
6145 * there is no pkey in EPT page table for L1 guest or EPT
6146 * shadow page table for L2 guest.
6147 */
6148 if (vcpu_match_mmio_gva(vcpu, gva)
6149 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6150 vcpu->arch.mmio_access, 0, access)) {
6151 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6152 (gva & (PAGE_SIZE - 1));
6153 trace_vcpu_match_mmio(gva, *gpa, write, false);
6154 return 1;
6155 }
6156
6157 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6158
6159 if (*gpa == UNMAPPED_GVA)
6160 return -1;
6161
6162 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6163 }
6164
6165 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6166 const void *val, int bytes)
6167 {
6168 int ret;
6169
6170 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6171 if (ret < 0)
6172 return 0;
6173 kvm_page_track_write(vcpu, gpa, val, bytes);
6174 return 1;
6175 }
6176
6177 struct read_write_emulator_ops {
6178 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6179 int bytes);
6180 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6181 void *val, int bytes);
6182 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6183 int bytes, void *val);
6184 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6185 void *val, int bytes);
6186 bool write;
6187 };
6188
6189 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6190 {
6191 if (vcpu->mmio_read_completed) {
6192 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6193 vcpu->mmio_fragments[0].gpa, val);
6194 vcpu->mmio_read_completed = 0;
6195 return 1;
6196 }
6197
6198 return 0;
6199 }
6200
6201 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6202 void *val, int bytes)
6203 {
6204 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6205 }
6206
6207 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6208 void *val, int bytes)
6209 {
6210 return emulator_write_phys(vcpu, gpa, val, bytes);
6211 }
6212
6213 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6214 {
6215 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6216 return vcpu_mmio_write(vcpu, gpa, bytes, val);
6217 }
6218
6219 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6220 void *val, int bytes)
6221 {
6222 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6223 return X86EMUL_IO_NEEDED;
6224 }
6225
6226 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6227 void *val, int bytes)
6228 {
6229 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6230
6231 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6232 return X86EMUL_CONTINUE;
6233 }
6234
6235 static const struct read_write_emulator_ops read_emultor = {
6236 .read_write_prepare = read_prepare,
6237 .read_write_emulate = read_emulate,
6238 .read_write_mmio = vcpu_mmio_read,
6239 .read_write_exit_mmio = read_exit_mmio,
6240 };
6241
6242 static const struct read_write_emulator_ops write_emultor = {
6243 .read_write_emulate = write_emulate,
6244 .read_write_mmio = write_mmio,
6245 .read_write_exit_mmio = write_exit_mmio,
6246 .write = true,
6247 };
6248
6249 static int emulator_read_write_onepage(unsigned long addr, void *val,
6250 unsigned int bytes,
6251 struct x86_exception *exception,
6252 struct kvm_vcpu *vcpu,
6253 const struct read_write_emulator_ops *ops)
6254 {
6255 gpa_t gpa;
6256 int handled, ret;
6257 bool write = ops->write;
6258 struct kvm_mmio_fragment *frag;
6259 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6260
6261 /*
6262 * If the exit was due to a NPF we may already have a GPA.
6263 * If the GPA is present, use it to avoid the GVA to GPA table walk.
6264 * Note, this cannot be used on string operations since string
6265 * operation using rep will only have the initial GPA from the NPF
6266 * occurred.
6267 */
6268 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6269 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6270 gpa = ctxt->gpa_val;
6271 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6272 } else {
6273 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6274 if (ret < 0)
6275 return X86EMUL_PROPAGATE_FAULT;
6276 }
6277
6278 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6279 return X86EMUL_CONTINUE;
6280
6281 /*
6282 * Is this MMIO handled locally?
6283 */
6284 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6285 if (handled == bytes)
6286 return X86EMUL_CONTINUE;
6287
6288 gpa += handled;
6289 bytes -= handled;
6290 val += handled;
6291
6292 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6293 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6294 frag->gpa = gpa;
6295 frag->data = val;
6296 frag->len = bytes;
6297 return X86EMUL_CONTINUE;
6298 }
6299
6300 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6301 unsigned long addr,
6302 void *val, unsigned int bytes,
6303 struct x86_exception *exception,
6304 const struct read_write_emulator_ops *ops)
6305 {
6306 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6307 gpa_t gpa;
6308 int rc;
6309
6310 if (ops->read_write_prepare &&
6311 ops->read_write_prepare(vcpu, val, bytes))
6312 return X86EMUL_CONTINUE;
6313
6314 vcpu->mmio_nr_fragments = 0;
6315
6316 /* Crossing a page boundary? */
6317 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6318 int now;
6319
6320 now = -addr & ~PAGE_MASK;
6321 rc = emulator_read_write_onepage(addr, val, now, exception,
6322 vcpu, ops);
6323
6324 if (rc != X86EMUL_CONTINUE)
6325 return rc;
6326 addr += now;
6327 if (ctxt->mode != X86EMUL_MODE_PROT64)
6328 addr = (u32)addr;
6329 val += now;
6330 bytes -= now;
6331 }
6332
6333 rc = emulator_read_write_onepage(addr, val, bytes, exception,
6334 vcpu, ops);
6335 if (rc != X86EMUL_CONTINUE)
6336 return rc;
6337
6338 if (!vcpu->mmio_nr_fragments)
6339 return rc;
6340
6341 gpa = vcpu->mmio_fragments[0].gpa;
6342
6343 vcpu->mmio_needed = 1;
6344 vcpu->mmio_cur_fragment = 0;
6345
6346 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6347 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6348 vcpu->run->exit_reason = KVM_EXIT_MMIO;
6349 vcpu->run->mmio.phys_addr = gpa;
6350
6351 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6352 }
6353
6354 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6355 unsigned long addr,
6356 void *val,
6357 unsigned int bytes,
6358 struct x86_exception *exception)
6359 {
6360 return emulator_read_write(ctxt, addr, val, bytes,
6361 exception, &read_emultor);
6362 }
6363
6364 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6365 unsigned long addr,
6366 const void *val,
6367 unsigned int bytes,
6368 struct x86_exception *exception)
6369 {
6370 return emulator_read_write(ctxt, addr, (void *)val, bytes,
6371 exception, &write_emultor);
6372 }
6373
6374 #define CMPXCHG_TYPE(t, ptr, old, new) \
6375 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6376
6377 #ifdef CONFIG_X86_64
6378 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6379 #else
6380 # define CMPXCHG64(ptr, old, new) \
6381 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6382 #endif
6383
6384 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6385 unsigned long addr,
6386 const void *old,
6387 const void *new,
6388 unsigned int bytes,
6389 struct x86_exception *exception)
6390 {
6391 struct kvm_host_map map;
6392 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6393 u64 page_line_mask;
6394 gpa_t gpa;
6395 char *kaddr;
6396 bool exchanged;
6397
6398 /* guests cmpxchg8b have to be emulated atomically */
6399 if (bytes > 8 || (bytes & (bytes - 1)))
6400 goto emul_write;
6401
6402 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6403
6404 if (gpa == UNMAPPED_GVA ||
6405 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6406 goto emul_write;
6407
6408 /*
6409 * Emulate the atomic as a straight write to avoid #AC if SLD is
6410 * enabled in the host and the access splits a cache line.
6411 */
6412 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6413 page_line_mask = ~(cache_line_size() - 1);
6414 else
6415 page_line_mask = PAGE_MASK;
6416
6417 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6418 goto emul_write;
6419
6420 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6421 goto emul_write;
6422
6423 kaddr = map.hva + offset_in_page(gpa);
6424
6425 switch (bytes) {
6426 case 1:
6427 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6428 break;
6429 case 2:
6430 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6431 break;
6432 case 4:
6433 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6434 break;
6435 case 8:
6436 exchanged = CMPXCHG64(kaddr, old, new);
6437 break;
6438 default:
6439 BUG();
6440 }
6441
6442 kvm_vcpu_unmap(vcpu, &map, true);
6443
6444 if (!exchanged)
6445 return X86EMUL_CMPXCHG_FAILED;
6446
6447 kvm_page_track_write(vcpu, gpa, new, bytes);
6448
6449 return X86EMUL_CONTINUE;
6450
6451 emul_write:
6452 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6453
6454 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6455 }
6456
6457 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6458 {
6459 int r = 0, i;
6460
6461 for (i = 0; i < vcpu->arch.pio.count; i++) {
6462 if (vcpu->arch.pio.in)
6463 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6464 vcpu->arch.pio.size, pd);
6465 else
6466 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6467 vcpu->arch.pio.port, vcpu->arch.pio.size,
6468 pd);
6469 if (r)
6470 break;
6471 pd += vcpu->arch.pio.size;
6472 }
6473 return r;
6474 }
6475
6476 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6477 unsigned short port, void *val,
6478 unsigned int count, bool in)
6479 {
6480 vcpu->arch.pio.port = port;
6481 vcpu->arch.pio.in = in;
6482 vcpu->arch.pio.count = count;
6483 vcpu->arch.pio.size = size;
6484
6485 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6486 vcpu->arch.pio.count = 0;
6487 return 1;
6488 }
6489
6490 vcpu->run->exit_reason = KVM_EXIT_IO;
6491 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6492 vcpu->run->io.size = size;
6493 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6494 vcpu->run->io.count = count;
6495 vcpu->run->io.port = port;
6496
6497 return 0;
6498 }
6499
6500 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6501 unsigned short port, void *val, unsigned int count)
6502 {
6503 int ret;
6504
6505 if (vcpu->arch.pio.count)
6506 goto data_avail;
6507
6508 memset(vcpu->arch.pio_data, 0, size * count);
6509
6510 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6511 if (ret) {
6512 data_avail:
6513 memcpy(val, vcpu->arch.pio_data, size * count);
6514 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6515 vcpu->arch.pio.count = 0;
6516 return 1;
6517 }
6518
6519 return 0;
6520 }
6521
6522 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6523 int size, unsigned short port, void *val,
6524 unsigned int count)
6525 {
6526 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6527
6528 }
6529
6530 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6531 unsigned short port, const void *val,
6532 unsigned int count)
6533 {
6534 memcpy(vcpu->arch.pio_data, val, size * count);
6535 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6536 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6537 }
6538
6539 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6540 int size, unsigned short port,
6541 const void *val, unsigned int count)
6542 {
6543 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6544 }
6545
6546 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6547 {
6548 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
6549 }
6550
6551 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6552 {
6553 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6554 }
6555
6556 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6557 {
6558 if (!need_emulate_wbinvd(vcpu))
6559 return X86EMUL_CONTINUE;
6560
6561 if (static_call(kvm_x86_has_wbinvd_exit)()) {
6562 int cpu = get_cpu();
6563
6564 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6565 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6566 wbinvd_ipi, NULL, 1);
6567 put_cpu();
6568 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6569 } else
6570 wbinvd();
6571 return X86EMUL_CONTINUE;
6572 }
6573
6574 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6575 {
6576 kvm_emulate_wbinvd_noskip(vcpu);
6577 return kvm_skip_emulated_instruction(vcpu);
6578 }
6579 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6580
6581
6582
6583 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6584 {
6585 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6586 }
6587
6588 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6589 unsigned long *dest)
6590 {
6591 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6592 }
6593
6594 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6595 unsigned long value)
6596 {
6597
6598 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6599 }
6600
6601 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6602 {
6603 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6604 }
6605
6606 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6607 {
6608 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6609 unsigned long value;
6610
6611 switch (cr) {
6612 case 0:
6613 value = kvm_read_cr0(vcpu);
6614 break;
6615 case 2:
6616 value = vcpu->arch.cr2;
6617 break;
6618 case 3:
6619 value = kvm_read_cr3(vcpu);
6620 break;
6621 case 4:
6622 value = kvm_read_cr4(vcpu);
6623 break;
6624 case 8:
6625 value = kvm_get_cr8(vcpu);
6626 break;
6627 default:
6628 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6629 return 0;
6630 }
6631
6632 return value;
6633 }
6634
6635 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6636 {
6637 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6638 int res = 0;
6639
6640 switch (cr) {
6641 case 0:
6642 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6643 break;
6644 case 2:
6645 vcpu->arch.cr2 = val;
6646 break;
6647 case 3:
6648 res = kvm_set_cr3(vcpu, val);
6649 break;
6650 case 4:
6651 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6652 break;
6653 case 8:
6654 res = kvm_set_cr8(vcpu, val);
6655 break;
6656 default:
6657 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6658 res = -1;
6659 }
6660
6661 return res;
6662 }
6663
6664 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6665 {
6666 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
6667 }
6668
6669 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6670 {
6671 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
6672 }
6673
6674 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6675 {
6676 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
6677 }
6678
6679 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6680 {
6681 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
6682 }
6683
6684 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6685 {
6686 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
6687 }
6688
6689 static unsigned long emulator_get_cached_segment_base(
6690 struct x86_emulate_ctxt *ctxt, int seg)
6691 {
6692 return get_segment_base(emul_to_vcpu(ctxt), seg);
6693 }
6694
6695 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6696 struct desc_struct *desc, u32 *base3,
6697 int seg)
6698 {
6699 struct kvm_segment var;
6700
6701 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6702 *selector = var.selector;
6703
6704 if (var.unusable) {
6705 memset(desc, 0, sizeof(*desc));
6706 if (base3)
6707 *base3 = 0;
6708 return false;
6709 }
6710
6711 if (var.g)
6712 var.limit >>= 12;
6713 set_desc_limit(desc, var.limit);
6714 set_desc_base(desc, (unsigned long)var.base);
6715 #ifdef CONFIG_X86_64
6716 if (base3)
6717 *base3 = var.base >> 32;
6718 #endif
6719 desc->type = var.type;
6720 desc->s = var.s;
6721 desc->dpl = var.dpl;
6722 desc->p = var.present;
6723 desc->avl = var.avl;
6724 desc->l = var.l;
6725 desc->d = var.db;
6726 desc->g = var.g;
6727
6728 return true;
6729 }
6730
6731 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6732 struct desc_struct *desc, u32 base3,
6733 int seg)
6734 {
6735 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6736 struct kvm_segment var;
6737
6738 var.selector = selector;
6739 var.base = get_desc_base(desc);
6740 #ifdef CONFIG_X86_64
6741 var.base |= ((u64)base3) << 32;
6742 #endif
6743 var.limit = get_desc_limit(desc);
6744 if (desc->g)
6745 var.limit = (var.limit << 12) | 0xfff;
6746 var.type = desc->type;
6747 var.dpl = desc->dpl;
6748 var.db = desc->d;
6749 var.s = desc->s;
6750 var.l = desc->l;
6751 var.g = desc->g;
6752 var.avl = desc->avl;
6753 var.present = desc->p;
6754 var.unusable = !var.present;
6755 var.padding = 0;
6756
6757 kvm_set_segment(vcpu, &var, seg);
6758 return;
6759 }
6760
6761 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6762 u32 msr_index, u64 *pdata)
6763 {
6764 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6765 int r;
6766
6767 r = kvm_get_msr(vcpu, msr_index, pdata);
6768
6769 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6770 /* Bounce to user space */
6771 return X86EMUL_IO_NEEDED;
6772 }
6773
6774 return r;
6775 }
6776
6777 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6778 u32 msr_index, u64 data)
6779 {
6780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6781 int r;
6782
6783 r = kvm_set_msr(vcpu, msr_index, data);
6784
6785 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6786 /* Bounce to user space */
6787 return X86EMUL_IO_NEEDED;
6788 }
6789
6790 return r;
6791 }
6792
6793 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6794 {
6795 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6796
6797 return vcpu->arch.smbase;
6798 }
6799
6800 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6801 {
6802 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6803
6804 vcpu->arch.smbase = smbase;
6805 }
6806
6807 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6808 u32 pmc)
6809 {
6810 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6811 }
6812
6813 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6814 u32 pmc, u64 *pdata)
6815 {
6816 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6817 }
6818
6819 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6820 {
6821 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6822 }
6823
6824 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6825 struct x86_instruction_info *info,
6826 enum x86_intercept_stage stage)
6827 {
6828 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
6829 &ctxt->exception);
6830 }
6831
6832 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6833 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6834 bool exact_only)
6835 {
6836 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6837 }
6838
6839 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6840 {
6841 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6842 }
6843
6844 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6845 {
6846 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6847 }
6848
6849 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6850 {
6851 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6852 }
6853
6854 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6855 {
6856 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6857 }
6858
6859 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6860 {
6861 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6862 }
6863
6864 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6865 {
6866 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
6867 }
6868
6869 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6870 {
6871 return emul_to_vcpu(ctxt)->arch.hflags;
6872 }
6873
6874 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6875 {
6876 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6877 }
6878
6879 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6880 const char *smstate)
6881 {
6882 return static_call(kvm_x86_pre_leave_smm)(emul_to_vcpu(ctxt), smstate);
6883 }
6884
6885 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6886 {
6887 kvm_smm_changed(emul_to_vcpu(ctxt));
6888 }
6889
6890 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6891 {
6892 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6893 }
6894
6895 static const struct x86_emulate_ops emulate_ops = {
6896 .read_gpr = emulator_read_gpr,
6897 .write_gpr = emulator_write_gpr,
6898 .read_std = emulator_read_std,
6899 .write_std = emulator_write_std,
6900 .read_phys = kvm_read_guest_phys_system,
6901 .fetch = kvm_fetch_guest_virt,
6902 .read_emulated = emulator_read_emulated,
6903 .write_emulated = emulator_write_emulated,
6904 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6905 .invlpg = emulator_invlpg,
6906 .pio_in_emulated = emulator_pio_in_emulated,
6907 .pio_out_emulated = emulator_pio_out_emulated,
6908 .get_segment = emulator_get_segment,
6909 .set_segment = emulator_set_segment,
6910 .get_cached_segment_base = emulator_get_cached_segment_base,
6911 .get_gdt = emulator_get_gdt,
6912 .get_idt = emulator_get_idt,
6913 .set_gdt = emulator_set_gdt,
6914 .set_idt = emulator_set_idt,
6915 .get_cr = emulator_get_cr,
6916 .set_cr = emulator_set_cr,
6917 .cpl = emulator_get_cpl,
6918 .get_dr = emulator_get_dr,
6919 .set_dr = emulator_set_dr,
6920 .get_smbase = emulator_get_smbase,
6921 .set_smbase = emulator_set_smbase,
6922 .set_msr = emulator_set_msr,
6923 .get_msr = emulator_get_msr,
6924 .check_pmc = emulator_check_pmc,
6925 .read_pmc = emulator_read_pmc,
6926 .halt = emulator_halt,
6927 .wbinvd = emulator_wbinvd,
6928 .fix_hypercall = emulator_fix_hypercall,
6929 .intercept = emulator_intercept,
6930 .get_cpuid = emulator_get_cpuid,
6931 .guest_has_long_mode = emulator_guest_has_long_mode,
6932 .guest_has_movbe = emulator_guest_has_movbe,
6933 .guest_has_fxsr = emulator_guest_has_fxsr,
6934 .set_nmi_mask = emulator_set_nmi_mask,
6935 .get_hflags = emulator_get_hflags,
6936 .set_hflags = emulator_set_hflags,
6937 .pre_leave_smm = emulator_pre_leave_smm,
6938 .post_leave_smm = emulator_post_leave_smm,
6939 .set_xcr = emulator_set_xcr,
6940 };
6941
6942 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6943 {
6944 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
6945 /*
6946 * an sti; sti; sequence only disable interrupts for the first
6947 * instruction. So, if the last instruction, be it emulated or
6948 * not, left the system with the INT_STI flag enabled, it
6949 * means that the last instruction is an sti. We should not
6950 * leave the flag on in this case. The same goes for mov ss
6951 */
6952 if (int_shadow & mask)
6953 mask = 0;
6954 if (unlikely(int_shadow || mask)) {
6955 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
6956 if (!mask)
6957 kvm_make_request(KVM_REQ_EVENT, vcpu);
6958 }
6959 }
6960
6961 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6962 {
6963 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6964 if (ctxt->exception.vector == PF_VECTOR)
6965 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6966
6967 if (ctxt->exception.error_code_valid)
6968 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6969 ctxt->exception.error_code);
6970 else
6971 kvm_queue_exception(vcpu, ctxt->exception.vector);
6972 return false;
6973 }
6974
6975 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6976 {
6977 struct x86_emulate_ctxt *ctxt;
6978
6979 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6980 if (!ctxt) {
6981 pr_err("kvm: failed to allocate vcpu's emulator\n");
6982 return NULL;
6983 }
6984
6985 ctxt->vcpu = vcpu;
6986 ctxt->ops = &emulate_ops;
6987 vcpu->arch.emulate_ctxt = ctxt;
6988
6989 return ctxt;
6990 }
6991
6992 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6993 {
6994 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6995 int cs_db, cs_l;
6996
6997 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
6998
6999 ctxt->gpa_available = false;
7000 ctxt->eflags = kvm_get_rflags(vcpu);
7001 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
7002
7003 ctxt->eip = kvm_rip_read(vcpu);
7004 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
7005 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
7006 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
7007 cs_db ? X86EMUL_MODE_PROT32 :
7008 X86EMUL_MODE_PROT16;
7009 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
7010 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
7011 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
7012
7013 init_decode_cache(ctxt);
7014 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7015 }
7016
7017 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
7018 {
7019 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7020 int ret;
7021
7022 init_emulate_ctxt(vcpu);
7023
7024 ctxt->op_bytes = 2;
7025 ctxt->ad_bytes = 2;
7026 ctxt->_eip = ctxt->eip + inc_eip;
7027 ret = emulate_int_real(ctxt, irq);
7028
7029 if (ret != X86EMUL_CONTINUE) {
7030 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7031 } else {
7032 ctxt->eip = ctxt->_eip;
7033 kvm_rip_write(vcpu, ctxt->eip);
7034 kvm_set_rflags(vcpu, ctxt->eflags);
7035 }
7036 }
7037 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
7038
7039 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
7040 {
7041 ++vcpu->stat.insn_emulation_fail;
7042 trace_kvm_emulate_insn_failed(vcpu);
7043
7044 if (emulation_type & EMULTYPE_VMWARE_GP) {
7045 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7046 return 1;
7047 }
7048
7049 if (emulation_type & EMULTYPE_SKIP) {
7050 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7051 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7052 vcpu->run->internal.ndata = 0;
7053 return 0;
7054 }
7055
7056 kvm_queue_exception(vcpu, UD_VECTOR);
7057
7058 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
7059 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7060 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7061 vcpu->run->internal.ndata = 0;
7062 return 0;
7063 }
7064
7065 return 1;
7066 }
7067
7068 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7069 bool write_fault_to_shadow_pgtable,
7070 int emulation_type)
7071 {
7072 gpa_t gpa = cr2_or_gpa;
7073 kvm_pfn_t pfn;
7074
7075 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7076 return false;
7077
7078 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7079 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7080 return false;
7081
7082 if (!vcpu->arch.mmu->direct_map) {
7083 /*
7084 * Write permission should be allowed since only
7085 * write access need to be emulated.
7086 */
7087 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7088
7089 /*
7090 * If the mapping is invalid in guest, let cpu retry
7091 * it to generate fault.
7092 */
7093 if (gpa == UNMAPPED_GVA)
7094 return true;
7095 }
7096
7097 /*
7098 * Do not retry the unhandleable instruction if it faults on the
7099 * readonly host memory, otherwise it will goto a infinite loop:
7100 * retry instruction -> write #PF -> emulation fail -> retry
7101 * instruction -> ...
7102 */
7103 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
7104
7105 /*
7106 * If the instruction failed on the error pfn, it can not be fixed,
7107 * report the error to userspace.
7108 */
7109 if (is_error_noslot_pfn(pfn))
7110 return false;
7111
7112 kvm_release_pfn_clean(pfn);
7113
7114 /* The instructions are well-emulated on direct mmu. */
7115 if (vcpu->arch.mmu->direct_map) {
7116 unsigned int indirect_shadow_pages;
7117
7118 write_lock(&vcpu->kvm->mmu_lock);
7119 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
7120 write_unlock(&vcpu->kvm->mmu_lock);
7121
7122 if (indirect_shadow_pages)
7123 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7124
7125 return true;
7126 }
7127
7128 /*
7129 * if emulation was due to access to shadowed page table
7130 * and it failed try to unshadow page and re-enter the
7131 * guest to let CPU execute the instruction.
7132 */
7133 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7134
7135 /*
7136 * If the access faults on its page table, it can not
7137 * be fixed by unprotecting shadow page and it should
7138 * be reported to userspace.
7139 */
7140 return !write_fault_to_shadow_pgtable;
7141 }
7142
7143 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7144 gpa_t cr2_or_gpa, int emulation_type)
7145 {
7146 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7147 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7148
7149 last_retry_eip = vcpu->arch.last_retry_eip;
7150 last_retry_addr = vcpu->arch.last_retry_addr;
7151
7152 /*
7153 * If the emulation is caused by #PF and it is non-page_table
7154 * writing instruction, it means the VM-EXIT is caused by shadow
7155 * page protected, we can zap the shadow page and retry this
7156 * instruction directly.
7157 *
7158 * Note: if the guest uses a non-page-table modifying instruction
7159 * on the PDE that points to the instruction, then we will unmap
7160 * the instruction and go to an infinite loop. So, we cache the
7161 * last retried eip and the last fault address, if we meet the eip
7162 * and the address again, we can break out of the potential infinite
7163 * loop.
7164 */
7165 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7166
7167 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7168 return false;
7169
7170 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7171 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7172 return false;
7173
7174 if (x86_page_table_writing_insn(ctxt))
7175 return false;
7176
7177 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7178 return false;
7179
7180 vcpu->arch.last_retry_eip = ctxt->eip;
7181 vcpu->arch.last_retry_addr = cr2_or_gpa;
7182
7183 if (!vcpu->arch.mmu->direct_map)
7184 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7185
7186 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7187
7188 return true;
7189 }
7190
7191 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7192 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7193
7194 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7195 {
7196 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7197 /* This is a good place to trace that we are exiting SMM. */
7198 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7199
7200 /* Process a latched INIT or SMI, if any. */
7201 kvm_make_request(KVM_REQ_EVENT, vcpu);
7202 }
7203
7204 kvm_mmu_reset_context(vcpu);
7205 }
7206
7207 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7208 unsigned long *db)
7209 {
7210 u32 dr6 = 0;
7211 int i;
7212 u32 enable, rwlen;
7213
7214 enable = dr7;
7215 rwlen = dr7 >> 16;
7216 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7217 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7218 dr6 |= (1 << i);
7219 return dr6;
7220 }
7221
7222 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7223 {
7224 struct kvm_run *kvm_run = vcpu->run;
7225
7226 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7227 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
7228 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7229 kvm_run->debug.arch.exception = DB_VECTOR;
7230 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7231 return 0;
7232 }
7233 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7234 return 1;
7235 }
7236
7237 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7238 {
7239 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
7240 int r;
7241
7242 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
7243 if (unlikely(!r))
7244 return 0;
7245
7246 /*
7247 * rflags is the old, "raw" value of the flags. The new value has
7248 * not been saved yet.
7249 *
7250 * This is correct even for TF set by the guest, because "the
7251 * processor will not generate this exception after the instruction
7252 * that sets the TF flag".
7253 */
7254 if (unlikely(rflags & X86_EFLAGS_TF))
7255 r = kvm_vcpu_do_singlestep(vcpu);
7256 return r;
7257 }
7258 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7259
7260 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7261 {
7262 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7263 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7264 struct kvm_run *kvm_run = vcpu->run;
7265 unsigned long eip = kvm_get_linear_rip(vcpu);
7266 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7267 vcpu->arch.guest_debug_dr7,
7268 vcpu->arch.eff_db);
7269
7270 if (dr6 != 0) {
7271 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
7272 kvm_run->debug.arch.pc = eip;
7273 kvm_run->debug.arch.exception = DB_VECTOR;
7274 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7275 *r = 0;
7276 return true;
7277 }
7278 }
7279
7280 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7281 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7282 unsigned long eip = kvm_get_linear_rip(vcpu);
7283 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7284 vcpu->arch.dr7,
7285 vcpu->arch.db);
7286
7287 if (dr6 != 0) {
7288 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7289 *r = 1;
7290 return true;
7291 }
7292 }
7293
7294 return false;
7295 }
7296
7297 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7298 {
7299 switch (ctxt->opcode_len) {
7300 case 1:
7301 switch (ctxt->b) {
7302 case 0xe4: /* IN */
7303 case 0xe5:
7304 case 0xec:
7305 case 0xed:
7306 case 0xe6: /* OUT */
7307 case 0xe7:
7308 case 0xee:
7309 case 0xef:
7310 case 0x6c: /* INS */
7311 case 0x6d:
7312 case 0x6e: /* OUTS */
7313 case 0x6f:
7314 return true;
7315 }
7316 break;
7317 case 2:
7318 switch (ctxt->b) {
7319 case 0x33: /* RDPMC */
7320 return true;
7321 }
7322 break;
7323 }
7324
7325 return false;
7326 }
7327
7328 /*
7329 * Decode to be emulated instruction. Return EMULATION_OK if success.
7330 */
7331 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
7332 void *insn, int insn_len)
7333 {
7334 int r = EMULATION_OK;
7335 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7336
7337 init_emulate_ctxt(vcpu);
7338
7339 /*
7340 * We will reenter on the same instruction since we do not set
7341 * complete_userspace_io. This does not handle watchpoints yet,
7342 * those would be handled in the emulate_ops.
7343 */
7344 if (!(emulation_type & EMULTYPE_SKIP) &&
7345 kvm_vcpu_check_breakpoint(vcpu, &r))
7346 return r;
7347
7348 ctxt->interruptibility = 0;
7349 ctxt->have_exception = false;
7350 ctxt->exception.vector = -1;
7351 ctxt->perm_ok = false;
7352
7353 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7354
7355 r = x86_decode_insn(ctxt, insn, insn_len);
7356
7357 trace_kvm_emulate_insn_start(vcpu);
7358 ++vcpu->stat.insn_emulation;
7359
7360 return r;
7361 }
7362 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
7363
7364 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7365 int emulation_type, void *insn, int insn_len)
7366 {
7367 int r;
7368 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7369 bool writeback = true;
7370 bool write_fault_to_spt;
7371
7372 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len)))
7373 return 1;
7374
7375 vcpu->arch.l1tf_flush_l1d = true;
7376
7377 /*
7378 * Clear write_fault_to_shadow_pgtable here to ensure it is
7379 * never reused.
7380 */
7381 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7382 vcpu->arch.write_fault_to_shadow_pgtable = false;
7383
7384 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7385 kvm_clear_exception_queue(vcpu);
7386
7387 r = x86_decode_emulated_instruction(vcpu, emulation_type,
7388 insn, insn_len);
7389 if (r != EMULATION_OK) {
7390 if ((emulation_type & EMULTYPE_TRAP_UD) ||
7391 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7392 kvm_queue_exception(vcpu, UD_VECTOR);
7393 return 1;
7394 }
7395 if (reexecute_instruction(vcpu, cr2_or_gpa,
7396 write_fault_to_spt,
7397 emulation_type))
7398 return 1;
7399 if (ctxt->have_exception) {
7400 /*
7401 * #UD should result in just EMULATION_FAILED, and trap-like
7402 * exception should not be encountered during decode.
7403 */
7404 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7405 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7406 inject_emulated_exception(vcpu);
7407 return 1;
7408 }
7409 return handle_emulation_failure(vcpu, emulation_type);
7410 }
7411 }
7412
7413 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7414 !is_vmware_backdoor_opcode(ctxt)) {
7415 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7416 return 1;
7417 }
7418
7419 /*
7420 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7421 * for kvm_skip_emulated_instruction(). The caller is responsible for
7422 * updating interruptibility state and injecting single-step #DBs.
7423 */
7424 if (emulation_type & EMULTYPE_SKIP) {
7425 kvm_rip_write(vcpu, ctxt->_eip);
7426 if (ctxt->eflags & X86_EFLAGS_RF)
7427 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7428 return 1;
7429 }
7430
7431 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7432 return 1;
7433
7434 /* this is needed for vmware backdoor interface to work since it
7435 changes registers values during IO operation */
7436 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7437 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7438 emulator_invalidate_register_cache(ctxt);
7439 }
7440
7441 restart:
7442 if (emulation_type & EMULTYPE_PF) {
7443 /* Save the faulting GPA (cr2) in the address field */
7444 ctxt->exception.address = cr2_or_gpa;
7445
7446 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7447 if (vcpu->arch.mmu->direct_map) {
7448 ctxt->gpa_available = true;
7449 ctxt->gpa_val = cr2_or_gpa;
7450 }
7451 } else {
7452 /* Sanitize the address out of an abundance of paranoia. */
7453 ctxt->exception.address = 0;
7454 }
7455
7456 r = x86_emulate_insn(ctxt);
7457
7458 if (r == EMULATION_INTERCEPTED)
7459 return 1;
7460
7461 if (r == EMULATION_FAILED) {
7462 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7463 emulation_type))
7464 return 1;
7465
7466 return handle_emulation_failure(vcpu, emulation_type);
7467 }
7468
7469 if (ctxt->have_exception) {
7470 r = 1;
7471 if (inject_emulated_exception(vcpu))
7472 return r;
7473 } else if (vcpu->arch.pio.count) {
7474 if (!vcpu->arch.pio.in) {
7475 /* FIXME: return into emulator if single-stepping. */
7476 vcpu->arch.pio.count = 0;
7477 } else {
7478 writeback = false;
7479 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7480 }
7481 r = 0;
7482 } else if (vcpu->mmio_needed) {
7483 ++vcpu->stat.mmio_exits;
7484
7485 if (!vcpu->mmio_is_write)
7486 writeback = false;
7487 r = 0;
7488 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7489 } else if (r == EMULATION_RESTART)
7490 goto restart;
7491 else
7492 r = 1;
7493
7494 if (writeback) {
7495 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
7496 toggle_interruptibility(vcpu, ctxt->interruptibility);
7497 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7498 if (!ctxt->have_exception ||
7499 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7500 kvm_rip_write(vcpu, ctxt->eip);
7501 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7502 r = kvm_vcpu_do_singlestep(vcpu);
7503 if (kvm_x86_ops.update_emulated_instruction)
7504 static_call(kvm_x86_update_emulated_instruction)(vcpu);
7505 __kvm_set_rflags(vcpu, ctxt->eflags);
7506 }
7507
7508 /*
7509 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7510 * do nothing, and it will be requested again as soon as
7511 * the shadow expires. But we still need to check here,
7512 * because POPF has no interrupt shadow.
7513 */
7514 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7515 kvm_make_request(KVM_REQ_EVENT, vcpu);
7516 } else
7517 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7518
7519 return r;
7520 }
7521
7522 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7523 {
7524 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7525 }
7526 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7527
7528 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7529 void *insn, int insn_len)
7530 {
7531 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7532 }
7533 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7534
7535 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7536 {
7537 vcpu->arch.pio.count = 0;
7538 return 1;
7539 }
7540
7541 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7542 {
7543 vcpu->arch.pio.count = 0;
7544
7545 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7546 return 1;
7547
7548 return kvm_skip_emulated_instruction(vcpu);
7549 }
7550
7551 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7552 unsigned short port)
7553 {
7554 unsigned long val = kvm_rax_read(vcpu);
7555 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7556
7557 if (ret)
7558 return ret;
7559
7560 /*
7561 * Workaround userspace that relies on old KVM behavior of %rip being
7562 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7563 */
7564 if (port == 0x7e &&
7565 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7566 vcpu->arch.complete_userspace_io =
7567 complete_fast_pio_out_port_0x7e;
7568 kvm_skip_emulated_instruction(vcpu);
7569 } else {
7570 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7571 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7572 }
7573 return 0;
7574 }
7575
7576 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7577 {
7578 unsigned long val;
7579
7580 /* We should only ever be called with arch.pio.count equal to 1 */
7581 BUG_ON(vcpu->arch.pio.count != 1);
7582
7583 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7584 vcpu->arch.pio.count = 0;
7585 return 1;
7586 }
7587
7588 /* For size less than 4 we merge, else we zero extend */
7589 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7590
7591 /*
7592 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7593 * the copy and tracing
7594 */
7595 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7596 kvm_rax_write(vcpu, val);
7597
7598 return kvm_skip_emulated_instruction(vcpu);
7599 }
7600
7601 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7602 unsigned short port)
7603 {
7604 unsigned long val;
7605 int ret;
7606
7607 /* For size less than 4 we merge, else we zero extend */
7608 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7609
7610 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7611 if (ret) {
7612 kvm_rax_write(vcpu, val);
7613 return ret;
7614 }
7615
7616 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7617 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7618
7619 return 0;
7620 }
7621
7622 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7623 {
7624 int ret;
7625
7626 if (in)
7627 ret = kvm_fast_pio_in(vcpu, size, port);
7628 else
7629 ret = kvm_fast_pio_out(vcpu, size, port);
7630 return ret && kvm_skip_emulated_instruction(vcpu);
7631 }
7632 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7633
7634 static int kvmclock_cpu_down_prep(unsigned int cpu)
7635 {
7636 __this_cpu_write(cpu_tsc_khz, 0);
7637 return 0;
7638 }
7639
7640 static void tsc_khz_changed(void *data)
7641 {
7642 struct cpufreq_freqs *freq = data;
7643 unsigned long khz = 0;
7644
7645 if (data)
7646 khz = freq->new;
7647 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7648 khz = cpufreq_quick_get(raw_smp_processor_id());
7649 if (!khz)
7650 khz = tsc_khz;
7651 __this_cpu_write(cpu_tsc_khz, khz);
7652 }
7653
7654 #ifdef CONFIG_X86_64
7655 static void kvm_hyperv_tsc_notifier(void)
7656 {
7657 struct kvm *kvm;
7658 struct kvm_vcpu *vcpu;
7659 int cpu;
7660
7661 mutex_lock(&kvm_lock);
7662 list_for_each_entry(kvm, &vm_list, vm_list)
7663 kvm_make_mclock_inprogress_request(kvm);
7664
7665 hyperv_stop_tsc_emulation();
7666
7667 /* TSC frequency always matches when on Hyper-V */
7668 for_each_present_cpu(cpu)
7669 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7670 kvm_max_guest_tsc_khz = tsc_khz;
7671
7672 list_for_each_entry(kvm, &vm_list, vm_list) {
7673 struct kvm_arch *ka = &kvm->arch;
7674
7675 spin_lock(&ka->pvclock_gtod_sync_lock);
7676
7677 pvclock_update_vm_gtod_copy(kvm);
7678
7679 kvm_for_each_vcpu(cpu, vcpu, kvm)
7680 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7681
7682 kvm_for_each_vcpu(cpu, vcpu, kvm)
7683 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7684
7685 spin_unlock(&ka->pvclock_gtod_sync_lock);
7686 }
7687 mutex_unlock(&kvm_lock);
7688 }
7689 #endif
7690
7691 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7692 {
7693 struct kvm *kvm;
7694 struct kvm_vcpu *vcpu;
7695 int i, send_ipi = 0;
7696
7697 /*
7698 * We allow guests to temporarily run on slowing clocks,
7699 * provided we notify them after, or to run on accelerating
7700 * clocks, provided we notify them before. Thus time never
7701 * goes backwards.
7702 *
7703 * However, we have a problem. We can't atomically update
7704 * the frequency of a given CPU from this function; it is
7705 * merely a notifier, which can be called from any CPU.
7706 * Changing the TSC frequency at arbitrary points in time
7707 * requires a recomputation of local variables related to
7708 * the TSC for each VCPU. We must flag these local variables
7709 * to be updated and be sure the update takes place with the
7710 * new frequency before any guests proceed.
7711 *
7712 * Unfortunately, the combination of hotplug CPU and frequency
7713 * change creates an intractable locking scenario; the order
7714 * of when these callouts happen is undefined with respect to
7715 * CPU hotplug, and they can race with each other. As such,
7716 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7717 * undefined; you can actually have a CPU frequency change take
7718 * place in between the computation of X and the setting of the
7719 * variable. To protect against this problem, all updates of
7720 * the per_cpu tsc_khz variable are done in an interrupt
7721 * protected IPI, and all callers wishing to update the value
7722 * must wait for a synchronous IPI to complete (which is trivial
7723 * if the caller is on the CPU already). This establishes the
7724 * necessary total order on variable updates.
7725 *
7726 * Note that because a guest time update may take place
7727 * anytime after the setting of the VCPU's request bit, the
7728 * correct TSC value must be set before the request. However,
7729 * to ensure the update actually makes it to any guest which
7730 * starts running in hardware virtualization between the set
7731 * and the acquisition of the spinlock, we must also ping the
7732 * CPU after setting the request bit.
7733 *
7734 */
7735
7736 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7737
7738 mutex_lock(&kvm_lock);
7739 list_for_each_entry(kvm, &vm_list, vm_list) {
7740 kvm_for_each_vcpu(i, vcpu, kvm) {
7741 if (vcpu->cpu != cpu)
7742 continue;
7743 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7744 if (vcpu->cpu != raw_smp_processor_id())
7745 send_ipi = 1;
7746 }
7747 }
7748 mutex_unlock(&kvm_lock);
7749
7750 if (freq->old < freq->new && send_ipi) {
7751 /*
7752 * We upscale the frequency. Must make the guest
7753 * doesn't see old kvmclock values while running with
7754 * the new frequency, otherwise we risk the guest sees
7755 * time go backwards.
7756 *
7757 * In case we update the frequency for another cpu
7758 * (which might be in guest context) send an interrupt
7759 * to kick the cpu out of guest context. Next time
7760 * guest context is entered kvmclock will be updated,
7761 * so the guest will not see stale values.
7762 */
7763 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7764 }
7765 }
7766
7767 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7768 void *data)
7769 {
7770 struct cpufreq_freqs *freq = data;
7771 int cpu;
7772
7773 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7774 return 0;
7775 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7776 return 0;
7777
7778 for_each_cpu(cpu, freq->policy->cpus)
7779 __kvmclock_cpufreq_notifier(freq, cpu);
7780
7781 return 0;
7782 }
7783
7784 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7785 .notifier_call = kvmclock_cpufreq_notifier
7786 };
7787
7788 static int kvmclock_cpu_online(unsigned int cpu)
7789 {
7790 tsc_khz_changed(NULL);
7791 return 0;
7792 }
7793
7794 static void kvm_timer_init(void)
7795 {
7796 max_tsc_khz = tsc_khz;
7797
7798 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7799 #ifdef CONFIG_CPU_FREQ
7800 struct cpufreq_policy *policy;
7801 int cpu;
7802
7803 cpu = get_cpu();
7804 policy = cpufreq_cpu_get(cpu);
7805 if (policy) {
7806 if (policy->cpuinfo.max_freq)
7807 max_tsc_khz = policy->cpuinfo.max_freq;
7808 cpufreq_cpu_put(policy);
7809 }
7810 put_cpu();
7811 #endif
7812 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7813 CPUFREQ_TRANSITION_NOTIFIER);
7814 }
7815
7816 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7817 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7818 }
7819
7820 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7821 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7822
7823 int kvm_is_in_guest(void)
7824 {
7825 return __this_cpu_read(current_vcpu) != NULL;
7826 }
7827
7828 static int kvm_is_user_mode(void)
7829 {
7830 int user_mode = 3;
7831
7832 if (__this_cpu_read(current_vcpu))
7833 user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu));
7834
7835 return user_mode != 0;
7836 }
7837
7838 static unsigned long kvm_get_guest_ip(void)
7839 {
7840 unsigned long ip = 0;
7841
7842 if (__this_cpu_read(current_vcpu))
7843 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7844
7845 return ip;
7846 }
7847
7848 static void kvm_handle_intel_pt_intr(void)
7849 {
7850 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7851
7852 kvm_make_request(KVM_REQ_PMI, vcpu);
7853 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7854 (unsigned long *)&vcpu->arch.pmu.global_status);
7855 }
7856
7857 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7858 .is_in_guest = kvm_is_in_guest,
7859 .is_user_mode = kvm_is_user_mode,
7860 .get_guest_ip = kvm_get_guest_ip,
7861 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7862 };
7863
7864 #ifdef CONFIG_X86_64
7865 static void pvclock_gtod_update_fn(struct work_struct *work)
7866 {
7867 struct kvm *kvm;
7868
7869 struct kvm_vcpu *vcpu;
7870 int i;
7871
7872 mutex_lock(&kvm_lock);
7873 list_for_each_entry(kvm, &vm_list, vm_list)
7874 kvm_for_each_vcpu(i, vcpu, kvm)
7875 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7876 atomic_set(&kvm_guest_has_master_clock, 0);
7877 mutex_unlock(&kvm_lock);
7878 }
7879
7880 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7881
7882 /*
7883 * Notification about pvclock gtod data update.
7884 */
7885 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7886 void *priv)
7887 {
7888 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7889 struct timekeeper *tk = priv;
7890
7891 update_pvclock_gtod(tk);
7892
7893 /* disable master clock if host does not trust, or does not
7894 * use, TSC based clocksource.
7895 */
7896 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7897 atomic_read(&kvm_guest_has_master_clock) != 0)
7898 queue_work(system_long_wq, &pvclock_gtod_work);
7899
7900 return 0;
7901 }
7902
7903 static struct notifier_block pvclock_gtod_notifier = {
7904 .notifier_call = pvclock_gtod_notify,
7905 };
7906 #endif
7907
7908 int kvm_arch_init(void *opaque)
7909 {
7910 struct kvm_x86_init_ops *ops = opaque;
7911 int r;
7912
7913 if (kvm_x86_ops.hardware_enable) {
7914 printk(KERN_ERR "kvm: already loaded the other module\n");
7915 r = -EEXIST;
7916 goto out;
7917 }
7918
7919 if (!ops->cpu_has_kvm_support()) {
7920 pr_err_ratelimited("kvm: no hardware support\n");
7921 r = -EOPNOTSUPP;
7922 goto out;
7923 }
7924 if (ops->disabled_by_bios()) {
7925 pr_err_ratelimited("kvm: disabled by bios\n");
7926 r = -EOPNOTSUPP;
7927 goto out;
7928 }
7929
7930 /*
7931 * KVM explicitly assumes that the guest has an FPU and
7932 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7933 * vCPU's FPU state as a fxregs_state struct.
7934 */
7935 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7936 printk(KERN_ERR "kvm: inadequate fpu\n");
7937 r = -EOPNOTSUPP;
7938 goto out;
7939 }
7940
7941 r = -ENOMEM;
7942 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7943 __alignof__(struct fpu), SLAB_ACCOUNT,
7944 NULL);
7945 if (!x86_fpu_cache) {
7946 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7947 goto out;
7948 }
7949
7950 x86_emulator_cache = kvm_alloc_emulator_cache();
7951 if (!x86_emulator_cache) {
7952 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7953 goto out_free_x86_fpu_cache;
7954 }
7955
7956 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7957 if (!user_return_msrs) {
7958 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7959 goto out_free_x86_emulator_cache;
7960 }
7961
7962 r = kvm_mmu_module_init();
7963 if (r)
7964 goto out_free_percpu;
7965
7966 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7967 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7968 PT_PRESENT_MASK, 0, sme_me_mask);
7969 kvm_timer_init();
7970
7971 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7972
7973 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7974 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7975 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7976 }
7977
7978 if (pi_inject_timer == -1)
7979 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7980 #ifdef CONFIG_X86_64
7981 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7982
7983 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7984 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7985 #endif
7986
7987 return 0;
7988
7989 out_free_percpu:
7990 free_percpu(user_return_msrs);
7991 out_free_x86_emulator_cache:
7992 kmem_cache_destroy(x86_emulator_cache);
7993 out_free_x86_fpu_cache:
7994 kmem_cache_destroy(x86_fpu_cache);
7995 out:
7996 return r;
7997 }
7998
7999 void kvm_arch_exit(void)
8000 {
8001 #ifdef CONFIG_X86_64
8002 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8003 clear_hv_tscchange_cb();
8004 #endif
8005 kvm_lapic_exit();
8006 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
8007
8008 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8009 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
8010 CPUFREQ_TRANSITION_NOTIFIER);
8011 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
8012 #ifdef CONFIG_X86_64
8013 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
8014 #endif
8015 kvm_x86_ops.hardware_enable = NULL;
8016 kvm_mmu_module_exit();
8017 free_percpu(user_return_msrs);
8018 kmem_cache_destroy(x86_fpu_cache);
8019 }
8020
8021 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason)
8022 {
8023 ++vcpu->stat.halt_exits;
8024 if (lapic_in_kernel(vcpu)) {
8025 vcpu->arch.mp_state = state;
8026 return 1;
8027 } else {
8028 vcpu->run->exit_reason = reason;
8029 return 0;
8030 }
8031 }
8032
8033 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8034 {
8035 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
8036 }
8037 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
8038
8039 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
8040 {
8041 int ret = kvm_skip_emulated_instruction(vcpu);
8042 /*
8043 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
8044 * KVM_EXIT_DEBUG here.
8045 */
8046 return kvm_vcpu_halt(vcpu) && ret;
8047 }
8048 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
8049
8050 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
8051 {
8052 int ret = kvm_skip_emulated_instruction(vcpu);
8053
8054 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret;
8055 }
8056 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
8057
8058 #ifdef CONFIG_X86_64
8059 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
8060 unsigned long clock_type)
8061 {
8062 struct kvm_clock_pairing clock_pairing;
8063 struct timespec64 ts;
8064 u64 cycle;
8065 int ret;
8066
8067 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
8068 return -KVM_EOPNOTSUPP;
8069
8070 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
8071 return -KVM_EOPNOTSUPP;
8072
8073 clock_pairing.sec = ts.tv_sec;
8074 clock_pairing.nsec = ts.tv_nsec;
8075 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
8076 clock_pairing.flags = 0;
8077 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
8078
8079 ret = 0;
8080 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
8081 sizeof(struct kvm_clock_pairing)))
8082 ret = -KVM_EFAULT;
8083
8084 return ret;
8085 }
8086 #endif
8087
8088 /*
8089 * kvm_pv_kick_cpu_op: Kick a vcpu.
8090 *
8091 * @apicid - apicid of vcpu to be kicked.
8092 */
8093 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
8094 {
8095 struct kvm_lapic_irq lapic_irq;
8096
8097 lapic_irq.shorthand = APIC_DEST_NOSHORT;
8098 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
8099 lapic_irq.level = 0;
8100 lapic_irq.dest_id = apicid;
8101 lapic_irq.msi_redir_hint = false;
8102
8103 lapic_irq.delivery_mode = APIC_DM_REMRD;
8104 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
8105 }
8106
8107 bool kvm_apicv_activated(struct kvm *kvm)
8108 {
8109 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
8110 }
8111 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
8112
8113 void kvm_apicv_init(struct kvm *kvm, bool enable)
8114 {
8115 if (enable)
8116 clear_bit(APICV_INHIBIT_REASON_DISABLE,
8117 &kvm->arch.apicv_inhibit_reasons);
8118 else
8119 set_bit(APICV_INHIBIT_REASON_DISABLE,
8120 &kvm->arch.apicv_inhibit_reasons);
8121 }
8122 EXPORT_SYMBOL_GPL(kvm_apicv_init);
8123
8124 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
8125 {
8126 struct kvm_vcpu *target = NULL;
8127 struct kvm_apic_map *map;
8128
8129 rcu_read_lock();
8130 map = rcu_dereference(kvm->arch.apic_map);
8131
8132 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
8133 target = map->phys_map[dest_id]->vcpu;
8134
8135 rcu_read_unlock();
8136
8137 if (target && READ_ONCE(target->ready))
8138 kvm_vcpu_yield_to(target);
8139 }
8140
8141 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
8142 {
8143 unsigned long nr, a0, a1, a2, a3, ret;
8144 int op_64_bit;
8145
8146 if (kvm_hv_hypercall_enabled(vcpu->kvm))
8147 return kvm_hv_hypercall(vcpu);
8148
8149 nr = kvm_rax_read(vcpu);
8150 a0 = kvm_rbx_read(vcpu);
8151 a1 = kvm_rcx_read(vcpu);
8152 a2 = kvm_rdx_read(vcpu);
8153 a3 = kvm_rsi_read(vcpu);
8154
8155 trace_kvm_hypercall(nr, a0, a1, a2, a3);
8156
8157 op_64_bit = is_64_bit_mode(vcpu);
8158 if (!op_64_bit) {
8159 nr &= 0xFFFFFFFF;
8160 a0 &= 0xFFFFFFFF;
8161 a1 &= 0xFFFFFFFF;
8162 a2 &= 0xFFFFFFFF;
8163 a3 &= 0xFFFFFFFF;
8164 }
8165
8166 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
8167 ret = -KVM_EPERM;
8168 goto out;
8169 }
8170
8171 ret = -KVM_ENOSYS;
8172
8173 switch (nr) {
8174 case KVM_HC_VAPIC_POLL_IRQ:
8175 ret = 0;
8176 break;
8177 case KVM_HC_KICK_CPU:
8178 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
8179 break;
8180
8181 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8182 kvm_sched_yield(vcpu->kvm, a1);
8183 ret = 0;
8184 break;
8185 #ifdef CONFIG_X86_64
8186 case KVM_HC_CLOCK_PAIRING:
8187 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8188 break;
8189 #endif
8190 case KVM_HC_SEND_IPI:
8191 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
8192 break;
8193
8194 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8195 break;
8196 case KVM_HC_SCHED_YIELD:
8197 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
8198 break;
8199
8200 kvm_sched_yield(vcpu->kvm, a0);
8201 ret = 0;
8202 break;
8203 default:
8204 ret = -KVM_ENOSYS;
8205 break;
8206 }
8207 out:
8208 if (!op_64_bit)
8209 ret = (u32)ret;
8210 kvm_rax_write(vcpu, ret);
8211
8212 ++vcpu->stat.hypercalls;
8213 return kvm_skip_emulated_instruction(vcpu);
8214 }
8215 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8216
8217 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8218 {
8219 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8220 char instruction[3];
8221 unsigned long rip = kvm_rip_read(vcpu);
8222
8223 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
8224
8225 return emulator_write_emulated(ctxt, rip, instruction, 3,
8226 &ctxt->exception);
8227 }
8228
8229 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8230 {
8231 return vcpu->run->request_interrupt_window &&
8232 likely(!pic_in_kernel(vcpu->kvm));
8233 }
8234
8235 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8236 {
8237 struct kvm_run *kvm_run = vcpu->run;
8238
8239 /*
8240 * if_flag is obsolete and useless, so do not bother
8241 * setting it for SEV-ES guests. Userspace can just
8242 * use kvm_run->ready_for_interrupt_injection.
8243 */
8244 kvm_run->if_flag = !vcpu->arch.guest_state_protected
8245 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8246
8247 kvm_run->cr8 = kvm_get_cr8(vcpu);
8248 kvm_run->apic_base = kvm_get_apic_base(vcpu);
8249 kvm_run->ready_for_interrupt_injection =
8250 pic_in_kernel(vcpu->kvm) ||
8251 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8252
8253 if (is_smm(vcpu))
8254 kvm_run->flags |= KVM_RUN_X86_SMM;
8255 }
8256
8257 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8258 {
8259 int max_irr, tpr;
8260
8261 if (!kvm_x86_ops.update_cr8_intercept)
8262 return;
8263
8264 if (!lapic_in_kernel(vcpu))
8265 return;
8266
8267 if (vcpu->arch.apicv_active)
8268 return;
8269
8270 if (!vcpu->arch.apic->vapic_addr)
8271 max_irr = kvm_lapic_find_highest_irr(vcpu);
8272 else
8273 max_irr = -1;
8274
8275 if (max_irr != -1)
8276 max_irr >>= 4;
8277
8278 tpr = kvm_lapic_get_cr8(vcpu);
8279
8280 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
8281 }
8282
8283 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8284 {
8285 int r;
8286 bool can_inject = true;
8287
8288 /* try to reinject previous events if any */
8289
8290 if (vcpu->arch.exception.injected) {
8291 static_call(kvm_x86_queue_exception)(vcpu);
8292 can_inject = false;
8293 }
8294 /*
8295 * Do not inject an NMI or interrupt if there is a pending
8296 * exception. Exceptions and interrupts are recognized at
8297 * instruction boundaries, i.e. the start of an instruction.
8298 * Trap-like exceptions, e.g. #DB, have higher priority than
8299 * NMIs and interrupts, i.e. traps are recognized before an
8300 * NMI/interrupt that's pending on the same instruction.
8301 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8302 * priority, but are only generated (pended) during instruction
8303 * execution, i.e. a pending fault-like exception means the
8304 * fault occurred on the *previous* instruction and must be
8305 * serviced prior to recognizing any new events in order to
8306 * fully complete the previous instruction.
8307 */
8308 else if (!vcpu->arch.exception.pending) {
8309 if (vcpu->arch.nmi_injected) {
8310 static_call(kvm_x86_set_nmi)(vcpu);
8311 can_inject = false;
8312 } else if (vcpu->arch.interrupt.injected) {
8313 static_call(kvm_x86_set_irq)(vcpu);
8314 can_inject = false;
8315 }
8316 }
8317
8318 WARN_ON_ONCE(vcpu->arch.exception.injected &&
8319 vcpu->arch.exception.pending);
8320
8321 /*
8322 * Call check_nested_events() even if we reinjected a previous event
8323 * in order for caller to determine if it should require immediate-exit
8324 * from L2 to L1 due to pending L1 events which require exit
8325 * from L2 to L1.
8326 */
8327 if (is_guest_mode(vcpu)) {
8328 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8329 if (r < 0)
8330 goto busy;
8331 }
8332
8333 /* try to inject new event if pending */
8334 if (vcpu->arch.exception.pending) {
8335 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8336 vcpu->arch.exception.has_error_code,
8337 vcpu->arch.exception.error_code);
8338
8339 vcpu->arch.exception.pending = false;
8340 vcpu->arch.exception.injected = true;
8341
8342 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8343 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8344 X86_EFLAGS_RF);
8345
8346 if (vcpu->arch.exception.nr == DB_VECTOR) {
8347 kvm_deliver_exception_payload(vcpu);
8348 if (vcpu->arch.dr7 & DR7_GD) {
8349 vcpu->arch.dr7 &= ~DR7_GD;
8350 kvm_update_dr7(vcpu);
8351 }
8352 }
8353
8354 static_call(kvm_x86_queue_exception)(vcpu);
8355 can_inject = false;
8356 }
8357
8358 /*
8359 * Finally, inject interrupt events. If an event cannot be injected
8360 * due to architectural conditions (e.g. IF=0) a window-open exit
8361 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
8362 * and can architecturally be injected, but we cannot do it right now:
8363 * an interrupt could have arrived just now and we have to inject it
8364 * as a vmexit, or there could already an event in the queue, which is
8365 * indicated by can_inject. In that case we request an immediate exit
8366 * in order to make progress and get back here for another iteration.
8367 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8368 */
8369 if (vcpu->arch.smi_pending) {
8370 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
8371 if (r < 0)
8372 goto busy;
8373 if (r) {
8374 vcpu->arch.smi_pending = false;
8375 ++vcpu->arch.smi_count;
8376 enter_smm(vcpu);
8377 can_inject = false;
8378 } else
8379 static_call(kvm_x86_enable_smi_window)(vcpu);
8380 }
8381
8382 if (vcpu->arch.nmi_pending) {
8383 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
8384 if (r < 0)
8385 goto busy;
8386 if (r) {
8387 --vcpu->arch.nmi_pending;
8388 vcpu->arch.nmi_injected = true;
8389 static_call(kvm_x86_set_nmi)(vcpu);
8390 can_inject = false;
8391 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
8392 }
8393 if (vcpu->arch.nmi_pending)
8394 static_call(kvm_x86_enable_nmi_window)(vcpu);
8395 }
8396
8397 if (kvm_cpu_has_injectable_intr(vcpu)) {
8398 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
8399 if (r < 0)
8400 goto busy;
8401 if (r) {
8402 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8403 static_call(kvm_x86_set_irq)(vcpu);
8404 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
8405 }
8406 if (kvm_cpu_has_injectable_intr(vcpu))
8407 static_call(kvm_x86_enable_irq_window)(vcpu);
8408 }
8409
8410 if (is_guest_mode(vcpu) &&
8411 kvm_x86_ops.nested_ops->hv_timer_pending &&
8412 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8413 *req_immediate_exit = true;
8414
8415 WARN_ON(vcpu->arch.exception.pending);
8416 return;
8417
8418 busy:
8419 *req_immediate_exit = true;
8420 return;
8421 }
8422
8423 static void process_nmi(struct kvm_vcpu *vcpu)
8424 {
8425 unsigned limit = 2;
8426
8427 /*
8428 * x86 is limited to one NMI running, and one NMI pending after it.
8429 * If an NMI is already in progress, limit further NMIs to just one.
8430 * Otherwise, allow two (and we'll inject the first one immediately).
8431 */
8432 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
8433 limit = 1;
8434
8435 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8436 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8437 kvm_make_request(KVM_REQ_EVENT, vcpu);
8438 }
8439
8440 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8441 {
8442 u32 flags = 0;
8443 flags |= seg->g << 23;
8444 flags |= seg->db << 22;
8445 flags |= seg->l << 21;
8446 flags |= seg->avl << 20;
8447 flags |= seg->present << 15;
8448 flags |= seg->dpl << 13;
8449 flags |= seg->s << 12;
8450 flags |= seg->type << 8;
8451 return flags;
8452 }
8453
8454 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8455 {
8456 struct kvm_segment seg;
8457 int offset;
8458
8459 kvm_get_segment(vcpu, &seg, n);
8460 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8461
8462 if (n < 3)
8463 offset = 0x7f84 + n * 12;
8464 else
8465 offset = 0x7f2c + (n - 3) * 12;
8466
8467 put_smstate(u32, buf, offset + 8, seg.base);
8468 put_smstate(u32, buf, offset + 4, seg.limit);
8469 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8470 }
8471
8472 #ifdef CONFIG_X86_64
8473 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8474 {
8475 struct kvm_segment seg;
8476 int offset;
8477 u16 flags;
8478
8479 kvm_get_segment(vcpu, &seg, n);
8480 offset = 0x7e00 + n * 16;
8481
8482 flags = enter_smm_get_segment_flags(&seg) >> 8;
8483 put_smstate(u16, buf, offset, seg.selector);
8484 put_smstate(u16, buf, offset + 2, flags);
8485 put_smstate(u32, buf, offset + 4, seg.limit);
8486 put_smstate(u64, buf, offset + 8, seg.base);
8487 }
8488 #endif
8489
8490 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8491 {
8492 struct desc_ptr dt;
8493 struct kvm_segment seg;
8494 unsigned long val;
8495 int i;
8496
8497 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8498 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8499 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8500 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8501
8502 for (i = 0; i < 8; i++)
8503 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8504
8505 kvm_get_dr(vcpu, 6, &val);
8506 put_smstate(u32, buf, 0x7fcc, (u32)val);
8507 kvm_get_dr(vcpu, 7, &val);
8508 put_smstate(u32, buf, 0x7fc8, (u32)val);
8509
8510 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8511 put_smstate(u32, buf, 0x7fc4, seg.selector);
8512 put_smstate(u32, buf, 0x7f64, seg.base);
8513 put_smstate(u32, buf, 0x7f60, seg.limit);
8514 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8515
8516 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8517 put_smstate(u32, buf, 0x7fc0, seg.selector);
8518 put_smstate(u32, buf, 0x7f80, seg.base);
8519 put_smstate(u32, buf, 0x7f7c, seg.limit);
8520 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8521
8522 static_call(kvm_x86_get_gdt)(vcpu, &dt);
8523 put_smstate(u32, buf, 0x7f74, dt.address);
8524 put_smstate(u32, buf, 0x7f70, dt.size);
8525
8526 static_call(kvm_x86_get_idt)(vcpu, &dt);
8527 put_smstate(u32, buf, 0x7f58, dt.address);
8528 put_smstate(u32, buf, 0x7f54, dt.size);
8529
8530 for (i = 0; i < 6; i++)
8531 enter_smm_save_seg_32(vcpu, buf, i);
8532
8533 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8534
8535 /* revision id */
8536 put_smstate(u32, buf, 0x7efc, 0x00020000);
8537 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8538 }
8539
8540 #ifdef CONFIG_X86_64
8541 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8542 {
8543 struct desc_ptr dt;
8544 struct kvm_segment seg;
8545 unsigned long val;
8546 int i;
8547
8548 for (i = 0; i < 16; i++)
8549 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8550
8551 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8552 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8553
8554 kvm_get_dr(vcpu, 6, &val);
8555 put_smstate(u64, buf, 0x7f68, val);
8556 kvm_get_dr(vcpu, 7, &val);
8557 put_smstate(u64, buf, 0x7f60, val);
8558
8559 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8560 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8561 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8562
8563 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8564
8565 /* revision id */
8566 put_smstate(u32, buf, 0x7efc, 0x00020064);
8567
8568 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8569
8570 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8571 put_smstate(u16, buf, 0x7e90, seg.selector);
8572 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8573 put_smstate(u32, buf, 0x7e94, seg.limit);
8574 put_smstate(u64, buf, 0x7e98, seg.base);
8575
8576 static_call(kvm_x86_get_idt)(vcpu, &dt);
8577 put_smstate(u32, buf, 0x7e84, dt.size);
8578 put_smstate(u64, buf, 0x7e88, dt.address);
8579
8580 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8581 put_smstate(u16, buf, 0x7e70, seg.selector);
8582 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8583 put_smstate(u32, buf, 0x7e74, seg.limit);
8584 put_smstate(u64, buf, 0x7e78, seg.base);
8585
8586 static_call(kvm_x86_get_gdt)(vcpu, &dt);
8587 put_smstate(u32, buf, 0x7e64, dt.size);
8588 put_smstate(u64, buf, 0x7e68, dt.address);
8589
8590 for (i = 0; i < 6; i++)
8591 enter_smm_save_seg_64(vcpu, buf, i);
8592 }
8593 #endif
8594
8595 static void enter_smm(struct kvm_vcpu *vcpu)
8596 {
8597 struct kvm_segment cs, ds;
8598 struct desc_ptr dt;
8599 char buf[512];
8600 u32 cr0;
8601
8602 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8603 memset(buf, 0, 512);
8604 #ifdef CONFIG_X86_64
8605 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8606 enter_smm_save_state_64(vcpu, buf);
8607 else
8608 #endif
8609 enter_smm_save_state_32(vcpu, buf);
8610
8611 /*
8612 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8613 * vCPU state (e.g. leave guest mode) after we've saved the state into
8614 * the SMM state-save area.
8615 */
8616 static_call(kvm_x86_pre_enter_smm)(vcpu, buf);
8617
8618 vcpu->arch.hflags |= HF_SMM_MASK;
8619 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8620
8621 if (static_call(kvm_x86_get_nmi_mask)(vcpu))
8622 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8623 else
8624 static_call(kvm_x86_set_nmi_mask)(vcpu, true);
8625
8626 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8627 kvm_rip_write(vcpu, 0x8000);
8628
8629 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8630 static_call(kvm_x86_set_cr0)(vcpu, cr0);
8631 vcpu->arch.cr0 = cr0;
8632
8633 static_call(kvm_x86_set_cr4)(vcpu, 0);
8634
8635 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8636 dt.address = dt.size = 0;
8637 static_call(kvm_x86_set_idt)(vcpu, &dt);
8638
8639 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8640
8641 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8642 cs.base = vcpu->arch.smbase;
8643
8644 ds.selector = 0;
8645 ds.base = 0;
8646
8647 cs.limit = ds.limit = 0xffffffff;
8648 cs.type = ds.type = 0x3;
8649 cs.dpl = ds.dpl = 0;
8650 cs.db = ds.db = 0;
8651 cs.s = ds.s = 1;
8652 cs.l = ds.l = 0;
8653 cs.g = ds.g = 1;
8654 cs.avl = ds.avl = 0;
8655 cs.present = ds.present = 1;
8656 cs.unusable = ds.unusable = 0;
8657 cs.padding = ds.padding = 0;
8658
8659 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8660 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8661 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8662 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8663 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8664 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8665
8666 #ifdef CONFIG_X86_64
8667 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8668 static_call(kvm_x86_set_efer)(vcpu, 0);
8669 #endif
8670
8671 kvm_update_cpuid_runtime(vcpu);
8672 kvm_mmu_reset_context(vcpu);
8673 }
8674
8675 static void process_smi(struct kvm_vcpu *vcpu)
8676 {
8677 vcpu->arch.smi_pending = true;
8678 kvm_make_request(KVM_REQ_EVENT, vcpu);
8679 }
8680
8681 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8682 unsigned long *vcpu_bitmap)
8683 {
8684 cpumask_var_t cpus;
8685
8686 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8687
8688 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8689 NULL, vcpu_bitmap, cpus);
8690
8691 free_cpumask_var(cpus);
8692 }
8693
8694 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8695 {
8696 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8697 }
8698
8699 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8700 {
8701 if (!lapic_in_kernel(vcpu))
8702 return;
8703
8704 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8705 kvm_apic_update_apicv(vcpu);
8706 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
8707 }
8708 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8709
8710 /*
8711 * NOTE: Do not hold any lock prior to calling this.
8712 *
8713 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8714 * locked, because it calls __x86_set_memory_region() which does
8715 * synchronize_srcu(&kvm->srcu).
8716 */
8717 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8718 {
8719 struct kvm_vcpu *except;
8720 unsigned long old, new, expected;
8721
8722 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8723 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit))
8724 return;
8725
8726 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8727 do {
8728 expected = new = old;
8729 if (activate)
8730 __clear_bit(bit, &new);
8731 else
8732 __set_bit(bit, &new);
8733 if (new == old)
8734 break;
8735 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8736 } while (old != expected);
8737
8738 if (!!old == !!new)
8739 return;
8740
8741 trace_kvm_apicv_update_request(activate, bit);
8742 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8743 static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate);
8744
8745 /*
8746 * Sending request to update APICV for all other vcpus,
8747 * while update the calling vcpu immediately instead of
8748 * waiting for another #VMEXIT to handle the request.
8749 */
8750 except = kvm_get_running_vcpu();
8751 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8752 except);
8753 if (except)
8754 kvm_vcpu_update_apicv(except);
8755 }
8756 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8757
8758 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8759 {
8760 if (!kvm_apic_present(vcpu))
8761 return;
8762
8763 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8764
8765 if (irqchip_split(vcpu->kvm))
8766 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8767 else {
8768 if (vcpu->arch.apicv_active)
8769 static_call(kvm_x86_sync_pir_to_irr)(vcpu);
8770 if (ioapic_in_kernel(vcpu->kvm))
8771 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8772 }
8773
8774 if (is_guest_mode(vcpu))
8775 vcpu->arch.load_eoi_exitmap_pending = true;
8776 else
8777 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8778 }
8779
8780 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8781 {
8782 u64 eoi_exit_bitmap[4];
8783
8784 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8785 return;
8786
8787 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8788 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8789 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
8790 }
8791
8792 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8793 unsigned long start, unsigned long end)
8794 {
8795 unsigned long apic_address;
8796
8797 /*
8798 * The physical address of apic access page is stored in the VMCS.
8799 * Update it when it becomes invalid.
8800 */
8801 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8802 if (start <= apic_address && apic_address < end)
8803 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8804 }
8805
8806 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8807 {
8808 if (!lapic_in_kernel(vcpu))
8809 return;
8810
8811 if (!kvm_x86_ops.set_apic_access_page_addr)
8812 return;
8813
8814 static_call(kvm_x86_set_apic_access_page_addr)(vcpu);
8815 }
8816
8817 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8818 {
8819 smp_send_reschedule(vcpu->cpu);
8820 }
8821 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8822
8823 /*
8824 * Returns 1 to let vcpu_run() continue the guest execution loop without
8825 * exiting to the userspace. Otherwise, the value will be returned to the
8826 * userspace.
8827 */
8828 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8829 {
8830 int r;
8831 bool req_int_win =
8832 dm_request_for_irq_injection(vcpu) &&
8833 kvm_cpu_accept_dm_intr(vcpu);
8834 fastpath_t exit_fastpath;
8835
8836 bool req_immediate_exit = false;
8837
8838 /* Forbid vmenter if vcpu dirty ring is soft-full */
8839 if (unlikely(vcpu->kvm->dirty_ring_size &&
8840 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
8841 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
8842 trace_kvm_dirty_ring_exit(vcpu);
8843 r = 0;
8844 goto out;
8845 }
8846
8847 if (kvm_request_pending(vcpu)) {
8848 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8849 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8850 r = 0;
8851 goto out;
8852 }
8853 }
8854 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8855 kvm_mmu_unload(vcpu);
8856 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8857 __kvm_migrate_timers(vcpu);
8858 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8859 kvm_gen_update_masterclock(vcpu->kvm);
8860 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8861 kvm_gen_kvmclock_update(vcpu);
8862 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8863 r = kvm_guest_time_update(vcpu);
8864 if (unlikely(r))
8865 goto out;
8866 }
8867 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8868 kvm_mmu_sync_roots(vcpu);
8869 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8870 kvm_mmu_load_pgd(vcpu);
8871 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8872 kvm_vcpu_flush_tlb_all(vcpu);
8873
8874 /* Flushing all ASIDs flushes the current ASID... */
8875 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8876 }
8877 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8878 kvm_vcpu_flush_tlb_current(vcpu);
8879 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8880 kvm_vcpu_flush_tlb_guest(vcpu);
8881
8882 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8883 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8884 r = 0;
8885 goto out;
8886 }
8887 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8888 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8889 vcpu->mmio_needed = 0;
8890 r = 0;
8891 goto out;
8892 }
8893 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8894 /* Page is swapped out. Do synthetic halt */
8895 vcpu->arch.apf.halted = true;
8896 r = 1;
8897 goto out;
8898 }
8899 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8900 record_steal_time(vcpu);
8901 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8902 process_smi(vcpu);
8903 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8904 process_nmi(vcpu);
8905 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8906 kvm_pmu_handle_event(vcpu);
8907 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8908 kvm_pmu_deliver_pmi(vcpu);
8909 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8910 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8911 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8912 vcpu->arch.ioapic_handled_vectors)) {
8913 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8914 vcpu->run->eoi.vector =
8915 vcpu->arch.pending_ioapic_eoi;
8916 r = 0;
8917 goto out;
8918 }
8919 }
8920 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8921 vcpu_scan_ioapic(vcpu);
8922 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8923 vcpu_load_eoi_exitmap(vcpu);
8924 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8925 kvm_vcpu_reload_apic_access_page(vcpu);
8926 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8927 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8928 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8929 r = 0;
8930 goto out;
8931 }
8932 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8933 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8934 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8935 r = 0;
8936 goto out;
8937 }
8938 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8939 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8940 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8941 r = 0;
8942 goto out;
8943 }
8944
8945 /*
8946 * KVM_REQ_HV_STIMER has to be processed after
8947 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8948 * depend on the guest clock being up-to-date
8949 */
8950 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8951 kvm_hv_process_stimers(vcpu);
8952 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8953 kvm_vcpu_update_apicv(vcpu);
8954 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8955 kvm_check_async_pf_completion(vcpu);
8956 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8957 static_call(kvm_x86_msr_filter_changed)(vcpu);
8958 }
8959
8960 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8961 ++vcpu->stat.req_event;
8962 kvm_apic_accept_events(vcpu);
8963 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8964 r = 1;
8965 goto out;
8966 }
8967
8968 inject_pending_event(vcpu, &req_immediate_exit);
8969 if (req_int_win)
8970 static_call(kvm_x86_enable_irq_window)(vcpu);
8971
8972 if (kvm_lapic_enabled(vcpu)) {
8973 update_cr8_intercept(vcpu);
8974 kvm_lapic_sync_to_vapic(vcpu);
8975 }
8976 }
8977
8978 r = kvm_mmu_reload(vcpu);
8979 if (unlikely(r)) {
8980 goto cancel_injection;
8981 }
8982
8983 preempt_disable();
8984
8985 static_call(kvm_x86_prepare_guest_switch)(vcpu);
8986
8987 /*
8988 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8989 * IPI are then delayed after guest entry, which ensures that they
8990 * result in virtual interrupt delivery.
8991 */
8992 local_irq_disable();
8993 vcpu->mode = IN_GUEST_MODE;
8994
8995 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8996
8997 /*
8998 * 1) We should set ->mode before checking ->requests. Please see
8999 * the comment in kvm_vcpu_exiting_guest_mode().
9000 *
9001 * 2) For APICv, we should set ->mode before checking PID.ON. This
9002 * pairs with the memory barrier implicit in pi_test_and_set_on
9003 * (see vmx_deliver_posted_interrupt).
9004 *
9005 * 3) This also orders the write to mode from any reads to the page
9006 * tables done while the VCPU is running. Please see the comment
9007 * in kvm_flush_remote_tlbs.
9008 */
9009 smp_mb__after_srcu_read_unlock();
9010
9011 /*
9012 * This handles the case where a posted interrupt was
9013 * notified with kvm_vcpu_kick.
9014 */
9015 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
9016 static_call(kvm_x86_sync_pir_to_irr)(vcpu);
9017
9018 if (kvm_vcpu_exit_request(vcpu)) {
9019 vcpu->mode = OUTSIDE_GUEST_MODE;
9020 smp_wmb();
9021 local_irq_enable();
9022 preempt_enable();
9023 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9024 r = 1;
9025 goto cancel_injection;
9026 }
9027
9028 if (req_immediate_exit) {
9029 kvm_make_request(KVM_REQ_EVENT, vcpu);
9030 static_call(kvm_x86_request_immediate_exit)(vcpu);
9031 }
9032
9033 fpregs_assert_state_consistent();
9034 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9035 switch_fpu_return();
9036
9037 if (unlikely(vcpu->arch.switch_db_regs)) {
9038 set_debugreg(0, 7);
9039 set_debugreg(vcpu->arch.eff_db[0], 0);
9040 set_debugreg(vcpu->arch.eff_db[1], 1);
9041 set_debugreg(vcpu->arch.eff_db[2], 2);
9042 set_debugreg(vcpu->arch.eff_db[3], 3);
9043 set_debugreg(vcpu->arch.dr6, 6);
9044 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9045 }
9046
9047 for (;;) {
9048 exit_fastpath = static_call(kvm_x86_run)(vcpu);
9049 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
9050 break;
9051
9052 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
9053 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
9054 break;
9055 }
9056
9057 if (vcpu->arch.apicv_active)
9058 static_call(kvm_x86_sync_pir_to_irr)(vcpu);
9059 }
9060
9061 /*
9062 * Do this here before restoring debug registers on the host. And
9063 * since we do this before handling the vmexit, a DR access vmexit
9064 * can (a) read the correct value of the debug registers, (b) set
9065 * KVM_DEBUGREG_WONT_EXIT again.
9066 */
9067 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
9068 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
9069 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
9070 kvm_update_dr0123(vcpu);
9071 kvm_update_dr7(vcpu);
9072 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9073 }
9074
9075 /*
9076 * If the guest has used debug registers, at least dr7
9077 * will be disabled while returning to the host.
9078 * If we don't have active breakpoints in the host, we don't
9079 * care about the messed up debug address registers. But if
9080 * we have some of them active, restore the old state.
9081 */
9082 if (hw_breakpoint_active())
9083 hw_breakpoint_restore();
9084
9085 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
9086 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
9087
9088 vcpu->mode = OUTSIDE_GUEST_MODE;
9089 smp_wmb();
9090
9091 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
9092
9093 /*
9094 * Consume any pending interrupts, including the possible source of
9095 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
9096 * An instruction is required after local_irq_enable() to fully unblock
9097 * interrupts on processors that implement an interrupt shadow, the
9098 * stat.exits increment will do nicely.
9099 */
9100 kvm_before_interrupt(vcpu);
9101 local_irq_enable();
9102 ++vcpu->stat.exits;
9103 local_irq_disable();
9104 kvm_after_interrupt(vcpu);
9105
9106 if (lapic_in_kernel(vcpu)) {
9107 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
9108 if (delta != S64_MIN) {
9109 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
9110 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
9111 }
9112 }
9113
9114 local_irq_enable();
9115 preempt_enable();
9116
9117 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9118
9119 /*
9120 * Profile KVM exit RIPs:
9121 */
9122 if (unlikely(prof_on == KVM_PROFILING)) {
9123 unsigned long rip = kvm_rip_read(vcpu);
9124 profile_hit(KVM_PROFILING, (void *)rip);
9125 }
9126
9127 if (unlikely(vcpu->arch.tsc_always_catchup))
9128 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9129
9130 if (vcpu->arch.apic_attention)
9131 kvm_lapic_sync_from_vapic(vcpu);
9132
9133 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
9134 return r;
9135
9136 cancel_injection:
9137 if (req_immediate_exit)
9138 kvm_make_request(KVM_REQ_EVENT, vcpu);
9139 static_call(kvm_x86_cancel_injection)(vcpu);
9140 if (unlikely(vcpu->arch.apic_attention))
9141 kvm_lapic_sync_from_vapic(vcpu);
9142 out:
9143 return r;
9144 }
9145
9146 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
9147 {
9148 if (!kvm_arch_vcpu_runnable(vcpu) &&
9149 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) {
9150 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9151 kvm_vcpu_block(vcpu);
9152 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9153
9154 if (kvm_x86_ops.post_block)
9155 static_call(kvm_x86_post_block)(vcpu);
9156
9157 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
9158 return 1;
9159 }
9160
9161 kvm_apic_accept_events(vcpu);
9162 switch(vcpu->arch.mp_state) {
9163 case KVM_MP_STATE_HALTED:
9164 case KVM_MP_STATE_AP_RESET_HOLD:
9165 vcpu->arch.pv.pv_unhalted = false;
9166 vcpu->arch.mp_state =
9167 KVM_MP_STATE_RUNNABLE;
9168 fallthrough;
9169 case KVM_MP_STATE_RUNNABLE:
9170 vcpu->arch.apf.halted = false;
9171 break;
9172 case KVM_MP_STATE_INIT_RECEIVED:
9173 break;
9174 default:
9175 return -EINTR;
9176 }
9177 return 1;
9178 }
9179
9180 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
9181 {
9182 if (is_guest_mode(vcpu))
9183 kvm_x86_ops.nested_ops->check_events(vcpu);
9184
9185 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
9186 !vcpu->arch.apf.halted);
9187 }
9188
9189 static int vcpu_run(struct kvm_vcpu *vcpu)
9190 {
9191 int r;
9192 struct kvm *kvm = vcpu->kvm;
9193
9194 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9195 vcpu->arch.l1tf_flush_l1d = true;
9196
9197 for (;;) {
9198 if (kvm_vcpu_running(vcpu)) {
9199 r = vcpu_enter_guest(vcpu);
9200 } else {
9201 r = vcpu_block(kvm, vcpu);
9202 }
9203
9204 if (r <= 0)
9205 break;
9206
9207 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
9208 if (kvm_cpu_has_pending_timer(vcpu))
9209 kvm_inject_pending_timer_irqs(vcpu);
9210
9211 if (dm_request_for_irq_injection(vcpu) &&
9212 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9213 r = 0;
9214 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9215 ++vcpu->stat.request_irq_exits;
9216 break;
9217 }
9218
9219 if (__xfer_to_guest_mode_work_pending()) {
9220 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9221 r = xfer_to_guest_mode_handle_work(vcpu);
9222 if (r)
9223 return r;
9224 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9225 }
9226 }
9227
9228 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9229
9230 return r;
9231 }
9232
9233 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9234 {
9235 int r;
9236
9237 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9238 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9239 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9240 return r;
9241 }
9242
9243 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9244 {
9245 BUG_ON(!vcpu->arch.pio.count);
9246
9247 return complete_emulated_io(vcpu);
9248 }
9249
9250 /*
9251 * Implements the following, as a state machine:
9252 *
9253 * read:
9254 * for each fragment
9255 * for each mmio piece in the fragment
9256 * write gpa, len
9257 * exit
9258 * copy data
9259 * execute insn
9260 *
9261 * write:
9262 * for each fragment
9263 * for each mmio piece in the fragment
9264 * write gpa, len
9265 * copy data
9266 * exit
9267 */
9268 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9269 {
9270 struct kvm_run *run = vcpu->run;
9271 struct kvm_mmio_fragment *frag;
9272 unsigned len;
9273
9274 BUG_ON(!vcpu->mmio_needed);
9275
9276 /* Complete previous fragment */
9277 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9278 len = min(8u, frag->len);
9279 if (!vcpu->mmio_is_write)
9280 memcpy(frag->data, run->mmio.data, len);
9281
9282 if (frag->len <= 8) {
9283 /* Switch to the next fragment. */
9284 frag++;
9285 vcpu->mmio_cur_fragment++;
9286 } else {
9287 /* Go forward to the next mmio piece. */
9288 frag->data += len;
9289 frag->gpa += len;
9290 frag->len -= len;
9291 }
9292
9293 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9294 vcpu->mmio_needed = 0;
9295
9296 /* FIXME: return into emulator if single-stepping. */
9297 if (vcpu->mmio_is_write)
9298 return 1;
9299 vcpu->mmio_read_completed = 1;
9300 return complete_emulated_io(vcpu);
9301 }
9302
9303 run->exit_reason = KVM_EXIT_MMIO;
9304 run->mmio.phys_addr = frag->gpa;
9305 if (vcpu->mmio_is_write)
9306 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9307 run->mmio.len = min(8u, frag->len);
9308 run->mmio.is_write = vcpu->mmio_is_write;
9309 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9310 return 0;
9311 }
9312
9313 static void kvm_save_current_fpu(struct fpu *fpu)
9314 {
9315 /*
9316 * If the target FPU state is not resident in the CPU registers, just
9317 * memcpy() from current, else save CPU state directly to the target.
9318 */
9319 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9320 memcpy(&fpu->state, &current->thread.fpu.state,
9321 fpu_kernel_xstate_size);
9322 else
9323 copy_fpregs_to_fpstate(fpu);
9324 }
9325
9326 /* Swap (qemu) user FPU context for the guest FPU context. */
9327 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9328 {
9329 fpregs_lock();
9330
9331 kvm_save_current_fpu(vcpu->arch.user_fpu);
9332
9333 /*
9334 * Guests with protected state can't have it set by the hypervisor,
9335 * so skip trying to set it.
9336 */
9337 if (vcpu->arch.guest_fpu)
9338 /* PKRU is separately restored in kvm_x86_ops.run. */
9339 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9340 ~XFEATURE_MASK_PKRU);
9341
9342 fpregs_mark_activate();
9343 fpregs_unlock();
9344
9345 trace_kvm_fpu(1);
9346 }
9347
9348 /* When vcpu_run ends, restore user space FPU context. */
9349 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9350 {
9351 fpregs_lock();
9352
9353 /*
9354 * Guests with protected state can't have it read by the hypervisor,
9355 * so skip trying to save it.
9356 */
9357 if (vcpu->arch.guest_fpu)
9358 kvm_save_current_fpu(vcpu->arch.guest_fpu);
9359
9360 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9361
9362 fpregs_mark_activate();
9363 fpregs_unlock();
9364
9365 ++vcpu->stat.fpu_reload;
9366 trace_kvm_fpu(0);
9367 }
9368
9369 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9370 {
9371 struct kvm_run *kvm_run = vcpu->run;
9372 int r;
9373
9374 vcpu_load(vcpu);
9375 kvm_sigset_activate(vcpu);
9376 kvm_run->flags = 0;
9377 kvm_load_guest_fpu(vcpu);
9378
9379 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9380 if (kvm_run->immediate_exit) {
9381 r = -EINTR;
9382 goto out;
9383 }
9384 kvm_vcpu_block(vcpu);
9385 kvm_apic_accept_events(vcpu);
9386 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9387 r = -EAGAIN;
9388 if (signal_pending(current)) {
9389 r = -EINTR;
9390 kvm_run->exit_reason = KVM_EXIT_INTR;
9391 ++vcpu->stat.signal_exits;
9392 }
9393 goto out;
9394 }
9395
9396 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9397 r = -EINVAL;
9398 goto out;
9399 }
9400
9401 if (kvm_run->kvm_dirty_regs) {
9402 r = sync_regs(vcpu);
9403 if (r != 0)
9404 goto out;
9405 }
9406
9407 /* re-sync apic's tpr */
9408 if (!lapic_in_kernel(vcpu)) {
9409 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9410 r = -EINVAL;
9411 goto out;
9412 }
9413 }
9414
9415 if (unlikely(vcpu->arch.complete_userspace_io)) {
9416 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9417 vcpu->arch.complete_userspace_io = NULL;
9418 r = cui(vcpu);
9419 if (r <= 0)
9420 goto out;
9421 } else
9422 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9423
9424 if (kvm_run->immediate_exit)
9425 r = -EINTR;
9426 else
9427 r = vcpu_run(vcpu);
9428
9429 out:
9430 kvm_put_guest_fpu(vcpu);
9431 if (kvm_run->kvm_valid_regs)
9432 store_regs(vcpu);
9433 post_kvm_run_save(vcpu);
9434 kvm_sigset_deactivate(vcpu);
9435
9436 vcpu_put(vcpu);
9437 return r;
9438 }
9439
9440 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9441 {
9442 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9443 /*
9444 * We are here if userspace calls get_regs() in the middle of
9445 * instruction emulation. Registers state needs to be copied
9446 * back from emulation context to vcpu. Userspace shouldn't do
9447 * that usually, but some bad designed PV devices (vmware
9448 * backdoor interface) need this to work
9449 */
9450 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9451 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9452 }
9453 regs->rax = kvm_rax_read(vcpu);
9454 regs->rbx = kvm_rbx_read(vcpu);
9455 regs->rcx = kvm_rcx_read(vcpu);
9456 regs->rdx = kvm_rdx_read(vcpu);
9457 regs->rsi = kvm_rsi_read(vcpu);
9458 regs->rdi = kvm_rdi_read(vcpu);
9459 regs->rsp = kvm_rsp_read(vcpu);
9460 regs->rbp = kvm_rbp_read(vcpu);
9461 #ifdef CONFIG_X86_64
9462 regs->r8 = kvm_r8_read(vcpu);
9463 regs->r9 = kvm_r9_read(vcpu);
9464 regs->r10 = kvm_r10_read(vcpu);
9465 regs->r11 = kvm_r11_read(vcpu);
9466 regs->r12 = kvm_r12_read(vcpu);
9467 regs->r13 = kvm_r13_read(vcpu);
9468 regs->r14 = kvm_r14_read(vcpu);
9469 regs->r15 = kvm_r15_read(vcpu);
9470 #endif
9471
9472 regs->rip = kvm_rip_read(vcpu);
9473 regs->rflags = kvm_get_rflags(vcpu);
9474 }
9475
9476 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9477 {
9478 vcpu_load(vcpu);
9479 __get_regs(vcpu, regs);
9480 vcpu_put(vcpu);
9481 return 0;
9482 }
9483
9484 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9485 {
9486 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9487 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9488
9489 kvm_rax_write(vcpu, regs->rax);
9490 kvm_rbx_write(vcpu, regs->rbx);
9491 kvm_rcx_write(vcpu, regs->rcx);
9492 kvm_rdx_write(vcpu, regs->rdx);
9493 kvm_rsi_write(vcpu, regs->rsi);
9494 kvm_rdi_write(vcpu, regs->rdi);
9495 kvm_rsp_write(vcpu, regs->rsp);
9496 kvm_rbp_write(vcpu, regs->rbp);
9497 #ifdef CONFIG_X86_64
9498 kvm_r8_write(vcpu, regs->r8);
9499 kvm_r9_write(vcpu, regs->r9);
9500 kvm_r10_write(vcpu, regs->r10);
9501 kvm_r11_write(vcpu, regs->r11);
9502 kvm_r12_write(vcpu, regs->r12);
9503 kvm_r13_write(vcpu, regs->r13);
9504 kvm_r14_write(vcpu, regs->r14);
9505 kvm_r15_write(vcpu, regs->r15);
9506 #endif
9507
9508 kvm_rip_write(vcpu, regs->rip);
9509 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9510
9511 vcpu->arch.exception.pending = false;
9512
9513 kvm_make_request(KVM_REQ_EVENT, vcpu);
9514 }
9515
9516 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9517 {
9518 vcpu_load(vcpu);
9519 __set_regs(vcpu, regs);
9520 vcpu_put(vcpu);
9521 return 0;
9522 }
9523
9524 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9525 {
9526 struct kvm_segment cs;
9527
9528 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9529 *db = cs.db;
9530 *l = cs.l;
9531 }
9532 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9533
9534 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9535 {
9536 struct desc_ptr dt;
9537
9538 if (vcpu->arch.guest_state_protected)
9539 goto skip_protected_regs;
9540
9541 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9542 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9543 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9544 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9545 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9546 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9547
9548 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9549 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9550
9551 static_call(kvm_x86_get_idt)(vcpu, &dt);
9552 sregs->idt.limit = dt.size;
9553 sregs->idt.base = dt.address;
9554 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9555 sregs->gdt.limit = dt.size;
9556 sregs->gdt.base = dt.address;
9557
9558 sregs->cr2 = vcpu->arch.cr2;
9559 sregs->cr3 = kvm_read_cr3(vcpu);
9560
9561 skip_protected_regs:
9562 sregs->cr0 = kvm_read_cr0(vcpu);
9563 sregs->cr4 = kvm_read_cr4(vcpu);
9564 sregs->cr8 = kvm_get_cr8(vcpu);
9565 sregs->efer = vcpu->arch.efer;
9566 sregs->apic_base = kvm_get_apic_base(vcpu);
9567
9568 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9569
9570 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9571 set_bit(vcpu->arch.interrupt.nr,
9572 (unsigned long *)sregs->interrupt_bitmap);
9573 }
9574
9575 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9576 struct kvm_sregs *sregs)
9577 {
9578 vcpu_load(vcpu);
9579 __get_sregs(vcpu, sregs);
9580 vcpu_put(vcpu);
9581 return 0;
9582 }
9583
9584 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9585 struct kvm_mp_state *mp_state)
9586 {
9587 vcpu_load(vcpu);
9588 if (kvm_mpx_supported())
9589 kvm_load_guest_fpu(vcpu);
9590
9591 kvm_apic_accept_events(vcpu);
9592 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
9593 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
9594 vcpu->arch.pv.pv_unhalted)
9595 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9596 else
9597 mp_state->mp_state = vcpu->arch.mp_state;
9598
9599 if (kvm_mpx_supported())
9600 kvm_put_guest_fpu(vcpu);
9601 vcpu_put(vcpu);
9602 return 0;
9603 }
9604
9605 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9606 struct kvm_mp_state *mp_state)
9607 {
9608 int ret = -EINVAL;
9609
9610 vcpu_load(vcpu);
9611
9612 if (!lapic_in_kernel(vcpu) &&
9613 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9614 goto out;
9615
9616 /*
9617 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9618 * INIT state; latched init should be reported using
9619 * KVM_SET_VCPU_EVENTS, so reject it here.
9620 */
9621 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9622 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9623 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9624 goto out;
9625
9626 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9627 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9628 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9629 } else
9630 vcpu->arch.mp_state = mp_state->mp_state;
9631 kvm_make_request(KVM_REQ_EVENT, vcpu);
9632
9633 ret = 0;
9634 out:
9635 vcpu_put(vcpu);
9636 return ret;
9637 }
9638
9639 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9640 int reason, bool has_error_code, u32 error_code)
9641 {
9642 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9643 int ret;
9644
9645 init_emulate_ctxt(vcpu);
9646
9647 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9648 has_error_code, error_code);
9649 if (ret) {
9650 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9651 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9652 vcpu->run->internal.ndata = 0;
9653 return 0;
9654 }
9655
9656 kvm_rip_write(vcpu, ctxt->eip);
9657 kvm_set_rflags(vcpu, ctxt->eflags);
9658 return 1;
9659 }
9660 EXPORT_SYMBOL_GPL(kvm_task_switch);
9661
9662 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9663 {
9664 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9665 /*
9666 * When EFER.LME and CR0.PG are set, the processor is in
9667 * 64-bit mode (though maybe in a 32-bit code segment).
9668 * CR4.PAE and EFER.LMA must be set.
9669 */
9670 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
9671 return false;
9672 if (sregs->cr3 & vcpu->arch.cr3_lm_rsvd_bits)
9673 return false;
9674 } else {
9675 /*
9676 * Not in 64-bit mode: EFER.LMA is clear and the code
9677 * segment cannot be 64-bit.
9678 */
9679 if (sregs->efer & EFER_LMA || sregs->cs.l)
9680 return false;
9681 }
9682
9683 return kvm_is_valid_cr4(vcpu, sregs->cr4);
9684 }
9685
9686 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9687 {
9688 struct msr_data apic_base_msr;
9689 int mmu_reset_needed = 0;
9690 int pending_vec, max_bits, idx;
9691 struct desc_ptr dt;
9692 int ret = -EINVAL;
9693
9694 if (!kvm_is_valid_sregs(vcpu, sregs))
9695 goto out;
9696
9697 apic_base_msr.data = sregs->apic_base;
9698 apic_base_msr.host_initiated = true;
9699 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9700 goto out;
9701
9702 if (vcpu->arch.guest_state_protected)
9703 goto skip_protected_regs;
9704
9705 dt.size = sregs->idt.limit;
9706 dt.address = sregs->idt.base;
9707 static_call(kvm_x86_set_idt)(vcpu, &dt);
9708 dt.size = sregs->gdt.limit;
9709 dt.address = sregs->gdt.base;
9710 static_call(kvm_x86_set_gdt)(vcpu, &dt);
9711
9712 vcpu->arch.cr2 = sregs->cr2;
9713 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9714 vcpu->arch.cr3 = sregs->cr3;
9715 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9716
9717 kvm_set_cr8(vcpu, sregs->cr8);
9718
9719 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9720 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
9721
9722 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9723 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
9724 vcpu->arch.cr0 = sregs->cr0;
9725
9726 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9727 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
9728
9729 idx = srcu_read_lock(&vcpu->kvm->srcu);
9730 if (is_pae_paging(vcpu)) {
9731 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9732 mmu_reset_needed = 1;
9733 }
9734 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9735
9736 if (mmu_reset_needed)
9737 kvm_mmu_reset_context(vcpu);
9738
9739 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9740 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9741 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9742 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9743 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9744 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9745
9746 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9747 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9748
9749 update_cr8_intercept(vcpu);
9750
9751 /* Older userspace won't unhalt the vcpu on reset. */
9752 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9753 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9754 !is_protmode(vcpu))
9755 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9756
9757 skip_protected_regs:
9758 max_bits = KVM_NR_INTERRUPTS;
9759 pending_vec = find_first_bit(
9760 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9761 if (pending_vec < max_bits) {
9762 kvm_queue_interrupt(vcpu, pending_vec, false);
9763 pr_debug("Set back pending irq %d\n", pending_vec);
9764 }
9765
9766 kvm_make_request(KVM_REQ_EVENT, vcpu);
9767
9768 ret = 0;
9769 out:
9770 return ret;
9771 }
9772
9773 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9774 struct kvm_sregs *sregs)
9775 {
9776 int ret;
9777
9778 vcpu_load(vcpu);
9779 ret = __set_sregs(vcpu, sregs);
9780 vcpu_put(vcpu);
9781 return ret;
9782 }
9783
9784 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9785 struct kvm_guest_debug *dbg)
9786 {
9787 unsigned long rflags;
9788 int i, r;
9789
9790 if (vcpu->arch.guest_state_protected)
9791 return -EINVAL;
9792
9793 vcpu_load(vcpu);
9794
9795 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9796 r = -EBUSY;
9797 if (vcpu->arch.exception.pending)
9798 goto out;
9799 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9800 kvm_queue_exception(vcpu, DB_VECTOR);
9801 else
9802 kvm_queue_exception(vcpu, BP_VECTOR);
9803 }
9804
9805 /*
9806 * Read rflags as long as potentially injected trace flags are still
9807 * filtered out.
9808 */
9809 rflags = kvm_get_rflags(vcpu);
9810
9811 vcpu->guest_debug = dbg->control;
9812 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9813 vcpu->guest_debug = 0;
9814
9815 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9816 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9817 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9818 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9819 } else {
9820 for (i = 0; i < KVM_NR_DB_REGS; i++)
9821 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9822 }
9823 kvm_update_dr7(vcpu);
9824
9825 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9826 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9827 get_segment_base(vcpu, VCPU_SREG_CS);
9828
9829 /*
9830 * Trigger an rflags update that will inject or remove the trace
9831 * flags.
9832 */
9833 kvm_set_rflags(vcpu, rflags);
9834
9835 static_call(kvm_x86_update_exception_bitmap)(vcpu);
9836
9837 r = 0;
9838
9839 out:
9840 vcpu_put(vcpu);
9841 return r;
9842 }
9843
9844 /*
9845 * Translate a guest virtual address to a guest physical address.
9846 */
9847 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9848 struct kvm_translation *tr)
9849 {
9850 unsigned long vaddr = tr->linear_address;
9851 gpa_t gpa;
9852 int idx;
9853
9854 vcpu_load(vcpu);
9855
9856 idx = srcu_read_lock(&vcpu->kvm->srcu);
9857 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9858 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9859 tr->physical_address = gpa;
9860 tr->valid = gpa != UNMAPPED_GVA;
9861 tr->writeable = 1;
9862 tr->usermode = 0;
9863
9864 vcpu_put(vcpu);
9865 return 0;
9866 }
9867
9868 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9869 {
9870 struct fxregs_state *fxsave;
9871
9872 if (!vcpu->arch.guest_fpu)
9873 return 0;
9874
9875 vcpu_load(vcpu);
9876
9877 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9878 memcpy(fpu->fpr, fxsave->st_space, 128);
9879 fpu->fcw = fxsave->cwd;
9880 fpu->fsw = fxsave->swd;
9881 fpu->ftwx = fxsave->twd;
9882 fpu->last_opcode = fxsave->fop;
9883 fpu->last_ip = fxsave->rip;
9884 fpu->last_dp = fxsave->rdp;
9885 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9886
9887 vcpu_put(vcpu);
9888 return 0;
9889 }
9890
9891 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9892 {
9893 struct fxregs_state *fxsave;
9894
9895 if (!vcpu->arch.guest_fpu)
9896 return 0;
9897
9898 vcpu_load(vcpu);
9899
9900 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9901
9902 memcpy(fxsave->st_space, fpu->fpr, 128);
9903 fxsave->cwd = fpu->fcw;
9904 fxsave->swd = fpu->fsw;
9905 fxsave->twd = fpu->ftwx;
9906 fxsave->fop = fpu->last_opcode;
9907 fxsave->rip = fpu->last_ip;
9908 fxsave->rdp = fpu->last_dp;
9909 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9910
9911 vcpu_put(vcpu);
9912 return 0;
9913 }
9914
9915 static void store_regs(struct kvm_vcpu *vcpu)
9916 {
9917 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9918
9919 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9920 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9921
9922 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9923 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9924
9925 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9926 kvm_vcpu_ioctl_x86_get_vcpu_events(
9927 vcpu, &vcpu->run->s.regs.events);
9928 }
9929
9930 static int sync_regs(struct kvm_vcpu *vcpu)
9931 {
9932 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9933 return -EINVAL;
9934
9935 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9936 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9937 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9938 }
9939 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9940 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9941 return -EINVAL;
9942 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9943 }
9944 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9945 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9946 vcpu, &vcpu->run->s.regs.events))
9947 return -EINVAL;
9948 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9949 }
9950
9951 return 0;
9952 }
9953
9954 static void fx_init(struct kvm_vcpu *vcpu)
9955 {
9956 if (!vcpu->arch.guest_fpu)
9957 return;
9958
9959 fpstate_init(&vcpu->arch.guest_fpu->state);
9960 if (boot_cpu_has(X86_FEATURE_XSAVES))
9961 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9962 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9963
9964 /*
9965 * Ensure guest xcr0 is valid for loading
9966 */
9967 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9968
9969 vcpu->arch.cr0 |= X86_CR0_ET;
9970 }
9971
9972 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu)
9973 {
9974 if (vcpu->arch.guest_fpu) {
9975 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9976 vcpu->arch.guest_fpu = NULL;
9977 }
9978 }
9979 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu);
9980
9981 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9982 {
9983 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9984 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9985 "guest TSC will not be reliable\n");
9986
9987 return 0;
9988 }
9989
9990 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9991 {
9992 struct page *page;
9993 int r;
9994
9995 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9996 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9997 else
9998 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9999
10000 kvm_set_tsc_khz(vcpu, max_tsc_khz);
10001
10002 r = kvm_mmu_create(vcpu);
10003 if (r < 0)
10004 return r;
10005
10006 if (irqchip_in_kernel(vcpu->kvm)) {
10007 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
10008 if (r < 0)
10009 goto fail_mmu_destroy;
10010 if (kvm_apicv_activated(vcpu->kvm))
10011 vcpu->arch.apicv_active = true;
10012 } else
10013 static_branch_inc(&kvm_has_noapic_vcpu);
10014
10015 r = -ENOMEM;
10016
10017 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
10018 if (!page)
10019 goto fail_free_lapic;
10020 vcpu->arch.pio_data = page_address(page);
10021
10022 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
10023 GFP_KERNEL_ACCOUNT);
10024 if (!vcpu->arch.mce_banks)
10025 goto fail_free_pio_data;
10026 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
10027
10028 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
10029 GFP_KERNEL_ACCOUNT))
10030 goto fail_free_mce_banks;
10031
10032 if (!alloc_emulate_ctxt(vcpu))
10033 goto free_wbinvd_dirty_mask;
10034
10035 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
10036 GFP_KERNEL_ACCOUNT);
10037 if (!vcpu->arch.user_fpu) {
10038 pr_err("kvm: failed to allocate userspace's fpu\n");
10039 goto free_emulate_ctxt;
10040 }
10041
10042 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
10043 GFP_KERNEL_ACCOUNT);
10044 if (!vcpu->arch.guest_fpu) {
10045 pr_err("kvm: failed to allocate vcpu's fpu\n");
10046 goto free_user_fpu;
10047 }
10048 fx_init(vcpu);
10049
10050 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
10051
10052 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
10053
10054 kvm_async_pf_hash_reset(vcpu);
10055 kvm_pmu_init(vcpu);
10056
10057 vcpu->arch.pending_external_vector = -1;
10058 vcpu->arch.preempted_in_kernel = false;
10059
10060 kvm_hv_vcpu_init(vcpu);
10061
10062 r = static_call(kvm_x86_vcpu_create)(vcpu);
10063 if (r)
10064 goto free_guest_fpu;
10065
10066 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
10067 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
10068 kvm_vcpu_mtrr_init(vcpu);
10069 vcpu_load(vcpu);
10070 kvm_vcpu_reset(vcpu, false);
10071 kvm_init_mmu(vcpu, false);
10072 vcpu_put(vcpu);
10073 return 0;
10074
10075 free_guest_fpu:
10076 kvm_free_guest_fpu(vcpu);
10077 free_user_fpu:
10078 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10079 free_emulate_ctxt:
10080 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10081 free_wbinvd_dirty_mask:
10082 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10083 fail_free_mce_banks:
10084 kfree(vcpu->arch.mce_banks);
10085 fail_free_pio_data:
10086 free_page((unsigned long)vcpu->arch.pio_data);
10087 fail_free_lapic:
10088 kvm_free_lapic(vcpu);
10089 fail_mmu_destroy:
10090 kvm_mmu_destroy(vcpu);
10091 return r;
10092 }
10093
10094 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
10095 {
10096 struct kvm *kvm = vcpu->kvm;
10097
10098 kvm_hv_vcpu_postcreate(vcpu);
10099
10100 if (mutex_lock_killable(&vcpu->mutex))
10101 return;
10102 vcpu_load(vcpu);
10103 kvm_synchronize_tsc(vcpu, 0);
10104 vcpu_put(vcpu);
10105
10106 /* poll control enabled by default */
10107 vcpu->arch.msr_kvm_poll_control = 1;
10108
10109 mutex_unlock(&vcpu->mutex);
10110
10111 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
10112 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
10113 KVMCLOCK_SYNC_PERIOD);
10114 }
10115
10116 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
10117 {
10118 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
10119 int idx;
10120
10121 kvm_release_pfn(cache->pfn, cache->dirty, cache);
10122
10123 kvmclock_reset(vcpu);
10124
10125 static_call(kvm_x86_vcpu_free)(vcpu);
10126
10127 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10128 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10129 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10130 kvm_free_guest_fpu(vcpu);
10131
10132 kvm_hv_vcpu_uninit(vcpu);
10133 kvm_pmu_destroy(vcpu);
10134 kfree(vcpu->arch.mce_banks);
10135 kvm_free_lapic(vcpu);
10136 idx = srcu_read_lock(&vcpu->kvm->srcu);
10137 kvm_mmu_destroy(vcpu);
10138 srcu_read_unlock(&vcpu->kvm->srcu, idx);
10139 free_page((unsigned long)vcpu->arch.pio_data);
10140 kvfree(vcpu->arch.cpuid_entries);
10141 if (!lapic_in_kernel(vcpu))
10142 static_branch_dec(&kvm_has_noapic_vcpu);
10143 }
10144
10145 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
10146 {
10147 kvm_lapic_reset(vcpu, init_event);
10148
10149 vcpu->arch.hflags = 0;
10150
10151 vcpu->arch.smi_pending = 0;
10152 vcpu->arch.smi_count = 0;
10153 atomic_set(&vcpu->arch.nmi_queued, 0);
10154 vcpu->arch.nmi_pending = 0;
10155 vcpu->arch.nmi_injected = false;
10156 kvm_clear_interrupt_queue(vcpu);
10157 kvm_clear_exception_queue(vcpu);
10158
10159 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
10160 kvm_update_dr0123(vcpu);
10161 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
10162 vcpu->arch.dr7 = DR7_FIXED_1;
10163 kvm_update_dr7(vcpu);
10164
10165 vcpu->arch.cr2 = 0;
10166
10167 kvm_make_request(KVM_REQ_EVENT, vcpu);
10168 vcpu->arch.apf.msr_en_val = 0;
10169 vcpu->arch.apf.msr_int_val = 0;
10170 vcpu->arch.st.msr_val = 0;
10171
10172 kvmclock_reset(vcpu);
10173
10174 kvm_clear_async_pf_completion_queue(vcpu);
10175 kvm_async_pf_hash_reset(vcpu);
10176 vcpu->arch.apf.halted = false;
10177
10178 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) {
10179 void *mpx_state_buffer;
10180
10181 /*
10182 * To avoid have the INIT path from kvm_apic_has_events() that be
10183 * called with loaded FPU and does not let userspace fix the state.
10184 */
10185 if (init_event)
10186 kvm_put_guest_fpu(vcpu);
10187 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10188 XFEATURE_BNDREGS);
10189 if (mpx_state_buffer)
10190 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
10191 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10192 XFEATURE_BNDCSR);
10193 if (mpx_state_buffer)
10194 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
10195 if (init_event)
10196 kvm_load_guest_fpu(vcpu);
10197 }
10198
10199 if (!init_event) {
10200 kvm_pmu_reset(vcpu);
10201 vcpu->arch.smbase = 0x30000;
10202
10203 vcpu->arch.msr_misc_features_enables = 0;
10204
10205 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
10206 }
10207
10208 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
10209 vcpu->arch.regs_avail = ~0;
10210 vcpu->arch.regs_dirty = ~0;
10211
10212 vcpu->arch.ia32_xss = 0;
10213
10214 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
10215 }
10216
10217 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
10218 {
10219 struct kvm_segment cs;
10220
10221 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
10222 cs.selector = vector << 8;
10223 cs.base = vector << 12;
10224 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10225 kvm_rip_write(vcpu, 0);
10226 }
10227 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
10228
10229 int kvm_arch_hardware_enable(void)
10230 {
10231 struct kvm *kvm;
10232 struct kvm_vcpu *vcpu;
10233 int i;
10234 int ret;
10235 u64 local_tsc;
10236 u64 max_tsc = 0;
10237 bool stable, backwards_tsc = false;
10238
10239 kvm_user_return_msr_cpu_online();
10240 ret = static_call(kvm_x86_hardware_enable)();
10241 if (ret != 0)
10242 return ret;
10243
10244 local_tsc = rdtsc();
10245 stable = !kvm_check_tsc_unstable();
10246 list_for_each_entry(kvm, &vm_list, vm_list) {
10247 kvm_for_each_vcpu(i, vcpu, kvm) {
10248 if (!stable && vcpu->cpu == smp_processor_id())
10249 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10250 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10251 backwards_tsc = true;
10252 if (vcpu->arch.last_host_tsc > max_tsc)
10253 max_tsc = vcpu->arch.last_host_tsc;
10254 }
10255 }
10256 }
10257
10258 /*
10259 * Sometimes, even reliable TSCs go backwards. This happens on
10260 * platforms that reset TSC during suspend or hibernate actions, but
10261 * maintain synchronization. We must compensate. Fortunately, we can
10262 * detect that condition here, which happens early in CPU bringup,
10263 * before any KVM threads can be running. Unfortunately, we can't
10264 * bring the TSCs fully up to date with real time, as we aren't yet far
10265 * enough into CPU bringup that we know how much real time has actually
10266 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10267 * variables that haven't been updated yet.
10268 *
10269 * So we simply find the maximum observed TSC above, then record the
10270 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
10271 * the adjustment will be applied. Note that we accumulate
10272 * adjustments, in case multiple suspend cycles happen before some VCPU
10273 * gets a chance to run again. In the event that no KVM threads get a
10274 * chance to run, we will miss the entire elapsed period, as we'll have
10275 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10276 * loose cycle time. This isn't too big a deal, since the loss will be
10277 * uniform across all VCPUs (not to mention the scenario is extremely
10278 * unlikely). It is possible that a second hibernate recovery happens
10279 * much faster than a first, causing the observed TSC here to be
10280 * smaller; this would require additional padding adjustment, which is
10281 * why we set last_host_tsc to the local tsc observed here.
10282 *
10283 * N.B. - this code below runs only on platforms with reliable TSC,
10284 * as that is the only way backwards_tsc is set above. Also note
10285 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10286 * have the same delta_cyc adjustment applied if backwards_tsc
10287 * is detected. Note further, this adjustment is only done once,
10288 * as we reset last_host_tsc on all VCPUs to stop this from being
10289 * called multiple times (one for each physical CPU bringup).
10290 *
10291 * Platforms with unreliable TSCs don't have to deal with this, they
10292 * will be compensated by the logic in vcpu_load, which sets the TSC to
10293 * catchup mode. This will catchup all VCPUs to real time, but cannot
10294 * guarantee that they stay in perfect synchronization.
10295 */
10296 if (backwards_tsc) {
10297 u64 delta_cyc = max_tsc - local_tsc;
10298 list_for_each_entry(kvm, &vm_list, vm_list) {
10299 kvm->arch.backwards_tsc_observed = true;
10300 kvm_for_each_vcpu(i, vcpu, kvm) {
10301 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10302 vcpu->arch.last_host_tsc = local_tsc;
10303 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10304 }
10305
10306 /*
10307 * We have to disable TSC offset matching.. if you were
10308 * booting a VM while issuing an S4 host suspend....
10309 * you may have some problem. Solving this issue is
10310 * left as an exercise to the reader.
10311 */
10312 kvm->arch.last_tsc_nsec = 0;
10313 kvm->arch.last_tsc_write = 0;
10314 }
10315
10316 }
10317 return 0;
10318 }
10319
10320 void kvm_arch_hardware_disable(void)
10321 {
10322 static_call(kvm_x86_hardware_disable)();
10323 drop_user_return_notifiers();
10324 }
10325
10326 int kvm_arch_hardware_setup(void *opaque)
10327 {
10328 struct kvm_x86_init_ops *ops = opaque;
10329 int r;
10330
10331 rdmsrl_safe(MSR_EFER, &host_efer);
10332
10333 if (boot_cpu_has(X86_FEATURE_XSAVES))
10334 rdmsrl(MSR_IA32_XSS, host_xss);
10335
10336 r = ops->hardware_setup();
10337 if (r != 0)
10338 return r;
10339
10340 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10341 kvm_ops_static_call_update();
10342
10343 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10344 supported_xss = 0;
10345
10346 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10347 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10348 #undef __kvm_cpu_cap_has
10349
10350 if (kvm_has_tsc_control) {
10351 /*
10352 * Make sure the user can only configure tsc_khz values that
10353 * fit into a signed integer.
10354 * A min value is not calculated because it will always
10355 * be 1 on all machines.
10356 */
10357 u64 max = min(0x7fffffffULL,
10358 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10359 kvm_max_guest_tsc_khz = max;
10360
10361 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10362 }
10363
10364 kvm_init_msr_list();
10365 return 0;
10366 }
10367
10368 void kvm_arch_hardware_unsetup(void)
10369 {
10370 static_call(kvm_x86_hardware_unsetup)();
10371 }
10372
10373 int kvm_arch_check_processor_compat(void *opaque)
10374 {
10375 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10376 struct kvm_x86_init_ops *ops = opaque;
10377
10378 WARN_ON(!irqs_disabled());
10379
10380 if (__cr4_reserved_bits(cpu_has, c) !=
10381 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10382 return -EIO;
10383
10384 return ops->check_processor_compatibility();
10385 }
10386
10387 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10388 {
10389 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10390 }
10391 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10392
10393 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10394 {
10395 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10396 }
10397
10398 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
10399 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
10400
10401 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10402 {
10403 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10404
10405 vcpu->arch.l1tf_flush_l1d = true;
10406 if (pmu->version && unlikely(pmu->event_count)) {
10407 pmu->need_cleanup = true;
10408 kvm_make_request(KVM_REQ_PMU, vcpu);
10409 }
10410 static_call(kvm_x86_sched_in)(vcpu, cpu);
10411 }
10412
10413 void kvm_arch_free_vm(struct kvm *kvm)
10414 {
10415 kfree(kvm->arch.hyperv.hv_pa_pg);
10416 vfree(kvm);
10417 }
10418
10419
10420 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10421 {
10422 if (type)
10423 return -EINVAL;
10424
10425 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10426 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10427 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10428 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10429 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10430 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10431
10432 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10433 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10434 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10435 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10436 &kvm->arch.irq_sources_bitmap);
10437
10438 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10439 mutex_init(&kvm->arch.apic_map_lock);
10440 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10441
10442 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10443 pvclock_update_vm_gtod_copy(kvm);
10444
10445 kvm->arch.guest_can_read_msr_platform_info = true;
10446
10447 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10448 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10449
10450 kvm_hv_init_vm(kvm);
10451 kvm_page_track_init(kvm);
10452 kvm_mmu_init_vm(kvm);
10453
10454 return static_call(kvm_x86_vm_init)(kvm);
10455 }
10456
10457 int kvm_arch_post_init_vm(struct kvm *kvm)
10458 {
10459 return kvm_mmu_post_init_vm(kvm);
10460 }
10461
10462 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10463 {
10464 vcpu_load(vcpu);
10465 kvm_mmu_unload(vcpu);
10466 vcpu_put(vcpu);
10467 }
10468
10469 static void kvm_free_vcpus(struct kvm *kvm)
10470 {
10471 unsigned int i;
10472 struct kvm_vcpu *vcpu;
10473
10474 /*
10475 * Unpin any mmu pages first.
10476 */
10477 kvm_for_each_vcpu(i, vcpu, kvm) {
10478 kvm_clear_async_pf_completion_queue(vcpu);
10479 kvm_unload_vcpu_mmu(vcpu);
10480 }
10481 kvm_for_each_vcpu(i, vcpu, kvm)
10482 kvm_vcpu_destroy(vcpu);
10483
10484 mutex_lock(&kvm->lock);
10485 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10486 kvm->vcpus[i] = NULL;
10487
10488 atomic_set(&kvm->online_vcpus, 0);
10489 mutex_unlock(&kvm->lock);
10490 }
10491
10492 void kvm_arch_sync_events(struct kvm *kvm)
10493 {
10494 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10495 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10496 kvm_free_pit(kvm);
10497 }
10498
10499 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
10500
10501 /**
10502 * __x86_set_memory_region: Setup KVM internal memory slot
10503 *
10504 * @kvm: the kvm pointer to the VM.
10505 * @id: the slot ID to setup.
10506 * @gpa: the GPA to install the slot (unused when @size == 0).
10507 * @size: the size of the slot. Set to zero to uninstall a slot.
10508 *
10509 * This function helps to setup a KVM internal memory slot. Specify
10510 * @size > 0 to install a new slot, while @size == 0 to uninstall a
10511 * slot. The return code can be one of the following:
10512 *
10513 * HVA: on success (uninstall will return a bogus HVA)
10514 * -errno: on error
10515 *
10516 * The caller should always use IS_ERR() to check the return value
10517 * before use. Note, the KVM internal memory slots are guaranteed to
10518 * remain valid and unchanged until the VM is destroyed, i.e., the
10519 * GPA->HVA translation will not change. However, the HVA is a user
10520 * address, i.e. its accessibility is not guaranteed, and must be
10521 * accessed via __copy_{to,from}_user().
10522 */
10523 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
10524 u32 size)
10525 {
10526 int i, r;
10527 unsigned long hva, old_npages;
10528 struct kvm_memslots *slots = kvm_memslots(kvm);
10529 struct kvm_memory_slot *slot;
10530
10531 /* Called with kvm->slots_lock held. */
10532 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10533 return ERR_PTR_USR(-EINVAL);
10534
10535 slot = id_to_memslot(slots, id);
10536 if (size) {
10537 if (slot && slot->npages)
10538 return ERR_PTR_USR(-EEXIST);
10539
10540 /*
10541 * MAP_SHARED to prevent internal slot pages from being moved
10542 * by fork()/COW.
10543 */
10544 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10545 MAP_SHARED | MAP_ANONYMOUS, 0);
10546 if (IS_ERR((void *)hva))
10547 return (void __user *)hva;
10548 } else {
10549 if (!slot || !slot->npages)
10550 return 0;
10551
10552 old_npages = slot->npages;
10553 hva = slot->userspace_addr;
10554 }
10555
10556 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10557 struct kvm_userspace_memory_region m;
10558
10559 m.slot = id | (i << 16);
10560 m.flags = 0;
10561 m.guest_phys_addr = gpa;
10562 m.userspace_addr = hva;
10563 m.memory_size = size;
10564 r = __kvm_set_memory_region(kvm, &m);
10565 if (r < 0)
10566 return ERR_PTR_USR(r);
10567 }
10568
10569 if (!size)
10570 vm_munmap(hva, old_npages * PAGE_SIZE);
10571
10572 return (void __user *)hva;
10573 }
10574 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10575
10576 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10577 {
10578 kvm_mmu_pre_destroy_vm(kvm);
10579 }
10580
10581 void kvm_arch_destroy_vm(struct kvm *kvm)
10582 {
10583 u32 i;
10584
10585 if (current->mm == kvm->mm) {
10586 /*
10587 * Free memory regions allocated on behalf of userspace,
10588 * unless the the memory map has changed due to process exit
10589 * or fd copying.
10590 */
10591 mutex_lock(&kvm->slots_lock);
10592 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10593 0, 0);
10594 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10595 0, 0);
10596 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10597 mutex_unlock(&kvm->slots_lock);
10598 }
10599 static_call_cond(kvm_x86_vm_destroy)(kvm);
10600 for (i = 0; i < kvm->arch.msr_filter.count; i++)
10601 kfree(kvm->arch.msr_filter.ranges[i].bitmap);
10602 kvm_pic_destroy(kvm);
10603 kvm_ioapic_destroy(kvm);
10604 kvm_free_vcpus(kvm);
10605 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10606 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10607 kvm_mmu_uninit_vm(kvm);
10608 kvm_page_track_cleanup(kvm);
10609 kvm_hv_destroy_vm(kvm);
10610 }
10611
10612 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10613 {
10614 int i;
10615
10616 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10617 kvfree(slot->arch.rmap[i]);
10618 slot->arch.rmap[i] = NULL;
10619
10620 if (i == 0)
10621 continue;
10622
10623 kvfree(slot->arch.lpage_info[i - 1]);
10624 slot->arch.lpage_info[i - 1] = NULL;
10625 }
10626
10627 kvm_page_track_free_memslot(slot);
10628 }
10629
10630 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10631 unsigned long npages)
10632 {
10633 int i;
10634
10635 /*
10636 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10637 * old arrays will be freed by __kvm_set_memory_region() if installing
10638 * the new memslot is successful.
10639 */
10640 memset(&slot->arch, 0, sizeof(slot->arch));
10641
10642 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10643 struct kvm_lpage_info *linfo;
10644 unsigned long ugfn;
10645 int lpages;
10646 int level = i + 1;
10647
10648 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10649 slot->base_gfn, level) + 1;
10650
10651 slot->arch.rmap[i] =
10652 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10653 GFP_KERNEL_ACCOUNT);
10654 if (!slot->arch.rmap[i])
10655 goto out_free;
10656 if (i == 0)
10657 continue;
10658
10659 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10660 if (!linfo)
10661 goto out_free;
10662
10663 slot->arch.lpage_info[i - 1] = linfo;
10664
10665 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10666 linfo[0].disallow_lpage = 1;
10667 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10668 linfo[lpages - 1].disallow_lpage = 1;
10669 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10670 /*
10671 * If the gfn and userspace address are not aligned wrt each
10672 * other, disable large page support for this slot.
10673 */
10674 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10675 unsigned long j;
10676
10677 for (j = 0; j < lpages; ++j)
10678 linfo[j].disallow_lpage = 1;
10679 }
10680 }
10681
10682 if (kvm_page_track_create_memslot(slot, npages))
10683 goto out_free;
10684
10685 return 0;
10686
10687 out_free:
10688 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10689 kvfree(slot->arch.rmap[i]);
10690 slot->arch.rmap[i] = NULL;
10691 if (i == 0)
10692 continue;
10693
10694 kvfree(slot->arch.lpage_info[i - 1]);
10695 slot->arch.lpage_info[i - 1] = NULL;
10696 }
10697 return -ENOMEM;
10698 }
10699
10700 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10701 {
10702 struct kvm_vcpu *vcpu;
10703 int i;
10704
10705 /*
10706 * memslots->generation has been incremented.
10707 * mmio generation may have reached its maximum value.
10708 */
10709 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10710
10711 /* Force re-initialization of steal_time cache */
10712 kvm_for_each_vcpu(i, vcpu, kvm)
10713 kvm_vcpu_kick(vcpu);
10714 }
10715
10716 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10717 struct kvm_memory_slot *memslot,
10718 const struct kvm_userspace_memory_region *mem,
10719 enum kvm_mr_change change)
10720 {
10721 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10722 return kvm_alloc_memslot_metadata(memslot,
10723 mem->memory_size >> PAGE_SHIFT);
10724 return 0;
10725 }
10726
10727 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10728 struct kvm_memory_slot *old,
10729 struct kvm_memory_slot *new,
10730 enum kvm_mr_change change)
10731 {
10732 /*
10733 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10734 * See comments below.
10735 */
10736 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10737 return;
10738
10739 /*
10740 * Dirty logging tracks sptes in 4k granularity, meaning that large
10741 * sptes have to be split. If live migration is successful, the guest
10742 * in the source machine will be destroyed and large sptes will be
10743 * created in the destination. However, if the guest continues to run
10744 * in the source machine (for example if live migration fails), small
10745 * sptes will remain around and cause bad performance.
10746 *
10747 * Scan sptes if dirty logging has been stopped, dropping those
10748 * which can be collapsed into a single large-page spte. Later
10749 * page faults will create the large-page sptes.
10750 *
10751 * There is no need to do this in any of the following cases:
10752 * CREATE: No dirty mappings will already exist.
10753 * MOVE/DELETE: The old mappings will already have been cleaned up by
10754 * kvm_arch_flush_shadow_memslot()
10755 */
10756 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10757 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10758 kvm_mmu_zap_collapsible_sptes(kvm, new);
10759
10760 /*
10761 * Enable or disable dirty logging for the slot.
10762 *
10763 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10764 * slot have been zapped so no dirty logging updates are needed for
10765 * the old slot.
10766 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10767 * any mappings that might be created in it will consume the
10768 * properties of the new slot and do not need to be updated here.
10769 *
10770 * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10771 * called to enable/disable dirty logging.
10772 *
10773 * When disabling dirty logging with PML enabled, the D-bit is set
10774 * for sptes in the slot in order to prevent unnecessary GPA
10775 * logging in the PML buffer (and potential PML buffer full VMEXIT).
10776 * This guarantees leaving PML enabled for the guest's lifetime
10777 * won't have any additional overhead from PML when the guest is
10778 * running with dirty logging disabled.
10779 *
10780 * When enabling dirty logging, large sptes are write-protected
10781 * so they can be split on first write. New large sptes cannot
10782 * be created for this slot until the end of the logging.
10783 * See the comments in fast_page_fault().
10784 * For small sptes, nothing is done if the dirty log is in the
10785 * initial-all-set state. Otherwise, depending on whether pml
10786 * is enabled the D-bit or the W-bit will be cleared.
10787 */
10788 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10789 if (kvm_x86_ops.slot_enable_log_dirty) {
10790 static_call(kvm_x86_slot_enable_log_dirty)(kvm, new);
10791 } else {
10792 int level =
10793 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10794 PG_LEVEL_2M : PG_LEVEL_4K;
10795
10796 /*
10797 * If we're with initial-all-set, we don't need
10798 * to write protect any small page because
10799 * they're reported as dirty already. However
10800 * we still need to write-protect huge pages
10801 * so that the page split can happen lazily on
10802 * the first write to the huge page.
10803 */
10804 kvm_mmu_slot_remove_write_access(kvm, new, level);
10805 }
10806 } else {
10807 static_call_cond(kvm_x86_slot_disable_log_dirty)(kvm, new);
10808 }
10809 }
10810
10811 void kvm_arch_commit_memory_region(struct kvm *kvm,
10812 const struct kvm_userspace_memory_region *mem,
10813 struct kvm_memory_slot *old,
10814 const struct kvm_memory_slot *new,
10815 enum kvm_mr_change change)
10816 {
10817 if (!kvm->arch.n_requested_mmu_pages)
10818 kvm_mmu_change_mmu_pages(kvm,
10819 kvm_mmu_calculate_default_mmu_pages(kvm));
10820
10821 /*
10822 * FIXME: const-ify all uses of struct kvm_memory_slot.
10823 */
10824 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10825
10826 /* Free the arrays associated with the old memslot. */
10827 if (change == KVM_MR_MOVE)
10828 kvm_arch_free_memslot(kvm, old);
10829 }
10830
10831 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10832 {
10833 kvm_mmu_zap_all(kvm);
10834 }
10835
10836 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10837 struct kvm_memory_slot *slot)
10838 {
10839 kvm_page_track_flush_slot(kvm, slot);
10840 }
10841
10842 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10843 {
10844 return (is_guest_mode(vcpu) &&
10845 kvm_x86_ops.guest_apic_has_interrupt &&
10846 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
10847 }
10848
10849 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10850 {
10851 if (!list_empty_careful(&vcpu->async_pf.done))
10852 return true;
10853
10854 if (kvm_apic_has_events(vcpu))
10855 return true;
10856
10857 if (vcpu->arch.pv.pv_unhalted)
10858 return true;
10859
10860 if (vcpu->arch.exception.pending)
10861 return true;
10862
10863 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10864 (vcpu->arch.nmi_pending &&
10865 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
10866 return true;
10867
10868 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10869 (vcpu->arch.smi_pending &&
10870 static_call(kvm_x86_smi_allowed)(vcpu, false)))
10871 return true;
10872
10873 if (kvm_arch_interrupt_allowed(vcpu) &&
10874 (kvm_cpu_has_interrupt(vcpu) ||
10875 kvm_guest_apic_has_interrupt(vcpu)))
10876 return true;
10877
10878 if (kvm_hv_has_stimer_pending(vcpu))
10879 return true;
10880
10881 if (is_guest_mode(vcpu) &&
10882 kvm_x86_ops.nested_ops->hv_timer_pending &&
10883 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10884 return true;
10885
10886 return false;
10887 }
10888
10889 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10890 {
10891 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10892 }
10893
10894 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10895 {
10896 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10897 return true;
10898
10899 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10900 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10901 kvm_test_request(KVM_REQ_EVENT, vcpu))
10902 return true;
10903
10904 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
10905 return true;
10906
10907 return false;
10908 }
10909
10910 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10911 {
10912 return vcpu->arch.preempted_in_kernel;
10913 }
10914
10915 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10916 {
10917 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10918 }
10919
10920 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10921 {
10922 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
10923 }
10924
10925 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10926 {
10927 /* Can't read the RIP when guest state is protected, just return 0 */
10928 if (vcpu->arch.guest_state_protected)
10929 return 0;
10930
10931 if (is_64_bit_mode(vcpu))
10932 return kvm_rip_read(vcpu);
10933 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10934 kvm_rip_read(vcpu));
10935 }
10936 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10937
10938 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10939 {
10940 return kvm_get_linear_rip(vcpu) == linear_rip;
10941 }
10942 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10943
10944 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10945 {
10946 unsigned long rflags;
10947
10948 rflags = static_call(kvm_x86_get_rflags)(vcpu);
10949 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10950 rflags &= ~X86_EFLAGS_TF;
10951 return rflags;
10952 }
10953 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10954
10955 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10956 {
10957 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10958 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10959 rflags |= X86_EFLAGS_TF;
10960 static_call(kvm_x86_set_rflags)(vcpu, rflags);
10961 }
10962
10963 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10964 {
10965 __kvm_set_rflags(vcpu, rflags);
10966 kvm_make_request(KVM_REQ_EVENT, vcpu);
10967 }
10968 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10969
10970 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10971 {
10972 int r;
10973
10974 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10975 work->wakeup_all)
10976 return;
10977
10978 r = kvm_mmu_reload(vcpu);
10979 if (unlikely(r))
10980 return;
10981
10982 if (!vcpu->arch.mmu->direct_map &&
10983 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10984 return;
10985
10986 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10987 }
10988
10989 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10990 {
10991 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10992
10993 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10994 }
10995
10996 static inline u32 kvm_async_pf_next_probe(u32 key)
10997 {
10998 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10999 }
11000
11001 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
11002 {
11003 u32 key = kvm_async_pf_hash_fn(gfn);
11004
11005 while (vcpu->arch.apf.gfns[key] != ~0)
11006 key = kvm_async_pf_next_probe(key);
11007
11008 vcpu->arch.apf.gfns[key] = gfn;
11009 }
11010
11011 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
11012 {
11013 int i;
11014 u32 key = kvm_async_pf_hash_fn(gfn);
11015
11016 for (i = 0; i < ASYNC_PF_PER_VCPU &&
11017 (vcpu->arch.apf.gfns[key] != gfn &&
11018 vcpu->arch.apf.gfns[key] != ~0); i++)
11019 key = kvm_async_pf_next_probe(key);
11020
11021 return key;
11022 }
11023
11024 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
11025 {
11026 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
11027 }
11028
11029 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
11030 {
11031 u32 i, j, k;
11032
11033 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
11034
11035 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
11036 return;
11037
11038 while (true) {
11039 vcpu->arch.apf.gfns[i] = ~0;
11040 do {
11041 j = kvm_async_pf_next_probe(j);
11042 if (vcpu->arch.apf.gfns[j] == ~0)
11043 return;
11044 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
11045 /*
11046 * k lies cyclically in ]i,j]
11047 * | i.k.j |
11048 * |....j i.k.| or |.k..j i...|
11049 */
11050 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
11051 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
11052 i = j;
11053 }
11054 }
11055
11056 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
11057 {
11058 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
11059
11060 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
11061 sizeof(reason));
11062 }
11063
11064 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
11065 {
11066 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11067
11068 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11069 &token, offset, sizeof(token));
11070 }
11071
11072 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
11073 {
11074 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11075 u32 val;
11076
11077 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11078 &val, offset, sizeof(val)))
11079 return false;
11080
11081 return !val;
11082 }
11083
11084 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
11085 {
11086 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
11087 return false;
11088
11089 if (!kvm_pv_async_pf_enabled(vcpu) ||
11090 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0))
11091 return false;
11092
11093 return true;
11094 }
11095
11096 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
11097 {
11098 if (unlikely(!lapic_in_kernel(vcpu) ||
11099 kvm_event_needs_reinjection(vcpu) ||
11100 vcpu->arch.exception.pending))
11101 return false;
11102
11103 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
11104 return false;
11105
11106 /*
11107 * If interrupts are off we cannot even use an artificial
11108 * halt state.
11109 */
11110 return kvm_arch_interrupt_allowed(vcpu);
11111 }
11112
11113 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
11114 struct kvm_async_pf *work)
11115 {
11116 struct x86_exception fault;
11117
11118 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
11119 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
11120
11121 if (kvm_can_deliver_async_pf(vcpu) &&
11122 !apf_put_user_notpresent(vcpu)) {
11123 fault.vector = PF_VECTOR;
11124 fault.error_code_valid = true;
11125 fault.error_code = 0;
11126 fault.nested_page_fault = false;
11127 fault.address = work->arch.token;
11128 fault.async_page_fault = true;
11129 kvm_inject_page_fault(vcpu, &fault);
11130 return true;
11131 } else {
11132 /*
11133 * It is not possible to deliver a paravirtualized asynchronous
11134 * page fault, but putting the guest in an artificial halt state
11135 * can be beneficial nevertheless: if an interrupt arrives, we
11136 * can deliver it timely and perhaps the guest will schedule
11137 * another process. When the instruction that triggered a page
11138 * fault is retried, hopefully the page will be ready in the host.
11139 */
11140 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
11141 return false;
11142 }
11143 }
11144
11145 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
11146 struct kvm_async_pf *work)
11147 {
11148 struct kvm_lapic_irq irq = {
11149 .delivery_mode = APIC_DM_FIXED,
11150 .vector = vcpu->arch.apf.vec
11151 };
11152
11153 if (work->wakeup_all)
11154 work->arch.token = ~0; /* broadcast wakeup */
11155 else
11156 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
11157 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
11158
11159 if ((work->wakeup_all || work->notpresent_injected) &&
11160 kvm_pv_async_pf_enabled(vcpu) &&
11161 !apf_put_user_ready(vcpu, work->arch.token)) {
11162 vcpu->arch.apf.pageready_pending = true;
11163 kvm_apic_set_irq(vcpu, &irq, NULL);
11164 }
11165
11166 vcpu->arch.apf.halted = false;
11167 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11168 }
11169
11170 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
11171 {
11172 kvm_make_request(KVM_REQ_APF_READY, vcpu);
11173 if (!vcpu->arch.apf.pageready_pending)
11174 kvm_vcpu_kick(vcpu);
11175 }
11176
11177 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
11178 {
11179 if (!kvm_pv_async_pf_enabled(vcpu))
11180 return true;
11181 else
11182 return apf_pageready_slot_free(vcpu);
11183 }
11184
11185 void kvm_arch_start_assignment(struct kvm *kvm)
11186 {
11187 atomic_inc(&kvm->arch.assigned_device_count);
11188 }
11189 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
11190
11191 void kvm_arch_end_assignment(struct kvm *kvm)
11192 {
11193 atomic_dec(&kvm->arch.assigned_device_count);
11194 }
11195 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
11196
11197 bool kvm_arch_has_assigned_device(struct kvm *kvm)
11198 {
11199 return atomic_read(&kvm->arch.assigned_device_count);
11200 }
11201 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
11202
11203 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
11204 {
11205 atomic_inc(&kvm->arch.noncoherent_dma_count);
11206 }
11207 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
11208
11209 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
11210 {
11211 atomic_dec(&kvm->arch.noncoherent_dma_count);
11212 }
11213 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
11214
11215 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
11216 {
11217 return atomic_read(&kvm->arch.noncoherent_dma_count);
11218 }
11219 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
11220
11221 bool kvm_arch_has_irq_bypass(void)
11222 {
11223 return true;
11224 }
11225
11226 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
11227 struct irq_bypass_producer *prod)
11228 {
11229 struct kvm_kernel_irqfd *irqfd =
11230 container_of(cons, struct kvm_kernel_irqfd, consumer);
11231 int ret;
11232
11233 irqfd->producer = prod;
11234 kvm_arch_start_assignment(irqfd->kvm);
11235 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm,
11236 prod->irq, irqfd->gsi, 1);
11237
11238 if (ret)
11239 kvm_arch_end_assignment(irqfd->kvm);
11240
11241 return ret;
11242 }
11243
11244 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
11245 struct irq_bypass_producer *prod)
11246 {
11247 int ret;
11248 struct kvm_kernel_irqfd *irqfd =
11249 container_of(cons, struct kvm_kernel_irqfd, consumer);
11250
11251 WARN_ON(irqfd->producer != prod);
11252 irqfd->producer = NULL;
11253
11254 /*
11255 * When producer of consumer is unregistered, we change back to
11256 * remapped mode, so we can re-use the current implementation
11257 * when the irq is masked/disabled or the consumer side (KVM
11258 * int this case doesn't want to receive the interrupts.
11259 */
11260 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
11261 if (ret)
11262 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
11263 " fails: %d\n", irqfd->consumer.token, ret);
11264
11265 kvm_arch_end_assignment(irqfd->kvm);
11266 }
11267
11268 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
11269 uint32_t guest_irq, bool set)
11270 {
11271 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set);
11272 }
11273
11274 bool kvm_vector_hashing_enabled(void)
11275 {
11276 return vector_hashing;
11277 }
11278
11279 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11280 {
11281 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11282 }
11283 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11284
11285
11286 int kvm_spec_ctrl_test_value(u64 value)
11287 {
11288 /*
11289 * test that setting IA32_SPEC_CTRL to given value
11290 * is allowed by the host processor
11291 */
11292
11293 u64 saved_value;
11294 unsigned long flags;
11295 int ret = 0;
11296
11297 local_irq_save(flags);
11298
11299 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11300 ret = 1;
11301 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11302 ret = 1;
11303 else
11304 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11305
11306 local_irq_restore(flags);
11307
11308 return ret;
11309 }
11310 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11311
11312 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11313 {
11314 struct x86_exception fault;
11315 u32 access = error_code &
11316 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11317
11318 if (!(error_code & PFERR_PRESENT_MASK) ||
11319 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11320 /*
11321 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11322 * tables probably do not match the TLB. Just proceed
11323 * with the error code that the processor gave.
11324 */
11325 fault.vector = PF_VECTOR;
11326 fault.error_code_valid = true;
11327 fault.error_code = error_code;
11328 fault.nested_page_fault = false;
11329 fault.address = gva;
11330 }
11331 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11332 }
11333 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11334
11335 /*
11336 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11337 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11338 * indicates whether exit to userspace is needed.
11339 */
11340 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11341 struct x86_exception *e)
11342 {
11343 if (r == X86EMUL_PROPAGATE_FAULT) {
11344 kvm_inject_emulated_page_fault(vcpu, e);
11345 return 1;
11346 }
11347
11348 /*
11349 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11350 * while handling a VMX instruction KVM could've handled the request
11351 * correctly by exiting to userspace and performing I/O but there
11352 * doesn't seem to be a real use-case behind such requests, just return
11353 * KVM_EXIT_INTERNAL_ERROR for now.
11354 */
11355 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11356 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11357 vcpu->run->internal.ndata = 0;
11358
11359 return 0;
11360 }
11361 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11362
11363 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11364 {
11365 bool pcid_enabled;
11366 struct x86_exception e;
11367 unsigned i;
11368 unsigned long roots_to_free = 0;
11369 struct {
11370 u64 pcid;
11371 u64 gla;
11372 } operand;
11373 int r;
11374
11375 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11376 if (r != X86EMUL_CONTINUE)
11377 return kvm_handle_memory_failure(vcpu, r, &e);
11378
11379 if (operand.pcid >> 12 != 0) {
11380 kvm_inject_gp(vcpu, 0);
11381 return 1;
11382 }
11383
11384 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11385
11386 switch (type) {
11387 case INVPCID_TYPE_INDIV_ADDR:
11388 if ((!pcid_enabled && (operand.pcid != 0)) ||
11389 is_noncanonical_address(operand.gla, vcpu)) {
11390 kvm_inject_gp(vcpu, 0);
11391 return 1;
11392 }
11393 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11394 return kvm_skip_emulated_instruction(vcpu);
11395
11396 case INVPCID_TYPE_SINGLE_CTXT:
11397 if (!pcid_enabled && (operand.pcid != 0)) {
11398 kvm_inject_gp(vcpu, 0);
11399 return 1;
11400 }
11401
11402 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11403 kvm_mmu_sync_roots(vcpu);
11404 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11405 }
11406
11407 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11408 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11409 == operand.pcid)
11410 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11411
11412 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11413 /*
11414 * If neither the current cr3 nor any of the prev_roots use the
11415 * given PCID, then nothing needs to be done here because a
11416 * resync will happen anyway before switching to any other CR3.
11417 */
11418
11419 return kvm_skip_emulated_instruction(vcpu);
11420
11421 case INVPCID_TYPE_ALL_NON_GLOBAL:
11422 /*
11423 * Currently, KVM doesn't mark global entries in the shadow
11424 * page tables, so a non-global flush just degenerates to a
11425 * global flush. If needed, we could optimize this later by
11426 * keeping track of global entries in shadow page tables.
11427 */
11428
11429 fallthrough;
11430 case INVPCID_TYPE_ALL_INCL_GLOBAL:
11431 kvm_mmu_unload(vcpu);
11432 return kvm_skip_emulated_instruction(vcpu);
11433
11434 default:
11435 BUG(); /* We have already checked above that type <= 3 */
11436 }
11437 }
11438 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11439
11440 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
11441 {
11442 struct kvm_run *run = vcpu->run;
11443 struct kvm_mmio_fragment *frag;
11444 unsigned int len;
11445
11446 BUG_ON(!vcpu->mmio_needed);
11447
11448 /* Complete previous fragment */
11449 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11450 len = min(8u, frag->len);
11451 if (!vcpu->mmio_is_write)
11452 memcpy(frag->data, run->mmio.data, len);
11453
11454 if (frag->len <= 8) {
11455 /* Switch to the next fragment. */
11456 frag++;
11457 vcpu->mmio_cur_fragment++;
11458 } else {
11459 /* Go forward to the next mmio piece. */
11460 frag->data += len;
11461 frag->gpa += len;
11462 frag->len -= len;
11463 }
11464
11465 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11466 vcpu->mmio_needed = 0;
11467
11468 // VMG change, at this point, we're always done
11469 // RIP has already been advanced
11470 return 1;
11471 }
11472
11473 // More MMIO is needed
11474 run->mmio.phys_addr = frag->gpa;
11475 run->mmio.len = min(8u, frag->len);
11476 run->mmio.is_write = vcpu->mmio_is_write;
11477 if (run->mmio.is_write)
11478 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11479 run->exit_reason = KVM_EXIT_MMIO;
11480
11481 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11482
11483 return 0;
11484 }
11485
11486 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11487 void *data)
11488 {
11489 int handled;
11490 struct kvm_mmio_fragment *frag;
11491
11492 if (!data)
11493 return -EINVAL;
11494
11495 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11496 if (handled == bytes)
11497 return 1;
11498
11499 bytes -= handled;
11500 gpa += handled;
11501 data += handled;
11502
11503 /*TODO: Check if need to increment number of frags */
11504 frag = vcpu->mmio_fragments;
11505 vcpu->mmio_nr_fragments = 1;
11506 frag->len = bytes;
11507 frag->gpa = gpa;
11508 frag->data = data;
11509
11510 vcpu->mmio_needed = 1;
11511 vcpu->mmio_cur_fragment = 0;
11512
11513 vcpu->run->mmio.phys_addr = gpa;
11514 vcpu->run->mmio.len = min(8u, frag->len);
11515 vcpu->run->mmio.is_write = 1;
11516 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
11517 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11518
11519 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11520
11521 return 0;
11522 }
11523 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
11524
11525 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11526 void *data)
11527 {
11528 int handled;
11529 struct kvm_mmio_fragment *frag;
11530
11531 if (!data)
11532 return -EINVAL;
11533
11534 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11535 if (handled == bytes)
11536 return 1;
11537
11538 bytes -= handled;
11539 gpa += handled;
11540 data += handled;
11541
11542 /*TODO: Check if need to increment number of frags */
11543 frag = vcpu->mmio_fragments;
11544 vcpu->mmio_nr_fragments = 1;
11545 frag->len = bytes;
11546 frag->gpa = gpa;
11547 frag->data = data;
11548
11549 vcpu->mmio_needed = 1;
11550 vcpu->mmio_cur_fragment = 0;
11551
11552 vcpu->run->mmio.phys_addr = gpa;
11553 vcpu->run->mmio.len = min(8u, frag->len);
11554 vcpu->run->mmio.is_write = 0;
11555 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11556
11557 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11558
11559 return 0;
11560 }
11561 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
11562
11563 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
11564 {
11565 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data,
11566 vcpu->arch.pio.count * vcpu->arch.pio.size);
11567 vcpu->arch.pio.count = 0;
11568
11569 return 1;
11570 }
11571
11572 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
11573 unsigned int port, void *data, unsigned int count)
11574 {
11575 int ret;
11576
11577 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port,
11578 data, count);
11579 if (ret)
11580 return ret;
11581
11582 vcpu->arch.pio.count = 0;
11583
11584 return 0;
11585 }
11586
11587 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
11588 unsigned int port, void *data, unsigned int count)
11589 {
11590 int ret;
11591
11592 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port,
11593 data, count);
11594 if (ret) {
11595 vcpu->arch.pio.count = 0;
11596 } else {
11597 vcpu->arch.guest_ins_data = data;
11598 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
11599 }
11600
11601 return 0;
11602 }
11603
11604 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
11605 unsigned int port, void *data, unsigned int count,
11606 int in)
11607 {
11608 return in ? kvm_sev_es_ins(vcpu, size, port, data, count)
11609 : kvm_sev_es_outs(vcpu, size, port, data, count);
11610 }
11611 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
11612
11613 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
11614 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11615 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11616 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11617 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11618 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11619 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11620 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11621 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11622 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11623 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11624 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11625 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11626 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11627 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11628 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11629 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11630 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11631 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11632 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11633 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11634 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11635 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
11636 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
11637 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
11638 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
11639 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
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