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KVM: x86: Fold "write-protect large" use case into generic write-protect
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / x86.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18
19 #include <linux/kvm_host.h>
20 #include "irq.h"
21 #include "ioapic.h"
22 #include "mmu.h"
23 #include "i8254.h"
24 #include "tss.h"
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
27 #include "x86.h"
28 #include "cpuid.h"
29 #include "pmu.h"
30 #include "hyperv.h"
31 #include "lapic.h"
32 #include "xen.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <linux/sched/stat.h>
58 #include <linux/sched/isolation.h>
59 #include <linux/mem_encrypt.h>
60 #include <linux/entry-kvm.h>
61
62 #include <trace/events/kvm.h>
63
64 #include <asm/debugreg.h>
65 #include <asm/msr.h>
66 #include <asm/desc.h>
67 #include <asm/mce.h>
68 #include <linux/kernel_stat.h>
69 #include <asm/fpu/internal.h> /* Ugh! */
70 #include <asm/pvclock.h>
71 #include <asm/div64.h>
72 #include <asm/irq_remapping.h>
73 #include <asm/mshyperv.h>
74 #include <asm/hypervisor.h>
75 #include <asm/tlbflush.h>
76 #include <asm/intel_pt.h>
77 #include <asm/emulate_prefix.h>
78 #include <clocksource/hyperv_timer.h>
79
80 #define CREATE_TRACE_POINTS
81 #include "trace.h"
82
83 #define MAX_IO_MSRS 256
84 #define KVM_MAX_MCE_BANKS 32
85 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
86 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
87
88 #define emul_to_vcpu(ctxt) \
89 ((struct kvm_vcpu *)(ctxt)->vcpu)
90
91 /* EFER defaults:
92 * - enable syscall per default because its emulated by KVM
93 * - enable LME and LMA per default on 64 bit KVM
94 */
95 #ifdef CONFIG_X86_64
96 static
97 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
98 #else
99 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
100 #endif
101
102 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
103
104 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
105 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
106
107 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
108 static void process_nmi(struct kvm_vcpu *vcpu);
109 static void process_smi(struct kvm_vcpu *vcpu);
110 static void enter_smm(struct kvm_vcpu *vcpu);
111 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
112 static void store_regs(struct kvm_vcpu *vcpu);
113 static int sync_regs(struct kvm_vcpu *vcpu);
114
115 struct kvm_x86_ops kvm_x86_ops __read_mostly;
116 EXPORT_SYMBOL_GPL(kvm_x86_ops);
117
118 #define KVM_X86_OP(func) \
119 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
120 *(((struct kvm_x86_ops *)0)->func));
121 #define KVM_X86_OP_NULL KVM_X86_OP
122 #include <asm/kvm-x86-ops.h>
123 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
124 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
125 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current);
126
127 static bool __read_mostly ignore_msrs = 0;
128 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
129
130 bool __read_mostly report_ignored_msrs = true;
131 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
132 EXPORT_SYMBOL_GPL(report_ignored_msrs);
133
134 unsigned int min_timer_period_us = 200;
135 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
136
137 static bool __read_mostly kvmclock_periodic_sync = true;
138 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
139
140 bool __read_mostly kvm_has_tsc_control;
141 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
142 u32 __read_mostly kvm_max_guest_tsc_khz;
143 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
144 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
145 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
146 u64 __read_mostly kvm_max_tsc_scaling_ratio;
147 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
148 u64 __read_mostly kvm_default_tsc_scaling_ratio;
149 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
150 bool __read_mostly kvm_has_bus_lock_exit;
151 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit);
152
153 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
154 static u32 __read_mostly tsc_tolerance_ppm = 250;
155 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
156
157 /*
158 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
159 * adaptive tuning starting from default advancment of 1000ns. '0' disables
160 * advancement entirely. Any other value is used as-is and disables adaptive
161 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
162 */
163 static int __read_mostly lapic_timer_advance_ns = -1;
164 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
165
166 static bool __read_mostly vector_hashing = true;
167 module_param(vector_hashing, bool, S_IRUGO);
168
169 bool __read_mostly enable_vmware_backdoor = false;
170 module_param(enable_vmware_backdoor, bool, S_IRUGO);
171 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
172
173 static bool __read_mostly force_emulation_prefix = false;
174 module_param(force_emulation_prefix, bool, S_IRUGO);
175
176 int __read_mostly pi_inject_timer = -1;
177 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
178
179 /*
180 * Restoring the host value for MSRs that are only consumed when running in
181 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
182 * returns to userspace, i.e. the kernel can run with the guest's value.
183 */
184 #define KVM_MAX_NR_USER_RETURN_MSRS 16
185
186 struct kvm_user_return_msrs_global {
187 int nr;
188 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
189 };
190
191 struct kvm_user_return_msrs {
192 struct user_return_notifier urn;
193 bool registered;
194 struct kvm_user_return_msr_values {
195 u64 host;
196 u64 curr;
197 } values[KVM_MAX_NR_USER_RETURN_MSRS];
198 };
199
200 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
201 static struct kvm_user_return_msrs __percpu *user_return_msrs;
202
203 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
204 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
205 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
206 | XFEATURE_MASK_PKRU)
207
208 u64 __read_mostly host_efer;
209 EXPORT_SYMBOL_GPL(host_efer);
210
211 bool __read_mostly allow_smaller_maxphyaddr = 0;
212 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
213
214 u64 __read_mostly host_xss;
215 EXPORT_SYMBOL_GPL(host_xss);
216 u64 __read_mostly supported_xss;
217 EXPORT_SYMBOL_GPL(supported_xss);
218
219 struct kvm_stats_debugfs_item debugfs_entries[] = {
220 VCPU_STAT("pf_fixed", pf_fixed),
221 VCPU_STAT("pf_guest", pf_guest),
222 VCPU_STAT("tlb_flush", tlb_flush),
223 VCPU_STAT("invlpg", invlpg),
224 VCPU_STAT("exits", exits),
225 VCPU_STAT("io_exits", io_exits),
226 VCPU_STAT("mmio_exits", mmio_exits),
227 VCPU_STAT("signal_exits", signal_exits),
228 VCPU_STAT("irq_window", irq_window_exits),
229 VCPU_STAT("nmi_window", nmi_window_exits),
230 VCPU_STAT("halt_exits", halt_exits),
231 VCPU_STAT("halt_successful_poll", halt_successful_poll),
232 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
233 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
234 VCPU_STAT("halt_wakeup", halt_wakeup),
235 VCPU_STAT("hypercalls", hypercalls),
236 VCPU_STAT("request_irq", request_irq_exits),
237 VCPU_STAT("irq_exits", irq_exits),
238 VCPU_STAT("host_state_reload", host_state_reload),
239 VCPU_STAT("fpu_reload", fpu_reload),
240 VCPU_STAT("insn_emulation", insn_emulation),
241 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
242 VCPU_STAT("irq_injections", irq_injections),
243 VCPU_STAT("nmi_injections", nmi_injections),
244 VCPU_STAT("req_event", req_event),
245 VCPU_STAT("l1d_flush", l1d_flush),
246 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
247 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
248 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
249 VM_STAT("mmu_pte_write", mmu_pte_write),
250 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
251 VM_STAT("mmu_flooded", mmu_flooded),
252 VM_STAT("mmu_recycled", mmu_recycled),
253 VM_STAT("mmu_cache_miss", mmu_cache_miss),
254 VM_STAT("mmu_unsync", mmu_unsync),
255 VM_STAT("remote_tlb_flush", remote_tlb_flush),
256 VM_STAT("largepages", lpages, .mode = 0444),
257 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
258 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
259 { NULL }
260 };
261
262 u64 __read_mostly host_xcr0;
263 u64 __read_mostly supported_xcr0;
264 EXPORT_SYMBOL_GPL(supported_xcr0);
265
266 static struct kmem_cache *x86_fpu_cache;
267
268 static struct kmem_cache *x86_emulator_cache;
269
270 /*
271 * When called, it means the previous get/set msr reached an invalid msr.
272 * Return true if we want to ignore/silent this failed msr access.
273 */
274 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
275 u64 data, bool write)
276 {
277 const char *op = write ? "wrmsr" : "rdmsr";
278
279 if (ignore_msrs) {
280 if (report_ignored_msrs)
281 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
282 op, msr, data);
283 /* Mask the error */
284 return true;
285 } else {
286 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
287 op, msr, data);
288 return false;
289 }
290 }
291
292 static struct kmem_cache *kvm_alloc_emulator_cache(void)
293 {
294 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
295 unsigned int size = sizeof(struct x86_emulate_ctxt);
296
297 return kmem_cache_create_usercopy("x86_emulator", size,
298 __alignof__(struct x86_emulate_ctxt),
299 SLAB_ACCOUNT, useroffset,
300 size - useroffset, NULL);
301 }
302
303 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
304
305 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
306 {
307 int i;
308 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
309 vcpu->arch.apf.gfns[i] = ~0;
310 }
311
312 static void kvm_on_user_return(struct user_return_notifier *urn)
313 {
314 unsigned slot;
315 struct kvm_user_return_msrs *msrs
316 = container_of(urn, struct kvm_user_return_msrs, urn);
317 struct kvm_user_return_msr_values *values;
318 unsigned long flags;
319
320 /*
321 * Disabling irqs at this point since the following code could be
322 * interrupted and executed through kvm_arch_hardware_disable()
323 */
324 local_irq_save(flags);
325 if (msrs->registered) {
326 msrs->registered = false;
327 user_return_notifier_unregister(urn);
328 }
329 local_irq_restore(flags);
330 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
331 values = &msrs->values[slot];
332 if (values->host != values->curr) {
333 wrmsrl(user_return_msrs_global.msrs[slot], values->host);
334 values->curr = values->host;
335 }
336 }
337 }
338
339 void kvm_define_user_return_msr(unsigned slot, u32 msr)
340 {
341 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
342 user_return_msrs_global.msrs[slot] = msr;
343 if (slot >= user_return_msrs_global.nr)
344 user_return_msrs_global.nr = slot + 1;
345 }
346 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
347
348 static void kvm_user_return_msr_cpu_online(void)
349 {
350 unsigned int cpu = smp_processor_id();
351 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
352 u64 value;
353 int i;
354
355 for (i = 0; i < user_return_msrs_global.nr; ++i) {
356 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
357 msrs->values[i].host = value;
358 msrs->values[i].curr = value;
359 }
360 }
361
362 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
363 {
364 unsigned int cpu = smp_processor_id();
365 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
366 int err;
367
368 value = (value & mask) | (msrs->values[slot].host & ~mask);
369 if (value == msrs->values[slot].curr)
370 return 0;
371 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
372 if (err)
373 return 1;
374
375 msrs->values[slot].curr = value;
376 if (!msrs->registered) {
377 msrs->urn.on_user_return = kvm_on_user_return;
378 user_return_notifier_register(&msrs->urn);
379 msrs->registered = true;
380 }
381 return 0;
382 }
383 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
384
385 static void drop_user_return_notifiers(void)
386 {
387 unsigned int cpu = smp_processor_id();
388 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
389
390 if (msrs->registered)
391 kvm_on_user_return(&msrs->urn);
392 }
393
394 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
395 {
396 return vcpu->arch.apic_base;
397 }
398 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
399
400 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
401 {
402 return kvm_apic_mode(kvm_get_apic_base(vcpu));
403 }
404 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
405
406 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
407 {
408 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
409 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
410 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
411 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
412
413 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
414 return 1;
415 if (!msr_info->host_initiated) {
416 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
417 return 1;
418 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
419 return 1;
420 }
421
422 kvm_lapic_set_base(vcpu, msr_info->data);
423 kvm_recalculate_apic_map(vcpu->kvm);
424 return 0;
425 }
426 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
427
428 asmlinkage __visible noinstr void kvm_spurious_fault(void)
429 {
430 /* Fault while not rebooting. We want the trace. */
431 BUG_ON(!kvm_rebooting);
432 }
433 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
434
435 #define EXCPT_BENIGN 0
436 #define EXCPT_CONTRIBUTORY 1
437 #define EXCPT_PF 2
438
439 static int exception_class(int vector)
440 {
441 switch (vector) {
442 case PF_VECTOR:
443 return EXCPT_PF;
444 case DE_VECTOR:
445 case TS_VECTOR:
446 case NP_VECTOR:
447 case SS_VECTOR:
448 case GP_VECTOR:
449 return EXCPT_CONTRIBUTORY;
450 default:
451 break;
452 }
453 return EXCPT_BENIGN;
454 }
455
456 #define EXCPT_FAULT 0
457 #define EXCPT_TRAP 1
458 #define EXCPT_ABORT 2
459 #define EXCPT_INTERRUPT 3
460
461 static int exception_type(int vector)
462 {
463 unsigned int mask;
464
465 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
466 return EXCPT_INTERRUPT;
467
468 mask = 1 << vector;
469
470 /* #DB is trap, as instruction watchpoints are handled elsewhere */
471 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
472 return EXCPT_TRAP;
473
474 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
475 return EXCPT_ABORT;
476
477 /* Reserved exceptions will result in fault */
478 return EXCPT_FAULT;
479 }
480
481 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
482 {
483 unsigned nr = vcpu->arch.exception.nr;
484 bool has_payload = vcpu->arch.exception.has_payload;
485 unsigned long payload = vcpu->arch.exception.payload;
486
487 if (!has_payload)
488 return;
489
490 switch (nr) {
491 case DB_VECTOR:
492 /*
493 * "Certain debug exceptions may clear bit 0-3. The
494 * remaining contents of the DR6 register are never
495 * cleared by the processor".
496 */
497 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
498 /*
499 * In order to reflect the #DB exception payload in guest
500 * dr6, three components need to be considered: active low
501 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
502 * DR6_BS and DR6_BT)
503 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
504 * In the target guest dr6:
505 * FIXED_1 bits should always be set.
506 * Active low bits should be cleared if 1-setting in payload.
507 * Active high bits should be set if 1-setting in payload.
508 *
509 * Note, the payload is compatible with the pending debug
510 * exceptions/exit qualification under VMX, that active_low bits
511 * are active high in payload.
512 * So they need to be flipped for DR6.
513 */
514 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
515 vcpu->arch.dr6 |= payload;
516 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW;
517
518 /*
519 * The #DB payload is defined as compatible with the 'pending
520 * debug exceptions' field under VMX, not DR6. While bit 12 is
521 * defined in the 'pending debug exceptions' field (enabled
522 * breakpoint), it is reserved and must be zero in DR6.
523 */
524 vcpu->arch.dr6 &= ~BIT(12);
525 break;
526 case PF_VECTOR:
527 vcpu->arch.cr2 = payload;
528 break;
529 }
530
531 vcpu->arch.exception.has_payload = false;
532 vcpu->arch.exception.payload = 0;
533 }
534 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
535
536 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
537 unsigned nr, bool has_error, u32 error_code,
538 bool has_payload, unsigned long payload, bool reinject)
539 {
540 u32 prev_nr;
541 int class1, class2;
542
543 kvm_make_request(KVM_REQ_EVENT, vcpu);
544
545 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
546 queue:
547 if (has_error && !is_protmode(vcpu))
548 has_error = false;
549 if (reinject) {
550 /*
551 * On vmentry, vcpu->arch.exception.pending is only
552 * true if an event injection was blocked by
553 * nested_run_pending. In that case, however,
554 * vcpu_enter_guest requests an immediate exit,
555 * and the guest shouldn't proceed far enough to
556 * need reinjection.
557 */
558 WARN_ON_ONCE(vcpu->arch.exception.pending);
559 vcpu->arch.exception.injected = true;
560 if (WARN_ON_ONCE(has_payload)) {
561 /*
562 * A reinjected event has already
563 * delivered its payload.
564 */
565 has_payload = false;
566 payload = 0;
567 }
568 } else {
569 vcpu->arch.exception.pending = true;
570 vcpu->arch.exception.injected = false;
571 }
572 vcpu->arch.exception.has_error_code = has_error;
573 vcpu->arch.exception.nr = nr;
574 vcpu->arch.exception.error_code = error_code;
575 vcpu->arch.exception.has_payload = has_payload;
576 vcpu->arch.exception.payload = payload;
577 if (!is_guest_mode(vcpu))
578 kvm_deliver_exception_payload(vcpu);
579 return;
580 }
581
582 /* to check exception */
583 prev_nr = vcpu->arch.exception.nr;
584 if (prev_nr == DF_VECTOR) {
585 /* triple fault -> shutdown */
586 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
587 return;
588 }
589 class1 = exception_class(prev_nr);
590 class2 = exception_class(nr);
591 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
592 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
593 /*
594 * Generate double fault per SDM Table 5-5. Set
595 * exception.pending = true so that the double fault
596 * can trigger a nested vmexit.
597 */
598 vcpu->arch.exception.pending = true;
599 vcpu->arch.exception.injected = false;
600 vcpu->arch.exception.has_error_code = true;
601 vcpu->arch.exception.nr = DF_VECTOR;
602 vcpu->arch.exception.error_code = 0;
603 vcpu->arch.exception.has_payload = false;
604 vcpu->arch.exception.payload = 0;
605 } else
606 /* replace previous exception with a new one in a hope
607 that instruction re-execution will regenerate lost
608 exception */
609 goto queue;
610 }
611
612 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
613 {
614 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
615 }
616 EXPORT_SYMBOL_GPL(kvm_queue_exception);
617
618 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
619 {
620 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
621 }
622 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
623
624 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
625 unsigned long payload)
626 {
627 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
628 }
629 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
630
631 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
632 u32 error_code, unsigned long payload)
633 {
634 kvm_multiple_exception(vcpu, nr, true, error_code,
635 true, payload, false);
636 }
637
638 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
639 {
640 if (err)
641 kvm_inject_gp(vcpu, 0);
642 else
643 return kvm_skip_emulated_instruction(vcpu);
644
645 return 1;
646 }
647 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
648
649 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
650 {
651 ++vcpu->stat.pf_guest;
652 vcpu->arch.exception.nested_apf =
653 is_guest_mode(vcpu) && fault->async_page_fault;
654 if (vcpu->arch.exception.nested_apf) {
655 vcpu->arch.apf.nested_apf_token = fault->address;
656 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
657 } else {
658 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
659 fault->address);
660 }
661 }
662 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
663
664 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
665 struct x86_exception *fault)
666 {
667 struct kvm_mmu *fault_mmu;
668 WARN_ON_ONCE(fault->vector != PF_VECTOR);
669
670 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
671 vcpu->arch.walk_mmu;
672
673 /*
674 * Invalidate the TLB entry for the faulting address, if it exists,
675 * else the access will fault indefinitely (and to emulate hardware).
676 */
677 if ((fault->error_code & PFERR_PRESENT_MASK) &&
678 !(fault->error_code & PFERR_RSVD_MASK))
679 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
680 fault_mmu->root_hpa);
681
682 fault_mmu->inject_page_fault(vcpu, fault);
683 return fault->nested_page_fault;
684 }
685 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
686
687 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
688 {
689 atomic_inc(&vcpu->arch.nmi_queued);
690 kvm_make_request(KVM_REQ_NMI, vcpu);
691 }
692 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
693
694 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
695 {
696 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
697 }
698 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
699
700 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
701 {
702 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
703 }
704 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
705
706 /*
707 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
708 * a #GP and return false.
709 */
710 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
711 {
712 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
713 return true;
714 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
715 return false;
716 }
717 EXPORT_SYMBOL_GPL(kvm_require_cpl);
718
719 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
720 {
721 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
722 return true;
723
724 kvm_queue_exception(vcpu, UD_VECTOR);
725 return false;
726 }
727 EXPORT_SYMBOL_GPL(kvm_require_dr);
728
729 /*
730 * This function will be used to read from the physical memory of the currently
731 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
732 * can read from guest physical or from the guest's guest physical memory.
733 */
734 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
735 gfn_t ngfn, void *data, int offset, int len,
736 u32 access)
737 {
738 struct x86_exception exception;
739 gfn_t real_gfn;
740 gpa_t ngpa;
741
742 ngpa = gfn_to_gpa(ngfn);
743 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
744 if (real_gfn == UNMAPPED_GVA)
745 return -EFAULT;
746
747 real_gfn = gpa_to_gfn(real_gfn);
748
749 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
750 }
751 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
752
753 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
754 void *data, int offset, int len, u32 access)
755 {
756 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
757 data, offset, len, access);
758 }
759
760 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
761 {
762 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
763 }
764
765 /*
766 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
767 */
768 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
769 {
770 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
771 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
772 int i;
773 int ret;
774 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
775
776 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
777 offset * sizeof(u64), sizeof(pdpte),
778 PFERR_USER_MASK|PFERR_WRITE_MASK);
779 if (ret < 0) {
780 ret = 0;
781 goto out;
782 }
783 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
784 if ((pdpte[i] & PT_PRESENT_MASK) &&
785 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
786 ret = 0;
787 goto out;
788 }
789 }
790 ret = 1;
791
792 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
793 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
794
795 out:
796
797 return ret;
798 }
799 EXPORT_SYMBOL_GPL(load_pdptrs);
800
801 bool pdptrs_changed(struct kvm_vcpu *vcpu)
802 {
803 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
804 int offset;
805 gfn_t gfn;
806 int r;
807
808 if (!is_pae_paging(vcpu))
809 return false;
810
811 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
812 return true;
813
814 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
815 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
816 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
817 PFERR_USER_MASK | PFERR_WRITE_MASK);
818 if (r < 0)
819 return true;
820
821 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
822 }
823 EXPORT_SYMBOL_GPL(pdptrs_changed);
824
825 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
826 {
827 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
828
829 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
830 kvm_clear_async_pf_completion_queue(vcpu);
831 kvm_async_pf_hash_reset(vcpu);
832 }
833
834 if ((cr0 ^ old_cr0) & update_bits)
835 kvm_mmu_reset_context(vcpu);
836
837 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
838 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
839 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
840 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
841 }
842 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
843
844 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
845 {
846 unsigned long old_cr0 = kvm_read_cr0(vcpu);
847 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
848
849 cr0 |= X86_CR0_ET;
850
851 #ifdef CONFIG_X86_64
852 if (cr0 & 0xffffffff00000000UL)
853 return 1;
854 #endif
855
856 cr0 &= ~CR0_RESERVED_BITS;
857
858 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
859 return 1;
860
861 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
862 return 1;
863
864 #ifdef CONFIG_X86_64
865 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
866 (cr0 & X86_CR0_PG)) {
867 int cs_db, cs_l;
868
869 if (!is_pae(vcpu))
870 return 1;
871 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
872 if (cs_l)
873 return 1;
874 }
875 #endif
876 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
877 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
878 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
879 return 1;
880
881 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
882 return 1;
883
884 static_call(kvm_x86_set_cr0)(vcpu, cr0);
885
886 kvm_post_set_cr0(vcpu, old_cr0, cr0);
887
888 return 0;
889 }
890 EXPORT_SYMBOL_GPL(kvm_set_cr0);
891
892 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
893 {
894 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
895 }
896 EXPORT_SYMBOL_GPL(kvm_lmsw);
897
898 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
899 {
900 if (vcpu->arch.guest_state_protected)
901 return;
902
903 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
904
905 if (vcpu->arch.xcr0 != host_xcr0)
906 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
907
908 if (vcpu->arch.xsaves_enabled &&
909 vcpu->arch.ia32_xss != host_xss)
910 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
911 }
912
913 if (static_cpu_has(X86_FEATURE_PKU) &&
914 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
915 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
916 vcpu->arch.pkru != vcpu->arch.host_pkru)
917 __write_pkru(vcpu->arch.pkru);
918 }
919 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
920
921 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
922 {
923 if (vcpu->arch.guest_state_protected)
924 return;
925
926 if (static_cpu_has(X86_FEATURE_PKU) &&
927 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
928 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
929 vcpu->arch.pkru = rdpkru();
930 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
931 __write_pkru(vcpu->arch.host_pkru);
932 }
933
934 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
935
936 if (vcpu->arch.xcr0 != host_xcr0)
937 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
938
939 if (vcpu->arch.xsaves_enabled &&
940 vcpu->arch.ia32_xss != host_xss)
941 wrmsrl(MSR_IA32_XSS, host_xss);
942 }
943
944 }
945 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
946
947 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
948 {
949 u64 xcr0 = xcr;
950 u64 old_xcr0 = vcpu->arch.xcr0;
951 u64 valid_bits;
952
953 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
954 if (index != XCR_XFEATURE_ENABLED_MASK)
955 return 1;
956 if (!(xcr0 & XFEATURE_MASK_FP))
957 return 1;
958 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
959 return 1;
960
961 /*
962 * Do not allow the guest to set bits that we do not support
963 * saving. However, xcr0 bit 0 is always set, even if the
964 * emulated CPU does not support XSAVE (see fx_init).
965 */
966 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
967 if (xcr0 & ~valid_bits)
968 return 1;
969
970 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
971 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
972 return 1;
973
974 if (xcr0 & XFEATURE_MASK_AVX512) {
975 if (!(xcr0 & XFEATURE_MASK_YMM))
976 return 1;
977 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
978 return 1;
979 }
980 vcpu->arch.xcr0 = xcr0;
981
982 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
983 kvm_update_cpuid_runtime(vcpu);
984 return 0;
985 }
986
987 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
988 {
989 if (static_call(kvm_x86_get_cpl)(vcpu) == 0)
990 return __kvm_set_xcr(vcpu, index, xcr);
991
992 return 1;
993 }
994 EXPORT_SYMBOL_GPL(kvm_set_xcr);
995
996 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
997 {
998 if (cr4 & cr4_reserved_bits)
999 return false;
1000
1001 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1002 return false;
1003
1004 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1005 }
1006 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
1007
1008 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1009 {
1010 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
1011 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
1012
1013 if (((cr4 ^ old_cr4) & mmu_role_bits) ||
1014 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1015 kvm_mmu_reset_context(vcpu);
1016 }
1017 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1018
1019 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1020 {
1021 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1022 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
1023 X86_CR4_SMEP;
1024
1025 if (!kvm_is_valid_cr4(vcpu, cr4))
1026 return 1;
1027
1028 if (is_long_mode(vcpu)) {
1029 if (!(cr4 & X86_CR4_PAE))
1030 return 1;
1031 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1032 return 1;
1033 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1034 && ((cr4 ^ old_cr4) & pdptr_bits)
1035 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
1036 kvm_read_cr3(vcpu)))
1037 return 1;
1038
1039 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1040 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1041 return 1;
1042
1043 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1044 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1045 return 1;
1046 }
1047
1048 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1049
1050 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1051
1052 return 0;
1053 }
1054 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1055
1056 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1057 {
1058 bool skip_tlb_flush = false;
1059 #ifdef CONFIG_X86_64
1060 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1061
1062 if (pcid_enabled) {
1063 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1064 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1065 }
1066 #endif
1067
1068 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1069 if (!skip_tlb_flush) {
1070 kvm_mmu_sync_roots(vcpu);
1071 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1072 }
1073 return 0;
1074 }
1075
1076 if (is_long_mode(vcpu) && kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1077 return 1;
1078 else if (is_pae_paging(vcpu) &&
1079 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1080 return 1;
1081
1082 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1083 vcpu->arch.cr3 = cr3;
1084 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1085
1086 return 0;
1087 }
1088 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1089
1090 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1091 {
1092 if (cr8 & CR8_RESERVED_BITS)
1093 return 1;
1094 if (lapic_in_kernel(vcpu))
1095 kvm_lapic_set_tpr(vcpu, cr8);
1096 else
1097 vcpu->arch.cr8 = cr8;
1098 return 0;
1099 }
1100 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1101
1102 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1103 {
1104 if (lapic_in_kernel(vcpu))
1105 return kvm_lapic_get_cr8(vcpu);
1106 else
1107 return vcpu->arch.cr8;
1108 }
1109 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1110
1111 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1112 {
1113 int i;
1114
1115 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1116 for (i = 0; i < KVM_NR_DB_REGS; i++)
1117 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1118 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1119 }
1120 }
1121
1122 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1123 {
1124 unsigned long dr7;
1125
1126 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1127 dr7 = vcpu->arch.guest_debug_dr7;
1128 else
1129 dr7 = vcpu->arch.dr7;
1130 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1131 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1132 if (dr7 & DR7_BP_EN_MASK)
1133 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1134 }
1135 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1136
1137 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1138 {
1139 u64 fixed = DR6_FIXED_1;
1140
1141 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1142 fixed |= DR6_RTM;
1143 return fixed;
1144 }
1145
1146 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1147 {
1148 size_t size = ARRAY_SIZE(vcpu->arch.db);
1149
1150 switch (dr) {
1151 case 0 ... 3:
1152 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1153 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1154 vcpu->arch.eff_db[dr] = val;
1155 break;
1156 case 4:
1157 case 6:
1158 if (!kvm_dr6_valid(val))
1159 return 1; /* #GP */
1160 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1161 break;
1162 case 5:
1163 default: /* 7 */
1164 if (!kvm_dr7_valid(val))
1165 return 1; /* #GP */
1166 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1167 kvm_update_dr7(vcpu);
1168 break;
1169 }
1170
1171 return 0;
1172 }
1173 EXPORT_SYMBOL_GPL(kvm_set_dr);
1174
1175 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1176 {
1177 size_t size = ARRAY_SIZE(vcpu->arch.db);
1178
1179 switch (dr) {
1180 case 0 ... 3:
1181 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1182 break;
1183 case 4:
1184 case 6:
1185 *val = vcpu->arch.dr6;
1186 break;
1187 case 5:
1188 default: /* 7 */
1189 *val = vcpu->arch.dr7;
1190 break;
1191 }
1192 }
1193 EXPORT_SYMBOL_GPL(kvm_get_dr);
1194
1195 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1196 {
1197 u32 ecx = kvm_rcx_read(vcpu);
1198 u64 data;
1199 int err;
1200
1201 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1202 if (err)
1203 return err;
1204 kvm_rax_write(vcpu, (u32)data);
1205 kvm_rdx_write(vcpu, data >> 32);
1206 return err;
1207 }
1208 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1209
1210 /*
1211 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1212 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1213 *
1214 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1215 * extract the supported MSRs from the related const lists.
1216 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1217 * capabilities of the host cpu. This capabilities test skips MSRs that are
1218 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1219 * may depend on host virtualization features rather than host cpu features.
1220 */
1221
1222 static const u32 msrs_to_save_all[] = {
1223 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1224 MSR_STAR,
1225 #ifdef CONFIG_X86_64
1226 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1227 #endif
1228 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1229 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1230 MSR_IA32_SPEC_CTRL,
1231 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1232 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1233 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1234 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1235 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1236 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1237 MSR_IA32_UMWAIT_CONTROL,
1238
1239 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1240 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1241 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1242 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1243 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1244 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1245 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1246 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1247 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1248 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1249 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1250 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1251 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1252 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1253 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1254 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1255 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1256 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1257 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1258 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1259 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1260 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1261 };
1262
1263 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1264 static unsigned num_msrs_to_save;
1265
1266 static const u32 emulated_msrs_all[] = {
1267 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1268 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1269 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1270 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1271 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1272 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1273 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1274 HV_X64_MSR_RESET,
1275 HV_X64_MSR_VP_INDEX,
1276 HV_X64_MSR_VP_RUNTIME,
1277 HV_X64_MSR_SCONTROL,
1278 HV_X64_MSR_STIMER0_CONFIG,
1279 HV_X64_MSR_VP_ASSIST_PAGE,
1280 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1281 HV_X64_MSR_TSC_EMULATION_STATUS,
1282 HV_X64_MSR_SYNDBG_OPTIONS,
1283 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1284 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1285 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1286
1287 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1288 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1289
1290 MSR_IA32_TSC_ADJUST,
1291 MSR_IA32_TSCDEADLINE,
1292 MSR_IA32_ARCH_CAPABILITIES,
1293 MSR_IA32_PERF_CAPABILITIES,
1294 MSR_IA32_MISC_ENABLE,
1295 MSR_IA32_MCG_STATUS,
1296 MSR_IA32_MCG_CTL,
1297 MSR_IA32_MCG_EXT_CTL,
1298 MSR_IA32_SMBASE,
1299 MSR_SMI_COUNT,
1300 MSR_PLATFORM_INFO,
1301 MSR_MISC_FEATURES_ENABLES,
1302 MSR_AMD64_VIRT_SPEC_CTRL,
1303 MSR_IA32_POWER_CTL,
1304 MSR_IA32_UCODE_REV,
1305
1306 /*
1307 * The following list leaves out MSRs whose values are determined
1308 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1309 * We always support the "true" VMX control MSRs, even if the host
1310 * processor does not, so I am putting these registers here rather
1311 * than in msrs_to_save_all.
1312 */
1313 MSR_IA32_VMX_BASIC,
1314 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1315 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1316 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1317 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1318 MSR_IA32_VMX_MISC,
1319 MSR_IA32_VMX_CR0_FIXED0,
1320 MSR_IA32_VMX_CR4_FIXED0,
1321 MSR_IA32_VMX_VMCS_ENUM,
1322 MSR_IA32_VMX_PROCBASED_CTLS2,
1323 MSR_IA32_VMX_EPT_VPID_CAP,
1324 MSR_IA32_VMX_VMFUNC,
1325
1326 MSR_K7_HWCR,
1327 MSR_KVM_POLL_CONTROL,
1328 };
1329
1330 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1331 static unsigned num_emulated_msrs;
1332
1333 /*
1334 * List of msr numbers which are used to expose MSR-based features that
1335 * can be used by a hypervisor to validate requested CPU features.
1336 */
1337 static const u32 msr_based_features_all[] = {
1338 MSR_IA32_VMX_BASIC,
1339 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1340 MSR_IA32_VMX_PINBASED_CTLS,
1341 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1342 MSR_IA32_VMX_PROCBASED_CTLS,
1343 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1344 MSR_IA32_VMX_EXIT_CTLS,
1345 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1346 MSR_IA32_VMX_ENTRY_CTLS,
1347 MSR_IA32_VMX_MISC,
1348 MSR_IA32_VMX_CR0_FIXED0,
1349 MSR_IA32_VMX_CR0_FIXED1,
1350 MSR_IA32_VMX_CR4_FIXED0,
1351 MSR_IA32_VMX_CR4_FIXED1,
1352 MSR_IA32_VMX_VMCS_ENUM,
1353 MSR_IA32_VMX_PROCBASED_CTLS2,
1354 MSR_IA32_VMX_EPT_VPID_CAP,
1355 MSR_IA32_VMX_VMFUNC,
1356
1357 MSR_F10H_DECFG,
1358 MSR_IA32_UCODE_REV,
1359 MSR_IA32_ARCH_CAPABILITIES,
1360 MSR_IA32_PERF_CAPABILITIES,
1361 };
1362
1363 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1364 static unsigned int num_msr_based_features;
1365
1366 static u64 kvm_get_arch_capabilities(void)
1367 {
1368 u64 data = 0;
1369
1370 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1371 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1372
1373 /*
1374 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1375 * the nested hypervisor runs with NX huge pages. If it is not,
1376 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1377 * L1 guests, so it need not worry about its own (L2) guests.
1378 */
1379 data |= ARCH_CAP_PSCHANGE_MC_NO;
1380
1381 /*
1382 * If we're doing cache flushes (either "always" or "cond")
1383 * we will do one whenever the guest does a vmlaunch/vmresume.
1384 * If an outer hypervisor is doing the cache flush for us
1385 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1386 * capability to the guest too, and if EPT is disabled we're not
1387 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1388 * require a nested hypervisor to do a flush of its own.
1389 */
1390 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1391 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1392
1393 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1394 data |= ARCH_CAP_RDCL_NO;
1395 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1396 data |= ARCH_CAP_SSB_NO;
1397 if (!boot_cpu_has_bug(X86_BUG_MDS))
1398 data |= ARCH_CAP_MDS_NO;
1399
1400 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1401 /*
1402 * If RTM=0 because the kernel has disabled TSX, the host might
1403 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1404 * and therefore knows that there cannot be TAA) but keep
1405 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1406 * and we want to allow migrating those guests to tsx=off hosts.
1407 */
1408 data &= ~ARCH_CAP_TAA_NO;
1409 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1410 data |= ARCH_CAP_TAA_NO;
1411 } else {
1412 /*
1413 * Nothing to do here; we emulate TSX_CTRL if present on the
1414 * host so the guest can choose between disabling TSX or
1415 * using VERW to clear CPU buffers.
1416 */
1417 }
1418
1419 return data;
1420 }
1421
1422 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1423 {
1424 switch (msr->index) {
1425 case MSR_IA32_ARCH_CAPABILITIES:
1426 msr->data = kvm_get_arch_capabilities();
1427 break;
1428 case MSR_IA32_UCODE_REV:
1429 rdmsrl_safe(msr->index, &msr->data);
1430 break;
1431 default:
1432 return static_call(kvm_x86_get_msr_feature)(msr);
1433 }
1434 return 0;
1435 }
1436
1437 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1438 {
1439 struct kvm_msr_entry msr;
1440 int r;
1441
1442 msr.index = index;
1443 r = kvm_get_msr_feature(&msr);
1444
1445 if (r == KVM_MSR_RET_INVALID) {
1446 /* Unconditionally clear the output for simplicity */
1447 *data = 0;
1448 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1449 r = 0;
1450 }
1451
1452 if (r)
1453 return r;
1454
1455 *data = msr.data;
1456
1457 return 0;
1458 }
1459
1460 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1461 {
1462 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1463 return false;
1464
1465 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1466 return false;
1467
1468 if (efer & (EFER_LME | EFER_LMA) &&
1469 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1470 return false;
1471
1472 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1473 return false;
1474
1475 return true;
1476
1477 }
1478 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1479 {
1480 if (efer & efer_reserved_bits)
1481 return false;
1482
1483 return __kvm_valid_efer(vcpu, efer);
1484 }
1485 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1486
1487 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1488 {
1489 u64 old_efer = vcpu->arch.efer;
1490 u64 efer = msr_info->data;
1491 int r;
1492
1493 if (efer & efer_reserved_bits)
1494 return 1;
1495
1496 if (!msr_info->host_initiated) {
1497 if (!__kvm_valid_efer(vcpu, efer))
1498 return 1;
1499
1500 if (is_paging(vcpu) &&
1501 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1502 return 1;
1503 }
1504
1505 efer &= ~EFER_LMA;
1506 efer |= vcpu->arch.efer & EFER_LMA;
1507
1508 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1509 if (r) {
1510 WARN_ON(r > 0);
1511 return r;
1512 }
1513
1514 /* Update reserved bits */
1515 if ((efer ^ old_efer) & EFER_NX)
1516 kvm_mmu_reset_context(vcpu);
1517
1518 return 0;
1519 }
1520
1521 void kvm_enable_efer_bits(u64 mask)
1522 {
1523 efer_reserved_bits &= ~mask;
1524 }
1525 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1526
1527 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1528 {
1529 struct kvm *kvm = vcpu->kvm;
1530 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
1531 u32 count = kvm->arch.msr_filter.count;
1532 u32 i;
1533 bool r = kvm->arch.msr_filter.default_allow;
1534 int idx;
1535
1536 /* MSR filtering not set up or x2APIC enabled, allow everything */
1537 if (!count || (index >= 0x800 && index <= 0x8ff))
1538 return true;
1539
1540 /* Prevent collision with set_msr_filter */
1541 idx = srcu_read_lock(&kvm->srcu);
1542
1543 for (i = 0; i < count; i++) {
1544 u32 start = ranges[i].base;
1545 u32 end = start + ranges[i].nmsrs;
1546 u32 flags = ranges[i].flags;
1547 unsigned long *bitmap = ranges[i].bitmap;
1548
1549 if ((index >= start) && (index < end) && (flags & type)) {
1550 r = !!test_bit(index - start, bitmap);
1551 break;
1552 }
1553 }
1554
1555 srcu_read_unlock(&kvm->srcu, idx);
1556
1557 return r;
1558 }
1559 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1560
1561 /*
1562 * Write @data into the MSR specified by @index. Select MSR specific fault
1563 * checks are bypassed if @host_initiated is %true.
1564 * Returns 0 on success, non-0 otherwise.
1565 * Assumes vcpu_load() was already called.
1566 */
1567 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1568 bool host_initiated)
1569 {
1570 struct msr_data msr;
1571
1572 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1573 return KVM_MSR_RET_FILTERED;
1574
1575 switch (index) {
1576 case MSR_FS_BASE:
1577 case MSR_GS_BASE:
1578 case MSR_KERNEL_GS_BASE:
1579 case MSR_CSTAR:
1580 case MSR_LSTAR:
1581 if (is_noncanonical_address(data, vcpu))
1582 return 1;
1583 break;
1584 case MSR_IA32_SYSENTER_EIP:
1585 case MSR_IA32_SYSENTER_ESP:
1586 /*
1587 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1588 * non-canonical address is written on Intel but not on
1589 * AMD (which ignores the top 32-bits, because it does
1590 * not implement 64-bit SYSENTER).
1591 *
1592 * 64-bit code should hence be able to write a non-canonical
1593 * value on AMD. Making the address canonical ensures that
1594 * vmentry does not fail on Intel after writing a non-canonical
1595 * value, and that something deterministic happens if the guest
1596 * invokes 64-bit SYSENTER.
1597 */
1598 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1599 }
1600
1601 msr.data = data;
1602 msr.index = index;
1603 msr.host_initiated = host_initiated;
1604
1605 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1606 }
1607
1608 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1609 u32 index, u64 data, bool host_initiated)
1610 {
1611 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1612
1613 if (ret == KVM_MSR_RET_INVALID)
1614 if (kvm_msr_ignored_check(vcpu, index, data, true))
1615 ret = 0;
1616
1617 return ret;
1618 }
1619
1620 /*
1621 * Read the MSR specified by @index into @data. Select MSR specific fault
1622 * checks are bypassed if @host_initiated is %true.
1623 * Returns 0 on success, non-0 otherwise.
1624 * Assumes vcpu_load() was already called.
1625 */
1626 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1627 bool host_initiated)
1628 {
1629 struct msr_data msr;
1630 int ret;
1631
1632 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1633 return KVM_MSR_RET_FILTERED;
1634
1635 msr.index = index;
1636 msr.host_initiated = host_initiated;
1637
1638 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1639 if (!ret)
1640 *data = msr.data;
1641 return ret;
1642 }
1643
1644 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1645 u32 index, u64 *data, bool host_initiated)
1646 {
1647 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1648
1649 if (ret == KVM_MSR_RET_INVALID) {
1650 /* Unconditionally clear *data for simplicity */
1651 *data = 0;
1652 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1653 ret = 0;
1654 }
1655
1656 return ret;
1657 }
1658
1659 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1660 {
1661 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1662 }
1663 EXPORT_SYMBOL_GPL(kvm_get_msr);
1664
1665 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1666 {
1667 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1668 }
1669 EXPORT_SYMBOL_GPL(kvm_set_msr);
1670
1671 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1672 {
1673 int err = vcpu->run->msr.error;
1674 if (!err) {
1675 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1676 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1677 }
1678
1679 return static_call(kvm_x86_complete_emulated_msr)(vcpu, err);
1680 }
1681
1682 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1683 {
1684 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1685 }
1686
1687 static u64 kvm_msr_reason(int r)
1688 {
1689 switch (r) {
1690 case KVM_MSR_RET_INVALID:
1691 return KVM_MSR_EXIT_REASON_UNKNOWN;
1692 case KVM_MSR_RET_FILTERED:
1693 return KVM_MSR_EXIT_REASON_FILTER;
1694 default:
1695 return KVM_MSR_EXIT_REASON_INVAL;
1696 }
1697 }
1698
1699 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1700 u32 exit_reason, u64 data,
1701 int (*completion)(struct kvm_vcpu *vcpu),
1702 int r)
1703 {
1704 u64 msr_reason = kvm_msr_reason(r);
1705
1706 /* Check if the user wanted to know about this MSR fault */
1707 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1708 return 0;
1709
1710 vcpu->run->exit_reason = exit_reason;
1711 vcpu->run->msr.error = 0;
1712 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1713 vcpu->run->msr.reason = msr_reason;
1714 vcpu->run->msr.index = index;
1715 vcpu->run->msr.data = data;
1716 vcpu->arch.complete_userspace_io = completion;
1717
1718 return 1;
1719 }
1720
1721 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1722 {
1723 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1724 complete_emulated_rdmsr, r);
1725 }
1726
1727 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1728 {
1729 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1730 complete_emulated_wrmsr, r);
1731 }
1732
1733 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1734 {
1735 u32 ecx = kvm_rcx_read(vcpu);
1736 u64 data;
1737 int r;
1738
1739 r = kvm_get_msr(vcpu, ecx, &data);
1740
1741 /* MSR read failed? See if we should ask user space */
1742 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1743 /* Bounce to user space */
1744 return 0;
1745 }
1746
1747 if (!r) {
1748 trace_kvm_msr_read(ecx, data);
1749
1750 kvm_rax_write(vcpu, data & -1u);
1751 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1752 } else {
1753 trace_kvm_msr_read_ex(ecx);
1754 }
1755
1756 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
1757 }
1758 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1759
1760 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1761 {
1762 u32 ecx = kvm_rcx_read(vcpu);
1763 u64 data = kvm_read_edx_eax(vcpu);
1764 int r;
1765
1766 r = kvm_set_msr(vcpu, ecx, data);
1767
1768 /* MSR write failed? See if we should ask user space */
1769 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r))
1770 /* Bounce to user space */
1771 return 0;
1772
1773 /* Signal all other negative errors to userspace */
1774 if (r < 0)
1775 return r;
1776
1777 if (!r)
1778 trace_kvm_msr_write(ecx, data);
1779 else
1780 trace_kvm_msr_write_ex(ecx, data);
1781
1782 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
1783 }
1784 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1785
1786 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1787 {
1788 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1789 xfer_to_guest_mode_work_pending();
1790 }
1791
1792 /*
1793 * The fast path for frequent and performance sensitive wrmsr emulation,
1794 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1795 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1796 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1797 * other cases which must be called after interrupts are enabled on the host.
1798 */
1799 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1800 {
1801 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1802 return 1;
1803
1804 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1805 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1806 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1807 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1808
1809 data &= ~(1 << 12);
1810 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1811 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1812 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1813 trace_kvm_apic_write(APIC_ICR, (u32)data);
1814 return 0;
1815 }
1816
1817 return 1;
1818 }
1819
1820 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1821 {
1822 if (!kvm_can_use_hv_timer(vcpu))
1823 return 1;
1824
1825 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1826 return 0;
1827 }
1828
1829 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1830 {
1831 u32 msr = kvm_rcx_read(vcpu);
1832 u64 data;
1833 fastpath_t ret = EXIT_FASTPATH_NONE;
1834
1835 switch (msr) {
1836 case APIC_BASE_MSR + (APIC_ICR >> 4):
1837 data = kvm_read_edx_eax(vcpu);
1838 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1839 kvm_skip_emulated_instruction(vcpu);
1840 ret = EXIT_FASTPATH_EXIT_HANDLED;
1841 }
1842 break;
1843 case MSR_IA32_TSCDEADLINE:
1844 data = kvm_read_edx_eax(vcpu);
1845 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1846 kvm_skip_emulated_instruction(vcpu);
1847 ret = EXIT_FASTPATH_REENTER_GUEST;
1848 }
1849 break;
1850 default:
1851 break;
1852 }
1853
1854 if (ret != EXIT_FASTPATH_NONE)
1855 trace_kvm_msr_write(msr, data);
1856
1857 return ret;
1858 }
1859 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1860
1861 /*
1862 * Adapt set_msr() to msr_io()'s calling convention
1863 */
1864 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1865 {
1866 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1867 }
1868
1869 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1870 {
1871 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1872 }
1873
1874 #ifdef CONFIG_X86_64
1875 struct pvclock_clock {
1876 int vclock_mode;
1877 u64 cycle_last;
1878 u64 mask;
1879 u32 mult;
1880 u32 shift;
1881 u64 base_cycles;
1882 u64 offset;
1883 };
1884
1885 struct pvclock_gtod_data {
1886 seqcount_t seq;
1887
1888 struct pvclock_clock clock; /* extract of a clocksource struct */
1889 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1890
1891 ktime_t offs_boot;
1892 u64 wall_time_sec;
1893 };
1894
1895 static struct pvclock_gtod_data pvclock_gtod_data;
1896
1897 static void update_pvclock_gtod(struct timekeeper *tk)
1898 {
1899 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1900
1901 write_seqcount_begin(&vdata->seq);
1902
1903 /* copy pvclock gtod data */
1904 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1905 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1906 vdata->clock.mask = tk->tkr_mono.mask;
1907 vdata->clock.mult = tk->tkr_mono.mult;
1908 vdata->clock.shift = tk->tkr_mono.shift;
1909 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1910 vdata->clock.offset = tk->tkr_mono.base;
1911
1912 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1913 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1914 vdata->raw_clock.mask = tk->tkr_raw.mask;
1915 vdata->raw_clock.mult = tk->tkr_raw.mult;
1916 vdata->raw_clock.shift = tk->tkr_raw.shift;
1917 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1918 vdata->raw_clock.offset = tk->tkr_raw.base;
1919
1920 vdata->wall_time_sec = tk->xtime_sec;
1921
1922 vdata->offs_boot = tk->offs_boot;
1923
1924 write_seqcount_end(&vdata->seq);
1925 }
1926
1927 static s64 get_kvmclock_base_ns(void)
1928 {
1929 /* Count up from boot time, but with the frequency of the raw clock. */
1930 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1931 }
1932 #else
1933 static s64 get_kvmclock_base_ns(void)
1934 {
1935 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1936 return ktime_get_boottime_ns();
1937 }
1938 #endif
1939
1940 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
1941 {
1942 int version;
1943 int r;
1944 struct pvclock_wall_clock wc;
1945 u32 wc_sec_hi;
1946 u64 wall_nsec;
1947
1948 if (!wall_clock)
1949 return;
1950
1951 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1952 if (r)
1953 return;
1954
1955 if (version & 1)
1956 ++version; /* first time write, random junk */
1957
1958 ++version;
1959
1960 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1961 return;
1962
1963 /*
1964 * The guest calculates current wall clock time by adding
1965 * system time (updated by kvm_guest_time_update below) to the
1966 * wall clock specified here. We do the reverse here.
1967 */
1968 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1969
1970 wc.nsec = do_div(wall_nsec, 1000000000);
1971 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1972 wc.version = version;
1973
1974 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1975
1976 if (sec_hi_ofs) {
1977 wc_sec_hi = wall_nsec >> 32;
1978 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
1979 &wc_sec_hi, sizeof(wc_sec_hi));
1980 }
1981
1982 version++;
1983 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1984 }
1985
1986 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1987 bool old_msr, bool host_initiated)
1988 {
1989 struct kvm_arch *ka = &vcpu->kvm->arch;
1990
1991 if (vcpu->vcpu_id == 0 && !host_initiated) {
1992 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
1993 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1994
1995 ka->boot_vcpu_runs_old_kvmclock = old_msr;
1996 }
1997
1998 vcpu->arch.time = system_time;
1999 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2000
2001 /* we verify if the enable bit is set... */
2002 vcpu->arch.pv_time_enabled = false;
2003 if (!(system_time & 1))
2004 return;
2005
2006 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2007 &vcpu->arch.pv_time, system_time & ~1ULL,
2008 sizeof(struct pvclock_vcpu_time_info)))
2009 vcpu->arch.pv_time_enabled = true;
2010
2011 return;
2012 }
2013
2014 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2015 {
2016 do_shl32_div32(dividend, divisor);
2017 return dividend;
2018 }
2019
2020 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2021 s8 *pshift, u32 *pmultiplier)
2022 {
2023 uint64_t scaled64;
2024 int32_t shift = 0;
2025 uint64_t tps64;
2026 uint32_t tps32;
2027
2028 tps64 = base_hz;
2029 scaled64 = scaled_hz;
2030 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2031 tps64 >>= 1;
2032 shift--;
2033 }
2034
2035 tps32 = (uint32_t)tps64;
2036 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2037 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2038 scaled64 >>= 1;
2039 else
2040 tps32 <<= 1;
2041 shift++;
2042 }
2043
2044 *pshift = shift;
2045 *pmultiplier = div_frac(scaled64, tps32);
2046 }
2047
2048 #ifdef CONFIG_X86_64
2049 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2050 #endif
2051
2052 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2053 static unsigned long max_tsc_khz;
2054
2055 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2056 {
2057 u64 v = (u64)khz * (1000000 + ppm);
2058 do_div(v, 1000000);
2059 return v;
2060 }
2061
2062 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2063 {
2064 u64 ratio;
2065
2066 /* Guest TSC same frequency as host TSC? */
2067 if (!scale) {
2068 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2069 return 0;
2070 }
2071
2072 /* TSC scaling supported? */
2073 if (!kvm_has_tsc_control) {
2074 if (user_tsc_khz > tsc_khz) {
2075 vcpu->arch.tsc_catchup = 1;
2076 vcpu->arch.tsc_always_catchup = 1;
2077 return 0;
2078 } else {
2079 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2080 return -1;
2081 }
2082 }
2083
2084 /* TSC scaling required - calculate ratio */
2085 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2086 user_tsc_khz, tsc_khz);
2087
2088 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2089 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2090 user_tsc_khz);
2091 return -1;
2092 }
2093
2094 vcpu->arch.tsc_scaling_ratio = ratio;
2095 return 0;
2096 }
2097
2098 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2099 {
2100 u32 thresh_lo, thresh_hi;
2101 int use_scaling = 0;
2102
2103 /* tsc_khz can be zero if TSC calibration fails */
2104 if (user_tsc_khz == 0) {
2105 /* set tsc_scaling_ratio to a safe value */
2106 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2107 return -1;
2108 }
2109
2110 /* Compute a scale to convert nanoseconds in TSC cycles */
2111 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2112 &vcpu->arch.virtual_tsc_shift,
2113 &vcpu->arch.virtual_tsc_mult);
2114 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2115
2116 /*
2117 * Compute the variation in TSC rate which is acceptable
2118 * within the range of tolerance and decide if the
2119 * rate being applied is within that bounds of the hardware
2120 * rate. If so, no scaling or compensation need be done.
2121 */
2122 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2123 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2124 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2125 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2126 use_scaling = 1;
2127 }
2128 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2129 }
2130
2131 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2132 {
2133 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2134 vcpu->arch.virtual_tsc_mult,
2135 vcpu->arch.virtual_tsc_shift);
2136 tsc += vcpu->arch.this_tsc_write;
2137 return tsc;
2138 }
2139
2140 static inline int gtod_is_based_on_tsc(int mode)
2141 {
2142 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2143 }
2144
2145 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2146 {
2147 #ifdef CONFIG_X86_64
2148 bool vcpus_matched;
2149 struct kvm_arch *ka = &vcpu->kvm->arch;
2150 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2151
2152 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2153 atomic_read(&vcpu->kvm->online_vcpus));
2154
2155 /*
2156 * Once the masterclock is enabled, always perform request in
2157 * order to update it.
2158 *
2159 * In order to enable masterclock, the host clocksource must be TSC
2160 * and the vcpus need to have matched TSCs. When that happens,
2161 * perform request to enable masterclock.
2162 */
2163 if (ka->use_master_clock ||
2164 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2165 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2166
2167 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2168 atomic_read(&vcpu->kvm->online_vcpus),
2169 ka->use_master_clock, gtod->clock.vclock_mode);
2170 #endif
2171 }
2172
2173 /*
2174 * Multiply tsc by a fixed point number represented by ratio.
2175 *
2176 * The most significant 64-N bits (mult) of ratio represent the
2177 * integral part of the fixed point number; the remaining N bits
2178 * (frac) represent the fractional part, ie. ratio represents a fixed
2179 * point number (mult + frac * 2^(-N)).
2180 *
2181 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2182 */
2183 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2184 {
2185 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2186 }
2187
2188 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2189 {
2190 u64 _tsc = tsc;
2191 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2192
2193 if (ratio != kvm_default_tsc_scaling_ratio)
2194 _tsc = __scale_tsc(ratio, tsc);
2195
2196 return _tsc;
2197 }
2198 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2199
2200 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2201 {
2202 u64 tsc;
2203
2204 tsc = kvm_scale_tsc(vcpu, rdtsc());
2205
2206 return target_tsc - tsc;
2207 }
2208
2209 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2210 {
2211 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2212 }
2213 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2214
2215 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2216 {
2217 vcpu->arch.l1_tsc_offset = offset;
2218 vcpu->arch.tsc_offset = static_call(kvm_x86_write_l1_tsc_offset)(vcpu, offset);
2219 }
2220
2221 static inline bool kvm_check_tsc_unstable(void)
2222 {
2223 #ifdef CONFIG_X86_64
2224 /*
2225 * TSC is marked unstable when we're running on Hyper-V,
2226 * 'TSC page' clocksource is good.
2227 */
2228 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2229 return false;
2230 #endif
2231 return check_tsc_unstable();
2232 }
2233
2234 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2235 {
2236 struct kvm *kvm = vcpu->kvm;
2237 u64 offset, ns, elapsed;
2238 unsigned long flags;
2239 bool matched;
2240 bool already_matched;
2241 bool synchronizing = false;
2242
2243 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2244 offset = kvm_compute_tsc_offset(vcpu, data);
2245 ns = get_kvmclock_base_ns();
2246 elapsed = ns - kvm->arch.last_tsc_nsec;
2247
2248 if (vcpu->arch.virtual_tsc_khz) {
2249 if (data == 0) {
2250 /*
2251 * detection of vcpu initialization -- need to sync
2252 * with other vCPUs. This particularly helps to keep
2253 * kvm_clock stable after CPU hotplug
2254 */
2255 synchronizing = true;
2256 } else {
2257 u64 tsc_exp = kvm->arch.last_tsc_write +
2258 nsec_to_cycles(vcpu, elapsed);
2259 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2260 /*
2261 * Special case: TSC write with a small delta (1 second)
2262 * of virtual cycle time against real time is
2263 * interpreted as an attempt to synchronize the CPU.
2264 */
2265 synchronizing = data < tsc_exp + tsc_hz &&
2266 data + tsc_hz > tsc_exp;
2267 }
2268 }
2269
2270 /*
2271 * For a reliable TSC, we can match TSC offsets, and for an unstable
2272 * TSC, we add elapsed time in this computation. We could let the
2273 * compensation code attempt to catch up if we fall behind, but
2274 * it's better to try to match offsets from the beginning.
2275 */
2276 if (synchronizing &&
2277 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2278 if (!kvm_check_tsc_unstable()) {
2279 offset = kvm->arch.cur_tsc_offset;
2280 } else {
2281 u64 delta = nsec_to_cycles(vcpu, elapsed);
2282 data += delta;
2283 offset = kvm_compute_tsc_offset(vcpu, data);
2284 }
2285 matched = true;
2286 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2287 } else {
2288 /*
2289 * We split periods of matched TSC writes into generations.
2290 * For each generation, we track the original measured
2291 * nanosecond time, offset, and write, so if TSCs are in
2292 * sync, we can match exact offset, and if not, we can match
2293 * exact software computation in compute_guest_tsc()
2294 *
2295 * These values are tracked in kvm->arch.cur_xxx variables.
2296 */
2297 kvm->arch.cur_tsc_generation++;
2298 kvm->arch.cur_tsc_nsec = ns;
2299 kvm->arch.cur_tsc_write = data;
2300 kvm->arch.cur_tsc_offset = offset;
2301 matched = false;
2302 }
2303
2304 /*
2305 * We also track th most recent recorded KHZ, write and time to
2306 * allow the matching interval to be extended at each write.
2307 */
2308 kvm->arch.last_tsc_nsec = ns;
2309 kvm->arch.last_tsc_write = data;
2310 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2311
2312 vcpu->arch.last_guest_tsc = data;
2313
2314 /* Keep track of which generation this VCPU has synchronized to */
2315 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2316 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2317 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2318
2319 kvm_vcpu_write_tsc_offset(vcpu, offset);
2320 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2321
2322 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2323 if (!matched) {
2324 kvm->arch.nr_vcpus_matched_tsc = 0;
2325 } else if (!already_matched) {
2326 kvm->arch.nr_vcpus_matched_tsc++;
2327 }
2328
2329 kvm_track_tsc_matching(vcpu);
2330 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2331 }
2332
2333 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2334 s64 adjustment)
2335 {
2336 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2337 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2338 }
2339
2340 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2341 {
2342 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2343 WARN_ON(adjustment < 0);
2344 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2345 adjust_tsc_offset_guest(vcpu, adjustment);
2346 }
2347
2348 #ifdef CONFIG_X86_64
2349
2350 static u64 read_tsc(void)
2351 {
2352 u64 ret = (u64)rdtsc_ordered();
2353 u64 last = pvclock_gtod_data.clock.cycle_last;
2354
2355 if (likely(ret >= last))
2356 return ret;
2357
2358 /*
2359 * GCC likes to generate cmov here, but this branch is extremely
2360 * predictable (it's just a function of time and the likely is
2361 * very likely) and there's a data dependence, so force GCC
2362 * to generate a branch instead. I don't barrier() because
2363 * we don't actually need a barrier, and if this function
2364 * ever gets inlined it will generate worse code.
2365 */
2366 asm volatile ("");
2367 return last;
2368 }
2369
2370 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2371 int *mode)
2372 {
2373 long v;
2374 u64 tsc_pg_val;
2375
2376 switch (clock->vclock_mode) {
2377 case VDSO_CLOCKMODE_HVCLOCK:
2378 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2379 tsc_timestamp);
2380 if (tsc_pg_val != U64_MAX) {
2381 /* TSC page valid */
2382 *mode = VDSO_CLOCKMODE_HVCLOCK;
2383 v = (tsc_pg_val - clock->cycle_last) &
2384 clock->mask;
2385 } else {
2386 /* TSC page invalid */
2387 *mode = VDSO_CLOCKMODE_NONE;
2388 }
2389 break;
2390 case VDSO_CLOCKMODE_TSC:
2391 *mode = VDSO_CLOCKMODE_TSC;
2392 *tsc_timestamp = read_tsc();
2393 v = (*tsc_timestamp - clock->cycle_last) &
2394 clock->mask;
2395 break;
2396 default:
2397 *mode = VDSO_CLOCKMODE_NONE;
2398 }
2399
2400 if (*mode == VDSO_CLOCKMODE_NONE)
2401 *tsc_timestamp = v = 0;
2402
2403 return v * clock->mult;
2404 }
2405
2406 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2407 {
2408 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2409 unsigned long seq;
2410 int mode;
2411 u64 ns;
2412
2413 do {
2414 seq = read_seqcount_begin(&gtod->seq);
2415 ns = gtod->raw_clock.base_cycles;
2416 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2417 ns >>= gtod->raw_clock.shift;
2418 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2419 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2420 *t = ns;
2421
2422 return mode;
2423 }
2424
2425 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2426 {
2427 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2428 unsigned long seq;
2429 int mode;
2430 u64 ns;
2431
2432 do {
2433 seq = read_seqcount_begin(&gtod->seq);
2434 ts->tv_sec = gtod->wall_time_sec;
2435 ns = gtod->clock.base_cycles;
2436 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2437 ns >>= gtod->clock.shift;
2438 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2439
2440 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2441 ts->tv_nsec = ns;
2442
2443 return mode;
2444 }
2445
2446 /* returns true if host is using TSC based clocksource */
2447 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2448 {
2449 /* checked again under seqlock below */
2450 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2451 return false;
2452
2453 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2454 tsc_timestamp));
2455 }
2456
2457 /* returns true if host is using TSC based clocksource */
2458 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2459 u64 *tsc_timestamp)
2460 {
2461 /* checked again under seqlock below */
2462 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2463 return false;
2464
2465 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2466 }
2467 #endif
2468
2469 /*
2470 *
2471 * Assuming a stable TSC across physical CPUS, and a stable TSC
2472 * across virtual CPUs, the following condition is possible.
2473 * Each numbered line represents an event visible to both
2474 * CPUs at the next numbered event.
2475 *
2476 * "timespecX" represents host monotonic time. "tscX" represents
2477 * RDTSC value.
2478 *
2479 * VCPU0 on CPU0 | VCPU1 on CPU1
2480 *
2481 * 1. read timespec0,tsc0
2482 * 2. | timespec1 = timespec0 + N
2483 * | tsc1 = tsc0 + M
2484 * 3. transition to guest | transition to guest
2485 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2486 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2487 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2488 *
2489 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2490 *
2491 * - ret0 < ret1
2492 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2493 * ...
2494 * - 0 < N - M => M < N
2495 *
2496 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2497 * always the case (the difference between two distinct xtime instances
2498 * might be smaller then the difference between corresponding TSC reads,
2499 * when updating guest vcpus pvclock areas).
2500 *
2501 * To avoid that problem, do not allow visibility of distinct
2502 * system_timestamp/tsc_timestamp values simultaneously: use a master
2503 * copy of host monotonic time values. Update that master copy
2504 * in lockstep.
2505 *
2506 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2507 *
2508 */
2509
2510 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2511 {
2512 #ifdef CONFIG_X86_64
2513 struct kvm_arch *ka = &kvm->arch;
2514 int vclock_mode;
2515 bool host_tsc_clocksource, vcpus_matched;
2516
2517 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2518 atomic_read(&kvm->online_vcpus));
2519
2520 /*
2521 * If the host uses TSC clock, then passthrough TSC as stable
2522 * to the guest.
2523 */
2524 host_tsc_clocksource = kvm_get_time_and_clockread(
2525 &ka->master_kernel_ns,
2526 &ka->master_cycle_now);
2527
2528 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2529 && !ka->backwards_tsc_observed
2530 && !ka->boot_vcpu_runs_old_kvmclock;
2531
2532 if (ka->use_master_clock)
2533 atomic_set(&kvm_guest_has_master_clock, 1);
2534
2535 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2536 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2537 vcpus_matched);
2538 #endif
2539 }
2540
2541 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2542 {
2543 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2544 }
2545
2546 static void kvm_gen_update_masterclock(struct kvm *kvm)
2547 {
2548 #ifdef CONFIG_X86_64
2549 int i;
2550 struct kvm_vcpu *vcpu;
2551 struct kvm_arch *ka = &kvm->arch;
2552
2553 spin_lock(&ka->pvclock_gtod_sync_lock);
2554 kvm_make_mclock_inprogress_request(kvm);
2555 /* no guest entries from this point */
2556 pvclock_update_vm_gtod_copy(kvm);
2557
2558 kvm_for_each_vcpu(i, vcpu, kvm)
2559 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2560
2561 /* guest entries allowed */
2562 kvm_for_each_vcpu(i, vcpu, kvm)
2563 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2564
2565 spin_unlock(&ka->pvclock_gtod_sync_lock);
2566 #endif
2567 }
2568
2569 u64 get_kvmclock_ns(struct kvm *kvm)
2570 {
2571 struct kvm_arch *ka = &kvm->arch;
2572 struct pvclock_vcpu_time_info hv_clock;
2573 u64 ret;
2574
2575 spin_lock(&ka->pvclock_gtod_sync_lock);
2576 if (!ka->use_master_clock) {
2577 spin_unlock(&ka->pvclock_gtod_sync_lock);
2578 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2579 }
2580
2581 hv_clock.tsc_timestamp = ka->master_cycle_now;
2582 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2583 spin_unlock(&ka->pvclock_gtod_sync_lock);
2584
2585 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2586 get_cpu();
2587
2588 if (__this_cpu_read(cpu_tsc_khz)) {
2589 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2590 &hv_clock.tsc_shift,
2591 &hv_clock.tsc_to_system_mul);
2592 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2593 } else
2594 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2595
2596 put_cpu();
2597
2598 return ret;
2599 }
2600
2601 static void kvm_setup_pvclock_page(struct kvm_vcpu *v,
2602 struct gfn_to_hva_cache *cache,
2603 unsigned int offset)
2604 {
2605 struct kvm_vcpu_arch *vcpu = &v->arch;
2606 struct pvclock_vcpu_time_info guest_hv_clock;
2607
2608 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache,
2609 &guest_hv_clock, offset, sizeof(guest_hv_clock))))
2610 return;
2611
2612 /* This VCPU is paused, but it's legal for a guest to read another
2613 * VCPU's kvmclock, so we really have to follow the specification where
2614 * it says that version is odd if data is being modified, and even after
2615 * it is consistent.
2616 *
2617 * Version field updates must be kept separate. This is because
2618 * kvm_write_guest_cached might use a "rep movs" instruction, and
2619 * writes within a string instruction are weakly ordered. So there
2620 * are three writes overall.
2621 *
2622 * As a small optimization, only write the version field in the first
2623 * and third write. The vcpu->pv_time cache is still valid, because the
2624 * version field is the first in the struct.
2625 */
2626 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2627
2628 if (guest_hv_clock.version & 1)
2629 ++guest_hv_clock.version; /* first time write, random junk */
2630
2631 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2632 kvm_write_guest_offset_cached(v->kvm, cache,
2633 &vcpu->hv_clock, offset,
2634 sizeof(vcpu->hv_clock.version));
2635
2636 smp_wmb();
2637
2638 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2639 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2640
2641 if (vcpu->pvclock_set_guest_stopped_request) {
2642 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2643 vcpu->pvclock_set_guest_stopped_request = false;
2644 }
2645
2646 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2647
2648 kvm_write_guest_offset_cached(v->kvm, cache,
2649 &vcpu->hv_clock, offset,
2650 sizeof(vcpu->hv_clock));
2651
2652 smp_wmb();
2653
2654 vcpu->hv_clock.version++;
2655 kvm_write_guest_offset_cached(v->kvm, cache,
2656 &vcpu->hv_clock, offset,
2657 sizeof(vcpu->hv_clock.version));
2658 }
2659
2660 static int kvm_guest_time_update(struct kvm_vcpu *v)
2661 {
2662 unsigned long flags, tgt_tsc_khz;
2663 struct kvm_vcpu_arch *vcpu = &v->arch;
2664 struct kvm_arch *ka = &v->kvm->arch;
2665 s64 kernel_ns;
2666 u64 tsc_timestamp, host_tsc;
2667 u8 pvclock_flags;
2668 bool use_master_clock;
2669
2670 kernel_ns = 0;
2671 host_tsc = 0;
2672
2673 /*
2674 * If the host uses TSC clock, then passthrough TSC as stable
2675 * to the guest.
2676 */
2677 spin_lock(&ka->pvclock_gtod_sync_lock);
2678 use_master_clock = ka->use_master_clock;
2679 if (use_master_clock) {
2680 host_tsc = ka->master_cycle_now;
2681 kernel_ns = ka->master_kernel_ns;
2682 }
2683 spin_unlock(&ka->pvclock_gtod_sync_lock);
2684
2685 /* Keep irq disabled to prevent changes to the clock */
2686 local_irq_save(flags);
2687 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2688 if (unlikely(tgt_tsc_khz == 0)) {
2689 local_irq_restore(flags);
2690 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2691 return 1;
2692 }
2693 if (!use_master_clock) {
2694 host_tsc = rdtsc();
2695 kernel_ns = get_kvmclock_base_ns();
2696 }
2697
2698 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2699
2700 /*
2701 * We may have to catch up the TSC to match elapsed wall clock
2702 * time for two reasons, even if kvmclock is used.
2703 * 1) CPU could have been running below the maximum TSC rate
2704 * 2) Broken TSC compensation resets the base at each VCPU
2705 * entry to avoid unknown leaps of TSC even when running
2706 * again on the same CPU. This may cause apparent elapsed
2707 * time to disappear, and the guest to stand still or run
2708 * very slowly.
2709 */
2710 if (vcpu->tsc_catchup) {
2711 u64 tsc = compute_guest_tsc(v, kernel_ns);
2712 if (tsc > tsc_timestamp) {
2713 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2714 tsc_timestamp = tsc;
2715 }
2716 }
2717
2718 local_irq_restore(flags);
2719
2720 /* With all the info we got, fill in the values */
2721
2722 if (kvm_has_tsc_control)
2723 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2724
2725 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2726 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2727 &vcpu->hv_clock.tsc_shift,
2728 &vcpu->hv_clock.tsc_to_system_mul);
2729 vcpu->hw_tsc_khz = tgt_tsc_khz;
2730 }
2731
2732 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2733 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2734 vcpu->last_guest_tsc = tsc_timestamp;
2735
2736 /* If the host uses TSC clocksource, then it is stable */
2737 pvclock_flags = 0;
2738 if (use_master_clock)
2739 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2740
2741 vcpu->hv_clock.flags = pvclock_flags;
2742
2743 if (vcpu->pv_time_enabled)
2744 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0);
2745 if (vcpu->xen.vcpu_info_set)
2746 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache,
2747 offsetof(struct compat_vcpu_info, time));
2748 if (vcpu->xen.vcpu_time_info_set)
2749 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0);
2750 if (v == kvm_get_vcpu(v->kvm, 0))
2751 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2752 return 0;
2753 }
2754
2755 /*
2756 * kvmclock updates which are isolated to a given vcpu, such as
2757 * vcpu->cpu migration, should not allow system_timestamp from
2758 * the rest of the vcpus to remain static. Otherwise ntp frequency
2759 * correction applies to one vcpu's system_timestamp but not
2760 * the others.
2761 *
2762 * So in those cases, request a kvmclock update for all vcpus.
2763 * We need to rate-limit these requests though, as they can
2764 * considerably slow guests that have a large number of vcpus.
2765 * The time for a remote vcpu to update its kvmclock is bound
2766 * by the delay we use to rate-limit the updates.
2767 */
2768
2769 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2770
2771 static void kvmclock_update_fn(struct work_struct *work)
2772 {
2773 int i;
2774 struct delayed_work *dwork = to_delayed_work(work);
2775 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2776 kvmclock_update_work);
2777 struct kvm *kvm = container_of(ka, struct kvm, arch);
2778 struct kvm_vcpu *vcpu;
2779
2780 kvm_for_each_vcpu(i, vcpu, kvm) {
2781 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2782 kvm_vcpu_kick(vcpu);
2783 }
2784 }
2785
2786 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2787 {
2788 struct kvm *kvm = v->kvm;
2789
2790 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2791 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2792 KVMCLOCK_UPDATE_DELAY);
2793 }
2794
2795 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2796
2797 static void kvmclock_sync_fn(struct work_struct *work)
2798 {
2799 struct delayed_work *dwork = to_delayed_work(work);
2800 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2801 kvmclock_sync_work);
2802 struct kvm *kvm = container_of(ka, struct kvm, arch);
2803
2804 if (!kvmclock_periodic_sync)
2805 return;
2806
2807 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2808 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2809 KVMCLOCK_SYNC_PERIOD);
2810 }
2811
2812 /*
2813 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2814 */
2815 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2816 {
2817 /* McStatusWrEn enabled? */
2818 if (guest_cpuid_is_amd_or_hygon(vcpu))
2819 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2820
2821 return false;
2822 }
2823
2824 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2825 {
2826 u64 mcg_cap = vcpu->arch.mcg_cap;
2827 unsigned bank_num = mcg_cap & 0xff;
2828 u32 msr = msr_info->index;
2829 u64 data = msr_info->data;
2830
2831 switch (msr) {
2832 case MSR_IA32_MCG_STATUS:
2833 vcpu->arch.mcg_status = data;
2834 break;
2835 case MSR_IA32_MCG_CTL:
2836 if (!(mcg_cap & MCG_CTL_P) &&
2837 (data || !msr_info->host_initiated))
2838 return 1;
2839 if (data != 0 && data != ~(u64)0)
2840 return 1;
2841 vcpu->arch.mcg_ctl = data;
2842 break;
2843 default:
2844 if (msr >= MSR_IA32_MC0_CTL &&
2845 msr < MSR_IA32_MCx_CTL(bank_num)) {
2846 u32 offset = array_index_nospec(
2847 msr - MSR_IA32_MC0_CTL,
2848 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2849
2850 /* only 0 or all 1s can be written to IA32_MCi_CTL
2851 * some Linux kernels though clear bit 10 in bank 4 to
2852 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2853 * this to avoid an uncatched #GP in the guest
2854 */
2855 if ((offset & 0x3) == 0 &&
2856 data != 0 && (data | (1 << 10)) != ~(u64)0)
2857 return -1;
2858
2859 /* MCi_STATUS */
2860 if (!msr_info->host_initiated &&
2861 (offset & 0x3) == 1 && data != 0) {
2862 if (!can_set_mci_status(vcpu))
2863 return -1;
2864 }
2865
2866 vcpu->arch.mce_banks[offset] = data;
2867 break;
2868 }
2869 return 1;
2870 }
2871 return 0;
2872 }
2873
2874 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2875 {
2876 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2877
2878 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2879 }
2880
2881 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2882 {
2883 gpa_t gpa = data & ~0x3f;
2884
2885 /* Bits 4:5 are reserved, Should be zero */
2886 if (data & 0x30)
2887 return 1;
2888
2889 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
2890 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
2891 return 1;
2892
2893 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
2894 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
2895 return 1;
2896
2897 if (!lapic_in_kernel(vcpu))
2898 return data ? 1 : 0;
2899
2900 vcpu->arch.apf.msr_en_val = data;
2901
2902 if (!kvm_pv_async_pf_enabled(vcpu)) {
2903 kvm_clear_async_pf_completion_queue(vcpu);
2904 kvm_async_pf_hash_reset(vcpu);
2905 return 0;
2906 }
2907
2908 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2909 sizeof(u64)))
2910 return 1;
2911
2912 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2913 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2914
2915 kvm_async_pf_wakeup_all(vcpu);
2916
2917 return 0;
2918 }
2919
2920 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2921 {
2922 /* Bits 8-63 are reserved */
2923 if (data >> 8)
2924 return 1;
2925
2926 if (!lapic_in_kernel(vcpu))
2927 return 1;
2928
2929 vcpu->arch.apf.msr_int_val = data;
2930
2931 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2932
2933 return 0;
2934 }
2935
2936 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2937 {
2938 vcpu->arch.pv_time_enabled = false;
2939 vcpu->arch.time = 0;
2940 }
2941
2942 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2943 {
2944 ++vcpu->stat.tlb_flush;
2945 static_call(kvm_x86_tlb_flush_all)(vcpu);
2946 }
2947
2948 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2949 {
2950 ++vcpu->stat.tlb_flush;
2951 static_call(kvm_x86_tlb_flush_guest)(vcpu);
2952 }
2953
2954 static void record_steal_time(struct kvm_vcpu *vcpu)
2955 {
2956 struct kvm_host_map map;
2957 struct kvm_steal_time *st;
2958
2959 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2960 return;
2961
2962 /* -EAGAIN is returned in atomic context so we can just return. */
2963 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2964 &map, &vcpu->arch.st.cache, false))
2965 return;
2966
2967 st = map.hva +
2968 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2969
2970 /*
2971 * Doing a TLB flush here, on the guest's behalf, can avoid
2972 * expensive IPIs.
2973 */
2974 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
2975 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2976 st->preempted & KVM_VCPU_FLUSH_TLB);
2977 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2978 kvm_vcpu_flush_tlb_guest(vcpu);
2979 }
2980
2981 vcpu->arch.st.preempted = 0;
2982
2983 if (st->version & 1)
2984 st->version += 1; /* first time write, random junk */
2985
2986 st->version += 1;
2987
2988 smp_wmb();
2989
2990 st->steal += current->sched_info.run_delay -
2991 vcpu->arch.st.last_steal;
2992 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2993
2994 smp_wmb();
2995
2996 st->version += 1;
2997
2998 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2999 }
3000
3001 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3002 {
3003 bool pr = false;
3004 u32 msr = msr_info->index;
3005 u64 data = msr_info->data;
3006
3007 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3008 return kvm_xen_write_hypercall_page(vcpu, data);
3009
3010 switch (msr) {
3011 case MSR_AMD64_NB_CFG:
3012 case MSR_IA32_UCODE_WRITE:
3013 case MSR_VM_HSAVE_PA:
3014 case MSR_AMD64_PATCH_LOADER:
3015 case MSR_AMD64_BU_CFG2:
3016 case MSR_AMD64_DC_CFG:
3017 case MSR_F15H_EX_CFG:
3018 break;
3019
3020 case MSR_IA32_UCODE_REV:
3021 if (msr_info->host_initiated)
3022 vcpu->arch.microcode_version = data;
3023 break;
3024 case MSR_IA32_ARCH_CAPABILITIES:
3025 if (!msr_info->host_initiated)
3026 return 1;
3027 vcpu->arch.arch_capabilities = data;
3028 break;
3029 case MSR_IA32_PERF_CAPABILITIES: {
3030 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3031
3032 if (!msr_info->host_initiated)
3033 return 1;
3034 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3035 return 1;
3036 if (data & ~msr_ent.data)
3037 return 1;
3038
3039 vcpu->arch.perf_capabilities = data;
3040
3041 return 0;
3042 }
3043 case MSR_EFER:
3044 return set_efer(vcpu, msr_info);
3045 case MSR_K7_HWCR:
3046 data &= ~(u64)0x40; /* ignore flush filter disable */
3047 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3048 data &= ~(u64)0x8; /* ignore TLB cache disable */
3049
3050 /* Handle McStatusWrEn */
3051 if (data == BIT_ULL(18)) {
3052 vcpu->arch.msr_hwcr = data;
3053 } else if (data != 0) {
3054 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3055 data);
3056 return 1;
3057 }
3058 break;
3059 case MSR_FAM10H_MMIO_CONF_BASE:
3060 if (data != 0) {
3061 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3062 "0x%llx\n", data);
3063 return 1;
3064 }
3065 break;
3066 case 0x200 ... 0x2ff:
3067 return kvm_mtrr_set_msr(vcpu, msr, data);
3068 case MSR_IA32_APICBASE:
3069 return kvm_set_apic_base(vcpu, msr_info);
3070 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3071 return kvm_x2apic_msr_write(vcpu, msr, data);
3072 case MSR_IA32_TSCDEADLINE:
3073 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3074 break;
3075 case MSR_IA32_TSC_ADJUST:
3076 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3077 if (!msr_info->host_initiated) {
3078 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3079 adjust_tsc_offset_guest(vcpu, adj);
3080 }
3081 vcpu->arch.ia32_tsc_adjust_msr = data;
3082 }
3083 break;
3084 case MSR_IA32_MISC_ENABLE:
3085 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3086 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3087 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3088 return 1;
3089 vcpu->arch.ia32_misc_enable_msr = data;
3090 kvm_update_cpuid_runtime(vcpu);
3091 } else {
3092 vcpu->arch.ia32_misc_enable_msr = data;
3093 }
3094 break;
3095 case MSR_IA32_SMBASE:
3096 if (!msr_info->host_initiated)
3097 return 1;
3098 vcpu->arch.smbase = data;
3099 break;
3100 case MSR_IA32_POWER_CTL:
3101 vcpu->arch.msr_ia32_power_ctl = data;
3102 break;
3103 case MSR_IA32_TSC:
3104 if (msr_info->host_initiated) {
3105 kvm_synchronize_tsc(vcpu, data);
3106 } else {
3107 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3108 adjust_tsc_offset_guest(vcpu, adj);
3109 vcpu->arch.ia32_tsc_adjust_msr += adj;
3110 }
3111 break;
3112 case MSR_IA32_XSS:
3113 if (!msr_info->host_initiated &&
3114 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3115 return 1;
3116 /*
3117 * KVM supports exposing PT to the guest, but does not support
3118 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3119 * XSAVES/XRSTORS to save/restore PT MSRs.
3120 */
3121 if (data & ~supported_xss)
3122 return 1;
3123 vcpu->arch.ia32_xss = data;
3124 break;
3125 case MSR_SMI_COUNT:
3126 if (!msr_info->host_initiated)
3127 return 1;
3128 vcpu->arch.smi_count = data;
3129 break;
3130 case MSR_KVM_WALL_CLOCK_NEW:
3131 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3132 return 1;
3133
3134 vcpu->kvm->arch.wall_clock = data;
3135 kvm_write_wall_clock(vcpu->kvm, data, 0);
3136 break;
3137 case MSR_KVM_WALL_CLOCK:
3138 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3139 return 1;
3140
3141 vcpu->kvm->arch.wall_clock = data;
3142 kvm_write_wall_clock(vcpu->kvm, data, 0);
3143 break;
3144 case MSR_KVM_SYSTEM_TIME_NEW:
3145 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3146 return 1;
3147
3148 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3149 break;
3150 case MSR_KVM_SYSTEM_TIME:
3151 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3152 return 1;
3153
3154 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3155 break;
3156 case MSR_KVM_ASYNC_PF_EN:
3157 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3158 return 1;
3159
3160 if (kvm_pv_enable_async_pf(vcpu, data))
3161 return 1;
3162 break;
3163 case MSR_KVM_ASYNC_PF_INT:
3164 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3165 return 1;
3166
3167 if (kvm_pv_enable_async_pf_int(vcpu, data))
3168 return 1;
3169 break;
3170 case MSR_KVM_ASYNC_PF_ACK:
3171 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3172 return 1;
3173 if (data & 0x1) {
3174 vcpu->arch.apf.pageready_pending = false;
3175 kvm_check_async_pf_completion(vcpu);
3176 }
3177 break;
3178 case MSR_KVM_STEAL_TIME:
3179 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3180 return 1;
3181
3182 if (unlikely(!sched_info_on()))
3183 return 1;
3184
3185 if (data & KVM_STEAL_RESERVED_MASK)
3186 return 1;
3187
3188 vcpu->arch.st.msr_val = data;
3189
3190 if (!(data & KVM_MSR_ENABLED))
3191 break;
3192
3193 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3194
3195 break;
3196 case MSR_KVM_PV_EOI_EN:
3197 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3198 return 1;
3199
3200 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3201 return 1;
3202 break;
3203
3204 case MSR_KVM_POLL_CONTROL:
3205 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3206 return 1;
3207
3208 /* only enable bit supported */
3209 if (data & (-1ULL << 1))
3210 return 1;
3211
3212 vcpu->arch.msr_kvm_poll_control = data;
3213 break;
3214
3215 case MSR_IA32_MCG_CTL:
3216 case MSR_IA32_MCG_STATUS:
3217 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3218 return set_msr_mce(vcpu, msr_info);
3219
3220 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3221 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3222 pr = true;
3223 fallthrough;
3224 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3225 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3226 if (kvm_pmu_is_valid_msr(vcpu, msr))
3227 return kvm_pmu_set_msr(vcpu, msr_info);
3228
3229 if (pr || data != 0)
3230 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3231 "0x%x data 0x%llx\n", msr, data);
3232 break;
3233 case MSR_K7_CLK_CTL:
3234 /*
3235 * Ignore all writes to this no longer documented MSR.
3236 * Writes are only relevant for old K7 processors,
3237 * all pre-dating SVM, but a recommended workaround from
3238 * AMD for these chips. It is possible to specify the
3239 * affected processor models on the command line, hence
3240 * the need to ignore the workaround.
3241 */
3242 break;
3243 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3244 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3245 case HV_X64_MSR_SYNDBG_OPTIONS:
3246 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3247 case HV_X64_MSR_CRASH_CTL:
3248 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3249 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3250 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3251 case HV_X64_MSR_TSC_EMULATION_STATUS:
3252 return kvm_hv_set_msr_common(vcpu, msr, data,
3253 msr_info->host_initiated);
3254 case MSR_IA32_BBL_CR_CTL3:
3255 /* Drop writes to this legacy MSR -- see rdmsr
3256 * counterpart for further detail.
3257 */
3258 if (report_ignored_msrs)
3259 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3260 msr, data);
3261 break;
3262 case MSR_AMD64_OSVW_ID_LENGTH:
3263 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3264 return 1;
3265 vcpu->arch.osvw.length = data;
3266 break;
3267 case MSR_AMD64_OSVW_STATUS:
3268 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3269 return 1;
3270 vcpu->arch.osvw.status = data;
3271 break;
3272 case MSR_PLATFORM_INFO:
3273 if (!msr_info->host_initiated ||
3274 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3275 cpuid_fault_enabled(vcpu)))
3276 return 1;
3277 vcpu->arch.msr_platform_info = data;
3278 break;
3279 case MSR_MISC_FEATURES_ENABLES:
3280 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3281 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3282 !supports_cpuid_fault(vcpu)))
3283 return 1;
3284 vcpu->arch.msr_misc_features_enables = data;
3285 break;
3286 default:
3287 if (kvm_pmu_is_valid_msr(vcpu, msr))
3288 return kvm_pmu_set_msr(vcpu, msr_info);
3289 return KVM_MSR_RET_INVALID;
3290 }
3291 return 0;
3292 }
3293 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3294
3295 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3296 {
3297 u64 data;
3298 u64 mcg_cap = vcpu->arch.mcg_cap;
3299 unsigned bank_num = mcg_cap & 0xff;
3300
3301 switch (msr) {
3302 case MSR_IA32_P5_MC_ADDR:
3303 case MSR_IA32_P5_MC_TYPE:
3304 data = 0;
3305 break;
3306 case MSR_IA32_MCG_CAP:
3307 data = vcpu->arch.mcg_cap;
3308 break;
3309 case MSR_IA32_MCG_CTL:
3310 if (!(mcg_cap & MCG_CTL_P) && !host)
3311 return 1;
3312 data = vcpu->arch.mcg_ctl;
3313 break;
3314 case MSR_IA32_MCG_STATUS:
3315 data = vcpu->arch.mcg_status;
3316 break;
3317 default:
3318 if (msr >= MSR_IA32_MC0_CTL &&
3319 msr < MSR_IA32_MCx_CTL(bank_num)) {
3320 u32 offset = array_index_nospec(
3321 msr - MSR_IA32_MC0_CTL,
3322 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3323
3324 data = vcpu->arch.mce_banks[offset];
3325 break;
3326 }
3327 return 1;
3328 }
3329 *pdata = data;
3330 return 0;
3331 }
3332
3333 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3334 {
3335 switch (msr_info->index) {
3336 case MSR_IA32_PLATFORM_ID:
3337 case MSR_IA32_EBL_CR_POWERON:
3338 case MSR_IA32_LASTBRANCHFROMIP:
3339 case MSR_IA32_LASTBRANCHTOIP:
3340 case MSR_IA32_LASTINTFROMIP:
3341 case MSR_IA32_LASTINTTOIP:
3342 case MSR_K8_SYSCFG:
3343 case MSR_K8_TSEG_ADDR:
3344 case MSR_K8_TSEG_MASK:
3345 case MSR_VM_HSAVE_PA:
3346 case MSR_K8_INT_PENDING_MSG:
3347 case MSR_AMD64_NB_CFG:
3348 case MSR_FAM10H_MMIO_CONF_BASE:
3349 case MSR_AMD64_BU_CFG2:
3350 case MSR_IA32_PERF_CTL:
3351 case MSR_AMD64_DC_CFG:
3352 case MSR_F15H_EX_CFG:
3353 /*
3354 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3355 * limit) MSRs. Just return 0, as we do not want to expose the host
3356 * data here. Do not conditionalize this on CPUID, as KVM does not do
3357 * so for existing CPU-specific MSRs.
3358 */
3359 case MSR_RAPL_POWER_UNIT:
3360 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3361 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3362 case MSR_PKG_ENERGY_STATUS: /* Total package */
3363 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3364 msr_info->data = 0;
3365 break;
3366 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3367 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3368 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3369 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3370 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3371 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3372 return kvm_pmu_get_msr(vcpu, msr_info);
3373 msr_info->data = 0;
3374 break;
3375 case MSR_IA32_UCODE_REV:
3376 msr_info->data = vcpu->arch.microcode_version;
3377 break;
3378 case MSR_IA32_ARCH_CAPABILITIES:
3379 if (!msr_info->host_initiated &&
3380 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3381 return 1;
3382 msr_info->data = vcpu->arch.arch_capabilities;
3383 break;
3384 case MSR_IA32_PERF_CAPABILITIES:
3385 if (!msr_info->host_initiated &&
3386 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3387 return 1;
3388 msr_info->data = vcpu->arch.perf_capabilities;
3389 break;
3390 case MSR_IA32_POWER_CTL:
3391 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3392 break;
3393 case MSR_IA32_TSC: {
3394 /*
3395 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3396 * even when not intercepted. AMD manual doesn't explicitly
3397 * state this but appears to behave the same.
3398 *
3399 * On userspace reads and writes, however, we unconditionally
3400 * return L1's TSC value to ensure backwards-compatible
3401 * behavior for migration.
3402 */
3403 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3404 vcpu->arch.tsc_offset;
3405
3406 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3407 break;
3408 }
3409 case MSR_MTRRcap:
3410 case 0x200 ... 0x2ff:
3411 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3412 case 0xcd: /* fsb frequency */
3413 msr_info->data = 3;
3414 break;
3415 /*
3416 * MSR_EBC_FREQUENCY_ID
3417 * Conservative value valid for even the basic CPU models.
3418 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3419 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3420 * and 266MHz for model 3, or 4. Set Core Clock
3421 * Frequency to System Bus Frequency Ratio to 1 (bits
3422 * 31:24) even though these are only valid for CPU
3423 * models > 2, however guests may end up dividing or
3424 * multiplying by zero otherwise.
3425 */
3426 case MSR_EBC_FREQUENCY_ID:
3427 msr_info->data = 1 << 24;
3428 break;
3429 case MSR_IA32_APICBASE:
3430 msr_info->data = kvm_get_apic_base(vcpu);
3431 break;
3432 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3433 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3434 case MSR_IA32_TSCDEADLINE:
3435 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3436 break;
3437 case MSR_IA32_TSC_ADJUST:
3438 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3439 break;
3440 case MSR_IA32_MISC_ENABLE:
3441 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3442 break;
3443 case MSR_IA32_SMBASE:
3444 if (!msr_info->host_initiated)
3445 return 1;
3446 msr_info->data = vcpu->arch.smbase;
3447 break;
3448 case MSR_SMI_COUNT:
3449 msr_info->data = vcpu->arch.smi_count;
3450 break;
3451 case MSR_IA32_PERF_STATUS:
3452 /* TSC increment by tick */
3453 msr_info->data = 1000ULL;
3454 /* CPU multiplier */
3455 msr_info->data |= (((uint64_t)4ULL) << 40);
3456 break;
3457 case MSR_EFER:
3458 msr_info->data = vcpu->arch.efer;
3459 break;
3460 case MSR_KVM_WALL_CLOCK:
3461 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3462 return 1;
3463
3464 msr_info->data = vcpu->kvm->arch.wall_clock;
3465 break;
3466 case MSR_KVM_WALL_CLOCK_NEW:
3467 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3468 return 1;
3469
3470 msr_info->data = vcpu->kvm->arch.wall_clock;
3471 break;
3472 case MSR_KVM_SYSTEM_TIME:
3473 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3474 return 1;
3475
3476 msr_info->data = vcpu->arch.time;
3477 break;
3478 case MSR_KVM_SYSTEM_TIME_NEW:
3479 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3480 return 1;
3481
3482 msr_info->data = vcpu->arch.time;
3483 break;
3484 case MSR_KVM_ASYNC_PF_EN:
3485 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3486 return 1;
3487
3488 msr_info->data = vcpu->arch.apf.msr_en_val;
3489 break;
3490 case MSR_KVM_ASYNC_PF_INT:
3491 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3492 return 1;
3493
3494 msr_info->data = vcpu->arch.apf.msr_int_val;
3495 break;
3496 case MSR_KVM_ASYNC_PF_ACK:
3497 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3498 return 1;
3499
3500 msr_info->data = 0;
3501 break;
3502 case MSR_KVM_STEAL_TIME:
3503 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3504 return 1;
3505
3506 msr_info->data = vcpu->arch.st.msr_val;
3507 break;
3508 case MSR_KVM_PV_EOI_EN:
3509 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3510 return 1;
3511
3512 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3513 break;
3514 case MSR_KVM_POLL_CONTROL:
3515 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3516 return 1;
3517
3518 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3519 break;
3520 case MSR_IA32_P5_MC_ADDR:
3521 case MSR_IA32_P5_MC_TYPE:
3522 case MSR_IA32_MCG_CAP:
3523 case MSR_IA32_MCG_CTL:
3524 case MSR_IA32_MCG_STATUS:
3525 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3526 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3527 msr_info->host_initiated);
3528 case MSR_IA32_XSS:
3529 if (!msr_info->host_initiated &&
3530 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3531 return 1;
3532 msr_info->data = vcpu->arch.ia32_xss;
3533 break;
3534 case MSR_K7_CLK_CTL:
3535 /*
3536 * Provide expected ramp-up count for K7. All other
3537 * are set to zero, indicating minimum divisors for
3538 * every field.
3539 *
3540 * This prevents guest kernels on AMD host with CPU
3541 * type 6, model 8 and higher from exploding due to
3542 * the rdmsr failing.
3543 */
3544 msr_info->data = 0x20000000;
3545 break;
3546 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3547 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3548 case HV_X64_MSR_SYNDBG_OPTIONS:
3549 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3550 case HV_X64_MSR_CRASH_CTL:
3551 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3552 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3553 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3554 case HV_X64_MSR_TSC_EMULATION_STATUS:
3555 return kvm_hv_get_msr_common(vcpu,
3556 msr_info->index, &msr_info->data,
3557 msr_info->host_initiated);
3558 case MSR_IA32_BBL_CR_CTL3:
3559 /* This legacy MSR exists but isn't fully documented in current
3560 * silicon. It is however accessed by winxp in very narrow
3561 * scenarios where it sets bit #19, itself documented as
3562 * a "reserved" bit. Best effort attempt to source coherent
3563 * read data here should the balance of the register be
3564 * interpreted by the guest:
3565 *
3566 * L2 cache control register 3: 64GB range, 256KB size,
3567 * enabled, latency 0x1, configured
3568 */
3569 msr_info->data = 0xbe702111;
3570 break;
3571 case MSR_AMD64_OSVW_ID_LENGTH:
3572 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3573 return 1;
3574 msr_info->data = vcpu->arch.osvw.length;
3575 break;
3576 case MSR_AMD64_OSVW_STATUS:
3577 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3578 return 1;
3579 msr_info->data = vcpu->arch.osvw.status;
3580 break;
3581 case MSR_PLATFORM_INFO:
3582 if (!msr_info->host_initiated &&
3583 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3584 return 1;
3585 msr_info->data = vcpu->arch.msr_platform_info;
3586 break;
3587 case MSR_MISC_FEATURES_ENABLES:
3588 msr_info->data = vcpu->arch.msr_misc_features_enables;
3589 break;
3590 case MSR_K7_HWCR:
3591 msr_info->data = vcpu->arch.msr_hwcr;
3592 break;
3593 default:
3594 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3595 return kvm_pmu_get_msr(vcpu, msr_info);
3596 return KVM_MSR_RET_INVALID;
3597 }
3598 return 0;
3599 }
3600 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3601
3602 /*
3603 * Read or write a bunch of msrs. All parameters are kernel addresses.
3604 *
3605 * @return number of msrs set successfully.
3606 */
3607 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3608 struct kvm_msr_entry *entries,
3609 int (*do_msr)(struct kvm_vcpu *vcpu,
3610 unsigned index, u64 *data))
3611 {
3612 int i;
3613
3614 for (i = 0; i < msrs->nmsrs; ++i)
3615 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3616 break;
3617
3618 return i;
3619 }
3620
3621 /*
3622 * Read or write a bunch of msrs. Parameters are user addresses.
3623 *
3624 * @return number of msrs set successfully.
3625 */
3626 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3627 int (*do_msr)(struct kvm_vcpu *vcpu,
3628 unsigned index, u64 *data),
3629 int writeback)
3630 {
3631 struct kvm_msrs msrs;
3632 struct kvm_msr_entry *entries;
3633 int r, n;
3634 unsigned size;
3635
3636 r = -EFAULT;
3637 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3638 goto out;
3639
3640 r = -E2BIG;
3641 if (msrs.nmsrs >= MAX_IO_MSRS)
3642 goto out;
3643
3644 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3645 entries = memdup_user(user_msrs->entries, size);
3646 if (IS_ERR(entries)) {
3647 r = PTR_ERR(entries);
3648 goto out;
3649 }
3650
3651 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3652 if (r < 0)
3653 goto out_free;
3654
3655 r = -EFAULT;
3656 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3657 goto out_free;
3658
3659 r = n;
3660
3661 out_free:
3662 kfree(entries);
3663 out:
3664 return r;
3665 }
3666
3667 static inline bool kvm_can_mwait_in_guest(void)
3668 {
3669 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3670 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3671 boot_cpu_has(X86_FEATURE_ARAT);
3672 }
3673
3674 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
3675 struct kvm_cpuid2 __user *cpuid_arg)
3676 {
3677 struct kvm_cpuid2 cpuid;
3678 int r;
3679
3680 r = -EFAULT;
3681 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3682 return r;
3683
3684 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3685 if (r)
3686 return r;
3687
3688 r = -EFAULT;
3689 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3690 return r;
3691
3692 return 0;
3693 }
3694
3695 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3696 {
3697 int r = 0;
3698
3699 switch (ext) {
3700 case KVM_CAP_IRQCHIP:
3701 case KVM_CAP_HLT:
3702 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3703 case KVM_CAP_SET_TSS_ADDR:
3704 case KVM_CAP_EXT_CPUID:
3705 case KVM_CAP_EXT_EMUL_CPUID:
3706 case KVM_CAP_CLOCKSOURCE:
3707 case KVM_CAP_PIT:
3708 case KVM_CAP_NOP_IO_DELAY:
3709 case KVM_CAP_MP_STATE:
3710 case KVM_CAP_SYNC_MMU:
3711 case KVM_CAP_USER_NMI:
3712 case KVM_CAP_REINJECT_CONTROL:
3713 case KVM_CAP_IRQ_INJECT_STATUS:
3714 case KVM_CAP_IOEVENTFD:
3715 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3716 case KVM_CAP_PIT2:
3717 case KVM_CAP_PIT_STATE2:
3718 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3719 case KVM_CAP_VCPU_EVENTS:
3720 case KVM_CAP_HYPERV:
3721 case KVM_CAP_HYPERV_VAPIC:
3722 case KVM_CAP_HYPERV_SPIN:
3723 case KVM_CAP_HYPERV_SYNIC:
3724 case KVM_CAP_HYPERV_SYNIC2:
3725 case KVM_CAP_HYPERV_VP_INDEX:
3726 case KVM_CAP_HYPERV_EVENTFD:
3727 case KVM_CAP_HYPERV_TLBFLUSH:
3728 case KVM_CAP_HYPERV_SEND_IPI:
3729 case KVM_CAP_HYPERV_CPUID:
3730 case KVM_CAP_SYS_HYPERV_CPUID:
3731 case KVM_CAP_PCI_SEGMENT:
3732 case KVM_CAP_DEBUGREGS:
3733 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3734 case KVM_CAP_XSAVE:
3735 case KVM_CAP_ASYNC_PF:
3736 case KVM_CAP_ASYNC_PF_INT:
3737 case KVM_CAP_GET_TSC_KHZ:
3738 case KVM_CAP_KVMCLOCK_CTRL:
3739 case KVM_CAP_READONLY_MEM:
3740 case KVM_CAP_HYPERV_TIME:
3741 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3742 case KVM_CAP_TSC_DEADLINE_TIMER:
3743 case KVM_CAP_DISABLE_QUIRKS:
3744 case KVM_CAP_SET_BOOT_CPU_ID:
3745 case KVM_CAP_SPLIT_IRQCHIP:
3746 case KVM_CAP_IMMEDIATE_EXIT:
3747 case KVM_CAP_PMU_EVENT_FILTER:
3748 case KVM_CAP_GET_MSR_FEATURES:
3749 case KVM_CAP_MSR_PLATFORM_INFO:
3750 case KVM_CAP_EXCEPTION_PAYLOAD:
3751 case KVM_CAP_SET_GUEST_DEBUG:
3752 case KVM_CAP_LAST_CPU:
3753 case KVM_CAP_X86_USER_SPACE_MSR:
3754 case KVM_CAP_X86_MSR_FILTER:
3755 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
3756 r = 1;
3757 break;
3758 case KVM_CAP_XEN_HVM:
3759 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
3760 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
3761 KVM_XEN_HVM_CONFIG_SHARED_INFO;
3762 break;
3763 case KVM_CAP_SYNC_REGS:
3764 r = KVM_SYNC_X86_VALID_FIELDS;
3765 break;
3766 case KVM_CAP_ADJUST_CLOCK:
3767 r = KVM_CLOCK_TSC_STABLE;
3768 break;
3769 case KVM_CAP_X86_DISABLE_EXITS:
3770 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3771 KVM_X86_DISABLE_EXITS_CSTATE;
3772 if(kvm_can_mwait_in_guest())
3773 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3774 break;
3775 case KVM_CAP_X86_SMM:
3776 /* SMBASE is usually relocated above 1M on modern chipsets,
3777 * and SMM handlers might indeed rely on 4G segment limits,
3778 * so do not report SMM to be available if real mode is
3779 * emulated via vm86 mode. Still, do not go to great lengths
3780 * to avoid userspace's usage of the feature, because it is a
3781 * fringe case that is not enabled except via specific settings
3782 * of the module parameters.
3783 */
3784 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
3785 break;
3786 case KVM_CAP_VAPIC:
3787 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)();
3788 break;
3789 case KVM_CAP_NR_VCPUS:
3790 r = KVM_SOFT_MAX_VCPUS;
3791 break;
3792 case KVM_CAP_MAX_VCPUS:
3793 r = KVM_MAX_VCPUS;
3794 break;
3795 case KVM_CAP_MAX_VCPU_ID:
3796 r = KVM_MAX_VCPU_ID;
3797 break;
3798 case KVM_CAP_PV_MMU: /* obsolete */
3799 r = 0;
3800 break;
3801 case KVM_CAP_MCE:
3802 r = KVM_MAX_MCE_BANKS;
3803 break;
3804 case KVM_CAP_XCRS:
3805 r = boot_cpu_has(X86_FEATURE_XSAVE);
3806 break;
3807 case KVM_CAP_TSC_CONTROL:
3808 r = kvm_has_tsc_control;
3809 break;
3810 case KVM_CAP_X2APIC_API:
3811 r = KVM_X2APIC_API_VALID_FLAGS;
3812 break;
3813 case KVM_CAP_NESTED_STATE:
3814 r = kvm_x86_ops.nested_ops->get_state ?
3815 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3816 break;
3817 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3818 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3819 break;
3820 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3821 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3822 break;
3823 case KVM_CAP_SMALLER_MAXPHYADDR:
3824 r = (int) allow_smaller_maxphyaddr;
3825 break;
3826 case KVM_CAP_STEAL_TIME:
3827 r = sched_info_on();
3828 break;
3829 case KVM_CAP_X86_BUS_LOCK_EXIT:
3830 if (kvm_has_bus_lock_exit)
3831 r = KVM_BUS_LOCK_DETECTION_OFF |
3832 KVM_BUS_LOCK_DETECTION_EXIT;
3833 else
3834 r = 0;
3835 break;
3836 default:
3837 break;
3838 }
3839 return r;
3840
3841 }
3842
3843 long kvm_arch_dev_ioctl(struct file *filp,
3844 unsigned int ioctl, unsigned long arg)
3845 {
3846 void __user *argp = (void __user *)arg;
3847 long r;
3848
3849 switch (ioctl) {
3850 case KVM_GET_MSR_INDEX_LIST: {
3851 struct kvm_msr_list __user *user_msr_list = argp;
3852 struct kvm_msr_list msr_list;
3853 unsigned n;
3854
3855 r = -EFAULT;
3856 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3857 goto out;
3858 n = msr_list.nmsrs;
3859 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3860 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3861 goto out;
3862 r = -E2BIG;
3863 if (n < msr_list.nmsrs)
3864 goto out;
3865 r = -EFAULT;
3866 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3867 num_msrs_to_save * sizeof(u32)))
3868 goto out;
3869 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3870 &emulated_msrs,
3871 num_emulated_msrs * sizeof(u32)))
3872 goto out;
3873 r = 0;
3874 break;
3875 }
3876 case KVM_GET_SUPPORTED_CPUID:
3877 case KVM_GET_EMULATED_CPUID: {
3878 struct kvm_cpuid2 __user *cpuid_arg = argp;
3879 struct kvm_cpuid2 cpuid;
3880
3881 r = -EFAULT;
3882 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3883 goto out;
3884
3885 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3886 ioctl);
3887 if (r)
3888 goto out;
3889
3890 r = -EFAULT;
3891 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3892 goto out;
3893 r = 0;
3894 break;
3895 }
3896 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3897 r = -EFAULT;
3898 if (copy_to_user(argp, &kvm_mce_cap_supported,
3899 sizeof(kvm_mce_cap_supported)))
3900 goto out;
3901 r = 0;
3902 break;
3903 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3904 struct kvm_msr_list __user *user_msr_list = argp;
3905 struct kvm_msr_list msr_list;
3906 unsigned int n;
3907
3908 r = -EFAULT;
3909 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3910 goto out;
3911 n = msr_list.nmsrs;
3912 msr_list.nmsrs = num_msr_based_features;
3913 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3914 goto out;
3915 r = -E2BIG;
3916 if (n < msr_list.nmsrs)
3917 goto out;
3918 r = -EFAULT;
3919 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3920 num_msr_based_features * sizeof(u32)))
3921 goto out;
3922 r = 0;
3923 break;
3924 }
3925 case KVM_GET_MSRS:
3926 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3927 break;
3928 case KVM_GET_SUPPORTED_HV_CPUID:
3929 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
3930 break;
3931 default:
3932 r = -EINVAL;
3933 break;
3934 }
3935 out:
3936 return r;
3937 }
3938
3939 static void wbinvd_ipi(void *garbage)
3940 {
3941 wbinvd();
3942 }
3943
3944 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3945 {
3946 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3947 }
3948
3949 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3950 {
3951 /* Address WBINVD may be executed by guest */
3952 if (need_emulate_wbinvd(vcpu)) {
3953 if (static_call(kvm_x86_has_wbinvd_exit)())
3954 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3955 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3956 smp_call_function_single(vcpu->cpu,
3957 wbinvd_ipi, NULL, 1);
3958 }
3959
3960 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
3961
3962 /* Save host pkru register if supported */
3963 vcpu->arch.host_pkru = read_pkru();
3964
3965 /* Apply any externally detected TSC adjustments (due to suspend) */
3966 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3967 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3968 vcpu->arch.tsc_offset_adjustment = 0;
3969 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3970 }
3971
3972 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3973 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3974 rdtsc() - vcpu->arch.last_host_tsc;
3975 if (tsc_delta < 0)
3976 mark_tsc_unstable("KVM discovered backwards TSC");
3977
3978 if (kvm_check_tsc_unstable()) {
3979 u64 offset = kvm_compute_tsc_offset(vcpu,
3980 vcpu->arch.last_guest_tsc);
3981 kvm_vcpu_write_tsc_offset(vcpu, offset);
3982 vcpu->arch.tsc_catchup = 1;
3983 }
3984
3985 if (kvm_lapic_hv_timer_in_use(vcpu))
3986 kvm_lapic_restart_hv_timer(vcpu);
3987
3988 /*
3989 * On a host with synchronized TSC, there is no need to update
3990 * kvmclock on vcpu->cpu migration
3991 */
3992 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3993 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3994 if (vcpu->cpu != cpu)
3995 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3996 vcpu->cpu = cpu;
3997 }
3998
3999 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4000 }
4001
4002 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4003 {
4004 struct kvm_host_map map;
4005 struct kvm_steal_time *st;
4006 int idx;
4007
4008 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4009 return;
4010
4011 if (vcpu->arch.st.preempted)
4012 return;
4013
4014 /*
4015 * Take the srcu lock as memslots will be accessed to check the gfn
4016 * cache generation against the memslots generation.
4017 */
4018 idx = srcu_read_lock(&vcpu->kvm->srcu);
4019
4020 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
4021 &vcpu->arch.st.cache, true))
4022 goto out;
4023
4024 st = map.hva +
4025 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
4026
4027 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4028
4029 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
4030
4031 out:
4032 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4033 }
4034
4035 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4036 {
4037 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4038 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4039
4040 kvm_steal_time_set_preempted(vcpu);
4041 static_call(kvm_x86_vcpu_put)(vcpu);
4042 vcpu->arch.last_host_tsc = rdtsc();
4043 /*
4044 * If userspace has set any breakpoints or watchpoints, dr6 is restored
4045 * on every vmexit, but if not, we might have a stale dr6 from the
4046 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
4047 */
4048 set_debugreg(0, 6);
4049 }
4050
4051 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4052 struct kvm_lapic_state *s)
4053 {
4054 if (vcpu->arch.apicv_active)
4055 static_call(kvm_x86_sync_pir_to_irr)(vcpu);
4056
4057 return kvm_apic_get_state(vcpu, s);
4058 }
4059
4060 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4061 struct kvm_lapic_state *s)
4062 {
4063 int r;
4064
4065 r = kvm_apic_set_state(vcpu, s);
4066 if (r)
4067 return r;
4068 update_cr8_intercept(vcpu);
4069
4070 return 0;
4071 }
4072
4073 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4074 {
4075 /*
4076 * We can accept userspace's request for interrupt injection
4077 * as long as we have a place to store the interrupt number.
4078 * The actual injection will happen when the CPU is able to
4079 * deliver the interrupt.
4080 */
4081 if (kvm_cpu_has_extint(vcpu))
4082 return false;
4083
4084 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4085 return (!lapic_in_kernel(vcpu) ||
4086 kvm_apic_accept_pic_intr(vcpu));
4087 }
4088
4089 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4090 {
4091 return kvm_arch_interrupt_allowed(vcpu) &&
4092 kvm_cpu_accept_dm_intr(vcpu);
4093 }
4094
4095 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4096 struct kvm_interrupt *irq)
4097 {
4098 if (irq->irq >= KVM_NR_INTERRUPTS)
4099 return -EINVAL;
4100
4101 if (!irqchip_in_kernel(vcpu->kvm)) {
4102 kvm_queue_interrupt(vcpu, irq->irq, false);
4103 kvm_make_request(KVM_REQ_EVENT, vcpu);
4104 return 0;
4105 }
4106
4107 /*
4108 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4109 * fail for in-kernel 8259.
4110 */
4111 if (pic_in_kernel(vcpu->kvm))
4112 return -ENXIO;
4113
4114 if (vcpu->arch.pending_external_vector != -1)
4115 return -EEXIST;
4116
4117 vcpu->arch.pending_external_vector = irq->irq;
4118 kvm_make_request(KVM_REQ_EVENT, vcpu);
4119 return 0;
4120 }
4121
4122 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4123 {
4124 kvm_inject_nmi(vcpu);
4125
4126 return 0;
4127 }
4128
4129 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4130 {
4131 kvm_make_request(KVM_REQ_SMI, vcpu);
4132
4133 return 0;
4134 }
4135
4136 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4137 struct kvm_tpr_access_ctl *tac)
4138 {
4139 if (tac->flags)
4140 return -EINVAL;
4141 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4142 return 0;
4143 }
4144
4145 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4146 u64 mcg_cap)
4147 {
4148 int r;
4149 unsigned bank_num = mcg_cap & 0xff, bank;
4150
4151 r = -EINVAL;
4152 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4153 goto out;
4154 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4155 goto out;
4156 r = 0;
4157 vcpu->arch.mcg_cap = mcg_cap;
4158 /* Init IA32_MCG_CTL to all 1s */
4159 if (mcg_cap & MCG_CTL_P)
4160 vcpu->arch.mcg_ctl = ~(u64)0;
4161 /* Init IA32_MCi_CTL to all 1s */
4162 for (bank = 0; bank < bank_num; bank++)
4163 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4164
4165 static_call(kvm_x86_setup_mce)(vcpu);
4166 out:
4167 return r;
4168 }
4169
4170 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4171 struct kvm_x86_mce *mce)
4172 {
4173 u64 mcg_cap = vcpu->arch.mcg_cap;
4174 unsigned bank_num = mcg_cap & 0xff;
4175 u64 *banks = vcpu->arch.mce_banks;
4176
4177 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4178 return -EINVAL;
4179 /*
4180 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4181 * reporting is disabled
4182 */
4183 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4184 vcpu->arch.mcg_ctl != ~(u64)0)
4185 return 0;
4186 banks += 4 * mce->bank;
4187 /*
4188 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4189 * reporting is disabled for the bank
4190 */
4191 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4192 return 0;
4193 if (mce->status & MCI_STATUS_UC) {
4194 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4195 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4196 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4197 return 0;
4198 }
4199 if (banks[1] & MCI_STATUS_VAL)
4200 mce->status |= MCI_STATUS_OVER;
4201 banks[2] = mce->addr;
4202 banks[3] = mce->misc;
4203 vcpu->arch.mcg_status = mce->mcg_status;
4204 banks[1] = mce->status;
4205 kvm_queue_exception(vcpu, MC_VECTOR);
4206 } else if (!(banks[1] & MCI_STATUS_VAL)
4207 || !(banks[1] & MCI_STATUS_UC)) {
4208 if (banks[1] & MCI_STATUS_VAL)
4209 mce->status |= MCI_STATUS_OVER;
4210 banks[2] = mce->addr;
4211 banks[3] = mce->misc;
4212 banks[1] = mce->status;
4213 } else
4214 banks[1] |= MCI_STATUS_OVER;
4215 return 0;
4216 }
4217
4218 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4219 struct kvm_vcpu_events *events)
4220 {
4221 process_nmi(vcpu);
4222
4223 if (kvm_check_request(KVM_REQ_SMI, vcpu))
4224 process_smi(vcpu);
4225
4226 /*
4227 * In guest mode, payload delivery should be deferred,
4228 * so that the L1 hypervisor can intercept #PF before
4229 * CR2 is modified (or intercept #DB before DR6 is
4230 * modified under nVMX). Unless the per-VM capability,
4231 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4232 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4233 * opportunistically defer the exception payload, deliver it if the
4234 * capability hasn't been requested before processing a
4235 * KVM_GET_VCPU_EVENTS.
4236 */
4237 if (!vcpu->kvm->arch.exception_payload_enabled &&
4238 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4239 kvm_deliver_exception_payload(vcpu);
4240
4241 /*
4242 * The API doesn't provide the instruction length for software
4243 * exceptions, so don't report them. As long as the guest RIP
4244 * isn't advanced, we should expect to encounter the exception
4245 * again.
4246 */
4247 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4248 events->exception.injected = 0;
4249 events->exception.pending = 0;
4250 } else {
4251 events->exception.injected = vcpu->arch.exception.injected;
4252 events->exception.pending = vcpu->arch.exception.pending;
4253 /*
4254 * For ABI compatibility, deliberately conflate
4255 * pending and injected exceptions when
4256 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4257 */
4258 if (!vcpu->kvm->arch.exception_payload_enabled)
4259 events->exception.injected |=
4260 vcpu->arch.exception.pending;
4261 }
4262 events->exception.nr = vcpu->arch.exception.nr;
4263 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4264 events->exception.error_code = vcpu->arch.exception.error_code;
4265 events->exception_has_payload = vcpu->arch.exception.has_payload;
4266 events->exception_payload = vcpu->arch.exception.payload;
4267
4268 events->interrupt.injected =
4269 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4270 events->interrupt.nr = vcpu->arch.interrupt.nr;
4271 events->interrupt.soft = 0;
4272 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
4273
4274 events->nmi.injected = vcpu->arch.nmi_injected;
4275 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4276 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
4277 events->nmi.pad = 0;
4278
4279 events->sipi_vector = 0; /* never valid when reporting to user space */
4280
4281 events->smi.smm = is_smm(vcpu);
4282 events->smi.pending = vcpu->arch.smi_pending;
4283 events->smi.smm_inside_nmi =
4284 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4285 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4286
4287 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4288 | KVM_VCPUEVENT_VALID_SHADOW
4289 | KVM_VCPUEVENT_VALID_SMM);
4290 if (vcpu->kvm->arch.exception_payload_enabled)
4291 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4292
4293 memset(&events->reserved, 0, sizeof(events->reserved));
4294 }
4295
4296 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4297
4298 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4299 struct kvm_vcpu_events *events)
4300 {
4301 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4302 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4303 | KVM_VCPUEVENT_VALID_SHADOW
4304 | KVM_VCPUEVENT_VALID_SMM
4305 | KVM_VCPUEVENT_VALID_PAYLOAD))
4306 return -EINVAL;
4307
4308 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4309 if (!vcpu->kvm->arch.exception_payload_enabled)
4310 return -EINVAL;
4311 if (events->exception.pending)
4312 events->exception.injected = 0;
4313 else
4314 events->exception_has_payload = 0;
4315 } else {
4316 events->exception.pending = 0;
4317 events->exception_has_payload = 0;
4318 }
4319
4320 if ((events->exception.injected || events->exception.pending) &&
4321 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4322 return -EINVAL;
4323
4324 /* INITs are latched while in SMM */
4325 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4326 (events->smi.smm || events->smi.pending) &&
4327 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4328 return -EINVAL;
4329
4330 process_nmi(vcpu);
4331 vcpu->arch.exception.injected = events->exception.injected;
4332 vcpu->arch.exception.pending = events->exception.pending;
4333 vcpu->arch.exception.nr = events->exception.nr;
4334 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4335 vcpu->arch.exception.error_code = events->exception.error_code;
4336 vcpu->arch.exception.has_payload = events->exception_has_payload;
4337 vcpu->arch.exception.payload = events->exception_payload;
4338
4339 vcpu->arch.interrupt.injected = events->interrupt.injected;
4340 vcpu->arch.interrupt.nr = events->interrupt.nr;
4341 vcpu->arch.interrupt.soft = events->interrupt.soft;
4342 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4343 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
4344 events->interrupt.shadow);
4345
4346 vcpu->arch.nmi_injected = events->nmi.injected;
4347 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4348 vcpu->arch.nmi_pending = events->nmi.pending;
4349 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
4350
4351 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4352 lapic_in_kernel(vcpu))
4353 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4354
4355 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4356 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4357 if (events->smi.smm)
4358 vcpu->arch.hflags |= HF_SMM_MASK;
4359 else
4360 vcpu->arch.hflags &= ~HF_SMM_MASK;
4361 kvm_smm_changed(vcpu);
4362 }
4363
4364 vcpu->arch.smi_pending = events->smi.pending;
4365
4366 if (events->smi.smm) {
4367 if (events->smi.smm_inside_nmi)
4368 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4369 else
4370 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4371 }
4372
4373 if (lapic_in_kernel(vcpu)) {
4374 if (events->smi.latched_init)
4375 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4376 else
4377 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4378 }
4379 }
4380
4381 kvm_make_request(KVM_REQ_EVENT, vcpu);
4382
4383 return 0;
4384 }
4385
4386 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4387 struct kvm_debugregs *dbgregs)
4388 {
4389 unsigned long val;
4390
4391 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4392 kvm_get_dr(vcpu, 6, &val);
4393 dbgregs->dr6 = val;
4394 dbgregs->dr7 = vcpu->arch.dr7;
4395 dbgregs->flags = 0;
4396 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4397 }
4398
4399 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4400 struct kvm_debugregs *dbgregs)
4401 {
4402 if (dbgregs->flags)
4403 return -EINVAL;
4404
4405 if (!kvm_dr6_valid(dbgregs->dr6))
4406 return -EINVAL;
4407 if (!kvm_dr7_valid(dbgregs->dr7))
4408 return -EINVAL;
4409
4410 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4411 kvm_update_dr0123(vcpu);
4412 vcpu->arch.dr6 = dbgregs->dr6;
4413 vcpu->arch.dr7 = dbgregs->dr7;
4414 kvm_update_dr7(vcpu);
4415
4416 return 0;
4417 }
4418
4419 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4420
4421 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4422 {
4423 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4424 u64 xstate_bv = xsave->header.xfeatures;
4425 u64 valid;
4426
4427 /*
4428 * Copy legacy XSAVE area, to avoid complications with CPUID
4429 * leaves 0 and 1 in the loop below.
4430 */
4431 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4432
4433 /* Set XSTATE_BV */
4434 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4435 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4436
4437 /*
4438 * Copy each region from the possibly compacted offset to the
4439 * non-compacted offset.
4440 */
4441 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4442 while (valid) {
4443 u64 xfeature_mask = valid & -valid;
4444 int xfeature_nr = fls64(xfeature_mask) - 1;
4445 void *src = get_xsave_addr(xsave, xfeature_nr);
4446
4447 if (src) {
4448 u32 size, offset, ecx, edx;
4449 cpuid_count(XSTATE_CPUID, xfeature_nr,
4450 &size, &offset, &ecx, &edx);
4451 if (xfeature_nr == XFEATURE_PKRU)
4452 memcpy(dest + offset, &vcpu->arch.pkru,
4453 sizeof(vcpu->arch.pkru));
4454 else
4455 memcpy(dest + offset, src, size);
4456
4457 }
4458
4459 valid -= xfeature_mask;
4460 }
4461 }
4462
4463 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4464 {
4465 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4466 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4467 u64 valid;
4468
4469 /*
4470 * Copy legacy XSAVE area, to avoid complications with CPUID
4471 * leaves 0 and 1 in the loop below.
4472 */
4473 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4474
4475 /* Set XSTATE_BV and possibly XCOMP_BV. */
4476 xsave->header.xfeatures = xstate_bv;
4477 if (boot_cpu_has(X86_FEATURE_XSAVES))
4478 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4479
4480 /*
4481 * Copy each region from the non-compacted offset to the
4482 * possibly compacted offset.
4483 */
4484 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4485 while (valid) {
4486 u64 xfeature_mask = valid & -valid;
4487 int xfeature_nr = fls64(xfeature_mask) - 1;
4488 void *dest = get_xsave_addr(xsave, xfeature_nr);
4489
4490 if (dest) {
4491 u32 size, offset, ecx, edx;
4492 cpuid_count(XSTATE_CPUID, xfeature_nr,
4493 &size, &offset, &ecx, &edx);
4494 if (xfeature_nr == XFEATURE_PKRU)
4495 memcpy(&vcpu->arch.pkru, src + offset,
4496 sizeof(vcpu->arch.pkru));
4497 else
4498 memcpy(dest, src + offset, size);
4499 }
4500
4501 valid -= xfeature_mask;
4502 }
4503 }
4504
4505 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4506 struct kvm_xsave *guest_xsave)
4507 {
4508 if (!vcpu->arch.guest_fpu)
4509 return;
4510
4511 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4512 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4513 fill_xsave((u8 *) guest_xsave->region, vcpu);
4514 } else {
4515 memcpy(guest_xsave->region,
4516 &vcpu->arch.guest_fpu->state.fxsave,
4517 sizeof(struct fxregs_state));
4518 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4519 XFEATURE_MASK_FPSSE;
4520 }
4521 }
4522
4523 #define XSAVE_MXCSR_OFFSET 24
4524
4525 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4526 struct kvm_xsave *guest_xsave)
4527 {
4528 u64 xstate_bv;
4529 u32 mxcsr;
4530
4531 if (!vcpu->arch.guest_fpu)
4532 return 0;
4533
4534 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4535 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4536
4537 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4538 /*
4539 * Here we allow setting states that are not present in
4540 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4541 * with old userspace.
4542 */
4543 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4544 return -EINVAL;
4545 load_xsave(vcpu, (u8 *)guest_xsave->region);
4546 } else {
4547 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4548 mxcsr & ~mxcsr_feature_mask)
4549 return -EINVAL;
4550 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4551 guest_xsave->region, sizeof(struct fxregs_state));
4552 }
4553 return 0;
4554 }
4555
4556 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4557 struct kvm_xcrs *guest_xcrs)
4558 {
4559 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4560 guest_xcrs->nr_xcrs = 0;
4561 return;
4562 }
4563
4564 guest_xcrs->nr_xcrs = 1;
4565 guest_xcrs->flags = 0;
4566 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4567 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4568 }
4569
4570 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4571 struct kvm_xcrs *guest_xcrs)
4572 {
4573 int i, r = 0;
4574
4575 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4576 return -EINVAL;
4577
4578 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4579 return -EINVAL;
4580
4581 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4582 /* Only support XCR0 currently */
4583 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4584 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4585 guest_xcrs->xcrs[i].value);
4586 break;
4587 }
4588 if (r)
4589 r = -EINVAL;
4590 return r;
4591 }
4592
4593 /*
4594 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4595 * stopped by the hypervisor. This function will be called from the host only.
4596 * EINVAL is returned when the host attempts to set the flag for a guest that
4597 * does not support pv clocks.
4598 */
4599 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4600 {
4601 if (!vcpu->arch.pv_time_enabled)
4602 return -EINVAL;
4603 vcpu->arch.pvclock_set_guest_stopped_request = true;
4604 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4605 return 0;
4606 }
4607
4608 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4609 struct kvm_enable_cap *cap)
4610 {
4611 int r;
4612 uint16_t vmcs_version;
4613 void __user *user_ptr;
4614
4615 if (cap->flags)
4616 return -EINVAL;
4617
4618 switch (cap->cap) {
4619 case KVM_CAP_HYPERV_SYNIC2:
4620 if (cap->args[0])
4621 return -EINVAL;
4622 fallthrough;
4623
4624 case KVM_CAP_HYPERV_SYNIC:
4625 if (!irqchip_in_kernel(vcpu->kvm))
4626 return -EINVAL;
4627 return kvm_hv_activate_synic(vcpu, cap->cap ==
4628 KVM_CAP_HYPERV_SYNIC2);
4629 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4630 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4631 return -ENOTTY;
4632 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4633 if (!r) {
4634 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4635 if (copy_to_user(user_ptr, &vmcs_version,
4636 sizeof(vmcs_version)))
4637 r = -EFAULT;
4638 }
4639 return r;
4640 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4641 if (!kvm_x86_ops.enable_direct_tlbflush)
4642 return -ENOTTY;
4643
4644 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu);
4645
4646 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4647 vcpu->arch.pv_cpuid.enforce = cap->args[0];
4648 if (vcpu->arch.pv_cpuid.enforce)
4649 kvm_update_pv_runtime(vcpu);
4650
4651 return 0;
4652
4653 default:
4654 return -EINVAL;
4655 }
4656 }
4657
4658 long kvm_arch_vcpu_ioctl(struct file *filp,
4659 unsigned int ioctl, unsigned long arg)
4660 {
4661 struct kvm_vcpu *vcpu = filp->private_data;
4662 void __user *argp = (void __user *)arg;
4663 int r;
4664 union {
4665 struct kvm_lapic_state *lapic;
4666 struct kvm_xsave *xsave;
4667 struct kvm_xcrs *xcrs;
4668 void *buffer;
4669 } u;
4670
4671 vcpu_load(vcpu);
4672
4673 u.buffer = NULL;
4674 switch (ioctl) {
4675 case KVM_GET_LAPIC: {
4676 r = -EINVAL;
4677 if (!lapic_in_kernel(vcpu))
4678 goto out;
4679 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4680 GFP_KERNEL_ACCOUNT);
4681
4682 r = -ENOMEM;
4683 if (!u.lapic)
4684 goto out;
4685 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4686 if (r)
4687 goto out;
4688 r = -EFAULT;
4689 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4690 goto out;
4691 r = 0;
4692 break;
4693 }
4694 case KVM_SET_LAPIC: {
4695 r = -EINVAL;
4696 if (!lapic_in_kernel(vcpu))
4697 goto out;
4698 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4699 if (IS_ERR(u.lapic)) {
4700 r = PTR_ERR(u.lapic);
4701 goto out_nofree;
4702 }
4703
4704 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4705 break;
4706 }
4707 case KVM_INTERRUPT: {
4708 struct kvm_interrupt irq;
4709
4710 r = -EFAULT;
4711 if (copy_from_user(&irq, argp, sizeof(irq)))
4712 goto out;
4713 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4714 break;
4715 }
4716 case KVM_NMI: {
4717 r = kvm_vcpu_ioctl_nmi(vcpu);
4718 break;
4719 }
4720 case KVM_SMI: {
4721 r = kvm_vcpu_ioctl_smi(vcpu);
4722 break;
4723 }
4724 case KVM_SET_CPUID: {
4725 struct kvm_cpuid __user *cpuid_arg = argp;
4726 struct kvm_cpuid cpuid;
4727
4728 r = -EFAULT;
4729 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4730 goto out;
4731 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4732 break;
4733 }
4734 case KVM_SET_CPUID2: {
4735 struct kvm_cpuid2 __user *cpuid_arg = argp;
4736 struct kvm_cpuid2 cpuid;
4737
4738 r = -EFAULT;
4739 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4740 goto out;
4741 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4742 cpuid_arg->entries);
4743 break;
4744 }
4745 case KVM_GET_CPUID2: {
4746 struct kvm_cpuid2 __user *cpuid_arg = argp;
4747 struct kvm_cpuid2 cpuid;
4748
4749 r = -EFAULT;
4750 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4751 goto out;
4752 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4753 cpuid_arg->entries);
4754 if (r)
4755 goto out;
4756 r = -EFAULT;
4757 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4758 goto out;
4759 r = 0;
4760 break;
4761 }
4762 case KVM_GET_MSRS: {
4763 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4764 r = msr_io(vcpu, argp, do_get_msr, 1);
4765 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4766 break;
4767 }
4768 case KVM_SET_MSRS: {
4769 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4770 r = msr_io(vcpu, argp, do_set_msr, 0);
4771 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4772 break;
4773 }
4774 case KVM_TPR_ACCESS_REPORTING: {
4775 struct kvm_tpr_access_ctl tac;
4776
4777 r = -EFAULT;
4778 if (copy_from_user(&tac, argp, sizeof(tac)))
4779 goto out;
4780 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4781 if (r)
4782 goto out;
4783 r = -EFAULT;
4784 if (copy_to_user(argp, &tac, sizeof(tac)))
4785 goto out;
4786 r = 0;
4787 break;
4788 };
4789 case KVM_SET_VAPIC_ADDR: {
4790 struct kvm_vapic_addr va;
4791 int idx;
4792
4793 r = -EINVAL;
4794 if (!lapic_in_kernel(vcpu))
4795 goto out;
4796 r = -EFAULT;
4797 if (copy_from_user(&va, argp, sizeof(va)))
4798 goto out;
4799 idx = srcu_read_lock(&vcpu->kvm->srcu);
4800 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4801 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4802 break;
4803 }
4804 case KVM_X86_SETUP_MCE: {
4805 u64 mcg_cap;
4806
4807 r = -EFAULT;
4808 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4809 goto out;
4810 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4811 break;
4812 }
4813 case KVM_X86_SET_MCE: {
4814 struct kvm_x86_mce mce;
4815
4816 r = -EFAULT;
4817 if (copy_from_user(&mce, argp, sizeof(mce)))
4818 goto out;
4819 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4820 break;
4821 }
4822 case KVM_GET_VCPU_EVENTS: {
4823 struct kvm_vcpu_events events;
4824
4825 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4826
4827 r = -EFAULT;
4828 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4829 break;
4830 r = 0;
4831 break;
4832 }
4833 case KVM_SET_VCPU_EVENTS: {
4834 struct kvm_vcpu_events events;
4835
4836 r = -EFAULT;
4837 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4838 break;
4839
4840 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4841 break;
4842 }
4843 case KVM_GET_DEBUGREGS: {
4844 struct kvm_debugregs dbgregs;
4845
4846 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4847
4848 r = -EFAULT;
4849 if (copy_to_user(argp, &dbgregs,
4850 sizeof(struct kvm_debugregs)))
4851 break;
4852 r = 0;
4853 break;
4854 }
4855 case KVM_SET_DEBUGREGS: {
4856 struct kvm_debugregs dbgregs;
4857
4858 r = -EFAULT;
4859 if (copy_from_user(&dbgregs, argp,
4860 sizeof(struct kvm_debugregs)))
4861 break;
4862
4863 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4864 break;
4865 }
4866 case KVM_GET_XSAVE: {
4867 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4868 r = -ENOMEM;
4869 if (!u.xsave)
4870 break;
4871
4872 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4873
4874 r = -EFAULT;
4875 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4876 break;
4877 r = 0;
4878 break;
4879 }
4880 case KVM_SET_XSAVE: {
4881 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4882 if (IS_ERR(u.xsave)) {
4883 r = PTR_ERR(u.xsave);
4884 goto out_nofree;
4885 }
4886
4887 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4888 break;
4889 }
4890 case KVM_GET_XCRS: {
4891 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4892 r = -ENOMEM;
4893 if (!u.xcrs)
4894 break;
4895
4896 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4897
4898 r = -EFAULT;
4899 if (copy_to_user(argp, u.xcrs,
4900 sizeof(struct kvm_xcrs)))
4901 break;
4902 r = 0;
4903 break;
4904 }
4905 case KVM_SET_XCRS: {
4906 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4907 if (IS_ERR(u.xcrs)) {
4908 r = PTR_ERR(u.xcrs);
4909 goto out_nofree;
4910 }
4911
4912 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4913 break;
4914 }
4915 case KVM_SET_TSC_KHZ: {
4916 u32 user_tsc_khz;
4917
4918 r = -EINVAL;
4919 user_tsc_khz = (u32)arg;
4920
4921 if (kvm_has_tsc_control &&
4922 user_tsc_khz >= kvm_max_guest_tsc_khz)
4923 goto out;
4924
4925 if (user_tsc_khz == 0)
4926 user_tsc_khz = tsc_khz;
4927
4928 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4929 r = 0;
4930
4931 goto out;
4932 }
4933 case KVM_GET_TSC_KHZ: {
4934 r = vcpu->arch.virtual_tsc_khz;
4935 goto out;
4936 }
4937 case KVM_KVMCLOCK_CTRL: {
4938 r = kvm_set_guest_paused(vcpu);
4939 goto out;
4940 }
4941 case KVM_ENABLE_CAP: {
4942 struct kvm_enable_cap cap;
4943
4944 r = -EFAULT;
4945 if (copy_from_user(&cap, argp, sizeof(cap)))
4946 goto out;
4947 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4948 break;
4949 }
4950 case KVM_GET_NESTED_STATE: {
4951 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4952 u32 user_data_size;
4953
4954 r = -EINVAL;
4955 if (!kvm_x86_ops.nested_ops->get_state)
4956 break;
4957
4958 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4959 r = -EFAULT;
4960 if (get_user(user_data_size, &user_kvm_nested_state->size))
4961 break;
4962
4963 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4964 user_data_size);
4965 if (r < 0)
4966 break;
4967
4968 if (r > user_data_size) {
4969 if (put_user(r, &user_kvm_nested_state->size))
4970 r = -EFAULT;
4971 else
4972 r = -E2BIG;
4973 break;
4974 }
4975
4976 r = 0;
4977 break;
4978 }
4979 case KVM_SET_NESTED_STATE: {
4980 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4981 struct kvm_nested_state kvm_state;
4982 int idx;
4983
4984 r = -EINVAL;
4985 if (!kvm_x86_ops.nested_ops->set_state)
4986 break;
4987
4988 r = -EFAULT;
4989 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4990 break;
4991
4992 r = -EINVAL;
4993 if (kvm_state.size < sizeof(kvm_state))
4994 break;
4995
4996 if (kvm_state.flags &
4997 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4998 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
4999 | KVM_STATE_NESTED_GIF_SET))
5000 break;
5001
5002 /* nested_run_pending implies guest_mode. */
5003 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5004 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5005 break;
5006
5007 idx = srcu_read_lock(&vcpu->kvm->srcu);
5008 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5009 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5010 break;
5011 }
5012 case KVM_GET_SUPPORTED_HV_CPUID:
5013 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5014 break;
5015 case KVM_XEN_VCPU_GET_ATTR: {
5016 struct kvm_xen_vcpu_attr xva;
5017
5018 r = -EFAULT;
5019 if (copy_from_user(&xva, argp, sizeof(xva)))
5020 goto out;
5021 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5022 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5023 r = -EFAULT;
5024 break;
5025 }
5026 case KVM_XEN_VCPU_SET_ATTR: {
5027 struct kvm_xen_vcpu_attr xva;
5028
5029 r = -EFAULT;
5030 if (copy_from_user(&xva, argp, sizeof(xva)))
5031 goto out;
5032 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5033 break;
5034 }
5035 default:
5036 r = -EINVAL;
5037 }
5038 out:
5039 kfree(u.buffer);
5040 out_nofree:
5041 vcpu_put(vcpu);
5042 return r;
5043 }
5044
5045 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5046 {
5047 return VM_FAULT_SIGBUS;
5048 }
5049
5050 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5051 {
5052 int ret;
5053
5054 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5055 return -EINVAL;
5056 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
5057 return ret;
5058 }
5059
5060 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5061 u64 ident_addr)
5062 {
5063 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
5064 }
5065
5066 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5067 unsigned long kvm_nr_mmu_pages)
5068 {
5069 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5070 return -EINVAL;
5071
5072 mutex_lock(&kvm->slots_lock);
5073
5074 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5075 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5076
5077 mutex_unlock(&kvm->slots_lock);
5078 return 0;
5079 }
5080
5081 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5082 {
5083 return kvm->arch.n_max_mmu_pages;
5084 }
5085
5086 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5087 {
5088 struct kvm_pic *pic = kvm->arch.vpic;
5089 int r;
5090
5091 r = 0;
5092 switch (chip->chip_id) {
5093 case KVM_IRQCHIP_PIC_MASTER:
5094 memcpy(&chip->chip.pic, &pic->pics[0],
5095 sizeof(struct kvm_pic_state));
5096 break;
5097 case KVM_IRQCHIP_PIC_SLAVE:
5098 memcpy(&chip->chip.pic, &pic->pics[1],
5099 sizeof(struct kvm_pic_state));
5100 break;
5101 case KVM_IRQCHIP_IOAPIC:
5102 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5103 break;
5104 default:
5105 r = -EINVAL;
5106 break;
5107 }
5108 return r;
5109 }
5110
5111 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5112 {
5113 struct kvm_pic *pic = kvm->arch.vpic;
5114 int r;
5115
5116 r = 0;
5117 switch (chip->chip_id) {
5118 case KVM_IRQCHIP_PIC_MASTER:
5119 spin_lock(&pic->lock);
5120 memcpy(&pic->pics[0], &chip->chip.pic,
5121 sizeof(struct kvm_pic_state));
5122 spin_unlock(&pic->lock);
5123 break;
5124 case KVM_IRQCHIP_PIC_SLAVE:
5125 spin_lock(&pic->lock);
5126 memcpy(&pic->pics[1], &chip->chip.pic,
5127 sizeof(struct kvm_pic_state));
5128 spin_unlock(&pic->lock);
5129 break;
5130 case KVM_IRQCHIP_IOAPIC:
5131 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5132 break;
5133 default:
5134 r = -EINVAL;
5135 break;
5136 }
5137 kvm_pic_update_irq(pic);
5138 return r;
5139 }
5140
5141 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5142 {
5143 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5144
5145 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5146
5147 mutex_lock(&kps->lock);
5148 memcpy(ps, &kps->channels, sizeof(*ps));
5149 mutex_unlock(&kps->lock);
5150 return 0;
5151 }
5152
5153 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5154 {
5155 int i;
5156 struct kvm_pit *pit = kvm->arch.vpit;
5157
5158 mutex_lock(&pit->pit_state.lock);
5159 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5160 for (i = 0; i < 3; i++)
5161 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5162 mutex_unlock(&pit->pit_state.lock);
5163 return 0;
5164 }
5165
5166 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5167 {
5168 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5169 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5170 sizeof(ps->channels));
5171 ps->flags = kvm->arch.vpit->pit_state.flags;
5172 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5173 memset(&ps->reserved, 0, sizeof(ps->reserved));
5174 return 0;
5175 }
5176
5177 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5178 {
5179 int start = 0;
5180 int i;
5181 u32 prev_legacy, cur_legacy;
5182 struct kvm_pit *pit = kvm->arch.vpit;
5183
5184 mutex_lock(&pit->pit_state.lock);
5185 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5186 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5187 if (!prev_legacy && cur_legacy)
5188 start = 1;
5189 memcpy(&pit->pit_state.channels, &ps->channels,
5190 sizeof(pit->pit_state.channels));
5191 pit->pit_state.flags = ps->flags;
5192 for (i = 0; i < 3; i++)
5193 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5194 start && i == 0);
5195 mutex_unlock(&pit->pit_state.lock);
5196 return 0;
5197 }
5198
5199 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5200 struct kvm_reinject_control *control)
5201 {
5202 struct kvm_pit *pit = kvm->arch.vpit;
5203
5204 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5205 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5206 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5207 */
5208 mutex_lock(&pit->pit_state.lock);
5209 kvm_pit_set_reinject(pit, control->pit_reinject);
5210 mutex_unlock(&pit->pit_state.lock);
5211
5212 return 0;
5213 }
5214
5215 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5216 {
5217
5218 /*
5219 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
5220 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
5221 * on all VM-Exits, thus we only need to kick running vCPUs to force a
5222 * VM-Exit.
5223 */
5224 struct kvm_vcpu *vcpu;
5225 int i;
5226
5227 kvm_for_each_vcpu(i, vcpu, kvm)
5228 kvm_vcpu_kick(vcpu);
5229 }
5230
5231 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5232 bool line_status)
5233 {
5234 if (!irqchip_in_kernel(kvm))
5235 return -ENXIO;
5236
5237 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5238 irq_event->irq, irq_event->level,
5239 line_status);
5240 return 0;
5241 }
5242
5243 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5244 struct kvm_enable_cap *cap)
5245 {
5246 int r;
5247
5248 if (cap->flags)
5249 return -EINVAL;
5250
5251 switch (cap->cap) {
5252 case KVM_CAP_DISABLE_QUIRKS:
5253 kvm->arch.disabled_quirks = cap->args[0];
5254 r = 0;
5255 break;
5256 case KVM_CAP_SPLIT_IRQCHIP: {
5257 mutex_lock(&kvm->lock);
5258 r = -EINVAL;
5259 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5260 goto split_irqchip_unlock;
5261 r = -EEXIST;
5262 if (irqchip_in_kernel(kvm))
5263 goto split_irqchip_unlock;
5264 if (kvm->created_vcpus)
5265 goto split_irqchip_unlock;
5266 r = kvm_setup_empty_irq_routing(kvm);
5267 if (r)
5268 goto split_irqchip_unlock;
5269 /* Pairs with irqchip_in_kernel. */
5270 smp_wmb();
5271 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5272 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5273 r = 0;
5274 split_irqchip_unlock:
5275 mutex_unlock(&kvm->lock);
5276 break;
5277 }
5278 case KVM_CAP_X2APIC_API:
5279 r = -EINVAL;
5280 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5281 break;
5282
5283 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5284 kvm->arch.x2apic_format = true;
5285 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5286 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5287
5288 r = 0;
5289 break;
5290 case KVM_CAP_X86_DISABLE_EXITS:
5291 r = -EINVAL;
5292 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5293 break;
5294
5295 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5296 kvm_can_mwait_in_guest())
5297 kvm->arch.mwait_in_guest = true;
5298 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5299 kvm->arch.hlt_in_guest = true;
5300 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5301 kvm->arch.pause_in_guest = true;
5302 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5303 kvm->arch.cstate_in_guest = true;
5304 r = 0;
5305 break;
5306 case KVM_CAP_MSR_PLATFORM_INFO:
5307 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5308 r = 0;
5309 break;
5310 case KVM_CAP_EXCEPTION_PAYLOAD:
5311 kvm->arch.exception_payload_enabled = cap->args[0];
5312 r = 0;
5313 break;
5314 case KVM_CAP_X86_USER_SPACE_MSR:
5315 kvm->arch.user_space_msr_mask = cap->args[0];
5316 r = 0;
5317 break;
5318 case KVM_CAP_X86_BUS_LOCK_EXIT:
5319 r = -EINVAL;
5320 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
5321 break;
5322
5323 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
5324 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
5325 break;
5326
5327 if (kvm_has_bus_lock_exit &&
5328 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
5329 kvm->arch.bus_lock_detection_enabled = true;
5330 r = 0;
5331 break;
5332 default:
5333 r = -EINVAL;
5334 break;
5335 }
5336 return r;
5337 }
5338
5339 static void kvm_clear_msr_filter(struct kvm *kvm)
5340 {
5341 u32 i;
5342 u32 count = kvm->arch.msr_filter.count;
5343 struct msr_bitmap_range ranges[16];
5344
5345 mutex_lock(&kvm->lock);
5346 kvm->arch.msr_filter.count = 0;
5347 memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0]));
5348 mutex_unlock(&kvm->lock);
5349 synchronize_srcu(&kvm->srcu);
5350
5351 for (i = 0; i < count; i++)
5352 kfree(ranges[i].bitmap);
5353 }
5354
5355 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range)
5356 {
5357 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
5358 struct msr_bitmap_range range;
5359 unsigned long *bitmap = NULL;
5360 size_t bitmap_size;
5361 int r;
5362
5363 if (!user_range->nmsrs)
5364 return 0;
5365
5366 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5367 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5368 return -EINVAL;
5369
5370 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5371 if (IS_ERR(bitmap))
5372 return PTR_ERR(bitmap);
5373
5374 range = (struct msr_bitmap_range) {
5375 .flags = user_range->flags,
5376 .base = user_range->base,
5377 .nmsrs = user_range->nmsrs,
5378 .bitmap = bitmap,
5379 };
5380
5381 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5382 r = -EINVAL;
5383 goto err;
5384 }
5385
5386 if (!range.flags) {
5387 r = -EINVAL;
5388 goto err;
5389 }
5390
5391 /* Everything ok, add this range identifier to our global pool */
5392 ranges[kvm->arch.msr_filter.count] = range;
5393 /* Make sure we filled the array before we tell anyone to walk it */
5394 smp_wmb();
5395 kvm->arch.msr_filter.count++;
5396
5397 return 0;
5398 err:
5399 kfree(bitmap);
5400 return r;
5401 }
5402
5403 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5404 {
5405 struct kvm_msr_filter __user *user_msr_filter = argp;
5406 struct kvm_msr_filter filter;
5407 bool default_allow;
5408 int r = 0;
5409 bool empty = true;
5410 u32 i;
5411
5412 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5413 return -EFAULT;
5414
5415 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5416 empty &= !filter.ranges[i].nmsrs;
5417
5418 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5419 if (empty && !default_allow)
5420 return -EINVAL;
5421
5422 kvm_clear_msr_filter(kvm);
5423
5424 kvm->arch.msr_filter.default_allow = default_allow;
5425
5426 /*
5427 * Protect from concurrent calls to this function that could trigger
5428 * a TOCTOU violation on kvm->arch.msr_filter.count.
5429 */
5430 mutex_lock(&kvm->lock);
5431 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5432 r = kvm_add_msr_filter(kvm, &filter.ranges[i]);
5433 if (r)
5434 break;
5435 }
5436
5437 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5438 mutex_unlock(&kvm->lock);
5439
5440 return r;
5441 }
5442
5443 long kvm_arch_vm_ioctl(struct file *filp,
5444 unsigned int ioctl, unsigned long arg)
5445 {
5446 struct kvm *kvm = filp->private_data;
5447 void __user *argp = (void __user *)arg;
5448 int r = -ENOTTY;
5449 /*
5450 * This union makes it completely explicit to gcc-3.x
5451 * that these two variables' stack usage should be
5452 * combined, not added together.
5453 */
5454 union {
5455 struct kvm_pit_state ps;
5456 struct kvm_pit_state2 ps2;
5457 struct kvm_pit_config pit_config;
5458 } u;
5459
5460 switch (ioctl) {
5461 case KVM_SET_TSS_ADDR:
5462 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5463 break;
5464 case KVM_SET_IDENTITY_MAP_ADDR: {
5465 u64 ident_addr;
5466
5467 mutex_lock(&kvm->lock);
5468 r = -EINVAL;
5469 if (kvm->created_vcpus)
5470 goto set_identity_unlock;
5471 r = -EFAULT;
5472 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5473 goto set_identity_unlock;
5474 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5475 set_identity_unlock:
5476 mutex_unlock(&kvm->lock);
5477 break;
5478 }
5479 case KVM_SET_NR_MMU_PAGES:
5480 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5481 break;
5482 case KVM_GET_NR_MMU_PAGES:
5483 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5484 break;
5485 case KVM_CREATE_IRQCHIP: {
5486 mutex_lock(&kvm->lock);
5487
5488 r = -EEXIST;
5489 if (irqchip_in_kernel(kvm))
5490 goto create_irqchip_unlock;
5491
5492 r = -EINVAL;
5493 if (kvm->created_vcpus)
5494 goto create_irqchip_unlock;
5495
5496 r = kvm_pic_init(kvm);
5497 if (r)
5498 goto create_irqchip_unlock;
5499
5500 r = kvm_ioapic_init(kvm);
5501 if (r) {
5502 kvm_pic_destroy(kvm);
5503 goto create_irqchip_unlock;
5504 }
5505
5506 r = kvm_setup_default_irq_routing(kvm);
5507 if (r) {
5508 kvm_ioapic_destroy(kvm);
5509 kvm_pic_destroy(kvm);
5510 goto create_irqchip_unlock;
5511 }
5512 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5513 smp_wmb();
5514 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5515 create_irqchip_unlock:
5516 mutex_unlock(&kvm->lock);
5517 break;
5518 }
5519 case KVM_CREATE_PIT:
5520 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5521 goto create_pit;
5522 case KVM_CREATE_PIT2:
5523 r = -EFAULT;
5524 if (copy_from_user(&u.pit_config, argp,
5525 sizeof(struct kvm_pit_config)))
5526 goto out;
5527 create_pit:
5528 mutex_lock(&kvm->lock);
5529 r = -EEXIST;
5530 if (kvm->arch.vpit)
5531 goto create_pit_unlock;
5532 r = -ENOMEM;
5533 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5534 if (kvm->arch.vpit)
5535 r = 0;
5536 create_pit_unlock:
5537 mutex_unlock(&kvm->lock);
5538 break;
5539 case KVM_GET_IRQCHIP: {
5540 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5541 struct kvm_irqchip *chip;
5542
5543 chip = memdup_user(argp, sizeof(*chip));
5544 if (IS_ERR(chip)) {
5545 r = PTR_ERR(chip);
5546 goto out;
5547 }
5548
5549 r = -ENXIO;
5550 if (!irqchip_kernel(kvm))
5551 goto get_irqchip_out;
5552 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5553 if (r)
5554 goto get_irqchip_out;
5555 r = -EFAULT;
5556 if (copy_to_user(argp, chip, sizeof(*chip)))
5557 goto get_irqchip_out;
5558 r = 0;
5559 get_irqchip_out:
5560 kfree(chip);
5561 break;
5562 }
5563 case KVM_SET_IRQCHIP: {
5564 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5565 struct kvm_irqchip *chip;
5566
5567 chip = memdup_user(argp, sizeof(*chip));
5568 if (IS_ERR(chip)) {
5569 r = PTR_ERR(chip);
5570 goto out;
5571 }
5572
5573 r = -ENXIO;
5574 if (!irqchip_kernel(kvm))
5575 goto set_irqchip_out;
5576 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5577 set_irqchip_out:
5578 kfree(chip);
5579 break;
5580 }
5581 case KVM_GET_PIT: {
5582 r = -EFAULT;
5583 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5584 goto out;
5585 r = -ENXIO;
5586 if (!kvm->arch.vpit)
5587 goto out;
5588 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5589 if (r)
5590 goto out;
5591 r = -EFAULT;
5592 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5593 goto out;
5594 r = 0;
5595 break;
5596 }
5597 case KVM_SET_PIT: {
5598 r = -EFAULT;
5599 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5600 goto out;
5601 mutex_lock(&kvm->lock);
5602 r = -ENXIO;
5603 if (!kvm->arch.vpit)
5604 goto set_pit_out;
5605 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5606 set_pit_out:
5607 mutex_unlock(&kvm->lock);
5608 break;
5609 }
5610 case KVM_GET_PIT2: {
5611 r = -ENXIO;
5612 if (!kvm->arch.vpit)
5613 goto out;
5614 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5615 if (r)
5616 goto out;
5617 r = -EFAULT;
5618 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5619 goto out;
5620 r = 0;
5621 break;
5622 }
5623 case KVM_SET_PIT2: {
5624 r = -EFAULT;
5625 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5626 goto out;
5627 mutex_lock(&kvm->lock);
5628 r = -ENXIO;
5629 if (!kvm->arch.vpit)
5630 goto set_pit2_out;
5631 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5632 set_pit2_out:
5633 mutex_unlock(&kvm->lock);
5634 break;
5635 }
5636 case KVM_REINJECT_CONTROL: {
5637 struct kvm_reinject_control control;
5638 r = -EFAULT;
5639 if (copy_from_user(&control, argp, sizeof(control)))
5640 goto out;
5641 r = -ENXIO;
5642 if (!kvm->arch.vpit)
5643 goto out;
5644 r = kvm_vm_ioctl_reinject(kvm, &control);
5645 break;
5646 }
5647 case KVM_SET_BOOT_CPU_ID:
5648 r = 0;
5649 mutex_lock(&kvm->lock);
5650 if (kvm->created_vcpus)
5651 r = -EBUSY;
5652 else
5653 kvm->arch.bsp_vcpu_id = arg;
5654 mutex_unlock(&kvm->lock);
5655 break;
5656 case KVM_XEN_HVM_CONFIG: {
5657 struct kvm_xen_hvm_config xhc;
5658 r = -EFAULT;
5659 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5660 goto out;
5661 r = kvm_xen_hvm_config(kvm, &xhc);
5662 break;
5663 }
5664 case KVM_XEN_HVM_GET_ATTR: {
5665 struct kvm_xen_hvm_attr xha;
5666
5667 r = -EFAULT;
5668 if (copy_from_user(&xha, argp, sizeof(xha)))
5669 goto out;
5670 r = kvm_xen_hvm_get_attr(kvm, &xha);
5671 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
5672 r = -EFAULT;
5673 break;
5674 }
5675 case KVM_XEN_HVM_SET_ATTR: {
5676 struct kvm_xen_hvm_attr xha;
5677
5678 r = -EFAULT;
5679 if (copy_from_user(&xha, argp, sizeof(xha)))
5680 goto out;
5681 r = kvm_xen_hvm_set_attr(kvm, &xha);
5682 break;
5683 }
5684 case KVM_SET_CLOCK: {
5685 struct kvm_clock_data user_ns;
5686 u64 now_ns;
5687
5688 r = -EFAULT;
5689 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5690 goto out;
5691
5692 r = -EINVAL;
5693 if (user_ns.flags)
5694 goto out;
5695
5696 r = 0;
5697 /*
5698 * TODO: userspace has to take care of races with VCPU_RUN, so
5699 * kvm_gen_update_masterclock() can be cut down to locked
5700 * pvclock_update_vm_gtod_copy().
5701 */
5702 kvm_gen_update_masterclock(kvm);
5703 now_ns = get_kvmclock_ns(kvm);
5704 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5705 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5706 break;
5707 }
5708 case KVM_GET_CLOCK: {
5709 struct kvm_clock_data user_ns;
5710 u64 now_ns;
5711
5712 now_ns = get_kvmclock_ns(kvm);
5713 user_ns.clock = now_ns;
5714 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5715 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5716
5717 r = -EFAULT;
5718 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5719 goto out;
5720 r = 0;
5721 break;
5722 }
5723 case KVM_MEMORY_ENCRYPT_OP: {
5724 r = -ENOTTY;
5725 if (kvm_x86_ops.mem_enc_op)
5726 r = static_call(kvm_x86_mem_enc_op)(kvm, argp);
5727 break;
5728 }
5729 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5730 struct kvm_enc_region region;
5731
5732 r = -EFAULT;
5733 if (copy_from_user(&region, argp, sizeof(region)))
5734 goto out;
5735
5736 r = -ENOTTY;
5737 if (kvm_x86_ops.mem_enc_reg_region)
5738 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, &region);
5739 break;
5740 }
5741 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5742 struct kvm_enc_region region;
5743
5744 r = -EFAULT;
5745 if (copy_from_user(&region, argp, sizeof(region)))
5746 goto out;
5747
5748 r = -ENOTTY;
5749 if (kvm_x86_ops.mem_enc_unreg_region)
5750 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, &region);
5751 break;
5752 }
5753 case KVM_HYPERV_EVENTFD: {
5754 struct kvm_hyperv_eventfd hvevfd;
5755
5756 r = -EFAULT;
5757 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5758 goto out;
5759 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5760 break;
5761 }
5762 case KVM_SET_PMU_EVENT_FILTER:
5763 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5764 break;
5765 case KVM_X86_SET_MSR_FILTER:
5766 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5767 break;
5768 default:
5769 r = -ENOTTY;
5770 }
5771 out:
5772 return r;
5773 }
5774
5775 static void kvm_init_msr_list(void)
5776 {
5777 struct x86_pmu_capability x86_pmu;
5778 u32 dummy[2];
5779 unsigned i;
5780
5781 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5782 "Please update the fixed PMCs in msrs_to_saved_all[]");
5783
5784 perf_get_x86_pmu_capability(&x86_pmu);
5785
5786 num_msrs_to_save = 0;
5787 num_emulated_msrs = 0;
5788 num_msr_based_features = 0;
5789
5790 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5791 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5792 continue;
5793
5794 /*
5795 * Even MSRs that are valid in the host may not be exposed
5796 * to the guests in some cases.
5797 */
5798 switch (msrs_to_save_all[i]) {
5799 case MSR_IA32_BNDCFGS:
5800 if (!kvm_mpx_supported())
5801 continue;
5802 break;
5803 case MSR_TSC_AUX:
5804 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5805 continue;
5806 break;
5807 case MSR_IA32_UMWAIT_CONTROL:
5808 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5809 continue;
5810 break;
5811 case MSR_IA32_RTIT_CTL:
5812 case MSR_IA32_RTIT_STATUS:
5813 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5814 continue;
5815 break;
5816 case MSR_IA32_RTIT_CR3_MATCH:
5817 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5818 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5819 continue;
5820 break;
5821 case MSR_IA32_RTIT_OUTPUT_BASE:
5822 case MSR_IA32_RTIT_OUTPUT_MASK:
5823 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5824 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5825 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5826 continue;
5827 break;
5828 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5829 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5830 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5831 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5832 continue;
5833 break;
5834 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5835 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5836 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5837 continue;
5838 break;
5839 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5840 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5841 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5842 continue;
5843 break;
5844 default:
5845 break;
5846 }
5847
5848 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5849 }
5850
5851 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5852 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
5853 continue;
5854
5855 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5856 }
5857
5858 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5859 struct kvm_msr_entry msr;
5860
5861 msr.index = msr_based_features_all[i];
5862 if (kvm_get_msr_feature(&msr))
5863 continue;
5864
5865 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5866 }
5867 }
5868
5869 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5870 const void *v)
5871 {
5872 int handled = 0;
5873 int n;
5874
5875 do {
5876 n = min(len, 8);
5877 if (!(lapic_in_kernel(vcpu) &&
5878 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5879 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5880 break;
5881 handled += n;
5882 addr += n;
5883 len -= n;
5884 v += n;
5885 } while (len);
5886
5887 return handled;
5888 }
5889
5890 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5891 {
5892 int handled = 0;
5893 int n;
5894
5895 do {
5896 n = min(len, 8);
5897 if (!(lapic_in_kernel(vcpu) &&
5898 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5899 addr, n, v))
5900 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5901 break;
5902 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5903 handled += n;
5904 addr += n;
5905 len -= n;
5906 v += n;
5907 } while (len);
5908
5909 return handled;
5910 }
5911
5912 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5913 struct kvm_segment *var, int seg)
5914 {
5915 static_call(kvm_x86_set_segment)(vcpu, var, seg);
5916 }
5917
5918 void kvm_get_segment(struct kvm_vcpu *vcpu,
5919 struct kvm_segment *var, int seg)
5920 {
5921 static_call(kvm_x86_get_segment)(vcpu, var, seg);
5922 }
5923
5924 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5925 struct x86_exception *exception)
5926 {
5927 gpa_t t_gpa;
5928
5929 BUG_ON(!mmu_is_nested(vcpu));
5930
5931 /* NPT walks are always user-walks */
5932 access |= PFERR_USER_MASK;
5933 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5934
5935 return t_gpa;
5936 }
5937
5938 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5939 struct x86_exception *exception)
5940 {
5941 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
5942 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5943 }
5944
5945 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5946 struct x86_exception *exception)
5947 {
5948 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
5949 access |= PFERR_FETCH_MASK;
5950 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5951 }
5952
5953 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5954 struct x86_exception *exception)
5955 {
5956 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
5957 access |= PFERR_WRITE_MASK;
5958 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5959 }
5960
5961 /* uses this to access any guest's mapped memory without checking CPL */
5962 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5963 struct x86_exception *exception)
5964 {
5965 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5966 }
5967
5968 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5969 struct kvm_vcpu *vcpu, u32 access,
5970 struct x86_exception *exception)
5971 {
5972 void *data = val;
5973 int r = X86EMUL_CONTINUE;
5974
5975 while (bytes) {
5976 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5977 exception);
5978 unsigned offset = addr & (PAGE_SIZE-1);
5979 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5980 int ret;
5981
5982 if (gpa == UNMAPPED_GVA)
5983 return X86EMUL_PROPAGATE_FAULT;
5984 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5985 offset, toread);
5986 if (ret < 0) {
5987 r = X86EMUL_IO_NEEDED;
5988 goto out;
5989 }
5990
5991 bytes -= toread;
5992 data += toread;
5993 addr += toread;
5994 }
5995 out:
5996 return r;
5997 }
5998
5999 /* used for instruction fetching */
6000 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
6001 gva_t addr, void *val, unsigned int bytes,
6002 struct x86_exception *exception)
6003 {
6004 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6005 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6006 unsigned offset;
6007 int ret;
6008
6009 /* Inline kvm_read_guest_virt_helper for speed. */
6010 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
6011 exception);
6012 if (unlikely(gpa == UNMAPPED_GVA))
6013 return X86EMUL_PROPAGATE_FAULT;
6014
6015 offset = addr & (PAGE_SIZE-1);
6016 if (WARN_ON(offset + bytes > PAGE_SIZE))
6017 bytes = (unsigned)PAGE_SIZE - offset;
6018 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
6019 offset, bytes);
6020 if (unlikely(ret < 0))
6021 return X86EMUL_IO_NEEDED;
6022
6023 return X86EMUL_CONTINUE;
6024 }
6025
6026 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
6027 gva_t addr, void *val, unsigned int bytes,
6028 struct x86_exception *exception)
6029 {
6030 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6031
6032 /*
6033 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
6034 * is returned, but our callers are not ready for that and they blindly
6035 * call kvm_inject_page_fault. Ensure that they at least do not leak
6036 * uninitialized kernel stack memory into cr2 and error code.
6037 */
6038 memset(exception, 0, sizeof(*exception));
6039 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
6040 exception);
6041 }
6042 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
6043
6044 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
6045 gva_t addr, void *val, unsigned int bytes,
6046 struct x86_exception *exception, bool system)
6047 {
6048 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6049 u32 access = 0;
6050
6051 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3)
6052 access |= PFERR_USER_MASK;
6053
6054 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
6055 }
6056
6057 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
6058 unsigned long addr, void *val, unsigned int bytes)
6059 {
6060 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6061 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
6062
6063 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
6064 }
6065
6066 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6067 struct kvm_vcpu *vcpu, u32 access,
6068 struct x86_exception *exception)
6069 {
6070 void *data = val;
6071 int r = X86EMUL_CONTINUE;
6072
6073 while (bytes) {
6074 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
6075 access,
6076 exception);
6077 unsigned offset = addr & (PAGE_SIZE-1);
6078 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6079 int ret;
6080
6081 if (gpa == UNMAPPED_GVA)
6082 return X86EMUL_PROPAGATE_FAULT;
6083 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6084 if (ret < 0) {
6085 r = X86EMUL_IO_NEEDED;
6086 goto out;
6087 }
6088
6089 bytes -= towrite;
6090 data += towrite;
6091 addr += towrite;
6092 }
6093 out:
6094 return r;
6095 }
6096
6097 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6098 unsigned int bytes, struct x86_exception *exception,
6099 bool system)
6100 {
6101 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6102 u32 access = PFERR_WRITE_MASK;
6103
6104 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3)
6105 access |= PFERR_USER_MASK;
6106
6107 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6108 access, exception);
6109 }
6110
6111 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6112 unsigned int bytes, struct x86_exception *exception)
6113 {
6114 /* kvm_write_guest_virt_system can pull in tons of pages. */
6115 vcpu->arch.l1tf_flush_l1d = true;
6116
6117 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6118 PFERR_WRITE_MASK, exception);
6119 }
6120 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6121
6122 int handle_ud(struct kvm_vcpu *vcpu)
6123 {
6124 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6125 int emul_type = EMULTYPE_TRAP_UD;
6126 char sig[5]; /* ud2; .ascii "kvm" */
6127 struct x86_exception e;
6128
6129 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0)))
6130 return 1;
6131
6132 if (force_emulation_prefix &&
6133 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6134 sig, sizeof(sig), &e) == 0 &&
6135 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6136 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6137 emul_type = EMULTYPE_TRAP_UD_FORCED;
6138 }
6139
6140 return kvm_emulate_instruction(vcpu, emul_type);
6141 }
6142 EXPORT_SYMBOL_GPL(handle_ud);
6143
6144 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6145 gpa_t gpa, bool write)
6146 {
6147 /* For APIC access vmexit */
6148 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6149 return 1;
6150
6151 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6152 trace_vcpu_match_mmio(gva, gpa, write, true);
6153 return 1;
6154 }
6155
6156 return 0;
6157 }
6158
6159 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6160 gpa_t *gpa, struct x86_exception *exception,
6161 bool write)
6162 {
6163 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
6164 | (write ? PFERR_WRITE_MASK : 0);
6165
6166 /*
6167 * currently PKRU is only applied to ept enabled guest so
6168 * there is no pkey in EPT page table for L1 guest or EPT
6169 * shadow page table for L2 guest.
6170 */
6171 if (vcpu_match_mmio_gva(vcpu, gva)
6172 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6173 vcpu->arch.mmio_access, 0, access)) {
6174 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6175 (gva & (PAGE_SIZE - 1));
6176 trace_vcpu_match_mmio(gva, *gpa, write, false);
6177 return 1;
6178 }
6179
6180 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6181
6182 if (*gpa == UNMAPPED_GVA)
6183 return -1;
6184
6185 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6186 }
6187
6188 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6189 const void *val, int bytes)
6190 {
6191 int ret;
6192
6193 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6194 if (ret < 0)
6195 return 0;
6196 kvm_page_track_write(vcpu, gpa, val, bytes);
6197 return 1;
6198 }
6199
6200 struct read_write_emulator_ops {
6201 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6202 int bytes);
6203 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6204 void *val, int bytes);
6205 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6206 int bytes, void *val);
6207 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6208 void *val, int bytes);
6209 bool write;
6210 };
6211
6212 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6213 {
6214 if (vcpu->mmio_read_completed) {
6215 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6216 vcpu->mmio_fragments[0].gpa, val);
6217 vcpu->mmio_read_completed = 0;
6218 return 1;
6219 }
6220
6221 return 0;
6222 }
6223
6224 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6225 void *val, int bytes)
6226 {
6227 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6228 }
6229
6230 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6231 void *val, int bytes)
6232 {
6233 return emulator_write_phys(vcpu, gpa, val, bytes);
6234 }
6235
6236 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6237 {
6238 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6239 return vcpu_mmio_write(vcpu, gpa, bytes, val);
6240 }
6241
6242 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6243 void *val, int bytes)
6244 {
6245 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6246 return X86EMUL_IO_NEEDED;
6247 }
6248
6249 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6250 void *val, int bytes)
6251 {
6252 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6253
6254 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6255 return X86EMUL_CONTINUE;
6256 }
6257
6258 static const struct read_write_emulator_ops read_emultor = {
6259 .read_write_prepare = read_prepare,
6260 .read_write_emulate = read_emulate,
6261 .read_write_mmio = vcpu_mmio_read,
6262 .read_write_exit_mmio = read_exit_mmio,
6263 };
6264
6265 static const struct read_write_emulator_ops write_emultor = {
6266 .read_write_emulate = write_emulate,
6267 .read_write_mmio = write_mmio,
6268 .read_write_exit_mmio = write_exit_mmio,
6269 .write = true,
6270 };
6271
6272 static int emulator_read_write_onepage(unsigned long addr, void *val,
6273 unsigned int bytes,
6274 struct x86_exception *exception,
6275 struct kvm_vcpu *vcpu,
6276 const struct read_write_emulator_ops *ops)
6277 {
6278 gpa_t gpa;
6279 int handled, ret;
6280 bool write = ops->write;
6281 struct kvm_mmio_fragment *frag;
6282 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6283
6284 /*
6285 * If the exit was due to a NPF we may already have a GPA.
6286 * If the GPA is present, use it to avoid the GVA to GPA table walk.
6287 * Note, this cannot be used on string operations since string
6288 * operation using rep will only have the initial GPA from the NPF
6289 * occurred.
6290 */
6291 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6292 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6293 gpa = ctxt->gpa_val;
6294 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6295 } else {
6296 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6297 if (ret < 0)
6298 return X86EMUL_PROPAGATE_FAULT;
6299 }
6300
6301 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6302 return X86EMUL_CONTINUE;
6303
6304 /*
6305 * Is this MMIO handled locally?
6306 */
6307 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6308 if (handled == bytes)
6309 return X86EMUL_CONTINUE;
6310
6311 gpa += handled;
6312 bytes -= handled;
6313 val += handled;
6314
6315 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6316 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6317 frag->gpa = gpa;
6318 frag->data = val;
6319 frag->len = bytes;
6320 return X86EMUL_CONTINUE;
6321 }
6322
6323 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6324 unsigned long addr,
6325 void *val, unsigned int bytes,
6326 struct x86_exception *exception,
6327 const struct read_write_emulator_ops *ops)
6328 {
6329 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6330 gpa_t gpa;
6331 int rc;
6332
6333 if (ops->read_write_prepare &&
6334 ops->read_write_prepare(vcpu, val, bytes))
6335 return X86EMUL_CONTINUE;
6336
6337 vcpu->mmio_nr_fragments = 0;
6338
6339 /* Crossing a page boundary? */
6340 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6341 int now;
6342
6343 now = -addr & ~PAGE_MASK;
6344 rc = emulator_read_write_onepage(addr, val, now, exception,
6345 vcpu, ops);
6346
6347 if (rc != X86EMUL_CONTINUE)
6348 return rc;
6349 addr += now;
6350 if (ctxt->mode != X86EMUL_MODE_PROT64)
6351 addr = (u32)addr;
6352 val += now;
6353 bytes -= now;
6354 }
6355
6356 rc = emulator_read_write_onepage(addr, val, bytes, exception,
6357 vcpu, ops);
6358 if (rc != X86EMUL_CONTINUE)
6359 return rc;
6360
6361 if (!vcpu->mmio_nr_fragments)
6362 return rc;
6363
6364 gpa = vcpu->mmio_fragments[0].gpa;
6365
6366 vcpu->mmio_needed = 1;
6367 vcpu->mmio_cur_fragment = 0;
6368
6369 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6370 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6371 vcpu->run->exit_reason = KVM_EXIT_MMIO;
6372 vcpu->run->mmio.phys_addr = gpa;
6373
6374 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6375 }
6376
6377 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6378 unsigned long addr,
6379 void *val,
6380 unsigned int bytes,
6381 struct x86_exception *exception)
6382 {
6383 return emulator_read_write(ctxt, addr, val, bytes,
6384 exception, &read_emultor);
6385 }
6386
6387 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6388 unsigned long addr,
6389 const void *val,
6390 unsigned int bytes,
6391 struct x86_exception *exception)
6392 {
6393 return emulator_read_write(ctxt, addr, (void *)val, bytes,
6394 exception, &write_emultor);
6395 }
6396
6397 #define CMPXCHG_TYPE(t, ptr, old, new) \
6398 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6399
6400 #ifdef CONFIG_X86_64
6401 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6402 #else
6403 # define CMPXCHG64(ptr, old, new) \
6404 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6405 #endif
6406
6407 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6408 unsigned long addr,
6409 const void *old,
6410 const void *new,
6411 unsigned int bytes,
6412 struct x86_exception *exception)
6413 {
6414 struct kvm_host_map map;
6415 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6416 u64 page_line_mask;
6417 gpa_t gpa;
6418 char *kaddr;
6419 bool exchanged;
6420
6421 /* guests cmpxchg8b have to be emulated atomically */
6422 if (bytes > 8 || (bytes & (bytes - 1)))
6423 goto emul_write;
6424
6425 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6426
6427 if (gpa == UNMAPPED_GVA ||
6428 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6429 goto emul_write;
6430
6431 /*
6432 * Emulate the atomic as a straight write to avoid #AC if SLD is
6433 * enabled in the host and the access splits a cache line.
6434 */
6435 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6436 page_line_mask = ~(cache_line_size() - 1);
6437 else
6438 page_line_mask = PAGE_MASK;
6439
6440 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6441 goto emul_write;
6442
6443 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6444 goto emul_write;
6445
6446 kaddr = map.hva + offset_in_page(gpa);
6447
6448 switch (bytes) {
6449 case 1:
6450 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6451 break;
6452 case 2:
6453 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6454 break;
6455 case 4:
6456 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6457 break;
6458 case 8:
6459 exchanged = CMPXCHG64(kaddr, old, new);
6460 break;
6461 default:
6462 BUG();
6463 }
6464
6465 kvm_vcpu_unmap(vcpu, &map, true);
6466
6467 if (!exchanged)
6468 return X86EMUL_CMPXCHG_FAILED;
6469
6470 kvm_page_track_write(vcpu, gpa, new, bytes);
6471
6472 return X86EMUL_CONTINUE;
6473
6474 emul_write:
6475 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6476
6477 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6478 }
6479
6480 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6481 {
6482 int r = 0, i;
6483
6484 for (i = 0; i < vcpu->arch.pio.count; i++) {
6485 if (vcpu->arch.pio.in)
6486 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6487 vcpu->arch.pio.size, pd);
6488 else
6489 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6490 vcpu->arch.pio.port, vcpu->arch.pio.size,
6491 pd);
6492 if (r)
6493 break;
6494 pd += vcpu->arch.pio.size;
6495 }
6496 return r;
6497 }
6498
6499 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6500 unsigned short port, void *val,
6501 unsigned int count, bool in)
6502 {
6503 vcpu->arch.pio.port = port;
6504 vcpu->arch.pio.in = in;
6505 vcpu->arch.pio.count = count;
6506 vcpu->arch.pio.size = size;
6507
6508 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6509 vcpu->arch.pio.count = 0;
6510 return 1;
6511 }
6512
6513 vcpu->run->exit_reason = KVM_EXIT_IO;
6514 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6515 vcpu->run->io.size = size;
6516 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6517 vcpu->run->io.count = count;
6518 vcpu->run->io.port = port;
6519
6520 return 0;
6521 }
6522
6523 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6524 unsigned short port, void *val, unsigned int count)
6525 {
6526 int ret;
6527
6528 if (vcpu->arch.pio.count)
6529 goto data_avail;
6530
6531 memset(vcpu->arch.pio_data, 0, size * count);
6532
6533 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6534 if (ret) {
6535 data_avail:
6536 memcpy(val, vcpu->arch.pio_data, size * count);
6537 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6538 vcpu->arch.pio.count = 0;
6539 return 1;
6540 }
6541
6542 return 0;
6543 }
6544
6545 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6546 int size, unsigned short port, void *val,
6547 unsigned int count)
6548 {
6549 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6550
6551 }
6552
6553 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6554 unsigned short port, const void *val,
6555 unsigned int count)
6556 {
6557 memcpy(vcpu->arch.pio_data, val, size * count);
6558 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6559 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6560 }
6561
6562 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6563 int size, unsigned short port,
6564 const void *val, unsigned int count)
6565 {
6566 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6567 }
6568
6569 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6570 {
6571 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
6572 }
6573
6574 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6575 {
6576 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6577 }
6578
6579 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6580 {
6581 if (!need_emulate_wbinvd(vcpu))
6582 return X86EMUL_CONTINUE;
6583
6584 if (static_call(kvm_x86_has_wbinvd_exit)()) {
6585 int cpu = get_cpu();
6586
6587 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6588 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6589 wbinvd_ipi, NULL, 1);
6590 put_cpu();
6591 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6592 } else
6593 wbinvd();
6594 return X86EMUL_CONTINUE;
6595 }
6596
6597 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6598 {
6599 kvm_emulate_wbinvd_noskip(vcpu);
6600 return kvm_skip_emulated_instruction(vcpu);
6601 }
6602 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6603
6604
6605
6606 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6607 {
6608 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6609 }
6610
6611 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6612 unsigned long *dest)
6613 {
6614 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6615 }
6616
6617 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6618 unsigned long value)
6619 {
6620
6621 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6622 }
6623
6624 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6625 {
6626 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6627 }
6628
6629 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6630 {
6631 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6632 unsigned long value;
6633
6634 switch (cr) {
6635 case 0:
6636 value = kvm_read_cr0(vcpu);
6637 break;
6638 case 2:
6639 value = vcpu->arch.cr2;
6640 break;
6641 case 3:
6642 value = kvm_read_cr3(vcpu);
6643 break;
6644 case 4:
6645 value = kvm_read_cr4(vcpu);
6646 break;
6647 case 8:
6648 value = kvm_get_cr8(vcpu);
6649 break;
6650 default:
6651 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6652 return 0;
6653 }
6654
6655 return value;
6656 }
6657
6658 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6659 {
6660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6661 int res = 0;
6662
6663 switch (cr) {
6664 case 0:
6665 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6666 break;
6667 case 2:
6668 vcpu->arch.cr2 = val;
6669 break;
6670 case 3:
6671 res = kvm_set_cr3(vcpu, val);
6672 break;
6673 case 4:
6674 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6675 break;
6676 case 8:
6677 res = kvm_set_cr8(vcpu, val);
6678 break;
6679 default:
6680 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6681 res = -1;
6682 }
6683
6684 return res;
6685 }
6686
6687 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6688 {
6689 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
6690 }
6691
6692 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6693 {
6694 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
6695 }
6696
6697 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6698 {
6699 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
6700 }
6701
6702 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6703 {
6704 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
6705 }
6706
6707 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6708 {
6709 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
6710 }
6711
6712 static unsigned long emulator_get_cached_segment_base(
6713 struct x86_emulate_ctxt *ctxt, int seg)
6714 {
6715 return get_segment_base(emul_to_vcpu(ctxt), seg);
6716 }
6717
6718 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6719 struct desc_struct *desc, u32 *base3,
6720 int seg)
6721 {
6722 struct kvm_segment var;
6723
6724 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6725 *selector = var.selector;
6726
6727 if (var.unusable) {
6728 memset(desc, 0, sizeof(*desc));
6729 if (base3)
6730 *base3 = 0;
6731 return false;
6732 }
6733
6734 if (var.g)
6735 var.limit >>= 12;
6736 set_desc_limit(desc, var.limit);
6737 set_desc_base(desc, (unsigned long)var.base);
6738 #ifdef CONFIG_X86_64
6739 if (base3)
6740 *base3 = var.base >> 32;
6741 #endif
6742 desc->type = var.type;
6743 desc->s = var.s;
6744 desc->dpl = var.dpl;
6745 desc->p = var.present;
6746 desc->avl = var.avl;
6747 desc->l = var.l;
6748 desc->d = var.db;
6749 desc->g = var.g;
6750
6751 return true;
6752 }
6753
6754 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6755 struct desc_struct *desc, u32 base3,
6756 int seg)
6757 {
6758 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6759 struct kvm_segment var;
6760
6761 var.selector = selector;
6762 var.base = get_desc_base(desc);
6763 #ifdef CONFIG_X86_64
6764 var.base |= ((u64)base3) << 32;
6765 #endif
6766 var.limit = get_desc_limit(desc);
6767 if (desc->g)
6768 var.limit = (var.limit << 12) | 0xfff;
6769 var.type = desc->type;
6770 var.dpl = desc->dpl;
6771 var.db = desc->d;
6772 var.s = desc->s;
6773 var.l = desc->l;
6774 var.g = desc->g;
6775 var.avl = desc->avl;
6776 var.present = desc->p;
6777 var.unusable = !var.present;
6778 var.padding = 0;
6779
6780 kvm_set_segment(vcpu, &var, seg);
6781 return;
6782 }
6783
6784 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6785 u32 msr_index, u64 *pdata)
6786 {
6787 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6788 int r;
6789
6790 r = kvm_get_msr(vcpu, msr_index, pdata);
6791
6792 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6793 /* Bounce to user space */
6794 return X86EMUL_IO_NEEDED;
6795 }
6796
6797 return r;
6798 }
6799
6800 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6801 u32 msr_index, u64 data)
6802 {
6803 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6804 int r;
6805
6806 r = kvm_set_msr(vcpu, msr_index, data);
6807
6808 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6809 /* Bounce to user space */
6810 return X86EMUL_IO_NEEDED;
6811 }
6812
6813 return r;
6814 }
6815
6816 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6817 {
6818 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6819
6820 return vcpu->arch.smbase;
6821 }
6822
6823 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6824 {
6825 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6826
6827 vcpu->arch.smbase = smbase;
6828 }
6829
6830 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6831 u32 pmc)
6832 {
6833 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6834 }
6835
6836 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6837 u32 pmc, u64 *pdata)
6838 {
6839 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6840 }
6841
6842 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6843 {
6844 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6845 }
6846
6847 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6848 struct x86_instruction_info *info,
6849 enum x86_intercept_stage stage)
6850 {
6851 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
6852 &ctxt->exception);
6853 }
6854
6855 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6856 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6857 bool exact_only)
6858 {
6859 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6860 }
6861
6862 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6863 {
6864 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6865 }
6866
6867 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6868 {
6869 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6870 }
6871
6872 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6873 {
6874 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6875 }
6876
6877 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6878 {
6879 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6880 }
6881
6882 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6883 {
6884 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6885 }
6886
6887 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6888 {
6889 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
6890 }
6891
6892 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6893 {
6894 return emul_to_vcpu(ctxt)->arch.hflags;
6895 }
6896
6897 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6898 {
6899 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6900 }
6901
6902 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6903 const char *smstate)
6904 {
6905 return static_call(kvm_x86_pre_leave_smm)(emul_to_vcpu(ctxt), smstate);
6906 }
6907
6908 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6909 {
6910 kvm_smm_changed(emul_to_vcpu(ctxt));
6911 }
6912
6913 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6914 {
6915 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6916 }
6917
6918 static const struct x86_emulate_ops emulate_ops = {
6919 .read_gpr = emulator_read_gpr,
6920 .write_gpr = emulator_write_gpr,
6921 .read_std = emulator_read_std,
6922 .write_std = emulator_write_std,
6923 .read_phys = kvm_read_guest_phys_system,
6924 .fetch = kvm_fetch_guest_virt,
6925 .read_emulated = emulator_read_emulated,
6926 .write_emulated = emulator_write_emulated,
6927 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6928 .invlpg = emulator_invlpg,
6929 .pio_in_emulated = emulator_pio_in_emulated,
6930 .pio_out_emulated = emulator_pio_out_emulated,
6931 .get_segment = emulator_get_segment,
6932 .set_segment = emulator_set_segment,
6933 .get_cached_segment_base = emulator_get_cached_segment_base,
6934 .get_gdt = emulator_get_gdt,
6935 .get_idt = emulator_get_idt,
6936 .set_gdt = emulator_set_gdt,
6937 .set_idt = emulator_set_idt,
6938 .get_cr = emulator_get_cr,
6939 .set_cr = emulator_set_cr,
6940 .cpl = emulator_get_cpl,
6941 .get_dr = emulator_get_dr,
6942 .set_dr = emulator_set_dr,
6943 .get_smbase = emulator_get_smbase,
6944 .set_smbase = emulator_set_smbase,
6945 .set_msr = emulator_set_msr,
6946 .get_msr = emulator_get_msr,
6947 .check_pmc = emulator_check_pmc,
6948 .read_pmc = emulator_read_pmc,
6949 .halt = emulator_halt,
6950 .wbinvd = emulator_wbinvd,
6951 .fix_hypercall = emulator_fix_hypercall,
6952 .intercept = emulator_intercept,
6953 .get_cpuid = emulator_get_cpuid,
6954 .guest_has_long_mode = emulator_guest_has_long_mode,
6955 .guest_has_movbe = emulator_guest_has_movbe,
6956 .guest_has_fxsr = emulator_guest_has_fxsr,
6957 .set_nmi_mask = emulator_set_nmi_mask,
6958 .get_hflags = emulator_get_hflags,
6959 .set_hflags = emulator_set_hflags,
6960 .pre_leave_smm = emulator_pre_leave_smm,
6961 .post_leave_smm = emulator_post_leave_smm,
6962 .set_xcr = emulator_set_xcr,
6963 };
6964
6965 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6966 {
6967 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
6968 /*
6969 * an sti; sti; sequence only disable interrupts for the first
6970 * instruction. So, if the last instruction, be it emulated or
6971 * not, left the system with the INT_STI flag enabled, it
6972 * means that the last instruction is an sti. We should not
6973 * leave the flag on in this case. The same goes for mov ss
6974 */
6975 if (int_shadow & mask)
6976 mask = 0;
6977 if (unlikely(int_shadow || mask)) {
6978 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
6979 if (!mask)
6980 kvm_make_request(KVM_REQ_EVENT, vcpu);
6981 }
6982 }
6983
6984 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6985 {
6986 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6987 if (ctxt->exception.vector == PF_VECTOR)
6988 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6989
6990 if (ctxt->exception.error_code_valid)
6991 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6992 ctxt->exception.error_code);
6993 else
6994 kvm_queue_exception(vcpu, ctxt->exception.vector);
6995 return false;
6996 }
6997
6998 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6999 {
7000 struct x86_emulate_ctxt *ctxt;
7001
7002 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
7003 if (!ctxt) {
7004 pr_err("kvm: failed to allocate vcpu's emulator\n");
7005 return NULL;
7006 }
7007
7008 ctxt->vcpu = vcpu;
7009 ctxt->ops = &emulate_ops;
7010 vcpu->arch.emulate_ctxt = ctxt;
7011
7012 return ctxt;
7013 }
7014
7015 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
7016 {
7017 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7018 int cs_db, cs_l;
7019
7020 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
7021
7022 ctxt->gpa_available = false;
7023 ctxt->eflags = kvm_get_rflags(vcpu);
7024 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
7025
7026 ctxt->eip = kvm_rip_read(vcpu);
7027 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
7028 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
7029 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
7030 cs_db ? X86EMUL_MODE_PROT32 :
7031 X86EMUL_MODE_PROT16;
7032 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
7033 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
7034 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
7035
7036 init_decode_cache(ctxt);
7037 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7038 }
7039
7040 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
7041 {
7042 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7043 int ret;
7044
7045 init_emulate_ctxt(vcpu);
7046
7047 ctxt->op_bytes = 2;
7048 ctxt->ad_bytes = 2;
7049 ctxt->_eip = ctxt->eip + inc_eip;
7050 ret = emulate_int_real(ctxt, irq);
7051
7052 if (ret != X86EMUL_CONTINUE) {
7053 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7054 } else {
7055 ctxt->eip = ctxt->_eip;
7056 kvm_rip_write(vcpu, ctxt->eip);
7057 kvm_set_rflags(vcpu, ctxt->eflags);
7058 }
7059 }
7060 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
7061
7062 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
7063 {
7064 ++vcpu->stat.insn_emulation_fail;
7065 trace_kvm_emulate_insn_failed(vcpu);
7066
7067 if (emulation_type & EMULTYPE_VMWARE_GP) {
7068 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7069 return 1;
7070 }
7071
7072 if (emulation_type & EMULTYPE_SKIP) {
7073 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7074 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7075 vcpu->run->internal.ndata = 0;
7076 return 0;
7077 }
7078
7079 kvm_queue_exception(vcpu, UD_VECTOR);
7080
7081 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
7082 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7083 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7084 vcpu->run->internal.ndata = 0;
7085 return 0;
7086 }
7087
7088 return 1;
7089 }
7090
7091 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7092 bool write_fault_to_shadow_pgtable,
7093 int emulation_type)
7094 {
7095 gpa_t gpa = cr2_or_gpa;
7096 kvm_pfn_t pfn;
7097
7098 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7099 return false;
7100
7101 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7102 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7103 return false;
7104
7105 if (!vcpu->arch.mmu->direct_map) {
7106 /*
7107 * Write permission should be allowed since only
7108 * write access need to be emulated.
7109 */
7110 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7111
7112 /*
7113 * If the mapping is invalid in guest, let cpu retry
7114 * it to generate fault.
7115 */
7116 if (gpa == UNMAPPED_GVA)
7117 return true;
7118 }
7119
7120 /*
7121 * Do not retry the unhandleable instruction if it faults on the
7122 * readonly host memory, otherwise it will goto a infinite loop:
7123 * retry instruction -> write #PF -> emulation fail -> retry
7124 * instruction -> ...
7125 */
7126 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
7127
7128 /*
7129 * If the instruction failed on the error pfn, it can not be fixed,
7130 * report the error to userspace.
7131 */
7132 if (is_error_noslot_pfn(pfn))
7133 return false;
7134
7135 kvm_release_pfn_clean(pfn);
7136
7137 /* The instructions are well-emulated on direct mmu. */
7138 if (vcpu->arch.mmu->direct_map) {
7139 unsigned int indirect_shadow_pages;
7140
7141 write_lock(&vcpu->kvm->mmu_lock);
7142 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
7143 write_unlock(&vcpu->kvm->mmu_lock);
7144
7145 if (indirect_shadow_pages)
7146 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7147
7148 return true;
7149 }
7150
7151 /*
7152 * if emulation was due to access to shadowed page table
7153 * and it failed try to unshadow page and re-enter the
7154 * guest to let CPU execute the instruction.
7155 */
7156 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7157
7158 /*
7159 * If the access faults on its page table, it can not
7160 * be fixed by unprotecting shadow page and it should
7161 * be reported to userspace.
7162 */
7163 return !write_fault_to_shadow_pgtable;
7164 }
7165
7166 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7167 gpa_t cr2_or_gpa, int emulation_type)
7168 {
7169 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7170 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7171
7172 last_retry_eip = vcpu->arch.last_retry_eip;
7173 last_retry_addr = vcpu->arch.last_retry_addr;
7174
7175 /*
7176 * If the emulation is caused by #PF and it is non-page_table
7177 * writing instruction, it means the VM-EXIT is caused by shadow
7178 * page protected, we can zap the shadow page and retry this
7179 * instruction directly.
7180 *
7181 * Note: if the guest uses a non-page-table modifying instruction
7182 * on the PDE that points to the instruction, then we will unmap
7183 * the instruction and go to an infinite loop. So, we cache the
7184 * last retried eip and the last fault address, if we meet the eip
7185 * and the address again, we can break out of the potential infinite
7186 * loop.
7187 */
7188 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7189
7190 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7191 return false;
7192
7193 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7194 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7195 return false;
7196
7197 if (x86_page_table_writing_insn(ctxt))
7198 return false;
7199
7200 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7201 return false;
7202
7203 vcpu->arch.last_retry_eip = ctxt->eip;
7204 vcpu->arch.last_retry_addr = cr2_or_gpa;
7205
7206 if (!vcpu->arch.mmu->direct_map)
7207 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7208
7209 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7210
7211 return true;
7212 }
7213
7214 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7215 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7216
7217 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7218 {
7219 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7220 /* This is a good place to trace that we are exiting SMM. */
7221 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7222
7223 /* Process a latched INIT or SMI, if any. */
7224 kvm_make_request(KVM_REQ_EVENT, vcpu);
7225 }
7226
7227 kvm_mmu_reset_context(vcpu);
7228 }
7229
7230 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7231 unsigned long *db)
7232 {
7233 u32 dr6 = 0;
7234 int i;
7235 u32 enable, rwlen;
7236
7237 enable = dr7;
7238 rwlen = dr7 >> 16;
7239 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7240 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7241 dr6 |= (1 << i);
7242 return dr6;
7243 }
7244
7245 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7246 {
7247 struct kvm_run *kvm_run = vcpu->run;
7248
7249 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7250 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
7251 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7252 kvm_run->debug.arch.exception = DB_VECTOR;
7253 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7254 return 0;
7255 }
7256 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7257 return 1;
7258 }
7259
7260 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7261 {
7262 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
7263 int r;
7264
7265 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
7266 if (unlikely(!r))
7267 return 0;
7268
7269 /*
7270 * rflags is the old, "raw" value of the flags. The new value has
7271 * not been saved yet.
7272 *
7273 * This is correct even for TF set by the guest, because "the
7274 * processor will not generate this exception after the instruction
7275 * that sets the TF flag".
7276 */
7277 if (unlikely(rflags & X86_EFLAGS_TF))
7278 r = kvm_vcpu_do_singlestep(vcpu);
7279 return r;
7280 }
7281 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7282
7283 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7284 {
7285 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7286 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7287 struct kvm_run *kvm_run = vcpu->run;
7288 unsigned long eip = kvm_get_linear_rip(vcpu);
7289 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7290 vcpu->arch.guest_debug_dr7,
7291 vcpu->arch.eff_db);
7292
7293 if (dr6 != 0) {
7294 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
7295 kvm_run->debug.arch.pc = eip;
7296 kvm_run->debug.arch.exception = DB_VECTOR;
7297 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7298 *r = 0;
7299 return true;
7300 }
7301 }
7302
7303 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7304 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7305 unsigned long eip = kvm_get_linear_rip(vcpu);
7306 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7307 vcpu->arch.dr7,
7308 vcpu->arch.db);
7309
7310 if (dr6 != 0) {
7311 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7312 *r = 1;
7313 return true;
7314 }
7315 }
7316
7317 return false;
7318 }
7319
7320 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7321 {
7322 switch (ctxt->opcode_len) {
7323 case 1:
7324 switch (ctxt->b) {
7325 case 0xe4: /* IN */
7326 case 0xe5:
7327 case 0xec:
7328 case 0xed:
7329 case 0xe6: /* OUT */
7330 case 0xe7:
7331 case 0xee:
7332 case 0xef:
7333 case 0x6c: /* INS */
7334 case 0x6d:
7335 case 0x6e: /* OUTS */
7336 case 0x6f:
7337 return true;
7338 }
7339 break;
7340 case 2:
7341 switch (ctxt->b) {
7342 case 0x33: /* RDPMC */
7343 return true;
7344 }
7345 break;
7346 }
7347
7348 return false;
7349 }
7350
7351 /*
7352 * Decode to be emulated instruction. Return EMULATION_OK if success.
7353 */
7354 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
7355 void *insn, int insn_len)
7356 {
7357 int r = EMULATION_OK;
7358 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7359
7360 init_emulate_ctxt(vcpu);
7361
7362 /*
7363 * We will reenter on the same instruction since we do not set
7364 * complete_userspace_io. This does not handle watchpoints yet,
7365 * those would be handled in the emulate_ops.
7366 */
7367 if (!(emulation_type & EMULTYPE_SKIP) &&
7368 kvm_vcpu_check_breakpoint(vcpu, &r))
7369 return r;
7370
7371 ctxt->interruptibility = 0;
7372 ctxt->have_exception = false;
7373 ctxt->exception.vector = -1;
7374 ctxt->perm_ok = false;
7375
7376 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7377
7378 r = x86_decode_insn(ctxt, insn, insn_len);
7379
7380 trace_kvm_emulate_insn_start(vcpu);
7381 ++vcpu->stat.insn_emulation;
7382
7383 return r;
7384 }
7385 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
7386
7387 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7388 int emulation_type, void *insn, int insn_len)
7389 {
7390 int r;
7391 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7392 bool writeback = true;
7393 bool write_fault_to_spt;
7394
7395 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len)))
7396 return 1;
7397
7398 vcpu->arch.l1tf_flush_l1d = true;
7399
7400 /*
7401 * Clear write_fault_to_shadow_pgtable here to ensure it is
7402 * never reused.
7403 */
7404 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7405 vcpu->arch.write_fault_to_shadow_pgtable = false;
7406
7407 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7408 kvm_clear_exception_queue(vcpu);
7409
7410 r = x86_decode_emulated_instruction(vcpu, emulation_type,
7411 insn, insn_len);
7412 if (r != EMULATION_OK) {
7413 if ((emulation_type & EMULTYPE_TRAP_UD) ||
7414 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7415 kvm_queue_exception(vcpu, UD_VECTOR);
7416 return 1;
7417 }
7418 if (reexecute_instruction(vcpu, cr2_or_gpa,
7419 write_fault_to_spt,
7420 emulation_type))
7421 return 1;
7422 if (ctxt->have_exception) {
7423 /*
7424 * #UD should result in just EMULATION_FAILED, and trap-like
7425 * exception should not be encountered during decode.
7426 */
7427 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7428 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7429 inject_emulated_exception(vcpu);
7430 return 1;
7431 }
7432 return handle_emulation_failure(vcpu, emulation_type);
7433 }
7434 }
7435
7436 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7437 !is_vmware_backdoor_opcode(ctxt)) {
7438 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7439 return 1;
7440 }
7441
7442 /*
7443 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7444 * for kvm_skip_emulated_instruction(). The caller is responsible for
7445 * updating interruptibility state and injecting single-step #DBs.
7446 */
7447 if (emulation_type & EMULTYPE_SKIP) {
7448 kvm_rip_write(vcpu, ctxt->_eip);
7449 if (ctxt->eflags & X86_EFLAGS_RF)
7450 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7451 return 1;
7452 }
7453
7454 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7455 return 1;
7456
7457 /* this is needed for vmware backdoor interface to work since it
7458 changes registers values during IO operation */
7459 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7460 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7461 emulator_invalidate_register_cache(ctxt);
7462 }
7463
7464 restart:
7465 if (emulation_type & EMULTYPE_PF) {
7466 /* Save the faulting GPA (cr2) in the address field */
7467 ctxt->exception.address = cr2_or_gpa;
7468
7469 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7470 if (vcpu->arch.mmu->direct_map) {
7471 ctxt->gpa_available = true;
7472 ctxt->gpa_val = cr2_or_gpa;
7473 }
7474 } else {
7475 /* Sanitize the address out of an abundance of paranoia. */
7476 ctxt->exception.address = 0;
7477 }
7478
7479 r = x86_emulate_insn(ctxt);
7480
7481 if (r == EMULATION_INTERCEPTED)
7482 return 1;
7483
7484 if (r == EMULATION_FAILED) {
7485 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7486 emulation_type))
7487 return 1;
7488
7489 return handle_emulation_failure(vcpu, emulation_type);
7490 }
7491
7492 if (ctxt->have_exception) {
7493 r = 1;
7494 if (inject_emulated_exception(vcpu))
7495 return r;
7496 } else if (vcpu->arch.pio.count) {
7497 if (!vcpu->arch.pio.in) {
7498 /* FIXME: return into emulator if single-stepping. */
7499 vcpu->arch.pio.count = 0;
7500 } else {
7501 writeback = false;
7502 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7503 }
7504 r = 0;
7505 } else if (vcpu->mmio_needed) {
7506 ++vcpu->stat.mmio_exits;
7507
7508 if (!vcpu->mmio_is_write)
7509 writeback = false;
7510 r = 0;
7511 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7512 } else if (r == EMULATION_RESTART)
7513 goto restart;
7514 else
7515 r = 1;
7516
7517 if (writeback) {
7518 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
7519 toggle_interruptibility(vcpu, ctxt->interruptibility);
7520 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7521 if (!ctxt->have_exception ||
7522 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7523 kvm_rip_write(vcpu, ctxt->eip);
7524 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7525 r = kvm_vcpu_do_singlestep(vcpu);
7526 if (kvm_x86_ops.update_emulated_instruction)
7527 static_call(kvm_x86_update_emulated_instruction)(vcpu);
7528 __kvm_set_rflags(vcpu, ctxt->eflags);
7529 }
7530
7531 /*
7532 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7533 * do nothing, and it will be requested again as soon as
7534 * the shadow expires. But we still need to check here,
7535 * because POPF has no interrupt shadow.
7536 */
7537 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7538 kvm_make_request(KVM_REQ_EVENT, vcpu);
7539 } else
7540 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7541
7542 return r;
7543 }
7544
7545 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7546 {
7547 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7548 }
7549 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7550
7551 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7552 void *insn, int insn_len)
7553 {
7554 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7555 }
7556 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7557
7558 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7559 {
7560 vcpu->arch.pio.count = 0;
7561 return 1;
7562 }
7563
7564 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7565 {
7566 vcpu->arch.pio.count = 0;
7567
7568 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7569 return 1;
7570
7571 return kvm_skip_emulated_instruction(vcpu);
7572 }
7573
7574 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7575 unsigned short port)
7576 {
7577 unsigned long val = kvm_rax_read(vcpu);
7578 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7579
7580 if (ret)
7581 return ret;
7582
7583 /*
7584 * Workaround userspace that relies on old KVM behavior of %rip being
7585 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7586 */
7587 if (port == 0x7e &&
7588 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7589 vcpu->arch.complete_userspace_io =
7590 complete_fast_pio_out_port_0x7e;
7591 kvm_skip_emulated_instruction(vcpu);
7592 } else {
7593 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7594 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7595 }
7596 return 0;
7597 }
7598
7599 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7600 {
7601 unsigned long val;
7602
7603 /* We should only ever be called with arch.pio.count equal to 1 */
7604 BUG_ON(vcpu->arch.pio.count != 1);
7605
7606 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7607 vcpu->arch.pio.count = 0;
7608 return 1;
7609 }
7610
7611 /* For size less than 4 we merge, else we zero extend */
7612 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7613
7614 /*
7615 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7616 * the copy and tracing
7617 */
7618 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7619 kvm_rax_write(vcpu, val);
7620
7621 return kvm_skip_emulated_instruction(vcpu);
7622 }
7623
7624 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7625 unsigned short port)
7626 {
7627 unsigned long val;
7628 int ret;
7629
7630 /* For size less than 4 we merge, else we zero extend */
7631 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7632
7633 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7634 if (ret) {
7635 kvm_rax_write(vcpu, val);
7636 return ret;
7637 }
7638
7639 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7640 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7641
7642 return 0;
7643 }
7644
7645 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7646 {
7647 int ret;
7648
7649 if (in)
7650 ret = kvm_fast_pio_in(vcpu, size, port);
7651 else
7652 ret = kvm_fast_pio_out(vcpu, size, port);
7653 return ret && kvm_skip_emulated_instruction(vcpu);
7654 }
7655 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7656
7657 static int kvmclock_cpu_down_prep(unsigned int cpu)
7658 {
7659 __this_cpu_write(cpu_tsc_khz, 0);
7660 return 0;
7661 }
7662
7663 static void tsc_khz_changed(void *data)
7664 {
7665 struct cpufreq_freqs *freq = data;
7666 unsigned long khz = 0;
7667
7668 if (data)
7669 khz = freq->new;
7670 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7671 khz = cpufreq_quick_get(raw_smp_processor_id());
7672 if (!khz)
7673 khz = tsc_khz;
7674 __this_cpu_write(cpu_tsc_khz, khz);
7675 }
7676
7677 #ifdef CONFIG_X86_64
7678 static void kvm_hyperv_tsc_notifier(void)
7679 {
7680 struct kvm *kvm;
7681 struct kvm_vcpu *vcpu;
7682 int cpu;
7683
7684 mutex_lock(&kvm_lock);
7685 list_for_each_entry(kvm, &vm_list, vm_list)
7686 kvm_make_mclock_inprogress_request(kvm);
7687
7688 hyperv_stop_tsc_emulation();
7689
7690 /* TSC frequency always matches when on Hyper-V */
7691 for_each_present_cpu(cpu)
7692 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7693 kvm_max_guest_tsc_khz = tsc_khz;
7694
7695 list_for_each_entry(kvm, &vm_list, vm_list) {
7696 struct kvm_arch *ka = &kvm->arch;
7697
7698 spin_lock(&ka->pvclock_gtod_sync_lock);
7699
7700 pvclock_update_vm_gtod_copy(kvm);
7701
7702 kvm_for_each_vcpu(cpu, vcpu, kvm)
7703 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7704
7705 kvm_for_each_vcpu(cpu, vcpu, kvm)
7706 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7707
7708 spin_unlock(&ka->pvclock_gtod_sync_lock);
7709 }
7710 mutex_unlock(&kvm_lock);
7711 }
7712 #endif
7713
7714 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7715 {
7716 struct kvm *kvm;
7717 struct kvm_vcpu *vcpu;
7718 int i, send_ipi = 0;
7719
7720 /*
7721 * We allow guests to temporarily run on slowing clocks,
7722 * provided we notify them after, or to run on accelerating
7723 * clocks, provided we notify them before. Thus time never
7724 * goes backwards.
7725 *
7726 * However, we have a problem. We can't atomically update
7727 * the frequency of a given CPU from this function; it is
7728 * merely a notifier, which can be called from any CPU.
7729 * Changing the TSC frequency at arbitrary points in time
7730 * requires a recomputation of local variables related to
7731 * the TSC for each VCPU. We must flag these local variables
7732 * to be updated and be sure the update takes place with the
7733 * new frequency before any guests proceed.
7734 *
7735 * Unfortunately, the combination of hotplug CPU and frequency
7736 * change creates an intractable locking scenario; the order
7737 * of when these callouts happen is undefined with respect to
7738 * CPU hotplug, and they can race with each other. As such,
7739 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7740 * undefined; you can actually have a CPU frequency change take
7741 * place in between the computation of X and the setting of the
7742 * variable. To protect against this problem, all updates of
7743 * the per_cpu tsc_khz variable are done in an interrupt
7744 * protected IPI, and all callers wishing to update the value
7745 * must wait for a synchronous IPI to complete (which is trivial
7746 * if the caller is on the CPU already). This establishes the
7747 * necessary total order on variable updates.
7748 *
7749 * Note that because a guest time update may take place
7750 * anytime after the setting of the VCPU's request bit, the
7751 * correct TSC value must be set before the request. However,
7752 * to ensure the update actually makes it to any guest which
7753 * starts running in hardware virtualization between the set
7754 * and the acquisition of the spinlock, we must also ping the
7755 * CPU after setting the request bit.
7756 *
7757 */
7758
7759 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7760
7761 mutex_lock(&kvm_lock);
7762 list_for_each_entry(kvm, &vm_list, vm_list) {
7763 kvm_for_each_vcpu(i, vcpu, kvm) {
7764 if (vcpu->cpu != cpu)
7765 continue;
7766 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7767 if (vcpu->cpu != raw_smp_processor_id())
7768 send_ipi = 1;
7769 }
7770 }
7771 mutex_unlock(&kvm_lock);
7772
7773 if (freq->old < freq->new && send_ipi) {
7774 /*
7775 * We upscale the frequency. Must make the guest
7776 * doesn't see old kvmclock values while running with
7777 * the new frequency, otherwise we risk the guest sees
7778 * time go backwards.
7779 *
7780 * In case we update the frequency for another cpu
7781 * (which might be in guest context) send an interrupt
7782 * to kick the cpu out of guest context. Next time
7783 * guest context is entered kvmclock will be updated,
7784 * so the guest will not see stale values.
7785 */
7786 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7787 }
7788 }
7789
7790 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7791 void *data)
7792 {
7793 struct cpufreq_freqs *freq = data;
7794 int cpu;
7795
7796 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7797 return 0;
7798 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7799 return 0;
7800
7801 for_each_cpu(cpu, freq->policy->cpus)
7802 __kvmclock_cpufreq_notifier(freq, cpu);
7803
7804 return 0;
7805 }
7806
7807 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7808 .notifier_call = kvmclock_cpufreq_notifier
7809 };
7810
7811 static int kvmclock_cpu_online(unsigned int cpu)
7812 {
7813 tsc_khz_changed(NULL);
7814 return 0;
7815 }
7816
7817 static void kvm_timer_init(void)
7818 {
7819 max_tsc_khz = tsc_khz;
7820
7821 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7822 #ifdef CONFIG_CPU_FREQ
7823 struct cpufreq_policy *policy;
7824 int cpu;
7825
7826 cpu = get_cpu();
7827 policy = cpufreq_cpu_get(cpu);
7828 if (policy) {
7829 if (policy->cpuinfo.max_freq)
7830 max_tsc_khz = policy->cpuinfo.max_freq;
7831 cpufreq_cpu_put(policy);
7832 }
7833 put_cpu();
7834 #endif
7835 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7836 CPUFREQ_TRANSITION_NOTIFIER);
7837 }
7838
7839 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7840 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7841 }
7842
7843 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7844 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7845
7846 int kvm_is_in_guest(void)
7847 {
7848 return __this_cpu_read(current_vcpu) != NULL;
7849 }
7850
7851 static int kvm_is_user_mode(void)
7852 {
7853 int user_mode = 3;
7854
7855 if (__this_cpu_read(current_vcpu))
7856 user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu));
7857
7858 return user_mode != 0;
7859 }
7860
7861 static unsigned long kvm_get_guest_ip(void)
7862 {
7863 unsigned long ip = 0;
7864
7865 if (__this_cpu_read(current_vcpu))
7866 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7867
7868 return ip;
7869 }
7870
7871 static void kvm_handle_intel_pt_intr(void)
7872 {
7873 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7874
7875 kvm_make_request(KVM_REQ_PMI, vcpu);
7876 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7877 (unsigned long *)&vcpu->arch.pmu.global_status);
7878 }
7879
7880 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7881 .is_in_guest = kvm_is_in_guest,
7882 .is_user_mode = kvm_is_user_mode,
7883 .get_guest_ip = kvm_get_guest_ip,
7884 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7885 };
7886
7887 #ifdef CONFIG_X86_64
7888 static void pvclock_gtod_update_fn(struct work_struct *work)
7889 {
7890 struct kvm *kvm;
7891
7892 struct kvm_vcpu *vcpu;
7893 int i;
7894
7895 mutex_lock(&kvm_lock);
7896 list_for_each_entry(kvm, &vm_list, vm_list)
7897 kvm_for_each_vcpu(i, vcpu, kvm)
7898 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7899 atomic_set(&kvm_guest_has_master_clock, 0);
7900 mutex_unlock(&kvm_lock);
7901 }
7902
7903 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7904
7905 /*
7906 * Notification about pvclock gtod data update.
7907 */
7908 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7909 void *priv)
7910 {
7911 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7912 struct timekeeper *tk = priv;
7913
7914 update_pvclock_gtod(tk);
7915
7916 /* disable master clock if host does not trust, or does not
7917 * use, TSC based clocksource.
7918 */
7919 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7920 atomic_read(&kvm_guest_has_master_clock) != 0)
7921 queue_work(system_long_wq, &pvclock_gtod_work);
7922
7923 return 0;
7924 }
7925
7926 static struct notifier_block pvclock_gtod_notifier = {
7927 .notifier_call = pvclock_gtod_notify,
7928 };
7929 #endif
7930
7931 int kvm_arch_init(void *opaque)
7932 {
7933 struct kvm_x86_init_ops *ops = opaque;
7934 int r;
7935
7936 if (kvm_x86_ops.hardware_enable) {
7937 printk(KERN_ERR "kvm: already loaded the other module\n");
7938 r = -EEXIST;
7939 goto out;
7940 }
7941
7942 if (!ops->cpu_has_kvm_support()) {
7943 pr_err_ratelimited("kvm: no hardware support\n");
7944 r = -EOPNOTSUPP;
7945 goto out;
7946 }
7947 if (ops->disabled_by_bios()) {
7948 pr_err_ratelimited("kvm: disabled by bios\n");
7949 r = -EOPNOTSUPP;
7950 goto out;
7951 }
7952
7953 /*
7954 * KVM explicitly assumes that the guest has an FPU and
7955 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7956 * vCPU's FPU state as a fxregs_state struct.
7957 */
7958 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7959 printk(KERN_ERR "kvm: inadequate fpu\n");
7960 r = -EOPNOTSUPP;
7961 goto out;
7962 }
7963
7964 r = -ENOMEM;
7965 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7966 __alignof__(struct fpu), SLAB_ACCOUNT,
7967 NULL);
7968 if (!x86_fpu_cache) {
7969 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7970 goto out;
7971 }
7972
7973 x86_emulator_cache = kvm_alloc_emulator_cache();
7974 if (!x86_emulator_cache) {
7975 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7976 goto out_free_x86_fpu_cache;
7977 }
7978
7979 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7980 if (!user_return_msrs) {
7981 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7982 goto out_free_x86_emulator_cache;
7983 }
7984
7985 r = kvm_mmu_module_init();
7986 if (r)
7987 goto out_free_percpu;
7988
7989 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7990 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7991 PT_PRESENT_MASK, 0, sme_me_mask);
7992 kvm_timer_init();
7993
7994 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7995
7996 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7997 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7998 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7999 }
8000
8001 if (pi_inject_timer == -1)
8002 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
8003 #ifdef CONFIG_X86_64
8004 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
8005
8006 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8007 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
8008 #endif
8009
8010 return 0;
8011
8012 out_free_percpu:
8013 free_percpu(user_return_msrs);
8014 out_free_x86_emulator_cache:
8015 kmem_cache_destroy(x86_emulator_cache);
8016 out_free_x86_fpu_cache:
8017 kmem_cache_destroy(x86_fpu_cache);
8018 out:
8019 return r;
8020 }
8021
8022 void kvm_arch_exit(void)
8023 {
8024 #ifdef CONFIG_X86_64
8025 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8026 clear_hv_tscchange_cb();
8027 #endif
8028 kvm_lapic_exit();
8029 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
8030
8031 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8032 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
8033 CPUFREQ_TRANSITION_NOTIFIER);
8034 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
8035 #ifdef CONFIG_X86_64
8036 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
8037 #endif
8038 kvm_x86_ops.hardware_enable = NULL;
8039 kvm_mmu_module_exit();
8040 free_percpu(user_return_msrs);
8041 kmem_cache_destroy(x86_fpu_cache);
8042 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
8043 }
8044
8045 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason)
8046 {
8047 ++vcpu->stat.halt_exits;
8048 if (lapic_in_kernel(vcpu)) {
8049 vcpu->arch.mp_state = state;
8050 return 1;
8051 } else {
8052 vcpu->run->exit_reason = reason;
8053 return 0;
8054 }
8055 }
8056
8057 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8058 {
8059 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
8060 }
8061 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
8062
8063 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
8064 {
8065 int ret = kvm_skip_emulated_instruction(vcpu);
8066 /*
8067 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
8068 * KVM_EXIT_DEBUG here.
8069 */
8070 return kvm_vcpu_halt(vcpu) && ret;
8071 }
8072 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
8073
8074 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
8075 {
8076 int ret = kvm_skip_emulated_instruction(vcpu);
8077
8078 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret;
8079 }
8080 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
8081
8082 #ifdef CONFIG_X86_64
8083 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
8084 unsigned long clock_type)
8085 {
8086 struct kvm_clock_pairing clock_pairing;
8087 struct timespec64 ts;
8088 u64 cycle;
8089 int ret;
8090
8091 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
8092 return -KVM_EOPNOTSUPP;
8093
8094 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
8095 return -KVM_EOPNOTSUPP;
8096
8097 clock_pairing.sec = ts.tv_sec;
8098 clock_pairing.nsec = ts.tv_nsec;
8099 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
8100 clock_pairing.flags = 0;
8101 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
8102
8103 ret = 0;
8104 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
8105 sizeof(struct kvm_clock_pairing)))
8106 ret = -KVM_EFAULT;
8107
8108 return ret;
8109 }
8110 #endif
8111
8112 /*
8113 * kvm_pv_kick_cpu_op: Kick a vcpu.
8114 *
8115 * @apicid - apicid of vcpu to be kicked.
8116 */
8117 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
8118 {
8119 struct kvm_lapic_irq lapic_irq;
8120
8121 lapic_irq.shorthand = APIC_DEST_NOSHORT;
8122 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
8123 lapic_irq.level = 0;
8124 lapic_irq.dest_id = apicid;
8125 lapic_irq.msi_redir_hint = false;
8126
8127 lapic_irq.delivery_mode = APIC_DM_REMRD;
8128 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
8129 }
8130
8131 bool kvm_apicv_activated(struct kvm *kvm)
8132 {
8133 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
8134 }
8135 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
8136
8137 void kvm_apicv_init(struct kvm *kvm, bool enable)
8138 {
8139 if (enable)
8140 clear_bit(APICV_INHIBIT_REASON_DISABLE,
8141 &kvm->arch.apicv_inhibit_reasons);
8142 else
8143 set_bit(APICV_INHIBIT_REASON_DISABLE,
8144 &kvm->arch.apicv_inhibit_reasons);
8145 }
8146 EXPORT_SYMBOL_GPL(kvm_apicv_init);
8147
8148 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
8149 {
8150 struct kvm_vcpu *target = NULL;
8151 struct kvm_apic_map *map;
8152
8153 rcu_read_lock();
8154 map = rcu_dereference(kvm->arch.apic_map);
8155
8156 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
8157 target = map->phys_map[dest_id]->vcpu;
8158
8159 rcu_read_unlock();
8160
8161 if (target && READ_ONCE(target->ready))
8162 kvm_vcpu_yield_to(target);
8163 }
8164
8165 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
8166 {
8167 unsigned long nr, a0, a1, a2, a3, ret;
8168 int op_64_bit;
8169
8170 if (kvm_xen_hypercall_enabled(vcpu->kvm))
8171 return kvm_xen_hypercall(vcpu);
8172
8173 if (kvm_hv_hypercall_enabled(vcpu))
8174 return kvm_hv_hypercall(vcpu);
8175
8176 nr = kvm_rax_read(vcpu);
8177 a0 = kvm_rbx_read(vcpu);
8178 a1 = kvm_rcx_read(vcpu);
8179 a2 = kvm_rdx_read(vcpu);
8180 a3 = kvm_rsi_read(vcpu);
8181
8182 trace_kvm_hypercall(nr, a0, a1, a2, a3);
8183
8184 op_64_bit = is_64_bit_mode(vcpu);
8185 if (!op_64_bit) {
8186 nr &= 0xFFFFFFFF;
8187 a0 &= 0xFFFFFFFF;
8188 a1 &= 0xFFFFFFFF;
8189 a2 &= 0xFFFFFFFF;
8190 a3 &= 0xFFFFFFFF;
8191 }
8192
8193 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
8194 ret = -KVM_EPERM;
8195 goto out;
8196 }
8197
8198 ret = -KVM_ENOSYS;
8199
8200 switch (nr) {
8201 case KVM_HC_VAPIC_POLL_IRQ:
8202 ret = 0;
8203 break;
8204 case KVM_HC_KICK_CPU:
8205 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
8206 break;
8207
8208 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8209 kvm_sched_yield(vcpu->kvm, a1);
8210 ret = 0;
8211 break;
8212 #ifdef CONFIG_X86_64
8213 case KVM_HC_CLOCK_PAIRING:
8214 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8215 break;
8216 #endif
8217 case KVM_HC_SEND_IPI:
8218 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
8219 break;
8220
8221 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8222 break;
8223 case KVM_HC_SCHED_YIELD:
8224 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
8225 break;
8226
8227 kvm_sched_yield(vcpu->kvm, a0);
8228 ret = 0;
8229 break;
8230 default:
8231 ret = -KVM_ENOSYS;
8232 break;
8233 }
8234 out:
8235 if (!op_64_bit)
8236 ret = (u32)ret;
8237 kvm_rax_write(vcpu, ret);
8238
8239 ++vcpu->stat.hypercalls;
8240 return kvm_skip_emulated_instruction(vcpu);
8241 }
8242 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8243
8244 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8245 {
8246 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8247 char instruction[3];
8248 unsigned long rip = kvm_rip_read(vcpu);
8249
8250 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
8251
8252 return emulator_write_emulated(ctxt, rip, instruction, 3,
8253 &ctxt->exception);
8254 }
8255
8256 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8257 {
8258 return vcpu->run->request_interrupt_window &&
8259 likely(!pic_in_kernel(vcpu->kvm));
8260 }
8261
8262 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8263 {
8264 struct kvm_run *kvm_run = vcpu->run;
8265
8266 /*
8267 * if_flag is obsolete and useless, so do not bother
8268 * setting it for SEV-ES guests. Userspace can just
8269 * use kvm_run->ready_for_interrupt_injection.
8270 */
8271 kvm_run->if_flag = !vcpu->arch.guest_state_protected
8272 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8273
8274 kvm_run->cr8 = kvm_get_cr8(vcpu);
8275 kvm_run->apic_base = kvm_get_apic_base(vcpu);
8276 kvm_run->ready_for_interrupt_injection =
8277 pic_in_kernel(vcpu->kvm) ||
8278 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8279
8280 if (is_smm(vcpu))
8281 kvm_run->flags |= KVM_RUN_X86_SMM;
8282 }
8283
8284 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8285 {
8286 int max_irr, tpr;
8287
8288 if (!kvm_x86_ops.update_cr8_intercept)
8289 return;
8290
8291 if (!lapic_in_kernel(vcpu))
8292 return;
8293
8294 if (vcpu->arch.apicv_active)
8295 return;
8296
8297 if (!vcpu->arch.apic->vapic_addr)
8298 max_irr = kvm_lapic_find_highest_irr(vcpu);
8299 else
8300 max_irr = -1;
8301
8302 if (max_irr != -1)
8303 max_irr >>= 4;
8304
8305 tpr = kvm_lapic_get_cr8(vcpu);
8306
8307 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
8308 }
8309
8310 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8311 {
8312 int r;
8313 bool can_inject = true;
8314
8315 /* try to reinject previous events if any */
8316
8317 if (vcpu->arch.exception.injected) {
8318 static_call(kvm_x86_queue_exception)(vcpu);
8319 can_inject = false;
8320 }
8321 /*
8322 * Do not inject an NMI or interrupt if there is a pending
8323 * exception. Exceptions and interrupts are recognized at
8324 * instruction boundaries, i.e. the start of an instruction.
8325 * Trap-like exceptions, e.g. #DB, have higher priority than
8326 * NMIs and interrupts, i.e. traps are recognized before an
8327 * NMI/interrupt that's pending on the same instruction.
8328 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8329 * priority, but are only generated (pended) during instruction
8330 * execution, i.e. a pending fault-like exception means the
8331 * fault occurred on the *previous* instruction and must be
8332 * serviced prior to recognizing any new events in order to
8333 * fully complete the previous instruction.
8334 */
8335 else if (!vcpu->arch.exception.pending) {
8336 if (vcpu->arch.nmi_injected) {
8337 static_call(kvm_x86_set_nmi)(vcpu);
8338 can_inject = false;
8339 } else if (vcpu->arch.interrupt.injected) {
8340 static_call(kvm_x86_set_irq)(vcpu);
8341 can_inject = false;
8342 }
8343 }
8344
8345 WARN_ON_ONCE(vcpu->arch.exception.injected &&
8346 vcpu->arch.exception.pending);
8347
8348 /*
8349 * Call check_nested_events() even if we reinjected a previous event
8350 * in order for caller to determine if it should require immediate-exit
8351 * from L2 to L1 due to pending L1 events which require exit
8352 * from L2 to L1.
8353 */
8354 if (is_guest_mode(vcpu)) {
8355 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8356 if (r < 0)
8357 goto busy;
8358 }
8359
8360 /* try to inject new event if pending */
8361 if (vcpu->arch.exception.pending) {
8362 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8363 vcpu->arch.exception.has_error_code,
8364 vcpu->arch.exception.error_code);
8365
8366 vcpu->arch.exception.pending = false;
8367 vcpu->arch.exception.injected = true;
8368
8369 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8370 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8371 X86_EFLAGS_RF);
8372
8373 if (vcpu->arch.exception.nr == DB_VECTOR) {
8374 kvm_deliver_exception_payload(vcpu);
8375 if (vcpu->arch.dr7 & DR7_GD) {
8376 vcpu->arch.dr7 &= ~DR7_GD;
8377 kvm_update_dr7(vcpu);
8378 }
8379 }
8380
8381 static_call(kvm_x86_queue_exception)(vcpu);
8382 can_inject = false;
8383 }
8384
8385 /*
8386 * Finally, inject interrupt events. If an event cannot be injected
8387 * due to architectural conditions (e.g. IF=0) a window-open exit
8388 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
8389 * and can architecturally be injected, but we cannot do it right now:
8390 * an interrupt could have arrived just now and we have to inject it
8391 * as a vmexit, or there could already an event in the queue, which is
8392 * indicated by can_inject. In that case we request an immediate exit
8393 * in order to make progress and get back here for another iteration.
8394 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8395 */
8396 if (vcpu->arch.smi_pending) {
8397 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
8398 if (r < 0)
8399 goto busy;
8400 if (r) {
8401 vcpu->arch.smi_pending = false;
8402 ++vcpu->arch.smi_count;
8403 enter_smm(vcpu);
8404 can_inject = false;
8405 } else
8406 static_call(kvm_x86_enable_smi_window)(vcpu);
8407 }
8408
8409 if (vcpu->arch.nmi_pending) {
8410 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
8411 if (r < 0)
8412 goto busy;
8413 if (r) {
8414 --vcpu->arch.nmi_pending;
8415 vcpu->arch.nmi_injected = true;
8416 static_call(kvm_x86_set_nmi)(vcpu);
8417 can_inject = false;
8418 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
8419 }
8420 if (vcpu->arch.nmi_pending)
8421 static_call(kvm_x86_enable_nmi_window)(vcpu);
8422 }
8423
8424 if (kvm_cpu_has_injectable_intr(vcpu)) {
8425 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
8426 if (r < 0)
8427 goto busy;
8428 if (r) {
8429 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8430 static_call(kvm_x86_set_irq)(vcpu);
8431 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
8432 }
8433 if (kvm_cpu_has_injectable_intr(vcpu))
8434 static_call(kvm_x86_enable_irq_window)(vcpu);
8435 }
8436
8437 if (is_guest_mode(vcpu) &&
8438 kvm_x86_ops.nested_ops->hv_timer_pending &&
8439 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8440 *req_immediate_exit = true;
8441
8442 WARN_ON(vcpu->arch.exception.pending);
8443 return;
8444
8445 busy:
8446 *req_immediate_exit = true;
8447 return;
8448 }
8449
8450 static void process_nmi(struct kvm_vcpu *vcpu)
8451 {
8452 unsigned limit = 2;
8453
8454 /*
8455 * x86 is limited to one NMI running, and one NMI pending after it.
8456 * If an NMI is already in progress, limit further NMIs to just one.
8457 * Otherwise, allow two (and we'll inject the first one immediately).
8458 */
8459 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
8460 limit = 1;
8461
8462 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8463 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8464 kvm_make_request(KVM_REQ_EVENT, vcpu);
8465 }
8466
8467 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8468 {
8469 u32 flags = 0;
8470 flags |= seg->g << 23;
8471 flags |= seg->db << 22;
8472 flags |= seg->l << 21;
8473 flags |= seg->avl << 20;
8474 flags |= seg->present << 15;
8475 flags |= seg->dpl << 13;
8476 flags |= seg->s << 12;
8477 flags |= seg->type << 8;
8478 return flags;
8479 }
8480
8481 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8482 {
8483 struct kvm_segment seg;
8484 int offset;
8485
8486 kvm_get_segment(vcpu, &seg, n);
8487 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8488
8489 if (n < 3)
8490 offset = 0x7f84 + n * 12;
8491 else
8492 offset = 0x7f2c + (n - 3) * 12;
8493
8494 put_smstate(u32, buf, offset + 8, seg.base);
8495 put_smstate(u32, buf, offset + 4, seg.limit);
8496 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8497 }
8498
8499 #ifdef CONFIG_X86_64
8500 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8501 {
8502 struct kvm_segment seg;
8503 int offset;
8504 u16 flags;
8505
8506 kvm_get_segment(vcpu, &seg, n);
8507 offset = 0x7e00 + n * 16;
8508
8509 flags = enter_smm_get_segment_flags(&seg) >> 8;
8510 put_smstate(u16, buf, offset, seg.selector);
8511 put_smstate(u16, buf, offset + 2, flags);
8512 put_smstate(u32, buf, offset + 4, seg.limit);
8513 put_smstate(u64, buf, offset + 8, seg.base);
8514 }
8515 #endif
8516
8517 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8518 {
8519 struct desc_ptr dt;
8520 struct kvm_segment seg;
8521 unsigned long val;
8522 int i;
8523
8524 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8525 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8526 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8527 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8528
8529 for (i = 0; i < 8; i++)
8530 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8531
8532 kvm_get_dr(vcpu, 6, &val);
8533 put_smstate(u32, buf, 0x7fcc, (u32)val);
8534 kvm_get_dr(vcpu, 7, &val);
8535 put_smstate(u32, buf, 0x7fc8, (u32)val);
8536
8537 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8538 put_smstate(u32, buf, 0x7fc4, seg.selector);
8539 put_smstate(u32, buf, 0x7f64, seg.base);
8540 put_smstate(u32, buf, 0x7f60, seg.limit);
8541 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8542
8543 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8544 put_smstate(u32, buf, 0x7fc0, seg.selector);
8545 put_smstate(u32, buf, 0x7f80, seg.base);
8546 put_smstate(u32, buf, 0x7f7c, seg.limit);
8547 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8548
8549 static_call(kvm_x86_get_gdt)(vcpu, &dt);
8550 put_smstate(u32, buf, 0x7f74, dt.address);
8551 put_smstate(u32, buf, 0x7f70, dt.size);
8552
8553 static_call(kvm_x86_get_idt)(vcpu, &dt);
8554 put_smstate(u32, buf, 0x7f58, dt.address);
8555 put_smstate(u32, buf, 0x7f54, dt.size);
8556
8557 for (i = 0; i < 6; i++)
8558 enter_smm_save_seg_32(vcpu, buf, i);
8559
8560 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8561
8562 /* revision id */
8563 put_smstate(u32, buf, 0x7efc, 0x00020000);
8564 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8565 }
8566
8567 #ifdef CONFIG_X86_64
8568 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8569 {
8570 struct desc_ptr dt;
8571 struct kvm_segment seg;
8572 unsigned long val;
8573 int i;
8574
8575 for (i = 0; i < 16; i++)
8576 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8577
8578 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8579 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8580
8581 kvm_get_dr(vcpu, 6, &val);
8582 put_smstate(u64, buf, 0x7f68, val);
8583 kvm_get_dr(vcpu, 7, &val);
8584 put_smstate(u64, buf, 0x7f60, val);
8585
8586 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8587 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8588 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8589
8590 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8591
8592 /* revision id */
8593 put_smstate(u32, buf, 0x7efc, 0x00020064);
8594
8595 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8596
8597 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8598 put_smstate(u16, buf, 0x7e90, seg.selector);
8599 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8600 put_smstate(u32, buf, 0x7e94, seg.limit);
8601 put_smstate(u64, buf, 0x7e98, seg.base);
8602
8603 static_call(kvm_x86_get_idt)(vcpu, &dt);
8604 put_smstate(u32, buf, 0x7e84, dt.size);
8605 put_smstate(u64, buf, 0x7e88, dt.address);
8606
8607 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8608 put_smstate(u16, buf, 0x7e70, seg.selector);
8609 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8610 put_smstate(u32, buf, 0x7e74, seg.limit);
8611 put_smstate(u64, buf, 0x7e78, seg.base);
8612
8613 static_call(kvm_x86_get_gdt)(vcpu, &dt);
8614 put_smstate(u32, buf, 0x7e64, dt.size);
8615 put_smstate(u64, buf, 0x7e68, dt.address);
8616
8617 for (i = 0; i < 6; i++)
8618 enter_smm_save_seg_64(vcpu, buf, i);
8619 }
8620 #endif
8621
8622 static void enter_smm(struct kvm_vcpu *vcpu)
8623 {
8624 struct kvm_segment cs, ds;
8625 struct desc_ptr dt;
8626 char buf[512];
8627 u32 cr0;
8628
8629 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8630 memset(buf, 0, 512);
8631 #ifdef CONFIG_X86_64
8632 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8633 enter_smm_save_state_64(vcpu, buf);
8634 else
8635 #endif
8636 enter_smm_save_state_32(vcpu, buf);
8637
8638 /*
8639 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8640 * vCPU state (e.g. leave guest mode) after we've saved the state into
8641 * the SMM state-save area.
8642 */
8643 static_call(kvm_x86_pre_enter_smm)(vcpu, buf);
8644
8645 vcpu->arch.hflags |= HF_SMM_MASK;
8646 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8647
8648 if (static_call(kvm_x86_get_nmi_mask)(vcpu))
8649 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8650 else
8651 static_call(kvm_x86_set_nmi_mask)(vcpu, true);
8652
8653 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8654 kvm_rip_write(vcpu, 0x8000);
8655
8656 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8657 static_call(kvm_x86_set_cr0)(vcpu, cr0);
8658 vcpu->arch.cr0 = cr0;
8659
8660 static_call(kvm_x86_set_cr4)(vcpu, 0);
8661
8662 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8663 dt.address = dt.size = 0;
8664 static_call(kvm_x86_set_idt)(vcpu, &dt);
8665
8666 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8667
8668 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8669 cs.base = vcpu->arch.smbase;
8670
8671 ds.selector = 0;
8672 ds.base = 0;
8673
8674 cs.limit = ds.limit = 0xffffffff;
8675 cs.type = ds.type = 0x3;
8676 cs.dpl = ds.dpl = 0;
8677 cs.db = ds.db = 0;
8678 cs.s = ds.s = 1;
8679 cs.l = ds.l = 0;
8680 cs.g = ds.g = 1;
8681 cs.avl = ds.avl = 0;
8682 cs.present = ds.present = 1;
8683 cs.unusable = ds.unusable = 0;
8684 cs.padding = ds.padding = 0;
8685
8686 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8687 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8688 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8689 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8690 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8691 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8692
8693 #ifdef CONFIG_X86_64
8694 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8695 static_call(kvm_x86_set_efer)(vcpu, 0);
8696 #endif
8697
8698 kvm_update_cpuid_runtime(vcpu);
8699 kvm_mmu_reset_context(vcpu);
8700 }
8701
8702 static void process_smi(struct kvm_vcpu *vcpu)
8703 {
8704 vcpu->arch.smi_pending = true;
8705 kvm_make_request(KVM_REQ_EVENT, vcpu);
8706 }
8707
8708 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8709 unsigned long *vcpu_bitmap)
8710 {
8711 cpumask_var_t cpus;
8712
8713 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8714
8715 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8716 NULL, vcpu_bitmap, cpus);
8717
8718 free_cpumask_var(cpus);
8719 }
8720
8721 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8722 {
8723 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8724 }
8725
8726 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8727 {
8728 if (!lapic_in_kernel(vcpu))
8729 return;
8730
8731 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8732 kvm_apic_update_apicv(vcpu);
8733 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
8734 }
8735 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8736
8737 /*
8738 * NOTE: Do not hold any lock prior to calling this.
8739 *
8740 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8741 * locked, because it calls __x86_set_memory_region() which does
8742 * synchronize_srcu(&kvm->srcu).
8743 */
8744 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8745 {
8746 struct kvm_vcpu *except;
8747 unsigned long old, new, expected;
8748
8749 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8750 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit))
8751 return;
8752
8753 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8754 do {
8755 expected = new = old;
8756 if (activate)
8757 __clear_bit(bit, &new);
8758 else
8759 __set_bit(bit, &new);
8760 if (new == old)
8761 break;
8762 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8763 } while (old != expected);
8764
8765 if (!!old == !!new)
8766 return;
8767
8768 trace_kvm_apicv_update_request(activate, bit);
8769 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8770 static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate);
8771
8772 /*
8773 * Sending request to update APICV for all other vcpus,
8774 * while update the calling vcpu immediately instead of
8775 * waiting for another #VMEXIT to handle the request.
8776 */
8777 except = kvm_get_running_vcpu();
8778 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8779 except);
8780 if (except)
8781 kvm_vcpu_update_apicv(except);
8782 }
8783 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8784
8785 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8786 {
8787 if (!kvm_apic_present(vcpu))
8788 return;
8789
8790 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8791
8792 if (irqchip_split(vcpu->kvm))
8793 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8794 else {
8795 if (vcpu->arch.apicv_active)
8796 static_call(kvm_x86_sync_pir_to_irr)(vcpu);
8797 if (ioapic_in_kernel(vcpu->kvm))
8798 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8799 }
8800
8801 if (is_guest_mode(vcpu))
8802 vcpu->arch.load_eoi_exitmap_pending = true;
8803 else
8804 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8805 }
8806
8807 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8808 {
8809 u64 eoi_exit_bitmap[4];
8810
8811 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8812 return;
8813
8814 if (to_hv_vcpu(vcpu))
8815 bitmap_or((ulong *)eoi_exit_bitmap,
8816 vcpu->arch.ioapic_handled_vectors,
8817 to_hv_synic(vcpu)->vec_bitmap, 256);
8818
8819 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
8820 }
8821
8822 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8823 unsigned long start, unsigned long end)
8824 {
8825 unsigned long apic_address;
8826
8827 /*
8828 * The physical address of apic access page is stored in the VMCS.
8829 * Update it when it becomes invalid.
8830 */
8831 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8832 if (start <= apic_address && apic_address < end)
8833 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8834 }
8835
8836 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8837 {
8838 if (!lapic_in_kernel(vcpu))
8839 return;
8840
8841 if (!kvm_x86_ops.set_apic_access_page_addr)
8842 return;
8843
8844 static_call(kvm_x86_set_apic_access_page_addr)(vcpu);
8845 }
8846
8847 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8848 {
8849 smp_send_reschedule(vcpu->cpu);
8850 }
8851 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8852
8853 /*
8854 * Returns 1 to let vcpu_run() continue the guest execution loop without
8855 * exiting to the userspace. Otherwise, the value will be returned to the
8856 * userspace.
8857 */
8858 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8859 {
8860 int r;
8861 bool req_int_win =
8862 dm_request_for_irq_injection(vcpu) &&
8863 kvm_cpu_accept_dm_intr(vcpu);
8864 fastpath_t exit_fastpath;
8865
8866 bool req_immediate_exit = false;
8867
8868 /* Forbid vmenter if vcpu dirty ring is soft-full */
8869 if (unlikely(vcpu->kvm->dirty_ring_size &&
8870 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
8871 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
8872 trace_kvm_dirty_ring_exit(vcpu);
8873 r = 0;
8874 goto out;
8875 }
8876
8877 if (kvm_request_pending(vcpu)) {
8878 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8879 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8880 r = 0;
8881 goto out;
8882 }
8883 }
8884 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8885 kvm_mmu_unload(vcpu);
8886 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8887 __kvm_migrate_timers(vcpu);
8888 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8889 kvm_gen_update_masterclock(vcpu->kvm);
8890 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8891 kvm_gen_kvmclock_update(vcpu);
8892 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8893 r = kvm_guest_time_update(vcpu);
8894 if (unlikely(r))
8895 goto out;
8896 }
8897 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8898 kvm_mmu_sync_roots(vcpu);
8899 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8900 kvm_mmu_load_pgd(vcpu);
8901 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8902 kvm_vcpu_flush_tlb_all(vcpu);
8903
8904 /* Flushing all ASIDs flushes the current ASID... */
8905 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8906 }
8907 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8908 kvm_vcpu_flush_tlb_current(vcpu);
8909 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8910 kvm_vcpu_flush_tlb_guest(vcpu);
8911
8912 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8913 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8914 r = 0;
8915 goto out;
8916 }
8917 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8918 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8919 vcpu->mmio_needed = 0;
8920 r = 0;
8921 goto out;
8922 }
8923 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8924 /* Page is swapped out. Do synthetic halt */
8925 vcpu->arch.apf.halted = true;
8926 r = 1;
8927 goto out;
8928 }
8929 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8930 record_steal_time(vcpu);
8931 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8932 process_smi(vcpu);
8933 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8934 process_nmi(vcpu);
8935 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8936 kvm_pmu_handle_event(vcpu);
8937 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8938 kvm_pmu_deliver_pmi(vcpu);
8939 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8940 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8941 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8942 vcpu->arch.ioapic_handled_vectors)) {
8943 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8944 vcpu->run->eoi.vector =
8945 vcpu->arch.pending_ioapic_eoi;
8946 r = 0;
8947 goto out;
8948 }
8949 }
8950 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8951 vcpu_scan_ioapic(vcpu);
8952 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8953 vcpu_load_eoi_exitmap(vcpu);
8954 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8955 kvm_vcpu_reload_apic_access_page(vcpu);
8956 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8957 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8958 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8959 r = 0;
8960 goto out;
8961 }
8962 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8963 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8964 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8965 r = 0;
8966 goto out;
8967 }
8968 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8969 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
8970
8971 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8972 vcpu->run->hyperv = hv_vcpu->exit;
8973 r = 0;
8974 goto out;
8975 }
8976
8977 /*
8978 * KVM_REQ_HV_STIMER has to be processed after
8979 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8980 * depend on the guest clock being up-to-date
8981 */
8982 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8983 kvm_hv_process_stimers(vcpu);
8984 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8985 kvm_vcpu_update_apicv(vcpu);
8986 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8987 kvm_check_async_pf_completion(vcpu);
8988 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8989 static_call(kvm_x86_msr_filter_changed)(vcpu);
8990
8991 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
8992 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
8993 }
8994
8995 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
8996 kvm_xen_has_interrupt(vcpu)) {
8997 ++vcpu->stat.req_event;
8998 kvm_apic_accept_events(vcpu);
8999 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
9000 r = 1;
9001 goto out;
9002 }
9003
9004 inject_pending_event(vcpu, &req_immediate_exit);
9005 if (req_int_win)
9006 static_call(kvm_x86_enable_irq_window)(vcpu);
9007
9008 if (kvm_lapic_enabled(vcpu)) {
9009 update_cr8_intercept(vcpu);
9010 kvm_lapic_sync_to_vapic(vcpu);
9011 }
9012 }
9013
9014 r = kvm_mmu_reload(vcpu);
9015 if (unlikely(r)) {
9016 goto cancel_injection;
9017 }
9018
9019 preempt_disable();
9020
9021 static_call(kvm_x86_prepare_guest_switch)(vcpu);
9022
9023 /*
9024 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
9025 * IPI are then delayed after guest entry, which ensures that they
9026 * result in virtual interrupt delivery.
9027 */
9028 local_irq_disable();
9029 vcpu->mode = IN_GUEST_MODE;
9030
9031 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9032
9033 /*
9034 * 1) We should set ->mode before checking ->requests. Please see
9035 * the comment in kvm_vcpu_exiting_guest_mode().
9036 *
9037 * 2) For APICv, we should set ->mode before checking PID.ON. This
9038 * pairs with the memory barrier implicit in pi_test_and_set_on
9039 * (see vmx_deliver_posted_interrupt).
9040 *
9041 * 3) This also orders the write to mode from any reads to the page
9042 * tables done while the VCPU is running. Please see the comment
9043 * in kvm_flush_remote_tlbs.
9044 */
9045 smp_mb__after_srcu_read_unlock();
9046
9047 /*
9048 * This handles the case where a posted interrupt was
9049 * notified with kvm_vcpu_kick.
9050 */
9051 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
9052 static_call(kvm_x86_sync_pir_to_irr)(vcpu);
9053
9054 if (kvm_vcpu_exit_request(vcpu)) {
9055 vcpu->mode = OUTSIDE_GUEST_MODE;
9056 smp_wmb();
9057 local_irq_enable();
9058 preempt_enable();
9059 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9060 r = 1;
9061 goto cancel_injection;
9062 }
9063
9064 if (req_immediate_exit) {
9065 kvm_make_request(KVM_REQ_EVENT, vcpu);
9066 static_call(kvm_x86_request_immediate_exit)(vcpu);
9067 }
9068
9069 fpregs_assert_state_consistent();
9070 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9071 switch_fpu_return();
9072
9073 if (unlikely(vcpu->arch.switch_db_regs)) {
9074 set_debugreg(0, 7);
9075 set_debugreg(vcpu->arch.eff_db[0], 0);
9076 set_debugreg(vcpu->arch.eff_db[1], 1);
9077 set_debugreg(vcpu->arch.eff_db[2], 2);
9078 set_debugreg(vcpu->arch.eff_db[3], 3);
9079 set_debugreg(vcpu->arch.dr6, 6);
9080 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9081 }
9082
9083 for (;;) {
9084 exit_fastpath = static_call(kvm_x86_run)(vcpu);
9085 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
9086 break;
9087
9088 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
9089 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
9090 break;
9091 }
9092
9093 if (vcpu->arch.apicv_active)
9094 static_call(kvm_x86_sync_pir_to_irr)(vcpu);
9095 }
9096
9097 /*
9098 * Do this here before restoring debug registers on the host. And
9099 * since we do this before handling the vmexit, a DR access vmexit
9100 * can (a) read the correct value of the debug registers, (b) set
9101 * KVM_DEBUGREG_WONT_EXIT again.
9102 */
9103 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
9104 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
9105 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
9106 kvm_update_dr0123(vcpu);
9107 kvm_update_dr7(vcpu);
9108 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
9109 }
9110
9111 /*
9112 * If the guest has used debug registers, at least dr7
9113 * will be disabled while returning to the host.
9114 * If we don't have active breakpoints in the host, we don't
9115 * care about the messed up debug address registers. But if
9116 * we have some of them active, restore the old state.
9117 */
9118 if (hw_breakpoint_active())
9119 hw_breakpoint_restore();
9120
9121 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
9122 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
9123
9124 vcpu->mode = OUTSIDE_GUEST_MODE;
9125 smp_wmb();
9126
9127 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
9128
9129 /*
9130 * Consume any pending interrupts, including the possible source of
9131 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
9132 * An instruction is required after local_irq_enable() to fully unblock
9133 * interrupts on processors that implement an interrupt shadow, the
9134 * stat.exits increment will do nicely.
9135 */
9136 kvm_before_interrupt(vcpu);
9137 local_irq_enable();
9138 ++vcpu->stat.exits;
9139 local_irq_disable();
9140 kvm_after_interrupt(vcpu);
9141
9142 if (lapic_in_kernel(vcpu)) {
9143 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
9144 if (delta != S64_MIN) {
9145 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
9146 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
9147 }
9148 }
9149
9150 local_irq_enable();
9151 preempt_enable();
9152
9153 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9154
9155 /*
9156 * Profile KVM exit RIPs:
9157 */
9158 if (unlikely(prof_on == KVM_PROFILING)) {
9159 unsigned long rip = kvm_rip_read(vcpu);
9160 profile_hit(KVM_PROFILING, (void *)rip);
9161 }
9162
9163 if (unlikely(vcpu->arch.tsc_always_catchup))
9164 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9165
9166 if (vcpu->arch.apic_attention)
9167 kvm_lapic_sync_from_vapic(vcpu);
9168
9169 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
9170 return r;
9171
9172 cancel_injection:
9173 if (req_immediate_exit)
9174 kvm_make_request(KVM_REQ_EVENT, vcpu);
9175 static_call(kvm_x86_cancel_injection)(vcpu);
9176 if (unlikely(vcpu->arch.apic_attention))
9177 kvm_lapic_sync_from_vapic(vcpu);
9178 out:
9179 return r;
9180 }
9181
9182 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
9183 {
9184 if (!kvm_arch_vcpu_runnable(vcpu) &&
9185 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) {
9186 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9187 kvm_vcpu_block(vcpu);
9188 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9189
9190 if (kvm_x86_ops.post_block)
9191 static_call(kvm_x86_post_block)(vcpu);
9192
9193 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
9194 return 1;
9195 }
9196
9197 kvm_apic_accept_events(vcpu);
9198 switch(vcpu->arch.mp_state) {
9199 case KVM_MP_STATE_HALTED:
9200 case KVM_MP_STATE_AP_RESET_HOLD:
9201 vcpu->arch.pv.pv_unhalted = false;
9202 vcpu->arch.mp_state =
9203 KVM_MP_STATE_RUNNABLE;
9204 fallthrough;
9205 case KVM_MP_STATE_RUNNABLE:
9206 vcpu->arch.apf.halted = false;
9207 break;
9208 case KVM_MP_STATE_INIT_RECEIVED:
9209 break;
9210 default:
9211 return -EINTR;
9212 }
9213 return 1;
9214 }
9215
9216 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
9217 {
9218 if (is_guest_mode(vcpu))
9219 kvm_x86_ops.nested_ops->check_events(vcpu);
9220
9221 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
9222 !vcpu->arch.apf.halted);
9223 }
9224
9225 static int vcpu_run(struct kvm_vcpu *vcpu)
9226 {
9227 int r;
9228 struct kvm *kvm = vcpu->kvm;
9229
9230 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9231 vcpu->arch.l1tf_flush_l1d = true;
9232
9233 for (;;) {
9234 if (kvm_vcpu_running(vcpu)) {
9235 r = vcpu_enter_guest(vcpu);
9236 } else {
9237 r = vcpu_block(kvm, vcpu);
9238 }
9239
9240 if (r <= 0)
9241 break;
9242
9243 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
9244 if (kvm_cpu_has_pending_timer(vcpu))
9245 kvm_inject_pending_timer_irqs(vcpu);
9246
9247 if (dm_request_for_irq_injection(vcpu) &&
9248 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9249 r = 0;
9250 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9251 ++vcpu->stat.request_irq_exits;
9252 break;
9253 }
9254
9255 if (__xfer_to_guest_mode_work_pending()) {
9256 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9257 r = xfer_to_guest_mode_handle_work(vcpu);
9258 if (r)
9259 return r;
9260 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9261 }
9262 }
9263
9264 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9265
9266 return r;
9267 }
9268
9269 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9270 {
9271 int r;
9272
9273 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9274 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9275 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9276 return r;
9277 }
9278
9279 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9280 {
9281 BUG_ON(!vcpu->arch.pio.count);
9282
9283 return complete_emulated_io(vcpu);
9284 }
9285
9286 /*
9287 * Implements the following, as a state machine:
9288 *
9289 * read:
9290 * for each fragment
9291 * for each mmio piece in the fragment
9292 * write gpa, len
9293 * exit
9294 * copy data
9295 * execute insn
9296 *
9297 * write:
9298 * for each fragment
9299 * for each mmio piece in the fragment
9300 * write gpa, len
9301 * copy data
9302 * exit
9303 */
9304 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9305 {
9306 struct kvm_run *run = vcpu->run;
9307 struct kvm_mmio_fragment *frag;
9308 unsigned len;
9309
9310 BUG_ON(!vcpu->mmio_needed);
9311
9312 /* Complete previous fragment */
9313 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9314 len = min(8u, frag->len);
9315 if (!vcpu->mmio_is_write)
9316 memcpy(frag->data, run->mmio.data, len);
9317
9318 if (frag->len <= 8) {
9319 /* Switch to the next fragment. */
9320 frag++;
9321 vcpu->mmio_cur_fragment++;
9322 } else {
9323 /* Go forward to the next mmio piece. */
9324 frag->data += len;
9325 frag->gpa += len;
9326 frag->len -= len;
9327 }
9328
9329 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9330 vcpu->mmio_needed = 0;
9331
9332 /* FIXME: return into emulator if single-stepping. */
9333 if (vcpu->mmio_is_write)
9334 return 1;
9335 vcpu->mmio_read_completed = 1;
9336 return complete_emulated_io(vcpu);
9337 }
9338
9339 run->exit_reason = KVM_EXIT_MMIO;
9340 run->mmio.phys_addr = frag->gpa;
9341 if (vcpu->mmio_is_write)
9342 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9343 run->mmio.len = min(8u, frag->len);
9344 run->mmio.is_write = vcpu->mmio_is_write;
9345 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9346 return 0;
9347 }
9348
9349 static void kvm_save_current_fpu(struct fpu *fpu)
9350 {
9351 /*
9352 * If the target FPU state is not resident in the CPU registers, just
9353 * memcpy() from current, else save CPU state directly to the target.
9354 */
9355 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9356 memcpy(&fpu->state, &current->thread.fpu.state,
9357 fpu_kernel_xstate_size);
9358 else
9359 copy_fpregs_to_fpstate(fpu);
9360 }
9361
9362 /* Swap (qemu) user FPU context for the guest FPU context. */
9363 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9364 {
9365 fpregs_lock();
9366
9367 kvm_save_current_fpu(vcpu->arch.user_fpu);
9368
9369 /*
9370 * Guests with protected state can't have it set by the hypervisor,
9371 * so skip trying to set it.
9372 */
9373 if (vcpu->arch.guest_fpu)
9374 /* PKRU is separately restored in kvm_x86_ops.run. */
9375 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9376 ~XFEATURE_MASK_PKRU);
9377
9378 fpregs_mark_activate();
9379 fpregs_unlock();
9380
9381 trace_kvm_fpu(1);
9382 }
9383
9384 /* When vcpu_run ends, restore user space FPU context. */
9385 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9386 {
9387 fpregs_lock();
9388
9389 /*
9390 * Guests with protected state can't have it read by the hypervisor,
9391 * so skip trying to save it.
9392 */
9393 if (vcpu->arch.guest_fpu)
9394 kvm_save_current_fpu(vcpu->arch.guest_fpu);
9395
9396 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9397
9398 fpregs_mark_activate();
9399 fpregs_unlock();
9400
9401 ++vcpu->stat.fpu_reload;
9402 trace_kvm_fpu(0);
9403 }
9404
9405 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9406 {
9407 struct kvm_run *kvm_run = vcpu->run;
9408 int r;
9409
9410 vcpu_load(vcpu);
9411 kvm_sigset_activate(vcpu);
9412 kvm_run->flags = 0;
9413 kvm_load_guest_fpu(vcpu);
9414
9415 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9416 if (kvm_run->immediate_exit) {
9417 r = -EINTR;
9418 goto out;
9419 }
9420 kvm_vcpu_block(vcpu);
9421 kvm_apic_accept_events(vcpu);
9422 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9423 r = -EAGAIN;
9424 if (signal_pending(current)) {
9425 r = -EINTR;
9426 kvm_run->exit_reason = KVM_EXIT_INTR;
9427 ++vcpu->stat.signal_exits;
9428 }
9429 goto out;
9430 }
9431
9432 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9433 r = -EINVAL;
9434 goto out;
9435 }
9436
9437 if (kvm_run->kvm_dirty_regs) {
9438 r = sync_regs(vcpu);
9439 if (r != 0)
9440 goto out;
9441 }
9442
9443 /* re-sync apic's tpr */
9444 if (!lapic_in_kernel(vcpu)) {
9445 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9446 r = -EINVAL;
9447 goto out;
9448 }
9449 }
9450
9451 if (unlikely(vcpu->arch.complete_userspace_io)) {
9452 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9453 vcpu->arch.complete_userspace_io = NULL;
9454 r = cui(vcpu);
9455 if (r <= 0)
9456 goto out;
9457 } else
9458 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9459
9460 if (kvm_run->immediate_exit)
9461 r = -EINTR;
9462 else
9463 r = vcpu_run(vcpu);
9464
9465 out:
9466 kvm_put_guest_fpu(vcpu);
9467 if (kvm_run->kvm_valid_regs)
9468 store_regs(vcpu);
9469 post_kvm_run_save(vcpu);
9470 kvm_sigset_deactivate(vcpu);
9471
9472 vcpu_put(vcpu);
9473 return r;
9474 }
9475
9476 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9477 {
9478 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9479 /*
9480 * We are here if userspace calls get_regs() in the middle of
9481 * instruction emulation. Registers state needs to be copied
9482 * back from emulation context to vcpu. Userspace shouldn't do
9483 * that usually, but some bad designed PV devices (vmware
9484 * backdoor interface) need this to work
9485 */
9486 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9487 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9488 }
9489 regs->rax = kvm_rax_read(vcpu);
9490 regs->rbx = kvm_rbx_read(vcpu);
9491 regs->rcx = kvm_rcx_read(vcpu);
9492 regs->rdx = kvm_rdx_read(vcpu);
9493 regs->rsi = kvm_rsi_read(vcpu);
9494 regs->rdi = kvm_rdi_read(vcpu);
9495 regs->rsp = kvm_rsp_read(vcpu);
9496 regs->rbp = kvm_rbp_read(vcpu);
9497 #ifdef CONFIG_X86_64
9498 regs->r8 = kvm_r8_read(vcpu);
9499 regs->r9 = kvm_r9_read(vcpu);
9500 regs->r10 = kvm_r10_read(vcpu);
9501 regs->r11 = kvm_r11_read(vcpu);
9502 regs->r12 = kvm_r12_read(vcpu);
9503 regs->r13 = kvm_r13_read(vcpu);
9504 regs->r14 = kvm_r14_read(vcpu);
9505 regs->r15 = kvm_r15_read(vcpu);
9506 #endif
9507
9508 regs->rip = kvm_rip_read(vcpu);
9509 regs->rflags = kvm_get_rflags(vcpu);
9510 }
9511
9512 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9513 {
9514 vcpu_load(vcpu);
9515 __get_regs(vcpu, regs);
9516 vcpu_put(vcpu);
9517 return 0;
9518 }
9519
9520 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9521 {
9522 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9523 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9524
9525 kvm_rax_write(vcpu, regs->rax);
9526 kvm_rbx_write(vcpu, regs->rbx);
9527 kvm_rcx_write(vcpu, regs->rcx);
9528 kvm_rdx_write(vcpu, regs->rdx);
9529 kvm_rsi_write(vcpu, regs->rsi);
9530 kvm_rdi_write(vcpu, regs->rdi);
9531 kvm_rsp_write(vcpu, regs->rsp);
9532 kvm_rbp_write(vcpu, regs->rbp);
9533 #ifdef CONFIG_X86_64
9534 kvm_r8_write(vcpu, regs->r8);
9535 kvm_r9_write(vcpu, regs->r9);
9536 kvm_r10_write(vcpu, regs->r10);
9537 kvm_r11_write(vcpu, regs->r11);
9538 kvm_r12_write(vcpu, regs->r12);
9539 kvm_r13_write(vcpu, regs->r13);
9540 kvm_r14_write(vcpu, regs->r14);
9541 kvm_r15_write(vcpu, regs->r15);
9542 #endif
9543
9544 kvm_rip_write(vcpu, regs->rip);
9545 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9546
9547 vcpu->arch.exception.pending = false;
9548
9549 kvm_make_request(KVM_REQ_EVENT, vcpu);
9550 }
9551
9552 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9553 {
9554 vcpu_load(vcpu);
9555 __set_regs(vcpu, regs);
9556 vcpu_put(vcpu);
9557 return 0;
9558 }
9559
9560 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9561 {
9562 struct kvm_segment cs;
9563
9564 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9565 *db = cs.db;
9566 *l = cs.l;
9567 }
9568 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9569
9570 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9571 {
9572 struct desc_ptr dt;
9573
9574 if (vcpu->arch.guest_state_protected)
9575 goto skip_protected_regs;
9576
9577 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9578 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9579 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9580 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9581 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9582 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9583
9584 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9585 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9586
9587 static_call(kvm_x86_get_idt)(vcpu, &dt);
9588 sregs->idt.limit = dt.size;
9589 sregs->idt.base = dt.address;
9590 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9591 sregs->gdt.limit = dt.size;
9592 sregs->gdt.base = dt.address;
9593
9594 sregs->cr2 = vcpu->arch.cr2;
9595 sregs->cr3 = kvm_read_cr3(vcpu);
9596
9597 skip_protected_regs:
9598 sregs->cr0 = kvm_read_cr0(vcpu);
9599 sregs->cr4 = kvm_read_cr4(vcpu);
9600 sregs->cr8 = kvm_get_cr8(vcpu);
9601 sregs->efer = vcpu->arch.efer;
9602 sregs->apic_base = kvm_get_apic_base(vcpu);
9603
9604 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9605
9606 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9607 set_bit(vcpu->arch.interrupt.nr,
9608 (unsigned long *)sregs->interrupt_bitmap);
9609 }
9610
9611 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9612 struct kvm_sregs *sregs)
9613 {
9614 vcpu_load(vcpu);
9615 __get_sregs(vcpu, sregs);
9616 vcpu_put(vcpu);
9617 return 0;
9618 }
9619
9620 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9621 struct kvm_mp_state *mp_state)
9622 {
9623 vcpu_load(vcpu);
9624 if (kvm_mpx_supported())
9625 kvm_load_guest_fpu(vcpu);
9626
9627 kvm_apic_accept_events(vcpu);
9628 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
9629 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
9630 vcpu->arch.pv.pv_unhalted)
9631 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9632 else
9633 mp_state->mp_state = vcpu->arch.mp_state;
9634
9635 if (kvm_mpx_supported())
9636 kvm_put_guest_fpu(vcpu);
9637 vcpu_put(vcpu);
9638 return 0;
9639 }
9640
9641 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9642 struct kvm_mp_state *mp_state)
9643 {
9644 int ret = -EINVAL;
9645
9646 vcpu_load(vcpu);
9647
9648 if (!lapic_in_kernel(vcpu) &&
9649 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9650 goto out;
9651
9652 /*
9653 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9654 * INIT state; latched init should be reported using
9655 * KVM_SET_VCPU_EVENTS, so reject it here.
9656 */
9657 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9658 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9659 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9660 goto out;
9661
9662 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9663 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9664 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9665 } else
9666 vcpu->arch.mp_state = mp_state->mp_state;
9667 kvm_make_request(KVM_REQ_EVENT, vcpu);
9668
9669 ret = 0;
9670 out:
9671 vcpu_put(vcpu);
9672 return ret;
9673 }
9674
9675 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9676 int reason, bool has_error_code, u32 error_code)
9677 {
9678 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9679 int ret;
9680
9681 init_emulate_ctxt(vcpu);
9682
9683 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9684 has_error_code, error_code);
9685 if (ret) {
9686 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9687 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9688 vcpu->run->internal.ndata = 0;
9689 return 0;
9690 }
9691
9692 kvm_rip_write(vcpu, ctxt->eip);
9693 kvm_set_rflags(vcpu, ctxt->eflags);
9694 return 1;
9695 }
9696 EXPORT_SYMBOL_GPL(kvm_task_switch);
9697
9698 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9699 {
9700 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9701 /*
9702 * When EFER.LME and CR0.PG are set, the processor is in
9703 * 64-bit mode (though maybe in a 32-bit code segment).
9704 * CR4.PAE and EFER.LMA must be set.
9705 */
9706 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
9707 return false;
9708 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
9709 return false;
9710 } else {
9711 /*
9712 * Not in 64-bit mode: EFER.LMA is clear and the code
9713 * segment cannot be 64-bit.
9714 */
9715 if (sregs->efer & EFER_LMA || sregs->cs.l)
9716 return false;
9717 }
9718
9719 return kvm_is_valid_cr4(vcpu, sregs->cr4);
9720 }
9721
9722 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9723 {
9724 struct msr_data apic_base_msr;
9725 int mmu_reset_needed = 0;
9726 int pending_vec, max_bits, idx;
9727 struct desc_ptr dt;
9728 int ret = -EINVAL;
9729
9730 if (!kvm_is_valid_sregs(vcpu, sregs))
9731 goto out;
9732
9733 apic_base_msr.data = sregs->apic_base;
9734 apic_base_msr.host_initiated = true;
9735 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9736 goto out;
9737
9738 if (vcpu->arch.guest_state_protected)
9739 goto skip_protected_regs;
9740
9741 dt.size = sregs->idt.limit;
9742 dt.address = sregs->idt.base;
9743 static_call(kvm_x86_set_idt)(vcpu, &dt);
9744 dt.size = sregs->gdt.limit;
9745 dt.address = sregs->gdt.base;
9746 static_call(kvm_x86_set_gdt)(vcpu, &dt);
9747
9748 vcpu->arch.cr2 = sregs->cr2;
9749 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9750 vcpu->arch.cr3 = sregs->cr3;
9751 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9752
9753 kvm_set_cr8(vcpu, sregs->cr8);
9754
9755 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9756 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
9757
9758 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9759 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
9760 vcpu->arch.cr0 = sregs->cr0;
9761
9762 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9763 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
9764
9765 idx = srcu_read_lock(&vcpu->kvm->srcu);
9766 if (is_pae_paging(vcpu)) {
9767 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9768 mmu_reset_needed = 1;
9769 }
9770 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9771
9772 if (mmu_reset_needed)
9773 kvm_mmu_reset_context(vcpu);
9774
9775 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9776 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9777 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9778 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9779 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9780 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9781
9782 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9783 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9784
9785 update_cr8_intercept(vcpu);
9786
9787 /* Older userspace won't unhalt the vcpu on reset. */
9788 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9789 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9790 !is_protmode(vcpu))
9791 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9792
9793 skip_protected_regs:
9794 max_bits = KVM_NR_INTERRUPTS;
9795 pending_vec = find_first_bit(
9796 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9797 if (pending_vec < max_bits) {
9798 kvm_queue_interrupt(vcpu, pending_vec, false);
9799 pr_debug("Set back pending irq %d\n", pending_vec);
9800 }
9801
9802 kvm_make_request(KVM_REQ_EVENT, vcpu);
9803
9804 ret = 0;
9805 out:
9806 return ret;
9807 }
9808
9809 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9810 struct kvm_sregs *sregs)
9811 {
9812 int ret;
9813
9814 vcpu_load(vcpu);
9815 ret = __set_sregs(vcpu, sregs);
9816 vcpu_put(vcpu);
9817 return ret;
9818 }
9819
9820 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9821 struct kvm_guest_debug *dbg)
9822 {
9823 unsigned long rflags;
9824 int i, r;
9825
9826 if (vcpu->arch.guest_state_protected)
9827 return -EINVAL;
9828
9829 vcpu_load(vcpu);
9830
9831 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9832 r = -EBUSY;
9833 if (vcpu->arch.exception.pending)
9834 goto out;
9835 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9836 kvm_queue_exception(vcpu, DB_VECTOR);
9837 else
9838 kvm_queue_exception(vcpu, BP_VECTOR);
9839 }
9840
9841 /*
9842 * Read rflags as long as potentially injected trace flags are still
9843 * filtered out.
9844 */
9845 rflags = kvm_get_rflags(vcpu);
9846
9847 vcpu->guest_debug = dbg->control;
9848 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9849 vcpu->guest_debug = 0;
9850
9851 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9852 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9853 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9854 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9855 } else {
9856 for (i = 0; i < KVM_NR_DB_REGS; i++)
9857 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9858 }
9859 kvm_update_dr7(vcpu);
9860
9861 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9862 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9863 get_segment_base(vcpu, VCPU_SREG_CS);
9864
9865 /*
9866 * Trigger an rflags update that will inject or remove the trace
9867 * flags.
9868 */
9869 kvm_set_rflags(vcpu, rflags);
9870
9871 static_call(kvm_x86_update_exception_bitmap)(vcpu);
9872
9873 r = 0;
9874
9875 out:
9876 vcpu_put(vcpu);
9877 return r;
9878 }
9879
9880 /*
9881 * Translate a guest virtual address to a guest physical address.
9882 */
9883 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9884 struct kvm_translation *tr)
9885 {
9886 unsigned long vaddr = tr->linear_address;
9887 gpa_t gpa;
9888 int idx;
9889
9890 vcpu_load(vcpu);
9891
9892 idx = srcu_read_lock(&vcpu->kvm->srcu);
9893 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9894 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9895 tr->physical_address = gpa;
9896 tr->valid = gpa != UNMAPPED_GVA;
9897 tr->writeable = 1;
9898 tr->usermode = 0;
9899
9900 vcpu_put(vcpu);
9901 return 0;
9902 }
9903
9904 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9905 {
9906 struct fxregs_state *fxsave;
9907
9908 if (!vcpu->arch.guest_fpu)
9909 return 0;
9910
9911 vcpu_load(vcpu);
9912
9913 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9914 memcpy(fpu->fpr, fxsave->st_space, 128);
9915 fpu->fcw = fxsave->cwd;
9916 fpu->fsw = fxsave->swd;
9917 fpu->ftwx = fxsave->twd;
9918 fpu->last_opcode = fxsave->fop;
9919 fpu->last_ip = fxsave->rip;
9920 fpu->last_dp = fxsave->rdp;
9921 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9922
9923 vcpu_put(vcpu);
9924 return 0;
9925 }
9926
9927 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9928 {
9929 struct fxregs_state *fxsave;
9930
9931 if (!vcpu->arch.guest_fpu)
9932 return 0;
9933
9934 vcpu_load(vcpu);
9935
9936 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9937
9938 memcpy(fxsave->st_space, fpu->fpr, 128);
9939 fxsave->cwd = fpu->fcw;
9940 fxsave->swd = fpu->fsw;
9941 fxsave->twd = fpu->ftwx;
9942 fxsave->fop = fpu->last_opcode;
9943 fxsave->rip = fpu->last_ip;
9944 fxsave->rdp = fpu->last_dp;
9945 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9946
9947 vcpu_put(vcpu);
9948 return 0;
9949 }
9950
9951 static void store_regs(struct kvm_vcpu *vcpu)
9952 {
9953 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9954
9955 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9956 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9957
9958 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9959 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9960
9961 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9962 kvm_vcpu_ioctl_x86_get_vcpu_events(
9963 vcpu, &vcpu->run->s.regs.events);
9964 }
9965
9966 static int sync_regs(struct kvm_vcpu *vcpu)
9967 {
9968 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9969 return -EINVAL;
9970
9971 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9972 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9973 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9974 }
9975 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9976 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9977 return -EINVAL;
9978 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9979 }
9980 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9981 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9982 vcpu, &vcpu->run->s.regs.events))
9983 return -EINVAL;
9984 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9985 }
9986
9987 return 0;
9988 }
9989
9990 static void fx_init(struct kvm_vcpu *vcpu)
9991 {
9992 if (!vcpu->arch.guest_fpu)
9993 return;
9994
9995 fpstate_init(&vcpu->arch.guest_fpu->state);
9996 if (boot_cpu_has(X86_FEATURE_XSAVES))
9997 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9998 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9999
10000 /*
10001 * Ensure guest xcr0 is valid for loading
10002 */
10003 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
10004
10005 vcpu->arch.cr0 |= X86_CR0_ET;
10006 }
10007
10008 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu)
10009 {
10010 if (vcpu->arch.guest_fpu) {
10011 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
10012 vcpu->arch.guest_fpu = NULL;
10013 }
10014 }
10015 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu);
10016
10017 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
10018 {
10019 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
10020 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
10021 "guest TSC will not be reliable\n");
10022
10023 return 0;
10024 }
10025
10026 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
10027 {
10028 struct page *page;
10029 int r;
10030
10031 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
10032 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10033 else
10034 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
10035
10036 kvm_set_tsc_khz(vcpu, max_tsc_khz);
10037
10038 r = kvm_mmu_create(vcpu);
10039 if (r < 0)
10040 return r;
10041
10042 if (irqchip_in_kernel(vcpu->kvm)) {
10043 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
10044 if (r < 0)
10045 goto fail_mmu_destroy;
10046 if (kvm_apicv_activated(vcpu->kvm))
10047 vcpu->arch.apicv_active = true;
10048 } else
10049 static_branch_inc(&kvm_has_noapic_vcpu);
10050
10051 r = -ENOMEM;
10052
10053 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
10054 if (!page)
10055 goto fail_free_lapic;
10056 vcpu->arch.pio_data = page_address(page);
10057
10058 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
10059 GFP_KERNEL_ACCOUNT);
10060 if (!vcpu->arch.mce_banks)
10061 goto fail_free_pio_data;
10062 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
10063
10064 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
10065 GFP_KERNEL_ACCOUNT))
10066 goto fail_free_mce_banks;
10067
10068 if (!alloc_emulate_ctxt(vcpu))
10069 goto free_wbinvd_dirty_mask;
10070
10071 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
10072 GFP_KERNEL_ACCOUNT);
10073 if (!vcpu->arch.user_fpu) {
10074 pr_err("kvm: failed to allocate userspace's fpu\n");
10075 goto free_emulate_ctxt;
10076 }
10077
10078 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
10079 GFP_KERNEL_ACCOUNT);
10080 if (!vcpu->arch.guest_fpu) {
10081 pr_err("kvm: failed to allocate vcpu's fpu\n");
10082 goto free_user_fpu;
10083 }
10084 fx_init(vcpu);
10085
10086 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
10087 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
10088
10089 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
10090
10091 kvm_async_pf_hash_reset(vcpu);
10092 kvm_pmu_init(vcpu);
10093
10094 vcpu->arch.pending_external_vector = -1;
10095 vcpu->arch.preempted_in_kernel = false;
10096
10097 r = static_call(kvm_x86_vcpu_create)(vcpu);
10098 if (r)
10099 goto free_guest_fpu;
10100
10101 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
10102 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
10103 kvm_vcpu_mtrr_init(vcpu);
10104 vcpu_load(vcpu);
10105 kvm_vcpu_reset(vcpu, false);
10106 kvm_init_mmu(vcpu, false);
10107 vcpu_put(vcpu);
10108 return 0;
10109
10110 free_guest_fpu:
10111 kvm_free_guest_fpu(vcpu);
10112 free_user_fpu:
10113 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10114 free_emulate_ctxt:
10115 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10116 free_wbinvd_dirty_mask:
10117 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10118 fail_free_mce_banks:
10119 kfree(vcpu->arch.mce_banks);
10120 fail_free_pio_data:
10121 free_page((unsigned long)vcpu->arch.pio_data);
10122 fail_free_lapic:
10123 kvm_free_lapic(vcpu);
10124 fail_mmu_destroy:
10125 kvm_mmu_destroy(vcpu);
10126 return r;
10127 }
10128
10129 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
10130 {
10131 struct kvm *kvm = vcpu->kvm;
10132
10133 if (mutex_lock_killable(&vcpu->mutex))
10134 return;
10135 vcpu_load(vcpu);
10136 kvm_synchronize_tsc(vcpu, 0);
10137 vcpu_put(vcpu);
10138
10139 /* poll control enabled by default */
10140 vcpu->arch.msr_kvm_poll_control = 1;
10141
10142 mutex_unlock(&vcpu->mutex);
10143
10144 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
10145 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
10146 KVMCLOCK_SYNC_PERIOD);
10147 }
10148
10149 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
10150 {
10151 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
10152 int idx;
10153
10154 kvm_release_pfn(cache->pfn, cache->dirty, cache);
10155
10156 kvmclock_reset(vcpu);
10157
10158 static_call(kvm_x86_vcpu_free)(vcpu);
10159
10160 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
10161 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
10162 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
10163 kvm_free_guest_fpu(vcpu);
10164
10165 kvm_hv_vcpu_uninit(vcpu);
10166 kvm_pmu_destroy(vcpu);
10167 kfree(vcpu->arch.mce_banks);
10168 kvm_free_lapic(vcpu);
10169 idx = srcu_read_lock(&vcpu->kvm->srcu);
10170 kvm_mmu_destroy(vcpu);
10171 srcu_read_unlock(&vcpu->kvm->srcu, idx);
10172 free_page((unsigned long)vcpu->arch.pio_data);
10173 kvfree(vcpu->arch.cpuid_entries);
10174 if (!lapic_in_kernel(vcpu))
10175 static_branch_dec(&kvm_has_noapic_vcpu);
10176 }
10177
10178 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
10179 {
10180 kvm_lapic_reset(vcpu, init_event);
10181
10182 vcpu->arch.hflags = 0;
10183
10184 vcpu->arch.smi_pending = 0;
10185 vcpu->arch.smi_count = 0;
10186 atomic_set(&vcpu->arch.nmi_queued, 0);
10187 vcpu->arch.nmi_pending = 0;
10188 vcpu->arch.nmi_injected = false;
10189 kvm_clear_interrupt_queue(vcpu);
10190 kvm_clear_exception_queue(vcpu);
10191
10192 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
10193 kvm_update_dr0123(vcpu);
10194 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
10195 vcpu->arch.dr7 = DR7_FIXED_1;
10196 kvm_update_dr7(vcpu);
10197
10198 vcpu->arch.cr2 = 0;
10199
10200 kvm_make_request(KVM_REQ_EVENT, vcpu);
10201 vcpu->arch.apf.msr_en_val = 0;
10202 vcpu->arch.apf.msr_int_val = 0;
10203 vcpu->arch.st.msr_val = 0;
10204
10205 kvmclock_reset(vcpu);
10206
10207 kvm_clear_async_pf_completion_queue(vcpu);
10208 kvm_async_pf_hash_reset(vcpu);
10209 vcpu->arch.apf.halted = false;
10210
10211 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) {
10212 void *mpx_state_buffer;
10213
10214 /*
10215 * To avoid have the INIT path from kvm_apic_has_events() that be
10216 * called with loaded FPU and does not let userspace fix the state.
10217 */
10218 if (init_event)
10219 kvm_put_guest_fpu(vcpu);
10220 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10221 XFEATURE_BNDREGS);
10222 if (mpx_state_buffer)
10223 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
10224 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10225 XFEATURE_BNDCSR);
10226 if (mpx_state_buffer)
10227 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
10228 if (init_event)
10229 kvm_load_guest_fpu(vcpu);
10230 }
10231
10232 if (!init_event) {
10233 kvm_pmu_reset(vcpu);
10234 vcpu->arch.smbase = 0x30000;
10235
10236 vcpu->arch.msr_misc_features_enables = 0;
10237
10238 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
10239 }
10240
10241 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
10242 vcpu->arch.regs_avail = ~0;
10243 vcpu->arch.regs_dirty = ~0;
10244
10245 vcpu->arch.ia32_xss = 0;
10246
10247 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
10248 }
10249
10250 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
10251 {
10252 struct kvm_segment cs;
10253
10254 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
10255 cs.selector = vector << 8;
10256 cs.base = vector << 12;
10257 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10258 kvm_rip_write(vcpu, 0);
10259 }
10260 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
10261
10262 int kvm_arch_hardware_enable(void)
10263 {
10264 struct kvm *kvm;
10265 struct kvm_vcpu *vcpu;
10266 int i;
10267 int ret;
10268 u64 local_tsc;
10269 u64 max_tsc = 0;
10270 bool stable, backwards_tsc = false;
10271
10272 kvm_user_return_msr_cpu_online();
10273 ret = static_call(kvm_x86_hardware_enable)();
10274 if (ret != 0)
10275 return ret;
10276
10277 local_tsc = rdtsc();
10278 stable = !kvm_check_tsc_unstable();
10279 list_for_each_entry(kvm, &vm_list, vm_list) {
10280 kvm_for_each_vcpu(i, vcpu, kvm) {
10281 if (!stable && vcpu->cpu == smp_processor_id())
10282 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10283 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10284 backwards_tsc = true;
10285 if (vcpu->arch.last_host_tsc > max_tsc)
10286 max_tsc = vcpu->arch.last_host_tsc;
10287 }
10288 }
10289 }
10290
10291 /*
10292 * Sometimes, even reliable TSCs go backwards. This happens on
10293 * platforms that reset TSC during suspend or hibernate actions, but
10294 * maintain synchronization. We must compensate. Fortunately, we can
10295 * detect that condition here, which happens early in CPU bringup,
10296 * before any KVM threads can be running. Unfortunately, we can't
10297 * bring the TSCs fully up to date with real time, as we aren't yet far
10298 * enough into CPU bringup that we know how much real time has actually
10299 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10300 * variables that haven't been updated yet.
10301 *
10302 * So we simply find the maximum observed TSC above, then record the
10303 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
10304 * the adjustment will be applied. Note that we accumulate
10305 * adjustments, in case multiple suspend cycles happen before some VCPU
10306 * gets a chance to run again. In the event that no KVM threads get a
10307 * chance to run, we will miss the entire elapsed period, as we'll have
10308 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10309 * loose cycle time. This isn't too big a deal, since the loss will be
10310 * uniform across all VCPUs (not to mention the scenario is extremely
10311 * unlikely). It is possible that a second hibernate recovery happens
10312 * much faster than a first, causing the observed TSC here to be
10313 * smaller; this would require additional padding adjustment, which is
10314 * why we set last_host_tsc to the local tsc observed here.
10315 *
10316 * N.B. - this code below runs only on platforms with reliable TSC,
10317 * as that is the only way backwards_tsc is set above. Also note
10318 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10319 * have the same delta_cyc adjustment applied if backwards_tsc
10320 * is detected. Note further, this adjustment is only done once,
10321 * as we reset last_host_tsc on all VCPUs to stop this from being
10322 * called multiple times (one for each physical CPU bringup).
10323 *
10324 * Platforms with unreliable TSCs don't have to deal with this, they
10325 * will be compensated by the logic in vcpu_load, which sets the TSC to
10326 * catchup mode. This will catchup all VCPUs to real time, but cannot
10327 * guarantee that they stay in perfect synchronization.
10328 */
10329 if (backwards_tsc) {
10330 u64 delta_cyc = max_tsc - local_tsc;
10331 list_for_each_entry(kvm, &vm_list, vm_list) {
10332 kvm->arch.backwards_tsc_observed = true;
10333 kvm_for_each_vcpu(i, vcpu, kvm) {
10334 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10335 vcpu->arch.last_host_tsc = local_tsc;
10336 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10337 }
10338
10339 /*
10340 * We have to disable TSC offset matching.. if you were
10341 * booting a VM while issuing an S4 host suspend....
10342 * you may have some problem. Solving this issue is
10343 * left as an exercise to the reader.
10344 */
10345 kvm->arch.last_tsc_nsec = 0;
10346 kvm->arch.last_tsc_write = 0;
10347 }
10348
10349 }
10350 return 0;
10351 }
10352
10353 void kvm_arch_hardware_disable(void)
10354 {
10355 static_call(kvm_x86_hardware_disable)();
10356 drop_user_return_notifiers();
10357 }
10358
10359 int kvm_arch_hardware_setup(void *opaque)
10360 {
10361 struct kvm_x86_init_ops *ops = opaque;
10362 int r;
10363
10364 rdmsrl_safe(MSR_EFER, &host_efer);
10365
10366 if (boot_cpu_has(X86_FEATURE_XSAVES))
10367 rdmsrl(MSR_IA32_XSS, host_xss);
10368
10369 r = ops->hardware_setup();
10370 if (r != 0)
10371 return r;
10372
10373 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10374 kvm_ops_static_call_update();
10375
10376 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10377 supported_xss = 0;
10378
10379 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10380 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10381 #undef __kvm_cpu_cap_has
10382
10383 if (kvm_has_tsc_control) {
10384 /*
10385 * Make sure the user can only configure tsc_khz values that
10386 * fit into a signed integer.
10387 * A min value is not calculated because it will always
10388 * be 1 on all machines.
10389 */
10390 u64 max = min(0x7fffffffULL,
10391 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10392 kvm_max_guest_tsc_khz = max;
10393
10394 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10395 }
10396
10397 kvm_init_msr_list();
10398 return 0;
10399 }
10400
10401 void kvm_arch_hardware_unsetup(void)
10402 {
10403 static_call(kvm_x86_hardware_unsetup)();
10404 }
10405
10406 int kvm_arch_check_processor_compat(void *opaque)
10407 {
10408 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10409 struct kvm_x86_init_ops *ops = opaque;
10410
10411 WARN_ON(!irqs_disabled());
10412
10413 if (__cr4_reserved_bits(cpu_has, c) !=
10414 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10415 return -EIO;
10416
10417 return ops->check_processor_compatibility();
10418 }
10419
10420 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10421 {
10422 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10423 }
10424 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10425
10426 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10427 {
10428 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10429 }
10430
10431 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
10432 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
10433
10434 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10435 {
10436 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10437
10438 vcpu->arch.l1tf_flush_l1d = true;
10439 if (pmu->version && unlikely(pmu->event_count)) {
10440 pmu->need_cleanup = true;
10441 kvm_make_request(KVM_REQ_PMU, vcpu);
10442 }
10443 static_call(kvm_x86_sched_in)(vcpu, cpu);
10444 }
10445
10446 void kvm_arch_free_vm(struct kvm *kvm)
10447 {
10448 kfree(to_kvm_hv(kvm)->hv_pa_pg);
10449 vfree(kvm);
10450 }
10451
10452
10453 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10454 {
10455 if (type)
10456 return -EINVAL;
10457
10458 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10459 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10460 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10461 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10462 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10463 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10464
10465 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10466 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10467 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10468 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10469 &kvm->arch.irq_sources_bitmap);
10470
10471 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10472 mutex_init(&kvm->arch.apic_map_lock);
10473 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10474
10475 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10476 pvclock_update_vm_gtod_copy(kvm);
10477
10478 kvm->arch.guest_can_read_msr_platform_info = true;
10479
10480 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10481 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10482
10483 kvm_hv_init_vm(kvm);
10484 kvm_page_track_init(kvm);
10485 kvm_mmu_init_vm(kvm);
10486
10487 return static_call(kvm_x86_vm_init)(kvm);
10488 }
10489
10490 int kvm_arch_post_init_vm(struct kvm *kvm)
10491 {
10492 return kvm_mmu_post_init_vm(kvm);
10493 }
10494
10495 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10496 {
10497 vcpu_load(vcpu);
10498 kvm_mmu_unload(vcpu);
10499 vcpu_put(vcpu);
10500 }
10501
10502 static void kvm_free_vcpus(struct kvm *kvm)
10503 {
10504 unsigned int i;
10505 struct kvm_vcpu *vcpu;
10506
10507 /*
10508 * Unpin any mmu pages first.
10509 */
10510 kvm_for_each_vcpu(i, vcpu, kvm) {
10511 kvm_clear_async_pf_completion_queue(vcpu);
10512 kvm_unload_vcpu_mmu(vcpu);
10513 }
10514 kvm_for_each_vcpu(i, vcpu, kvm)
10515 kvm_vcpu_destroy(vcpu);
10516
10517 mutex_lock(&kvm->lock);
10518 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10519 kvm->vcpus[i] = NULL;
10520
10521 atomic_set(&kvm->online_vcpus, 0);
10522 mutex_unlock(&kvm->lock);
10523 }
10524
10525 void kvm_arch_sync_events(struct kvm *kvm)
10526 {
10527 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10528 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10529 kvm_free_pit(kvm);
10530 }
10531
10532 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
10533
10534 /**
10535 * __x86_set_memory_region: Setup KVM internal memory slot
10536 *
10537 * @kvm: the kvm pointer to the VM.
10538 * @id: the slot ID to setup.
10539 * @gpa: the GPA to install the slot (unused when @size == 0).
10540 * @size: the size of the slot. Set to zero to uninstall a slot.
10541 *
10542 * This function helps to setup a KVM internal memory slot. Specify
10543 * @size > 0 to install a new slot, while @size == 0 to uninstall a
10544 * slot. The return code can be one of the following:
10545 *
10546 * HVA: on success (uninstall will return a bogus HVA)
10547 * -errno: on error
10548 *
10549 * The caller should always use IS_ERR() to check the return value
10550 * before use. Note, the KVM internal memory slots are guaranteed to
10551 * remain valid and unchanged until the VM is destroyed, i.e., the
10552 * GPA->HVA translation will not change. However, the HVA is a user
10553 * address, i.e. its accessibility is not guaranteed, and must be
10554 * accessed via __copy_{to,from}_user().
10555 */
10556 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
10557 u32 size)
10558 {
10559 int i, r;
10560 unsigned long hva, old_npages;
10561 struct kvm_memslots *slots = kvm_memslots(kvm);
10562 struct kvm_memory_slot *slot;
10563
10564 /* Called with kvm->slots_lock held. */
10565 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10566 return ERR_PTR_USR(-EINVAL);
10567
10568 slot = id_to_memslot(slots, id);
10569 if (size) {
10570 if (slot && slot->npages)
10571 return ERR_PTR_USR(-EEXIST);
10572
10573 /*
10574 * MAP_SHARED to prevent internal slot pages from being moved
10575 * by fork()/COW.
10576 */
10577 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10578 MAP_SHARED | MAP_ANONYMOUS, 0);
10579 if (IS_ERR((void *)hva))
10580 return (void __user *)hva;
10581 } else {
10582 if (!slot || !slot->npages)
10583 return 0;
10584
10585 old_npages = slot->npages;
10586 hva = slot->userspace_addr;
10587 }
10588
10589 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10590 struct kvm_userspace_memory_region m;
10591
10592 m.slot = id | (i << 16);
10593 m.flags = 0;
10594 m.guest_phys_addr = gpa;
10595 m.userspace_addr = hva;
10596 m.memory_size = size;
10597 r = __kvm_set_memory_region(kvm, &m);
10598 if (r < 0)
10599 return ERR_PTR_USR(r);
10600 }
10601
10602 if (!size)
10603 vm_munmap(hva, old_npages * PAGE_SIZE);
10604
10605 return (void __user *)hva;
10606 }
10607 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10608
10609 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10610 {
10611 kvm_mmu_pre_destroy_vm(kvm);
10612 }
10613
10614 void kvm_arch_destroy_vm(struct kvm *kvm)
10615 {
10616 u32 i;
10617
10618 if (current->mm == kvm->mm) {
10619 /*
10620 * Free memory regions allocated on behalf of userspace,
10621 * unless the the memory map has changed due to process exit
10622 * or fd copying.
10623 */
10624 mutex_lock(&kvm->slots_lock);
10625 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10626 0, 0);
10627 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10628 0, 0);
10629 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10630 mutex_unlock(&kvm->slots_lock);
10631 }
10632 static_call_cond(kvm_x86_vm_destroy)(kvm);
10633 for (i = 0; i < kvm->arch.msr_filter.count; i++)
10634 kfree(kvm->arch.msr_filter.ranges[i].bitmap);
10635 kvm_pic_destroy(kvm);
10636 kvm_ioapic_destroy(kvm);
10637 kvm_free_vcpus(kvm);
10638 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10639 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10640 kvm_mmu_uninit_vm(kvm);
10641 kvm_page_track_cleanup(kvm);
10642 kvm_xen_destroy_vm(kvm);
10643 kvm_hv_destroy_vm(kvm);
10644 }
10645
10646 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10647 {
10648 int i;
10649
10650 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10651 kvfree(slot->arch.rmap[i]);
10652 slot->arch.rmap[i] = NULL;
10653
10654 if (i == 0)
10655 continue;
10656
10657 kvfree(slot->arch.lpage_info[i - 1]);
10658 slot->arch.lpage_info[i - 1] = NULL;
10659 }
10660
10661 kvm_page_track_free_memslot(slot);
10662 }
10663
10664 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10665 unsigned long npages)
10666 {
10667 int i;
10668
10669 /*
10670 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10671 * old arrays will be freed by __kvm_set_memory_region() if installing
10672 * the new memslot is successful.
10673 */
10674 memset(&slot->arch, 0, sizeof(slot->arch));
10675
10676 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10677 struct kvm_lpage_info *linfo;
10678 unsigned long ugfn;
10679 int lpages;
10680 int level = i + 1;
10681
10682 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10683 slot->base_gfn, level) + 1;
10684
10685 slot->arch.rmap[i] =
10686 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10687 GFP_KERNEL_ACCOUNT);
10688 if (!slot->arch.rmap[i])
10689 goto out_free;
10690 if (i == 0)
10691 continue;
10692
10693 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10694 if (!linfo)
10695 goto out_free;
10696
10697 slot->arch.lpage_info[i - 1] = linfo;
10698
10699 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10700 linfo[0].disallow_lpage = 1;
10701 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10702 linfo[lpages - 1].disallow_lpage = 1;
10703 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10704 /*
10705 * If the gfn and userspace address are not aligned wrt each
10706 * other, disable large page support for this slot.
10707 */
10708 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10709 unsigned long j;
10710
10711 for (j = 0; j < lpages; ++j)
10712 linfo[j].disallow_lpage = 1;
10713 }
10714 }
10715
10716 if (kvm_page_track_create_memslot(slot, npages))
10717 goto out_free;
10718
10719 return 0;
10720
10721 out_free:
10722 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10723 kvfree(slot->arch.rmap[i]);
10724 slot->arch.rmap[i] = NULL;
10725 if (i == 0)
10726 continue;
10727
10728 kvfree(slot->arch.lpage_info[i - 1]);
10729 slot->arch.lpage_info[i - 1] = NULL;
10730 }
10731 return -ENOMEM;
10732 }
10733
10734 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10735 {
10736 struct kvm_vcpu *vcpu;
10737 int i;
10738
10739 /*
10740 * memslots->generation has been incremented.
10741 * mmio generation may have reached its maximum value.
10742 */
10743 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10744
10745 /* Force re-initialization of steal_time cache */
10746 kvm_for_each_vcpu(i, vcpu, kvm)
10747 kvm_vcpu_kick(vcpu);
10748 }
10749
10750 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10751 struct kvm_memory_slot *memslot,
10752 const struct kvm_userspace_memory_region *mem,
10753 enum kvm_mr_change change)
10754 {
10755 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10756 return kvm_alloc_memslot_metadata(memslot,
10757 mem->memory_size >> PAGE_SHIFT);
10758 return 0;
10759 }
10760
10761
10762 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
10763 {
10764 struct kvm_arch *ka = &kvm->arch;
10765
10766 if (!kvm_x86_ops.cpu_dirty_log_size)
10767 return;
10768
10769 if ((enable && ++ka->cpu_dirty_logging_count == 1) ||
10770 (!enable && --ka->cpu_dirty_logging_count == 0))
10771 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
10772
10773 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0);
10774 }
10775
10776 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10777 struct kvm_memory_slot *old,
10778 struct kvm_memory_slot *new,
10779 enum kvm_mr_change change)
10780 {
10781 bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES;
10782
10783 /*
10784 * Update CPU dirty logging if dirty logging is being toggled. This
10785 * applies to all operations.
10786 */
10787 if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES)
10788 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
10789
10790 /*
10791 * Nothing more to do for RO slots (which can't be dirtied and can't be
10792 * made writable) or CREATE/MOVE/DELETE of a slot.
10793 *
10794 * For a memslot with dirty logging disabled:
10795 * CREATE: No dirty mappings will already exist.
10796 * MOVE/DELETE: The old mappings will already have been cleaned up by
10797 * kvm_arch_flush_shadow_memslot()
10798 *
10799 * For a memslot with dirty logging enabled:
10800 * CREATE: No shadow pages exist, thus nothing to write-protect
10801 * and no dirty bits to clear.
10802 * MOVE/DELETE: The old mappings will already have been cleaned up by
10803 * kvm_arch_flush_shadow_memslot().
10804 */
10805 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10806 return;
10807
10808 /*
10809 * READONLY and non-flags changes were filtered out above, and the only
10810 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
10811 * logging isn't being toggled on or off.
10812 */
10813 if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES)))
10814 return;
10815
10816 if (!log_dirty_pages) {
10817 /*
10818 * Dirty logging tracks sptes in 4k granularity, meaning that
10819 * large sptes have to be split. If live migration succeeds,
10820 * the guest in the source machine will be destroyed and large
10821 * sptes will be created in the destination. However, if the
10822 * guest continues to run in the source machine (for example if
10823 * live migration fails), small sptes will remain around and
10824 * cause bad performance.
10825 *
10826 * Scan sptes if dirty logging has been stopped, dropping those
10827 * which can be collapsed into a single large-page spte. Later
10828 * page faults will create the large-page sptes.
10829 */
10830 kvm_mmu_zap_collapsible_sptes(kvm, new);
10831 } else {
10832 /* By default, write-protect everything to log writes. */
10833 int level = PG_LEVEL_4K;
10834
10835 if (kvm_x86_ops.cpu_dirty_log_size) {
10836 /*
10837 * Clear all dirty bits, unless pages are treated as
10838 * dirty from the get-go.
10839 */
10840 if (!kvm_dirty_log_manual_protect_and_init_set(kvm))
10841 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
10842
10843 /*
10844 * Write-protect large pages on write so that dirty
10845 * logging happens at 4k granularity. No need to
10846 * write-protect small SPTEs since write accesses are
10847 * logged by the CPU via dirty bits.
10848 */
10849 level = PG_LEVEL_2M;
10850 } else if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
10851 /*
10852 * If we're with initial-all-set, we don't need
10853 * to write protect any small page because
10854 * they're reported as dirty already. However
10855 * we still need to write-protect huge pages
10856 * so that the page split can happen lazily on
10857 * the first write to the huge page.
10858 */
10859 level = PG_LEVEL_2M;
10860 }
10861 kvm_mmu_slot_remove_write_access(kvm, new, level);
10862 }
10863 }
10864
10865 void kvm_arch_commit_memory_region(struct kvm *kvm,
10866 const struct kvm_userspace_memory_region *mem,
10867 struct kvm_memory_slot *old,
10868 const struct kvm_memory_slot *new,
10869 enum kvm_mr_change change)
10870 {
10871 if (!kvm->arch.n_requested_mmu_pages)
10872 kvm_mmu_change_mmu_pages(kvm,
10873 kvm_mmu_calculate_default_mmu_pages(kvm));
10874
10875 /*
10876 * FIXME: const-ify all uses of struct kvm_memory_slot.
10877 */
10878 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10879
10880 /* Free the arrays associated with the old memslot. */
10881 if (change == KVM_MR_MOVE)
10882 kvm_arch_free_memslot(kvm, old);
10883 }
10884
10885 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10886 {
10887 kvm_mmu_zap_all(kvm);
10888 }
10889
10890 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10891 struct kvm_memory_slot *slot)
10892 {
10893 kvm_page_track_flush_slot(kvm, slot);
10894 }
10895
10896 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10897 {
10898 return (is_guest_mode(vcpu) &&
10899 kvm_x86_ops.guest_apic_has_interrupt &&
10900 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
10901 }
10902
10903 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10904 {
10905 if (!list_empty_careful(&vcpu->async_pf.done))
10906 return true;
10907
10908 if (kvm_apic_has_events(vcpu))
10909 return true;
10910
10911 if (vcpu->arch.pv.pv_unhalted)
10912 return true;
10913
10914 if (vcpu->arch.exception.pending)
10915 return true;
10916
10917 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10918 (vcpu->arch.nmi_pending &&
10919 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
10920 return true;
10921
10922 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10923 (vcpu->arch.smi_pending &&
10924 static_call(kvm_x86_smi_allowed)(vcpu, false)))
10925 return true;
10926
10927 if (kvm_arch_interrupt_allowed(vcpu) &&
10928 (kvm_cpu_has_interrupt(vcpu) ||
10929 kvm_guest_apic_has_interrupt(vcpu)))
10930 return true;
10931
10932 if (kvm_hv_has_stimer_pending(vcpu))
10933 return true;
10934
10935 if (is_guest_mode(vcpu) &&
10936 kvm_x86_ops.nested_ops->hv_timer_pending &&
10937 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10938 return true;
10939
10940 return false;
10941 }
10942
10943 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10944 {
10945 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10946 }
10947
10948 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10949 {
10950 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10951 return true;
10952
10953 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10954 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10955 kvm_test_request(KVM_REQ_EVENT, vcpu))
10956 return true;
10957
10958 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
10959 return true;
10960
10961 return false;
10962 }
10963
10964 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10965 {
10966 return vcpu->arch.preempted_in_kernel;
10967 }
10968
10969 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10970 {
10971 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10972 }
10973
10974 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10975 {
10976 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
10977 }
10978
10979 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10980 {
10981 /* Can't read the RIP when guest state is protected, just return 0 */
10982 if (vcpu->arch.guest_state_protected)
10983 return 0;
10984
10985 if (is_64_bit_mode(vcpu))
10986 return kvm_rip_read(vcpu);
10987 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10988 kvm_rip_read(vcpu));
10989 }
10990 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10991
10992 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10993 {
10994 return kvm_get_linear_rip(vcpu) == linear_rip;
10995 }
10996 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10997
10998 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10999 {
11000 unsigned long rflags;
11001
11002 rflags = static_call(kvm_x86_get_rflags)(vcpu);
11003 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11004 rflags &= ~X86_EFLAGS_TF;
11005 return rflags;
11006 }
11007 EXPORT_SYMBOL_GPL(kvm_get_rflags);
11008
11009 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
11010 {
11011 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
11012 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
11013 rflags |= X86_EFLAGS_TF;
11014 static_call(kvm_x86_set_rflags)(vcpu, rflags);
11015 }
11016
11017 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
11018 {
11019 __kvm_set_rflags(vcpu, rflags);
11020 kvm_make_request(KVM_REQ_EVENT, vcpu);
11021 }
11022 EXPORT_SYMBOL_GPL(kvm_set_rflags);
11023
11024 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
11025 {
11026 int r;
11027
11028 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
11029 work->wakeup_all)
11030 return;
11031
11032 r = kvm_mmu_reload(vcpu);
11033 if (unlikely(r))
11034 return;
11035
11036 if (!vcpu->arch.mmu->direct_map &&
11037 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
11038 return;
11039
11040 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
11041 }
11042
11043 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
11044 {
11045 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
11046
11047 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
11048 }
11049
11050 static inline u32 kvm_async_pf_next_probe(u32 key)
11051 {
11052 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
11053 }
11054
11055 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
11056 {
11057 u32 key = kvm_async_pf_hash_fn(gfn);
11058
11059 while (vcpu->arch.apf.gfns[key] != ~0)
11060 key = kvm_async_pf_next_probe(key);
11061
11062 vcpu->arch.apf.gfns[key] = gfn;
11063 }
11064
11065 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
11066 {
11067 int i;
11068 u32 key = kvm_async_pf_hash_fn(gfn);
11069
11070 for (i = 0; i < ASYNC_PF_PER_VCPU &&
11071 (vcpu->arch.apf.gfns[key] != gfn &&
11072 vcpu->arch.apf.gfns[key] != ~0); i++)
11073 key = kvm_async_pf_next_probe(key);
11074
11075 return key;
11076 }
11077
11078 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
11079 {
11080 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
11081 }
11082
11083 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
11084 {
11085 u32 i, j, k;
11086
11087 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
11088
11089 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
11090 return;
11091
11092 while (true) {
11093 vcpu->arch.apf.gfns[i] = ~0;
11094 do {
11095 j = kvm_async_pf_next_probe(j);
11096 if (vcpu->arch.apf.gfns[j] == ~0)
11097 return;
11098 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
11099 /*
11100 * k lies cyclically in ]i,j]
11101 * | i.k.j |
11102 * |....j i.k.| or |.k..j i...|
11103 */
11104 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
11105 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
11106 i = j;
11107 }
11108 }
11109
11110 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
11111 {
11112 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
11113
11114 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
11115 sizeof(reason));
11116 }
11117
11118 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
11119 {
11120 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11121
11122 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11123 &token, offset, sizeof(token));
11124 }
11125
11126 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
11127 {
11128 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
11129 u32 val;
11130
11131 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
11132 &val, offset, sizeof(val)))
11133 return false;
11134
11135 return !val;
11136 }
11137
11138 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
11139 {
11140 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
11141 return false;
11142
11143 if (!kvm_pv_async_pf_enabled(vcpu) ||
11144 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0))
11145 return false;
11146
11147 return true;
11148 }
11149
11150 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
11151 {
11152 if (unlikely(!lapic_in_kernel(vcpu) ||
11153 kvm_event_needs_reinjection(vcpu) ||
11154 vcpu->arch.exception.pending))
11155 return false;
11156
11157 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
11158 return false;
11159
11160 /*
11161 * If interrupts are off we cannot even use an artificial
11162 * halt state.
11163 */
11164 return kvm_arch_interrupt_allowed(vcpu);
11165 }
11166
11167 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
11168 struct kvm_async_pf *work)
11169 {
11170 struct x86_exception fault;
11171
11172 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
11173 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
11174
11175 if (kvm_can_deliver_async_pf(vcpu) &&
11176 !apf_put_user_notpresent(vcpu)) {
11177 fault.vector = PF_VECTOR;
11178 fault.error_code_valid = true;
11179 fault.error_code = 0;
11180 fault.nested_page_fault = false;
11181 fault.address = work->arch.token;
11182 fault.async_page_fault = true;
11183 kvm_inject_page_fault(vcpu, &fault);
11184 return true;
11185 } else {
11186 /*
11187 * It is not possible to deliver a paravirtualized asynchronous
11188 * page fault, but putting the guest in an artificial halt state
11189 * can be beneficial nevertheless: if an interrupt arrives, we
11190 * can deliver it timely and perhaps the guest will schedule
11191 * another process. When the instruction that triggered a page
11192 * fault is retried, hopefully the page will be ready in the host.
11193 */
11194 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
11195 return false;
11196 }
11197 }
11198
11199 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
11200 struct kvm_async_pf *work)
11201 {
11202 struct kvm_lapic_irq irq = {
11203 .delivery_mode = APIC_DM_FIXED,
11204 .vector = vcpu->arch.apf.vec
11205 };
11206
11207 if (work->wakeup_all)
11208 work->arch.token = ~0; /* broadcast wakeup */
11209 else
11210 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
11211 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
11212
11213 if ((work->wakeup_all || work->notpresent_injected) &&
11214 kvm_pv_async_pf_enabled(vcpu) &&
11215 !apf_put_user_ready(vcpu, work->arch.token)) {
11216 vcpu->arch.apf.pageready_pending = true;
11217 kvm_apic_set_irq(vcpu, &irq, NULL);
11218 }
11219
11220 vcpu->arch.apf.halted = false;
11221 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11222 }
11223
11224 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
11225 {
11226 kvm_make_request(KVM_REQ_APF_READY, vcpu);
11227 if (!vcpu->arch.apf.pageready_pending)
11228 kvm_vcpu_kick(vcpu);
11229 }
11230
11231 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
11232 {
11233 if (!kvm_pv_async_pf_enabled(vcpu))
11234 return true;
11235 else
11236 return apf_pageready_slot_free(vcpu);
11237 }
11238
11239 void kvm_arch_start_assignment(struct kvm *kvm)
11240 {
11241 atomic_inc(&kvm->arch.assigned_device_count);
11242 }
11243 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
11244
11245 void kvm_arch_end_assignment(struct kvm *kvm)
11246 {
11247 atomic_dec(&kvm->arch.assigned_device_count);
11248 }
11249 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
11250
11251 bool kvm_arch_has_assigned_device(struct kvm *kvm)
11252 {
11253 return atomic_read(&kvm->arch.assigned_device_count);
11254 }
11255 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
11256
11257 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
11258 {
11259 atomic_inc(&kvm->arch.noncoherent_dma_count);
11260 }
11261 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
11262
11263 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
11264 {
11265 atomic_dec(&kvm->arch.noncoherent_dma_count);
11266 }
11267 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
11268
11269 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
11270 {
11271 return atomic_read(&kvm->arch.noncoherent_dma_count);
11272 }
11273 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
11274
11275 bool kvm_arch_has_irq_bypass(void)
11276 {
11277 return true;
11278 }
11279
11280 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
11281 struct irq_bypass_producer *prod)
11282 {
11283 struct kvm_kernel_irqfd *irqfd =
11284 container_of(cons, struct kvm_kernel_irqfd, consumer);
11285 int ret;
11286
11287 irqfd->producer = prod;
11288 kvm_arch_start_assignment(irqfd->kvm);
11289 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm,
11290 prod->irq, irqfd->gsi, 1);
11291
11292 if (ret)
11293 kvm_arch_end_assignment(irqfd->kvm);
11294
11295 return ret;
11296 }
11297
11298 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
11299 struct irq_bypass_producer *prod)
11300 {
11301 int ret;
11302 struct kvm_kernel_irqfd *irqfd =
11303 container_of(cons, struct kvm_kernel_irqfd, consumer);
11304
11305 WARN_ON(irqfd->producer != prod);
11306 irqfd->producer = NULL;
11307
11308 /*
11309 * When producer of consumer is unregistered, we change back to
11310 * remapped mode, so we can re-use the current implementation
11311 * when the irq is masked/disabled or the consumer side (KVM
11312 * int this case doesn't want to receive the interrupts.
11313 */
11314 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
11315 if (ret)
11316 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
11317 " fails: %d\n", irqfd->consumer.token, ret);
11318
11319 kvm_arch_end_assignment(irqfd->kvm);
11320 }
11321
11322 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
11323 uint32_t guest_irq, bool set)
11324 {
11325 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set);
11326 }
11327
11328 bool kvm_vector_hashing_enabled(void)
11329 {
11330 return vector_hashing;
11331 }
11332
11333 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11334 {
11335 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11336 }
11337 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11338
11339
11340 int kvm_spec_ctrl_test_value(u64 value)
11341 {
11342 /*
11343 * test that setting IA32_SPEC_CTRL to given value
11344 * is allowed by the host processor
11345 */
11346
11347 u64 saved_value;
11348 unsigned long flags;
11349 int ret = 0;
11350
11351 local_irq_save(flags);
11352
11353 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11354 ret = 1;
11355 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11356 ret = 1;
11357 else
11358 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11359
11360 local_irq_restore(flags);
11361
11362 return ret;
11363 }
11364 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11365
11366 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11367 {
11368 struct x86_exception fault;
11369 u32 access = error_code &
11370 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11371
11372 if (!(error_code & PFERR_PRESENT_MASK) ||
11373 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11374 /*
11375 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11376 * tables probably do not match the TLB. Just proceed
11377 * with the error code that the processor gave.
11378 */
11379 fault.vector = PF_VECTOR;
11380 fault.error_code_valid = true;
11381 fault.error_code = error_code;
11382 fault.nested_page_fault = false;
11383 fault.address = gva;
11384 }
11385 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11386 }
11387 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11388
11389 /*
11390 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11391 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11392 * indicates whether exit to userspace is needed.
11393 */
11394 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11395 struct x86_exception *e)
11396 {
11397 if (r == X86EMUL_PROPAGATE_FAULT) {
11398 kvm_inject_emulated_page_fault(vcpu, e);
11399 return 1;
11400 }
11401
11402 /*
11403 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11404 * while handling a VMX instruction KVM could've handled the request
11405 * correctly by exiting to userspace and performing I/O but there
11406 * doesn't seem to be a real use-case behind such requests, just return
11407 * KVM_EXIT_INTERNAL_ERROR for now.
11408 */
11409 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11410 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11411 vcpu->run->internal.ndata = 0;
11412
11413 return 0;
11414 }
11415 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11416
11417 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11418 {
11419 bool pcid_enabled;
11420 struct x86_exception e;
11421 unsigned i;
11422 unsigned long roots_to_free = 0;
11423 struct {
11424 u64 pcid;
11425 u64 gla;
11426 } operand;
11427 int r;
11428
11429 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11430 if (r != X86EMUL_CONTINUE)
11431 return kvm_handle_memory_failure(vcpu, r, &e);
11432
11433 if (operand.pcid >> 12 != 0) {
11434 kvm_inject_gp(vcpu, 0);
11435 return 1;
11436 }
11437
11438 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11439
11440 switch (type) {
11441 case INVPCID_TYPE_INDIV_ADDR:
11442 if ((!pcid_enabled && (operand.pcid != 0)) ||
11443 is_noncanonical_address(operand.gla, vcpu)) {
11444 kvm_inject_gp(vcpu, 0);
11445 return 1;
11446 }
11447 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11448 return kvm_skip_emulated_instruction(vcpu);
11449
11450 case INVPCID_TYPE_SINGLE_CTXT:
11451 if (!pcid_enabled && (operand.pcid != 0)) {
11452 kvm_inject_gp(vcpu, 0);
11453 return 1;
11454 }
11455
11456 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11457 kvm_mmu_sync_roots(vcpu);
11458 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11459 }
11460
11461 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11462 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11463 == operand.pcid)
11464 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11465
11466 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11467 /*
11468 * If neither the current cr3 nor any of the prev_roots use the
11469 * given PCID, then nothing needs to be done here because a
11470 * resync will happen anyway before switching to any other CR3.
11471 */
11472
11473 return kvm_skip_emulated_instruction(vcpu);
11474
11475 case INVPCID_TYPE_ALL_NON_GLOBAL:
11476 /*
11477 * Currently, KVM doesn't mark global entries in the shadow
11478 * page tables, so a non-global flush just degenerates to a
11479 * global flush. If needed, we could optimize this later by
11480 * keeping track of global entries in shadow page tables.
11481 */
11482
11483 fallthrough;
11484 case INVPCID_TYPE_ALL_INCL_GLOBAL:
11485 kvm_mmu_unload(vcpu);
11486 return kvm_skip_emulated_instruction(vcpu);
11487
11488 default:
11489 BUG(); /* We have already checked above that type <= 3 */
11490 }
11491 }
11492 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11493
11494 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
11495 {
11496 struct kvm_run *run = vcpu->run;
11497 struct kvm_mmio_fragment *frag;
11498 unsigned int len;
11499
11500 BUG_ON(!vcpu->mmio_needed);
11501
11502 /* Complete previous fragment */
11503 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11504 len = min(8u, frag->len);
11505 if (!vcpu->mmio_is_write)
11506 memcpy(frag->data, run->mmio.data, len);
11507
11508 if (frag->len <= 8) {
11509 /* Switch to the next fragment. */
11510 frag++;
11511 vcpu->mmio_cur_fragment++;
11512 } else {
11513 /* Go forward to the next mmio piece. */
11514 frag->data += len;
11515 frag->gpa += len;
11516 frag->len -= len;
11517 }
11518
11519 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11520 vcpu->mmio_needed = 0;
11521
11522 // VMG change, at this point, we're always done
11523 // RIP has already been advanced
11524 return 1;
11525 }
11526
11527 // More MMIO is needed
11528 run->mmio.phys_addr = frag->gpa;
11529 run->mmio.len = min(8u, frag->len);
11530 run->mmio.is_write = vcpu->mmio_is_write;
11531 if (run->mmio.is_write)
11532 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11533 run->exit_reason = KVM_EXIT_MMIO;
11534
11535 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11536
11537 return 0;
11538 }
11539
11540 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11541 void *data)
11542 {
11543 int handled;
11544 struct kvm_mmio_fragment *frag;
11545
11546 if (!data)
11547 return -EINVAL;
11548
11549 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11550 if (handled == bytes)
11551 return 1;
11552
11553 bytes -= handled;
11554 gpa += handled;
11555 data += handled;
11556
11557 /*TODO: Check if need to increment number of frags */
11558 frag = vcpu->mmio_fragments;
11559 vcpu->mmio_nr_fragments = 1;
11560 frag->len = bytes;
11561 frag->gpa = gpa;
11562 frag->data = data;
11563
11564 vcpu->mmio_needed = 1;
11565 vcpu->mmio_cur_fragment = 0;
11566
11567 vcpu->run->mmio.phys_addr = gpa;
11568 vcpu->run->mmio.len = min(8u, frag->len);
11569 vcpu->run->mmio.is_write = 1;
11570 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
11571 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11572
11573 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11574
11575 return 0;
11576 }
11577 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
11578
11579 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11580 void *data)
11581 {
11582 int handled;
11583 struct kvm_mmio_fragment *frag;
11584
11585 if (!data)
11586 return -EINVAL;
11587
11588 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11589 if (handled == bytes)
11590 return 1;
11591
11592 bytes -= handled;
11593 gpa += handled;
11594 data += handled;
11595
11596 /*TODO: Check if need to increment number of frags */
11597 frag = vcpu->mmio_fragments;
11598 vcpu->mmio_nr_fragments = 1;
11599 frag->len = bytes;
11600 frag->gpa = gpa;
11601 frag->data = data;
11602
11603 vcpu->mmio_needed = 1;
11604 vcpu->mmio_cur_fragment = 0;
11605
11606 vcpu->run->mmio.phys_addr = gpa;
11607 vcpu->run->mmio.len = min(8u, frag->len);
11608 vcpu->run->mmio.is_write = 0;
11609 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11610
11611 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11612
11613 return 0;
11614 }
11615 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
11616
11617 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
11618 {
11619 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data,
11620 vcpu->arch.pio.count * vcpu->arch.pio.size);
11621 vcpu->arch.pio.count = 0;
11622
11623 return 1;
11624 }
11625
11626 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
11627 unsigned int port, void *data, unsigned int count)
11628 {
11629 int ret;
11630
11631 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port,
11632 data, count);
11633 if (ret)
11634 return ret;
11635
11636 vcpu->arch.pio.count = 0;
11637
11638 return 0;
11639 }
11640
11641 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
11642 unsigned int port, void *data, unsigned int count)
11643 {
11644 int ret;
11645
11646 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port,
11647 data, count);
11648 if (ret) {
11649 vcpu->arch.pio.count = 0;
11650 } else {
11651 vcpu->arch.guest_ins_data = data;
11652 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
11653 }
11654
11655 return 0;
11656 }
11657
11658 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
11659 unsigned int port, void *data, unsigned int count,
11660 int in)
11661 {
11662 return in ? kvm_sev_es_ins(vcpu, size, port, data, count)
11663 : kvm_sev_es_outs(vcpu, size, port, data, count);
11664 }
11665 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
11666
11667 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
11668 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11669 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11670 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11671 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11672 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11673 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11674 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11675 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11676 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11677 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11678 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11679 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11680 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11681 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11682 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11683 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11684 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11685 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11686 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11687 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11688 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11689 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
11690 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
11691 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
11692 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
11693 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
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