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Merge branch 'for-linus' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
50
51 #define CREATE_TRACE_POINTS
52 #include "trace.h"
53
54 #include <asm/debugreg.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <asm/mtrr.h>
58 #include <asm/mce.h>
59 #include <asm/i387.h>
60 #include <asm/fpu-internal.h> /* Ugh! */
61 #include <asm/xcr.h>
62 #include <asm/pvclock.h>
63 #include <asm/div64.h>
64
65 #define MAX_IO_MSRS 256
66 #define KVM_MAX_MCE_BANKS 32
67 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
68
69 #define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
72 /* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76 #ifdef CONFIG_X86_64
77 static
78 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
79 #else
80 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
81 #endif
82
83 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
85
86 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
87 static void process_nmi(struct kvm_vcpu *vcpu);
88
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
91
92 static bool ignore_msrs = 0;
93 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
95 bool kvm_has_tsc_control;
96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97 u32 kvm_max_guest_tsc_khz;
98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
100 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101 static u32 tsc_tolerance_ppm = 250;
102 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
104 #define KVM_NR_SHARED_MSRS 16
105
106 struct kvm_shared_msrs_global {
107 int nr;
108 u32 msrs[KVM_NR_SHARED_MSRS];
109 };
110
111 struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
118 };
119
120 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
123 struct kvm_stats_debugfs_item debugfs_entries[] = {
124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
136 { "hypercalls", VCPU_STAT(hypercalls) },
137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
144 { "irq_injections", VCPU_STAT(irq_injections) },
145 { "nmi_injections", VCPU_STAT(nmi_injections) },
146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
153 { "mmu_unsync", VM_STAT(mmu_unsync) },
154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
155 { "largepages", VM_STAT(lpages) },
156 { NULL }
157 };
158
159 u64 __read_mostly host_xcr0;
160
161 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
163 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164 {
165 int i;
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
168 }
169
170 static void kvm_on_user_return(struct user_return_notifier *urn)
171 {
172 unsigned slot;
173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
175 struct kvm_shared_msr_values *values;
176
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
182 }
183 }
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
186 }
187
188 static void shared_msr_update(unsigned slot, u32 msr)
189 {
190 struct kvm_shared_msrs *smsr;
191 u64 value;
192
193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
198 return;
199 }
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
203 }
204
205 void kvm_define_shared_msr(unsigned slot, u32 msr)
206 {
207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
211 smp_wmb();
212 }
213 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215 static void kvm_shared_msr_cpu_online(void)
216 {
217 unsigned i;
218
219 for (i = 0; i < shared_msrs_global.nr; ++i)
220 shared_msr_update(i, shared_msrs_global.msrs[i]);
221 }
222
223 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
224 {
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
228 return;
229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
235 }
236 }
237 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
239 static void drop_user_return_notifiers(void *ignore)
240 {
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
245 }
246
247 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248 {
249 if (irqchip_in_kernel(vcpu->kvm))
250 return vcpu->arch.apic_base;
251 else
252 return vcpu->arch.apic_base;
253 }
254 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
255
256 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
257 {
258 /* TODO: reserve bits check */
259 if (irqchip_in_kernel(vcpu->kvm))
260 kvm_lapic_set_base(vcpu, data);
261 else
262 vcpu->arch.apic_base = data;
263 }
264 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
266 #define EXCPT_BENIGN 0
267 #define EXCPT_CONTRIBUTORY 1
268 #define EXCPT_PF 2
269
270 static int exception_class(int vector)
271 {
272 switch (vector) {
273 case PF_VECTOR:
274 return EXCPT_PF;
275 case DE_VECTOR:
276 case TS_VECTOR:
277 case NP_VECTOR:
278 case SS_VECTOR:
279 case GP_VECTOR:
280 return EXCPT_CONTRIBUTORY;
281 default:
282 break;
283 }
284 return EXCPT_BENIGN;
285 }
286
287 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
288 unsigned nr, bool has_error, u32 error_code,
289 bool reinject)
290 {
291 u32 prev_nr;
292 int class1, class2;
293
294 kvm_make_request(KVM_REQ_EVENT, vcpu);
295
296 if (!vcpu->arch.exception.pending) {
297 queue:
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
302 vcpu->arch.exception.reinject = reinject;
303 return;
304 }
305
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
311 return;
312 }
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
322 } else
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
325 exception */
326 goto queue;
327 }
328
329 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 {
331 kvm_multiple_exception(vcpu, nr, false, 0, false);
332 }
333 EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
335 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336 {
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
338 }
339 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
341 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
342 {
343 if (err)
344 kvm_inject_gp(vcpu, 0);
345 else
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
347 }
348 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
349
350 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
351 {
352 ++vcpu->stat.pf_guest;
353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
355 }
356 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
357
358 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
359 {
360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
362 else
363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
364 }
365
366 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367 {
368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
370 }
371 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
373 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374 {
375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
376 }
377 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
379 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380 {
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382 }
383 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
385 /*
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
388 */
389 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
390 {
391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 return true;
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394 return false;
395 }
396 EXPORT_SYMBOL_GPL(kvm_require_cpl);
397
398 /*
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
402 */
403 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
405 u32 access)
406 {
407 gfn_t real_gfn;
408 gpa_t ngpa;
409
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
413 return -EFAULT;
414
415 real_gfn = gpa_to_gfn(real_gfn);
416
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418 }
419 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
421 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
423 {
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
426 }
427
428 /*
429 * Load the pae pdptrs. Return true is they are all valid.
430 */
431 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
432 {
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435 int i;
436 int ret;
437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
438
439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
442 if (ret < 0) {
443 ret = 0;
444 goto out;
445 }
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
447 if (is_present_gpte(pdpte[i]) &&
448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
449 ret = 0;
450 goto out;
451 }
452 }
453 ret = 1;
454
455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
460 out:
461
462 return ret;
463 }
464 EXPORT_SYMBOL_GPL(load_pdptrs);
465
466 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467 {
468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
469 bool changed = true;
470 int offset;
471 gfn_t gfn;
472 int r;
473
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
475 return false;
476
477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
479 return true;
480
481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
485 if (r < 0)
486 goto out;
487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
488 out:
489
490 return changed;
491 }
492
493 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
494 {
495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
498
499 cr0 |= X86_CR0_ET;
500
501 #ifdef CONFIG_X86_64
502 if (cr0 & 0xffffffff00000000UL)
503 return 1;
504 #endif
505
506 cr0 &= ~CR0_RESERVED_BITS;
507
508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509 return 1;
510
511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512 return 1;
513
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515 #ifdef CONFIG_X86_64
516 if ((vcpu->arch.efer & EFER_LME)) {
517 int cs_db, cs_l;
518
519 if (!is_pae(vcpu))
520 return 1;
521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
522 if (cs_l)
523 return 1;
524 } else
525 #endif
526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
527 kvm_read_cr3(vcpu)))
528 return 1;
529 }
530
531 kvm_x86_ops->set_cr0(vcpu, cr0);
532
533 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
534 kvm_clear_async_pf_completion_queue(vcpu);
535 kvm_async_pf_hash_reset(vcpu);
536 }
537
538 if ((cr0 ^ old_cr0) & update_bits)
539 kvm_mmu_reset_context(vcpu);
540 return 0;
541 }
542 EXPORT_SYMBOL_GPL(kvm_set_cr0);
543
544 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
545 {
546 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
547 }
548 EXPORT_SYMBOL_GPL(kvm_lmsw);
549
550 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
551 {
552 u64 xcr0;
553
554 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
555 if (index != XCR_XFEATURE_ENABLED_MASK)
556 return 1;
557 xcr0 = xcr;
558 if (kvm_x86_ops->get_cpl(vcpu) != 0)
559 return 1;
560 if (!(xcr0 & XSTATE_FP))
561 return 1;
562 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
563 return 1;
564 if (xcr0 & ~host_xcr0)
565 return 1;
566 vcpu->arch.xcr0 = xcr0;
567 vcpu->guest_xcr0_loaded = 0;
568 return 0;
569 }
570
571 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
572 {
573 if (__kvm_set_xcr(vcpu, index, xcr)) {
574 kvm_inject_gp(vcpu, 0);
575 return 1;
576 }
577 return 0;
578 }
579 EXPORT_SYMBOL_GPL(kvm_set_xcr);
580
581 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
582 {
583 unsigned long old_cr4 = kvm_read_cr4(vcpu);
584 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
585 X86_CR4_PAE | X86_CR4_SMEP;
586 if (cr4 & CR4_RESERVED_BITS)
587 return 1;
588
589 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
590 return 1;
591
592 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
593 return 1;
594
595 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
596 return 1;
597
598 if (is_long_mode(vcpu)) {
599 if (!(cr4 & X86_CR4_PAE))
600 return 1;
601 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
602 && ((cr4 ^ old_cr4) & pdptr_bits)
603 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
604 kvm_read_cr3(vcpu)))
605 return 1;
606
607 if (kvm_x86_ops->set_cr4(vcpu, cr4))
608 return 1;
609
610 if ((cr4 ^ old_cr4) & pdptr_bits)
611 kvm_mmu_reset_context(vcpu);
612
613 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
614 kvm_update_cpuid(vcpu);
615
616 return 0;
617 }
618 EXPORT_SYMBOL_GPL(kvm_set_cr4);
619
620 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
621 {
622 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
623 kvm_mmu_sync_roots(vcpu);
624 kvm_mmu_flush_tlb(vcpu);
625 return 0;
626 }
627
628 if (is_long_mode(vcpu)) {
629 if (cr3 & CR3_L_MODE_RESERVED_BITS)
630 return 1;
631 } else {
632 if (is_pae(vcpu)) {
633 if (cr3 & CR3_PAE_RESERVED_BITS)
634 return 1;
635 if (is_paging(vcpu) &&
636 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
637 return 1;
638 }
639 /*
640 * We don't check reserved bits in nonpae mode, because
641 * this isn't enforced, and VMware depends on this.
642 */
643 }
644
645 /*
646 * Does the new cr3 value map to physical memory? (Note, we
647 * catch an invalid cr3 even in real-mode, because it would
648 * cause trouble later on when we turn on paging anyway.)
649 *
650 * A real CPU would silently accept an invalid cr3 and would
651 * attempt to use it - with largely undefined (and often hard
652 * to debug) behavior on the guest side.
653 */
654 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
655 return 1;
656 vcpu->arch.cr3 = cr3;
657 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
658 vcpu->arch.mmu.new_cr3(vcpu);
659 return 0;
660 }
661 EXPORT_SYMBOL_GPL(kvm_set_cr3);
662
663 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
664 {
665 if (cr8 & CR8_RESERVED_BITS)
666 return 1;
667 if (irqchip_in_kernel(vcpu->kvm))
668 kvm_lapic_set_tpr(vcpu, cr8);
669 else
670 vcpu->arch.cr8 = cr8;
671 return 0;
672 }
673 EXPORT_SYMBOL_GPL(kvm_set_cr8);
674
675 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
676 {
677 if (irqchip_in_kernel(vcpu->kvm))
678 return kvm_lapic_get_cr8(vcpu);
679 else
680 return vcpu->arch.cr8;
681 }
682 EXPORT_SYMBOL_GPL(kvm_get_cr8);
683
684 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
685 {
686 switch (dr) {
687 case 0 ... 3:
688 vcpu->arch.db[dr] = val;
689 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
690 vcpu->arch.eff_db[dr] = val;
691 break;
692 case 4:
693 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
694 return 1; /* #UD */
695 /* fall through */
696 case 6:
697 if (val & 0xffffffff00000000ULL)
698 return -1; /* #GP */
699 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
700 break;
701 case 5:
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
703 return 1; /* #UD */
704 /* fall through */
705 default: /* 7 */
706 if (val & 0xffffffff00000000ULL)
707 return -1; /* #GP */
708 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
709 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
710 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
711 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
712 }
713 break;
714 }
715
716 return 0;
717 }
718
719 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
720 {
721 int res;
722
723 res = __kvm_set_dr(vcpu, dr, val);
724 if (res > 0)
725 kvm_queue_exception(vcpu, UD_VECTOR);
726 else if (res < 0)
727 kvm_inject_gp(vcpu, 0);
728
729 return res;
730 }
731 EXPORT_SYMBOL_GPL(kvm_set_dr);
732
733 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
734 {
735 switch (dr) {
736 case 0 ... 3:
737 *val = vcpu->arch.db[dr];
738 break;
739 case 4:
740 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
741 return 1;
742 /* fall through */
743 case 6:
744 *val = vcpu->arch.dr6;
745 break;
746 case 5:
747 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
748 return 1;
749 /* fall through */
750 default: /* 7 */
751 *val = vcpu->arch.dr7;
752 break;
753 }
754
755 return 0;
756 }
757
758 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
759 {
760 if (_kvm_get_dr(vcpu, dr, val)) {
761 kvm_queue_exception(vcpu, UD_VECTOR);
762 return 1;
763 }
764 return 0;
765 }
766 EXPORT_SYMBOL_GPL(kvm_get_dr);
767
768 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
769 {
770 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
771 u64 data;
772 int err;
773
774 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
775 if (err)
776 return err;
777 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
778 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
779 return err;
780 }
781 EXPORT_SYMBOL_GPL(kvm_rdpmc);
782
783 /*
784 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
785 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
786 *
787 * This list is modified at module load time to reflect the
788 * capabilities of the host cpu. This capabilities test skips MSRs that are
789 * kvm-specific. Those are put in the beginning of the list.
790 */
791
792 #define KVM_SAVE_MSRS_BEGIN 9
793 static u32 msrs_to_save[] = {
794 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
795 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
796 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
797 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
798 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
799 MSR_STAR,
800 #ifdef CONFIG_X86_64
801 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
802 #endif
803 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
804 };
805
806 static unsigned num_msrs_to_save;
807
808 static u32 emulated_msrs[] = {
809 MSR_IA32_TSCDEADLINE,
810 MSR_IA32_MISC_ENABLE,
811 MSR_IA32_MCG_STATUS,
812 MSR_IA32_MCG_CTL,
813 };
814
815 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
816 {
817 u64 old_efer = vcpu->arch.efer;
818
819 if (efer & efer_reserved_bits)
820 return 1;
821
822 if (is_paging(vcpu)
823 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
824 return 1;
825
826 if (efer & EFER_FFXSR) {
827 struct kvm_cpuid_entry2 *feat;
828
829 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
830 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
831 return 1;
832 }
833
834 if (efer & EFER_SVME) {
835 struct kvm_cpuid_entry2 *feat;
836
837 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
838 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
839 return 1;
840 }
841
842 efer &= ~EFER_LMA;
843 efer |= vcpu->arch.efer & EFER_LMA;
844
845 kvm_x86_ops->set_efer(vcpu, efer);
846
847 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
848
849 /* Update reserved bits */
850 if ((efer ^ old_efer) & EFER_NX)
851 kvm_mmu_reset_context(vcpu);
852
853 return 0;
854 }
855
856 void kvm_enable_efer_bits(u64 mask)
857 {
858 efer_reserved_bits &= ~mask;
859 }
860 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
861
862
863 /*
864 * Writes msr value into into the appropriate "register".
865 * Returns 0 on success, non-0 otherwise.
866 * Assumes vcpu_load() was already called.
867 */
868 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
869 {
870 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
871 }
872
873 /*
874 * Adapt set_msr() to msr_io()'s calling convention
875 */
876 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
877 {
878 return kvm_set_msr(vcpu, index, *data);
879 }
880
881 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
882 {
883 int version;
884 int r;
885 struct pvclock_wall_clock wc;
886 struct timespec boot;
887
888 if (!wall_clock)
889 return;
890
891 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
892 if (r)
893 return;
894
895 if (version & 1)
896 ++version; /* first time write, random junk */
897
898 ++version;
899
900 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
901
902 /*
903 * The guest calculates current wall clock time by adding
904 * system time (updated by kvm_guest_time_update below) to the
905 * wall clock specified here. guest system time equals host
906 * system time for us, thus we must fill in host boot time here.
907 */
908 getboottime(&boot);
909
910 wc.sec = boot.tv_sec;
911 wc.nsec = boot.tv_nsec;
912 wc.version = version;
913
914 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
915
916 version++;
917 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
918 }
919
920 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
921 {
922 uint32_t quotient, remainder;
923
924 /* Don't try to replace with do_div(), this one calculates
925 * "(dividend << 32) / divisor" */
926 __asm__ ( "divl %4"
927 : "=a" (quotient), "=d" (remainder)
928 : "0" (0), "1" (dividend), "r" (divisor) );
929 return quotient;
930 }
931
932 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
933 s8 *pshift, u32 *pmultiplier)
934 {
935 uint64_t scaled64;
936 int32_t shift = 0;
937 uint64_t tps64;
938 uint32_t tps32;
939
940 tps64 = base_khz * 1000LL;
941 scaled64 = scaled_khz * 1000LL;
942 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
943 tps64 >>= 1;
944 shift--;
945 }
946
947 tps32 = (uint32_t)tps64;
948 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
949 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
950 scaled64 >>= 1;
951 else
952 tps32 <<= 1;
953 shift++;
954 }
955
956 *pshift = shift;
957 *pmultiplier = div_frac(scaled64, tps32);
958
959 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
960 __func__, base_khz, scaled_khz, shift, *pmultiplier);
961 }
962
963 static inline u64 get_kernel_ns(void)
964 {
965 struct timespec ts;
966
967 WARN_ON(preemptible());
968 ktime_get_ts(&ts);
969 monotonic_to_bootbased(&ts);
970 return timespec_to_ns(&ts);
971 }
972
973 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
974 unsigned long max_tsc_khz;
975
976 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
977 {
978 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
979 vcpu->arch.virtual_tsc_shift);
980 }
981
982 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
983 {
984 u64 v = (u64)khz * (1000000 + ppm);
985 do_div(v, 1000000);
986 return v;
987 }
988
989 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
990 {
991 u32 thresh_lo, thresh_hi;
992 int use_scaling = 0;
993
994 /* Compute a scale to convert nanoseconds in TSC cycles */
995 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
996 &vcpu->arch.virtual_tsc_shift,
997 &vcpu->arch.virtual_tsc_mult);
998 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
999
1000 /*
1001 * Compute the variation in TSC rate which is acceptable
1002 * within the range of tolerance and decide if the
1003 * rate being applied is within that bounds of the hardware
1004 * rate. If so, no scaling or compensation need be done.
1005 */
1006 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1007 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1008 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1009 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1010 use_scaling = 1;
1011 }
1012 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1013 }
1014
1015 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1016 {
1017 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1018 vcpu->arch.virtual_tsc_mult,
1019 vcpu->arch.virtual_tsc_shift);
1020 tsc += vcpu->arch.this_tsc_write;
1021 return tsc;
1022 }
1023
1024 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1025 {
1026 struct kvm *kvm = vcpu->kvm;
1027 u64 offset, ns, elapsed;
1028 unsigned long flags;
1029 s64 usdiff;
1030
1031 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1032 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1033 ns = get_kernel_ns();
1034 elapsed = ns - kvm->arch.last_tsc_nsec;
1035
1036 /* n.b - signed multiplication and division required */
1037 usdiff = data - kvm->arch.last_tsc_write;
1038 #ifdef CONFIG_X86_64
1039 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1040 #else
1041 /* do_div() only does unsigned */
1042 asm("idivl %2; xor %%edx, %%edx"
1043 : "=A"(usdiff)
1044 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1045 #endif
1046 do_div(elapsed, 1000);
1047 usdiff -= elapsed;
1048 if (usdiff < 0)
1049 usdiff = -usdiff;
1050
1051 /*
1052 * Special case: TSC write with a small delta (1 second) of virtual
1053 * cycle time against real time is interpreted as an attempt to
1054 * synchronize the CPU.
1055 *
1056 * For a reliable TSC, we can match TSC offsets, and for an unstable
1057 * TSC, we add elapsed time in this computation. We could let the
1058 * compensation code attempt to catch up if we fall behind, but
1059 * it's better to try to match offsets from the beginning.
1060 */
1061 if (usdiff < USEC_PER_SEC &&
1062 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1063 if (!check_tsc_unstable()) {
1064 offset = kvm->arch.cur_tsc_offset;
1065 pr_debug("kvm: matched tsc offset for %llu\n", data);
1066 } else {
1067 u64 delta = nsec_to_cycles(vcpu, elapsed);
1068 data += delta;
1069 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1070 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1071 }
1072 } else {
1073 /*
1074 * We split periods of matched TSC writes into generations.
1075 * For each generation, we track the original measured
1076 * nanosecond time, offset, and write, so if TSCs are in
1077 * sync, we can match exact offset, and if not, we can match
1078 * exact software computaion in compute_guest_tsc()
1079 *
1080 * These values are tracked in kvm->arch.cur_xxx variables.
1081 */
1082 kvm->arch.cur_tsc_generation++;
1083 kvm->arch.cur_tsc_nsec = ns;
1084 kvm->arch.cur_tsc_write = data;
1085 kvm->arch.cur_tsc_offset = offset;
1086 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1087 kvm->arch.cur_tsc_generation, data);
1088 }
1089
1090 /*
1091 * We also track th most recent recorded KHZ, write and time to
1092 * allow the matching interval to be extended at each write.
1093 */
1094 kvm->arch.last_tsc_nsec = ns;
1095 kvm->arch.last_tsc_write = data;
1096 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1097
1098 /* Reset of TSC must disable overshoot protection below */
1099 vcpu->arch.hv_clock.tsc_timestamp = 0;
1100 vcpu->arch.last_guest_tsc = data;
1101
1102 /* Keep track of which generation this VCPU has synchronized to */
1103 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1104 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1105 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1106
1107 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1108 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1109 }
1110
1111 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1112
1113 static int kvm_guest_time_update(struct kvm_vcpu *v)
1114 {
1115 unsigned long flags;
1116 struct kvm_vcpu_arch *vcpu = &v->arch;
1117 void *shared_kaddr;
1118 unsigned long this_tsc_khz;
1119 s64 kernel_ns, max_kernel_ns;
1120 u64 tsc_timestamp;
1121
1122 /* Keep irq disabled to prevent changes to the clock */
1123 local_irq_save(flags);
1124 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1125 kernel_ns = get_kernel_ns();
1126 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1127 if (unlikely(this_tsc_khz == 0)) {
1128 local_irq_restore(flags);
1129 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1130 return 1;
1131 }
1132
1133 /*
1134 * We may have to catch up the TSC to match elapsed wall clock
1135 * time for two reasons, even if kvmclock is used.
1136 * 1) CPU could have been running below the maximum TSC rate
1137 * 2) Broken TSC compensation resets the base at each VCPU
1138 * entry to avoid unknown leaps of TSC even when running
1139 * again on the same CPU. This may cause apparent elapsed
1140 * time to disappear, and the guest to stand still or run
1141 * very slowly.
1142 */
1143 if (vcpu->tsc_catchup) {
1144 u64 tsc = compute_guest_tsc(v, kernel_ns);
1145 if (tsc > tsc_timestamp) {
1146 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1147 tsc_timestamp = tsc;
1148 }
1149 }
1150
1151 local_irq_restore(flags);
1152
1153 if (!vcpu->time_page)
1154 return 0;
1155
1156 /*
1157 * Time as measured by the TSC may go backwards when resetting the base
1158 * tsc_timestamp. The reason for this is that the TSC resolution is
1159 * higher than the resolution of the other clock scales. Thus, many
1160 * possible measurments of the TSC correspond to one measurement of any
1161 * other clock, and so a spread of values is possible. This is not a
1162 * problem for the computation of the nanosecond clock; with TSC rates
1163 * around 1GHZ, there can only be a few cycles which correspond to one
1164 * nanosecond value, and any path through this code will inevitably
1165 * take longer than that. However, with the kernel_ns value itself,
1166 * the precision may be much lower, down to HZ granularity. If the
1167 * first sampling of TSC against kernel_ns ends in the low part of the
1168 * range, and the second in the high end of the range, we can get:
1169 *
1170 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1171 *
1172 * As the sampling errors potentially range in the thousands of cycles,
1173 * it is possible such a time value has already been observed by the
1174 * guest. To protect against this, we must compute the system time as
1175 * observed by the guest and ensure the new system time is greater.
1176 */
1177 max_kernel_ns = 0;
1178 if (vcpu->hv_clock.tsc_timestamp) {
1179 max_kernel_ns = vcpu->last_guest_tsc -
1180 vcpu->hv_clock.tsc_timestamp;
1181 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1182 vcpu->hv_clock.tsc_to_system_mul,
1183 vcpu->hv_clock.tsc_shift);
1184 max_kernel_ns += vcpu->last_kernel_ns;
1185 }
1186
1187 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1188 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1189 &vcpu->hv_clock.tsc_shift,
1190 &vcpu->hv_clock.tsc_to_system_mul);
1191 vcpu->hw_tsc_khz = this_tsc_khz;
1192 }
1193
1194 if (max_kernel_ns > kernel_ns)
1195 kernel_ns = max_kernel_ns;
1196
1197 /* With all the info we got, fill in the values */
1198 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1199 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1200 vcpu->last_kernel_ns = kernel_ns;
1201 vcpu->last_guest_tsc = tsc_timestamp;
1202 vcpu->hv_clock.flags = 0;
1203
1204 /*
1205 * The interface expects us to write an even number signaling that the
1206 * update is finished. Since the guest won't see the intermediate
1207 * state, we just increase by 2 at the end.
1208 */
1209 vcpu->hv_clock.version += 2;
1210
1211 shared_kaddr = kmap_atomic(vcpu->time_page);
1212
1213 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1214 sizeof(vcpu->hv_clock));
1215
1216 kunmap_atomic(shared_kaddr);
1217
1218 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1219 return 0;
1220 }
1221
1222 static bool msr_mtrr_valid(unsigned msr)
1223 {
1224 switch (msr) {
1225 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1226 case MSR_MTRRfix64K_00000:
1227 case MSR_MTRRfix16K_80000:
1228 case MSR_MTRRfix16K_A0000:
1229 case MSR_MTRRfix4K_C0000:
1230 case MSR_MTRRfix4K_C8000:
1231 case MSR_MTRRfix4K_D0000:
1232 case MSR_MTRRfix4K_D8000:
1233 case MSR_MTRRfix4K_E0000:
1234 case MSR_MTRRfix4K_E8000:
1235 case MSR_MTRRfix4K_F0000:
1236 case MSR_MTRRfix4K_F8000:
1237 case MSR_MTRRdefType:
1238 case MSR_IA32_CR_PAT:
1239 return true;
1240 case 0x2f8:
1241 return true;
1242 }
1243 return false;
1244 }
1245
1246 static bool valid_pat_type(unsigned t)
1247 {
1248 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1249 }
1250
1251 static bool valid_mtrr_type(unsigned t)
1252 {
1253 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1254 }
1255
1256 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1257 {
1258 int i;
1259
1260 if (!msr_mtrr_valid(msr))
1261 return false;
1262
1263 if (msr == MSR_IA32_CR_PAT) {
1264 for (i = 0; i < 8; i++)
1265 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1266 return false;
1267 return true;
1268 } else if (msr == MSR_MTRRdefType) {
1269 if (data & ~0xcff)
1270 return false;
1271 return valid_mtrr_type(data & 0xff);
1272 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1273 for (i = 0; i < 8 ; i++)
1274 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1275 return false;
1276 return true;
1277 }
1278
1279 /* variable MTRRs */
1280 return valid_mtrr_type(data & 0xff);
1281 }
1282
1283 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1284 {
1285 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1286
1287 if (!mtrr_valid(vcpu, msr, data))
1288 return 1;
1289
1290 if (msr == MSR_MTRRdefType) {
1291 vcpu->arch.mtrr_state.def_type = data;
1292 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1293 } else if (msr == MSR_MTRRfix64K_00000)
1294 p[0] = data;
1295 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1296 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1297 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1298 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1299 else if (msr == MSR_IA32_CR_PAT)
1300 vcpu->arch.pat = data;
1301 else { /* Variable MTRRs */
1302 int idx, is_mtrr_mask;
1303 u64 *pt;
1304
1305 idx = (msr - 0x200) / 2;
1306 is_mtrr_mask = msr - 0x200 - 2 * idx;
1307 if (!is_mtrr_mask)
1308 pt =
1309 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1310 else
1311 pt =
1312 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1313 *pt = data;
1314 }
1315
1316 kvm_mmu_reset_context(vcpu);
1317 return 0;
1318 }
1319
1320 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1321 {
1322 u64 mcg_cap = vcpu->arch.mcg_cap;
1323 unsigned bank_num = mcg_cap & 0xff;
1324
1325 switch (msr) {
1326 case MSR_IA32_MCG_STATUS:
1327 vcpu->arch.mcg_status = data;
1328 break;
1329 case MSR_IA32_MCG_CTL:
1330 if (!(mcg_cap & MCG_CTL_P))
1331 return 1;
1332 if (data != 0 && data != ~(u64)0)
1333 return -1;
1334 vcpu->arch.mcg_ctl = data;
1335 break;
1336 default:
1337 if (msr >= MSR_IA32_MC0_CTL &&
1338 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1339 u32 offset = msr - MSR_IA32_MC0_CTL;
1340 /* only 0 or all 1s can be written to IA32_MCi_CTL
1341 * some Linux kernels though clear bit 10 in bank 4 to
1342 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1343 * this to avoid an uncatched #GP in the guest
1344 */
1345 if ((offset & 0x3) == 0 &&
1346 data != 0 && (data | (1 << 10)) != ~(u64)0)
1347 return -1;
1348 vcpu->arch.mce_banks[offset] = data;
1349 break;
1350 }
1351 return 1;
1352 }
1353 return 0;
1354 }
1355
1356 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1357 {
1358 struct kvm *kvm = vcpu->kvm;
1359 int lm = is_long_mode(vcpu);
1360 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1361 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1362 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1363 : kvm->arch.xen_hvm_config.blob_size_32;
1364 u32 page_num = data & ~PAGE_MASK;
1365 u64 page_addr = data & PAGE_MASK;
1366 u8 *page;
1367 int r;
1368
1369 r = -E2BIG;
1370 if (page_num >= blob_size)
1371 goto out;
1372 r = -ENOMEM;
1373 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1374 if (IS_ERR(page)) {
1375 r = PTR_ERR(page);
1376 goto out;
1377 }
1378 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1379 goto out_free;
1380 r = 0;
1381 out_free:
1382 kfree(page);
1383 out:
1384 return r;
1385 }
1386
1387 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1388 {
1389 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1390 }
1391
1392 static bool kvm_hv_msr_partition_wide(u32 msr)
1393 {
1394 bool r = false;
1395 switch (msr) {
1396 case HV_X64_MSR_GUEST_OS_ID:
1397 case HV_X64_MSR_HYPERCALL:
1398 r = true;
1399 break;
1400 }
1401
1402 return r;
1403 }
1404
1405 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1406 {
1407 struct kvm *kvm = vcpu->kvm;
1408
1409 switch (msr) {
1410 case HV_X64_MSR_GUEST_OS_ID:
1411 kvm->arch.hv_guest_os_id = data;
1412 /* setting guest os id to zero disables hypercall page */
1413 if (!kvm->arch.hv_guest_os_id)
1414 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1415 break;
1416 case HV_X64_MSR_HYPERCALL: {
1417 u64 gfn;
1418 unsigned long addr;
1419 u8 instructions[4];
1420
1421 /* if guest os id is not set hypercall should remain disabled */
1422 if (!kvm->arch.hv_guest_os_id)
1423 break;
1424 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1425 kvm->arch.hv_hypercall = data;
1426 break;
1427 }
1428 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1429 addr = gfn_to_hva(kvm, gfn);
1430 if (kvm_is_error_hva(addr))
1431 return 1;
1432 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1433 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1434 if (__copy_to_user((void __user *)addr, instructions, 4))
1435 return 1;
1436 kvm->arch.hv_hypercall = data;
1437 break;
1438 }
1439 default:
1440 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1441 "data 0x%llx\n", msr, data);
1442 return 1;
1443 }
1444 return 0;
1445 }
1446
1447 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1448 {
1449 switch (msr) {
1450 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1451 unsigned long addr;
1452
1453 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1454 vcpu->arch.hv_vapic = data;
1455 break;
1456 }
1457 addr = gfn_to_hva(vcpu->kvm, data >>
1458 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1459 if (kvm_is_error_hva(addr))
1460 return 1;
1461 if (__clear_user((void __user *)addr, PAGE_SIZE))
1462 return 1;
1463 vcpu->arch.hv_vapic = data;
1464 break;
1465 }
1466 case HV_X64_MSR_EOI:
1467 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1468 case HV_X64_MSR_ICR:
1469 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1470 case HV_X64_MSR_TPR:
1471 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1472 default:
1473 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1474 "data 0x%llx\n", msr, data);
1475 return 1;
1476 }
1477
1478 return 0;
1479 }
1480
1481 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1482 {
1483 gpa_t gpa = data & ~0x3f;
1484
1485 /* Bits 2:5 are resrved, Should be zero */
1486 if (data & 0x3c)
1487 return 1;
1488
1489 vcpu->arch.apf.msr_val = data;
1490
1491 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1492 kvm_clear_async_pf_completion_queue(vcpu);
1493 kvm_async_pf_hash_reset(vcpu);
1494 return 0;
1495 }
1496
1497 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1498 return 1;
1499
1500 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1501 kvm_async_pf_wakeup_all(vcpu);
1502 return 0;
1503 }
1504
1505 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1506 {
1507 if (vcpu->arch.time_page) {
1508 kvm_release_page_dirty(vcpu->arch.time_page);
1509 vcpu->arch.time_page = NULL;
1510 }
1511 }
1512
1513 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1514 {
1515 u64 delta;
1516
1517 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1518 return;
1519
1520 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1521 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1522 vcpu->arch.st.accum_steal = delta;
1523 }
1524
1525 static void record_steal_time(struct kvm_vcpu *vcpu)
1526 {
1527 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1528 return;
1529
1530 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1531 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1532 return;
1533
1534 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1535 vcpu->arch.st.steal.version += 2;
1536 vcpu->arch.st.accum_steal = 0;
1537
1538 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1539 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1540 }
1541
1542 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1543 {
1544 bool pr = false;
1545
1546 switch (msr) {
1547 case MSR_EFER:
1548 return set_efer(vcpu, data);
1549 case MSR_K7_HWCR:
1550 data &= ~(u64)0x40; /* ignore flush filter disable */
1551 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1552 data &= ~(u64)0x8; /* ignore TLB cache disable */
1553 if (data != 0) {
1554 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1555 data);
1556 return 1;
1557 }
1558 break;
1559 case MSR_FAM10H_MMIO_CONF_BASE:
1560 if (data != 0) {
1561 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1562 "0x%llx\n", data);
1563 return 1;
1564 }
1565 break;
1566 case MSR_AMD64_NB_CFG:
1567 break;
1568 case MSR_IA32_DEBUGCTLMSR:
1569 if (!data) {
1570 /* We support the non-activated case already */
1571 break;
1572 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1573 /* Values other than LBR and BTF are vendor-specific,
1574 thus reserved and should throw a #GP */
1575 return 1;
1576 }
1577 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1578 __func__, data);
1579 break;
1580 case MSR_IA32_UCODE_REV:
1581 case MSR_IA32_UCODE_WRITE:
1582 case MSR_VM_HSAVE_PA:
1583 case MSR_AMD64_PATCH_LOADER:
1584 break;
1585 case 0x200 ... 0x2ff:
1586 return set_msr_mtrr(vcpu, msr, data);
1587 case MSR_IA32_APICBASE:
1588 kvm_set_apic_base(vcpu, data);
1589 break;
1590 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1591 return kvm_x2apic_msr_write(vcpu, msr, data);
1592 case MSR_IA32_TSCDEADLINE:
1593 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1594 break;
1595 case MSR_IA32_MISC_ENABLE:
1596 vcpu->arch.ia32_misc_enable_msr = data;
1597 break;
1598 case MSR_KVM_WALL_CLOCK_NEW:
1599 case MSR_KVM_WALL_CLOCK:
1600 vcpu->kvm->arch.wall_clock = data;
1601 kvm_write_wall_clock(vcpu->kvm, data);
1602 break;
1603 case MSR_KVM_SYSTEM_TIME_NEW:
1604 case MSR_KVM_SYSTEM_TIME: {
1605 kvmclock_reset(vcpu);
1606
1607 vcpu->arch.time = data;
1608 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1609
1610 /* we verify if the enable bit is set... */
1611 if (!(data & 1))
1612 break;
1613
1614 /* ...but clean it before doing the actual write */
1615 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1616
1617 vcpu->arch.time_page =
1618 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1619
1620 if (is_error_page(vcpu->arch.time_page)) {
1621 kvm_release_page_clean(vcpu->arch.time_page);
1622 vcpu->arch.time_page = NULL;
1623 }
1624 break;
1625 }
1626 case MSR_KVM_ASYNC_PF_EN:
1627 if (kvm_pv_enable_async_pf(vcpu, data))
1628 return 1;
1629 break;
1630 case MSR_KVM_STEAL_TIME:
1631
1632 if (unlikely(!sched_info_on()))
1633 return 1;
1634
1635 if (data & KVM_STEAL_RESERVED_MASK)
1636 return 1;
1637
1638 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1639 data & KVM_STEAL_VALID_BITS))
1640 return 1;
1641
1642 vcpu->arch.st.msr_val = data;
1643
1644 if (!(data & KVM_MSR_ENABLED))
1645 break;
1646
1647 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1648
1649 preempt_disable();
1650 accumulate_steal_time(vcpu);
1651 preempt_enable();
1652
1653 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1654
1655 break;
1656
1657 case MSR_IA32_MCG_CTL:
1658 case MSR_IA32_MCG_STATUS:
1659 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1660 return set_msr_mce(vcpu, msr, data);
1661
1662 /* Performance counters are not protected by a CPUID bit,
1663 * so we should check all of them in the generic path for the sake of
1664 * cross vendor migration.
1665 * Writing a zero into the event select MSRs disables them,
1666 * which we perfectly emulate ;-). Any other value should be at least
1667 * reported, some guests depend on them.
1668 */
1669 case MSR_K7_EVNTSEL0:
1670 case MSR_K7_EVNTSEL1:
1671 case MSR_K7_EVNTSEL2:
1672 case MSR_K7_EVNTSEL3:
1673 if (data != 0)
1674 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1675 "0x%x data 0x%llx\n", msr, data);
1676 break;
1677 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1678 * so we ignore writes to make it happy.
1679 */
1680 case MSR_K7_PERFCTR0:
1681 case MSR_K7_PERFCTR1:
1682 case MSR_K7_PERFCTR2:
1683 case MSR_K7_PERFCTR3:
1684 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1685 "0x%x data 0x%llx\n", msr, data);
1686 break;
1687 case MSR_P6_PERFCTR0:
1688 case MSR_P6_PERFCTR1:
1689 pr = true;
1690 case MSR_P6_EVNTSEL0:
1691 case MSR_P6_EVNTSEL1:
1692 if (kvm_pmu_msr(vcpu, msr))
1693 return kvm_pmu_set_msr(vcpu, msr, data);
1694
1695 if (pr || data != 0)
1696 pr_unimpl(vcpu, "disabled perfctr wrmsr: "
1697 "0x%x data 0x%llx\n", msr, data);
1698 break;
1699 case MSR_K7_CLK_CTL:
1700 /*
1701 * Ignore all writes to this no longer documented MSR.
1702 * Writes are only relevant for old K7 processors,
1703 * all pre-dating SVM, but a recommended workaround from
1704 * AMD for these chips. It is possible to speicify the
1705 * affected processor models on the command line, hence
1706 * the need to ignore the workaround.
1707 */
1708 break;
1709 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1710 if (kvm_hv_msr_partition_wide(msr)) {
1711 int r;
1712 mutex_lock(&vcpu->kvm->lock);
1713 r = set_msr_hyperv_pw(vcpu, msr, data);
1714 mutex_unlock(&vcpu->kvm->lock);
1715 return r;
1716 } else
1717 return set_msr_hyperv(vcpu, msr, data);
1718 break;
1719 case MSR_IA32_BBL_CR_CTL3:
1720 /* Drop writes to this legacy MSR -- see rdmsr
1721 * counterpart for further detail.
1722 */
1723 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1724 break;
1725 case MSR_AMD64_OSVW_ID_LENGTH:
1726 if (!guest_cpuid_has_osvw(vcpu))
1727 return 1;
1728 vcpu->arch.osvw.length = data;
1729 break;
1730 case MSR_AMD64_OSVW_STATUS:
1731 if (!guest_cpuid_has_osvw(vcpu))
1732 return 1;
1733 vcpu->arch.osvw.status = data;
1734 break;
1735 default:
1736 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1737 return xen_hvm_config(vcpu, data);
1738 if (kvm_pmu_msr(vcpu, msr))
1739 return kvm_pmu_set_msr(vcpu, msr, data);
1740 if (!ignore_msrs) {
1741 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1742 msr, data);
1743 return 1;
1744 } else {
1745 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1746 msr, data);
1747 break;
1748 }
1749 }
1750 return 0;
1751 }
1752 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1753
1754
1755 /*
1756 * Reads an msr value (of 'msr_index') into 'pdata'.
1757 * Returns 0 on success, non-0 otherwise.
1758 * Assumes vcpu_load() was already called.
1759 */
1760 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1761 {
1762 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1763 }
1764
1765 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1766 {
1767 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1768
1769 if (!msr_mtrr_valid(msr))
1770 return 1;
1771
1772 if (msr == MSR_MTRRdefType)
1773 *pdata = vcpu->arch.mtrr_state.def_type +
1774 (vcpu->arch.mtrr_state.enabled << 10);
1775 else if (msr == MSR_MTRRfix64K_00000)
1776 *pdata = p[0];
1777 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1778 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1779 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1780 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1781 else if (msr == MSR_IA32_CR_PAT)
1782 *pdata = vcpu->arch.pat;
1783 else { /* Variable MTRRs */
1784 int idx, is_mtrr_mask;
1785 u64 *pt;
1786
1787 idx = (msr - 0x200) / 2;
1788 is_mtrr_mask = msr - 0x200 - 2 * idx;
1789 if (!is_mtrr_mask)
1790 pt =
1791 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1792 else
1793 pt =
1794 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1795 *pdata = *pt;
1796 }
1797
1798 return 0;
1799 }
1800
1801 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1802 {
1803 u64 data;
1804 u64 mcg_cap = vcpu->arch.mcg_cap;
1805 unsigned bank_num = mcg_cap & 0xff;
1806
1807 switch (msr) {
1808 case MSR_IA32_P5_MC_ADDR:
1809 case MSR_IA32_P5_MC_TYPE:
1810 data = 0;
1811 break;
1812 case MSR_IA32_MCG_CAP:
1813 data = vcpu->arch.mcg_cap;
1814 break;
1815 case MSR_IA32_MCG_CTL:
1816 if (!(mcg_cap & MCG_CTL_P))
1817 return 1;
1818 data = vcpu->arch.mcg_ctl;
1819 break;
1820 case MSR_IA32_MCG_STATUS:
1821 data = vcpu->arch.mcg_status;
1822 break;
1823 default:
1824 if (msr >= MSR_IA32_MC0_CTL &&
1825 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1826 u32 offset = msr - MSR_IA32_MC0_CTL;
1827 data = vcpu->arch.mce_banks[offset];
1828 break;
1829 }
1830 return 1;
1831 }
1832 *pdata = data;
1833 return 0;
1834 }
1835
1836 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1837 {
1838 u64 data = 0;
1839 struct kvm *kvm = vcpu->kvm;
1840
1841 switch (msr) {
1842 case HV_X64_MSR_GUEST_OS_ID:
1843 data = kvm->arch.hv_guest_os_id;
1844 break;
1845 case HV_X64_MSR_HYPERCALL:
1846 data = kvm->arch.hv_hypercall;
1847 break;
1848 default:
1849 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1850 return 1;
1851 }
1852
1853 *pdata = data;
1854 return 0;
1855 }
1856
1857 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1858 {
1859 u64 data = 0;
1860
1861 switch (msr) {
1862 case HV_X64_MSR_VP_INDEX: {
1863 int r;
1864 struct kvm_vcpu *v;
1865 kvm_for_each_vcpu(r, v, vcpu->kvm)
1866 if (v == vcpu)
1867 data = r;
1868 break;
1869 }
1870 case HV_X64_MSR_EOI:
1871 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1872 case HV_X64_MSR_ICR:
1873 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1874 case HV_X64_MSR_TPR:
1875 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1876 case HV_X64_MSR_APIC_ASSIST_PAGE:
1877 data = vcpu->arch.hv_vapic;
1878 break;
1879 default:
1880 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1881 return 1;
1882 }
1883 *pdata = data;
1884 return 0;
1885 }
1886
1887 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1888 {
1889 u64 data;
1890
1891 switch (msr) {
1892 case MSR_IA32_PLATFORM_ID:
1893 case MSR_IA32_EBL_CR_POWERON:
1894 case MSR_IA32_DEBUGCTLMSR:
1895 case MSR_IA32_LASTBRANCHFROMIP:
1896 case MSR_IA32_LASTBRANCHTOIP:
1897 case MSR_IA32_LASTINTFROMIP:
1898 case MSR_IA32_LASTINTTOIP:
1899 case MSR_K8_SYSCFG:
1900 case MSR_K7_HWCR:
1901 case MSR_VM_HSAVE_PA:
1902 case MSR_K7_EVNTSEL0:
1903 case MSR_K7_PERFCTR0:
1904 case MSR_K8_INT_PENDING_MSG:
1905 case MSR_AMD64_NB_CFG:
1906 case MSR_FAM10H_MMIO_CONF_BASE:
1907 data = 0;
1908 break;
1909 case MSR_P6_PERFCTR0:
1910 case MSR_P6_PERFCTR1:
1911 case MSR_P6_EVNTSEL0:
1912 case MSR_P6_EVNTSEL1:
1913 if (kvm_pmu_msr(vcpu, msr))
1914 return kvm_pmu_get_msr(vcpu, msr, pdata);
1915 data = 0;
1916 break;
1917 case MSR_IA32_UCODE_REV:
1918 data = 0x100000000ULL;
1919 break;
1920 case MSR_MTRRcap:
1921 data = 0x500 | KVM_NR_VAR_MTRR;
1922 break;
1923 case 0x200 ... 0x2ff:
1924 return get_msr_mtrr(vcpu, msr, pdata);
1925 case 0xcd: /* fsb frequency */
1926 data = 3;
1927 break;
1928 /*
1929 * MSR_EBC_FREQUENCY_ID
1930 * Conservative value valid for even the basic CPU models.
1931 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1932 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1933 * and 266MHz for model 3, or 4. Set Core Clock
1934 * Frequency to System Bus Frequency Ratio to 1 (bits
1935 * 31:24) even though these are only valid for CPU
1936 * models > 2, however guests may end up dividing or
1937 * multiplying by zero otherwise.
1938 */
1939 case MSR_EBC_FREQUENCY_ID:
1940 data = 1 << 24;
1941 break;
1942 case MSR_IA32_APICBASE:
1943 data = kvm_get_apic_base(vcpu);
1944 break;
1945 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1946 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1947 break;
1948 case MSR_IA32_TSCDEADLINE:
1949 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1950 break;
1951 case MSR_IA32_MISC_ENABLE:
1952 data = vcpu->arch.ia32_misc_enable_msr;
1953 break;
1954 case MSR_IA32_PERF_STATUS:
1955 /* TSC increment by tick */
1956 data = 1000ULL;
1957 /* CPU multiplier */
1958 data |= (((uint64_t)4ULL) << 40);
1959 break;
1960 case MSR_EFER:
1961 data = vcpu->arch.efer;
1962 break;
1963 case MSR_KVM_WALL_CLOCK:
1964 case MSR_KVM_WALL_CLOCK_NEW:
1965 data = vcpu->kvm->arch.wall_clock;
1966 break;
1967 case MSR_KVM_SYSTEM_TIME:
1968 case MSR_KVM_SYSTEM_TIME_NEW:
1969 data = vcpu->arch.time;
1970 break;
1971 case MSR_KVM_ASYNC_PF_EN:
1972 data = vcpu->arch.apf.msr_val;
1973 break;
1974 case MSR_KVM_STEAL_TIME:
1975 data = vcpu->arch.st.msr_val;
1976 break;
1977 case MSR_IA32_P5_MC_ADDR:
1978 case MSR_IA32_P5_MC_TYPE:
1979 case MSR_IA32_MCG_CAP:
1980 case MSR_IA32_MCG_CTL:
1981 case MSR_IA32_MCG_STATUS:
1982 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1983 return get_msr_mce(vcpu, msr, pdata);
1984 case MSR_K7_CLK_CTL:
1985 /*
1986 * Provide expected ramp-up count for K7. All other
1987 * are set to zero, indicating minimum divisors for
1988 * every field.
1989 *
1990 * This prevents guest kernels on AMD host with CPU
1991 * type 6, model 8 and higher from exploding due to
1992 * the rdmsr failing.
1993 */
1994 data = 0x20000000;
1995 break;
1996 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1997 if (kvm_hv_msr_partition_wide(msr)) {
1998 int r;
1999 mutex_lock(&vcpu->kvm->lock);
2000 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2001 mutex_unlock(&vcpu->kvm->lock);
2002 return r;
2003 } else
2004 return get_msr_hyperv(vcpu, msr, pdata);
2005 break;
2006 case MSR_IA32_BBL_CR_CTL3:
2007 /* This legacy MSR exists but isn't fully documented in current
2008 * silicon. It is however accessed by winxp in very narrow
2009 * scenarios where it sets bit #19, itself documented as
2010 * a "reserved" bit. Best effort attempt to source coherent
2011 * read data here should the balance of the register be
2012 * interpreted by the guest:
2013 *
2014 * L2 cache control register 3: 64GB range, 256KB size,
2015 * enabled, latency 0x1, configured
2016 */
2017 data = 0xbe702111;
2018 break;
2019 case MSR_AMD64_OSVW_ID_LENGTH:
2020 if (!guest_cpuid_has_osvw(vcpu))
2021 return 1;
2022 data = vcpu->arch.osvw.length;
2023 break;
2024 case MSR_AMD64_OSVW_STATUS:
2025 if (!guest_cpuid_has_osvw(vcpu))
2026 return 1;
2027 data = vcpu->arch.osvw.status;
2028 break;
2029 default:
2030 if (kvm_pmu_msr(vcpu, msr))
2031 return kvm_pmu_get_msr(vcpu, msr, pdata);
2032 if (!ignore_msrs) {
2033 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2034 return 1;
2035 } else {
2036 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2037 data = 0;
2038 }
2039 break;
2040 }
2041 *pdata = data;
2042 return 0;
2043 }
2044 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2045
2046 /*
2047 * Read or write a bunch of msrs. All parameters are kernel addresses.
2048 *
2049 * @return number of msrs set successfully.
2050 */
2051 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2052 struct kvm_msr_entry *entries,
2053 int (*do_msr)(struct kvm_vcpu *vcpu,
2054 unsigned index, u64 *data))
2055 {
2056 int i, idx;
2057
2058 idx = srcu_read_lock(&vcpu->kvm->srcu);
2059 for (i = 0; i < msrs->nmsrs; ++i)
2060 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2061 break;
2062 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2063
2064 return i;
2065 }
2066
2067 /*
2068 * Read or write a bunch of msrs. Parameters are user addresses.
2069 *
2070 * @return number of msrs set successfully.
2071 */
2072 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2073 int (*do_msr)(struct kvm_vcpu *vcpu,
2074 unsigned index, u64 *data),
2075 int writeback)
2076 {
2077 struct kvm_msrs msrs;
2078 struct kvm_msr_entry *entries;
2079 int r, n;
2080 unsigned size;
2081
2082 r = -EFAULT;
2083 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2084 goto out;
2085
2086 r = -E2BIG;
2087 if (msrs.nmsrs >= MAX_IO_MSRS)
2088 goto out;
2089
2090 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2091 entries = memdup_user(user_msrs->entries, size);
2092 if (IS_ERR(entries)) {
2093 r = PTR_ERR(entries);
2094 goto out;
2095 }
2096
2097 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2098 if (r < 0)
2099 goto out_free;
2100
2101 r = -EFAULT;
2102 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2103 goto out_free;
2104
2105 r = n;
2106
2107 out_free:
2108 kfree(entries);
2109 out:
2110 return r;
2111 }
2112
2113 int kvm_dev_ioctl_check_extension(long ext)
2114 {
2115 int r;
2116
2117 switch (ext) {
2118 case KVM_CAP_IRQCHIP:
2119 case KVM_CAP_HLT:
2120 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2121 case KVM_CAP_SET_TSS_ADDR:
2122 case KVM_CAP_EXT_CPUID:
2123 case KVM_CAP_CLOCKSOURCE:
2124 case KVM_CAP_PIT:
2125 case KVM_CAP_NOP_IO_DELAY:
2126 case KVM_CAP_MP_STATE:
2127 case KVM_CAP_SYNC_MMU:
2128 case KVM_CAP_USER_NMI:
2129 case KVM_CAP_REINJECT_CONTROL:
2130 case KVM_CAP_IRQ_INJECT_STATUS:
2131 case KVM_CAP_ASSIGN_DEV_IRQ:
2132 case KVM_CAP_IRQFD:
2133 case KVM_CAP_IOEVENTFD:
2134 case KVM_CAP_PIT2:
2135 case KVM_CAP_PIT_STATE2:
2136 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2137 case KVM_CAP_XEN_HVM:
2138 case KVM_CAP_ADJUST_CLOCK:
2139 case KVM_CAP_VCPU_EVENTS:
2140 case KVM_CAP_HYPERV:
2141 case KVM_CAP_HYPERV_VAPIC:
2142 case KVM_CAP_HYPERV_SPIN:
2143 case KVM_CAP_PCI_SEGMENT:
2144 case KVM_CAP_DEBUGREGS:
2145 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2146 case KVM_CAP_XSAVE:
2147 case KVM_CAP_ASYNC_PF:
2148 case KVM_CAP_GET_TSC_KHZ:
2149 case KVM_CAP_PCI_2_3:
2150 case KVM_CAP_KVMCLOCK_CTRL:
2151 r = 1;
2152 break;
2153 case KVM_CAP_COALESCED_MMIO:
2154 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2155 break;
2156 case KVM_CAP_VAPIC:
2157 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2158 break;
2159 case KVM_CAP_NR_VCPUS:
2160 r = KVM_SOFT_MAX_VCPUS;
2161 break;
2162 case KVM_CAP_MAX_VCPUS:
2163 r = KVM_MAX_VCPUS;
2164 break;
2165 case KVM_CAP_NR_MEMSLOTS:
2166 r = KVM_MEMORY_SLOTS;
2167 break;
2168 case KVM_CAP_PV_MMU: /* obsolete */
2169 r = 0;
2170 break;
2171 case KVM_CAP_IOMMU:
2172 r = iommu_present(&pci_bus_type);
2173 break;
2174 case KVM_CAP_MCE:
2175 r = KVM_MAX_MCE_BANKS;
2176 break;
2177 case KVM_CAP_XCRS:
2178 r = cpu_has_xsave;
2179 break;
2180 case KVM_CAP_TSC_CONTROL:
2181 r = kvm_has_tsc_control;
2182 break;
2183 case KVM_CAP_TSC_DEADLINE_TIMER:
2184 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2185 break;
2186 default:
2187 r = 0;
2188 break;
2189 }
2190 return r;
2191
2192 }
2193
2194 long kvm_arch_dev_ioctl(struct file *filp,
2195 unsigned int ioctl, unsigned long arg)
2196 {
2197 void __user *argp = (void __user *)arg;
2198 long r;
2199
2200 switch (ioctl) {
2201 case KVM_GET_MSR_INDEX_LIST: {
2202 struct kvm_msr_list __user *user_msr_list = argp;
2203 struct kvm_msr_list msr_list;
2204 unsigned n;
2205
2206 r = -EFAULT;
2207 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2208 goto out;
2209 n = msr_list.nmsrs;
2210 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2211 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2212 goto out;
2213 r = -E2BIG;
2214 if (n < msr_list.nmsrs)
2215 goto out;
2216 r = -EFAULT;
2217 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2218 num_msrs_to_save * sizeof(u32)))
2219 goto out;
2220 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2221 &emulated_msrs,
2222 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2223 goto out;
2224 r = 0;
2225 break;
2226 }
2227 case KVM_GET_SUPPORTED_CPUID: {
2228 struct kvm_cpuid2 __user *cpuid_arg = argp;
2229 struct kvm_cpuid2 cpuid;
2230
2231 r = -EFAULT;
2232 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2233 goto out;
2234 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2235 cpuid_arg->entries);
2236 if (r)
2237 goto out;
2238
2239 r = -EFAULT;
2240 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2241 goto out;
2242 r = 0;
2243 break;
2244 }
2245 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2246 u64 mce_cap;
2247
2248 mce_cap = KVM_MCE_CAP_SUPPORTED;
2249 r = -EFAULT;
2250 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2251 goto out;
2252 r = 0;
2253 break;
2254 }
2255 default:
2256 r = -EINVAL;
2257 }
2258 out:
2259 return r;
2260 }
2261
2262 static void wbinvd_ipi(void *garbage)
2263 {
2264 wbinvd();
2265 }
2266
2267 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2268 {
2269 return vcpu->kvm->arch.iommu_domain &&
2270 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2271 }
2272
2273 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2274 {
2275 /* Address WBINVD may be executed by guest */
2276 if (need_emulate_wbinvd(vcpu)) {
2277 if (kvm_x86_ops->has_wbinvd_exit())
2278 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2279 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2280 smp_call_function_single(vcpu->cpu,
2281 wbinvd_ipi, NULL, 1);
2282 }
2283
2284 kvm_x86_ops->vcpu_load(vcpu, cpu);
2285
2286 /* Apply any externally detected TSC adjustments (due to suspend) */
2287 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2288 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2289 vcpu->arch.tsc_offset_adjustment = 0;
2290 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2291 }
2292
2293 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2294 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2295 native_read_tsc() - vcpu->arch.last_host_tsc;
2296 if (tsc_delta < 0)
2297 mark_tsc_unstable("KVM discovered backwards TSC");
2298 if (check_tsc_unstable()) {
2299 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2300 vcpu->arch.last_guest_tsc);
2301 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2302 vcpu->arch.tsc_catchup = 1;
2303 }
2304 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2305 if (vcpu->cpu != cpu)
2306 kvm_migrate_timers(vcpu);
2307 vcpu->cpu = cpu;
2308 }
2309
2310 accumulate_steal_time(vcpu);
2311 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2312 }
2313
2314 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2315 {
2316 kvm_x86_ops->vcpu_put(vcpu);
2317 kvm_put_guest_fpu(vcpu);
2318 vcpu->arch.last_host_tsc = native_read_tsc();
2319 }
2320
2321 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2322 struct kvm_lapic_state *s)
2323 {
2324 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2325
2326 return 0;
2327 }
2328
2329 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2330 struct kvm_lapic_state *s)
2331 {
2332 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2333 kvm_apic_post_state_restore(vcpu);
2334 update_cr8_intercept(vcpu);
2335
2336 return 0;
2337 }
2338
2339 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2340 struct kvm_interrupt *irq)
2341 {
2342 if (irq->irq < 0 || irq->irq >= 256)
2343 return -EINVAL;
2344 if (irqchip_in_kernel(vcpu->kvm))
2345 return -ENXIO;
2346
2347 kvm_queue_interrupt(vcpu, irq->irq, false);
2348 kvm_make_request(KVM_REQ_EVENT, vcpu);
2349
2350 return 0;
2351 }
2352
2353 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2354 {
2355 kvm_inject_nmi(vcpu);
2356
2357 return 0;
2358 }
2359
2360 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2361 struct kvm_tpr_access_ctl *tac)
2362 {
2363 if (tac->flags)
2364 return -EINVAL;
2365 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2366 return 0;
2367 }
2368
2369 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2370 u64 mcg_cap)
2371 {
2372 int r;
2373 unsigned bank_num = mcg_cap & 0xff, bank;
2374
2375 r = -EINVAL;
2376 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2377 goto out;
2378 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2379 goto out;
2380 r = 0;
2381 vcpu->arch.mcg_cap = mcg_cap;
2382 /* Init IA32_MCG_CTL to all 1s */
2383 if (mcg_cap & MCG_CTL_P)
2384 vcpu->arch.mcg_ctl = ~(u64)0;
2385 /* Init IA32_MCi_CTL to all 1s */
2386 for (bank = 0; bank < bank_num; bank++)
2387 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2388 out:
2389 return r;
2390 }
2391
2392 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2393 struct kvm_x86_mce *mce)
2394 {
2395 u64 mcg_cap = vcpu->arch.mcg_cap;
2396 unsigned bank_num = mcg_cap & 0xff;
2397 u64 *banks = vcpu->arch.mce_banks;
2398
2399 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2400 return -EINVAL;
2401 /*
2402 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2403 * reporting is disabled
2404 */
2405 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2406 vcpu->arch.mcg_ctl != ~(u64)0)
2407 return 0;
2408 banks += 4 * mce->bank;
2409 /*
2410 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2411 * reporting is disabled for the bank
2412 */
2413 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2414 return 0;
2415 if (mce->status & MCI_STATUS_UC) {
2416 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2417 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2418 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2419 return 0;
2420 }
2421 if (banks[1] & MCI_STATUS_VAL)
2422 mce->status |= MCI_STATUS_OVER;
2423 banks[2] = mce->addr;
2424 banks[3] = mce->misc;
2425 vcpu->arch.mcg_status = mce->mcg_status;
2426 banks[1] = mce->status;
2427 kvm_queue_exception(vcpu, MC_VECTOR);
2428 } else if (!(banks[1] & MCI_STATUS_VAL)
2429 || !(banks[1] & MCI_STATUS_UC)) {
2430 if (banks[1] & MCI_STATUS_VAL)
2431 mce->status |= MCI_STATUS_OVER;
2432 banks[2] = mce->addr;
2433 banks[3] = mce->misc;
2434 banks[1] = mce->status;
2435 } else
2436 banks[1] |= MCI_STATUS_OVER;
2437 return 0;
2438 }
2439
2440 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2441 struct kvm_vcpu_events *events)
2442 {
2443 process_nmi(vcpu);
2444 events->exception.injected =
2445 vcpu->arch.exception.pending &&
2446 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2447 events->exception.nr = vcpu->arch.exception.nr;
2448 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2449 events->exception.pad = 0;
2450 events->exception.error_code = vcpu->arch.exception.error_code;
2451
2452 events->interrupt.injected =
2453 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2454 events->interrupt.nr = vcpu->arch.interrupt.nr;
2455 events->interrupt.soft = 0;
2456 events->interrupt.shadow =
2457 kvm_x86_ops->get_interrupt_shadow(vcpu,
2458 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2459
2460 events->nmi.injected = vcpu->arch.nmi_injected;
2461 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2462 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2463 events->nmi.pad = 0;
2464
2465 events->sipi_vector = vcpu->arch.sipi_vector;
2466
2467 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2468 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2469 | KVM_VCPUEVENT_VALID_SHADOW);
2470 memset(&events->reserved, 0, sizeof(events->reserved));
2471 }
2472
2473 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2474 struct kvm_vcpu_events *events)
2475 {
2476 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2477 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2478 | KVM_VCPUEVENT_VALID_SHADOW))
2479 return -EINVAL;
2480
2481 process_nmi(vcpu);
2482 vcpu->arch.exception.pending = events->exception.injected;
2483 vcpu->arch.exception.nr = events->exception.nr;
2484 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2485 vcpu->arch.exception.error_code = events->exception.error_code;
2486
2487 vcpu->arch.interrupt.pending = events->interrupt.injected;
2488 vcpu->arch.interrupt.nr = events->interrupt.nr;
2489 vcpu->arch.interrupt.soft = events->interrupt.soft;
2490 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2491 kvm_x86_ops->set_interrupt_shadow(vcpu,
2492 events->interrupt.shadow);
2493
2494 vcpu->arch.nmi_injected = events->nmi.injected;
2495 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2496 vcpu->arch.nmi_pending = events->nmi.pending;
2497 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2498
2499 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2500 vcpu->arch.sipi_vector = events->sipi_vector;
2501
2502 kvm_make_request(KVM_REQ_EVENT, vcpu);
2503
2504 return 0;
2505 }
2506
2507 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2508 struct kvm_debugregs *dbgregs)
2509 {
2510 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2511 dbgregs->dr6 = vcpu->arch.dr6;
2512 dbgregs->dr7 = vcpu->arch.dr7;
2513 dbgregs->flags = 0;
2514 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2515 }
2516
2517 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2518 struct kvm_debugregs *dbgregs)
2519 {
2520 if (dbgregs->flags)
2521 return -EINVAL;
2522
2523 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2524 vcpu->arch.dr6 = dbgregs->dr6;
2525 vcpu->arch.dr7 = dbgregs->dr7;
2526
2527 return 0;
2528 }
2529
2530 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2531 struct kvm_xsave *guest_xsave)
2532 {
2533 if (cpu_has_xsave)
2534 memcpy(guest_xsave->region,
2535 &vcpu->arch.guest_fpu.state->xsave,
2536 xstate_size);
2537 else {
2538 memcpy(guest_xsave->region,
2539 &vcpu->arch.guest_fpu.state->fxsave,
2540 sizeof(struct i387_fxsave_struct));
2541 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2542 XSTATE_FPSSE;
2543 }
2544 }
2545
2546 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2547 struct kvm_xsave *guest_xsave)
2548 {
2549 u64 xstate_bv =
2550 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2551
2552 if (cpu_has_xsave)
2553 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2554 guest_xsave->region, xstate_size);
2555 else {
2556 if (xstate_bv & ~XSTATE_FPSSE)
2557 return -EINVAL;
2558 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2559 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2560 }
2561 return 0;
2562 }
2563
2564 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2565 struct kvm_xcrs *guest_xcrs)
2566 {
2567 if (!cpu_has_xsave) {
2568 guest_xcrs->nr_xcrs = 0;
2569 return;
2570 }
2571
2572 guest_xcrs->nr_xcrs = 1;
2573 guest_xcrs->flags = 0;
2574 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2575 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2576 }
2577
2578 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2579 struct kvm_xcrs *guest_xcrs)
2580 {
2581 int i, r = 0;
2582
2583 if (!cpu_has_xsave)
2584 return -EINVAL;
2585
2586 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2587 return -EINVAL;
2588
2589 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2590 /* Only support XCR0 currently */
2591 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2592 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2593 guest_xcrs->xcrs[0].value);
2594 break;
2595 }
2596 if (r)
2597 r = -EINVAL;
2598 return r;
2599 }
2600
2601 /*
2602 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2603 * stopped by the hypervisor. This function will be called from the host only.
2604 * EINVAL is returned when the host attempts to set the flag for a guest that
2605 * does not support pv clocks.
2606 */
2607 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2608 {
2609 struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2610 if (!vcpu->arch.time_page)
2611 return -EINVAL;
2612 src->flags |= PVCLOCK_GUEST_STOPPED;
2613 mark_page_dirty(vcpu->kvm, vcpu->arch.time >> PAGE_SHIFT);
2614 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2615 return 0;
2616 }
2617
2618 long kvm_arch_vcpu_ioctl(struct file *filp,
2619 unsigned int ioctl, unsigned long arg)
2620 {
2621 struct kvm_vcpu *vcpu = filp->private_data;
2622 void __user *argp = (void __user *)arg;
2623 int r;
2624 union {
2625 struct kvm_lapic_state *lapic;
2626 struct kvm_xsave *xsave;
2627 struct kvm_xcrs *xcrs;
2628 void *buffer;
2629 } u;
2630
2631 u.buffer = NULL;
2632 switch (ioctl) {
2633 case KVM_GET_LAPIC: {
2634 r = -EINVAL;
2635 if (!vcpu->arch.apic)
2636 goto out;
2637 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2638
2639 r = -ENOMEM;
2640 if (!u.lapic)
2641 goto out;
2642 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2643 if (r)
2644 goto out;
2645 r = -EFAULT;
2646 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2647 goto out;
2648 r = 0;
2649 break;
2650 }
2651 case KVM_SET_LAPIC: {
2652 r = -EINVAL;
2653 if (!vcpu->arch.apic)
2654 goto out;
2655 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2656 if (IS_ERR(u.lapic)) {
2657 r = PTR_ERR(u.lapic);
2658 goto out;
2659 }
2660
2661 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2662 if (r)
2663 goto out;
2664 r = 0;
2665 break;
2666 }
2667 case KVM_INTERRUPT: {
2668 struct kvm_interrupt irq;
2669
2670 r = -EFAULT;
2671 if (copy_from_user(&irq, argp, sizeof irq))
2672 goto out;
2673 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2674 if (r)
2675 goto out;
2676 r = 0;
2677 break;
2678 }
2679 case KVM_NMI: {
2680 r = kvm_vcpu_ioctl_nmi(vcpu);
2681 if (r)
2682 goto out;
2683 r = 0;
2684 break;
2685 }
2686 case KVM_SET_CPUID: {
2687 struct kvm_cpuid __user *cpuid_arg = argp;
2688 struct kvm_cpuid cpuid;
2689
2690 r = -EFAULT;
2691 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2692 goto out;
2693 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2694 if (r)
2695 goto out;
2696 break;
2697 }
2698 case KVM_SET_CPUID2: {
2699 struct kvm_cpuid2 __user *cpuid_arg = argp;
2700 struct kvm_cpuid2 cpuid;
2701
2702 r = -EFAULT;
2703 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2704 goto out;
2705 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2706 cpuid_arg->entries);
2707 if (r)
2708 goto out;
2709 break;
2710 }
2711 case KVM_GET_CPUID2: {
2712 struct kvm_cpuid2 __user *cpuid_arg = argp;
2713 struct kvm_cpuid2 cpuid;
2714
2715 r = -EFAULT;
2716 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2717 goto out;
2718 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2719 cpuid_arg->entries);
2720 if (r)
2721 goto out;
2722 r = -EFAULT;
2723 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2724 goto out;
2725 r = 0;
2726 break;
2727 }
2728 case KVM_GET_MSRS:
2729 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2730 break;
2731 case KVM_SET_MSRS:
2732 r = msr_io(vcpu, argp, do_set_msr, 0);
2733 break;
2734 case KVM_TPR_ACCESS_REPORTING: {
2735 struct kvm_tpr_access_ctl tac;
2736
2737 r = -EFAULT;
2738 if (copy_from_user(&tac, argp, sizeof tac))
2739 goto out;
2740 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2741 if (r)
2742 goto out;
2743 r = -EFAULT;
2744 if (copy_to_user(argp, &tac, sizeof tac))
2745 goto out;
2746 r = 0;
2747 break;
2748 };
2749 case KVM_SET_VAPIC_ADDR: {
2750 struct kvm_vapic_addr va;
2751
2752 r = -EINVAL;
2753 if (!irqchip_in_kernel(vcpu->kvm))
2754 goto out;
2755 r = -EFAULT;
2756 if (copy_from_user(&va, argp, sizeof va))
2757 goto out;
2758 r = 0;
2759 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2760 break;
2761 }
2762 case KVM_X86_SETUP_MCE: {
2763 u64 mcg_cap;
2764
2765 r = -EFAULT;
2766 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2767 goto out;
2768 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2769 break;
2770 }
2771 case KVM_X86_SET_MCE: {
2772 struct kvm_x86_mce mce;
2773
2774 r = -EFAULT;
2775 if (copy_from_user(&mce, argp, sizeof mce))
2776 goto out;
2777 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2778 break;
2779 }
2780 case KVM_GET_VCPU_EVENTS: {
2781 struct kvm_vcpu_events events;
2782
2783 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2784
2785 r = -EFAULT;
2786 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2787 break;
2788 r = 0;
2789 break;
2790 }
2791 case KVM_SET_VCPU_EVENTS: {
2792 struct kvm_vcpu_events events;
2793
2794 r = -EFAULT;
2795 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2796 break;
2797
2798 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2799 break;
2800 }
2801 case KVM_GET_DEBUGREGS: {
2802 struct kvm_debugregs dbgregs;
2803
2804 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2805
2806 r = -EFAULT;
2807 if (copy_to_user(argp, &dbgregs,
2808 sizeof(struct kvm_debugregs)))
2809 break;
2810 r = 0;
2811 break;
2812 }
2813 case KVM_SET_DEBUGREGS: {
2814 struct kvm_debugregs dbgregs;
2815
2816 r = -EFAULT;
2817 if (copy_from_user(&dbgregs, argp,
2818 sizeof(struct kvm_debugregs)))
2819 break;
2820
2821 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2822 break;
2823 }
2824 case KVM_GET_XSAVE: {
2825 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2826 r = -ENOMEM;
2827 if (!u.xsave)
2828 break;
2829
2830 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2831
2832 r = -EFAULT;
2833 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2834 break;
2835 r = 0;
2836 break;
2837 }
2838 case KVM_SET_XSAVE: {
2839 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2840 if (IS_ERR(u.xsave)) {
2841 r = PTR_ERR(u.xsave);
2842 goto out;
2843 }
2844
2845 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2846 break;
2847 }
2848 case KVM_GET_XCRS: {
2849 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2850 r = -ENOMEM;
2851 if (!u.xcrs)
2852 break;
2853
2854 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2855
2856 r = -EFAULT;
2857 if (copy_to_user(argp, u.xcrs,
2858 sizeof(struct kvm_xcrs)))
2859 break;
2860 r = 0;
2861 break;
2862 }
2863 case KVM_SET_XCRS: {
2864 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2865 if (IS_ERR(u.xcrs)) {
2866 r = PTR_ERR(u.xcrs);
2867 goto out;
2868 }
2869
2870 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2871 break;
2872 }
2873 case KVM_SET_TSC_KHZ: {
2874 u32 user_tsc_khz;
2875
2876 r = -EINVAL;
2877 user_tsc_khz = (u32)arg;
2878
2879 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2880 goto out;
2881
2882 if (user_tsc_khz == 0)
2883 user_tsc_khz = tsc_khz;
2884
2885 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2886
2887 r = 0;
2888 goto out;
2889 }
2890 case KVM_GET_TSC_KHZ: {
2891 r = vcpu->arch.virtual_tsc_khz;
2892 goto out;
2893 }
2894 case KVM_KVMCLOCK_CTRL: {
2895 r = kvm_set_guest_paused(vcpu);
2896 goto out;
2897 }
2898 default:
2899 r = -EINVAL;
2900 }
2901 out:
2902 kfree(u.buffer);
2903 return r;
2904 }
2905
2906 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2907 {
2908 return VM_FAULT_SIGBUS;
2909 }
2910
2911 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2912 {
2913 int ret;
2914
2915 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2916 return -1;
2917 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2918 return ret;
2919 }
2920
2921 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2922 u64 ident_addr)
2923 {
2924 kvm->arch.ept_identity_map_addr = ident_addr;
2925 return 0;
2926 }
2927
2928 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2929 u32 kvm_nr_mmu_pages)
2930 {
2931 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2932 return -EINVAL;
2933
2934 mutex_lock(&kvm->slots_lock);
2935 spin_lock(&kvm->mmu_lock);
2936
2937 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2938 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2939
2940 spin_unlock(&kvm->mmu_lock);
2941 mutex_unlock(&kvm->slots_lock);
2942 return 0;
2943 }
2944
2945 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2946 {
2947 return kvm->arch.n_max_mmu_pages;
2948 }
2949
2950 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2951 {
2952 int r;
2953
2954 r = 0;
2955 switch (chip->chip_id) {
2956 case KVM_IRQCHIP_PIC_MASTER:
2957 memcpy(&chip->chip.pic,
2958 &pic_irqchip(kvm)->pics[0],
2959 sizeof(struct kvm_pic_state));
2960 break;
2961 case KVM_IRQCHIP_PIC_SLAVE:
2962 memcpy(&chip->chip.pic,
2963 &pic_irqchip(kvm)->pics[1],
2964 sizeof(struct kvm_pic_state));
2965 break;
2966 case KVM_IRQCHIP_IOAPIC:
2967 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2968 break;
2969 default:
2970 r = -EINVAL;
2971 break;
2972 }
2973 return r;
2974 }
2975
2976 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2977 {
2978 int r;
2979
2980 r = 0;
2981 switch (chip->chip_id) {
2982 case KVM_IRQCHIP_PIC_MASTER:
2983 spin_lock(&pic_irqchip(kvm)->lock);
2984 memcpy(&pic_irqchip(kvm)->pics[0],
2985 &chip->chip.pic,
2986 sizeof(struct kvm_pic_state));
2987 spin_unlock(&pic_irqchip(kvm)->lock);
2988 break;
2989 case KVM_IRQCHIP_PIC_SLAVE:
2990 spin_lock(&pic_irqchip(kvm)->lock);
2991 memcpy(&pic_irqchip(kvm)->pics[1],
2992 &chip->chip.pic,
2993 sizeof(struct kvm_pic_state));
2994 spin_unlock(&pic_irqchip(kvm)->lock);
2995 break;
2996 case KVM_IRQCHIP_IOAPIC:
2997 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
2998 break;
2999 default:
3000 r = -EINVAL;
3001 break;
3002 }
3003 kvm_pic_update_irq(pic_irqchip(kvm));
3004 return r;
3005 }
3006
3007 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3008 {
3009 int r = 0;
3010
3011 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3012 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3013 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3014 return r;
3015 }
3016
3017 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3018 {
3019 int r = 0;
3020
3021 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3022 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3023 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3024 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3025 return r;
3026 }
3027
3028 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3029 {
3030 int r = 0;
3031
3032 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3033 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3034 sizeof(ps->channels));
3035 ps->flags = kvm->arch.vpit->pit_state.flags;
3036 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3037 memset(&ps->reserved, 0, sizeof(ps->reserved));
3038 return r;
3039 }
3040
3041 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3042 {
3043 int r = 0, start = 0;
3044 u32 prev_legacy, cur_legacy;
3045 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3046 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3047 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3048 if (!prev_legacy && cur_legacy)
3049 start = 1;
3050 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3051 sizeof(kvm->arch.vpit->pit_state.channels));
3052 kvm->arch.vpit->pit_state.flags = ps->flags;
3053 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3054 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3055 return r;
3056 }
3057
3058 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3059 struct kvm_reinject_control *control)
3060 {
3061 if (!kvm->arch.vpit)
3062 return -ENXIO;
3063 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3064 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3065 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3066 return 0;
3067 }
3068
3069 /**
3070 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3071 * @kvm: kvm instance
3072 * @log: slot id and address to which we copy the log
3073 *
3074 * We need to keep it in mind that VCPU threads can write to the bitmap
3075 * concurrently. So, to avoid losing data, we keep the following order for
3076 * each bit:
3077 *
3078 * 1. Take a snapshot of the bit and clear it if needed.
3079 * 2. Write protect the corresponding page.
3080 * 3. Flush TLB's if needed.
3081 * 4. Copy the snapshot to the userspace.
3082 *
3083 * Between 2 and 3, the guest may write to the page using the remaining TLB
3084 * entry. This is not a problem because the page will be reported dirty at
3085 * step 4 using the snapshot taken before and step 3 ensures that successive
3086 * writes will be logged for the next call.
3087 */
3088 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3089 {
3090 int r;
3091 struct kvm_memory_slot *memslot;
3092 unsigned long n, i;
3093 unsigned long *dirty_bitmap;
3094 unsigned long *dirty_bitmap_buffer;
3095 bool is_dirty = false;
3096
3097 mutex_lock(&kvm->slots_lock);
3098
3099 r = -EINVAL;
3100 if (log->slot >= KVM_MEMORY_SLOTS)
3101 goto out;
3102
3103 memslot = id_to_memslot(kvm->memslots, log->slot);
3104
3105 dirty_bitmap = memslot->dirty_bitmap;
3106 r = -ENOENT;
3107 if (!dirty_bitmap)
3108 goto out;
3109
3110 n = kvm_dirty_bitmap_bytes(memslot);
3111
3112 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3113 memset(dirty_bitmap_buffer, 0, n);
3114
3115 spin_lock(&kvm->mmu_lock);
3116
3117 for (i = 0; i < n / sizeof(long); i++) {
3118 unsigned long mask;
3119 gfn_t offset;
3120
3121 if (!dirty_bitmap[i])
3122 continue;
3123
3124 is_dirty = true;
3125
3126 mask = xchg(&dirty_bitmap[i], 0);
3127 dirty_bitmap_buffer[i] = mask;
3128
3129 offset = i * BITS_PER_LONG;
3130 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3131 }
3132 if (is_dirty)
3133 kvm_flush_remote_tlbs(kvm);
3134
3135 spin_unlock(&kvm->mmu_lock);
3136
3137 r = -EFAULT;
3138 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3139 goto out;
3140
3141 r = 0;
3142 out:
3143 mutex_unlock(&kvm->slots_lock);
3144 return r;
3145 }
3146
3147 long kvm_arch_vm_ioctl(struct file *filp,
3148 unsigned int ioctl, unsigned long arg)
3149 {
3150 struct kvm *kvm = filp->private_data;
3151 void __user *argp = (void __user *)arg;
3152 int r = -ENOTTY;
3153 /*
3154 * This union makes it completely explicit to gcc-3.x
3155 * that these two variables' stack usage should be
3156 * combined, not added together.
3157 */
3158 union {
3159 struct kvm_pit_state ps;
3160 struct kvm_pit_state2 ps2;
3161 struct kvm_pit_config pit_config;
3162 } u;
3163
3164 switch (ioctl) {
3165 case KVM_SET_TSS_ADDR:
3166 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3167 if (r < 0)
3168 goto out;
3169 break;
3170 case KVM_SET_IDENTITY_MAP_ADDR: {
3171 u64 ident_addr;
3172
3173 r = -EFAULT;
3174 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3175 goto out;
3176 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3177 if (r < 0)
3178 goto out;
3179 break;
3180 }
3181 case KVM_SET_NR_MMU_PAGES:
3182 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3183 if (r)
3184 goto out;
3185 break;
3186 case KVM_GET_NR_MMU_PAGES:
3187 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3188 break;
3189 case KVM_CREATE_IRQCHIP: {
3190 struct kvm_pic *vpic;
3191
3192 mutex_lock(&kvm->lock);
3193 r = -EEXIST;
3194 if (kvm->arch.vpic)
3195 goto create_irqchip_unlock;
3196 r = -EINVAL;
3197 if (atomic_read(&kvm->online_vcpus))
3198 goto create_irqchip_unlock;
3199 r = -ENOMEM;
3200 vpic = kvm_create_pic(kvm);
3201 if (vpic) {
3202 r = kvm_ioapic_init(kvm);
3203 if (r) {
3204 mutex_lock(&kvm->slots_lock);
3205 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3206 &vpic->dev_master);
3207 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3208 &vpic->dev_slave);
3209 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3210 &vpic->dev_eclr);
3211 mutex_unlock(&kvm->slots_lock);
3212 kfree(vpic);
3213 goto create_irqchip_unlock;
3214 }
3215 } else
3216 goto create_irqchip_unlock;
3217 smp_wmb();
3218 kvm->arch.vpic = vpic;
3219 smp_wmb();
3220 r = kvm_setup_default_irq_routing(kvm);
3221 if (r) {
3222 mutex_lock(&kvm->slots_lock);
3223 mutex_lock(&kvm->irq_lock);
3224 kvm_ioapic_destroy(kvm);
3225 kvm_destroy_pic(kvm);
3226 mutex_unlock(&kvm->irq_lock);
3227 mutex_unlock(&kvm->slots_lock);
3228 }
3229 create_irqchip_unlock:
3230 mutex_unlock(&kvm->lock);
3231 break;
3232 }
3233 case KVM_CREATE_PIT:
3234 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3235 goto create_pit;
3236 case KVM_CREATE_PIT2:
3237 r = -EFAULT;
3238 if (copy_from_user(&u.pit_config, argp,
3239 sizeof(struct kvm_pit_config)))
3240 goto out;
3241 create_pit:
3242 mutex_lock(&kvm->slots_lock);
3243 r = -EEXIST;
3244 if (kvm->arch.vpit)
3245 goto create_pit_unlock;
3246 r = -ENOMEM;
3247 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3248 if (kvm->arch.vpit)
3249 r = 0;
3250 create_pit_unlock:
3251 mutex_unlock(&kvm->slots_lock);
3252 break;
3253 case KVM_IRQ_LINE_STATUS:
3254 case KVM_IRQ_LINE: {
3255 struct kvm_irq_level irq_event;
3256
3257 r = -EFAULT;
3258 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3259 goto out;
3260 r = -ENXIO;
3261 if (irqchip_in_kernel(kvm)) {
3262 __s32 status;
3263 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3264 irq_event.irq, irq_event.level);
3265 if (ioctl == KVM_IRQ_LINE_STATUS) {
3266 r = -EFAULT;
3267 irq_event.status = status;
3268 if (copy_to_user(argp, &irq_event,
3269 sizeof irq_event))
3270 goto out;
3271 }
3272 r = 0;
3273 }
3274 break;
3275 }
3276 case KVM_GET_IRQCHIP: {
3277 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3278 struct kvm_irqchip *chip;
3279
3280 chip = memdup_user(argp, sizeof(*chip));
3281 if (IS_ERR(chip)) {
3282 r = PTR_ERR(chip);
3283 goto out;
3284 }
3285
3286 r = -ENXIO;
3287 if (!irqchip_in_kernel(kvm))
3288 goto get_irqchip_out;
3289 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3290 if (r)
3291 goto get_irqchip_out;
3292 r = -EFAULT;
3293 if (copy_to_user(argp, chip, sizeof *chip))
3294 goto get_irqchip_out;
3295 r = 0;
3296 get_irqchip_out:
3297 kfree(chip);
3298 if (r)
3299 goto out;
3300 break;
3301 }
3302 case KVM_SET_IRQCHIP: {
3303 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3304 struct kvm_irqchip *chip;
3305
3306 chip = memdup_user(argp, sizeof(*chip));
3307 if (IS_ERR(chip)) {
3308 r = PTR_ERR(chip);
3309 goto out;
3310 }
3311
3312 r = -ENXIO;
3313 if (!irqchip_in_kernel(kvm))
3314 goto set_irqchip_out;
3315 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3316 if (r)
3317 goto set_irqchip_out;
3318 r = 0;
3319 set_irqchip_out:
3320 kfree(chip);
3321 if (r)
3322 goto out;
3323 break;
3324 }
3325 case KVM_GET_PIT: {
3326 r = -EFAULT;
3327 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3328 goto out;
3329 r = -ENXIO;
3330 if (!kvm->arch.vpit)
3331 goto out;
3332 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3333 if (r)
3334 goto out;
3335 r = -EFAULT;
3336 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3337 goto out;
3338 r = 0;
3339 break;
3340 }
3341 case KVM_SET_PIT: {
3342 r = -EFAULT;
3343 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3344 goto out;
3345 r = -ENXIO;
3346 if (!kvm->arch.vpit)
3347 goto out;
3348 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3349 if (r)
3350 goto out;
3351 r = 0;
3352 break;
3353 }
3354 case KVM_GET_PIT2: {
3355 r = -ENXIO;
3356 if (!kvm->arch.vpit)
3357 goto out;
3358 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3359 if (r)
3360 goto out;
3361 r = -EFAULT;
3362 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3363 goto out;
3364 r = 0;
3365 break;
3366 }
3367 case KVM_SET_PIT2: {
3368 r = -EFAULT;
3369 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3370 goto out;
3371 r = -ENXIO;
3372 if (!kvm->arch.vpit)
3373 goto out;
3374 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3375 if (r)
3376 goto out;
3377 r = 0;
3378 break;
3379 }
3380 case KVM_REINJECT_CONTROL: {
3381 struct kvm_reinject_control control;
3382 r = -EFAULT;
3383 if (copy_from_user(&control, argp, sizeof(control)))
3384 goto out;
3385 r = kvm_vm_ioctl_reinject(kvm, &control);
3386 if (r)
3387 goto out;
3388 r = 0;
3389 break;
3390 }
3391 case KVM_XEN_HVM_CONFIG: {
3392 r = -EFAULT;
3393 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3394 sizeof(struct kvm_xen_hvm_config)))
3395 goto out;
3396 r = -EINVAL;
3397 if (kvm->arch.xen_hvm_config.flags)
3398 goto out;
3399 r = 0;
3400 break;
3401 }
3402 case KVM_SET_CLOCK: {
3403 struct kvm_clock_data user_ns;
3404 u64 now_ns;
3405 s64 delta;
3406
3407 r = -EFAULT;
3408 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3409 goto out;
3410
3411 r = -EINVAL;
3412 if (user_ns.flags)
3413 goto out;
3414
3415 r = 0;
3416 local_irq_disable();
3417 now_ns = get_kernel_ns();
3418 delta = user_ns.clock - now_ns;
3419 local_irq_enable();
3420 kvm->arch.kvmclock_offset = delta;
3421 break;
3422 }
3423 case KVM_GET_CLOCK: {
3424 struct kvm_clock_data user_ns;
3425 u64 now_ns;
3426
3427 local_irq_disable();
3428 now_ns = get_kernel_ns();
3429 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3430 local_irq_enable();
3431 user_ns.flags = 0;
3432 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3433
3434 r = -EFAULT;
3435 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3436 goto out;
3437 r = 0;
3438 break;
3439 }
3440
3441 default:
3442 ;
3443 }
3444 out:
3445 return r;
3446 }
3447
3448 static void kvm_init_msr_list(void)
3449 {
3450 u32 dummy[2];
3451 unsigned i, j;
3452
3453 /* skip the first msrs in the list. KVM-specific */
3454 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3455 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3456 continue;
3457 if (j < i)
3458 msrs_to_save[j] = msrs_to_save[i];
3459 j++;
3460 }
3461 num_msrs_to_save = j;
3462 }
3463
3464 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3465 const void *v)
3466 {
3467 int handled = 0;
3468 int n;
3469
3470 do {
3471 n = min(len, 8);
3472 if (!(vcpu->arch.apic &&
3473 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3474 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3475 break;
3476 handled += n;
3477 addr += n;
3478 len -= n;
3479 v += n;
3480 } while (len);
3481
3482 return handled;
3483 }
3484
3485 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3486 {
3487 int handled = 0;
3488 int n;
3489
3490 do {
3491 n = min(len, 8);
3492 if (!(vcpu->arch.apic &&
3493 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3494 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3495 break;
3496 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3497 handled += n;
3498 addr += n;
3499 len -= n;
3500 v += n;
3501 } while (len);
3502
3503 return handled;
3504 }
3505
3506 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3507 struct kvm_segment *var, int seg)
3508 {
3509 kvm_x86_ops->set_segment(vcpu, var, seg);
3510 }
3511
3512 void kvm_get_segment(struct kvm_vcpu *vcpu,
3513 struct kvm_segment *var, int seg)
3514 {
3515 kvm_x86_ops->get_segment(vcpu, var, seg);
3516 }
3517
3518 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3519 {
3520 gpa_t t_gpa;
3521 struct x86_exception exception;
3522
3523 BUG_ON(!mmu_is_nested(vcpu));
3524
3525 /* NPT walks are always user-walks */
3526 access |= PFERR_USER_MASK;
3527 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3528
3529 return t_gpa;
3530 }
3531
3532 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3533 struct x86_exception *exception)
3534 {
3535 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3536 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3537 }
3538
3539 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3540 struct x86_exception *exception)
3541 {
3542 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3543 access |= PFERR_FETCH_MASK;
3544 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3545 }
3546
3547 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3548 struct x86_exception *exception)
3549 {
3550 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3551 access |= PFERR_WRITE_MASK;
3552 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3553 }
3554
3555 /* uses this to access any guest's mapped memory without checking CPL */
3556 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3557 struct x86_exception *exception)
3558 {
3559 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3560 }
3561
3562 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3563 struct kvm_vcpu *vcpu, u32 access,
3564 struct x86_exception *exception)
3565 {
3566 void *data = val;
3567 int r = X86EMUL_CONTINUE;
3568
3569 while (bytes) {
3570 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3571 exception);
3572 unsigned offset = addr & (PAGE_SIZE-1);
3573 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3574 int ret;
3575
3576 if (gpa == UNMAPPED_GVA)
3577 return X86EMUL_PROPAGATE_FAULT;
3578 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3579 if (ret < 0) {
3580 r = X86EMUL_IO_NEEDED;
3581 goto out;
3582 }
3583
3584 bytes -= toread;
3585 data += toread;
3586 addr += toread;
3587 }
3588 out:
3589 return r;
3590 }
3591
3592 /* used for instruction fetching */
3593 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3594 gva_t addr, void *val, unsigned int bytes,
3595 struct x86_exception *exception)
3596 {
3597 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3598 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3599
3600 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3601 access | PFERR_FETCH_MASK,
3602 exception);
3603 }
3604
3605 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3606 gva_t addr, void *val, unsigned int bytes,
3607 struct x86_exception *exception)
3608 {
3609 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3610 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3611
3612 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3613 exception);
3614 }
3615 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3616
3617 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3618 gva_t addr, void *val, unsigned int bytes,
3619 struct x86_exception *exception)
3620 {
3621 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3622 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3623 }
3624
3625 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3626 gva_t addr, void *val,
3627 unsigned int bytes,
3628 struct x86_exception *exception)
3629 {
3630 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3631 void *data = val;
3632 int r = X86EMUL_CONTINUE;
3633
3634 while (bytes) {
3635 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3636 PFERR_WRITE_MASK,
3637 exception);
3638 unsigned offset = addr & (PAGE_SIZE-1);
3639 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3640 int ret;
3641
3642 if (gpa == UNMAPPED_GVA)
3643 return X86EMUL_PROPAGATE_FAULT;
3644 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3645 if (ret < 0) {
3646 r = X86EMUL_IO_NEEDED;
3647 goto out;
3648 }
3649
3650 bytes -= towrite;
3651 data += towrite;
3652 addr += towrite;
3653 }
3654 out:
3655 return r;
3656 }
3657 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3658
3659 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3660 gpa_t *gpa, struct x86_exception *exception,
3661 bool write)
3662 {
3663 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3664
3665 if (vcpu_match_mmio_gva(vcpu, gva) &&
3666 check_write_user_access(vcpu, write, access,
3667 vcpu->arch.access)) {
3668 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3669 (gva & (PAGE_SIZE - 1));
3670 trace_vcpu_match_mmio(gva, *gpa, write, false);
3671 return 1;
3672 }
3673
3674 if (write)
3675 access |= PFERR_WRITE_MASK;
3676
3677 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3678
3679 if (*gpa == UNMAPPED_GVA)
3680 return -1;
3681
3682 /* For APIC access vmexit */
3683 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3684 return 1;
3685
3686 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3687 trace_vcpu_match_mmio(gva, *gpa, write, true);
3688 return 1;
3689 }
3690
3691 return 0;
3692 }
3693
3694 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3695 const void *val, int bytes)
3696 {
3697 int ret;
3698
3699 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3700 if (ret < 0)
3701 return 0;
3702 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3703 return 1;
3704 }
3705
3706 struct read_write_emulator_ops {
3707 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3708 int bytes);
3709 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3710 void *val, int bytes);
3711 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3712 int bytes, void *val);
3713 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3714 void *val, int bytes);
3715 bool write;
3716 };
3717
3718 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3719 {
3720 if (vcpu->mmio_read_completed) {
3721 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3722 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
3723 vcpu->mmio_read_completed = 0;
3724 return 1;
3725 }
3726
3727 return 0;
3728 }
3729
3730 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3731 void *val, int bytes)
3732 {
3733 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3734 }
3735
3736 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3737 void *val, int bytes)
3738 {
3739 return emulator_write_phys(vcpu, gpa, val, bytes);
3740 }
3741
3742 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3743 {
3744 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3745 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3746 }
3747
3748 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3749 void *val, int bytes)
3750 {
3751 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3752 return X86EMUL_IO_NEEDED;
3753 }
3754
3755 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3756 void *val, int bytes)
3757 {
3758 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3759
3760 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
3761 return X86EMUL_CONTINUE;
3762 }
3763
3764 static struct read_write_emulator_ops read_emultor = {
3765 .read_write_prepare = read_prepare,
3766 .read_write_emulate = read_emulate,
3767 .read_write_mmio = vcpu_mmio_read,
3768 .read_write_exit_mmio = read_exit_mmio,
3769 };
3770
3771 static struct read_write_emulator_ops write_emultor = {
3772 .read_write_emulate = write_emulate,
3773 .read_write_mmio = write_mmio,
3774 .read_write_exit_mmio = write_exit_mmio,
3775 .write = true,
3776 };
3777
3778 static int emulator_read_write_onepage(unsigned long addr, void *val,
3779 unsigned int bytes,
3780 struct x86_exception *exception,
3781 struct kvm_vcpu *vcpu,
3782 struct read_write_emulator_ops *ops)
3783 {
3784 gpa_t gpa;
3785 int handled, ret;
3786 bool write = ops->write;
3787 struct kvm_mmio_fragment *frag;
3788
3789 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3790
3791 if (ret < 0)
3792 return X86EMUL_PROPAGATE_FAULT;
3793
3794 /* For APIC access vmexit */
3795 if (ret)
3796 goto mmio;
3797
3798 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3799 return X86EMUL_CONTINUE;
3800
3801 mmio:
3802 /*
3803 * Is this MMIO handled locally?
3804 */
3805 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3806 if (handled == bytes)
3807 return X86EMUL_CONTINUE;
3808
3809 gpa += handled;
3810 bytes -= handled;
3811 val += handled;
3812
3813 while (bytes) {
3814 unsigned now = min(bytes, 8U);
3815
3816 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3817 frag->gpa = gpa;
3818 frag->data = val;
3819 frag->len = now;
3820
3821 gpa += now;
3822 val += now;
3823 bytes -= now;
3824 }
3825 return X86EMUL_CONTINUE;
3826 }
3827
3828 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3829 void *val, unsigned int bytes,
3830 struct x86_exception *exception,
3831 struct read_write_emulator_ops *ops)
3832 {
3833 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3834 gpa_t gpa;
3835 int rc;
3836
3837 if (ops->read_write_prepare &&
3838 ops->read_write_prepare(vcpu, val, bytes))
3839 return X86EMUL_CONTINUE;
3840
3841 vcpu->mmio_nr_fragments = 0;
3842
3843 /* Crossing a page boundary? */
3844 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3845 int now;
3846
3847 now = -addr & ~PAGE_MASK;
3848 rc = emulator_read_write_onepage(addr, val, now, exception,
3849 vcpu, ops);
3850
3851 if (rc != X86EMUL_CONTINUE)
3852 return rc;
3853 addr += now;
3854 val += now;
3855 bytes -= now;
3856 }
3857
3858 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3859 vcpu, ops);
3860 if (rc != X86EMUL_CONTINUE)
3861 return rc;
3862
3863 if (!vcpu->mmio_nr_fragments)
3864 return rc;
3865
3866 gpa = vcpu->mmio_fragments[0].gpa;
3867
3868 vcpu->mmio_needed = 1;
3869 vcpu->mmio_cur_fragment = 0;
3870
3871 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3872 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3873 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3874 vcpu->run->mmio.phys_addr = gpa;
3875
3876 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3877 }
3878
3879 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3880 unsigned long addr,
3881 void *val,
3882 unsigned int bytes,
3883 struct x86_exception *exception)
3884 {
3885 return emulator_read_write(ctxt, addr, val, bytes,
3886 exception, &read_emultor);
3887 }
3888
3889 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3890 unsigned long addr,
3891 const void *val,
3892 unsigned int bytes,
3893 struct x86_exception *exception)
3894 {
3895 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3896 exception, &write_emultor);
3897 }
3898
3899 #define CMPXCHG_TYPE(t, ptr, old, new) \
3900 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3901
3902 #ifdef CONFIG_X86_64
3903 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3904 #else
3905 # define CMPXCHG64(ptr, old, new) \
3906 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3907 #endif
3908
3909 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3910 unsigned long addr,
3911 const void *old,
3912 const void *new,
3913 unsigned int bytes,
3914 struct x86_exception *exception)
3915 {
3916 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3917 gpa_t gpa;
3918 struct page *page;
3919 char *kaddr;
3920 bool exchanged;
3921
3922 /* guests cmpxchg8b have to be emulated atomically */
3923 if (bytes > 8 || (bytes & (bytes - 1)))
3924 goto emul_write;
3925
3926 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3927
3928 if (gpa == UNMAPPED_GVA ||
3929 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3930 goto emul_write;
3931
3932 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3933 goto emul_write;
3934
3935 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3936 if (is_error_page(page)) {
3937 kvm_release_page_clean(page);
3938 goto emul_write;
3939 }
3940
3941 kaddr = kmap_atomic(page);
3942 kaddr += offset_in_page(gpa);
3943 switch (bytes) {
3944 case 1:
3945 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3946 break;
3947 case 2:
3948 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3949 break;
3950 case 4:
3951 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3952 break;
3953 case 8:
3954 exchanged = CMPXCHG64(kaddr, old, new);
3955 break;
3956 default:
3957 BUG();
3958 }
3959 kunmap_atomic(kaddr);
3960 kvm_release_page_dirty(page);
3961
3962 if (!exchanged)
3963 return X86EMUL_CMPXCHG_FAILED;
3964
3965 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3966
3967 return X86EMUL_CONTINUE;
3968
3969 emul_write:
3970 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3971
3972 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
3973 }
3974
3975 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3976 {
3977 /* TODO: String I/O for in kernel device */
3978 int r;
3979
3980 if (vcpu->arch.pio.in)
3981 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3982 vcpu->arch.pio.size, pd);
3983 else
3984 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3985 vcpu->arch.pio.port, vcpu->arch.pio.size,
3986 pd);
3987 return r;
3988 }
3989
3990 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3991 unsigned short port, void *val,
3992 unsigned int count, bool in)
3993 {
3994 trace_kvm_pio(!in, port, size, count);
3995
3996 vcpu->arch.pio.port = port;
3997 vcpu->arch.pio.in = in;
3998 vcpu->arch.pio.count = count;
3999 vcpu->arch.pio.size = size;
4000
4001 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4002 vcpu->arch.pio.count = 0;
4003 return 1;
4004 }
4005
4006 vcpu->run->exit_reason = KVM_EXIT_IO;
4007 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4008 vcpu->run->io.size = size;
4009 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4010 vcpu->run->io.count = count;
4011 vcpu->run->io.port = port;
4012
4013 return 0;
4014 }
4015
4016 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4017 int size, unsigned short port, void *val,
4018 unsigned int count)
4019 {
4020 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4021 int ret;
4022
4023 if (vcpu->arch.pio.count)
4024 goto data_avail;
4025
4026 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4027 if (ret) {
4028 data_avail:
4029 memcpy(val, vcpu->arch.pio_data, size * count);
4030 vcpu->arch.pio.count = 0;
4031 return 1;
4032 }
4033
4034 return 0;
4035 }
4036
4037 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4038 int size, unsigned short port,
4039 const void *val, unsigned int count)
4040 {
4041 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4042
4043 memcpy(vcpu->arch.pio_data, val, size * count);
4044 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4045 }
4046
4047 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4048 {
4049 return kvm_x86_ops->get_segment_base(vcpu, seg);
4050 }
4051
4052 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4053 {
4054 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4055 }
4056
4057 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4058 {
4059 if (!need_emulate_wbinvd(vcpu))
4060 return X86EMUL_CONTINUE;
4061
4062 if (kvm_x86_ops->has_wbinvd_exit()) {
4063 int cpu = get_cpu();
4064
4065 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4066 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4067 wbinvd_ipi, NULL, 1);
4068 put_cpu();
4069 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4070 } else
4071 wbinvd();
4072 return X86EMUL_CONTINUE;
4073 }
4074 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4075
4076 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4077 {
4078 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4079 }
4080
4081 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4082 {
4083 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4084 }
4085
4086 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4087 {
4088
4089 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4090 }
4091
4092 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4093 {
4094 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4095 }
4096
4097 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4098 {
4099 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4100 unsigned long value;
4101
4102 switch (cr) {
4103 case 0:
4104 value = kvm_read_cr0(vcpu);
4105 break;
4106 case 2:
4107 value = vcpu->arch.cr2;
4108 break;
4109 case 3:
4110 value = kvm_read_cr3(vcpu);
4111 break;
4112 case 4:
4113 value = kvm_read_cr4(vcpu);
4114 break;
4115 case 8:
4116 value = kvm_get_cr8(vcpu);
4117 break;
4118 default:
4119 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4120 return 0;
4121 }
4122
4123 return value;
4124 }
4125
4126 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4127 {
4128 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4129 int res = 0;
4130
4131 switch (cr) {
4132 case 0:
4133 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4134 break;
4135 case 2:
4136 vcpu->arch.cr2 = val;
4137 break;
4138 case 3:
4139 res = kvm_set_cr3(vcpu, val);
4140 break;
4141 case 4:
4142 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4143 break;
4144 case 8:
4145 res = kvm_set_cr8(vcpu, val);
4146 break;
4147 default:
4148 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4149 res = -1;
4150 }
4151
4152 return res;
4153 }
4154
4155 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4156 {
4157 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4158 }
4159
4160 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4161 {
4162 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4163 }
4164
4165 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4166 {
4167 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4168 }
4169
4170 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4171 {
4172 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4173 }
4174
4175 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4176 {
4177 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4178 }
4179
4180 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4181 {
4182 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4183 }
4184
4185 static unsigned long emulator_get_cached_segment_base(
4186 struct x86_emulate_ctxt *ctxt, int seg)
4187 {
4188 return get_segment_base(emul_to_vcpu(ctxt), seg);
4189 }
4190
4191 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4192 struct desc_struct *desc, u32 *base3,
4193 int seg)
4194 {
4195 struct kvm_segment var;
4196
4197 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4198 *selector = var.selector;
4199
4200 if (var.unusable)
4201 return false;
4202
4203 if (var.g)
4204 var.limit >>= 12;
4205 set_desc_limit(desc, var.limit);
4206 set_desc_base(desc, (unsigned long)var.base);
4207 #ifdef CONFIG_X86_64
4208 if (base3)
4209 *base3 = var.base >> 32;
4210 #endif
4211 desc->type = var.type;
4212 desc->s = var.s;
4213 desc->dpl = var.dpl;
4214 desc->p = var.present;
4215 desc->avl = var.avl;
4216 desc->l = var.l;
4217 desc->d = var.db;
4218 desc->g = var.g;
4219
4220 return true;
4221 }
4222
4223 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4224 struct desc_struct *desc, u32 base3,
4225 int seg)
4226 {
4227 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4228 struct kvm_segment var;
4229
4230 var.selector = selector;
4231 var.base = get_desc_base(desc);
4232 #ifdef CONFIG_X86_64
4233 var.base |= ((u64)base3) << 32;
4234 #endif
4235 var.limit = get_desc_limit(desc);
4236 if (desc->g)
4237 var.limit = (var.limit << 12) | 0xfff;
4238 var.type = desc->type;
4239 var.present = desc->p;
4240 var.dpl = desc->dpl;
4241 var.db = desc->d;
4242 var.s = desc->s;
4243 var.l = desc->l;
4244 var.g = desc->g;
4245 var.avl = desc->avl;
4246 var.present = desc->p;
4247 var.unusable = !var.present;
4248 var.padding = 0;
4249
4250 kvm_set_segment(vcpu, &var, seg);
4251 return;
4252 }
4253
4254 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4255 u32 msr_index, u64 *pdata)
4256 {
4257 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4258 }
4259
4260 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4261 u32 msr_index, u64 data)
4262 {
4263 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4264 }
4265
4266 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4267 u32 pmc, u64 *pdata)
4268 {
4269 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4270 }
4271
4272 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4273 {
4274 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4275 }
4276
4277 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4278 {
4279 preempt_disable();
4280 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4281 /*
4282 * CR0.TS may reference the host fpu state, not the guest fpu state,
4283 * so it may be clear at this point.
4284 */
4285 clts();
4286 }
4287
4288 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4289 {
4290 preempt_enable();
4291 }
4292
4293 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4294 struct x86_instruction_info *info,
4295 enum x86_intercept_stage stage)
4296 {
4297 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4298 }
4299
4300 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4301 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4302 {
4303 struct kvm_cpuid_entry2 *cpuid = NULL;
4304
4305 if (eax && ecx)
4306 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4307 *eax, *ecx);
4308
4309 if (cpuid) {
4310 *eax = cpuid->eax;
4311 *ecx = cpuid->ecx;
4312 if (ebx)
4313 *ebx = cpuid->ebx;
4314 if (edx)
4315 *edx = cpuid->edx;
4316 return true;
4317 }
4318
4319 return false;
4320 }
4321
4322 static struct x86_emulate_ops emulate_ops = {
4323 .read_std = kvm_read_guest_virt_system,
4324 .write_std = kvm_write_guest_virt_system,
4325 .fetch = kvm_fetch_guest_virt,
4326 .read_emulated = emulator_read_emulated,
4327 .write_emulated = emulator_write_emulated,
4328 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4329 .invlpg = emulator_invlpg,
4330 .pio_in_emulated = emulator_pio_in_emulated,
4331 .pio_out_emulated = emulator_pio_out_emulated,
4332 .get_segment = emulator_get_segment,
4333 .set_segment = emulator_set_segment,
4334 .get_cached_segment_base = emulator_get_cached_segment_base,
4335 .get_gdt = emulator_get_gdt,
4336 .get_idt = emulator_get_idt,
4337 .set_gdt = emulator_set_gdt,
4338 .set_idt = emulator_set_idt,
4339 .get_cr = emulator_get_cr,
4340 .set_cr = emulator_set_cr,
4341 .set_rflags = emulator_set_rflags,
4342 .cpl = emulator_get_cpl,
4343 .get_dr = emulator_get_dr,
4344 .set_dr = emulator_set_dr,
4345 .set_msr = emulator_set_msr,
4346 .get_msr = emulator_get_msr,
4347 .read_pmc = emulator_read_pmc,
4348 .halt = emulator_halt,
4349 .wbinvd = emulator_wbinvd,
4350 .fix_hypercall = emulator_fix_hypercall,
4351 .get_fpu = emulator_get_fpu,
4352 .put_fpu = emulator_put_fpu,
4353 .intercept = emulator_intercept,
4354 .get_cpuid = emulator_get_cpuid,
4355 };
4356
4357 static void cache_all_regs(struct kvm_vcpu *vcpu)
4358 {
4359 kvm_register_read(vcpu, VCPU_REGS_RAX);
4360 kvm_register_read(vcpu, VCPU_REGS_RSP);
4361 kvm_register_read(vcpu, VCPU_REGS_RIP);
4362 vcpu->arch.regs_dirty = ~0;
4363 }
4364
4365 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4366 {
4367 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4368 /*
4369 * an sti; sti; sequence only disable interrupts for the first
4370 * instruction. So, if the last instruction, be it emulated or
4371 * not, left the system with the INT_STI flag enabled, it
4372 * means that the last instruction is an sti. We should not
4373 * leave the flag on in this case. The same goes for mov ss
4374 */
4375 if (!(int_shadow & mask))
4376 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4377 }
4378
4379 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4380 {
4381 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4382 if (ctxt->exception.vector == PF_VECTOR)
4383 kvm_propagate_fault(vcpu, &ctxt->exception);
4384 else if (ctxt->exception.error_code_valid)
4385 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4386 ctxt->exception.error_code);
4387 else
4388 kvm_queue_exception(vcpu, ctxt->exception.vector);
4389 }
4390
4391 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4392 const unsigned long *regs)
4393 {
4394 memset(&ctxt->twobyte, 0,
4395 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4396 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4397
4398 ctxt->fetch.start = 0;
4399 ctxt->fetch.end = 0;
4400 ctxt->io_read.pos = 0;
4401 ctxt->io_read.end = 0;
4402 ctxt->mem_read.pos = 0;
4403 ctxt->mem_read.end = 0;
4404 }
4405
4406 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4407 {
4408 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4409 int cs_db, cs_l;
4410
4411 /*
4412 * TODO: fix emulate.c to use guest_read/write_register
4413 * instead of direct ->regs accesses, can save hundred cycles
4414 * on Intel for instructions that don't read/change RSP, for
4415 * for example.
4416 */
4417 cache_all_regs(vcpu);
4418
4419 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4420
4421 ctxt->eflags = kvm_get_rflags(vcpu);
4422 ctxt->eip = kvm_rip_read(vcpu);
4423 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4424 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4425 cs_l ? X86EMUL_MODE_PROT64 :
4426 cs_db ? X86EMUL_MODE_PROT32 :
4427 X86EMUL_MODE_PROT16;
4428 ctxt->guest_mode = is_guest_mode(vcpu);
4429
4430 init_decode_cache(ctxt, vcpu->arch.regs);
4431 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4432 }
4433
4434 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4435 {
4436 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4437 int ret;
4438
4439 init_emulate_ctxt(vcpu);
4440
4441 ctxt->op_bytes = 2;
4442 ctxt->ad_bytes = 2;
4443 ctxt->_eip = ctxt->eip + inc_eip;
4444 ret = emulate_int_real(ctxt, irq);
4445
4446 if (ret != X86EMUL_CONTINUE)
4447 return EMULATE_FAIL;
4448
4449 ctxt->eip = ctxt->_eip;
4450 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4451 kvm_rip_write(vcpu, ctxt->eip);
4452 kvm_set_rflags(vcpu, ctxt->eflags);
4453
4454 if (irq == NMI_VECTOR)
4455 vcpu->arch.nmi_pending = 0;
4456 else
4457 vcpu->arch.interrupt.pending = false;
4458
4459 return EMULATE_DONE;
4460 }
4461 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4462
4463 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4464 {
4465 int r = EMULATE_DONE;
4466
4467 ++vcpu->stat.insn_emulation_fail;
4468 trace_kvm_emulate_insn_failed(vcpu);
4469 if (!is_guest_mode(vcpu)) {
4470 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4471 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4472 vcpu->run->internal.ndata = 0;
4473 r = EMULATE_FAIL;
4474 }
4475 kvm_queue_exception(vcpu, UD_VECTOR);
4476
4477 return r;
4478 }
4479
4480 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4481 {
4482 gpa_t gpa;
4483
4484 if (tdp_enabled)
4485 return false;
4486
4487 /*
4488 * if emulation was due to access to shadowed page table
4489 * and it failed try to unshadow page and re-entetr the
4490 * guest to let CPU execute the instruction.
4491 */
4492 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4493 return true;
4494
4495 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4496
4497 if (gpa == UNMAPPED_GVA)
4498 return true; /* let cpu generate fault */
4499
4500 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4501 return true;
4502
4503 return false;
4504 }
4505
4506 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4507 unsigned long cr2, int emulation_type)
4508 {
4509 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4510 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4511
4512 last_retry_eip = vcpu->arch.last_retry_eip;
4513 last_retry_addr = vcpu->arch.last_retry_addr;
4514
4515 /*
4516 * If the emulation is caused by #PF and it is non-page_table
4517 * writing instruction, it means the VM-EXIT is caused by shadow
4518 * page protected, we can zap the shadow page and retry this
4519 * instruction directly.
4520 *
4521 * Note: if the guest uses a non-page-table modifying instruction
4522 * on the PDE that points to the instruction, then we will unmap
4523 * the instruction and go to an infinite loop. So, we cache the
4524 * last retried eip and the last fault address, if we meet the eip
4525 * and the address again, we can break out of the potential infinite
4526 * loop.
4527 */
4528 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4529
4530 if (!(emulation_type & EMULTYPE_RETRY))
4531 return false;
4532
4533 if (x86_page_table_writing_insn(ctxt))
4534 return false;
4535
4536 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4537 return false;
4538
4539 vcpu->arch.last_retry_eip = ctxt->eip;
4540 vcpu->arch.last_retry_addr = cr2;
4541
4542 if (!vcpu->arch.mmu.direct_map)
4543 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4544
4545 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4546
4547 return true;
4548 }
4549
4550 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4551 unsigned long cr2,
4552 int emulation_type,
4553 void *insn,
4554 int insn_len)
4555 {
4556 int r;
4557 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4558 bool writeback = true;
4559
4560 kvm_clear_exception_queue(vcpu);
4561
4562 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4563 init_emulate_ctxt(vcpu);
4564 ctxt->interruptibility = 0;
4565 ctxt->have_exception = false;
4566 ctxt->perm_ok = false;
4567
4568 ctxt->only_vendor_specific_insn
4569 = emulation_type & EMULTYPE_TRAP_UD;
4570
4571 r = x86_decode_insn(ctxt, insn, insn_len);
4572
4573 trace_kvm_emulate_insn_start(vcpu);
4574 ++vcpu->stat.insn_emulation;
4575 if (r != EMULATION_OK) {
4576 if (emulation_type & EMULTYPE_TRAP_UD)
4577 return EMULATE_FAIL;
4578 if (reexecute_instruction(vcpu, cr2))
4579 return EMULATE_DONE;
4580 if (emulation_type & EMULTYPE_SKIP)
4581 return EMULATE_FAIL;
4582 return handle_emulation_failure(vcpu);
4583 }
4584 }
4585
4586 if (emulation_type & EMULTYPE_SKIP) {
4587 kvm_rip_write(vcpu, ctxt->_eip);
4588 return EMULATE_DONE;
4589 }
4590
4591 if (retry_instruction(ctxt, cr2, emulation_type))
4592 return EMULATE_DONE;
4593
4594 /* this is needed for vmware backdoor interface to work since it
4595 changes registers values during IO operation */
4596 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4597 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4598 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4599 }
4600
4601 restart:
4602 r = x86_emulate_insn(ctxt);
4603
4604 if (r == EMULATION_INTERCEPTED)
4605 return EMULATE_DONE;
4606
4607 if (r == EMULATION_FAILED) {
4608 if (reexecute_instruction(vcpu, cr2))
4609 return EMULATE_DONE;
4610
4611 return handle_emulation_failure(vcpu);
4612 }
4613
4614 if (ctxt->have_exception) {
4615 inject_emulated_exception(vcpu);
4616 r = EMULATE_DONE;
4617 } else if (vcpu->arch.pio.count) {
4618 if (!vcpu->arch.pio.in)
4619 vcpu->arch.pio.count = 0;
4620 else
4621 writeback = false;
4622 r = EMULATE_DO_MMIO;
4623 } else if (vcpu->mmio_needed) {
4624 if (!vcpu->mmio_is_write)
4625 writeback = false;
4626 r = EMULATE_DO_MMIO;
4627 } else if (r == EMULATION_RESTART)
4628 goto restart;
4629 else
4630 r = EMULATE_DONE;
4631
4632 if (writeback) {
4633 toggle_interruptibility(vcpu, ctxt->interruptibility);
4634 kvm_set_rflags(vcpu, ctxt->eflags);
4635 kvm_make_request(KVM_REQ_EVENT, vcpu);
4636 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4637 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4638 kvm_rip_write(vcpu, ctxt->eip);
4639 } else
4640 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4641
4642 return r;
4643 }
4644 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4645
4646 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4647 {
4648 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4649 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4650 size, port, &val, 1);
4651 /* do not return to emulator after return from userspace */
4652 vcpu->arch.pio.count = 0;
4653 return ret;
4654 }
4655 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4656
4657 static void tsc_bad(void *info)
4658 {
4659 __this_cpu_write(cpu_tsc_khz, 0);
4660 }
4661
4662 static void tsc_khz_changed(void *data)
4663 {
4664 struct cpufreq_freqs *freq = data;
4665 unsigned long khz = 0;
4666
4667 if (data)
4668 khz = freq->new;
4669 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4670 khz = cpufreq_quick_get(raw_smp_processor_id());
4671 if (!khz)
4672 khz = tsc_khz;
4673 __this_cpu_write(cpu_tsc_khz, khz);
4674 }
4675
4676 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4677 void *data)
4678 {
4679 struct cpufreq_freqs *freq = data;
4680 struct kvm *kvm;
4681 struct kvm_vcpu *vcpu;
4682 int i, send_ipi = 0;
4683
4684 /*
4685 * We allow guests to temporarily run on slowing clocks,
4686 * provided we notify them after, or to run on accelerating
4687 * clocks, provided we notify them before. Thus time never
4688 * goes backwards.
4689 *
4690 * However, we have a problem. We can't atomically update
4691 * the frequency of a given CPU from this function; it is
4692 * merely a notifier, which can be called from any CPU.
4693 * Changing the TSC frequency at arbitrary points in time
4694 * requires a recomputation of local variables related to
4695 * the TSC for each VCPU. We must flag these local variables
4696 * to be updated and be sure the update takes place with the
4697 * new frequency before any guests proceed.
4698 *
4699 * Unfortunately, the combination of hotplug CPU and frequency
4700 * change creates an intractable locking scenario; the order
4701 * of when these callouts happen is undefined with respect to
4702 * CPU hotplug, and they can race with each other. As such,
4703 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4704 * undefined; you can actually have a CPU frequency change take
4705 * place in between the computation of X and the setting of the
4706 * variable. To protect against this problem, all updates of
4707 * the per_cpu tsc_khz variable are done in an interrupt
4708 * protected IPI, and all callers wishing to update the value
4709 * must wait for a synchronous IPI to complete (which is trivial
4710 * if the caller is on the CPU already). This establishes the
4711 * necessary total order on variable updates.
4712 *
4713 * Note that because a guest time update may take place
4714 * anytime after the setting of the VCPU's request bit, the
4715 * correct TSC value must be set before the request. However,
4716 * to ensure the update actually makes it to any guest which
4717 * starts running in hardware virtualization between the set
4718 * and the acquisition of the spinlock, we must also ping the
4719 * CPU after setting the request bit.
4720 *
4721 */
4722
4723 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4724 return 0;
4725 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4726 return 0;
4727
4728 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4729
4730 raw_spin_lock(&kvm_lock);
4731 list_for_each_entry(kvm, &vm_list, vm_list) {
4732 kvm_for_each_vcpu(i, vcpu, kvm) {
4733 if (vcpu->cpu != freq->cpu)
4734 continue;
4735 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4736 if (vcpu->cpu != smp_processor_id())
4737 send_ipi = 1;
4738 }
4739 }
4740 raw_spin_unlock(&kvm_lock);
4741
4742 if (freq->old < freq->new && send_ipi) {
4743 /*
4744 * We upscale the frequency. Must make the guest
4745 * doesn't see old kvmclock values while running with
4746 * the new frequency, otherwise we risk the guest sees
4747 * time go backwards.
4748 *
4749 * In case we update the frequency for another cpu
4750 * (which might be in guest context) send an interrupt
4751 * to kick the cpu out of guest context. Next time
4752 * guest context is entered kvmclock will be updated,
4753 * so the guest will not see stale values.
4754 */
4755 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4756 }
4757 return 0;
4758 }
4759
4760 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4761 .notifier_call = kvmclock_cpufreq_notifier
4762 };
4763
4764 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4765 unsigned long action, void *hcpu)
4766 {
4767 unsigned int cpu = (unsigned long)hcpu;
4768
4769 switch (action) {
4770 case CPU_ONLINE:
4771 case CPU_DOWN_FAILED:
4772 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4773 break;
4774 case CPU_DOWN_PREPARE:
4775 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4776 break;
4777 }
4778 return NOTIFY_OK;
4779 }
4780
4781 static struct notifier_block kvmclock_cpu_notifier_block = {
4782 .notifier_call = kvmclock_cpu_notifier,
4783 .priority = -INT_MAX
4784 };
4785
4786 static void kvm_timer_init(void)
4787 {
4788 int cpu;
4789
4790 max_tsc_khz = tsc_khz;
4791 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4792 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4793 #ifdef CONFIG_CPU_FREQ
4794 struct cpufreq_policy policy;
4795 memset(&policy, 0, sizeof(policy));
4796 cpu = get_cpu();
4797 cpufreq_get_policy(&policy, cpu);
4798 if (policy.cpuinfo.max_freq)
4799 max_tsc_khz = policy.cpuinfo.max_freq;
4800 put_cpu();
4801 #endif
4802 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4803 CPUFREQ_TRANSITION_NOTIFIER);
4804 }
4805 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4806 for_each_online_cpu(cpu)
4807 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4808 }
4809
4810 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4811
4812 int kvm_is_in_guest(void)
4813 {
4814 return __this_cpu_read(current_vcpu) != NULL;
4815 }
4816
4817 static int kvm_is_user_mode(void)
4818 {
4819 int user_mode = 3;
4820
4821 if (__this_cpu_read(current_vcpu))
4822 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4823
4824 return user_mode != 0;
4825 }
4826
4827 static unsigned long kvm_get_guest_ip(void)
4828 {
4829 unsigned long ip = 0;
4830
4831 if (__this_cpu_read(current_vcpu))
4832 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4833
4834 return ip;
4835 }
4836
4837 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4838 .is_in_guest = kvm_is_in_guest,
4839 .is_user_mode = kvm_is_user_mode,
4840 .get_guest_ip = kvm_get_guest_ip,
4841 };
4842
4843 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4844 {
4845 __this_cpu_write(current_vcpu, vcpu);
4846 }
4847 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4848
4849 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4850 {
4851 __this_cpu_write(current_vcpu, NULL);
4852 }
4853 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4854
4855 static void kvm_set_mmio_spte_mask(void)
4856 {
4857 u64 mask;
4858 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4859
4860 /*
4861 * Set the reserved bits and the present bit of an paging-structure
4862 * entry to generate page fault with PFER.RSV = 1.
4863 */
4864 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4865 mask |= 1ull;
4866
4867 #ifdef CONFIG_X86_64
4868 /*
4869 * If reserved bit is not supported, clear the present bit to disable
4870 * mmio page fault.
4871 */
4872 if (maxphyaddr == 52)
4873 mask &= ~1ull;
4874 #endif
4875
4876 kvm_mmu_set_mmio_spte_mask(mask);
4877 }
4878
4879 int kvm_arch_init(void *opaque)
4880 {
4881 int r;
4882 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4883
4884 if (kvm_x86_ops) {
4885 printk(KERN_ERR "kvm: already loaded the other module\n");
4886 r = -EEXIST;
4887 goto out;
4888 }
4889
4890 if (!ops->cpu_has_kvm_support()) {
4891 printk(KERN_ERR "kvm: no hardware support\n");
4892 r = -EOPNOTSUPP;
4893 goto out;
4894 }
4895 if (ops->disabled_by_bios()) {
4896 printk(KERN_ERR "kvm: disabled by bios\n");
4897 r = -EOPNOTSUPP;
4898 goto out;
4899 }
4900
4901 r = kvm_mmu_module_init();
4902 if (r)
4903 goto out;
4904
4905 kvm_set_mmio_spte_mask();
4906 kvm_init_msr_list();
4907
4908 kvm_x86_ops = ops;
4909 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4910 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4911
4912 kvm_timer_init();
4913
4914 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4915
4916 if (cpu_has_xsave)
4917 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4918
4919 return 0;
4920
4921 out:
4922 return r;
4923 }
4924
4925 void kvm_arch_exit(void)
4926 {
4927 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4928
4929 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4930 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4931 CPUFREQ_TRANSITION_NOTIFIER);
4932 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4933 kvm_x86_ops = NULL;
4934 kvm_mmu_module_exit();
4935 }
4936
4937 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4938 {
4939 ++vcpu->stat.halt_exits;
4940 if (irqchip_in_kernel(vcpu->kvm)) {
4941 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4942 return 1;
4943 } else {
4944 vcpu->run->exit_reason = KVM_EXIT_HLT;
4945 return 0;
4946 }
4947 }
4948 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4949
4950 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4951 {
4952 u64 param, ingpa, outgpa, ret;
4953 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4954 bool fast, longmode;
4955 int cs_db, cs_l;
4956
4957 /*
4958 * hypercall generates UD from non zero cpl and real mode
4959 * per HYPER-V spec
4960 */
4961 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4962 kvm_queue_exception(vcpu, UD_VECTOR);
4963 return 0;
4964 }
4965
4966 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4967 longmode = is_long_mode(vcpu) && cs_l == 1;
4968
4969 if (!longmode) {
4970 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4971 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4972 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4973 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4974 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4975 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4976 }
4977 #ifdef CONFIG_X86_64
4978 else {
4979 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4980 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4981 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4982 }
4983 #endif
4984
4985 code = param & 0xffff;
4986 fast = (param >> 16) & 0x1;
4987 rep_cnt = (param >> 32) & 0xfff;
4988 rep_idx = (param >> 48) & 0xfff;
4989
4990 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4991
4992 switch (code) {
4993 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4994 kvm_vcpu_on_spin(vcpu);
4995 break;
4996 default:
4997 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4998 break;
4999 }
5000
5001 ret = res | (((u64)rep_done & 0xfff) << 32);
5002 if (longmode) {
5003 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5004 } else {
5005 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5006 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5007 }
5008
5009 return 1;
5010 }
5011
5012 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5013 {
5014 unsigned long nr, a0, a1, a2, a3, ret;
5015 int r = 1;
5016
5017 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5018 return kvm_hv_hypercall(vcpu);
5019
5020 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5021 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5022 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5023 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5024 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5025
5026 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5027
5028 if (!is_long_mode(vcpu)) {
5029 nr &= 0xFFFFFFFF;
5030 a0 &= 0xFFFFFFFF;
5031 a1 &= 0xFFFFFFFF;
5032 a2 &= 0xFFFFFFFF;
5033 a3 &= 0xFFFFFFFF;
5034 }
5035
5036 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5037 ret = -KVM_EPERM;
5038 goto out;
5039 }
5040
5041 switch (nr) {
5042 case KVM_HC_VAPIC_POLL_IRQ:
5043 ret = 0;
5044 break;
5045 default:
5046 ret = -KVM_ENOSYS;
5047 break;
5048 }
5049 out:
5050 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5051 ++vcpu->stat.hypercalls;
5052 return r;
5053 }
5054 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5055
5056 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5057 {
5058 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5059 char instruction[3];
5060 unsigned long rip = kvm_rip_read(vcpu);
5061
5062 /*
5063 * Blow out the MMU to ensure that no other VCPU has an active mapping
5064 * to ensure that the updated hypercall appears atomically across all
5065 * VCPUs.
5066 */
5067 kvm_mmu_zap_all(vcpu->kvm);
5068
5069 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5070
5071 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5072 }
5073
5074 /*
5075 * Check if userspace requested an interrupt window, and that the
5076 * interrupt window is open.
5077 *
5078 * No need to exit to userspace if we already have an interrupt queued.
5079 */
5080 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5081 {
5082 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5083 vcpu->run->request_interrupt_window &&
5084 kvm_arch_interrupt_allowed(vcpu));
5085 }
5086
5087 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5088 {
5089 struct kvm_run *kvm_run = vcpu->run;
5090
5091 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5092 kvm_run->cr8 = kvm_get_cr8(vcpu);
5093 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5094 if (irqchip_in_kernel(vcpu->kvm))
5095 kvm_run->ready_for_interrupt_injection = 1;
5096 else
5097 kvm_run->ready_for_interrupt_injection =
5098 kvm_arch_interrupt_allowed(vcpu) &&
5099 !kvm_cpu_has_interrupt(vcpu) &&
5100 !kvm_event_needs_reinjection(vcpu);
5101 }
5102
5103 static void vapic_enter(struct kvm_vcpu *vcpu)
5104 {
5105 struct kvm_lapic *apic = vcpu->arch.apic;
5106 struct page *page;
5107
5108 if (!apic || !apic->vapic_addr)
5109 return;
5110
5111 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5112
5113 vcpu->arch.apic->vapic_page = page;
5114 }
5115
5116 static void vapic_exit(struct kvm_vcpu *vcpu)
5117 {
5118 struct kvm_lapic *apic = vcpu->arch.apic;
5119 int idx;
5120
5121 if (!apic || !apic->vapic_addr)
5122 return;
5123
5124 idx = srcu_read_lock(&vcpu->kvm->srcu);
5125 kvm_release_page_dirty(apic->vapic_page);
5126 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5127 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5128 }
5129
5130 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5131 {
5132 int max_irr, tpr;
5133
5134 if (!kvm_x86_ops->update_cr8_intercept)
5135 return;
5136
5137 if (!vcpu->arch.apic)
5138 return;
5139
5140 if (!vcpu->arch.apic->vapic_addr)
5141 max_irr = kvm_lapic_find_highest_irr(vcpu);
5142 else
5143 max_irr = -1;
5144
5145 if (max_irr != -1)
5146 max_irr >>= 4;
5147
5148 tpr = kvm_lapic_get_cr8(vcpu);
5149
5150 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5151 }
5152
5153 static void inject_pending_event(struct kvm_vcpu *vcpu)
5154 {
5155 /* try to reinject previous events if any */
5156 if (vcpu->arch.exception.pending) {
5157 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5158 vcpu->arch.exception.has_error_code,
5159 vcpu->arch.exception.error_code);
5160 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5161 vcpu->arch.exception.has_error_code,
5162 vcpu->arch.exception.error_code,
5163 vcpu->arch.exception.reinject);
5164 return;
5165 }
5166
5167 if (vcpu->arch.nmi_injected) {
5168 kvm_x86_ops->set_nmi(vcpu);
5169 return;
5170 }
5171
5172 if (vcpu->arch.interrupt.pending) {
5173 kvm_x86_ops->set_irq(vcpu);
5174 return;
5175 }
5176
5177 /* try to inject new event if pending */
5178 if (vcpu->arch.nmi_pending) {
5179 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5180 --vcpu->arch.nmi_pending;
5181 vcpu->arch.nmi_injected = true;
5182 kvm_x86_ops->set_nmi(vcpu);
5183 }
5184 } else if (kvm_cpu_has_interrupt(vcpu)) {
5185 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5186 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5187 false);
5188 kvm_x86_ops->set_irq(vcpu);
5189 }
5190 }
5191 }
5192
5193 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5194 {
5195 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5196 !vcpu->guest_xcr0_loaded) {
5197 /* kvm_set_xcr() also depends on this */
5198 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5199 vcpu->guest_xcr0_loaded = 1;
5200 }
5201 }
5202
5203 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5204 {
5205 if (vcpu->guest_xcr0_loaded) {
5206 if (vcpu->arch.xcr0 != host_xcr0)
5207 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5208 vcpu->guest_xcr0_loaded = 0;
5209 }
5210 }
5211
5212 static void process_nmi(struct kvm_vcpu *vcpu)
5213 {
5214 unsigned limit = 2;
5215
5216 /*
5217 * x86 is limited to one NMI running, and one NMI pending after it.
5218 * If an NMI is already in progress, limit further NMIs to just one.
5219 * Otherwise, allow two (and we'll inject the first one immediately).
5220 */
5221 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5222 limit = 1;
5223
5224 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5225 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5226 kvm_make_request(KVM_REQ_EVENT, vcpu);
5227 }
5228
5229 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5230 {
5231 int r;
5232 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5233 vcpu->run->request_interrupt_window;
5234 bool req_immediate_exit = 0;
5235
5236 if (vcpu->requests) {
5237 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5238 kvm_mmu_unload(vcpu);
5239 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5240 __kvm_migrate_timers(vcpu);
5241 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5242 r = kvm_guest_time_update(vcpu);
5243 if (unlikely(r))
5244 goto out;
5245 }
5246 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5247 kvm_mmu_sync_roots(vcpu);
5248 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5249 kvm_x86_ops->tlb_flush(vcpu);
5250 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5251 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5252 r = 0;
5253 goto out;
5254 }
5255 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5256 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5257 r = 0;
5258 goto out;
5259 }
5260 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5261 vcpu->fpu_active = 0;
5262 kvm_x86_ops->fpu_deactivate(vcpu);
5263 }
5264 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5265 /* Page is swapped out. Do synthetic halt */
5266 vcpu->arch.apf.halted = true;
5267 r = 1;
5268 goto out;
5269 }
5270 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5271 record_steal_time(vcpu);
5272 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5273 process_nmi(vcpu);
5274 req_immediate_exit =
5275 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5276 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5277 kvm_handle_pmu_event(vcpu);
5278 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5279 kvm_deliver_pmi(vcpu);
5280 }
5281
5282 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5283 inject_pending_event(vcpu);
5284
5285 /* enable NMI/IRQ window open exits if needed */
5286 if (vcpu->arch.nmi_pending)
5287 kvm_x86_ops->enable_nmi_window(vcpu);
5288 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5289 kvm_x86_ops->enable_irq_window(vcpu);
5290
5291 if (kvm_lapic_enabled(vcpu)) {
5292 update_cr8_intercept(vcpu);
5293 kvm_lapic_sync_to_vapic(vcpu);
5294 }
5295 }
5296
5297 r = kvm_mmu_reload(vcpu);
5298 if (unlikely(r)) {
5299 kvm_x86_ops->cancel_injection(vcpu);
5300 goto out;
5301 }
5302
5303 preempt_disable();
5304
5305 kvm_x86_ops->prepare_guest_switch(vcpu);
5306 if (vcpu->fpu_active)
5307 kvm_load_guest_fpu(vcpu);
5308 kvm_load_guest_xcr0(vcpu);
5309
5310 vcpu->mode = IN_GUEST_MODE;
5311
5312 /* We should set ->mode before check ->requests,
5313 * see the comment in make_all_cpus_request.
5314 */
5315 smp_mb();
5316
5317 local_irq_disable();
5318
5319 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5320 || need_resched() || signal_pending(current)) {
5321 vcpu->mode = OUTSIDE_GUEST_MODE;
5322 smp_wmb();
5323 local_irq_enable();
5324 preempt_enable();
5325 kvm_x86_ops->cancel_injection(vcpu);
5326 r = 1;
5327 goto out;
5328 }
5329
5330 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5331
5332 if (req_immediate_exit)
5333 smp_send_reschedule(vcpu->cpu);
5334
5335 kvm_guest_enter();
5336
5337 if (unlikely(vcpu->arch.switch_db_regs)) {
5338 set_debugreg(0, 7);
5339 set_debugreg(vcpu->arch.eff_db[0], 0);
5340 set_debugreg(vcpu->arch.eff_db[1], 1);
5341 set_debugreg(vcpu->arch.eff_db[2], 2);
5342 set_debugreg(vcpu->arch.eff_db[3], 3);
5343 }
5344
5345 trace_kvm_entry(vcpu->vcpu_id);
5346 kvm_x86_ops->run(vcpu);
5347
5348 /*
5349 * If the guest has used debug registers, at least dr7
5350 * will be disabled while returning to the host.
5351 * If we don't have active breakpoints in the host, we don't
5352 * care about the messed up debug address registers. But if
5353 * we have some of them active, restore the old state.
5354 */
5355 if (hw_breakpoint_active())
5356 hw_breakpoint_restore();
5357
5358 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5359
5360 vcpu->mode = OUTSIDE_GUEST_MODE;
5361 smp_wmb();
5362 local_irq_enable();
5363
5364 ++vcpu->stat.exits;
5365
5366 /*
5367 * We must have an instruction between local_irq_enable() and
5368 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5369 * the interrupt shadow. The stat.exits increment will do nicely.
5370 * But we need to prevent reordering, hence this barrier():
5371 */
5372 barrier();
5373
5374 kvm_guest_exit();
5375
5376 preempt_enable();
5377
5378 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5379
5380 /*
5381 * Profile KVM exit RIPs:
5382 */
5383 if (unlikely(prof_on == KVM_PROFILING)) {
5384 unsigned long rip = kvm_rip_read(vcpu);
5385 profile_hit(KVM_PROFILING, (void *)rip);
5386 }
5387
5388 if (unlikely(vcpu->arch.tsc_always_catchup))
5389 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5390
5391 kvm_lapic_sync_from_vapic(vcpu);
5392
5393 r = kvm_x86_ops->handle_exit(vcpu);
5394 out:
5395 return r;
5396 }
5397
5398
5399 static int __vcpu_run(struct kvm_vcpu *vcpu)
5400 {
5401 int r;
5402 struct kvm *kvm = vcpu->kvm;
5403
5404 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5405 pr_debug("vcpu %d received sipi with vector # %x\n",
5406 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5407 kvm_lapic_reset(vcpu);
5408 r = kvm_arch_vcpu_reset(vcpu);
5409 if (r)
5410 return r;
5411 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5412 }
5413
5414 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5415 vapic_enter(vcpu);
5416
5417 r = 1;
5418 while (r > 0) {
5419 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5420 !vcpu->arch.apf.halted)
5421 r = vcpu_enter_guest(vcpu);
5422 else {
5423 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5424 kvm_vcpu_block(vcpu);
5425 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5426 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5427 {
5428 switch(vcpu->arch.mp_state) {
5429 case KVM_MP_STATE_HALTED:
5430 vcpu->arch.mp_state =
5431 KVM_MP_STATE_RUNNABLE;
5432 case KVM_MP_STATE_RUNNABLE:
5433 vcpu->arch.apf.halted = false;
5434 break;
5435 case KVM_MP_STATE_SIPI_RECEIVED:
5436 default:
5437 r = -EINTR;
5438 break;
5439 }
5440 }
5441 }
5442
5443 if (r <= 0)
5444 break;
5445
5446 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5447 if (kvm_cpu_has_pending_timer(vcpu))
5448 kvm_inject_pending_timer_irqs(vcpu);
5449
5450 if (dm_request_for_irq_injection(vcpu)) {
5451 r = -EINTR;
5452 vcpu->run->exit_reason = KVM_EXIT_INTR;
5453 ++vcpu->stat.request_irq_exits;
5454 }
5455
5456 kvm_check_async_pf_completion(vcpu);
5457
5458 if (signal_pending(current)) {
5459 r = -EINTR;
5460 vcpu->run->exit_reason = KVM_EXIT_INTR;
5461 ++vcpu->stat.signal_exits;
5462 }
5463 if (need_resched()) {
5464 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5465 kvm_resched(vcpu);
5466 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5467 }
5468 }
5469
5470 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5471
5472 vapic_exit(vcpu);
5473
5474 return r;
5475 }
5476
5477 /*
5478 * Implements the following, as a state machine:
5479 *
5480 * read:
5481 * for each fragment
5482 * write gpa, len
5483 * exit
5484 * copy data
5485 * execute insn
5486 *
5487 * write:
5488 * for each fragment
5489 * write gpa, len
5490 * copy data
5491 * exit
5492 */
5493 static int complete_mmio(struct kvm_vcpu *vcpu)
5494 {
5495 struct kvm_run *run = vcpu->run;
5496 struct kvm_mmio_fragment *frag;
5497 int r;
5498
5499 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5500 return 1;
5501
5502 if (vcpu->mmio_needed) {
5503 /* Complete previous fragment */
5504 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5505 if (!vcpu->mmio_is_write)
5506 memcpy(frag->data, run->mmio.data, frag->len);
5507 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5508 vcpu->mmio_needed = 0;
5509 if (vcpu->mmio_is_write)
5510 return 1;
5511 vcpu->mmio_read_completed = 1;
5512 goto done;
5513 }
5514 /* Initiate next fragment */
5515 ++frag;
5516 run->exit_reason = KVM_EXIT_MMIO;
5517 run->mmio.phys_addr = frag->gpa;
5518 if (vcpu->mmio_is_write)
5519 memcpy(run->mmio.data, frag->data, frag->len);
5520 run->mmio.len = frag->len;
5521 run->mmio.is_write = vcpu->mmio_is_write;
5522 return 0;
5523
5524 }
5525 done:
5526 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5527 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5528 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5529 if (r != EMULATE_DONE)
5530 return 0;
5531 return 1;
5532 }
5533
5534 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5535 {
5536 int r;
5537 sigset_t sigsaved;
5538
5539 if (!tsk_used_math(current) && init_fpu(current))
5540 return -ENOMEM;
5541
5542 if (vcpu->sigset_active)
5543 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5544
5545 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5546 kvm_vcpu_block(vcpu);
5547 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5548 r = -EAGAIN;
5549 goto out;
5550 }
5551
5552 /* re-sync apic's tpr */
5553 if (!irqchip_in_kernel(vcpu->kvm)) {
5554 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5555 r = -EINVAL;
5556 goto out;
5557 }
5558 }
5559
5560 r = complete_mmio(vcpu);
5561 if (r <= 0)
5562 goto out;
5563
5564 r = __vcpu_run(vcpu);
5565
5566 out:
5567 post_kvm_run_save(vcpu);
5568 if (vcpu->sigset_active)
5569 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5570
5571 return r;
5572 }
5573
5574 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5575 {
5576 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5577 /*
5578 * We are here if userspace calls get_regs() in the middle of
5579 * instruction emulation. Registers state needs to be copied
5580 * back from emulation context to vcpu. Usrapace shouldn't do
5581 * that usually, but some bad designed PV devices (vmware
5582 * backdoor interface) need this to work
5583 */
5584 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5585 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5586 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5587 }
5588 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5589 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5590 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5591 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5592 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5593 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5594 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5595 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5596 #ifdef CONFIG_X86_64
5597 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5598 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5599 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5600 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5601 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5602 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5603 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5604 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5605 #endif
5606
5607 regs->rip = kvm_rip_read(vcpu);
5608 regs->rflags = kvm_get_rflags(vcpu);
5609
5610 return 0;
5611 }
5612
5613 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5614 {
5615 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5616 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5617
5618 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5619 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5620 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5621 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5622 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5623 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5624 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5625 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5626 #ifdef CONFIG_X86_64
5627 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5628 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5629 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5630 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5631 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5632 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5633 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5634 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5635 #endif
5636
5637 kvm_rip_write(vcpu, regs->rip);
5638 kvm_set_rflags(vcpu, regs->rflags);
5639
5640 vcpu->arch.exception.pending = false;
5641
5642 kvm_make_request(KVM_REQ_EVENT, vcpu);
5643
5644 return 0;
5645 }
5646
5647 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5648 {
5649 struct kvm_segment cs;
5650
5651 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5652 *db = cs.db;
5653 *l = cs.l;
5654 }
5655 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5656
5657 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5658 struct kvm_sregs *sregs)
5659 {
5660 struct desc_ptr dt;
5661
5662 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5663 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5664 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5665 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5666 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5667 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5668
5669 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5670 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5671
5672 kvm_x86_ops->get_idt(vcpu, &dt);
5673 sregs->idt.limit = dt.size;
5674 sregs->idt.base = dt.address;
5675 kvm_x86_ops->get_gdt(vcpu, &dt);
5676 sregs->gdt.limit = dt.size;
5677 sregs->gdt.base = dt.address;
5678
5679 sregs->cr0 = kvm_read_cr0(vcpu);
5680 sregs->cr2 = vcpu->arch.cr2;
5681 sregs->cr3 = kvm_read_cr3(vcpu);
5682 sregs->cr4 = kvm_read_cr4(vcpu);
5683 sregs->cr8 = kvm_get_cr8(vcpu);
5684 sregs->efer = vcpu->arch.efer;
5685 sregs->apic_base = kvm_get_apic_base(vcpu);
5686
5687 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5688
5689 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5690 set_bit(vcpu->arch.interrupt.nr,
5691 (unsigned long *)sregs->interrupt_bitmap);
5692
5693 return 0;
5694 }
5695
5696 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5697 struct kvm_mp_state *mp_state)
5698 {
5699 mp_state->mp_state = vcpu->arch.mp_state;
5700 return 0;
5701 }
5702
5703 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5704 struct kvm_mp_state *mp_state)
5705 {
5706 vcpu->arch.mp_state = mp_state->mp_state;
5707 kvm_make_request(KVM_REQ_EVENT, vcpu);
5708 return 0;
5709 }
5710
5711 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5712 int reason, bool has_error_code, u32 error_code)
5713 {
5714 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5715 int ret;
5716
5717 init_emulate_ctxt(vcpu);
5718
5719 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
5720 has_error_code, error_code);
5721
5722 if (ret)
5723 return EMULATE_FAIL;
5724
5725 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5726 kvm_rip_write(vcpu, ctxt->eip);
5727 kvm_set_rflags(vcpu, ctxt->eflags);
5728 kvm_make_request(KVM_REQ_EVENT, vcpu);
5729 return EMULATE_DONE;
5730 }
5731 EXPORT_SYMBOL_GPL(kvm_task_switch);
5732
5733 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5734 struct kvm_sregs *sregs)
5735 {
5736 int mmu_reset_needed = 0;
5737 int pending_vec, max_bits, idx;
5738 struct desc_ptr dt;
5739
5740 dt.size = sregs->idt.limit;
5741 dt.address = sregs->idt.base;
5742 kvm_x86_ops->set_idt(vcpu, &dt);
5743 dt.size = sregs->gdt.limit;
5744 dt.address = sregs->gdt.base;
5745 kvm_x86_ops->set_gdt(vcpu, &dt);
5746
5747 vcpu->arch.cr2 = sregs->cr2;
5748 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5749 vcpu->arch.cr3 = sregs->cr3;
5750 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5751
5752 kvm_set_cr8(vcpu, sregs->cr8);
5753
5754 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5755 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5756 kvm_set_apic_base(vcpu, sregs->apic_base);
5757
5758 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5759 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5760 vcpu->arch.cr0 = sregs->cr0;
5761
5762 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5763 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5764 if (sregs->cr4 & X86_CR4_OSXSAVE)
5765 kvm_update_cpuid(vcpu);
5766
5767 idx = srcu_read_lock(&vcpu->kvm->srcu);
5768 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5769 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5770 mmu_reset_needed = 1;
5771 }
5772 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5773
5774 if (mmu_reset_needed)
5775 kvm_mmu_reset_context(vcpu);
5776
5777 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5778 pending_vec = find_first_bit(
5779 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5780 if (pending_vec < max_bits) {
5781 kvm_queue_interrupt(vcpu, pending_vec, false);
5782 pr_debug("Set back pending irq %d\n", pending_vec);
5783 }
5784
5785 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5786 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5787 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5788 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5789 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5790 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5791
5792 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5793 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5794
5795 update_cr8_intercept(vcpu);
5796
5797 /* Older userspace won't unhalt the vcpu on reset. */
5798 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5799 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5800 !is_protmode(vcpu))
5801 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5802
5803 kvm_make_request(KVM_REQ_EVENT, vcpu);
5804
5805 return 0;
5806 }
5807
5808 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5809 struct kvm_guest_debug *dbg)
5810 {
5811 unsigned long rflags;
5812 int i, r;
5813
5814 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5815 r = -EBUSY;
5816 if (vcpu->arch.exception.pending)
5817 goto out;
5818 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5819 kvm_queue_exception(vcpu, DB_VECTOR);
5820 else
5821 kvm_queue_exception(vcpu, BP_VECTOR);
5822 }
5823
5824 /*
5825 * Read rflags as long as potentially injected trace flags are still
5826 * filtered out.
5827 */
5828 rflags = kvm_get_rflags(vcpu);
5829
5830 vcpu->guest_debug = dbg->control;
5831 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5832 vcpu->guest_debug = 0;
5833
5834 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5835 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5836 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5837 vcpu->arch.switch_db_regs =
5838 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5839 } else {
5840 for (i = 0; i < KVM_NR_DB_REGS; i++)
5841 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5842 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5843 }
5844
5845 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5846 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5847 get_segment_base(vcpu, VCPU_SREG_CS);
5848
5849 /*
5850 * Trigger an rflags update that will inject or remove the trace
5851 * flags.
5852 */
5853 kvm_set_rflags(vcpu, rflags);
5854
5855 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5856
5857 r = 0;
5858
5859 out:
5860
5861 return r;
5862 }
5863
5864 /*
5865 * Translate a guest virtual address to a guest physical address.
5866 */
5867 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5868 struct kvm_translation *tr)
5869 {
5870 unsigned long vaddr = tr->linear_address;
5871 gpa_t gpa;
5872 int idx;
5873
5874 idx = srcu_read_lock(&vcpu->kvm->srcu);
5875 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5876 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5877 tr->physical_address = gpa;
5878 tr->valid = gpa != UNMAPPED_GVA;
5879 tr->writeable = 1;
5880 tr->usermode = 0;
5881
5882 return 0;
5883 }
5884
5885 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5886 {
5887 struct i387_fxsave_struct *fxsave =
5888 &vcpu->arch.guest_fpu.state->fxsave;
5889
5890 memcpy(fpu->fpr, fxsave->st_space, 128);
5891 fpu->fcw = fxsave->cwd;
5892 fpu->fsw = fxsave->swd;
5893 fpu->ftwx = fxsave->twd;
5894 fpu->last_opcode = fxsave->fop;
5895 fpu->last_ip = fxsave->rip;
5896 fpu->last_dp = fxsave->rdp;
5897 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5898
5899 return 0;
5900 }
5901
5902 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5903 {
5904 struct i387_fxsave_struct *fxsave =
5905 &vcpu->arch.guest_fpu.state->fxsave;
5906
5907 memcpy(fxsave->st_space, fpu->fpr, 128);
5908 fxsave->cwd = fpu->fcw;
5909 fxsave->swd = fpu->fsw;
5910 fxsave->twd = fpu->ftwx;
5911 fxsave->fop = fpu->last_opcode;
5912 fxsave->rip = fpu->last_ip;
5913 fxsave->rdp = fpu->last_dp;
5914 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5915
5916 return 0;
5917 }
5918
5919 int fx_init(struct kvm_vcpu *vcpu)
5920 {
5921 int err;
5922
5923 err = fpu_alloc(&vcpu->arch.guest_fpu);
5924 if (err)
5925 return err;
5926
5927 fpu_finit(&vcpu->arch.guest_fpu);
5928
5929 /*
5930 * Ensure guest xcr0 is valid for loading
5931 */
5932 vcpu->arch.xcr0 = XSTATE_FP;
5933
5934 vcpu->arch.cr0 |= X86_CR0_ET;
5935
5936 return 0;
5937 }
5938 EXPORT_SYMBOL_GPL(fx_init);
5939
5940 static void fx_free(struct kvm_vcpu *vcpu)
5941 {
5942 fpu_free(&vcpu->arch.guest_fpu);
5943 }
5944
5945 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5946 {
5947 if (vcpu->guest_fpu_loaded)
5948 return;
5949
5950 /*
5951 * Restore all possible states in the guest,
5952 * and assume host would use all available bits.
5953 * Guest xcr0 would be loaded later.
5954 */
5955 kvm_put_guest_xcr0(vcpu);
5956 vcpu->guest_fpu_loaded = 1;
5957 unlazy_fpu(current);
5958 fpu_restore_checking(&vcpu->arch.guest_fpu);
5959 trace_kvm_fpu(1);
5960 }
5961
5962 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5963 {
5964 kvm_put_guest_xcr0(vcpu);
5965
5966 if (!vcpu->guest_fpu_loaded)
5967 return;
5968
5969 vcpu->guest_fpu_loaded = 0;
5970 fpu_save_init(&vcpu->arch.guest_fpu);
5971 ++vcpu->stat.fpu_reload;
5972 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5973 trace_kvm_fpu(0);
5974 }
5975
5976 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5977 {
5978 kvmclock_reset(vcpu);
5979
5980 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5981 fx_free(vcpu);
5982 kvm_x86_ops->vcpu_free(vcpu);
5983 }
5984
5985 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5986 unsigned int id)
5987 {
5988 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5989 printk_once(KERN_WARNING
5990 "kvm: SMP vm created on host with unstable TSC; "
5991 "guest TSC will not be reliable\n");
5992 return kvm_x86_ops->vcpu_create(kvm, id);
5993 }
5994
5995 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5996 {
5997 int r;
5998
5999 vcpu->arch.mtrr_state.have_fixed = 1;
6000 vcpu_load(vcpu);
6001 r = kvm_arch_vcpu_reset(vcpu);
6002 if (r == 0)
6003 r = kvm_mmu_setup(vcpu);
6004 vcpu_put(vcpu);
6005
6006 return r;
6007 }
6008
6009 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6010 {
6011 vcpu->arch.apf.msr_val = 0;
6012
6013 vcpu_load(vcpu);
6014 kvm_mmu_unload(vcpu);
6015 vcpu_put(vcpu);
6016
6017 fx_free(vcpu);
6018 kvm_x86_ops->vcpu_free(vcpu);
6019 }
6020
6021 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6022 {
6023 atomic_set(&vcpu->arch.nmi_queued, 0);
6024 vcpu->arch.nmi_pending = 0;
6025 vcpu->arch.nmi_injected = false;
6026
6027 vcpu->arch.switch_db_regs = 0;
6028 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6029 vcpu->arch.dr6 = DR6_FIXED_1;
6030 vcpu->arch.dr7 = DR7_FIXED_1;
6031
6032 kvm_make_request(KVM_REQ_EVENT, vcpu);
6033 vcpu->arch.apf.msr_val = 0;
6034 vcpu->arch.st.msr_val = 0;
6035
6036 kvmclock_reset(vcpu);
6037
6038 kvm_clear_async_pf_completion_queue(vcpu);
6039 kvm_async_pf_hash_reset(vcpu);
6040 vcpu->arch.apf.halted = false;
6041
6042 kvm_pmu_reset(vcpu);
6043
6044 return kvm_x86_ops->vcpu_reset(vcpu);
6045 }
6046
6047 int kvm_arch_hardware_enable(void *garbage)
6048 {
6049 struct kvm *kvm;
6050 struct kvm_vcpu *vcpu;
6051 int i;
6052 int ret;
6053 u64 local_tsc;
6054 u64 max_tsc = 0;
6055 bool stable, backwards_tsc = false;
6056
6057 kvm_shared_msr_cpu_online();
6058 ret = kvm_x86_ops->hardware_enable(garbage);
6059 if (ret != 0)
6060 return ret;
6061
6062 local_tsc = native_read_tsc();
6063 stable = !check_tsc_unstable();
6064 list_for_each_entry(kvm, &vm_list, vm_list) {
6065 kvm_for_each_vcpu(i, vcpu, kvm) {
6066 if (!stable && vcpu->cpu == smp_processor_id())
6067 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6068 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6069 backwards_tsc = true;
6070 if (vcpu->arch.last_host_tsc > max_tsc)
6071 max_tsc = vcpu->arch.last_host_tsc;
6072 }
6073 }
6074 }
6075
6076 /*
6077 * Sometimes, even reliable TSCs go backwards. This happens on
6078 * platforms that reset TSC during suspend or hibernate actions, but
6079 * maintain synchronization. We must compensate. Fortunately, we can
6080 * detect that condition here, which happens early in CPU bringup,
6081 * before any KVM threads can be running. Unfortunately, we can't
6082 * bring the TSCs fully up to date with real time, as we aren't yet far
6083 * enough into CPU bringup that we know how much real time has actually
6084 * elapsed; our helper function, get_kernel_ns() will be using boot
6085 * variables that haven't been updated yet.
6086 *
6087 * So we simply find the maximum observed TSC above, then record the
6088 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6089 * the adjustment will be applied. Note that we accumulate
6090 * adjustments, in case multiple suspend cycles happen before some VCPU
6091 * gets a chance to run again. In the event that no KVM threads get a
6092 * chance to run, we will miss the entire elapsed period, as we'll have
6093 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6094 * loose cycle time. This isn't too big a deal, since the loss will be
6095 * uniform across all VCPUs (not to mention the scenario is extremely
6096 * unlikely). It is possible that a second hibernate recovery happens
6097 * much faster than a first, causing the observed TSC here to be
6098 * smaller; this would require additional padding adjustment, which is
6099 * why we set last_host_tsc to the local tsc observed here.
6100 *
6101 * N.B. - this code below runs only on platforms with reliable TSC,
6102 * as that is the only way backwards_tsc is set above. Also note
6103 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6104 * have the same delta_cyc adjustment applied if backwards_tsc
6105 * is detected. Note further, this adjustment is only done once,
6106 * as we reset last_host_tsc on all VCPUs to stop this from being
6107 * called multiple times (one for each physical CPU bringup).
6108 *
6109 * Platforms with unnreliable TSCs don't have to deal with this, they
6110 * will be compensated by the logic in vcpu_load, which sets the TSC to
6111 * catchup mode. This will catchup all VCPUs to real time, but cannot
6112 * guarantee that they stay in perfect synchronization.
6113 */
6114 if (backwards_tsc) {
6115 u64 delta_cyc = max_tsc - local_tsc;
6116 list_for_each_entry(kvm, &vm_list, vm_list) {
6117 kvm_for_each_vcpu(i, vcpu, kvm) {
6118 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6119 vcpu->arch.last_host_tsc = local_tsc;
6120 }
6121
6122 /*
6123 * We have to disable TSC offset matching.. if you were
6124 * booting a VM while issuing an S4 host suspend....
6125 * you may have some problem. Solving this issue is
6126 * left as an exercise to the reader.
6127 */
6128 kvm->arch.last_tsc_nsec = 0;
6129 kvm->arch.last_tsc_write = 0;
6130 }
6131
6132 }
6133 return 0;
6134 }
6135
6136 void kvm_arch_hardware_disable(void *garbage)
6137 {
6138 kvm_x86_ops->hardware_disable(garbage);
6139 drop_user_return_notifiers(garbage);
6140 }
6141
6142 int kvm_arch_hardware_setup(void)
6143 {
6144 return kvm_x86_ops->hardware_setup();
6145 }
6146
6147 void kvm_arch_hardware_unsetup(void)
6148 {
6149 kvm_x86_ops->hardware_unsetup();
6150 }
6151
6152 void kvm_arch_check_processor_compat(void *rtn)
6153 {
6154 kvm_x86_ops->check_processor_compatibility(rtn);
6155 }
6156
6157 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6158 {
6159 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6160 }
6161
6162 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6163 {
6164 struct page *page;
6165 struct kvm *kvm;
6166 int r;
6167
6168 BUG_ON(vcpu->kvm == NULL);
6169 kvm = vcpu->kvm;
6170
6171 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6172 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6173 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6174 else
6175 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6176
6177 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6178 if (!page) {
6179 r = -ENOMEM;
6180 goto fail;
6181 }
6182 vcpu->arch.pio_data = page_address(page);
6183
6184 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6185
6186 r = kvm_mmu_create(vcpu);
6187 if (r < 0)
6188 goto fail_free_pio_data;
6189
6190 if (irqchip_in_kernel(kvm)) {
6191 r = kvm_create_lapic(vcpu);
6192 if (r < 0)
6193 goto fail_mmu_destroy;
6194 }
6195
6196 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6197 GFP_KERNEL);
6198 if (!vcpu->arch.mce_banks) {
6199 r = -ENOMEM;
6200 goto fail_free_lapic;
6201 }
6202 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6203
6204 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6205 goto fail_free_mce_banks;
6206
6207 kvm_async_pf_hash_reset(vcpu);
6208 kvm_pmu_init(vcpu);
6209
6210 return 0;
6211 fail_free_mce_banks:
6212 kfree(vcpu->arch.mce_banks);
6213 fail_free_lapic:
6214 kvm_free_lapic(vcpu);
6215 fail_mmu_destroy:
6216 kvm_mmu_destroy(vcpu);
6217 fail_free_pio_data:
6218 free_page((unsigned long)vcpu->arch.pio_data);
6219 fail:
6220 return r;
6221 }
6222
6223 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6224 {
6225 int idx;
6226
6227 kvm_pmu_destroy(vcpu);
6228 kfree(vcpu->arch.mce_banks);
6229 kvm_free_lapic(vcpu);
6230 idx = srcu_read_lock(&vcpu->kvm->srcu);
6231 kvm_mmu_destroy(vcpu);
6232 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6233 free_page((unsigned long)vcpu->arch.pio_data);
6234 }
6235
6236 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6237 {
6238 if (type)
6239 return -EINVAL;
6240
6241 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6242 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6243
6244 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6245 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6246
6247 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6248
6249 return 0;
6250 }
6251
6252 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6253 {
6254 vcpu_load(vcpu);
6255 kvm_mmu_unload(vcpu);
6256 vcpu_put(vcpu);
6257 }
6258
6259 static void kvm_free_vcpus(struct kvm *kvm)
6260 {
6261 unsigned int i;
6262 struct kvm_vcpu *vcpu;
6263
6264 /*
6265 * Unpin any mmu pages first.
6266 */
6267 kvm_for_each_vcpu(i, vcpu, kvm) {
6268 kvm_clear_async_pf_completion_queue(vcpu);
6269 kvm_unload_vcpu_mmu(vcpu);
6270 }
6271 kvm_for_each_vcpu(i, vcpu, kvm)
6272 kvm_arch_vcpu_free(vcpu);
6273
6274 mutex_lock(&kvm->lock);
6275 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6276 kvm->vcpus[i] = NULL;
6277
6278 atomic_set(&kvm->online_vcpus, 0);
6279 mutex_unlock(&kvm->lock);
6280 }
6281
6282 void kvm_arch_sync_events(struct kvm *kvm)
6283 {
6284 kvm_free_all_assigned_devices(kvm);
6285 kvm_free_pit(kvm);
6286 }
6287
6288 void kvm_arch_destroy_vm(struct kvm *kvm)
6289 {
6290 kvm_iommu_unmap_guest(kvm);
6291 kfree(kvm->arch.vpic);
6292 kfree(kvm->arch.vioapic);
6293 kvm_free_vcpus(kvm);
6294 if (kvm->arch.apic_access_page)
6295 put_page(kvm->arch.apic_access_page);
6296 if (kvm->arch.ept_identity_pagetable)
6297 put_page(kvm->arch.ept_identity_pagetable);
6298 }
6299
6300 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6301 struct kvm_memory_slot *dont)
6302 {
6303 int i;
6304
6305 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6306 if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) {
6307 vfree(free->arch.lpage_info[i]);
6308 free->arch.lpage_info[i] = NULL;
6309 }
6310 }
6311 }
6312
6313 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6314 {
6315 int i;
6316
6317 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6318 unsigned long ugfn;
6319 int lpages;
6320 int level = i + 2;
6321
6322 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6323 slot->base_gfn, level) + 1;
6324
6325 slot->arch.lpage_info[i] =
6326 vzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
6327 if (!slot->arch.lpage_info[i])
6328 goto out_free;
6329
6330 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6331 slot->arch.lpage_info[i][0].write_count = 1;
6332 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6333 slot->arch.lpage_info[i][lpages - 1].write_count = 1;
6334 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6335 /*
6336 * If the gfn and userspace address are not aligned wrt each
6337 * other, or if explicitly asked to, disable large page
6338 * support for this slot
6339 */
6340 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6341 !kvm_largepages_enabled()) {
6342 unsigned long j;
6343
6344 for (j = 0; j < lpages; ++j)
6345 slot->arch.lpage_info[i][j].write_count = 1;
6346 }
6347 }
6348
6349 return 0;
6350
6351 out_free:
6352 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6353 vfree(slot->arch.lpage_info[i]);
6354 slot->arch.lpage_info[i] = NULL;
6355 }
6356 return -ENOMEM;
6357 }
6358
6359 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6360 struct kvm_memory_slot *memslot,
6361 struct kvm_memory_slot old,
6362 struct kvm_userspace_memory_region *mem,
6363 int user_alloc)
6364 {
6365 int npages = memslot->npages;
6366 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6367
6368 /* Prevent internal slot pages from being moved by fork()/COW. */
6369 if (memslot->id >= KVM_MEMORY_SLOTS)
6370 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6371
6372 /*To keep backward compatibility with older userspace,
6373 *x86 needs to hanlde !user_alloc case.
6374 */
6375 if (!user_alloc) {
6376 if (npages && !old.rmap) {
6377 unsigned long userspace_addr;
6378
6379 userspace_addr = vm_mmap(NULL, 0,
6380 npages * PAGE_SIZE,
6381 PROT_READ | PROT_WRITE,
6382 map_flags,
6383 0);
6384
6385 if (IS_ERR((void *)userspace_addr))
6386 return PTR_ERR((void *)userspace_addr);
6387
6388 memslot->userspace_addr = userspace_addr;
6389 }
6390 }
6391
6392
6393 return 0;
6394 }
6395
6396 void kvm_arch_commit_memory_region(struct kvm *kvm,
6397 struct kvm_userspace_memory_region *mem,
6398 struct kvm_memory_slot old,
6399 int user_alloc)
6400 {
6401
6402 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6403
6404 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6405 int ret;
6406
6407 ret = vm_munmap(old.userspace_addr,
6408 old.npages * PAGE_SIZE);
6409 if (ret < 0)
6410 printk(KERN_WARNING
6411 "kvm_vm_ioctl_set_memory_region: "
6412 "failed to munmap memory\n");
6413 }
6414
6415 if (!kvm->arch.n_requested_mmu_pages)
6416 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6417
6418 spin_lock(&kvm->mmu_lock);
6419 if (nr_mmu_pages)
6420 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6421 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6422 spin_unlock(&kvm->mmu_lock);
6423 }
6424
6425 void kvm_arch_flush_shadow(struct kvm *kvm)
6426 {
6427 kvm_mmu_zap_all(kvm);
6428 kvm_reload_remote_mmus(kvm);
6429 }
6430
6431 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6432 {
6433 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6434 !vcpu->arch.apf.halted)
6435 || !list_empty_careful(&vcpu->async_pf.done)
6436 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6437 || atomic_read(&vcpu->arch.nmi_queued) ||
6438 (kvm_arch_interrupt_allowed(vcpu) &&
6439 kvm_cpu_has_interrupt(vcpu));
6440 }
6441
6442 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
6443 {
6444 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
6445 }
6446
6447 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6448 {
6449 return kvm_x86_ops->interrupt_allowed(vcpu);
6450 }
6451
6452 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6453 {
6454 unsigned long current_rip = kvm_rip_read(vcpu) +
6455 get_segment_base(vcpu, VCPU_SREG_CS);
6456
6457 return current_rip == linear_rip;
6458 }
6459 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6460
6461 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6462 {
6463 unsigned long rflags;
6464
6465 rflags = kvm_x86_ops->get_rflags(vcpu);
6466 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6467 rflags &= ~X86_EFLAGS_TF;
6468 return rflags;
6469 }
6470 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6471
6472 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6473 {
6474 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6475 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6476 rflags |= X86_EFLAGS_TF;
6477 kvm_x86_ops->set_rflags(vcpu, rflags);
6478 kvm_make_request(KVM_REQ_EVENT, vcpu);
6479 }
6480 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6481
6482 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6483 {
6484 int r;
6485
6486 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6487 is_error_page(work->page))
6488 return;
6489
6490 r = kvm_mmu_reload(vcpu);
6491 if (unlikely(r))
6492 return;
6493
6494 if (!vcpu->arch.mmu.direct_map &&
6495 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6496 return;
6497
6498 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6499 }
6500
6501 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6502 {
6503 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6504 }
6505
6506 static inline u32 kvm_async_pf_next_probe(u32 key)
6507 {
6508 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6509 }
6510
6511 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6512 {
6513 u32 key = kvm_async_pf_hash_fn(gfn);
6514
6515 while (vcpu->arch.apf.gfns[key] != ~0)
6516 key = kvm_async_pf_next_probe(key);
6517
6518 vcpu->arch.apf.gfns[key] = gfn;
6519 }
6520
6521 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6522 {
6523 int i;
6524 u32 key = kvm_async_pf_hash_fn(gfn);
6525
6526 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6527 (vcpu->arch.apf.gfns[key] != gfn &&
6528 vcpu->arch.apf.gfns[key] != ~0); i++)
6529 key = kvm_async_pf_next_probe(key);
6530
6531 return key;
6532 }
6533
6534 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6535 {
6536 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6537 }
6538
6539 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6540 {
6541 u32 i, j, k;
6542
6543 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6544 while (true) {
6545 vcpu->arch.apf.gfns[i] = ~0;
6546 do {
6547 j = kvm_async_pf_next_probe(j);
6548 if (vcpu->arch.apf.gfns[j] == ~0)
6549 return;
6550 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6551 /*
6552 * k lies cyclically in ]i,j]
6553 * | i.k.j |
6554 * |....j i.k.| or |.k..j i...|
6555 */
6556 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6557 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6558 i = j;
6559 }
6560 }
6561
6562 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6563 {
6564
6565 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6566 sizeof(val));
6567 }
6568
6569 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6570 struct kvm_async_pf *work)
6571 {
6572 struct x86_exception fault;
6573
6574 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6575 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6576
6577 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6578 (vcpu->arch.apf.send_user_only &&
6579 kvm_x86_ops->get_cpl(vcpu) == 0))
6580 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6581 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6582 fault.vector = PF_VECTOR;
6583 fault.error_code_valid = true;
6584 fault.error_code = 0;
6585 fault.nested_page_fault = false;
6586 fault.address = work->arch.token;
6587 kvm_inject_page_fault(vcpu, &fault);
6588 }
6589 }
6590
6591 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6592 struct kvm_async_pf *work)
6593 {
6594 struct x86_exception fault;
6595
6596 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6597 if (is_error_page(work->page))
6598 work->arch.token = ~0; /* broadcast wakeup */
6599 else
6600 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6601
6602 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6603 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6604 fault.vector = PF_VECTOR;
6605 fault.error_code_valid = true;
6606 fault.error_code = 0;
6607 fault.nested_page_fault = false;
6608 fault.address = work->arch.token;
6609 kvm_inject_page_fault(vcpu, &fault);
6610 }
6611 vcpu->arch.apf.halted = false;
6612 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6613 }
6614
6615 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6616 {
6617 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6618 return true;
6619 else
6620 return !kvm_event_needs_reinjection(vcpu) &&
6621 kvm_x86_ops->interrupt_allowed(vcpu);
6622 }
6623
6624 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6625 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6626 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6627 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6628 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6629 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6630 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6631 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6632 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6633 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6634 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6635 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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