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1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
27 #else
28 #include <linux/kvm_host.h>
29 #define DPRINTF(x...) do {} while (0)
30 #endif
31 #include <linux/module.h>
32 #include <asm/kvm_x86_emulate.h>
33
34 /*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43 /* Operand sizes: 8-bit operands or specified/overridden size. */
44 #define ByteOp (1<<0) /* 8-bit operands. */
45 /* Destination operand type. */
46 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47 #define DstReg (2<<1) /* Register operand. */
48 #define DstMem (3<<1) /* Memory operand. */
49 #define DstMask (3<<1)
50 /* Source operand type. */
51 #define SrcNone (0<<3) /* No source operand. */
52 #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53 #define SrcReg (1<<3) /* Register operand. */
54 #define SrcMem (2<<3) /* Memory operand. */
55 #define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57 #define SrcImm (5<<3) /* Immediate operand. */
58 #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59 #define SrcMask (7<<3)
60 /* Generic ModRM decode. */
61 #define ModRM (1<<6)
62 /* Destination is only written; never read. */
63 #define Mov (1<<7)
64 #define BitOp (1<<8)
65 #define MemAbs (1<<9) /* Memory operand is absolute displacement */
66 #define String (1<<10) /* String instruction (rep capable) */
67 #define Stack (1<<11) /* Stack instruction (push/pop) */
68 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
69 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
70 #define GroupMask 0xff /* Group number stored in bits 0:7 */
71
72 enum {
73 Group1_80, Group1_81, Group1_82, Group1_83,
74 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
75 };
76
77 static u16 opcode_table[256] = {
78 /* 0x00 - 0x07 */
79 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
80 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
81 0, 0, 0, 0,
82 /* 0x08 - 0x0F */
83 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
84 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
85 0, 0, 0, 0,
86 /* 0x10 - 0x17 */
87 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
88 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
89 0, 0, 0, 0,
90 /* 0x18 - 0x1F */
91 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
92 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
93 0, 0, 0, 0,
94 /* 0x20 - 0x27 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
97 SrcImmByte, SrcImm, 0, 0,
98 /* 0x28 - 0x2F */
99 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
100 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
101 0, 0, 0, 0,
102 /* 0x30 - 0x37 */
103 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
105 0, 0, 0, 0,
106 /* 0x38 - 0x3F */
107 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
109 0, 0, 0, 0,
110 /* 0x40 - 0x47 */
111 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
112 /* 0x48 - 0x4F */
113 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
114 /* 0x50 - 0x57 */
115 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
117 /* 0x58 - 0x5F */
118 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
120 /* 0x60 - 0x67 */
121 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
122 0, 0, 0, 0,
123 /* 0x68 - 0x6F */
124 0, 0, ImplicitOps | Mov | Stack, 0,
125 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
127 /* 0x70 - 0x77 */
128 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
130 /* 0x78 - 0x7F */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
133 /* 0x80 - 0x87 */
134 Group | Group1_80, Group | Group1_81,
135 Group | Group1_82, Group | Group1_83,
136 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 /* 0x88 - 0x8F */
139 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
140 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
141 0, ModRM | DstReg, 0, Group | Group1A,
142 /* 0x90 - 0x9F */
143 0, 0, 0, 0, 0, 0, 0, 0,
144 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
145 /* 0xA0 - 0xA7 */
146 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
147 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
148 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
149 ByteOp | ImplicitOps | String, ImplicitOps | String,
150 /* 0xA8 - 0xAF */
151 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
152 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
153 ByteOp | ImplicitOps | String, ImplicitOps | String,
154 /* 0xB0 - 0xBF */
155 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
156 /* 0xC0 - 0xC7 */
157 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
158 0, ImplicitOps | Stack, 0, 0,
159 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
160 /* 0xC8 - 0xCF */
161 0, 0, 0, 0, 0, 0, 0, 0,
162 /* 0xD0 - 0xD7 */
163 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
164 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
165 0, 0, 0, 0,
166 /* 0xD8 - 0xDF */
167 0, 0, 0, 0, 0, 0, 0, 0,
168 /* 0xE0 - 0xE7 */
169 0, 0, 0, 0, 0, 0, 0, 0,
170 /* 0xE8 - 0xEF */
171 ImplicitOps | Stack, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps,
172 0, 0, 0, 0,
173 /* 0xF0 - 0xF7 */
174 0, 0, 0, 0,
175 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
176 /* 0xF8 - 0xFF */
177 ImplicitOps, 0, ImplicitOps, ImplicitOps,
178 0, 0, Group | Group4, Group | Group5,
179 };
180
181 static u16 twobyte_table[256] = {
182 /* 0x00 - 0x0F */
183 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
184 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
185 /* 0x10 - 0x1F */
186 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
187 /* 0x20 - 0x2F */
188 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
189 0, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x30 - 0x3F */
191 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
192 /* 0x40 - 0x47 */
193 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
194 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
195 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
196 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
197 /* 0x48 - 0x4F */
198 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
199 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
200 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
201 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
202 /* 0x50 - 0x5F */
203 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
204 /* 0x60 - 0x6F */
205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
206 /* 0x70 - 0x7F */
207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
208 /* 0x80 - 0x8F */
209 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
210 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
211 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
212 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
213 /* 0x90 - 0x9F */
214 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
215 /* 0xA0 - 0xA7 */
216 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
217 /* 0xA8 - 0xAF */
218 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
219 /* 0xB0 - 0xB7 */
220 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
221 DstMem | SrcReg | ModRM | BitOp,
222 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
223 DstReg | SrcMem16 | ModRM | Mov,
224 /* 0xB8 - 0xBF */
225 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
226 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
227 DstReg | SrcMem16 | ModRM | Mov,
228 /* 0xC0 - 0xCF */
229 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
230 0, 0, 0, 0, 0, 0, 0, 0,
231 /* 0xD0 - 0xDF */
232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
233 /* 0xE0 - 0xEF */
234 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
235 /* 0xF0 - 0xFF */
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
237 };
238
239 static u16 group_table[] = {
240 [Group1_80*8] =
241 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
242 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
243 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
244 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
245 [Group1_81*8] =
246 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
247 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
248 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
249 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
250 [Group1_82*8] =
251 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
252 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
253 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
254 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
255 [Group1_83*8] =
256 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
257 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
258 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
259 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
260 [Group1A*8] =
261 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
262 [Group3_Byte*8] =
263 ByteOp | SrcImm | DstMem | ModRM, 0,
264 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
265 0, 0, 0, 0,
266 [Group3*8] =
267 DstMem | SrcImm | ModRM | SrcImm, 0,
268 DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
269 0, 0, 0, 0,
270 [Group4*8] =
271 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
272 0, 0, 0, 0, 0, 0,
273 [Group5*8] =
274 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
275 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
276 [Group7*8] =
277 0, 0, ModRM | SrcMem, ModRM | SrcMem,
278 SrcNone | ModRM | DstMem | Mov, 0,
279 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
280 };
281
282 static u16 group2_table[] = {
283 [Group7*8] =
284 SrcNone | ModRM, 0, 0, 0,
285 SrcNone | ModRM | DstMem | Mov, 0,
286 SrcMem16 | ModRM | Mov, 0,
287 };
288
289 /* EFLAGS bit definitions. */
290 #define EFLG_OF (1<<11)
291 #define EFLG_DF (1<<10)
292 #define EFLG_SF (1<<7)
293 #define EFLG_ZF (1<<6)
294 #define EFLG_AF (1<<4)
295 #define EFLG_PF (1<<2)
296 #define EFLG_CF (1<<0)
297
298 /*
299 * Instruction emulation:
300 * Most instructions are emulated directly via a fragment of inline assembly
301 * code. This allows us to save/restore EFLAGS and thus very easily pick up
302 * any modified flags.
303 */
304
305 #if defined(CONFIG_X86_64)
306 #define _LO32 "k" /* force 32-bit operand */
307 #define _STK "%%rsp" /* stack pointer */
308 #elif defined(__i386__)
309 #define _LO32 "" /* force 32-bit operand */
310 #define _STK "%%esp" /* stack pointer */
311 #endif
312
313 /*
314 * These EFLAGS bits are restored from saved value during emulation, and
315 * any changes are written back to the saved value after emulation.
316 */
317 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
318
319 /* Before executing instruction: restore necessary bits in EFLAGS. */
320 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
321 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
322 "movl %"_sav",%"_LO32 _tmp"; " \
323 "push %"_tmp"; " \
324 "push %"_tmp"; " \
325 "movl %"_msk",%"_LO32 _tmp"; " \
326 "andl %"_LO32 _tmp",("_STK"); " \
327 "pushf; " \
328 "notl %"_LO32 _tmp"; " \
329 "andl %"_LO32 _tmp",("_STK"); " \
330 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
331 "pop %"_tmp"; " \
332 "orl %"_LO32 _tmp",("_STK"); " \
333 "popf; " \
334 "pop %"_sav"; "
335
336 /* After executing instruction: write-back necessary bits in EFLAGS. */
337 #define _POST_EFLAGS(_sav, _msk, _tmp) \
338 /* _sav |= EFLAGS & _msk; */ \
339 "pushf; " \
340 "pop %"_tmp"; " \
341 "andl %"_msk",%"_LO32 _tmp"; " \
342 "orl %"_LO32 _tmp",%"_sav"; "
343
344 /* Raw emulation: instruction has two explicit operands. */
345 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
346 do { \
347 unsigned long _tmp; \
348 \
349 switch ((_dst).bytes) { \
350 case 2: \
351 __asm__ __volatile__ ( \
352 _PRE_EFLAGS("0", "4", "2") \
353 _op"w %"_wx"3,%1; " \
354 _POST_EFLAGS("0", "4", "2") \
355 : "=m" (_eflags), "=m" ((_dst).val), \
356 "=&r" (_tmp) \
357 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
358 break; \
359 case 4: \
360 __asm__ __volatile__ ( \
361 _PRE_EFLAGS("0", "4", "2") \
362 _op"l %"_lx"3,%1; " \
363 _POST_EFLAGS("0", "4", "2") \
364 : "=m" (_eflags), "=m" ((_dst).val), \
365 "=&r" (_tmp) \
366 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
367 break; \
368 case 8: \
369 __emulate_2op_8byte(_op, _src, _dst, \
370 _eflags, _qx, _qy); \
371 break; \
372 } \
373 } while (0)
374
375 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
376 do { \
377 unsigned long __tmp; \
378 switch ((_dst).bytes) { \
379 case 1: \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0", "4", "2") \
382 _op"b %"_bx"3,%1; " \
383 _POST_EFLAGS("0", "4", "2") \
384 : "=m" (_eflags), "=m" ((_dst).val), \
385 "=&r" (__tmp) \
386 : _by ((_src).val), "i" (EFLAGS_MASK)); \
387 break; \
388 default: \
389 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
390 _wx, _wy, _lx, _ly, _qx, _qy); \
391 break; \
392 } \
393 } while (0)
394
395 /* Source operand is byte-sized and may be restricted to just %cl. */
396 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
397 __emulate_2op(_op, _src, _dst, _eflags, \
398 "b", "c", "b", "c", "b", "c", "b", "c")
399
400 /* Source operand is byte, word, long or quad sized. */
401 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
402 __emulate_2op(_op, _src, _dst, _eflags, \
403 "b", "q", "w", "r", _LO32, "r", "", "r")
404
405 /* Source operand is word, long or quad sized. */
406 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
407 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
408 "w", "r", _LO32, "r", "", "r")
409
410 /* Instruction has only one explicit operand (no source operand). */
411 #define emulate_1op(_op, _dst, _eflags) \
412 do { \
413 unsigned long _tmp; \
414 \
415 switch ((_dst).bytes) { \
416 case 1: \
417 __asm__ __volatile__ ( \
418 _PRE_EFLAGS("0", "3", "2") \
419 _op"b %1; " \
420 _POST_EFLAGS("0", "3", "2") \
421 : "=m" (_eflags), "=m" ((_dst).val), \
422 "=&r" (_tmp) \
423 : "i" (EFLAGS_MASK)); \
424 break; \
425 case 2: \
426 __asm__ __volatile__ ( \
427 _PRE_EFLAGS("0", "3", "2") \
428 _op"w %1; " \
429 _POST_EFLAGS("0", "3", "2") \
430 : "=m" (_eflags), "=m" ((_dst).val), \
431 "=&r" (_tmp) \
432 : "i" (EFLAGS_MASK)); \
433 break; \
434 case 4: \
435 __asm__ __volatile__ ( \
436 _PRE_EFLAGS("0", "3", "2") \
437 _op"l %1; " \
438 _POST_EFLAGS("0", "3", "2") \
439 : "=m" (_eflags), "=m" ((_dst).val), \
440 "=&r" (_tmp) \
441 : "i" (EFLAGS_MASK)); \
442 break; \
443 case 8: \
444 __emulate_1op_8byte(_op, _dst, _eflags); \
445 break; \
446 } \
447 } while (0)
448
449 /* Emulate an instruction with quadword operands (x86/64 only). */
450 #if defined(CONFIG_X86_64)
451 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
452 do { \
453 __asm__ __volatile__ ( \
454 _PRE_EFLAGS("0", "4", "2") \
455 _op"q %"_qx"3,%1; " \
456 _POST_EFLAGS("0", "4", "2") \
457 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
458 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
459 } while (0)
460
461 #define __emulate_1op_8byte(_op, _dst, _eflags) \
462 do { \
463 __asm__ __volatile__ ( \
464 _PRE_EFLAGS("0", "3", "2") \
465 _op"q %1; " \
466 _POST_EFLAGS("0", "3", "2") \
467 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
468 : "i" (EFLAGS_MASK)); \
469 } while (0)
470
471 #elif defined(__i386__)
472 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
473 #define __emulate_1op_8byte(_op, _dst, _eflags)
474 #endif /* __i386__ */
475
476 /* Fetch next part of the instruction being emulated. */
477 #define insn_fetch(_type, _size, _eip) \
478 ({ unsigned long _x; \
479 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
480 if (rc != 0) \
481 goto done; \
482 (_eip) += (_size); \
483 (_type)_x; \
484 })
485
486 static inline unsigned long ad_mask(struct decode_cache *c)
487 {
488 return (1UL << (c->ad_bytes << 3)) - 1;
489 }
490
491 /* Access/update address held in a register, based on addressing mode. */
492 static inline unsigned long
493 address_mask(struct decode_cache *c, unsigned long reg)
494 {
495 if (c->ad_bytes == sizeof(unsigned long))
496 return reg;
497 else
498 return reg & ad_mask(c);
499 }
500
501 static inline unsigned long
502 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
503 {
504 return base + address_mask(c, reg);
505 }
506
507 static inline void
508 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
509 {
510 if (c->ad_bytes == sizeof(unsigned long))
511 *reg += inc;
512 else
513 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
514 }
515
516 static inline void jmp_rel(struct decode_cache *c, int rel)
517 {
518 register_address_increment(c, &c->eip, rel);
519 }
520
521 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
522 struct x86_emulate_ops *ops,
523 unsigned long linear, u8 *dest)
524 {
525 struct fetch_cache *fc = &ctxt->decode.fetch;
526 int rc;
527 int size;
528
529 if (linear < fc->start || linear >= fc->end) {
530 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
531 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
532 if (rc)
533 return rc;
534 fc->start = linear;
535 fc->end = linear + size;
536 }
537 *dest = fc->data[linear - fc->start];
538 return 0;
539 }
540
541 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
542 struct x86_emulate_ops *ops,
543 unsigned long eip, void *dest, unsigned size)
544 {
545 int rc = 0;
546
547 eip += ctxt->cs_base;
548 while (size--) {
549 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
550 if (rc)
551 return rc;
552 }
553 return 0;
554 }
555
556 /*
557 * Given the 'reg' portion of a ModRM byte, and a register block, return a
558 * pointer into the block that addresses the relevant register.
559 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
560 */
561 static void *decode_register(u8 modrm_reg, unsigned long *regs,
562 int highbyte_regs)
563 {
564 void *p;
565
566 p = &regs[modrm_reg];
567 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
568 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
569 return p;
570 }
571
572 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
573 struct x86_emulate_ops *ops,
574 void *ptr,
575 u16 *size, unsigned long *address, int op_bytes)
576 {
577 int rc;
578
579 if (op_bytes == 2)
580 op_bytes = 3;
581 *address = 0;
582 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
583 ctxt->vcpu);
584 if (rc)
585 return rc;
586 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
587 ctxt->vcpu);
588 return rc;
589 }
590
591 static int test_cc(unsigned int condition, unsigned int flags)
592 {
593 int rc = 0;
594
595 switch ((condition & 15) >> 1) {
596 case 0: /* o */
597 rc |= (flags & EFLG_OF);
598 break;
599 case 1: /* b/c/nae */
600 rc |= (flags & EFLG_CF);
601 break;
602 case 2: /* z/e */
603 rc |= (flags & EFLG_ZF);
604 break;
605 case 3: /* be/na */
606 rc |= (flags & (EFLG_CF|EFLG_ZF));
607 break;
608 case 4: /* s */
609 rc |= (flags & EFLG_SF);
610 break;
611 case 5: /* p/pe */
612 rc |= (flags & EFLG_PF);
613 break;
614 case 7: /* le/ng */
615 rc |= (flags & EFLG_ZF);
616 /* fall through */
617 case 6: /* l/nge */
618 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
619 break;
620 }
621
622 /* Odd condition identifiers (lsb == 1) have inverted sense. */
623 return (!!rc ^ (condition & 1));
624 }
625
626 static void decode_register_operand(struct operand *op,
627 struct decode_cache *c,
628 int inhibit_bytereg)
629 {
630 unsigned reg = c->modrm_reg;
631 int highbyte_regs = c->rex_prefix == 0;
632
633 if (!(c->d & ModRM))
634 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
635 op->type = OP_REG;
636 if ((c->d & ByteOp) && !inhibit_bytereg) {
637 op->ptr = decode_register(reg, c->regs, highbyte_regs);
638 op->val = *(u8 *)op->ptr;
639 op->bytes = 1;
640 } else {
641 op->ptr = decode_register(reg, c->regs, 0);
642 op->bytes = c->op_bytes;
643 switch (op->bytes) {
644 case 2:
645 op->val = *(u16 *)op->ptr;
646 break;
647 case 4:
648 op->val = *(u32 *)op->ptr;
649 break;
650 case 8:
651 op->val = *(u64 *) op->ptr;
652 break;
653 }
654 }
655 op->orig_val = op->val;
656 }
657
658 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
659 struct x86_emulate_ops *ops)
660 {
661 struct decode_cache *c = &ctxt->decode;
662 u8 sib;
663 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
664 int rc = 0;
665
666 if (c->rex_prefix) {
667 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
668 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
669 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
670 }
671
672 c->modrm = insn_fetch(u8, 1, c->eip);
673 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
674 c->modrm_reg |= (c->modrm & 0x38) >> 3;
675 c->modrm_rm |= (c->modrm & 0x07);
676 c->modrm_ea = 0;
677 c->use_modrm_ea = 1;
678
679 if (c->modrm_mod == 3) {
680 c->modrm_val = *(unsigned long *)
681 decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
682 return rc;
683 }
684
685 if (c->ad_bytes == 2) {
686 unsigned bx = c->regs[VCPU_REGS_RBX];
687 unsigned bp = c->regs[VCPU_REGS_RBP];
688 unsigned si = c->regs[VCPU_REGS_RSI];
689 unsigned di = c->regs[VCPU_REGS_RDI];
690
691 /* 16-bit ModR/M decode. */
692 switch (c->modrm_mod) {
693 case 0:
694 if (c->modrm_rm == 6)
695 c->modrm_ea += insn_fetch(u16, 2, c->eip);
696 break;
697 case 1:
698 c->modrm_ea += insn_fetch(s8, 1, c->eip);
699 break;
700 case 2:
701 c->modrm_ea += insn_fetch(u16, 2, c->eip);
702 break;
703 }
704 switch (c->modrm_rm) {
705 case 0:
706 c->modrm_ea += bx + si;
707 break;
708 case 1:
709 c->modrm_ea += bx + di;
710 break;
711 case 2:
712 c->modrm_ea += bp + si;
713 break;
714 case 3:
715 c->modrm_ea += bp + di;
716 break;
717 case 4:
718 c->modrm_ea += si;
719 break;
720 case 5:
721 c->modrm_ea += di;
722 break;
723 case 6:
724 if (c->modrm_mod != 0)
725 c->modrm_ea += bp;
726 break;
727 case 7:
728 c->modrm_ea += bx;
729 break;
730 }
731 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
732 (c->modrm_rm == 6 && c->modrm_mod != 0))
733 if (!c->override_base)
734 c->override_base = &ctxt->ss_base;
735 c->modrm_ea = (u16)c->modrm_ea;
736 } else {
737 /* 32/64-bit ModR/M decode. */
738 switch (c->modrm_rm) {
739 case 4:
740 case 12:
741 sib = insn_fetch(u8, 1, c->eip);
742 index_reg |= (sib >> 3) & 7;
743 base_reg |= sib & 7;
744 scale = sib >> 6;
745
746 switch (base_reg) {
747 case 5:
748 if (c->modrm_mod != 0)
749 c->modrm_ea += c->regs[base_reg];
750 else
751 c->modrm_ea +=
752 insn_fetch(s32, 4, c->eip);
753 break;
754 default:
755 c->modrm_ea += c->regs[base_reg];
756 }
757 switch (index_reg) {
758 case 4:
759 break;
760 default:
761 c->modrm_ea += c->regs[index_reg] << scale;
762 }
763 break;
764 case 5:
765 if (c->modrm_mod != 0)
766 c->modrm_ea += c->regs[c->modrm_rm];
767 else if (ctxt->mode == X86EMUL_MODE_PROT64)
768 rip_relative = 1;
769 break;
770 default:
771 c->modrm_ea += c->regs[c->modrm_rm];
772 break;
773 }
774 switch (c->modrm_mod) {
775 case 0:
776 if (c->modrm_rm == 5)
777 c->modrm_ea += insn_fetch(s32, 4, c->eip);
778 break;
779 case 1:
780 c->modrm_ea += insn_fetch(s8, 1, c->eip);
781 break;
782 case 2:
783 c->modrm_ea += insn_fetch(s32, 4, c->eip);
784 break;
785 }
786 }
787 if (rip_relative) {
788 c->modrm_ea += c->eip;
789 switch (c->d & SrcMask) {
790 case SrcImmByte:
791 c->modrm_ea += 1;
792 break;
793 case SrcImm:
794 if (c->d & ByteOp)
795 c->modrm_ea += 1;
796 else
797 if (c->op_bytes == 8)
798 c->modrm_ea += 4;
799 else
800 c->modrm_ea += c->op_bytes;
801 }
802 }
803 done:
804 return rc;
805 }
806
807 static int decode_abs(struct x86_emulate_ctxt *ctxt,
808 struct x86_emulate_ops *ops)
809 {
810 struct decode_cache *c = &ctxt->decode;
811 int rc = 0;
812
813 switch (c->ad_bytes) {
814 case 2:
815 c->modrm_ea = insn_fetch(u16, 2, c->eip);
816 break;
817 case 4:
818 c->modrm_ea = insn_fetch(u32, 4, c->eip);
819 break;
820 case 8:
821 c->modrm_ea = insn_fetch(u64, 8, c->eip);
822 break;
823 }
824 done:
825 return rc;
826 }
827
828 int
829 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
830 {
831 struct decode_cache *c = &ctxt->decode;
832 int rc = 0;
833 int mode = ctxt->mode;
834 int def_op_bytes, def_ad_bytes, group;
835
836 /* Shadow copy of register state. Committed on successful emulation. */
837
838 memset(c, 0, sizeof(struct decode_cache));
839 c->eip = ctxt->vcpu->arch.rip;
840 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
841
842 switch (mode) {
843 case X86EMUL_MODE_REAL:
844 case X86EMUL_MODE_PROT16:
845 def_op_bytes = def_ad_bytes = 2;
846 break;
847 case X86EMUL_MODE_PROT32:
848 def_op_bytes = def_ad_bytes = 4;
849 break;
850 #ifdef CONFIG_X86_64
851 case X86EMUL_MODE_PROT64:
852 def_op_bytes = 4;
853 def_ad_bytes = 8;
854 break;
855 #endif
856 default:
857 return -1;
858 }
859
860 c->op_bytes = def_op_bytes;
861 c->ad_bytes = def_ad_bytes;
862
863 /* Legacy prefixes. */
864 for (;;) {
865 switch (c->b = insn_fetch(u8, 1, c->eip)) {
866 case 0x66: /* operand-size override */
867 /* switch between 2/4 bytes */
868 c->op_bytes = def_op_bytes ^ 6;
869 break;
870 case 0x67: /* address-size override */
871 if (mode == X86EMUL_MODE_PROT64)
872 /* switch between 4/8 bytes */
873 c->ad_bytes = def_ad_bytes ^ 12;
874 else
875 /* switch between 2/4 bytes */
876 c->ad_bytes = def_ad_bytes ^ 6;
877 break;
878 case 0x2e: /* CS override */
879 c->override_base = &ctxt->cs_base;
880 break;
881 case 0x3e: /* DS override */
882 c->override_base = &ctxt->ds_base;
883 break;
884 case 0x26: /* ES override */
885 c->override_base = &ctxt->es_base;
886 break;
887 case 0x64: /* FS override */
888 c->override_base = &ctxt->fs_base;
889 break;
890 case 0x65: /* GS override */
891 c->override_base = &ctxt->gs_base;
892 break;
893 case 0x36: /* SS override */
894 c->override_base = &ctxt->ss_base;
895 break;
896 case 0x40 ... 0x4f: /* REX */
897 if (mode != X86EMUL_MODE_PROT64)
898 goto done_prefixes;
899 c->rex_prefix = c->b;
900 continue;
901 case 0xf0: /* LOCK */
902 c->lock_prefix = 1;
903 break;
904 case 0xf2: /* REPNE/REPNZ */
905 c->rep_prefix = REPNE_PREFIX;
906 break;
907 case 0xf3: /* REP/REPE/REPZ */
908 c->rep_prefix = REPE_PREFIX;
909 break;
910 default:
911 goto done_prefixes;
912 }
913
914 /* Any legacy prefix after a REX prefix nullifies its effect. */
915
916 c->rex_prefix = 0;
917 }
918
919 done_prefixes:
920
921 /* REX prefix. */
922 if (c->rex_prefix)
923 if (c->rex_prefix & 8)
924 c->op_bytes = 8; /* REX.W */
925
926 /* Opcode byte(s). */
927 c->d = opcode_table[c->b];
928 if (c->d == 0) {
929 /* Two-byte opcode? */
930 if (c->b == 0x0f) {
931 c->twobyte = 1;
932 c->b = insn_fetch(u8, 1, c->eip);
933 c->d = twobyte_table[c->b];
934 }
935 }
936
937 if (c->d & Group) {
938 group = c->d & GroupMask;
939 c->modrm = insn_fetch(u8, 1, c->eip);
940 --c->eip;
941
942 group = (group << 3) + ((c->modrm >> 3) & 7);
943 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
944 c->d = group2_table[group];
945 else
946 c->d = group_table[group];
947 }
948
949 /* Unrecognised? */
950 if (c->d == 0) {
951 DPRINTF("Cannot emulate %02x\n", c->b);
952 return -1;
953 }
954
955 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
956 c->op_bytes = 8;
957
958 /* ModRM and SIB bytes. */
959 if (c->d & ModRM)
960 rc = decode_modrm(ctxt, ops);
961 else if (c->d & MemAbs)
962 rc = decode_abs(ctxt, ops);
963 if (rc)
964 goto done;
965
966 if (!c->override_base)
967 c->override_base = &ctxt->ds_base;
968 if (mode == X86EMUL_MODE_PROT64 &&
969 c->override_base != &ctxt->fs_base &&
970 c->override_base != &ctxt->gs_base)
971 c->override_base = NULL;
972
973 if (c->override_base)
974 c->modrm_ea += *c->override_base;
975
976 if (c->ad_bytes != 8)
977 c->modrm_ea = (u32)c->modrm_ea;
978 /*
979 * Decode and fetch the source operand: register, memory
980 * or immediate.
981 */
982 switch (c->d & SrcMask) {
983 case SrcNone:
984 break;
985 case SrcReg:
986 decode_register_operand(&c->src, c, 0);
987 break;
988 case SrcMem16:
989 c->src.bytes = 2;
990 goto srcmem_common;
991 case SrcMem32:
992 c->src.bytes = 4;
993 goto srcmem_common;
994 case SrcMem:
995 c->src.bytes = (c->d & ByteOp) ? 1 :
996 c->op_bytes;
997 /* Don't fetch the address for invlpg: it could be unmapped. */
998 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
999 break;
1000 srcmem_common:
1001 /*
1002 * For instructions with a ModR/M byte, switch to register
1003 * access if Mod = 3.
1004 */
1005 if ((c->d & ModRM) && c->modrm_mod == 3) {
1006 c->src.type = OP_REG;
1007 c->src.val = c->modrm_val;
1008 break;
1009 }
1010 c->src.type = OP_MEM;
1011 break;
1012 case SrcImm:
1013 c->src.type = OP_IMM;
1014 c->src.ptr = (unsigned long *)c->eip;
1015 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1016 if (c->src.bytes == 8)
1017 c->src.bytes = 4;
1018 /* NB. Immediates are sign-extended as necessary. */
1019 switch (c->src.bytes) {
1020 case 1:
1021 c->src.val = insn_fetch(s8, 1, c->eip);
1022 break;
1023 case 2:
1024 c->src.val = insn_fetch(s16, 2, c->eip);
1025 break;
1026 case 4:
1027 c->src.val = insn_fetch(s32, 4, c->eip);
1028 break;
1029 }
1030 break;
1031 case SrcImmByte:
1032 c->src.type = OP_IMM;
1033 c->src.ptr = (unsigned long *)c->eip;
1034 c->src.bytes = 1;
1035 c->src.val = insn_fetch(s8, 1, c->eip);
1036 break;
1037 }
1038
1039 /* Decode and fetch the destination operand: register or memory. */
1040 switch (c->d & DstMask) {
1041 case ImplicitOps:
1042 /* Special instructions do their own operand decoding. */
1043 return 0;
1044 case DstReg:
1045 decode_register_operand(&c->dst, c,
1046 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1047 break;
1048 case DstMem:
1049 if ((c->d & ModRM) && c->modrm_mod == 3) {
1050 c->dst.type = OP_REG;
1051 c->dst.val = c->dst.orig_val = c->modrm_val;
1052 break;
1053 }
1054 c->dst.type = OP_MEM;
1055 break;
1056 }
1057
1058 done:
1059 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1060 }
1061
1062 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1063 {
1064 struct decode_cache *c = &ctxt->decode;
1065
1066 c->dst.type = OP_MEM;
1067 c->dst.bytes = c->op_bytes;
1068 c->dst.val = c->src.val;
1069 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1070 c->dst.ptr = (void *) register_address(c, ctxt->ss_base,
1071 c->regs[VCPU_REGS_RSP]);
1072 }
1073
1074 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1075 struct x86_emulate_ops *ops)
1076 {
1077 struct decode_cache *c = &ctxt->decode;
1078 int rc;
1079
1080 rc = ops->read_std(register_address(c, ctxt->ss_base,
1081 c->regs[VCPU_REGS_RSP]),
1082 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1083 if (rc != 0)
1084 return rc;
1085
1086 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
1087
1088 return 0;
1089 }
1090
1091 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1092 {
1093 struct decode_cache *c = &ctxt->decode;
1094 switch (c->modrm_reg) {
1095 case 0: /* rol */
1096 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1097 break;
1098 case 1: /* ror */
1099 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1100 break;
1101 case 2: /* rcl */
1102 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1103 break;
1104 case 3: /* rcr */
1105 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1106 break;
1107 case 4: /* sal/shl */
1108 case 6: /* sal/shl */
1109 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1110 break;
1111 case 5: /* shr */
1112 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1113 break;
1114 case 7: /* sar */
1115 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1116 break;
1117 }
1118 }
1119
1120 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1121 struct x86_emulate_ops *ops)
1122 {
1123 struct decode_cache *c = &ctxt->decode;
1124 int rc = 0;
1125
1126 switch (c->modrm_reg) {
1127 case 0 ... 1: /* test */
1128 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1129 break;
1130 case 2: /* not */
1131 c->dst.val = ~c->dst.val;
1132 break;
1133 case 3: /* neg */
1134 emulate_1op("neg", c->dst, ctxt->eflags);
1135 break;
1136 default:
1137 DPRINTF("Cannot emulate %02x\n", c->b);
1138 rc = X86EMUL_UNHANDLEABLE;
1139 break;
1140 }
1141 return rc;
1142 }
1143
1144 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1145 struct x86_emulate_ops *ops)
1146 {
1147 struct decode_cache *c = &ctxt->decode;
1148
1149 switch (c->modrm_reg) {
1150 case 0: /* inc */
1151 emulate_1op("inc", c->dst, ctxt->eflags);
1152 break;
1153 case 1: /* dec */
1154 emulate_1op("dec", c->dst, ctxt->eflags);
1155 break;
1156 case 4: /* jmp abs */
1157 c->eip = c->src.val;
1158 break;
1159 case 6: /* push */
1160 emulate_push(ctxt);
1161 break;
1162 }
1163 return 0;
1164 }
1165
1166 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1167 struct x86_emulate_ops *ops,
1168 unsigned long memop)
1169 {
1170 struct decode_cache *c = &ctxt->decode;
1171 u64 old, new;
1172 int rc;
1173
1174 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
1175 if (rc != 0)
1176 return rc;
1177
1178 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1179 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1180
1181 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1182 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1183 ctxt->eflags &= ~EFLG_ZF;
1184
1185 } else {
1186 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1187 (u32) c->regs[VCPU_REGS_RBX];
1188
1189 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
1190 if (rc != 0)
1191 return rc;
1192 ctxt->eflags |= EFLG_ZF;
1193 }
1194 return 0;
1195 }
1196
1197 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1198 struct x86_emulate_ops *ops)
1199 {
1200 int rc;
1201 struct decode_cache *c = &ctxt->decode;
1202
1203 switch (c->dst.type) {
1204 case OP_REG:
1205 /* The 4-byte case *is* correct:
1206 * in 64-bit mode we zero-extend.
1207 */
1208 switch (c->dst.bytes) {
1209 case 1:
1210 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1211 break;
1212 case 2:
1213 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1214 break;
1215 case 4:
1216 *c->dst.ptr = (u32)c->dst.val;
1217 break; /* 64b: zero-ext */
1218 case 8:
1219 *c->dst.ptr = c->dst.val;
1220 break;
1221 }
1222 break;
1223 case OP_MEM:
1224 if (c->lock_prefix)
1225 rc = ops->cmpxchg_emulated(
1226 (unsigned long)c->dst.ptr,
1227 &c->dst.orig_val,
1228 &c->dst.val,
1229 c->dst.bytes,
1230 ctxt->vcpu);
1231 else
1232 rc = ops->write_emulated(
1233 (unsigned long)c->dst.ptr,
1234 &c->dst.val,
1235 c->dst.bytes,
1236 ctxt->vcpu);
1237 if (rc != 0)
1238 return rc;
1239 break;
1240 case OP_NONE:
1241 /* no writeback */
1242 break;
1243 default:
1244 break;
1245 }
1246 return 0;
1247 }
1248
1249 int
1250 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1251 {
1252 unsigned long memop = 0;
1253 u64 msr_data;
1254 unsigned long saved_eip = 0;
1255 struct decode_cache *c = &ctxt->decode;
1256 int rc = 0;
1257
1258 /* Shadow copy of register state. Committed on successful emulation.
1259 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1260 * modify them.
1261 */
1262
1263 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
1264 saved_eip = c->eip;
1265
1266 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
1267 memop = c->modrm_ea;
1268
1269 if (c->rep_prefix && (c->d & String)) {
1270 /* All REP prefixes have the same first termination condition */
1271 if (c->regs[VCPU_REGS_RCX] == 0) {
1272 ctxt->vcpu->arch.rip = c->eip;
1273 goto done;
1274 }
1275 /* The second termination condition only applies for REPE
1276 * and REPNE. Test if the repeat string operation prefix is
1277 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1278 * corresponding termination condition according to:
1279 * - if REPE/REPZ and ZF = 0 then done
1280 * - if REPNE/REPNZ and ZF = 1 then done
1281 */
1282 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1283 (c->b == 0xae) || (c->b == 0xaf)) {
1284 if ((c->rep_prefix == REPE_PREFIX) &&
1285 ((ctxt->eflags & EFLG_ZF) == 0)) {
1286 ctxt->vcpu->arch.rip = c->eip;
1287 goto done;
1288 }
1289 if ((c->rep_prefix == REPNE_PREFIX) &&
1290 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1291 ctxt->vcpu->arch.rip = c->eip;
1292 goto done;
1293 }
1294 }
1295 c->regs[VCPU_REGS_RCX]--;
1296 c->eip = ctxt->vcpu->arch.rip;
1297 }
1298
1299 if (c->src.type == OP_MEM) {
1300 c->src.ptr = (unsigned long *)memop;
1301 c->src.val = 0;
1302 rc = ops->read_emulated((unsigned long)c->src.ptr,
1303 &c->src.val,
1304 c->src.bytes,
1305 ctxt->vcpu);
1306 if (rc != 0)
1307 goto done;
1308 c->src.orig_val = c->src.val;
1309 }
1310
1311 if ((c->d & DstMask) == ImplicitOps)
1312 goto special_insn;
1313
1314
1315 if (c->dst.type == OP_MEM) {
1316 c->dst.ptr = (unsigned long *)memop;
1317 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1318 c->dst.val = 0;
1319 if (c->d & BitOp) {
1320 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1321
1322 c->dst.ptr = (void *)c->dst.ptr +
1323 (c->src.val & mask) / 8;
1324 }
1325 if (!(c->d & Mov) &&
1326 /* optimisation - avoid slow emulated read */
1327 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1328 &c->dst.val,
1329 c->dst.bytes, ctxt->vcpu)) != 0))
1330 goto done;
1331 }
1332 c->dst.orig_val = c->dst.val;
1333
1334 special_insn:
1335
1336 if (c->twobyte)
1337 goto twobyte_insn;
1338
1339 switch (c->b) {
1340 case 0x00 ... 0x05:
1341 add: /* add */
1342 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1343 break;
1344 case 0x08 ... 0x0d:
1345 or: /* or */
1346 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1347 break;
1348 case 0x10 ... 0x15:
1349 adc: /* adc */
1350 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1351 break;
1352 case 0x18 ... 0x1d:
1353 sbb: /* sbb */
1354 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1355 break;
1356 case 0x20 ... 0x23:
1357 and: /* and */
1358 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1359 break;
1360 case 0x24: /* and al imm8 */
1361 c->dst.type = OP_REG;
1362 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1363 c->dst.val = *(u8 *)c->dst.ptr;
1364 c->dst.bytes = 1;
1365 c->dst.orig_val = c->dst.val;
1366 goto and;
1367 case 0x25: /* and ax imm16, or eax imm32 */
1368 c->dst.type = OP_REG;
1369 c->dst.bytes = c->op_bytes;
1370 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1371 if (c->op_bytes == 2)
1372 c->dst.val = *(u16 *)c->dst.ptr;
1373 else
1374 c->dst.val = *(u32 *)c->dst.ptr;
1375 c->dst.orig_val = c->dst.val;
1376 goto and;
1377 case 0x28 ... 0x2d:
1378 sub: /* sub */
1379 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1380 break;
1381 case 0x30 ... 0x35:
1382 xor: /* xor */
1383 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1384 break;
1385 case 0x38 ... 0x3d:
1386 cmp: /* cmp */
1387 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1388 break;
1389 case 0x40 ... 0x47: /* inc r16/r32 */
1390 emulate_1op("inc", c->dst, ctxt->eflags);
1391 break;
1392 case 0x48 ... 0x4f: /* dec r16/r32 */
1393 emulate_1op("dec", c->dst, ctxt->eflags);
1394 break;
1395 case 0x50 ... 0x57: /* push reg */
1396 c->dst.type = OP_MEM;
1397 c->dst.bytes = c->op_bytes;
1398 c->dst.val = c->src.val;
1399 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1400 -c->op_bytes);
1401 c->dst.ptr = (void *) register_address(
1402 c, ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
1403 break;
1404 case 0x58 ... 0x5f: /* pop reg */
1405 pop_instruction:
1406 if ((rc = ops->read_std(register_address(c, ctxt->ss_base,
1407 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1408 c->op_bytes, ctxt->vcpu)) != 0)
1409 goto done;
1410
1411 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1412 c->op_bytes);
1413 c->dst.type = OP_NONE; /* Disable writeback. */
1414 break;
1415 case 0x63: /* movsxd */
1416 if (ctxt->mode != X86EMUL_MODE_PROT64)
1417 goto cannot_emulate;
1418 c->dst.val = (s32) c->src.val;
1419 break;
1420 case 0x6a: /* push imm8 */
1421 c->src.val = 0L;
1422 c->src.val = insn_fetch(s8, 1, c->eip);
1423 emulate_push(ctxt);
1424 break;
1425 case 0x6c: /* insb */
1426 case 0x6d: /* insw/insd */
1427 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1428 1,
1429 (c->d & ByteOp) ? 1 : c->op_bytes,
1430 c->rep_prefix ?
1431 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1432 (ctxt->eflags & EFLG_DF),
1433 register_address(c, ctxt->es_base,
1434 c->regs[VCPU_REGS_RDI]),
1435 c->rep_prefix,
1436 c->regs[VCPU_REGS_RDX]) == 0) {
1437 c->eip = saved_eip;
1438 return -1;
1439 }
1440 return 0;
1441 case 0x6e: /* outsb */
1442 case 0x6f: /* outsw/outsd */
1443 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1444 0,
1445 (c->d & ByteOp) ? 1 : c->op_bytes,
1446 c->rep_prefix ?
1447 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1448 (ctxt->eflags & EFLG_DF),
1449 register_address(c, c->override_base ?
1450 *c->override_base :
1451 ctxt->ds_base,
1452 c->regs[VCPU_REGS_RSI]),
1453 c->rep_prefix,
1454 c->regs[VCPU_REGS_RDX]) == 0) {
1455 c->eip = saved_eip;
1456 return -1;
1457 }
1458 return 0;
1459 case 0x70 ... 0x7f: /* jcc (short) */ {
1460 int rel = insn_fetch(s8, 1, c->eip);
1461
1462 if (test_cc(c->b, ctxt->eflags))
1463 jmp_rel(c, rel);
1464 break;
1465 }
1466 case 0x80 ... 0x83: /* Grp1 */
1467 switch (c->modrm_reg) {
1468 case 0:
1469 goto add;
1470 case 1:
1471 goto or;
1472 case 2:
1473 goto adc;
1474 case 3:
1475 goto sbb;
1476 case 4:
1477 goto and;
1478 case 5:
1479 goto sub;
1480 case 6:
1481 goto xor;
1482 case 7:
1483 goto cmp;
1484 }
1485 break;
1486 case 0x84 ... 0x85:
1487 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1488 break;
1489 case 0x86 ... 0x87: /* xchg */
1490 /* Write back the register source. */
1491 switch (c->dst.bytes) {
1492 case 1:
1493 *(u8 *) c->src.ptr = (u8) c->dst.val;
1494 break;
1495 case 2:
1496 *(u16 *) c->src.ptr = (u16) c->dst.val;
1497 break;
1498 case 4:
1499 *c->src.ptr = (u32) c->dst.val;
1500 break; /* 64b reg: zero-extend */
1501 case 8:
1502 *c->src.ptr = c->dst.val;
1503 break;
1504 }
1505 /*
1506 * Write back the memory destination with implicit LOCK
1507 * prefix.
1508 */
1509 c->dst.val = c->src.val;
1510 c->lock_prefix = 1;
1511 break;
1512 case 0x88 ... 0x8b: /* mov */
1513 goto mov;
1514 case 0x8d: /* lea r16/r32, m */
1515 c->dst.val = c->modrm_ea;
1516 break;
1517 case 0x8f: /* pop (sole member of Grp1a) */
1518 rc = emulate_grp1a(ctxt, ops);
1519 if (rc != 0)
1520 goto done;
1521 break;
1522 case 0x9c: /* pushf */
1523 c->src.val = (unsigned long) ctxt->eflags;
1524 emulate_push(ctxt);
1525 break;
1526 case 0x9d: /* popf */
1527 c->dst.ptr = (unsigned long *) &ctxt->eflags;
1528 goto pop_instruction;
1529 case 0xa0 ... 0xa1: /* mov */
1530 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1531 c->dst.val = c->src.val;
1532 break;
1533 case 0xa2 ... 0xa3: /* mov */
1534 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1535 break;
1536 case 0xa4 ... 0xa5: /* movs */
1537 c->dst.type = OP_MEM;
1538 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1539 c->dst.ptr = (unsigned long *)register_address(c,
1540 ctxt->es_base,
1541 c->regs[VCPU_REGS_RDI]);
1542 if ((rc = ops->read_emulated(register_address(c,
1543 c->override_base ? *c->override_base :
1544 ctxt->ds_base,
1545 c->regs[VCPU_REGS_RSI]),
1546 &c->dst.val,
1547 c->dst.bytes, ctxt->vcpu)) != 0)
1548 goto done;
1549 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1550 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1551 : c->dst.bytes);
1552 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1553 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1554 : c->dst.bytes);
1555 break;
1556 case 0xa6 ... 0xa7: /* cmps */
1557 c->src.type = OP_NONE; /* Disable writeback. */
1558 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1559 c->src.ptr = (unsigned long *)register_address(c,
1560 c->override_base ? *c->override_base :
1561 ctxt->ds_base,
1562 c->regs[VCPU_REGS_RSI]);
1563 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1564 &c->src.val,
1565 c->src.bytes,
1566 ctxt->vcpu)) != 0)
1567 goto done;
1568
1569 c->dst.type = OP_NONE; /* Disable writeback. */
1570 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1571 c->dst.ptr = (unsigned long *)register_address(c,
1572 ctxt->es_base,
1573 c->regs[VCPU_REGS_RDI]);
1574 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1575 &c->dst.val,
1576 c->dst.bytes,
1577 ctxt->vcpu)) != 0)
1578 goto done;
1579
1580 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1581
1582 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1583
1584 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1585 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1586 : c->src.bytes);
1587 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1588 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1589 : c->dst.bytes);
1590
1591 break;
1592 case 0xaa ... 0xab: /* stos */
1593 c->dst.type = OP_MEM;
1594 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1595 c->dst.ptr = (unsigned long *)register_address(c,
1596 ctxt->es_base,
1597 c->regs[VCPU_REGS_RDI]);
1598 c->dst.val = c->regs[VCPU_REGS_RAX];
1599 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1600 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1601 : c->dst.bytes);
1602 break;
1603 case 0xac ... 0xad: /* lods */
1604 c->dst.type = OP_REG;
1605 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1606 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1607 if ((rc = ops->read_emulated(register_address(c,
1608 c->override_base ? *c->override_base :
1609 ctxt->ds_base,
1610 c->regs[VCPU_REGS_RSI]),
1611 &c->dst.val,
1612 c->dst.bytes,
1613 ctxt->vcpu)) != 0)
1614 goto done;
1615 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1616 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1617 : c->dst.bytes);
1618 break;
1619 case 0xae ... 0xaf: /* scas */
1620 DPRINTF("Urk! I don't handle SCAS.\n");
1621 goto cannot_emulate;
1622 case 0xc0 ... 0xc1:
1623 emulate_grp2(ctxt);
1624 break;
1625 case 0xc3: /* ret */
1626 c->dst.ptr = &c->eip;
1627 goto pop_instruction;
1628 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1629 mov:
1630 c->dst.val = c->src.val;
1631 break;
1632 case 0xd0 ... 0xd1: /* Grp2 */
1633 c->src.val = 1;
1634 emulate_grp2(ctxt);
1635 break;
1636 case 0xd2 ... 0xd3: /* Grp2 */
1637 c->src.val = c->regs[VCPU_REGS_RCX];
1638 emulate_grp2(ctxt);
1639 break;
1640 case 0xe8: /* call (near) */ {
1641 long int rel;
1642 switch (c->op_bytes) {
1643 case 2:
1644 rel = insn_fetch(s16, 2, c->eip);
1645 break;
1646 case 4:
1647 rel = insn_fetch(s32, 4, c->eip);
1648 break;
1649 default:
1650 DPRINTF("Call: Invalid op_bytes\n");
1651 goto cannot_emulate;
1652 }
1653 c->src.val = (unsigned long) c->eip;
1654 jmp_rel(c, rel);
1655 c->op_bytes = c->ad_bytes;
1656 emulate_push(ctxt);
1657 break;
1658 }
1659 case 0xe9: /* jmp rel */
1660 case 0xeb: /* jmp rel short */
1661 jmp_rel(c, c->src.val);
1662 c->dst.type = OP_NONE; /* Disable writeback. */
1663 break;
1664 case 0xf4: /* hlt */
1665 ctxt->vcpu->arch.halt_request = 1;
1666 goto done;
1667 case 0xf5: /* cmc */
1668 /* complement carry flag from eflags reg */
1669 ctxt->eflags ^= EFLG_CF;
1670 c->dst.type = OP_NONE; /* Disable writeback. */
1671 break;
1672 case 0xf6 ... 0xf7: /* Grp3 */
1673 rc = emulate_grp3(ctxt, ops);
1674 if (rc != 0)
1675 goto done;
1676 break;
1677 case 0xf8: /* clc */
1678 ctxt->eflags &= ~EFLG_CF;
1679 c->dst.type = OP_NONE; /* Disable writeback. */
1680 break;
1681 case 0xfa: /* cli */
1682 ctxt->eflags &= ~X86_EFLAGS_IF;
1683 c->dst.type = OP_NONE; /* Disable writeback. */
1684 break;
1685 case 0xfb: /* sti */
1686 ctxt->eflags |= X86_EFLAGS_IF;
1687 c->dst.type = OP_NONE; /* Disable writeback. */
1688 break;
1689 case 0xfe ... 0xff: /* Grp4/Grp5 */
1690 rc = emulate_grp45(ctxt, ops);
1691 if (rc != 0)
1692 goto done;
1693 break;
1694 }
1695
1696 writeback:
1697 rc = writeback(ctxt, ops);
1698 if (rc != 0)
1699 goto done;
1700
1701 /* Commit shadow register state. */
1702 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1703 ctxt->vcpu->arch.rip = c->eip;
1704
1705 done:
1706 if (rc == X86EMUL_UNHANDLEABLE) {
1707 c->eip = saved_eip;
1708 return -1;
1709 }
1710 return 0;
1711
1712 twobyte_insn:
1713 switch (c->b) {
1714 case 0x01: /* lgdt, lidt, lmsw */
1715 switch (c->modrm_reg) {
1716 u16 size;
1717 unsigned long address;
1718
1719 case 0: /* vmcall */
1720 if (c->modrm_mod != 3 || c->modrm_rm != 1)
1721 goto cannot_emulate;
1722
1723 rc = kvm_fix_hypercall(ctxt->vcpu);
1724 if (rc)
1725 goto done;
1726
1727 kvm_emulate_hypercall(ctxt->vcpu);
1728 /* Disable writeback. */
1729 c->dst.type = OP_NONE;
1730 break;
1731 case 2: /* lgdt */
1732 rc = read_descriptor(ctxt, ops, c->src.ptr,
1733 &size, &address, c->op_bytes);
1734 if (rc)
1735 goto done;
1736 realmode_lgdt(ctxt->vcpu, size, address);
1737 /* Disable writeback. */
1738 c->dst.type = OP_NONE;
1739 break;
1740 case 3: /* lidt/vmmcall */
1741 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
1742 rc = kvm_fix_hypercall(ctxt->vcpu);
1743 if (rc)
1744 goto done;
1745 kvm_emulate_hypercall(ctxt->vcpu);
1746 } else {
1747 rc = read_descriptor(ctxt, ops, c->src.ptr,
1748 &size, &address,
1749 c->op_bytes);
1750 if (rc)
1751 goto done;
1752 realmode_lidt(ctxt->vcpu, size, address);
1753 }
1754 /* Disable writeback. */
1755 c->dst.type = OP_NONE;
1756 break;
1757 case 4: /* smsw */
1758 c->dst.bytes = 2;
1759 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
1760 break;
1761 case 6: /* lmsw */
1762 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1763 &ctxt->eflags);
1764 break;
1765 case 7: /* invlpg*/
1766 emulate_invlpg(ctxt->vcpu, memop);
1767 /* Disable writeback. */
1768 c->dst.type = OP_NONE;
1769 break;
1770 default:
1771 goto cannot_emulate;
1772 }
1773 break;
1774 case 0x06:
1775 emulate_clts(ctxt->vcpu);
1776 c->dst.type = OP_NONE;
1777 break;
1778 case 0x08: /* invd */
1779 case 0x09: /* wbinvd */
1780 case 0x0d: /* GrpP (prefetch) */
1781 case 0x18: /* Grp16 (prefetch/nop) */
1782 c->dst.type = OP_NONE;
1783 break;
1784 case 0x20: /* mov cr, reg */
1785 if (c->modrm_mod != 3)
1786 goto cannot_emulate;
1787 c->regs[c->modrm_rm] =
1788 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1789 c->dst.type = OP_NONE; /* no writeback */
1790 break;
1791 case 0x21: /* mov from dr to reg */
1792 if (c->modrm_mod != 3)
1793 goto cannot_emulate;
1794 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
1795 if (rc)
1796 goto cannot_emulate;
1797 c->dst.type = OP_NONE; /* no writeback */
1798 break;
1799 case 0x22: /* mov reg, cr */
1800 if (c->modrm_mod != 3)
1801 goto cannot_emulate;
1802 realmode_set_cr(ctxt->vcpu,
1803 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1804 c->dst.type = OP_NONE;
1805 break;
1806 case 0x23: /* mov from reg to dr */
1807 if (c->modrm_mod != 3)
1808 goto cannot_emulate;
1809 rc = emulator_set_dr(ctxt, c->modrm_reg,
1810 c->regs[c->modrm_rm]);
1811 if (rc)
1812 goto cannot_emulate;
1813 c->dst.type = OP_NONE; /* no writeback */
1814 break;
1815 case 0x30:
1816 /* wrmsr */
1817 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1818 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1819 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1820 if (rc) {
1821 kvm_inject_gp(ctxt->vcpu, 0);
1822 c->eip = ctxt->vcpu->arch.rip;
1823 }
1824 rc = X86EMUL_CONTINUE;
1825 c->dst.type = OP_NONE;
1826 break;
1827 case 0x32:
1828 /* rdmsr */
1829 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1830 if (rc) {
1831 kvm_inject_gp(ctxt->vcpu, 0);
1832 c->eip = ctxt->vcpu->arch.rip;
1833 } else {
1834 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1835 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1836 }
1837 rc = X86EMUL_CONTINUE;
1838 c->dst.type = OP_NONE;
1839 break;
1840 case 0x40 ... 0x4f: /* cmov */
1841 c->dst.val = c->dst.orig_val = c->src.val;
1842 if (!test_cc(c->b, ctxt->eflags))
1843 c->dst.type = OP_NONE; /* no writeback */
1844 break;
1845 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1846 long int rel;
1847
1848 switch (c->op_bytes) {
1849 case 2:
1850 rel = insn_fetch(s16, 2, c->eip);
1851 break;
1852 case 4:
1853 rel = insn_fetch(s32, 4, c->eip);
1854 break;
1855 case 8:
1856 rel = insn_fetch(s64, 8, c->eip);
1857 break;
1858 default:
1859 DPRINTF("jnz: Invalid op_bytes\n");
1860 goto cannot_emulate;
1861 }
1862 if (test_cc(c->b, ctxt->eflags))
1863 jmp_rel(c, rel);
1864 c->dst.type = OP_NONE;
1865 break;
1866 }
1867 case 0xa3:
1868 bt: /* bt */
1869 c->dst.type = OP_NONE;
1870 /* only subword offset */
1871 c->src.val &= (c->dst.bytes << 3) - 1;
1872 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
1873 break;
1874 case 0xab:
1875 bts: /* bts */
1876 /* only subword offset */
1877 c->src.val &= (c->dst.bytes << 3) - 1;
1878 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
1879 break;
1880 case 0xb0 ... 0xb1: /* cmpxchg */
1881 /*
1882 * Save real source value, then compare EAX against
1883 * destination.
1884 */
1885 c->src.orig_val = c->src.val;
1886 c->src.val = c->regs[VCPU_REGS_RAX];
1887 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1888 if (ctxt->eflags & EFLG_ZF) {
1889 /* Success: write back to memory. */
1890 c->dst.val = c->src.orig_val;
1891 } else {
1892 /* Failure: write the value we saw to EAX. */
1893 c->dst.type = OP_REG;
1894 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1895 }
1896 break;
1897 case 0xb3:
1898 btr: /* btr */
1899 /* only subword offset */
1900 c->src.val &= (c->dst.bytes << 3) - 1;
1901 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
1902 break;
1903 case 0xb6 ... 0xb7: /* movzx */
1904 c->dst.bytes = c->op_bytes;
1905 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1906 : (u16) c->src.val;
1907 break;
1908 case 0xba: /* Grp8 */
1909 switch (c->modrm_reg & 3) {
1910 case 0:
1911 goto bt;
1912 case 1:
1913 goto bts;
1914 case 2:
1915 goto btr;
1916 case 3:
1917 goto btc;
1918 }
1919 break;
1920 case 0xbb:
1921 btc: /* btc */
1922 /* only subword offset */
1923 c->src.val &= (c->dst.bytes << 3) - 1;
1924 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
1925 break;
1926 case 0xbe ... 0xbf: /* movsx */
1927 c->dst.bytes = c->op_bytes;
1928 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1929 (s16) c->src.val;
1930 break;
1931 case 0xc3: /* movnti */
1932 c->dst.bytes = c->op_bytes;
1933 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1934 (u64) c->src.val;
1935 break;
1936 case 0xc7: /* Grp9 (cmpxchg8b) */
1937 rc = emulate_grp9(ctxt, ops, memop);
1938 if (rc != 0)
1939 goto done;
1940 c->dst.type = OP_NONE;
1941 break;
1942 }
1943 goto writeback;
1944
1945 cannot_emulate:
1946 DPRINTF("Cannot emulate %02x\n", c->b);
1947 c->eip = saved_eip;
1948 return -1;
1949 }
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