1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * This file provides all the same external entries as smp.c but uses
8 * the voyager hal to provide the functionality
10 #include <linux/module.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/delay.h>
14 #include <linux/mc146818rtc.h>
15 #include <linux/cache.h>
16 #include <linux/interrupt.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/bootmem.h>
20 #include <linux/completion.h>
22 #include <asm/voyager.h>
25 #include <asm/pgalloc.h>
26 #include <asm/tlbflush.h>
27 #include <asm/arch_hooks.h>
28 #include <asm/trampoline.h>
30 /* TLB state -- visible externally, indexed physically */
31 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state
, cpu_tlbstate
) = { &init_mm
, 0 };
33 /* CPU IRQ affinity -- set to all ones initially */
34 static unsigned long cpu_irq_affinity
[NR_CPUS
] __cacheline_aligned
=
35 {[0 ... NR_CPUS
-1] = ~0UL };
37 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
38 * indexed physically */
39 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
40 EXPORT_PER_CPU_SYMBOL(cpu_info
);
42 /* physical ID of the CPU used to boot the system */
43 unsigned char boot_cpu_id
;
45 /* The memory line addresses for the Quad CPIs */
46 struct voyager_qic_cpi
*voyager_quad_cpi_addr
[NR_CPUS
] __cacheline_aligned
;
48 /* The masks for the Extended VIC processors, filled in by cat_init */
49 __u32 voyager_extended_vic_processors
= 0;
51 /* Masks for the extended Quad processors which cannot be VIC booted */
52 __u32 voyager_allowed_boot_processors
= 0;
54 /* The mask for the Quad Processors (both extended and non-extended) */
55 __u32 voyager_quad_processors
= 0;
57 /* Total count of live CPUs, used in process.c to display
58 * the CPU information and in irq.c for the per CPU irq
59 * activity count. Finally exported by i386_ksyms.c */
60 static int voyager_extended_cpus
= 1;
62 /* Have we found an SMP box - used by time.c to do the profiling
63 interrupt for timeslicing; do not set to 1 until the per CPU timer
64 interrupt is active */
65 int smp_found_config
= 0;
67 /* Used for the invalidate map that's also checked in the spinlock */
68 static volatile unsigned long smp_invalidate_needed
;
70 /* Bitmask of currently online CPUs - used by setup.c for
71 /proc/cpuinfo, visible externally but still physical */
72 cpumask_t cpu_online_map
= CPU_MASK_NONE
;
73 EXPORT_SYMBOL(cpu_online_map
);
75 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
76 * by scheduler but indexed physically */
77 cpumask_t phys_cpu_present_map
= CPU_MASK_NONE
;
79 /* The internal functions */
80 static void send_CPI(__u32 cpuset
, __u8 cpi
);
81 static void ack_CPI(__u8 cpi
);
82 static int ack_QIC_CPI(__u8 cpi
);
83 static void ack_special_QIC_CPI(__u8 cpi
);
84 static void ack_VIC_CPI(__u8 cpi
);
85 static void send_CPI_allbutself(__u8 cpi
);
86 static void mask_vic_irq(unsigned int irq
);
87 static void unmask_vic_irq(unsigned int irq
);
88 static unsigned int startup_vic_irq(unsigned int irq
);
89 static void enable_local_vic_irq(unsigned int irq
);
90 static void disable_local_vic_irq(unsigned int irq
);
91 static void before_handle_vic_irq(unsigned int irq
);
92 static void after_handle_vic_irq(unsigned int irq
);
93 static void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
);
94 static void ack_vic_irq(unsigned int irq
);
95 static void vic_enable_cpi(void);
96 static void do_boot_cpu(__u8 cpuid
);
97 static void do_quad_bootstrap(void);
99 int hard_smp_processor_id(void);
100 int safe_smp_processor_id(void);
102 /* Inline functions */
103 static inline void send_one_QIC_CPI(__u8 cpu
, __u8 cpi
)
105 voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
=
106 (smp_processor_id() << 16) + cpi
;
109 static inline void send_QIC_CPI(__u32 cpuset
, __u8 cpi
)
113 for_each_online_cpu(cpu
) {
114 if (cpuset
& (1 << cpu
)) {
116 if (!cpu_online(cpu
))
117 VDEBUG(("CPU%d sending cpi %d to CPU%d not in "
119 hard_smp_processor_id(), cpi
, cpu
));
121 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
126 static inline void wrapper_smp_local_timer_interrupt(void)
129 smp_local_timer_interrupt();
133 static inline void send_one_CPI(__u8 cpu
, __u8 cpi
)
135 if (voyager_quad_processors
& (1 << cpu
))
136 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
138 send_CPI(1 << cpu
, cpi
);
141 static inline void send_CPI_allbutself(__u8 cpi
)
143 __u8 cpu
= smp_processor_id();
144 __u32 mask
= cpus_addr(cpu_online_map
)[0] & ~(1 << cpu
);
148 static inline int is_cpu_quad(void)
150 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
151 return ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
);
154 static inline int is_cpu_extended(void)
156 __u8 cpu
= hard_smp_processor_id();
158 return (voyager_extended_vic_processors
& (1 << cpu
));
161 static inline int is_cpu_vic_boot(void)
163 __u8 cpu
= hard_smp_processor_id();
165 return (voyager_extended_vic_processors
166 & voyager_allowed_boot_processors
& (1 << cpu
));
169 static inline void ack_CPI(__u8 cpi
)
172 case VIC_CPU_BOOT_CPI
:
173 if (is_cpu_quad() && !is_cpu_vic_boot())
180 /* These are slightly strange. Even on the Quad card,
181 * They are vectored as VIC CPIs */
183 ack_special_QIC_CPI(cpi
);
188 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi
);
193 /* local variables */
195 /* The VIC IRQ descriptors -- these look almost identical to the
196 * 8259 IRQs except that masks and things must be kept per processor
198 static struct irq_chip vic_chip
= {
200 .startup
= startup_vic_irq
,
201 .mask
= mask_vic_irq
,
202 .unmask
= unmask_vic_irq
,
203 .set_affinity
= set_vic_irq_affinity
,
206 /* used to count up as CPUs are brought on line (starts at 0) */
207 static int cpucount
= 0;
209 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
210 static DEFINE_PER_CPU(int, prof_multiplier
) = 1;
211 static DEFINE_PER_CPU(int, prof_old_multiplier
) = 1;
212 static DEFINE_PER_CPU(int, prof_counter
) = 1;
214 /* the map used to check if a CPU has booted */
215 static __u32 cpu_booted_map
;
217 /* the synchronize flag used to hold all secondary CPUs spinning in
218 * a tight loop until the boot sequence is ready for them */
219 static cpumask_t smp_commenced_mask
= CPU_MASK_NONE
;
221 /* This is for the new dynamic CPU boot code */
222 cpumask_t cpu_callin_map
= CPU_MASK_NONE
;
223 cpumask_t cpu_callout_map
= CPU_MASK_NONE
;
224 cpumask_t cpu_possible_map
= CPU_MASK_NONE
;
225 EXPORT_SYMBOL(cpu_possible_map
);
227 /* The per processor IRQ masks (these are usually kept in sync) */
228 static __u16 vic_irq_mask
[NR_CPUS
] __cacheline_aligned
;
230 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
231 static __u16 vic_irq_enable_mask
[NR_CPUS
] __cacheline_aligned
= { 0 };
233 /* Lock for enable/disable of VIC interrupts */
234 static __cacheline_aligned
DEFINE_SPINLOCK(vic_irq_lock
);
236 /* The boot processor is correctly set up in PC mode when it
237 * comes up, but the secondaries need their master/slave 8259
238 * pairs initializing correctly */
240 /* Interrupt counters (per cpu) and total - used to try to
241 * even up the interrupt handling routines */
242 static long vic_intr_total
= 0;
243 static long vic_intr_count
[NR_CPUS
] __cacheline_aligned
= { 0 };
244 static unsigned long vic_tick
[NR_CPUS
] __cacheline_aligned
= { 0 };
246 /* Since we can only use CPI0, we fake all the other CPIs */
247 static unsigned long vic_cpi_mailbox
[NR_CPUS
] __cacheline_aligned
;
249 /* debugging routine to read the isr of the cpu's pic */
250 static inline __u16
vic_read_isr(void)
255 isr
= inb(0xa0) << 8;
262 static __init
void qic_setup(void)
264 if (!is_cpu_quad()) {
265 /* not a quad, no setup */
268 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
269 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
271 if (is_cpu_extended()) {
272 /* the QIC duplicate of the VIC base register */
273 outb(VIC_DEFAULT_CPI_BASE
, QIC_VIC_CPI_BASE_REGISTER
);
274 outb(QIC_DEFAULT_CPI_BASE
, QIC_CPI_BASE_REGISTER
);
276 /* FIXME: should set up the QIC timer and memory parity
277 * error vectors here */
281 static __init
void vic_setup_pic(void)
283 outb(1, VIC_REDIRECT_REGISTER_1
);
284 /* clear the claim registers for dynamic routing */
285 outb(0, VIC_CLAIM_REGISTER_0
);
286 outb(0, VIC_CLAIM_REGISTER_1
);
288 outb(0, VIC_PRIORITY_REGISTER
);
289 /* Set the Primary and Secondary Microchannel vector
290 * bases to be the same as the ordinary interrupts
292 * FIXME: This would be more efficient using separate
294 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
295 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
296 /* Now initiallise the master PIC belonging to this CPU by
297 * sending the four ICWs */
299 /* ICW1: level triggered, ICW4 needed */
302 /* ICW2: vector base */
303 outb(FIRST_EXTERNAL_VECTOR
, 0x21);
305 /* ICW3: slave at line 2 */
308 /* ICW4: 8086 mode */
311 /* now the same for the slave PIC */
313 /* ICW1: level trigger, ICW4 needed */
316 /* ICW2: slave vector base */
317 outb(FIRST_EXTERNAL_VECTOR
+ 8, 0xA1);
322 /* ICW4: 8086 mode */
326 static void do_quad_bootstrap(void)
328 if (is_cpu_quad() && is_cpu_vic_boot()) {
331 __u8 cpuid
= hard_smp_processor_id();
333 local_irq_save(flags
);
335 for (i
= 0; i
< 4; i
++) {
336 /* FIXME: this would be >>3 &0x7 on the 32 way */
337 if (((cpuid
>> 2) & 0x03) == i
)
338 /* don't lower our own mask! */
341 /* masquerade as local Quad CPU */
342 outb(QIC_CPUID_ENABLE
| i
, QIC_PROCESSOR_ID
);
343 /* enable the startup CPI */
344 outb(QIC_BOOT_CPI_MASK
, QIC_MASK_REGISTER1
);
346 outb(0, QIC_PROCESSOR_ID
);
348 local_irq_restore(flags
);
352 /* Set up all the basic stuff: read the SMP config and make all the
353 * SMP information reflect only the boot cpu. All others will be
354 * brought on-line later. */
355 void __init
find_smp_config(void)
359 boot_cpu_id
= hard_smp_processor_id();
361 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id
);
363 /* initialize the CPU structures (moved from smp_boot_cpus) */
364 for (i
= 0; i
< NR_CPUS
; i
++) {
365 cpu_irq_affinity
[i
] = ~0;
367 cpu_online_map
= cpumask_of_cpu(boot_cpu_id
);
369 /* The boot CPU must be extended */
370 voyager_extended_vic_processors
= 1 << boot_cpu_id
;
371 /* initially, all of the first 8 CPUs can boot */
372 voyager_allowed_boot_processors
= 0xff;
373 /* set up everything for just this CPU, we can alter
374 * this as we start the other CPUs later */
375 /* now get the CPU disposition from the extended CMOS */
376 cpus_addr(phys_cpu_present_map
)[0] =
377 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
);
378 cpus_addr(phys_cpu_present_map
)[0] |=
379 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+ 1) << 8;
380 cpus_addr(phys_cpu_present_map
)[0] |=
381 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+
383 cpus_addr(phys_cpu_present_map
)[0] |=
384 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+
386 cpu_possible_map
= phys_cpu_present_map
;
387 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n",
388 cpus_addr(phys_cpu_present_map
)[0]);
389 /* Here we set up the VIC to enable SMP */
390 /* enable the CPIs by writing the base vector to their register */
391 outb(VIC_DEFAULT_CPI_BASE
, VIC_CPI_BASE_REGISTER
);
392 outb(1, VIC_REDIRECT_REGISTER_1
);
393 /* set the claim registers for static routing --- Boot CPU gets
394 * all interrupts untill all other CPUs started */
395 outb(0xff, VIC_CLAIM_REGISTER_0
);
396 outb(0xff, VIC_CLAIM_REGISTER_1
);
397 /* Set the Primary and Secondary Microchannel vector
398 * bases to be the same as the ordinary interrupts
400 * FIXME: This would be more efficient using separate
402 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
403 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
405 /* Finally tell the firmware that we're driving */
406 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT
) | VOYAGER_IN_CONTROL_FLAG
,
407 VOYAGER_SUS_IN_CONTROL_PORT
);
409 current_thread_info()->cpu
= boot_cpu_id
;
410 x86_write_percpu(cpu_number
, boot_cpu_id
);
414 * The bootstrap kernel entry code has set these up. Save them
415 * for a given CPU, id is physical */
416 void __init
smp_store_cpu_info(int id
)
418 struct cpuinfo_x86
*c
= &cpu_data(id
);
422 identify_secondary_cpu(c
);
425 /* Routine initially called when a non-boot CPU is brought online */
426 static void __init
start_secondary(void *unused
)
428 __u8 cpuid
= hard_smp_processor_id();
432 /* OK, we're in the routine */
433 ack_CPI(VIC_CPU_BOOT_CPI
);
435 /* setup the 8259 master slave pair belonging to this CPU ---
436 * we won't actually receive any until the boot CPU
437 * relinquishes it's static routing mask */
442 if (is_cpu_quad() && !is_cpu_vic_boot()) {
443 /* clear the boot CPI */
447 voyager_quad_cpi_addr
[cpuid
]->qic_cpi
[VIC_CPU_BOOT_CPI
].cpi
;
448 printk("read dummy %d\n", dummy
);
451 /* lower the mask to receive CPIs */
454 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid
, &cpuid
));
456 /* enable interrupts */
459 /* get our bogomips */
462 /* save our processor parameters */
463 smp_store_cpu_info(cpuid
);
465 /* if we're a quad, we may need to bootstrap other CPUs */
468 /* FIXME: this is rather a poor hack to prevent the CPU
469 * activating softirqs while it's supposed to be waiting for
470 * permission to proceed. Without this, the new per CPU stuff
471 * in the softirqs will fail */
473 cpu_set(cpuid
, cpu_callin_map
);
475 /* signal that we're done */
478 while (!cpu_isset(cpuid
, smp_commenced_mask
))
484 cpu_set(cpuid
, cpu_online_map
);
489 /* Routine to kick start the given CPU and wait for it to report ready
490 * (or timeout in startup). When this routine returns, the requested
491 * CPU is either fully running and configured or known to be dead.
493 * We call this routine sequentially 1 CPU at a time, so no need for
496 static void __init
do_boot_cpu(__u8 cpu
)
498 struct task_struct
*idle
;
501 int quad_boot
= (1 << cpu
) & voyager_quad_processors
502 & ~(voyager_extended_vic_processors
503 & voyager_allowed_boot_processors
);
505 /* This is the format of the CPI IDT gate (in real mode) which
506 * we're hijacking to boot the CPU */
515 __u32
*hijack_vector
;
516 __u32 start_phys_address
= setup_trampoline();
518 /* There's a clever trick to this: The linux trampoline is
519 * compiled to begin at absolute location zero, so make the
520 * address zero but have the data segment selector compensate
521 * for the actual address */
522 hijack_source
.idt
.Offset
= start_phys_address
& 0x000F;
523 hijack_source
.idt
.Segment
= (start_phys_address
>> 4) & 0xFFFF;
526 alternatives_smp_switch(1);
528 idle
= fork_idle(cpu
);
530 panic("failed fork for CPU%d", cpu
);
531 idle
->thread
.ip
= (unsigned long)start_secondary
;
532 /* init_tasks (in sched.c) is indexed logically */
533 stack_start
.sp
= (void *)idle
->thread
.sp
;
536 per_cpu(current_task
, cpu
) = idle
;
537 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
540 /* Note: Don't modify initial ss override */
541 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu
,
542 (unsigned long)hijack_source
.val
, hijack_source
.idt
.Segment
,
543 hijack_source
.idt
.Offset
, stack_start
.sp
));
545 /* init lowmem identity mapping */
546 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ KERNEL_PGD_BOUNDARY
,
547 min_t(unsigned long, KERNEL_PGD_PTRS
, KERNEL_PGD_BOUNDARY
));
551 printk("CPU %d: non extended Quad boot\n", cpu
);
554 phys_to_virt((VIC_CPU_BOOT_CPI
+ QIC_DEFAULT_CPI_BASE
) * 4);
555 *hijack_vector
= hijack_source
.val
;
557 printk("CPU%d: extended VIC boot\n", cpu
);
560 phys_to_virt((VIC_CPU_BOOT_CPI
+ VIC_DEFAULT_CPI_BASE
) * 4);
561 *hijack_vector
= hijack_source
.val
;
562 /* VIC errata, may also receive interrupt at this address */
565 phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI
+
566 VIC_DEFAULT_CPI_BASE
) * 4);
567 *hijack_vector
= hijack_source
.val
;
569 /* All non-boot CPUs start with interrupts fully masked. Need
570 * to lower the mask of the CPI we're about to send. We do
571 * this in the VIC by masquerading as the processor we're
572 * about to boot and lowering its interrupt mask */
573 local_irq_save(flags
);
575 send_one_QIC_CPI(cpu
, VIC_CPU_BOOT_CPI
);
577 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
578 /* here we're altering registers belonging to `cpu' */
580 outb(VIC_BOOT_INTERRUPT_MASK
, 0x21);
581 /* now go back to our original identity */
582 outb(boot_cpu_id
, VIC_PROCESSOR_ID
);
584 /* and boot the CPU */
586 send_CPI((1 << cpu
), VIC_CPU_BOOT_CPI
);
589 local_irq_restore(flags
);
591 /* now wait for it to become ready (or timeout) */
592 for (timeout
= 0; timeout
< 50000; timeout
++) {
597 /* reset the page table */
600 if (cpu_booted_map
) {
601 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
602 cpu
, smp_processor_id()));
604 printk("CPU%d: ", cpu
);
605 print_cpu_info(&cpu_data(cpu
));
607 cpu_set(cpu
, cpu_callout_map
);
608 cpu_set(cpu
, cpu_present_map
);
610 printk("CPU%d FAILED TO BOOT: ", cpu
);
612 ((volatile unsigned char *)phys_to_virt(start_phys_address
))
616 printk("Not responding.\n");
622 void __init
smp_boot_cpus(void)
626 /* CAT BUS initialisation must be done after the memory */
627 /* FIXME: The L4 has a catbus too, it just needs to be
628 * accessed in a totally different way */
629 if (voyager_level
== 5) {
632 /* now that the cat has probed the Voyager System Bus, sanity
633 * check the cpu map */
634 if (((voyager_quad_processors
| voyager_extended_vic_processors
)
635 & cpus_addr(phys_cpu_present_map
)[0]) !=
636 cpus_addr(phys_cpu_present_map
)[0]) {
638 printk("\n\n***WARNING*** "
639 "Sanity check of CPU present map FAILED\n");
641 } else if (voyager_level
== 4)
642 voyager_extended_vic_processors
=
643 cpus_addr(phys_cpu_present_map
)[0];
645 /* this sets up the idle task to run on the current cpu */
646 voyager_extended_cpus
= 1;
647 /* Remove the global_irq_holder setting, it triggers a BUG() on
648 * schedule at the moment */
649 //global_irq_holder = boot_cpu_id;
651 /* FIXME: Need to do something about this but currently only works
652 * on CPUs with a tsc which none of mine have.
653 smp_tune_scheduling();
655 smp_store_cpu_info(boot_cpu_id
);
656 printk("CPU%d: ", boot_cpu_id
);
657 print_cpu_info(&cpu_data(boot_cpu_id
));
660 /* booting on a Quad CPU */
661 printk("VOYAGER SMP: Boot CPU is Quad\n");
666 /* enable our own CPIs */
669 cpu_set(boot_cpu_id
, cpu_online_map
);
670 cpu_set(boot_cpu_id
, cpu_callout_map
);
672 /* loop over all the extended VIC CPUs and boot them. The
673 * Quad CPUs must be bootstrapped by their extended VIC cpu */
674 for (i
= 0; i
< NR_CPUS
; i
++) {
675 if (i
== boot_cpu_id
|| !cpu_isset(i
, phys_cpu_present_map
))
678 /* This udelay seems to be needed for the Quad boots
679 * don't remove unless you know what you're doing */
682 /* we could compute the total bogomips here, but why bother?,
683 * Code added from smpboot.c */
685 unsigned long bogosum
= 0;
687 for_each_online_cpu(i
)
688 bogosum
+= cpu_data(i
).loops_per_jiffy
;
689 printk(KERN_INFO
"Total of %d processors activated "
690 "(%lu.%02lu BogoMIPS).\n",
691 cpucount
+ 1, bogosum
/ (500000 / HZ
),
692 (bogosum
/ (5000 / HZ
)) % 100);
694 voyager_extended_cpus
= hweight32(voyager_extended_vic_processors
);
695 printk("VOYAGER: Extended (interrupt handling CPUs): "
696 "%d, non-extended: %d\n", voyager_extended_cpus
,
697 num_booting_cpus() - voyager_extended_cpus
);
698 /* that's it, switch to symmetric mode */
699 outb(0, VIC_PRIORITY_REGISTER
);
700 outb(0, VIC_CLAIM_REGISTER_0
);
701 outb(0, VIC_CLAIM_REGISTER_1
);
703 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
706 /* Reload the secondary CPUs task structure (this function does not
708 void __init
initialize_secondary(void)
712 set_current(hard_get_current());
716 * We don't actually need to load the full TSS,
717 * basically just the stack pointer and the eip.
720 asm volatile ("movl %0,%%esp\n\t"
721 "jmp *%1"::"r" (current
->thread
.sp
),
722 "r"(current
->thread
.ip
));
725 /* handle a Voyager SYS_INT -- If we don't, the base board will
728 * System interrupts occur because some problem was detected on the
729 * various busses. To find out what you have to probe all the
730 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
731 void smp_vic_sys_interrupt(struct pt_regs
*regs
)
733 ack_CPI(VIC_SYS_INT
);
734 printk("Voyager SYSTEM INTERRUPT\n");
737 /* Handle a voyager CMN_INT; These interrupts occur either because of
738 * a system status change or because a single bit memory error
739 * occurred. FIXME: At the moment, ignore all this. */
740 void smp_vic_cmn_interrupt(struct pt_regs
*regs
)
742 static __u8 in_cmn_int
= 0;
743 static DEFINE_SPINLOCK(cmn_int_lock
);
745 /* common ints are broadcast, so make sure we only do this once */
746 _raw_spin_lock(&cmn_int_lock
);
751 _raw_spin_unlock(&cmn_int_lock
);
753 VDEBUG(("Voyager COMMON INTERRUPT\n"));
755 if (voyager_level
== 5)
756 voyager_cat_do_common_interrupt();
758 _raw_spin_lock(&cmn_int_lock
);
761 _raw_spin_unlock(&cmn_int_lock
);
762 ack_CPI(VIC_CMN_INT
);
766 * Reschedule call back. Nothing to do, all the work is done
767 * automatically when we return from the interrupt. */
768 static void smp_reschedule_interrupt(void)
773 static struct mm_struct
*flush_mm
;
774 static unsigned long flush_va
;
775 static DEFINE_SPINLOCK(tlbstate_lock
);
778 * We cannot call mmdrop() because we are in interrupt context,
779 * instead update mm->cpu_vm_mask.
781 * We need to reload %cr3 since the page tables may be going
782 * away from under us..
784 static inline void voyager_leave_mm(unsigned long cpu
)
786 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
)
788 cpu_clear(cpu
, per_cpu(cpu_tlbstate
, cpu
).active_mm
->cpu_vm_mask
);
789 load_cr3(swapper_pg_dir
);
793 * Invalidate call-back
795 static void smp_invalidate_interrupt(void)
797 __u8 cpu
= smp_processor_id();
799 if (!test_bit(cpu
, &smp_invalidate_needed
))
801 /* This will flood messages. Don't uncomment unless you see
802 * Problems with cross cpu invalidation
803 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
804 smp_processor_id()));
807 if (flush_mm
== per_cpu(cpu_tlbstate
, cpu
).active_mm
) {
808 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
) {
809 if (flush_va
== TLB_FLUSH_ALL
)
812 __flush_tlb_one(flush_va
);
814 voyager_leave_mm(cpu
);
816 smp_mb__before_clear_bit();
817 clear_bit(cpu
, &smp_invalidate_needed
);
818 smp_mb__after_clear_bit();
821 /* All the new flush operations for 2.4 */
823 /* This routine is called with a physical cpu mask */
825 voyager_flush_tlb_others(unsigned long cpumask
, struct mm_struct
*mm
,
832 if ((cpumask
& cpus_addr(cpu_online_map
)[0]) != cpumask
)
834 if (cpumask
& (1 << smp_processor_id()))
839 spin_lock(&tlbstate_lock
);
843 atomic_set_mask(cpumask
, &smp_invalidate_needed
);
845 * We have to send the CPI only to
848 send_CPI(cpumask
, VIC_INVALIDATE_CPI
);
850 while (smp_invalidate_needed
) {
853 printk("***WARNING*** Stuck doing invalidate CPI "
854 "(CPU%d)\n", smp_processor_id());
859 /* Uncomment only to debug invalidation problems
860 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
865 spin_unlock(&tlbstate_lock
);
868 void flush_tlb_current_task(void)
870 struct mm_struct
*mm
= current
->mm
;
871 unsigned long cpu_mask
;
875 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
878 voyager_flush_tlb_others(cpu_mask
, mm
, TLB_FLUSH_ALL
);
883 void flush_tlb_mm(struct mm_struct
*mm
)
885 unsigned long cpu_mask
;
889 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
891 if (current
->active_mm
== mm
) {
895 voyager_leave_mm(smp_processor_id());
898 voyager_flush_tlb_others(cpu_mask
, mm
, TLB_FLUSH_ALL
);
903 void flush_tlb_page(struct vm_area_struct
*vma
, unsigned long va
)
905 struct mm_struct
*mm
= vma
->vm_mm
;
906 unsigned long cpu_mask
;
910 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
911 if (current
->active_mm
== mm
) {
915 voyager_leave_mm(smp_processor_id());
919 voyager_flush_tlb_others(cpu_mask
, mm
, va
);
924 EXPORT_SYMBOL(flush_tlb_page
);
926 /* enable the requested IRQs */
927 static void smp_enable_irq_interrupt(void)
930 __u8 cpu
= get_cpu();
932 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu
,
933 vic_irq_enable_mask
[cpu
]));
935 spin_lock(&vic_irq_lock
);
936 for (irq
= 0; irq
< 16; irq
++) {
937 if (vic_irq_enable_mask
[cpu
] & (1 << irq
))
938 enable_local_vic_irq(irq
);
940 vic_irq_enable_mask
[cpu
] = 0;
941 spin_unlock(&vic_irq_lock
);
943 put_cpu_no_resched();
949 static void smp_stop_cpu_function(void *dummy
)
951 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
952 cpu_clear(smp_processor_id(), cpu_online_map
);
958 /* execute a thread on a new CPU. The function to be called must be
959 * previously set up. This is used to schedule a function for
960 * execution on all CPUs - set up the function then broadcast a
961 * function_interrupt CPI to come here on each CPU */
962 static void smp_call_function_interrupt(void)
965 generic_smp_call_function_interrupt();
966 __get_cpu_var(irq_stat
).irq_call_count
++;
970 static void smp_call_function_single_interrupt(void)
973 generic_smp_call_function_single_interrupt();
974 __get_cpu_var(irq_stat
).irq_call_count
++;
978 /* Sorry about the name. In an APIC based system, the APICs
979 * themselves are programmed to send a timer interrupt. This is used
980 * by linux to reschedule the processor. Voyager doesn't have this,
981 * so we use the system clock to interrupt one processor, which in
982 * turn, broadcasts a timer CPI to all the others --- we receive that
983 * CPI here. We don't use this actually for counting so losing
984 * ticks doesn't matter
986 * FIXME: For those CPUs which actually have a local APIC, we could
987 * try to use it to trigger this interrupt instead of having to
988 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
989 * no local APIC, so I can't do this
991 * This function is currently a placeholder and is unused in the code */
992 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
994 struct pt_regs
*old_regs
= set_irq_regs(regs
);
995 wrapper_smp_local_timer_interrupt();
996 set_irq_regs(old_regs
);
999 /* All of the QUAD interrupt GATES */
1000 void smp_qic_timer_interrupt(struct pt_regs
*regs
)
1002 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1003 ack_QIC_CPI(QIC_TIMER_CPI
);
1004 wrapper_smp_local_timer_interrupt();
1005 set_irq_regs(old_regs
);
1008 void smp_qic_invalidate_interrupt(struct pt_regs
*regs
)
1010 ack_QIC_CPI(QIC_INVALIDATE_CPI
);
1011 smp_invalidate_interrupt();
1014 void smp_qic_reschedule_interrupt(struct pt_regs
*regs
)
1016 ack_QIC_CPI(QIC_RESCHEDULE_CPI
);
1017 smp_reschedule_interrupt();
1020 void smp_qic_enable_irq_interrupt(struct pt_regs
*regs
)
1022 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI
);
1023 smp_enable_irq_interrupt();
1026 void smp_qic_call_function_interrupt(struct pt_regs
*regs
)
1028 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI
);
1029 smp_call_function_interrupt();
1032 void smp_qic_call_function_single_interrupt(struct pt_regs
*regs
)
1034 ack_QIC_CPI(QIC_CALL_FUNCTION_SINGLE_CPI
);
1035 smp_call_function_single_interrupt();
1038 void smp_vic_cpi_interrupt(struct pt_regs
*regs
)
1040 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1041 __u8 cpu
= smp_processor_id();
1044 ack_QIC_CPI(VIC_CPI_LEVEL0
);
1046 ack_VIC_CPI(VIC_CPI_LEVEL0
);
1048 if (test_and_clear_bit(VIC_TIMER_CPI
, &vic_cpi_mailbox
[cpu
]))
1049 wrapper_smp_local_timer_interrupt();
1050 if (test_and_clear_bit(VIC_INVALIDATE_CPI
, &vic_cpi_mailbox
[cpu
]))
1051 smp_invalidate_interrupt();
1052 if (test_and_clear_bit(VIC_RESCHEDULE_CPI
, &vic_cpi_mailbox
[cpu
]))
1053 smp_reschedule_interrupt();
1054 if (test_and_clear_bit(VIC_ENABLE_IRQ_CPI
, &vic_cpi_mailbox
[cpu
]))
1055 smp_enable_irq_interrupt();
1056 if (test_and_clear_bit(VIC_CALL_FUNCTION_CPI
, &vic_cpi_mailbox
[cpu
]))
1057 smp_call_function_interrupt();
1058 if (test_and_clear_bit(VIC_CALL_FUNCTION_SINGLE_CPI
, &vic_cpi_mailbox
[cpu
]))
1059 smp_call_function_single_interrupt();
1060 set_irq_regs(old_regs
);
1063 static void do_flush_tlb_all(void *info
)
1065 unsigned long cpu
= smp_processor_id();
1068 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_LAZY
)
1069 voyager_leave_mm(cpu
);
1072 /* flush the TLB of every active CPU in the system */
1073 void flush_tlb_all(void)
1075 on_each_cpu(do_flush_tlb_all
, 0, 1);
1078 /* used to set up the trampoline for other CPUs when the memory manager
1080 void __init
smp_alloc_memory(void)
1082 trampoline_base
= alloc_bootmem_low_pages(PAGE_SIZE
);
1083 if (__pa(trampoline_base
) >= 0x93000)
1087 /* send a reschedule CPI to one CPU by physical CPU number*/
1088 static void voyager_smp_send_reschedule(int cpu
)
1090 send_one_CPI(cpu
, VIC_RESCHEDULE_CPI
);
1093 int hard_smp_processor_id(void)
1096 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
1097 if ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
)
1098 return cpumask
& 0x1F;
1100 for (i
= 0; i
< 8; i
++) {
1101 if (cpumask
& (1 << i
))
1104 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask
);
1108 int safe_smp_processor_id(void)
1110 return hard_smp_processor_id();
1113 /* broadcast a halt to all other CPUs */
1114 static void voyager_smp_send_stop(void)
1116 smp_call_function(smp_stop_cpu_function
, NULL
, 1);
1119 /* this function is triggered in time.c when a clock tick fires
1120 * we need to re-broadcast the tick to all CPUs */
1121 void smp_vic_timer_interrupt(void)
1123 send_CPI_allbutself(VIC_TIMER_CPI
);
1124 smp_local_timer_interrupt();
1127 /* local (per CPU) timer interrupt. It does both profiling and
1128 * process statistics/rescheduling.
1130 * We do profiling in every local tick, statistics/rescheduling
1131 * happen only every 'profiling multiplier' ticks. The default
1132 * multiplier is 1 and it can be changed by writing the new multiplier
1133 * value into /proc/profile.
1135 void smp_local_timer_interrupt(void)
1137 int cpu
= smp_processor_id();
1140 profile_tick(CPU_PROFILING
);
1141 if (--per_cpu(prof_counter
, cpu
) <= 0) {
1143 * The multiplier may have changed since the last time we got
1144 * to this point as a result of the user writing to
1145 * /proc/profile. In this case we need to adjust the APIC
1146 * timer accordingly.
1148 * Interrupts are already masked off at this point.
1150 per_cpu(prof_counter
, cpu
) = per_cpu(prof_multiplier
, cpu
);
1151 if (per_cpu(prof_counter
, cpu
) !=
1152 per_cpu(prof_old_multiplier
, cpu
)) {
1153 /* FIXME: need to update the vic timer tick here */
1154 per_cpu(prof_old_multiplier
, cpu
) =
1155 per_cpu(prof_counter
, cpu
);
1158 update_process_times(user_mode_vm(get_irq_regs()));
1161 if (((1 << cpu
) & voyager_extended_vic_processors
) == 0)
1162 /* only extended VIC processors participate in
1163 * interrupt distribution */
1167 * We take the 'long' return path, and there every subsystem
1168 * grabs the appropriate locks (kernel lock/ irq lock).
1170 * we might want to decouple profiling from the 'long path',
1171 * and do the profiling totally in assembly.
1173 * Currently this isn't too much of an issue (performance wise),
1174 * we can take more than 100K local irqs per second on a 100 MHz P5.
1177 if ((++vic_tick
[cpu
] & 0x7) != 0)
1179 /* get here every 16 ticks (about every 1/6 of a second) */
1181 /* Change our priority to give someone else a chance at getting
1182 * the IRQ. The algorithm goes like this:
1184 * In the VIC, the dynamically routed interrupt is always
1185 * handled by the lowest priority eligible (i.e. receiving
1186 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1187 * lowest processor number gets it.
1189 * The priority of a CPU is controlled by a special per-CPU
1190 * VIC priority register which is 3 bits wide 0 being lowest
1191 * and 7 highest priority..
1193 * Therefore we subtract the average number of interrupts from
1194 * the number we've fielded. If this number is negative, we
1195 * lower the activity count and if it is positive, we raise
1198 * I'm afraid this still leads to odd looking interrupt counts:
1199 * the totals are all roughly equal, but the individual ones
1200 * look rather skewed.
1202 * FIXME: This algorithm is total crap when mixed with SMP
1203 * affinity code since we now try to even up the interrupt
1204 * counts when an affinity binding is keeping them on a
1206 weight
= (vic_intr_count
[cpu
] * voyager_extended_cpus
1207 - vic_intr_total
) >> 4;
1214 outb((__u8
) weight
, VIC_PRIORITY_REGISTER
);
1216 #ifdef VOYAGER_DEBUG
1217 if ((vic_tick
[cpu
] & 0xFFF) == 0) {
1218 /* print this message roughly every 25 secs */
1219 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1220 cpu
, vic_tick
[cpu
], weight
);
1225 /* setup the profiling timer */
1226 int setup_profiling_timer(unsigned int multiplier
)
1234 * Set the new multiplier for each CPU. CPUs don't start using the
1235 * new values until the next timer interrupt in which they do process
1238 for (i
= 0; i
< NR_CPUS
; ++i
)
1239 per_cpu(prof_multiplier
, i
) = multiplier
;
1244 /* This is a bit of a mess, but forced on us by the genirq changes
1245 * there's no genirq handler that really does what voyager wants
1246 * so hack it up with the simple IRQ handler */
1247 static void handle_vic_irq(unsigned int irq
, struct irq_desc
*desc
)
1249 before_handle_vic_irq(irq
);
1250 handle_simple_irq(irq
, desc
);
1251 after_handle_vic_irq(irq
);
1254 /* The CPIs are handled in the per cpu 8259s, so they must be
1255 * enabled to be received: FIX: enabling the CPIs in the early
1256 * boot sequence interferes with bug checking; enable them later
1258 #define VIC_SET_GATE(cpi, vector) \
1259 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1260 #define QIC_SET_GATE(cpi, vector) \
1261 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1263 void __init
smp_intr_init(void)
1267 /* initialize the per cpu irq mask to all disabled */
1268 for (i
= 0; i
< NR_CPUS
; i
++)
1269 vic_irq_mask
[i
] = 0xFFFF;
1271 VIC_SET_GATE(VIC_CPI_LEVEL0
, vic_cpi_interrupt
);
1273 VIC_SET_GATE(VIC_SYS_INT
, vic_sys_interrupt
);
1274 VIC_SET_GATE(VIC_CMN_INT
, vic_cmn_interrupt
);
1276 QIC_SET_GATE(QIC_TIMER_CPI
, qic_timer_interrupt
);
1277 QIC_SET_GATE(QIC_INVALIDATE_CPI
, qic_invalidate_interrupt
);
1278 QIC_SET_GATE(QIC_RESCHEDULE_CPI
, qic_reschedule_interrupt
);
1279 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI
, qic_enable_irq_interrupt
);
1280 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI
, qic_call_function_interrupt
);
1282 /* now put the VIC descriptor into the first 48 IRQs
1284 * This is for later: first 16 correspond to PC IRQs; next 16
1285 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1286 for (i
= 0; i
< 48; i
++)
1287 set_irq_chip_and_handler(i
, &vic_chip
, handle_vic_irq
);
1290 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1291 * processor to receive CPI */
1292 static void send_CPI(__u32 cpuset
, __u8 cpi
)
1295 __u32 quad_cpuset
= (cpuset
& voyager_quad_processors
);
1297 if (cpi
< VIC_START_FAKE_CPI
) {
1298 /* fake CPI are only used for booting, so send to the
1299 * extended quads as well---Quads must be VIC booted */
1300 outb((__u8
) (cpuset
), VIC_CPI_Registers
[cpi
]);
1304 send_QIC_CPI(quad_cpuset
, cpi
);
1305 cpuset
&= ~quad_cpuset
;
1306 cpuset
&= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1309 for_each_online_cpu(cpu
) {
1310 if (cpuset
& (1 << cpu
))
1311 set_bit(cpi
, &vic_cpi_mailbox
[cpu
]);
1314 outb((__u8
) cpuset
, VIC_CPI_Registers
[VIC_CPI_LEVEL0
]);
1317 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1318 * set the cache line to shared by reading it.
1320 * DON'T make this inline otherwise the cache line read will be
1323 static int ack_QIC_CPI(__u8 cpi
)
1325 __u8 cpu
= hard_smp_processor_id();
1329 outb(1 << cpi
, QIC_INTERRUPT_CLEAR1
);
1330 return voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
;
1333 static void ack_special_QIC_CPI(__u8 cpi
)
1337 outb(QIC_CMN_INT
, QIC_INTERRUPT_CLEAR0
);
1340 outb(QIC_SYS_INT
, QIC_INTERRUPT_CLEAR0
);
1343 /* also clear at the VIC, just in case (nop for non-extended proc) */
1347 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1348 static void ack_VIC_CPI(__u8 cpi
)
1350 #ifdef VOYAGER_DEBUG
1351 unsigned long flags
;
1353 __u8 cpu
= smp_processor_id();
1355 local_irq_save(flags
);
1356 isr
= vic_read_isr();
1357 if ((isr
& (1 << (cpi
& 7))) == 0) {
1358 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu
, cpi
);
1361 /* send specific EOI; the two system interrupts have
1362 * bit 4 set for a separate vector but behave as the
1363 * corresponding 3 bit intr */
1364 outb_p(0x60 | (cpi
& 7), 0x20);
1366 #ifdef VOYAGER_DEBUG
1367 if ((vic_read_isr() & (1 << (cpi
& 7))) != 0) {
1368 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu
, cpi
);
1370 local_irq_restore(flags
);
1374 /* cribbed with thanks from irq.c */
1375 #define __byte(x,y) (((unsigned char *)&(y))[x])
1376 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1377 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1379 static unsigned int startup_vic_irq(unsigned int irq
)
1381 unmask_vic_irq(irq
);
1386 /* The enable and disable routines. This is where we run into
1387 * conflicting architectural philosophy. Fundamentally, the voyager
1388 * architecture does not expect to have to disable interrupts globally
1389 * (the IRQ controllers belong to each CPU). The processor masquerade
1390 * which is used to start the system shouldn't be used in a running OS
1391 * since it will cause great confusion if two separate CPUs drive to
1392 * the same IRQ controller (I know, I've tried it).
1394 * The solution is a variant on the NCR lazy SPL design:
1396 * 1) To disable an interrupt, do nothing (other than set the
1397 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1399 * 2) If the interrupt dares to come in, raise the local mask against
1400 * it (this will result in all the CPU masks being raised
1403 * 3) To enable the interrupt, lower the mask on the local CPU and
1404 * broadcast an Interrupt enable CPI which causes all other CPUs to
1405 * adjust their masks accordingly. */
1407 static void unmask_vic_irq(unsigned int irq
)
1409 /* linux doesn't to processor-irq affinity, so enable on
1410 * all CPUs we know about */
1411 int cpu
= smp_processor_id(), real_cpu
;
1412 __u16 mask
= (1 << irq
);
1413 __u32 processorList
= 0;
1414 unsigned long flags
;
1416 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
1417 irq
, cpu
, cpu_irq_affinity
[cpu
]));
1418 spin_lock_irqsave(&vic_irq_lock
, flags
);
1419 for_each_online_cpu(real_cpu
) {
1420 if (!(voyager_extended_vic_processors
& (1 << real_cpu
)))
1422 if (!(cpu_irq_affinity
[real_cpu
] & mask
)) {
1423 /* irq has no affinity for this CPU, ignore */
1426 if (real_cpu
== cpu
) {
1427 enable_local_vic_irq(irq
);
1428 } else if (vic_irq_mask
[real_cpu
] & mask
) {
1429 vic_irq_enable_mask
[real_cpu
] |= mask
;
1430 processorList
|= (1 << real_cpu
);
1433 spin_unlock_irqrestore(&vic_irq_lock
, flags
);
1435 send_CPI(processorList
, VIC_ENABLE_IRQ_CPI
);
1438 static void mask_vic_irq(unsigned int irq
)
1440 /* lazy disable, do nothing */
1443 static void enable_local_vic_irq(unsigned int irq
)
1445 __u8 cpu
= smp_processor_id();
1446 __u16 mask
= ~(1 << irq
);
1447 __u16 old_mask
= vic_irq_mask
[cpu
];
1449 vic_irq_mask
[cpu
] &= mask
;
1450 if (vic_irq_mask
[cpu
] == old_mask
)
1453 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1457 outb_p(cached_A1(cpu
), 0xA1);
1460 outb_p(cached_21(cpu
), 0x21);
1465 static void disable_local_vic_irq(unsigned int irq
)
1467 __u8 cpu
= smp_processor_id();
1468 __u16 mask
= (1 << irq
);
1469 __u16 old_mask
= vic_irq_mask
[cpu
];
1474 vic_irq_mask
[cpu
] |= mask
;
1475 if (old_mask
== vic_irq_mask
[cpu
])
1478 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1482 outb_p(cached_A1(cpu
), 0xA1);
1485 outb_p(cached_21(cpu
), 0x21);
1490 /* The VIC is level triggered, so the ack can only be issued after the
1491 * interrupt completes. However, we do Voyager lazy interrupt
1492 * handling here: It is an extremely expensive operation to mask an
1493 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1494 * this interrupt actually comes in, then we mask and ack here to push
1495 * the interrupt off to another CPU */
1496 static void before_handle_vic_irq(unsigned int irq
)
1498 irq_desc_t
*desc
= irq_desc
+ irq
;
1499 __u8 cpu
= smp_processor_id();
1501 _raw_spin_lock(&vic_irq_lock
);
1503 vic_intr_count
[cpu
]++;
1505 if (!(cpu_irq_affinity
[cpu
] & (1 << irq
))) {
1506 /* The irq is not in our affinity mask, push it off
1507 * onto another CPU */
1508 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d "
1509 "on cpu %d\n", irq
, cpu
));
1510 disable_local_vic_irq(irq
);
1511 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1512 * actually calling the interrupt routine */
1513 desc
->status
|= IRQ_REPLAY
| IRQ_INPROGRESS
;
1514 } else if (desc
->status
& IRQ_DISABLED
) {
1515 /* Damn, the interrupt actually arrived, do the lazy
1516 * disable thing. The interrupt routine in irq.c will
1517 * not handle a IRQ_DISABLED interrupt, so nothing more
1518 * need be done here */
1519 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1521 disable_local_vic_irq(irq
);
1522 desc
->status
|= IRQ_REPLAY
;
1524 desc
->status
&= ~IRQ_REPLAY
;
1527 _raw_spin_unlock(&vic_irq_lock
);
1530 /* Finish the VIC interrupt: basically mask */
1531 static void after_handle_vic_irq(unsigned int irq
)
1533 irq_desc_t
*desc
= irq_desc
+ irq
;
1535 _raw_spin_lock(&vic_irq_lock
);
1537 unsigned int status
= desc
->status
& ~IRQ_INPROGRESS
;
1538 #ifdef VOYAGER_DEBUG
1542 desc
->status
= status
;
1543 if ((status
& IRQ_DISABLED
))
1544 disable_local_vic_irq(irq
);
1545 #ifdef VOYAGER_DEBUG
1546 /* DEBUG: before we ack, check what's in progress */
1547 isr
= vic_read_isr();
1548 if ((isr
& (1 << irq
) && !(status
& IRQ_REPLAY
)) == 0) {
1550 __u8 cpu
= smp_processor_id();
1552 int mask
; /* Um... initialize me??? --RR */
1554 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1556 for_each_possible_cpu(real_cpu
, mask
) {
1558 outb(VIC_CPU_MASQUERADE_ENABLE
| real_cpu
,
1560 isr
= vic_read_isr();
1561 if (isr
& (1 << irq
)) {
1563 ("VOYAGER SMP: CPU%d ack irq %d\n",
1567 outb(cpu
, VIC_PROCESSOR_ID
);
1570 #endif /* VOYAGER_DEBUG */
1571 /* as soon as we ack, the interrupt is eligible for
1572 * receipt by another CPU so everything must be in
1575 if (status
& IRQ_REPLAY
) {
1576 /* replay is set if we disable the interrupt
1577 * in the before_handle_vic_irq() routine, so
1578 * clear the in progress bit here to allow the
1579 * next CPU to handle this correctly */
1580 desc
->status
&= ~(IRQ_REPLAY
| IRQ_INPROGRESS
);
1582 #ifdef VOYAGER_DEBUG
1583 isr
= vic_read_isr();
1584 if ((isr
& (1 << irq
)) != 0)
1585 printk("VOYAGER SMP: after_handle_vic_irq() after "
1586 "ack irq=%d, isr=0x%x\n", irq
, isr
);
1587 #endif /* VOYAGER_DEBUG */
1589 _raw_spin_unlock(&vic_irq_lock
);
1591 /* All code after this point is out of the main path - the IRQ
1592 * may be intercepted by another CPU if reasserted */
1595 /* Linux processor - interrupt affinity manipulations.
1597 * For each processor, we maintain a 32 bit irq affinity mask.
1598 * Initially it is set to all 1's so every processor accepts every
1599 * interrupt. In this call, we change the processor's affinity mask:
1601 * Change from enable to disable:
1603 * If the interrupt ever comes in to the processor, we will disable it
1604 * and ack it to push it off to another CPU, so just accept the mask here.
1606 * Change from disable to enable:
1608 * change the mask and then do an interrupt enable CPI to re-enable on
1609 * the selected processors */
1611 void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
)
1613 /* Only extended processors handle interrupts */
1614 unsigned long real_mask
;
1615 unsigned long irq_mask
= 1 << irq
;
1618 real_mask
= cpus_addr(mask
)[0] & voyager_extended_vic_processors
;
1620 if (cpus_addr(mask
)[0] == 0)
1621 /* can't have no CPUs to accept the interrupt -- extremely
1622 * bad things will happen */
1626 /* can't change the affinity of the timer IRQ. This
1627 * is due to the constraint in the voyager
1628 * architecture that the CPI also comes in on and IRQ
1629 * line and we have chosen IRQ0 for this. If you
1630 * raise the mask on this interrupt, the processor
1631 * will no-longer be able to accept VIC CPIs */
1635 /* You can only have 32 interrupts in a voyager system
1636 * (and 32 only if you have a secondary microchannel
1640 for_each_online_cpu(cpu
) {
1641 unsigned long cpu_mask
= 1 << cpu
;
1643 if (cpu_mask
& real_mask
) {
1644 /* enable the interrupt for this cpu */
1645 cpu_irq_affinity
[cpu
] |= irq_mask
;
1647 /* disable the interrupt for this cpu */
1648 cpu_irq_affinity
[cpu
] &= ~irq_mask
;
1651 /* this is magic, we now have the correct affinity maps, so
1652 * enable the interrupt. This will send an enable CPI to
1653 * those CPUs who need to enable it in their local masks,
1654 * causing them to correct for the new affinity . If the
1655 * interrupt is currently globally disabled, it will simply be
1656 * disabled again as it comes in (voyager lazy disable). If
1657 * the affinity map is tightened to disable the interrupt on a
1658 * cpu, it will be pushed off when it comes in */
1659 unmask_vic_irq(irq
);
1662 static void ack_vic_irq(unsigned int irq
)
1665 outb(0x62, 0x20); /* Specific EOI to cascade */
1666 outb(0x60 | (irq
& 7), 0xA0);
1668 outb(0x60 | (irq
& 7), 0x20);
1672 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1673 * but are not vectored by it. This means that the 8259 mask must be
1674 * lowered to receive them */
1675 static __init
void vic_enable_cpi(void)
1677 __u8 cpu
= smp_processor_id();
1679 /* just take a copy of the current mask (nop for boot cpu) */
1680 vic_irq_mask
[cpu
] = vic_irq_mask
[boot_cpu_id
];
1682 enable_local_vic_irq(VIC_CPI_LEVEL0
);
1683 enable_local_vic_irq(VIC_CPI_LEVEL1
);
1684 /* for sys int and cmn int */
1685 enable_local_vic_irq(7);
1687 if (is_cpu_quad()) {
1688 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
1689 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
1690 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1691 cpu
, QIC_CPI_ENABLE
));
1694 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1695 cpu
, vic_irq_mask
[cpu
]));
1698 void voyager_smp_dump()
1700 int old_cpu
= smp_processor_id(), cpu
;
1702 /* dump the interrupt masks of each processor */
1703 for_each_online_cpu(cpu
) {
1704 __u16 imr
, isr
, irr
;
1705 unsigned long flags
;
1707 local_irq_save(flags
);
1708 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
1709 imr
= (inb(0xa1) << 8) | inb(0x21);
1711 irr
= inb(0xa0) << 8;
1715 isr
= inb(0xa0) << 8;
1718 outb(old_cpu
, VIC_PROCESSOR_ID
);
1719 local_irq_restore(flags
);
1720 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1721 cpu
, vic_irq_mask
[cpu
], imr
, irr
, isr
);
1723 /* These lines are put in to try to unstick an un ack'd irq */
1726 for (irq
= 0; irq
< 16; irq
++) {
1727 if (isr
& (1 << irq
)) {
1728 printk("\tCPU%d: ack irq %d\n",
1730 local_irq_save(flags
);
1731 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
,
1734 outb(old_cpu
, VIC_PROCESSOR_ID
);
1735 local_irq_restore(flags
);
1743 void smp_voyager_power_off(void *dummy
)
1745 if (smp_processor_id() == boot_cpu_id
)
1746 voyager_power_off();
1748 smp_stop_cpu_function(NULL
);
1751 static void __init
voyager_smp_prepare_cpus(unsigned int max_cpus
)
1753 /* FIXME: ignore max_cpus for now */
1757 static void __cpuinit
voyager_smp_prepare_boot_cpu(void)
1759 init_gdt(smp_processor_id());
1760 switch_to_new_gdt();
1762 cpu_set(smp_processor_id(), cpu_online_map
);
1763 cpu_set(smp_processor_id(), cpu_callout_map
);
1764 cpu_set(smp_processor_id(), cpu_possible_map
);
1765 cpu_set(smp_processor_id(), cpu_present_map
);
1768 static int __cpuinit
voyager_cpu_up(unsigned int cpu
)
1770 /* This only works at boot for x86. See "rewrite" above. */
1771 if (cpu_isset(cpu
, smp_commenced_mask
))
1774 /* In case one didn't come up */
1775 if (!cpu_isset(cpu
, cpu_callin_map
))
1777 /* Unleash the CPU! */
1778 cpu_set(cpu
, smp_commenced_mask
);
1779 while (!cpu_online(cpu
))
1784 static void __init
voyager_smp_cpus_done(unsigned int max_cpus
)
1789 void __init
smp_setup_processor_id(void)
1791 current_thread_info()->cpu
= hard_smp_processor_id();
1792 x86_write_percpu(cpu_number
, hard_smp_processor_id());
1795 struct smp_ops smp_ops
= {
1796 .smp_prepare_boot_cpu
= voyager_smp_prepare_boot_cpu
,
1797 .smp_prepare_cpus
= voyager_smp_prepare_cpus
,
1798 .cpu_up
= voyager_cpu_up
,
1799 .smp_cpus_done
= voyager_smp_cpus_done
,
1801 .smp_send_stop
= voyager_smp_send_stop
,
1802 .smp_send_reschedule
= voyager_smp_send_reschedule
,
1804 .send_call_func_ipi
= native_send_call_func_ipi
,
1805 .send_call_func_single_ipi
= native_send_call_func_single_ipi
,