1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * This file provides all the same external entries as smp.c but uses
8 * the voyager hal to provide the functionality
10 #include <linux/cpu.h>
11 #include <linux/module.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/delay.h>
15 #include <linux/mc146818rtc.h>
16 #include <linux/cache.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/bootmem.h>
21 #include <linux/completion.h>
23 #include <asm/voyager.h>
26 #include <asm/pgalloc.h>
27 #include <asm/tlbflush.h>
28 #include <asm/arch_hooks.h>
29 #include <asm/trampoline.h>
31 /* TLB state -- visible externally, indexed physically */
32 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state
, cpu_tlbstate
) = { &init_mm
, 0 };
34 /* CPU IRQ affinity -- set to all ones initially */
35 static unsigned long cpu_irq_affinity
[NR_CPUS
] __cacheline_aligned
=
36 {[0 ... NR_CPUS
-1] = ~0UL };
38 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
39 * indexed physically */
40 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
41 EXPORT_PER_CPU_SYMBOL(cpu_info
);
43 /* physical ID of the CPU used to boot the system */
44 unsigned char boot_cpu_id
;
46 /* The memory line addresses for the Quad CPIs */
47 struct voyager_qic_cpi
*voyager_quad_cpi_addr
[NR_CPUS
] __cacheline_aligned
;
49 /* The masks for the Extended VIC processors, filled in by cat_init */
50 __u32 voyager_extended_vic_processors
= 0;
52 /* Masks for the extended Quad processors which cannot be VIC booted */
53 __u32 voyager_allowed_boot_processors
= 0;
55 /* The mask for the Quad Processors (both extended and non-extended) */
56 __u32 voyager_quad_processors
= 0;
58 /* Total count of live CPUs, used in process.c to display
59 * the CPU information and in irq.c for the per CPU irq
60 * activity count. Finally exported by i386_ksyms.c */
61 static int voyager_extended_cpus
= 1;
63 /* Used for the invalidate map that's also checked in the spinlock */
64 static volatile unsigned long smp_invalidate_needed
;
66 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
67 * by scheduler but indexed physically */
68 cpumask_t phys_cpu_present_map
= CPU_MASK_NONE
;
70 /* The internal functions */
71 static void send_CPI(__u32 cpuset
, __u8 cpi
);
72 static void ack_CPI(__u8 cpi
);
73 static int ack_QIC_CPI(__u8 cpi
);
74 static void ack_special_QIC_CPI(__u8 cpi
);
75 static void ack_VIC_CPI(__u8 cpi
);
76 static void send_CPI_allbutself(__u8 cpi
);
77 static void mask_vic_irq(unsigned int irq
);
78 static void unmask_vic_irq(unsigned int irq
);
79 static unsigned int startup_vic_irq(unsigned int irq
);
80 static void enable_local_vic_irq(unsigned int irq
);
81 static void disable_local_vic_irq(unsigned int irq
);
82 static void before_handle_vic_irq(unsigned int irq
);
83 static void after_handle_vic_irq(unsigned int irq
);
84 static void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
);
85 static void ack_vic_irq(unsigned int irq
);
86 static void vic_enable_cpi(void);
87 static void do_boot_cpu(__u8 cpuid
);
88 static void do_quad_bootstrap(void);
89 static void initialize_secondary(void);
91 int hard_smp_processor_id(void);
92 int safe_smp_processor_id(void);
94 /* Inline functions */
95 static inline void send_one_QIC_CPI(__u8 cpu
, __u8 cpi
)
97 voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
=
98 (smp_processor_id() << 16) + cpi
;
101 static inline void send_QIC_CPI(__u32 cpuset
, __u8 cpi
)
105 for_each_online_cpu(cpu
) {
106 if (cpuset
& (1 << cpu
)) {
108 if (!cpu_online(cpu
))
109 VDEBUG(("CPU%d sending cpi %d to CPU%d not in "
111 hard_smp_processor_id(), cpi
, cpu
));
113 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
118 static inline void wrapper_smp_local_timer_interrupt(void)
121 smp_local_timer_interrupt();
125 static inline void send_one_CPI(__u8 cpu
, __u8 cpi
)
127 if (voyager_quad_processors
& (1 << cpu
))
128 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
130 send_CPI(1 << cpu
, cpi
);
133 static inline void send_CPI_allbutself(__u8 cpi
)
135 __u8 cpu
= smp_processor_id();
136 __u32 mask
= cpus_addr(cpu_online_map
)[0] & ~(1 << cpu
);
140 static inline int is_cpu_quad(void)
142 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
143 return ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
);
146 static inline int is_cpu_extended(void)
148 __u8 cpu
= hard_smp_processor_id();
150 return (voyager_extended_vic_processors
& (1 << cpu
));
153 static inline int is_cpu_vic_boot(void)
155 __u8 cpu
= hard_smp_processor_id();
157 return (voyager_extended_vic_processors
158 & voyager_allowed_boot_processors
& (1 << cpu
));
161 static inline void ack_CPI(__u8 cpi
)
164 case VIC_CPU_BOOT_CPI
:
165 if (is_cpu_quad() && !is_cpu_vic_boot())
172 /* These are slightly strange. Even on the Quad card,
173 * They are vectored as VIC CPIs */
175 ack_special_QIC_CPI(cpi
);
180 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi
);
185 /* local variables */
187 /* The VIC IRQ descriptors -- these look almost identical to the
188 * 8259 IRQs except that masks and things must be kept per processor
190 static struct irq_chip vic_chip
= {
192 .startup
= startup_vic_irq
,
193 .mask
= mask_vic_irq
,
194 .unmask
= unmask_vic_irq
,
195 .set_affinity
= set_vic_irq_affinity
,
198 /* used to count up as CPUs are brought on line (starts at 0) */
199 static int cpucount
= 0;
201 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
202 static DEFINE_PER_CPU(int, prof_multiplier
) = 1;
203 static DEFINE_PER_CPU(int, prof_old_multiplier
) = 1;
204 static DEFINE_PER_CPU(int, prof_counter
) = 1;
206 /* the map used to check if a CPU has booted */
207 static __u32 cpu_booted_map
;
209 /* the synchronize flag used to hold all secondary CPUs spinning in
210 * a tight loop until the boot sequence is ready for them */
211 static cpumask_t smp_commenced_mask
= CPU_MASK_NONE
;
213 /* This is for the new dynamic CPU boot code */
214 cpumask_t cpu_callin_map
= CPU_MASK_NONE
;
215 cpumask_t cpu_callout_map
= CPU_MASK_NONE
;
217 /* The per processor IRQ masks (these are usually kept in sync) */
218 static __u16 vic_irq_mask
[NR_CPUS
] __cacheline_aligned
;
220 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
221 static __u16 vic_irq_enable_mask
[NR_CPUS
] __cacheline_aligned
= { 0 };
223 /* Lock for enable/disable of VIC interrupts */
224 static __cacheline_aligned
DEFINE_SPINLOCK(vic_irq_lock
);
226 /* The boot processor is correctly set up in PC mode when it
227 * comes up, but the secondaries need their master/slave 8259
228 * pairs initializing correctly */
230 /* Interrupt counters (per cpu) and total - used to try to
231 * even up the interrupt handling routines */
232 static long vic_intr_total
= 0;
233 static long vic_intr_count
[NR_CPUS
] __cacheline_aligned
= { 0 };
234 static unsigned long vic_tick
[NR_CPUS
] __cacheline_aligned
= { 0 };
236 /* Since we can only use CPI0, we fake all the other CPIs */
237 static unsigned long vic_cpi_mailbox
[NR_CPUS
] __cacheline_aligned
;
239 /* debugging routine to read the isr of the cpu's pic */
240 static inline __u16
vic_read_isr(void)
245 isr
= inb(0xa0) << 8;
252 static __init
void qic_setup(void)
254 if (!is_cpu_quad()) {
255 /* not a quad, no setup */
258 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
259 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
261 if (is_cpu_extended()) {
262 /* the QIC duplicate of the VIC base register */
263 outb(VIC_DEFAULT_CPI_BASE
, QIC_VIC_CPI_BASE_REGISTER
);
264 outb(QIC_DEFAULT_CPI_BASE
, QIC_CPI_BASE_REGISTER
);
266 /* FIXME: should set up the QIC timer and memory parity
267 * error vectors here */
271 static __init
void vic_setup_pic(void)
273 outb(1, VIC_REDIRECT_REGISTER_1
);
274 /* clear the claim registers for dynamic routing */
275 outb(0, VIC_CLAIM_REGISTER_0
);
276 outb(0, VIC_CLAIM_REGISTER_1
);
278 outb(0, VIC_PRIORITY_REGISTER
);
279 /* Set the Primary and Secondary Microchannel vector
280 * bases to be the same as the ordinary interrupts
282 * FIXME: This would be more efficient using separate
284 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
285 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
286 /* Now initiallise the master PIC belonging to this CPU by
287 * sending the four ICWs */
289 /* ICW1: level triggered, ICW4 needed */
292 /* ICW2: vector base */
293 outb(FIRST_EXTERNAL_VECTOR
, 0x21);
295 /* ICW3: slave at line 2 */
298 /* ICW4: 8086 mode */
301 /* now the same for the slave PIC */
303 /* ICW1: level trigger, ICW4 needed */
306 /* ICW2: slave vector base */
307 outb(FIRST_EXTERNAL_VECTOR
+ 8, 0xA1);
312 /* ICW4: 8086 mode */
316 static void do_quad_bootstrap(void)
318 if (is_cpu_quad() && is_cpu_vic_boot()) {
321 __u8 cpuid
= hard_smp_processor_id();
323 local_irq_save(flags
);
325 for (i
= 0; i
< 4; i
++) {
326 /* FIXME: this would be >>3 &0x7 on the 32 way */
327 if (((cpuid
>> 2) & 0x03) == i
)
328 /* don't lower our own mask! */
331 /* masquerade as local Quad CPU */
332 outb(QIC_CPUID_ENABLE
| i
, QIC_PROCESSOR_ID
);
333 /* enable the startup CPI */
334 outb(QIC_BOOT_CPI_MASK
, QIC_MASK_REGISTER1
);
336 outb(0, QIC_PROCESSOR_ID
);
338 local_irq_restore(flags
);
342 void prefill_possible_map(void)
344 /* This is empty on voyager because we need a much
345 * earlier detection which is done in find_smp_config */
348 /* Set up all the basic stuff: read the SMP config and make all the
349 * SMP information reflect only the boot cpu. All others will be
350 * brought on-line later. */
351 void __init
find_smp_config(void)
355 boot_cpu_id
= hard_smp_processor_id();
357 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id
);
359 /* initialize the CPU structures (moved from smp_boot_cpus) */
360 for (i
= 0; i
< NR_CPUS
; i
++) {
361 cpu_irq_affinity
[i
] = ~0;
363 cpu_online_map
= cpumask_of_cpu(boot_cpu_id
);
365 /* The boot CPU must be extended */
366 voyager_extended_vic_processors
= 1 << boot_cpu_id
;
367 /* initially, all of the first 8 CPUs can boot */
368 voyager_allowed_boot_processors
= 0xff;
369 /* set up everything for just this CPU, we can alter
370 * this as we start the other CPUs later */
371 /* now get the CPU disposition from the extended CMOS */
372 cpus_addr(phys_cpu_present_map
)[0] =
373 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
);
374 cpus_addr(phys_cpu_present_map
)[0] |=
375 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+ 1) << 8;
376 cpus_addr(phys_cpu_present_map
)[0] |=
377 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+
379 cpus_addr(phys_cpu_present_map
)[0] |=
380 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+
382 cpu_possible_map
= phys_cpu_present_map
;
383 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n",
384 cpus_addr(phys_cpu_present_map
)[0]);
385 /* Here we set up the VIC to enable SMP */
386 /* enable the CPIs by writing the base vector to their register */
387 outb(VIC_DEFAULT_CPI_BASE
, VIC_CPI_BASE_REGISTER
);
388 outb(1, VIC_REDIRECT_REGISTER_1
);
389 /* set the claim registers for static routing --- Boot CPU gets
390 * all interrupts untill all other CPUs started */
391 outb(0xff, VIC_CLAIM_REGISTER_0
);
392 outb(0xff, VIC_CLAIM_REGISTER_1
);
393 /* Set the Primary and Secondary Microchannel vector
394 * bases to be the same as the ordinary interrupts
396 * FIXME: This would be more efficient using separate
398 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
399 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
401 /* Finally tell the firmware that we're driving */
402 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT
) | VOYAGER_IN_CONTROL_FLAG
,
403 VOYAGER_SUS_IN_CONTROL_PORT
);
405 current_thread_info()->cpu
= boot_cpu_id
;
406 x86_write_percpu(cpu_number
, boot_cpu_id
);
410 * The bootstrap kernel entry code has set these up. Save them
411 * for a given CPU, id is physical */
412 void __init
smp_store_cpu_info(int id
)
414 struct cpuinfo_x86
*c
= &cpu_data(id
);
419 identify_secondary_cpu(c
);
422 /* Routine initially called when a non-boot CPU is brought online */
423 static void __init
start_secondary(void *unused
)
425 __u8 cpuid
= hard_smp_processor_id();
429 /* OK, we're in the routine */
430 ack_CPI(VIC_CPU_BOOT_CPI
);
432 /* setup the 8259 master slave pair belonging to this CPU ---
433 * we won't actually receive any until the boot CPU
434 * relinquishes it's static routing mask */
439 if (is_cpu_quad() && !is_cpu_vic_boot()) {
440 /* clear the boot CPI */
444 voyager_quad_cpi_addr
[cpuid
]->qic_cpi
[VIC_CPU_BOOT_CPI
].cpi
;
445 printk("read dummy %d\n", dummy
);
448 /* lower the mask to receive CPIs */
451 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid
, &cpuid
));
453 notify_cpu_starting(cpuid
);
455 /* enable interrupts */
458 /* get our bogomips */
461 /* save our processor parameters */
462 smp_store_cpu_info(cpuid
);
464 /* if we're a quad, we may need to bootstrap other CPUs */
467 /* FIXME: this is rather a poor hack to prevent the CPU
468 * activating softirqs while it's supposed to be waiting for
469 * permission to proceed. Without this, the new per CPU stuff
470 * in the softirqs will fail */
472 cpu_set(cpuid
, cpu_callin_map
);
474 /* signal that we're done */
477 while (!cpu_isset(cpuid
, smp_commenced_mask
))
483 cpu_set(cpuid
, cpu_online_map
);
488 /* Routine to kick start the given CPU and wait for it to report ready
489 * (or timeout in startup). When this routine returns, the requested
490 * CPU is either fully running and configured or known to be dead.
492 * We call this routine sequentially 1 CPU at a time, so no need for
495 static void __init
do_boot_cpu(__u8 cpu
)
497 struct task_struct
*idle
;
500 int quad_boot
= (1 << cpu
) & voyager_quad_processors
501 & ~(voyager_extended_vic_processors
502 & voyager_allowed_boot_processors
);
504 /* This is the format of the CPI IDT gate (in real mode) which
505 * we're hijacking to boot the CPU */
514 __u32
*hijack_vector
;
515 __u32 start_phys_address
= setup_trampoline();
517 /* There's a clever trick to this: The linux trampoline is
518 * compiled to begin at absolute location zero, so make the
519 * address zero but have the data segment selector compensate
520 * for the actual address */
521 hijack_source
.idt
.Offset
= start_phys_address
& 0x000F;
522 hijack_source
.idt
.Segment
= (start_phys_address
>> 4) & 0xFFFF;
525 alternatives_smp_switch(1);
527 idle
= fork_idle(cpu
);
529 panic("failed fork for CPU%d", cpu
);
530 idle
->thread
.ip
= (unsigned long)start_secondary
;
531 /* init_tasks (in sched.c) is indexed logically */
532 stack_start
.sp
= (void *)idle
->thread
.sp
;
535 per_cpu(current_task
, cpu
) = idle
;
536 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
539 /* Note: Don't modify initial ss override */
540 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu
,
541 (unsigned long)hijack_source
.val
, hijack_source
.idt
.Segment
,
542 hijack_source
.idt
.Offset
, stack_start
.sp
));
544 /* init lowmem identity mapping */
545 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ KERNEL_PGD_BOUNDARY
,
546 min_t(unsigned long, KERNEL_PGD_PTRS
, KERNEL_PGD_BOUNDARY
));
550 printk("CPU %d: non extended Quad boot\n", cpu
);
553 phys_to_virt((VIC_CPU_BOOT_CPI
+ QIC_DEFAULT_CPI_BASE
) * 4);
554 *hijack_vector
= hijack_source
.val
;
556 printk("CPU%d: extended VIC boot\n", cpu
);
559 phys_to_virt((VIC_CPU_BOOT_CPI
+ VIC_DEFAULT_CPI_BASE
) * 4);
560 *hijack_vector
= hijack_source
.val
;
561 /* VIC errata, may also receive interrupt at this address */
564 phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI
+
565 VIC_DEFAULT_CPI_BASE
) * 4);
566 *hijack_vector
= hijack_source
.val
;
568 /* All non-boot CPUs start with interrupts fully masked. Need
569 * to lower the mask of the CPI we're about to send. We do
570 * this in the VIC by masquerading as the processor we're
571 * about to boot and lowering its interrupt mask */
572 local_irq_save(flags
);
574 send_one_QIC_CPI(cpu
, VIC_CPU_BOOT_CPI
);
576 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
577 /* here we're altering registers belonging to `cpu' */
579 outb(VIC_BOOT_INTERRUPT_MASK
, 0x21);
580 /* now go back to our original identity */
581 outb(boot_cpu_id
, VIC_PROCESSOR_ID
);
583 /* and boot the CPU */
585 send_CPI((1 << cpu
), VIC_CPU_BOOT_CPI
);
588 local_irq_restore(flags
);
590 /* now wait for it to become ready (or timeout) */
591 for (timeout
= 0; timeout
< 50000; timeout
++) {
596 /* reset the page table */
599 if (cpu_booted_map
) {
600 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
601 cpu
, smp_processor_id()));
603 printk("CPU%d: ", cpu
);
604 print_cpu_info(&cpu_data(cpu
));
606 cpu_set(cpu
, cpu_callout_map
);
607 cpu_set(cpu
, cpu_present_map
);
609 printk("CPU%d FAILED TO BOOT: ", cpu
);
611 ((volatile unsigned char *)phys_to_virt(start_phys_address
))
615 printk("Not responding.\n");
621 void __init
smp_boot_cpus(void)
625 /* CAT BUS initialisation must be done after the memory */
626 /* FIXME: The L4 has a catbus too, it just needs to be
627 * accessed in a totally different way */
628 if (voyager_level
== 5) {
631 /* now that the cat has probed the Voyager System Bus, sanity
632 * check the cpu map */
633 if (((voyager_quad_processors
| voyager_extended_vic_processors
)
634 & cpus_addr(phys_cpu_present_map
)[0]) !=
635 cpus_addr(phys_cpu_present_map
)[0]) {
637 printk("\n\n***WARNING*** "
638 "Sanity check of CPU present map FAILED\n");
640 } else if (voyager_level
== 4)
641 voyager_extended_vic_processors
=
642 cpus_addr(phys_cpu_present_map
)[0];
644 /* this sets up the idle task to run on the current cpu */
645 voyager_extended_cpus
= 1;
646 /* Remove the global_irq_holder setting, it triggers a BUG() on
647 * schedule at the moment */
648 //global_irq_holder = boot_cpu_id;
650 /* FIXME: Need to do something about this but currently only works
651 * on CPUs with a tsc which none of mine have.
652 smp_tune_scheduling();
654 smp_store_cpu_info(boot_cpu_id
);
655 /* setup the jump vector */
656 initial_code
= (unsigned long)initialize_secondary
;
657 printk("CPU%d: ", boot_cpu_id
);
658 print_cpu_info(&cpu_data(boot_cpu_id
));
661 /* booting on a Quad CPU */
662 printk("VOYAGER SMP: Boot CPU is Quad\n");
667 /* enable our own CPIs */
670 cpu_set(boot_cpu_id
, cpu_online_map
);
671 cpu_set(boot_cpu_id
, cpu_callout_map
);
673 /* loop over all the extended VIC CPUs and boot them. The
674 * Quad CPUs must be bootstrapped by their extended VIC cpu */
675 for (i
= 0; i
< nr_cpu_ids
; i
++) {
676 if (i
== boot_cpu_id
|| !cpu_isset(i
, phys_cpu_present_map
))
679 /* This udelay seems to be needed for the Quad boots
680 * don't remove unless you know what you're doing */
683 /* we could compute the total bogomips here, but why bother?,
684 * Code added from smpboot.c */
686 unsigned long bogosum
= 0;
688 for_each_online_cpu(i
)
689 bogosum
+= cpu_data(i
).loops_per_jiffy
;
690 printk(KERN_INFO
"Total of %d processors activated "
691 "(%lu.%02lu BogoMIPS).\n",
692 cpucount
+ 1, bogosum
/ (500000 / HZ
),
693 (bogosum
/ (5000 / HZ
)) % 100);
695 voyager_extended_cpus
= hweight32(voyager_extended_vic_processors
);
696 printk("VOYAGER: Extended (interrupt handling CPUs): "
697 "%d, non-extended: %d\n", voyager_extended_cpus
,
698 num_booting_cpus() - voyager_extended_cpus
);
699 /* that's it, switch to symmetric mode */
700 outb(0, VIC_PRIORITY_REGISTER
);
701 outb(0, VIC_CLAIM_REGISTER_0
);
702 outb(0, VIC_CLAIM_REGISTER_1
);
704 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
707 /* Reload the secondary CPUs task structure (this function does not
709 static void __init
initialize_secondary(void)
713 set_current(hard_get_current());
717 * We don't actually need to load the full TSS,
718 * basically just the stack pointer and the eip.
721 asm volatile ("movl %0,%%esp\n\t"
722 "jmp *%1"::"r" (current
->thread
.sp
),
723 "r"(current
->thread
.ip
));
726 /* handle a Voyager SYS_INT -- If we don't, the base board will
729 * System interrupts occur because some problem was detected on the
730 * various busses. To find out what you have to probe all the
731 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
732 void smp_vic_sys_interrupt(struct pt_regs
*regs
)
734 ack_CPI(VIC_SYS_INT
);
735 printk("Voyager SYSTEM INTERRUPT\n");
738 /* Handle a voyager CMN_INT; These interrupts occur either because of
739 * a system status change or because a single bit memory error
740 * occurred. FIXME: At the moment, ignore all this. */
741 void smp_vic_cmn_interrupt(struct pt_regs
*regs
)
743 static __u8 in_cmn_int
= 0;
744 static DEFINE_SPINLOCK(cmn_int_lock
);
746 /* common ints are broadcast, so make sure we only do this once */
747 _raw_spin_lock(&cmn_int_lock
);
752 _raw_spin_unlock(&cmn_int_lock
);
754 VDEBUG(("Voyager COMMON INTERRUPT\n"));
756 if (voyager_level
== 5)
757 voyager_cat_do_common_interrupt();
759 _raw_spin_lock(&cmn_int_lock
);
762 _raw_spin_unlock(&cmn_int_lock
);
763 ack_CPI(VIC_CMN_INT
);
767 * Reschedule call back. Nothing to do, all the work is done
768 * automatically when we return from the interrupt. */
769 static void smp_reschedule_interrupt(void)
774 static struct mm_struct
*flush_mm
;
775 static unsigned long flush_va
;
776 static DEFINE_SPINLOCK(tlbstate_lock
);
779 * We cannot call mmdrop() because we are in interrupt context,
780 * instead update mm->cpu_vm_mask.
782 * We need to reload %cr3 since the page tables may be going
783 * away from under us..
785 static inline void voyager_leave_mm(unsigned long cpu
)
787 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
)
789 cpu_clear(cpu
, per_cpu(cpu_tlbstate
, cpu
).active_mm
->cpu_vm_mask
);
790 load_cr3(swapper_pg_dir
);
794 * Invalidate call-back
796 static void smp_invalidate_interrupt(void)
798 __u8 cpu
= smp_processor_id();
800 if (!test_bit(cpu
, &smp_invalidate_needed
))
802 /* This will flood messages. Don't uncomment unless you see
803 * Problems with cross cpu invalidation
804 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
805 smp_processor_id()));
808 if (flush_mm
== per_cpu(cpu_tlbstate
, cpu
).active_mm
) {
809 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
) {
810 if (flush_va
== TLB_FLUSH_ALL
)
813 __flush_tlb_one(flush_va
);
815 voyager_leave_mm(cpu
);
817 smp_mb__before_clear_bit();
818 clear_bit(cpu
, &smp_invalidate_needed
);
819 smp_mb__after_clear_bit();
822 /* All the new flush operations for 2.4 */
824 /* This routine is called with a physical cpu mask */
826 voyager_flush_tlb_others(unsigned long cpumask
, struct mm_struct
*mm
,
833 if ((cpumask
& cpus_addr(cpu_online_map
)[0]) != cpumask
)
835 if (cpumask
& (1 << smp_processor_id()))
840 spin_lock(&tlbstate_lock
);
844 atomic_set_mask(cpumask
, &smp_invalidate_needed
);
846 * We have to send the CPI only to
849 send_CPI(cpumask
, VIC_INVALIDATE_CPI
);
851 while (smp_invalidate_needed
) {
854 printk("***WARNING*** Stuck doing invalidate CPI "
855 "(CPU%d)\n", smp_processor_id());
860 /* Uncomment only to debug invalidation problems
861 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
866 spin_unlock(&tlbstate_lock
);
869 void flush_tlb_current_task(void)
871 struct mm_struct
*mm
= current
->mm
;
872 unsigned long cpu_mask
;
876 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
879 voyager_flush_tlb_others(cpu_mask
, mm
, TLB_FLUSH_ALL
);
884 void flush_tlb_mm(struct mm_struct
*mm
)
886 unsigned long cpu_mask
;
890 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
892 if (current
->active_mm
== mm
) {
896 voyager_leave_mm(smp_processor_id());
899 voyager_flush_tlb_others(cpu_mask
, mm
, TLB_FLUSH_ALL
);
904 void flush_tlb_page(struct vm_area_struct
*vma
, unsigned long va
)
906 struct mm_struct
*mm
= vma
->vm_mm
;
907 unsigned long cpu_mask
;
911 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
912 if (current
->active_mm
== mm
) {
916 voyager_leave_mm(smp_processor_id());
920 voyager_flush_tlb_others(cpu_mask
, mm
, va
);
925 EXPORT_SYMBOL(flush_tlb_page
);
927 /* enable the requested IRQs */
928 static void smp_enable_irq_interrupt(void)
931 __u8 cpu
= get_cpu();
933 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu
,
934 vic_irq_enable_mask
[cpu
]));
936 spin_lock(&vic_irq_lock
);
937 for (irq
= 0; irq
< 16; irq
++) {
938 if (vic_irq_enable_mask
[cpu
] & (1 << irq
))
939 enable_local_vic_irq(irq
);
941 vic_irq_enable_mask
[cpu
] = 0;
942 spin_unlock(&vic_irq_lock
);
944 put_cpu_no_resched();
950 static void smp_stop_cpu_function(void *dummy
)
952 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
953 cpu_clear(smp_processor_id(), cpu_online_map
);
959 /* execute a thread on a new CPU. The function to be called must be
960 * previously set up. This is used to schedule a function for
961 * execution on all CPUs - set up the function then broadcast a
962 * function_interrupt CPI to come here on each CPU */
963 static void smp_call_function_interrupt(void)
966 generic_smp_call_function_interrupt();
967 __get_cpu_var(irq_stat
).irq_call_count
++;
971 static void smp_call_function_single_interrupt(void)
974 generic_smp_call_function_single_interrupt();
975 __get_cpu_var(irq_stat
).irq_call_count
++;
979 /* Sorry about the name. In an APIC based system, the APICs
980 * themselves are programmed to send a timer interrupt. This is used
981 * by linux to reschedule the processor. Voyager doesn't have this,
982 * so we use the system clock to interrupt one processor, which in
983 * turn, broadcasts a timer CPI to all the others --- we receive that
984 * CPI here. We don't use this actually for counting so losing
985 * ticks doesn't matter
987 * FIXME: For those CPUs which actually have a local APIC, we could
988 * try to use it to trigger this interrupt instead of having to
989 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
990 * no local APIC, so I can't do this
992 * This function is currently a placeholder and is unused in the code */
993 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
995 struct pt_regs
*old_regs
= set_irq_regs(regs
);
996 wrapper_smp_local_timer_interrupt();
997 set_irq_regs(old_regs
);
1000 /* All of the QUAD interrupt GATES */
1001 void smp_qic_timer_interrupt(struct pt_regs
*regs
)
1003 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1004 ack_QIC_CPI(QIC_TIMER_CPI
);
1005 wrapper_smp_local_timer_interrupt();
1006 set_irq_regs(old_regs
);
1009 void smp_qic_invalidate_interrupt(struct pt_regs
*regs
)
1011 ack_QIC_CPI(QIC_INVALIDATE_CPI
);
1012 smp_invalidate_interrupt();
1015 void smp_qic_reschedule_interrupt(struct pt_regs
*regs
)
1017 ack_QIC_CPI(QIC_RESCHEDULE_CPI
);
1018 smp_reschedule_interrupt();
1021 void smp_qic_enable_irq_interrupt(struct pt_regs
*regs
)
1023 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI
);
1024 smp_enable_irq_interrupt();
1027 void smp_qic_call_function_interrupt(struct pt_regs
*regs
)
1029 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI
);
1030 smp_call_function_interrupt();
1033 void smp_qic_call_function_single_interrupt(struct pt_regs
*regs
)
1035 ack_QIC_CPI(QIC_CALL_FUNCTION_SINGLE_CPI
);
1036 smp_call_function_single_interrupt();
1039 void smp_vic_cpi_interrupt(struct pt_regs
*regs
)
1041 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1042 __u8 cpu
= smp_processor_id();
1045 ack_QIC_CPI(VIC_CPI_LEVEL0
);
1047 ack_VIC_CPI(VIC_CPI_LEVEL0
);
1049 if (test_and_clear_bit(VIC_TIMER_CPI
, &vic_cpi_mailbox
[cpu
]))
1050 wrapper_smp_local_timer_interrupt();
1051 if (test_and_clear_bit(VIC_INVALIDATE_CPI
, &vic_cpi_mailbox
[cpu
]))
1052 smp_invalidate_interrupt();
1053 if (test_and_clear_bit(VIC_RESCHEDULE_CPI
, &vic_cpi_mailbox
[cpu
]))
1054 smp_reschedule_interrupt();
1055 if (test_and_clear_bit(VIC_ENABLE_IRQ_CPI
, &vic_cpi_mailbox
[cpu
]))
1056 smp_enable_irq_interrupt();
1057 if (test_and_clear_bit(VIC_CALL_FUNCTION_CPI
, &vic_cpi_mailbox
[cpu
]))
1058 smp_call_function_interrupt();
1059 if (test_and_clear_bit(VIC_CALL_FUNCTION_SINGLE_CPI
, &vic_cpi_mailbox
[cpu
]))
1060 smp_call_function_single_interrupt();
1061 set_irq_regs(old_regs
);
1064 static void do_flush_tlb_all(void *info
)
1066 unsigned long cpu
= smp_processor_id();
1069 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_LAZY
)
1070 voyager_leave_mm(cpu
);
1073 /* flush the TLB of every active CPU in the system */
1074 void flush_tlb_all(void)
1076 on_each_cpu(do_flush_tlb_all
, 0, 1);
1079 /* send a reschedule CPI to one CPU by physical CPU number*/
1080 static void voyager_smp_send_reschedule(int cpu
)
1082 send_one_CPI(cpu
, VIC_RESCHEDULE_CPI
);
1085 int hard_smp_processor_id(void)
1088 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
1089 if ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
)
1090 return cpumask
& 0x1F;
1092 for (i
= 0; i
< 8; i
++) {
1093 if (cpumask
& (1 << i
))
1096 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask
);
1100 int safe_smp_processor_id(void)
1102 return hard_smp_processor_id();
1105 /* broadcast a halt to all other CPUs */
1106 static void voyager_smp_send_stop(void)
1108 smp_call_function(smp_stop_cpu_function
, NULL
, 1);
1111 /* this function is triggered in time.c when a clock tick fires
1112 * we need to re-broadcast the tick to all CPUs */
1113 void smp_vic_timer_interrupt(void)
1115 send_CPI_allbutself(VIC_TIMER_CPI
);
1116 smp_local_timer_interrupt();
1119 /* local (per CPU) timer interrupt. It does both profiling and
1120 * process statistics/rescheduling.
1122 * We do profiling in every local tick, statistics/rescheduling
1123 * happen only every 'profiling multiplier' ticks. The default
1124 * multiplier is 1 and it can be changed by writing the new multiplier
1125 * value into /proc/profile.
1127 void smp_local_timer_interrupt(void)
1129 int cpu
= smp_processor_id();
1132 profile_tick(CPU_PROFILING
);
1133 if (--per_cpu(prof_counter
, cpu
) <= 0) {
1135 * The multiplier may have changed since the last time we got
1136 * to this point as a result of the user writing to
1137 * /proc/profile. In this case we need to adjust the APIC
1138 * timer accordingly.
1140 * Interrupts are already masked off at this point.
1142 per_cpu(prof_counter
, cpu
) = per_cpu(prof_multiplier
, cpu
);
1143 if (per_cpu(prof_counter
, cpu
) !=
1144 per_cpu(prof_old_multiplier
, cpu
)) {
1145 /* FIXME: need to update the vic timer tick here */
1146 per_cpu(prof_old_multiplier
, cpu
) =
1147 per_cpu(prof_counter
, cpu
);
1150 update_process_times(user_mode_vm(get_irq_regs()));
1153 if (((1 << cpu
) & voyager_extended_vic_processors
) == 0)
1154 /* only extended VIC processors participate in
1155 * interrupt distribution */
1159 * We take the 'long' return path, and there every subsystem
1160 * grabs the appropriate locks (kernel lock/ irq lock).
1162 * we might want to decouple profiling from the 'long path',
1163 * and do the profiling totally in assembly.
1165 * Currently this isn't too much of an issue (performance wise),
1166 * we can take more than 100K local irqs per second on a 100 MHz P5.
1169 if ((++vic_tick
[cpu
] & 0x7) != 0)
1171 /* get here every 16 ticks (about every 1/6 of a second) */
1173 /* Change our priority to give someone else a chance at getting
1174 * the IRQ. The algorithm goes like this:
1176 * In the VIC, the dynamically routed interrupt is always
1177 * handled by the lowest priority eligible (i.e. receiving
1178 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1179 * lowest processor number gets it.
1181 * The priority of a CPU is controlled by a special per-CPU
1182 * VIC priority register which is 3 bits wide 0 being lowest
1183 * and 7 highest priority..
1185 * Therefore we subtract the average number of interrupts from
1186 * the number we've fielded. If this number is negative, we
1187 * lower the activity count and if it is positive, we raise
1190 * I'm afraid this still leads to odd looking interrupt counts:
1191 * the totals are all roughly equal, but the individual ones
1192 * look rather skewed.
1194 * FIXME: This algorithm is total crap when mixed with SMP
1195 * affinity code since we now try to even up the interrupt
1196 * counts when an affinity binding is keeping them on a
1198 weight
= (vic_intr_count
[cpu
] * voyager_extended_cpus
1199 - vic_intr_total
) >> 4;
1206 outb((__u8
) weight
, VIC_PRIORITY_REGISTER
);
1208 #ifdef VOYAGER_DEBUG
1209 if ((vic_tick
[cpu
] & 0xFFF) == 0) {
1210 /* print this message roughly every 25 secs */
1211 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1212 cpu
, vic_tick
[cpu
], weight
);
1217 /* setup the profiling timer */
1218 int setup_profiling_timer(unsigned int multiplier
)
1226 * Set the new multiplier for each CPU. CPUs don't start using the
1227 * new values until the next timer interrupt in which they do process
1230 for (i
= 0; i
< NR_CPUS
; ++i
)
1231 per_cpu(prof_multiplier
, i
) = multiplier
;
1236 /* This is a bit of a mess, but forced on us by the genirq changes
1237 * there's no genirq handler that really does what voyager wants
1238 * so hack it up with the simple IRQ handler */
1239 static void handle_vic_irq(unsigned int irq
, struct irq_desc
*desc
)
1241 before_handle_vic_irq(irq
);
1242 handle_simple_irq(irq
, desc
);
1243 after_handle_vic_irq(irq
);
1246 /* The CPIs are handled in the per cpu 8259s, so they must be
1247 * enabled to be received: FIX: enabling the CPIs in the early
1248 * boot sequence interferes with bug checking; enable them later
1250 #define VIC_SET_GATE(cpi, vector) \
1251 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1252 #define QIC_SET_GATE(cpi, vector) \
1253 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1255 void __init
voyager_smp_intr_init(void)
1259 /* initialize the per cpu irq mask to all disabled */
1260 for (i
= 0; i
< NR_CPUS
; i
++)
1261 vic_irq_mask
[i
] = 0xFFFF;
1263 VIC_SET_GATE(VIC_CPI_LEVEL0
, vic_cpi_interrupt
);
1265 VIC_SET_GATE(VIC_SYS_INT
, vic_sys_interrupt
);
1266 VIC_SET_GATE(VIC_CMN_INT
, vic_cmn_interrupt
);
1268 QIC_SET_GATE(QIC_TIMER_CPI
, qic_timer_interrupt
);
1269 QIC_SET_GATE(QIC_INVALIDATE_CPI
, qic_invalidate_interrupt
);
1270 QIC_SET_GATE(QIC_RESCHEDULE_CPI
, qic_reschedule_interrupt
);
1271 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI
, qic_enable_irq_interrupt
);
1272 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI
, qic_call_function_interrupt
);
1274 /* now put the VIC descriptor into the first 48 IRQs
1276 * This is for later: first 16 correspond to PC IRQs; next 16
1277 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1278 for (i
= 0; i
< 48; i
++)
1279 set_irq_chip_and_handler(i
, &vic_chip
, handle_vic_irq
);
1282 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1283 * processor to receive CPI */
1284 static void send_CPI(__u32 cpuset
, __u8 cpi
)
1287 __u32 quad_cpuset
= (cpuset
& voyager_quad_processors
);
1289 if (cpi
< VIC_START_FAKE_CPI
) {
1290 /* fake CPI are only used for booting, so send to the
1291 * extended quads as well---Quads must be VIC booted */
1292 outb((__u8
) (cpuset
), VIC_CPI_Registers
[cpi
]);
1296 send_QIC_CPI(quad_cpuset
, cpi
);
1297 cpuset
&= ~quad_cpuset
;
1298 cpuset
&= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1301 for_each_online_cpu(cpu
) {
1302 if (cpuset
& (1 << cpu
))
1303 set_bit(cpi
, &vic_cpi_mailbox
[cpu
]);
1306 outb((__u8
) cpuset
, VIC_CPI_Registers
[VIC_CPI_LEVEL0
]);
1309 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1310 * set the cache line to shared by reading it.
1312 * DON'T make this inline otherwise the cache line read will be
1315 static int ack_QIC_CPI(__u8 cpi
)
1317 __u8 cpu
= hard_smp_processor_id();
1321 outb(1 << cpi
, QIC_INTERRUPT_CLEAR1
);
1322 return voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
;
1325 static void ack_special_QIC_CPI(__u8 cpi
)
1329 outb(QIC_CMN_INT
, QIC_INTERRUPT_CLEAR0
);
1332 outb(QIC_SYS_INT
, QIC_INTERRUPT_CLEAR0
);
1335 /* also clear at the VIC, just in case (nop for non-extended proc) */
1339 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1340 static void ack_VIC_CPI(__u8 cpi
)
1342 #ifdef VOYAGER_DEBUG
1343 unsigned long flags
;
1345 __u8 cpu
= smp_processor_id();
1347 local_irq_save(flags
);
1348 isr
= vic_read_isr();
1349 if ((isr
& (1 << (cpi
& 7))) == 0) {
1350 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu
, cpi
);
1353 /* send specific EOI; the two system interrupts have
1354 * bit 4 set for a separate vector but behave as the
1355 * corresponding 3 bit intr */
1356 outb_p(0x60 | (cpi
& 7), 0x20);
1358 #ifdef VOYAGER_DEBUG
1359 if ((vic_read_isr() & (1 << (cpi
& 7))) != 0) {
1360 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu
, cpi
);
1362 local_irq_restore(flags
);
1366 /* cribbed with thanks from irq.c */
1367 #define __byte(x,y) (((unsigned char *)&(y))[x])
1368 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1369 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1371 static unsigned int startup_vic_irq(unsigned int irq
)
1373 unmask_vic_irq(irq
);
1378 /* The enable and disable routines. This is where we run into
1379 * conflicting architectural philosophy. Fundamentally, the voyager
1380 * architecture does not expect to have to disable interrupts globally
1381 * (the IRQ controllers belong to each CPU). The processor masquerade
1382 * which is used to start the system shouldn't be used in a running OS
1383 * since it will cause great confusion if two separate CPUs drive to
1384 * the same IRQ controller (I know, I've tried it).
1386 * The solution is a variant on the NCR lazy SPL design:
1388 * 1) To disable an interrupt, do nothing (other than set the
1389 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1391 * 2) If the interrupt dares to come in, raise the local mask against
1392 * it (this will result in all the CPU masks being raised
1395 * 3) To enable the interrupt, lower the mask on the local CPU and
1396 * broadcast an Interrupt enable CPI which causes all other CPUs to
1397 * adjust their masks accordingly. */
1399 static void unmask_vic_irq(unsigned int irq
)
1401 /* linux doesn't to processor-irq affinity, so enable on
1402 * all CPUs we know about */
1403 int cpu
= smp_processor_id(), real_cpu
;
1404 __u16 mask
= (1 << irq
);
1405 __u32 processorList
= 0;
1406 unsigned long flags
;
1408 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
1409 irq
, cpu
, cpu_irq_affinity
[cpu
]));
1410 spin_lock_irqsave(&vic_irq_lock
, flags
);
1411 for_each_online_cpu(real_cpu
) {
1412 if (!(voyager_extended_vic_processors
& (1 << real_cpu
)))
1414 if (!(cpu_irq_affinity
[real_cpu
] & mask
)) {
1415 /* irq has no affinity for this CPU, ignore */
1418 if (real_cpu
== cpu
) {
1419 enable_local_vic_irq(irq
);
1420 } else if (vic_irq_mask
[real_cpu
] & mask
) {
1421 vic_irq_enable_mask
[real_cpu
] |= mask
;
1422 processorList
|= (1 << real_cpu
);
1425 spin_unlock_irqrestore(&vic_irq_lock
, flags
);
1427 send_CPI(processorList
, VIC_ENABLE_IRQ_CPI
);
1430 static void mask_vic_irq(unsigned int irq
)
1432 /* lazy disable, do nothing */
1435 static void enable_local_vic_irq(unsigned int irq
)
1437 __u8 cpu
= smp_processor_id();
1438 __u16 mask
= ~(1 << irq
);
1439 __u16 old_mask
= vic_irq_mask
[cpu
];
1441 vic_irq_mask
[cpu
] &= mask
;
1442 if (vic_irq_mask
[cpu
] == old_mask
)
1445 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1449 outb_p(cached_A1(cpu
), 0xA1);
1452 outb_p(cached_21(cpu
), 0x21);
1457 static void disable_local_vic_irq(unsigned int irq
)
1459 __u8 cpu
= smp_processor_id();
1460 __u16 mask
= (1 << irq
);
1461 __u16 old_mask
= vic_irq_mask
[cpu
];
1466 vic_irq_mask
[cpu
] |= mask
;
1467 if (old_mask
== vic_irq_mask
[cpu
])
1470 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1474 outb_p(cached_A1(cpu
), 0xA1);
1477 outb_p(cached_21(cpu
), 0x21);
1482 /* The VIC is level triggered, so the ack can only be issued after the
1483 * interrupt completes. However, we do Voyager lazy interrupt
1484 * handling here: It is an extremely expensive operation to mask an
1485 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1486 * this interrupt actually comes in, then we mask and ack here to push
1487 * the interrupt off to another CPU */
1488 static void before_handle_vic_irq(unsigned int irq
)
1490 irq_desc_t
*desc
= irq_to_desc(irq
);
1491 __u8 cpu
= smp_processor_id();
1493 _raw_spin_lock(&vic_irq_lock
);
1495 vic_intr_count
[cpu
]++;
1497 if (!(cpu_irq_affinity
[cpu
] & (1 << irq
))) {
1498 /* The irq is not in our affinity mask, push it off
1499 * onto another CPU */
1500 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d "
1501 "on cpu %d\n", irq
, cpu
));
1502 disable_local_vic_irq(irq
);
1503 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1504 * actually calling the interrupt routine */
1505 desc
->status
|= IRQ_REPLAY
| IRQ_INPROGRESS
;
1506 } else if (desc
->status
& IRQ_DISABLED
) {
1507 /* Damn, the interrupt actually arrived, do the lazy
1508 * disable thing. The interrupt routine in irq.c will
1509 * not handle a IRQ_DISABLED interrupt, so nothing more
1510 * need be done here */
1511 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1513 disable_local_vic_irq(irq
);
1514 desc
->status
|= IRQ_REPLAY
;
1516 desc
->status
&= ~IRQ_REPLAY
;
1519 _raw_spin_unlock(&vic_irq_lock
);
1522 /* Finish the VIC interrupt: basically mask */
1523 static void after_handle_vic_irq(unsigned int irq
)
1525 irq_desc_t
*desc
= irq_to_desc(irq
);
1527 _raw_spin_lock(&vic_irq_lock
);
1529 unsigned int status
= desc
->status
& ~IRQ_INPROGRESS
;
1530 #ifdef VOYAGER_DEBUG
1534 desc
->status
= status
;
1535 if ((status
& IRQ_DISABLED
))
1536 disable_local_vic_irq(irq
);
1537 #ifdef VOYAGER_DEBUG
1538 /* DEBUG: before we ack, check what's in progress */
1539 isr
= vic_read_isr();
1540 if ((isr
& (1 << irq
) && !(status
& IRQ_REPLAY
)) == 0) {
1542 __u8 cpu
= smp_processor_id();
1544 int mask
; /* Um... initialize me??? --RR */
1546 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1548 for_each_possible_cpu(real_cpu
, mask
) {
1550 outb(VIC_CPU_MASQUERADE_ENABLE
| real_cpu
,
1552 isr
= vic_read_isr();
1553 if (isr
& (1 << irq
)) {
1555 ("VOYAGER SMP: CPU%d ack irq %d\n",
1559 outb(cpu
, VIC_PROCESSOR_ID
);
1562 #endif /* VOYAGER_DEBUG */
1563 /* as soon as we ack, the interrupt is eligible for
1564 * receipt by another CPU so everything must be in
1567 if (status
& IRQ_REPLAY
) {
1568 /* replay is set if we disable the interrupt
1569 * in the before_handle_vic_irq() routine, so
1570 * clear the in progress bit here to allow the
1571 * next CPU to handle this correctly */
1572 desc
->status
&= ~(IRQ_REPLAY
| IRQ_INPROGRESS
);
1574 #ifdef VOYAGER_DEBUG
1575 isr
= vic_read_isr();
1576 if ((isr
& (1 << irq
)) != 0)
1577 printk("VOYAGER SMP: after_handle_vic_irq() after "
1578 "ack irq=%d, isr=0x%x\n", irq
, isr
);
1579 #endif /* VOYAGER_DEBUG */
1581 _raw_spin_unlock(&vic_irq_lock
);
1583 /* All code after this point is out of the main path - the IRQ
1584 * may be intercepted by another CPU if reasserted */
1587 /* Linux processor - interrupt affinity manipulations.
1589 * For each processor, we maintain a 32 bit irq affinity mask.
1590 * Initially it is set to all 1's so every processor accepts every
1591 * interrupt. In this call, we change the processor's affinity mask:
1593 * Change from enable to disable:
1595 * If the interrupt ever comes in to the processor, we will disable it
1596 * and ack it to push it off to another CPU, so just accept the mask here.
1598 * Change from disable to enable:
1600 * change the mask and then do an interrupt enable CPI to re-enable on
1601 * the selected processors */
1603 void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
)
1605 /* Only extended processors handle interrupts */
1606 unsigned long real_mask
;
1607 unsigned long irq_mask
= 1 << irq
;
1610 real_mask
= cpus_addr(mask
)[0] & voyager_extended_vic_processors
;
1612 if (cpus_addr(mask
)[0] == 0)
1613 /* can't have no CPUs to accept the interrupt -- extremely
1614 * bad things will happen */
1618 /* can't change the affinity of the timer IRQ. This
1619 * is due to the constraint in the voyager
1620 * architecture that the CPI also comes in on and IRQ
1621 * line and we have chosen IRQ0 for this. If you
1622 * raise the mask on this interrupt, the processor
1623 * will no-longer be able to accept VIC CPIs */
1627 /* You can only have 32 interrupts in a voyager system
1628 * (and 32 only if you have a secondary microchannel
1632 for_each_online_cpu(cpu
) {
1633 unsigned long cpu_mask
= 1 << cpu
;
1635 if (cpu_mask
& real_mask
) {
1636 /* enable the interrupt for this cpu */
1637 cpu_irq_affinity
[cpu
] |= irq_mask
;
1639 /* disable the interrupt for this cpu */
1640 cpu_irq_affinity
[cpu
] &= ~irq_mask
;
1643 /* this is magic, we now have the correct affinity maps, so
1644 * enable the interrupt. This will send an enable CPI to
1645 * those CPUs who need to enable it in their local masks,
1646 * causing them to correct for the new affinity . If the
1647 * interrupt is currently globally disabled, it will simply be
1648 * disabled again as it comes in (voyager lazy disable). If
1649 * the affinity map is tightened to disable the interrupt on a
1650 * cpu, it will be pushed off when it comes in */
1651 unmask_vic_irq(irq
);
1654 static void ack_vic_irq(unsigned int irq
)
1657 outb(0x62, 0x20); /* Specific EOI to cascade */
1658 outb(0x60 | (irq
& 7), 0xA0);
1660 outb(0x60 | (irq
& 7), 0x20);
1664 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1665 * but are not vectored by it. This means that the 8259 mask must be
1666 * lowered to receive them */
1667 static __init
void vic_enable_cpi(void)
1669 __u8 cpu
= smp_processor_id();
1671 /* just take a copy of the current mask (nop for boot cpu) */
1672 vic_irq_mask
[cpu
] = vic_irq_mask
[boot_cpu_id
];
1674 enable_local_vic_irq(VIC_CPI_LEVEL0
);
1675 enable_local_vic_irq(VIC_CPI_LEVEL1
);
1676 /* for sys int and cmn int */
1677 enable_local_vic_irq(7);
1679 if (is_cpu_quad()) {
1680 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
1681 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
1682 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1683 cpu
, QIC_CPI_ENABLE
));
1686 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1687 cpu
, vic_irq_mask
[cpu
]));
1690 void voyager_smp_dump()
1692 int old_cpu
= smp_processor_id(), cpu
;
1694 /* dump the interrupt masks of each processor */
1695 for_each_online_cpu(cpu
) {
1696 __u16 imr
, isr
, irr
;
1697 unsigned long flags
;
1699 local_irq_save(flags
);
1700 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
1701 imr
= (inb(0xa1) << 8) | inb(0x21);
1703 irr
= inb(0xa0) << 8;
1707 isr
= inb(0xa0) << 8;
1710 outb(old_cpu
, VIC_PROCESSOR_ID
);
1711 local_irq_restore(flags
);
1712 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1713 cpu
, vic_irq_mask
[cpu
], imr
, irr
, isr
);
1715 /* These lines are put in to try to unstick an un ack'd irq */
1718 for (irq
= 0; irq
< 16; irq
++) {
1719 if (isr
& (1 << irq
)) {
1720 printk("\tCPU%d: ack irq %d\n",
1722 local_irq_save(flags
);
1723 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
,
1726 outb(old_cpu
, VIC_PROCESSOR_ID
);
1727 local_irq_restore(flags
);
1735 void smp_voyager_power_off(void *dummy
)
1737 if (smp_processor_id() == boot_cpu_id
)
1738 voyager_power_off();
1740 smp_stop_cpu_function(NULL
);
1743 static void __init
voyager_smp_prepare_cpus(unsigned int max_cpus
)
1745 /* FIXME: ignore max_cpus for now */
1749 static void __cpuinit
voyager_smp_prepare_boot_cpu(void)
1751 init_gdt(smp_processor_id());
1752 switch_to_new_gdt();
1754 cpu_set(smp_processor_id(), cpu_online_map
);
1755 cpu_set(smp_processor_id(), cpu_callout_map
);
1756 cpu_set(smp_processor_id(), cpu_possible_map
);
1757 cpu_set(smp_processor_id(), cpu_present_map
);
1760 static int __cpuinit
voyager_cpu_up(unsigned int cpu
)
1762 /* This only works at boot for x86. See "rewrite" above. */
1763 if (cpu_isset(cpu
, smp_commenced_mask
))
1766 /* In case one didn't come up */
1767 if (!cpu_isset(cpu
, cpu_callin_map
))
1769 /* Unleash the CPU! */
1770 cpu_set(cpu
, smp_commenced_mask
);
1771 while (!cpu_online(cpu
))
1776 static void __init
voyager_smp_cpus_done(unsigned int max_cpus
)
1781 void __init
smp_setup_processor_id(void)
1783 current_thread_info()->cpu
= hard_smp_processor_id();
1784 x86_write_percpu(cpu_number
, hard_smp_processor_id());
1787 static void voyager_send_call_func(cpumask_t callmask
)
1789 __u32 mask
= cpus_addr(callmask
)[0] & ~(1 << smp_processor_id());
1790 send_CPI(mask
, VIC_CALL_FUNCTION_CPI
);
1793 static void voyager_send_call_func_single(int cpu
)
1795 send_CPI(1 << cpu
, VIC_CALL_FUNCTION_SINGLE_CPI
);
1798 struct smp_ops smp_ops
= {
1799 .smp_prepare_boot_cpu
= voyager_smp_prepare_boot_cpu
,
1800 .smp_prepare_cpus
= voyager_smp_prepare_cpus
,
1801 .cpu_up
= voyager_cpu_up
,
1802 .smp_cpus_done
= voyager_smp_cpus_done
,
1804 .smp_send_stop
= voyager_smp_send_stop
,
1805 .smp_send_reschedule
= voyager_smp_send_reschedule
,
1807 .send_call_func_ipi
= voyager_send_call_func
,
1808 .send_call_func_single_ipi
= voyager_send_call_func_single
,