1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * linux/arch/i386/kernel/voyager_smp.c
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
12 #include <linux/module.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/mc146818rtc.h>
17 #include <linux/cache.h>
18 #include <linux/interrupt.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/bootmem.h>
22 #include <linux/completion.h>
24 #include <asm/voyager.h>
27 #include <asm/pgalloc.h>
28 #include <asm/tlbflush.h>
29 #include <asm/arch_hooks.h>
30 #include <asm/trampoline.h>
32 /* TLB state -- visible externally, indexed physically */
33 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state
, cpu_tlbstate
) = { &init_mm
, 0 };
35 /* CPU IRQ affinity -- set to all ones initially */
36 static unsigned long cpu_irq_affinity
[NR_CPUS
] __cacheline_aligned
=
37 {[0 ... NR_CPUS
-1] = ~0UL };
39 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
40 * indexed physically */
41 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
42 EXPORT_PER_CPU_SYMBOL(cpu_info
);
44 /* physical ID of the CPU used to boot the system */
45 unsigned char boot_cpu_id
;
47 /* The memory line addresses for the Quad CPIs */
48 struct voyager_qic_cpi
*voyager_quad_cpi_addr
[NR_CPUS
] __cacheline_aligned
;
50 /* The masks for the Extended VIC processors, filled in by cat_init */
51 __u32 voyager_extended_vic_processors
= 0;
53 /* Masks for the extended Quad processors which cannot be VIC booted */
54 __u32 voyager_allowed_boot_processors
= 0;
56 /* The mask for the Quad Processors (both extended and non-extended) */
57 __u32 voyager_quad_processors
= 0;
59 /* Total count of live CPUs, used in process.c to display
60 * the CPU information and in irq.c for the per CPU irq
61 * activity count. Finally exported by i386_ksyms.c */
62 static int voyager_extended_cpus
= 1;
64 /* Have we found an SMP box - used by time.c to do the profiling
65 interrupt for timeslicing; do not set to 1 until the per CPU timer
66 interrupt is active */
67 int smp_found_config
= 0;
69 /* Used for the invalidate map that's also checked in the spinlock */
70 static volatile unsigned long smp_invalidate_needed
;
72 /* Bitmask of currently online CPUs - used by setup.c for
73 /proc/cpuinfo, visible externally but still physical */
74 cpumask_t cpu_online_map
= CPU_MASK_NONE
;
75 EXPORT_SYMBOL(cpu_online_map
);
77 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
78 * by scheduler but indexed physically */
79 cpumask_t phys_cpu_present_map
= CPU_MASK_NONE
;
81 /* The internal functions */
82 static void send_CPI(__u32 cpuset
, __u8 cpi
);
83 static void ack_CPI(__u8 cpi
);
84 static int ack_QIC_CPI(__u8 cpi
);
85 static void ack_special_QIC_CPI(__u8 cpi
);
86 static void ack_VIC_CPI(__u8 cpi
);
87 static void send_CPI_allbutself(__u8 cpi
);
88 static void mask_vic_irq(unsigned int irq
);
89 static void unmask_vic_irq(unsigned int irq
);
90 static unsigned int startup_vic_irq(unsigned int irq
);
91 static void enable_local_vic_irq(unsigned int irq
);
92 static void disable_local_vic_irq(unsigned int irq
);
93 static void before_handle_vic_irq(unsigned int irq
);
94 static void after_handle_vic_irq(unsigned int irq
);
95 static void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
);
96 static void ack_vic_irq(unsigned int irq
);
97 static void vic_enable_cpi(void);
98 static void do_boot_cpu(__u8 cpuid
);
99 static void do_quad_bootstrap(void);
101 int hard_smp_processor_id(void);
102 int safe_smp_processor_id(void);
104 /* Inline functions */
105 static inline void send_one_QIC_CPI(__u8 cpu
, __u8 cpi
)
107 voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
=
108 (smp_processor_id() << 16) + cpi
;
111 static inline void send_QIC_CPI(__u32 cpuset
, __u8 cpi
)
115 for_each_online_cpu(cpu
) {
116 if (cpuset
& (1 << cpu
)) {
118 if (!cpu_isset(cpu
, cpu_online_map
))
119 VDEBUG(("CPU%d sending cpi %d to CPU%d not in "
121 hard_smp_processor_id(), cpi
, cpu
));
123 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
128 static inline void wrapper_smp_local_timer_interrupt(void)
131 smp_local_timer_interrupt();
135 static inline void send_one_CPI(__u8 cpu
, __u8 cpi
)
137 if (voyager_quad_processors
& (1 << cpu
))
138 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
140 send_CPI(1 << cpu
, cpi
);
143 static inline void send_CPI_allbutself(__u8 cpi
)
145 __u8 cpu
= smp_processor_id();
146 __u32 mask
= cpus_addr(cpu_online_map
)[0] & ~(1 << cpu
);
150 static inline int is_cpu_quad(void)
152 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
153 return ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
);
156 static inline int is_cpu_extended(void)
158 __u8 cpu
= hard_smp_processor_id();
160 return (voyager_extended_vic_processors
& (1 << cpu
));
163 static inline int is_cpu_vic_boot(void)
165 __u8 cpu
= hard_smp_processor_id();
167 return (voyager_extended_vic_processors
168 & voyager_allowed_boot_processors
& (1 << cpu
));
171 static inline void ack_CPI(__u8 cpi
)
174 case VIC_CPU_BOOT_CPI
:
175 if (is_cpu_quad() && !is_cpu_vic_boot())
182 /* These are slightly strange. Even on the Quad card,
183 * They are vectored as VIC CPIs */
185 ack_special_QIC_CPI(cpi
);
190 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi
);
195 /* local variables */
197 /* The VIC IRQ descriptors -- these look almost identical to the
198 * 8259 IRQs except that masks and things must be kept per processor
200 static struct irq_chip vic_chip
= {
202 .startup
= startup_vic_irq
,
203 .mask
= mask_vic_irq
,
204 .unmask
= unmask_vic_irq
,
205 .set_affinity
= set_vic_irq_affinity
,
208 /* used to count up as CPUs are brought on line (starts at 0) */
209 static int cpucount
= 0;
211 /* steal a page from the bottom of memory for the trampoline and
212 * squirrel its address away here. This will be in kernel virtual
214 unsigned char *trampoline_base
;
216 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
217 static DEFINE_PER_CPU(int, prof_multiplier
) = 1;
218 static DEFINE_PER_CPU(int, prof_old_multiplier
) = 1;
219 static DEFINE_PER_CPU(int, prof_counter
) = 1;
221 /* the map used to check if a CPU has booted */
222 static __u32 cpu_booted_map
;
224 /* the synchronize flag used to hold all secondary CPUs spinning in
225 * a tight loop until the boot sequence is ready for them */
226 static cpumask_t smp_commenced_mask
= CPU_MASK_NONE
;
228 /* This is for the new dynamic CPU boot code */
229 cpumask_t cpu_callin_map
= CPU_MASK_NONE
;
230 cpumask_t cpu_callout_map
= CPU_MASK_NONE
;
231 cpumask_t cpu_possible_map
= CPU_MASK_NONE
;
232 EXPORT_SYMBOL(cpu_possible_map
);
234 /* The per processor IRQ masks (these are usually kept in sync) */
235 static __u16 vic_irq_mask
[NR_CPUS
] __cacheline_aligned
;
237 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
238 static __u16 vic_irq_enable_mask
[NR_CPUS
] __cacheline_aligned
= { 0 };
240 /* Lock for enable/disable of VIC interrupts */
241 static __cacheline_aligned
DEFINE_SPINLOCK(vic_irq_lock
);
243 /* The boot processor is correctly set up in PC mode when it
244 * comes up, but the secondaries need their master/slave 8259
245 * pairs initializing correctly */
247 /* Interrupt counters (per cpu) and total - used to try to
248 * even up the interrupt handling routines */
249 static long vic_intr_total
= 0;
250 static long vic_intr_count
[NR_CPUS
] __cacheline_aligned
= { 0 };
251 static unsigned long vic_tick
[NR_CPUS
] __cacheline_aligned
= { 0 };
253 /* Since we can only use CPI0, we fake all the other CPIs */
254 static unsigned long vic_cpi_mailbox
[NR_CPUS
] __cacheline_aligned
;
256 /* debugging routine to read the isr of the cpu's pic */
257 static inline __u16
vic_read_isr(void)
262 isr
= inb(0xa0) << 8;
269 static __init
void qic_setup(void)
271 if (!is_cpu_quad()) {
272 /* not a quad, no setup */
275 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
276 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
278 if (is_cpu_extended()) {
279 /* the QIC duplicate of the VIC base register */
280 outb(VIC_DEFAULT_CPI_BASE
, QIC_VIC_CPI_BASE_REGISTER
);
281 outb(QIC_DEFAULT_CPI_BASE
, QIC_CPI_BASE_REGISTER
);
283 /* FIXME: should set up the QIC timer and memory parity
284 * error vectors here */
288 static __init
void vic_setup_pic(void)
290 outb(1, VIC_REDIRECT_REGISTER_1
);
291 /* clear the claim registers for dynamic routing */
292 outb(0, VIC_CLAIM_REGISTER_0
);
293 outb(0, VIC_CLAIM_REGISTER_1
);
295 outb(0, VIC_PRIORITY_REGISTER
);
296 /* Set the Primary and Secondary Microchannel vector
297 * bases to be the same as the ordinary interrupts
299 * FIXME: This would be more efficient using separate
301 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
302 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
303 /* Now initiallise the master PIC belonging to this CPU by
304 * sending the four ICWs */
306 /* ICW1: level triggered, ICW4 needed */
309 /* ICW2: vector base */
310 outb(FIRST_EXTERNAL_VECTOR
, 0x21);
312 /* ICW3: slave at line 2 */
315 /* ICW4: 8086 mode */
318 /* now the same for the slave PIC */
320 /* ICW1: level trigger, ICW4 needed */
323 /* ICW2: slave vector base */
324 outb(FIRST_EXTERNAL_VECTOR
+ 8, 0xA1);
329 /* ICW4: 8086 mode */
333 static void do_quad_bootstrap(void)
335 if (is_cpu_quad() && is_cpu_vic_boot()) {
338 __u8 cpuid
= hard_smp_processor_id();
340 local_irq_save(flags
);
342 for (i
= 0; i
< 4; i
++) {
343 /* FIXME: this would be >>3 &0x7 on the 32 way */
344 if (((cpuid
>> 2) & 0x03) == i
)
345 /* don't lower our own mask! */
348 /* masquerade as local Quad CPU */
349 outb(QIC_CPUID_ENABLE
| i
, QIC_PROCESSOR_ID
);
350 /* enable the startup CPI */
351 outb(QIC_BOOT_CPI_MASK
, QIC_MASK_REGISTER1
);
353 outb(0, QIC_PROCESSOR_ID
);
355 local_irq_restore(flags
);
359 /* Set up all the basic stuff: read the SMP config and make all the
360 * SMP information reflect only the boot cpu. All others will be
361 * brought on-line later. */
362 void __init
find_smp_config(void)
366 boot_cpu_id
= hard_smp_processor_id();
368 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id
);
370 /* initialize the CPU structures (moved from smp_boot_cpus) */
371 for (i
= 0; i
< NR_CPUS
; i
++) {
372 cpu_irq_affinity
[i
] = ~0;
374 cpu_online_map
= cpumask_of_cpu(boot_cpu_id
);
376 /* The boot CPU must be extended */
377 voyager_extended_vic_processors
= 1 << boot_cpu_id
;
378 /* initially, all of the first 8 CPUs can boot */
379 voyager_allowed_boot_processors
= 0xff;
380 /* set up everything for just this CPU, we can alter
381 * this as we start the other CPUs later */
382 /* now get the CPU disposition from the extended CMOS */
383 cpus_addr(phys_cpu_present_map
)[0] =
384 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
);
385 cpus_addr(phys_cpu_present_map
)[0] |=
386 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+ 1) << 8;
387 cpus_addr(phys_cpu_present_map
)[0] |=
388 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+
390 cpus_addr(phys_cpu_present_map
)[0] |=
391 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+
393 cpu_possible_map
= phys_cpu_present_map
;
394 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n",
395 cpus_addr(phys_cpu_present_map
)[0]);
396 /* Here we set up the VIC to enable SMP */
397 /* enable the CPIs by writing the base vector to their register */
398 outb(VIC_DEFAULT_CPI_BASE
, VIC_CPI_BASE_REGISTER
);
399 outb(1, VIC_REDIRECT_REGISTER_1
);
400 /* set the claim registers for static routing --- Boot CPU gets
401 * all interrupts untill all other CPUs started */
402 outb(0xff, VIC_CLAIM_REGISTER_0
);
403 outb(0xff, VIC_CLAIM_REGISTER_1
);
404 /* Set the Primary and Secondary Microchannel vector
405 * bases to be the same as the ordinary interrupts
407 * FIXME: This would be more efficient using separate
409 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
410 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
412 /* Finally tell the firmware that we're driving */
413 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT
) | VOYAGER_IN_CONTROL_FLAG
,
414 VOYAGER_SUS_IN_CONTROL_PORT
);
416 current_thread_info()->cpu
= boot_cpu_id
;
417 x86_write_percpu(cpu_number
, boot_cpu_id
);
421 * The bootstrap kernel entry code has set these up. Save them
422 * for a given CPU, id is physical */
423 void __init
smp_store_cpu_info(int id
)
425 struct cpuinfo_x86
*c
= &cpu_data(id
);
429 identify_secondary_cpu(c
);
432 /* set up the trampoline and return the physical address of the code */
433 unsigned long __init
setup_trampoline(void)
435 /* these two are global symbols in trampoline.S */
436 extern const __u8 trampoline_end
[];
437 extern const __u8 trampoline_data
[];
439 memcpy(trampoline_base
, trampoline_data
,
440 trampoline_end
- trampoline_data
);
441 return virt_to_phys(trampoline_base
);
444 /* Routine initially called when a non-boot CPU is brought online */
445 static void __init
start_secondary(void *unused
)
447 __u8 cpuid
= hard_smp_processor_id();
451 /* OK, we're in the routine */
452 ack_CPI(VIC_CPU_BOOT_CPI
);
454 /* setup the 8259 master slave pair belonging to this CPU ---
455 * we won't actually receive any until the boot CPU
456 * relinquishes it's static routing mask */
461 if (is_cpu_quad() && !is_cpu_vic_boot()) {
462 /* clear the boot CPI */
466 voyager_quad_cpi_addr
[cpuid
]->qic_cpi
[VIC_CPU_BOOT_CPI
].cpi
;
467 printk("read dummy %d\n", dummy
);
470 /* lower the mask to receive CPIs */
473 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid
, &cpuid
));
475 /* enable interrupts */
478 /* get our bogomips */
481 /* save our processor parameters */
482 smp_store_cpu_info(cpuid
);
484 /* if we're a quad, we may need to bootstrap other CPUs */
487 /* FIXME: this is rather a poor hack to prevent the CPU
488 * activating softirqs while it's supposed to be waiting for
489 * permission to proceed. Without this, the new per CPU stuff
490 * in the softirqs will fail */
492 cpu_set(cpuid
, cpu_callin_map
);
494 /* signal that we're done */
497 while (!cpu_isset(cpuid
, smp_commenced_mask
))
503 cpu_set(cpuid
, cpu_online_map
);
508 /* Routine to kick start the given CPU and wait for it to report ready
509 * (or timeout in startup). When this routine returns, the requested
510 * CPU is either fully running and configured or known to be dead.
512 * We call this routine sequentially 1 CPU at a time, so no need for
515 static void __init
do_boot_cpu(__u8 cpu
)
517 struct task_struct
*idle
;
520 int quad_boot
= (1 << cpu
) & voyager_quad_processors
521 & ~(voyager_extended_vic_processors
522 & voyager_allowed_boot_processors
);
524 /* This is the format of the CPI IDT gate (in real mode) which
525 * we're hijacking to boot the CPU */
534 __u32
*hijack_vector
;
535 __u32 start_phys_address
= setup_trampoline();
537 /* There's a clever trick to this: The linux trampoline is
538 * compiled to begin at absolute location zero, so make the
539 * address zero but have the data segment selector compensate
540 * for the actual address */
541 hijack_source
.idt
.Offset
= start_phys_address
& 0x000F;
542 hijack_source
.idt
.Segment
= (start_phys_address
>> 4) & 0xFFFF;
545 alternatives_smp_switch(1);
547 idle
= fork_idle(cpu
);
549 panic("failed fork for CPU%d", cpu
);
550 idle
->thread
.ip
= (unsigned long)start_secondary
;
551 /* init_tasks (in sched.c) is indexed logically */
552 stack_start
.sp
= (void *)idle
->thread
.sp
;
555 per_cpu(current_task
, cpu
) = idle
;
556 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
559 /* Note: Don't modify initial ss override */
560 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu
,
561 (unsigned long)hijack_source
.val
, hijack_source
.idt
.Segment
,
562 hijack_source
.idt
.Offset
, stack_start
.sp
));
564 /* init lowmem identity mapping */
565 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ USER_PGD_PTRS
,
566 min_t(unsigned long, KERNEL_PGD_PTRS
, USER_PGD_PTRS
));
570 printk("CPU %d: non extended Quad boot\n", cpu
);
573 phys_to_virt((VIC_CPU_BOOT_CPI
+ QIC_DEFAULT_CPI_BASE
) * 4);
574 *hijack_vector
= hijack_source
.val
;
576 printk("CPU%d: extended VIC boot\n", cpu
);
579 phys_to_virt((VIC_CPU_BOOT_CPI
+ VIC_DEFAULT_CPI_BASE
) * 4);
580 *hijack_vector
= hijack_source
.val
;
581 /* VIC errata, may also receive interrupt at this address */
584 phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI
+
585 VIC_DEFAULT_CPI_BASE
) * 4);
586 *hijack_vector
= hijack_source
.val
;
588 /* All non-boot CPUs start with interrupts fully masked. Need
589 * to lower the mask of the CPI we're about to send. We do
590 * this in the VIC by masquerading as the processor we're
591 * about to boot and lowering its interrupt mask */
592 local_irq_save(flags
);
594 send_one_QIC_CPI(cpu
, VIC_CPU_BOOT_CPI
);
596 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
597 /* here we're altering registers belonging to `cpu' */
599 outb(VIC_BOOT_INTERRUPT_MASK
, 0x21);
600 /* now go back to our original identity */
601 outb(boot_cpu_id
, VIC_PROCESSOR_ID
);
603 /* and boot the CPU */
605 send_CPI((1 << cpu
), VIC_CPU_BOOT_CPI
);
608 local_irq_restore(flags
);
610 /* now wait for it to become ready (or timeout) */
611 for (timeout
= 0; timeout
< 50000; timeout
++) {
616 /* reset the page table */
619 if (cpu_booted_map
) {
620 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
621 cpu
, smp_processor_id()));
623 printk("CPU%d: ", cpu
);
624 print_cpu_info(&cpu_data(cpu
));
626 cpu_set(cpu
, cpu_callout_map
);
627 cpu_set(cpu
, cpu_present_map
);
629 printk("CPU%d FAILED TO BOOT: ", cpu
);
631 ((volatile unsigned char *)phys_to_virt(start_phys_address
))
635 printk("Not responding.\n");
641 void __init
smp_boot_cpus(void)
645 /* CAT BUS initialisation must be done after the memory */
646 /* FIXME: The L4 has a catbus too, it just needs to be
647 * accessed in a totally different way */
648 if (voyager_level
== 5) {
651 /* now that the cat has probed the Voyager System Bus, sanity
652 * check the cpu map */
653 if (((voyager_quad_processors
| voyager_extended_vic_processors
)
654 & cpus_addr(phys_cpu_present_map
)[0]) !=
655 cpus_addr(phys_cpu_present_map
)[0]) {
657 printk("\n\n***WARNING*** "
658 "Sanity check of CPU present map FAILED\n");
660 } else if (voyager_level
== 4)
661 voyager_extended_vic_processors
=
662 cpus_addr(phys_cpu_present_map
)[0];
664 /* this sets up the idle task to run on the current cpu */
665 voyager_extended_cpus
= 1;
666 /* Remove the global_irq_holder setting, it triggers a BUG() on
667 * schedule at the moment */
668 //global_irq_holder = boot_cpu_id;
670 /* FIXME: Need to do something about this but currently only works
671 * on CPUs with a tsc which none of mine have.
672 smp_tune_scheduling();
674 smp_store_cpu_info(boot_cpu_id
);
675 printk("CPU%d: ", boot_cpu_id
);
676 print_cpu_info(&cpu_data(boot_cpu_id
));
679 /* booting on a Quad CPU */
680 printk("VOYAGER SMP: Boot CPU is Quad\n");
685 /* enable our own CPIs */
688 cpu_set(boot_cpu_id
, cpu_online_map
);
689 cpu_set(boot_cpu_id
, cpu_callout_map
);
691 /* loop over all the extended VIC CPUs and boot them. The
692 * Quad CPUs must be bootstrapped by their extended VIC cpu */
693 for (i
= 0; i
< NR_CPUS
; i
++) {
694 if (i
== boot_cpu_id
|| !cpu_isset(i
, phys_cpu_present_map
))
697 /* This udelay seems to be needed for the Quad boots
698 * don't remove unless you know what you're doing */
701 /* we could compute the total bogomips here, but why bother?,
702 * Code added from smpboot.c */
704 unsigned long bogosum
= 0;
705 for (i
= 0; i
< NR_CPUS
; i
++)
706 if (cpu_isset(i
, cpu_online_map
))
707 bogosum
+= cpu_data(i
).loops_per_jiffy
;
708 printk(KERN_INFO
"Total of %d processors activated "
709 "(%lu.%02lu BogoMIPS).\n",
710 cpucount
+ 1, bogosum
/ (500000 / HZ
),
711 (bogosum
/ (5000 / HZ
)) % 100);
713 voyager_extended_cpus
= hweight32(voyager_extended_vic_processors
);
714 printk("VOYAGER: Extended (interrupt handling CPUs): "
715 "%d, non-extended: %d\n", voyager_extended_cpus
,
716 num_booting_cpus() - voyager_extended_cpus
);
717 /* that's it, switch to symmetric mode */
718 outb(0, VIC_PRIORITY_REGISTER
);
719 outb(0, VIC_CLAIM_REGISTER_0
);
720 outb(0, VIC_CLAIM_REGISTER_1
);
722 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
725 /* Reload the secondary CPUs task structure (this function does not
727 void __init
initialize_secondary(void)
731 set_current(hard_get_current());
735 * We don't actually need to load the full TSS,
736 * basically just the stack pointer and the eip.
739 asm volatile ("movl %0,%%esp\n\t"
740 "jmp *%1"::"r" (current
->thread
.sp
),
741 "r"(current
->thread
.ip
));
744 /* handle a Voyager SYS_INT -- If we don't, the base board will
747 * System interrupts occur because some problem was detected on the
748 * various busses. To find out what you have to probe all the
749 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
750 void smp_vic_sys_interrupt(struct pt_regs
*regs
)
752 ack_CPI(VIC_SYS_INT
);
753 printk("Voyager SYSTEM INTERRUPT\n");
756 /* Handle a voyager CMN_INT; These interrupts occur either because of
757 * a system status change or because a single bit memory error
758 * occurred. FIXME: At the moment, ignore all this. */
759 void smp_vic_cmn_interrupt(struct pt_regs
*regs
)
761 static __u8 in_cmn_int
= 0;
762 static DEFINE_SPINLOCK(cmn_int_lock
);
764 /* common ints are broadcast, so make sure we only do this once */
765 _raw_spin_lock(&cmn_int_lock
);
770 _raw_spin_unlock(&cmn_int_lock
);
772 VDEBUG(("Voyager COMMON INTERRUPT\n"));
774 if (voyager_level
== 5)
775 voyager_cat_do_common_interrupt();
777 _raw_spin_lock(&cmn_int_lock
);
780 _raw_spin_unlock(&cmn_int_lock
);
781 ack_CPI(VIC_CMN_INT
);
785 * Reschedule call back. Nothing to do, all the work is done
786 * automatically when we return from the interrupt. */
787 static void smp_reschedule_interrupt(void)
792 static struct mm_struct
*flush_mm
;
793 static unsigned long flush_va
;
794 static DEFINE_SPINLOCK(tlbstate_lock
);
797 * We cannot call mmdrop() because we are in interrupt context,
798 * instead update mm->cpu_vm_mask.
800 * We need to reload %cr3 since the page tables may be going
801 * away from under us..
803 static inline void voyager_leave_mm(unsigned long cpu
)
805 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
)
807 cpu_clear(cpu
, per_cpu(cpu_tlbstate
, cpu
).active_mm
->cpu_vm_mask
);
808 load_cr3(swapper_pg_dir
);
812 * Invalidate call-back
814 static void smp_invalidate_interrupt(void)
816 __u8 cpu
= smp_processor_id();
818 if (!test_bit(cpu
, &smp_invalidate_needed
))
820 /* This will flood messages. Don't uncomment unless you see
821 * Problems with cross cpu invalidation
822 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
823 smp_processor_id()));
826 if (flush_mm
== per_cpu(cpu_tlbstate
, cpu
).active_mm
) {
827 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
) {
828 if (flush_va
== TLB_FLUSH_ALL
)
831 __flush_tlb_one(flush_va
);
833 voyager_leave_mm(cpu
);
835 smp_mb__before_clear_bit();
836 clear_bit(cpu
, &smp_invalidate_needed
);
837 smp_mb__after_clear_bit();
840 /* All the new flush operations for 2.4 */
842 /* This routine is called with a physical cpu mask */
844 voyager_flush_tlb_others(unsigned long cpumask
, struct mm_struct
*mm
,
851 if ((cpumask
& cpus_addr(cpu_online_map
)[0]) != cpumask
)
853 if (cpumask
& (1 << smp_processor_id()))
858 spin_lock(&tlbstate_lock
);
862 atomic_set_mask(cpumask
, &smp_invalidate_needed
);
864 * We have to send the CPI only to
867 send_CPI(cpumask
, VIC_INVALIDATE_CPI
);
869 while (smp_invalidate_needed
) {
872 printk("***WARNING*** Stuck doing invalidate CPI "
873 "(CPU%d)\n", smp_processor_id());
878 /* Uncomment only to debug invalidation problems
879 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
884 spin_unlock(&tlbstate_lock
);
887 void flush_tlb_current_task(void)
889 struct mm_struct
*mm
= current
->mm
;
890 unsigned long cpu_mask
;
894 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
897 voyager_flush_tlb_others(cpu_mask
, mm
, TLB_FLUSH_ALL
);
902 void flush_tlb_mm(struct mm_struct
*mm
)
904 unsigned long cpu_mask
;
908 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
910 if (current
->active_mm
== mm
) {
914 voyager_leave_mm(smp_processor_id());
917 voyager_flush_tlb_others(cpu_mask
, mm
, TLB_FLUSH_ALL
);
922 void flush_tlb_page(struct vm_area_struct
*vma
, unsigned long va
)
924 struct mm_struct
*mm
= vma
->vm_mm
;
925 unsigned long cpu_mask
;
929 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
930 if (current
->active_mm
== mm
) {
934 voyager_leave_mm(smp_processor_id());
938 voyager_flush_tlb_others(cpu_mask
, mm
, va
);
943 EXPORT_SYMBOL(flush_tlb_page
);
945 /* enable the requested IRQs */
946 static void smp_enable_irq_interrupt(void)
949 __u8 cpu
= get_cpu();
951 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu
,
952 vic_irq_enable_mask
[cpu
]));
954 spin_lock(&vic_irq_lock
);
955 for (irq
= 0; irq
< 16; irq
++) {
956 if (vic_irq_enable_mask
[cpu
] & (1 << irq
))
957 enable_local_vic_irq(irq
);
959 vic_irq_enable_mask
[cpu
] = 0;
960 spin_unlock(&vic_irq_lock
);
962 put_cpu_no_resched();
968 static void smp_stop_cpu_function(void *dummy
)
970 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
971 cpu_clear(smp_processor_id(), cpu_online_map
);
977 static DEFINE_SPINLOCK(call_lock
);
979 struct call_data_struct
{
980 void (*func
) (void *info
);
982 volatile unsigned long started
;
983 volatile unsigned long finished
;
987 static struct call_data_struct
*call_data
;
989 /* execute a thread on a new CPU. The function to be called must be
990 * previously set up. This is used to schedule a function for
991 * execution on all CPUs - set up the function then broadcast a
992 * function_interrupt CPI to come here on each CPU */
993 static void smp_call_function_interrupt(void)
995 void (*func
) (void *info
) = call_data
->func
;
996 void *info
= call_data
->info
;
997 /* must take copy of wait because call_data may be replaced
998 * unless the function is waiting for us to finish */
999 int wait
= call_data
->wait
;
1000 __u8 cpu
= smp_processor_id();
1003 * Notify initiating CPU that I've grabbed the data and am
1004 * about to execute the function
1007 if (!test_and_clear_bit(cpu
, &call_data
->started
)) {
1008 /* If the bit wasn't set, this could be a replay */
1009 printk(KERN_WARNING
"VOYAGER SMP: CPU %d received call funtion"
1010 " with no call pending\n", cpu
);
1014 * At this point the info structure may be out of scope unless wait==1
1018 __get_cpu_var(irq_stat
).irq_call_count
++;
1022 clear_bit(cpu
, &call_data
->finished
);
1027 voyager_smp_call_function_mask(cpumask_t cpumask
,
1028 void (*func
) (void *info
), void *info
, int wait
)
1030 struct call_data_struct data
;
1031 u32 mask
= cpus_addr(cpumask
)[0];
1033 mask
&= ~(1 << smp_processor_id());
1038 /* Can deadlock when called with interrupts disabled */
1039 WARN_ON(irqs_disabled());
1043 data
.started
= mask
;
1046 data
.finished
= mask
;
1048 spin_lock(&call_lock
);
1051 /* Send a message to all other CPUs and wait for them to respond */
1052 send_CPI(mask
, VIC_CALL_FUNCTION_CPI
);
1054 /* Wait for response */
1055 while (data
.started
)
1059 while (data
.finished
)
1062 spin_unlock(&call_lock
);
1067 /* Sorry about the name. In an APIC based system, the APICs
1068 * themselves are programmed to send a timer interrupt. This is used
1069 * by linux to reschedule the processor. Voyager doesn't have this,
1070 * so we use the system clock to interrupt one processor, which in
1071 * turn, broadcasts a timer CPI to all the others --- we receive that
1072 * CPI here. We don't use this actually for counting so losing
1073 * ticks doesn't matter
1075 * FIXME: For those CPUs which actually have a local APIC, we could
1076 * try to use it to trigger this interrupt instead of having to
1077 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1078 * no local APIC, so I can't do this
1080 * This function is currently a placeholder and is unused in the code */
1081 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1083 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1084 wrapper_smp_local_timer_interrupt();
1085 set_irq_regs(old_regs
);
1088 /* All of the QUAD interrupt GATES */
1089 void smp_qic_timer_interrupt(struct pt_regs
*regs
)
1091 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1092 ack_QIC_CPI(QIC_TIMER_CPI
);
1093 wrapper_smp_local_timer_interrupt();
1094 set_irq_regs(old_regs
);
1097 void smp_qic_invalidate_interrupt(struct pt_regs
*regs
)
1099 ack_QIC_CPI(QIC_INVALIDATE_CPI
);
1100 smp_invalidate_interrupt();
1103 void smp_qic_reschedule_interrupt(struct pt_regs
*regs
)
1105 ack_QIC_CPI(QIC_RESCHEDULE_CPI
);
1106 smp_reschedule_interrupt();
1109 void smp_qic_enable_irq_interrupt(struct pt_regs
*regs
)
1111 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI
);
1112 smp_enable_irq_interrupt();
1115 void smp_qic_call_function_interrupt(struct pt_regs
*regs
)
1117 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI
);
1118 smp_call_function_interrupt();
1121 void smp_vic_cpi_interrupt(struct pt_regs
*regs
)
1123 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1124 __u8 cpu
= smp_processor_id();
1127 ack_QIC_CPI(VIC_CPI_LEVEL0
);
1129 ack_VIC_CPI(VIC_CPI_LEVEL0
);
1131 if (test_and_clear_bit(VIC_TIMER_CPI
, &vic_cpi_mailbox
[cpu
]))
1132 wrapper_smp_local_timer_interrupt();
1133 if (test_and_clear_bit(VIC_INVALIDATE_CPI
, &vic_cpi_mailbox
[cpu
]))
1134 smp_invalidate_interrupt();
1135 if (test_and_clear_bit(VIC_RESCHEDULE_CPI
, &vic_cpi_mailbox
[cpu
]))
1136 smp_reschedule_interrupt();
1137 if (test_and_clear_bit(VIC_ENABLE_IRQ_CPI
, &vic_cpi_mailbox
[cpu
]))
1138 smp_enable_irq_interrupt();
1139 if (test_and_clear_bit(VIC_CALL_FUNCTION_CPI
, &vic_cpi_mailbox
[cpu
]))
1140 smp_call_function_interrupt();
1141 set_irq_regs(old_regs
);
1144 static void do_flush_tlb_all(void *info
)
1146 unsigned long cpu
= smp_processor_id();
1149 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_LAZY
)
1150 voyager_leave_mm(cpu
);
1153 /* flush the TLB of every active CPU in the system */
1154 void flush_tlb_all(void)
1156 on_each_cpu(do_flush_tlb_all
, 0, 1, 1);
1159 /* used to set up the trampoline for other CPUs when the memory manager
1161 void __init
smp_alloc_memory(void)
1163 trampoline_base
= alloc_bootmem_low_pages(PAGE_SIZE
);
1164 if (__pa(trampoline_base
) >= 0x93000)
1168 /* send a reschedule CPI to one CPU by physical CPU number*/
1169 static void voyager_smp_send_reschedule(int cpu
)
1171 send_one_CPI(cpu
, VIC_RESCHEDULE_CPI
);
1174 int hard_smp_processor_id(void)
1177 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
1178 if ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
)
1179 return cpumask
& 0x1F;
1181 for (i
= 0; i
< 8; i
++) {
1182 if (cpumask
& (1 << i
))
1185 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask
);
1189 int safe_smp_processor_id(void)
1191 return hard_smp_processor_id();
1194 /* broadcast a halt to all other CPUs */
1195 static void voyager_smp_send_stop(void)
1197 smp_call_function(smp_stop_cpu_function
, NULL
, 1, 1);
1200 /* this function is triggered in time.c when a clock tick fires
1201 * we need to re-broadcast the tick to all CPUs */
1202 void smp_vic_timer_interrupt(void)
1204 send_CPI_allbutself(VIC_TIMER_CPI
);
1205 smp_local_timer_interrupt();
1208 /* local (per CPU) timer interrupt. It does both profiling and
1209 * process statistics/rescheduling.
1211 * We do profiling in every local tick, statistics/rescheduling
1212 * happen only every 'profiling multiplier' ticks. The default
1213 * multiplier is 1 and it can be changed by writing the new multiplier
1214 * value into /proc/profile.
1216 void smp_local_timer_interrupt(void)
1218 int cpu
= smp_processor_id();
1221 profile_tick(CPU_PROFILING
);
1222 if (--per_cpu(prof_counter
, cpu
) <= 0) {
1224 * The multiplier may have changed since the last time we got
1225 * to this point as a result of the user writing to
1226 * /proc/profile. In this case we need to adjust the APIC
1227 * timer accordingly.
1229 * Interrupts are already masked off at this point.
1231 per_cpu(prof_counter
, cpu
) = per_cpu(prof_multiplier
, cpu
);
1232 if (per_cpu(prof_counter
, cpu
) !=
1233 per_cpu(prof_old_multiplier
, cpu
)) {
1234 /* FIXME: need to update the vic timer tick here */
1235 per_cpu(prof_old_multiplier
, cpu
) =
1236 per_cpu(prof_counter
, cpu
);
1239 update_process_times(user_mode_vm(get_irq_regs()));
1242 if (((1 << cpu
) & voyager_extended_vic_processors
) == 0)
1243 /* only extended VIC processors participate in
1244 * interrupt distribution */
1248 * We take the 'long' return path, and there every subsystem
1249 * grabs the appropriate locks (kernel lock/ irq lock).
1251 * we might want to decouple profiling from the 'long path',
1252 * and do the profiling totally in assembly.
1254 * Currently this isn't too much of an issue (performance wise),
1255 * we can take more than 100K local irqs per second on a 100 MHz P5.
1258 if ((++vic_tick
[cpu
] & 0x7) != 0)
1260 /* get here every 16 ticks (about every 1/6 of a second) */
1262 /* Change our priority to give someone else a chance at getting
1263 * the IRQ. The algorithm goes like this:
1265 * In the VIC, the dynamically routed interrupt is always
1266 * handled by the lowest priority eligible (i.e. receiving
1267 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1268 * lowest processor number gets it.
1270 * The priority of a CPU is controlled by a special per-CPU
1271 * VIC priority register which is 3 bits wide 0 being lowest
1272 * and 7 highest priority..
1274 * Therefore we subtract the average number of interrupts from
1275 * the number we've fielded. If this number is negative, we
1276 * lower the activity count and if it is positive, we raise
1279 * I'm afraid this still leads to odd looking interrupt counts:
1280 * the totals are all roughly equal, but the individual ones
1281 * look rather skewed.
1283 * FIXME: This algorithm is total crap when mixed with SMP
1284 * affinity code since we now try to even up the interrupt
1285 * counts when an affinity binding is keeping them on a
1287 weight
= (vic_intr_count
[cpu
] * voyager_extended_cpus
1288 - vic_intr_total
) >> 4;
1295 outb((__u8
) weight
, VIC_PRIORITY_REGISTER
);
1297 #ifdef VOYAGER_DEBUG
1298 if ((vic_tick
[cpu
] & 0xFFF) == 0) {
1299 /* print this message roughly every 25 secs */
1300 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1301 cpu
, vic_tick
[cpu
], weight
);
1306 /* setup the profiling timer */
1307 int setup_profiling_timer(unsigned int multiplier
)
1315 * Set the new multiplier for each CPU. CPUs don't start using the
1316 * new values until the next timer interrupt in which they do process
1319 for (i
= 0; i
< NR_CPUS
; ++i
)
1320 per_cpu(prof_multiplier
, i
) = multiplier
;
1325 /* This is a bit of a mess, but forced on us by the genirq changes
1326 * there's no genirq handler that really does what voyager wants
1327 * so hack it up with the simple IRQ handler */
1328 static void handle_vic_irq(unsigned int irq
, struct irq_desc
*desc
)
1330 before_handle_vic_irq(irq
);
1331 handle_simple_irq(irq
, desc
);
1332 after_handle_vic_irq(irq
);
1335 /* The CPIs are handled in the per cpu 8259s, so they must be
1336 * enabled to be received: FIX: enabling the CPIs in the early
1337 * boot sequence interferes with bug checking; enable them later
1339 #define VIC_SET_GATE(cpi, vector) \
1340 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1341 #define QIC_SET_GATE(cpi, vector) \
1342 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1344 void __init
smp_intr_init(void)
1348 /* initialize the per cpu irq mask to all disabled */
1349 for (i
= 0; i
< NR_CPUS
; i
++)
1350 vic_irq_mask
[i
] = 0xFFFF;
1352 VIC_SET_GATE(VIC_CPI_LEVEL0
, vic_cpi_interrupt
);
1354 VIC_SET_GATE(VIC_SYS_INT
, vic_sys_interrupt
);
1355 VIC_SET_GATE(VIC_CMN_INT
, vic_cmn_interrupt
);
1357 QIC_SET_GATE(QIC_TIMER_CPI
, qic_timer_interrupt
);
1358 QIC_SET_GATE(QIC_INVALIDATE_CPI
, qic_invalidate_interrupt
);
1359 QIC_SET_GATE(QIC_RESCHEDULE_CPI
, qic_reschedule_interrupt
);
1360 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI
, qic_enable_irq_interrupt
);
1361 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI
, qic_call_function_interrupt
);
1363 /* now put the VIC descriptor into the first 48 IRQs
1365 * This is for later: first 16 correspond to PC IRQs; next 16
1366 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1367 for (i
= 0; i
< 48; i
++)
1368 set_irq_chip_and_handler(i
, &vic_chip
, handle_vic_irq
);
1371 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1372 * processor to receive CPI */
1373 static void send_CPI(__u32 cpuset
, __u8 cpi
)
1376 __u32 quad_cpuset
= (cpuset
& voyager_quad_processors
);
1378 if (cpi
< VIC_START_FAKE_CPI
) {
1379 /* fake CPI are only used for booting, so send to the
1380 * extended quads as well---Quads must be VIC booted */
1381 outb((__u8
) (cpuset
), VIC_CPI_Registers
[cpi
]);
1385 send_QIC_CPI(quad_cpuset
, cpi
);
1386 cpuset
&= ~quad_cpuset
;
1387 cpuset
&= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1390 for_each_online_cpu(cpu
) {
1391 if (cpuset
& (1 << cpu
))
1392 set_bit(cpi
, &vic_cpi_mailbox
[cpu
]);
1395 outb((__u8
) cpuset
, VIC_CPI_Registers
[VIC_CPI_LEVEL0
]);
1398 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1399 * set the cache line to shared by reading it.
1401 * DON'T make this inline otherwise the cache line read will be
1404 static int ack_QIC_CPI(__u8 cpi
)
1406 __u8 cpu
= hard_smp_processor_id();
1410 outb(1 << cpi
, QIC_INTERRUPT_CLEAR1
);
1411 return voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
;
1414 static void ack_special_QIC_CPI(__u8 cpi
)
1418 outb(QIC_CMN_INT
, QIC_INTERRUPT_CLEAR0
);
1421 outb(QIC_SYS_INT
, QIC_INTERRUPT_CLEAR0
);
1424 /* also clear at the VIC, just in case (nop for non-extended proc) */
1428 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1429 static void ack_VIC_CPI(__u8 cpi
)
1431 #ifdef VOYAGER_DEBUG
1432 unsigned long flags
;
1434 __u8 cpu
= smp_processor_id();
1436 local_irq_save(flags
);
1437 isr
= vic_read_isr();
1438 if ((isr
& (1 << (cpi
& 7))) == 0) {
1439 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu
, cpi
);
1442 /* send specific EOI; the two system interrupts have
1443 * bit 4 set for a separate vector but behave as the
1444 * corresponding 3 bit intr */
1445 outb_p(0x60 | (cpi
& 7), 0x20);
1447 #ifdef VOYAGER_DEBUG
1448 if ((vic_read_isr() & (1 << (cpi
& 7))) != 0) {
1449 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu
, cpi
);
1451 local_irq_restore(flags
);
1455 /* cribbed with thanks from irq.c */
1456 #define __byte(x,y) (((unsigned char *)&(y))[x])
1457 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1458 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1460 static unsigned int startup_vic_irq(unsigned int irq
)
1462 unmask_vic_irq(irq
);
1467 /* The enable and disable routines. This is where we run into
1468 * conflicting architectural philosophy. Fundamentally, the voyager
1469 * architecture does not expect to have to disable interrupts globally
1470 * (the IRQ controllers belong to each CPU). The processor masquerade
1471 * which is used to start the system shouldn't be used in a running OS
1472 * since it will cause great confusion if two separate CPUs drive to
1473 * the same IRQ controller (I know, I've tried it).
1475 * The solution is a variant on the NCR lazy SPL design:
1477 * 1) To disable an interrupt, do nothing (other than set the
1478 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1480 * 2) If the interrupt dares to come in, raise the local mask against
1481 * it (this will result in all the CPU masks being raised
1484 * 3) To enable the interrupt, lower the mask on the local CPU and
1485 * broadcast an Interrupt enable CPI which causes all other CPUs to
1486 * adjust their masks accordingly. */
1488 static void unmask_vic_irq(unsigned int irq
)
1490 /* linux doesn't to processor-irq affinity, so enable on
1491 * all CPUs we know about */
1492 int cpu
= smp_processor_id(), real_cpu
;
1493 __u16 mask
= (1 << irq
);
1494 __u32 processorList
= 0;
1495 unsigned long flags
;
1497 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
1498 irq
, cpu
, cpu_irq_affinity
[cpu
]));
1499 spin_lock_irqsave(&vic_irq_lock
, flags
);
1500 for_each_online_cpu(real_cpu
) {
1501 if (!(voyager_extended_vic_processors
& (1 << real_cpu
)))
1503 if (!(cpu_irq_affinity
[real_cpu
] & mask
)) {
1504 /* irq has no affinity for this CPU, ignore */
1507 if (real_cpu
== cpu
) {
1508 enable_local_vic_irq(irq
);
1509 } else if (vic_irq_mask
[real_cpu
] & mask
) {
1510 vic_irq_enable_mask
[real_cpu
] |= mask
;
1511 processorList
|= (1 << real_cpu
);
1514 spin_unlock_irqrestore(&vic_irq_lock
, flags
);
1516 send_CPI(processorList
, VIC_ENABLE_IRQ_CPI
);
1519 static void mask_vic_irq(unsigned int irq
)
1521 /* lazy disable, do nothing */
1524 static void enable_local_vic_irq(unsigned int irq
)
1526 __u8 cpu
= smp_processor_id();
1527 __u16 mask
= ~(1 << irq
);
1528 __u16 old_mask
= vic_irq_mask
[cpu
];
1530 vic_irq_mask
[cpu
] &= mask
;
1531 if (vic_irq_mask
[cpu
] == old_mask
)
1534 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1538 outb_p(cached_A1(cpu
), 0xA1);
1541 outb_p(cached_21(cpu
), 0x21);
1546 static void disable_local_vic_irq(unsigned int irq
)
1548 __u8 cpu
= smp_processor_id();
1549 __u16 mask
= (1 << irq
);
1550 __u16 old_mask
= vic_irq_mask
[cpu
];
1555 vic_irq_mask
[cpu
] |= mask
;
1556 if (old_mask
== vic_irq_mask
[cpu
])
1559 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1563 outb_p(cached_A1(cpu
), 0xA1);
1566 outb_p(cached_21(cpu
), 0x21);
1571 /* The VIC is level triggered, so the ack can only be issued after the
1572 * interrupt completes. However, we do Voyager lazy interrupt
1573 * handling here: It is an extremely expensive operation to mask an
1574 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1575 * this interrupt actually comes in, then we mask and ack here to push
1576 * the interrupt off to another CPU */
1577 static void before_handle_vic_irq(unsigned int irq
)
1579 irq_desc_t
*desc
= irq_desc
+ irq
;
1580 __u8 cpu
= smp_processor_id();
1582 _raw_spin_lock(&vic_irq_lock
);
1584 vic_intr_count
[cpu
]++;
1586 if (!(cpu_irq_affinity
[cpu
] & (1 << irq
))) {
1587 /* The irq is not in our affinity mask, push it off
1588 * onto another CPU */
1589 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d "
1590 "on cpu %d\n", irq
, cpu
));
1591 disable_local_vic_irq(irq
);
1592 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1593 * actually calling the interrupt routine */
1594 desc
->status
|= IRQ_REPLAY
| IRQ_INPROGRESS
;
1595 } else if (desc
->status
& IRQ_DISABLED
) {
1596 /* Damn, the interrupt actually arrived, do the lazy
1597 * disable thing. The interrupt routine in irq.c will
1598 * not handle a IRQ_DISABLED interrupt, so nothing more
1599 * need be done here */
1600 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1602 disable_local_vic_irq(irq
);
1603 desc
->status
|= IRQ_REPLAY
;
1605 desc
->status
&= ~IRQ_REPLAY
;
1608 _raw_spin_unlock(&vic_irq_lock
);
1611 /* Finish the VIC interrupt: basically mask */
1612 static void after_handle_vic_irq(unsigned int irq
)
1614 irq_desc_t
*desc
= irq_desc
+ irq
;
1616 _raw_spin_lock(&vic_irq_lock
);
1618 unsigned int status
= desc
->status
& ~IRQ_INPROGRESS
;
1619 #ifdef VOYAGER_DEBUG
1623 desc
->status
= status
;
1624 if ((status
& IRQ_DISABLED
))
1625 disable_local_vic_irq(irq
);
1626 #ifdef VOYAGER_DEBUG
1627 /* DEBUG: before we ack, check what's in progress */
1628 isr
= vic_read_isr();
1629 if ((isr
& (1 << irq
) && !(status
& IRQ_REPLAY
)) == 0) {
1631 __u8 cpu
= smp_processor_id();
1633 int mask
; /* Um... initialize me??? --RR */
1635 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1637 for_each_possible_cpu(real_cpu
, mask
) {
1639 outb(VIC_CPU_MASQUERADE_ENABLE
| real_cpu
,
1641 isr
= vic_read_isr();
1642 if (isr
& (1 << irq
)) {
1644 ("VOYAGER SMP: CPU%d ack irq %d\n",
1648 outb(cpu
, VIC_PROCESSOR_ID
);
1651 #endif /* VOYAGER_DEBUG */
1652 /* as soon as we ack, the interrupt is eligible for
1653 * receipt by another CPU so everything must be in
1656 if (status
& IRQ_REPLAY
) {
1657 /* replay is set if we disable the interrupt
1658 * in the before_handle_vic_irq() routine, so
1659 * clear the in progress bit here to allow the
1660 * next CPU to handle this correctly */
1661 desc
->status
&= ~(IRQ_REPLAY
| IRQ_INPROGRESS
);
1663 #ifdef VOYAGER_DEBUG
1664 isr
= vic_read_isr();
1665 if ((isr
& (1 << irq
)) != 0)
1666 printk("VOYAGER SMP: after_handle_vic_irq() after "
1667 "ack irq=%d, isr=0x%x\n", irq
, isr
);
1668 #endif /* VOYAGER_DEBUG */
1670 _raw_spin_unlock(&vic_irq_lock
);
1672 /* All code after this point is out of the main path - the IRQ
1673 * may be intercepted by another CPU if reasserted */
1676 /* Linux processor - interrupt affinity manipulations.
1678 * For each processor, we maintain a 32 bit irq affinity mask.
1679 * Initially it is set to all 1's so every processor accepts every
1680 * interrupt. In this call, we change the processor's affinity mask:
1682 * Change from enable to disable:
1684 * If the interrupt ever comes in to the processor, we will disable it
1685 * and ack it to push it off to another CPU, so just accept the mask here.
1687 * Change from disable to enable:
1689 * change the mask and then do an interrupt enable CPI to re-enable on
1690 * the selected processors */
1692 void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
)
1694 /* Only extended processors handle interrupts */
1695 unsigned long real_mask
;
1696 unsigned long irq_mask
= 1 << irq
;
1699 real_mask
= cpus_addr(mask
)[0] & voyager_extended_vic_processors
;
1701 if (cpus_addr(mask
)[0] == 0)
1702 /* can't have no CPUs to accept the interrupt -- extremely
1703 * bad things will happen */
1707 /* can't change the affinity of the timer IRQ. This
1708 * is due to the constraint in the voyager
1709 * architecture that the CPI also comes in on and IRQ
1710 * line and we have chosen IRQ0 for this. If you
1711 * raise the mask on this interrupt, the processor
1712 * will no-longer be able to accept VIC CPIs */
1716 /* You can only have 32 interrupts in a voyager system
1717 * (and 32 only if you have a secondary microchannel
1721 for_each_online_cpu(cpu
) {
1722 unsigned long cpu_mask
= 1 << cpu
;
1724 if (cpu_mask
& real_mask
) {
1725 /* enable the interrupt for this cpu */
1726 cpu_irq_affinity
[cpu
] |= irq_mask
;
1728 /* disable the interrupt for this cpu */
1729 cpu_irq_affinity
[cpu
] &= ~irq_mask
;
1732 /* this is magic, we now have the correct affinity maps, so
1733 * enable the interrupt. This will send an enable CPI to
1734 * those CPUs who need to enable it in their local masks,
1735 * causing them to correct for the new affinity . If the
1736 * interrupt is currently globally disabled, it will simply be
1737 * disabled again as it comes in (voyager lazy disable). If
1738 * the affinity map is tightened to disable the interrupt on a
1739 * cpu, it will be pushed off when it comes in */
1740 unmask_vic_irq(irq
);
1743 static void ack_vic_irq(unsigned int irq
)
1746 outb(0x62, 0x20); /* Specific EOI to cascade */
1747 outb(0x60 | (irq
& 7), 0xA0);
1749 outb(0x60 | (irq
& 7), 0x20);
1753 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1754 * but are not vectored by it. This means that the 8259 mask must be
1755 * lowered to receive them */
1756 static __init
void vic_enable_cpi(void)
1758 __u8 cpu
= smp_processor_id();
1760 /* just take a copy of the current mask (nop for boot cpu) */
1761 vic_irq_mask
[cpu
] = vic_irq_mask
[boot_cpu_id
];
1763 enable_local_vic_irq(VIC_CPI_LEVEL0
);
1764 enable_local_vic_irq(VIC_CPI_LEVEL1
);
1765 /* for sys int and cmn int */
1766 enable_local_vic_irq(7);
1768 if (is_cpu_quad()) {
1769 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
1770 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
1771 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1772 cpu
, QIC_CPI_ENABLE
));
1775 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1776 cpu
, vic_irq_mask
[cpu
]));
1779 void voyager_smp_dump()
1781 int old_cpu
= smp_processor_id(), cpu
;
1783 /* dump the interrupt masks of each processor */
1784 for_each_online_cpu(cpu
) {
1785 __u16 imr
, isr
, irr
;
1786 unsigned long flags
;
1788 local_irq_save(flags
);
1789 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
1790 imr
= (inb(0xa1) << 8) | inb(0x21);
1792 irr
= inb(0xa0) << 8;
1796 isr
= inb(0xa0) << 8;
1799 outb(old_cpu
, VIC_PROCESSOR_ID
);
1800 local_irq_restore(flags
);
1801 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1802 cpu
, vic_irq_mask
[cpu
], imr
, irr
, isr
);
1804 /* These lines are put in to try to unstick an un ack'd irq */
1807 for (irq
= 0; irq
< 16; irq
++) {
1808 if (isr
& (1 << irq
)) {
1809 printk("\tCPU%d: ack irq %d\n",
1811 local_irq_save(flags
);
1812 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
,
1815 outb(old_cpu
, VIC_PROCESSOR_ID
);
1816 local_irq_restore(flags
);
1824 void smp_voyager_power_off(void *dummy
)
1826 if (smp_processor_id() == boot_cpu_id
)
1827 voyager_power_off();
1829 smp_stop_cpu_function(NULL
);
1832 static void __init
voyager_smp_prepare_cpus(unsigned int max_cpus
)
1834 /* FIXME: ignore max_cpus for now */
1838 static void __cpuinit
voyager_smp_prepare_boot_cpu(void)
1840 init_gdt(smp_processor_id());
1841 switch_to_new_gdt();
1843 cpu_set(smp_processor_id(), cpu_online_map
);
1844 cpu_set(smp_processor_id(), cpu_callout_map
);
1845 cpu_set(smp_processor_id(), cpu_possible_map
);
1846 cpu_set(smp_processor_id(), cpu_present_map
);
1849 static int __cpuinit
voyager_cpu_up(unsigned int cpu
)
1851 /* This only works at boot for x86. See "rewrite" above. */
1852 if (cpu_isset(cpu
, smp_commenced_mask
))
1855 /* In case one didn't come up */
1856 if (!cpu_isset(cpu
, cpu_callin_map
))
1858 /* Unleash the CPU! */
1859 cpu_set(cpu
, smp_commenced_mask
);
1860 while (!cpu_isset(cpu
, cpu_online_map
))
1865 static void __init
voyager_smp_cpus_done(unsigned int max_cpus
)
1870 void __init
smp_setup_processor_id(void)
1872 current_thread_info()->cpu
= hard_smp_processor_id();
1873 x86_write_percpu(cpu_number
, hard_smp_processor_id());
1876 struct smp_ops smp_ops
= {
1877 .smp_prepare_boot_cpu
= voyager_smp_prepare_boot_cpu
,
1878 .smp_prepare_cpus
= voyager_smp_prepare_cpus
,
1879 .cpu_up
= voyager_cpu_up
,
1880 .smp_cpus_done
= voyager_smp_cpus_done
,
1882 .smp_send_stop
= voyager_smp_send_stop
,
1883 .smp_send_reschedule
= voyager_smp_send_reschedule
,
1884 .smp_call_function_mask
= voyager_smp_call_function_mask
,