1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * This file provides all the same external entries as smp.c but uses
8 * the voyager hal to provide the functionality
10 #include <linux/module.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/delay.h>
14 #include <linux/mc146818rtc.h>
15 #include <linux/cache.h>
16 #include <linux/interrupt.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/bootmem.h>
20 #include <linux/completion.h>
22 #include <asm/voyager.h>
25 #include <asm/pgalloc.h>
26 #include <asm/tlbflush.h>
27 #include <asm/arch_hooks.h>
28 #include <asm/trampoline.h>
30 /* TLB state -- visible externally, indexed physically */
31 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state
, cpu_tlbstate
) = { &init_mm
, 0 };
33 /* CPU IRQ affinity -- set to all ones initially */
34 static unsigned long cpu_irq_affinity
[NR_CPUS
] __cacheline_aligned
=
35 {[0 ... NR_CPUS
-1] = ~0UL };
37 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
38 * indexed physically */
39 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
40 EXPORT_PER_CPU_SYMBOL(cpu_info
);
42 /* physical ID of the CPU used to boot the system */
43 unsigned char boot_cpu_id
;
45 /* The memory line addresses for the Quad CPIs */
46 struct voyager_qic_cpi
*voyager_quad_cpi_addr
[NR_CPUS
] __cacheline_aligned
;
48 /* The masks for the Extended VIC processors, filled in by cat_init */
49 __u32 voyager_extended_vic_processors
= 0;
51 /* Masks for the extended Quad processors which cannot be VIC booted */
52 __u32 voyager_allowed_boot_processors
= 0;
54 /* The mask for the Quad Processors (both extended and non-extended) */
55 __u32 voyager_quad_processors
= 0;
57 /* Total count of live CPUs, used in process.c to display
58 * the CPU information and in irq.c for the per CPU irq
59 * activity count. Finally exported by i386_ksyms.c */
60 static int voyager_extended_cpus
= 1;
62 /* Have we found an SMP box - used by time.c to do the profiling
63 interrupt for timeslicing; do not set to 1 until the per CPU timer
64 interrupt is active */
65 int smp_found_config
= 0;
67 /* Used for the invalidate map that's also checked in the spinlock */
68 static volatile unsigned long smp_invalidate_needed
;
70 /* Bitmask of currently online CPUs - used by setup.c for
71 /proc/cpuinfo, visible externally but still physical */
72 cpumask_t cpu_online_map
= CPU_MASK_NONE
;
73 EXPORT_SYMBOL(cpu_online_map
);
75 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
76 * by scheduler but indexed physically */
77 cpumask_t phys_cpu_present_map
= CPU_MASK_NONE
;
79 /* The internal functions */
80 static void send_CPI(__u32 cpuset
, __u8 cpi
);
81 static void ack_CPI(__u8 cpi
);
82 static int ack_QIC_CPI(__u8 cpi
);
83 static void ack_special_QIC_CPI(__u8 cpi
);
84 static void ack_VIC_CPI(__u8 cpi
);
85 static void send_CPI_allbutself(__u8 cpi
);
86 static void mask_vic_irq(unsigned int irq
);
87 static void unmask_vic_irq(unsigned int irq
);
88 static unsigned int startup_vic_irq(unsigned int irq
);
89 static void enable_local_vic_irq(unsigned int irq
);
90 static void disable_local_vic_irq(unsigned int irq
);
91 static void before_handle_vic_irq(unsigned int irq
);
92 static void after_handle_vic_irq(unsigned int irq
);
93 static void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
);
94 static void ack_vic_irq(unsigned int irq
);
95 static void vic_enable_cpi(void);
96 static void do_boot_cpu(__u8 cpuid
);
97 static void do_quad_bootstrap(void);
99 int hard_smp_processor_id(void);
100 int safe_smp_processor_id(void);
102 /* Inline functions */
103 static inline void send_one_QIC_CPI(__u8 cpu
, __u8 cpi
)
105 voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
=
106 (smp_processor_id() << 16) + cpi
;
109 static inline void send_QIC_CPI(__u32 cpuset
, __u8 cpi
)
113 for_each_online_cpu(cpu
) {
114 if (cpuset
& (1 << cpu
)) {
116 if (!cpu_isset(cpu
, cpu_online_map
))
117 VDEBUG(("CPU%d sending cpi %d to CPU%d not in "
119 hard_smp_processor_id(), cpi
, cpu
));
121 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
126 static inline void wrapper_smp_local_timer_interrupt(void)
129 smp_local_timer_interrupt();
133 static inline void send_one_CPI(__u8 cpu
, __u8 cpi
)
135 if (voyager_quad_processors
& (1 << cpu
))
136 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
138 send_CPI(1 << cpu
, cpi
);
141 static inline void send_CPI_allbutself(__u8 cpi
)
143 __u8 cpu
= smp_processor_id();
144 __u32 mask
= cpus_addr(cpu_online_map
)[0] & ~(1 << cpu
);
148 static inline int is_cpu_quad(void)
150 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
151 return ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
);
154 static inline int is_cpu_extended(void)
156 __u8 cpu
= hard_smp_processor_id();
158 return (voyager_extended_vic_processors
& (1 << cpu
));
161 static inline int is_cpu_vic_boot(void)
163 __u8 cpu
= hard_smp_processor_id();
165 return (voyager_extended_vic_processors
166 & voyager_allowed_boot_processors
& (1 << cpu
));
169 static inline void ack_CPI(__u8 cpi
)
172 case VIC_CPU_BOOT_CPI
:
173 if (is_cpu_quad() && !is_cpu_vic_boot())
180 /* These are slightly strange. Even on the Quad card,
181 * They are vectored as VIC CPIs */
183 ack_special_QIC_CPI(cpi
);
188 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi
);
193 /* local variables */
195 /* The VIC IRQ descriptors -- these look almost identical to the
196 * 8259 IRQs except that masks and things must be kept per processor
198 static struct irq_chip vic_chip
= {
200 .startup
= startup_vic_irq
,
201 .mask
= mask_vic_irq
,
202 .unmask
= unmask_vic_irq
,
203 .set_affinity
= set_vic_irq_affinity
,
206 /* used to count up as CPUs are brought on line (starts at 0) */
207 static int cpucount
= 0;
209 /* steal a page from the bottom of memory for the trampoline and
210 * squirrel its address away here. This will be in kernel virtual
212 unsigned char *trampoline_base
;
214 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
215 static DEFINE_PER_CPU(int, prof_multiplier
) = 1;
216 static DEFINE_PER_CPU(int, prof_old_multiplier
) = 1;
217 static DEFINE_PER_CPU(int, prof_counter
) = 1;
219 /* the map used to check if a CPU has booted */
220 static __u32 cpu_booted_map
;
222 /* the synchronize flag used to hold all secondary CPUs spinning in
223 * a tight loop until the boot sequence is ready for them */
224 static cpumask_t smp_commenced_mask
= CPU_MASK_NONE
;
226 /* This is for the new dynamic CPU boot code */
227 cpumask_t cpu_callin_map
= CPU_MASK_NONE
;
228 cpumask_t cpu_callout_map
= CPU_MASK_NONE
;
229 cpumask_t cpu_possible_map
= CPU_MASK_NONE
;
230 EXPORT_SYMBOL(cpu_possible_map
);
232 /* The per processor IRQ masks (these are usually kept in sync) */
233 static __u16 vic_irq_mask
[NR_CPUS
] __cacheline_aligned
;
235 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
236 static __u16 vic_irq_enable_mask
[NR_CPUS
] __cacheline_aligned
= { 0 };
238 /* Lock for enable/disable of VIC interrupts */
239 static __cacheline_aligned
DEFINE_SPINLOCK(vic_irq_lock
);
241 /* The boot processor is correctly set up in PC mode when it
242 * comes up, but the secondaries need their master/slave 8259
243 * pairs initializing correctly */
245 /* Interrupt counters (per cpu) and total - used to try to
246 * even up the interrupt handling routines */
247 static long vic_intr_total
= 0;
248 static long vic_intr_count
[NR_CPUS
] __cacheline_aligned
= { 0 };
249 static unsigned long vic_tick
[NR_CPUS
] __cacheline_aligned
= { 0 };
251 /* Since we can only use CPI0, we fake all the other CPIs */
252 static unsigned long vic_cpi_mailbox
[NR_CPUS
] __cacheline_aligned
;
254 /* debugging routine to read the isr of the cpu's pic */
255 static inline __u16
vic_read_isr(void)
260 isr
= inb(0xa0) << 8;
267 static __init
void qic_setup(void)
269 if (!is_cpu_quad()) {
270 /* not a quad, no setup */
273 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
274 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
276 if (is_cpu_extended()) {
277 /* the QIC duplicate of the VIC base register */
278 outb(VIC_DEFAULT_CPI_BASE
, QIC_VIC_CPI_BASE_REGISTER
);
279 outb(QIC_DEFAULT_CPI_BASE
, QIC_CPI_BASE_REGISTER
);
281 /* FIXME: should set up the QIC timer and memory parity
282 * error vectors here */
286 static __init
void vic_setup_pic(void)
288 outb(1, VIC_REDIRECT_REGISTER_1
);
289 /* clear the claim registers for dynamic routing */
290 outb(0, VIC_CLAIM_REGISTER_0
);
291 outb(0, VIC_CLAIM_REGISTER_1
);
293 outb(0, VIC_PRIORITY_REGISTER
);
294 /* Set the Primary and Secondary Microchannel vector
295 * bases to be the same as the ordinary interrupts
297 * FIXME: This would be more efficient using separate
299 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
300 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
301 /* Now initiallise the master PIC belonging to this CPU by
302 * sending the four ICWs */
304 /* ICW1: level triggered, ICW4 needed */
307 /* ICW2: vector base */
308 outb(FIRST_EXTERNAL_VECTOR
, 0x21);
310 /* ICW3: slave at line 2 */
313 /* ICW4: 8086 mode */
316 /* now the same for the slave PIC */
318 /* ICW1: level trigger, ICW4 needed */
321 /* ICW2: slave vector base */
322 outb(FIRST_EXTERNAL_VECTOR
+ 8, 0xA1);
327 /* ICW4: 8086 mode */
331 static void do_quad_bootstrap(void)
333 if (is_cpu_quad() && is_cpu_vic_boot()) {
336 __u8 cpuid
= hard_smp_processor_id();
338 local_irq_save(flags
);
340 for (i
= 0; i
< 4; i
++) {
341 /* FIXME: this would be >>3 &0x7 on the 32 way */
342 if (((cpuid
>> 2) & 0x03) == i
)
343 /* don't lower our own mask! */
346 /* masquerade as local Quad CPU */
347 outb(QIC_CPUID_ENABLE
| i
, QIC_PROCESSOR_ID
);
348 /* enable the startup CPI */
349 outb(QIC_BOOT_CPI_MASK
, QIC_MASK_REGISTER1
);
351 outb(0, QIC_PROCESSOR_ID
);
353 local_irq_restore(flags
);
357 /* Set up all the basic stuff: read the SMP config and make all the
358 * SMP information reflect only the boot cpu. All others will be
359 * brought on-line later. */
360 void __init
find_smp_config(void)
364 boot_cpu_id
= hard_smp_processor_id();
366 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id
);
368 /* initialize the CPU structures (moved from smp_boot_cpus) */
369 for (i
= 0; i
< NR_CPUS
; i
++) {
370 cpu_irq_affinity
[i
] = ~0;
372 cpu_online_map
= cpumask_of_cpu(boot_cpu_id
);
374 /* The boot CPU must be extended */
375 voyager_extended_vic_processors
= 1 << boot_cpu_id
;
376 /* initially, all of the first 8 CPUs can boot */
377 voyager_allowed_boot_processors
= 0xff;
378 /* set up everything for just this CPU, we can alter
379 * this as we start the other CPUs later */
380 /* now get the CPU disposition from the extended CMOS */
381 cpus_addr(phys_cpu_present_map
)[0] =
382 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
);
383 cpus_addr(phys_cpu_present_map
)[0] |=
384 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+ 1) << 8;
385 cpus_addr(phys_cpu_present_map
)[0] |=
386 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+
388 cpus_addr(phys_cpu_present_map
)[0] |=
389 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+
391 cpu_possible_map
= phys_cpu_present_map
;
392 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n",
393 cpus_addr(phys_cpu_present_map
)[0]);
394 /* Here we set up the VIC to enable SMP */
395 /* enable the CPIs by writing the base vector to their register */
396 outb(VIC_DEFAULT_CPI_BASE
, VIC_CPI_BASE_REGISTER
);
397 outb(1, VIC_REDIRECT_REGISTER_1
);
398 /* set the claim registers for static routing --- Boot CPU gets
399 * all interrupts untill all other CPUs started */
400 outb(0xff, VIC_CLAIM_REGISTER_0
);
401 outb(0xff, VIC_CLAIM_REGISTER_1
);
402 /* Set the Primary and Secondary Microchannel vector
403 * bases to be the same as the ordinary interrupts
405 * FIXME: This would be more efficient using separate
407 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
408 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
410 /* Finally tell the firmware that we're driving */
411 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT
) | VOYAGER_IN_CONTROL_FLAG
,
412 VOYAGER_SUS_IN_CONTROL_PORT
);
414 current_thread_info()->cpu
= boot_cpu_id
;
415 x86_write_percpu(cpu_number
, boot_cpu_id
);
419 * The bootstrap kernel entry code has set these up. Save them
420 * for a given CPU, id is physical */
421 void __init
smp_store_cpu_info(int id
)
423 struct cpuinfo_x86
*c
= &cpu_data(id
);
427 identify_secondary_cpu(c
);
430 /* set up the trampoline and return the physical address of the code */
431 unsigned long __init
setup_trampoline(void)
433 /* these two are global symbols in trampoline.S */
434 extern const __u8 trampoline_end
[];
435 extern const __u8 trampoline_data
[];
437 memcpy(trampoline_base
, trampoline_data
,
438 trampoline_end
- trampoline_data
);
439 return virt_to_phys(trampoline_base
);
442 /* Routine initially called when a non-boot CPU is brought online */
443 static void __init
start_secondary(void *unused
)
445 __u8 cpuid
= hard_smp_processor_id();
449 /* OK, we're in the routine */
450 ack_CPI(VIC_CPU_BOOT_CPI
);
452 /* setup the 8259 master slave pair belonging to this CPU ---
453 * we won't actually receive any until the boot CPU
454 * relinquishes it's static routing mask */
459 if (is_cpu_quad() && !is_cpu_vic_boot()) {
460 /* clear the boot CPI */
464 voyager_quad_cpi_addr
[cpuid
]->qic_cpi
[VIC_CPU_BOOT_CPI
].cpi
;
465 printk("read dummy %d\n", dummy
);
468 /* lower the mask to receive CPIs */
471 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid
, &cpuid
));
473 /* enable interrupts */
476 /* get our bogomips */
479 /* save our processor parameters */
480 smp_store_cpu_info(cpuid
);
482 /* if we're a quad, we may need to bootstrap other CPUs */
485 /* FIXME: this is rather a poor hack to prevent the CPU
486 * activating softirqs while it's supposed to be waiting for
487 * permission to proceed. Without this, the new per CPU stuff
488 * in the softirqs will fail */
490 cpu_set(cpuid
, cpu_callin_map
);
492 /* signal that we're done */
495 while (!cpu_isset(cpuid
, smp_commenced_mask
))
501 cpu_set(cpuid
, cpu_online_map
);
506 /* Routine to kick start the given CPU and wait for it to report ready
507 * (or timeout in startup). When this routine returns, the requested
508 * CPU is either fully running and configured or known to be dead.
510 * We call this routine sequentially 1 CPU at a time, so no need for
513 static void __init
do_boot_cpu(__u8 cpu
)
515 struct task_struct
*idle
;
518 int quad_boot
= (1 << cpu
) & voyager_quad_processors
519 & ~(voyager_extended_vic_processors
520 & voyager_allowed_boot_processors
);
522 /* This is the format of the CPI IDT gate (in real mode) which
523 * we're hijacking to boot the CPU */
532 __u32
*hijack_vector
;
533 __u32 start_phys_address
= setup_trampoline();
535 /* There's a clever trick to this: The linux trampoline is
536 * compiled to begin at absolute location zero, so make the
537 * address zero but have the data segment selector compensate
538 * for the actual address */
539 hijack_source
.idt
.Offset
= start_phys_address
& 0x000F;
540 hijack_source
.idt
.Segment
= (start_phys_address
>> 4) & 0xFFFF;
543 alternatives_smp_switch(1);
545 idle
= fork_idle(cpu
);
547 panic("failed fork for CPU%d", cpu
);
548 idle
->thread
.ip
= (unsigned long)start_secondary
;
549 /* init_tasks (in sched.c) is indexed logically */
550 stack_start
.sp
= (void *)idle
->thread
.sp
;
553 per_cpu(current_task
, cpu
) = idle
;
554 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
557 /* Note: Don't modify initial ss override */
558 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu
,
559 (unsigned long)hijack_source
.val
, hijack_source
.idt
.Segment
,
560 hijack_source
.idt
.Offset
, stack_start
.sp
));
562 /* init lowmem identity mapping */
563 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ USER_PGD_PTRS
,
564 min_t(unsigned long, KERNEL_PGD_PTRS
, USER_PGD_PTRS
));
568 printk("CPU %d: non extended Quad boot\n", cpu
);
571 phys_to_virt((VIC_CPU_BOOT_CPI
+ QIC_DEFAULT_CPI_BASE
) * 4);
572 *hijack_vector
= hijack_source
.val
;
574 printk("CPU%d: extended VIC boot\n", cpu
);
577 phys_to_virt((VIC_CPU_BOOT_CPI
+ VIC_DEFAULT_CPI_BASE
) * 4);
578 *hijack_vector
= hijack_source
.val
;
579 /* VIC errata, may also receive interrupt at this address */
582 phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI
+
583 VIC_DEFAULT_CPI_BASE
) * 4);
584 *hijack_vector
= hijack_source
.val
;
586 /* All non-boot CPUs start with interrupts fully masked. Need
587 * to lower the mask of the CPI we're about to send. We do
588 * this in the VIC by masquerading as the processor we're
589 * about to boot and lowering its interrupt mask */
590 local_irq_save(flags
);
592 send_one_QIC_CPI(cpu
, VIC_CPU_BOOT_CPI
);
594 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
595 /* here we're altering registers belonging to `cpu' */
597 outb(VIC_BOOT_INTERRUPT_MASK
, 0x21);
598 /* now go back to our original identity */
599 outb(boot_cpu_id
, VIC_PROCESSOR_ID
);
601 /* and boot the CPU */
603 send_CPI((1 << cpu
), VIC_CPU_BOOT_CPI
);
606 local_irq_restore(flags
);
608 /* now wait for it to become ready (or timeout) */
609 for (timeout
= 0; timeout
< 50000; timeout
++) {
614 /* reset the page table */
617 if (cpu_booted_map
) {
618 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
619 cpu
, smp_processor_id()));
621 printk("CPU%d: ", cpu
);
622 print_cpu_info(&cpu_data(cpu
));
624 cpu_set(cpu
, cpu_callout_map
);
625 cpu_set(cpu
, cpu_present_map
);
627 printk("CPU%d FAILED TO BOOT: ", cpu
);
629 ((volatile unsigned char *)phys_to_virt(start_phys_address
))
633 printk("Not responding.\n");
639 void __init
smp_boot_cpus(void)
643 /* CAT BUS initialisation must be done after the memory */
644 /* FIXME: The L4 has a catbus too, it just needs to be
645 * accessed in a totally different way */
646 if (voyager_level
== 5) {
649 /* now that the cat has probed the Voyager System Bus, sanity
650 * check the cpu map */
651 if (((voyager_quad_processors
| voyager_extended_vic_processors
)
652 & cpus_addr(phys_cpu_present_map
)[0]) !=
653 cpus_addr(phys_cpu_present_map
)[0]) {
655 printk("\n\n***WARNING*** "
656 "Sanity check of CPU present map FAILED\n");
658 } else if (voyager_level
== 4)
659 voyager_extended_vic_processors
=
660 cpus_addr(phys_cpu_present_map
)[0];
662 /* this sets up the idle task to run on the current cpu */
663 voyager_extended_cpus
= 1;
664 /* Remove the global_irq_holder setting, it triggers a BUG() on
665 * schedule at the moment */
666 //global_irq_holder = boot_cpu_id;
668 /* FIXME: Need to do something about this but currently only works
669 * on CPUs with a tsc which none of mine have.
670 smp_tune_scheduling();
672 smp_store_cpu_info(boot_cpu_id
);
673 printk("CPU%d: ", boot_cpu_id
);
674 print_cpu_info(&cpu_data(boot_cpu_id
));
677 /* booting on a Quad CPU */
678 printk("VOYAGER SMP: Boot CPU is Quad\n");
683 /* enable our own CPIs */
686 cpu_set(boot_cpu_id
, cpu_online_map
);
687 cpu_set(boot_cpu_id
, cpu_callout_map
);
689 /* loop over all the extended VIC CPUs and boot them. The
690 * Quad CPUs must be bootstrapped by their extended VIC cpu */
691 for (i
= 0; i
< NR_CPUS
; i
++) {
692 if (i
== boot_cpu_id
|| !cpu_isset(i
, phys_cpu_present_map
))
695 /* This udelay seems to be needed for the Quad boots
696 * don't remove unless you know what you're doing */
699 /* we could compute the total bogomips here, but why bother?,
700 * Code added from smpboot.c */
702 unsigned long bogosum
= 0;
703 for (i
= 0; i
< NR_CPUS
; i
++)
704 if (cpu_isset(i
, cpu_online_map
))
705 bogosum
+= cpu_data(i
).loops_per_jiffy
;
706 printk(KERN_INFO
"Total of %d processors activated "
707 "(%lu.%02lu BogoMIPS).\n",
708 cpucount
+ 1, bogosum
/ (500000 / HZ
),
709 (bogosum
/ (5000 / HZ
)) % 100);
711 voyager_extended_cpus
= hweight32(voyager_extended_vic_processors
);
712 printk("VOYAGER: Extended (interrupt handling CPUs): "
713 "%d, non-extended: %d\n", voyager_extended_cpus
,
714 num_booting_cpus() - voyager_extended_cpus
);
715 /* that's it, switch to symmetric mode */
716 outb(0, VIC_PRIORITY_REGISTER
);
717 outb(0, VIC_CLAIM_REGISTER_0
);
718 outb(0, VIC_CLAIM_REGISTER_1
);
720 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
723 /* Reload the secondary CPUs task structure (this function does not
725 void __init
initialize_secondary(void)
729 set_current(hard_get_current());
733 * We don't actually need to load the full TSS,
734 * basically just the stack pointer and the eip.
737 asm volatile ("movl %0,%%esp\n\t"
738 "jmp *%1"::"r" (current
->thread
.sp
),
739 "r"(current
->thread
.ip
));
742 /* handle a Voyager SYS_INT -- If we don't, the base board will
745 * System interrupts occur because some problem was detected on the
746 * various busses. To find out what you have to probe all the
747 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
748 void smp_vic_sys_interrupt(struct pt_regs
*regs
)
750 ack_CPI(VIC_SYS_INT
);
751 printk("Voyager SYSTEM INTERRUPT\n");
754 /* Handle a voyager CMN_INT; These interrupts occur either because of
755 * a system status change or because a single bit memory error
756 * occurred. FIXME: At the moment, ignore all this. */
757 void smp_vic_cmn_interrupt(struct pt_regs
*regs
)
759 static __u8 in_cmn_int
= 0;
760 static DEFINE_SPINLOCK(cmn_int_lock
);
762 /* common ints are broadcast, so make sure we only do this once */
763 _raw_spin_lock(&cmn_int_lock
);
768 _raw_spin_unlock(&cmn_int_lock
);
770 VDEBUG(("Voyager COMMON INTERRUPT\n"));
772 if (voyager_level
== 5)
773 voyager_cat_do_common_interrupt();
775 _raw_spin_lock(&cmn_int_lock
);
778 _raw_spin_unlock(&cmn_int_lock
);
779 ack_CPI(VIC_CMN_INT
);
783 * Reschedule call back. Nothing to do, all the work is done
784 * automatically when we return from the interrupt. */
785 static void smp_reschedule_interrupt(void)
790 static struct mm_struct
*flush_mm
;
791 static unsigned long flush_va
;
792 static DEFINE_SPINLOCK(tlbstate_lock
);
795 * We cannot call mmdrop() because we are in interrupt context,
796 * instead update mm->cpu_vm_mask.
798 * We need to reload %cr3 since the page tables may be going
799 * away from under us..
801 static inline void voyager_leave_mm(unsigned long cpu
)
803 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
)
805 cpu_clear(cpu
, per_cpu(cpu_tlbstate
, cpu
).active_mm
->cpu_vm_mask
);
806 load_cr3(swapper_pg_dir
);
810 * Invalidate call-back
812 static void smp_invalidate_interrupt(void)
814 __u8 cpu
= smp_processor_id();
816 if (!test_bit(cpu
, &smp_invalidate_needed
))
818 /* This will flood messages. Don't uncomment unless you see
819 * Problems with cross cpu invalidation
820 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
821 smp_processor_id()));
824 if (flush_mm
== per_cpu(cpu_tlbstate
, cpu
).active_mm
) {
825 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
) {
826 if (flush_va
== TLB_FLUSH_ALL
)
829 __flush_tlb_one(flush_va
);
831 voyager_leave_mm(cpu
);
833 smp_mb__before_clear_bit();
834 clear_bit(cpu
, &smp_invalidate_needed
);
835 smp_mb__after_clear_bit();
838 /* All the new flush operations for 2.4 */
840 /* This routine is called with a physical cpu mask */
842 voyager_flush_tlb_others(unsigned long cpumask
, struct mm_struct
*mm
,
849 if ((cpumask
& cpus_addr(cpu_online_map
)[0]) != cpumask
)
851 if (cpumask
& (1 << smp_processor_id()))
856 spin_lock(&tlbstate_lock
);
860 atomic_set_mask(cpumask
, &smp_invalidate_needed
);
862 * We have to send the CPI only to
865 send_CPI(cpumask
, VIC_INVALIDATE_CPI
);
867 while (smp_invalidate_needed
) {
870 printk("***WARNING*** Stuck doing invalidate CPI "
871 "(CPU%d)\n", smp_processor_id());
876 /* Uncomment only to debug invalidation problems
877 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
882 spin_unlock(&tlbstate_lock
);
885 void flush_tlb_current_task(void)
887 struct mm_struct
*mm
= current
->mm
;
888 unsigned long cpu_mask
;
892 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
895 voyager_flush_tlb_others(cpu_mask
, mm
, TLB_FLUSH_ALL
);
900 void flush_tlb_mm(struct mm_struct
*mm
)
902 unsigned long cpu_mask
;
906 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
908 if (current
->active_mm
== mm
) {
912 voyager_leave_mm(smp_processor_id());
915 voyager_flush_tlb_others(cpu_mask
, mm
, TLB_FLUSH_ALL
);
920 void flush_tlb_page(struct vm_area_struct
*vma
, unsigned long va
)
922 struct mm_struct
*mm
= vma
->vm_mm
;
923 unsigned long cpu_mask
;
927 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
928 if (current
->active_mm
== mm
) {
932 voyager_leave_mm(smp_processor_id());
936 voyager_flush_tlb_others(cpu_mask
, mm
, va
);
941 EXPORT_SYMBOL(flush_tlb_page
);
943 /* enable the requested IRQs */
944 static void smp_enable_irq_interrupt(void)
947 __u8 cpu
= get_cpu();
949 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu
,
950 vic_irq_enable_mask
[cpu
]));
952 spin_lock(&vic_irq_lock
);
953 for (irq
= 0; irq
< 16; irq
++) {
954 if (vic_irq_enable_mask
[cpu
] & (1 << irq
))
955 enable_local_vic_irq(irq
);
957 vic_irq_enable_mask
[cpu
] = 0;
958 spin_unlock(&vic_irq_lock
);
960 put_cpu_no_resched();
966 static void smp_stop_cpu_function(void *dummy
)
968 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
969 cpu_clear(smp_processor_id(), cpu_online_map
);
975 static DEFINE_SPINLOCK(call_lock
);
977 struct call_data_struct
{
978 void (*func
) (void *info
);
980 volatile unsigned long started
;
981 volatile unsigned long finished
;
985 static struct call_data_struct
*call_data
;
987 /* execute a thread on a new CPU. The function to be called must be
988 * previously set up. This is used to schedule a function for
989 * execution on all CPUs - set up the function then broadcast a
990 * function_interrupt CPI to come here on each CPU */
991 static void smp_call_function_interrupt(void)
993 void (*func
) (void *info
) = call_data
->func
;
994 void *info
= call_data
->info
;
995 /* must take copy of wait because call_data may be replaced
996 * unless the function is waiting for us to finish */
997 int wait
= call_data
->wait
;
998 __u8 cpu
= smp_processor_id();
1001 * Notify initiating CPU that I've grabbed the data and am
1002 * about to execute the function
1005 if (!test_and_clear_bit(cpu
, &call_data
->started
)) {
1006 /* If the bit wasn't set, this could be a replay */
1007 printk(KERN_WARNING
"VOYAGER SMP: CPU %d received call funtion"
1008 " with no call pending\n", cpu
);
1012 * At this point the info structure may be out of scope unless wait==1
1016 __get_cpu_var(irq_stat
).irq_call_count
++;
1020 clear_bit(cpu
, &call_data
->finished
);
1025 voyager_smp_call_function_mask(cpumask_t cpumask
,
1026 void (*func
) (void *info
), void *info
, int wait
)
1028 struct call_data_struct data
;
1029 u32 mask
= cpus_addr(cpumask
)[0];
1031 mask
&= ~(1 << smp_processor_id());
1036 /* Can deadlock when called with interrupts disabled */
1037 WARN_ON(irqs_disabled());
1041 data
.started
= mask
;
1044 data
.finished
= mask
;
1046 spin_lock(&call_lock
);
1049 /* Send a message to all other CPUs and wait for them to respond */
1050 send_CPI(mask
, VIC_CALL_FUNCTION_CPI
);
1052 /* Wait for response */
1053 while (data
.started
)
1057 while (data
.finished
)
1060 spin_unlock(&call_lock
);
1065 /* Sorry about the name. In an APIC based system, the APICs
1066 * themselves are programmed to send a timer interrupt. This is used
1067 * by linux to reschedule the processor. Voyager doesn't have this,
1068 * so we use the system clock to interrupt one processor, which in
1069 * turn, broadcasts a timer CPI to all the others --- we receive that
1070 * CPI here. We don't use this actually for counting so losing
1071 * ticks doesn't matter
1073 * FIXME: For those CPUs which actually have a local APIC, we could
1074 * try to use it to trigger this interrupt instead of having to
1075 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1076 * no local APIC, so I can't do this
1078 * This function is currently a placeholder and is unused in the code */
1079 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1081 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1082 wrapper_smp_local_timer_interrupt();
1083 set_irq_regs(old_regs
);
1086 /* All of the QUAD interrupt GATES */
1087 void smp_qic_timer_interrupt(struct pt_regs
*regs
)
1089 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1090 ack_QIC_CPI(QIC_TIMER_CPI
);
1091 wrapper_smp_local_timer_interrupt();
1092 set_irq_regs(old_regs
);
1095 void smp_qic_invalidate_interrupt(struct pt_regs
*regs
)
1097 ack_QIC_CPI(QIC_INVALIDATE_CPI
);
1098 smp_invalidate_interrupt();
1101 void smp_qic_reschedule_interrupt(struct pt_regs
*regs
)
1103 ack_QIC_CPI(QIC_RESCHEDULE_CPI
);
1104 smp_reschedule_interrupt();
1107 void smp_qic_enable_irq_interrupt(struct pt_regs
*regs
)
1109 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI
);
1110 smp_enable_irq_interrupt();
1113 void smp_qic_call_function_interrupt(struct pt_regs
*regs
)
1115 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI
);
1116 smp_call_function_interrupt();
1119 void smp_vic_cpi_interrupt(struct pt_regs
*regs
)
1121 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1122 __u8 cpu
= smp_processor_id();
1125 ack_QIC_CPI(VIC_CPI_LEVEL0
);
1127 ack_VIC_CPI(VIC_CPI_LEVEL0
);
1129 if (test_and_clear_bit(VIC_TIMER_CPI
, &vic_cpi_mailbox
[cpu
]))
1130 wrapper_smp_local_timer_interrupt();
1131 if (test_and_clear_bit(VIC_INVALIDATE_CPI
, &vic_cpi_mailbox
[cpu
]))
1132 smp_invalidate_interrupt();
1133 if (test_and_clear_bit(VIC_RESCHEDULE_CPI
, &vic_cpi_mailbox
[cpu
]))
1134 smp_reschedule_interrupt();
1135 if (test_and_clear_bit(VIC_ENABLE_IRQ_CPI
, &vic_cpi_mailbox
[cpu
]))
1136 smp_enable_irq_interrupt();
1137 if (test_and_clear_bit(VIC_CALL_FUNCTION_CPI
, &vic_cpi_mailbox
[cpu
]))
1138 smp_call_function_interrupt();
1139 set_irq_regs(old_regs
);
1142 static void do_flush_tlb_all(void *info
)
1144 unsigned long cpu
= smp_processor_id();
1147 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_LAZY
)
1148 voyager_leave_mm(cpu
);
1151 /* flush the TLB of every active CPU in the system */
1152 void flush_tlb_all(void)
1154 on_each_cpu(do_flush_tlb_all
, 0, 1, 1);
1157 /* used to set up the trampoline for other CPUs when the memory manager
1159 void __init
smp_alloc_memory(void)
1161 trampoline_base
= alloc_bootmem_low_pages(PAGE_SIZE
);
1162 if (__pa(trampoline_base
) >= 0x93000)
1166 /* send a reschedule CPI to one CPU by physical CPU number*/
1167 static void voyager_smp_send_reschedule(int cpu
)
1169 send_one_CPI(cpu
, VIC_RESCHEDULE_CPI
);
1172 int hard_smp_processor_id(void)
1175 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
1176 if ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
)
1177 return cpumask
& 0x1F;
1179 for (i
= 0; i
< 8; i
++) {
1180 if (cpumask
& (1 << i
))
1183 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask
);
1187 int safe_smp_processor_id(void)
1189 return hard_smp_processor_id();
1192 /* broadcast a halt to all other CPUs */
1193 static void voyager_smp_send_stop(void)
1195 smp_call_function(smp_stop_cpu_function
, NULL
, 1, 1);
1198 /* this function is triggered in time.c when a clock tick fires
1199 * we need to re-broadcast the tick to all CPUs */
1200 void smp_vic_timer_interrupt(void)
1202 send_CPI_allbutself(VIC_TIMER_CPI
);
1203 smp_local_timer_interrupt();
1206 /* local (per CPU) timer interrupt. It does both profiling and
1207 * process statistics/rescheduling.
1209 * We do profiling in every local tick, statistics/rescheduling
1210 * happen only every 'profiling multiplier' ticks. The default
1211 * multiplier is 1 and it can be changed by writing the new multiplier
1212 * value into /proc/profile.
1214 void smp_local_timer_interrupt(void)
1216 int cpu
= smp_processor_id();
1219 profile_tick(CPU_PROFILING
);
1220 if (--per_cpu(prof_counter
, cpu
) <= 0) {
1222 * The multiplier may have changed since the last time we got
1223 * to this point as a result of the user writing to
1224 * /proc/profile. In this case we need to adjust the APIC
1225 * timer accordingly.
1227 * Interrupts are already masked off at this point.
1229 per_cpu(prof_counter
, cpu
) = per_cpu(prof_multiplier
, cpu
);
1230 if (per_cpu(prof_counter
, cpu
) !=
1231 per_cpu(prof_old_multiplier
, cpu
)) {
1232 /* FIXME: need to update the vic timer tick here */
1233 per_cpu(prof_old_multiplier
, cpu
) =
1234 per_cpu(prof_counter
, cpu
);
1237 update_process_times(user_mode_vm(get_irq_regs()));
1240 if (((1 << cpu
) & voyager_extended_vic_processors
) == 0)
1241 /* only extended VIC processors participate in
1242 * interrupt distribution */
1246 * We take the 'long' return path, and there every subsystem
1247 * grabs the appropriate locks (kernel lock/ irq lock).
1249 * we might want to decouple profiling from the 'long path',
1250 * and do the profiling totally in assembly.
1252 * Currently this isn't too much of an issue (performance wise),
1253 * we can take more than 100K local irqs per second on a 100 MHz P5.
1256 if ((++vic_tick
[cpu
] & 0x7) != 0)
1258 /* get here every 16 ticks (about every 1/6 of a second) */
1260 /* Change our priority to give someone else a chance at getting
1261 * the IRQ. The algorithm goes like this:
1263 * In the VIC, the dynamically routed interrupt is always
1264 * handled by the lowest priority eligible (i.e. receiving
1265 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1266 * lowest processor number gets it.
1268 * The priority of a CPU is controlled by a special per-CPU
1269 * VIC priority register which is 3 bits wide 0 being lowest
1270 * and 7 highest priority..
1272 * Therefore we subtract the average number of interrupts from
1273 * the number we've fielded. If this number is negative, we
1274 * lower the activity count and if it is positive, we raise
1277 * I'm afraid this still leads to odd looking interrupt counts:
1278 * the totals are all roughly equal, but the individual ones
1279 * look rather skewed.
1281 * FIXME: This algorithm is total crap when mixed with SMP
1282 * affinity code since we now try to even up the interrupt
1283 * counts when an affinity binding is keeping them on a
1285 weight
= (vic_intr_count
[cpu
] * voyager_extended_cpus
1286 - vic_intr_total
) >> 4;
1293 outb((__u8
) weight
, VIC_PRIORITY_REGISTER
);
1295 #ifdef VOYAGER_DEBUG
1296 if ((vic_tick
[cpu
] & 0xFFF) == 0) {
1297 /* print this message roughly every 25 secs */
1298 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1299 cpu
, vic_tick
[cpu
], weight
);
1304 /* setup the profiling timer */
1305 int setup_profiling_timer(unsigned int multiplier
)
1313 * Set the new multiplier for each CPU. CPUs don't start using the
1314 * new values until the next timer interrupt in which they do process
1317 for (i
= 0; i
< NR_CPUS
; ++i
)
1318 per_cpu(prof_multiplier
, i
) = multiplier
;
1323 /* This is a bit of a mess, but forced on us by the genirq changes
1324 * there's no genirq handler that really does what voyager wants
1325 * so hack it up with the simple IRQ handler */
1326 static void handle_vic_irq(unsigned int irq
, struct irq_desc
*desc
)
1328 before_handle_vic_irq(irq
);
1329 handle_simple_irq(irq
, desc
);
1330 after_handle_vic_irq(irq
);
1333 /* The CPIs are handled in the per cpu 8259s, so they must be
1334 * enabled to be received: FIX: enabling the CPIs in the early
1335 * boot sequence interferes with bug checking; enable them later
1337 #define VIC_SET_GATE(cpi, vector) \
1338 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1339 #define QIC_SET_GATE(cpi, vector) \
1340 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1342 void __init
smp_intr_init(void)
1346 /* initialize the per cpu irq mask to all disabled */
1347 for (i
= 0; i
< NR_CPUS
; i
++)
1348 vic_irq_mask
[i
] = 0xFFFF;
1350 VIC_SET_GATE(VIC_CPI_LEVEL0
, vic_cpi_interrupt
);
1352 VIC_SET_GATE(VIC_SYS_INT
, vic_sys_interrupt
);
1353 VIC_SET_GATE(VIC_CMN_INT
, vic_cmn_interrupt
);
1355 QIC_SET_GATE(QIC_TIMER_CPI
, qic_timer_interrupt
);
1356 QIC_SET_GATE(QIC_INVALIDATE_CPI
, qic_invalidate_interrupt
);
1357 QIC_SET_GATE(QIC_RESCHEDULE_CPI
, qic_reschedule_interrupt
);
1358 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI
, qic_enable_irq_interrupt
);
1359 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI
, qic_call_function_interrupt
);
1361 /* now put the VIC descriptor into the first 48 IRQs
1363 * This is for later: first 16 correspond to PC IRQs; next 16
1364 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1365 for (i
= 0; i
< 48; i
++)
1366 set_irq_chip_and_handler(i
, &vic_chip
, handle_vic_irq
);
1369 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1370 * processor to receive CPI */
1371 static void send_CPI(__u32 cpuset
, __u8 cpi
)
1374 __u32 quad_cpuset
= (cpuset
& voyager_quad_processors
);
1376 if (cpi
< VIC_START_FAKE_CPI
) {
1377 /* fake CPI are only used for booting, so send to the
1378 * extended quads as well---Quads must be VIC booted */
1379 outb((__u8
) (cpuset
), VIC_CPI_Registers
[cpi
]);
1383 send_QIC_CPI(quad_cpuset
, cpi
);
1384 cpuset
&= ~quad_cpuset
;
1385 cpuset
&= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1388 for_each_online_cpu(cpu
) {
1389 if (cpuset
& (1 << cpu
))
1390 set_bit(cpi
, &vic_cpi_mailbox
[cpu
]);
1393 outb((__u8
) cpuset
, VIC_CPI_Registers
[VIC_CPI_LEVEL0
]);
1396 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1397 * set the cache line to shared by reading it.
1399 * DON'T make this inline otherwise the cache line read will be
1402 static int ack_QIC_CPI(__u8 cpi
)
1404 __u8 cpu
= hard_smp_processor_id();
1408 outb(1 << cpi
, QIC_INTERRUPT_CLEAR1
);
1409 return voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
;
1412 static void ack_special_QIC_CPI(__u8 cpi
)
1416 outb(QIC_CMN_INT
, QIC_INTERRUPT_CLEAR0
);
1419 outb(QIC_SYS_INT
, QIC_INTERRUPT_CLEAR0
);
1422 /* also clear at the VIC, just in case (nop for non-extended proc) */
1426 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1427 static void ack_VIC_CPI(__u8 cpi
)
1429 #ifdef VOYAGER_DEBUG
1430 unsigned long flags
;
1432 __u8 cpu
= smp_processor_id();
1434 local_irq_save(flags
);
1435 isr
= vic_read_isr();
1436 if ((isr
& (1 << (cpi
& 7))) == 0) {
1437 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu
, cpi
);
1440 /* send specific EOI; the two system interrupts have
1441 * bit 4 set for a separate vector but behave as the
1442 * corresponding 3 bit intr */
1443 outb_p(0x60 | (cpi
& 7), 0x20);
1445 #ifdef VOYAGER_DEBUG
1446 if ((vic_read_isr() & (1 << (cpi
& 7))) != 0) {
1447 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu
, cpi
);
1449 local_irq_restore(flags
);
1453 /* cribbed with thanks from irq.c */
1454 #define __byte(x,y) (((unsigned char *)&(y))[x])
1455 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1456 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1458 static unsigned int startup_vic_irq(unsigned int irq
)
1460 unmask_vic_irq(irq
);
1465 /* The enable and disable routines. This is where we run into
1466 * conflicting architectural philosophy. Fundamentally, the voyager
1467 * architecture does not expect to have to disable interrupts globally
1468 * (the IRQ controllers belong to each CPU). The processor masquerade
1469 * which is used to start the system shouldn't be used in a running OS
1470 * since it will cause great confusion if two separate CPUs drive to
1471 * the same IRQ controller (I know, I've tried it).
1473 * The solution is a variant on the NCR lazy SPL design:
1475 * 1) To disable an interrupt, do nothing (other than set the
1476 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1478 * 2) If the interrupt dares to come in, raise the local mask against
1479 * it (this will result in all the CPU masks being raised
1482 * 3) To enable the interrupt, lower the mask on the local CPU and
1483 * broadcast an Interrupt enable CPI which causes all other CPUs to
1484 * adjust their masks accordingly. */
1486 static void unmask_vic_irq(unsigned int irq
)
1488 /* linux doesn't to processor-irq affinity, so enable on
1489 * all CPUs we know about */
1490 int cpu
= smp_processor_id(), real_cpu
;
1491 __u16 mask
= (1 << irq
);
1492 __u32 processorList
= 0;
1493 unsigned long flags
;
1495 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
1496 irq
, cpu
, cpu_irq_affinity
[cpu
]));
1497 spin_lock_irqsave(&vic_irq_lock
, flags
);
1498 for_each_online_cpu(real_cpu
) {
1499 if (!(voyager_extended_vic_processors
& (1 << real_cpu
)))
1501 if (!(cpu_irq_affinity
[real_cpu
] & mask
)) {
1502 /* irq has no affinity for this CPU, ignore */
1505 if (real_cpu
== cpu
) {
1506 enable_local_vic_irq(irq
);
1507 } else if (vic_irq_mask
[real_cpu
] & mask
) {
1508 vic_irq_enable_mask
[real_cpu
] |= mask
;
1509 processorList
|= (1 << real_cpu
);
1512 spin_unlock_irqrestore(&vic_irq_lock
, flags
);
1514 send_CPI(processorList
, VIC_ENABLE_IRQ_CPI
);
1517 static void mask_vic_irq(unsigned int irq
)
1519 /* lazy disable, do nothing */
1522 static void enable_local_vic_irq(unsigned int irq
)
1524 __u8 cpu
= smp_processor_id();
1525 __u16 mask
= ~(1 << irq
);
1526 __u16 old_mask
= vic_irq_mask
[cpu
];
1528 vic_irq_mask
[cpu
] &= mask
;
1529 if (vic_irq_mask
[cpu
] == old_mask
)
1532 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1536 outb_p(cached_A1(cpu
), 0xA1);
1539 outb_p(cached_21(cpu
), 0x21);
1544 static void disable_local_vic_irq(unsigned int irq
)
1546 __u8 cpu
= smp_processor_id();
1547 __u16 mask
= (1 << irq
);
1548 __u16 old_mask
= vic_irq_mask
[cpu
];
1553 vic_irq_mask
[cpu
] |= mask
;
1554 if (old_mask
== vic_irq_mask
[cpu
])
1557 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1561 outb_p(cached_A1(cpu
), 0xA1);
1564 outb_p(cached_21(cpu
), 0x21);
1569 /* The VIC is level triggered, so the ack can only be issued after the
1570 * interrupt completes. However, we do Voyager lazy interrupt
1571 * handling here: It is an extremely expensive operation to mask an
1572 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1573 * this interrupt actually comes in, then we mask and ack here to push
1574 * the interrupt off to another CPU */
1575 static void before_handle_vic_irq(unsigned int irq
)
1577 irq_desc_t
*desc
= irq_desc
+ irq
;
1578 __u8 cpu
= smp_processor_id();
1580 _raw_spin_lock(&vic_irq_lock
);
1582 vic_intr_count
[cpu
]++;
1584 if (!(cpu_irq_affinity
[cpu
] & (1 << irq
))) {
1585 /* The irq is not in our affinity mask, push it off
1586 * onto another CPU */
1587 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d "
1588 "on cpu %d\n", irq
, cpu
));
1589 disable_local_vic_irq(irq
);
1590 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1591 * actually calling the interrupt routine */
1592 desc
->status
|= IRQ_REPLAY
| IRQ_INPROGRESS
;
1593 } else if (desc
->status
& IRQ_DISABLED
) {
1594 /* Damn, the interrupt actually arrived, do the lazy
1595 * disable thing. The interrupt routine in irq.c will
1596 * not handle a IRQ_DISABLED interrupt, so nothing more
1597 * need be done here */
1598 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1600 disable_local_vic_irq(irq
);
1601 desc
->status
|= IRQ_REPLAY
;
1603 desc
->status
&= ~IRQ_REPLAY
;
1606 _raw_spin_unlock(&vic_irq_lock
);
1609 /* Finish the VIC interrupt: basically mask */
1610 static void after_handle_vic_irq(unsigned int irq
)
1612 irq_desc_t
*desc
= irq_desc
+ irq
;
1614 _raw_spin_lock(&vic_irq_lock
);
1616 unsigned int status
= desc
->status
& ~IRQ_INPROGRESS
;
1617 #ifdef VOYAGER_DEBUG
1621 desc
->status
= status
;
1622 if ((status
& IRQ_DISABLED
))
1623 disable_local_vic_irq(irq
);
1624 #ifdef VOYAGER_DEBUG
1625 /* DEBUG: before we ack, check what's in progress */
1626 isr
= vic_read_isr();
1627 if ((isr
& (1 << irq
) && !(status
& IRQ_REPLAY
)) == 0) {
1629 __u8 cpu
= smp_processor_id();
1631 int mask
; /* Um... initialize me??? --RR */
1633 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1635 for_each_possible_cpu(real_cpu
, mask
) {
1637 outb(VIC_CPU_MASQUERADE_ENABLE
| real_cpu
,
1639 isr
= vic_read_isr();
1640 if (isr
& (1 << irq
)) {
1642 ("VOYAGER SMP: CPU%d ack irq %d\n",
1646 outb(cpu
, VIC_PROCESSOR_ID
);
1649 #endif /* VOYAGER_DEBUG */
1650 /* as soon as we ack, the interrupt is eligible for
1651 * receipt by another CPU so everything must be in
1654 if (status
& IRQ_REPLAY
) {
1655 /* replay is set if we disable the interrupt
1656 * in the before_handle_vic_irq() routine, so
1657 * clear the in progress bit here to allow the
1658 * next CPU to handle this correctly */
1659 desc
->status
&= ~(IRQ_REPLAY
| IRQ_INPROGRESS
);
1661 #ifdef VOYAGER_DEBUG
1662 isr
= vic_read_isr();
1663 if ((isr
& (1 << irq
)) != 0)
1664 printk("VOYAGER SMP: after_handle_vic_irq() after "
1665 "ack irq=%d, isr=0x%x\n", irq
, isr
);
1666 #endif /* VOYAGER_DEBUG */
1668 _raw_spin_unlock(&vic_irq_lock
);
1670 /* All code after this point is out of the main path - the IRQ
1671 * may be intercepted by another CPU if reasserted */
1674 /* Linux processor - interrupt affinity manipulations.
1676 * For each processor, we maintain a 32 bit irq affinity mask.
1677 * Initially it is set to all 1's so every processor accepts every
1678 * interrupt. In this call, we change the processor's affinity mask:
1680 * Change from enable to disable:
1682 * If the interrupt ever comes in to the processor, we will disable it
1683 * and ack it to push it off to another CPU, so just accept the mask here.
1685 * Change from disable to enable:
1687 * change the mask and then do an interrupt enable CPI to re-enable on
1688 * the selected processors */
1690 void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
)
1692 /* Only extended processors handle interrupts */
1693 unsigned long real_mask
;
1694 unsigned long irq_mask
= 1 << irq
;
1697 real_mask
= cpus_addr(mask
)[0] & voyager_extended_vic_processors
;
1699 if (cpus_addr(mask
)[0] == 0)
1700 /* can't have no CPUs to accept the interrupt -- extremely
1701 * bad things will happen */
1705 /* can't change the affinity of the timer IRQ. This
1706 * is due to the constraint in the voyager
1707 * architecture that the CPI also comes in on and IRQ
1708 * line and we have chosen IRQ0 for this. If you
1709 * raise the mask on this interrupt, the processor
1710 * will no-longer be able to accept VIC CPIs */
1714 /* You can only have 32 interrupts in a voyager system
1715 * (and 32 only if you have a secondary microchannel
1719 for_each_online_cpu(cpu
) {
1720 unsigned long cpu_mask
= 1 << cpu
;
1722 if (cpu_mask
& real_mask
) {
1723 /* enable the interrupt for this cpu */
1724 cpu_irq_affinity
[cpu
] |= irq_mask
;
1726 /* disable the interrupt for this cpu */
1727 cpu_irq_affinity
[cpu
] &= ~irq_mask
;
1730 /* this is magic, we now have the correct affinity maps, so
1731 * enable the interrupt. This will send an enable CPI to
1732 * those CPUs who need to enable it in their local masks,
1733 * causing them to correct for the new affinity . If the
1734 * interrupt is currently globally disabled, it will simply be
1735 * disabled again as it comes in (voyager lazy disable). If
1736 * the affinity map is tightened to disable the interrupt on a
1737 * cpu, it will be pushed off when it comes in */
1738 unmask_vic_irq(irq
);
1741 static void ack_vic_irq(unsigned int irq
)
1744 outb(0x62, 0x20); /* Specific EOI to cascade */
1745 outb(0x60 | (irq
& 7), 0xA0);
1747 outb(0x60 | (irq
& 7), 0x20);
1751 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1752 * but are not vectored by it. This means that the 8259 mask must be
1753 * lowered to receive them */
1754 static __init
void vic_enable_cpi(void)
1756 __u8 cpu
= smp_processor_id();
1758 /* just take a copy of the current mask (nop for boot cpu) */
1759 vic_irq_mask
[cpu
] = vic_irq_mask
[boot_cpu_id
];
1761 enable_local_vic_irq(VIC_CPI_LEVEL0
);
1762 enable_local_vic_irq(VIC_CPI_LEVEL1
);
1763 /* for sys int and cmn int */
1764 enable_local_vic_irq(7);
1766 if (is_cpu_quad()) {
1767 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
1768 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
1769 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1770 cpu
, QIC_CPI_ENABLE
));
1773 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1774 cpu
, vic_irq_mask
[cpu
]));
1777 void voyager_smp_dump()
1779 int old_cpu
= smp_processor_id(), cpu
;
1781 /* dump the interrupt masks of each processor */
1782 for_each_online_cpu(cpu
) {
1783 __u16 imr
, isr
, irr
;
1784 unsigned long flags
;
1786 local_irq_save(flags
);
1787 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
1788 imr
= (inb(0xa1) << 8) | inb(0x21);
1790 irr
= inb(0xa0) << 8;
1794 isr
= inb(0xa0) << 8;
1797 outb(old_cpu
, VIC_PROCESSOR_ID
);
1798 local_irq_restore(flags
);
1799 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1800 cpu
, vic_irq_mask
[cpu
], imr
, irr
, isr
);
1802 /* These lines are put in to try to unstick an un ack'd irq */
1805 for (irq
= 0; irq
< 16; irq
++) {
1806 if (isr
& (1 << irq
)) {
1807 printk("\tCPU%d: ack irq %d\n",
1809 local_irq_save(flags
);
1810 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
,
1813 outb(old_cpu
, VIC_PROCESSOR_ID
);
1814 local_irq_restore(flags
);
1822 void smp_voyager_power_off(void *dummy
)
1824 if (smp_processor_id() == boot_cpu_id
)
1825 voyager_power_off();
1827 smp_stop_cpu_function(NULL
);
1830 static void __init
voyager_smp_prepare_cpus(unsigned int max_cpus
)
1832 /* FIXME: ignore max_cpus for now */
1836 static void __cpuinit
voyager_smp_prepare_boot_cpu(void)
1838 init_gdt(smp_processor_id());
1839 switch_to_new_gdt();
1841 cpu_set(smp_processor_id(), cpu_online_map
);
1842 cpu_set(smp_processor_id(), cpu_callout_map
);
1843 cpu_set(smp_processor_id(), cpu_possible_map
);
1844 cpu_set(smp_processor_id(), cpu_present_map
);
1847 static int __cpuinit
voyager_cpu_up(unsigned int cpu
)
1849 /* This only works at boot for x86. See "rewrite" above. */
1850 if (cpu_isset(cpu
, smp_commenced_mask
))
1853 /* In case one didn't come up */
1854 if (!cpu_isset(cpu
, cpu_callin_map
))
1856 /* Unleash the CPU! */
1857 cpu_set(cpu
, smp_commenced_mask
);
1858 while (!cpu_isset(cpu
, cpu_online_map
))
1863 static void __init
voyager_smp_cpus_done(unsigned int max_cpus
)
1868 void __init
smp_setup_processor_id(void)
1870 current_thread_info()->cpu
= hard_smp_processor_id();
1871 x86_write_percpu(cpu_number
, hard_smp_processor_id());
1874 struct smp_ops smp_ops
= {
1875 .smp_prepare_boot_cpu
= voyager_smp_prepare_boot_cpu
,
1876 .smp_prepare_cpus
= voyager_smp_prepare_cpus
,
1877 .cpu_up
= voyager_cpu_up
,
1878 .smp_cpus_done
= voyager_smp_cpus_done
,
1880 .smp_send_stop
= voyager_smp_send_stop
,
1881 .smp_send_reschedule
= voyager_smp_send_reschedule
,
1882 .smp_call_function_mask
= voyager_smp_call_function_mask
,