1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * This file provides all the same external entries as smp.c but uses
8 * the voyager hal to provide the functionality
10 #include <linux/cpu.h>
11 #include <linux/module.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/delay.h>
15 #include <linux/mc146818rtc.h>
16 #include <linux/cache.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/bootmem.h>
21 #include <linux/completion.h>
23 #include <asm/voyager.h>
26 #include <asm/pgalloc.h>
27 #include <asm/tlbflush.h>
28 #include <asm/arch_hooks.h>
29 #include <asm/trampoline.h>
31 /* TLB state -- visible externally, indexed physically */
32 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state
, cpu_tlbstate
) = { &init_mm
, 0 };
34 /* CPU IRQ affinity -- set to all ones initially */
35 static unsigned long cpu_irq_affinity
[NR_CPUS
] __cacheline_aligned
=
36 {[0 ... NR_CPUS
-1] = ~0UL };
38 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
39 * indexed physically */
40 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
41 EXPORT_PER_CPU_SYMBOL(cpu_info
);
43 /* physical ID of the CPU used to boot the system */
44 unsigned char boot_cpu_id
;
46 /* The memory line addresses for the Quad CPIs */
47 struct voyager_qic_cpi
*voyager_quad_cpi_addr
[NR_CPUS
] __cacheline_aligned
;
49 /* The masks for the Extended VIC processors, filled in by cat_init */
50 __u32 voyager_extended_vic_processors
= 0;
52 /* Masks for the extended Quad processors which cannot be VIC booted */
53 __u32 voyager_allowed_boot_processors
= 0;
55 /* The mask for the Quad Processors (both extended and non-extended) */
56 __u32 voyager_quad_processors
= 0;
58 /* Total count of live CPUs, used in process.c to display
59 * the CPU information and in irq.c for the per CPU irq
60 * activity count. Finally exported by i386_ksyms.c */
61 static int voyager_extended_cpus
= 1;
63 /* Used for the invalidate map that's also checked in the spinlock */
64 static volatile unsigned long smp_invalidate_needed
;
66 /* Bitmask of currently online CPUs - used by setup.c for
67 /proc/cpuinfo, visible externally but still physical */
68 cpumask_t cpu_online_map
= CPU_MASK_NONE
;
69 EXPORT_SYMBOL(cpu_online_map
);
71 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
72 * by scheduler but indexed physically */
73 cpumask_t phys_cpu_present_map
= CPU_MASK_NONE
;
75 /* The internal functions */
76 static void send_CPI(__u32 cpuset
, __u8 cpi
);
77 static void ack_CPI(__u8 cpi
);
78 static int ack_QIC_CPI(__u8 cpi
);
79 static void ack_special_QIC_CPI(__u8 cpi
);
80 static void ack_VIC_CPI(__u8 cpi
);
81 static void send_CPI_allbutself(__u8 cpi
);
82 static void mask_vic_irq(unsigned int irq
);
83 static void unmask_vic_irq(unsigned int irq
);
84 static unsigned int startup_vic_irq(unsigned int irq
);
85 static void enable_local_vic_irq(unsigned int irq
);
86 static void disable_local_vic_irq(unsigned int irq
);
87 static void before_handle_vic_irq(unsigned int irq
);
88 static void after_handle_vic_irq(unsigned int irq
);
89 static void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
);
90 static void ack_vic_irq(unsigned int irq
);
91 static void vic_enable_cpi(void);
92 static void do_boot_cpu(__u8 cpuid
);
93 static void do_quad_bootstrap(void);
94 static void initialize_secondary(void);
96 int hard_smp_processor_id(void);
97 int safe_smp_processor_id(void);
99 /* Inline functions */
100 static inline void send_one_QIC_CPI(__u8 cpu
, __u8 cpi
)
102 voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
=
103 (smp_processor_id() << 16) + cpi
;
106 static inline void send_QIC_CPI(__u32 cpuset
, __u8 cpi
)
110 for_each_online_cpu(cpu
) {
111 if (cpuset
& (1 << cpu
)) {
113 if (!cpu_online(cpu
))
114 VDEBUG(("CPU%d sending cpi %d to CPU%d not in "
116 hard_smp_processor_id(), cpi
, cpu
));
118 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
123 static inline void wrapper_smp_local_timer_interrupt(void)
126 smp_local_timer_interrupt();
130 static inline void send_one_CPI(__u8 cpu
, __u8 cpi
)
132 if (voyager_quad_processors
& (1 << cpu
))
133 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
135 send_CPI(1 << cpu
, cpi
);
138 static inline void send_CPI_allbutself(__u8 cpi
)
140 __u8 cpu
= smp_processor_id();
141 __u32 mask
= cpus_addr(cpu_online_map
)[0] & ~(1 << cpu
);
145 static inline int is_cpu_quad(void)
147 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
148 return ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
);
151 static inline int is_cpu_extended(void)
153 __u8 cpu
= hard_smp_processor_id();
155 return (voyager_extended_vic_processors
& (1 << cpu
));
158 static inline int is_cpu_vic_boot(void)
160 __u8 cpu
= hard_smp_processor_id();
162 return (voyager_extended_vic_processors
163 & voyager_allowed_boot_processors
& (1 << cpu
));
166 static inline void ack_CPI(__u8 cpi
)
169 case VIC_CPU_BOOT_CPI
:
170 if (is_cpu_quad() && !is_cpu_vic_boot())
177 /* These are slightly strange. Even on the Quad card,
178 * They are vectored as VIC CPIs */
180 ack_special_QIC_CPI(cpi
);
185 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi
);
190 /* local variables */
192 /* The VIC IRQ descriptors -- these look almost identical to the
193 * 8259 IRQs except that masks and things must be kept per processor
195 static struct irq_chip vic_chip
= {
197 .startup
= startup_vic_irq
,
198 .mask
= mask_vic_irq
,
199 .unmask
= unmask_vic_irq
,
200 .set_affinity
= set_vic_irq_affinity
,
203 /* used to count up as CPUs are brought on line (starts at 0) */
204 static int cpucount
= 0;
206 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
207 static DEFINE_PER_CPU(int, prof_multiplier
) = 1;
208 static DEFINE_PER_CPU(int, prof_old_multiplier
) = 1;
209 static DEFINE_PER_CPU(int, prof_counter
) = 1;
211 /* the map used to check if a CPU has booted */
212 static __u32 cpu_booted_map
;
214 /* the synchronize flag used to hold all secondary CPUs spinning in
215 * a tight loop until the boot sequence is ready for them */
216 static cpumask_t smp_commenced_mask
= CPU_MASK_NONE
;
218 /* This is for the new dynamic CPU boot code */
219 cpumask_t cpu_callin_map
= CPU_MASK_NONE
;
220 cpumask_t cpu_callout_map
= CPU_MASK_NONE
;
221 cpumask_t cpu_possible_map
= CPU_MASK_NONE
;
222 EXPORT_SYMBOL(cpu_possible_map
);
224 /* The per processor IRQ masks (these are usually kept in sync) */
225 static __u16 vic_irq_mask
[NR_CPUS
] __cacheline_aligned
;
227 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
228 static __u16 vic_irq_enable_mask
[NR_CPUS
] __cacheline_aligned
= { 0 };
230 /* Lock for enable/disable of VIC interrupts */
231 static __cacheline_aligned
DEFINE_SPINLOCK(vic_irq_lock
);
233 /* The boot processor is correctly set up in PC mode when it
234 * comes up, but the secondaries need their master/slave 8259
235 * pairs initializing correctly */
237 /* Interrupt counters (per cpu) and total - used to try to
238 * even up the interrupt handling routines */
239 static long vic_intr_total
= 0;
240 static long vic_intr_count
[NR_CPUS
] __cacheline_aligned
= { 0 };
241 static unsigned long vic_tick
[NR_CPUS
] __cacheline_aligned
= { 0 };
243 /* Since we can only use CPI0, we fake all the other CPIs */
244 static unsigned long vic_cpi_mailbox
[NR_CPUS
] __cacheline_aligned
;
246 /* debugging routine to read the isr of the cpu's pic */
247 static inline __u16
vic_read_isr(void)
252 isr
= inb(0xa0) << 8;
259 static __init
void qic_setup(void)
261 if (!is_cpu_quad()) {
262 /* not a quad, no setup */
265 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
266 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
268 if (is_cpu_extended()) {
269 /* the QIC duplicate of the VIC base register */
270 outb(VIC_DEFAULT_CPI_BASE
, QIC_VIC_CPI_BASE_REGISTER
);
271 outb(QIC_DEFAULT_CPI_BASE
, QIC_CPI_BASE_REGISTER
);
273 /* FIXME: should set up the QIC timer and memory parity
274 * error vectors here */
278 static __init
void vic_setup_pic(void)
280 outb(1, VIC_REDIRECT_REGISTER_1
);
281 /* clear the claim registers for dynamic routing */
282 outb(0, VIC_CLAIM_REGISTER_0
);
283 outb(0, VIC_CLAIM_REGISTER_1
);
285 outb(0, VIC_PRIORITY_REGISTER
);
286 /* Set the Primary and Secondary Microchannel vector
287 * bases to be the same as the ordinary interrupts
289 * FIXME: This would be more efficient using separate
291 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
292 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
293 /* Now initiallise the master PIC belonging to this CPU by
294 * sending the four ICWs */
296 /* ICW1: level triggered, ICW4 needed */
299 /* ICW2: vector base */
300 outb(FIRST_EXTERNAL_VECTOR
, 0x21);
302 /* ICW3: slave at line 2 */
305 /* ICW4: 8086 mode */
308 /* now the same for the slave PIC */
310 /* ICW1: level trigger, ICW4 needed */
313 /* ICW2: slave vector base */
314 outb(FIRST_EXTERNAL_VECTOR
+ 8, 0xA1);
319 /* ICW4: 8086 mode */
323 static void do_quad_bootstrap(void)
325 if (is_cpu_quad() && is_cpu_vic_boot()) {
328 __u8 cpuid
= hard_smp_processor_id();
330 local_irq_save(flags
);
332 for (i
= 0; i
< 4; i
++) {
333 /* FIXME: this would be >>3 &0x7 on the 32 way */
334 if (((cpuid
>> 2) & 0x03) == i
)
335 /* don't lower our own mask! */
338 /* masquerade as local Quad CPU */
339 outb(QIC_CPUID_ENABLE
| i
, QIC_PROCESSOR_ID
);
340 /* enable the startup CPI */
341 outb(QIC_BOOT_CPI_MASK
, QIC_MASK_REGISTER1
);
343 outb(0, QIC_PROCESSOR_ID
);
345 local_irq_restore(flags
);
349 void prefill_possible_map(void)
351 /* This is empty on voyager because we need a much
352 * earlier detection which is done in find_smp_config */
355 /* Set up all the basic stuff: read the SMP config and make all the
356 * SMP information reflect only the boot cpu. All others will be
357 * brought on-line later. */
358 void __init
find_smp_config(void)
362 boot_cpu_id
= hard_smp_processor_id();
364 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id
);
366 /* initialize the CPU structures (moved from smp_boot_cpus) */
367 for (i
= 0; i
< NR_CPUS
; i
++) {
368 cpu_irq_affinity
[i
] = ~0;
370 cpu_online_map
= cpumask_of_cpu(boot_cpu_id
);
372 /* The boot CPU must be extended */
373 voyager_extended_vic_processors
= 1 << boot_cpu_id
;
374 /* initially, all of the first 8 CPUs can boot */
375 voyager_allowed_boot_processors
= 0xff;
376 /* set up everything for just this CPU, we can alter
377 * this as we start the other CPUs later */
378 /* now get the CPU disposition from the extended CMOS */
379 cpus_addr(phys_cpu_present_map
)[0] =
380 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
);
381 cpus_addr(phys_cpu_present_map
)[0] |=
382 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+ 1) << 8;
383 cpus_addr(phys_cpu_present_map
)[0] |=
384 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+
386 cpus_addr(phys_cpu_present_map
)[0] |=
387 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+
389 cpu_possible_map
= phys_cpu_present_map
;
390 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n",
391 cpus_addr(phys_cpu_present_map
)[0]);
392 /* Here we set up the VIC to enable SMP */
393 /* enable the CPIs by writing the base vector to their register */
394 outb(VIC_DEFAULT_CPI_BASE
, VIC_CPI_BASE_REGISTER
);
395 outb(1, VIC_REDIRECT_REGISTER_1
);
396 /* set the claim registers for static routing --- Boot CPU gets
397 * all interrupts untill all other CPUs started */
398 outb(0xff, VIC_CLAIM_REGISTER_0
);
399 outb(0xff, VIC_CLAIM_REGISTER_1
);
400 /* Set the Primary and Secondary Microchannel vector
401 * bases to be the same as the ordinary interrupts
403 * FIXME: This would be more efficient using separate
405 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
406 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
408 /* Finally tell the firmware that we're driving */
409 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT
) | VOYAGER_IN_CONTROL_FLAG
,
410 VOYAGER_SUS_IN_CONTROL_PORT
);
412 current_thread_info()->cpu
= boot_cpu_id
;
413 x86_write_percpu(cpu_number
, boot_cpu_id
);
417 * The bootstrap kernel entry code has set these up. Save them
418 * for a given CPU, id is physical */
419 void __init
smp_store_cpu_info(int id
)
421 struct cpuinfo_x86
*c
= &cpu_data(id
);
426 identify_secondary_cpu(c
);
429 /* Routine initially called when a non-boot CPU is brought online */
430 static void __init
start_secondary(void *unused
)
432 __u8 cpuid
= hard_smp_processor_id();
436 /* OK, we're in the routine */
437 ack_CPI(VIC_CPU_BOOT_CPI
);
439 /* setup the 8259 master slave pair belonging to this CPU ---
440 * we won't actually receive any until the boot CPU
441 * relinquishes it's static routing mask */
446 if (is_cpu_quad() && !is_cpu_vic_boot()) {
447 /* clear the boot CPI */
451 voyager_quad_cpi_addr
[cpuid
]->qic_cpi
[VIC_CPU_BOOT_CPI
].cpi
;
452 printk("read dummy %d\n", dummy
);
455 /* lower the mask to receive CPIs */
458 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid
, &cpuid
));
460 notify_cpu_starting(cpuid
);
462 /* enable interrupts */
465 /* get our bogomips */
468 /* save our processor parameters */
469 smp_store_cpu_info(cpuid
);
471 /* if we're a quad, we may need to bootstrap other CPUs */
474 /* FIXME: this is rather a poor hack to prevent the CPU
475 * activating softirqs while it's supposed to be waiting for
476 * permission to proceed. Without this, the new per CPU stuff
477 * in the softirqs will fail */
479 cpu_set(cpuid
, cpu_callin_map
);
481 /* signal that we're done */
484 while (!cpu_isset(cpuid
, smp_commenced_mask
))
490 cpu_set(cpuid
, cpu_online_map
);
495 /* Routine to kick start the given CPU and wait for it to report ready
496 * (or timeout in startup). When this routine returns, the requested
497 * CPU is either fully running and configured or known to be dead.
499 * We call this routine sequentially 1 CPU at a time, so no need for
502 static void __init
do_boot_cpu(__u8 cpu
)
504 struct task_struct
*idle
;
507 int quad_boot
= (1 << cpu
) & voyager_quad_processors
508 & ~(voyager_extended_vic_processors
509 & voyager_allowed_boot_processors
);
511 /* This is the format of the CPI IDT gate (in real mode) which
512 * we're hijacking to boot the CPU */
521 __u32
*hijack_vector
;
522 __u32 start_phys_address
= setup_trampoline();
524 /* There's a clever trick to this: The linux trampoline is
525 * compiled to begin at absolute location zero, so make the
526 * address zero but have the data segment selector compensate
527 * for the actual address */
528 hijack_source
.idt
.Offset
= start_phys_address
& 0x000F;
529 hijack_source
.idt
.Segment
= (start_phys_address
>> 4) & 0xFFFF;
532 alternatives_smp_switch(1);
534 idle
= fork_idle(cpu
);
536 panic("failed fork for CPU%d", cpu
);
537 idle
->thread
.ip
= (unsigned long)start_secondary
;
538 /* init_tasks (in sched.c) is indexed logically */
539 stack_start
.sp
= (void *)idle
->thread
.sp
;
542 per_cpu(current_task
, cpu
) = idle
;
543 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
546 /* Note: Don't modify initial ss override */
547 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu
,
548 (unsigned long)hijack_source
.val
, hijack_source
.idt
.Segment
,
549 hijack_source
.idt
.Offset
, stack_start
.sp
));
551 /* init lowmem identity mapping */
552 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ KERNEL_PGD_BOUNDARY
,
553 min_t(unsigned long, KERNEL_PGD_PTRS
, KERNEL_PGD_BOUNDARY
));
557 printk("CPU %d: non extended Quad boot\n", cpu
);
560 phys_to_virt((VIC_CPU_BOOT_CPI
+ QIC_DEFAULT_CPI_BASE
) * 4);
561 *hijack_vector
= hijack_source
.val
;
563 printk("CPU%d: extended VIC boot\n", cpu
);
566 phys_to_virt((VIC_CPU_BOOT_CPI
+ VIC_DEFAULT_CPI_BASE
) * 4);
567 *hijack_vector
= hijack_source
.val
;
568 /* VIC errata, may also receive interrupt at this address */
571 phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI
+
572 VIC_DEFAULT_CPI_BASE
) * 4);
573 *hijack_vector
= hijack_source
.val
;
575 /* All non-boot CPUs start with interrupts fully masked. Need
576 * to lower the mask of the CPI we're about to send. We do
577 * this in the VIC by masquerading as the processor we're
578 * about to boot and lowering its interrupt mask */
579 local_irq_save(flags
);
581 send_one_QIC_CPI(cpu
, VIC_CPU_BOOT_CPI
);
583 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
584 /* here we're altering registers belonging to `cpu' */
586 outb(VIC_BOOT_INTERRUPT_MASK
, 0x21);
587 /* now go back to our original identity */
588 outb(boot_cpu_id
, VIC_PROCESSOR_ID
);
590 /* and boot the CPU */
592 send_CPI((1 << cpu
), VIC_CPU_BOOT_CPI
);
595 local_irq_restore(flags
);
597 /* now wait for it to become ready (or timeout) */
598 for (timeout
= 0; timeout
< 50000; timeout
++) {
603 /* reset the page table */
606 if (cpu_booted_map
) {
607 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
608 cpu
, smp_processor_id()));
610 printk("CPU%d: ", cpu
);
611 print_cpu_info(&cpu_data(cpu
));
613 cpu_set(cpu
, cpu_callout_map
);
614 cpu_set(cpu
, cpu_present_map
);
616 printk("CPU%d FAILED TO BOOT: ", cpu
);
618 ((volatile unsigned char *)phys_to_virt(start_phys_address
))
622 printk("Not responding.\n");
628 void __init
smp_boot_cpus(void)
632 /* CAT BUS initialisation must be done after the memory */
633 /* FIXME: The L4 has a catbus too, it just needs to be
634 * accessed in a totally different way */
635 if (voyager_level
== 5) {
638 /* now that the cat has probed the Voyager System Bus, sanity
639 * check the cpu map */
640 if (((voyager_quad_processors
| voyager_extended_vic_processors
)
641 & cpus_addr(phys_cpu_present_map
)[0]) !=
642 cpus_addr(phys_cpu_present_map
)[0]) {
644 printk("\n\n***WARNING*** "
645 "Sanity check of CPU present map FAILED\n");
647 } else if (voyager_level
== 4)
648 voyager_extended_vic_processors
=
649 cpus_addr(phys_cpu_present_map
)[0];
651 /* this sets up the idle task to run on the current cpu */
652 voyager_extended_cpus
= 1;
653 /* Remove the global_irq_holder setting, it triggers a BUG() on
654 * schedule at the moment */
655 //global_irq_holder = boot_cpu_id;
657 /* FIXME: Need to do something about this but currently only works
658 * on CPUs with a tsc which none of mine have.
659 smp_tune_scheduling();
661 smp_store_cpu_info(boot_cpu_id
);
662 /* setup the jump vector */
663 initial_code
= (unsigned long)initialize_secondary
;
664 printk("CPU%d: ", boot_cpu_id
);
665 print_cpu_info(&cpu_data(boot_cpu_id
));
668 /* booting on a Quad CPU */
669 printk("VOYAGER SMP: Boot CPU is Quad\n");
674 /* enable our own CPIs */
677 cpu_set(boot_cpu_id
, cpu_online_map
);
678 cpu_set(boot_cpu_id
, cpu_callout_map
);
680 /* loop over all the extended VIC CPUs and boot them. The
681 * Quad CPUs must be bootstrapped by their extended VIC cpu */
682 for (i
= 0; i
< NR_CPUS
; i
++) {
683 if (i
== boot_cpu_id
|| !cpu_isset(i
, phys_cpu_present_map
))
686 /* This udelay seems to be needed for the Quad boots
687 * don't remove unless you know what you're doing */
690 /* we could compute the total bogomips here, but why bother?,
691 * Code added from smpboot.c */
693 unsigned long bogosum
= 0;
695 for_each_online_cpu(i
)
696 bogosum
+= cpu_data(i
).loops_per_jiffy
;
697 printk(KERN_INFO
"Total of %d processors activated "
698 "(%lu.%02lu BogoMIPS).\n",
699 cpucount
+ 1, bogosum
/ (500000 / HZ
),
700 (bogosum
/ (5000 / HZ
)) % 100);
702 voyager_extended_cpus
= hweight32(voyager_extended_vic_processors
);
703 printk("VOYAGER: Extended (interrupt handling CPUs): "
704 "%d, non-extended: %d\n", voyager_extended_cpus
,
705 num_booting_cpus() - voyager_extended_cpus
);
706 /* that's it, switch to symmetric mode */
707 outb(0, VIC_PRIORITY_REGISTER
);
708 outb(0, VIC_CLAIM_REGISTER_0
);
709 outb(0, VIC_CLAIM_REGISTER_1
);
711 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
714 /* Reload the secondary CPUs task structure (this function does not
716 static void __init
initialize_secondary(void)
720 set_current(hard_get_current());
724 * We don't actually need to load the full TSS,
725 * basically just the stack pointer and the eip.
728 asm volatile ("movl %0,%%esp\n\t"
729 "jmp *%1"::"r" (current
->thread
.sp
),
730 "r"(current
->thread
.ip
));
733 /* handle a Voyager SYS_INT -- If we don't, the base board will
736 * System interrupts occur because some problem was detected on the
737 * various busses. To find out what you have to probe all the
738 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
739 void smp_vic_sys_interrupt(struct pt_regs
*regs
)
741 ack_CPI(VIC_SYS_INT
);
742 printk("Voyager SYSTEM INTERRUPT\n");
745 /* Handle a voyager CMN_INT; These interrupts occur either because of
746 * a system status change or because a single bit memory error
747 * occurred. FIXME: At the moment, ignore all this. */
748 void smp_vic_cmn_interrupt(struct pt_regs
*regs
)
750 static __u8 in_cmn_int
= 0;
751 static DEFINE_SPINLOCK(cmn_int_lock
);
753 /* common ints are broadcast, so make sure we only do this once */
754 _raw_spin_lock(&cmn_int_lock
);
759 _raw_spin_unlock(&cmn_int_lock
);
761 VDEBUG(("Voyager COMMON INTERRUPT\n"));
763 if (voyager_level
== 5)
764 voyager_cat_do_common_interrupt();
766 _raw_spin_lock(&cmn_int_lock
);
769 _raw_spin_unlock(&cmn_int_lock
);
770 ack_CPI(VIC_CMN_INT
);
774 * Reschedule call back. Nothing to do, all the work is done
775 * automatically when we return from the interrupt. */
776 static void smp_reschedule_interrupt(void)
781 static struct mm_struct
*flush_mm
;
782 static unsigned long flush_va
;
783 static DEFINE_SPINLOCK(tlbstate_lock
);
786 * We cannot call mmdrop() because we are in interrupt context,
787 * instead update mm->cpu_vm_mask.
789 * We need to reload %cr3 since the page tables may be going
790 * away from under us..
792 static inline void voyager_leave_mm(unsigned long cpu
)
794 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
)
796 cpu_clear(cpu
, per_cpu(cpu_tlbstate
, cpu
).active_mm
->cpu_vm_mask
);
797 load_cr3(swapper_pg_dir
);
801 * Invalidate call-back
803 static void smp_invalidate_interrupt(void)
805 __u8 cpu
= smp_processor_id();
807 if (!test_bit(cpu
, &smp_invalidate_needed
))
809 /* This will flood messages. Don't uncomment unless you see
810 * Problems with cross cpu invalidation
811 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
812 smp_processor_id()));
815 if (flush_mm
== per_cpu(cpu_tlbstate
, cpu
).active_mm
) {
816 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
) {
817 if (flush_va
== TLB_FLUSH_ALL
)
820 __flush_tlb_one(flush_va
);
822 voyager_leave_mm(cpu
);
824 smp_mb__before_clear_bit();
825 clear_bit(cpu
, &smp_invalidate_needed
);
826 smp_mb__after_clear_bit();
829 /* All the new flush operations for 2.4 */
831 /* This routine is called with a physical cpu mask */
833 voyager_flush_tlb_others(unsigned long cpumask
, struct mm_struct
*mm
,
840 if ((cpumask
& cpus_addr(cpu_online_map
)[0]) != cpumask
)
842 if (cpumask
& (1 << smp_processor_id()))
847 spin_lock(&tlbstate_lock
);
851 atomic_set_mask(cpumask
, &smp_invalidate_needed
);
853 * We have to send the CPI only to
856 send_CPI(cpumask
, VIC_INVALIDATE_CPI
);
858 while (smp_invalidate_needed
) {
861 printk("***WARNING*** Stuck doing invalidate CPI "
862 "(CPU%d)\n", smp_processor_id());
867 /* Uncomment only to debug invalidation problems
868 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
873 spin_unlock(&tlbstate_lock
);
876 void flush_tlb_current_task(void)
878 struct mm_struct
*mm
= current
->mm
;
879 unsigned long cpu_mask
;
883 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
886 voyager_flush_tlb_others(cpu_mask
, mm
, TLB_FLUSH_ALL
);
891 void flush_tlb_mm(struct mm_struct
*mm
)
893 unsigned long cpu_mask
;
897 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
899 if (current
->active_mm
== mm
) {
903 voyager_leave_mm(smp_processor_id());
906 voyager_flush_tlb_others(cpu_mask
, mm
, TLB_FLUSH_ALL
);
911 void flush_tlb_page(struct vm_area_struct
*vma
, unsigned long va
)
913 struct mm_struct
*mm
= vma
->vm_mm
;
914 unsigned long cpu_mask
;
918 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
919 if (current
->active_mm
== mm
) {
923 voyager_leave_mm(smp_processor_id());
927 voyager_flush_tlb_others(cpu_mask
, mm
, va
);
932 EXPORT_SYMBOL(flush_tlb_page
);
934 /* enable the requested IRQs */
935 static void smp_enable_irq_interrupt(void)
938 __u8 cpu
= get_cpu();
940 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu
,
941 vic_irq_enable_mask
[cpu
]));
943 spin_lock(&vic_irq_lock
);
944 for (irq
= 0; irq
< 16; irq
++) {
945 if (vic_irq_enable_mask
[cpu
] & (1 << irq
))
946 enable_local_vic_irq(irq
);
948 vic_irq_enable_mask
[cpu
] = 0;
949 spin_unlock(&vic_irq_lock
);
951 put_cpu_no_resched();
957 static void smp_stop_cpu_function(void *dummy
)
959 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
960 cpu_clear(smp_processor_id(), cpu_online_map
);
966 /* execute a thread on a new CPU. The function to be called must be
967 * previously set up. This is used to schedule a function for
968 * execution on all CPUs - set up the function then broadcast a
969 * function_interrupt CPI to come here on each CPU */
970 static void smp_call_function_interrupt(void)
973 generic_smp_call_function_interrupt();
974 __get_cpu_var(irq_stat
).irq_call_count
++;
978 static void smp_call_function_single_interrupt(void)
981 generic_smp_call_function_single_interrupt();
982 __get_cpu_var(irq_stat
).irq_call_count
++;
986 /* Sorry about the name. In an APIC based system, the APICs
987 * themselves are programmed to send a timer interrupt. This is used
988 * by linux to reschedule the processor. Voyager doesn't have this,
989 * so we use the system clock to interrupt one processor, which in
990 * turn, broadcasts a timer CPI to all the others --- we receive that
991 * CPI here. We don't use this actually for counting so losing
992 * ticks doesn't matter
994 * FIXME: For those CPUs which actually have a local APIC, we could
995 * try to use it to trigger this interrupt instead of having to
996 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
997 * no local APIC, so I can't do this
999 * This function is currently a placeholder and is unused in the code */
1000 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1002 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1003 wrapper_smp_local_timer_interrupt();
1004 set_irq_regs(old_regs
);
1007 /* All of the QUAD interrupt GATES */
1008 void smp_qic_timer_interrupt(struct pt_regs
*regs
)
1010 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1011 ack_QIC_CPI(QIC_TIMER_CPI
);
1012 wrapper_smp_local_timer_interrupt();
1013 set_irq_regs(old_regs
);
1016 void smp_qic_invalidate_interrupt(struct pt_regs
*regs
)
1018 ack_QIC_CPI(QIC_INVALIDATE_CPI
);
1019 smp_invalidate_interrupt();
1022 void smp_qic_reschedule_interrupt(struct pt_regs
*regs
)
1024 ack_QIC_CPI(QIC_RESCHEDULE_CPI
);
1025 smp_reschedule_interrupt();
1028 void smp_qic_enable_irq_interrupt(struct pt_regs
*regs
)
1030 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI
);
1031 smp_enable_irq_interrupt();
1034 void smp_qic_call_function_interrupt(struct pt_regs
*regs
)
1036 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI
);
1037 smp_call_function_interrupt();
1040 void smp_qic_call_function_single_interrupt(struct pt_regs
*regs
)
1042 ack_QIC_CPI(QIC_CALL_FUNCTION_SINGLE_CPI
);
1043 smp_call_function_single_interrupt();
1046 void smp_vic_cpi_interrupt(struct pt_regs
*regs
)
1048 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1049 __u8 cpu
= smp_processor_id();
1052 ack_QIC_CPI(VIC_CPI_LEVEL0
);
1054 ack_VIC_CPI(VIC_CPI_LEVEL0
);
1056 if (test_and_clear_bit(VIC_TIMER_CPI
, &vic_cpi_mailbox
[cpu
]))
1057 wrapper_smp_local_timer_interrupt();
1058 if (test_and_clear_bit(VIC_INVALIDATE_CPI
, &vic_cpi_mailbox
[cpu
]))
1059 smp_invalidate_interrupt();
1060 if (test_and_clear_bit(VIC_RESCHEDULE_CPI
, &vic_cpi_mailbox
[cpu
]))
1061 smp_reschedule_interrupt();
1062 if (test_and_clear_bit(VIC_ENABLE_IRQ_CPI
, &vic_cpi_mailbox
[cpu
]))
1063 smp_enable_irq_interrupt();
1064 if (test_and_clear_bit(VIC_CALL_FUNCTION_CPI
, &vic_cpi_mailbox
[cpu
]))
1065 smp_call_function_interrupt();
1066 if (test_and_clear_bit(VIC_CALL_FUNCTION_SINGLE_CPI
, &vic_cpi_mailbox
[cpu
]))
1067 smp_call_function_single_interrupt();
1068 set_irq_regs(old_regs
);
1071 static void do_flush_tlb_all(void *info
)
1073 unsigned long cpu
= smp_processor_id();
1076 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_LAZY
)
1077 voyager_leave_mm(cpu
);
1080 /* flush the TLB of every active CPU in the system */
1081 void flush_tlb_all(void)
1083 on_each_cpu(do_flush_tlb_all
, 0, 1);
1086 /* send a reschedule CPI to one CPU by physical CPU number*/
1087 static void voyager_smp_send_reschedule(int cpu
)
1089 send_one_CPI(cpu
, VIC_RESCHEDULE_CPI
);
1092 int hard_smp_processor_id(void)
1095 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
1096 if ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
)
1097 return cpumask
& 0x1F;
1099 for (i
= 0; i
< 8; i
++) {
1100 if (cpumask
& (1 << i
))
1103 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask
);
1107 int safe_smp_processor_id(void)
1109 return hard_smp_processor_id();
1112 /* broadcast a halt to all other CPUs */
1113 static void voyager_smp_send_stop(void)
1115 smp_call_function(smp_stop_cpu_function
, NULL
, 1);
1118 /* this function is triggered in time.c when a clock tick fires
1119 * we need to re-broadcast the tick to all CPUs */
1120 void smp_vic_timer_interrupt(void)
1122 send_CPI_allbutself(VIC_TIMER_CPI
);
1123 smp_local_timer_interrupt();
1126 /* local (per CPU) timer interrupt. It does both profiling and
1127 * process statistics/rescheduling.
1129 * We do profiling in every local tick, statistics/rescheduling
1130 * happen only every 'profiling multiplier' ticks. The default
1131 * multiplier is 1 and it can be changed by writing the new multiplier
1132 * value into /proc/profile.
1134 void smp_local_timer_interrupt(void)
1136 int cpu
= smp_processor_id();
1139 profile_tick(CPU_PROFILING
);
1140 if (--per_cpu(prof_counter
, cpu
) <= 0) {
1142 * The multiplier may have changed since the last time we got
1143 * to this point as a result of the user writing to
1144 * /proc/profile. In this case we need to adjust the APIC
1145 * timer accordingly.
1147 * Interrupts are already masked off at this point.
1149 per_cpu(prof_counter
, cpu
) = per_cpu(prof_multiplier
, cpu
);
1150 if (per_cpu(prof_counter
, cpu
) !=
1151 per_cpu(prof_old_multiplier
, cpu
)) {
1152 /* FIXME: need to update the vic timer tick here */
1153 per_cpu(prof_old_multiplier
, cpu
) =
1154 per_cpu(prof_counter
, cpu
);
1157 update_process_times(user_mode_vm(get_irq_regs()));
1160 if (((1 << cpu
) & voyager_extended_vic_processors
) == 0)
1161 /* only extended VIC processors participate in
1162 * interrupt distribution */
1166 * We take the 'long' return path, and there every subsystem
1167 * grabs the appropriate locks (kernel lock/ irq lock).
1169 * we might want to decouple profiling from the 'long path',
1170 * and do the profiling totally in assembly.
1172 * Currently this isn't too much of an issue (performance wise),
1173 * we can take more than 100K local irqs per second on a 100 MHz P5.
1176 if ((++vic_tick
[cpu
] & 0x7) != 0)
1178 /* get here every 16 ticks (about every 1/6 of a second) */
1180 /* Change our priority to give someone else a chance at getting
1181 * the IRQ. The algorithm goes like this:
1183 * In the VIC, the dynamically routed interrupt is always
1184 * handled by the lowest priority eligible (i.e. receiving
1185 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1186 * lowest processor number gets it.
1188 * The priority of a CPU is controlled by a special per-CPU
1189 * VIC priority register which is 3 bits wide 0 being lowest
1190 * and 7 highest priority..
1192 * Therefore we subtract the average number of interrupts from
1193 * the number we've fielded. If this number is negative, we
1194 * lower the activity count and if it is positive, we raise
1197 * I'm afraid this still leads to odd looking interrupt counts:
1198 * the totals are all roughly equal, but the individual ones
1199 * look rather skewed.
1201 * FIXME: This algorithm is total crap when mixed with SMP
1202 * affinity code since we now try to even up the interrupt
1203 * counts when an affinity binding is keeping them on a
1205 weight
= (vic_intr_count
[cpu
] * voyager_extended_cpus
1206 - vic_intr_total
) >> 4;
1213 outb((__u8
) weight
, VIC_PRIORITY_REGISTER
);
1215 #ifdef VOYAGER_DEBUG
1216 if ((vic_tick
[cpu
] & 0xFFF) == 0) {
1217 /* print this message roughly every 25 secs */
1218 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1219 cpu
, vic_tick
[cpu
], weight
);
1224 /* setup the profiling timer */
1225 int setup_profiling_timer(unsigned int multiplier
)
1233 * Set the new multiplier for each CPU. CPUs don't start using the
1234 * new values until the next timer interrupt in which they do process
1237 for (i
= 0; i
< NR_CPUS
; ++i
)
1238 per_cpu(prof_multiplier
, i
) = multiplier
;
1243 /* This is a bit of a mess, but forced on us by the genirq changes
1244 * there's no genirq handler that really does what voyager wants
1245 * so hack it up with the simple IRQ handler */
1246 static void handle_vic_irq(unsigned int irq
, struct irq_desc
*desc
)
1248 before_handle_vic_irq(irq
);
1249 handle_simple_irq(irq
, desc
);
1250 after_handle_vic_irq(irq
);
1253 /* The CPIs are handled in the per cpu 8259s, so they must be
1254 * enabled to be received: FIX: enabling the CPIs in the early
1255 * boot sequence interferes with bug checking; enable them later
1257 #define VIC_SET_GATE(cpi, vector) \
1258 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1259 #define QIC_SET_GATE(cpi, vector) \
1260 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1262 void __init
voyager_smp_intr_init(void)
1266 /* initialize the per cpu irq mask to all disabled */
1267 for (i
= 0; i
< NR_CPUS
; i
++)
1268 vic_irq_mask
[i
] = 0xFFFF;
1270 VIC_SET_GATE(VIC_CPI_LEVEL0
, vic_cpi_interrupt
);
1272 VIC_SET_GATE(VIC_SYS_INT
, vic_sys_interrupt
);
1273 VIC_SET_GATE(VIC_CMN_INT
, vic_cmn_interrupt
);
1275 QIC_SET_GATE(QIC_TIMER_CPI
, qic_timer_interrupt
);
1276 QIC_SET_GATE(QIC_INVALIDATE_CPI
, qic_invalidate_interrupt
);
1277 QIC_SET_GATE(QIC_RESCHEDULE_CPI
, qic_reschedule_interrupt
);
1278 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI
, qic_enable_irq_interrupt
);
1279 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI
, qic_call_function_interrupt
);
1281 /* now put the VIC descriptor into the first 48 IRQs
1283 * This is for later: first 16 correspond to PC IRQs; next 16
1284 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1285 for (i
= 0; i
< 48; i
++)
1286 set_irq_chip_and_handler(i
, &vic_chip
, handle_vic_irq
);
1289 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1290 * processor to receive CPI */
1291 static void send_CPI(__u32 cpuset
, __u8 cpi
)
1294 __u32 quad_cpuset
= (cpuset
& voyager_quad_processors
);
1296 if (cpi
< VIC_START_FAKE_CPI
) {
1297 /* fake CPI are only used for booting, so send to the
1298 * extended quads as well---Quads must be VIC booted */
1299 outb((__u8
) (cpuset
), VIC_CPI_Registers
[cpi
]);
1303 send_QIC_CPI(quad_cpuset
, cpi
);
1304 cpuset
&= ~quad_cpuset
;
1305 cpuset
&= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1308 for_each_online_cpu(cpu
) {
1309 if (cpuset
& (1 << cpu
))
1310 set_bit(cpi
, &vic_cpi_mailbox
[cpu
]);
1313 outb((__u8
) cpuset
, VIC_CPI_Registers
[VIC_CPI_LEVEL0
]);
1316 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1317 * set the cache line to shared by reading it.
1319 * DON'T make this inline otherwise the cache line read will be
1322 static int ack_QIC_CPI(__u8 cpi
)
1324 __u8 cpu
= hard_smp_processor_id();
1328 outb(1 << cpi
, QIC_INTERRUPT_CLEAR1
);
1329 return voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
;
1332 static void ack_special_QIC_CPI(__u8 cpi
)
1336 outb(QIC_CMN_INT
, QIC_INTERRUPT_CLEAR0
);
1339 outb(QIC_SYS_INT
, QIC_INTERRUPT_CLEAR0
);
1342 /* also clear at the VIC, just in case (nop for non-extended proc) */
1346 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1347 static void ack_VIC_CPI(__u8 cpi
)
1349 #ifdef VOYAGER_DEBUG
1350 unsigned long flags
;
1352 __u8 cpu
= smp_processor_id();
1354 local_irq_save(flags
);
1355 isr
= vic_read_isr();
1356 if ((isr
& (1 << (cpi
& 7))) == 0) {
1357 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu
, cpi
);
1360 /* send specific EOI; the two system interrupts have
1361 * bit 4 set for a separate vector but behave as the
1362 * corresponding 3 bit intr */
1363 outb_p(0x60 | (cpi
& 7), 0x20);
1365 #ifdef VOYAGER_DEBUG
1366 if ((vic_read_isr() & (1 << (cpi
& 7))) != 0) {
1367 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu
, cpi
);
1369 local_irq_restore(flags
);
1373 /* cribbed with thanks from irq.c */
1374 #define __byte(x,y) (((unsigned char *)&(y))[x])
1375 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1376 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1378 static unsigned int startup_vic_irq(unsigned int irq
)
1380 unmask_vic_irq(irq
);
1385 /* The enable and disable routines. This is where we run into
1386 * conflicting architectural philosophy. Fundamentally, the voyager
1387 * architecture does not expect to have to disable interrupts globally
1388 * (the IRQ controllers belong to each CPU). The processor masquerade
1389 * which is used to start the system shouldn't be used in a running OS
1390 * since it will cause great confusion if two separate CPUs drive to
1391 * the same IRQ controller (I know, I've tried it).
1393 * The solution is a variant on the NCR lazy SPL design:
1395 * 1) To disable an interrupt, do nothing (other than set the
1396 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1398 * 2) If the interrupt dares to come in, raise the local mask against
1399 * it (this will result in all the CPU masks being raised
1402 * 3) To enable the interrupt, lower the mask on the local CPU and
1403 * broadcast an Interrupt enable CPI which causes all other CPUs to
1404 * adjust their masks accordingly. */
1406 static void unmask_vic_irq(unsigned int irq
)
1408 /* linux doesn't to processor-irq affinity, so enable on
1409 * all CPUs we know about */
1410 int cpu
= smp_processor_id(), real_cpu
;
1411 __u16 mask
= (1 << irq
);
1412 __u32 processorList
= 0;
1413 unsigned long flags
;
1415 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
1416 irq
, cpu
, cpu_irq_affinity
[cpu
]));
1417 spin_lock_irqsave(&vic_irq_lock
, flags
);
1418 for_each_online_cpu(real_cpu
) {
1419 if (!(voyager_extended_vic_processors
& (1 << real_cpu
)))
1421 if (!(cpu_irq_affinity
[real_cpu
] & mask
)) {
1422 /* irq has no affinity for this CPU, ignore */
1425 if (real_cpu
== cpu
) {
1426 enable_local_vic_irq(irq
);
1427 } else if (vic_irq_mask
[real_cpu
] & mask
) {
1428 vic_irq_enable_mask
[real_cpu
] |= mask
;
1429 processorList
|= (1 << real_cpu
);
1432 spin_unlock_irqrestore(&vic_irq_lock
, flags
);
1434 send_CPI(processorList
, VIC_ENABLE_IRQ_CPI
);
1437 static void mask_vic_irq(unsigned int irq
)
1439 /* lazy disable, do nothing */
1442 static void enable_local_vic_irq(unsigned int irq
)
1444 __u8 cpu
= smp_processor_id();
1445 __u16 mask
= ~(1 << irq
);
1446 __u16 old_mask
= vic_irq_mask
[cpu
];
1448 vic_irq_mask
[cpu
] &= mask
;
1449 if (vic_irq_mask
[cpu
] == old_mask
)
1452 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1456 outb_p(cached_A1(cpu
), 0xA1);
1459 outb_p(cached_21(cpu
), 0x21);
1464 static void disable_local_vic_irq(unsigned int irq
)
1466 __u8 cpu
= smp_processor_id();
1467 __u16 mask
= (1 << irq
);
1468 __u16 old_mask
= vic_irq_mask
[cpu
];
1473 vic_irq_mask
[cpu
] |= mask
;
1474 if (old_mask
== vic_irq_mask
[cpu
])
1477 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1481 outb_p(cached_A1(cpu
), 0xA1);
1484 outb_p(cached_21(cpu
), 0x21);
1489 /* The VIC is level triggered, so the ack can only be issued after the
1490 * interrupt completes. However, we do Voyager lazy interrupt
1491 * handling here: It is an extremely expensive operation to mask an
1492 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1493 * this interrupt actually comes in, then we mask and ack here to push
1494 * the interrupt off to another CPU */
1495 static void before_handle_vic_irq(unsigned int irq
)
1497 irq_desc_t
*desc
= irq_to_desc(irq
);
1498 __u8 cpu
= smp_processor_id();
1500 _raw_spin_lock(&vic_irq_lock
);
1502 vic_intr_count
[cpu
]++;
1504 if (!(cpu_irq_affinity
[cpu
] & (1 << irq
))) {
1505 /* The irq is not in our affinity mask, push it off
1506 * onto another CPU */
1507 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d "
1508 "on cpu %d\n", irq
, cpu
));
1509 disable_local_vic_irq(irq
);
1510 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1511 * actually calling the interrupt routine */
1512 desc
->status
|= IRQ_REPLAY
| IRQ_INPROGRESS
;
1513 } else if (desc
->status
& IRQ_DISABLED
) {
1514 /* Damn, the interrupt actually arrived, do the lazy
1515 * disable thing. The interrupt routine in irq.c will
1516 * not handle a IRQ_DISABLED interrupt, so nothing more
1517 * need be done here */
1518 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1520 disable_local_vic_irq(irq
);
1521 desc
->status
|= IRQ_REPLAY
;
1523 desc
->status
&= ~IRQ_REPLAY
;
1526 _raw_spin_unlock(&vic_irq_lock
);
1529 /* Finish the VIC interrupt: basically mask */
1530 static void after_handle_vic_irq(unsigned int irq
)
1532 irq_desc_t
*desc
= irq_to_desc(irq
);
1534 _raw_spin_lock(&vic_irq_lock
);
1536 unsigned int status
= desc
->status
& ~IRQ_INPROGRESS
;
1537 #ifdef VOYAGER_DEBUG
1541 desc
->status
= status
;
1542 if ((status
& IRQ_DISABLED
))
1543 disable_local_vic_irq(irq
);
1544 #ifdef VOYAGER_DEBUG
1545 /* DEBUG: before we ack, check what's in progress */
1546 isr
= vic_read_isr();
1547 if ((isr
& (1 << irq
) && !(status
& IRQ_REPLAY
)) == 0) {
1549 __u8 cpu
= smp_processor_id();
1551 int mask
; /* Um... initialize me??? --RR */
1553 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1555 for_each_possible_cpu(real_cpu
, mask
) {
1557 outb(VIC_CPU_MASQUERADE_ENABLE
| real_cpu
,
1559 isr
= vic_read_isr();
1560 if (isr
& (1 << irq
)) {
1562 ("VOYAGER SMP: CPU%d ack irq %d\n",
1566 outb(cpu
, VIC_PROCESSOR_ID
);
1569 #endif /* VOYAGER_DEBUG */
1570 /* as soon as we ack, the interrupt is eligible for
1571 * receipt by another CPU so everything must be in
1574 if (status
& IRQ_REPLAY
) {
1575 /* replay is set if we disable the interrupt
1576 * in the before_handle_vic_irq() routine, so
1577 * clear the in progress bit here to allow the
1578 * next CPU to handle this correctly */
1579 desc
->status
&= ~(IRQ_REPLAY
| IRQ_INPROGRESS
);
1581 #ifdef VOYAGER_DEBUG
1582 isr
= vic_read_isr();
1583 if ((isr
& (1 << irq
)) != 0)
1584 printk("VOYAGER SMP: after_handle_vic_irq() after "
1585 "ack irq=%d, isr=0x%x\n", irq
, isr
);
1586 #endif /* VOYAGER_DEBUG */
1588 _raw_spin_unlock(&vic_irq_lock
);
1590 /* All code after this point is out of the main path - the IRQ
1591 * may be intercepted by another CPU if reasserted */
1594 /* Linux processor - interrupt affinity manipulations.
1596 * For each processor, we maintain a 32 bit irq affinity mask.
1597 * Initially it is set to all 1's so every processor accepts every
1598 * interrupt. In this call, we change the processor's affinity mask:
1600 * Change from enable to disable:
1602 * If the interrupt ever comes in to the processor, we will disable it
1603 * and ack it to push it off to another CPU, so just accept the mask here.
1605 * Change from disable to enable:
1607 * change the mask and then do an interrupt enable CPI to re-enable on
1608 * the selected processors */
1610 void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
)
1612 /* Only extended processors handle interrupts */
1613 unsigned long real_mask
;
1614 unsigned long irq_mask
= 1 << irq
;
1617 real_mask
= cpus_addr(mask
)[0] & voyager_extended_vic_processors
;
1619 if (cpus_addr(mask
)[0] == 0)
1620 /* can't have no CPUs to accept the interrupt -- extremely
1621 * bad things will happen */
1625 /* can't change the affinity of the timer IRQ. This
1626 * is due to the constraint in the voyager
1627 * architecture that the CPI also comes in on and IRQ
1628 * line and we have chosen IRQ0 for this. If you
1629 * raise the mask on this interrupt, the processor
1630 * will no-longer be able to accept VIC CPIs */
1634 /* You can only have 32 interrupts in a voyager system
1635 * (and 32 only if you have a secondary microchannel
1639 for_each_online_cpu(cpu
) {
1640 unsigned long cpu_mask
= 1 << cpu
;
1642 if (cpu_mask
& real_mask
) {
1643 /* enable the interrupt for this cpu */
1644 cpu_irq_affinity
[cpu
] |= irq_mask
;
1646 /* disable the interrupt for this cpu */
1647 cpu_irq_affinity
[cpu
] &= ~irq_mask
;
1650 /* this is magic, we now have the correct affinity maps, so
1651 * enable the interrupt. This will send an enable CPI to
1652 * those CPUs who need to enable it in their local masks,
1653 * causing them to correct for the new affinity . If the
1654 * interrupt is currently globally disabled, it will simply be
1655 * disabled again as it comes in (voyager lazy disable). If
1656 * the affinity map is tightened to disable the interrupt on a
1657 * cpu, it will be pushed off when it comes in */
1658 unmask_vic_irq(irq
);
1661 static void ack_vic_irq(unsigned int irq
)
1664 outb(0x62, 0x20); /* Specific EOI to cascade */
1665 outb(0x60 | (irq
& 7), 0xA0);
1667 outb(0x60 | (irq
& 7), 0x20);
1671 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1672 * but are not vectored by it. This means that the 8259 mask must be
1673 * lowered to receive them */
1674 static __init
void vic_enable_cpi(void)
1676 __u8 cpu
= smp_processor_id();
1678 /* just take a copy of the current mask (nop for boot cpu) */
1679 vic_irq_mask
[cpu
] = vic_irq_mask
[boot_cpu_id
];
1681 enable_local_vic_irq(VIC_CPI_LEVEL0
);
1682 enable_local_vic_irq(VIC_CPI_LEVEL1
);
1683 /* for sys int and cmn int */
1684 enable_local_vic_irq(7);
1686 if (is_cpu_quad()) {
1687 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
1688 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
1689 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1690 cpu
, QIC_CPI_ENABLE
));
1693 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1694 cpu
, vic_irq_mask
[cpu
]));
1697 void voyager_smp_dump()
1699 int old_cpu
= smp_processor_id(), cpu
;
1701 /* dump the interrupt masks of each processor */
1702 for_each_online_cpu(cpu
) {
1703 __u16 imr
, isr
, irr
;
1704 unsigned long flags
;
1706 local_irq_save(flags
);
1707 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
1708 imr
= (inb(0xa1) << 8) | inb(0x21);
1710 irr
= inb(0xa0) << 8;
1714 isr
= inb(0xa0) << 8;
1717 outb(old_cpu
, VIC_PROCESSOR_ID
);
1718 local_irq_restore(flags
);
1719 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1720 cpu
, vic_irq_mask
[cpu
], imr
, irr
, isr
);
1722 /* These lines are put in to try to unstick an un ack'd irq */
1725 for (irq
= 0; irq
< 16; irq
++) {
1726 if (isr
& (1 << irq
)) {
1727 printk("\tCPU%d: ack irq %d\n",
1729 local_irq_save(flags
);
1730 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
,
1733 outb(old_cpu
, VIC_PROCESSOR_ID
);
1734 local_irq_restore(flags
);
1742 void smp_voyager_power_off(void *dummy
)
1744 if (smp_processor_id() == boot_cpu_id
)
1745 voyager_power_off();
1747 smp_stop_cpu_function(NULL
);
1750 static void __init
voyager_smp_prepare_cpus(unsigned int max_cpus
)
1752 /* FIXME: ignore max_cpus for now */
1756 static void __cpuinit
voyager_smp_prepare_boot_cpu(void)
1758 init_gdt(smp_processor_id());
1759 switch_to_new_gdt();
1761 cpu_set(smp_processor_id(), cpu_online_map
);
1762 cpu_set(smp_processor_id(), cpu_callout_map
);
1763 cpu_set(smp_processor_id(), cpu_possible_map
);
1764 cpu_set(smp_processor_id(), cpu_present_map
);
1767 static int __cpuinit
voyager_cpu_up(unsigned int cpu
)
1769 /* This only works at boot for x86. See "rewrite" above. */
1770 if (cpu_isset(cpu
, smp_commenced_mask
))
1773 /* In case one didn't come up */
1774 if (!cpu_isset(cpu
, cpu_callin_map
))
1776 /* Unleash the CPU! */
1777 cpu_set(cpu
, smp_commenced_mask
);
1778 while (!cpu_online(cpu
))
1783 static void __init
voyager_smp_cpus_done(unsigned int max_cpus
)
1788 void __init
smp_setup_processor_id(void)
1790 current_thread_info()->cpu
= hard_smp_processor_id();
1791 x86_write_percpu(cpu_number
, hard_smp_processor_id());
1794 static void voyager_send_call_func(cpumask_t callmask
)
1796 __u32 mask
= cpus_addr(callmask
)[0] & ~(1 << smp_processor_id());
1797 send_CPI(mask
, VIC_CALL_FUNCTION_CPI
);
1800 static void voyager_send_call_func_single(int cpu
)
1802 send_CPI(1 << cpu
, VIC_CALL_FUNCTION_SINGLE_CPI
);
1805 struct smp_ops smp_ops
= {
1806 .smp_prepare_boot_cpu
= voyager_smp_prepare_boot_cpu
,
1807 .smp_prepare_cpus
= voyager_smp_prepare_cpus
,
1808 .cpu_up
= voyager_cpu_up
,
1809 .smp_cpus_done
= voyager_smp_cpus_done
,
1811 .smp_send_stop
= voyager_smp_send_stop
,
1812 .smp_send_reschedule
= voyager_smp_send_reschedule
,
1814 .send_call_func_ipi
= voyager_send_call_func
,
1815 .send_call_func_single_ipi
= voyager_send_call_func_single
,