1 #include <linux/init.h>
4 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/module.h>
9 #include <asm/tlbflush.h>
10 #include <asm/mmu_context.h>
12 #include <asm/uv/uv.h>
14 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state
, cpu_tlbstate
)
19 * Smarter SMP flushing macros.
22 * These mean you can really definitely utterly forget about
23 * writing to user space from interrupts. (Its not allowed anyway).
25 * Optimizations Manfred Spraul <manfred@colorfullife.com>
27 * More scalable flush, from Andi Kleen
29 * To avoid global state use 8 different call vectors.
30 * Each CPU uses a specific vector to trigger flushes on other
31 * CPUs. Depending on the received vector the target CPUs look into
32 * the right array slot for the flush data.
34 * With more than 8 CPUs they are hashed to the 8 available
35 * vectors. The limited global vector space forces us to this right now.
36 * In future when interrupts are split into per CPU domains this could be
37 * fixed, at the cost of triggering multiple IPIs in some cases.
40 union smp_flush_state
{
42 struct mm_struct
*flush_mm
;
43 unsigned long flush_va
;
44 spinlock_t tlbstate_lock
;
45 DECLARE_BITMAP(flush_cpumask
, NR_CPUS
);
47 char pad
[CONFIG_X86_INTERNODE_CACHE_BYTES
];
48 } ____cacheline_internodealigned_in_smp
;
50 /* State is put into the per CPU data section, but padded
51 to a full cache line because other CPUs can access it and we don't
52 want false sharing in the per cpu data segment. */
53 static union smp_flush_state flush_state
[NUM_INVALIDATE_TLB_VECTORS
];
56 * We cannot call mmdrop() because we are in interrupt context,
57 * instead update mm->cpu_vm_mask.
59 void leave_mm(int cpu
)
61 if (percpu_read(cpu_tlbstate
.state
) == TLBSTATE_OK
)
63 cpu_clear(cpu
, percpu_read(cpu_tlbstate
.active_mm
)->cpu_vm_mask
);
64 load_cr3(swapper_pg_dir
);
66 EXPORT_SYMBOL_GPL(leave_mm
);
70 * The flush IPI assumes that a thread switch happens in this order:
71 * [cpu0: the cpu that switches]
72 * 1) switch_mm() either 1a) or 1b)
73 * 1a) thread switch to a different mm
74 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
75 * Stop ipi delivery for the old mm. This is not synchronized with
76 * the other cpus, but smp_invalidate_interrupt ignore flush ipis
77 * for the wrong mm, and in the worst case we perform a superfluous
79 * 1a2) set cpu mmu_state to TLBSTATE_OK
80 * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
81 * was in lazy tlb mode.
82 * 1a3) update cpu active_mm
83 * Now cpu0 accepts tlb flushes for the new mm.
84 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
85 * Now the other cpus will send tlb flush ipis.
87 * 1b) thread switch without mm change
88 * cpu active_mm is correct, cpu0 already handles
90 * 1b1) set cpu mmu_state to TLBSTATE_OK
91 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
92 * Atomically set the bit [other cpus will start sending flush ipis],
94 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
95 * 2) switch %%esp, ie current
97 * The interrupt must handle 2 special cases:
98 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
99 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
100 * runs in kernel space, the cpu could load tlb entries for user space
103 * The good news is that cpu mmu_state is local to each cpu, no
104 * write/read ordering problems.
110 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
111 * 2) Leave the mm if we are in the lazy tlb mode.
113 * Interrupts are disabled.
117 * FIXME: use of asmlinkage is not consistent. On x86_64 it's noop
118 * but still used for documentation purpose but the usage is slightly
119 * inconsistent. On x86_32, asmlinkage is regparm(0) but interrupt
120 * entry calls in with the first parameter in %eax. Maybe define
126 void smp_invalidate_interrupt(struct pt_regs
*regs
)
130 union smp_flush_state
*f
;
132 cpu
= smp_processor_id();
134 * orig_rax contains the negated interrupt vector.
135 * Use that to determine where the sender put the data.
137 sender
= ~regs
->orig_ax
- INVALIDATE_TLB_VECTOR_START
;
138 f
= &flush_state
[sender
];
140 if (!cpumask_test_cpu(cpu
, to_cpumask(f
->flush_cpumask
)))
143 * This was a BUG() but until someone can quote me the
144 * line from the intel manual that guarantees an IPI to
145 * multiple CPUs is retried _only_ on the erroring CPUs
146 * its staying as a return
151 if (f
->flush_mm
== percpu_read(cpu_tlbstate
.active_mm
)) {
152 if (percpu_read(cpu_tlbstate
.state
) == TLBSTATE_OK
) {
153 if (f
->flush_va
== TLB_FLUSH_ALL
)
156 __flush_tlb_one(f
->flush_va
);
162 smp_mb__before_clear_bit();
163 cpumask_clear_cpu(cpu
, to_cpumask(f
->flush_cpumask
));
164 smp_mb__after_clear_bit();
165 inc_irq_stat(irq_tlb_count
);
168 static void flush_tlb_others_ipi(const struct cpumask
*cpumask
,
169 struct mm_struct
*mm
, unsigned long va
)
172 union smp_flush_state
*f
;
174 /* Caller has disabled preemption */
175 sender
= smp_processor_id() % NUM_INVALIDATE_TLB_VECTORS
;
176 f
= &flush_state
[sender
];
179 * Could avoid this lock when
180 * num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is
181 * probably not worth checking this for a cache-hot lock.
183 spin_lock(&f
->tlbstate_lock
);
187 cpumask_andnot(to_cpumask(f
->flush_cpumask
),
188 cpumask
, cpumask_of(smp_processor_id()));
191 * Make the above memory operations globally visible before
196 * We have to send the IPI only to
199 apic
->send_IPI_mask(to_cpumask(f
->flush_cpumask
),
200 INVALIDATE_TLB_VECTOR_START
+ sender
);
202 while (!cpumask_empty(to_cpumask(f
->flush_cpumask
)))
207 spin_unlock(&f
->tlbstate_lock
);
210 void native_flush_tlb_others(const struct cpumask
*cpumask
,
211 struct mm_struct
*mm
, unsigned long va
)
213 if (is_uv_system()) {
217 cpumask
= uv_flush_tlb_others(cpumask
, mm
, va
, cpu
);
219 flush_tlb_others_ipi(cpumask
, mm
, va
);
223 flush_tlb_others_ipi(cpumask
, mm
, va
);
226 static int __cpuinit
init_smp_flush(void)
230 for (i
= 0; i
< ARRAY_SIZE(flush_state
); i
++)
231 spin_lock_init(&flush_state
[i
].tlbstate_lock
);
235 core_initcall(init_smp_flush
);
237 void flush_tlb_current_task(void)
239 struct mm_struct
*mm
= current
->mm
;
244 if (cpumask_any_but(&mm
->cpu_vm_mask
, smp_processor_id()) < nr_cpu_ids
)
245 flush_tlb_others(&mm
->cpu_vm_mask
, mm
, TLB_FLUSH_ALL
);
249 void flush_tlb_mm(struct mm_struct
*mm
)
253 if (current
->active_mm
== mm
) {
257 leave_mm(smp_processor_id());
259 if (cpumask_any_but(&mm
->cpu_vm_mask
, smp_processor_id()) < nr_cpu_ids
)
260 flush_tlb_others(&mm
->cpu_vm_mask
, mm
, TLB_FLUSH_ALL
);
265 void flush_tlb_page(struct vm_area_struct
*vma
, unsigned long va
)
267 struct mm_struct
*mm
= vma
->vm_mm
;
271 if (current
->active_mm
== mm
) {
275 leave_mm(smp_processor_id());
278 if (cpumask_any_but(&mm
->cpu_vm_mask
, smp_processor_id()) < nr_cpu_ids
)
279 flush_tlb_others(&mm
->cpu_vm_mask
, mm
, va
);
284 static void do_flush_tlb_all(void *info
)
286 unsigned long cpu
= smp_processor_id();
289 if (percpu_read(cpu_tlbstate
.state
) == TLBSTATE_LAZY
)
293 void flush_tlb_all(void)
295 on_each_cpu(do_flush_tlb_all
, NULL
, 1);