1 #include <linux/init.h>
4 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/export.h>
10 #include <asm/tlbflush.h>
11 #include <asm/mmu_context.h>
12 #include <asm/cache.h>
14 #include <asm/uv/uv.h>
15 #include <linux/debugfs.h>
18 * TLB flushing, formerly SMP-only
21 * These mean you can really definitely utterly forget about
22 * writing to user space from interrupts. (Its not allowed anyway).
24 * Optimizations Manfred Spraul <manfred@colorfullife.com>
26 * More scalable flush, from Andi Kleen
28 * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
32 * We get here when we do something requiring a TLB invalidation
33 * but could not go invalidate all of the contexts. We do the
34 * necessary invalidation by clearing out the 'ctx_id' which
35 * forces a TLB flush when the context is loaded.
37 void clear_asid_other(void)
42 * This is only expected to be set if we have disabled
43 * kernel _PAGE_GLOBAL pages.
45 if (!static_cpu_has(X86_FEATURE_PTI
)) {
50 for (asid
= 0; asid
< TLB_NR_DYN_ASIDS
; asid
++) {
51 /* Do not need to flush the current asid */
52 if (asid
== this_cpu_read(cpu_tlbstate
.loaded_mm_asid
))
55 * Make sure the next time we go to switch to
56 * this asid, we do a flush:
58 this_cpu_write(cpu_tlbstate
.ctxs
[asid
].ctx_id
, 0);
60 this_cpu_write(cpu_tlbstate
.invalidate_other
, false);
63 atomic64_t last_mm_ctx_id
= ATOMIC64_INIT(1);
66 static void choose_new_asid(struct mm_struct
*next
, u64 next_tlb_gen
,
67 u16
*new_asid
, bool *need_flush
)
71 if (!static_cpu_has(X86_FEATURE_PCID
)) {
77 if (this_cpu_read(cpu_tlbstate
.invalidate_other
))
80 for (asid
= 0; asid
< TLB_NR_DYN_ASIDS
; asid
++) {
81 if (this_cpu_read(cpu_tlbstate
.ctxs
[asid
].ctx_id
) !=
86 *need_flush
= (this_cpu_read(cpu_tlbstate
.ctxs
[asid
].tlb_gen
) <
92 * We don't currently own an ASID slot on this CPU.
95 *new_asid
= this_cpu_add_return(cpu_tlbstate
.next_asid
, 1) - 1;
96 if (*new_asid
>= TLB_NR_DYN_ASIDS
) {
98 this_cpu_write(cpu_tlbstate
.next_asid
, 1);
103 static void load_new_mm_cr3(pgd_t
*pgdir
, u16 new_asid
, bool need_flush
)
105 unsigned long new_mm_cr3
;
108 invalidate_user_asid(new_asid
);
109 new_mm_cr3
= build_cr3(pgdir
, new_asid
);
111 new_mm_cr3
= build_cr3_noflush(pgdir
, new_asid
);
115 * Caution: many callers of this function expect
116 * that load_cr3() is serializing and orders TLB
117 * fills with respect to the mm_cpumask writes.
119 write_cr3(new_mm_cr3
);
122 void leave_mm(int cpu
)
124 struct mm_struct
*loaded_mm
= this_cpu_read(cpu_tlbstate
.loaded_mm
);
127 * It's plausible that we're in lazy TLB mode while our mm is init_mm.
128 * If so, our callers still expect us to flush the TLB, but there
129 * aren't any user TLB entries in init_mm to worry about.
131 * This needs to happen before any other sanity checks due to
132 * intel_idle's shenanigans.
134 if (loaded_mm
== &init_mm
)
137 /* Warn if we're not lazy. */
138 WARN_ON(!this_cpu_read(cpu_tlbstate
.is_lazy
));
140 switch_mm(NULL
, &init_mm
, NULL
);
142 EXPORT_SYMBOL_GPL(leave_mm
);
144 void switch_mm(struct mm_struct
*prev
, struct mm_struct
*next
,
145 struct task_struct
*tsk
)
149 local_irq_save(flags
);
150 switch_mm_irqs_off(prev
, next
, tsk
);
151 local_irq_restore(flags
);
154 static void sync_current_stack_to_mm(struct mm_struct
*mm
)
156 unsigned long sp
= current_stack_pointer
;
157 pgd_t
*pgd
= pgd_offset(mm
, sp
);
159 if (CONFIG_PGTABLE_LEVELS
> 4) {
160 if (unlikely(pgd_none(*pgd
))) {
161 pgd_t
*pgd_ref
= pgd_offset_k(sp
);
163 set_pgd(pgd
, *pgd_ref
);
167 * "pgd" is faked. The top level entries are "p4d"s, so sync
168 * the p4d. This compiles to approximately the same code as
171 p4d_t
*p4d
= p4d_offset(pgd
, sp
);
173 if (unlikely(p4d_none(*p4d
))) {
174 pgd_t
*pgd_ref
= pgd_offset_k(sp
);
175 p4d_t
*p4d_ref
= p4d_offset(pgd_ref
, sp
);
177 set_p4d(p4d
, *p4d_ref
);
182 void switch_mm_irqs_off(struct mm_struct
*prev
, struct mm_struct
*next
,
183 struct task_struct
*tsk
)
185 struct mm_struct
*real_prev
= this_cpu_read(cpu_tlbstate
.loaded_mm
);
186 u16 prev_asid
= this_cpu_read(cpu_tlbstate
.loaded_mm_asid
);
187 unsigned cpu
= smp_processor_id();
191 * NB: The scheduler will call us with prev == next when switching
192 * from lazy TLB mode to normal mode if active_mm isn't changing.
193 * When this happens, we don't assume that CR3 (and hence
194 * cpu_tlbstate.loaded_mm) matches next.
196 * NB: leave_mm() calls us with prev == NULL and tsk == NULL.
199 /* We don't want flush_tlb_func_* to run concurrently with us. */
200 if (IS_ENABLED(CONFIG_PROVE_LOCKING
))
201 WARN_ON_ONCE(!irqs_disabled());
204 * Verify that CR3 is what we think it is. This will catch
205 * hypothetical buggy code that directly switches to swapper_pg_dir
206 * without going through leave_mm() / switch_mm_irqs_off() or that
207 * does something like write_cr3(read_cr3_pa()).
209 * Only do this check if CONFIG_DEBUG_VM=y because __read_cr3()
212 #ifdef CONFIG_DEBUG_VM
213 if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev
->pgd
, prev_asid
))) {
215 * If we were to BUG here, we'd be very likely to kill
216 * the system so hard that we don't see the call trace.
217 * Try to recover instead by ignoring the error and doing
218 * a global flush to minimize the chance of corruption.
220 * (This is far from being a fully correct recovery.
221 * Architecturally, the CPU could prefetch something
222 * back into an incorrect ASID slot and leave it there
223 * to cause trouble down the road. It's better than
229 this_cpu_write(cpu_tlbstate
.is_lazy
, false);
231 if (real_prev
== next
) {
232 VM_WARN_ON(this_cpu_read(cpu_tlbstate
.ctxs
[prev_asid
].ctx_id
) !=
233 next
->context
.ctx_id
);
236 * We don't currently support having a real mm loaded without
237 * our cpu set in mm_cpumask(). We have all the bookkeeping
238 * in place to figure out whether we would need to flush
239 * if our cpu were cleared in mm_cpumask(), but we don't
242 if (WARN_ON_ONCE(real_prev
!= &init_mm
&&
243 !cpumask_test_cpu(cpu
, mm_cpumask(next
))))
244 cpumask_set_cpu(cpu
, mm_cpumask(next
));
251 if (IS_ENABLED(CONFIG_VMAP_STACK
)) {
253 * If our current stack is in vmalloc space and isn't
254 * mapped in the new pgd, we'll double-fault. Forcibly
257 sync_current_stack_to_mm(next
);
260 /* Stop remote flushes for the previous mm */
261 VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu
, mm_cpumask(real_prev
)) &&
262 real_prev
!= &init_mm
);
263 cpumask_clear_cpu(cpu
, mm_cpumask(real_prev
));
266 * Start remote flushes and then read tlb_gen.
268 cpumask_set_cpu(cpu
, mm_cpumask(next
));
269 next_tlb_gen
= atomic64_read(&next
->context
.tlb_gen
);
271 choose_new_asid(next
, next_tlb_gen
, &new_asid
, &need_flush
);
274 this_cpu_write(cpu_tlbstate
.ctxs
[new_asid
].ctx_id
, next
->context
.ctx_id
);
275 this_cpu_write(cpu_tlbstate
.ctxs
[new_asid
].tlb_gen
, next_tlb_gen
);
276 load_new_mm_cr3(next
->pgd
, new_asid
, true);
279 * NB: This gets called via leave_mm() in the idle path
280 * where RCU functions differently. Tracing normally
281 * uses RCU, so we need to use the _rcuidle variant.
283 * (There is no good reason for this. The idle code should
284 * be rearranged to call this before rcu_idle_enter().)
286 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH
, TLB_FLUSH_ALL
);
288 /* The new ASID is already up to date. */
289 load_new_mm_cr3(next
->pgd
, new_asid
, false);
291 /* See above wrt _rcuidle. */
292 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH
, 0);
295 this_cpu_write(cpu_tlbstate
.loaded_mm
, next
);
296 this_cpu_write(cpu_tlbstate
.loaded_mm_asid
, new_asid
);
300 switch_ldt(real_prev
, next
);
304 * Please ignore the name of this function. It should be called
305 * switch_to_kernel_thread().
307 * enter_lazy_tlb() is a hint from the scheduler that we are entering a
308 * kernel thread or other context without an mm. Acceptable implementations
309 * include doing nothing whatsoever, switching to init_mm, or various clever
310 * lazy tricks to try to minimize TLB flushes.
312 * The scheduler reserves the right to call enter_lazy_tlb() several times
313 * in a row. It will notify us that we're going back to a real mm by
314 * calling switch_mm_irqs_off().
316 void enter_lazy_tlb(struct mm_struct
*mm
, struct task_struct
*tsk
)
318 if (this_cpu_read(cpu_tlbstate
.loaded_mm
) == &init_mm
)
321 if (tlb_defer_switch_to_init_mm()) {
323 * There's a significant optimization that may be possible
324 * here. We have accurate enough TLB flush tracking that we
325 * don't need to maintain coherence of TLB per se when we're
326 * lazy. We do, however, need to maintain coherence of
327 * paging-structure caches. We could, in principle, leave our
328 * old mm loaded and only switch to init_mm when
329 * tlb_remove_page() happens.
331 this_cpu_write(cpu_tlbstate
.is_lazy
, true);
333 switch_mm(NULL
, &init_mm
, NULL
);
338 * Call this when reinitializing a CPU. It fixes the following potential
341 * - The ASID changed from what cpu_tlbstate thinks it is (most likely
342 * because the CPU was taken down and came back up with CR3's PCID
343 * bits clear. CPU hotplug can do this.
345 * - The TLB contains junk in slots corresponding to inactive ASIDs.
347 * - The CPU went so far out to lunch that it may have missed a TLB
350 void initialize_tlbstate_and_flush(void)
353 struct mm_struct
*mm
= this_cpu_read(cpu_tlbstate
.loaded_mm
);
354 u64 tlb_gen
= atomic64_read(&init_mm
.context
.tlb_gen
);
355 unsigned long cr3
= __read_cr3();
357 /* Assert that CR3 already references the right mm. */
358 WARN_ON((cr3
& CR3_ADDR_MASK
) != __pa(mm
->pgd
));
361 * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization
362 * doesn't work like other CR4 bits because it can only be set from
365 WARN_ON(boot_cpu_has(X86_FEATURE_PCID
) &&
366 !(cr4_read_shadow() & X86_CR4_PCIDE
));
368 /* Force ASID 0 and force a TLB flush. */
369 write_cr3(build_cr3(mm
->pgd
, 0));
371 /* Reinitialize tlbstate. */
372 this_cpu_write(cpu_tlbstate
.loaded_mm_asid
, 0);
373 this_cpu_write(cpu_tlbstate
.next_asid
, 1);
374 this_cpu_write(cpu_tlbstate
.ctxs
[0].ctx_id
, mm
->context
.ctx_id
);
375 this_cpu_write(cpu_tlbstate
.ctxs
[0].tlb_gen
, tlb_gen
);
377 for (i
= 1; i
< TLB_NR_DYN_ASIDS
; i
++)
378 this_cpu_write(cpu_tlbstate
.ctxs
[i
].ctx_id
, 0);
382 * flush_tlb_func_common()'s memory ordering requirement is that any
383 * TLB fills that happen after we flush the TLB are ordered after we
384 * read active_mm's tlb_gen. We don't need any explicit barriers
385 * because all x86 flush operations are serializing and the
386 * atomic64_read operation won't be reordered by the compiler.
388 static void flush_tlb_func_common(const struct flush_tlb_info
*f
,
389 bool local
, enum tlb_flush_reason reason
)
392 * We have three different tlb_gen values in here. They are:
394 * - mm_tlb_gen: the latest generation.
395 * - local_tlb_gen: the generation that this CPU has already caught
397 * - f->new_tlb_gen: the generation that the requester of the flush
398 * wants us to catch up to.
400 struct mm_struct
*loaded_mm
= this_cpu_read(cpu_tlbstate
.loaded_mm
);
401 u32 loaded_mm_asid
= this_cpu_read(cpu_tlbstate
.loaded_mm_asid
);
402 u64 mm_tlb_gen
= atomic64_read(&loaded_mm
->context
.tlb_gen
);
403 u64 local_tlb_gen
= this_cpu_read(cpu_tlbstate
.ctxs
[loaded_mm_asid
].tlb_gen
);
405 /* This code cannot presently handle being reentered. */
406 VM_WARN_ON(!irqs_disabled());
408 if (unlikely(loaded_mm
== &init_mm
))
411 VM_WARN_ON(this_cpu_read(cpu_tlbstate
.ctxs
[loaded_mm_asid
].ctx_id
) !=
412 loaded_mm
->context
.ctx_id
);
414 if (this_cpu_read(cpu_tlbstate
.is_lazy
)) {
416 * We're in lazy mode. We need to at least flush our
417 * paging-structure cache to avoid speculatively reading
418 * garbage into our TLB. Since switching to init_mm is barely
419 * slower than a minimal flush, just switch to init_mm.
421 switch_mm_irqs_off(NULL
, &init_mm
, NULL
);
425 if (unlikely(local_tlb_gen
== mm_tlb_gen
)) {
427 * There's nothing to do: we're already up to date. This can
428 * happen if two concurrent flushes happen -- the first flush to
429 * be handled can catch us all the way up, leaving no work for
432 trace_tlb_flush(reason
, 0);
436 WARN_ON_ONCE(local_tlb_gen
> mm_tlb_gen
);
437 WARN_ON_ONCE(f
->new_tlb_gen
> mm_tlb_gen
);
440 * If we get to this point, we know that our TLB is out of date.
441 * This does not strictly imply that we need to flush (it's
442 * possible that f->new_tlb_gen <= local_tlb_gen), but we're
443 * going to need to flush in the very near future, so we might
444 * as well get it over with.
446 * The only question is whether to do a full or partial flush.
448 * We do a partial flush if requested and two extra conditions
451 * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that
452 * we've always done all needed flushes to catch up to
453 * local_tlb_gen. If, for example, local_tlb_gen == 2 and
454 * f->new_tlb_gen == 3, then we know that the flush needed to bring
455 * us up to date for tlb_gen 3 is the partial flush we're
458 * As an example of why this check is needed, suppose that there
459 * are two concurrent flushes. The first is a full flush that
460 * changes context.tlb_gen from 1 to 2. The second is a partial
461 * flush that changes context.tlb_gen from 2 to 3. If they get
462 * processed on this CPU in reverse order, we'll see
463 * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.
464 * If we were to use __flush_tlb_single() and set local_tlb_gen to
465 * 3, we'd be break the invariant: we'd update local_tlb_gen above
466 * 1 without the full flush that's needed for tlb_gen 2.
468 * 2. f->new_tlb_gen == mm_tlb_gen. This is purely an optimiation.
469 * Partial TLB flushes are not all that much cheaper than full TLB
470 * flushes, so it seems unlikely that it would be a performance win
471 * to do a partial flush if that won't bring our TLB fully up to
472 * date. By doing a full flush instead, we can increase
473 * local_tlb_gen all the way to mm_tlb_gen and we can probably
474 * avoid another flush in the very near future.
476 if (f
->end
!= TLB_FLUSH_ALL
&&
477 f
->new_tlb_gen
== local_tlb_gen
+ 1 &&
478 f
->new_tlb_gen
== mm_tlb_gen
) {
481 unsigned long nr_pages
= (f
->end
- f
->start
) >> PAGE_SHIFT
;
484 while (addr
< f
->end
) {
485 __flush_tlb_single(addr
);
489 count_vm_tlb_events(NR_TLB_LOCAL_FLUSH_ONE
, nr_pages
);
490 trace_tlb_flush(reason
, nr_pages
);
495 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL
);
496 trace_tlb_flush(reason
, TLB_FLUSH_ALL
);
499 /* Both paths above update our state to mm_tlb_gen. */
500 this_cpu_write(cpu_tlbstate
.ctxs
[loaded_mm_asid
].tlb_gen
, mm_tlb_gen
);
503 static void flush_tlb_func_local(void *info
, enum tlb_flush_reason reason
)
505 const struct flush_tlb_info
*f
= info
;
507 flush_tlb_func_common(f
, true, reason
);
510 static void flush_tlb_func_remote(void *info
)
512 const struct flush_tlb_info
*f
= info
;
514 inc_irq_stat(irq_tlb_count
);
516 if (f
->mm
&& f
->mm
!= this_cpu_read(cpu_tlbstate
.loaded_mm
))
519 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED
);
520 flush_tlb_func_common(f
, false, TLB_REMOTE_SHOOTDOWN
);
523 void native_flush_tlb_others(const struct cpumask
*cpumask
,
524 const struct flush_tlb_info
*info
)
526 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH
);
527 if (info
->end
== TLB_FLUSH_ALL
)
528 trace_tlb_flush(TLB_REMOTE_SEND_IPI
, TLB_FLUSH_ALL
);
530 trace_tlb_flush(TLB_REMOTE_SEND_IPI
,
531 (info
->end
- info
->start
) >> PAGE_SHIFT
);
533 if (is_uv_system()) {
535 * This whole special case is confused. UV has a "Broadcast
536 * Assist Unit", which seems to be a fancy way to send IPIs.
537 * Back when x86 used an explicit TLB flush IPI, UV was
538 * optimized to use its own mechanism. These days, x86 uses
539 * smp_call_function_many(), but UV still uses a manual IPI,
540 * and that IPI's action is out of date -- it does a manual
541 * flush instead of calling flush_tlb_func_remote(). This
542 * means that the percpu tlb_gen variables won't be updated
543 * and we'll do pointless flushes on future context switches.
545 * Rather than hooking native_flush_tlb_others() here, I think
546 * that UV should be updated so that smp_call_function_many(),
547 * etc, are optimal on UV.
551 cpu
= smp_processor_id();
552 cpumask
= uv_flush_tlb_others(cpumask
, info
);
554 smp_call_function_many(cpumask
, flush_tlb_func_remote
,
558 smp_call_function_many(cpumask
, flush_tlb_func_remote
,
563 * See Documentation/x86/tlb.txt for details. We choose 33
564 * because it is large enough to cover the vast majority (at
565 * least 95%) of allocations, and is small enough that we are
566 * confident it will not cause too much overhead. Each single
567 * flush is about 100 ns, so this caps the maximum overhead at
570 * This is in units of pages.
572 static unsigned long tlb_single_page_flush_ceiling __read_mostly
= 33;
574 void flush_tlb_mm_range(struct mm_struct
*mm
, unsigned long start
,
575 unsigned long end
, unsigned long vmflag
)
579 struct flush_tlb_info info
= {
585 /* This is also a barrier that synchronizes with switch_mm(). */
586 info
.new_tlb_gen
= inc_mm_tlb_gen(mm
);
588 /* Should we flush just the requested range? */
589 if ((end
!= TLB_FLUSH_ALL
) &&
590 !(vmflag
& VM_HUGETLB
) &&
591 ((end
- start
) >> PAGE_SHIFT
) <= tlb_single_page_flush_ceiling
) {
596 info
.end
= TLB_FLUSH_ALL
;
599 if (mm
== this_cpu_read(cpu_tlbstate
.loaded_mm
)) {
600 VM_WARN_ON(irqs_disabled());
602 flush_tlb_func_local(&info
, TLB_LOCAL_MM_SHOOTDOWN
);
606 if (cpumask_any_but(mm_cpumask(mm
), cpu
) < nr_cpu_ids
)
607 flush_tlb_others(mm_cpumask(mm
), &info
);
613 static void do_flush_tlb_all(void *info
)
615 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED
);
619 void flush_tlb_all(void)
621 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH
);
622 on_each_cpu(do_flush_tlb_all
, NULL
, 1);
625 static void do_kernel_range_flush(void *info
)
627 struct flush_tlb_info
*f
= info
;
630 /* flush range by one by one 'invlpg' */
631 for (addr
= f
->start
; addr
< f
->end
; addr
+= PAGE_SIZE
)
632 __flush_tlb_one(addr
);
635 void flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
638 /* Balance as user space task's flush, a bit conservative */
639 if (end
== TLB_FLUSH_ALL
||
640 (end
- start
) > tlb_single_page_flush_ceiling
<< PAGE_SHIFT
) {
641 on_each_cpu(do_flush_tlb_all
, NULL
, 1);
643 struct flush_tlb_info info
;
646 on_each_cpu(do_kernel_range_flush
, &info
, 1);
650 void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch
*batch
)
652 struct flush_tlb_info info
= {
655 .end
= TLB_FLUSH_ALL
,
660 if (cpumask_test_cpu(cpu
, &batch
->cpumask
)) {
661 VM_WARN_ON(irqs_disabled());
663 flush_tlb_func_local(&info
, TLB_LOCAL_SHOOTDOWN
);
667 if (cpumask_any_but(&batch
->cpumask
, cpu
) < nr_cpu_ids
)
668 flush_tlb_others(&batch
->cpumask
, &info
);
670 cpumask_clear(&batch
->cpumask
);
675 static ssize_t
tlbflush_read_file(struct file
*file
, char __user
*user_buf
,
676 size_t count
, loff_t
*ppos
)
681 len
= sprintf(buf
, "%ld\n", tlb_single_page_flush_ceiling
);
682 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
685 static ssize_t
tlbflush_write_file(struct file
*file
,
686 const char __user
*user_buf
, size_t count
, loff_t
*ppos
)
692 len
= min(count
, sizeof(buf
) - 1);
693 if (copy_from_user(buf
, user_buf
, len
))
697 if (kstrtoint(buf
, 0, &ceiling
))
703 tlb_single_page_flush_ceiling
= ceiling
;
707 static const struct file_operations fops_tlbflush
= {
708 .read
= tlbflush_read_file
,
709 .write
= tlbflush_write_file
,
710 .llseek
= default_llseek
,
713 static int __init
create_tlb_single_page_flush_ceiling(void)
715 debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR
| S_IWUSR
,
716 arch_debugfs_dir
, NULL
, &fops_tlbflush
);
719 late_initcall(create_tlb_single_page_flush_ceiling
);