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[mirror_ubuntu-bionic-kernel.git] / arch / x86 / oprofile / op_model_amd.c
1 /*
2 * @file op_model_amd.c
3 * athlon / K7 / K8 / Family 10h model-specific MSR operations
4 *
5 * @remark Copyright 2002-2009 OProfile authors
6 * @remark Read the file COPYING
7 *
8 * @author John Levon
9 * @author Philippe Elie
10 * @author Graydon Hoare
11 * @author Robert Richter <robert.richter@amd.com>
12 * @author Barry Kasindorf <barry.kasindorf@amd.com>
13 * @author Jason Yeh <jason.yeh@amd.com>
14 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
15 */
16
17 #include <linux/oprofile.h>
18 #include <linux/device.h>
19 #include <linux/pci.h>
20 #include <linux/percpu.h>
21
22 #include <asm/ptrace.h>
23 #include <asm/msr.h>
24 #include <asm/nmi.h>
25 #include <asm/apic.h>
26 #include <asm/processor.h>
27 #include <asm/cpufeature.h>
28
29 #include "op_x86_model.h"
30 #include "op_counter.h"
31
32 #define NUM_COUNTERS 4
33 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
34 #define NUM_VIRT_COUNTERS 32
35 #else
36 #define NUM_VIRT_COUNTERS NUM_COUNTERS
37 #endif
38
39 #define OP_EVENT_MASK 0x0FFF
40 #define OP_CTR_OVERFLOW (1ULL<<31)
41
42 #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
43
44 static unsigned long reset_value[NUM_VIRT_COUNTERS];
45
46 #define IBS_FETCH_SIZE 6
47 #define IBS_OP_SIZE 12
48
49 static u32 ibs_caps;
50
51 struct ibs_config {
52 unsigned long op_enabled;
53 unsigned long fetch_enabled;
54 unsigned long max_cnt_fetch;
55 unsigned long max_cnt_op;
56 unsigned long rand_en;
57 unsigned long dispatched_ops;
58 unsigned long branch_target;
59 };
60
61 struct ibs_state {
62 u64 ibs_op_ctl;
63 int branch_target;
64 unsigned long sample_size;
65 };
66
67 static struct ibs_config ibs_config;
68 static struct ibs_state ibs_state;
69
70 /*
71 * IBS cpuid feature detection
72 */
73
74 #define IBS_CPUID_FEATURES 0x8000001b
75
76 /*
77 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
78 * bit 0 is used to indicate the existence of IBS.
79 */
80 #define IBS_CAPS_AVAIL (1U<<0)
81 #define IBS_CAPS_FETCHSAM (1U<<1)
82 #define IBS_CAPS_OPSAM (1U<<2)
83 #define IBS_CAPS_RDWROPCNT (1U<<3)
84 #define IBS_CAPS_OPCNT (1U<<4)
85 #define IBS_CAPS_BRNTRGT (1U<<5)
86 #define IBS_CAPS_OPCNTEXT (1U<<6)
87
88 #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
89 | IBS_CAPS_FETCHSAM \
90 | IBS_CAPS_OPSAM)
91
92 /*
93 * IBS APIC setup
94 */
95 #define IBSCTL 0x1cc
96 #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
97 #define IBSCTL_LVT_OFFSET_MASK 0x0F
98
99 /*
100 * IBS randomization macros
101 */
102 #define IBS_RANDOM_BITS 12
103 #define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1)
104 #define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5))
105
106 static u32 get_ibs_caps(void)
107 {
108 u32 ibs_caps;
109 unsigned int max_level;
110
111 if (!boot_cpu_has(X86_FEATURE_IBS))
112 return 0;
113
114 /* check IBS cpuid feature flags */
115 max_level = cpuid_eax(0x80000000);
116 if (max_level < IBS_CPUID_FEATURES)
117 return IBS_CAPS_DEFAULT;
118
119 ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
120 if (!(ibs_caps & IBS_CAPS_AVAIL))
121 /* cpuid flags not valid */
122 return IBS_CAPS_DEFAULT;
123
124 return ibs_caps;
125 }
126
127 /*
128 * 16-bit Linear Feedback Shift Register (LFSR)
129 *
130 * 16 14 13 11
131 * Feedback polynomial = X + X + X + X + 1
132 */
133 static unsigned int lfsr_random(void)
134 {
135 static unsigned int lfsr_value = 0xF00D;
136 unsigned int bit;
137
138 /* Compute next bit to shift in */
139 bit = ((lfsr_value >> 0) ^
140 (lfsr_value >> 2) ^
141 (lfsr_value >> 3) ^
142 (lfsr_value >> 5)) & 0x0001;
143
144 /* Advance to next register value */
145 lfsr_value = (lfsr_value >> 1) | (bit << 15);
146
147 return lfsr_value;
148 }
149
150 /*
151 * IBS software randomization
152 *
153 * The IBS periodic op counter is randomized in software. The lower 12
154 * bits of the 20 bit counter are randomized. IbsOpCurCnt is
155 * initialized with a 12 bit random value.
156 */
157 static inline u64 op_amd_randomize_ibs_op(u64 val)
158 {
159 unsigned int random = lfsr_random();
160
161 if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
162 /*
163 * Work around if the hw can not write to IbsOpCurCnt
164 *
165 * Randomize the lower 8 bits of the 16 bit
166 * IbsOpMaxCnt [15:0] value in the range of -128 to
167 * +127 by adding/subtracting an offset to the
168 * maximum count (IbsOpMaxCnt).
169 *
170 * To avoid over or underflows and protect upper bits
171 * starting at bit 16, the initial value for
172 * IbsOpMaxCnt must fit in the range from 0x0081 to
173 * 0xff80.
174 */
175 val += (s8)(random >> 4);
176 else
177 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
178
179 return val;
180 }
181
182 static inline void
183 op_amd_handle_ibs(struct pt_regs * const regs,
184 struct op_msrs const * const msrs)
185 {
186 u64 val, ctl;
187 struct op_entry entry;
188
189 if (!ibs_caps)
190 return;
191
192 if (ibs_config.fetch_enabled) {
193 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
194 if (ctl & IBS_FETCH_VAL) {
195 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
196 oprofile_write_reserve(&entry, regs, val,
197 IBS_FETCH_CODE, IBS_FETCH_SIZE);
198 oprofile_add_data64(&entry, val);
199 oprofile_add_data64(&entry, ctl);
200 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
201 oprofile_add_data64(&entry, val);
202 oprofile_write_commit(&entry);
203
204 /* reenable the IRQ */
205 ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
206 ctl |= IBS_FETCH_ENABLE;
207 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
208 }
209 }
210
211 if (ibs_config.op_enabled) {
212 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
213 if (ctl & IBS_OP_VAL) {
214 rdmsrl(MSR_AMD64_IBSOPRIP, val);
215 oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE,
216 ibs_state.sample_size);
217 oprofile_add_data64(&entry, val);
218 rdmsrl(MSR_AMD64_IBSOPDATA, val);
219 oprofile_add_data64(&entry, val);
220 rdmsrl(MSR_AMD64_IBSOPDATA2, val);
221 oprofile_add_data64(&entry, val);
222 rdmsrl(MSR_AMD64_IBSOPDATA3, val);
223 oprofile_add_data64(&entry, val);
224 rdmsrl(MSR_AMD64_IBSDCLINAD, val);
225 oprofile_add_data64(&entry, val);
226 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
227 oprofile_add_data64(&entry, val);
228 if (ibs_state.branch_target) {
229 rdmsrl(MSR_AMD64_IBSBRTARGET, val);
230 oprofile_add_data(&entry, (unsigned long)val);
231 }
232 oprofile_write_commit(&entry);
233
234 /* reenable the IRQ */
235 ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
236 wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
237 }
238 }
239 }
240
241 static inline void op_amd_start_ibs(void)
242 {
243 u64 val;
244
245 if (!ibs_caps)
246 return;
247
248 memset(&ibs_state, 0, sizeof(ibs_state));
249
250 /*
251 * Note: Since the max count settings may out of range we
252 * write back the actual used values so that userland can read
253 * it.
254 */
255
256 if (ibs_config.fetch_enabled) {
257 val = ibs_config.max_cnt_fetch >> 4;
258 val = min(val, IBS_FETCH_MAX_CNT);
259 ibs_config.max_cnt_fetch = val << 4;
260 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
261 val |= IBS_FETCH_ENABLE;
262 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
263 }
264
265 if (ibs_config.op_enabled) {
266 val = ibs_config.max_cnt_op >> 4;
267 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
268 /*
269 * IbsOpCurCnt not supported. See
270 * op_amd_randomize_ibs_op() for details.
271 */
272 val = clamp(val, 0x0081ULL, 0xFF80ULL);
273 ibs_config.max_cnt_op = val << 4;
274 } else {
275 /*
276 * The start value is randomized with a
277 * positive offset, we need to compensate it
278 * with the half of the randomized range. Also
279 * avoid underflows.
280 */
281 val += IBS_RANDOM_MAXCNT_OFFSET;
282 if (ibs_caps & IBS_CAPS_OPCNTEXT)
283 val = min(val, IBS_OP_MAX_CNT_EXT);
284 else
285 val = min(val, IBS_OP_MAX_CNT);
286 ibs_config.max_cnt_op =
287 (val - IBS_RANDOM_MAXCNT_OFFSET) << 4;
288 }
289 val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT);
290 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
291 val |= IBS_OP_ENABLE;
292 ibs_state.ibs_op_ctl = val;
293 ibs_state.sample_size = IBS_OP_SIZE;
294 if (ibs_config.branch_target) {
295 ibs_state.branch_target = 1;
296 ibs_state.sample_size++;
297 }
298 val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
299 wrmsrl(MSR_AMD64_IBSOPCTL, val);
300 }
301 }
302
303 static void op_amd_stop_ibs(void)
304 {
305 if (!ibs_caps)
306 return;
307
308 if (ibs_config.fetch_enabled)
309 /* clear max count and enable */
310 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
311
312 if (ibs_config.op_enabled)
313 /* clear max count and enable */
314 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
315 }
316
317 static inline int eilvt_is_available(int offset)
318 {
319 /* check if we may assign a vector */
320 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
321 }
322
323 static inline int ibs_eilvt_valid(void)
324 {
325 int offset;
326 u64 val;
327
328 rdmsrl(MSR_AMD64_IBSCTL, val);
329 offset = val & IBSCTL_LVT_OFFSET_MASK;
330
331 if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
332 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
333 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
334 return 0;
335 }
336
337 if (!eilvt_is_available(offset)) {
338 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
339 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
340 return 0;
341 }
342
343 return 1;
344 }
345
346 static inline int get_ibs_offset(void)
347 {
348 u64 val;
349
350 rdmsrl(MSR_AMD64_IBSCTL, val);
351 if (!(val & IBSCTL_LVT_OFFSET_VALID))
352 return -EINVAL;
353
354 return val & IBSCTL_LVT_OFFSET_MASK;
355 }
356
357 static void setup_APIC_ibs(void)
358 {
359 int offset;
360
361 offset = get_ibs_offset();
362 if (offset < 0)
363 goto failed;
364
365 if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
366 return;
367 failed:
368 pr_warn("oprofile: IBS APIC setup failed on cpu #%d\n",
369 smp_processor_id());
370 }
371
372 static void clear_APIC_ibs(void)
373 {
374 int offset;
375
376 offset = get_ibs_offset();
377 if (offset >= 0)
378 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
379 }
380
381 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
382
383 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
384 struct op_msrs const * const msrs)
385 {
386 u64 val;
387 int i;
388
389 /* enable active counters */
390 for (i = 0; i < NUM_COUNTERS; ++i) {
391 int virt = op_x86_phys_to_virt(i);
392 if (!reset_value[virt])
393 continue;
394 rdmsrl(msrs->controls[i].addr, val);
395 val &= model->reserved;
396 val |= op_x86_get_ctrl(model, &counter_config[virt]);
397 wrmsrl(msrs->controls[i].addr, val);
398 }
399 }
400
401 #endif
402
403 /* functions for op_amd_spec */
404
405 static void op_amd_shutdown(struct op_msrs const * const msrs)
406 {
407 int i;
408
409 for (i = 0; i < NUM_COUNTERS; ++i) {
410 if (!msrs->counters[i].addr)
411 continue;
412 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
413 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
414 }
415 }
416
417 static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
418 {
419 int i;
420
421 for (i = 0; i < NUM_COUNTERS; i++) {
422 if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
423 goto fail;
424 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
425 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
426 goto fail;
427 }
428 /* both registers must be reserved */
429 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
430 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
431 continue;
432 fail:
433 if (!counter_config[i].enabled)
434 continue;
435 op_x86_warn_reserved(i);
436 op_amd_shutdown(msrs);
437 return -EBUSY;
438 }
439
440 return 0;
441 }
442
443 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
444 struct op_msrs const * const msrs)
445 {
446 u64 val;
447 int i;
448
449 /* setup reset_value */
450 for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
451 if (counter_config[i].enabled
452 && msrs->counters[op_x86_virt_to_phys(i)].addr)
453 reset_value[i] = counter_config[i].count;
454 else
455 reset_value[i] = 0;
456 }
457
458 /* clear all counters */
459 for (i = 0; i < NUM_COUNTERS; ++i) {
460 if (!msrs->controls[i].addr)
461 continue;
462 rdmsrl(msrs->controls[i].addr, val);
463 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
464 op_x86_warn_in_use(i);
465 val &= model->reserved;
466 wrmsrl(msrs->controls[i].addr, val);
467 /*
468 * avoid a false detection of ctr overflows in NMI
469 * handler
470 */
471 wrmsrl(msrs->counters[i].addr, -1LL);
472 }
473
474 /* enable active counters */
475 for (i = 0; i < NUM_COUNTERS; ++i) {
476 int virt = op_x86_phys_to_virt(i);
477 if (!reset_value[virt])
478 continue;
479
480 /* setup counter registers */
481 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
482
483 /* setup control registers */
484 rdmsrl(msrs->controls[i].addr, val);
485 val &= model->reserved;
486 val |= op_x86_get_ctrl(model, &counter_config[virt]);
487 wrmsrl(msrs->controls[i].addr, val);
488 }
489
490 if (ibs_caps)
491 setup_APIC_ibs();
492 }
493
494 static void op_amd_cpu_shutdown(void)
495 {
496 if (ibs_caps)
497 clear_APIC_ibs();
498 }
499
500 static int op_amd_check_ctrs(struct pt_regs * const regs,
501 struct op_msrs const * const msrs)
502 {
503 u64 val;
504 int i;
505
506 for (i = 0; i < NUM_COUNTERS; ++i) {
507 int virt = op_x86_phys_to_virt(i);
508 if (!reset_value[virt])
509 continue;
510 rdmsrl(msrs->counters[i].addr, val);
511 /* bit is clear if overflowed: */
512 if (val & OP_CTR_OVERFLOW)
513 continue;
514 oprofile_add_sample(regs, virt);
515 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
516 }
517
518 op_amd_handle_ibs(regs, msrs);
519
520 /* See op_model_ppro.c */
521 return 1;
522 }
523
524 static void op_amd_start(struct op_msrs const * const msrs)
525 {
526 u64 val;
527 int i;
528
529 for (i = 0; i < NUM_COUNTERS; ++i) {
530 if (!reset_value[op_x86_phys_to_virt(i)])
531 continue;
532 rdmsrl(msrs->controls[i].addr, val);
533 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
534 wrmsrl(msrs->controls[i].addr, val);
535 }
536
537 op_amd_start_ibs();
538 }
539
540 static void op_amd_stop(struct op_msrs const * const msrs)
541 {
542 u64 val;
543 int i;
544
545 /*
546 * Subtle: stop on all counters to avoid race with setting our
547 * pm callback
548 */
549 for (i = 0; i < NUM_COUNTERS; ++i) {
550 if (!reset_value[op_x86_phys_to_virt(i)])
551 continue;
552 rdmsrl(msrs->controls[i].addr, val);
553 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
554 wrmsrl(msrs->controls[i].addr, val);
555 }
556
557 op_amd_stop_ibs();
558 }
559
560 static int setup_ibs_ctl(int ibs_eilvt_off)
561 {
562 struct pci_dev *cpu_cfg;
563 int nodes;
564 u32 value = 0;
565
566 nodes = 0;
567 cpu_cfg = NULL;
568 do {
569 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
570 PCI_DEVICE_ID_AMD_10H_NB_MISC,
571 cpu_cfg);
572 if (!cpu_cfg)
573 break;
574 ++nodes;
575 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
576 | IBSCTL_LVT_OFFSET_VALID);
577 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
578 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
579 pci_dev_put(cpu_cfg);
580 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
581 "IBSCTL = 0x%08x\n", value);
582 return -EINVAL;
583 }
584 } while (1);
585
586 if (!nodes) {
587 printk(KERN_DEBUG "No CPU node configured for IBS\n");
588 return -ENODEV;
589 }
590
591 return 0;
592 }
593
594 static int force_ibs_eilvt_setup(void)
595 {
596 int i;
597 int ret;
598
599 /* find the next free available EILVT entry */
600 for (i = 1; i < 4; i++) {
601 if (!eilvt_is_available(i))
602 continue;
603 ret = setup_ibs_ctl(i);
604 if (ret)
605 return ret;
606 return 0;
607 }
608
609 printk(KERN_DEBUG "No EILVT entry available\n");
610
611 return -EBUSY;
612 }
613
614 static int __init_ibs_nmi(void)
615 {
616 int ret;
617
618 if (ibs_eilvt_valid())
619 return 0;
620
621 ret = force_ibs_eilvt_setup();
622 if (ret)
623 return ret;
624
625 if (!ibs_eilvt_valid())
626 return -EFAULT;
627
628 pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
629
630 return 0;
631 }
632
633 /* initialize the APIC for the IBS interrupts if available */
634 static void init_ibs(void)
635 {
636 ibs_caps = get_ibs_caps();
637
638 if (!ibs_caps)
639 return;
640
641 if (__init_ibs_nmi()) {
642 ibs_caps = 0;
643 return;
644 }
645
646 printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
647 (unsigned)ibs_caps);
648 }
649
650 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
651
652 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
653 {
654 struct dentry *dir;
655 int ret = 0;
656
657 /* architecture specific files */
658 if (create_arch_files)
659 ret = create_arch_files(sb, root);
660
661 if (ret)
662 return ret;
663
664 if (!ibs_caps)
665 return ret;
666
667 /* model specific files */
668
669 /* setup some reasonable defaults */
670 memset(&ibs_config, 0, sizeof(ibs_config));
671 ibs_config.max_cnt_fetch = 250000;
672 ibs_config.max_cnt_op = 250000;
673
674 if (ibs_caps & IBS_CAPS_FETCHSAM) {
675 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
676 oprofilefs_create_ulong(sb, dir, "enable",
677 &ibs_config.fetch_enabled);
678 oprofilefs_create_ulong(sb, dir, "max_count",
679 &ibs_config.max_cnt_fetch);
680 oprofilefs_create_ulong(sb, dir, "rand_enable",
681 &ibs_config.rand_en);
682 }
683
684 if (ibs_caps & IBS_CAPS_OPSAM) {
685 dir = oprofilefs_mkdir(sb, root, "ibs_op");
686 oprofilefs_create_ulong(sb, dir, "enable",
687 &ibs_config.op_enabled);
688 oprofilefs_create_ulong(sb, dir, "max_count",
689 &ibs_config.max_cnt_op);
690 if (ibs_caps & IBS_CAPS_OPCNT)
691 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
692 &ibs_config.dispatched_ops);
693 if (ibs_caps & IBS_CAPS_BRNTRGT)
694 oprofilefs_create_ulong(sb, dir, "branch_target",
695 &ibs_config.branch_target);
696 }
697
698 return 0;
699 }
700
701 static int op_amd_init(struct oprofile_operations *ops)
702 {
703 init_ibs();
704 create_arch_files = ops->create_files;
705 ops->create_files = setup_ibs_files;
706 return 0;
707 }
708
709 struct op_x86_model_spec op_amd_spec = {
710 .num_counters = NUM_COUNTERS,
711 .num_controls = NUM_COUNTERS,
712 .num_virt_counters = NUM_VIRT_COUNTERS,
713 .reserved = MSR_AMD_EVENTSEL_RESERVED,
714 .event_mask = OP_EVENT_MASK,
715 .init = op_amd_init,
716 .fill_in_addresses = &op_amd_fill_in_addresses,
717 .setup_ctrs = &op_amd_setup_ctrs,
718 .cpu_down = &op_amd_cpu_shutdown,
719 .check_ctrs = &op_amd_check_ctrs,
720 .start = &op_amd_start,
721 .stop = &op_amd_stop,
722 .shutdown = &op_amd_shutdown,
723 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
724 .switch_ctrl = &op_mux_switch_ctrl,
725 #endif
726 };
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