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1 /*
2 * Low-Level PCI Support for PC
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
6
7 #include <linux/sched.h>
8 #include <linux/pci.h>
9 #include <linux/ioport.h>
10 #include <linux/init.h>
11 #include <linux/dmi.h>
12
13 #include <asm/acpi.h>
14 #include <asm/segment.h>
15 #include <asm/io.h>
16 #include <asm/smp.h>
17
18 #include "pci.h"
19
20 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
21 PCI_PROBE_MMCONF;
22
23 static int pci_bf_sort;
24 int pci_routeirq;
25 int pcibios_last_bus = -1;
26 unsigned long pirq_table_addr;
27 struct pci_bus *pci_root_bus;
28 struct pci_raw_ops *raw_pci_ops;
29 struct pci_raw_ops *raw_pci_ext_ops;
30
31 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
32 int reg, int len, u32 *val)
33 {
34 if (reg < 256 && raw_pci_ops)
35 return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
36 if (raw_pci_ext_ops)
37 return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
38 return -EINVAL;
39 }
40
41 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
42 int reg, int len, u32 val)
43 {
44 if (reg < 256 && raw_pci_ops)
45 return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
46 if (raw_pci_ext_ops)
47 return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
48 return -EINVAL;
49 }
50
51 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
52 {
53 return raw_pci_read(pci_domain_nr(bus), bus->number,
54 devfn, where, size, value);
55 }
56
57 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
58 {
59 return raw_pci_write(pci_domain_nr(bus), bus->number,
60 devfn, where, size, value);
61 }
62
63 struct pci_ops pci_root_ops = {
64 .read = pci_read,
65 .write = pci_write,
66 };
67
68 /*
69 * legacy, numa, and acpi all want to call pcibios_scan_root
70 * from their initcalls. This flag prevents that.
71 */
72 int pcibios_scanned;
73
74 /*
75 * This interrupt-safe spinlock protects all accesses to PCI
76 * configuration space.
77 */
78 DEFINE_SPINLOCK(pci_config_lock);
79
80 static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
81 {
82 struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
83
84 if (rom_r->parent)
85 return;
86 if (rom_r->start)
87 /* we deal with BIOS assigned ROM later */
88 return;
89 if (!(pci_probe & PCI_ASSIGN_ROMS))
90 rom_r->start = rom_r->end = rom_r->flags = 0;
91 }
92
93 /*
94 * Called after each bus is probed, but before its children
95 * are examined.
96 */
97
98 void __devinit pcibios_fixup_bus(struct pci_bus *b)
99 {
100 struct pci_dev *dev;
101
102 pci_read_bridge_bases(b);
103 list_for_each_entry(dev, &b->devices, bus_list)
104 pcibios_fixup_device_resources(dev);
105 }
106
107 /*
108 * Only use DMI information to set this if nothing was passed
109 * on the kernel command line (which was parsed earlier).
110 */
111
112 static int __devinit set_bf_sort(const struct dmi_system_id *d)
113 {
114 if (pci_bf_sort == pci_bf_sort_default) {
115 pci_bf_sort = pci_dmi_bf;
116 printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
117 }
118 return 0;
119 }
120
121 /*
122 * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
123 */
124 #ifdef __i386__
125 static int __devinit assign_all_busses(const struct dmi_system_id *d)
126 {
127 pci_probe |= PCI_ASSIGN_ALL_BUSSES;
128 printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
129 " (pci=assign-busses)\n", d->ident);
130 return 0;
131 }
132 #endif
133
134 static struct dmi_system_id __devinitdata pciprobe_dmi_table[] = {
135 #ifdef __i386__
136 /*
137 * Laptops which need pci=assign-busses to see Cardbus cards
138 */
139 {
140 .callback = assign_all_busses,
141 .ident = "Samsung X20 Laptop",
142 .matches = {
143 DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
144 DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
145 },
146 },
147 #endif /* __i386__ */
148 {
149 .callback = set_bf_sort,
150 .ident = "Dell PowerEdge 1950",
151 .matches = {
152 DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
153 DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
154 },
155 },
156 {
157 .callback = set_bf_sort,
158 .ident = "Dell PowerEdge 1955",
159 .matches = {
160 DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
161 DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
162 },
163 },
164 {
165 .callback = set_bf_sort,
166 .ident = "Dell PowerEdge 2900",
167 .matches = {
168 DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
169 DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
170 },
171 },
172 {
173 .callback = set_bf_sort,
174 .ident = "Dell PowerEdge 2950",
175 .matches = {
176 DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
177 DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
178 },
179 },
180 {
181 .callback = set_bf_sort,
182 .ident = "Dell PowerEdge R900",
183 .matches = {
184 DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
185 DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
186 },
187 },
188 {
189 .callback = set_bf_sort,
190 .ident = "HP ProLiant BL20p G3",
191 .matches = {
192 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
193 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
194 },
195 },
196 {
197 .callback = set_bf_sort,
198 .ident = "HP ProLiant BL20p G4",
199 .matches = {
200 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
201 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
202 },
203 },
204 {
205 .callback = set_bf_sort,
206 .ident = "HP ProLiant BL30p G1",
207 .matches = {
208 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
209 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
210 },
211 },
212 {
213 .callback = set_bf_sort,
214 .ident = "HP ProLiant BL25p G1",
215 .matches = {
216 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
217 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
218 },
219 },
220 {
221 .callback = set_bf_sort,
222 .ident = "HP ProLiant BL35p G1",
223 .matches = {
224 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
225 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
226 },
227 },
228 {
229 .callback = set_bf_sort,
230 .ident = "HP ProLiant BL45p G1",
231 .matches = {
232 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
233 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
234 },
235 },
236 {
237 .callback = set_bf_sort,
238 .ident = "HP ProLiant BL45p G2",
239 .matches = {
240 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
241 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
242 },
243 },
244 {
245 .callback = set_bf_sort,
246 .ident = "HP ProLiant BL460c G1",
247 .matches = {
248 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
249 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
250 },
251 },
252 {
253 .callback = set_bf_sort,
254 .ident = "HP ProLiant BL465c G1",
255 .matches = {
256 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
257 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
258 },
259 },
260 {
261 .callback = set_bf_sort,
262 .ident = "HP ProLiant BL480c G1",
263 .matches = {
264 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
265 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
266 },
267 },
268 {
269 .callback = set_bf_sort,
270 .ident = "HP ProLiant BL685c G1",
271 .matches = {
272 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
273 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
274 },
275 },
276 {
277 .callback = set_bf_sort,
278 .ident = "HP ProLiant DL385 G2",
279 .matches = {
280 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
281 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
282 },
283 },
284 {
285 .callback = set_bf_sort,
286 .ident = "HP ProLiant DL585 G2",
287 .matches = {
288 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
289 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
290 },
291 },
292 #ifdef __i386__
293 {
294 .callback = assign_all_busses,
295 .ident = "Compaq EVO N800c",
296 .matches = {
297 DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
298 DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
299 },
300 },
301 #endif
302 {
303 .callback = set_bf_sort,
304 .ident = "HP ProLiant DL385 G2",
305 .matches = {
306 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
307 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
308 },
309 },
310 {
311 .callback = set_bf_sort,
312 .ident = "HP ProLiant DL585 G2",
313 .matches = {
314 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
315 DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
316 },
317 },
318 {}
319 };
320
321 struct pci_bus * __devinit pcibios_scan_root(int busnum)
322 {
323 struct pci_bus *bus = NULL;
324 struct pci_sysdata *sd;
325
326 dmi_check_system(pciprobe_dmi_table);
327
328 while ((bus = pci_find_next_bus(bus)) != NULL) {
329 if (bus->number == busnum) {
330 /* Already scanned */
331 return bus;
332 }
333 }
334
335 /* Allocate per-root-bus (not per bus) arch-specific data.
336 * TODO: leak; this memory is never freed.
337 * It's arguable whether it's worth the trouble to care.
338 */
339 sd = kzalloc(sizeof(*sd), GFP_KERNEL);
340 if (!sd) {
341 printk(KERN_ERR "PCI: OOM, not probing PCI bus %02x\n", busnum);
342 return NULL;
343 }
344
345 sd->node = get_mp_bus_to_node(busnum);
346
347 printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
348 bus = pci_scan_bus_parented(NULL, busnum, &pci_root_ops, sd);
349 if (!bus)
350 kfree(sd);
351
352 return bus;
353 }
354
355 extern u8 pci_cache_line_size;
356
357 static int __init pcibios_init(void)
358 {
359 struct cpuinfo_x86 *c = &boot_cpu_data;
360
361 if (!raw_pci_ops) {
362 printk(KERN_WARNING "PCI: System does not support PCI\n");
363 return 0;
364 }
365
366 /*
367 * Assume PCI cacheline size of 32 bytes for all x86s except K7/K8
368 * and P4. It's also good for 386/486s (which actually have 16)
369 * as quite a few PCI devices do not support smaller values.
370 */
371 pci_cache_line_size = 32 >> 2;
372 if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
373 pci_cache_line_size = 64 >> 2; /* K7 & K8 */
374 else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
375 pci_cache_line_size = 128 >> 2; /* P4 */
376
377 pcibios_resource_survey();
378
379 if (pci_bf_sort >= pci_force_bf)
380 pci_sort_breadthfirst();
381 return 0;
382 }
383
384 subsys_initcall(pcibios_init);
385
386 char * __devinit pcibios_setup(char *str)
387 {
388 if (!strcmp(str, "off")) {
389 pci_probe = 0;
390 return NULL;
391 } else if (!strcmp(str, "bfsort")) {
392 pci_bf_sort = pci_force_bf;
393 return NULL;
394 } else if (!strcmp(str, "nobfsort")) {
395 pci_bf_sort = pci_force_nobf;
396 return NULL;
397 }
398 #ifdef CONFIG_PCI_BIOS
399 else if (!strcmp(str, "bios")) {
400 pci_probe = PCI_PROBE_BIOS;
401 return NULL;
402 } else if (!strcmp(str, "nobios")) {
403 pci_probe &= ~PCI_PROBE_BIOS;
404 return NULL;
405 } else if (!strcmp(str, "biosirq")) {
406 pci_probe |= PCI_BIOS_IRQ_SCAN;
407 return NULL;
408 } else if (!strncmp(str, "pirqaddr=", 9)) {
409 pirq_table_addr = simple_strtoul(str+9, NULL, 0);
410 return NULL;
411 }
412 #endif
413 #ifdef CONFIG_PCI_DIRECT
414 else if (!strcmp(str, "conf1")) {
415 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
416 return NULL;
417 }
418 else if (!strcmp(str, "conf2")) {
419 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
420 return NULL;
421 }
422 #endif
423 #ifdef CONFIG_PCI_MMCONFIG
424 else if (!strcmp(str, "nommconf")) {
425 pci_probe &= ~PCI_PROBE_MMCONF;
426 return NULL;
427 }
428 else if (!strcmp(str, "check_enable_amd_mmconf")) {
429 pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
430 return NULL;
431 }
432 #endif
433 else if (!strcmp(str, "noacpi")) {
434 acpi_noirq_set();
435 return NULL;
436 }
437 else if (!strcmp(str, "noearly")) {
438 pci_probe |= PCI_PROBE_NOEARLY;
439 return NULL;
440 }
441 #ifndef CONFIG_X86_VISWS
442 else if (!strcmp(str, "usepirqmask")) {
443 pci_probe |= PCI_USE_PIRQ_MASK;
444 return NULL;
445 } else if (!strncmp(str, "irqmask=", 8)) {
446 pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
447 return NULL;
448 } else if (!strncmp(str, "lastbus=", 8)) {
449 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
450 return NULL;
451 }
452 #endif
453 else if (!strcmp(str, "rom")) {
454 pci_probe |= PCI_ASSIGN_ROMS;
455 return NULL;
456 } else if (!strcmp(str, "assign-busses")) {
457 pci_probe |= PCI_ASSIGN_ALL_BUSSES;
458 return NULL;
459 } else if (!strcmp(str, "use_crs")) {
460 pci_probe |= PCI_USE__CRS;
461 return NULL;
462 } else if (!strcmp(str, "routeirq")) {
463 pci_routeirq = 1;
464 return NULL;
465 }
466 return str;
467 }
468
469 unsigned int pcibios_assign_all_busses(void)
470 {
471 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
472 }
473
474 int pcibios_enable_device(struct pci_dev *dev, int mask)
475 {
476 int err;
477
478 if ((err = pci_enable_resources(dev, mask)) < 0)
479 return err;
480
481 if (!dev->msi_enabled)
482 return pcibios_enable_irq(dev);
483 return 0;
484 }
485
486 void pcibios_disable_device (struct pci_dev *dev)
487 {
488 if (!dev->msi_enabled && pcibios_disable_irq)
489 pcibios_disable_irq(dev);
490 }
491
492 struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node)
493 {
494 struct pci_bus *bus = NULL;
495 struct pci_sysdata *sd;
496
497 /*
498 * Allocate per-root-bus (not per bus) arch-specific data.
499 * TODO: leak; this memory is never freed.
500 * It's arguable whether it's worth the trouble to care.
501 */
502 sd = kzalloc(sizeof(*sd), GFP_KERNEL);
503 if (!sd) {
504 printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busno);
505 return NULL;
506 }
507 sd->node = node;
508 bus = pci_scan_bus(busno, ops, sd);
509 if (!bus)
510 kfree(sd);
511
512 return bus;
513 }
514
515 struct pci_bus *pci_scan_bus_with_sysdata(int busno)
516 {
517 return pci_scan_bus_on_node(busno, &pci_root_ops, -1);
518 }