arch/x86/pci/intel_mid_pci.c

   1 /*
   2  * Intel MID PCI support
   3  *   Copyright (c) 2008 Intel Corporation
   4  *     Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Moorestown has an interesting PCI implementation:
   7  *   - configuration space is memory mapped (as defined by MCFG)
   8  *   - Lincroft devices also have a real, type 1 configuration space
   9  *   - Early Lincroft silicon has a type 1 access bug that will cause
  10  *     a hang if non-existent devices are accessed
  11  *   - some devices have the "fixed BAR" capability, which means
  12  *     they can't be relocated or modified; check for that during
  13  *     BAR sizing
  14  *
  15  * So, we use the MCFG space for all reads and writes, but also send
  16  * Lincroft writes to type 1 space.  But only read/write if the device
  17  * actually exists, otherwise return all 1s for reads and bit bucket
  18  * the writes.
  19  */
  20
  21 #include <linux/sched.h>
  22 #include <linux/pci.h>
  23 #include <linux/ioport.h>
  24 #include <linux/init.h>
  25 #include <linux/dmi.h>
  26 #include <linux/acpi.h>
  27 #include <linux/io.h>
  28 #include <linux/smp.h>
  29
  30 #include <asm/segment.h>
  31 #include <asm/pci_x86.h>
  32 #include <asm/hw_irq.h>
  33 #include <asm/io_apic.h>
  34 #include <asm/intel-mid.h>
  35
  36 #define PCIE_CAP_OFFSET 0x100
  37
  38 /* Quirks for the listed devices */
  39 #define PCI_DEVICE_ID_INTEL_MRFL_MMC    0x1190
  40
  41 /* Fixed BAR fields */
  42 #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
  43 #define PCI_FIXED_BAR_0_SIZE    0x04
  44 #define PCI_FIXED_BAR_1_SIZE    0x08
  45 #define PCI_FIXED_BAR_2_SIZE    0x0c
  46 #define PCI_FIXED_BAR_3_SIZE    0x10
  47 #define PCI_FIXED_BAR_4_SIZE    0x14
  48 #define PCI_FIXED_BAR_5_SIZE    0x1c
  49
  50 static int pci_soc_mode;
  51
  52 /**
  53  * fixed_bar_cap - return the offset of the fixed BAR cap if found
  54  * @bus: PCI bus
  55  * @devfn: device in question
  56  *
  57  * Look for the fixed BAR cap on @bus and @devfn, returning its offset
  58  * if found or 0 otherwise.
  59  */
  60 static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
  61 {
  62         int pos;
  63         u32 pcie_cap = 0, cap_data;
  64
  65         pos = PCIE_CAP_OFFSET;
  66
  67         if (!raw_pci_ext_ops)
  68                 return 0;
  69
  70         while (pos) {
  71                 if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
  72                                           devfn, pos, 4, &pcie_cap))
  73                         return 0;
  74
  75                 if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
  76                         PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
  77                         break;
  78
  79                 if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
  80                         raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
  81                                               devfn, pos + 4, 4, &cap_data);
  82                         if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
  83                                 return pos;
  84                 }
  85
  86                 pos = PCI_EXT_CAP_NEXT(pcie_cap);
  87         }
  88
  89         return 0;
  90 }
  91
  92 static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
  93                                    int reg, int len, u32 val, int offset)
  94 {
  95         u32 size;
  96         unsigned int domain, busnum;
  97         int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
  98
  99         domain = pci_domain_nr(bus);
 100         busnum = bus->number;
 101
 102         if (val == ~0 && len == 4) {
 103                 unsigned long decode;
 104
 105                 raw_pci_ext_ops->read(domain, busnum, devfn,
 106                                offset + 8 + (bar * 4), 4, &size);
 107
 108                 /* Turn the size into a decode pattern for the sizing code */
 109                 if (size) {
 110                         decode = size - 1;
 111                         decode |= decode >> 1;
 112                         decode |= decode >> 2;
 113                         decode |= decode >> 4;
 114                         decode |= decode >> 8;
 115                         decode |= decode >> 16;
 116                         decode++;
 117                         decode = ~(decode - 1);
 118                 } else {
 119                         decode = 0;
 120                 }
 121
 122                 /*
 123                  * If val is all ones, the core code is trying to size the reg,
 124                  * so update the mmconfig space with the real size.
 125                  *
 126                  * Note: this assumes the fixed size we got is a power of two.
 127                  */
 128                 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
 129                                        decode);
 130         }
 131
 132         /* This is some other kind of BAR write, so just do it. */
 133         return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
 134 }
 135
 136 /**
 137  * type1_access_ok - check whether to use type 1
 138  * @bus: bus number
 139  * @devfn: device & function in question
 140  *
 141  * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
 142  * all, the we can go ahead with any reads & writes.  If it's on a Lincroft,
 143  * but doesn't exist, avoid the access altogether to keep the chip from
 144  * hanging.
 145  */
 146 static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
 147 {
 148         /*
 149          * This is a workaround for A0 LNC bug where PCI status register does
 150          * not have new CAP bit set. can not be written by SW either.
 151          *
 152          * PCI header type in real LNC indicates a single function device, this
 153          * will prevent probing other devices under the same function in PCI
 154          * shim. Therefore, use the header type in shim instead.
 155          */
 156         if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
 157                 return false;
 158         if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
 159                                 || devfn == PCI_DEVFN(0, 0)
 160                                 || devfn == PCI_DEVFN(3, 0)))
 161                 return true;
 162         return false; /* Langwell on others */
 163 }
 164
 165 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
 166                     int size, u32 *value)
 167 {
 168         if (type1_access_ok(bus->number, devfn, where))
 169                 return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
 170                                         devfn, where, size, value);
 171         return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
 172                               devfn, where, size, value);
 173 }
 174
 175 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
 176                      int size, u32 value)
 177 {
 178         int offset;
 179
 180         /*
 181          * On MRST, there is no PCI ROM BAR, this will cause a subsequent read
 182          * to ROM BAR return 0 then being ignored.
 183          */
 184         if (where == PCI_ROM_ADDRESS)
 185                 return 0;
 186
 187         /*
 188          * Devices with fixed BARs need special handling:
 189          *   - BAR sizing code will save, write ~0, read size, restore
 190          *   - so writes to fixed BARs need special handling
 191          *   - other writes to fixed BAR devices should go through mmconfig
 192          */
 193         offset = fixed_bar_cap(bus, devfn);
 194         if (offset &&
 195             (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
 196                 return pci_device_update_fixed(bus, devfn, where, size, value,
 197                                                offset);
 198         }
 199
 200         /*
 201          * On Moorestown update both real & mmconfig space
 202          * Note: early Lincroft silicon can't handle type 1 accesses to
 203          *       non-existent devices, so just eat the write in that case.
 204          */
 205         if (type1_access_ok(bus->number, devfn, where))
 206                 return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
 207                                               devfn, where, size, value);
 208         return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
 209                                where, size, value);
 210 }
 211
 212 static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 213 {
 214         struct irq_alloc_info info;
 215         int polarity;
 216         int ret;
 217
 218         if (pci_has_managed_irq(dev))
 219                 return 0;
 220
 221         switch (intel_mid_identify_cpu()) {
 222         case INTEL_MID_CPU_CHIP_TANGIER:
 223                 polarity = IOAPIC_POL_HIGH;
 224
 225                 /* Special treatment for IRQ0 */
 226                 if (dev->irq == 0) {
 227                         /*
 228                          * TNG has IRQ0 assigned to eMMC controller. But there
 229                          * are also other devices with bogus PCI configuration
 230                          * that have IRQ0 assigned. This check ensures that
 231                          * eMMC gets it.
 232                          */
 233                         if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)
 234                                 return -EBUSY;
 235                 }
 236                 break;
 237         default:
 238                 polarity = IOAPIC_POL_LOW;
 239                 break;
 240         }
 241
 242         ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity);
 243
 244         /*
 245          * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
 246          * IOAPIC RTE entries, so we just enable RTE for the device.
 247          */
 248         ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);
 249         if (ret < 0)
 250                 return ret;
 251
 252         dev->irq_managed = 1;
 253
 254         return 0;
 255 }
 256
 257 static void intel_mid_pci_irq_disable(struct pci_dev *dev)
 258 {
 259         if (pci_has_managed_irq(dev)) {
 260                 mp_unmap_irq(dev->irq);
 261                 dev->irq_managed = 0;
 262                 /*
 263                  * Don't reset dev->irq here, otherwise
 264                  * intel_mid_pci_irq_enable() will fail on next call.
 265                  */
 266         }
 267 }
 268
 269 static struct pci_ops intel_mid_pci_ops = {
 270         .read = pci_read,
 271         .write = pci_write,
 272 };
 273
 274 /**
 275  * intel_mid_pci_init - installs intel_mid_pci_ops
 276  *
 277  * Moorestown has an interesting PCI implementation (see above).
 278  * Called when the early platform detection installs it.
 279  */
 280 int __init intel_mid_pci_init(void)
 281 {
 282         pr_info("Intel MID platform detected, using MID PCI ops\n");
 283         pci_mmcfg_late_init();
 284         pcibios_enable_irq = intel_mid_pci_irq_enable;
 285         pcibios_disable_irq = intel_mid_pci_irq_disable;
 286         pci_root_ops = intel_mid_pci_ops;
 287         pci_soc_mode = 1;
 288         /* Continue with standard init */
 289         return 1;
 290 }
 291
 292 /*
 293  * Langwell devices are not true PCI devices; they are not subject to 10 ms
 294  * d3 to d0 delay required by PCI spec.
 295  */
 296 static void pci_d3delay_fixup(struct pci_dev *dev)
 297 {
 298         /*
 299          * PCI fixups are effectively decided compile time. If we have a dual
 300          * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
 301          */
 302         if (!pci_soc_mode)
 303                 return;
 304         /*
 305          * True PCI devices in Lincroft should allow type 1 access, the rest
 306          * are Langwell fake PCI devices.
 307          */
 308         if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
 309                 return;
 310         dev->d3_delay = 0;
 311 }
 312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
 313
 314 static void mrst_power_off_unused_dev(struct pci_dev *dev)
 315 {
 316         pci_set_power_state(dev, PCI_D3hot);
 317 }
 318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
 319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
 320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
 321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
 322
 323 /*
 324  * Langwell devices reside at fixed offsets, don't try to move them.
 325  */
 326 static void pci_fixed_bar_fixup(struct pci_dev *dev)
 327 {
 328         unsigned long offset;
 329         u32 size;
 330         int i;
 331
 332         if (!pci_soc_mode)
 333                 return;
 334
 335         /* Must have extended configuration space */
 336         if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
 337                 return;
 338
 339         /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
 340         offset = fixed_bar_cap(dev->bus, dev->devfn);
 341         if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
 342             PCI_DEVFN(2, 2) == dev->devfn)
 343                 return;
 344
 345         for (i = 0; i < PCI_ROM_RESOURCE; i++) {
 346                 pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
 347                 dev->resource[i].end = dev->resource[i].start + size - 1;
 348                 dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
 349         }
 350 }
 351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);