arch/x86/pci/pci.h

   1 /*
   2  *      Low-Level PCI Access for i386 machines.
   3  *
   4  *      (c) 1999 Martin Mares <mj@ucw.cz>
   5  */
   6
   7 #undef DEBUG
   8
   9 #ifdef DEBUG
  10 #define DBG(x...) printk(x)
  11 #else
  12 #define DBG(x...)
  13 #endif
  14
  15 #define PCI_PROBE_BIOS          0x0001
  16 #define PCI_PROBE_CONF1         0x0002
  17 #define PCI_PROBE_CONF2         0x0004
  18 #define PCI_PROBE_MMCONF        0x0008
  19 #define PCI_PROBE_MASK          0x000f
  20 #define PCI_PROBE_NOEARLY       0x0010
  21
  22 #define PCI_NO_CHECKS           0x0400
  23 #define PCI_USE_PIRQ_MASK       0x0800
  24 #define PCI_ASSIGN_ROMS         0x1000
  25 #define PCI_BIOS_IRQ_SCAN       0x2000
  26 #define PCI_ASSIGN_ALL_BUSSES   0x4000
  27 #define PCI_CAN_SKIP_ISA_ALIGN  0x8000
  28 #define PCI_USE__CRS            0x10000
  29
  30 extern unsigned int pci_probe;
  31 extern unsigned long pirq_table_addr;
  32
  33 enum pci_bf_sort_state {
  34         pci_bf_sort_default,
  35         pci_force_nobf,
  36         pci_force_bf,
  37         pci_dmi_bf,
  38 };
  39
  40 /* pci-i386.c */
  41
  42 extern unsigned int pcibios_max_latency;
  43
  44 void pcibios_resource_survey(void);
  45
  46 /* pci-pc.c */
  47
  48 extern int pcibios_last_bus;
  49 extern struct pci_bus *pci_root_bus;
  50 extern struct pci_ops pci_root_ops;
  51
  52 /* pci-irq.c */
  53
  54 struct irq_info {
  55         u8 bus, devfn;                  /* Bus, device and function */
  56         struct {
  57                 u8 link;                /* IRQ line ID, chipset dependent, 0=not routed */
  58                 u16 bitmap;             /* Available IRQs */
  59         } __attribute__((packed)) irq[4];
  60         u8 slot;                        /* Slot number, 0=onboard */
  61         u8 rfu;
  62 } __attribute__((packed));
  63
  64 struct irq_routing_table {
  65         u32 signature;                  /* PIRQ_SIGNATURE should be here */
  66         u16 version;                    /* PIRQ_VERSION */
  67         u16 size;                       /* Table size in bytes */
  68         u8 rtr_bus, rtr_devfn;          /* Where the interrupt router lies */
  69         u16 exclusive_irqs;             /* IRQs devoted exclusively to PCI usage */
  70         u16 rtr_vendor, rtr_device;     /* Vendor and device ID of interrupt router */
  71         u32 miniport_data;              /* Crap */
  72         u8 rfu[11];
  73         u8 checksum;                    /* Modulo 256 checksum must give zero */
  74         struct irq_info slots[0];
  75 } __attribute__((packed));
  76
  77 extern unsigned int pcibios_irq_mask;
  78
  79 extern int pcibios_scanned;
  80 extern spinlock_t pci_config_lock;
  81
  82 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
  83 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
  84
  85 struct pci_raw_ops {
  86         int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
  87                                                 int reg, int len, u32 *val);
  88         int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
  89                                                 int reg, int len, u32 val);
  90 };
  91
  92 extern struct pci_raw_ops *raw_pci_ops;
  93 extern struct pci_raw_ops *raw_pci_ext_ops;
  94
  95 extern struct pci_raw_ops pci_direct_conf1;
  96
  97 extern int pci_direct_probe(void);
  98 extern void pci_direct_init(int type);
  99 extern void pci_pcbios_init(void);
 100 extern void pci_mmcfg_init(int type);
 101 extern void pci_olpc_init(void);
 102
 103 /* pci-mmconfig.c */
 104
 105 extern int __init pci_mmcfg_arch_init(void);
 106
 107 /*
 108  * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
 109  * on their northbrige except through the * %eax register. As such, you MUST
 110  * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
 111  * accessor functions.
 112  * In fact just use pci_config_*, nothing else please.
 113  */
 114 static inline unsigned char mmio_config_readb(void __iomem *pos)
 115 {
 116         u8 val;
 117         asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
 118         return val;
 119 }
 120
 121 static inline unsigned short mmio_config_readw(void __iomem *pos)
 122 {
 123         u16 val;
 124         asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
 125         return val;
 126 }
 127
 128 static inline unsigned int mmio_config_readl(void __iomem *pos)
 129 {
 130         u32 val;
 131         asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
 132         return val;
 133 }
 134
 135 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
 136 {
 137         asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
 138 }
 139
 140 static inline void mmio_config_writew(void __iomem *pos, u16 val)
 141 {
 142         asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
 143 }
 144
 145 static inline void mmio_config_writel(void __iomem *pos, u32 val)
 146 {
 147         asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
 148 }