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1 /*
2 * SGI UltraViolet TLB flush routines.
3 *
4 * (c) 2008-2014 Cliff Wickman <cpw@sgi.com>, SGI.
5 *
6 * This code is released under the GNU General Public License version 2 or
7 * later.
8 */
9 #include <linux/seq_file.h>
10 #include <linux/proc_fs.h>
11 #include <linux/debugfs.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
15
16 #include <asm/mmu_context.h>
17 #include <asm/uv/uv.h>
18 #include <asm/uv/uv_mmrs.h>
19 #include <asm/uv/uv_hub.h>
20 #include <asm/uv/uv_bau.h>
21 #include <asm/apic.h>
22 #include <asm/tsc.h>
23 #include <asm/irq_vectors.h>
24 #include <asm/timer.h>
25
26 static struct bau_operations ops __ro_after_init;
27
28 /* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */
29 static int timeout_base_ns[] = {
30 20,
31 160,
32 1280,
33 10240,
34 81920,
35 655360,
36 5242880,
37 167772160
38 };
39
40 static int timeout_us;
41 static bool nobau = true;
42 static int nobau_perm;
43 static cycles_t congested_cycles;
44
45 /* tunables: */
46 static int max_concurr = MAX_BAU_CONCURRENT;
47 static int max_concurr_const = MAX_BAU_CONCURRENT;
48 static int plugged_delay = PLUGGED_DELAY;
49 static int plugsb4reset = PLUGSB4RESET;
50 static int giveup_limit = GIVEUP_LIMIT;
51 static int timeoutsb4reset = TIMEOUTSB4RESET;
52 static int ipi_reset_limit = IPI_RESET_LIMIT;
53 static int complete_threshold = COMPLETE_THRESHOLD;
54 static int congested_respns_us = CONGESTED_RESPONSE_US;
55 static int congested_reps = CONGESTED_REPS;
56 static int disabled_period = DISABLED_PERIOD;
57
58 static struct tunables tunables[] = {
59 {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */
60 {&plugged_delay, PLUGGED_DELAY},
61 {&plugsb4reset, PLUGSB4RESET},
62 {&timeoutsb4reset, TIMEOUTSB4RESET},
63 {&ipi_reset_limit, IPI_RESET_LIMIT},
64 {&complete_threshold, COMPLETE_THRESHOLD},
65 {&congested_respns_us, CONGESTED_RESPONSE_US},
66 {&congested_reps, CONGESTED_REPS},
67 {&disabled_period, DISABLED_PERIOD},
68 {&giveup_limit, GIVEUP_LIMIT}
69 };
70
71 static struct dentry *tunables_dir;
72 static struct dentry *tunables_file;
73
74 /* these correspond to the statistics printed by ptc_seq_show() */
75 static char *stat_description[] = {
76 "sent: number of shootdown messages sent",
77 "stime: time spent sending messages",
78 "numuvhubs: number of hubs targeted with shootdown",
79 "numuvhubs16: number times 16 or more hubs targeted",
80 "numuvhubs8: number times 8 or more hubs targeted",
81 "numuvhubs4: number times 4 or more hubs targeted",
82 "numuvhubs2: number times 2 or more hubs targeted",
83 "numuvhubs1: number times 1 hub targeted",
84 "numcpus: number of cpus targeted with shootdown",
85 "dto: number of destination timeouts",
86 "retries: destination timeout retries sent",
87 "rok: : destination timeouts successfully retried",
88 "resetp: ipi-style resource resets for plugs",
89 "resett: ipi-style resource resets for timeouts",
90 "giveup: fall-backs to ipi-style shootdowns",
91 "sto: number of source timeouts",
92 "bz: number of stay-busy's",
93 "throt: number times spun in throttle",
94 "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE",
95 "recv: shootdown messages received",
96 "rtime: time spent processing messages",
97 "all: shootdown all-tlb messages",
98 "one: shootdown one-tlb messages",
99 "mult: interrupts that found multiple messages",
100 "none: interrupts that found no messages",
101 "retry: number of retry messages processed",
102 "canc: number messages canceled by retries",
103 "nocan: number retries that found nothing to cancel",
104 "reset: number of ipi-style reset requests processed",
105 "rcan: number messages canceled by reset requests",
106 "disable: number times use of the BAU was disabled",
107 "enable: number times use of the BAU was re-enabled"
108 };
109
110 static int __init setup_bau(char *arg)
111 {
112 int result;
113
114 if (!arg)
115 return -EINVAL;
116
117 result = strtobool(arg, &nobau);
118 if (result)
119 return result;
120
121 /* we need to flip the logic here, so that bau=y sets nobau to false */
122 nobau = !nobau;
123
124 if (!nobau)
125 pr_info("UV BAU Enabled\n");
126 else
127 pr_info("UV BAU Disabled\n");
128
129 return 0;
130 }
131 early_param("bau", setup_bau);
132
133 /* base pnode in this partition */
134 static int uv_base_pnode __read_mostly;
135
136 static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
137 static DEFINE_PER_CPU(struct bau_control, bau_control);
138 static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask);
139
140 static void
141 set_bau_on(void)
142 {
143 int cpu;
144 struct bau_control *bcp;
145
146 if (nobau_perm) {
147 pr_info("BAU not initialized; cannot be turned on\n");
148 return;
149 }
150 nobau = false;
151 for_each_present_cpu(cpu) {
152 bcp = &per_cpu(bau_control, cpu);
153 bcp->nobau = false;
154 }
155 pr_info("BAU turned on\n");
156 return;
157 }
158
159 static void
160 set_bau_off(void)
161 {
162 int cpu;
163 struct bau_control *bcp;
164
165 nobau = true;
166 for_each_present_cpu(cpu) {
167 bcp = &per_cpu(bau_control, cpu);
168 bcp->nobau = true;
169 }
170 pr_info("BAU turned off\n");
171 return;
172 }
173
174 /*
175 * Determine the first node on a uvhub. 'Nodes' are used for kernel
176 * memory allocation.
177 */
178 static int __init uvhub_to_first_node(int uvhub)
179 {
180 int node, b;
181
182 for_each_online_node(node) {
183 b = uv_node_to_blade_id(node);
184 if (uvhub == b)
185 return node;
186 }
187 return -1;
188 }
189
190 /*
191 * Determine the apicid of the first cpu on a uvhub.
192 */
193 static int __init uvhub_to_first_apicid(int uvhub)
194 {
195 int cpu;
196
197 for_each_present_cpu(cpu)
198 if (uvhub == uv_cpu_to_blade_id(cpu))
199 return per_cpu(x86_cpu_to_apicid, cpu);
200 return -1;
201 }
202
203 /*
204 * Free a software acknowledge hardware resource by clearing its Pending
205 * bit. This will return a reply to the sender.
206 * If the message has timed out, a reply has already been sent by the
207 * hardware but the resource has not been released. In that case our
208 * clear of the Timeout bit (as well) will free the resource. No reply will
209 * be sent (the hardware will only do one reply per message).
210 */
211 static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp,
212 int do_acknowledge)
213 {
214 unsigned long dw;
215 struct bau_pq_entry *msg;
216
217 msg = mdp->msg;
218 if (!msg->canceled && do_acknowledge) {
219 dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec;
220 ops.write_l_sw_ack(dw);
221 }
222 msg->replied_to = 1;
223 msg->swack_vec = 0;
224 }
225
226 /*
227 * Process the receipt of a RETRY message
228 */
229 static void bau_process_retry_msg(struct msg_desc *mdp,
230 struct bau_control *bcp)
231 {
232 int i;
233 int cancel_count = 0;
234 unsigned long msg_res;
235 unsigned long mmr = 0;
236 struct bau_pq_entry *msg = mdp->msg;
237 struct bau_pq_entry *msg2;
238 struct ptc_stats *stat = bcp->statp;
239
240 stat->d_retries++;
241 /*
242 * cancel any message from msg+1 to the retry itself
243 */
244 for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
245 if (msg2 > mdp->queue_last)
246 msg2 = mdp->queue_first;
247 if (msg2 == msg)
248 break;
249
250 /* same conditions for cancellation as do_reset */
251 if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
252 (msg2->swack_vec) && ((msg2->swack_vec &
253 msg->swack_vec) == 0) &&
254 (msg2->sending_cpu == msg->sending_cpu) &&
255 (msg2->msg_type != MSG_NOOP)) {
256 mmr = ops.read_l_sw_ack();
257 msg_res = msg2->swack_vec;
258 /*
259 * This is a message retry; clear the resources held
260 * by the previous message only if they timed out.
261 * If it has not timed out we have an unexpected
262 * situation to report.
263 */
264 if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
265 unsigned long mr;
266 /*
267 * Is the resource timed out?
268 * Make everyone ignore the cancelled message.
269 */
270 msg2->canceled = 1;
271 stat->d_canceled++;
272 cancel_count++;
273 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
274 ops.write_l_sw_ack(mr);
275 }
276 }
277 }
278 if (!cancel_count)
279 stat->d_nocanceled++;
280 }
281
282 /*
283 * Do all the things a cpu should do for a TLB shootdown message.
284 * Other cpu's may come here at the same time for this message.
285 */
286 static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
287 int do_acknowledge)
288 {
289 short socket_ack_count = 0;
290 short *sp;
291 struct atomic_short *asp;
292 struct ptc_stats *stat = bcp->statp;
293 struct bau_pq_entry *msg = mdp->msg;
294 struct bau_control *smaster = bcp->socket_master;
295
296 /*
297 * This must be a normal message, or retry of a normal message
298 */
299 if (msg->address == TLB_FLUSH_ALL) {
300 local_flush_tlb();
301 stat->d_alltlb++;
302 } else {
303 __flush_tlb_one(msg->address);
304 stat->d_onetlb++;
305 }
306 stat->d_requestee++;
307
308 /*
309 * One cpu on each uvhub has the additional job on a RETRY
310 * of releasing the resource held by the message that is
311 * being retried. That message is identified by sending
312 * cpu number.
313 */
314 if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
315 bau_process_retry_msg(mdp, bcp);
316
317 /*
318 * This is a swack message, so we have to reply to it.
319 * Count each responding cpu on the socket. This avoids
320 * pinging the count's cache line back and forth between
321 * the sockets.
322 */
323 sp = &smaster->socket_acknowledge_count[mdp->msg_slot];
324 asp = (struct atomic_short *)sp;
325 socket_ack_count = atom_asr(1, asp);
326 if (socket_ack_count == bcp->cpus_in_socket) {
327 int msg_ack_count;
328 /*
329 * Both sockets dump their completed count total into
330 * the message's count.
331 */
332 *sp = 0;
333 asp = (struct atomic_short *)&msg->acknowledge_count;
334 msg_ack_count = atom_asr(socket_ack_count, asp);
335
336 if (msg_ack_count == bcp->cpus_in_uvhub) {
337 /*
338 * All cpus in uvhub saw it; reply
339 * (unless we are in the UV2 workaround)
340 */
341 reply_to_message(mdp, bcp, do_acknowledge);
342 }
343 }
344
345 return;
346 }
347
348 /*
349 * Determine the first cpu on a pnode.
350 */
351 static int pnode_to_first_cpu(int pnode, struct bau_control *smaster)
352 {
353 int cpu;
354 struct hub_and_pnode *hpp;
355
356 for_each_present_cpu(cpu) {
357 hpp = &smaster->thp[cpu];
358 if (pnode == hpp->pnode)
359 return cpu;
360 }
361 return -1;
362 }
363
364 /*
365 * Last resort when we get a large number of destination timeouts is
366 * to clear resources held by a given cpu.
367 * Do this with IPI so that all messages in the BAU message queue
368 * can be identified by their nonzero swack_vec field.
369 *
370 * This is entered for a single cpu on the uvhub.
371 * The sender want's this uvhub to free a specific message's
372 * swack resources.
373 */
374 static void do_reset(void *ptr)
375 {
376 int i;
377 struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id());
378 struct reset_args *rap = (struct reset_args *)ptr;
379 struct bau_pq_entry *msg;
380 struct ptc_stats *stat = bcp->statp;
381
382 stat->d_resets++;
383 /*
384 * We're looking for the given sender, and
385 * will free its swack resource.
386 * If all cpu's finally responded after the timeout, its
387 * message 'replied_to' was set.
388 */
389 for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
390 unsigned long msg_res;
391 /* do_reset: same conditions for cancellation as
392 bau_process_retry_msg() */
393 if ((msg->replied_to == 0) &&
394 (msg->canceled == 0) &&
395 (msg->sending_cpu == rap->sender) &&
396 (msg->swack_vec) &&
397 (msg->msg_type != MSG_NOOP)) {
398 unsigned long mmr;
399 unsigned long mr;
400 /*
401 * make everyone else ignore this message
402 */
403 msg->canceled = 1;
404 /*
405 * only reset the resource if it is still pending
406 */
407 mmr = ops.read_l_sw_ack();
408 msg_res = msg->swack_vec;
409 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
410 if (mmr & msg_res) {
411 stat->d_rcanceled++;
412 ops.write_l_sw_ack(mr);
413 }
414 }
415 }
416 return;
417 }
418
419 /*
420 * Use IPI to get all target uvhubs to release resources held by
421 * a given sending cpu number.
422 */
423 static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp)
424 {
425 int pnode;
426 int apnode;
427 int maskbits;
428 int sender = bcp->cpu;
429 cpumask_t *mask = bcp->uvhub_master->cpumask;
430 struct bau_control *smaster = bcp->socket_master;
431 struct reset_args reset_args;
432
433 reset_args.sender = sender;
434 cpumask_clear(mask);
435 /* find a single cpu for each uvhub in this distribution mask */
436 maskbits = sizeof(struct pnmask) * BITSPERBYTE;
437 /* each bit is a pnode relative to the partition base pnode */
438 for (pnode = 0; pnode < maskbits; pnode++) {
439 int cpu;
440 if (!bau_uvhub_isset(pnode, distribution))
441 continue;
442 apnode = pnode + bcp->partition_base_pnode;
443 cpu = pnode_to_first_cpu(apnode, smaster);
444 cpumask_set_cpu(cpu, mask);
445 }
446
447 /* IPI all cpus; preemption is already disabled */
448 smp_call_function_many(mask, do_reset, (void *)&reset_args, 1);
449 return;
450 }
451
452 /*
453 * Not to be confused with cycles_2_ns() from tsc.c; this gives a relative
454 * number, not an absolute. It converts a duration in cycles to a duration in
455 * ns.
456 */
457 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
458 {
459 struct cyc2ns_data data;
460 unsigned long long ns;
461
462 cyc2ns_read_begin(&data);
463 ns = mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift);
464 cyc2ns_read_end();
465
466 return ns;
467 }
468
469 /*
470 * The reverse of the above; converts a duration in ns to a duration in cycles.
471 */
472 static inline unsigned long long ns_2_cycles(unsigned long long ns)
473 {
474 struct cyc2ns_data data;
475 unsigned long long cyc;
476
477 cyc2ns_read_begin(&data);
478 cyc = (ns << data.cyc2ns_shift) / data.cyc2ns_mul;
479 cyc2ns_read_end();
480
481 return cyc;
482 }
483
484 static inline unsigned long cycles_2_us(unsigned long long cyc)
485 {
486 return cycles_2_ns(cyc) / NSEC_PER_USEC;
487 }
488
489 static inline cycles_t sec_2_cycles(unsigned long sec)
490 {
491 return ns_2_cycles(sec * NSEC_PER_SEC);
492 }
493
494 static inline unsigned long long usec_2_cycles(unsigned long usec)
495 {
496 return ns_2_cycles(usec * NSEC_PER_USEC);
497 }
498
499 /*
500 * wait for all cpus on this hub to finish their sends and go quiet
501 * leaves uvhub_quiesce set so that no new broadcasts are started by
502 * bau_flush_send_and_wait()
503 */
504 static inline void quiesce_local_uvhub(struct bau_control *hmaster)
505 {
506 atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce);
507 }
508
509 /*
510 * mark this quiet-requestor as done
511 */
512 static inline void end_uvhub_quiesce(struct bau_control *hmaster)
513 {
514 atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce);
515 }
516
517 static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
518 {
519 unsigned long descriptor_status;
520
521 descriptor_status = uv_read_local_mmr(mmr_offset);
522 descriptor_status >>= right_shift;
523 descriptor_status &= UV_ACT_STATUS_MASK;
524 return descriptor_status;
525 }
526
527 /*
528 * Wait for completion of a broadcast software ack message
529 * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
530 */
531 static int uv1_wait_completion(struct bau_desc *bau_desc,
532 struct bau_control *bcp, long try)
533 {
534 unsigned long descriptor_status;
535 cycles_t ttm;
536 u64 mmr_offset = bcp->status_mmr;
537 int right_shift = bcp->status_index;
538 struct ptc_stats *stat = bcp->statp;
539
540 descriptor_status = uv1_read_status(mmr_offset, right_shift);
541 /* spin on the status MMR, waiting for it to go idle */
542 while ((descriptor_status != DS_IDLE)) {
543 /*
544 * Our software ack messages may be blocked because
545 * there are no swack resources available. As long
546 * as none of them has timed out hardware will NACK
547 * our message and its state will stay IDLE.
548 */
549 if (descriptor_status == DS_SOURCE_TIMEOUT) {
550 stat->s_stimeout++;
551 return FLUSH_GIVEUP;
552 } else if (descriptor_status == DS_DESTINATION_TIMEOUT) {
553 stat->s_dtimeout++;
554 ttm = get_cycles();
555
556 /*
557 * Our retries may be blocked by all destination
558 * swack resources being consumed, and a timeout
559 * pending. In that case hardware returns the
560 * ERROR that looks like a destination timeout.
561 */
562 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
563 bcp->conseccompletes = 0;
564 return FLUSH_RETRY_PLUGGED;
565 }
566
567 bcp->conseccompletes = 0;
568 return FLUSH_RETRY_TIMEOUT;
569 } else {
570 /*
571 * descriptor_status is still BUSY
572 */
573 cpu_relax();
574 }
575 descriptor_status = uv1_read_status(mmr_offset, right_shift);
576 }
577 bcp->conseccompletes++;
578 return FLUSH_COMPLETE;
579 }
580
581 /*
582 * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register.
583 * But not currently used.
584 */
585 static unsigned long uv2_3_read_status(unsigned long offset, int rshft, int desc)
586 {
587 return ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1;
588 }
589
590 /*
591 * Entered when a bau descriptor has gone into a permanent busy wait because
592 * of a hardware bug.
593 * Workaround the bug.
594 */
595 static int handle_uv2_busy(struct bau_control *bcp)
596 {
597 struct ptc_stats *stat = bcp->statp;
598
599 stat->s_uv2_wars++;
600 bcp->busy = 1;
601 return FLUSH_GIVEUP;
602 }
603
604 static int uv2_3_wait_completion(struct bau_desc *bau_desc,
605 struct bau_control *bcp, long try)
606 {
607 unsigned long descriptor_stat;
608 cycles_t ttm;
609 u64 mmr_offset = bcp->status_mmr;
610 int right_shift = bcp->status_index;
611 int desc = bcp->uvhub_cpu;
612 long busy_reps = 0;
613 struct ptc_stats *stat = bcp->statp;
614
615 descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
616
617 /* spin on the status MMR, waiting for it to go idle */
618 while (descriptor_stat != UV2H_DESC_IDLE) {
619 if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT)) {
620 /*
621 * A h/w bug on the destination side may
622 * have prevented the message being marked
623 * pending, thus it doesn't get replied to
624 * and gets continually nacked until it times
625 * out with a SOURCE_TIMEOUT.
626 */
627 stat->s_stimeout++;
628 return FLUSH_GIVEUP;
629 } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
630 ttm = get_cycles();
631
632 /*
633 * Our retries may be blocked by all destination
634 * swack resources being consumed, and a timeout
635 * pending. In that case hardware returns the
636 * ERROR that looks like a destination timeout.
637 * Without using the extended status we have to
638 * deduce from the short time that this was a
639 * strong nack.
640 */
641 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
642 bcp->conseccompletes = 0;
643 stat->s_plugged++;
644 /* FLUSH_RETRY_PLUGGED causes hang on boot */
645 return FLUSH_GIVEUP;
646 }
647 stat->s_dtimeout++;
648 bcp->conseccompletes = 0;
649 /* FLUSH_RETRY_TIMEOUT causes hang on boot */
650 return FLUSH_GIVEUP;
651 } else {
652 busy_reps++;
653 if (busy_reps > 1000000) {
654 /* not to hammer on the clock */
655 busy_reps = 0;
656 ttm = get_cycles();
657 if ((ttm - bcp->send_message) > bcp->timeout_interval)
658 return handle_uv2_busy(bcp);
659 }
660 /*
661 * descriptor_stat is still BUSY
662 */
663 cpu_relax();
664 }
665 descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
666 }
667 bcp->conseccompletes++;
668 return FLUSH_COMPLETE;
669 }
670
671 /*
672 * Returns the status of current BAU message for cpu desc as a bit field
673 * [Error][Busy][Aux]
674 */
675 static u64 read_status(u64 status_mmr, int index, int desc)
676 {
677 u64 stat;
678
679 stat = ((read_lmmr(status_mmr) >> index) & UV_ACT_STATUS_MASK) << 1;
680 stat |= (read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_2) >> desc) & 0x1;
681
682 return stat;
683 }
684
685 static int uv4_wait_completion(struct bau_desc *bau_desc,
686 struct bau_control *bcp, long try)
687 {
688 struct ptc_stats *stat = bcp->statp;
689 u64 descriptor_stat;
690 u64 mmr = bcp->status_mmr;
691 int index = bcp->status_index;
692 int desc = bcp->uvhub_cpu;
693
694 descriptor_stat = read_status(mmr, index, desc);
695
696 /* spin on the status MMR, waiting for it to go idle */
697 while (descriptor_stat != UV2H_DESC_IDLE) {
698 switch (descriptor_stat) {
699 case UV2H_DESC_SOURCE_TIMEOUT:
700 stat->s_stimeout++;
701 return FLUSH_GIVEUP;
702
703 case UV2H_DESC_DEST_TIMEOUT:
704 stat->s_dtimeout++;
705 bcp->conseccompletes = 0;
706 return FLUSH_RETRY_TIMEOUT;
707
708 case UV2H_DESC_DEST_STRONG_NACK:
709 stat->s_plugged++;
710 bcp->conseccompletes = 0;
711 return FLUSH_RETRY_PLUGGED;
712
713 case UV2H_DESC_DEST_PUT_ERR:
714 bcp->conseccompletes = 0;
715 return FLUSH_GIVEUP;
716
717 default:
718 /* descriptor_stat is still BUSY */
719 cpu_relax();
720 }
721 descriptor_stat = read_status(mmr, index, desc);
722 }
723 bcp->conseccompletes++;
724 return FLUSH_COMPLETE;
725 }
726
727 /*
728 * Our retries are blocked by all destination sw ack resources being
729 * in use, and a timeout is pending. In that case hardware immediately
730 * returns the ERROR that looks like a destination timeout.
731 */
732 static void destination_plugged(struct bau_desc *bau_desc,
733 struct bau_control *bcp,
734 struct bau_control *hmaster, struct ptc_stats *stat)
735 {
736 udelay(bcp->plugged_delay);
737 bcp->plugged_tries++;
738
739 if (bcp->plugged_tries >= bcp->plugsb4reset) {
740 bcp->plugged_tries = 0;
741
742 quiesce_local_uvhub(hmaster);
743
744 spin_lock(&hmaster->queue_lock);
745 reset_with_ipi(&bau_desc->distribution, bcp);
746 spin_unlock(&hmaster->queue_lock);
747
748 end_uvhub_quiesce(hmaster);
749
750 bcp->ipi_attempts++;
751 stat->s_resets_plug++;
752 }
753 }
754
755 static void destination_timeout(struct bau_desc *bau_desc,
756 struct bau_control *bcp, struct bau_control *hmaster,
757 struct ptc_stats *stat)
758 {
759 hmaster->max_concurr = 1;
760 bcp->timeout_tries++;
761 if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
762 bcp->timeout_tries = 0;
763
764 quiesce_local_uvhub(hmaster);
765
766 spin_lock(&hmaster->queue_lock);
767 reset_with_ipi(&bau_desc->distribution, bcp);
768 spin_unlock(&hmaster->queue_lock);
769
770 end_uvhub_quiesce(hmaster);
771
772 bcp->ipi_attempts++;
773 stat->s_resets_timeout++;
774 }
775 }
776
777 /*
778 * Stop all cpus on a uvhub from using the BAU for a period of time.
779 * This is reversed by check_enable.
780 */
781 static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat)
782 {
783 int tcpu;
784 struct bau_control *tbcp;
785 struct bau_control *hmaster;
786 cycles_t tm1;
787
788 hmaster = bcp->uvhub_master;
789 spin_lock(&hmaster->disable_lock);
790 if (!bcp->baudisabled) {
791 stat->s_bau_disabled++;
792 tm1 = get_cycles();
793 for_each_present_cpu(tcpu) {
794 tbcp = &per_cpu(bau_control, tcpu);
795 if (tbcp->uvhub_master == hmaster) {
796 tbcp->baudisabled = 1;
797 tbcp->set_bau_on_time =
798 tm1 + bcp->disabled_period;
799 }
800 }
801 }
802 spin_unlock(&hmaster->disable_lock);
803 }
804
805 static void count_max_concurr(int stat, struct bau_control *bcp,
806 struct bau_control *hmaster)
807 {
808 bcp->plugged_tries = 0;
809 bcp->timeout_tries = 0;
810 if (stat != FLUSH_COMPLETE)
811 return;
812 if (bcp->conseccompletes <= bcp->complete_threshold)
813 return;
814 if (hmaster->max_concurr >= hmaster->max_concurr_const)
815 return;
816 hmaster->max_concurr++;
817 }
818
819 static void record_send_stats(cycles_t time1, cycles_t time2,
820 struct bau_control *bcp, struct ptc_stats *stat,
821 int completion_status, int try)
822 {
823 cycles_t elapsed;
824
825 if (time2 > time1) {
826 elapsed = time2 - time1;
827 stat->s_time += elapsed;
828
829 if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
830 bcp->period_requests++;
831 bcp->period_time += elapsed;
832 if ((elapsed > congested_cycles) &&
833 (bcp->period_requests > bcp->cong_reps) &&
834 ((bcp->period_time / bcp->period_requests) >
835 congested_cycles)) {
836 stat->s_congested++;
837 disable_for_period(bcp, stat);
838 }
839 }
840 } else
841 stat->s_requestor--;
842
843 if (completion_status == FLUSH_COMPLETE && try > 1)
844 stat->s_retriesok++;
845 else if (completion_status == FLUSH_GIVEUP) {
846 stat->s_giveup++;
847 if (get_cycles() > bcp->period_end)
848 bcp->period_giveups = 0;
849 bcp->period_giveups++;
850 if (bcp->period_giveups == 1)
851 bcp->period_end = get_cycles() + bcp->disabled_period;
852 if (bcp->period_giveups > bcp->giveup_limit) {
853 disable_for_period(bcp, stat);
854 stat->s_giveuplimit++;
855 }
856 }
857 }
858
859 /*
860 * Because of a uv1 hardware bug only a limited number of concurrent
861 * requests can be made.
862 */
863 static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat)
864 {
865 spinlock_t *lock = &hmaster->uvhub_lock;
866 atomic_t *v;
867
868 v = &hmaster->active_descriptor_count;
869 if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) {
870 stat->s_throttles++;
871 do {
872 cpu_relax();
873 } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr));
874 }
875 }
876
877 /*
878 * Handle the completion status of a message send.
879 */
880 static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
881 struct bau_control *bcp, struct bau_control *hmaster,
882 struct ptc_stats *stat)
883 {
884 if (completion_status == FLUSH_RETRY_PLUGGED)
885 destination_plugged(bau_desc, bcp, hmaster, stat);
886 else if (completion_status == FLUSH_RETRY_TIMEOUT)
887 destination_timeout(bau_desc, bcp, hmaster, stat);
888 }
889
890 /*
891 * Send a broadcast and wait for it to complete.
892 *
893 * The flush_mask contains the cpus the broadcast is to be sent to including
894 * cpus that are on the local uvhub.
895 *
896 * Returns 0 if all flushing represented in the mask was done.
897 * Returns 1 if it gives up entirely and the original cpu mask is to be
898 * returned to the kernel.
899 */
900 static int uv_flush_send_and_wait(struct cpumask *flush_mask,
901 struct bau_control *bcp,
902 struct bau_desc *bau_desc)
903 {
904 int seq_number = 0;
905 int completion_stat = 0;
906 int uv1 = 0;
907 long try = 0;
908 unsigned long index;
909 cycles_t time1;
910 cycles_t time2;
911 struct ptc_stats *stat = bcp->statp;
912 struct bau_control *hmaster = bcp->uvhub_master;
913 struct uv1_bau_msg_header *uv1_hdr = NULL;
914 struct uv2_3_bau_msg_header *uv2_3_hdr = NULL;
915
916 if (bcp->uvhub_version == UV_BAU_V1) {
917 uv1 = 1;
918 uv1_throttle(hmaster, stat);
919 }
920
921 while (hmaster->uvhub_quiesce)
922 cpu_relax();
923
924 time1 = get_cycles();
925 if (uv1)
926 uv1_hdr = &bau_desc->header.uv1_hdr;
927 else
928 /* uv2 and uv3 */
929 uv2_3_hdr = &bau_desc->header.uv2_3_hdr;
930
931 do {
932 if (try == 0) {
933 if (uv1)
934 uv1_hdr->msg_type = MSG_REGULAR;
935 else
936 uv2_3_hdr->msg_type = MSG_REGULAR;
937 seq_number = bcp->message_number++;
938 } else {
939 if (uv1)
940 uv1_hdr->msg_type = MSG_RETRY;
941 else
942 uv2_3_hdr->msg_type = MSG_RETRY;
943 stat->s_retry_messages++;
944 }
945
946 if (uv1)
947 uv1_hdr->sequence = seq_number;
948 else
949 uv2_3_hdr->sequence = seq_number;
950 index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu;
951 bcp->send_message = get_cycles();
952
953 write_mmr_activation(index);
954
955 try++;
956 completion_stat = ops.wait_completion(bau_desc, bcp, try);
957
958 handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
959
960 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
961 bcp->ipi_attempts = 0;
962 stat->s_overipilimit++;
963 completion_stat = FLUSH_GIVEUP;
964 break;
965 }
966 cpu_relax();
967 } while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
968 (completion_stat == FLUSH_RETRY_TIMEOUT));
969
970 time2 = get_cycles();
971
972 count_max_concurr(completion_stat, bcp, hmaster);
973
974 while (hmaster->uvhub_quiesce)
975 cpu_relax();
976
977 atomic_dec(&hmaster->active_descriptor_count);
978
979 record_send_stats(time1, time2, bcp, stat, completion_stat, try);
980
981 if (completion_stat == FLUSH_GIVEUP)
982 /* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */
983 return 1;
984 return 0;
985 }
986
987 /*
988 * The BAU is disabled for this uvhub. When the disabled time period has
989 * expired re-enable it.
990 * Return 0 if it is re-enabled for all cpus on this uvhub.
991 */
992 static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
993 {
994 int tcpu;
995 struct bau_control *tbcp;
996 struct bau_control *hmaster;
997
998 hmaster = bcp->uvhub_master;
999 spin_lock(&hmaster->disable_lock);
1000 if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) {
1001 stat->s_bau_reenabled++;
1002 for_each_present_cpu(tcpu) {
1003 tbcp = &per_cpu(bau_control, tcpu);
1004 if (tbcp->uvhub_master == hmaster) {
1005 tbcp->baudisabled = 0;
1006 tbcp->period_requests = 0;
1007 tbcp->period_time = 0;
1008 tbcp->period_giveups = 0;
1009 }
1010 }
1011 spin_unlock(&hmaster->disable_lock);
1012 return 0;
1013 }
1014 spin_unlock(&hmaster->disable_lock);
1015 return -1;
1016 }
1017
1018 static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs,
1019 int remotes, struct bau_desc *bau_desc)
1020 {
1021 stat->s_requestor++;
1022 stat->s_ntargcpu += remotes + locals;
1023 stat->s_ntargremotes += remotes;
1024 stat->s_ntarglocals += locals;
1025
1026 /* uvhub statistics */
1027 hubs = bau_uvhub_weight(&bau_desc->distribution);
1028 if (locals) {
1029 stat->s_ntarglocaluvhub++;
1030 stat->s_ntargremoteuvhub += (hubs - 1);
1031 } else
1032 stat->s_ntargremoteuvhub += hubs;
1033
1034 stat->s_ntarguvhub += hubs;
1035
1036 if (hubs >= 16)
1037 stat->s_ntarguvhub16++;
1038 else if (hubs >= 8)
1039 stat->s_ntarguvhub8++;
1040 else if (hubs >= 4)
1041 stat->s_ntarguvhub4++;
1042 else if (hubs >= 2)
1043 stat->s_ntarguvhub2++;
1044 else
1045 stat->s_ntarguvhub1++;
1046 }
1047
1048 /*
1049 * Translate a cpu mask to the uvhub distribution mask in the BAU
1050 * activation descriptor.
1051 */
1052 static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
1053 struct bau_desc *bau_desc, int *localsp, int *remotesp)
1054 {
1055 int cpu;
1056 int pnode;
1057 int cnt = 0;
1058 struct hub_and_pnode *hpp;
1059
1060 for_each_cpu(cpu, flush_mask) {
1061 /*
1062 * The distribution vector is a bit map of pnodes, relative
1063 * to the partition base pnode (and the partition base nasid
1064 * in the header).
1065 * Translate cpu to pnode and hub using a local memory array.
1066 */
1067 hpp = &bcp->socket_master->thp[cpu];
1068 pnode = hpp->pnode - bcp->partition_base_pnode;
1069 bau_uvhub_set(pnode, &bau_desc->distribution);
1070 cnt++;
1071 if (hpp->uvhub == bcp->uvhub)
1072 (*localsp)++;
1073 else
1074 (*remotesp)++;
1075 }
1076 if (!cnt)
1077 return 1;
1078 return 0;
1079 }
1080
1081 /*
1082 * globally purge translation cache of a virtual address or all TLB's
1083 * @cpumask: mask of all cpu's in which the address is to be removed
1084 * @mm: mm_struct containing virtual address range
1085 * @start: start virtual address to be removed from TLB
1086 * @end: end virtual address to be remove from TLB
1087 * @cpu: the current cpu
1088 *
1089 * This is the entry point for initiating any UV global TLB shootdown.
1090 *
1091 * Purges the translation caches of all specified processors of the given
1092 * virtual address, or purges all TLB's on specified processors.
1093 *
1094 * The caller has derived the cpumask from the mm_struct. This function
1095 * is called only if there are bits set in the mask. (e.g. flush_tlb_page())
1096 *
1097 * The cpumask is converted into a uvhubmask of the uvhubs containing
1098 * those cpus.
1099 *
1100 * Note that this function should be called with preemption disabled.
1101 *
1102 * Returns NULL if all remote flushing was done.
1103 * Returns pointer to cpumask if some remote flushing remains to be
1104 * done. The returned pointer is valid till preemption is re-enabled.
1105 */
1106 const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
1107 const struct flush_tlb_info *info)
1108 {
1109 unsigned int cpu = smp_processor_id();
1110 int locals = 0, remotes = 0, hubs = 0;
1111 struct bau_desc *bau_desc;
1112 struct cpumask *flush_mask;
1113 struct ptc_stats *stat;
1114 struct bau_control *bcp;
1115 unsigned long descriptor_status, status, address;
1116
1117 bcp = &per_cpu(bau_control, cpu);
1118
1119 if (bcp->nobau)
1120 return cpumask;
1121
1122 stat = bcp->statp;
1123 stat->s_enters++;
1124
1125 if (bcp->busy) {
1126 descriptor_status =
1127 read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0);
1128 status = ((descriptor_status >> (bcp->uvhub_cpu *
1129 UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1;
1130 if (status == UV2H_DESC_BUSY)
1131 return cpumask;
1132 bcp->busy = 0;
1133 }
1134
1135 /* bau was disabled due to slow response */
1136 if (bcp->baudisabled) {
1137 if (check_enable(bcp, stat)) {
1138 stat->s_ipifordisabled++;
1139 return cpumask;
1140 }
1141 }
1142
1143 /*
1144 * Each sending cpu has a per-cpu mask which it fills from the caller's
1145 * cpu mask. All cpus are converted to uvhubs and copied to the
1146 * activation descriptor.
1147 */
1148 flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
1149 /* don't actually do a shootdown of the local cpu */
1150 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
1151
1152 if (cpumask_test_cpu(cpu, cpumask))
1153 stat->s_ntargself++;
1154
1155 bau_desc = bcp->descriptor_base;
1156 bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu);
1157 bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
1158 if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
1159 return NULL;
1160
1161 record_send_statistics(stat, locals, hubs, remotes, bau_desc);
1162
1163 if (!info->end || (info->end - info->start) <= PAGE_SIZE)
1164 address = info->start;
1165 else
1166 address = TLB_FLUSH_ALL;
1167
1168 switch (bcp->uvhub_version) {
1169 case UV_BAU_V1:
1170 case UV_BAU_V2:
1171 case UV_BAU_V3:
1172 bau_desc->payload.uv1_2_3.address = address;
1173 bau_desc->payload.uv1_2_3.sending_cpu = cpu;
1174 break;
1175 case UV_BAU_V4:
1176 bau_desc->payload.uv4.address = address;
1177 bau_desc->payload.uv4.sending_cpu = cpu;
1178 bau_desc->payload.uv4.qualifier = BAU_DESC_QUALIFIER;
1179 break;
1180 }
1181
1182 /*
1183 * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
1184 * or 1 if it gave up and the original cpumask should be returned.
1185 */
1186 if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc))
1187 return NULL;
1188 else
1189 return cpumask;
1190 }
1191
1192 /*
1193 * Search the message queue for any 'other' unprocessed message with the
1194 * same software acknowledge resource bit vector as the 'msg' message.
1195 */
1196 static struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg,
1197 struct bau_control *bcp)
1198 {
1199 struct bau_pq_entry *msg_next = msg + 1;
1200 unsigned char swack_vec = msg->swack_vec;
1201
1202 if (msg_next > bcp->queue_last)
1203 msg_next = bcp->queue_first;
1204 while (msg_next != msg) {
1205 if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) &&
1206 (msg_next->swack_vec == swack_vec))
1207 return msg_next;
1208 msg_next++;
1209 if (msg_next > bcp->queue_last)
1210 msg_next = bcp->queue_first;
1211 }
1212 return NULL;
1213 }
1214
1215 /*
1216 * UV2 needs to work around a bug in which an arriving message has not
1217 * set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register.
1218 * Such a message must be ignored.
1219 */
1220 void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp)
1221 {
1222 unsigned long mmr_image;
1223 unsigned char swack_vec;
1224 struct bau_pq_entry *msg = mdp->msg;
1225 struct bau_pq_entry *other_msg;
1226
1227 mmr_image = ops.read_l_sw_ack();
1228 swack_vec = msg->swack_vec;
1229
1230 if ((swack_vec & mmr_image) == 0) {
1231 /*
1232 * This message was assigned a swack resource, but no
1233 * reserved acknowlegment is pending.
1234 * The bug has prevented this message from setting the MMR.
1235 */
1236 /*
1237 * Some message has set the MMR 'pending' bit; it might have
1238 * been another message. Look for that message.
1239 */
1240 other_msg = find_another_by_swack(msg, bcp);
1241 if (other_msg) {
1242 /*
1243 * There is another. Process this one but do not
1244 * ack it.
1245 */
1246 bau_process_message(mdp, bcp, 0);
1247 /*
1248 * Let the natural processing of that other message
1249 * acknowledge it. Don't get the processing of sw_ack's
1250 * out of order.
1251 */
1252 return;
1253 }
1254 }
1255
1256 /*
1257 * Either the MMR shows this one pending a reply or there is no
1258 * other message using this sw_ack, so it is safe to acknowledge it.
1259 */
1260 bau_process_message(mdp, bcp, 1);
1261
1262 return;
1263 }
1264
1265 /*
1266 * The BAU message interrupt comes here. (registered by set_intr_gate)
1267 * See entry_64.S
1268 *
1269 * We received a broadcast assist message.
1270 *
1271 * Interrupts are disabled; this interrupt could represent
1272 * the receipt of several messages.
1273 *
1274 * All cores/threads on this hub get this interrupt.
1275 * The last one to see it does the software ack.
1276 * (the resource will not be freed until noninterruptable cpus see this
1277 * interrupt; hardware may timeout the s/w ack and reply ERROR)
1278 */
1279 void uv_bau_message_interrupt(struct pt_regs *regs)
1280 {
1281 int count = 0;
1282 cycles_t time_start;
1283 struct bau_pq_entry *msg;
1284 struct bau_control *bcp;
1285 struct ptc_stats *stat;
1286 struct msg_desc msgdesc;
1287
1288 ack_APIC_irq();
1289 time_start = get_cycles();
1290
1291 bcp = &per_cpu(bau_control, smp_processor_id());
1292 stat = bcp->statp;
1293
1294 msgdesc.queue_first = bcp->queue_first;
1295 msgdesc.queue_last = bcp->queue_last;
1296
1297 msg = bcp->bau_msg_head;
1298 while (msg->swack_vec) {
1299 count++;
1300
1301 msgdesc.msg_slot = msg - msgdesc.queue_first;
1302 msgdesc.msg = msg;
1303 if (bcp->uvhub_version == UV_BAU_V2)
1304 process_uv2_message(&msgdesc, bcp);
1305 else
1306 /* no error workaround for uv1 or uv3 */
1307 bau_process_message(&msgdesc, bcp, 1);
1308
1309 msg++;
1310 if (msg > msgdesc.queue_last)
1311 msg = msgdesc.queue_first;
1312 bcp->bau_msg_head = msg;
1313 }
1314 stat->d_time += (get_cycles() - time_start);
1315 if (!count)
1316 stat->d_nomsg++;
1317 else if (count > 1)
1318 stat->d_multmsg++;
1319 }
1320
1321 /*
1322 * Each target uvhub (i.e. a uvhub that has cpu's) needs to have
1323 * shootdown message timeouts enabled. The timeout does not cause
1324 * an interrupt, but causes an error message to be returned to
1325 * the sender.
1326 */
1327 static void __init enable_timeouts(void)
1328 {
1329 int uvhub;
1330 int nuvhubs;
1331 int pnode;
1332 unsigned long mmr_image;
1333
1334 nuvhubs = uv_num_possible_blades();
1335
1336 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
1337 if (!uv_blade_nr_possible_cpus(uvhub))
1338 continue;
1339
1340 pnode = uv_blade_to_pnode(uvhub);
1341 mmr_image = read_mmr_misc_control(pnode);
1342 /*
1343 * Set the timeout period and then lock it in, in three
1344 * steps; captures and locks in the period.
1345 *
1346 * To program the period, the SOFT_ACK_MODE must be off.
1347 */
1348 mmr_image &= ~(1L << SOFTACK_MSHIFT);
1349 write_mmr_misc_control(pnode, mmr_image);
1350 /*
1351 * Set the 4-bit period.
1352 */
1353 mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT);
1354 mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT);
1355 write_mmr_misc_control(pnode, mmr_image);
1356 /*
1357 * UV1:
1358 * Subsequent reversals of the timebase bit (3) cause an
1359 * immediate timeout of one or all INTD resources as
1360 * indicated in bits 2:0 (7 causes all of them to timeout).
1361 */
1362 mmr_image |= (1L << SOFTACK_MSHIFT);
1363 if (is_uv2_hub()) {
1364 /* do not touch the legacy mode bit */
1365 /* hw bug workaround; do not use extended status */
1366 mmr_image &= ~(1L << UV2_EXT_SHFT);
1367 } else if (is_uv3_hub()) {
1368 mmr_image &= ~(1L << PREFETCH_HINT_SHFT);
1369 mmr_image |= (1L << SB_STATUS_SHFT);
1370 }
1371 write_mmr_misc_control(pnode, mmr_image);
1372 }
1373 }
1374
1375 static void *ptc_seq_start(struct seq_file *file, loff_t *offset)
1376 {
1377 if (*offset < num_possible_cpus())
1378 return offset;
1379 return NULL;
1380 }
1381
1382 static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
1383 {
1384 (*offset)++;
1385 if (*offset < num_possible_cpus())
1386 return offset;
1387 return NULL;
1388 }
1389
1390 static void ptc_seq_stop(struct seq_file *file, void *data)
1391 {
1392 }
1393
1394 /*
1395 * Display the statistics thru /proc/sgi_uv/ptc_statistics
1396 * 'data' points to the cpu number
1397 * Note: see the descriptions in stat_description[].
1398 */
1399 static int ptc_seq_show(struct seq_file *file, void *data)
1400 {
1401 struct ptc_stats *stat;
1402 struct bau_control *bcp;
1403 int cpu;
1404
1405 cpu = *(loff_t *)data;
1406 if (!cpu) {
1407 seq_puts(file,
1408 "# cpu bauoff sent stime self locals remotes ncpus localhub ");
1409 seq_puts(file, "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
1410 seq_puts(file,
1411 "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries ");
1412 seq_puts(file,
1413 "rok resetp resett giveup sto bz throt disable ");
1414 seq_puts(file,
1415 "enable wars warshw warwaits enters ipidis plugged ");
1416 seq_puts(file,
1417 "ipiover glim cong swack recv rtime all one mult ");
1418 seq_puts(file, "none retry canc nocan reset rcan\n");
1419 }
1420 if (cpu < num_possible_cpus() && cpu_online(cpu)) {
1421 bcp = &per_cpu(bau_control, cpu);
1422 if (bcp->nobau) {
1423 seq_printf(file, "cpu %d bau disabled\n", cpu);
1424 return 0;
1425 }
1426 stat = bcp->statp;
1427 /* source side statistics */
1428 seq_printf(file,
1429 "cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1430 cpu, bcp->nobau, stat->s_requestor,
1431 cycles_2_us(stat->s_time),
1432 stat->s_ntargself, stat->s_ntarglocals,
1433 stat->s_ntargremotes, stat->s_ntargcpu,
1434 stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub,
1435 stat->s_ntarguvhub, stat->s_ntarguvhub16);
1436 seq_printf(file, "%ld %ld %ld %ld %ld %ld ",
1437 stat->s_ntarguvhub8, stat->s_ntarguvhub4,
1438 stat->s_ntarguvhub2, stat->s_ntarguvhub1,
1439 stat->s_dtimeout, stat->s_strongnacks);
1440 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ",
1441 stat->s_retry_messages, stat->s_retriesok,
1442 stat->s_resets_plug, stat->s_resets_timeout,
1443 stat->s_giveup, stat->s_stimeout,
1444 stat->s_busy, stat->s_throttles);
1445 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1446 stat->s_bau_disabled, stat->s_bau_reenabled,
1447 stat->s_uv2_wars, stat->s_uv2_wars_hw,
1448 stat->s_uv2_war_waits, stat->s_enters,
1449 stat->s_ipifordisabled, stat->s_plugged,
1450 stat->s_overipilimit, stat->s_giveuplimit,
1451 stat->s_congested);
1452
1453 /* destination side statistics */
1454 seq_printf(file,
1455 "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n",
1456 ops.read_g_sw_ack(uv_cpu_to_pnode(cpu)),
1457 stat->d_requestee, cycles_2_us(stat->d_time),
1458 stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
1459 stat->d_nomsg, stat->d_retries, stat->d_canceled,
1460 stat->d_nocanceled, stat->d_resets,
1461 stat->d_rcanceled);
1462 }
1463 return 0;
1464 }
1465
1466 /*
1467 * Display the tunables thru debugfs
1468 */
1469 static ssize_t tunables_read(struct file *file, char __user *userbuf,
1470 size_t count, loff_t *ppos)
1471 {
1472 char *buf;
1473 int ret;
1474
1475 buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n",
1476 "max_concur plugged_delay plugsb4reset timeoutsb4reset",
1477 "ipi_reset_limit complete_threshold congested_response_us",
1478 "congested_reps disabled_period giveup_limit",
1479 max_concurr, plugged_delay, plugsb4reset,
1480 timeoutsb4reset, ipi_reset_limit, complete_threshold,
1481 congested_respns_us, congested_reps, disabled_period,
1482 giveup_limit);
1483
1484 if (!buf)
1485 return -ENOMEM;
1486
1487 ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
1488 kfree(buf);
1489 return ret;
1490 }
1491
1492 /*
1493 * handle a write to /proc/sgi_uv/ptc_statistics
1494 * -1: reset the statistics
1495 * 0: display meaning of the statistics
1496 */
1497 static ssize_t ptc_proc_write(struct file *file, const char __user *user,
1498 size_t count, loff_t *data)
1499 {
1500 int cpu;
1501 int i;
1502 int elements;
1503 long input_arg;
1504 char optstr[64];
1505 struct ptc_stats *stat;
1506
1507 if (count == 0 || count > sizeof(optstr))
1508 return -EINVAL;
1509 if (copy_from_user(optstr, user, count))
1510 return -EFAULT;
1511 optstr[count - 1] = '\0';
1512
1513 if (!strcmp(optstr, "on")) {
1514 set_bau_on();
1515 return count;
1516 } else if (!strcmp(optstr, "off")) {
1517 set_bau_off();
1518 return count;
1519 }
1520
1521 if (kstrtol(optstr, 10, &input_arg) < 0) {
1522 pr_debug("%s is invalid\n", optstr);
1523 return -EINVAL;
1524 }
1525
1526 if (input_arg == 0) {
1527 elements = ARRAY_SIZE(stat_description);
1528 pr_debug("# cpu: cpu number\n");
1529 pr_debug("Sender statistics:\n");
1530 for (i = 0; i < elements; i++)
1531 pr_debug("%s\n", stat_description[i]);
1532 } else if (input_arg == -1) {
1533 for_each_present_cpu(cpu) {
1534 stat = &per_cpu(ptcstats, cpu);
1535 memset(stat, 0, sizeof(struct ptc_stats));
1536 }
1537 }
1538
1539 return count;
1540 }
1541
1542 static int local_atoi(const char *name)
1543 {
1544 int val = 0;
1545
1546 for (;; name++) {
1547 switch (*name) {
1548 case '0' ... '9':
1549 val = 10*val+(*name-'0');
1550 break;
1551 default:
1552 return val;
1553 }
1554 }
1555 }
1556
1557 /*
1558 * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables.
1559 * Zero values reset them to defaults.
1560 */
1561 static int parse_tunables_write(struct bau_control *bcp, char *instr,
1562 int count)
1563 {
1564 char *p;
1565 char *q;
1566 int cnt = 0;
1567 int val;
1568 int e = ARRAY_SIZE(tunables);
1569
1570 p = instr + strspn(instr, WHITESPACE);
1571 q = p;
1572 for (; *p; p = q + strspn(q, WHITESPACE)) {
1573 q = p + strcspn(p, WHITESPACE);
1574 cnt++;
1575 if (q == p)
1576 break;
1577 }
1578 if (cnt != e) {
1579 pr_info("bau tunable error: should be %d values\n", e);
1580 return -EINVAL;
1581 }
1582
1583 p = instr + strspn(instr, WHITESPACE);
1584 q = p;
1585 for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) {
1586 q = p + strcspn(p, WHITESPACE);
1587 val = local_atoi(p);
1588 switch (cnt) {
1589 case 0:
1590 if (val == 0) {
1591 max_concurr = MAX_BAU_CONCURRENT;
1592 max_concurr_const = MAX_BAU_CONCURRENT;
1593 continue;
1594 }
1595 if (val < 1 || val > bcp->cpus_in_uvhub) {
1596 pr_debug(
1597 "Error: BAU max concurrent %d is invalid\n",
1598 val);
1599 return -EINVAL;
1600 }
1601 max_concurr = val;
1602 max_concurr_const = val;
1603 continue;
1604 default:
1605 if (val == 0)
1606 *tunables[cnt].tunp = tunables[cnt].deflt;
1607 else
1608 *tunables[cnt].tunp = val;
1609 continue;
1610 }
1611 if (q == p)
1612 break;
1613 }
1614 return 0;
1615 }
1616
1617 /*
1618 * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables)
1619 */
1620 static ssize_t tunables_write(struct file *file, const char __user *user,
1621 size_t count, loff_t *data)
1622 {
1623 int cpu;
1624 int ret;
1625 char instr[100];
1626 struct bau_control *bcp;
1627
1628 if (count == 0 || count > sizeof(instr)-1)
1629 return -EINVAL;
1630 if (copy_from_user(instr, user, count))
1631 return -EFAULT;
1632
1633 instr[count] = '\0';
1634
1635 cpu = get_cpu();
1636 bcp = &per_cpu(bau_control, cpu);
1637 ret = parse_tunables_write(bcp, instr, count);
1638 put_cpu();
1639 if (ret)
1640 return ret;
1641
1642 for_each_present_cpu(cpu) {
1643 bcp = &per_cpu(bau_control, cpu);
1644 bcp->max_concurr = max_concurr;
1645 bcp->max_concurr_const = max_concurr;
1646 bcp->plugged_delay = plugged_delay;
1647 bcp->plugsb4reset = plugsb4reset;
1648 bcp->timeoutsb4reset = timeoutsb4reset;
1649 bcp->ipi_reset_limit = ipi_reset_limit;
1650 bcp->complete_threshold = complete_threshold;
1651 bcp->cong_response_us = congested_respns_us;
1652 bcp->cong_reps = congested_reps;
1653 bcp->disabled_period = sec_2_cycles(disabled_period);
1654 bcp->giveup_limit = giveup_limit;
1655 }
1656 return count;
1657 }
1658
1659 static const struct seq_operations uv_ptc_seq_ops = {
1660 .start = ptc_seq_start,
1661 .next = ptc_seq_next,
1662 .stop = ptc_seq_stop,
1663 .show = ptc_seq_show
1664 };
1665
1666 static int ptc_proc_open(struct inode *inode, struct file *file)
1667 {
1668 return seq_open(file, &uv_ptc_seq_ops);
1669 }
1670
1671 static int tunables_open(struct inode *inode, struct file *file)
1672 {
1673 return 0;
1674 }
1675
1676 static const struct file_operations proc_uv_ptc_operations = {
1677 .open = ptc_proc_open,
1678 .read = seq_read,
1679 .write = ptc_proc_write,
1680 .llseek = seq_lseek,
1681 .release = seq_release,
1682 };
1683
1684 static const struct file_operations tunables_fops = {
1685 .open = tunables_open,
1686 .read = tunables_read,
1687 .write = tunables_write,
1688 .llseek = default_llseek,
1689 };
1690
1691 static int __init uv_ptc_init(void)
1692 {
1693 struct proc_dir_entry *proc_uv_ptc;
1694
1695 if (!is_uv_system())
1696 return 0;
1697
1698 proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL,
1699 &proc_uv_ptc_operations);
1700 if (!proc_uv_ptc) {
1701 pr_err("unable to create %s proc entry\n",
1702 UV_PTC_BASENAME);
1703 return -EINVAL;
1704 }
1705
1706 tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL);
1707 if (!tunables_dir) {
1708 pr_err("unable to create debugfs directory %s\n",
1709 UV_BAU_TUNABLES_DIR);
1710 return -EINVAL;
1711 }
1712 tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600,
1713 tunables_dir, NULL, &tunables_fops);
1714 if (!tunables_file) {
1715 pr_err("unable to create debugfs file %s\n",
1716 UV_BAU_TUNABLES_FILE);
1717 return -EINVAL;
1718 }
1719 return 0;
1720 }
1721
1722 /*
1723 * Initialize the sending side's sending buffers.
1724 */
1725 static void activation_descriptor_init(int node, int pnode, int base_pnode)
1726 {
1727 int i;
1728 int cpu;
1729 int uv1 = 0;
1730 unsigned long gpa;
1731 unsigned long m;
1732 unsigned long n;
1733 size_t dsize;
1734 struct bau_desc *bau_desc;
1735 struct bau_desc *bd2;
1736 struct uv1_bau_msg_header *uv1_hdr;
1737 struct uv2_3_bau_msg_header *uv2_3_hdr;
1738 struct bau_control *bcp;
1739
1740 /*
1741 * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC)
1742 * per cpu; and one per cpu on the uvhub (ADP_SZ)
1743 */
1744 dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC;
1745 bau_desc = kmalloc_node(dsize, GFP_KERNEL, node);
1746 BUG_ON(!bau_desc);
1747
1748 gpa = uv_gpa(bau_desc);
1749 n = uv_gpa_to_gnode(gpa);
1750 m = ops.bau_gpa_to_offset(gpa);
1751 if (is_uv1_hub())
1752 uv1 = 1;
1753
1754 /* the 14-bit pnode */
1755 write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m));
1756 /*
1757 * Initializing all 8 (ITEMS_PER_DESC) descriptors for each
1758 * cpu even though we only use the first one; one descriptor can
1759 * describe a broadcast to 256 uv hubs.
1760 */
1761 for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) {
1762 memset(bd2, 0, sizeof(struct bau_desc));
1763 if (uv1) {
1764 uv1_hdr = &bd2->header.uv1_hdr;
1765 uv1_hdr->swack_flag = 1;
1766 /*
1767 * The base_dest_nasid set in the message header
1768 * is the nasid of the first uvhub in the partition.
1769 * The bit map will indicate destination pnode numbers
1770 * relative to that base. They may not be consecutive
1771 * if nasid striding is being used.
1772 */
1773 uv1_hdr->base_dest_nasid =
1774 UV_PNODE_TO_NASID(base_pnode);
1775 uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID;
1776 uv1_hdr->command = UV_NET_ENDPOINT_INTD;
1777 uv1_hdr->int_both = 1;
1778 /*
1779 * all others need to be set to zero:
1780 * fairness chaining multilevel count replied_to
1781 */
1782 } else {
1783 /*
1784 * BIOS uses legacy mode, but uv2 and uv3 hardware always
1785 * uses native mode for selective broadcasts.
1786 */
1787 uv2_3_hdr = &bd2->header.uv2_3_hdr;
1788 uv2_3_hdr->swack_flag = 1;
1789 uv2_3_hdr->base_dest_nasid =
1790 UV_PNODE_TO_NASID(base_pnode);
1791 uv2_3_hdr->dest_subnodeid = UV_LB_SUBNODEID;
1792 uv2_3_hdr->command = UV_NET_ENDPOINT_INTD;
1793 }
1794 }
1795 for_each_present_cpu(cpu) {
1796 if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu)))
1797 continue;
1798 bcp = &per_cpu(bau_control, cpu);
1799 bcp->descriptor_base = bau_desc;
1800 }
1801 }
1802
1803 /*
1804 * initialize the destination side's receiving buffers
1805 * entered for each uvhub in the partition
1806 * - node is first node (kernel memory notion) on the uvhub
1807 * - pnode is the uvhub's physical identifier
1808 */
1809 static void pq_init(int node, int pnode)
1810 {
1811 int cpu;
1812 size_t plsize;
1813 char *cp;
1814 void *vp;
1815 unsigned long gnode, first, last, tail;
1816 struct bau_pq_entry *pqp;
1817 struct bau_control *bcp;
1818
1819 plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry);
1820 vp = kmalloc_node(plsize, GFP_KERNEL, node);
1821 pqp = (struct bau_pq_entry *)vp;
1822 BUG_ON(!pqp);
1823
1824 cp = (char *)pqp + 31;
1825 pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5);
1826
1827 for_each_present_cpu(cpu) {
1828 if (pnode != uv_cpu_to_pnode(cpu))
1829 continue;
1830 /* for every cpu on this pnode: */
1831 bcp = &per_cpu(bau_control, cpu);
1832 bcp->queue_first = pqp;
1833 bcp->bau_msg_head = pqp;
1834 bcp->queue_last = pqp + (DEST_Q_SIZE - 1);
1835 }
1836
1837 first = ops.bau_gpa_to_offset(uv_gpa(pqp));
1838 last = ops.bau_gpa_to_offset(uv_gpa(pqp + (DEST_Q_SIZE - 1)));
1839
1840 /*
1841 * Pre UV4, the gnode is required to locate the payload queue
1842 * and the payload queue tail must be maintained by the kernel.
1843 */
1844 bcp = &per_cpu(bau_control, smp_processor_id());
1845 if (bcp->uvhub_version <= UV_BAU_V3) {
1846 tail = first;
1847 gnode = uv_gpa_to_gnode(uv_gpa(pqp));
1848 first = (gnode << UV_PAYLOADQ_GNODE_SHIFT) | tail;
1849 write_mmr_payload_tail(pnode, tail);
1850 }
1851
1852 ops.write_payload_first(pnode, first);
1853 ops.write_payload_last(pnode, last);
1854
1855 /* in effect, all msg_type's are set to MSG_NOOP */
1856 memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE);
1857 }
1858
1859 /*
1860 * Initialization of each UV hub's structures
1861 */
1862 static void __init init_uvhub(int uvhub, int vector, int base_pnode)
1863 {
1864 int node;
1865 int pnode;
1866 unsigned long apicid;
1867
1868 node = uvhub_to_first_node(uvhub);
1869 pnode = uv_blade_to_pnode(uvhub);
1870
1871 activation_descriptor_init(node, pnode, base_pnode);
1872
1873 pq_init(node, pnode);
1874 /*
1875 * The below initialization can't be in firmware because the
1876 * messaging IRQ will be determined by the OS.
1877 */
1878 apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
1879 write_mmr_data_config(pnode, ((apicid << 32) | vector));
1880 }
1881
1882 /*
1883 * We will set BAU_MISC_CONTROL with a timeout period.
1884 * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
1885 * So the destination timeout period has to be calculated from them.
1886 */
1887 static int calculate_destination_timeout(void)
1888 {
1889 unsigned long mmr_image;
1890 int mult1;
1891 int mult2;
1892 int index;
1893 int base;
1894 int ret;
1895 unsigned long ts_ns;
1896
1897 if (is_uv1_hub()) {
1898 mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
1899 mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
1900 index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
1901 mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
1902 mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
1903 ts_ns = timeout_base_ns[index];
1904 ts_ns *= (mult1 * mult2);
1905 ret = ts_ns / 1000;
1906 } else {
1907 /* same destination timeout for uv2 and uv3 */
1908 /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */
1909 mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL);
1910 mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
1911 if (mmr_image & (1L << UV2_ACK_UNITS_SHFT))
1912 base = 80;
1913 else
1914 base = 10;
1915 mult1 = mmr_image & UV2_ACK_MASK;
1916 ret = mult1 * base;
1917 }
1918 return ret;
1919 }
1920
1921 static void __init init_per_cpu_tunables(void)
1922 {
1923 int cpu;
1924 struct bau_control *bcp;
1925
1926 for_each_present_cpu(cpu) {
1927 bcp = &per_cpu(bau_control, cpu);
1928 bcp->baudisabled = 0;
1929 if (nobau)
1930 bcp->nobau = true;
1931 bcp->statp = &per_cpu(ptcstats, cpu);
1932 /* time interval to catch a hardware stay-busy bug */
1933 bcp->timeout_interval = usec_2_cycles(2*timeout_us);
1934 bcp->max_concurr = max_concurr;
1935 bcp->max_concurr_const = max_concurr;
1936 bcp->plugged_delay = plugged_delay;
1937 bcp->plugsb4reset = plugsb4reset;
1938 bcp->timeoutsb4reset = timeoutsb4reset;
1939 bcp->ipi_reset_limit = ipi_reset_limit;
1940 bcp->complete_threshold = complete_threshold;
1941 bcp->cong_response_us = congested_respns_us;
1942 bcp->cong_reps = congested_reps;
1943 bcp->disabled_period = sec_2_cycles(disabled_period);
1944 bcp->giveup_limit = giveup_limit;
1945 spin_lock_init(&bcp->queue_lock);
1946 spin_lock_init(&bcp->uvhub_lock);
1947 spin_lock_init(&bcp->disable_lock);
1948 }
1949 }
1950
1951 /*
1952 * Scan all cpus to collect blade and socket summaries.
1953 */
1954 static int __init get_cpu_topology(int base_pnode,
1955 struct uvhub_desc *uvhub_descs,
1956 unsigned char *uvhub_mask)
1957 {
1958 int cpu;
1959 int pnode;
1960 int uvhub;
1961 int socket;
1962 struct bau_control *bcp;
1963 struct uvhub_desc *bdp;
1964 struct socket_desc *sdp;
1965
1966 for_each_present_cpu(cpu) {
1967 bcp = &per_cpu(bau_control, cpu);
1968
1969 memset(bcp, 0, sizeof(struct bau_control));
1970
1971 pnode = uv_cpu_hub_info(cpu)->pnode;
1972 if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) {
1973 pr_emerg(
1974 "cpu %d pnode %d-%d beyond %d; BAU disabled\n",
1975 cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE);
1976 return 1;
1977 }
1978
1979 bcp->osnode = cpu_to_node(cpu);
1980 bcp->partition_base_pnode = base_pnode;
1981
1982 uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
1983 *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
1984 bdp = &uvhub_descs[uvhub];
1985
1986 bdp->num_cpus++;
1987 bdp->uvhub = uvhub;
1988 bdp->pnode = pnode;
1989
1990 /* kludge: 'assuming' one node per socket, and assuming that
1991 disabling a socket just leaves a gap in node numbers */
1992 socket = bcp->osnode & 1;
1993 bdp->socket_mask |= (1 << socket);
1994 sdp = &bdp->socket[socket];
1995 sdp->cpu_number[sdp->num_cpus] = cpu;
1996 sdp->num_cpus++;
1997 if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
1998 pr_emerg("%d cpus per socket invalid\n",
1999 sdp->num_cpus);
2000 return 1;
2001 }
2002 }
2003 return 0;
2004 }
2005
2006 /*
2007 * Each socket is to get a local array of pnodes/hubs.
2008 */
2009 static void make_per_cpu_thp(struct bau_control *smaster)
2010 {
2011 int cpu;
2012 size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus();
2013
2014 smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode);
2015 memset(smaster->thp, 0, hpsz);
2016 for_each_present_cpu(cpu) {
2017 smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode;
2018 smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
2019 }
2020 }
2021
2022 /*
2023 * Each uvhub is to get a local cpumask.
2024 */
2025 static void make_per_hub_cpumask(struct bau_control *hmaster)
2026 {
2027 int sz = sizeof(cpumask_t);
2028
2029 hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode);
2030 }
2031
2032 /*
2033 * Initialize all the per_cpu information for the cpu's on a given socket,
2034 * given what has been gathered into the socket_desc struct.
2035 * And reports the chosen hub and socket masters back to the caller.
2036 */
2037 static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
2038 struct bau_control **smasterp,
2039 struct bau_control **hmasterp)
2040 {
2041 int i, cpu, uvhub_cpu;
2042 struct bau_control *bcp;
2043
2044 for (i = 0; i < sdp->num_cpus; i++) {
2045 cpu = sdp->cpu_number[i];
2046 bcp = &per_cpu(bau_control, cpu);
2047 bcp->cpu = cpu;
2048 if (i == 0) {
2049 *smasterp = bcp;
2050 if (!(*hmasterp))
2051 *hmasterp = bcp;
2052 }
2053 bcp->cpus_in_uvhub = bdp->num_cpus;
2054 bcp->cpus_in_socket = sdp->num_cpus;
2055 bcp->socket_master = *smasterp;
2056 bcp->uvhub = bdp->uvhub;
2057 if (is_uv1_hub())
2058 bcp->uvhub_version = UV_BAU_V1;
2059 else if (is_uv2_hub())
2060 bcp->uvhub_version = UV_BAU_V2;
2061 else if (is_uv3_hub())
2062 bcp->uvhub_version = UV_BAU_V3;
2063 else if (is_uv4_hub())
2064 bcp->uvhub_version = UV_BAU_V4;
2065 else {
2066 pr_emerg("uvhub version not 1, 2, 3, or 4\n");
2067 return 1;
2068 }
2069 bcp->uvhub_master = *hmasterp;
2070 uvhub_cpu = uv_cpu_blade_processor_id(cpu);
2071 bcp->uvhub_cpu = uvhub_cpu;
2072
2073 /*
2074 * The ERROR and BUSY status registers are located pairwise over
2075 * the STATUS_0 and STATUS_1 mmrs; each an array[32] of 2 bits.
2076 */
2077 if (uvhub_cpu < UV_CPUS_PER_AS) {
2078 bcp->status_mmr = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
2079 bcp->status_index = uvhub_cpu * UV_ACT_STATUS_SIZE;
2080 } else {
2081 bcp->status_mmr = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
2082 bcp->status_index = (uvhub_cpu - UV_CPUS_PER_AS)
2083 * UV_ACT_STATUS_SIZE;
2084 }
2085
2086 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
2087 pr_emerg("%d cpus per uvhub invalid\n",
2088 bcp->uvhub_cpu);
2089 return 1;
2090 }
2091 }
2092 return 0;
2093 }
2094
2095 /*
2096 * Summarize the blade and socket topology into the per_cpu structures.
2097 */
2098 static int __init summarize_uvhub_sockets(int nuvhubs,
2099 struct uvhub_desc *uvhub_descs,
2100 unsigned char *uvhub_mask)
2101 {
2102 int socket;
2103 int uvhub;
2104 unsigned short socket_mask;
2105
2106 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
2107 struct uvhub_desc *bdp;
2108 struct bau_control *smaster = NULL;
2109 struct bau_control *hmaster = NULL;
2110
2111 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
2112 continue;
2113
2114 bdp = &uvhub_descs[uvhub];
2115 socket_mask = bdp->socket_mask;
2116 socket = 0;
2117 while (socket_mask) {
2118 struct socket_desc *sdp;
2119 if ((socket_mask & 1)) {
2120 sdp = &bdp->socket[socket];
2121 if (scan_sock(sdp, bdp, &smaster, &hmaster))
2122 return 1;
2123 make_per_cpu_thp(smaster);
2124 }
2125 socket++;
2126 socket_mask = (socket_mask >> 1);
2127 }
2128 make_per_hub_cpumask(hmaster);
2129 }
2130 return 0;
2131 }
2132
2133 /*
2134 * initialize the bau_control structure for each cpu
2135 */
2136 static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
2137 {
2138 unsigned char *uvhub_mask;
2139 void *vp;
2140 struct uvhub_desc *uvhub_descs;
2141
2142 if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub())
2143 timeout_us = calculate_destination_timeout();
2144
2145 vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
2146 uvhub_descs = (struct uvhub_desc *)vp;
2147 memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
2148 uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
2149
2150 if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
2151 goto fail;
2152
2153 if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
2154 goto fail;
2155
2156 kfree(uvhub_descs);
2157 kfree(uvhub_mask);
2158 init_per_cpu_tunables();
2159 return 0;
2160
2161 fail:
2162 kfree(uvhub_descs);
2163 kfree(uvhub_mask);
2164 return 1;
2165 }
2166
2167 static const struct bau_operations uv1_bau_ops __initconst = {
2168 .bau_gpa_to_offset = uv_gpa_to_offset,
2169 .read_l_sw_ack = read_mmr_sw_ack,
2170 .read_g_sw_ack = read_gmmr_sw_ack,
2171 .write_l_sw_ack = write_mmr_sw_ack,
2172 .write_g_sw_ack = write_gmmr_sw_ack,
2173 .write_payload_first = write_mmr_payload_first,
2174 .write_payload_last = write_mmr_payload_last,
2175 .wait_completion = uv1_wait_completion,
2176 };
2177
2178 static const struct bau_operations uv2_3_bau_ops __initconst = {
2179 .bau_gpa_to_offset = uv_gpa_to_offset,
2180 .read_l_sw_ack = read_mmr_sw_ack,
2181 .read_g_sw_ack = read_gmmr_sw_ack,
2182 .write_l_sw_ack = write_mmr_sw_ack,
2183 .write_g_sw_ack = write_gmmr_sw_ack,
2184 .write_payload_first = write_mmr_payload_first,
2185 .write_payload_last = write_mmr_payload_last,
2186 .wait_completion = uv2_3_wait_completion,
2187 };
2188
2189 static const struct bau_operations uv4_bau_ops __initconst = {
2190 .bau_gpa_to_offset = uv_gpa_to_soc_phys_ram,
2191 .read_l_sw_ack = read_mmr_proc_sw_ack,
2192 .read_g_sw_ack = read_gmmr_proc_sw_ack,
2193 .write_l_sw_ack = write_mmr_proc_sw_ack,
2194 .write_g_sw_ack = write_gmmr_proc_sw_ack,
2195 .write_payload_first = write_mmr_proc_payload_first,
2196 .write_payload_last = write_mmr_proc_payload_last,
2197 .wait_completion = uv4_wait_completion,
2198 };
2199
2200 /*
2201 * Initialization of BAU-related structures
2202 */
2203 static int __init uv_bau_init(void)
2204 {
2205 int uvhub;
2206 int pnode;
2207 int nuvhubs;
2208 int cur_cpu;
2209 int cpus;
2210 int vector;
2211 cpumask_var_t *mask;
2212
2213 if (!is_uv_system())
2214 return 0;
2215
2216 if (is_uv4_hub())
2217 ops = uv4_bau_ops;
2218 else if (is_uv3_hub())
2219 ops = uv2_3_bau_ops;
2220 else if (is_uv2_hub())
2221 ops = uv2_3_bau_ops;
2222 else if (is_uv1_hub())
2223 ops = uv1_bau_ops;
2224
2225 for_each_possible_cpu(cur_cpu) {
2226 mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
2227 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
2228 }
2229
2230 nuvhubs = uv_num_possible_blades();
2231 congested_cycles = usec_2_cycles(congested_respns_us);
2232
2233 uv_base_pnode = 0x7fffffff;
2234 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
2235 cpus = uv_blade_nr_possible_cpus(uvhub);
2236 if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode))
2237 uv_base_pnode = uv_blade_to_pnode(uvhub);
2238 }
2239
2240 /* software timeouts are not supported on UV4 */
2241 if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub())
2242 enable_timeouts();
2243
2244 if (init_per_cpu(nuvhubs, uv_base_pnode)) {
2245 set_bau_off();
2246 nobau_perm = 1;
2247 return 0;
2248 }
2249
2250 vector = UV_BAU_MESSAGE;
2251 for_each_possible_blade(uvhub) {
2252 if (uv_blade_nr_possible_cpus(uvhub))
2253 init_uvhub(uvhub, vector, uv_base_pnode);
2254 }
2255
2256 alloc_intr_gate(vector, uv_bau_message_intr1);
2257
2258 for_each_possible_blade(uvhub) {
2259 if (uv_blade_nr_possible_cpus(uvhub)) {
2260 unsigned long val;
2261 unsigned long mmr;
2262 pnode = uv_blade_to_pnode(uvhub);
2263 /* INIT the bau */
2264 val = 1L << 63;
2265 write_gmmr_activation(pnode, val);
2266 mmr = 1; /* should be 1 to broadcast to both sockets */
2267 if (!is_uv1_hub())
2268 write_mmr_data_broadcast(pnode, mmr);
2269 }
2270 }
2271
2272 return 0;
2273 }
2274 core_initcall(uv_bau_init);
2275 fs_initcall(uv_ptc_init);