arch/x86/power/cpu.c

   1 /*
   2  * Suspend support specific for i386/x86-64.
   3  *
   4  * Distribute under GPLv2
   5  *
   6  * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
   7  * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
   8  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
   9  */
  10
  11 #include <linux/suspend.h>
  12 #include <linux/export.h>
  13 #include <linux/smp.h>
  14
  15 #include <asm/pgtable.h>
  16 #include <asm/proto.h>
  17 #include <asm/mtrr.h>
  18 #include <asm/page.h>
  19 #include <asm/mce.h>
  20 #include <asm/xcr.h>
  21 #include <asm/suspend.h>
  22 #include <asm/debugreg.h>
  23 #include <asm/fpu-internal.h> /* pcntxt_mask */
  24
  25 #ifdef CONFIG_X86_32
  26 static struct saved_context saved_context;
  27
  28 unsigned long saved_context_ebx;
  29 unsigned long saved_context_esp, saved_context_ebp;
  30 unsigned long saved_context_esi, saved_context_edi;
  31 unsigned long saved_context_eflags;
  32 #else
  33 /* CONFIG_X86_64 */
  34 struct saved_context saved_context;
  35 #endif
  36
  37 /**
  38  *      __save_processor_state - save CPU registers before creating a
  39  *              hibernation image and before restoring the memory state from it
  40  *      @ctxt - structure to store the registers contents in
  41  *
  42  *      NOTE: If there is a CPU register the modification of which by the
  43  *      boot kernel (ie. the kernel used for loading the hibernation image)
  44  *      might affect the operations of the restored target kernel (ie. the one
  45  *      saved in the hibernation image), then its contents must be saved by this
  46  *      function.  In other words, if kernel A is hibernated and different
  47  *      kernel B is used for loading the hibernation image into memory, the
  48  *      kernel A's __save_processor_state() function must save all registers
  49  *      needed by kernel A, so that it can operate correctly after the resume
  50  *      regardless of what kernel B does in the meantime.
  51  */
  52 static void __save_processor_state(struct saved_context *ctxt)
  53 {
  54 #ifdef CONFIG_X86_32
  55         mtrr_save_fixed_ranges(NULL);
  56 #endif
  57         kernel_fpu_begin();
  58
  59         /*
  60          * descriptor tables
  61          */
  62 #ifdef CONFIG_X86_32
  63         store_gdt(&ctxt->gdt);
  64         store_idt(&ctxt->idt);
  65 #else
  66 /* CONFIG_X86_64 */
  67         store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
  68         store_idt((struct desc_ptr *)&ctxt->idt_limit);
  69 #endif
  70         store_tr(ctxt->tr);
  71
  72         /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
  73         /*
  74          * segment registers
  75          */
  76 #ifdef CONFIG_X86_32
  77         savesegment(es, ctxt->es);
  78         savesegment(fs, ctxt->fs);
  79         savesegment(gs, ctxt->gs);
  80         savesegment(ss, ctxt->ss);
  81 #else
  82 /* CONFIG_X86_64 */
  83         asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
  84         asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
  85         asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
  86         asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
  87         asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
  88
  89         rdmsrl(MSR_FS_BASE, ctxt->fs_base);
  90         rdmsrl(MSR_GS_BASE, ctxt->gs_base);
  91         rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
  92         mtrr_save_fixed_ranges(NULL);
  93
  94         rdmsrl(MSR_EFER, ctxt->efer);
  95 #endif
  96
  97         /*
  98          * control registers
  99          */
 100         ctxt->cr0 = read_cr0();
 101         ctxt->cr2 = read_cr2();
 102         ctxt->cr3 = read_cr3();
 103 #ifdef CONFIG_X86_32
 104         ctxt->cr4 = read_cr4_safe();
 105 #else
 106 /* CONFIG_X86_64 */
 107         ctxt->cr4 = read_cr4();
 108         ctxt->cr8 = read_cr8();
 109 #endif
 110         ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
 111                                                &ctxt->misc_enable);
 112 }
 113
 114 /* Needed by apm.c */
 115 void save_processor_state(void)
 116 {
 117         __save_processor_state(&saved_context);
 118         x86_platform.save_sched_clock_state();
 119 }
 120 #ifdef CONFIG_X86_32
 121 EXPORT_SYMBOL(save_processor_state);
 122 #endif
 123
 124 static void do_fpu_end(void)
 125 {
 126         /*
 127          * Restore FPU regs if necessary.
 128          */
 129         kernel_fpu_end();
 130 }
 131
 132 static void fix_processor_context(void)
 133 {
 134         int cpu = smp_processor_id();
 135         struct tss_struct *t = &per_cpu(init_tss, cpu);
 136
 137         set_tss_desc(cpu, t);   /*
 138                                  * This just modifies memory; should not be
 139                                  * necessary. But... This is necessary, because
 140                                  * 386 hardware has concept of busy TSS or some
 141                                  * similar stupidity.
 142                                  */
 143
 144 #ifdef CONFIG_X86_64
 145         get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
 146
 147         syscall_init();                         /* This sets MSR_*STAR and related */
 148 #endif
 149         load_TR_desc();                         /* This does ltr */
 150         load_LDT(&current->active_mm->context); /* This does lldt */
 151 }
 152
 153 /**
 154  *      __restore_processor_state - restore the contents of CPU registers saved
 155  *              by __save_processor_state()
 156  *      @ctxt - structure to load the registers contents from
 157  */
 158 static void __restore_processor_state(struct saved_context *ctxt)
 159 {
 160         if (ctxt->misc_enable_saved)
 161                 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
 162         /*
 163          * control registers
 164          */
 165         /* cr4 was introduced in the Pentium CPU */
 166 #ifdef CONFIG_X86_32
 167         if (ctxt->cr4)
 168                 write_cr4(ctxt->cr4);
 169 #else
 170 /* CONFIG X86_64 */
 171         wrmsrl(MSR_EFER, ctxt->efer);
 172         write_cr8(ctxt->cr8);
 173         write_cr4(ctxt->cr4);
 174 #endif
 175         write_cr3(ctxt->cr3);
 176         write_cr2(ctxt->cr2);
 177         write_cr0(ctxt->cr0);
 178
 179         /*
 180          * now restore the descriptor tables to their proper values
 181          * ltr is done i fix_processor_context().
 182          */
 183 #ifdef CONFIG_X86_32
 184         load_gdt(&ctxt->gdt);
 185         load_idt(&ctxt->idt);
 186 #else
 187 /* CONFIG_X86_64 */
 188         load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
 189         load_idt((const struct desc_ptr *)&ctxt->idt_limit);
 190 #endif
 191
 192         /*
 193          * segment registers
 194          */
 195 #ifdef CONFIG_X86_32
 196         loadsegment(es, ctxt->es);
 197         loadsegment(fs, ctxt->fs);
 198         loadsegment(gs, ctxt->gs);
 199         loadsegment(ss, ctxt->ss);
 200
 201         /*
 202          * sysenter MSRs
 203          */
 204         if (boot_cpu_has(X86_FEATURE_SEP))
 205                 enable_sep_cpu();
 206 #else
 207 /* CONFIG_X86_64 */
 208         asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
 209         asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
 210         asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
 211         load_gs_index(ctxt->gs);
 212         asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
 213
 214         wrmsrl(MSR_FS_BASE, ctxt->fs_base);
 215         wrmsrl(MSR_GS_BASE, ctxt->gs_base);
 216         wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
 217 #endif
 218
 219         /*
 220          * restore XCR0 for xsave capable cpu's.
 221          */
 222         if (cpu_has_xsave)
 223                 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
 224
 225         fix_processor_context();
 226
 227         do_fpu_end();
 228         x86_platform.restore_sched_clock_state();
 229         mtrr_bp_restore();
 230 }
 231
 232 /* Needed by apm.c */
 233 void restore_processor_state(void)
 234 {
 235         __restore_processor_state(&saved_context);
 236 }
 237 #ifdef CONFIG_X86_32
 238 EXPORT_SYMBOL(restore_processor_state);
 239 #endif