1 // SPDX-License-Identifier: GPL-2.0-only
3 * Suspend support specific for i386/x86-64.
5 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
6 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
7 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
10 #include <linux/suspend.h>
11 #include <linux/export.h>
12 #include <linux/smp.h>
13 #include <linux/perf_event.h>
14 #include <linux/tboot.h>
15 #include <linux/dmi.h>
16 #include <linux/pgtable.h>
18 #include <asm/proto.h>
22 #include <asm/suspend.h>
23 #include <asm/fpu/api.h>
24 #include <asm/debugreg.h>
26 #include <asm/mmu_context.h>
27 #include <asm/cpu_device_id.h>
30 __visible
unsigned long saved_context_ebx
;
31 __visible
unsigned long saved_context_esp
, saved_context_ebp
;
32 __visible
unsigned long saved_context_esi
, saved_context_edi
;
33 __visible
unsigned long saved_context_eflags
;
35 struct saved_context saved_context
;
37 static void msr_save_context(struct saved_context
*ctxt
)
39 struct saved_msr
*msr
= ctxt
->saved_msrs
.array
;
40 struct saved_msr
*end
= msr
+ ctxt
->saved_msrs
.num
;
44 rdmsrl(msr
->info
.msr_no
, msr
->info
.reg
.q
);
49 static void msr_restore_context(struct saved_context
*ctxt
)
51 struct saved_msr
*msr
= ctxt
->saved_msrs
.array
;
52 struct saved_msr
*end
= msr
+ ctxt
->saved_msrs
.num
;
56 wrmsrl(msr
->info
.msr_no
, msr
->info
.reg
.q
);
62 * __save_processor_state() - Save CPU registers before creating a
63 * hibernation image and before restoring
64 * the memory state from it
65 * @ctxt: Structure to store the registers contents in.
67 * NOTE: If there is a CPU register the modification of which by the
68 * boot kernel (ie. the kernel used for loading the hibernation image)
69 * might affect the operations of the restored target kernel (ie. the one
70 * saved in the hibernation image), then its contents must be saved by this
71 * function. In other words, if kernel A is hibernated and different
72 * kernel B is used for loading the hibernation image into memory, the
73 * kernel A's __save_processor_state() function must save all registers
74 * needed by kernel A, so that it can operate correctly after the resume
75 * regardless of what kernel B does in the meantime.
77 static void __save_processor_state(struct saved_context
*ctxt
)
80 mtrr_save_fixed_ranges(NULL
);
87 store_idt(&ctxt
->idt
);
90 * We save it here, but restore it only in the hibernate case.
91 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
92 * mode in "secondary_startup_64". In 32-bit mode it is done via
93 * 'pmode_gdt' in wakeup_start.
95 ctxt
->gdt_desc
.size
= GDT_SIZE
- 1;
96 ctxt
->gdt_desc
.address
= (unsigned long)get_cpu_gdt_rw(smp_processor_id());
100 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
104 savesegment(gs
, ctxt
->gs
);
106 savesegment(fs
, ctxt
->fs
);
107 savesegment(ds
, ctxt
->ds
);
108 savesegment(es
, ctxt
->es
);
110 rdmsrl(MSR_FS_BASE
, ctxt
->fs_base
);
111 rdmsrl(MSR_GS_BASE
, ctxt
->kernelmode_gs_base
);
112 rdmsrl(MSR_KERNEL_GS_BASE
, ctxt
->usermode_gs_base
);
113 mtrr_save_fixed_ranges(NULL
);
115 rdmsrl(MSR_EFER
, ctxt
->efer
);
121 ctxt
->cr0
= read_cr0();
122 ctxt
->cr2
= read_cr2();
123 ctxt
->cr3
= __read_cr3();
124 ctxt
->cr4
= __read_cr4();
125 ctxt
->misc_enable_saved
= !rdmsrl_safe(MSR_IA32_MISC_ENABLE
,
127 msr_save_context(ctxt
);
130 /* Needed by apm.c */
131 void save_processor_state(void)
133 __save_processor_state(&saved_context
);
134 x86_platform
.save_sched_clock_state();
137 EXPORT_SYMBOL(save_processor_state
);
140 static void do_fpu_end(void)
143 * Restore FPU regs if necessary.
148 static void fix_processor_context(void)
150 int cpu
= smp_processor_id();
152 struct desc_struct
*desc
= get_cpu_gdt_rw(cpu
);
157 * We need to reload TR, which requires that we change the
158 * GDT entry to indicate "available" first.
160 * XXX: This could probably all be replaced by a call to
163 set_tss_desc(cpu
, &get_cpu_entry_area(cpu
)->tss
.x86_tss
);
166 memcpy(&tss
, &desc
[GDT_ENTRY_TSS
], sizeof(tss_desc
));
167 tss
.type
= 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
168 write_gdt_entry(desc
, GDT_ENTRY_TSS
, &tss
, DESC_TSS
);
170 syscall_init(); /* This sets MSR_*STAR and related */
172 if (boot_cpu_has(X86_FEATURE_SEP
))
175 load_TR_desc(); /* This does ltr */
176 load_mm_ldt(current
->active_mm
); /* This does lldt */
177 initialize_tlbstate_and_flush();
181 /* The processor is back on the direct GDT, load back the fixmap */
182 load_fixmap_gdt(cpu
);
186 * __restore_processor_state() - Restore the contents of CPU registers saved
187 * by __save_processor_state()
188 * @ctxt: Structure to load the registers contents from.
190 * The asm code that gets us here will have restored a usable GDT, although
191 * it will be pointing to the wrong alias.
193 static void notrace
__restore_processor_state(struct saved_context
*ctxt
)
195 struct cpuinfo_x86
*c
;
197 if (ctxt
->misc_enable_saved
)
198 wrmsrl(MSR_IA32_MISC_ENABLE
, ctxt
->misc_enable
);
202 /* cr4 was introduced in the Pentium CPU */
205 __write_cr4(ctxt
->cr4
);
208 wrmsrl(MSR_EFER
, ctxt
->efer
);
209 __write_cr4(ctxt
->cr4
);
211 write_cr3(ctxt
->cr3
);
212 write_cr2(ctxt
->cr2
);
213 write_cr0(ctxt
->cr0
);
215 /* Restore the IDT. */
216 load_idt(&ctxt
->idt
);
219 * Just in case the asm code got us here with the SS, DS, or ES
220 * out of sync with the GDT, update them.
222 loadsegment(ss
, __KERNEL_DS
);
223 loadsegment(ds
, __USER_DS
);
224 loadsegment(es
, __USER_DS
);
227 * Restore percpu access. Percpu access can happen in exception
228 * handlers or in complicated helpers like load_gs_index().
231 wrmsrl(MSR_GS_BASE
, ctxt
->kernelmode_gs_base
);
233 loadsegment(fs
, __KERNEL_PERCPU
);
236 /* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */
237 fix_processor_context();
240 * Now that we have descriptor tables fully restored and working
241 * exception handling, restore the usermode segments.
244 loadsegment(ds
, ctxt
->es
);
245 loadsegment(es
, ctxt
->es
);
246 loadsegment(fs
, ctxt
->fs
);
247 load_gs_index(ctxt
->gs
);
250 * Restore FSBASE and GSBASE after restoring the selectors, since
251 * restoring the selectors clobbers the bases. Keep in mind
252 * that MSR_KERNEL_GS_BASE is horribly misnamed.
254 wrmsrl(MSR_FS_BASE
, ctxt
->fs_base
);
255 wrmsrl(MSR_KERNEL_GS_BASE
, ctxt
->usermode_gs_base
);
257 loadsegment(gs
, ctxt
->gs
);
261 tsc_verify_tsc_adjust(true);
262 x86_platform
.restore_sched_clock_state();
264 perf_restore_debug_store();
265 msr_restore_context(ctxt
);
267 c
= &cpu_data(smp_processor_id());
268 if (cpu_has(c
, X86_FEATURE_MSR_IA32_FEAT_CTL
))
269 init_ia32_feat_ctl(c
);
272 /* Needed by apm.c */
273 void notrace
restore_processor_state(void)
275 __restore_processor_state(&saved_context
);
278 EXPORT_SYMBOL(restore_processor_state
);
281 #if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
282 static void resume_play_dead(void)
285 tboot_shutdown(TB_SHUTDOWN_WFS
);
289 int hibernate_resume_nonboot_cpu_disable(void)
291 void (*play_dead
)(void) = smp_ops
.play_dead
;
295 * Ensure that MONITOR/MWAIT will not be used in the "play dead" loop
296 * during hibernate image restoration, because it is likely that the
297 * monitored address will be actually written to at that time and then
298 * the "dead" CPU will attempt to execute instructions again, but the
299 * address in its instruction pointer may not be possible to resolve
300 * any more at that point (the page tables used by it previously may
301 * have been overwritten by hibernate image data).
303 * First, make sure that we wake up all the potentially disabled SMT
304 * threads which have been initially brought up and then put into
305 * mwait/cpuidle sleep.
306 * Those will be put to proper (not interfering with hibernation
307 * resume) sleep afterwards, and the resumed kernel will decide itself
308 * what to do with them.
310 ret
= cpuhp_smt_enable();
313 smp_ops
.play_dead
= resume_play_dead
;
314 ret
= freeze_secondary_cpus(0);
315 smp_ops
.play_dead
= play_dead
;
321 * When bsp_check() is called in hibernate and suspend, cpu hotplug
322 * is disabled already. So it's unnecessary to handle race condition between
323 * cpumask query and cpu hotplug.
325 static int bsp_check(void)
327 if (cpumask_first(cpu_online_mask
) != 0) {
328 pr_warn("CPU0 is offline.\n");
335 static int bsp_pm_callback(struct notifier_block
*nb
, unsigned long action
,
341 case PM_SUSPEND_PREPARE
:
342 case PM_HIBERNATION_PREPARE
:
345 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
346 case PM_RESTORE_PREPARE
:
348 * When system resumes from hibernation, online CPU0 because
349 * 1. it's required for resume and
350 * 2. the CPU was online before hibernation
353 _debug_hotplug_cpu(0, 1);
355 case PM_POST_RESTORE
:
357 * When a resume really happens, this code won't be called.
359 * This code is called only when user space hibernation software
360 * prepares for snapshot device during boot time. So we just
361 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
362 * preparing the snapshot device.
364 * This works for normal boot case in our CPU0 hotplug debug
365 * mode, i.e. CPU0 is offline and user mode hibernation
366 * software initializes during boot time.
368 * If CPU0 is online and user application accesses snapshot
369 * device after boot time, this will offline CPU0 and user may
370 * see different CPU0 state before and after accessing
371 * the snapshot device. But hopefully this is not a case when
372 * user debugging CPU0 hotplug. Even if users hit this case,
373 * they can easily online CPU0 back.
375 * To simplify this debug code, we only consider normal boot
376 * case. Otherwise we need to remember CPU0's state and restore
377 * to that state and resolve racy conditions etc.
379 _debug_hotplug_cpu(0, 0);
385 return notifier_from_errno(ret
);
388 static int __init
bsp_pm_check_init(void)
391 * Set this bsp_pm_callback as lower priority than
392 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
393 * earlier to disable cpu hotplug before bsp online check.
395 pm_notifier(bsp_pm_callback
, -INT_MAX
);
399 core_initcall(bsp_pm_check_init
);
401 static int msr_build_context(const u32
*msr_id
, const int num
)
403 struct saved_msrs
*saved_msrs
= &saved_context
.saved_msrs
;
404 struct saved_msr
*msr_array
;
408 total_num
= saved_msrs
->num
+ num
;
410 msr_array
= kmalloc_array(total_num
, sizeof(struct saved_msr
), GFP_KERNEL
);
412 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
416 if (saved_msrs
->array
) {
418 * Multiple callbacks can invoke this function, so copy any
419 * MSR save requests from previous invocations.
421 memcpy(msr_array
, saved_msrs
->array
,
422 sizeof(struct saved_msr
) * saved_msrs
->num
);
424 kfree(saved_msrs
->array
);
427 for (i
= saved_msrs
->num
, j
= 0; i
< total_num
; i
++, j
++) {
430 msr_array
[i
].info
.msr_no
= msr_id
[j
];
431 msr_array
[i
].valid
= !rdmsrl_safe(msr_id
[j
], &dummy
);
432 msr_array
[i
].info
.reg
.q
= 0;
434 saved_msrs
->num
= total_num
;
435 saved_msrs
->array
= msr_array
;
441 * The following sections are a quirk framework for problematic BIOSen:
442 * Sometimes MSRs are modified by the BIOSen after suspended to
443 * RAM, this might cause unexpected behavior after wakeup.
444 * Thus we save/restore these specified MSRs across suspend/resume
445 * in order to work around it.
447 * For any further problematic BIOSen/platforms,
448 * please add your own function similar to msr_initialize_bdw.
450 static int msr_initialize_bdw(const struct dmi_system_id
*d
)
452 /* Add any extra MSR ids into this array. */
453 u32 bdw_msr_id
[] = { MSR_IA32_THERM_CONTROL
};
455 pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d
->ident
);
456 return msr_build_context(bdw_msr_id
, ARRAY_SIZE(bdw_msr_id
));
459 static const struct dmi_system_id msr_save_dmi_table
[] = {
461 .callback
= msr_initialize_bdw
,
462 .ident
= "BROADWELL BDX_EP",
464 DMI_MATCH(DMI_PRODUCT_NAME
, "GRANTLEY"),
465 DMI_MATCH(DMI_PRODUCT_VERSION
, "E63448-400"),
471 static int msr_save_cpuid_features(const struct x86_cpu_id
*c
)
473 u32 cpuid_msr_id
[] = {
474 MSR_AMD64_CPUID_FN_1
,
477 pr_info("x86/pm: family %#hx cpu detected, MSR saving is needed during suspending.\n",
480 return msr_build_context(cpuid_msr_id
, ARRAY_SIZE(cpuid_msr_id
));
483 static const struct x86_cpu_id msr_save_cpu_table
[] = {
484 X86_MATCH_VENDOR_FAM(AMD
, 0x15, &msr_save_cpuid_features
),
485 X86_MATCH_VENDOR_FAM(AMD
, 0x16, &msr_save_cpuid_features
),
489 typedef int (*pm_cpu_match_t
)(const struct x86_cpu_id
*);
490 static int pm_cpu_check(const struct x86_cpu_id
*c
)
492 const struct x86_cpu_id
*m
;
495 m
= x86_match_cpu(msr_save_cpu_table
);
499 fn
= (pm_cpu_match_t
)m
->driver_data
;
506 static void pm_save_spec_msr(void)
508 u32 spec_msr_id
[] = {
512 MSR_IA32_MCU_OPT_CTRL
,
516 msr_build_context(spec_msr_id
, ARRAY_SIZE(spec_msr_id
));
519 static int pm_check_save_msr(void)
521 dmi_check_system(msr_save_dmi_table
);
522 pm_cpu_check(msr_save_cpu_table
);
528 device_initcall(pm_check_save_msr
);