2 #include <linux/slab.h>
3 #include <linux/memblock.h>
4 #include <linux/mem_encrypt.h>
6 #include <asm/set_memory.h>
7 #include <asm/pgtable.h>
8 #include <asm/realmode.h>
9 #include <asm/tlbflush.h>
11 struct real_mode_header
*real_mode_header
;
12 u32
*trampoline_cr4_features
;
14 /* Hold the pgd entry used on booting additional CPUs */
15 pgd_t trampoline_pgd_entry
;
17 void __init
set_real_mode_mem(phys_addr_t mem
, size_t size
)
19 void *base
= __va(mem
);
21 real_mode_header
= (struct real_mode_header
*) base
;
22 printk(KERN_DEBUG
"Base memory trampoline at [%p] %llx size %zu\n",
23 base
, (unsigned long long)mem
, size
);
26 void __init
reserve_real_mode(void)
29 size_t size
= real_mode_size_needed();
34 WARN_ON(slab_is_available());
36 /* Has to be under 1M so we can execute real-mode AP code. */
37 mem
= memblock_find_in_range(0, 1<<20, size
, PAGE_SIZE
);
39 pr_info("No sub-1M memory is available for the trampoline\n");
43 memblock_reserve(mem
, size
);
44 set_real_mode_mem(mem
, size
);
47 static void __init
setup_real_mode(void)
53 unsigned long phys_base
;
54 struct trampoline_header
*trampoline_header
;
55 size_t size
= PAGE_ALIGN(real_mode_blob_end
- real_mode_blob
);
61 base
= (unsigned char *)real_mode_header
;
64 * If SME is active, the trampoline area will need to be in
65 * decrypted memory in order to bring up other processors
68 set_memory_decrypted((unsigned long)base
, size
>> PAGE_SHIFT
);
70 memcpy(base
, real_mode_blob
, size
);
72 phys_base
= __pa(base
);
73 real_mode_seg
= phys_base
>> 4;
75 rel
= (u32
*) real_mode_relocs
;
77 /* 16-bit segment relocations. */
80 u16
*seg
= (u16
*) (base
+ *rel
++);
84 /* 32-bit linear relocations. */
87 u32
*ptr
= (u32
*) (base
+ *rel
++);
91 /* Must be perfomed *after* relocation. */
92 trampoline_header
= (struct trampoline_header
*)
93 __va(real_mode_header
->trampoline_header
);
96 trampoline_header
->start
= __pa_symbol(startup_32_smp
);
97 trampoline_header
->gdt_limit
= __BOOT_DS
+ 7;
98 trampoline_header
->gdt_base
= __pa_symbol(boot_gdt
);
101 * Some AMD processors will #GP(0) if EFER.LMA is set in WRMSR
102 * so we need to mask it out.
104 rdmsrl(MSR_EFER
, efer
);
105 trampoline_header
->efer
= efer
& ~EFER_LMA
;
107 trampoline_header
->start
= (u64
) secondary_startup_64
;
108 trampoline_cr4_features
= &trampoline_header
->cr4
;
109 *trampoline_cr4_features
= mmu_cr4_features
;
111 trampoline_header
->flags
= 0;
113 trampoline_header
->flags
|= TH_FLAGS_SME_ACTIVE
;
115 trampoline_pgd
= (u64
*) __va(real_mode_header
->trampoline_pgd
);
116 trampoline_pgd
[0] = trampoline_pgd_entry
.pgd
;
117 trampoline_pgd
[511] = init_top_pgt
[511].pgd
;
122 * reserve_real_mode() gets called very early, to guarantee the
123 * availability of low memory. This is before the proper kernel page
124 * tables are set up, so we cannot set page permissions in that
125 * function. Also trampoline code will be executed by APs so we
126 * need to mark it executable at do_pre_smp_initcalls() at least,
127 * thus run it as a early_initcall().
129 static void __init
set_real_mode_permissions(void)
131 unsigned char *base
= (unsigned char *) real_mode_header
;
132 size_t size
= PAGE_ALIGN(real_mode_blob_end
- real_mode_blob
);
135 PAGE_ALIGN(real_mode_header
->ro_end
) -
139 PAGE_ALIGN(real_mode_header
->ro_end
) -
140 real_mode_header
->text_start
;
142 unsigned long text_start
=
143 (unsigned long) __va(real_mode_header
->text_start
);
145 set_memory_nx((unsigned long) base
, size
>> PAGE_SHIFT
);
146 set_memory_ro((unsigned long) base
, ro_size
>> PAGE_SHIFT
);
147 set_memory_x((unsigned long) text_start
, text_size
>> PAGE_SHIFT
);
150 static int __init
init_real_mode(void)
152 if (!real_mode_header
)
153 panic("Real mode trampoline was not allocated");
156 set_real_mode_permissions();
160 early_initcall(init_real_mode
);