1 #include <linux/linkage.h>
2 #include <linux/config.h>
3 #include <linux/errno.h>
4 #include <linux/signal.h>
5 #include <linux/sched.h>
6 #include <linux/ioport.h>
7 #include <linux/interrupt.h>
8 #include <linux/timex.h>
9 #include <linux/slab.h>
10 #include <linux/random.h>
11 #include <linux/smp_lock.h>
12 #include <linux/init.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/sysdev.h>
15 #include <linux/bitops.h>
18 #include <asm/atomic.h>
19 #include <asm/system.h>
22 #include <asm/hw_irq.h>
23 #include <asm/pgtable.h>
24 #include <asm/delay.h>
28 #include <linux/irq.h>
31 * Common place to define all x86 IRQ vectors
33 * This builds up the IRQ handler stubs using some ugly macros in irq.h
35 * These macros create the low-level assembly IRQ routines that save
36 * register context and call do_IRQ(). do_IRQ() then does all the
37 * operations that are needed to keep the AT (or SMP IOAPIC)
38 * interrupt-controller happy.
44 #define BUILD_16_IRQS(x) \
45 BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
46 BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
47 BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
48 BI(x,c) BI(x,d) BI(x,e) BI(x,f)
50 #define BUILD_14_IRQS(x) \
51 BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
52 BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
53 BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
57 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
58 * (these are usually mapped to vectors 0x20-0x2f)
62 #ifdef CONFIG_X86_LOCAL_APIC
64 * The IO-APIC gives us many more interrupt sources. Most of these
65 * are unused but an SMP system is supposed to have enough memory ...
66 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
67 * across the spectrum, so we really want to be prepared to get all
68 * of these. Plus, more powerful systems might have more than 64
71 * (these are usually mapped into the 0x30-0xff vector range)
73 BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
74 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
75 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
76 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
92 #define IRQLIST_16(x) \
93 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
94 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
95 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
96 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
98 #define IRQLIST_14(x) \
99 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
100 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
101 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
104 void (*interrupt
[NR_IRQS
])(void) = {
107 #ifdef CONFIG_X86_IO_APIC
108 IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
109 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
110 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
111 IRQLIST_16(0xc), IRQLIST_16(0xd)
113 #ifdef CONFIG_PCI_MSI
125 * This is the 'legacy' 8259A Programmable Interrupt Controller,
126 * present in the majority of PC/AT boxes.
127 * plus some generic x86 specific things if generic specifics makes
129 * this file should become arch/i386/kernel/irq.c when the old irq.c
130 * moves to arch independent land
133 DEFINE_SPINLOCK(i8259A_lock
);
135 static void end_8259A_irq (unsigned int irq
)
139 printk("return %p stack %p ti %p\n", __builtin_return_address(0), &var
, current
->thread_info
);
144 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
|IRQ_INPROGRESS
)) &&
145 irq_desc
[irq
].action
)
146 enable_8259A_irq(irq
);
149 #define shutdown_8259A_irq disable_8259A_irq
151 static void mask_and_ack_8259A(unsigned int);
153 static unsigned int startup_8259A_irq(unsigned int irq
)
155 enable_8259A_irq(irq
);
156 return 0; /* never anything pending */
159 static struct hw_interrupt_type i8259A_irq_type
= {
160 .typename
= "XT-PIC",
161 .startup
= startup_8259A_irq
,
162 .shutdown
= shutdown_8259A_irq
,
163 .enable
= enable_8259A_irq
,
164 .disable
= disable_8259A_irq
,
165 .ack
= mask_and_ack_8259A
,
166 .end
= end_8259A_irq
,
170 * 8259A PIC functions to handle ISA devices:
174 * This contains the irq mask for both 8259A irq controllers,
176 static unsigned int cached_irq_mask
= 0xffff;
178 #define __byte(x,y) (((unsigned char *)&(y))[x])
179 #define cached_21 (__byte(0,cached_irq_mask))
180 #define cached_A1 (__byte(1,cached_irq_mask))
183 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
184 * boards the timer interrupt is not really connected to any IO-APIC pin,
185 * it's fed to the master 8259A's IR0 line only.
187 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
188 * this 'mixed mode' IRQ handling costs nothing because it's only used
191 unsigned long io_apic_irqs
;
193 void disable_8259A_irq(unsigned int irq
)
195 unsigned int mask
= 1 << irq
;
198 spin_lock_irqsave(&i8259A_lock
, flags
);
199 cached_irq_mask
|= mask
;
201 outb(cached_A1
,0xA1);
203 outb(cached_21
,0x21);
204 spin_unlock_irqrestore(&i8259A_lock
, flags
);
207 void enable_8259A_irq(unsigned int irq
)
209 unsigned int mask
= ~(1 << irq
);
212 spin_lock_irqsave(&i8259A_lock
, flags
);
213 cached_irq_mask
&= mask
;
215 outb(cached_A1
,0xA1);
217 outb(cached_21
,0x21);
218 spin_unlock_irqrestore(&i8259A_lock
, flags
);
221 int i8259A_irq_pending(unsigned int irq
)
223 unsigned int mask
= 1<<irq
;
227 spin_lock_irqsave(&i8259A_lock
, flags
);
229 ret
= inb(0x20) & mask
;
231 ret
= inb(0xA0) & (mask
>> 8);
232 spin_unlock_irqrestore(&i8259A_lock
, flags
);
237 void make_8259A_irq(unsigned int irq
)
239 disable_irq_nosync(irq
);
240 io_apic_irqs
&= ~(1<<irq
);
241 irq_desc
[irq
].handler
= &i8259A_irq_type
;
246 * This function assumes to be called rarely. Switching between
247 * 8259A registers is slow.
248 * This has to be protected by the irq controller spinlock
249 * before being called.
251 static inline int i8259A_irq_real(unsigned int irq
)
254 int irqmask
= 1<<irq
;
257 outb(0x0B,0x20); /* ISR register */
258 value
= inb(0x20) & irqmask
;
259 outb(0x0A,0x20); /* back to the IRR register */
262 outb(0x0B,0xA0); /* ISR register */
263 value
= inb(0xA0) & (irqmask
>> 8);
264 outb(0x0A,0xA0); /* back to the IRR register */
269 * Careful! The 8259A is a fragile beast, it pretty
270 * much _has_ to be done exactly like this (mask it
271 * first, _then_ send the EOI, and the order of EOI
272 * to the two 8259s is important!
274 static void mask_and_ack_8259A(unsigned int irq
)
276 unsigned int irqmask
= 1 << irq
;
279 spin_lock_irqsave(&i8259A_lock
, flags
);
281 * Lightweight spurious IRQ detection. We do not want
282 * to overdo spurious IRQ handling - it's usually a sign
283 * of hardware problems, so we only do the checks we can
284 * do without slowing down good hardware unnecesserily.
286 * Note that IRQ7 and IRQ15 (the two spurious IRQs
287 * usually resulting from the 8259A-1|2 PICs) occur
288 * even if the IRQ is masked in the 8259A. Thus we
289 * can check spurious 8259A IRQs without doing the
290 * quite slow i8259A_irq_real() call for every IRQ.
291 * This does not cover 100% of spurious interrupts,
292 * but should be enough to warn the user that there
293 * is something bad going on ...
295 if (cached_irq_mask
& irqmask
)
296 goto spurious_8259A_irq
;
297 cached_irq_mask
|= irqmask
;
301 inb(0xA1); /* DUMMY - (do we need this?) */
302 outb(cached_A1
,0xA1);
303 outb(0x60+(irq
&7),0xA0);/* 'Specific EOI' to slave */
304 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
306 inb(0x21); /* DUMMY - (do we need this?) */
307 outb(cached_21
,0x21);
308 outb(0x60+irq
,0x20); /* 'Specific EOI' to master */
310 spin_unlock_irqrestore(&i8259A_lock
, flags
);
315 * this is the slow path - should happen rarely.
317 if (i8259A_irq_real(irq
))
319 * oops, the IRQ _is_ in service according to the
320 * 8259A - not spurious, go handle it.
322 goto handle_real_irq
;
325 static int spurious_irq_mask
;
327 * At this point we can be sure the IRQ is spurious,
328 * lets ACK and report it. [once per IRQ]
330 if (!(spurious_irq_mask
& irqmask
)) {
331 printk(KERN_DEBUG
"spurious 8259A interrupt: IRQ%d.\n", irq
);
332 spurious_irq_mask
|= irqmask
;
334 atomic_inc(&irq_err_count
);
336 * Theoretically we do not have to handle this IRQ,
337 * but in Linux this does not cause problems and is
340 goto handle_real_irq
;
344 void init_8259A(int auto_eoi
)
348 spin_lock_irqsave(&i8259A_lock
, flags
);
350 outb(0xff, 0x21); /* mask all of 8259A-1 */
351 outb(0xff, 0xA1); /* mask all of 8259A-2 */
354 * outb_p - this has to work on a wide range of PC hardware.
356 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
357 outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
358 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
360 outb_p(0x03, 0x21); /* master does Auto EOI */
362 outb_p(0x01, 0x21); /* master expects normal EOI */
364 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
365 outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
366 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
367 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
368 is to be investigated) */
372 * in AEOI mode we just have to mask the interrupt
375 i8259A_irq_type
.ack
= disable_8259A_irq
;
377 i8259A_irq_type
.ack
= mask_and_ack_8259A
;
379 udelay(100); /* wait for 8259A to initialize */
381 outb(cached_21
, 0x21); /* restore master IRQ mask */
382 outb(cached_A1
, 0xA1); /* restore slave IRQ mask */
384 spin_unlock_irqrestore(&i8259A_lock
, flags
);
387 static char irq_trigger
[2];
389 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
391 static void restore_ELCR(char *trigger
)
393 outb(trigger
[0], 0x4d0);
394 outb(trigger
[1], 0x4d1);
397 static void save_ELCR(char *trigger
)
399 /* IRQ 0,1,2,8,13 are marked as reserved */
400 trigger
[0] = inb(0x4d0) & 0xF8;
401 trigger
[1] = inb(0x4d1) & 0xDE;
404 static int i8259A_resume(struct sys_device
*dev
)
407 restore_ELCR(irq_trigger
);
411 static int i8259A_suspend(struct sys_device
*dev
, pm_message_t state
)
413 save_ELCR(irq_trigger
);
417 static int i8259A_shutdown(struct sys_device
*dev
)
419 /* Put the i8259A into a quiescent state that
420 * the kernel initialization code can get it
423 outb(0xff, 0x21); /* mask all of 8259A-1 */
424 outb(0xff, 0xA1); /* mask all of 8259A-1 */
428 static struct sysdev_class i8259_sysdev_class
= {
429 set_kset_name("i8259"),
430 .suspend
= i8259A_suspend
,
431 .resume
= i8259A_resume
,
432 .shutdown
= i8259A_shutdown
,
435 static struct sys_device device_i8259A
= {
437 .cls
= &i8259_sysdev_class
,
440 static int __init
i8259A_init_sysfs(void)
442 int error
= sysdev_class_register(&i8259_sysdev_class
);
444 error
= sysdev_register(&device_i8259A
);
448 device_initcall(i8259A_init_sysfs
);
451 * IRQ2 is cascade interrupt to second interrupt controller
454 static struct irqaction irq2
= { no_action
, 0, CPU_MASK_NONE
, "cascade", NULL
, NULL
};
456 void __init
init_ISA_irqs (void)
460 #ifdef CONFIG_X86_LOCAL_APIC
465 for (i
= 0; i
< NR_IRQS
; i
++) {
466 irq_desc
[i
].status
= IRQ_DISABLED
;
467 irq_desc
[i
].action
= NULL
;
468 irq_desc
[i
].depth
= 1;
472 * 16 old-style INTA-cycle interrupts:
474 irq_desc
[i
].handler
= &i8259A_irq_type
;
477 * 'high' PCI IRQs filled in on demand
479 irq_desc
[i
].handler
= &no_irq_type
;
484 void apic_timer_interrupt(void);
485 void spurious_interrupt(void);
486 void error_interrupt(void);
487 void reschedule_interrupt(void);
488 void call_function_interrupt(void);
489 void invalidate_interrupt(void);
490 void thermal_interrupt(void);
491 void i8254_timer_resume(void);
493 static void setup_timer(void)
495 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
497 outb_p(LATCH
& 0xff , 0x40); /* LSB */
499 outb(LATCH
>> 8 , 0x40); /* MSB */
502 static int timer_resume(struct sys_device
*dev
)
508 void i8254_timer_resume(void)
513 static struct sysdev_class timer_sysclass
= {
514 set_kset_name("timer"),
515 .resume
= timer_resume
,
518 static struct sys_device device_timer
= {
520 .cls
= &timer_sysclass
,
523 static int __init
init_timer_sysfs(void)
525 int error
= sysdev_class_register(&timer_sysclass
);
527 error
= sysdev_register(&device_timer
);
531 device_initcall(init_timer_sysfs
);
533 void __init
init_IRQ(void)
539 * Cover the whole vector space, no vector can escape
540 * us. (some of these will be overridden and become
541 * 'special' SMP interrupts)
543 for (i
= 0; i
< (NR_VECTORS
- FIRST_EXTERNAL_VECTOR
); i
++) {
544 int vector
= FIRST_EXTERNAL_VECTOR
+ i
;
547 if (vector
!= IA32_SYSCALL_VECTOR
&& vector
!= KDB_VECTOR
) {
548 set_intr_gate(vector
, interrupt
[i
]);
554 * IRQ0 must be given a fixed assignment and initialized,
555 * because it's used before the IO-APIC is set up.
557 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
560 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
561 * IPI, driven by wakeup.
563 set_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
565 /* IPI for invalidation */
566 set_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
568 /* IPI for generic function call */
569 set_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);
571 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
573 #ifdef CONFIG_X86_LOCAL_APIC
574 /* self generated IPI for local APIC timer */
575 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
577 /* IPI vectors for APIC spurious and error interrupts */
578 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
579 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
583 * Set the clock to HZ Hz, we already have a valid