]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/x86_64/kernel/time.c
Merge branch 'upstream-fixes' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
[mirror_ubuntu-artful-kernel.git] / arch / x86_64 / kernel / time.c
1 /*
2 * linux/arch/x86-64/kernel/time.c
3 *
4 * "High Precision Event Timer" based timekeeping.
5 *
6 * Copyright (c) 1991,1992,1995 Linus Torvalds
7 * Copyright (c) 1994 Alan Modra
8 * Copyright (c) 1995 Markus Kuhn
9 * Copyright (c) 1996 Ingo Molnar
10 * Copyright (c) 1998 Andrea Arcangeli
11 * Copyright (c) 2002 Vojtech Pavlik
12 * Copyright (c) 2003 Andi Kleen
13 * RTC support code taken from arch/i386/kernel/timers/time_hpet.c
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/interrupt.h>
19 #include <linux/init.h>
20 #include <linux/mc146818rtc.h>
21 #include <linux/time.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/device.h>
25 #include <linux/sysdev.h>
26 #include <linux/bcd.h>
27 #include <linux/kallsyms.h>
28 #include <linux/acpi.h>
29 #ifdef CONFIG_ACPI
30 #include <acpi/achware.h> /* for PM timer frequency */
31 #endif
32 #include <asm/8253pit.h>
33 #include <asm/pgtable.h>
34 #include <asm/vsyscall.h>
35 #include <asm/timex.h>
36 #include <asm/proto.h>
37 #include <asm/hpet.h>
38 #include <asm/sections.h>
39 #include <linux/cpufreq.h>
40 #include <linux/hpet.h>
41 #ifdef CONFIG_X86_LOCAL_APIC
42 #include <asm/apic.h>
43 #endif
44
45 #ifdef CONFIG_CPU_FREQ
46 static void cpufreq_delayed_get(void);
47 #endif
48 extern void i8254_timer_resume(void);
49 extern int using_apic_timer;
50
51 static char *time_init_gtod(void);
52
53 DEFINE_SPINLOCK(rtc_lock);
54 DEFINE_SPINLOCK(i8253_lock);
55
56 int nohpet __initdata = 0;
57 static int notsc __initdata = 0;
58
59 #undef HPET_HACK_ENABLE_DANGEROUS
60
61 unsigned int cpu_khz; /* TSC clocks / usec, not used here */
62 static unsigned long hpet_period; /* fsecs / HPET clock */
63 unsigned long hpet_tick; /* HPET clocks / interrupt */
64 int hpet_use_timer; /* Use counter of hpet for time keeping, otherwise PIT */
65 unsigned long vxtime_hz = PIT_TICK_RATE;
66 int report_lost_ticks; /* command line option */
67 unsigned long long monotonic_base;
68
69 struct vxtime_data __vxtime __section_vxtime; /* for vsyscalls */
70
71 volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES;
72 unsigned long __wall_jiffies __section_wall_jiffies = INITIAL_JIFFIES;
73 struct timespec __xtime __section_xtime;
74 struct timezone __sys_tz __section_sys_tz;
75
76 /*
77 * do_gettimeoffset() returns microseconds since last timer interrupt was
78 * triggered by hardware. A memory read of HPET is slower than a register read
79 * of TSC, but much more reliable. It's also synchronized to the timer
80 * interrupt. Note that do_gettimeoffset() may return more than hpet_tick, if a
81 * timer interrupt has happened already, but vxtime.trigger wasn't updated yet.
82 * This is not a problem, because jiffies hasn't updated either. They are bound
83 * together by xtime_lock.
84 */
85
86 static inline unsigned int do_gettimeoffset_tsc(void)
87 {
88 unsigned long t;
89 unsigned long x;
90 t = get_cycles_sync();
91 if (t < vxtime.last_tsc) t = vxtime.last_tsc; /* hack */
92 x = ((t - vxtime.last_tsc) * vxtime.tsc_quot) >> 32;
93 return x;
94 }
95
96 static inline unsigned int do_gettimeoffset_hpet(void)
97 {
98 /* cap counter read to one tick to avoid inconsistencies */
99 unsigned long counter = hpet_readl(HPET_COUNTER) - vxtime.last;
100 return (min(counter,hpet_tick) * vxtime.quot) >> 32;
101 }
102
103 unsigned int (*do_gettimeoffset)(void) = do_gettimeoffset_tsc;
104
105 /*
106 * This version of gettimeofday() has microsecond resolution and better than
107 * microsecond precision, as we're using at least a 10 MHz (usually 14.31818
108 * MHz) HPET timer.
109 */
110
111 void do_gettimeofday(struct timeval *tv)
112 {
113 unsigned long seq, t;
114 unsigned int sec, usec;
115
116 do {
117 seq = read_seqbegin(&xtime_lock);
118
119 sec = xtime.tv_sec;
120 usec = xtime.tv_nsec / 1000;
121
122 /* i386 does some correction here to keep the clock
123 monotonous even when ntpd is fixing drift.
124 But they didn't work for me, there is a non monotonic
125 clock anyways with ntp.
126 I dropped all corrections now until a real solution can
127 be found. Note when you fix it here you need to do the same
128 in arch/x86_64/kernel/vsyscall.c and export all needed
129 variables in vmlinux.lds. -AK */
130
131 t = (jiffies - wall_jiffies) * (1000000L / HZ) +
132 do_gettimeoffset();
133 usec += t;
134
135 } while (read_seqretry(&xtime_lock, seq));
136
137 tv->tv_sec = sec + usec / 1000000;
138 tv->tv_usec = usec % 1000000;
139 }
140
141 EXPORT_SYMBOL(do_gettimeofday);
142
143 /*
144 * settimeofday() first undoes the correction that gettimeofday would do
145 * on the time, and then saves it. This is ugly, but has been like this for
146 * ages already.
147 */
148
149 int do_settimeofday(struct timespec *tv)
150 {
151 time_t wtm_sec, sec = tv->tv_sec;
152 long wtm_nsec, nsec = tv->tv_nsec;
153
154 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
155 return -EINVAL;
156
157 write_seqlock_irq(&xtime_lock);
158
159 nsec -= do_gettimeoffset() * 1000 +
160 (jiffies - wall_jiffies) * (NSEC_PER_SEC/HZ);
161
162 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
163 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
164
165 set_normalized_timespec(&xtime, sec, nsec);
166 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
167
168 ntp_clear();
169
170 write_sequnlock_irq(&xtime_lock);
171 clock_was_set();
172 return 0;
173 }
174
175 EXPORT_SYMBOL(do_settimeofday);
176
177 unsigned long profile_pc(struct pt_regs *regs)
178 {
179 unsigned long pc = instruction_pointer(regs);
180
181 /* Assume the lock function has either no stack frame or only a single word.
182 This checks if the address on the stack looks like a kernel text address.
183 There is a small window for false hits, but in that case the tick
184 is just accounted to the spinlock function.
185 Better would be to write these functions in assembler again
186 and check exactly. */
187 if (in_lock_functions(pc)) {
188 char *v = *(char **)regs->rsp;
189 if ((v >= _stext && v <= _etext) ||
190 (v >= _sinittext && v <= _einittext) ||
191 (v >= (char *)MODULES_VADDR && v <= (char *)MODULES_END))
192 return (unsigned long)v;
193 return ((unsigned long *)regs->rsp)[1];
194 }
195 return pc;
196 }
197 EXPORT_SYMBOL(profile_pc);
198
199 /*
200 * In order to set the CMOS clock precisely, set_rtc_mmss has to be called 500
201 * ms after the second nowtime has started, because when nowtime is written
202 * into the registers of the CMOS clock, it will jump to the next second
203 * precisely 500 ms later. Check the Motorola MC146818A or Dallas DS12887 data
204 * sheet for details.
205 */
206
207 static void set_rtc_mmss(unsigned long nowtime)
208 {
209 int real_seconds, real_minutes, cmos_minutes;
210 unsigned char control, freq_select;
211
212 /*
213 * IRQs are disabled when we're called from the timer interrupt,
214 * no need for spin_lock_irqsave()
215 */
216
217 spin_lock(&rtc_lock);
218
219 /*
220 * Tell the clock it's being set and stop it.
221 */
222
223 control = CMOS_READ(RTC_CONTROL);
224 CMOS_WRITE(control | RTC_SET, RTC_CONTROL);
225
226 freq_select = CMOS_READ(RTC_FREQ_SELECT);
227 CMOS_WRITE(freq_select | RTC_DIV_RESET2, RTC_FREQ_SELECT);
228
229 cmos_minutes = CMOS_READ(RTC_MINUTES);
230 BCD_TO_BIN(cmos_minutes);
231
232 /*
233 * since we're only adjusting minutes and seconds, don't interfere with hour
234 * overflow. This avoids messing with unknown time zones but requires your RTC
235 * not to be off by more than 15 minutes. Since we're calling it only when
236 * our clock is externally synchronized using NTP, this shouldn't be a problem.
237 */
238
239 real_seconds = nowtime % 60;
240 real_minutes = nowtime / 60;
241 if (((abs(real_minutes - cmos_minutes) + 15) / 30) & 1)
242 real_minutes += 30; /* correct for half hour time zone */
243 real_minutes %= 60;
244
245 #if 0
246 /* AMD 8111 is a really bad time keeper and hits this regularly.
247 It probably was an attempt to avoid screwing up DST, but ignore
248 that for now. */
249 if (abs(real_minutes - cmos_minutes) >= 30) {
250 printk(KERN_WARNING "time.c: can't update CMOS clock "
251 "from %d to %d\n", cmos_minutes, real_minutes);
252 } else
253 #endif
254
255 {
256 BIN_TO_BCD(real_seconds);
257 BIN_TO_BCD(real_minutes);
258 CMOS_WRITE(real_seconds, RTC_SECONDS);
259 CMOS_WRITE(real_minutes, RTC_MINUTES);
260 }
261
262 /*
263 * The following flags have to be released exactly in this order, otherwise the
264 * DS12887 (popular MC146818A clone with integrated battery and quartz) will
265 * not reset the oscillator and will not update precisely 500 ms later. You
266 * won't find this mentioned in the Dallas Semiconductor data sheets, but who
267 * believes data sheets anyway ... -- Markus Kuhn
268 */
269
270 CMOS_WRITE(control, RTC_CONTROL);
271 CMOS_WRITE(freq_select, RTC_FREQ_SELECT);
272
273 spin_unlock(&rtc_lock);
274 }
275
276
277 /* monotonic_clock(): returns # of nanoseconds passed since time_init()
278 * Note: This function is required to return accurate
279 * time even in the absence of multiple timer ticks.
280 */
281 unsigned long long monotonic_clock(void)
282 {
283 unsigned long seq;
284 u32 last_offset, this_offset, offset;
285 unsigned long long base;
286
287 if (vxtime.mode == VXTIME_HPET) {
288 do {
289 seq = read_seqbegin(&xtime_lock);
290
291 last_offset = vxtime.last;
292 base = monotonic_base;
293 this_offset = hpet_readl(HPET_COUNTER);
294 } while (read_seqretry(&xtime_lock, seq));
295 offset = (this_offset - last_offset);
296 offset *=(NSEC_PER_SEC/HZ)/hpet_tick;
297 return base + offset;
298 } else {
299 do {
300 seq = read_seqbegin(&xtime_lock);
301
302 last_offset = vxtime.last_tsc;
303 base = monotonic_base;
304 } while (read_seqretry(&xtime_lock, seq));
305 this_offset = get_cycles_sync();
306 offset = (this_offset - last_offset)*1000/cpu_khz;
307 return base + offset;
308 }
309 }
310 EXPORT_SYMBOL(monotonic_clock);
311
312 static noinline void handle_lost_ticks(int lost, struct pt_regs *regs)
313 {
314 static long lost_count;
315 static int warned;
316
317 if (report_lost_ticks) {
318 printk(KERN_WARNING "time.c: Lost %d timer "
319 "tick(s)! ", lost);
320 print_symbol("rip %s)\n", regs->rip);
321 }
322
323 if (lost_count == 1000 && !warned) {
324 printk(KERN_WARNING
325 "warning: many lost ticks.\n"
326 KERN_WARNING "Your time source seems to be instable or "
327 "some driver is hogging interupts\n");
328 print_symbol("rip %s\n", regs->rip);
329 if (vxtime.mode == VXTIME_TSC && vxtime.hpet_address) {
330 printk(KERN_WARNING "Falling back to HPET\n");
331 if (hpet_use_timer)
332 vxtime.last = hpet_readl(HPET_T0_CMP) - hpet_tick;
333 else
334 vxtime.last = hpet_readl(HPET_COUNTER);
335 vxtime.mode = VXTIME_HPET;
336 do_gettimeoffset = do_gettimeoffset_hpet;
337 }
338 /* else should fall back to PIT, but code missing. */
339 warned = 1;
340 } else
341 lost_count++;
342
343 #ifdef CONFIG_CPU_FREQ
344 /* In some cases the CPU can change frequency without us noticing
345 (like going into thermal throttle)
346 Give cpufreq a change to catch up. */
347 if ((lost_count+1) % 25 == 0) {
348 cpufreq_delayed_get();
349 }
350 #endif
351 }
352
353 void main_timer_handler(struct pt_regs *regs)
354 {
355 static unsigned long rtc_update = 0;
356 unsigned long tsc;
357 int delay, offset = 0, lost = 0;
358
359 /*
360 * Here we are in the timer irq handler. We have irqs locally disabled (so we
361 * don't need spin_lock_irqsave()) but we don't know if the timer_bh is running
362 * on the other CPU, so we need a lock. We also need to lock the vsyscall
363 * variables, because both do_timer() and us change them -arca+vojtech
364 */
365
366 write_seqlock(&xtime_lock);
367
368 if (vxtime.hpet_address)
369 offset = hpet_readl(HPET_COUNTER);
370
371 if (hpet_use_timer) {
372 /* if we're using the hpet timer functionality,
373 * we can more accurately know the counter value
374 * when the timer interrupt occured.
375 */
376 offset = hpet_readl(HPET_T0_CMP) - hpet_tick;
377 delay = hpet_readl(HPET_COUNTER) - offset;
378 } else {
379 spin_lock(&i8253_lock);
380 outb_p(0x00, 0x43);
381 delay = inb_p(0x40);
382 delay |= inb(0x40) << 8;
383 spin_unlock(&i8253_lock);
384 delay = LATCH - 1 - delay;
385 }
386
387 tsc = get_cycles_sync();
388
389 if (vxtime.mode == VXTIME_HPET) {
390 if (offset - vxtime.last > hpet_tick) {
391 lost = (offset - vxtime.last) / hpet_tick - 1;
392 }
393
394 monotonic_base +=
395 (offset - vxtime.last)*(NSEC_PER_SEC/HZ) / hpet_tick;
396
397 vxtime.last = offset;
398 #ifdef CONFIG_X86_PM_TIMER
399 } else if (vxtime.mode == VXTIME_PMTMR) {
400 lost = pmtimer_mark_offset();
401 #endif
402 } else {
403 offset = (((tsc - vxtime.last_tsc) *
404 vxtime.tsc_quot) >> 32) - (USEC_PER_SEC / HZ);
405
406 if (offset < 0)
407 offset = 0;
408
409 if (offset > (USEC_PER_SEC / HZ)) {
410 lost = offset / (USEC_PER_SEC / HZ);
411 offset %= (USEC_PER_SEC / HZ);
412 }
413
414 monotonic_base += (tsc - vxtime.last_tsc)*1000000/cpu_khz ;
415
416 vxtime.last_tsc = tsc - vxtime.quot * delay / vxtime.tsc_quot;
417
418 if ((((tsc - vxtime.last_tsc) *
419 vxtime.tsc_quot) >> 32) < offset)
420 vxtime.last_tsc = tsc -
421 (((long) offset << 32) / vxtime.tsc_quot) - 1;
422 }
423
424 if (lost > 0) {
425 handle_lost_ticks(lost, regs);
426 jiffies += lost;
427 }
428
429 /*
430 * Do the timer stuff.
431 */
432
433 do_timer(regs);
434 #ifndef CONFIG_SMP
435 update_process_times(user_mode(regs));
436 #endif
437
438 /*
439 * In the SMP case we use the local APIC timer interrupt to do the profiling,
440 * except when we simulate SMP mode on a uniprocessor system, in that case we
441 * have to call the local interrupt handler.
442 */
443
444 #ifndef CONFIG_X86_LOCAL_APIC
445 profile_tick(CPU_PROFILING, regs);
446 #else
447 if (!using_apic_timer)
448 smp_local_timer_interrupt(regs);
449 #endif
450
451 /*
452 * If we have an externally synchronized Linux clock, then update CMOS clock
453 * accordingly every ~11 minutes. set_rtc_mmss() will be called in the jiffy
454 * closest to exactly 500 ms before the next second. If the update fails, we
455 * don't care, as it'll be updated on the next turn, and the problem (time way
456 * off) isn't likely to go away much sooner anyway.
457 */
458
459 if (ntp_synced() && xtime.tv_sec > rtc_update &&
460 abs(xtime.tv_nsec - 500000000) <= tick_nsec / 2) {
461 set_rtc_mmss(xtime.tv_sec);
462 rtc_update = xtime.tv_sec + 660;
463 }
464
465 write_sequnlock(&xtime_lock);
466 }
467
468 static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
469 {
470 if (apic_runs_main_timer > 1)
471 return IRQ_HANDLED;
472 main_timer_handler(regs);
473 #ifdef CONFIG_X86_LOCAL_APIC
474 if (using_apic_timer)
475 smp_send_timer_broadcast_ipi();
476 #endif
477 return IRQ_HANDLED;
478 }
479
480 static unsigned int cyc2ns_scale;
481 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
482
483 static inline void set_cyc2ns_scale(unsigned long cpu_khz)
484 {
485 cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
486 }
487
488 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
489 {
490 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
491 }
492
493 unsigned long long sched_clock(void)
494 {
495 unsigned long a = 0;
496
497 #if 0
498 /* Don't do a HPET read here. Using TSC always is much faster
499 and HPET may not be mapped yet when the scheduler first runs.
500 Disadvantage is a small drift between CPUs in some configurations,
501 but that should be tolerable. */
502 if (__vxtime.mode == VXTIME_HPET)
503 return (hpet_readl(HPET_COUNTER) * vxtime.quot) >> 32;
504 #endif
505
506 /* Could do CPU core sync here. Opteron can execute rdtsc speculatively,
507 which means it is not completely exact and may not be monotonous between
508 CPUs. But the errors should be too small to matter for scheduling
509 purposes. */
510
511 rdtscll(a);
512 return cycles_2_ns(a);
513 }
514
515 static unsigned long get_cmos_time(void)
516 {
517 unsigned int timeout = 1000000, year, mon, day, hour, min, sec;
518 unsigned char uip = 0, this = 0;
519 unsigned long flags;
520
521 /*
522 * The Linux interpretation of the CMOS clock register contents: When the
523 * Update-In-Progress (UIP) flag goes from 1 to 0, the RTC registers show the
524 * second which has precisely just started. Waiting for this can take up to 1
525 * second, we timeout approximately after 2.4 seconds on a machine with
526 * standard 8.3 MHz ISA bus.
527 */
528
529 spin_lock_irqsave(&rtc_lock, flags);
530
531 while (timeout && (!uip || this)) {
532 uip |= this;
533 this = CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP;
534 timeout--;
535 }
536
537 /*
538 * Here we are safe to assume the registers won't change for a whole
539 * second, so we just go ahead and read them.
540 */
541 sec = CMOS_READ(RTC_SECONDS);
542 min = CMOS_READ(RTC_MINUTES);
543 hour = CMOS_READ(RTC_HOURS);
544 day = CMOS_READ(RTC_DAY_OF_MONTH);
545 mon = CMOS_READ(RTC_MONTH);
546 year = CMOS_READ(RTC_YEAR);
547
548 spin_unlock_irqrestore(&rtc_lock, flags);
549
550 /*
551 * We know that x86-64 always uses BCD format, no need to check the
552 * config register.
553 */
554
555 BCD_TO_BIN(sec);
556 BCD_TO_BIN(min);
557 BCD_TO_BIN(hour);
558 BCD_TO_BIN(day);
559 BCD_TO_BIN(mon);
560 BCD_TO_BIN(year);
561
562 /*
563 * x86-64 systems only exists since 2002.
564 * This will work up to Dec 31, 2100
565 */
566 year += 2000;
567
568 return mktime(year, mon, day, hour, min, sec);
569 }
570
571 #ifdef CONFIG_CPU_FREQ
572
573 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
574 changes.
575
576 RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
577 not that important because current Opteron setups do not support
578 scaling on SMP anyroads.
579
580 Should fix up last_tsc too. Currently gettimeofday in the
581 first tick after the change will be slightly wrong. */
582
583 #include <linux/workqueue.h>
584
585 static unsigned int cpufreq_delayed_issched = 0;
586 static unsigned int cpufreq_init = 0;
587 static struct work_struct cpufreq_delayed_get_work;
588
589 static void handle_cpufreq_delayed_get(void *v)
590 {
591 unsigned int cpu;
592 for_each_online_cpu(cpu) {
593 cpufreq_get(cpu);
594 }
595 cpufreq_delayed_issched = 0;
596 }
597
598 /* if we notice lost ticks, schedule a call to cpufreq_get() as it tries
599 * to verify the CPU frequency the timing core thinks the CPU is running
600 * at is still correct.
601 */
602 static void cpufreq_delayed_get(void)
603 {
604 static int warned;
605 if (cpufreq_init && !cpufreq_delayed_issched) {
606 cpufreq_delayed_issched = 1;
607 if (!warned) {
608 warned = 1;
609 printk(KERN_DEBUG "Losing some ticks... checking if CPU frequency changed.\n");
610 }
611 schedule_work(&cpufreq_delayed_get_work);
612 }
613 }
614
615 static unsigned int ref_freq = 0;
616 static unsigned long loops_per_jiffy_ref = 0;
617
618 static unsigned long cpu_khz_ref = 0;
619
620 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
621 void *data)
622 {
623 struct cpufreq_freqs *freq = data;
624 unsigned long *lpj, dummy;
625
626 if (cpu_has(&cpu_data[freq->cpu], X86_FEATURE_CONSTANT_TSC))
627 return 0;
628
629 lpj = &dummy;
630 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
631 #ifdef CONFIG_SMP
632 lpj = &cpu_data[freq->cpu].loops_per_jiffy;
633 #else
634 lpj = &boot_cpu_data.loops_per_jiffy;
635 #endif
636
637 if (!ref_freq) {
638 ref_freq = freq->old;
639 loops_per_jiffy_ref = *lpj;
640 cpu_khz_ref = cpu_khz;
641 }
642 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
643 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
644 (val == CPUFREQ_RESUMECHANGE)) {
645 *lpj =
646 cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
647
648 cpu_khz = cpufreq_scale(cpu_khz_ref, ref_freq, freq->new);
649 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
650 vxtime.tsc_quot = (1000L << 32) / cpu_khz;
651 }
652
653 set_cyc2ns_scale(cpu_khz_ref);
654
655 return 0;
656 }
657
658 static struct notifier_block time_cpufreq_notifier_block = {
659 .notifier_call = time_cpufreq_notifier
660 };
661
662 static int __init cpufreq_tsc(void)
663 {
664 INIT_WORK(&cpufreq_delayed_get_work, handle_cpufreq_delayed_get, NULL);
665 if (!cpufreq_register_notifier(&time_cpufreq_notifier_block,
666 CPUFREQ_TRANSITION_NOTIFIER))
667 cpufreq_init = 1;
668 return 0;
669 }
670
671 core_initcall(cpufreq_tsc);
672
673 #endif
674
675 /*
676 * calibrate_tsc() calibrates the processor TSC in a very simple way, comparing
677 * it to the HPET timer of known frequency.
678 */
679
680 #define TICK_COUNT 100000000
681
682 static unsigned int __init hpet_calibrate_tsc(void)
683 {
684 int tsc_start, hpet_start;
685 int tsc_now, hpet_now;
686 unsigned long flags;
687
688 local_irq_save(flags);
689 local_irq_disable();
690
691 hpet_start = hpet_readl(HPET_COUNTER);
692 rdtscl(tsc_start);
693
694 do {
695 local_irq_disable();
696 hpet_now = hpet_readl(HPET_COUNTER);
697 tsc_now = get_cycles_sync();
698 local_irq_restore(flags);
699 } while ((tsc_now - tsc_start) < TICK_COUNT &&
700 (hpet_now - hpet_start) < TICK_COUNT);
701
702 return (tsc_now - tsc_start) * 1000000000L
703 / ((hpet_now - hpet_start) * hpet_period / 1000);
704 }
705
706
707 /*
708 * pit_calibrate_tsc() uses the speaker output (channel 2) of
709 * the PIT. This is better than using the timer interrupt output,
710 * because we can read the value of the speaker with just one inb(),
711 * where we need three i/o operations for the interrupt channel.
712 * We count how many ticks the TSC does in 50 ms.
713 */
714
715 static unsigned int __init pit_calibrate_tsc(void)
716 {
717 unsigned long start, end;
718 unsigned long flags;
719
720 spin_lock_irqsave(&i8253_lock, flags);
721
722 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
723
724 outb(0xb0, 0x43);
725 outb((PIT_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
726 outb((PIT_TICK_RATE / (1000 / 50)) >> 8, 0x42);
727 start = get_cycles_sync();
728 while ((inb(0x61) & 0x20) == 0);
729 end = get_cycles_sync();
730
731 spin_unlock_irqrestore(&i8253_lock, flags);
732
733 return (end - start) / 50;
734 }
735
736 #ifdef CONFIG_HPET
737 static __init int late_hpet_init(void)
738 {
739 struct hpet_data hd;
740 unsigned int ntimer;
741
742 if (!vxtime.hpet_address)
743 return -1;
744
745 memset(&hd, 0, sizeof (hd));
746
747 ntimer = hpet_readl(HPET_ID);
748 ntimer = (ntimer & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
749 ntimer++;
750
751 /*
752 * Register with driver.
753 * Timer0 and Timer1 is used by platform.
754 */
755 hd.hd_phys_address = vxtime.hpet_address;
756 hd.hd_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
757 hd.hd_nirqs = ntimer;
758 hd.hd_flags = HPET_DATA_PLATFORM;
759 hpet_reserve_timer(&hd, 0);
760 #ifdef CONFIG_HPET_EMULATE_RTC
761 hpet_reserve_timer(&hd, 1);
762 #endif
763 hd.hd_irq[0] = HPET_LEGACY_8254;
764 hd.hd_irq[1] = HPET_LEGACY_RTC;
765 if (ntimer > 2) {
766 struct hpet *hpet;
767 struct hpet_timer *timer;
768 int i;
769
770 hpet = (struct hpet *) fix_to_virt(FIX_HPET_BASE);
771
772 for (i = 2, timer = &hpet->hpet_timers[2]; i < ntimer;
773 timer++, i++)
774 hd.hd_irq[i] = (timer->hpet_config &
775 Tn_INT_ROUTE_CNF_MASK) >>
776 Tn_INT_ROUTE_CNF_SHIFT;
777
778 }
779
780 hpet_alloc(&hd);
781 return 0;
782 }
783 fs_initcall(late_hpet_init);
784 #endif
785
786 static int hpet_timer_stop_set_go(unsigned long tick)
787 {
788 unsigned int cfg;
789
790 /*
791 * Stop the timers and reset the main counter.
792 */
793
794 cfg = hpet_readl(HPET_CFG);
795 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
796 hpet_writel(cfg, HPET_CFG);
797 hpet_writel(0, HPET_COUNTER);
798 hpet_writel(0, HPET_COUNTER + 4);
799
800 /*
801 * Set up timer 0, as periodic with first interrupt to happen at hpet_tick,
802 * and period also hpet_tick.
803 */
804 if (hpet_use_timer) {
805 hpet_writel(HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
806 HPET_TN_32BIT, HPET_T0_CFG);
807 hpet_writel(hpet_tick, HPET_T0_CMP);
808 hpet_writel(hpet_tick, HPET_T0_CMP); /* AK: why twice? */
809 cfg |= HPET_CFG_LEGACY;
810 }
811 /*
812 * Go!
813 */
814
815 cfg |= HPET_CFG_ENABLE;
816 hpet_writel(cfg, HPET_CFG);
817
818 return 0;
819 }
820
821 static int hpet_init(void)
822 {
823 unsigned int id;
824
825 if (!vxtime.hpet_address)
826 return -1;
827 set_fixmap_nocache(FIX_HPET_BASE, vxtime.hpet_address);
828 __set_fixmap(VSYSCALL_HPET, vxtime.hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
829
830 /*
831 * Read the period, compute tick and quotient.
832 */
833
834 id = hpet_readl(HPET_ID);
835
836 if (!(id & HPET_ID_VENDOR) || !(id & HPET_ID_NUMBER))
837 return -1;
838
839 hpet_period = hpet_readl(HPET_PERIOD);
840 if (hpet_period < 100000 || hpet_period > 100000000)
841 return -1;
842
843 hpet_tick = (1000000000L * (USEC_PER_SEC / HZ) + hpet_period / 2) /
844 hpet_period;
845
846 hpet_use_timer = (id & HPET_ID_LEGSUP);
847
848 return hpet_timer_stop_set_go(hpet_tick);
849 }
850
851 static int hpet_reenable(void)
852 {
853 return hpet_timer_stop_set_go(hpet_tick);
854 }
855
856 #define PIT_MODE 0x43
857 #define PIT_CH0 0x40
858
859 static void __init __pit_init(int val, u8 mode)
860 {
861 unsigned long flags;
862
863 spin_lock_irqsave(&i8253_lock, flags);
864 outb_p(mode, PIT_MODE);
865 outb_p(val & 0xff, PIT_CH0); /* LSB */
866 outb_p(val >> 8, PIT_CH0); /* MSB */
867 spin_unlock_irqrestore(&i8253_lock, flags);
868 }
869
870 void __init pit_init(void)
871 {
872 __pit_init(LATCH, 0x34); /* binary, mode 2, LSB/MSB, ch 0 */
873 }
874
875 void __init pit_stop_interrupt(void)
876 {
877 __pit_init(0, 0x30); /* mode 0 */
878 }
879
880 void __init stop_timer_interrupt(void)
881 {
882 char *name;
883 if (vxtime.hpet_address) {
884 name = "HPET";
885 hpet_timer_stop_set_go(0);
886 } else {
887 name = "PIT";
888 pit_stop_interrupt();
889 }
890 printk(KERN_INFO "timer: %s interrupt stopped.\n", name);
891 }
892
893 int __init time_setup(char *str)
894 {
895 report_lost_ticks = 1;
896 return 1;
897 }
898
899 static struct irqaction irq0 = {
900 timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL
901 };
902
903 void __init time_init(void)
904 {
905 char *timename;
906 char *gtod;
907
908 #ifdef HPET_HACK_ENABLE_DANGEROUS
909 if (!vxtime.hpet_address) {
910 printk(KERN_WARNING "time.c: WARNING: Enabling HPET base "
911 "manually!\n");
912 outl(0x800038a0, 0xcf8);
913 outl(0xff000001, 0xcfc);
914 outl(0x800038a0, 0xcf8);
915 vxtime.hpet_address = inl(0xcfc) & 0xfffffffe;
916 printk(KERN_WARNING "time.c: WARNING: Enabled HPET "
917 "at %#lx.\n", vxtime.hpet_address);
918 }
919 #endif
920 if (nohpet)
921 vxtime.hpet_address = 0;
922
923 xtime.tv_sec = get_cmos_time();
924 xtime.tv_nsec = 0;
925
926 set_normalized_timespec(&wall_to_monotonic,
927 -xtime.tv_sec, -xtime.tv_nsec);
928
929 if (!hpet_init())
930 vxtime_hz = (1000000000000000L + hpet_period / 2) /
931 hpet_period;
932 else
933 vxtime.hpet_address = 0;
934
935 if (hpet_use_timer) {
936 cpu_khz = hpet_calibrate_tsc();
937 timename = "HPET";
938 #ifdef CONFIG_X86_PM_TIMER
939 } else if (pmtmr_ioport && !vxtime.hpet_address) {
940 vxtime_hz = PM_TIMER_FREQUENCY;
941 timename = "PM";
942 pit_init();
943 cpu_khz = pit_calibrate_tsc();
944 #endif
945 } else {
946 pit_init();
947 cpu_khz = pit_calibrate_tsc();
948 timename = "PIT";
949 }
950
951 vxtime.mode = VXTIME_TSC;
952 gtod = time_init_gtod();
953
954 printk(KERN_INFO "time.c: Using %ld.%06ld MHz WALL %s GTOD %s timer.\n",
955 vxtime_hz / 1000000, vxtime_hz % 1000000, timename, gtod);
956 printk(KERN_INFO "time.c: Detected %d.%03d MHz processor.\n",
957 cpu_khz / 1000, cpu_khz % 1000);
958 vxtime.quot = (1000000L << 32) / vxtime_hz;
959 vxtime.tsc_quot = (1000L << 32) / cpu_khz;
960 vxtime.last_tsc = get_cycles_sync();
961 setup_irq(0, &irq0);
962
963 set_cyc2ns_scale(cpu_khz);
964 }
965
966 /*
967 * Make an educated guess if the TSC is trustworthy and synchronized
968 * over all CPUs.
969 */
970 __cpuinit int unsynchronized_tsc(void)
971 {
972 #ifdef CONFIG_SMP
973 if (oem_force_hpet_timer())
974 return 1;
975 /* Intel systems are normally all synchronized. Exceptions
976 are handled in the OEM check above. */
977 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
978 return 0;
979 #endif
980 /* Assume multi socket systems are not synchronized */
981 return num_present_cpus() > 1;
982 }
983
984 /*
985 * Decide what mode gettimeofday should use.
986 */
987 __init static char *time_init_gtod(void)
988 {
989 char *timetype;
990
991 if (unsynchronized_tsc())
992 notsc = 1;
993 if (vxtime.hpet_address && notsc) {
994 timetype = hpet_use_timer ? "HPET" : "PIT/HPET";
995 if (hpet_use_timer)
996 vxtime.last = hpet_readl(HPET_T0_CMP) - hpet_tick;
997 else
998 vxtime.last = hpet_readl(HPET_COUNTER);
999 vxtime.mode = VXTIME_HPET;
1000 do_gettimeoffset = do_gettimeoffset_hpet;
1001 #ifdef CONFIG_X86_PM_TIMER
1002 /* Using PM for gettimeofday is quite slow, but we have no other
1003 choice because the TSC is too unreliable on some systems. */
1004 } else if (pmtmr_ioport && !vxtime.hpet_address && notsc) {
1005 timetype = "PM";
1006 do_gettimeoffset = do_gettimeoffset_pm;
1007 vxtime.mode = VXTIME_PMTMR;
1008 sysctl_vsyscall = 0;
1009 printk(KERN_INFO "Disabling vsyscall due to use of PM timer\n");
1010 #endif
1011 } else {
1012 timetype = hpet_use_timer ? "HPET/TSC" : "PIT/TSC";
1013 vxtime.mode = VXTIME_TSC;
1014 }
1015 return timetype;
1016 }
1017
1018 __setup("report_lost_ticks", time_setup);
1019
1020 static long clock_cmos_diff;
1021 static unsigned long sleep_start;
1022
1023 /*
1024 * sysfs support for the timer.
1025 */
1026
1027 static int timer_suspend(struct sys_device *dev, pm_message_t state)
1028 {
1029 /*
1030 * Estimate time zone so that set_time can update the clock
1031 */
1032 long cmos_time = get_cmos_time();
1033
1034 clock_cmos_diff = -cmos_time;
1035 clock_cmos_diff += get_seconds();
1036 sleep_start = cmos_time;
1037 return 0;
1038 }
1039
1040 static int timer_resume(struct sys_device *dev)
1041 {
1042 unsigned long flags;
1043 unsigned long sec;
1044 unsigned long ctime = get_cmos_time();
1045 unsigned long sleep_length = (ctime - sleep_start) * HZ;
1046
1047 if (vxtime.hpet_address)
1048 hpet_reenable();
1049 else
1050 i8254_timer_resume();
1051
1052 sec = ctime + clock_cmos_diff;
1053 write_seqlock_irqsave(&xtime_lock,flags);
1054 xtime.tv_sec = sec;
1055 xtime.tv_nsec = 0;
1056 if (vxtime.mode == VXTIME_HPET) {
1057 if (hpet_use_timer)
1058 vxtime.last = hpet_readl(HPET_T0_CMP) - hpet_tick;
1059 else
1060 vxtime.last = hpet_readl(HPET_COUNTER);
1061 #ifdef CONFIG_X86_PM_TIMER
1062 } else if (vxtime.mode == VXTIME_PMTMR) {
1063 pmtimer_resume();
1064 #endif
1065 } else
1066 vxtime.last_tsc = get_cycles_sync();
1067 write_sequnlock_irqrestore(&xtime_lock,flags);
1068 jiffies += sleep_length;
1069 wall_jiffies += sleep_length;
1070 monotonic_base += sleep_length * (NSEC_PER_SEC/HZ);
1071 touch_softlockup_watchdog();
1072 return 0;
1073 }
1074
1075 static struct sysdev_class timer_sysclass = {
1076 .resume = timer_resume,
1077 .suspend = timer_suspend,
1078 set_kset_name("timer"),
1079 };
1080
1081 /* XXX this driverfs stuff should probably go elsewhere later -john */
1082 static struct sys_device device_timer = {
1083 .id = 0,
1084 .cls = &timer_sysclass,
1085 };
1086
1087 static int time_init_device(void)
1088 {
1089 int error = sysdev_class_register(&timer_sysclass);
1090 if (!error)
1091 error = sysdev_register(&device_timer);
1092 return error;
1093 }
1094
1095 device_initcall(time_init_device);
1096
1097 #ifdef CONFIG_HPET_EMULATE_RTC
1098 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1099 * is enabled, we support RTC interrupt functionality in software.
1100 * RTC has 3 kinds of interrupts:
1101 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1102 * is updated
1103 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1104 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1105 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1106 * (1) and (2) above are implemented using polling at a frequency of
1107 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1108 * overhead. (DEFAULT_RTC_INT_FREQ)
1109 * For (3), we use interrupts at 64Hz or user specified periodic
1110 * frequency, whichever is higher.
1111 */
1112 #include <linux/rtc.h>
1113
1114 #define DEFAULT_RTC_INT_FREQ 64
1115 #define RTC_NUM_INTS 1
1116
1117 static unsigned long UIE_on;
1118 static unsigned long prev_update_sec;
1119
1120 static unsigned long AIE_on;
1121 static struct rtc_time alarm_time;
1122
1123 static unsigned long PIE_on;
1124 static unsigned long PIE_freq = DEFAULT_RTC_INT_FREQ;
1125 static unsigned long PIE_count;
1126
1127 static unsigned long hpet_rtc_int_freq; /* RTC interrupt frequency */
1128 static unsigned int hpet_t1_cmp; /* cached comparator register */
1129
1130 int is_hpet_enabled(void)
1131 {
1132 return vxtime.hpet_address != 0;
1133 }
1134
1135 /*
1136 * Timer 1 for RTC, we do not use periodic interrupt feature,
1137 * even if HPET supports periodic interrupts on Timer 1.
1138 * The reason being, to set up a periodic interrupt in HPET, we need to
1139 * stop the main counter. And if we do that everytime someone diables/enables
1140 * RTC, we will have adverse effect on main kernel timer running on Timer 0.
1141 * So, for the time being, simulate the periodic interrupt in software.
1142 *
1143 * hpet_rtc_timer_init() is called for the first time and during subsequent
1144 * interuppts reinit happens through hpet_rtc_timer_reinit().
1145 */
1146 int hpet_rtc_timer_init(void)
1147 {
1148 unsigned int cfg, cnt;
1149 unsigned long flags;
1150
1151 if (!is_hpet_enabled())
1152 return 0;
1153 /*
1154 * Set the counter 1 and enable the interrupts.
1155 */
1156 if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
1157 hpet_rtc_int_freq = PIE_freq;
1158 else
1159 hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;
1160
1161 local_irq_save(flags);
1162 cnt = hpet_readl(HPET_COUNTER);
1163 cnt += ((hpet_tick*HZ)/hpet_rtc_int_freq);
1164 hpet_writel(cnt, HPET_T1_CMP);
1165 hpet_t1_cmp = cnt;
1166 local_irq_restore(flags);
1167
1168 cfg = hpet_readl(HPET_T1_CFG);
1169 cfg &= ~HPET_TN_PERIODIC;
1170 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1171 hpet_writel(cfg, HPET_T1_CFG);
1172
1173 return 1;
1174 }
1175
1176 static void hpet_rtc_timer_reinit(void)
1177 {
1178 unsigned int cfg, cnt;
1179
1180 if (unlikely(!(PIE_on | AIE_on | UIE_on))) {
1181 cfg = hpet_readl(HPET_T1_CFG);
1182 cfg &= ~HPET_TN_ENABLE;
1183 hpet_writel(cfg, HPET_T1_CFG);
1184 return;
1185 }
1186
1187 if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
1188 hpet_rtc_int_freq = PIE_freq;
1189 else
1190 hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;
1191
1192 /* It is more accurate to use the comparator value than current count.*/
1193 cnt = hpet_t1_cmp;
1194 cnt += hpet_tick*HZ/hpet_rtc_int_freq;
1195 hpet_writel(cnt, HPET_T1_CMP);
1196 hpet_t1_cmp = cnt;
1197 }
1198
1199 /*
1200 * The functions below are called from rtc driver.
1201 * Return 0 if HPET is not being used.
1202 * Otherwise do the necessary changes and return 1.
1203 */
1204 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1205 {
1206 if (!is_hpet_enabled())
1207 return 0;
1208
1209 if (bit_mask & RTC_UIE)
1210 UIE_on = 0;
1211 if (bit_mask & RTC_PIE)
1212 PIE_on = 0;
1213 if (bit_mask & RTC_AIE)
1214 AIE_on = 0;
1215
1216 return 1;
1217 }
1218
1219 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1220 {
1221 int timer_init_reqd = 0;
1222
1223 if (!is_hpet_enabled())
1224 return 0;
1225
1226 if (!(PIE_on | AIE_on | UIE_on))
1227 timer_init_reqd = 1;
1228
1229 if (bit_mask & RTC_UIE) {
1230 UIE_on = 1;
1231 }
1232 if (bit_mask & RTC_PIE) {
1233 PIE_on = 1;
1234 PIE_count = 0;
1235 }
1236 if (bit_mask & RTC_AIE) {
1237 AIE_on = 1;
1238 }
1239
1240 if (timer_init_reqd)
1241 hpet_rtc_timer_init();
1242
1243 return 1;
1244 }
1245
1246 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
1247 {
1248 if (!is_hpet_enabled())
1249 return 0;
1250
1251 alarm_time.tm_hour = hrs;
1252 alarm_time.tm_min = min;
1253 alarm_time.tm_sec = sec;
1254
1255 return 1;
1256 }
1257
1258 int hpet_set_periodic_freq(unsigned long freq)
1259 {
1260 if (!is_hpet_enabled())
1261 return 0;
1262
1263 PIE_freq = freq;
1264 PIE_count = 0;
1265
1266 return 1;
1267 }
1268
1269 int hpet_rtc_dropped_irq(void)
1270 {
1271 if (!is_hpet_enabled())
1272 return 0;
1273
1274 return 1;
1275 }
1276
1277 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1278 {
1279 struct rtc_time curr_time;
1280 unsigned long rtc_int_flag = 0;
1281 int call_rtc_interrupt = 0;
1282
1283 hpet_rtc_timer_reinit();
1284
1285 if (UIE_on | AIE_on) {
1286 rtc_get_rtc_time(&curr_time);
1287 }
1288 if (UIE_on) {
1289 if (curr_time.tm_sec != prev_update_sec) {
1290 /* Set update int info, call real rtc int routine */
1291 call_rtc_interrupt = 1;
1292 rtc_int_flag = RTC_UF;
1293 prev_update_sec = curr_time.tm_sec;
1294 }
1295 }
1296 if (PIE_on) {
1297 PIE_count++;
1298 if (PIE_count >= hpet_rtc_int_freq/PIE_freq) {
1299 /* Set periodic int info, call real rtc int routine */
1300 call_rtc_interrupt = 1;
1301 rtc_int_flag |= RTC_PF;
1302 PIE_count = 0;
1303 }
1304 }
1305 if (AIE_on) {
1306 if ((curr_time.tm_sec == alarm_time.tm_sec) &&
1307 (curr_time.tm_min == alarm_time.tm_min) &&
1308 (curr_time.tm_hour == alarm_time.tm_hour)) {
1309 /* Set alarm int info, call real rtc int routine */
1310 call_rtc_interrupt = 1;
1311 rtc_int_flag |= RTC_AF;
1312 }
1313 }
1314 if (call_rtc_interrupt) {
1315 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1316 rtc_interrupt(rtc_int_flag, dev_id, regs);
1317 }
1318 return IRQ_HANDLED;
1319 }
1320 #endif
1321
1322 static int __init nohpet_setup(char *s)
1323 {
1324 nohpet = 1;
1325 return 0;
1326 }
1327
1328 __setup("nohpet", nohpet_setup);
1329
1330 int __init notsc_setup(char *s)
1331 {
1332 notsc = 1;
1333 return 0;
1334 }
1335
1336 __setup("notsc", notsc_setup);