arch/xtensa/include/asm/byteorder.h

   1 /*
   2  * include/asm-xtensa/byteorder.h
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2001 - 2005 Tensilica Inc.
   9  */
  10
  11 #ifndef _XTENSA_BYTEORDER_H
  12 #define _XTENSA_BYTEORDER_H
  13
  14 #include <asm/types.h>
  15 #include <linux/compiler.h>
  16
  17 #ifdef __XTENSA_EL__
  18 # define __LITTLE_ENDIAN
  19 #elif defined(__XTENSA_EB__)
  20 # define __BIG_ENDIAN
  21 #else
  22 # error processor byte order undefined!
  23 #endif
  24
  25 #define __SWAB_64_THRU_32__
  26
  27 static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
  28 {
  29     __u32 res;
  30     /* instruction sequence from Xtensa ISA release 2/2000 */
  31     __asm__("ssai     8           \n\t"
  32             "srli     %0, %1, 16  \n\t"
  33             "src      %0, %0, %1  \n\t"
  34             "src      %0, %0, %0  \n\t"
  35             "src      %0, %1, %0  \n"
  36             : "=&a" (res)
  37             : "a" (x)
  38             );
  39     return res;
  40 }
  41 #define __arch_swab32 __arch_swab32
  42
  43 static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
  44 {
  45     /* Given that 'short' values are signed (i.e., can be negative),
  46      * we cannot assume that the upper 16-bits of the register are
  47      * zero.  We are careful to mask values after shifting.
  48      */
  49
  50     /* There exists an anomaly between xt-gcc and xt-xcc.  xt-gcc
  51      * inserts an extui instruction after putting this function inline
  52      * to ensure that it uses only the least-significant 16 bits of
  53      * the result.  xt-xcc doesn't use an extui, but assumes the
  54      * __asm__ macro follows convention that the upper 16 bits of an
  55      * 'unsigned short' result are still zero.  This macro doesn't
  56      * follow convention; indeed, it leaves garbage in the upport 16
  57      * bits of the register.
  58
  59      * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
  60      * types while the return type of the function is a 16-bit type
  61      * forces both compilers to insert exactly one extui instruction
  62      * (or equivalent) to mask off the upper 16 bits. */
  63
  64     __u32 res;
  65     __u32 tmp;
  66
  67     __asm__("extui    %1, %2, 8, 8\n\t"
  68             "slli     %0, %2, 8   \n\t"
  69             "or       %0, %0, %1  \n"
  70             : "=&a" (res), "=&a" (tmp)
  71             : "a" (x)
  72             );
  73
  74     return res;
  75 }
  76 #define __arch_swab16 __arch_swab16
  77
  78 #include <linux/byteorder.h>
  79
  80 #endif /* _XTENSA_BYTEORDER_H */