2 * arch/xtensa/kernel/setup.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 * Chris Zankel <chris@zankel.net>
12 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
14 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
17 #include <linux/errno.h>
18 #include <linux/init.h>
20 #include <linux/proc_fs.h>
21 #include <linux/screen_info.h>
22 #include <linux/bootmem.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/cpu.h>
26 #include <linux/of_fdt.h>
27 #include <linux/of_platform.h>
29 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
30 # include <linux/console.h>
34 # include <linux/timex.h>
38 # include <linux/seq_file.h>
41 #include <asm/bootparam.h>
42 #include <asm/mmu_context.h>
43 #include <asm/pgtable.h>
44 #include <asm/processor.h>
45 #include <asm/timex.h>
46 #include <asm/platform.h>
48 #include <asm/setup.h>
49 #include <asm/param.h>
50 #include <asm/traps.h>
53 #include <platform/hardware.h>
55 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
56 struct screen_info screen_info
= { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
59 #ifdef CONFIG_BLK_DEV_FD
60 extern struct fd_ops no_fd_ops
;
61 struct fd_ops
*fd_ops
;
64 extern struct rtc_ops no_rtc_ops
;
65 struct rtc_ops
*rtc_ops
;
67 #ifdef CONFIG_BLK_DEV_INITRD
68 extern unsigned long initrd_start
;
69 extern unsigned long initrd_end
;
70 int initrd_is_mapped
= 0;
71 extern int initrd_below_start_ok
;
75 extern u32 __dtb_start
[];
76 void *dtb_start
= __dtb_start
;
79 unsigned char aux_device_present
;
80 extern unsigned long loops_per_jiffy
;
82 /* Command line specified as configuration option. */
84 static char __initdata command_line
[COMMAND_LINE_SIZE
];
86 #ifdef CONFIG_CMDLINE_BOOL
87 static char default_command_line
[COMMAND_LINE_SIZE
] __initdata
= CONFIG_CMDLINE
;
90 sysmem_info_t __initdata sysmem
;
92 extern int mem_reserve(unsigned long, unsigned long, int);
93 extern void bootmem_init(void);
94 extern void zones_init(void);
97 * Boot parameter parsing.
99 * The Xtensa port uses a list of variable-sized tags to pass data to
100 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
101 * to be recognised. The list is terminated with a zero-sized
105 typedef struct tagtable
{
107 int (*parse
)(const bp_tag_t
*);
110 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
111 __attribute__((used, section(".taglist"))) = { tag, fn }
113 /* parse current tag */
115 static int __init
add_sysmem_bank(unsigned long type
, unsigned long start
,
118 if (sysmem
.nr_banks
>= SYSMEM_BANKS_MAX
) {
120 "Ignoring memory bank 0x%08lx size %ldKB\n",
124 sysmem
.bank
[sysmem
.nr_banks
].type
= type
;
125 sysmem
.bank
[sysmem
.nr_banks
].start
= PAGE_ALIGN(start
);
126 sysmem
.bank
[sysmem
.nr_banks
].end
= end
& PAGE_MASK
;
132 static int __init
parse_tag_mem(const bp_tag_t
*tag
)
134 meminfo_t
*mi
= (meminfo_t
*)(tag
->data
);
136 if (mi
->type
!= MEMORY_TYPE_CONVENTIONAL
)
139 return add_sysmem_bank(mi
->type
, mi
->start
, mi
->end
);
142 __tagtable(BP_TAG_MEMORY
, parse_tag_mem
);
144 #ifdef CONFIG_BLK_DEV_INITRD
146 static int __init
parse_tag_initrd(const bp_tag_t
* tag
)
149 mi
= (meminfo_t
*)(tag
->data
);
150 initrd_start
= (unsigned long)__va(mi
->start
);
151 initrd_end
= (unsigned long)__va(mi
->end
);
156 __tagtable(BP_TAG_INITRD
, parse_tag_initrd
);
160 static int __init
parse_tag_fdt(const bp_tag_t
*tag
)
162 dtb_start
= __va(tag
->data
[0]);
166 __tagtable(BP_TAG_FDT
, parse_tag_fdt
);
168 #endif /* CONFIG_OF */
170 #endif /* CONFIG_BLK_DEV_INITRD */
172 static int __init
parse_tag_cmdline(const bp_tag_t
* tag
)
174 strlcpy(command_line
, (char *)(tag
->data
), COMMAND_LINE_SIZE
);
178 __tagtable(BP_TAG_COMMAND_LINE
, parse_tag_cmdline
);
180 static int __init
parse_bootparam(const bp_tag_t
* tag
)
182 extern tagtable_t __tagtable_begin
, __tagtable_end
;
185 /* Boot parameters must start with a BP_TAG_FIRST tag. */
187 if (tag
->id
!= BP_TAG_FIRST
) {
188 printk(KERN_WARNING
"Invalid boot parameters!\n");
192 tag
= (bp_tag_t
*)((unsigned long)tag
+ sizeof(bp_tag_t
) + tag
->size
);
194 /* Parse all tags. */
196 while (tag
!= NULL
&& tag
->id
!= BP_TAG_LAST
) {
197 for (t
= &__tagtable_begin
; t
< &__tagtable_end
; t
++) {
198 if (tag
->id
== t
->tag
) {
203 if (t
== &__tagtable_end
)
204 printk(KERN_WARNING
"Ignoring tag "
205 "0x%08x\n", tag
->id
);
206 tag
= (bp_tag_t
*)((unsigned long)(tag
+ 1) + tag
->size
);
213 bool __initdata dt_memory_scan
= false;
215 #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
216 unsigned long xtensa_kio_paddr
= XCHAL_KIO_DEFAULT_PADDR
;
217 EXPORT_SYMBOL(xtensa_kio_paddr
);
219 static int __init
xtensa_dt_io_area(unsigned long node
, const char *uname
,
220 int depth
, void *data
)
222 const __be32
*ranges
;
228 if (!of_flat_dt_is_compatible(node
, "simple-bus"))
231 ranges
= of_get_flat_dt_prop(node
, "ranges", &len
);
237 xtensa_kio_paddr
= of_read_ulong(ranges
+1, 1);
238 /* round down to nearest 256MB boundary */
239 xtensa_kio_paddr
&= 0xf0000000;
244 static int __init
xtensa_dt_io_area(unsigned long node
, const char *uname
,
245 int depth
, void *data
)
251 void __init
early_init_dt_add_memory_arch(u64 base
, u64 size
)
257 add_sysmem_bank(MEMORY_TYPE_CONVENTIONAL
, base
, base
+ size
);
260 void * __init
early_init_dt_alloc_memory_arch(u64 size
, u64 align
)
262 return __alloc_bootmem(size
, align
, 0);
265 void __init
early_init_devtree(void *params
)
267 if (sysmem
.nr_banks
== 0)
268 dt_memory_scan
= true;
270 early_init_dt_scan(params
);
271 of_scan_flat_dt(xtensa_dt_io_area
, NULL
);
273 if (!command_line
[0])
274 strlcpy(command_line
, boot_command_line
, COMMAND_LINE_SIZE
);
277 static int __init
xtensa_device_probe(void)
279 of_platform_populate(NULL
, of_default_bus_match_table
, NULL
, NULL
);
283 device_initcall(xtensa_device_probe
);
285 #endif /* CONFIG_OF */
288 * Initialize architecture. (Early stage)
291 void __init
init_arch(bp_tag_t
*bp_start
)
295 /* Parse boot parameters */
298 parse_bootparam(bp_start
);
301 early_init_devtree(dtb_start
);
304 if (sysmem
.nr_banks
== 0) {
306 sysmem
.bank
[0].start
= PLATFORM_DEFAULT_MEM_START
;
307 sysmem
.bank
[0].end
= PLATFORM_DEFAULT_MEM_START
308 + PLATFORM_DEFAULT_MEM_SIZE
;
311 #ifdef CONFIG_CMDLINE_BOOL
312 if (!command_line
[0])
313 strlcpy(command_line
, default_command_line
, COMMAND_LINE_SIZE
);
316 /* Early hook for platforms */
318 platform_init(bp_start
);
320 /* Initialize MMU. */
326 * Initialize system. Setup memory and reserve regions.
331 extern char _WindowVectors_text_start
;
332 extern char _WindowVectors_text_end
;
333 extern char _DebugInterruptVector_literal_start
;
334 extern char _DebugInterruptVector_text_end
;
335 extern char _KernelExceptionVector_literal_start
;
336 extern char _KernelExceptionVector_text_end
;
337 extern char _UserExceptionVector_literal_start
;
338 extern char _UserExceptionVector_text_end
;
339 extern char _DoubleExceptionVector_literal_start
;
340 extern char _DoubleExceptionVector_text_end
;
341 #if XCHAL_EXCM_LEVEL >= 2
342 extern char _Level2InterruptVector_text_start
;
343 extern char _Level2InterruptVector_text_end
;
345 #if XCHAL_EXCM_LEVEL >= 3
346 extern char _Level3InterruptVector_text_start
;
347 extern char _Level3InterruptVector_text_end
;
349 #if XCHAL_EXCM_LEVEL >= 4
350 extern char _Level4InterruptVector_text_start
;
351 extern char _Level4InterruptVector_text_end
;
353 #if XCHAL_EXCM_LEVEL >= 5
354 extern char _Level5InterruptVector_text_start
;
355 extern char _Level5InterruptVector_text_end
;
357 #if XCHAL_EXCM_LEVEL >= 6
358 extern char _Level6InterruptVector_text_start
;
359 extern char _Level6InterruptVector_text_end
;
364 #ifdef CONFIG_S32C1I_SELFTEST
365 #if XCHAL_HAVE_S32C1I
367 static int __initdata rcw_word
, rcw_probe_pc
, rcw_exc
;
370 * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
372 * If *v == cmp, set *v = set. Return previous *v.
374 static inline int probed_compare_swap(int *v
, int cmp
, int set
)
378 __asm__
__volatile__(
381 " wsr %2, scompare1\n"
382 "1: s32c1i %0, %3, 0\n"
383 : "=a" (set
), "=&a" (tmp
)
384 : "a" (cmp
), "a" (v
), "a" (&rcw_probe_pc
), "0" (set
)
390 /* Handle probed exception */
392 static void __init
do_probed_exception(struct pt_regs
*regs
,
393 unsigned long exccause
)
395 if (regs
->pc
== rcw_probe_pc
) { /* exception on s32c1i ? */
396 regs
->pc
+= 3; /* skip the s32c1i instruction */
399 do_unhandled(regs
, exccause
);
403 /* Simple test of S32C1I (soc bringup assist) */
405 static int __init
check_s32c1i(void)
407 int n
, cause1
, cause2
;
408 void *handbus
, *handdata
, *handaddr
; /* temporarily saved handlers */
411 handbus
= trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR
,
412 do_probed_exception
);
413 handdata
= trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR
,
414 do_probed_exception
);
415 handaddr
= trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR
,
416 do_probed_exception
);
418 /* First try an S32C1I that does not store: */
421 n
= probed_compare_swap(&rcw_word
, 0, 2);
424 /* took exception? */
426 /* unclean exception? */
427 if (n
!= 2 || rcw_word
!= 1)
428 panic("S32C1I exception error");
429 } else if (rcw_word
!= 1 || n
!= 1) {
430 panic("S32C1I compare error");
433 /* Then an S32C1I that stores: */
435 rcw_word
= 0x1234567;
436 n
= probed_compare_swap(&rcw_word
, 0x1234567, 0xabcde);
440 /* unclean exception? */
441 if (n
!= 0xabcde || rcw_word
!= 0x1234567)
442 panic("S32C1I exception error (b)");
443 } else if (rcw_word
!= 0xabcde || n
!= 0x1234567) {
444 panic("S32C1I store error");
447 /* Verify consistency of exceptions: */
448 if (cause1
|| cause2
) {
449 pr_warn("S32C1I took exception %d, %d\n", cause1
, cause2
);
450 /* If emulation of S32C1I upon bus error gets implemented,
451 we can get rid of this panic for single core (not SMP) */
452 panic("S32C1I exceptions not currently supported");
454 if (cause1
!= cause2
)
455 panic("inconsistent S32C1I exceptions");
457 trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR
, handbus
);
458 trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR
, handdata
);
459 trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR
, handaddr
);
463 #else /* XCHAL_HAVE_S32C1I */
465 /* This condition should not occur with a commercially deployed processor.
466 Display reminder for early engr test or demo chips / FPGA bitstreams */
467 static int __init
check_s32c1i(void)
469 pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
473 #endif /* XCHAL_HAVE_S32C1I */
474 early_initcall(check_s32c1i
);
475 #endif /* CONFIG_S32C1I_SELFTEST */
478 void __init
setup_arch(char **cmdline_p
)
480 strlcpy(boot_command_line
, command_line
, COMMAND_LINE_SIZE
);
481 *cmdline_p
= command_line
;
483 /* Reserve some memory regions */
485 #ifdef CONFIG_BLK_DEV_INITRD
486 if (initrd_start
< initrd_end
) {
487 initrd_is_mapped
= mem_reserve(__pa(initrd_start
),
488 __pa(initrd_end
), 0);
489 initrd_below_start_ok
= 1;
495 mem_reserve(__pa(&_stext
),__pa(&_end
), 1);
497 mem_reserve(__pa(&_WindowVectors_text_start
),
498 __pa(&_WindowVectors_text_end
), 0);
500 mem_reserve(__pa(&_DebugInterruptVector_literal_start
),
501 __pa(&_DebugInterruptVector_text_end
), 0);
503 mem_reserve(__pa(&_KernelExceptionVector_literal_start
),
504 __pa(&_KernelExceptionVector_text_end
), 0);
506 mem_reserve(__pa(&_UserExceptionVector_literal_start
),
507 __pa(&_UserExceptionVector_text_end
), 0);
509 mem_reserve(__pa(&_DoubleExceptionVector_literal_start
),
510 __pa(&_DoubleExceptionVector_text_end
), 0);
512 #if XCHAL_EXCM_LEVEL >= 2
513 mem_reserve(__pa(&_Level2InterruptVector_text_start
),
514 __pa(&_Level2InterruptVector_text_end
), 0);
516 #if XCHAL_EXCM_LEVEL >= 3
517 mem_reserve(__pa(&_Level3InterruptVector_text_start
),
518 __pa(&_Level3InterruptVector_text_end
), 0);
520 #if XCHAL_EXCM_LEVEL >= 4
521 mem_reserve(__pa(&_Level4InterruptVector_text_start
),
522 __pa(&_Level4InterruptVector_text_end
), 0);
524 #if XCHAL_EXCM_LEVEL >= 5
525 mem_reserve(__pa(&_Level5InterruptVector_text_start
),
526 __pa(&_Level5InterruptVector_text_end
), 0);
528 #if XCHAL_EXCM_LEVEL >= 6
529 mem_reserve(__pa(&_Level6InterruptVector_text_start
),
530 __pa(&_Level6InterruptVector_text_end
), 0);
535 unflatten_and_copy_device_tree();
537 platform_setup(cmdline_p
);
547 # if defined(CONFIG_VGA_CONSOLE)
548 conswitchp
= &vga_con
;
549 # elif defined(CONFIG_DUMMY_CONSOLE)
550 conswitchp
= &dummy_con
;
555 platform_pcibios_init();
559 static DEFINE_PER_CPU(struct cpu
, cpu_data
);
561 static int __init
topology_init(void)
565 for_each_possible_cpu(i
) {
566 struct cpu
*cpu
= &per_cpu(cpu_data
, i
);
567 cpu
->hotpluggable
= !!i
;
568 register_cpu(cpu
, i
);
573 subsys_initcall(topology_init
);
575 void machine_restart(char * cmd
)
580 void machine_halt(void)
586 void machine_power_off(void)
588 platform_power_off();
591 #ifdef CONFIG_PROC_FS
594 * Display some core information through /proc/cpuinfo.
598 c_show(struct seq_file
*f
, void *slot
)
600 char buf
[NR_CPUS
* 5];
602 cpulist_scnprintf(buf
, sizeof(buf
), cpu_online_mask
);
603 /* high-level stuff */
604 seq_printf(f
, "CPU count\t: %u\n"
606 "vendor_id\t: Tensilica\n"
607 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME
"\n"
608 "core ID\t\t: " XCHAL_CORE_ID
"\n"
611 "cpu MHz\t\t: %lu.%02lu\n"
612 "bogomips\t: %lu.%02lu\n",
615 XCHAL_BUILD_UNIQUE_ID
,
616 XCHAL_HAVE_BE
? "big" : "little",
618 (ccount_freq
/10000) % 100,
619 loops_per_jiffy
/(500000/HZ
),
620 (loops_per_jiffy
/(5000/HZ
)) % 100);
622 seq_printf(f
,"flags\t\t: "
632 #if XCHAL_HAVE_DENSITY
635 #if XCHAL_HAVE_BOOLEANS
644 #if XCHAL_HAVE_MINMAX
650 #if XCHAL_HAVE_CLAMPS
662 #if XCHAL_HAVE_MUL32_HIGH
668 #if XCHAL_HAVE_S32C1I
674 seq_printf(f
,"physical aregs\t: %d\n"
685 seq_printf(f
,"num ints\t: %d\n"
689 "debug level\t: %d\n",
690 XCHAL_NUM_INTERRUPTS
,
691 XCHAL_NUM_EXTINTERRUPTS
,
697 seq_printf(f
,"icache line size: %d\n"
698 "icache ways\t: %d\n"
699 "icache size\t: %d\n"
701 #if XCHAL_ICACHE_LINE_LOCKABLE
705 "dcache line size: %d\n"
706 "dcache ways\t: %d\n"
707 "dcache size\t: %d\n"
709 #if XCHAL_DCACHE_IS_WRITEBACK
712 #if XCHAL_DCACHE_LINE_LOCKABLE
716 XCHAL_ICACHE_LINESIZE
,
719 XCHAL_DCACHE_LINESIZE
,
727 * We show only CPU #0 info.
730 c_start(struct seq_file
*f
, loff_t
*pos
)
732 return (*pos
== 0) ? (void *)1 : NULL
;
736 c_next(struct seq_file
*f
, void *v
, loff_t
*pos
)
742 c_stop(struct seq_file
*f
, void *v
)
746 const struct seq_operations cpuinfo_op
=
754 #endif /* CONFIG_PROC_FS */