2 * NVMe block driver based on vfio
4 * Copyright 2016 - 2018 Red Hat, Inc.
7 * Fam Zheng <famz@redhat.com>
8 * Paolo Bonzini <pbonzini@redhat.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
14 #include "qemu/osdep.h"
15 #include <linux/vfio.h>
16 #include "qapi/error.h"
17 #include "qapi/qmp/qdict.h"
18 #include "qapi/qmp/qstring.h"
19 #include "qemu/error-report.h"
20 #include "qemu/main-loop.h"
21 #include "qemu/module.h"
22 #include "qemu/cutils.h"
23 #include "qemu/option.h"
24 #include "qemu/vfio-helpers.h"
25 #include "block/block_int.h"
26 #include "sysemu/replay.h"
29 #include "block/nvme.h"
31 #define NVME_SQ_ENTRY_BYTES 64
32 #define NVME_CQ_ENTRY_BYTES 16
33 #define NVME_QUEUE_SIZE 128
34 #define NVME_DOORBELL_SIZE 4096
37 * We have to leave one slot empty as that is the full queue case where
40 #define NVME_NUM_REQS (NVME_QUEUE_SIZE - 1)
42 typedef struct BDRVNVMeState BDRVNVMeState
;
48 /* Hardware MMIO register */
49 volatile uint32_t *doorbell
;
53 BlockCompletionFunc
*cb
;
57 uint64_t prp_list_iova
;
58 int free_req_next
; /* q->reqs[] index of next free req */
64 /* Read from I/O code path, initialized under BQL */
68 /* Fields protected by BQL */
69 uint8_t *prp_list_pages
;
71 /* Fields protected by @lock */
72 CoQueue free_req_queue
;
76 NVMeRequest reqs
[NVME_NUM_REQS
];
80 /* Thread-safe, no lock necessary */
81 QEMUBH
*completion_bh
;
85 #define INDEX_IO(n) (1 + n)
87 /* This driver shares a single MSIX IRQ for the admin and I/O queues */
89 MSIX_SHARED_IRQ_IDX
= 0,
93 struct BDRVNVMeState
{
94 AioContext
*aio_context
;
96 /* Memory mapped registers */
101 /* The submission/completion queue pairs.
105 NVMeQueuePair
**queues
;
108 /* How many uint32_t elements does each doorbell entry take. */
109 size_t doorbell_scale
;
110 bool write_cache_supported
;
111 EventNotifier irq_notifier
[MSIX_IRQ_COUNT
];
113 uint64_t nsze
; /* Namespace size reported by identify command */
114 int nsid
; /* The namespace id to read/write data. */
117 uint64_t max_transfer
;
120 bool supports_write_zeroes
;
121 bool supports_discard
;
123 CoMutex dma_map_lock
;
124 CoQueue dma_flush_queue
;
126 /* Total size of mapped qiov, accessed under dma_map_lock */
129 /* PCI address (required for nvme_refresh_filename()) */
133 uint64_t completion_errors
;
134 uint64_t aligned_accesses
;
135 uint64_t unaligned_accesses
;
139 #define NVME_BLOCK_OPT_DEVICE "device"
140 #define NVME_BLOCK_OPT_NAMESPACE "namespace"
142 static void nvme_process_completion_bh(void *opaque
);
144 static QemuOptsList runtime_opts
= {
146 .head
= QTAILQ_HEAD_INITIALIZER(runtime_opts
.head
),
149 .name
= NVME_BLOCK_OPT_DEVICE
,
150 .type
= QEMU_OPT_STRING
,
151 .help
= "NVMe PCI device address",
154 .name
= NVME_BLOCK_OPT_NAMESPACE
,
155 .type
= QEMU_OPT_NUMBER
,
156 .help
= "NVMe namespace",
158 { /* end of list */ }
162 static void nvme_init_queue(BDRVNVMeState
*s
, NVMeQueue
*q
,
163 int nentries
, int entry_bytes
, Error
**errp
)
168 bytes
= ROUND_UP(nentries
* entry_bytes
, s
->page_size
);
169 q
->head
= q
->tail
= 0;
170 q
->queue
= qemu_try_memalign(s
->page_size
, bytes
);
172 error_setg(errp
, "Cannot allocate queue");
175 memset(q
->queue
, 0, bytes
);
176 r
= qemu_vfio_dma_map(s
->vfio
, q
->queue
, bytes
, false, &q
->iova
);
178 error_setg(errp
, "Cannot map queue");
182 static void nvme_free_queue_pair(NVMeQueuePair
*q
)
184 if (q
->completion_bh
) {
185 qemu_bh_delete(q
->completion_bh
);
187 qemu_vfree(q
->prp_list_pages
);
188 qemu_vfree(q
->sq
.queue
);
189 qemu_vfree(q
->cq
.queue
);
190 qemu_mutex_destroy(&q
->lock
);
194 static void nvme_free_req_queue_cb(void *opaque
)
196 NVMeQueuePair
*q
= opaque
;
198 qemu_mutex_lock(&q
->lock
);
199 while (qemu_co_enter_next(&q
->free_req_queue
, &q
->lock
)) {
200 /* Retry all pending requests */
202 qemu_mutex_unlock(&q
->lock
);
205 static NVMeQueuePair
*nvme_create_queue_pair(BDRVNVMeState
*s
,
206 AioContext
*aio_context
,
211 Error
*local_err
= NULL
;
213 uint64_t prp_list_iova
;
215 q
= g_try_new0(NVMeQueuePair
, 1);
219 q
->prp_list_pages
= qemu_try_memalign(s
->page_size
,
220 s
->page_size
* NVME_NUM_REQS
);
221 if (!q
->prp_list_pages
) {
224 memset(q
->prp_list_pages
, 0, s
->page_size
* NVME_NUM_REQS
);
225 qemu_mutex_init(&q
->lock
);
228 qemu_co_queue_init(&q
->free_req_queue
);
229 q
->completion_bh
= aio_bh_new(aio_context
, nvme_process_completion_bh
, q
);
230 r
= qemu_vfio_dma_map(s
->vfio
, q
->prp_list_pages
,
231 s
->page_size
* NVME_NUM_REQS
,
232 false, &prp_list_iova
);
236 q
->free_req_head
= -1;
237 for (i
= 0; i
< NVME_NUM_REQS
; i
++) {
238 NVMeRequest
*req
= &q
->reqs
[i
];
240 req
->free_req_next
= q
->free_req_head
;
241 q
->free_req_head
= i
;
242 req
->prp_list_page
= q
->prp_list_pages
+ i
* s
->page_size
;
243 req
->prp_list_iova
= prp_list_iova
+ i
* s
->page_size
;
246 nvme_init_queue(s
, &q
->sq
, size
, NVME_SQ_ENTRY_BYTES
, &local_err
);
248 error_propagate(errp
, local_err
);
251 q
->sq
.doorbell
= &s
->doorbells
[idx
* s
->doorbell_scale
].sq_tail
;
253 nvme_init_queue(s
, &q
->cq
, size
, NVME_CQ_ENTRY_BYTES
, &local_err
);
255 error_propagate(errp
, local_err
);
258 q
->cq
.doorbell
= &s
->doorbells
[idx
* s
->doorbell_scale
].cq_head
;
262 nvme_free_queue_pair(q
);
267 static void nvme_kick(NVMeQueuePair
*q
)
269 BDRVNVMeState
*s
= q
->s
;
271 if (s
->plugged
|| !q
->need_kick
) {
274 trace_nvme_kick(s
, q
->index
);
275 assert(!(q
->sq
.tail
& 0xFF00));
276 /* Fence the write to submission queue entry before notifying the device. */
278 *q
->sq
.doorbell
= cpu_to_le32(q
->sq
.tail
);
279 q
->inflight
+= q
->need_kick
;
283 /* Find a free request element if any, otherwise:
284 * a) if in coroutine context, try to wait for one to become available;
285 * b) if not in coroutine, return NULL;
287 static NVMeRequest
*nvme_get_free_req(NVMeQueuePair
*q
)
291 qemu_mutex_lock(&q
->lock
);
293 while (q
->free_req_head
== -1) {
294 if (qemu_in_coroutine()) {
295 trace_nvme_free_req_queue_wait(q
->s
, q
->index
);
296 qemu_co_queue_wait(&q
->free_req_queue
, &q
->lock
);
298 qemu_mutex_unlock(&q
->lock
);
303 req
= &q
->reqs
[q
->free_req_head
];
304 q
->free_req_head
= req
->free_req_next
;
305 req
->free_req_next
= -1;
307 qemu_mutex_unlock(&q
->lock
);
312 static void nvme_put_free_req_locked(NVMeQueuePair
*q
, NVMeRequest
*req
)
314 req
->free_req_next
= q
->free_req_head
;
315 q
->free_req_head
= req
- q
->reqs
;
319 static void nvme_wake_free_req_locked(NVMeQueuePair
*q
)
321 if (!qemu_co_queue_empty(&q
->free_req_queue
)) {
322 replay_bh_schedule_oneshot_event(q
->s
->aio_context
,
323 nvme_free_req_queue_cb
, q
);
327 /* Insert a request in the freelist and wake waiters */
328 static void nvme_put_free_req_and_wake(NVMeQueuePair
*q
, NVMeRequest
*req
)
330 qemu_mutex_lock(&q
->lock
);
331 nvme_put_free_req_locked(q
, req
);
332 nvme_wake_free_req_locked(q
);
333 qemu_mutex_unlock(&q
->lock
);
336 static inline int nvme_translate_error(const NvmeCqe
*c
)
338 uint16_t status
= (le16_to_cpu(c
->status
) >> 1) & 0xFF;
340 trace_nvme_error(le32_to_cpu(c
->result
),
341 le16_to_cpu(c
->sq_head
),
342 le16_to_cpu(c
->sq_id
),
344 le16_to_cpu(status
));
359 static bool nvme_process_completion(NVMeQueuePair
*q
)
361 BDRVNVMeState
*s
= q
->s
;
362 bool progress
= false;
367 trace_nvme_process_completion(s
, q
->index
, q
->inflight
);
369 trace_nvme_process_completion_queue_plugged(s
, q
->index
);
374 * Support re-entrancy when a request cb() function invokes aio_poll().
375 * Pending completions must be visible to aio_poll() so that a cb()
376 * function can wait for the completion of another request.
378 * The aio_poll() loop will execute our BH and we'll resume completion
381 qemu_bh_schedule(q
->completion_bh
);
383 assert(q
->inflight
>= 0);
384 while (q
->inflight
) {
388 c
= (NvmeCqe
*)&q
->cq
.queue
[q
->cq
.head
* NVME_CQ_ENTRY_BYTES
];
389 if ((le16_to_cpu(c
->status
) & 0x1) == q
->cq_phase
) {
392 ret
= nvme_translate_error(c
);
394 s
->stats
.completion_errors
++;
396 q
->cq
.head
= (q
->cq
.head
+ 1) % NVME_QUEUE_SIZE
;
398 q
->cq_phase
= !q
->cq_phase
;
400 cid
= le16_to_cpu(c
->cid
);
401 if (cid
== 0 || cid
> NVME_QUEUE_SIZE
) {
402 warn_report("NVMe: Unexpected CID in completion queue: %"PRIu32
", "
403 "queue size: %u", cid
, NVME_QUEUE_SIZE
);
406 trace_nvme_complete_command(s
, q
->index
, cid
);
407 preq
= &q
->reqs
[cid
- 1];
409 assert(req
.cid
== cid
);
411 nvme_put_free_req_locked(q
, preq
);
412 preq
->cb
= preq
->opaque
= NULL
;
414 qemu_mutex_unlock(&q
->lock
);
415 req
.cb(req
.opaque
, ret
);
416 qemu_mutex_lock(&q
->lock
);
420 /* Notify the device so it can post more completions. */
422 *q
->cq
.doorbell
= cpu_to_le32(q
->cq
.head
);
423 nvme_wake_free_req_locked(q
);
426 qemu_bh_cancel(q
->completion_bh
);
431 static void nvme_process_completion_bh(void *opaque
)
433 NVMeQueuePair
*q
= opaque
;
436 * We're being invoked because a nvme_process_completion() cb() function
437 * called aio_poll(). The callback may be waiting for further completions
438 * so notify the device that it has space to fill in more completions now.
441 *q
->cq
.doorbell
= cpu_to_le32(q
->cq
.head
);
442 nvme_wake_free_req_locked(q
);
444 nvme_process_completion(q
);
447 static void nvme_trace_command(const NvmeCmd
*cmd
)
451 if (!trace_event_get_state_backends(TRACE_NVME_SUBMIT_COMMAND_RAW
)) {
454 for (i
= 0; i
< 8; ++i
) {
455 uint8_t *cmdp
= (uint8_t *)cmd
+ i
* 8;
456 trace_nvme_submit_command_raw(cmdp
[0], cmdp
[1], cmdp
[2], cmdp
[3],
457 cmdp
[4], cmdp
[5], cmdp
[6], cmdp
[7]);
461 static void nvme_submit_command(NVMeQueuePair
*q
, NVMeRequest
*req
,
462 NvmeCmd
*cmd
, BlockCompletionFunc cb
,
467 req
->opaque
= opaque
;
468 cmd
->cid
= cpu_to_le32(req
->cid
);
470 trace_nvme_submit_command(q
->s
, q
->index
, req
->cid
);
471 nvme_trace_command(cmd
);
472 qemu_mutex_lock(&q
->lock
);
473 memcpy((uint8_t *)q
->sq
.queue
+
474 q
->sq
.tail
* NVME_SQ_ENTRY_BYTES
, cmd
, sizeof(*cmd
));
475 q
->sq
.tail
= (q
->sq
.tail
+ 1) % NVME_QUEUE_SIZE
;
478 nvme_process_completion(q
);
479 qemu_mutex_unlock(&q
->lock
);
482 static void nvme_cmd_sync_cb(void *opaque
, int ret
)
489 static int nvme_cmd_sync(BlockDriverState
*bs
, NVMeQueuePair
*q
,
492 AioContext
*aio_context
= bdrv_get_aio_context(bs
);
494 int ret
= -EINPROGRESS
;
495 req
= nvme_get_free_req(q
);
499 nvme_submit_command(q
, req
, cmd
, nvme_cmd_sync_cb
, &ret
);
501 AIO_WAIT_WHILE(aio_context
, ret
== -EINPROGRESS
);
505 static void nvme_identify(BlockDriverState
*bs
, int namespace, Error
**errp
)
507 BDRVNVMeState
*s
= bs
->opaque
;
517 .opcode
= NVME_ADM_CMD_IDENTIFY
,
518 .cdw10
= cpu_to_le32(0x1),
521 id
= qemu_try_memalign(s
->page_size
, sizeof(*id
));
523 error_setg(errp
, "Cannot allocate buffer for identify response");
526 r
= qemu_vfio_dma_map(s
->vfio
, id
, sizeof(*id
), true, &iova
);
528 error_setg(errp
, "Cannot map buffer for DMA");
532 memset(id
, 0, sizeof(*id
));
533 cmd
.dptr
.prp1
= cpu_to_le64(iova
);
534 if (nvme_cmd_sync(bs
, s
->queues
[INDEX_ADMIN
], &cmd
)) {
535 error_setg(errp
, "Failed to identify controller");
539 if (le32_to_cpu(id
->ctrl
.nn
) < namespace) {
540 error_setg(errp
, "Invalid namespace");
543 s
->write_cache_supported
= le32_to_cpu(id
->ctrl
.vwc
) & 0x1;
544 s
->max_transfer
= (id
->ctrl
.mdts
? 1 << id
->ctrl
.mdts
: 0) * s
->page_size
;
545 /* For now the page list buffer per command is one page, to hold at most
546 * s->page_size / sizeof(uint64_t) entries. */
547 s
->max_transfer
= MIN_NON_ZERO(s
->max_transfer
,
548 s
->page_size
/ sizeof(uint64_t) * s
->page_size
);
550 oncs
= le16_to_cpu(id
->ctrl
.oncs
);
551 s
->supports_write_zeroes
= !!(oncs
& NVME_ONCS_WRITE_ZEROES
);
552 s
->supports_discard
= !!(oncs
& NVME_ONCS_DSM
);
554 memset(id
, 0, sizeof(*id
));
556 cmd
.nsid
= cpu_to_le32(namespace);
557 if (nvme_cmd_sync(bs
, s
->queues
[INDEX_ADMIN
], &cmd
)) {
558 error_setg(errp
, "Failed to identify namespace");
562 s
->nsze
= le64_to_cpu(id
->ns
.nsze
);
563 lbaf
= &id
->ns
.lbaf
[NVME_ID_NS_FLBAS_INDEX(id
->ns
.flbas
)];
565 if (NVME_ID_NS_DLFEAT_WRITE_ZEROES(id
->ns
.dlfeat
) &&
566 NVME_ID_NS_DLFEAT_READ_BEHAVIOR(id
->ns
.dlfeat
) ==
567 NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES
) {
568 bs
->supported_write_flags
|= BDRV_REQ_MAY_UNMAP
;
572 error_setg(errp
, "Namespaces with metadata are not yet supported");
576 if (lbaf
->ds
< BDRV_SECTOR_BITS
|| lbaf
->ds
> 12 ||
577 (1 << lbaf
->ds
) > s
->page_size
)
579 error_setg(errp
, "Namespace has unsupported block size (2^%d)",
584 s
->blkshift
= lbaf
->ds
;
586 qemu_vfio_dma_unmap(s
->vfio
, id
);
590 static bool nvme_poll_queue(NVMeQueuePair
*q
)
592 bool progress
= false;
594 const size_t cqe_offset
= q
->cq
.head
* NVME_CQ_ENTRY_BYTES
;
595 NvmeCqe
*cqe
= (NvmeCqe
*)&q
->cq
.queue
[cqe_offset
];
597 trace_nvme_poll_queue(q
->s
, q
->index
);
599 * Do an early check for completions. q->lock isn't needed because
600 * nvme_process_completion() only runs in the event loop thread and
601 * cannot race with itself.
603 if ((le16_to_cpu(cqe
->status
) & 0x1) == q
->cq_phase
) {
607 qemu_mutex_lock(&q
->lock
);
608 while (nvme_process_completion(q
)) {
612 qemu_mutex_unlock(&q
->lock
);
617 static bool nvme_poll_queues(BDRVNVMeState
*s
)
619 bool progress
= false;
622 for (i
= 0; i
< s
->nr_queues
; i
++) {
623 if (nvme_poll_queue(s
->queues
[i
])) {
630 static void nvme_handle_event(EventNotifier
*n
)
632 BDRVNVMeState
*s
= container_of(n
, BDRVNVMeState
,
633 irq_notifier
[MSIX_SHARED_IRQ_IDX
]);
635 trace_nvme_handle_event(s
);
636 event_notifier_test_and_clear(n
);
640 static bool nvme_add_io_queue(BlockDriverState
*bs
, Error
**errp
)
642 BDRVNVMeState
*s
= bs
->opaque
;
643 int n
= s
->nr_queues
;
646 int queue_size
= NVME_QUEUE_SIZE
;
648 q
= nvme_create_queue_pair(s
, bdrv_get_aio_context(bs
),
649 n
, queue_size
, errp
);
654 .opcode
= NVME_ADM_CMD_CREATE_CQ
,
655 .dptr
.prp1
= cpu_to_le64(q
->cq
.iova
),
656 .cdw10
= cpu_to_le32(((queue_size
- 1) << 16) | (n
& 0xFFFF)),
657 .cdw11
= cpu_to_le32(0x3),
659 if (nvme_cmd_sync(bs
, s
->queues
[INDEX_ADMIN
], &cmd
)) {
660 error_setg(errp
, "Failed to create CQ io queue [%d]", n
);
664 .opcode
= NVME_ADM_CMD_CREATE_SQ
,
665 .dptr
.prp1
= cpu_to_le64(q
->sq
.iova
),
666 .cdw10
= cpu_to_le32(((queue_size
- 1) << 16) | (n
& 0xFFFF)),
667 .cdw11
= cpu_to_le32(0x1 | (n
<< 16)),
669 if (nvme_cmd_sync(bs
, s
->queues
[INDEX_ADMIN
], &cmd
)) {
670 error_setg(errp
, "Failed to create SQ io queue [%d]", n
);
673 s
->queues
= g_renew(NVMeQueuePair
*, s
->queues
, n
+ 1);
678 nvme_free_queue_pair(q
);
682 static bool nvme_poll_cb(void *opaque
)
684 EventNotifier
*e
= opaque
;
685 BDRVNVMeState
*s
= container_of(e
, BDRVNVMeState
,
686 irq_notifier
[MSIX_SHARED_IRQ_IDX
]);
688 return nvme_poll_queues(s
);
691 static int nvme_init(BlockDriverState
*bs
, const char *device
, int namespace,
694 BDRVNVMeState
*s
= bs
->opaque
;
695 AioContext
*aio_context
= bdrv_get_aio_context(bs
);
699 uint64_t deadline
, now
;
700 Error
*local_err
= NULL
;
701 volatile NvmeBar
*regs
= NULL
;
703 qemu_co_mutex_init(&s
->dma_map_lock
);
704 qemu_co_queue_init(&s
->dma_flush_queue
);
705 s
->device
= g_strdup(device
);
707 s
->aio_context
= bdrv_get_aio_context(bs
);
708 ret
= event_notifier_init(&s
->irq_notifier
[MSIX_SHARED_IRQ_IDX
], 0);
710 error_setg(errp
, "Failed to init event notifier");
714 s
->vfio
= qemu_vfio_open_pci(device
, errp
);
720 regs
= qemu_vfio_pci_map_bar(s
->vfio
, 0, 0, sizeof(NvmeBar
),
721 PROT_READ
| PROT_WRITE
, errp
);
726 /* Perform initialize sequence as described in NVMe spec "7.6.1
727 * Initialization". */
729 cap
= le64_to_cpu(regs
->cap
);
730 trace_nvme_controller_capability_raw(cap
);
731 trace_nvme_controller_capability("Maximum Queue Entries Supported",
732 1 + NVME_CAP_MQES(cap
));
733 trace_nvme_controller_capability("Contiguous Queues Required",
735 trace_nvme_controller_capability("Doorbell Stride",
736 2 << (2 + NVME_CAP_DSTRD(cap
)));
737 trace_nvme_controller_capability("Subsystem Reset Supported",
738 NVME_CAP_NSSRS(cap
));
739 trace_nvme_controller_capability("Memory Page Size Minimum",
740 1 << (12 + NVME_CAP_MPSMIN(cap
)));
741 trace_nvme_controller_capability("Memory Page Size Maximum",
742 1 << (12 + NVME_CAP_MPSMAX(cap
)));
743 if (!NVME_CAP_CSS(cap
)) {
744 error_setg(errp
, "Device doesn't support NVMe command set");
749 s
->page_size
= MAX(4096, 1 << NVME_CAP_MPSMIN(cap
));
750 s
->doorbell_scale
= (4 << NVME_CAP_DSTRD(cap
)) / sizeof(uint32_t);
751 bs
->bl
.opt_mem_alignment
= s
->page_size
;
752 timeout_ms
= MIN(500 * NVME_CAP_TO(cap
), 30000);
754 /* Reset device to get a clean state. */
755 regs
->cc
= cpu_to_le32(le32_to_cpu(regs
->cc
) & 0xFE);
756 /* Wait for CSTS.RDY = 0. */
757 deadline
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) + timeout_ms
* SCALE_MS
;
758 while (NVME_CSTS_RDY(le32_to_cpu(regs
->csts
))) {
759 if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) > deadline
) {
760 error_setg(errp
, "Timeout while waiting for device to reset (%"
768 s
->doorbells
= qemu_vfio_pci_map_bar(s
->vfio
, 0, sizeof(NvmeBar
),
769 NVME_DOORBELL_SIZE
, PROT_WRITE
, errp
);
775 /* Set up admin queue. */
776 s
->queues
= g_new(NVMeQueuePair
*, 1);
777 s
->queues
[INDEX_ADMIN
] = nvme_create_queue_pair(s
, aio_context
, 0,
780 if (!s
->queues
[INDEX_ADMIN
]) {
785 QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE
& 0xF000);
786 regs
->aqa
= cpu_to_le32((NVME_QUEUE_SIZE
<< AQA_ACQS_SHIFT
) |
787 (NVME_QUEUE_SIZE
<< AQA_ASQS_SHIFT
));
788 regs
->asq
= cpu_to_le64(s
->queues
[INDEX_ADMIN
]->sq
.iova
);
789 regs
->acq
= cpu_to_le64(s
->queues
[INDEX_ADMIN
]->cq
.iova
);
791 /* After setting up all control registers we can enable device now. */
792 regs
->cc
= cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES
) << CC_IOCQES_SHIFT
) |
793 (ctz32(NVME_SQ_ENTRY_BYTES
) << CC_IOSQES_SHIFT
) |
795 /* Wait for CSTS.RDY = 1. */
796 now
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
797 deadline
= now
+ timeout_ms
* SCALE_MS
;
798 while (!NVME_CSTS_RDY(le32_to_cpu(regs
->csts
))) {
799 if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) > deadline
) {
800 error_setg(errp
, "Timeout while waiting for device to start (%"
808 ret
= qemu_vfio_pci_init_irq(s
->vfio
, s
->irq_notifier
,
809 VFIO_PCI_MSIX_IRQ_INDEX
, errp
);
813 aio_set_event_notifier(bdrv_get_aio_context(bs
),
814 &s
->irq_notifier
[MSIX_SHARED_IRQ_IDX
],
815 false, nvme_handle_event
, nvme_poll_cb
);
817 nvme_identify(bs
, namespace, &local_err
);
819 error_propagate(errp
, local_err
);
824 /* Set up command queues. */
825 if (!nvme_add_io_queue(bs
, errp
)) {
830 qemu_vfio_pci_unmap_bar(s
->vfio
, 0, (void *)regs
, 0, sizeof(NvmeBar
));
833 /* Cleaning up is done in nvme_file_open() upon error. */
837 /* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example:
839 * nvme://0000:44:00.0/1
841 * where the "nvme://" is a fixed form of the protocol prefix, the middle part
842 * is the PCI address, and the last part is the namespace number starting from
843 * 1 according to the NVMe spec. */
844 static void nvme_parse_filename(const char *filename
, QDict
*options
,
847 int pref
= strlen("nvme://");
849 if (strlen(filename
) > pref
&& !strncmp(filename
, "nvme://", pref
)) {
850 const char *tmp
= filename
+ pref
;
852 const char *namespace;
854 const char *slash
= strchr(tmp
, '/');
856 qdict_put_str(options
, NVME_BLOCK_OPT_DEVICE
, tmp
);
859 device
= g_strndup(tmp
, slash
- tmp
);
860 qdict_put_str(options
, NVME_BLOCK_OPT_DEVICE
, device
);
862 namespace = slash
+ 1;
863 if (*namespace && qemu_strtoul(namespace, NULL
, 10, &ns
)) {
864 error_setg(errp
, "Invalid namespace '%s', positive number expected",
868 qdict_put_str(options
, NVME_BLOCK_OPT_NAMESPACE
,
869 *namespace ? namespace : "1");
873 static int nvme_enable_disable_write_cache(BlockDriverState
*bs
, bool enable
,
877 BDRVNVMeState
*s
= bs
->opaque
;
879 .opcode
= NVME_ADM_CMD_SET_FEATURES
,
880 .nsid
= cpu_to_le32(s
->nsid
),
881 .cdw10
= cpu_to_le32(0x06),
882 .cdw11
= cpu_to_le32(enable
? 0x01 : 0x00),
885 ret
= nvme_cmd_sync(bs
, s
->queues
[INDEX_ADMIN
], &cmd
);
887 error_setg(errp
, "Failed to configure NVMe write cache");
892 static void nvme_close(BlockDriverState
*bs
)
895 BDRVNVMeState
*s
= bs
->opaque
;
897 for (i
= 0; i
< s
->nr_queues
; ++i
) {
898 nvme_free_queue_pair(s
->queues
[i
]);
901 aio_set_event_notifier(bdrv_get_aio_context(bs
),
902 &s
->irq_notifier
[MSIX_SHARED_IRQ_IDX
],
904 event_notifier_cleanup(&s
->irq_notifier
[MSIX_SHARED_IRQ_IDX
]);
905 qemu_vfio_pci_unmap_bar(s
->vfio
, 0, (void *)s
->doorbells
,
906 sizeof(NvmeBar
), NVME_DOORBELL_SIZE
);
907 qemu_vfio_close(s
->vfio
);
912 static int nvme_file_open(BlockDriverState
*bs
, QDict
*options
, int flags
,
919 BDRVNVMeState
*s
= bs
->opaque
;
921 bs
->supported_write_flags
= BDRV_REQ_FUA
;
923 opts
= qemu_opts_create(&runtime_opts
, NULL
, 0, &error_abort
);
924 qemu_opts_absorb_qdict(opts
, options
, &error_abort
);
925 device
= qemu_opt_get(opts
, NVME_BLOCK_OPT_DEVICE
);
927 error_setg(errp
, "'" NVME_BLOCK_OPT_DEVICE
"' option is required");
932 namespace = qemu_opt_get_number(opts
, NVME_BLOCK_OPT_NAMESPACE
, 1);
933 ret
= nvme_init(bs
, device
, namespace, errp
);
938 if (flags
& BDRV_O_NOCACHE
) {
939 if (!s
->write_cache_supported
) {
941 "NVMe controller doesn't support write cache configuration");
944 ret
= nvme_enable_disable_write_cache(bs
, !(flags
& BDRV_O_NOCACHE
),
957 static int64_t nvme_getlength(BlockDriverState
*bs
)
959 BDRVNVMeState
*s
= bs
->opaque
;
960 return s
->nsze
<< s
->blkshift
;
963 static uint32_t nvme_get_blocksize(BlockDriverState
*bs
)
965 BDRVNVMeState
*s
= bs
->opaque
;
966 assert(s
->blkshift
>= BDRV_SECTOR_BITS
&& s
->blkshift
<= 12);
967 return UINT32_C(1) << s
->blkshift
;
970 static int nvme_probe_blocksizes(BlockDriverState
*bs
, BlockSizes
*bsz
)
972 uint32_t blocksize
= nvme_get_blocksize(bs
);
973 bsz
->phys
= blocksize
;
974 bsz
->log
= blocksize
;
978 /* Called with s->dma_map_lock */
979 static coroutine_fn
int nvme_cmd_unmap_qiov(BlockDriverState
*bs
,
983 BDRVNVMeState
*s
= bs
->opaque
;
985 s
->dma_map_count
-= qiov
->size
;
986 if (!s
->dma_map_count
&& !qemu_co_queue_empty(&s
->dma_flush_queue
)) {
987 r
= qemu_vfio_dma_reset_temporary(s
->vfio
);
989 qemu_co_queue_restart_all(&s
->dma_flush_queue
);
995 /* Called with s->dma_map_lock */
996 static coroutine_fn
int nvme_cmd_map_qiov(BlockDriverState
*bs
, NvmeCmd
*cmd
,
997 NVMeRequest
*req
, QEMUIOVector
*qiov
)
999 BDRVNVMeState
*s
= bs
->opaque
;
1000 uint64_t *pagelist
= req
->prp_list_page
;
1005 assert(QEMU_IS_ALIGNED(qiov
->size
, s
->page_size
));
1006 assert(qiov
->size
/ s
->page_size
<= s
->page_size
/ sizeof(uint64_t));
1007 for (i
= 0; i
< qiov
->niov
; ++i
) {
1011 r
= qemu_vfio_dma_map(s
->vfio
,
1012 qiov
->iov
[i
].iov_base
,
1013 qiov
->iov
[i
].iov_len
,
1015 if (r
== -ENOMEM
&& retry
) {
1017 trace_nvme_dma_flush_queue_wait(s
);
1018 if (s
->dma_map_count
) {
1019 trace_nvme_dma_map_flush(s
);
1020 qemu_co_queue_wait(&s
->dma_flush_queue
, &s
->dma_map_lock
);
1022 r
= qemu_vfio_dma_reset_temporary(s
->vfio
);
1033 for (j
= 0; j
< qiov
->iov
[i
].iov_len
/ s
->page_size
; j
++) {
1034 pagelist
[entries
++] = cpu_to_le64(iova
+ j
* s
->page_size
);
1036 trace_nvme_cmd_map_qiov_iov(s
, i
, qiov
->iov
[i
].iov_base
,
1037 qiov
->iov
[i
].iov_len
/ s
->page_size
);
1040 s
->dma_map_count
+= qiov
->size
;
1042 assert(entries
<= s
->page_size
/ sizeof(uint64_t));
1047 cmd
->dptr
.prp1
= pagelist
[0];
1051 cmd
->dptr
.prp1
= pagelist
[0];
1052 cmd
->dptr
.prp2
= pagelist
[1];
1055 cmd
->dptr
.prp1
= pagelist
[0];
1056 cmd
->dptr
.prp2
= cpu_to_le64(req
->prp_list_iova
+ sizeof(uint64_t));
1059 trace_nvme_cmd_map_qiov(s
, cmd
, req
, qiov
, entries
);
1060 for (i
= 0; i
< entries
; ++i
) {
1061 trace_nvme_cmd_map_qiov_pages(s
, i
, pagelist
[i
]);
1065 /* No need to unmap [0 - i) iovs even if we've failed, since we don't
1066 * increment s->dma_map_count. This is okay for fixed mapping memory areas
1067 * because they are already mapped before calling this function; for
1068 * temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by
1069 * calling qemu_vfio_dma_reset_temporary when necessary. */
1079 static void nvme_rw_cb_bh(void *opaque
)
1081 NVMeCoData
*data
= opaque
;
1082 qemu_coroutine_enter(data
->co
);
1085 static void nvme_rw_cb(void *opaque
, int ret
)
1087 NVMeCoData
*data
= opaque
;
1090 /* The rw coroutine hasn't yielded, don't try to enter. */
1093 replay_bh_schedule_oneshot_event(data
->ctx
, nvme_rw_cb_bh
, data
);
1096 static coroutine_fn
int nvme_co_prw_aligned(BlockDriverState
*bs
,
1097 uint64_t offset
, uint64_t bytes
,
1103 BDRVNVMeState
*s
= bs
->opaque
;
1104 NVMeQueuePair
*ioq
= s
->queues
[INDEX_IO(0)];
1107 uint32_t cdw12
= (((bytes
>> s
->blkshift
) - 1) & 0xFFFF) |
1108 (flags
& BDRV_REQ_FUA
? 1 << 30 : 0);
1110 .opcode
= is_write
? NVME_CMD_WRITE
: NVME_CMD_READ
,
1111 .nsid
= cpu_to_le32(s
->nsid
),
1112 .cdw10
= cpu_to_le32((offset
>> s
->blkshift
) & 0xFFFFFFFF),
1113 .cdw11
= cpu_to_le32(((offset
>> s
->blkshift
) >> 32) & 0xFFFFFFFF),
1114 .cdw12
= cpu_to_le32(cdw12
),
1117 .ctx
= bdrv_get_aio_context(bs
),
1118 .ret
= -EINPROGRESS
,
1121 trace_nvme_prw_aligned(s
, is_write
, offset
, bytes
, flags
, qiov
->niov
);
1122 assert(s
->nr_queues
> 1);
1123 req
= nvme_get_free_req(ioq
);
1126 qemu_co_mutex_lock(&s
->dma_map_lock
);
1127 r
= nvme_cmd_map_qiov(bs
, &cmd
, req
, qiov
);
1128 qemu_co_mutex_unlock(&s
->dma_map_lock
);
1130 nvme_put_free_req_and_wake(ioq
, req
);
1133 nvme_submit_command(ioq
, req
, &cmd
, nvme_rw_cb
, &data
);
1135 data
.co
= qemu_coroutine_self();
1136 while (data
.ret
== -EINPROGRESS
) {
1137 qemu_coroutine_yield();
1140 qemu_co_mutex_lock(&s
->dma_map_lock
);
1141 r
= nvme_cmd_unmap_qiov(bs
, qiov
);
1142 qemu_co_mutex_unlock(&s
->dma_map_lock
);
1147 trace_nvme_rw_done(s
, is_write
, offset
, bytes
, data
.ret
);
1151 static inline bool nvme_qiov_aligned(BlockDriverState
*bs
,
1152 const QEMUIOVector
*qiov
)
1155 BDRVNVMeState
*s
= bs
->opaque
;
1157 for (i
= 0; i
< qiov
->niov
; ++i
) {
1158 if (!QEMU_PTR_IS_ALIGNED(qiov
->iov
[i
].iov_base
, s
->page_size
) ||
1159 !QEMU_IS_ALIGNED(qiov
->iov
[i
].iov_len
, s
->page_size
)) {
1160 trace_nvme_qiov_unaligned(qiov
, i
, qiov
->iov
[i
].iov_base
,
1161 qiov
->iov
[i
].iov_len
, s
->page_size
);
1168 static int nvme_co_prw(BlockDriverState
*bs
, uint64_t offset
, uint64_t bytes
,
1169 QEMUIOVector
*qiov
, bool is_write
, int flags
)
1171 BDRVNVMeState
*s
= bs
->opaque
;
1173 uint8_t *buf
= NULL
;
1174 QEMUIOVector local_qiov
;
1176 assert(QEMU_IS_ALIGNED(offset
, s
->page_size
));
1177 assert(QEMU_IS_ALIGNED(bytes
, s
->page_size
));
1178 assert(bytes
<= s
->max_transfer
);
1179 if (nvme_qiov_aligned(bs
, qiov
)) {
1180 s
->stats
.aligned_accesses
++;
1181 return nvme_co_prw_aligned(bs
, offset
, bytes
, qiov
, is_write
, flags
);
1183 s
->stats
.unaligned_accesses
++;
1184 trace_nvme_prw_buffered(s
, offset
, bytes
, qiov
->niov
, is_write
);
1185 buf
= qemu_try_memalign(s
->page_size
, bytes
);
1190 qemu_iovec_init(&local_qiov
, 1);
1192 qemu_iovec_to_buf(qiov
, 0, buf
, bytes
);
1194 qemu_iovec_add(&local_qiov
, buf
, bytes
);
1195 r
= nvme_co_prw_aligned(bs
, offset
, bytes
, &local_qiov
, is_write
, flags
);
1196 qemu_iovec_destroy(&local_qiov
);
1197 if (!r
&& !is_write
) {
1198 qemu_iovec_from_buf(qiov
, 0, buf
, bytes
);
1204 static coroutine_fn
int nvme_co_preadv(BlockDriverState
*bs
,
1205 uint64_t offset
, uint64_t bytes
,
1206 QEMUIOVector
*qiov
, int flags
)
1208 return nvme_co_prw(bs
, offset
, bytes
, qiov
, false, flags
);
1211 static coroutine_fn
int nvme_co_pwritev(BlockDriverState
*bs
,
1212 uint64_t offset
, uint64_t bytes
,
1213 QEMUIOVector
*qiov
, int flags
)
1215 return nvme_co_prw(bs
, offset
, bytes
, qiov
, true, flags
);
1218 static coroutine_fn
int nvme_co_flush(BlockDriverState
*bs
)
1220 BDRVNVMeState
*s
= bs
->opaque
;
1221 NVMeQueuePair
*ioq
= s
->queues
[INDEX_IO(0)];
1224 .opcode
= NVME_CMD_FLUSH
,
1225 .nsid
= cpu_to_le32(s
->nsid
),
1228 .ctx
= bdrv_get_aio_context(bs
),
1229 .ret
= -EINPROGRESS
,
1232 assert(s
->nr_queues
> 1);
1233 req
= nvme_get_free_req(ioq
);
1235 nvme_submit_command(ioq
, req
, &cmd
, nvme_rw_cb
, &data
);
1237 data
.co
= qemu_coroutine_self();
1238 if (data
.ret
== -EINPROGRESS
) {
1239 qemu_coroutine_yield();
1246 static coroutine_fn
int nvme_co_pwrite_zeroes(BlockDriverState
*bs
,
1249 BdrvRequestFlags flags
)
1251 BDRVNVMeState
*s
= bs
->opaque
;
1252 NVMeQueuePair
*ioq
= s
->queues
[INDEX_IO(0)];
1255 uint32_t cdw12
= ((bytes
>> s
->blkshift
) - 1) & 0xFFFF;
1257 if (!s
->supports_write_zeroes
) {
1262 .opcode
= NVME_CMD_WRITE_ZEROES
,
1263 .nsid
= cpu_to_le32(s
->nsid
),
1264 .cdw10
= cpu_to_le32((offset
>> s
->blkshift
) & 0xFFFFFFFF),
1265 .cdw11
= cpu_to_le32(((offset
>> s
->blkshift
) >> 32) & 0xFFFFFFFF),
1269 .ctx
= bdrv_get_aio_context(bs
),
1270 .ret
= -EINPROGRESS
,
1273 if (flags
& BDRV_REQ_MAY_UNMAP
) {
1277 if (flags
& BDRV_REQ_FUA
) {
1281 cmd
.cdw12
= cpu_to_le32(cdw12
);
1283 trace_nvme_write_zeroes(s
, offset
, bytes
, flags
);
1284 assert(s
->nr_queues
> 1);
1285 req
= nvme_get_free_req(ioq
);
1288 nvme_submit_command(ioq
, req
, &cmd
, nvme_rw_cb
, &data
);
1290 data
.co
= qemu_coroutine_self();
1291 while (data
.ret
== -EINPROGRESS
) {
1292 qemu_coroutine_yield();
1295 trace_nvme_rw_done(s
, true, offset
, bytes
, data
.ret
);
1300 static int coroutine_fn
nvme_co_pdiscard(BlockDriverState
*bs
,
1304 BDRVNVMeState
*s
= bs
->opaque
;
1305 NVMeQueuePair
*ioq
= s
->queues
[INDEX_IO(0)];
1308 QEMUIOVector local_qiov
;
1312 .opcode
= NVME_CMD_DSM
,
1313 .nsid
= cpu_to_le32(s
->nsid
),
1314 .cdw10
= cpu_to_le32(0), /*number of ranges - 0 based*/
1315 .cdw11
= cpu_to_le32(1 << 2), /*deallocate bit*/
1319 .ctx
= bdrv_get_aio_context(bs
),
1320 .ret
= -EINPROGRESS
,
1323 if (!s
->supports_discard
) {
1327 assert(s
->nr_queues
> 1);
1329 buf
= qemu_try_memalign(s
->page_size
, s
->page_size
);
1333 memset(buf
, 0, s
->page_size
);
1334 buf
->nlb
= cpu_to_le32(bytes
>> s
->blkshift
);
1335 buf
->slba
= cpu_to_le64(offset
>> s
->blkshift
);
1338 qemu_iovec_init(&local_qiov
, 1);
1339 qemu_iovec_add(&local_qiov
, buf
, 4096);
1341 req
= nvme_get_free_req(ioq
);
1344 qemu_co_mutex_lock(&s
->dma_map_lock
);
1345 ret
= nvme_cmd_map_qiov(bs
, &cmd
, req
, &local_qiov
);
1346 qemu_co_mutex_unlock(&s
->dma_map_lock
);
1349 nvme_put_free_req_and_wake(ioq
, req
);
1353 trace_nvme_dsm(s
, offset
, bytes
);
1355 nvme_submit_command(ioq
, req
, &cmd
, nvme_rw_cb
, &data
);
1357 data
.co
= qemu_coroutine_self();
1358 while (data
.ret
== -EINPROGRESS
) {
1359 qemu_coroutine_yield();
1362 qemu_co_mutex_lock(&s
->dma_map_lock
);
1363 ret
= nvme_cmd_unmap_qiov(bs
, &local_qiov
);
1364 qemu_co_mutex_unlock(&s
->dma_map_lock
);
1371 trace_nvme_dsm_done(s
, offset
, bytes
, ret
);
1373 qemu_iovec_destroy(&local_qiov
);
1380 static int nvme_reopen_prepare(BDRVReopenState
*reopen_state
,
1381 BlockReopenQueue
*queue
, Error
**errp
)
1386 static void nvme_refresh_filename(BlockDriverState
*bs
)
1388 BDRVNVMeState
*s
= bs
->opaque
;
1390 snprintf(bs
->exact_filename
, sizeof(bs
->exact_filename
), "nvme://%s/%i",
1391 s
->device
, s
->nsid
);
1394 static void nvme_refresh_limits(BlockDriverState
*bs
, Error
**errp
)
1396 BDRVNVMeState
*s
= bs
->opaque
;
1398 bs
->bl
.opt_mem_alignment
= s
->page_size
;
1399 bs
->bl
.request_alignment
= s
->page_size
;
1400 bs
->bl
.max_transfer
= s
->max_transfer
;
1403 static void nvme_detach_aio_context(BlockDriverState
*bs
)
1405 BDRVNVMeState
*s
= bs
->opaque
;
1407 for (int i
= 0; i
< s
->nr_queues
; i
++) {
1408 NVMeQueuePair
*q
= s
->queues
[i
];
1410 qemu_bh_delete(q
->completion_bh
);
1411 q
->completion_bh
= NULL
;
1414 aio_set_event_notifier(bdrv_get_aio_context(bs
),
1415 &s
->irq_notifier
[MSIX_SHARED_IRQ_IDX
],
1419 static void nvme_attach_aio_context(BlockDriverState
*bs
,
1420 AioContext
*new_context
)
1422 BDRVNVMeState
*s
= bs
->opaque
;
1424 s
->aio_context
= new_context
;
1425 aio_set_event_notifier(new_context
, &s
->irq_notifier
[MSIX_SHARED_IRQ_IDX
],
1426 false, nvme_handle_event
, nvme_poll_cb
);
1428 for (int i
= 0; i
< s
->nr_queues
; i
++) {
1429 NVMeQueuePair
*q
= s
->queues
[i
];
1432 aio_bh_new(new_context
, nvme_process_completion_bh
, q
);
1436 static void nvme_aio_plug(BlockDriverState
*bs
)
1438 BDRVNVMeState
*s
= bs
->opaque
;
1439 assert(!s
->plugged
);
1443 static void nvme_aio_unplug(BlockDriverState
*bs
)
1446 BDRVNVMeState
*s
= bs
->opaque
;
1449 for (i
= INDEX_IO(0); i
< s
->nr_queues
; i
++) {
1450 NVMeQueuePair
*q
= s
->queues
[i
];
1451 qemu_mutex_lock(&q
->lock
);
1453 nvme_process_completion(q
);
1454 qemu_mutex_unlock(&q
->lock
);
1458 static void nvme_register_buf(BlockDriverState
*bs
, void *host
, size_t size
)
1461 BDRVNVMeState
*s
= bs
->opaque
;
1463 ret
= qemu_vfio_dma_map(s
->vfio
, host
, size
, false, NULL
);
1465 /* FIXME: we may run out of IOVA addresses after repeated
1466 * bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap
1467 * doesn't reclaim addresses for fixed mappings. */
1468 error_report("nvme_register_buf failed: %s", strerror(-ret
));
1472 static void nvme_unregister_buf(BlockDriverState
*bs
, void *host
)
1474 BDRVNVMeState
*s
= bs
->opaque
;
1476 qemu_vfio_dma_unmap(s
->vfio
, host
);
1479 static BlockStatsSpecific
*nvme_get_specific_stats(BlockDriverState
*bs
)
1481 BlockStatsSpecific
*stats
= g_new(BlockStatsSpecific
, 1);
1482 BDRVNVMeState
*s
= bs
->opaque
;
1484 stats
->driver
= BLOCKDEV_DRIVER_NVME
;
1485 stats
->u
.nvme
= (BlockStatsSpecificNvme
) {
1486 .completion_errors
= s
->stats
.completion_errors
,
1487 .aligned_accesses
= s
->stats
.aligned_accesses
,
1488 .unaligned_accesses
= s
->stats
.unaligned_accesses
,
1494 static const char *const nvme_strong_runtime_opts
[] = {
1495 NVME_BLOCK_OPT_DEVICE
,
1496 NVME_BLOCK_OPT_NAMESPACE
,
1501 static BlockDriver bdrv_nvme
= {
1502 .format_name
= "nvme",
1503 .protocol_name
= "nvme",
1504 .instance_size
= sizeof(BDRVNVMeState
),
1506 .bdrv_co_create_opts
= bdrv_co_create_opts_simple
,
1507 .create_opts
= &bdrv_create_opts_simple
,
1509 .bdrv_parse_filename
= nvme_parse_filename
,
1510 .bdrv_file_open
= nvme_file_open
,
1511 .bdrv_close
= nvme_close
,
1512 .bdrv_getlength
= nvme_getlength
,
1513 .bdrv_probe_blocksizes
= nvme_probe_blocksizes
,
1515 .bdrv_co_preadv
= nvme_co_preadv
,
1516 .bdrv_co_pwritev
= nvme_co_pwritev
,
1518 .bdrv_co_pwrite_zeroes
= nvme_co_pwrite_zeroes
,
1519 .bdrv_co_pdiscard
= nvme_co_pdiscard
,
1521 .bdrv_co_flush_to_disk
= nvme_co_flush
,
1522 .bdrv_reopen_prepare
= nvme_reopen_prepare
,
1524 .bdrv_refresh_filename
= nvme_refresh_filename
,
1525 .bdrv_refresh_limits
= nvme_refresh_limits
,
1526 .strong_runtime_opts
= nvme_strong_runtime_opts
,
1527 .bdrv_get_specific_stats
= nvme_get_specific_stats
,
1529 .bdrv_detach_aio_context
= nvme_detach_aio_context
,
1530 .bdrv_attach_aio_context
= nvme_attach_aio_context
,
1532 .bdrv_io_plug
= nvme_aio_plug
,
1533 .bdrv_io_unplug
= nvme_aio_unplug
,
1535 .bdrv_register_buf
= nvme_register_buf
,
1536 .bdrv_unregister_buf
= nvme_unregister_buf
,
1539 static void bdrv_nvme_init(void)
1541 bdrv_register(&bdrv_nvme
);
1544 block_init(bdrv_nvme_init
);